[coreboot] New patch to review: 2bea70b Move existing AMD Ffamily14 code to f14 folder
Frank Vibrans III (efdesign98@gmail.com)
gerrit at coreboot.org
Tue Jun 21 03:15:55 CEST 2011
Frank Vibrans III (efdesign98 at gmail.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/52
-gerrit
commit 2bea70b63e83700860e4f65407495605cab01b72
Author: efdesign98 <efdesign98 at gmail.com>
Date: Mon Jun 20 18:12:43 2011 -0700
Move existing AMD Ffamily14 code to f14 folder
This change moves the AMD Family14 cpu Agesa code to
the vendorcode/amd/agesa/f14 folder to complete the
transition to the family oriented folder structure.
Change-Id: I211e80ee04574cc713f38b4cc1b767dbb2bfaa59
Signed-off-by: Frank Vibrans <frank.vibrans at amd.com>
Signed-off-by: efdesign98 <efdesign98 at gmail.com>
---
src/cpu/amd/Makefile.inc | 2 +-
src/cpu/amd/agesa/family14/Makefile.inc | 2 +-
src/mainboard/advansus/a785e-i/Makefile.inc | 14 +-
src/mainboard/amd/inagua/Makefile.inc | 2 +-
src/mainboard/amd/persimmon/Makefile.inc | 2 +-
src/mainboard/asrock/e350m1/Makefile.inc | 2 +-
src/northbridge/amd/Makefile.inc | 2 +-
src/vendorcode/amd/agesa/AGESA.h | 3022 -----
src/vendorcode/amd/agesa/AMD.h | 482 -
src/vendorcode/amd/agesa/Dispatcher.h | 54 -
src/vendorcode/amd/agesa/Include/AdvancedApi.h | 168 -
src/vendorcode/amd/agesa/Include/BrazosInstall.h | 102 -
src/vendorcode/amd/agesa/Include/CommonReturns.h | 125 -
src/vendorcode/amd/agesa/Include/DanNiInstall.h | 117 -
src/vendorcode/amd/agesa/Include/DanubeInstall.h | 102 -
src/vendorcode/amd/agesa/Include/DevTestInstall.h | 111 -
src/vendorcode/amd/agesa/Include/DragonInstall.h | 102 -
src/vendorcode/amd/agesa/Include/Filecode.h | 849 --
src/vendorcode/amd/agesa/Include/GeneralServices.h | 203 -
src/vendorcode/amd/agesa/Include/GnbInterface.h | 96 -
.../amd/agesa/Include/GnbInterfaceStub.h | 232 -
src/vendorcode/amd/agesa/Include/Ids.h | 927 --
src/vendorcode/amd/agesa/Include/IdsHt.h | 126 -
src/vendorcode/amd/agesa/Include/LynxInstall.h | 102 -
.../amd/agesa/Include/MaranelloInstall.h | 118 -
src/vendorcode/amd/agesa/Include/NileInstall.h | 102 -
src/vendorcode/amd/agesa/Include/OptionC6Install.h | 151 -
.../amd/agesa/Include/OptionCpbInstall.h | 122 -
.../Include/OptionCpuCacheFlushOnHaltInstall.h | 120 -
.../agesa/Include/OptionCpuCoreLevelingInstall.h | 115 -
.../amd/agesa/Include/OptionCpuFamiliesInstall.h | 406 -
.../amd/agesa/Include/OptionCpuFeaturesInstall.h | 78 -
src/vendorcode/amd/agesa/Include/OptionDmi.h | 92 -
.../amd/agesa/Include/OptionDmiInstall.h | 194 -
.../amd/agesa/Include/OptionFamily10hInstall.h | 1996 ----
.../amd/agesa/Include/OptionFamily12hEarlySample.h | 138 -
.../amd/agesa/Include/OptionFamily12hInstall.h | 665 --
.../amd/agesa/Include/OptionFamily14hEarlySample.h | 170 -
.../amd/agesa/Include/OptionFamily14hInstall.h | 661 --
.../amd/agesa/Include/OptionFamily15hInstall.h | 717 --
.../amd/agesa/Include/OptionGfxRecovery.h | 84 -
.../amd/agesa/Include/OptionGfxRecoveryInstall.h | 56 -
src/vendorcode/amd/agesa/Include/OptionGnb.h | 92 -
.../amd/agesa/Include/OptionGnbInstall.h | 449 -
.../amd/agesa/Include/OptionHtAssistInstall.h | 109 -
src/vendorcode/amd/agesa/Include/OptionHtInstall.h | 301 -
.../amd/agesa/Include/OptionHwC1eInstall.h | 83 -
.../amd/agesa/Include/OptionIdsInstall.h | 417 -
.../amd/agesa/Include/OptionIoCstateInstall.h | 135 -
.../amd/agesa/Include/OptionLowPwrPstateInstall.h | 89 -
src/vendorcode/amd/agesa/Include/OptionMemory.h | 342 -
.../amd/agesa/Include/OptionMemoryInstall.h | 4051 -------
.../amd/agesa/Include/OptionMemoryRecovery.h | 65 -
.../agesa/Include/OptionMemoryRecoveryInstall.h | 602 -
.../amd/agesa/Include/OptionMsgBasedC1eInstall.h | 119 -
.../amd/agesa/Include/OptionMultiSocket.h | 169 -
.../amd/agesa/Include/OptionMultiSocketInstall.h | 92 -
.../agesa/Include/OptionPreserveMailboxInstall.h | 107 -
src/vendorcode/amd/agesa/Include/OptionPstate.h | 118 -
.../amd/agesa/Include/OptionPstateInstall.h | 243 -
.../amd/agesa/Include/OptionS3ScriptInstall.h | 94 -
src/vendorcode/amd/agesa/Include/OptionSlit.h | 99 -
.../amd/agesa/Include/OptionSlitInstall.h | 82 -
src/vendorcode/amd/agesa/Include/OptionSrat.h | 85 -
.../amd/agesa/Include/OptionSratInstall.h | 76 -
.../amd/agesa/Include/OptionSwC1eInstall.h | 83 -
src/vendorcode/amd/agesa/Include/OptionWhea.h | 86 -
.../amd/agesa/Include/OptionWheaInstall.h | 77 -
src/vendorcode/amd/agesa/Include/Options.h | 94 -
src/vendorcode/amd/agesa/Include/OptionsHt.h | 103 -
src/vendorcode/amd/agesa/Include/OptionsPage.h | 375 -
src/vendorcode/amd/agesa/Include/PlatformInstall.h | 2599 ----
.../agesa/Include/PlatformMemoryConfiguration.h | 314 -
src/vendorcode/amd/agesa/Include/SabineInstall.h | 117 -
.../amd/agesa/Include/SanMarinoInstall.h | 118 -
src/vendorcode/amd/agesa/Include/ScorpiusInstall.h | 117 -
src/vendorcode/amd/agesa/Include/TigrisInstall.h | 102 -
src/vendorcode/amd/agesa/Include/Topology.h | 165 -
src/vendorcode/amd/agesa/Include/gcc-intrin.h | 630 -
.../agesa/Legacy/PlatformMemoryConfiguration.inc | 402 -
src/vendorcode/amd/agesa/Legacy/Proc/Dispatcher.c | 161 -
src/vendorcode/amd/agesa/Legacy/Proc/Legacy.bat | 286 -
.../amd/agesa/Legacy/Proc/agesaCallouts.c | 397 -
src/vendorcode/amd/agesa/Legacy/Proc/arch2008.asm | 2674 -----
src/vendorcode/amd/agesa/Legacy/Proc/hobTransfer.c | 394 -
src/vendorcode/amd/agesa/Legacy/agesa.inc | 2547 ----
src/vendorcode/amd/agesa/Legacy/amd.inc | 461 -
src/vendorcode/amd/agesa/Legacy/bridge32.inc | 577 -
src/vendorcode/amd/agesa/Lib/IA32/amdlib32.asm | 151 -
src/vendorcode/amd/agesa/Lib/IA32/ms_shift.asm | 110 -
src/vendorcode/amd/agesa/Lib/IA32/msmemcpy.asm | 84 -
src/vendorcode/amd/agesa/Lib/amdlib.c | 1340 ---
src/vendorcode/amd/agesa/Lib/amdlib.h | 421 -
src/vendorcode/amd/agesa/Lib/helper.c | 68 -
src/vendorcode/amd/agesa/Lib/x64/amdlib64.asm | 591 -
src/vendorcode/amd/agesa/MainPage.h | 121 -
src/vendorcode/amd/agesa/Makefile.inc | 62 -
src/vendorcode/amd/agesa/Porting.h | 296 -
.../agesa/Proc/CPU/Family/0x10/F10InitEarlyTable.c | 119 -
.../amd/agesa/Proc/CPU/Family/0x10/F10IoCstate.c | 294 -
.../Proc/CPU/Family/0x10/F10MultiLinkPciTables.c | 1527 ---
.../agesa/Proc/CPU/Family/0x10/F10PackageType.h | 85 -
.../Proc/CPU/Family/0x10/F10PmAsymBoostInit.c | 182 -
.../Proc/CPU/Family/0x10/F10PmAsymBoostInit.h | 79 -
.../CPU/Family/0x10/F10PmDualPlaneOnlySupport.c | 246 -
.../CPU/Family/0x10/F10PmDualPlaneOnlySupport.h | 79 -
.../agesa/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c | 300 -
.../agesa/Proc/CPU/Family/0x10/F10PmNbCofVidInit.h | 78 -
.../agesa/Proc/CPU/Family/0x10/F10PmNbPstateInit.c | 188 -
.../agesa/Proc/CPU/Family/0x10/F10PmNbPstateInit.h | 78 -
.../Proc/CPU/Family/0x10/F10SingleLinkPciTables.c | 1942 ---
.../Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c | 151 -
.../Family/0x10/RevC/BL/F10BlEquivalenceTable.c | 107 -
.../CPU/Family/0x10/RevC/BL/F10BlHtPhyTables.c | 123 -
.../CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c | 107 -
.../0x10/RevC/BL/F10BlMicrocodePatchTables.c | 107 -
.../Proc/CPU/Family/0x10/RevC/BL/F10BlMsrTables.c | 107 -
.../Proc/CPU/Family/0x10/RevC/BL/F10BlPciTables.c | 197 -
.../Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c | 144 -
.../Family/0x10/RevC/DA/F10DaEquivalenceTable.c | 108 -
.../CPU/Family/0x10/RevC/DA/F10DaHtPhyTables.c | 284 -
.../CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c | 108 -
.../0x10/RevC/DA/F10DaMicrocodePatchTables.c | 107 -
.../Proc/CPU/Family/0x10/RevC/DA/F10DaMsrTables.c | 107 -
.../Proc/CPU/Family/0x10/RevC/DA/F10DaPciTables.c | 193 -
.../Family/0x10/RevC/F10MicrocodePatch01000085.c | 1038 --
.../Family/0x10/RevC/F10MicrocodePatch010000c6.c | 1038 --
.../Family/0x10/RevC/F10MicrocodePatch010000c7.c | 1038 --
.../Family/0x10/RevC/F10MicrocodePatch010000c8.c | 1038 --
.../Proc/CPU/Family/0x10/RevC/F10RevCHtPhyTables.c | 440 -
.../agesa/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c | 189 -
.../Proc/CPU/Family/0x10/RevC/F10RevCMsrTables.c | 134 -
.../Proc/CPU/Family/0x10/RevC/F10RevCPciTables.c | 266 -
.../agesa/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c | 182 -
.../Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c | 436 -
.../Family/0x10/RevC/RB/F10RbEquivalenceTable.c | 111 -
.../CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c | 121 -
.../CPU/Family/0x10/RevC/RB/F10RbLogicalIdTables.c | 115 -
.../0x10/RevC/RB/F10RbMicrocodePatchTables.c | 107 -
.../Proc/CPU/Family/0x10/RevC/RB/F10RbMsrTables.c | 121 -
.../Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c | 235 -
.../Family/0x10/RevD/F10MicrocodePatch010000c4.c | 1040 --
.../Family/0x10/RevD/F10MicrocodePatch010000c5.c | 1040 --
.../agesa/Proc/CPU/Family/0x10/RevD/F10RevD32.asm | 113 -
.../agesa/Proc/CPU/Family/0x10/RevD/F10RevD64.asm | 127 -
.../Proc/CPU/Family/0x10/RevD/F10RevDHtAssist.c | 466 -
.../Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c | 277 -
.../Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c | 370 -
.../Family/0x10/RevD/HY/F10HyEquivalenceTable.c | 107 -
.../CPU/Family/0x10/RevD/HY/F10HyHtPhyTables.c | 1295 --
.../CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c | 137 -
.../CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c | 109 -
.../0x10/RevD/HY/F10HyMicrocodePatchTables.c | 107 -
.../Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c | 138 -
.../Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c | 350 -
.../Family/0x10/RevE/F10MicrocodePatch010000bf.c | 1040 --
.../Proc/CPU/Family/0x10/RevE/F10RevEHtPhyTables.c | 374 -
.../Proc/CPU/Family/0x10/RevE/F10RevEMsrTables.c | 135 -
.../Proc/CPU/Family/0x10/RevE/F10RevEPciTables.c | 227 -
.../Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c | 370 -
.../Family/0x10/RevE/PH/F10PhEquivalenceTable.c | 106 -
.../CPU/Family/0x10/RevE/PH/F10PhHtPhyTables.c | 118 -
.../CPU/Family/0x10/RevE/PH/F10PhLogicalIdTables.c | 97 -
.../0x10/RevE/PH/F10PhMicrocodePatchTables.c | 106 -
.../Proc/CPU/Family/0x10/cpuCommonF10Utilities.c | 330 -
.../Proc/CPU/Family/0x10/cpuCommonF10Utilities.h | 100 -
.../amd/agesa/Proc/CPU/Family/0x10/cpuF10BrandId.c | 145 -
.../agesa/Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c | 333 -
.../agesa/Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c | 138 -
.../agesa/Proc/CPU/Family/0x10/cpuF10BrandIdC32.c | 134 -
.../Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c | 175 -
.../agesa/Proc/CPU/Family/0x10/cpuF10BrandIdG34.c | 128 -
.../agesa/Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c | 129 -
.../agesa/Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c | 144 -
.../Proc/CPU/Family/0x10/cpuF10CacheDefaults.c | 127 -
.../Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c | 144 -
.../amd/agesa/Proc/CPU/Family/0x10/cpuF10Cpb.c | 179 -
.../amd/agesa/Proc/CPU/Family/0x10/cpuF10Dmi.c | 478 -
.../agesa/Proc/CPU/Family/0x10/cpuF10EarlyInit.c | 424 -
.../agesa/Proc/CPU/Family/0x10/cpuF10EarlyInit.h | 80 -
.../Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c | 394 -
.../Proc/CPU/Family/0x10/cpuF10FeatureLeveling.h | 196 -
.../agesa/Proc/CPU/Family/0x10/cpuF10HtPhyTables.c | 752 --
.../agesa/Proc/CPU/Family/0x10/cpuF10MsrTables.c | 275 -
.../agesa/Proc/CPU/Family/0x10/cpuF10PciTables.c | 773 --
.../agesa/Proc/CPU/Family/0x10/cpuF10PowerCheck.c | 421 -
.../agesa/Proc/CPU/Family/0x10/cpuF10PowerCheck.h | 84 -
.../agesa/Proc/CPU/Family/0x10/cpuF10PowerMgmt.h | 548 -
.../CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c | 176 -
.../agesa/Proc/CPU/Family/0x10/cpuF10PowerPlane.c | 484 -
.../agesa/Proc/CPU/Family/0x10/cpuF10PowerPlane.h | 78 -
.../amd/agesa/Proc/CPU/Family/0x10/cpuF10Pstate.c | 863 --
.../Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c | 124 -
.../Proc/CPU/Family/0x10/cpuF10SoftwareThermal.h | 80 -
.../agesa/Proc/CPU/Family/0x10/cpuF10Utilities.c | 1119 --
.../agesa/Proc/CPU/Family/0x10/cpuF10Utilities.h | 165 -
.../CPU/Family/0x10/cpuF10WheaInitDataTables.c | 121 -
.../Proc/CPU/Family/0x10/cpuF10WorkaroundsTable.c | 106 -
.../amd/agesa/Proc/CPU/Family/0x14/F14C6State.c | 238 -
.../amd/agesa/Proc/CPU/Family/0x14/F14IoCstate.c | 285 -
.../CPU/Family/0x14/F14MicrocodePatch0500000B.c | 1645 ---
.../CPU/Family/0x14/F14MicrocodePatch0500001A.c | 1645 ---
.../CPU/Family/0x14/F14MicrocodePatch05000025.c | 1645 ---
.../agesa/Proc/CPU/Family/0x14/F14PackageType.h | 77 -
.../CPU/Family/0x14/ON/F14OnEquivalenceTable.c | 125 -
.../Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.c | 309 -
.../Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.h | 69 -
.../Proc/CPU/Family/0x14/ON/F14OnLogicalIdTables.c | 102 -
.../CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c | 102 -
.../Proc/CPU/Family/0x14/cpuCommonF14Utilities.c | 518 -
.../Proc/CPU/Family/0x14/cpuCommonF14Utilities.h | 104 -
.../amd/agesa/Proc/CPU/Family/0x14/cpuF14BrandId.c | 139 -
.../agesa/Proc/CPU/Family/0x14/cpuF14BrandIdFt1.c | 145 -
.../Proc/CPU/Family/0x14/cpuF14CacheDefaults.c | 123 -
.../amd/agesa/Proc/CPU/Family/0x14/cpuF14Dmi.c | 272 -
.../agesa/Proc/CPU/Family/0x14/cpuF14MsrTables.c | 198 -
.../agesa/Proc/CPU/Family/0x14/cpuF14PciTables.c | 716 --
.../Proc/CPU/Family/0x14/cpuF14PerCorePciTables.c | 102 -
.../agesa/Proc/CPU/Family/0x14/cpuF14PowerCheck.c | 358 -
.../agesa/Proc/CPU/Family/0x14/cpuF14PowerCheck.h | 83 -
.../agesa/Proc/CPU/Family/0x14/cpuF14PowerMgmt.h | 477 -
.../CPU/Family/0x14/cpuF14PowerMgmtSystemTables.c | 133 -
.../agesa/Proc/CPU/Family/0x14/cpuF14PowerPlane.c | 272 -
.../agesa/Proc/CPU/Family/0x14/cpuF14PowerPlane.h | 78 -
.../amd/agesa/Proc/CPU/Family/0x14/cpuF14Pstate.c | 364 -
.../Proc/CPU/Family/0x14/cpuF14SoftwareThermal.c | 112 -
.../Proc/CPU/Family/0x14/cpuF14SoftwareThermal.h | 80 -
.../agesa/Proc/CPU/Family/0x14/cpuF14Utilities.c | 539 -
.../agesa/Proc/CPU/Family/0x14/cpuF14Utilities.h | 132 -
.../CPU/Family/0x14/cpuF14WheaInitDataTables.c | 117 -
.../amd/agesa/Proc/CPU/Family/cpuFamRegisters.h | 213 -
.../amd/agesa/Proc/CPU/Feature/PreserveMailbox.c | 218 -
.../amd/agesa/Proc/CPU/Feature/PreserveMailbox.h | 89 -
.../amd/agesa/Proc/CPU/Feature/cpuC6State.c | 262 -
.../amd/agesa/Proc/CPU/Feature/cpuC6State.h | 156 -
.../agesa/Proc/CPU/Feature/cpuCacheFlushOnHalt.c | 193 -
.../amd/agesa/Proc/CPU/Feature/cpuCacheInit.c | 744 --
.../amd/agesa/Proc/CPU/Feature/cpuCacheInit.h | 134 -
.../amd/agesa/Proc/CPU/Feature/cpuCoreLeveling.c | 353 -
src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuCpb.c | 177 -
src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuCpb.h | 135 -
src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuDmi.c | 681 --
.../agesa/Proc/CPU/Feature/cpuFeatureLeveling.c | 266 -
.../amd/agesa/Proc/CPU/Feature/cpuFeatures.c | 198 -
.../amd/agesa/Proc/CPU/Feature/cpuFeatures.h | 267 -
.../amd/agesa/Proc/CPU/Feature/cpuHtAssist.c | 357 -
.../amd/agesa/Proc/CPU/Feature/cpuHtAssist.h | 301 -
.../amd/agesa/Proc/CPU/Feature/cpuHwC1e.c | 175 -
.../amd/agesa/Proc/CPU/Feature/cpuHwC1e.h | 127 -
.../amd/agesa/Proc/CPU/Feature/cpuIoCstate.c | 209 -
.../amd/agesa/Proc/CPU/Feature/cpuIoCstate.h | 285 -
.../amd/agesa/Proc/CPU/Feature/cpuLowPwrPstate.c | 206 -
.../amd/agesa/Proc/CPU/Feature/cpuLowPwrPstate.h | 133 -
.../amd/agesa/Proc/CPU/Feature/cpuMsgBasedC1e.c | 213 -
.../amd/agesa/Proc/CPU/Feature/cpuMsgBasedC1e.h | 129 -
.../amd/agesa/Proc/CPU/Feature/cpuPstateGather.c | 397 -
.../amd/agesa/Proc/CPU/Feature/cpuPstateLeveling.c | 1073 --
.../amd/agesa/Proc/CPU/Feature/cpuPstateTables.c | 830 --
.../amd/agesa/Proc/CPU/Feature/cpuPstateTables.h | 329 -
.../amd/agesa/Proc/CPU/Feature/cpuSlit.c | 357 -
.../amd/agesa/Proc/CPU/Feature/cpuSrat.c | 565 -
.../amd/agesa/Proc/CPU/Feature/cpuSwC1e.c | 176 -
.../amd/agesa/Proc/CPU/Feature/cpuSwC1e.h | 121 -
.../amd/agesa/Proc/CPU/Feature/cpuWhea.c | 271 -
src/vendorcode/amd/agesa/Proc/CPU/S3.c | 1219 --
src/vendorcode/amd/agesa/Proc/CPU/S3.h | 395 -
src/vendorcode/amd/agesa/Proc/CPU/Table.c | 1664 ---
src/vendorcode/amd/agesa/Proc/CPU/Table.h | 1238 --
src/vendorcode/amd/agesa/Proc/CPU/cahalt.asm | 345 -
src/vendorcode/amd/agesa/Proc/CPU/cahalt.c | 317 -
src/vendorcode/amd/agesa/Proc/CPU/cahalt64.asm | 157 -
.../amd/agesa/Proc/CPU/cpuApicUtilities.c | 1466 ---
.../amd/agesa/Proc/CPU/cpuApicUtilities.h | 262 -
src/vendorcode/amd/agesa/Proc/CPU/cpuBist.c | 173 -
src/vendorcode/amd/agesa/Proc/CPU/cpuBrandId.c | 309 -
src/vendorcode/amd/agesa/Proc/CPU/cpuEarlyInit.c | 404 -
src/vendorcode/amd/agesa/Proc/CPU/cpuEarlyInit.h | 250 -
src/vendorcode/amd/agesa/Proc/CPU/cpuEnvInit.h | 75 -
src/vendorcode/amd/agesa/Proc/CPU/cpuEventLog.c | 399 -
.../amd/agesa/Proc/CPU/cpuFamilyTranslation.c | 483 -
.../amd/agesa/Proc/CPU/cpuFamilyTranslation.h | 957 --
.../amd/agesa/Proc/CPU/cpuGeneralServices.c | 1277 --
.../amd/agesa/Proc/CPU/cpuInitEarlyTable.c | 119 -
src/vendorcode/amd/agesa/Proc/CPU/cpuLateInit.c | 286 -
src/vendorcode/amd/agesa/Proc/CPU/cpuLateInit.h | 821 --
.../amd/agesa/Proc/CPU/cpuMicrocodePatch.c | 441 -
src/vendorcode/amd/agesa/Proc/CPU/cpuPage.h | 62 -
src/vendorcode/amd/agesa/Proc/CPU/cpuPostInit.c | 481 -
src/vendorcode/amd/agesa/Proc/CPU/cpuPostInit.h | 228 -
src/vendorcode/amd/agesa/Proc/CPU/cpuPowerMgmt.c | 253 -
.../amd/agesa/Proc/CPU/cpuPowerMgmtMultiSocket.c | 432 -
.../amd/agesa/Proc/CPU/cpuPowerMgmtMultiSocket.h | 102 -
.../amd/agesa/Proc/CPU/cpuPowerMgmtSingleSocket.c | 246 -
.../amd/agesa/Proc/CPU/cpuPowerMgmtSingleSocket.h | 102 -
.../amd/agesa/Proc/CPU/cpuPowerMgmtSystemTables.h | 94 -
src/vendorcode/amd/agesa/Proc/CPU/cpuRegisters.h | 407 -
src/vendorcode/amd/agesa/Proc/CPU/cpuServices.h | 347 -
src/vendorcode/amd/agesa/Proc/CPU/cpuWarmReset.c | 237 -
src/vendorcode/amd/agesa/Proc/CPU/heapManager.c | 853 --
src/vendorcode/amd/agesa/Proc/CPU/heapManager.h | 230 -
.../amd/agesa/Proc/Common/AmdInitEarly.c | 281 -
src/vendorcode/amd/agesa/Proc/Common/AmdInitEnv.c | 176 -
src/vendorcode/amd/agesa/Proc/Common/AmdInitLate.c | 292 -
src/vendorcode/amd/agesa/Proc/Common/AmdInitMid.c | 162 -
src/vendorcode/amd/agesa/Proc/Common/AmdInitPost.c | 339 -
.../amd/agesa/Proc/Common/AmdInitRecovery.c | 171 -
.../amd/agesa/Proc/Common/AmdInitReset.c | 245 -
.../amd/agesa/Proc/Common/AmdInitResume.c | 233 -
.../amd/agesa/Proc/Common/AmdLateRunApTask.c | 160 -
.../amd/agesa/Proc/Common/AmdS3LateRestore.c | 215 -
src/vendorcode/amd/agesa/Proc/Common/AmdS3Save.c | 381 -
src/vendorcode/amd/agesa/Proc/Common/CommonInits.c | 137 -
src/vendorcode/amd/agesa/Proc/Common/CommonInits.h | 66 -
src/vendorcode/amd/agesa/Proc/Common/CommonPage.h | 118 -
.../amd/agesa/Proc/Common/CommonReturns.c | 174 -
.../amd/agesa/Proc/Common/CreateStruct.c | 315 -
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src/vendorcode/amd/agesa/Proc/GNB/Common/GnbGfx.h | 290 -
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src/vendorcode/amd/agesa/Proc/GNB/Common/GnbPcie.h | 352 -
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src/vendorcode/amd/agesa/Proc/GNB/GnbPage.h | 1858 ---
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src/vendorcode/amd/agesa/Proc/GNB/Nb/NbPowerMgmt.c | 600 -
src/vendorcode/amd/agesa/Proc/GNB/Nb/NbPowerMgmt.h | 70 -
src/vendorcode/amd/agesa/Proc/GNB/Nb/NbSmuLib.c | 652 -
src/vendorcode/amd/agesa/Proc/GNB/Nb/NbSmuLib.h | 185 -
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src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInit.c | 349 -
src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInit.h | 67 -
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.../Proc/Mem/Feat/PARTRN/mfParallelTraining.c | 286 -
.../Proc/Mem/Feat/PARTRN/mfStandardTraining.c | 88 -
src/vendorcode/amd/agesa/Proc/Mem/Feat/S3/mfs3.c | 714 --
.../amd/agesa/Proc/Mem/Feat/TABLE/mftds.c | 324 -
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.../amd/agesa/Proc/Mem/Main/PH/mmflowPh.c | 380 -
.../amd/agesa/Proc/Mem/Main/RB/mmflowRb.c | 380 -
src/vendorcode/amd/agesa/Proc/Mem/Main/mdef.c | 143 -
src/vendorcode/amd/agesa/Proc/Mem/Main/merrhdl.c | 189 -
src/vendorcode/amd/agesa/Proc/Mem/Main/minit.c | 138 -
src/vendorcode/amd/agesa/Proc/Mem/Main/mm.c | 240 -
.../amd/agesa/Proc/Mem/Main/mmConditionalPso.c | 697 --
src/vendorcode/amd/agesa/Proc/Mem/Main/mmEcc.c | 128 -
.../amd/agesa/Proc/Mem/Main/mmExcludeDimm.c | 218 -
src/vendorcode/amd/agesa/Proc/Mem/Main/mmLvDdr3.c | 265 -
src/vendorcode/amd/agesa/Proc/Mem/Main/mmMemClr.c | 110 -
.../amd/agesa/Proc/Mem/Main/mmMemRestore.c | 597 -
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.../amd/agesa/Proc/Mem/Main/mmParallelTraining.c | 273 -
.../amd/agesa/Proc/Mem/Main/mmStandardTraining.c | 111 -
.../amd/agesa/Proc/Mem/Main/mmUmaAlloc.c | 242 -
src/vendorcode/amd/agesa/Proc/Mem/Main/mmflow.c | 384 -
src/vendorcode/amd/agesa/Proc/Mem/Main/mmlvddr3.h | 82 -
src/vendorcode/amd/agesa/Proc/Mem/Main/mu.asm | 497 -
src/vendorcode/amd/agesa/Proc/Mem/Main/mu.c | 253 -
src/vendorcode/amd/agesa/Proc/Mem/Main/muc.c | 652 -
.../amd/agesa/Proc/Mem/NB/C32/mnParTrainc32.c | 224 -
src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mnS3c32.c | 731 --
src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mnS3c32.h | 85 -
src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mnc32.c | 485 -
src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mnc32.h | 196 -
.../amd/agesa/Proc/Mem/NB/C32/mndctc32.c | 365 -
.../amd/agesa/Proc/Mem/NB/C32/mnflowc32.c | 136 -
.../amd/agesa/Proc/Mem/NB/C32/mnidendimmc32.c | 139 -
.../amd/agesa/Proc/Mem/NB/C32/mnmctc32.c | 195 -
src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mnotc32.c | 241 -
.../amd/agesa/Proc/Mem/NB/C32/mnphyc32.c | 167 -
.../amd/agesa/Proc/Mem/NB/C32/mnprotoc32.c | 67 -
.../amd/agesa/Proc/Mem/NB/C32/mnregc32.c | 627 -
.../amd/agesa/Proc/Mem/NB/DA/mnParTrainDa.c | 226 -
src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mnS3da.c | 748 --
src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mnS3da.h | 85 -
src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mnda.c | 490 -
src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mnda.h | 210 -
src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mndctda.c | 469 -
src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mnflowda.c | 140 -
.../amd/agesa/Proc/Mem/NB/DA/mnidendimmda.c | 140 -
src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mnmctda.c | 199 -
src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mnotda.c | 201 -
.../amd/agesa/Proc/Mem/NB/DA/mnprotoda.c | 87 -
src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mnregda.c | 574 -
.../amd/agesa/Proc/Mem/NB/DR/mnParTrainDr.c | 226 -
src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mnS3dr.c | 716 --
src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mnS3dr.h | 85 -
src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mndctdr.c | 515 -
src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mndr.c | 482 -
src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mndr.h | 199 -
src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mnflowdr.c | 142 -
.../amd/agesa/Proc/Mem/NB/DR/mnidendimmdr.c | 140 -
src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mnmctdr.c | 186 -
src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mnotdr.c | 200 -
.../amd/agesa/Proc/Mem/NB/DR/mnprotodr.c | 170 -
src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mnregdr.c | 548 -
.../amd/agesa/Proc/Mem/NB/HY/mnParTrainHy.c | 224 -
src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnS3hy.c | 740 --
src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnS3hy.h | 85 -
src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mndcthy.c | 409 -
src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnflowhy.c | 135 -
src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnhy.c | 487 -
src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnhy.h | 202 -
.../amd/agesa/Proc/Mem/NB/HY/mnidendimmhy.c | 139 -
src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnmcthy.c | 195 -
src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnothy.c | 241 -
src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnphyhy.c | 183 -
.../amd/agesa/Proc/Mem/NB/HY/mnprotohy.c | 67 -
src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnreghy.c | 630 -
src/vendorcode/amd/agesa/Proc/Mem/NB/NI/mnNi.c | 495 -
src/vendorcode/amd/agesa/Proc/Mem/NB/NI/mnNi.h | 114 -
src/vendorcode/amd/agesa/Proc/Mem/NB/NI/mnS3Ni.c | 747 --
src/vendorcode/amd/agesa/Proc/Mem/NB/NI/mnS3Ni.h | 85 -
src/vendorcode/amd/agesa/Proc/Mem/NB/NI/mnflowNi.c | 141 -
src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnS3on.c | 576 -
src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnS3on.h | 85 -
src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mndcton.c | 490 -
src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnflowon.c | 168 -
.../amd/agesa/Proc/Mem/NB/ON/mnidendimmon.c | 136 -
src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnmcton.c | 252 -
src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnon.c | 456 -
src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnon.h | 250 -
src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnoton.c | 230 -
src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnphyon.c | 244 -
.../amd/agesa/Proc/Mem/NB/ON/mnprotoon.c | 165 -
src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnregon.c | 600 -
src/vendorcode/amd/agesa/Proc/Mem/NB/PH/mnPh.c | 494 -
src/vendorcode/amd/agesa/Proc/Mem/NB/PH/mnPh.h | 125 -
src/vendorcode/amd/agesa/Proc/Mem/NB/PH/mnS3Ph.c | 776 --
src/vendorcode/amd/agesa/Proc/Mem/NB/PH/mnS3Ph.h | 85 -
src/vendorcode/amd/agesa/Proc/Mem/NB/PH/mnflowPh.c | 142 -
.../amd/agesa/Proc/Mem/NB/PH/mnidendimmPh.c | 141 -
src/vendorcode/amd/agesa/Proc/Mem/NB/RB/mnRb.c | 494 -
src/vendorcode/amd/agesa/Proc/Mem/NB/RB/mnRb.h | 125 -
src/vendorcode/amd/agesa/Proc/Mem/NB/RB/mnS3Rb.c | 776 --
src/vendorcode/amd/agesa/Proc/Mem/NB/RB/mnS3Rb.h | 85 -
src/vendorcode/amd/agesa/Proc/Mem/NB/RB/mnflowRb.c | 142 -
.../amd/agesa/Proc/Mem/NB/RB/mnidendimmRb.c | 141 -
src/vendorcode/amd/agesa/Proc/Mem/NB/mn.c | 527 -
src/vendorcode/amd/agesa/Proc/Mem/NB/mnS3.c | 929 --
src/vendorcode/amd/agesa/Proc/Mem/NB/mndct.c | 2651 -----
src/vendorcode/amd/agesa/Proc/Mem/NB/mnfeat.c | 1268 --
src/vendorcode/amd/agesa/Proc/Mem/NB/mnflow.c | 268 -
src/vendorcode/amd/agesa/Proc/Mem/NB/mnmct.c | 1184 --
src/vendorcode/amd/agesa/Proc/Mem/NB/mnphy.c | 1377 ---
src/vendorcode/amd/agesa/Proc/Mem/NB/mnreg.c | 437 -
src/vendorcode/amd/agesa/Proc/Mem/NB/mntrain2.c | 133 -
src/vendorcode/amd/agesa/Proc/Mem/NB/mntrain3.c | 236 -
.../amd/agesa/Proc/Mem/Ps/C32/mprc32_3.c | 326 -
.../amd/agesa/Proc/Mem/Ps/C32/mpuc32_3.c | 205 -
src/vendorcode/amd/agesa/Proc/Mem/Ps/DA/mpsda2.c | 161 -
src/vendorcode/amd/agesa/Proc/Mem/Ps/DA/mpsda3.c | 257 -
src/vendorcode/amd/agesa/Proc/Mem/Ps/DA/mpuda3.c | 210 -
src/vendorcode/amd/agesa/Proc/Mem/Ps/DR/mprdr2.c | 166 -
src/vendorcode/amd/agesa/Proc/Mem/Ps/DR/mprdr3.c | 205 -
src/vendorcode/amd/agesa/Proc/Mem/Ps/DR/mpsdr3.c | 192 -
src/vendorcode/amd/agesa/Proc/Mem/Ps/DR/mpudr2.c | 166 -
src/vendorcode/amd/agesa/Proc/Mem/Ps/DR/mpudr3.c | 161 -
src/vendorcode/amd/agesa/Proc/Mem/Ps/HY/mprhy3.c | 325 -
src/vendorcode/amd/agesa/Proc/Mem/Ps/HY/mpshy3.c | 221 -
src/vendorcode/amd/agesa/Proc/Mem/Ps/HY/mpuhy3.c | 199 -
src/vendorcode/amd/agesa/Proc/Mem/Ps/NI/mpsNi3.c | 257 -
src/vendorcode/amd/agesa/Proc/Mem/Ps/NI/mpuNi3.c | 235 -
src/vendorcode/amd/agesa/Proc/Mem/Ps/ON/mpson3.c | 181 -
src/vendorcode/amd/agesa/Proc/Mem/Ps/ON/mpuon3.c | 182 -
src/vendorcode/amd/agesa/Proc/Mem/Ps/PH/mpsph3.c | 257 -
src/vendorcode/amd/agesa/Proc/Mem/Ps/PH/mpuph3.c | 211 -
src/vendorcode/amd/agesa/Proc/Mem/Ps/RB/mpsRb3.c | 257 -
src/vendorcode/amd/agesa/Proc/Mem/Ps/RB/mpuRb3.c | 211 -
src/vendorcode/amd/agesa/Proc/Mem/Ps/mp.c | 510 -
src/vendorcode/amd/agesa/Proc/Mem/Ps/mplribt.c | 190 -
src/vendorcode/amd/agesa/Proc/Mem/Ps/mplrnlr.c | 111 -
src/vendorcode/amd/agesa/Proc/Mem/Ps/mplrnpr.c | 111 -
src/vendorcode/amd/agesa/Proc/Mem/Ps/mpmaxfreq.c | 250 -
src/vendorcode/amd/agesa/Proc/Mem/Ps/mpmr0.c | 179 -
src/vendorcode/amd/agesa/Proc/Mem/Ps/mpodtpat.c | 189 -
src/vendorcode/amd/agesa/Proc/Mem/Ps/mprc10opspd.c | 163 -
src/vendorcode/amd/agesa/Proc/Mem/Ps/mprc2ibt.c | 210 -
src/vendorcode/amd/agesa/Proc/Mem/Ps/mprtt.c | 229 -
src/vendorcode/amd/agesa/Proc/Mem/Ps/mpsao.c | 200 -
src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR2/mt2.c | 234 -
src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR2/mt2.h | 126 -
.../amd/agesa/Proc/Mem/Tech/DDR2/mtot2.c | 164 -
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.../amd/agesa/Proc/Mem/Tech/DDR2/mtspd2.c | 1117 --
.../amd/agesa/Proc/Mem/Tech/DDR2/mtspd2.h | 184 -
src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mt3.c | 237 -
src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mt3.h | 136 -
.../amd/agesa/Proc/Mem/Tech/DDR3/mtlrdimm3.c | 1102 --
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.../amd/agesa/Proc/Mem/Tech/DDR3/mtsdi3.c | 493 -
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src/vendorcode/amd/agesa/Proc/Mem/Tech/mt.c | 264 -
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.../amd/agesa/Proc/Mem/Tech/mttEdgeDetect.h | 119 -
src/vendorcode/amd/agesa/Proc/Mem/Tech/mttdimbt.c | 1279 --
src/vendorcode/amd/agesa/Proc/Mem/Tech/mttecc.c | 209 -
src/vendorcode/amd/agesa/Proc/Mem/Tech/mtthrc.c | 306 -
src/vendorcode/amd/agesa/Proc/Mem/Tech/mttml.c | 255 -
src/vendorcode/amd/agesa/Proc/Mem/Tech/mttoptsrc.c | 427 -
src/vendorcode/amd/agesa/Proc/Mem/Tech/mttsrc.c | 346 -
src/vendorcode/amd/agesa/Proc/Mem/ma.h | 318 -
src/vendorcode/amd/agesa/Proc/Mem/memPage.h | 59 -
src/vendorcode/amd/agesa/Proc/Mem/merrhdl.h | 105 -
.../amd/agesa/Proc/Mem/mfParallelTraining.h | 115 -
.../amd/agesa/Proc/Mem/mfStandardTraining.h | 83 -
src/vendorcode/amd/agesa/Proc/Mem/mfmemclr.h | 85 -
src/vendorcode/amd/agesa/Proc/Mem/mfs3.h | 283 -
src/vendorcode/amd/agesa/Proc/Mem/mftds.h | 82 -
src/vendorcode/amd/agesa/Proc/Mem/mm.h | 1003 --
src/vendorcode/amd/agesa/Proc/Mem/mn.h | 1375 ---
src/vendorcode/amd/agesa/Proc/Mem/mp.h | 569 -
src/vendorcode/amd/agesa/Proc/Mem/mport.h | 69 -
src/vendorcode/amd/agesa/Proc/Mem/mt.h | 435 -
src/vendorcode/amd/agesa/Proc/Mem/mu.h | 238 -
.../amd/agesa/Proc/Recovery/CPU/cpuRecovery.c | 104 -
.../amd/agesa/Proc/Recovery/CPU/cpuRecovery.h | 77 -
.../amd/agesa/Proc/Recovery/GNB/GfxRecovery.c | 112 -
.../amd/agesa/Proc/Recovery/GNB/GfxRecovery.h | 77 -
.../amd/agesa/Proc/Recovery/GNB/GnbRecovery.c | 103 -
.../amd/agesa/Proc/Recovery/GNB/NbInitRecovery.c | 138 -
.../amd/agesa/Proc/Recovery/GNB/NbInitRecovery.h | 57 -
.../amd/agesa/Proc/Recovery/HT/htInitRecovery.c | 163 -
.../amd/agesa/Proc/Recovery/HT/htInitReset.c | 332 -
.../amd/agesa/Proc/Recovery/Mem/NB/C32/mrnc32.c | 711 --
.../amd/agesa/Proc/Recovery/Mem/NB/C32/mrnc32.h | 110 -
.../amd/agesa/Proc/Recovery/Mem/NB/C32/mrnmctc32.c | 162 -
.../agesa/Proc/Recovery/Mem/NB/C32/mrnprotoc32.c | 62 -
.../amd/agesa/Proc/Recovery/Mem/NB/DA/mrnda.c | 651 -
.../amd/agesa/Proc/Recovery/Mem/NB/DA/mrnda.h | 110 -
.../amd/agesa/Proc/Recovery/Mem/NB/DA/mrnmctda.c | 165 -
.../amd/agesa/Proc/Recovery/Mem/NB/DR/mrndr.c | 655 --
.../amd/agesa/Proc/Recovery/Mem/NB/DR/mrndr.h | 110 -
.../amd/agesa/Proc/Recovery/Mem/NB/DR/mrnmctdr.c | 167 -
.../amd/agesa/Proc/Recovery/Mem/NB/HY/mrndcthy.c | 76 -
.../amd/agesa/Proc/Recovery/Mem/NB/HY/mrnhy.c | 710 --
.../amd/agesa/Proc/Recovery/Mem/NB/HY/mrnhy.h | 110 -
.../amd/agesa/Proc/Recovery/Mem/NB/HY/mrnmcthy.c | 162 -
.../amd/agesa/Proc/Recovery/Mem/NB/HY/mrnprotohy.c | 62 -
.../amd/agesa/Proc/Recovery/Mem/NB/NI/mrnNi.c | 651 -
.../amd/agesa/Proc/Recovery/Mem/NB/NI/mrnNi.h | 97 -
.../amd/agesa/Proc/Recovery/Mem/NB/ON/mrndcton.c | 363 -
.../amd/agesa/Proc/Recovery/Mem/NB/ON/mrnmcton.c | 191 -
.../amd/agesa/Proc/Recovery/Mem/NB/ON/mrnon.c | 653 -
.../amd/agesa/Proc/Recovery/Mem/NB/ON/mrnon.h | 125 -
.../amd/agesa/Proc/Recovery/Mem/NB/PH/mrnPh.c | 652 -
.../amd/agesa/Proc/Recovery/Mem/NB/PH/mrnPh.h | 97 -
.../amd/agesa/Proc/Recovery/Mem/NB/RB/mrnRb.c | 651 -
.../amd/agesa/Proc/Recovery/Mem/NB/RB/mrnRb.h | 97 -
.../amd/agesa/Proc/Recovery/Mem/NB/mrn.c | 190 -
.../amd/agesa/Proc/Recovery/Mem/NB/mrndct.c | 1502 ---
.../amd/agesa/Proc/Recovery/Mem/NB/mrnmct.c | 298 -
.../amd/agesa/Proc/Recovery/Mem/NB/mrntrain3.c | 127 -
.../amd/agesa/Proc/Recovery/Mem/Ps/mrp.c | 261 -
.../amd/agesa/Proc/Recovery/Mem/Ps/mrplribt.c | 183 -
.../amd/agesa/Proc/Recovery/Mem/Ps/mrplrnlr.c | 111 -
.../amd/agesa/Proc/Recovery/Mem/Ps/mrplrnpr.c | 111 -
.../amd/agesa/Proc/Recovery/Mem/Ps/mrpmr0.c | 178 -
.../amd/agesa/Proc/Recovery/Mem/Ps/mrpodtpat.c | 183 -
.../amd/agesa/Proc/Recovery/Mem/Ps/mrprc10opspd.c | 93 -
.../amd/agesa/Proc/Recovery/Mem/Ps/mrprc2ibt.c | 199 -
.../amd/agesa/Proc/Recovery/Mem/Ps/mrprtt.c | 218 -
.../amd/agesa/Proc/Recovery/Mem/Ps/mrpsao.c | 188 -
.../amd/agesa/Proc/Recovery/Mem/Tech/DDR3/mrt3.c | 189 -
.../agesa/Proc/Recovery/Mem/Tech/DDR3/mrtrci3.c | 244 -
.../agesa/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c | 360 -
.../agesa/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.c | 326 -
.../agesa/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.h | 132 -
.../agesa/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c | 347 -
.../amd/agesa/Proc/Recovery/Mem/Tech/mrtthrc.c | 287 -
.../amd/agesa/Proc/Recovery/Mem/Tech/mrttpos.c | 115 -
.../amd/agesa/Proc/Recovery/Mem/Tech/mrttsrc.c | 437 -
src/vendorcode/amd/agesa/Proc/Recovery/Mem/mrdef.c | 129 -
.../amd/agesa/Proc/Recovery/Mem/mrinit.c | 126 -
src/vendorcode/amd/agesa/Proc/Recovery/Mem/mrm.c | 288 -
.../amd/agesa/Proc/Recovery/Mem/mrport.h | 82 -
src/vendorcode/amd/agesa/Proc/Recovery/Mem/mrt3.h | 121 -
src/vendorcode/amd/agesa/Proc/Recovery/Mem/mru.asm | 187 -
src/vendorcode/amd/agesa/Proc/Recovery/Mem/mru.h | 140 -
src/vendorcode/amd/agesa/Proc/Recovery/Mem/mruc.c | 267 -
.../amd/agesa/Proc/Recovery/recoveryPage.h | 59 -
src/vendorcode/amd/agesa/cpcar.inc | 1124 --
src/vendorcode/amd/agesa/cpcarmac.inc | 447 -
src/vendorcode/amd/agesa/errno.h | 38 -
src/vendorcode/amd/agesa/f14/AGESA.h | 3022 +++++
src/vendorcode/amd/agesa/f14/AMD.h | 482 +
src/vendorcode/amd/agesa/f14/Dispatcher.h | 54 +
src/vendorcode/amd/agesa/f14/Include/AdvancedApi.h | 168 +
.../amd/agesa/f14/Include/BrazosInstall.h | 102 +
.../amd/agesa/f14/Include/CommonReturns.h | 125 +
.../amd/agesa/f14/Include/DanNiInstall.h | 117 +
.../amd/agesa/f14/Include/DanubeInstall.h | 102 +
.../amd/agesa/f14/Include/DevTestInstall.h | 111 +
.../amd/agesa/f14/Include/DragonInstall.h | 102 +
src/vendorcode/amd/agesa/f14/Include/Filecode.h | 849 ++
.../amd/agesa/f14/Include/GeneralServices.h | 203 +
.../amd/agesa/f14/Include/GnbInterface.h | 96 +
.../amd/agesa/f14/Include/GnbInterfaceStub.h | 232 +
src/vendorcode/amd/agesa/f14/Include/Ids.h | 927 ++
src/vendorcode/amd/agesa/f14/Include/IdsHt.h | 126 +
src/vendorcode/amd/agesa/f14/Include/LynxInstall.h | 102 +
.../amd/agesa/f14/Include/MaranelloInstall.h | 118 +
src/vendorcode/amd/agesa/f14/Include/NileInstall.h | 102 +
.../amd/agesa/f14/Include/OptionC6Install.h | 151 +
.../amd/agesa/f14/Include/OptionCpbInstall.h | 122 +
.../f14/Include/OptionCpuCacheFlushOnHaltInstall.h | 120 +
.../f14/Include/OptionCpuCoreLevelingInstall.h | 115 +
.../agesa/f14/Include/OptionCpuFamiliesInstall.h | 406 +
.../agesa/f14/Include/OptionCpuFeaturesInstall.h | 78 +
src/vendorcode/amd/agesa/f14/Include/OptionDmi.h | 92 +
.../amd/agesa/f14/Include/OptionDmiInstall.h | 194 +
.../amd/agesa/f14/Include/OptionFamily10hInstall.h | 1996 ++++
.../agesa/f14/Include/OptionFamily12hEarlySample.h | 138 +
.../amd/agesa/f14/Include/OptionFamily12hInstall.h | 665 ++
.../agesa/f14/Include/OptionFamily14hEarlySample.h | 170 +
.../amd/agesa/f14/Include/OptionFamily14hInstall.h | 661 ++
.../amd/agesa/f14/Include/OptionFamily15hInstall.h | 717 ++
.../amd/agesa/f14/Include/OptionGfxRecovery.h | 84 +
.../agesa/f14/Include/OptionGfxRecoveryInstall.h | 56 +
src/vendorcode/amd/agesa/f14/Include/OptionGnb.h | 92 +
.../amd/agesa/f14/Include/OptionGnbInstall.h | 449 +
.../amd/agesa/f14/Include/OptionHtAssistInstall.h | 109 +
.../amd/agesa/f14/Include/OptionHtInstall.h | 301 +
.../amd/agesa/f14/Include/OptionHwC1eInstall.h | 83 +
.../amd/agesa/f14/Include/OptionIdsInstall.h | 417 +
.../amd/agesa/f14/Include/OptionIoCstateInstall.h | 135 +
.../agesa/f14/Include/OptionLowPwrPstateInstall.h | 89 +
.../amd/agesa/f14/Include/OptionMemory.h | 342 +
.../amd/agesa/f14/Include/OptionMemoryInstall.h | 4051 +++++++
.../amd/agesa/f14/Include/OptionMemoryRecovery.h | 65 +
.../f14/Include/OptionMemoryRecoveryInstall.h | 602 +
.../agesa/f14/Include/OptionMsgBasedC1eInstall.h | 119 +
.../amd/agesa/f14/Include/OptionMultiSocket.h | 169 +
.../agesa/f14/Include/OptionMultiSocketInstall.h | 92 +
.../f14/Include/OptionPreserveMailboxInstall.h | 107 +
.../amd/agesa/f14/Include/OptionPstate.h | 118 +
.../amd/agesa/f14/Include/OptionPstateInstall.h | 243 +
.../amd/agesa/f14/Include/OptionS3ScriptInstall.h | 94 +
src/vendorcode/amd/agesa/f14/Include/OptionSlit.h | 99 +
.../amd/agesa/f14/Include/OptionSlitInstall.h | 82 +
src/vendorcode/amd/agesa/f14/Include/OptionSrat.h | 85 +
.../amd/agesa/f14/Include/OptionSratInstall.h | 76 +
.../amd/agesa/f14/Include/OptionSwC1eInstall.h | 83 +
src/vendorcode/amd/agesa/f14/Include/OptionWhea.h | 86 +
.../amd/agesa/f14/Include/OptionWheaInstall.h | 77 +
src/vendorcode/amd/agesa/f14/Include/Options.h | 94 +
src/vendorcode/amd/agesa/f14/Include/OptionsHt.h | 103 +
src/vendorcode/amd/agesa/f14/Include/OptionsPage.h | 375 +
.../amd/agesa/f14/Include/PlatformInstall.h | 2599 ++++
.../f14/Include/PlatformMemoryConfiguration.h | 314 +
.../amd/agesa/f14/Include/SabineInstall.h | 117 +
.../amd/agesa/f14/Include/SanMarinoInstall.h | 118 +
.../amd/agesa/f14/Include/ScorpiusInstall.h | 117 +
.../amd/agesa/f14/Include/TigrisInstall.h | 102 +
src/vendorcode/amd/agesa/f14/Include/Topology.h | 165 +
src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h | 630 +
.../f14/Legacy/PlatformMemoryConfiguration.inc | 402 +
.../amd/agesa/f14/Legacy/Proc/Dispatcher.c | 161 +
.../amd/agesa/f14/Legacy/Proc/Legacy.bat | 286 +
.../amd/agesa/f14/Legacy/Proc/agesaCallouts.c | 397 +
.../amd/agesa/f14/Legacy/Proc/arch2008.asm | 2674 +++++
.../amd/agesa/f14/Legacy/Proc/hobTransfer.c | 394 +
src/vendorcode/amd/agesa/f14/Legacy/agesa.inc | 2547 ++++
src/vendorcode/amd/agesa/f14/Legacy/amd.inc | 461 +
src/vendorcode/amd/agesa/f14/Legacy/bridge32.inc | 577 +
src/vendorcode/amd/agesa/f14/Lib/IA32/amdlib32.asm | 151 +
src/vendorcode/amd/agesa/f14/Lib/IA32/ms_shift.asm | 110 +
src/vendorcode/amd/agesa/f14/Lib/IA32/msmemcpy.asm | 84 +
src/vendorcode/amd/agesa/f14/Lib/amdlib.c | 1340 +++
src/vendorcode/amd/agesa/f14/Lib/amdlib.h | 421 +
src/vendorcode/amd/agesa/f14/Lib/helper.c | 68 +
src/vendorcode/amd/agesa/f14/Lib/x64/amdlib64.asm | 591 +
src/vendorcode/amd/agesa/f14/MainPage.h | 121 +
src/vendorcode/amd/agesa/f14/Makefile.inc | 62 +
src/vendorcode/amd/agesa/f14/Porting.h | 296 +
.../f14/Proc/CPU/Family/0x10/F10InitEarlyTable.c | 119 +
.../agesa/f14/Proc/CPU/Family/0x10/F10IoCstate.c | 294 +
.../Proc/CPU/Family/0x10/F10MultiLinkPciTables.c | 1527 +++
.../f14/Proc/CPU/Family/0x10/F10PackageType.h | 85 +
.../f14/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c | 182 +
.../f14/Proc/CPU/Family/0x10/F10PmAsymBoostInit.h | 79 +
.../CPU/Family/0x10/F10PmDualPlaneOnlySupport.c | 246 +
.../CPU/Family/0x10/F10PmDualPlaneOnlySupport.h | 79 +
.../f14/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c | 300 +
.../f14/Proc/CPU/Family/0x10/F10PmNbCofVidInit.h | 78 +
.../f14/Proc/CPU/Family/0x10/F10PmNbPstateInit.c | 188 +
.../f14/Proc/CPU/Family/0x10/F10PmNbPstateInit.h | 78 +
.../Proc/CPU/Family/0x10/F10SingleLinkPciTables.c | 1942 +++
.../Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c | 151 +
.../Family/0x10/RevC/BL/F10BlEquivalenceTable.c | 107 +
.../CPU/Family/0x10/RevC/BL/F10BlHtPhyTables.c | 123 +
.../CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c | 107 +
.../0x10/RevC/BL/F10BlMicrocodePatchTables.c | 107 +
.../Proc/CPU/Family/0x10/RevC/BL/F10BlMsrTables.c | 107 +
.../Proc/CPU/Family/0x10/RevC/BL/F10BlPciTables.c | 197 +
.../Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c | 144 +
.../Family/0x10/RevC/DA/F10DaEquivalenceTable.c | 108 +
.../CPU/Family/0x10/RevC/DA/F10DaHtPhyTables.c | 284 +
.../CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c | 108 +
.../0x10/RevC/DA/F10DaMicrocodePatchTables.c | 107 +
.../Proc/CPU/Family/0x10/RevC/DA/F10DaMsrTables.c | 107 +
.../Proc/CPU/Family/0x10/RevC/DA/F10DaPciTables.c | 193 +
.../Family/0x10/RevC/F10MicrocodePatch01000085.c | 1038 ++
.../Family/0x10/RevC/F10MicrocodePatch010000c6.c | 1038 ++
.../Family/0x10/RevC/F10MicrocodePatch010000c7.c | 1038 ++
.../Family/0x10/RevC/F10MicrocodePatch010000c8.c | 1038 ++
.../Proc/CPU/Family/0x10/RevC/F10RevCHtPhyTables.c | 440 +
.../f14/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c | 189 +
.../Proc/CPU/Family/0x10/RevC/F10RevCMsrTables.c | 134 +
.../Proc/CPU/Family/0x10/RevC/F10RevCPciTables.c | 266 +
.../f14/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c | 182 +
.../Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c | 436 +
.../Family/0x10/RevC/RB/F10RbEquivalenceTable.c | 111 +
.../CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c | 121 +
.../CPU/Family/0x10/RevC/RB/F10RbLogicalIdTables.c | 115 +
.../0x10/RevC/RB/F10RbMicrocodePatchTables.c | 107 +
.../Proc/CPU/Family/0x10/RevC/RB/F10RbMsrTables.c | 121 +
.../Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c | 235 +
.../Family/0x10/RevD/F10MicrocodePatch010000c4.c | 1040 ++
.../Family/0x10/RevD/F10MicrocodePatch010000c5.c | 1040 ++
.../f14/Proc/CPU/Family/0x10/RevD/F10RevD32.asm | 113 +
.../f14/Proc/CPU/Family/0x10/RevD/F10RevD64.asm | 127 +
.../Proc/CPU/Family/0x10/RevD/F10RevDHtAssist.c | 466 +
.../Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c | 277 +
.../Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c | 370 +
.../Family/0x10/RevD/HY/F10HyEquivalenceTable.c | 107 +
.../CPU/Family/0x10/RevD/HY/F10HyHtPhyTables.c | 1295 ++
.../CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c | 137 +
.../CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c | 109 +
.../0x10/RevD/HY/F10HyMicrocodePatchTables.c | 107 +
.../Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c | 138 +
.../Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c | 350 +
.../Family/0x10/RevE/F10MicrocodePatch010000bf.c | 1040 ++
.../Proc/CPU/Family/0x10/RevE/F10RevEHtPhyTables.c | 374 +
.../Proc/CPU/Family/0x10/RevE/F10RevEMsrTables.c | 135 +
.../Proc/CPU/Family/0x10/RevE/F10RevEPciTables.c | 227 +
.../Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c | 370 +
.../Family/0x10/RevE/PH/F10PhEquivalenceTable.c | 106 +
.../CPU/Family/0x10/RevE/PH/F10PhHtPhyTables.c | 118 +
.../CPU/Family/0x10/RevE/PH/F10PhLogicalIdTables.c | 97 +
.../0x10/RevE/PH/F10PhMicrocodePatchTables.c | 106 +
.../Proc/CPU/Family/0x10/cpuCommonF10Utilities.c | 330 +
.../Proc/CPU/Family/0x10/cpuCommonF10Utilities.h | 100 +
.../agesa/f14/Proc/CPU/Family/0x10/cpuF10BrandId.c | 145 +
.../f14/Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c | 333 +
.../f14/Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c | 138 +
.../f14/Proc/CPU/Family/0x10/cpuF10BrandIdC32.c | 134 +
.../f14/Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c | 175 +
.../f14/Proc/CPU/Family/0x10/cpuF10BrandIdG34.c | 128 +
.../f14/Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c | 129 +
.../f14/Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c | 144 +
.../f14/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c | 127 +
.../Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c | 144 +
.../amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Cpb.c | 179 +
.../amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Dmi.c | 478 +
.../f14/Proc/CPU/Family/0x10/cpuF10EarlyInit.c | 424 +
.../f14/Proc/CPU/Family/0x10/cpuF10EarlyInit.h | 80 +
.../Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c | 394 +
.../Proc/CPU/Family/0x10/cpuF10FeatureLeveling.h | 196 +
.../f14/Proc/CPU/Family/0x10/cpuF10HtPhyTables.c | 752 ++
.../f14/Proc/CPU/Family/0x10/cpuF10MsrTables.c | 275 +
.../f14/Proc/CPU/Family/0x10/cpuF10PciTables.c | 773 ++
.../f14/Proc/CPU/Family/0x10/cpuF10PowerCheck.c | 421 +
.../f14/Proc/CPU/Family/0x10/cpuF10PowerCheck.h | 84 +
.../f14/Proc/CPU/Family/0x10/cpuF10PowerMgmt.h | 548 +
.../CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c | 176 +
.../f14/Proc/CPU/Family/0x10/cpuF10PowerPlane.c | 484 +
.../f14/Proc/CPU/Family/0x10/cpuF10PowerPlane.h | 78 +
.../agesa/f14/Proc/CPU/Family/0x10/cpuF10Pstate.c | 863 ++
.../Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c | 124 +
.../Proc/CPU/Family/0x10/cpuF10SoftwareThermal.h | 80 +
.../f14/Proc/CPU/Family/0x10/cpuF10Utilities.c | 1119 ++
.../f14/Proc/CPU/Family/0x10/cpuF10Utilities.h | 165 +
.../CPU/Family/0x10/cpuF10WheaInitDataTables.c | 121 +
.../Proc/CPU/Family/0x10/cpuF10WorkaroundsTable.c | 106 +
.../agesa/f14/Proc/CPU/Family/0x14/F14C6State.c | 238 +
.../agesa/f14/Proc/CPU/Family/0x14/F14IoCstate.c | 285 +
.../CPU/Family/0x14/F14MicrocodePatch0500000B.c | 1645 +++
.../CPU/Family/0x14/F14MicrocodePatch0500001A.c | 1645 +++
.../CPU/Family/0x14/F14MicrocodePatch05000025.c | 1645 +++
.../f14/Proc/CPU/Family/0x14/F14PackageType.h | 77 +
.../CPU/Family/0x14/ON/F14OnEquivalenceTable.c | 125 +
.../Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.c | 309 +
.../Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.h | 69 +
.../Proc/CPU/Family/0x14/ON/F14OnLogicalIdTables.c | 102 +
.../CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c | 102 +
.../Proc/CPU/Family/0x14/cpuCommonF14Utilities.c | 518 +
.../Proc/CPU/Family/0x14/cpuCommonF14Utilities.h | 104 +
.../agesa/f14/Proc/CPU/Family/0x14/cpuF14BrandId.c | 139 +
.../f14/Proc/CPU/Family/0x14/cpuF14BrandIdFt1.c | 145 +
.../f14/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c | 123 +
.../amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Dmi.c | 272 +
.../f14/Proc/CPU/Family/0x14/cpuF14MsrTables.c | 198 +
.../f14/Proc/CPU/Family/0x14/cpuF14PciTables.c | 716 ++
.../Proc/CPU/Family/0x14/cpuF14PerCorePciTables.c | 102 +
.../f14/Proc/CPU/Family/0x14/cpuF14PowerCheck.c | 358 +
.../f14/Proc/CPU/Family/0x14/cpuF14PowerCheck.h | 83 +
.../f14/Proc/CPU/Family/0x14/cpuF14PowerMgmt.h | 477 +
.../CPU/Family/0x14/cpuF14PowerMgmtSystemTables.c | 133 +
.../f14/Proc/CPU/Family/0x14/cpuF14PowerPlane.c | 272 +
.../f14/Proc/CPU/Family/0x14/cpuF14PowerPlane.h | 78 +
.../agesa/f14/Proc/CPU/Family/0x14/cpuF14Pstate.c | 364 +
.../Proc/CPU/Family/0x14/cpuF14SoftwareThermal.c | 112 +
.../Proc/CPU/Family/0x14/cpuF14SoftwareThermal.h | 80 +
.../f14/Proc/CPU/Family/0x14/cpuF14Utilities.c | 539 +
.../f14/Proc/CPU/Family/0x14/cpuF14Utilities.h | 132 +
.../CPU/Family/0x14/cpuF14WheaInitDataTables.c | 117 +
.../agesa/f14/Proc/CPU/Family/cpuFamRegisters.h | 213 +
.../agesa/f14/Proc/CPU/Feature/PreserveMailbox.c | 218 +
.../agesa/f14/Proc/CPU/Feature/PreserveMailbox.h | 89 +
.../amd/agesa/f14/Proc/CPU/Feature/cpuC6State.c | 262 +
.../amd/agesa/f14/Proc/CPU/Feature/cpuC6State.h | 156 +
.../f14/Proc/CPU/Feature/cpuCacheFlushOnHalt.c | 193 +
.../amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.c | 744 ++
.../amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.h | 134 +
.../agesa/f14/Proc/CPU/Feature/cpuCoreLeveling.c | 353 +
.../amd/agesa/f14/Proc/CPU/Feature/cpuCpb.c | 177 +
.../amd/agesa/f14/Proc/CPU/Feature/cpuCpb.h | 135 +
.../amd/agesa/f14/Proc/CPU/Feature/cpuDmi.c | 681 ++
.../f14/Proc/CPU/Feature/cpuFeatureLeveling.c | 266 +
.../amd/agesa/f14/Proc/CPU/Feature/cpuFeatures.c | 198 +
.../amd/agesa/f14/Proc/CPU/Feature/cpuFeatures.h | 267 +
.../amd/agesa/f14/Proc/CPU/Feature/cpuHtAssist.c | 357 +
.../amd/agesa/f14/Proc/CPU/Feature/cpuHtAssist.h | 301 +
.../amd/agesa/f14/Proc/CPU/Feature/cpuHwC1e.c | 175 +
.../amd/agesa/f14/Proc/CPU/Feature/cpuHwC1e.h | 127 +
.../amd/agesa/f14/Proc/CPU/Feature/cpuIoCstate.c | 209 +
.../amd/agesa/f14/Proc/CPU/Feature/cpuIoCstate.h | 285 +
.../agesa/f14/Proc/CPU/Feature/cpuLowPwrPstate.c | 206 +
.../agesa/f14/Proc/CPU/Feature/cpuLowPwrPstate.h | 133 +
.../agesa/f14/Proc/CPU/Feature/cpuMsgBasedC1e.c | 213 +
.../agesa/f14/Proc/CPU/Feature/cpuMsgBasedC1e.h | 129 +
.../agesa/f14/Proc/CPU/Feature/cpuPstateGather.c | 397 +
.../agesa/f14/Proc/CPU/Feature/cpuPstateLeveling.c | 1073 ++
.../agesa/f14/Proc/CPU/Feature/cpuPstateTables.c | 830 ++
.../agesa/f14/Proc/CPU/Feature/cpuPstateTables.h | 329 +
.../amd/agesa/f14/Proc/CPU/Feature/cpuSlit.c | 357 +
.../amd/agesa/f14/Proc/CPU/Feature/cpuSrat.c | 565 +
.../amd/agesa/f14/Proc/CPU/Feature/cpuSwC1e.c | 176 +
.../amd/agesa/f14/Proc/CPU/Feature/cpuSwC1e.h | 121 +
.../amd/agesa/f14/Proc/CPU/Feature/cpuWhea.c | 271 +
src/vendorcode/amd/agesa/f14/Proc/CPU/S3.c | 1219 ++
src/vendorcode/amd/agesa/f14/Proc/CPU/S3.h | 395 +
src/vendorcode/amd/agesa/f14/Proc/CPU/Table.c | 1664 +++
src/vendorcode/amd/agesa/f14/Proc/CPU/Table.h | 1238 ++
src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.asm | 345 +
src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c | 317 +
src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt64.asm | 157 +
.../amd/agesa/f14/Proc/CPU/cpuApicUtilities.c | 1466 +++
.../amd/agesa/f14/Proc/CPU/cpuApicUtilities.h | 262 +
src/vendorcode/amd/agesa/f14/Proc/CPU/cpuBist.c | 173 +
src/vendorcode/amd/agesa/f14/Proc/CPU/cpuBrandId.c | 309 +
.../amd/agesa/f14/Proc/CPU/cpuEarlyInit.c | 404 +
.../amd/agesa/f14/Proc/CPU/cpuEarlyInit.h | 250 +
src/vendorcode/amd/agesa/f14/Proc/CPU/cpuEnvInit.h | 75 +
.../amd/agesa/f14/Proc/CPU/cpuEventLog.c | 399 +
.../amd/agesa/f14/Proc/CPU/cpuFamilyTranslation.c | 483 +
.../amd/agesa/f14/Proc/CPU/cpuFamilyTranslation.h | 957 ++
.../amd/agesa/f14/Proc/CPU/cpuGeneralServices.c | 1277 ++
.../amd/agesa/f14/Proc/CPU/cpuInitEarlyTable.c | 119 +
.../amd/agesa/f14/Proc/CPU/cpuLateInit.c | 286 +
.../amd/agesa/f14/Proc/CPU/cpuLateInit.h | 821 ++
.../amd/agesa/f14/Proc/CPU/cpuMicrocodePatch.c | 441 +
src/vendorcode/amd/agesa/f14/Proc/CPU/cpuPage.h | 62 +
.../amd/agesa/f14/Proc/CPU/cpuPostInit.c | 481 +
.../amd/agesa/f14/Proc/CPU/cpuPostInit.h | 228 +
.../amd/agesa/f14/Proc/CPU/cpuPowerMgmt.c | 253 +
.../agesa/f14/Proc/CPU/cpuPowerMgmtMultiSocket.c | 432 +
.../agesa/f14/Proc/CPU/cpuPowerMgmtMultiSocket.h | 102 +
.../agesa/f14/Proc/CPU/cpuPowerMgmtSingleSocket.c | 246 +
.../agesa/f14/Proc/CPU/cpuPowerMgmtSingleSocket.h | 102 +
.../agesa/f14/Proc/CPU/cpuPowerMgmtSystemTables.h | 94 +
.../amd/agesa/f14/Proc/CPU/cpuRegisters.h | 407 +
.../amd/agesa/f14/Proc/CPU/cpuServices.h | 347 +
.../amd/agesa/f14/Proc/CPU/cpuWarmReset.c | 237 +
.../amd/agesa/f14/Proc/CPU/heapManager.c | 853 ++
.../amd/agesa/f14/Proc/CPU/heapManager.h | 230 +
.../amd/agesa/f14/Proc/Common/AmdInitEarly.c | 281 +
.../amd/agesa/f14/Proc/Common/AmdInitEnv.c | 176 +
.../amd/agesa/f14/Proc/Common/AmdInitLate.c | 292 +
.../amd/agesa/f14/Proc/Common/AmdInitMid.c | 162 +
.../amd/agesa/f14/Proc/Common/AmdInitPost.c | 339 +
.../amd/agesa/f14/Proc/Common/AmdInitRecovery.c | 171 +
.../amd/agesa/f14/Proc/Common/AmdInitReset.c | 245 +
.../amd/agesa/f14/Proc/Common/AmdInitResume.c | 233 +
.../amd/agesa/f14/Proc/Common/AmdLateRunApTask.c | 160 +
.../amd/agesa/f14/Proc/Common/AmdS3LateRestore.c | 215 +
.../amd/agesa/f14/Proc/Common/AmdS3Save.c | 381 +
.../amd/agesa/f14/Proc/Common/CommonInits.c | 137 +
.../amd/agesa/f14/Proc/Common/CommonInits.h | 66 +
.../amd/agesa/f14/Proc/Common/CommonPage.h | 118 +
.../amd/agesa/f14/Proc/Common/CommonReturns.c | 174 +
.../amd/agesa/f14/Proc/Common/CreateStruct.c | 315 +
.../amd/agesa/f14/Proc/Common/CreateStruct.h | 197 +
.../amd/agesa/f14/Proc/Common/S3RestoreState.c | 443 +
.../amd/agesa/f14/Proc/Common/S3SaveState.c | 647 +
.../amd/agesa/f14/Proc/Common/S3SaveState.h | 357 +
src/vendorcode/amd/agesa/f14/Proc/GNB/Common/Gnb.h | 104 +
.../amd/agesa/f14/Proc/GNB/Common/GnbFuseTable.h | 80 +
.../amd/agesa/f14/Proc/GNB/Common/GnbGfx.h | 290 +
.../agesa/f14/Proc/GNB/Common/GnbGfxFamServices.h | 63 +
.../amd/agesa/f14/Proc/GNB/Common/GnbLibFeatures.c | 116 +
.../amd/agesa/f14/Proc/GNB/Common/GnbLibFeatures.h | 56 +
.../amd/agesa/f14/Proc/GNB/Common/GnbPcie.h | 352 +
.../agesa/f14/Proc/GNB/Common/GnbPcieFamServices.h | 117 +
.../amd/agesa/f14/Proc/GNB/Common/GnbRegistersON.h |12425 ++++++++++++++++++++
.../f14/Proc/GNB/Gfx/Family/0x14/F14GfxServices.c | 524 +
.../f14/Proc/GNB/Gfx/Family/GfxFamilyServices.h | 62 +
.../amd/agesa/f14/Proc/GNB/Gfx/GfxConfigData.c | 131 +
.../amd/agesa/f14/Proc/GNB/Gfx/GfxConfigData.h | 74 +
.../amd/agesa/f14/Proc/GNB/Gfx/GfxGmcInit.c | 722 ++
.../amd/agesa/f14/Proc/GNB/Gfx/GfxGmcInit.h | 56 +
.../amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtEnvPost.c | 112 +
.../amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtEnvPost.h | 55 +
.../amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtMidPost.c | 131 +
.../amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtMidPost.h | 56 +
.../amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtPost.c | 126 +
.../amd/agesa/f14/Proc/GNB/Gfx/GfxInitAtPost.h | 56 +
.../f14/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c | 666 ++
.../f14/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.h | 57 +
src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxLib.c | 364 +
src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/GfxLib.h | 98 +
.../amd/agesa/f14/Proc/GNB/Gfx/GfxRegisterAcc.c | 209 +
.../amd/agesa/f14/Proc/GNB/Gfx/GfxRegisterAcc.h | 113 +
.../amd/agesa/f14/Proc/GNB/Gfx/GfxStrapsInit.c | 315 +
.../amd/agesa/f14/Proc/GNB/Gfx/GfxStrapsInit.h | 78 +
.../amd/agesa/f14/Proc/GNB/GnbInitAtEarly.c | 95 +
.../amd/agesa/f14/Proc/GNB/GnbInitAtEnv.c | 112 +
.../amd/agesa/f14/Proc/GNB/GnbInitAtLate.c | 93 +
.../amd/agesa/f14/Proc/GNB/GnbInitAtMid.c | 93 +
.../amd/agesa/f14/Proc/GNB/GnbInitAtPost.c | 115 +
.../amd/agesa/f14/Proc/GNB/GnbInitAtReset.c | 90 +
src/vendorcode/amd/agesa/f14/Proc/GNB/GnbPage.h | 1858 +++
.../Proc/GNB/Modules/GnbCableSafe/GnbCableSafe.c | 222 +
.../GNB/Modules/GnbCableSafe/GnbCableSafeDefs.h | 66 +
.../Proc/GNB/Modules/GnbCommonLib/GnbCommonLib.h | 58 +
.../f14/Proc/GNB/Modules/GnbCommonLib/GnbLib.c | 460 +
.../f14/Proc/GNB/Modules/GnbCommonLib/GnbLib.h | 148 +
.../Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c | 130 +
.../Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.h | 66 +
.../f14/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c | 129 +
.../f14/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.h | 63 +
.../Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c | 123 +
.../Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.h | 67 +
.../Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c | 126 +
.../Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.h | 74 +
.../f14/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c | 405 +
.../f14/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.h | 148 +
.../Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c | 157 +
.../Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.h | 74 +
.../Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c | 176 +
.../Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c | 180 +
.../Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.h | 55 +
.../Proc/GNB/Modules/GnbGfxConfig/GnbGfxConfig.h | 56 +
.../Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c | 185 +
.../Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.h | 64 +
.../Modules/GnbGfxInitLibV1/GfxEnumConnectors.c | 574 +
.../Modules/GnbGfxInitLibV1/GfxEnumConnectors.h | 65 +
.../Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c | 572 +
.../Modules/GnbGfxInitLibV1/GfxPowerPlayTable.h | 200 +
.../GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.h | 56 +
.../GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c | 247 +
.../GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h | 74 +
.../f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c | 351 +
.../f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.h | 83 +
.../GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl | 68 +
.../GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl | 373 +
.../GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl | 328 +
.../GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl | 682 ++
.../Proc/GNB/Modules/GnbPcieConfig/GnbPcieConfig.h | 54 +
.../GNB/Modules/GnbPcieConfig/PcieConfigData.c | 379 +
.../GNB/Modules/GnbPcieConfig/PcieConfigData.h | 65 +
.../Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c | 356 +
.../Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h | 123 +
.../GNB/Modules/GnbPcieConfig/PcieInputParser.c | 218 +
.../GNB/Modules/GnbPcieConfig/PcieInputParser.h | 75 +
.../GNB/Modules/GnbPcieConfig/PcieMapTopology.c | 720 ++
.../GNB/Modules/GnbPcieConfig/PcieMapTopology.h | 58 +
.../Modules/GnbPcieInitLibV1/GnbPcieInitLibV1.h | 62 +
.../Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.c | 346 +
.../Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.h | 57 +
.../Modules/GnbPcieInitLibV1/PcieAspmBlackList.c | 141 +
.../Modules/GnbPcieInitLibV1/PcieAspmBlackList.h | 56 +
.../Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c | 192 +
.../Modules/GnbPcieInitLibV1/PcieAspmExitLatency.h | 56 +
.../GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c | 197 +
.../GNB/Modules/GnbPcieInitLibV1/PciePhyServices.h | 61 +
.../GNB/Modules/GnbPcieInitLibV1/PciePifServices.c | 558 +
.../GNB/Modules/GnbPcieInitLibV1/PciePifServices.h | 107 +
.../GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c | 230 +
.../GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.h | 95 +
.../Modules/GnbPcieInitLibV1/PciePortServices.c | 406 +
.../Modules/GnbPcieInitLibV1/PciePortServices.h | 101 +
.../GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c | 350 +
.../GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.h | 75 +
.../Proc/GNB/Modules/GnbPcieInitLibV1/PcieSbLink.c | 221 +
.../Proc/GNB/Modules/GnbPcieInitLibV1/PcieSbLink.h | 83 +
.../Modules/GnbPcieInitLibV1/PcieSiliconServices.c | 255 +
.../Modules/GnbPcieInitLibV1/PcieSiliconServices.h | 73 +
.../GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl | 217 +
.../Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c | 100 +
.../Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.h | 56 +
.../GnbPcieInitLibV1/PcieTopologyServices.c | 692 ++
.../GnbPcieInitLibV1/PcieTopologyServices.h | 134 +
.../GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c | 437 +
.../GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h | 128 +
.../Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c | 291 +
.../Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.h | 128 +
.../Modules/GnbPcieTrainingV1/GnbPcieTrainingV1.h | 52 +
.../GNB/Modules/GnbPcieTrainingV1/PcieTraining.c | 828 ++
.../GNB/Modules/GnbPcieTrainingV1/PcieTraining.h | 64 +
.../Modules/GnbPcieTrainingV1/PcieWorkarounds.c | 375 +
.../Modules/GnbPcieTrainingV1/PcieWorkarounds.h | 56 +
.../f14/Proc/GNB/Nb/Family/0x14/F14NbLclkDpm.c | 348 +
.../Proc/GNB/Nb/Family/0x14/F14NbLclkNclkRatio.c | 222 +
.../Proc/GNB/Nb/Family/0x14/F14NbLclkNclkRatio.h | 55 +
.../f14/Proc/GNB/Nb/Family/0x14/F14NbPowerGate.c | 636 +
.../f14/Proc/GNB/Nb/Family/0x14/F14NbPowerGate.h | 61 +
.../f14/Proc/GNB/Nb/Family/0x14/F14NbServices.c | 678 ++
.../agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmu.c | 98 +
.../f14/Proc/GNB/Nb/Family/0x14/F14NbSmuFirmware.h | 981 ++
.../f14/Proc/GNB/Nb/Family/NbFamilyServices.h | 109 +
.../agesa/f14/Proc/GNB/Nb/Feature/NbFuseTable.c | 401 +
.../agesa/f14/Proc/GNB/Nb/Feature/NbFuseTable.h | 54 +
.../amd/agesa/f14/Proc/GNB/Nb/Feature/NbLclkDpm.c | 109 +
.../amd/agesa/f14/Proc/GNB/Nb/Feature/NbLclkDpm.h | 61 +
.../amd/agesa/f14/Proc/GNB/Nb/NbConfigData.c | 95 +
.../amd/agesa/f14/Proc/GNB/Nb/NbConfigData.h | 69 +
src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInit.c | 204 +
src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbInit.h | 55 +
.../amd/agesa/f14/Proc/GNB/Nb/NbInitAtEarly.c | 123 +
.../amd/agesa/f14/Proc/GNB/Nb/NbInitAtEarly.h | 54 +
.../amd/agesa/f14/Proc/GNB/Nb/NbInitAtEnv.c | 124 +
.../amd/agesa/f14/Proc/GNB/Nb/NbInitAtEnv.h | 58 +
.../amd/agesa/f14/Proc/GNB/Nb/NbInitAtLatePost.c | 122 +
.../amd/agesa/f14/Proc/GNB/Nb/NbInitAtLatePost.h | 56 +
.../amd/agesa/f14/Proc/GNB/Nb/NbInitAtPost.c | 122 +
.../amd/agesa/f14/Proc/GNB/Nb/NbInitAtPost.h | 54 +
.../amd/agesa/f14/Proc/GNB/Nb/NbInitAtReset.c | 96 +
.../amd/agesa/f14/Proc/GNB/Nb/NbInitAtReset.h | 54 +
.../amd/agesa/f14/Proc/GNB/Nb/NbPowerMgmt.c | 600 +
.../amd/agesa/f14/Proc/GNB/Nb/NbPowerMgmt.h | 70 +
.../amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.c | 652 +
.../amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.h | 185 +
.../f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.c | 72 +
.../f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.esl | 126 +
.../Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h | 660 ++
.../GNB/PCIe/Family/0x14/F14PcieComplexConfig.c | 125 +
.../GNB/PCIe/Family/0x14/F14PcieComplexServices.c | 243 +
.../Proc/GNB/PCIe/Family/0x14/F14PciePhyServices.c | 167 +
.../Proc/GNB/PCIe/Family/0x14/F14PciePifServices.c | 120 +
.../GNB/PCIe/Family/0x14/F14PcieWrapperServices.c | 631 +
.../Proc/GNB/PCIe/Family/0x14/OntarioComplexData.h | 241 +
.../Proc/GNB/PCIe/Family/0x14/OntarioDefinitions.h | 102 +
.../f14/Proc/GNB/PCIe/Family/PcieFamilyServices.h | 135 +
.../f14/Proc/GNB/PCIe/Feature/PCieSmuLibV1.esl | 217 +
.../f14/Proc/GNB/PCIe/Feature/PciePowerGate.c | 372 +
.../f14/Proc/GNB/PCIe/Feature/PciePowerGate.h | 69 +
.../amd/agesa/f14/Proc/GNB/PCIe/PcieInit.c | 349 +
.../amd/agesa/f14/Proc/GNB/PCIe/PcieInit.h | 67 +
.../agesa/f14/Proc/GNB/PCIe/PcieInitAtEarlyPost.c | 125 +
.../agesa/f14/Proc/GNB/PCIe/PcieInitAtEarlyPost.h | 55 +
.../amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtEnv.c | 93 +
.../amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtEnv.h | 55 +
.../agesa/f14/Proc/GNB/PCIe/PcieInitAtLatePost.c | 114 +
.../agesa/f14/Proc/GNB/PCIe/PcieInitAtLatePost.h | 55 +
.../amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtPost.c | 139 +
.../amd/agesa/f14/Proc/GNB/PCIe/PcieInitAtPost.h | 62 +
.../amd/agesa/f14/Proc/GNB/PCIe/PcieLateInit.c | 154 +
.../amd/agesa/f14/Proc/GNB/PCIe/PcieLateInit.h | 56 +
.../amd/agesa/f14/Proc/GNB/PCIe/PcieMiscLib.c | 158 +
.../amd/agesa/f14/Proc/GNB/PCIe/PcieMiscLib.h | 56 +
.../amd/agesa/f14/Proc/GNB/PCIe/PciePortInit.c | 256 +
.../amd/agesa/f14/Proc/GNB/PCIe/PciePortInit.h | 62 +
.../amd/agesa/f14/Proc/GNB/PCIe/PciePortLateInit.c | 229 +
.../amd/agesa/f14/Proc/GNB/PCIe/PciePortLateInit.h | 55 +
.../agesa/f14/Proc/HT/Fam10/htNbCoherentFam10.c | 163 +
.../agesa/f14/Proc/HT/Fam10/htNbCoherentFam10.h | 67 +
.../amd/agesa/f14/Proc/HT/Fam10/htNbFam10.c | 362 +
.../agesa/f14/Proc/HT/Fam10/htNbNonCoherentFam10.c | 121 +
.../agesa/f14/Proc/HT/Fam10/htNbNonCoherentFam10.h | 58 +
.../f14/Proc/HT/Fam10/htNbOptimizationFam10.c | 222 +
.../f14/Proc/HT/Fam10/htNbOptimizationFam10.h | 74 +
.../amd/agesa/f14/Proc/HT/Fam10/htNbSystemFam10.c | 402 +
.../amd/agesa/f14/Proc/HT/Fam10/htNbSystemFam10.h | 91 +
.../agesa/f14/Proc/HT/Fam10/htNbUtilitiesFam10.c | 445 +
.../agesa/f14/Proc/HT/Fam10/htNbUtilitiesFam10.h | 129 +
.../amd/agesa/f14/Proc/HT/Fam14/htNbFam14.c | 147 +
.../agesa/f14/Proc/HT/Fam14/htNbUtilitiesFam14.c | 139 +
.../agesa/f14/Proc/HT/Fam14/htNbUtilitiesFam14.h | 68 +
.../f14/Proc/HT/Features/htFeatDynamicDiscovery.c | 783 ++
.../f14/Proc/HT/Features/htFeatDynamicDiscovery.h | 80 +
.../amd/agesa/f14/Proc/HT/Features/htFeatGanging.c | 218 +
.../amd/agesa/f14/Proc/HT/Features/htFeatGanging.h | 80 +
.../agesa/f14/Proc/HT/Features/htFeatNoncoherent.c | 375 +
.../agesa/f14/Proc/HT/Features/htFeatNoncoherent.h | 81 +
.../f14/Proc/HT/Features/htFeatOptimization.c | 886 ++
.../f14/Proc/HT/Features/htFeatOptimization.h | 140 +
.../amd/agesa/f14/Proc/HT/Features/htFeatRouting.c | 493 +
.../amd/agesa/f14/Proc/HT/Features/htFeatRouting.h | 90 +
.../amd/agesa/f14/Proc/HT/Features/htFeatSets.c | 114 +
.../agesa/f14/Proc/HT/Features/htFeatSublinks.c | 232 +
.../agesa/f14/Proc/HT/Features/htFeatSublinks.h | 80 +
.../Proc/HT/Features/htFeatTrafficDistribution.c | 278 +
.../Proc/HT/Features/htFeatTrafficDistribution.h | 79 +
.../amd/agesa/f14/Proc/HT/Features/htIds.c | 153 +
.../amd/agesa/f14/Proc/HT/NbCommon/htNbCoherent.c | 492 +
.../amd/agesa/f14/Proc/HT/NbCommon/htNbCoherent.h | 178 +
.../agesa/f14/Proc/HT/NbCommon/htNbNonCoherent.c | 142 +
.../agesa/f14/Proc/HT/NbCommon/htNbNonCoherent.h | 62 +
.../agesa/f14/Proc/HT/NbCommon/htNbOptimization.c | 258 +
.../agesa/f14/Proc/HT/NbCommon/htNbOptimization.h | 91 +
.../amd/agesa/f14/Proc/HT/NbCommon/htNbUtilities.c | 335 +
.../amd/agesa/f14/Proc/HT/NbCommon/htNbUtilities.h | 108 +
src/vendorcode/amd/agesa/f14/Proc/HT/htFeat.c | 112 +
src/vendorcode/amd/agesa/f14/Proc/HT/htFeat.h | 562 +
src/vendorcode/amd/agesa/f14/Proc/HT/htGraph.h | 144 +
.../amd/agesa/f14/Proc/HT/htGraph/htGraph.c | 199 +
.../amd/agesa/f14/Proc/HT/htGraph/htGraph1.c | 70 +
.../amd/agesa/f14/Proc/HT/htGraph/htGraph2.c | 71 +
.../amd/agesa/f14/Proc/HT/htGraph/htGraph3Line.c | 76 +
.../agesa/f14/Proc/HT/htGraph/htGraph3Triangle.c | 77 +
.../agesa/f14/Proc/HT/htGraph/htGraph4Degenerate.c | 80 +
.../f14/Proc/HT/htGraph/htGraph4FullyConnected.c | 83 +
.../amd/agesa/f14/Proc/HT/htGraph/htGraph4Kite.c | 81 +
.../amd/agesa/f14/Proc/HT/htGraph/htGraph4Line.c | 80 +
.../amd/agesa/f14/Proc/HT/htGraph/htGraph4Square.c | 80 +
.../amd/agesa/f14/Proc/HT/htGraph/htGraph4Star.c | 80 +
.../f14/Proc/HT/htGraph/htGraph5FullyConnected.c | 80 +
.../f14/Proc/HT/htGraph/htGraph5TwistedLadder.c | 89 +
.../f14/Proc/HT/htGraph/htGraph6DoubloonLower.c | 75 +
.../f14/Proc/HT/htGraph/htGraph6DoubloonUpper.c | 75 +
.../f14/Proc/HT/htGraph/htGraph6FullyConnected.c | 86 +
.../f14/Proc/HT/htGraph/htGraph6TwinTriangles.c | 92 +
.../f14/Proc/HT/htGraph/htGraph6TwistedLadder.c | 92 +
.../f14/Proc/HT/htGraph/htGraph7FullyConnected.c | 78 +
.../f14/Proc/HT/htGraph/htGraph7TwistedLadder.c | 95 +
.../agesa/f14/Proc/HT/htGraph/htGraph8DoubloonM.c | 76 +
.../f14/Proc/HT/htGraph/htGraph8FullyConnected.c | 79 +
.../amd/agesa/f14/Proc/HT/htGraph/htGraph8Ladder.c | 96 +
.../Proc/HT/htGraph/htGraph8TwinFullyFourWays.c | 96 +
.../f14/Proc/HT/htGraph/htGraph8TwistedLadder.c | 95 +
src/vendorcode/amd/agesa/f14/Proc/HT/htInterface.c | 242 +
src/vendorcode/amd/agesa/f14/Proc/HT/htInterface.h | 490 +
.../amd/agesa/f14/Proc/HT/htInterfaceCoherent.c | 264 +
.../amd/agesa/f14/Proc/HT/htInterfaceCoherent.h | 115 +
.../amd/agesa/f14/Proc/HT/htInterfaceGeneral.c | 539 +
.../amd/agesa/f14/Proc/HT/htInterfaceGeneral.h | 162 +
.../amd/agesa/f14/Proc/HT/htInterfaceNonCoherent.c | 394 +
.../amd/agesa/f14/Proc/HT/htInterfaceNonCoherent.h | 138 +
src/vendorcode/amd/agesa/f14/Proc/HT/htMain.c | 579 +
src/vendorcode/amd/agesa/f14/Proc/HT/htNb.c | 247 +
src/vendorcode/amd/agesa/f14/Proc/HT/htNb.h | 1112 ++
.../amd/agesa/f14/Proc/HT/htNbHardwareFam10.h | 123 +
src/vendorcode/amd/agesa/f14/Proc/HT/htNotify.c | 670 ++
src/vendorcode/amd/agesa/f14/Proc/HT/htNotify.h | 298 +
src/vendorcode/amd/agesa/f14/Proc/HT/htPage.h | 66 +
.../amd/agesa/f14/Proc/HT/htTopologies.h | 72 +
src/vendorcode/amd/agesa/f14/Proc/IDS/IdsLib.h | 128 +
src/vendorcode/amd/agesa/f14/Proc/IDS/IdsPage.h | 59 +
src/vendorcode/amd/agesa/f14/Proc/IDS/OptionsIds.h | 69 +
.../amd/agesa/f14/Proc/Mem/Ardk/C32/marc32_3.c | 594 +
.../amd/agesa/f14/Proc/Mem/Ardk/C32/mauc32_3.c | 357 +
.../amd/agesa/f14/Proc/Mem/Ardk/DA/masda2.c | 207 +
.../amd/agesa/f14/Proc/Mem/Ardk/DA/masda3.c | 261 +
.../amd/agesa/f14/Proc/Mem/Ardk/DA/mauda3.c | 260 +
.../amd/agesa/f14/Proc/Mem/Ardk/DR/mardr2.c | 274 +
.../amd/agesa/f14/Proc/Mem/Ardk/DR/mardr3.c | 429 +
.../amd/agesa/f14/Proc/Mem/Ardk/DR/maudr3.c | 260 +
.../amd/agesa/f14/Proc/Mem/Ardk/HY/marhy3.c | 578 +
.../amd/agesa/f14/Proc/Mem/Ardk/HY/mauhy3.c | 357 +
.../amd/agesa/f14/Proc/Mem/Ardk/NI/masNi3.c | 261 +
.../amd/agesa/f14/Proc/Mem/Ardk/NI/mauNi3.c | 260 +
.../amd/agesa/f14/Proc/Mem/Ardk/ON/mason3.c | 274 +
.../amd/agesa/f14/Proc/Mem/Ardk/ON/mauon3.c | 259 +
.../amd/agesa/f14/Proc/Mem/Ardk/PH/masph3.c | 261 +
.../amd/agesa/f14/Proc/Mem/Ardk/PH/mauPh3.c | 260 +
.../amd/agesa/f14/Proc/Mem/Ardk/RB/masRb3.c | 260 +
.../amd/agesa/f14/Proc/Mem/Ardk/RB/mauRb3.c | 259 +
src/vendorcode/amd/agesa/f14/Proc/Mem/Ardk/ma.c | 141 +
.../amd/agesa/f14/Proc/Mem/Feat/CHINTLV/mfchi.c | 213 +
.../amd/agesa/f14/Proc/Mem/Feat/CHINTLV/mfchi.h | 82 +
.../amd/agesa/f14/Proc/Mem/Feat/CSINTLV/mfcsi.c | 341 +
.../amd/agesa/f14/Proc/Mem/Feat/CSINTLV/mfcsi.h | 82 +
.../amd/agesa/f14/Proc/Mem/Feat/DMI/mfDMI.c | 573 +
.../amd/agesa/f14/Proc/Mem/Feat/ECC/mfecc.c | 321 +
.../amd/agesa/f14/Proc/Mem/Feat/ECC/mfecc.h | 82 +
.../amd/agesa/f14/Proc/Mem/Feat/ECC/mfemp.c | 174 +
.../f14/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c | 195 +
.../agesa/f14/Proc/Mem/Feat/IDENDIMM/mfidendimm.c | 528 +
.../agesa/f14/Proc/Mem/Feat/IDENDIMM/mfidendimm.h | 110 +
.../agesa/f14/Proc/Mem/Feat/INTLVRN/mfintlvrn.c | 152 +
.../agesa/f14/Proc/Mem/Feat/INTLVRN/mfintlvrn.h | 82 +
.../amd/agesa/f14/Proc/Mem/Feat/LVDDR3/mflvddr3.c | 172 +
.../amd/agesa/f14/Proc/Mem/Feat/LVDDR3/mflvddr3.h | 80 +
.../amd/agesa/f14/Proc/Mem/Feat/MEMCLR/mfmemclr.c | 144 +
.../amd/agesa/f14/Proc/Mem/Feat/NDINTLV/mfndi.c | 218 +
.../amd/agesa/f14/Proc/Mem/Feat/NDINTLV/mfndi.h | 80 +
.../f14/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c | 176 +
.../f14/Proc/Mem/Feat/ODTHERMAL/mfodthermal.h | 79 +
.../amd/agesa/f14/Proc/Mem/Feat/OLSPARE/mfspr.c | 171 +
.../amd/agesa/f14/Proc/Mem/Feat/OLSPARE/mfspr.h | 81 +
.../f14/Proc/Mem/Feat/PARTRN/mfParallelTraining.c | 286 +
.../f14/Proc/Mem/Feat/PARTRN/mfStandardTraining.c | 88 +
.../amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c | 714 ++
.../amd/agesa/f14/Proc/Mem/Feat/TABLE/mftds.c | 324 +
.../amd/agesa/f14/Proc/Mem/Main/C32/mmflowC32.c | 372 +
.../amd/agesa/f14/Proc/Mem/Main/DA/mmflowda.c | 379 +
.../amd/agesa/f14/Proc/Mem/Main/DR/mmflowdr.c | 373 +
.../amd/agesa/f14/Proc/Mem/Main/HY/mmflowhy.c | 372 +
.../amd/agesa/f14/Proc/Mem/Main/ON/mmflowon.c | 292 +
.../amd/agesa/f14/Proc/Mem/Main/PH/mmflowPh.c | 380 +
.../amd/agesa/f14/Proc/Mem/Main/RB/mmflowRb.c | 380 +
src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mdef.c | 143 +
.../amd/agesa/f14/Proc/Mem/Main/merrhdl.c | 189 +
src/vendorcode/amd/agesa/f14/Proc/Mem/Main/minit.c | 138 +
src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mm.c | 240 +
.../amd/agesa/f14/Proc/Mem/Main/mmConditionalPso.c | 697 ++
src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmEcc.c | 128 +
.../amd/agesa/f14/Proc/Mem/Main/mmExcludeDimm.c | 218 +
.../amd/agesa/f14/Proc/Mem/Main/mmLvDdr3.c | 265 +
.../amd/agesa/f14/Proc/Mem/Main/mmMemClr.c | 110 +
.../amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c | 597 +
.../amd/agesa/f14/Proc/Mem/Main/mmNodeInterleave.c | 138 +
.../amd/agesa/f14/Proc/Mem/Main/mmOnlineSpare.c | 158 +
.../agesa/f14/Proc/Mem/Main/mmParallelTraining.c | 273 +
.../agesa/f14/Proc/Mem/Main/mmStandardTraining.c | 111 +
.../amd/agesa/f14/Proc/Mem/Main/mmUmaAlloc.c | 242 +
.../amd/agesa/f14/Proc/Mem/Main/mmflow.c | 384 +
.../amd/agesa/f14/Proc/Mem/Main/mmlvddr3.h | 82 +
src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mu.asm | 497 +
src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mu.c | 253 +
src/vendorcode/amd/agesa/f14/Proc/Mem/Main/muc.c | 652 +
.../amd/agesa/f14/Proc/Mem/NB/C32/mnParTrainc32.c | 224 +
.../amd/agesa/f14/Proc/Mem/NB/C32/mnS3c32.c | 731 ++
.../amd/agesa/f14/Proc/Mem/NB/C32/mnS3c32.h | 85 +
.../amd/agesa/f14/Proc/Mem/NB/C32/mnc32.c | 485 +
.../amd/agesa/f14/Proc/Mem/NB/C32/mnc32.h | 196 +
.../amd/agesa/f14/Proc/Mem/NB/C32/mndctc32.c | 365 +
.../amd/agesa/f14/Proc/Mem/NB/C32/mnflowc32.c | 136 +
.../amd/agesa/f14/Proc/Mem/NB/C32/mnidendimmc32.c | 139 +
.../amd/agesa/f14/Proc/Mem/NB/C32/mnmctc32.c | 195 +
.../amd/agesa/f14/Proc/Mem/NB/C32/mnotc32.c | 241 +
.../amd/agesa/f14/Proc/Mem/NB/C32/mnphyc32.c | 167 +
.../amd/agesa/f14/Proc/Mem/NB/C32/mnprotoc32.c | 67 +
.../amd/agesa/f14/Proc/Mem/NB/C32/mnregc32.c | 627 +
.../amd/agesa/f14/Proc/Mem/NB/DA/mnParTrainDa.c | 226 +
.../amd/agesa/f14/Proc/Mem/NB/DA/mnS3da.c | 748 ++
.../amd/agesa/f14/Proc/Mem/NB/DA/mnS3da.h | 85 +
src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnda.c | 490 +
src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnda.h | 210 +
.../amd/agesa/f14/Proc/Mem/NB/DA/mndctda.c | 469 +
.../amd/agesa/f14/Proc/Mem/NB/DA/mnflowda.c | 140 +
.../amd/agesa/f14/Proc/Mem/NB/DA/mnidendimmda.c | 140 +
.../amd/agesa/f14/Proc/Mem/NB/DA/mnmctda.c | 199 +
.../amd/agesa/f14/Proc/Mem/NB/DA/mnotda.c | 201 +
.../amd/agesa/f14/Proc/Mem/NB/DA/mnprotoda.c | 87 +
.../amd/agesa/f14/Proc/Mem/NB/DA/mnregda.c | 574 +
.../amd/agesa/f14/Proc/Mem/NB/DR/mnParTrainDr.c | 226 +
.../amd/agesa/f14/Proc/Mem/NB/DR/mnS3dr.c | 716 ++
.../amd/agesa/f14/Proc/Mem/NB/DR/mnS3dr.h | 85 +
.../amd/agesa/f14/Proc/Mem/NB/DR/mndctdr.c | 515 +
src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mndr.c | 482 +
src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mndr.h | 199 +
.../amd/agesa/f14/Proc/Mem/NB/DR/mnflowdr.c | 142 +
.../amd/agesa/f14/Proc/Mem/NB/DR/mnidendimmdr.c | 140 +
.../amd/agesa/f14/Proc/Mem/NB/DR/mnmctdr.c | 186 +
.../amd/agesa/f14/Proc/Mem/NB/DR/mnotdr.c | 200 +
.../amd/agesa/f14/Proc/Mem/NB/DR/mnprotodr.c | 170 +
.../amd/agesa/f14/Proc/Mem/NB/DR/mnregdr.c | 548 +
.../amd/agesa/f14/Proc/Mem/NB/HY/mnParTrainHy.c | 224 +
.../amd/agesa/f14/Proc/Mem/NB/HY/mnS3hy.c | 740 ++
.../amd/agesa/f14/Proc/Mem/NB/HY/mnS3hy.h | 85 +
.../amd/agesa/f14/Proc/Mem/NB/HY/mndcthy.c | 409 +
.../amd/agesa/f14/Proc/Mem/NB/HY/mnflowhy.c | 135 +
src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnhy.c | 487 +
src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnhy.h | 202 +
.../amd/agesa/f14/Proc/Mem/NB/HY/mnidendimmhy.c | 139 +
.../amd/agesa/f14/Proc/Mem/NB/HY/mnmcthy.c | 195 +
.../amd/agesa/f14/Proc/Mem/NB/HY/mnothy.c | 241 +
.../amd/agesa/f14/Proc/Mem/NB/HY/mnphyhy.c | 183 +
.../amd/agesa/f14/Proc/Mem/NB/HY/mnprotohy.c | 67 +
.../amd/agesa/f14/Proc/Mem/NB/HY/mnreghy.c | 630 +
src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnNi.c | 495 +
src/vendorcode/amd/agesa/f14/Proc/Mem/NB/NI/mnNi.h | 114 +
.../amd/agesa/f14/Proc/Mem/NB/NI/mnS3Ni.c | 747 ++
.../amd/agesa/f14/Proc/Mem/NB/NI/mnS3Ni.h | 85 +
.../amd/agesa/f14/Proc/Mem/NB/NI/mnflowNi.c | 141 +
.../amd/agesa/f14/Proc/Mem/NB/ON/mnS3on.c | 576 +
.../amd/agesa/f14/Proc/Mem/NB/ON/mnS3on.h | 85 +
.../amd/agesa/f14/Proc/Mem/NB/ON/mndcton.c | 490 +
.../amd/agesa/f14/Proc/Mem/NB/ON/mnflowon.c | 168 +
.../amd/agesa/f14/Proc/Mem/NB/ON/mnidendimmon.c | 136 +
.../amd/agesa/f14/Proc/Mem/NB/ON/mnmcton.c | 252 +
src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.c | 456 +
src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnon.h | 250 +
.../amd/agesa/f14/Proc/Mem/NB/ON/mnoton.c | 230 +
.../amd/agesa/f14/Proc/Mem/NB/ON/mnphyon.c | 244 +
.../amd/agesa/f14/Proc/Mem/NB/ON/mnprotoon.c | 165 +
.../amd/agesa/f14/Proc/Mem/NB/ON/mnregon.c | 600 +
src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnPh.c | 494 +
src/vendorcode/amd/agesa/f14/Proc/Mem/NB/PH/mnPh.h | 125 +
.../amd/agesa/f14/Proc/Mem/NB/PH/mnS3Ph.c | 776 ++
.../amd/agesa/f14/Proc/Mem/NB/PH/mnS3Ph.h | 85 +
.../amd/agesa/f14/Proc/Mem/NB/PH/mnflowPh.c | 142 +
.../amd/agesa/f14/Proc/Mem/NB/PH/mnidendimmPh.c | 141 +
src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnRb.c | 494 +
src/vendorcode/amd/agesa/f14/Proc/Mem/NB/RB/mnRb.h | 125 +
.../amd/agesa/f14/Proc/Mem/NB/RB/mnS3Rb.c | 776 ++
.../amd/agesa/f14/Proc/Mem/NB/RB/mnS3Rb.h | 85 +
.../amd/agesa/f14/Proc/Mem/NB/RB/mnflowRb.c | 142 +
.../amd/agesa/f14/Proc/Mem/NB/RB/mnidendimmRb.c | 141 +
src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mn.c | 527 +
src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnS3.c | 929 ++
src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mndct.c | 2651 +++++
src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnfeat.c | 1268 ++
src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnflow.c | 268 +
src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c | 1184 ++
src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnphy.c | 1377 +++
src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnreg.c | 437 +
.../amd/agesa/f14/Proc/Mem/NB/mntrain2.c | 133 +
.../amd/agesa/f14/Proc/Mem/NB/mntrain3.c | 236 +
.../amd/agesa/f14/Proc/Mem/Ps/C32/mprc32_3.c | 326 +
.../amd/agesa/f14/Proc/Mem/Ps/C32/mpuc32_3.c | 205 +
.../amd/agesa/f14/Proc/Mem/Ps/DA/mpsda2.c | 161 +
.../amd/agesa/f14/Proc/Mem/Ps/DA/mpsda3.c | 257 +
.../amd/agesa/f14/Proc/Mem/Ps/DA/mpuda3.c | 210 +
.../amd/agesa/f14/Proc/Mem/Ps/DR/mprdr2.c | 166 +
.../amd/agesa/f14/Proc/Mem/Ps/DR/mprdr3.c | 205 +
.../amd/agesa/f14/Proc/Mem/Ps/DR/mpsdr3.c | 192 +
.../amd/agesa/f14/Proc/Mem/Ps/DR/mpudr2.c | 166 +
.../amd/agesa/f14/Proc/Mem/Ps/DR/mpudr3.c | 161 +
.../amd/agesa/f14/Proc/Mem/Ps/HY/mprhy3.c | 325 +
.../amd/agesa/f14/Proc/Mem/Ps/HY/mpshy3.c | 221 +
.../amd/agesa/f14/Proc/Mem/Ps/HY/mpuhy3.c | 199 +
.../amd/agesa/f14/Proc/Mem/Ps/NI/mpsNi3.c | 257 +
.../amd/agesa/f14/Proc/Mem/Ps/NI/mpuNi3.c | 235 +
.../amd/agesa/f14/Proc/Mem/Ps/ON/mpson3.c | 181 +
.../amd/agesa/f14/Proc/Mem/Ps/ON/mpuon3.c | 182 +
.../amd/agesa/f14/Proc/Mem/Ps/PH/mpsph3.c | 257 +
.../amd/agesa/f14/Proc/Mem/Ps/PH/mpuph3.c | 211 +
.../amd/agesa/f14/Proc/Mem/Ps/RB/mpsRb3.c | 257 +
.../amd/agesa/f14/Proc/Mem/Ps/RB/mpuRb3.c | 211 +
src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mp.c | 510 +
src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mplribt.c | 190 +
src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mplrnlr.c | 111 +
src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mplrnpr.c | 111 +
.../amd/agesa/f14/Proc/Mem/Ps/mpmaxfreq.c | 250 +
src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mpmr0.c | 179 +
.../amd/agesa/f14/Proc/Mem/Ps/mpodtpat.c | 189 +
.../amd/agesa/f14/Proc/Mem/Ps/mprc10opspd.c | 163 +
.../amd/agesa/f14/Proc/Mem/Ps/mprc2ibt.c | 210 +
src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mprtt.c | 229 +
src/vendorcode/amd/agesa/f14/Proc/Mem/Ps/mpsao.c | 200 +
.../amd/agesa/f14/Proc/Mem/Tech/DDR2/mt2.c | 234 +
.../amd/agesa/f14/Proc/Mem/Tech/DDR2/mt2.h | 126 +
.../amd/agesa/f14/Proc/Mem/Tech/DDR2/mtot2.c | 164 +
.../amd/agesa/f14/Proc/Mem/Tech/DDR2/mtot2.h | 90 +
.../amd/agesa/f14/Proc/Mem/Tech/DDR2/mtspd2.c | 1117 ++
.../amd/agesa/f14/Proc/Mem/Tech/DDR2/mtspd2.h | 184 +
.../amd/agesa/f14/Proc/Mem/Tech/DDR3/mt3.c | 237 +
.../amd/agesa/f14/Proc/Mem/Tech/DDR3/mt3.h | 136 +
.../amd/agesa/f14/Proc/Mem/Tech/DDR3/mtlrdimm3.c | 1102 ++
.../amd/agesa/f14/Proc/Mem/Tech/DDR3/mtlrdimm3.h | 127 +
.../amd/agesa/f14/Proc/Mem/Tech/DDR3/mtot3.c | 170 +
.../amd/agesa/f14/Proc/Mem/Tech/DDR3/mtot3.h | 92 +
.../amd/agesa/f14/Proc/Mem/Tech/DDR3/mtrci3.c | 297 +
.../amd/agesa/f14/Proc/Mem/Tech/DDR3/mtrci3.h | 89 +
.../amd/agesa/f14/Proc/Mem/Tech/DDR3/mtsdi3.c | 493 +
.../amd/agesa/f14/Proc/Mem/Tech/DDR3/mtsdi3.h | 98 +
.../amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.c | 1153 ++
.../amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h | 177 +
.../amd/agesa/f14/Proc/Mem/Tech/DDR3/mttecc3.c | 166 +
.../amd/agesa/f14/Proc/Mem/Tech/DDR3/mttwl3.c | 686 ++
src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mt.c | 264 +
src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mthdi.c | 127 +
.../amd/agesa/f14/Proc/Mem/Tech/mttEdgeDetect.c | 896 ++
.../amd/agesa/f14/Proc/Mem/Tech/mttEdgeDetect.h | 119 +
.../amd/agesa/f14/Proc/Mem/Tech/mttdimbt.c | 1279 ++
.../amd/agesa/f14/Proc/Mem/Tech/mttecc.c | 209 +
.../amd/agesa/f14/Proc/Mem/Tech/mtthrc.c | 306 +
src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/mttml.c | 255 +
.../amd/agesa/f14/Proc/Mem/Tech/mttoptsrc.c | 427 +
.../amd/agesa/f14/Proc/Mem/Tech/mttsrc.c | 346 +
src/vendorcode/amd/agesa/f14/Proc/Mem/ma.h | 318 +
src/vendorcode/amd/agesa/f14/Proc/Mem/memPage.h | 59 +
src/vendorcode/amd/agesa/f14/Proc/Mem/merrhdl.h | 105 +
.../amd/agesa/f14/Proc/Mem/mfParallelTraining.h | 115 +
.../amd/agesa/f14/Proc/Mem/mfStandardTraining.h | 83 +
src/vendorcode/amd/agesa/f14/Proc/Mem/mfmemclr.h | 85 +
src/vendorcode/amd/agesa/f14/Proc/Mem/mfs3.h | 283 +
src/vendorcode/amd/agesa/f14/Proc/Mem/mftds.h | 82 +
src/vendorcode/amd/agesa/f14/Proc/Mem/mm.h | 1003 ++
src/vendorcode/amd/agesa/f14/Proc/Mem/mn.h | 1375 +++
src/vendorcode/amd/agesa/f14/Proc/Mem/mp.h | 569 +
src/vendorcode/amd/agesa/f14/Proc/Mem/mport.h | 69 +
src/vendorcode/amd/agesa/f14/Proc/Mem/mt.h | 435 +
src/vendorcode/amd/agesa/f14/Proc/Mem/mu.h | 238 +
.../amd/agesa/f14/Proc/Recovery/CPU/cpuRecovery.c | 104 +
.../amd/agesa/f14/Proc/Recovery/CPU/cpuRecovery.h | 77 +
.../amd/agesa/f14/Proc/Recovery/GNB/GfxRecovery.c | 112 +
.../amd/agesa/f14/Proc/Recovery/GNB/GfxRecovery.h | 77 +
.../amd/agesa/f14/Proc/Recovery/GNB/GnbRecovery.c | 103 +
.../agesa/f14/Proc/Recovery/GNB/NbInitRecovery.c | 138 +
.../agesa/f14/Proc/Recovery/GNB/NbInitRecovery.h | 57 +
.../agesa/f14/Proc/Recovery/HT/htInitRecovery.c | 163 +
.../amd/agesa/f14/Proc/Recovery/HT/htInitReset.c | 332 +
.../agesa/f14/Proc/Recovery/Mem/NB/C32/mrnc32.c | 711 ++
.../agesa/f14/Proc/Recovery/Mem/NB/C32/mrnc32.h | 110 +
.../agesa/f14/Proc/Recovery/Mem/NB/C32/mrnmctc32.c | 162 +
.../f14/Proc/Recovery/Mem/NB/C32/mrnprotoc32.c | 62 +
.../amd/agesa/f14/Proc/Recovery/Mem/NB/DA/mrnda.c | 651 +
.../amd/agesa/f14/Proc/Recovery/Mem/NB/DA/mrnda.h | 110 +
.../agesa/f14/Proc/Recovery/Mem/NB/DA/mrnmctda.c | 165 +
.../amd/agesa/f14/Proc/Recovery/Mem/NB/DR/mrndr.c | 655 ++
.../amd/agesa/f14/Proc/Recovery/Mem/NB/DR/mrndr.h | 110 +
.../agesa/f14/Proc/Recovery/Mem/NB/DR/mrnmctdr.c | 167 +
.../agesa/f14/Proc/Recovery/Mem/NB/HY/mrndcthy.c | 76 +
.../amd/agesa/f14/Proc/Recovery/Mem/NB/HY/mrnhy.c | 710 ++
.../amd/agesa/f14/Proc/Recovery/Mem/NB/HY/mrnhy.h | 110 +
.../agesa/f14/Proc/Recovery/Mem/NB/HY/mrnmcthy.c | 162 +
.../agesa/f14/Proc/Recovery/Mem/NB/HY/mrnprotohy.c | 62 +
.../amd/agesa/f14/Proc/Recovery/Mem/NB/NI/mrnNi.c | 651 +
.../amd/agesa/f14/Proc/Recovery/Mem/NB/NI/mrnNi.h | 97 +
.../agesa/f14/Proc/Recovery/Mem/NB/ON/mrndcton.c | 363 +
.../agesa/f14/Proc/Recovery/Mem/NB/ON/mrnmcton.c | 191 +
.../amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrnon.c | 653 +
.../amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrnon.h | 125 +
.../amd/agesa/f14/Proc/Recovery/Mem/NB/PH/mrnPh.c | 652 +
.../amd/agesa/f14/Proc/Recovery/Mem/NB/PH/mrnPh.h | 97 +
.../amd/agesa/f14/Proc/Recovery/Mem/NB/RB/mrnRb.c | 651 +
.../amd/agesa/f14/Proc/Recovery/Mem/NB/RB/mrnRb.h | 97 +
.../amd/agesa/f14/Proc/Recovery/Mem/NB/mrn.c | 190 +
.../amd/agesa/f14/Proc/Recovery/Mem/NB/mrndct.c | 1502 +++
.../amd/agesa/f14/Proc/Recovery/Mem/NB/mrnmct.c | 298 +
.../amd/agesa/f14/Proc/Recovery/Mem/NB/mrntrain3.c | 127 +
.../amd/agesa/f14/Proc/Recovery/Mem/Ps/mrp.c | 261 +
.../amd/agesa/f14/Proc/Recovery/Mem/Ps/mrplribt.c | 183 +
.../amd/agesa/f14/Proc/Recovery/Mem/Ps/mrplrnlr.c | 111 +
.../amd/agesa/f14/Proc/Recovery/Mem/Ps/mrplrnpr.c | 111 +
.../amd/agesa/f14/Proc/Recovery/Mem/Ps/mrpmr0.c | 178 +
.../amd/agesa/f14/Proc/Recovery/Mem/Ps/mrpodtpat.c | 183 +
.../agesa/f14/Proc/Recovery/Mem/Ps/mrprc10opspd.c | 93 +
.../amd/agesa/f14/Proc/Recovery/Mem/Ps/mrprc2ibt.c | 199 +
.../amd/agesa/f14/Proc/Recovery/Mem/Ps/mrprtt.c | 218 +
.../amd/agesa/f14/Proc/Recovery/Mem/Ps/mrpsao.c | 188 +
.../agesa/f14/Proc/Recovery/Mem/Tech/DDR3/mrt3.c | 189 +
.../f14/Proc/Recovery/Mem/Tech/DDR3/mrtrci3.c | 244 +
.../f14/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c | 360 +
.../f14/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.c | 326 +
.../f14/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.h | 132 +
.../f14/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c | 347 +
.../amd/agesa/f14/Proc/Recovery/Mem/Tech/mrtthrc.c | 287 +
.../amd/agesa/f14/Proc/Recovery/Mem/Tech/mrttpos.c | 115 +
.../amd/agesa/f14/Proc/Recovery/Mem/Tech/mrttsrc.c | 437 +
.../amd/agesa/f14/Proc/Recovery/Mem/mrdef.c | 129 +
.../amd/agesa/f14/Proc/Recovery/Mem/mrinit.c | 126 +
.../amd/agesa/f14/Proc/Recovery/Mem/mrm.c | 288 +
.../amd/agesa/f14/Proc/Recovery/Mem/mrport.h | 82 +
.../amd/agesa/f14/Proc/Recovery/Mem/mrt3.h | 121 +
.../amd/agesa/f14/Proc/Recovery/Mem/mru.asm | 187 +
.../amd/agesa/f14/Proc/Recovery/Mem/mru.h | 140 +
.../amd/agesa/f14/Proc/Recovery/Mem/mruc.c | 267 +
.../amd/agesa/f14/Proc/Recovery/recoveryPage.h | 59 +
src/vendorcode/amd/agesa/f14/cpcar.inc | 1124 ++
src/vendorcode/amd/agesa/f14/cpcarmac.inc | 447 +
src/vendorcode/amd/agesa/f14/errno.h | 38 +
src/vendorcode/amd/agesa/f14/gcccar.inc | 1606 +++
src/vendorcode/amd/agesa/gcccar.inc | 1606 ---
1775 files changed, 272635 insertions(+), 272635 deletions(-)
diff --git a/src/cpu/amd/Makefile.inc b/src/cpu/amd/Makefile.inc
index dfa6d1e..c29b730 100644
--- a/src/cpu/amd/Makefile.inc
+++ b/src/cpu/amd/Makefile.inc
@@ -15,4 +15,4 @@ subdirs-$(CONFIG_CPU_AMD_SC520) += sc520
subdirs-$(CONFIG_CPU_AMD_SOCKET_S1G1) += socket_S1G1
subdirs-$(CONFIG_AMD_AGESA) += agesa
-subdirs-$(CONFIG_AMD_AGESA) += ../../vendorcode/amd/agesa
+subdirs-$(CONFIG_AMD_AGESA) += ../../vendorcode/amd/agesa/f14
diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc
index ea6c51a..1e0f37b 100644
--- a/src/cpu/amd/agesa/family14/Makefile.inc
+++ b/src/cpu/amd/agesa/family14/Makefile.inc
@@ -20,7 +20,7 @@
ramstage-y += chip_name.c
driver-y += model_14_init.c
-AGESA_ROOT = ../../../../vendorcode/amd/agesa
+AGESA_ROOT = ../../../../vendorcode/amd/agesa/f14
agesa_lib_src = $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c
agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c
diff --git a/src/mainboard/advansus/a785e-i/Makefile.inc b/src/mainboard/advansus/a785e-i/Makefile.inc
index 94433b7..a81d135 100644
--- a/src/mainboard/advansus/a785e-i/Makefile.inc
+++ b/src/mainboard/advansus/a785e-i/Makefile.inc
@@ -6,14 +6,14 @@ ramstage-y += pmio.c
#SB800 CIMx share AGESA V5 lib code
ifneq ($(CONFIG_AMD_AGESA),y)
- romstage-y += ../../../vendorcode/amd/agesa/Lib/amdlib.c
- ramstage-y += ../../../vendorcode/amd/agesa/Lib/amdlib.c
+ romstage-y += ../../../vendorcode/amd/agesa/f14/Lib/amdlib.c
+ ramstage-y += ../../../vendorcode/amd/agesa/f14/Lib/amdlib.c
- AGESA_INC := -Isrc/vendorcode/amd/agesa/ \
- -Isrc/vendorcode/amd/agesa/Include \
- -Isrc/vendorcode/amd/agesa/Proc/IDS/ \
- -Isrc/vendorcode/amd/agesa/Proc/CPU/ \
- -Isrc/vendorcode/amd/agesa/Proc/CPU/Family
+ AGESA_INC := -Isrc/vendorcode/amd/agesa/f14/ \
+ -Isrc/vendorcode/amd/agesa/f14/Include \
+ -Isrc/vendorcode/amd/agesa/f14/Proc/IDS/ \
+ -Isrc/vendorcode/amd/agesa/f14/Proc/CPU/ \
+ -Isrc/vendorcode/amd/agesa/f14/Proc/CPU/Family
CFLAGS += $(AGESA_INC)
endif
diff --git a/src/mainboard/amd/inagua/Makefile.inc b/src/mainboard/amd/inagua/Makefile.inc
index a8b8689..0f17032 100644
--- a/src/mainboard/amd/inagua/Makefile.inc
+++ b/src/mainboard/amd/inagua/Makefile.inc
@@ -32,4 +32,4 @@ ramstage-y += PlatformGnbPcie.c
ramstage-y += reset.c
ramstage-y += pmio.c
-subdirs-$(CONFIG_AMD_AGESA) += ../../../vendorcode/amd/agesa
+subdirs-$(CONFIG_AMD_AGESA) += ../../../vendorcode/amd/agesa/f14
diff --git a/src/mainboard/amd/persimmon/Makefile.inc b/src/mainboard/amd/persimmon/Makefile.inc
index a8b8689..0f17032 100644
--- a/src/mainboard/amd/persimmon/Makefile.inc
+++ b/src/mainboard/amd/persimmon/Makefile.inc
@@ -32,4 +32,4 @@ ramstage-y += PlatformGnbPcie.c
ramstage-y += reset.c
ramstage-y += pmio.c
-subdirs-$(CONFIG_AMD_AGESA) += ../../../vendorcode/amd/agesa
+subdirs-$(CONFIG_AMD_AGESA) += ../../../vendorcode/amd/agesa/f14
diff --git a/src/mainboard/asrock/e350m1/Makefile.inc b/src/mainboard/asrock/e350m1/Makefile.inc
index a8b8689..0f17032 100644
--- a/src/mainboard/asrock/e350m1/Makefile.inc
+++ b/src/mainboard/asrock/e350m1/Makefile.inc
@@ -32,4 +32,4 @@ ramstage-y += PlatformGnbPcie.c
ramstage-y += reset.c
ramstage-y += pmio.c
-subdirs-$(CONFIG_AMD_AGESA) += ../../../vendorcode/amd/agesa
+subdirs-$(CONFIG_AMD_AGESA) += ../../../vendorcode/amd/agesa/f14
diff --git a/src/northbridge/amd/Makefile.inc b/src/northbridge/amd/Makefile.inc
index 328fd0f..aeb373e 100644
--- a/src/northbridge/amd/Makefile.inc
+++ b/src/northbridge/amd/Makefile.inc
@@ -5,4 +5,4 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_GX2) += gx2
subdirs-$(CONFIG_NORTHBRIDGE_AMD_LX) += lx
subdirs-$(CONFIG_AMD_AGESA) += agesa
-subdirs-$(CONFIG_AMD_AGESA) += ../../vendorcode/amd/agesa
+subdirs-$(CONFIG_AMD_AGESA) += ../../vendorcode/amd/agesa/f14
diff --git a/src/vendorcode/amd/agesa/AGESA.h b/src/vendorcode/amd/agesa/AGESA.h
deleted file mode 100644
index 0f348d6..0000000
--- a/src/vendorcode/amd/agesa/AGESA.h
+++ /dev/null
@@ -1,3022 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Agesa structures and definitions
- *
- * Contains AMD AGESA core interface
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Include
- * @e \$Revision: 41504 $ @e \$Date: 2010-11-05 21:59:13 +0800 (Fri, 05 Nov 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-#ifndef _AGESA_H_
-#define _AGESA_H_
-
-#include "Porting.h"
-#include "AMD.h"
-
-//
-//
-// AGESA Types and Definitions
-//
-//
-
-// AGESA BASIC CALLOUTS
-#define AGESA_MEM_RELEASE 0x00028000
-
-// AGESA ADVANCED CALLOUTS, Processor
-#define AGESA_CHECK_UMA 0x00028100
-#define AGESA_DO_RESET 0x00028101
-#define AGESA_ALLOCATE_BUFFER 0x00028102
-#define AGESA_DEALLOCATE_BUFFER 0x00028103
-#define AGESA_LOCATE_BUFFER 0x00028104
-#define AGESA_RUNFUNC_ONAP 0x00028105
-
-// AGESA ADVANCED CALLOUTS, HyperTransport
-
-// AGESA ADVANCED CALLOUTS, Memory
-#define AGESA_READ_SPD 0x00028140
-#define AGESA_HOOKBEFORE_DRAM_INIT 0x00028141
-#define AGESA_HOOKBEFORE_DQS_TRAINING 0x00028142
-#define AGESA_READ_SPD_RECOVERY 0x00028143
-#define AGESA_HOOKBEFORE_EXIT_SELF_REF 0x00028144
-#define AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY 0x00028145
-
-// AGESA IDS CALLOUTS
-#define AGESA_GET_IDS_INIT_DATA 0x00028200
-
-// AGESA GNB CALLOUTS
-#define AGESA_GNB_PCIE_SLOT_RESET 0x00028301
-
-//------------------------------------------------------------------------
-//
-// HyperTransport Interface
-
-
-
-//-----------------------------------------------------------------------------
-// HT DEFINITIONS AND MACROS
-//
-//-----------------------------------------------------------------------------
-
-
-// Width equates for call backs
-#define HT_WIDTH_8_BITS 8 ///< Specifies 8 bit, or up to 8 bit widths.
-#define HT_WIDTH_16_BITS 16 ///< Specifies 16 bit, or up to 16 bit widths.
-#define HT_WIDTH_4_BITS 4
-#define HT_WIDTH_2_BITS 2
-#define HT_WIDTH_NO_LIMIT HT_WIDTH_16_BITS
-
-// Frequency Limit equates for call backs which take a frequency supported mask.
-#define HT_FREQUENCY_LIMIT_200M 1 ///< Specifies a limit of no more than 200 MHz HT frequency.
-#define HT_FREQUENCY_LIMIT_400M 7 ///< Specifies a limit of no more than 400 MHz HT frequency.
-#define HT_FREQUENCY_LIMIT_600M 0x1F ///< Specifies a limit of no more than 600 MHz HT frequency.
-#define HT_FREQUENCY_LIMIT_800M 0x3F ///< Specifies a limit of no more than 800 MHz HT frequency.
-#define HT_FREQUENCY_LIMIT_1000M 0x7F ///< Specifies a limit of no more than 1000 MHz HT frequency.
-#define HT_FREQUENCY_LIMIT_HT1_ONLY 0x7F ///< Specifies a limit of no more than 1000 MHz HT frequency.
-#define HT_FREQUENCY_LIMIT_1200M 0xFF ///< Specifies a limit of no more than 1200 MHz HT frequency.
-#define HT_FREQUENCY_LIMIT_1400M 0x1FF ///< Specifies a limit of no more than 1400 MHz HT frequency.
-#define HT_FREQUENCY_LIMIT_1600M 0x3FF ///< Specifies a limit of no more than 1600 MHz HT frequency.
-#define HT_FREQUENCY_LIMIT_1800M 0x7FF ///< Specifies a limit of no more than 1800 MHz HT frequency.
-#define HT_FREQUENCY_LIMIT_2000M 0xFFF ///< Specifies a limit of no more than 2000 MHz HT frequency.
-#define HT_FREQUENCY_LIMIT_2200M 0x1FFF ///< Specifies a limit of no more than 2200 MHz HT frequency.
-#define HT_FREQUENCY_LIMIT_2400M 0x3FFF ///< Specifies a limit of no more than 2400 MHz HT frequency.
-#define HT_FREQUENCY_LIMIT_2600M 0x7FFF ///< Specifies a limit of no more than 2600 MHz HT frequency.
-#define HT_FREQUENCY_LIMIT_2800M 0x27FFF ///< Specifies a limit of no more than 2800 MHz HT frequency.
-#define HT_FREQUENCY_LIMIT_3000M 0x67FFF ///< Specifies a limit of no more than 3000 MHz HT frequency.
-#define HT_FREQUENCY_LIMIT_3200M 0xE7FFF ///< Specifies a limit of no more than 3200 MHz HT frequency.
-#define HT_FREQUENCY_LIMIT_3600M 0x1E7FFF
-#define HT_FREQUENCY_LIMIT_MAX HT_FREQUENCY_LIMIT_3600M
-#define HT_FREQUENCY_NO_LIMIT 0xFFFFFFFF ///< Specifies a no limit of HT frequency.
-
-// Unit ID Clumping special values
-#define HT_CLUMPING_DISABLE 0x00000000
-#define HT_CLUMPING_NO_LIMIT 0xFFFFFFFF
-
-#define HT_LIST_TERMINAL 0xFF ///< End of list.
-#define HT_LIST_MATCH_ANY 0xFE ///< Match Any value, used for Sockets, Links, IO Chain Depth.
-#define HT_LIST_MATCH_INTERNAL_LINK 0xFD ///< Match all of the internal links.
-
-// Event Notify definitions
-
-// Event definitions.
-
-// Coherent subfunction events
-#define HT_EVENT_COH_EVENTS 0x10001000
-#define HT_EVENT_COH_NO_TOPOLOGY 0x10011000 ///< See ::HT_EVENT_DATA_COH_NO_TOPOLOGY.
-#define HT_EVENT_COH_OBSOLETE000 0x10021000 // No longer used.
-#define HT_EVENT_COH_PROCESSOR_TYPE_MIX 0x10031000 ///< See ::HT_EVENT_DATA_COH_PROCESSOR_TYPE_MIX.
-#define HT_EVENT_COH_NODE_DISCOVERED 0x10041000 ///< See ::HT_EVENT_COH_NODE_DISCOVERED.
-#define HT_EVENT_COH_MPCAP_MISMATCH 0x10051000 ///< See ::HT_EVENT_COH_MPCAP_MISMATCH.
-
-// Non-coherent subfunction events
-#define HT_EVENT_NCOH_EVENTS 0x10002000
-#define HT_EVENT_NCOH_BUID_EXCEED 0x10012000 ///< See ::HT_EVENT_DATA_NCOH_BUID_EXCEED
-#define HT_EVENT_NCOH_OBSOLETE000 0x10022000 // No longer used.
-#define HT_EVENT_NCOH_BUS_MAX_EXCEED 0x10032000 ///< See ::HT_EVENT_DATA_NCOH_BUS_MAX_EXCEED.
-#define HT_EVENT_NCOH_CFG_MAP_EXCEED 0x10042000 ///< See ::HT_EVENT_DATA_NCOH_CFG_MAP_EXCEED.
-#define HT_EVENT_NCOH_DEVICE_FAILED 0x10052000 ///< See ::HT_EVENT_DATA_NCOH_DEVICE_FAILED
-#define HT_EVENT_NCOH_AUTO_DEPTH 0x10062000 ///< See ::HT_EVENT_NCOH_AUTO_DEPTH
-
-// Optimization subfunction events
-#define HT_EVENT_OPT_EVENTS 0x10003000
-#define HT_EVENT_OPT_REQUIRED_CAP_RETRY 0x10013000 ///< See ::HT_EVENT_DATA_OPT_REQUIRED_CAP.
-#define HT_EVENT_OPT_REQUIRED_CAP_GEN3 0x10023000 ///< See ::HT_EVENT_DATA_OPT_REQUIRED_CAP.
-#define HT_EVENT_OPT_UNUSED_LINKS 0x10033000 ///< See ::HT_EVENT_DATA_OPT_UNUSED_LINKS.
-#define HT_EVENT_OPT_LINK_PAIR_EXCEED 0x10043000 ///< See ::HT_EVENT_DATA_OPT_LINK_PAIR_EXCEED.
-
-// HW Fault events
-#define HT_EVENT_HW_EVENTS 0x10004000
-#define HT_EVENT_HW_SYNCFLOOD 0x10014000 ///< See ::HT_EVENT_DATA_HW_SYNCFLOOD.
-#define HT_EVENT_HW_HTCRC 0x10024000 ///< See ::HT_EVENT_DATA_HW_HT_CRC.
-
-// The Recovery HT component uses 0x10005000 for events.
-// For consistency, we avoid that range here.
-
-#define HT_MAX_NC_BUIDS 32
-//----------------------------------------------------------------------------
-// HT TYPEDEFS, STRUCTURES, ENUMS
-//
-//----------------------------------------------------------------------------
-
-/// Specify the state redundant links are to be left in after match.
-///
-/// After matching a link for IGNORE_LINK or SKIP_REGANG, the link may be left alone,
-/// or powered off.
-
-typedef enum {
- MATCHED, ///< The link matches the requested customization.
- ///< When used with IGNORE_LINK,
- ///< this will generally require other software to initialize the link.
- ///< When used with SKIP_REGANG,
- ///< the two unganged links will be available for distribution.
-
- POWERED_OFF, ///< Power the link off. Support may vary based on processor model.
- ///< Power Off is only supported for coherent links.
- ///< Link power off may occur at a warm reset rather than immediately.
- ///< When used with SKIP_REGANG, the paired sublink is powered off, not the matching link.
-
- UNMATCHED, ///< The link should be processed according to normal defaults.
- ///< Effectively, the link does not match the requested customization.
- ///< This can be used to exclude links from a following match any.
-
- MaxFinalLinkState ///< Not a final link state, use for limit checking.
-} FINAL_LINK_STATE;
-
-/// Swap a device from its current id to a new one.
-
-typedef struct {
- IN UINT8 FromId; ///< The device responding to FromId,
- IN UINT8 ToId; ///< will be moved to ToId.
-} BUID_SWAP_ITEM;
-
-
-/// Each Non-coherent chain may have a list of device swaps. After performing the swaps,
-/// the final in order list of device ids is provided. (There can be more swaps than devices.)
-/// The unused entries in both are filled with 0xFF.
-
-typedef struct {
- IN BUID_SWAP_ITEM Swaps[HT_MAX_NC_BUIDS]; ///< The BUID Swaps to perform
- IN UINT8 FinalIds[HT_MAX_NC_BUIDS]; ///< The ordered final BUIDs, resulting from the swaps
-} BUID_SWAP_LIST;
-
-
-/// Control Manual Initialization of Non-Coherent Chains
-///
-/// This interface is checked every time a non-coherent chain is
-/// processed. BUID assignment may be controlled explicitly on a
-/// non-coherent chain. Provide a swap list. Swaps controls the
-/// BUID assignment and FinalIds provides the device to device
-/// Linking. Device orientation can be detected automatically, or
-/// explicitly. See interface documentation for more details.
-///
-/// If a manual swap list is not supplied,
-/// automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
-/// based on each device's unit count.
-
-typedef struct {
- // Match fields
- IN UINT8 Socket; ///< The Socket on which this chain is located
- IN UINT8 Link; ///< The Link on the host for this chain
- // Override fields
- IN BUID_SWAP_LIST SwapList; ///< The swap list
-} MANUAL_BUID_SWAP_LIST;
-
-
-/// Override options for DEVICE_CAP_OVERRIDE.
-///
-/// Specify which override actions should be performed. For Checks, 1 means to check the item
-/// and 0 means to skip the check. For the override options, 1 means to apply the override and
-/// 0 means to ignore the override.
-
-typedef struct {
- IN UINT32 IsCheckDevVenId:1; ///< Check Match on Device/Vendor id
- IN UINT32 IsCheckRevision:1; ///< Check Match on device Revision
- IN UINT32 IsOverrideWidthIn:1; ///< Override Width In
- IN UINT32 IsOverrideWidthOut:1; ///< Override Width Out
- IN UINT32 IsOverrideFreq:1; ///< Override Frequency
- IN UINT32 IsOverrideClumping:1; ///< Override Clumping
- IN UINT32 IsDoCallout:1; ///< Make the optional callout
-} DEVICE_CAP_OVERRIDE_OPTIONS;
-
-/// Override capabilities of a device.
-///
-/// This interface is checked once for every Link on every IO device.
-/// Provide the width and frequency capability if needed for this device.
-/// This is used along with device capabilities, the limit interfaces, and northbridge
-/// limits to compute the default settings. The components of the device's PCI config
-/// address are provided, so its settings can be consulted if need be.
-/// The optional callout is a catch all.
-
-typedef struct {
- // Match fields
- IN UINT8 HostSocket; ///< The Socket on which this chain is located.
- IN UINT8 HostLink; ///< The Link on the host for this chain.
- IN UINT8 Depth; ///< The Depth in the I/O chain from the Host.
- IN UINT32 DevVenId; ///< The Device's PCI Vendor + Device ID (offset 0x00).
- IN UINT8 Revision; ///< The Device's PCI Revision field (offset 0x08).
- IN UINT8 Link; ///< The Device's Link number (0 or 1).
- IN DEVICE_CAP_OVERRIDE_OPTIONS Options; ///< The options for this device override.
- // Override fields
- IN UINT8 LinkWidthIn; ///< modify to change the Link Width In.
- IN UINT8 LinkWidthOut; ///< modify to change the Link Width Out.
- IN UINT32 FreqCap; ///< modify to change the Link's frequency capability.
- IN UINT32 Clumping; ///< modify to change Unit ID clumping support.
- IN CALLOUT_ENTRY Callout; ///< optional call for really complex cases, or NULL.
-} DEVICE_CAP_OVERRIDE;
-
-/// Callout param struct for override capabilities of a device.
-///
-/// If the optional callout is implemented this param struct is passed to it.
-
-typedef struct {
- IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
- // Match fields
- IN UINT8 HostSocket; ///< The Socket on which this chain is located.
- IN UINT8 HostLink; ///< The Link on the host for this chain.
- IN UINT8 Depth; ///< The Depth in the I/O chain from the Host.
- IN UINT32 DevVenId; ///< The Device's PCI Vendor + Device ID (offset 0x00).
- IN UINT8 Revision; ///< The Device's PCI Revision field (offset 0x08).
- IN UINT8 Link; ///< The Device's Link number (0 or 1).
- IN PCI_ADDR PciAddress; ///< The Device's PCI Address.
- // Override fields
- OUT UINT8 *LinkWidthIn; ///< modify to change the Link Width In.
- OUT UINT8 *LinkWidthOut; ///< modify to change the Link Width Out.
- OUT UINT32 *FreqCap; ///< modify to change the Link's frequency capability.
- OUT UINT32 *Clumping; ///< modify to change Unit ID clumping support.
-} DEVICE_CAP_CALLOUT_PARAMS;
-
-/// Limits for CPU to CPU Links.
-///
-/// For each coherent connection this interface is checked once.
-/// Provide the frequency and width if needed for this Link (usually based on board
-/// restriction). This is used with CPU device capabilities and northbridge limits
-/// to compute the default settings.
-
-typedef struct {
- // Match fields
- IN UINT8 SocketA; ///< One Socket on which this Link is located
- IN UINT8 LinkA; ///< The Link on this Node
- IN UINT8 SocketB; ///< The other Socket on which this Link is located
- IN UINT8 LinkB; ///< The Link on that Node
- // Limit fields
- IN UINT8 ABLinkWidthLimit; ///< modify to change the Link Width A->B
- IN UINT8 BALinkWidthLimit; ///< modify to change the Link Width B-<A
- IN UINT32 PcbFreqCap; ///< modify to change the Link's frequency capability
-} CPU_TO_CPU_PCB_LIMITS;
-
-/// Get limits for non-coherent Links.
-///
-/// For each non-coherent connection this interface is checked once.
-/// Provide the frequency and width if needed for this Link (usually based on board
-/// restriction). This is used with device capabilities, device overrides, and northbridge limits
-/// to compute the default settings.
-///
-typedef struct {
- // Match fields
- IN UINT8 HostSocket; ///< The Socket on which this Link is located
- IN UINT8 HostLink; ///< The Link about to be initialized
- IN UINT8 Depth; ///< The Depth in the I/O chain from the Host
- // Limit fields
- IN UINT8 DownstreamLinkWidthLimit; ///< modify to change the Link Width going away from processor
- IN UINT8 UpstreamLinkWidthLimit; ///< modify to change the Link Width moving toward processor
- IN UINT32 PcbFreqCap; ///< modify to change the Link's frequency capability
-} IO_PCB_LIMITS;
-
-/// Manually control bus number assignment.
-///
-/// This interface is checked every time a non-coherent chain is processed.
-/// If a system can not use the auto Bus numbering feature for non-coherent chain bus
-/// assignments, this interface can provide explicit control. For each chain, provide
-/// the bus number range to use.
-
-typedef struct {
- // Match fields
- IN UINT8 Socket; ///< The Socket on which this chain is located
- IN UINT8 Link; ///< The Link on the host for this chain
- // Override fields
- IN UINT8 SecBus; ///< Secondary Bus number for this non-coherent chain
- IN UINT8 SubBus; ///< Subordinate Bus number
-} OVERRIDE_BUS_NUMBERS;
-
-
-/// Ignore a Link.
-///
-/// This interface is checked every time a coherent Link is found and then every
-/// time a non-coherent Link from a CPU is found.
-/// Any coherent or non-coherent Link from a CPU can be ignored and not used
-/// for discovery or initialization. Useful for connection based systems.
-/// (Note: not checked for IO device to IO Device Links.)
-/// (Note: not usable for internal links (MCM processors).)
-
-typedef struct {
- // Match fields
- IN UINT8 Socket; ///< The Socket on which this Link is located
- IN UINT8 Link; ///< The Link about to be initialized
- // Customization fields
- IN FINAL_LINK_STATE LinkState; ///< The link may be left unitialized, or powered off.
-} IGNORE_LINK;
-
-
-/// Skip reganging of subLinks.
-///
-/// This interface is checked whenever two subLinks are both connected to the same CPUs.
-/// Normally, unganged sublinks between the same two CPUs are reganged.
-/// Provide a matching structure to leave the Links unganged.
-
-typedef struct {
- // Match fields
- IN UINT8 SocketA; ///< One Socket on which this Link is located
- IN UINT8 LinkA; ///< The Link on this Node
- IN UINT8 SocketB; ///< The other Socket on which this Link is located
- IN UINT8 LinkB; ///< The Link on that Node
- // Customization fields
- IN FINAL_LINK_STATE LinkState; ///< The paired sublink may be active, or powered off.
-} SKIP_REGANG;
-
-/// The System Socket layout, which sockets are physically connected.
-///
-/// The hardware method for Socket naming is preferred. Use this software method only
-/// if required.
-
-typedef struct {
- IN UINT8 CurrentSocket; ///< The socket from which this connection originates.
- IN UINT8 CurrentLink; ///< The Link from the source socket connects to another socket.
- IN UINT8 TargetSocket; ///< The target socket which is connected on that link.
-} SYSTEM_PHYSICAL_SOCKET_MAP;
-
-//----------------------------------------------------------------------------
-///
-/// This is the input structure for AmdHtInitialize.
-///
-typedef struct {
- // Basic level customization
- IN UINT8 AutoBusStart; ///< For automatic bus number assignment, starting bus number - usually zero.
- ///< @BldCfgItem{BLDCFG_STARTING_BUSNUM}
- IN UINT8 AutoBusMax; ///< For automatic bus number assignment, do not assign above max.
- ///< @BldCfgItem{BLDCFG_MAXIMUM_BUSNUM}
- IN UINT8 AutoBusIncrement; ///< For automatic bus number assignment, each chain gets this many busses.
- ///< @BldCfgItem{BLDCFG_ALLOCATED_BUSNUMS}
-
- // Advanced Level Customization
- IN MANUAL_BUID_SWAP_LIST *ManualBuidSwapList; ///< Provide Manual Swap List, if any.
- ///< @BldCfgItem{BLDCFG_BUID_SWAP_LIST}
- IN DEVICE_CAP_OVERRIDE *DeviceCapOverrideList; ///< Provide Device Overrides, if any.
- ///< @BldCfgItem{BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST}
- IN CPU_TO_CPU_PCB_LIMITS *CpuToCpuPcbLimitsList; ///< Provide CPU PCB Limits, if any.
- ///< @BldCfgItem{BLDCFG_HTFABRIC_LIMITS_LIST}.
- ///< @n @e Examples: See @ref FrequencyLimitExamples "Frequency Limit Examples".
- IN IO_PCB_LIMITS *IoPcbLimitsList; ///< Provide IO PCB Limits, if any.
- ///< @BldCfgItem{BLDCFG_HTCHAIN_LIMITS_LIST}.
- ///< @n @e Examples: See @ref FrequencyLimitExamples "Frequency Limit Examples".
- IN OVERRIDE_BUS_NUMBERS *OverrideBusNumbersList; ///< Provide manual Bus Number assignment, if any.
- ///< Use either auto bus numbering or override bus
- ///< numbers, not both.
- ///< @BldCfgItem{BLDCFG_BUS_NUMBERS_LIST}
-
- IN IGNORE_LINK *IgnoreLinkList; ///< Provide links to ignore, if any.
- ///< @BldCfgItem{BLDCFG_IGNORE_LINK_LIST}
- IN SKIP_REGANG *SkipRegangList; ///< Provide links to remain unganged, if any.
- ///< @BldCfgItem{BLDCFG_LINK_SKIP_REGANG_LIST}
- ///< @n @e Examples: See @ref PerfPerWattHt "Performance-per-watt Optimization".
-
- // Expert Level Customization
- IN UINT8 **Topolist; ///< Use this topology list in addition to the built in, if not NULL.
- ///< @BldCfgItem{BLDCFG_ADDITIONAL_TOPOLOGIES_LIST}
- IN SYSTEM_PHYSICAL_SOCKET_MAP *SystemPhysicalSocketMap;
- ///< The hardware socket naming method is preferred,
- ///< If it can't be used, this provides a software method.
- ///< @BldCfgItem{BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP}
-} AMD_HT_INTERFACE;
-
-//-----------------------------------------------------------------------------
-//
-// HT Recovery Interface
-//
-
-
-/*-----------------------------------------------------------------------------
- * HT Recovery DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-// BBHT subfunction events
-#define HT_EVENT_BB_EVENTS 0x10005000
-#define HT_EVENT_BB_BUID_EXCEED 0x10015000
-#define HT_EVENT_BB_DEVICE_FAILED 0x10055000
-#define HT_EVENT_BB_AUTO_DEPTH 0x10065000
-
-/*----------------------------------------------------------------------------
- * HT Recovery TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/// The Interface structure to Recovery HT.
-
-typedef struct {
- IN MANUAL_BUID_SWAP_LIST *ManualBuidSwapList; ///< Option to manually control SB link init
- ///< @BldCfgItem{BLDCFG_BUID_SWAP_LIST}
- OUT UINT32 Depth; ///< If auto init was used this is set to the depth of the chain,
- ///< else, for manual init unmodified.
-} AMD_HT_RESET_INTERFACE;
-
-/*----------------------------------------------------------------------------
- * CPU Feature related info
- *----------------------------------------------------------------------------
- */
-
-/// Build Configuration values for BLDCFG_PLATFORM_C1E_MODE
-typedef enum {
- C1eModeDisabled = 0, ///< Disabled
- C1eModeHardware = 1, ///< Hardware method
- C1eModeMsgBased = 2, ///< Message-based method
- C1eModeSoftwareDeprecated = 3, ///< Deprecated software SMI method.
- ///< Refer to "Addendum\Examples\C1eSMMHandler.asm" for
- ///< example host BIOS SMM Handler implementation
- C1eModeHardwareSoftwareDeprecated = 4, ///< Hardware or deprecated software SMI method
- MaxC1eMode = 5 ///< Not a valid value, used for verifying input
-} PLATFORM_C1E_MODES;
-
-/// Build Configuration values for BLDCFG_PLATFORM_CSTATE_MODE
-typedef enum {
- CStateModeDisabled = 0, ///< Disabled
- CStateModeC6 = 1, ///< C6 State
- MaxCStateMode = 2 ///< Not a valid value, used for verifying input
-} PLATFORM_CSTATE_MODES;
-
-/// Build Configuration values for BLDCFG_PLATFORM_CPB_MODE
-typedef enum {
- CpbModeAuto = 0, ///< Auto
- CpbModeDisabled = 1, ///< Disabled
- MaxCpbMode = 2 ///< Not a valid value, used for verifying input
-} PLATFORM_CPB_MODES;
-
-/*----------------------------------------------------------------------------
- * GNB PCIe configuration info
- *----------------------------------------------------------------------------
- */
-
-// Event definitions
-
-
-#define GNB_EVENT_INVALID_CONFIGURATION 0x20010000 // User configuration invalid
-#define GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION 0x20010001 // Requested lane allocation for PCIe port can not be supported
-#define GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION 0x20010002 // Requested incorrect PCIe port device address
-#define GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION 0x20010003 // Incorrect parameter in DDI link configuration
-#define GNB_EVENT_INVALID_LINK_WIDTH_CONFIGURATION 0x20010004 // Invalid with for PCIe port or DDI link
-#define GNB_EVENT_INVALID_LANES_CONFIGURATION 0x20010005 // Lane double subscribe lanes
-#define GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION 0x20010006 // Requested lane allocation for DDI link(s) can not be supported
-#define GNB_EVENT_LINK_TRAINING_FAIL 0x20020000 // PCIe Link training fail
-#define GNB_EVENT_BROKEN_LANE_RECOVERY 0x20030000 // Broken lane workaround applied to recover link training
-#define GNB_EVENT_GEN2_SUPPORT_RECOVERY 0x20040000 // Scale back to GEN1 to recover link training
-
-
-#define DESCRIPTOR_TERMINATE_LIST 0x80000000ull
-
-/// PCIe port misc extended controls
-typedef struct {
- IN UINT8 LinkComplianceMode :1; ///< Force port into compliance mode (device will not be trained, port output compliance pattern)
- IN UINT8 LinkSafeMode :2; /**< Safe mode PCIe capability. (Parameter may limit PCIe speed requested through PCIe_PORT_DATA::LinkSpeedCapability)
- * @li @b 0 - port can advertize muximum supported capability
- * @li @b 1 - port limit advertized capability and speed to PCIe Gen1
- */
-} PCIe_PORT_MISC_CONTROL;
-
-
-/// PCIe port configuration data
-typedef struct {
- IN UINT8 PortPresent; ///< Enable PCIe port for initialization.
- IN UINT8 ChannelType; /**< Channel type.
- * @li @b 0 - "lowLoss",
- * @li @b 1 - "highLoss",
- * @li @b 2 - "mob0db",
- * @li @b 3 - "mob3db",
- * @li @b 4 - "extnd6db"
- * @li @b 5 - "extnd8db"
- */
- IN UINT8 DeviceNumber; /**< PCI Device number for port.
- * @li @b 0 - Native port device number
- * @li @b N - Port device number (See available configurations @ref F12LaneConfigurations "Family 0x12", @ref F14LaneConfigurations "Family 0x14")
- */
- IN UINT8 FunctionNumber; ///< Reserved for future use
- IN UINT8 LinkSpeedCapability; /**< PCIe link speed/
- * @li @b 0 - Maximum supported by silicon
- * @li @b 1 - Gen1
- * @li @b 2 - Gen2
- * @li @b 3 - Gen3
- */
- IN UINT8 LinkAspm; /**< ASPM control. (see AgesaPcieLinkAspm for additional option to control ASPM)
- * @li @b 0 - Disabled
- * @li @b 1 - L0s only
- * @li @b 2 - L1 only
- * @li @b 3 - L0s and L1
- */
- IN UINT8 LinkHotplug; /**< Hotplug control.
- * @li @b 0 - Disabled
- * @li @b 1 - Basic
- * @li @b 2 - Server
- * @li @b 3 - Enhanced
- */
- IN UINT8 ResetId; /**< Arbitrary number greater than 0 assigned by platform firmware for GPIO
- * identification which control reset for given port.
- * Each port with unique GPIO should have unique ResetId assigned.
- * All ports use same GPIO to control reset should have same ResetId assigned.
- * see AgesaPcieSlotResetContol.
- */
- IN PCIe_PORT_MISC_CONTROL MiscControls; ///< Misc extended controls
-} PCIe_PORT_DATA;
-
-/// DDI channel lane mapping
-typedef struct { ///< Structure that discribe lane mapping
- IN UINT8 Lane0 :2; /**< Lane 0 mapping
- * @li @b 0 - Map to lane 0
- * @li @b 1 - Map to lane 1
- * @li @b 2 - Map to lane 2
- * @li @b 2 - Map to lane 3
- */
- IN UINT8 Lane1 :2; ///< Lane 1 mapping (see "Lane 0 mapping")
- IN UINT8 Lane2 :2; ///< Lane 2 mapping (see "Lane 0 mapping")
- IN UINT8 Lane3 :2; ///< Lane 3 mapping (see "Lane 0 mapping")
-} CHANNEL_MAPPING; ///< Lane mapping
-
-/// Common Channel Mapping
-typedef union {
- IN UINT8 ChannelMappingValue; ///< Raw lane mapping
- IN CHANNEL_MAPPING ChannelMapping; ///< Channel mapping
-} CONN_CHANNEL_MAPPING;
-
-/// DDI Configuration data
-typedef struct {
- IN UINT8 ConnectorType; /**< Display Connector Type
- * @li @b 0 - DP
- * @li @b 1 - eDP
- * @li @b 2 - Single Link DVI-D
- * @li @b 3 - Dual Link DVI-D (see @ref F12DualLinkDviDescription "Family 0x12 Dual Link DVI connector description")
- * @li @b 4 - HDMI
- * @li @b 5 - Travis DP-to-VGA
- * @li @b 6 - Travis DP-to-LVDS
- * @li @b 7 - Hudson-2 NutMeg DP-to-VGA
- * @li @b 8 - Single Link DVI-I
- * @li @b 9 - Native CRT (Family 0x14)
- * @li @b 10 - Native LVDS (Family 0x14)
- * @li @b 11 - Auto detect LCD panel connector type. VBIOS is able to auto detect the LVDS connector type: native LVDS, eDP or Travis-LVDS
- * The auto detection method only support panel with EDID.
- */
- IN UINT8 AuxIndex; /**< Indicates which AUX or DDC Line is used
- * @li @b 0 - AUX1
- * @li @b 1 - AUX2
- * @li @b 2 - AUX3
- * @li @b 3 - AUX4
- * @li @b 4 - AUX5
- * @li @b 5 - AUX6
- */
- IN UINT8 HdpIndex; /**< Indicates which HDP pin is used
- * @li @b 0 - HDP1
- * @li @b 1 - HDP2
- * @li @b 2 - HDP3
- * @li @b 3 - HDP4
- * @li @b 4 - HDP5
- * @li @b 5 - HDP6
- */
- IN CONN_CHANNEL_MAPPING Mapping[2]; /**< Set specific mapping of lanes to connector pins
- * @li Mapping[0] define mapping for group of 4 lanes starting at PCIe_ENGINE_DATA.StartLane
- * @li Mapping[1] define mapping for group of 4 lanes ending at PCIe_ENGINE_DATA.EndLane (only applicable for Dual DDI link)
- * if Mapping[x] set to 0 than default mapping assumed
- */
-} PCIe_DDI_DATA;
-
-/// Engine Configuration
-typedef struct {
- IN UINT8 EngineType; /**< Engine type
- * @li @b 0 - Ignore engine configuration
- * @li @b 1 - PCIe port
- * @li @b 2 - DDI
- */
- IN UINT16 StartLane; /**< Start Lane ID (in reversed configuration StartLane > EndLane)
- * See lane description for @ref F12PcieLaneDescription "Family 0x12"
- * @ref F14PcieLaneDescription "Family 0x14".
- * See lane configurations for @ref F12LaneConfigurations "Family 0x12"
- * @ref F14LaneConfigurations "Family 0x14".
- */
- IN UINT16 EndLane; /**< End lane ID (in reversed configuration StartLane > EndLane)
- * See lane description for @ref F12PcieLaneDescription "Family 0x12",
- * @ref F14PcieLaneDescription "Family 0x14".
- * See lane configurations for @ref F12LaneConfigurations "Family 0x12"
- * @ref F14LaneConfigurations "Family 0x14".
- */
-
-} PCIe_ENGINE_DATA;
-
-/// PCIe port descriptor
-typedef struct {
- IN UINT32 Flags; /**< Descriptor flags
- * @li @b Bit31 - last descriptor in complex
- */
- IN PCIe_ENGINE_DATA EngineData; ///< Engine data
- IN PCIe_PORT_DATA Port; ///< PCIe port specific configuration info
-} PCIe_PORT_DESCRIPTOR;
-
-/// DDI descriptor
-typedef struct {
- IN UINT32 Flags; /**< Descriptor flags
- * @li @b Bit31 - last descriptor in complex
- */
- IN PCIe_ENGINE_DATA EngineData; ///< Engine data
- IN PCIe_DDI_DATA Ddi; ///< DDI port specific configuration info
-} PCIe_DDI_DESCRIPTOR;
-
-/// PCIe Complex descriptor
-typedef struct {
- IN UINT32 Flags; /**< Descriptor flags
- * @li @b Bit31 - last descriptor in topology
- */
- IN UINT32 SocketId; ///< Socket Id
- IN PCIe_PORT_DESCRIPTOR *PciePortList; ///< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
- IN PCIe_DDI_DESCRIPTOR *DdiLinkList; ///< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
- IN VOID *Reserved; ///< Reserved for future use
-} PCIe_COMPLEX_DESCRIPTOR;
-
-/// Action to control PCIe slot reset
-typedef enum {
- AssertSlotReset, ///< Assert slot reset
- DeassertSlotReset ///< Deassert slot reset
-} PCIE_RESET_CONTROL;
-
-///Slot Reset Info
-typedef struct {
- IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
- IN UINT8 ResetId; ///< Slot reset ID as specified in PCIe_PORT_DESCRIPTOR
- IN UINT8 ResetControl; ///< Reset control as in PCIE_RESET_CONTROL
-} PCIe_SLOT_RESET_INFO;
-
-/// Engine descriptor type
-typedef enum {
- PcieUnusedEngine = 0, ///< Unused descriptor
- PciePortEngine = 1, ///< PCIe port
- PcieDdiEngine = 2, ///< DDI
- MaxPcieEngine ///< Max engine type for boundary check.
-} PCIE_ENGINE_TYPE;
-
-/// PCIe link capability/speed
-typedef enum {
- PcieGenMaxSupported, ///< Maximum supported
- PcieGen1 = 1, ///< Gen1
- PcieGen2, ///< Gen2
- MaxPcieGen ///< Max Gen for boundary check
-} PCIE_LINK_SPEED_CAP;
-
-/// PCIe PSPP Power policy
-typedef enum {
- PsppDisabled, ///< PSPP disabled
- PsppPerformance = 1, ///< Performance
- PsppBalanceHigh, ///< Balance-High
- PsppBalanceLow, ///< Balance-Low
- PsppPowerSaving, ///< Power Saving
- MaxPspp ///< Max Pspp for boundary check
-} PCIE_PSPP_POLICY;
-
-/// DDI display connector type
-typedef enum {
- ConnectorTypeDP, ///< DP
- ConnectorTypeEDP, ///< eDP
- ConnectorTypeSingleLinkDVI, ///< Single Link DVI-D
- ConnectorTypeDualLinkDVI, ///< Dual Link DVI-D
- ConnectorTypeHDMI, ///< HDMI
- ConnectorTypeTravisDpToVga, ///< Travis DP-to-VGA
- ConnectorTypeTravisDpToLvds, ///< Travis DP-to-LVDS
- ConnectorTypeNutmegDpToVga, ///< Hudson-2 NutMeg DP-to-VGA
- ConnectorTypeSingleLinkDviI, ///< Single Link DVI-I
- ConnectorTypeCrt, ///< CRT (VGA)
- ConnectorTypeLvds, ///< LVDS
- ConnectorTypeAutoDetect, ///< VBIOS auto detect connector type (native LVDS, eDP or Travis-LVDS)
- MaxConnectorType ///< Not valid value, used to verify input
-} PCIE_CONNECTOR_TYPE;
-
-/// PCIe link channel type
-typedef enum {
- ChannelTypeLowLoss, ///< Low Loss
- ChannelTypeHighLoss, ///< High Loss
- ChannelTypeMob0db, ///< Mobile 0dB
- ChannelTypeMob3db, ///< Mobile 3dB
- ChannelTypeExt6db, ///< Extended 6dB
- ChannelTypeExt8db, ///< Extended 8dB
- MaxChannelType ///< Not valid value, used to verify input
-} PCIE_CHANNEL_TYPE;
-
-/// PCIe link ASPM
-typedef enum {
- AspmDisabled, ///< Disabled
- AspmL0s, ///< PCIe L0s link state
- AspmL1, ///< PCIe L1 link state
- AspmL0sL1, ///< PCIe L0s & L1 link state
- MaxAspm ///< Not valid value, used to verify input
-} PCIE_ASPM_TYPE;
-
-/// PCIe link hotplug support
-typedef enum {
- HotplugDisabled, ///< Hotplug disable
- HotplugBasic, ///< Basic Hotplug
- HotplugServer, ///< Server Hotplug
- HotplugEnhanced, ///< Enhanced
- HotplugInboard, ///< Inboard
- MaxHotplug ///< Not valid value, used to verify input
-} PCIE_HOTPLUG_TYPE;
-
-/// PCIe link initialization
-typedef enum {
- PortDisabled, ///< Disable
- PortEnabled ///< Enable
-} PCIE_PORT_ENABLE;
-
-/// DDI Aux channel
-typedef enum {
- Aux1, ///< Aux1
- Aux2, ///< Aux2
- Aux3, ///< Aux3
- Aux4, ///< Aux4
- Aux5, ///< Aux5
- Aux6, ///< Aux6
- MaxAux ///< Not valid value, used to verify input
-} PCIE_AUX_TYPE;
-
-/// DDI Hdp Index
-typedef enum {
- Hdp1, ///< Hdp1
- Hdp2, ///< Hdp2
- Hdp3, ///< Hdp3
- Hdp4, ///< Hdp4
- Hdp5, ///< Hdp5
- Hdp6, ///< Hdp6
- MaxHdp ///< Not valid value, used to verify input
-} PCIE_HDP_TYPE;
-
-// Macro for statically initialization of various structures
-#define PCIE_ENGINE_DATA_INITIALIZER(mType, mStartLane, mEndLane) {mType, mStartLane, mEndLane}
-#define PCIE_PORT_DATA_INITIALIZER(mPortPresent, mChannelType, mDevAddress, mHotplug, mMaxLinkSpeed, mMaxLinkCap, mAspm, mResetId) \
-{mPortPresent, mChannelType, mDevAddress, 0, mMaxLinkSpeed, mAspm, mHotplug, mResetId, {0, mMaxLinkCap} }
-#define PCIE_DDI_DATA_INITIALIZER(mConnectorType, mAuxIndex, mHpdIndex ) \
-{mConnectorType, mAuxIndex, mHpdIndex, {0, 0}}
-#define PCIE_DDI_DATA_INITIALIZER_V1(mConnectorType, mAuxIndex, mHpdIndex, mMapping0, mMapping1) \
-{mConnectorType, mAuxIndex, mHpdIndex, {mMapping0, mMapping1}}
-
-
-/*----------------------------------------------------------------------------
- * GNB configuration info
- *----------------------------------------------------------------------------
- */
-/// Configuration settings for GNB.
-typedef struct {
- IN UINT8 Gnb3dStereoPinIndex; ///< 3D Stereo Pin ID.
- ///< @li 0 = Stereo 3D is disabled (default).
- ///< @li 1 = Use processor pin HPD1.
- ///< @li 2 = Use processor pin HPD2
- ///< @li 3 = Use processor pin HPD3
- ///< @li 4 = Use processor pin HPD4
- ///< @li 5 = Use processor pin HPD5
- ///< @li 6 = Use processor pin HPD6
- ///< @BldCfgItem{BLDCFG_STEREO_3D_PINOUT}
- IN UINT16 LvdsSpreadSpectrum; ///< Spread spectrum value in 0.01 %
- ///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM}
- IN UINT16 LvdsSpreadSpectrumRate; ///< Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz
- ///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE}
-} GNB_ENV_CONFIGURATION;
-
-/// GNB configuration info
-typedef struct {
- IN PCIe_COMPLEX_DESCRIPTOR *PcieComplexList; /**< Pointer to array of structures describe PCIe topology on each processor package or NULL.
- * Last element of array must ne terminated with DESCRIPTOR_TERMINATE_LIST
- * Example of topology definition for single socket system:
- * @code
- * PCIe_PORT_DESCRIPTOR PortList [] = {
- * // Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...)
- * {
- * 0, //Descriptor flags
- * PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15),
- * PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
- * },
- * // Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...)
- * {
- * 0, //Descriptor flags
- * PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 19),
- * PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
- * },
- * // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
- * {
- * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
- * PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
- * PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
- * }
- * };
- * PCIe_PORT_DESCRIPTOR DdiList [] = {
- * // Initialize Ddi descriptor (DDI interface Lanes 24:27, Display Port Connector, ...)
- * {
- * 0, //Descriptor flags
- * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27),
- * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1, 0)
- * },
- * // Initialize Ddi descriptor (DDI interface Lanes 28:31, HDMI, ...)
- * {
- * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
- * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31),
- * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2, 0)
- * }
- * };
- * PCIe_COMPLEX_DESCRIPTOR PlatformTopology = {
- * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate complexes list
- * 0, //Socket ID
- * &PortList[0],
- * &DdiList[0],
- * }
- * @endcode
- */
- IN UINT8 PsppPolicy; /**< PSPP (PCIe Speed Power Policy)
- * @li @b 0 - Disabled
- * @li @b 1 - Performance
- * @li @b 2 - Balance-High
- * @li @b 3 - Balance-Low
- * @li @b 4 - Power Saving
- */
-
-} GNB_CONFIGURATION;
-//
-// MEMORY-SPECIFIC DATA STRUCTURES
-//
-//
-//
-//
-// AGESA MAXIMIUM VALUES
-//
-// These Max values are used to define array sizes and associated loop
-// counts in the code. They reflect the maximum values that AGESA
-// currently supports and does not necessarily reflect the hardware
-// capabilities of configuration.
-//
-
-#define MAX_SOCKETS_SUPPORTED 8 ///< Max number of sockets in system
-#define MAX_CHANNELS_PER_SOCKET 4 ///< Max Channels per sockets
-#define MAX_DIMMS_PER_CHANNEL 4 ///< Max DIMMs on a memory channel (independent of platform)
-#define NUMBER_OF_DELAY_TABLES 9 ///< Number of tables defined in CH_DEF_STRUCT.
- ///< Eg: UINT16 *RcvEnDlys;
- ///< UINT8 *WrDqsDlys;
- ///< UINT8 *RdDqsDlys;
- ///< UINT8 *WrDatDlys;
- ///< UINT8 *RdDqsMinDlys;
- ///< UINT8 *RdDqsMaxDlys;
- ///< UINT8 *WrDatMinDlys;
- ///< UINT8 *WrDatMaxDlys;
-#define NUMBER_OF_FAILURE_MASK_TABLES 1 ///< Number of failure mask tables
-
-#define MAX_PLATFORM_TYPES 16 ///< Platform types per system
-
-#define MCT_TRNG_KEEPOUT_START 0x00004000 ///< base [39:8]
-#define MCT_TRNG_KEEPOUT_END 0x00007FFF ///< base [39:8]
-
-#define UMA_ATTRIBUTE_INTERLEAVE 0x80000000 ///< Uma Region is interleaved
-#define UMA_ATTRIBUTE_ON_DCT0 0x40000000 ///< UMA resides on memory that belongs to DCT0
-#define UMA_ATTRIBUTE_ON_DCT1 0x20000000 ///< UMA resides on memory that belongs to DCT1
-
-typedef UINT8 PSO_TABLE; ///< Platform Configuration Table
-
-// AGESA DEFINITIONS
-//
-// Many of these are derived from the platform and hardware specific definitions
-
-/// EccSymbolSize override value
-#define ECCSYMBOLSIZE_USE_BKDG 0 ///< Use BKDG Recommended Value
-#define ECCSYMBOLSIZE_FORCE_X4 4 ///< Force to x4
-#define ECCSYMBOLSIZE_FORCE_X8 8 ///< Force to x8
-/// CPU Package Type
-#define PT_L1 0 ///< L1 Package type
-#define PT_M2 1 ///< AM Package type
-#define PT_S1 2 ///< S1 Package type
-
-/// Structures use to pass system Logical CPU-ID
-typedef struct {
- IN OUT UINT64 Family; ///< Indicates logical ID Family
- IN OUT UINT64 Revision; ///< Indicates logical ID Family
-} CPU_LOGICAL_ID;
-
-/// Build Configuration values for BLDCFG_AMD_PLATFORM_TYPE
-typedef enum {
- AMD_PLATFORM_SERVER = 0x8000, ///< Server
- AMD_PLATFORM_DESKTOP = 0x10000, ///< Desktop
- AMD_PLATFORM_MOBILE = 0x20000, ///< Mobile
-} AMD_PLATFORM_TYPE;
-
-/// Dram technology type
-typedef enum {
- DDR2_TECHNOLOGY, ///< DDR2 technology
- DDR3_TECHNOLOGY ///< DDR3 technology
-} TECHNOLOGY_TYPE;
-
-/// Build Configuration values for BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT & BLDCFG_MEMORY_CLOCK_SELECT
-typedef enum {
- DDR400_FREQUENCY = 200, ///< DDR 400
- DDR533_FREQUENCY = 266, ///< DDR 533
- DDR667_FREQUENCY = 333, ///< DDR 667
- DDR800_FREQUENCY = 400, ///< DDR 800
- DDR1066_FREQUENCY = 533, ///< DDR 1066
- DDR1333_FREQUENCY = 667, ///< DDR 1333
- DDR1600_FREQUENCY = 800, ///< DDR 1600
- DDR1866_FREQUENCY = 933, ///< DDR 1866
- UNSUPPORTED_DDR_FREQUENCY ///< Highest limit of DDR frequency
-} MEMORY_BUS_SPEED;
-
-/// Build Configuration values for BLDCFG_MEMORY_QUADRANK_TYPE
-typedef enum {
- QUADRANK_REGISTERED, ///< Quadrank registered DIMM
- QUADRANK_UNBUFFERED ///< Quadrank unbuffered DIMM
-} QUANDRANK_TYPE;
-
-/// Build Configuration values for BLDCFG_TIMING_MODE_SELECT
-typedef enum {
- TIMING_MODE_AUTO, ///< Use best rate possible
- TIMING_MODE_LIMITED, ///< Set user top limit
- TIMING_MODE_SPECIFIC ///< Set user specified speed
-} USER_MEMORY_TIMING_MODE;
-
-/// Build Configuration values for BLDCFG_POWER_DOWN_MODE
-typedef enum {
- POWER_DOWN_BY_CHANNEL, ///< Channel power down mode
- POWER_DOWN_BY_CHIP_SELECT, ///< Chip select power down mode
- POWER_DOWN_MODE_AUTO ///< AGESA to select power down mode
-} POWER_DOWN_MODE;
-
-/// Low voltage support
-typedef enum {
- VOLT1_5, ///< 1.5 Volt
- VOLT1_35, ///< 1.35 Volt
- VOLT1_25, ///< 1.25 Volt
- VOLT_UNSUPPORTED = 0xFF ///< No common voltage found
-} DIMM_VOLTAGE;
-
-/// UMA Mode
-typedef enum {
- UMA_NONE = 0, ///< UMA None
- UMA_SPECIFIED = 1, ///< UMA Specified
- UMA_AUTO = 2 ///< UMA Auto
-} UMA_MODE;
-
-/// Build Configuration values for BLDCFG_UMA_ALIGNMENT
-typedef enum {
- NO_UMA_ALIGNED = 0x00FFFFFF, ///< NO UMA aligned
- UMA_128MB_ALIGNED = 0x00FFF800, ///< UMA 128MB aligned
- UMA_256MB_ALIGNED = 0x00FFF000, ///< UMA 256MB aligned
- UMA_512MB_ALIGNED = 0x00FFE000, ///< UMA 512MB aligned
-} UMA_ALIGNMENT;
-
-///
-/// Global MCT Configuration Status Word (GStatus)
-///
-typedef enum {
- GsbMTRRshort, ///< Ran out of MTRRs while mapping memory
- GsbAllECCDimms, ///< All banks of all Nodes are ECC capable
- GsbDramECCDis, ///< Dram ECC requested but not enabled.
- GsbSoftHole, ///< A Node Base gap was created
- GsbHWHole, ///< A HW dram remap was created
- GsbNodeIntlv, ///< Node Memory interleaving was enabled
- GsbSpIntRemapHole, ///< Special condition for Node Interleave and HW remapping
- GsbEnDIMMSpareNW, ///< Indicates that DIMM Spare can be used without a warm reset
-
- GsbEOL ///< End of list
-} GLOBAL_STATUS_FIELD;
-
-///
-/// Local Error Status (DIE_STRUCT.ErrStatus[31:0])
-///
-typedef enum {
- EsbNoDimms, ///< No DIMMs
- EsbSpdChkSum, ///< SPD Checksum fail
- EsbDimmMismatchM, ///< dimm module type(buffer) mismatch
- EsbDimmMismatchT, ///< dimm CL/T mismatch
- EsbDimmMismatchO, ///< dimm organization mismatch (128-bit)
- EsbNoTrcTrfc, ///< SPD missing Trc or Trfc info
- EsbNoCycTime, ///< SPD missing byte 23 or 25
- EsbBkIntDis, ///< Bank interleave requested but not enabled
- EsbDramECCDis, ///< Dram ECC requested but not enabled
- EsbSpareDis, ///< Online spare requested but not enabled
- EsbMinimumMode, ///< Running in Minimum Mode
- EsbNoRcvrEn, ///< No DQS Receiver Enable pass window found
- EsbSmallRcvr, ///< DQS Rcvr En pass window too small (far right of dynamic range)
- EsbNoDqsPos, ///< No DQS-DQ passing positions
- EsbSmallDqs, ///< DQS-DQ passing window too small
- EsbDCBKScrubDis, ///< DCache scrub requested but not enabled
-
- EsbEMPNotSupported, ///< Processor is not capable for EMP.
- EsbEMPConflict, ///< EMP requested but cannot be enabled since
- ///< channel interleaving, bank interleaving, or bank swizzle is enabled.
- EsbEMPDis, ///< EMP requested but cannot be enabled since
- ///< memory size of each DCT is not a power of two.
-
- EsbEOL ///< End of list
-} ERROR_STATUS_FIELD;
-
-///
-/// Local Configuration Status (DIE_STRUCT.Status[31:0])
-///
-typedef enum {
- SbRegistered, ///< All DIMMs are Registered
- SbEccDimms, ///< All banks ECC capable
- SbParDimms, ///< All banks Addr/CMD Parity capable
- SbDiagClks, ///< Jedec ALL slots clock enable diag mode
- Sb128bitmode, ///< DCT in 128-bit mode operation
- Sb64MuxedMode, ///< DCT in 64-bit mux'ed mode.
- Sb2TMode, ///< 2T CMD timing mode is enabled.
- SbSWNodeHole, ///< Remapping of Node Base on this Node to create a gap.
- SbHWHole, ///< Memory Hole created on this Node using HW remapping.
- SbOver400Mhz, ///< DCT freq greater than or equal to 400MHz flag
- SbDQSPosPass2, ///< Used for TrainDQSPos DIMM0/1, when freq greater than or equal to 400MHz
- SbDQSRcvLimit, ///< Used for DQSRcvEnTrain to know we have reached the upper bound.
- SbExtConfig, ///< Indicate the default setting for extended PCI configuration support
- SbLrdimms, ///< All DIMMs are LRDIMMs
-
- SbEOL ///< End of list
-} LOCAL_STATUS_FIELD;
-
-
-///< CPU MSR Register definitions ------------------------------------------
-#define SYS_CFG 0xC0010010
-#define TOP_MEM 0xC001001A
-#define TOP_MEM2 0xC001001D
-#define HWCR 0xC0010015
-#define NB_CFG 0xC001001F
-
-#define FS_BASE 0xC0000100
-#define IORR0_BASE 0xC0010016
-#define IORR0_MASK 0xC0010017
-#define BU_CFG 0xC0011023
-#define BU_CFG2 0xC001102A
-#define COFVID_STAT 0xC0010071
-#define TSC 0x10
-
-//-----------------------------------------------------------------------------
-///
-/// SPD Data for each DIMM.
-///
-typedef struct _SPD_DEF_STRUCT {
- IN BOOLEAN DimmPresent; ///< Indicates that the DIMM is present and Data is valid
- IN UINT8 Data[256]; ///< Buffer for 256 Bytes of SPD data from DIMM
-} SPD_DEF_STRUCT;
-
-///
-/// Channel Definition Structure.
-/// This data structure defines entries that are specific to the channel initialization
-///
-typedef struct _CH_DEF_STRUCT {
- OUT UINT8 ChannelID; ///< Physical channel ID of a socket(0 = CH A, 1 = CH B, 2 = CH C, 3 = CH D)
- OUT TECHNOLOGY_TYPE TechType; ///< Technology type of this channel
- OUT UINT8 ChDimmPresent; ///< For each bit n 0..7, 1 = DIMM n is present.
- ///< DIMM# Select Signal
- ///< 0 MA0_CS_L[0, 1]
- ///< 1 MB0_CS_L[0, 1]
- ///< 2 MA1_CS_L[0, 1]
- ///< 3 MB1_CS_L[0, 1]
- ///< 4 MA2_CS_L[0, 1]
- ///< 5 MB2_CS_L[0, 1]
- ///< 6 MA3_CS_L[0, 1]
- ///< 7 MB3_CS_L[0, 1]
-
- OUT struct _DCT_STRUCT *DCTPtr; ///< Pointer to the DCT data of this channel.
- OUT struct _DIE_STRUCT *MCTPtr; ///< Pointer to the node data of this channel.
- OUT SPD_DEF_STRUCT *SpdPtr; ///< Pointer to the SPD data for this channel. (Setup by NB Constructor)
- OUT SPD_DEF_STRUCT *DimmSpdPtr[MAX_DIMMS_PER_CHANNEL]; ///< Array of pointers to
- ///< SPD Data for each Dimm. (Setup by Tech Block Constructor)
- OUT UINT8 ChDimmValid; ///< For each bit n 0..3, 1 = DIMM n is valid and is/will be configured where 4..7 are reserved.
- ///<
- OUT UINT8 RegDimmPresent; ///< For each bit n 0..3, 1 = DIMM n is a registered DIMM where 4..7 are reserved.
- OUT UINT8 LrDimmPresent; ///< For each bit n 0..3, 1 = DIMM n is Load Reduced DIMM where 4..7 are reserved.
- OUT UINT8 SODimmPresent; ///< For each bit n 0..3, 1 = DIMM n is a SO-DIMM, where 4..7 are reserved.
- OUT UINT8 Loads; ///< Number of devices loading bus
- OUT UINT8 Dimms; ///< Number of DIMMs loading Channel
- OUT UINT8 Ranks; ///< Number of ranks loading Channel DATA
- OUT BOOLEAN SlowMode; ///< 1T or 2T CMD mode (slow access mode)
- ///< FALSE = 1T
- ///< TRUE = 2T
- ///< The following pointers will be pointed to dynamically allocated buffers.
- ///< Each buffer is two dimensional (RowCount x ColumnCount) and is lay-outed as in below.
- ///< Example: If DIMM and Byte based training, then
- ///< XX is a value in Hex
- ///< BYTE 0, BYTE 1, BYTE 2, BYTE 3, BYTE 4, BYTE 5, BYTE 6, BYTE 7, ECC BYTE
- ///< Row1 - Logical DIMM0 XX XX XX XX XX XX XX XX XX
- ///< Row2 - Logical DIMM1 XX XX XX XX XX XX XX XX XX
- OUT UINT16 *RcvEnDlys; ///< DQS Receiver Enable Delays
- OUT UINT8 *WrDqsDlys; ///< Write DQS delays (only valid for DDR3)
- OUT UINT8 *RdDqsDlys; ///< Read Dqs delays
- OUT UINT8 *WrDatDlys; ///< Write Data delays
- OUT UINT8 *RdDqsMinDlys; ///< Minimum Window for Read DQS
- OUT UINT8 *RdDqsMaxDlys; ///< Maximum Window for Read DQS
- OUT UINT8 *WrDatMinDlys; ///< Minimum Window for Write data
- OUT UINT8 *WrDatMaxDlys; ///< Maximum Window for Write data
- OUT UINT8 RowCount; ///< Number of rows of the allocated buffer.
- OUT UINT8 ColumnCount; ///< Number of columns of the allocated buffer.
- OUT UINT8 *FailingBitMask; ///< Table of masks to Track Failing bits
- OUT UINT32 DctOdcCtl; ///< Output Driver Strength (see BKDG FN2:Offset 9Ch, index 00h)
- OUT UINT32 DctAddrTmg; ///< Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h)
- OUT UINT32 PhyRODTCSLow; ///< Phy Read ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 180h)
- OUT UINT32 PhyRODTCSHigh; ///< Phy Read ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 181h)
- OUT UINT32 PhyWODTCSLow; ///< Phy Write ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 182h)
- OUT UINT32 PhyWODTCSHigh; ///< Phy Write ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 183)
- OUT UINT8 PhyWLODT[4]; ///< Write Levelization ODT Pattern for Dimm 0-3 (see BKDG FN2:Offset 9Ch, index 0x8[11:8])
- OUT UINT16 DctEccDqsLike; ///< DCT DQS ECC UINT8 like...
- OUT UINT8 DctEccDqsScale; ///< DCT DQS ECC UINT8 scale
- OUT UINT16 PtrPatternBufA; ///< Ptr on stack to aligned DQS testing pattern
- OUT UINT16 PtrPatternBufB; ///< Ptr on stack to aligned DQS testing pattern
- OUT UINT8 ByteLane; ///< Current UINT8 Lane (0..7)
- OUT UINT8 Direction; ///< Current DQS-DQ training write direction (0=read, 1=write)
- OUT UINT8 Pattern; ///< Current pattern
- OUT UINT8 DqsDelay; ///< Current DQS delay value
- OUT UINT16 HostBiosSrvc1; ///< UINT16 sized general purpose field for use by host BIOS. Scratch space.
- OUT UINT32 HostBiosSrvc2; ///< UINT32 sized general purpose field for use by host BIOS. Scratch space.
- OUT UINT16 DctMaxRdLat; ///< Max Read Latency (ns) for the DCT
- OUT UINT8 DIMMValidCh; ///< DIMM# in CH
- OUT UINT8 MaxCh; ///< Max number of CH in system
- OUT UINT8 Dct; ///< Dct pointer
- OUT UINT8 WrDatGrossH; ///< Write Data Gross delay high value
- OUT UINT8 DqsRcvEnGrossL; ///< DQS Receive Enable Gross Delay low
-
- OUT UINT8 TrwtWB; ///< Non-SPD timing value for TrwtWB
- OUT UINT8 CurrRcvrDctADelay; ///< for keep current RcvrEnDly
- OUT UINT16 T1000; ///< get the T1000 figure (cycle time (ns) * 1K)
- OUT UINT8 DqsRcvEnPass; ///< for TrainRcvrEn UINT8 lane pass flag
- OUT UINT8 DqsRcvEnSaved; ///< for TrainRcvrEn UINT8 lane saved flag
- OUT UINT8 SeedPass1Remainder; ///< for Phy assisted DQS receiver enable training
-
- OUT UINT8 ClToNbFlag; ///< is used to restore ClLinesToNbDis bit after memory
- OUT UINT32 NodeSysBase; ///< for channel interleave usage
- OUT UINT8 RefRawCard[MAX_DIMMS_PER_CHANNEL]; ///< Array of rawcards detected
- OUT UINT8 CtrlWrd02[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 2 values per DIMM
- OUT UINT8 CtrlWrd03[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 3 values per DIMM
- OUT UINT8 CtrlWrd04[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 4 values per DIMM
- OUT UINT8 CtrlWrd05[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 5 values per DIMM
- OUT UINT8 CtrlWrd08[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 8 values per DIMM
-
- OUT UINT16 CsPresentDCT; ///< For each bit n 0..7, 1 = Chip-select n is present
- OUT UINT8 DimmMirrorPresent; ///< For each bit n 0..3, 1 = DIMM n is OnDimmMirror capable where 4..7 are reserved.
- OUT UINT8 DimmSpdCse; ///< For each bit n 0..3, 1 = DIMM n SPD checksum error where 4..7 are reserved.
- OUT UINT8 DimmExclude; ///< For each bit n 0..3, 1 = DIMM n gets excluded where 4..7 are reserved.
- OUT UINT8 DimmYr06; ///< Bitmap indicating which Dimms have a manufacturer's year code <= 2006
- OUT UINT8 DimmWk2406; ///< Bitmap indicating which Dimms have a manufacturer's week code <= 24 of 2006 (June)
- OUT UINT8 DimmPlPresent; ///< Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.
- OUT UINT8 DimmQrPresent; ///< QuadRank DIMM present?
- OUT UINT8 DimmDrPresent; ///< Bitmap indicating that Dual Rank Dimms are present
- OUT UINT8 DimmSRPresent; ///< Bitmap indicating that Single Rank Dimms are present
- OUT UINT8 Dimmx4Present; ///< For each bit n 0..3, 1 = DIMM n contains x4 data devices. where 4..7 are reserved.
- OUT UINT8 Dimmx8Present; ///< For each bit n 0..3, 1 = DIMM n contains x8 data devices. where 4..7 are reserved.
- OUT UINT8 Dimmx16Present; ///< For each bit n 0..3, 1 = DIMM n contains x16 data devices. where 4..7 are reserved.
- OUT UINT8 LrdimmPhysicalRanks[MAX_DIMMS_PER_CHANNEL];///< Number of Physical Ranks for LRDIMMs
- OUT UINT8 LrDimmLogicalRanks[MAX_DIMMS_PER_CHANNEL];///< Number of LRDIMM Logical ranks in this configuration
- OUT UINT8 LrDimmRankMult[MAX_DIMMS_PER_CHANNEL];///< Rank Multipication factor per dimm.
-
- OUT UINT8 *MemClkDisMap; ///< This pointer will be set to point to an array that describes
- ///< the routing of M[B,A]_CLK pins to the DIMMs' ranks. AGESA will
- ///< base on this array to disable unused MemClk to save power.
- ///<
- ///< The array must have 8 entries. Each entry, which associates with
- ///< one MemClkDis bit, is a bitmap of 8 CS that that MemClk is routed to.
- ///< Example:
- ///< BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package
- ///< is like below:
- ///< Bit AM3/S1g3 pin name
- ///< 0 M[B,A]_CLK_H/L[0]
- ///< 1 M[B,A]_CLK_H/L[1]
- ///< 2 M[B,A]_CLK_H/L[2]
- ///< 3 M[B,A]_CLK_H/L[3]
- ///< 4 M[B,A]_CLK_H/L[4]
- ///< 5 M[B,A]_CLK_H/L[5]
- ///< 6 M[B,A]_CLK_H/L[6]
- ///< 7 M[B,A]_CLK_H/L[7]
- ///< And platform has the following routing:
- ///< CS0 M[B,A]_CLK_H/L[4]
- ///< CS1 M[B,A]_CLK_H/L[2]
- ///< CS2 M[B,A]_CLK_H/L[3]
- ///< CS3 M[B,A]_CLK_H/L[5]
- ///< Then MemClkDisMap should be pointed to the following array:
- ///< CLK_2 CLK_3 CLK_4 CLK_5
- ///< 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00
- ///< Each entry of the array is the bitmask of 8 chip selects.
-
- OUT UINT8 *CKETriMap; ///< This pointer will be set to point to an array that describes
- ///< the routing of CKE pins to the DIMMs' ranks.
- ///< The array must have 2 entries. Each entry, which associates with
- ///< one CKE pin, is a bitmap of 8 CS that that CKE is routed to.
- ///< AGESA will base on this array to disable unused CKE pins to save power.
-
- OUT UINT8 *ODTTriMap; ///< This pointer will be set to point to an array that describes
- ///< the routing of ODT pins to the DIMMs' ranks.
- ///< The array must have 4 entries. Each entry, which associates with
- ///< one ODT pin, is a bitmap of 8 CS that that ODT is routed to.
- ///< AGESA will base on this array to disable unused ODT pins to save power.
-
- OUT UINT8 *ChipSelTriMap; ///< This pointer will be set to point to an array that describes
- ///< the routing of chip select pins to the DIMMs' ranks.
- ///< The array must have 8 entries. Each entry is a bitmap of 8 CS.
- ///< AGESA will base on this array to disable unused Chip select pins to save power.
-
- OUT BOOLEAN ExtendTmp; ///< If extended temperature is supported on all dimms on a channel.
-
- OUT UINT8 Reserved[100]; ///< Reserved
-} CH_DEF_STRUCT;
-
-///
-/// DCT Channel Timing Parameters.
-/// This data structure sets timings that are specific to the channel.
-///
-typedef struct _CH_TIMING_STRUCT {
- OUT UINT16 DctDimmValid; ///< For each bit n 0..3, 1=DIMM n is valid and is/will be configured where 4..7 are reserved.
- OUT UINT16 DimmMirrorPresent; ///< For each bit n 0..3, 1=DIMM n is OnDimmMirror capable where 4..7 are reserved.
- OUT UINT16 DimmSpdCse; ///< For each bit n 0..3, 1=DIMM n SPD checksum error where 4..7 are reserved.
- OUT UINT16 DimmExclude; ///< For each bit n 0..3, 1 = DIMM n gets excluded where 4..7 are reserved.
- OUT UINT16 CsPresent; ///< For each bit n 0..7, 1=Chip-select n is present
- OUT UINT16 CsEnabled; ///< For each bit n 0..7, 1=Chip-select n is enabled
- OUT UINT16 CsTestFail; ///< For each bit n 0..7, 1=Chip-select n is present but disabled
- OUT UINT16 CsTrainFail; ///< Bitmap showing which chipselects failed training
- OUT UINT16 DIMM1KPage; ///< For each bit n 0..3, 1=DIMM n contains 1K page devices. where 4..7 are reserved
- OUT UINT16 DimmQrPresent; ///< QuadRank DIMM present?
- OUT UINT16 DimmDrPresent; ///< Bitmap indicating that Dual Rank Dimms are present , where 4..7 are reserved
- OUT UINT8 DimmSRPresent; ///< Bitmap indicating that Single Rank Dimms are present, where 4..7 are reserved
- OUT UINT16 Dimmx4Present; ///< For each bit n 0..3, 1=DIMM n contains x4 data devices. where 4..7 are reserved
- OUT UINT16 Dimmx8Present; ///< For each bit n 0..3, 1=DIMM n contains x8 data devices. where 4..7 are reserved
- OUT UINT16 Dimmx16Present; ///< For each bit n 0..3, 1=DIMM n contains x16 data devices. where 4..7 are reserved
-
- OUT UINT16 DIMMTrcd; ///< Minimax Trcd*40 (ns) of DIMMs
- OUT UINT16 DIMMTrp; ///< Minimax Trp*40 (ns) of DIMMs
- OUT UINT16 DIMMTrtp; ///< Minimax Trtp*40 (ns) of DIMMs
- OUT UINT16 DIMMTras; ///< Minimax Tras*40 (ns) of DIMMs
- OUT UINT16 DIMMTrc; ///< Minimax Trc*40 (ns) of DIMMs
- OUT UINT16 DIMMTwr; ///< Minimax Twr*40 (ns) of DIMMs
- OUT UINT16 DIMMTrrd; ///< Minimax Trrd*40 (ns) of DIMMs
- OUT UINT16 DIMMTwtr; ///< Minimax Twtr*40 (ns) of DIMMs
- OUT UINT16 DIMMTfaw; ///< Minimax Tfaw*40 (ns) of DIMMs
- OUT UINT16 TargetSpeed; ///< Target DRAM bus speed in MHz
- OUT UINT16 Speed; ///< DRAM bus speed in MHz
- ///< 400 (MHz)
- ///< 533 (MHz)
- ///< 667 (MHz)
- ///< 800 (MHz)
- ///< and so on...
- OUT UINT8 CasL; ///< CAS latency DCT setting (busclocks)
- OUT UINT8 Trcd; ///< DCT Trcd (busclocks)
- OUT UINT8 Trp; ///< DCT Trp (busclocks)
- OUT UINT8 Trtp; ///< DCT Trtp (busclocks)
- OUT UINT8 Tras; ///< DCT Tras (busclocks)
- OUT UINT8 Trc; ///< DCT Trc (busclocks)
- OUT UINT8 Twr; ///< DCT Twr (busclocks)
- OUT UINT8 Trrd; ///< DCT Trrd (busclocks)
- OUT UINT8 Twtr; ///< DCT Twtr (busclocks)
- OUT UINT8 Tfaw; ///< DCT Tfaw (busclocks)
- OUT UINT8 Trfc0; ///< DCT Logical DIMM0 Trfc
- ///< 0 = 75ns (for 256Mb devs)
- ///< 1 = 105ns (for 512Mb devs)
- ///< 2 = 127.5ns (for 1Gb devs)
- ///< 3 = 195ns (for 2Gb devs)
- ///< 4 = 327.5ns (for 4Gb devs)
- OUT UINT8 Trfc1; ///< DCT Logical DIMM1 Trfc (see Trfc0 for format)
- OUT UINT8 Trfc2; ///< DCT Logical DIMM2 Trfc (see Trfc0 for format)
- OUT UINT8 Trfc3; ///< DCT Logical DIMM3 Trfc (see Trfc0 for format)
- OUT UINT32 DctMemSize; ///< Base[47:16], total DRAM size controlled by this DCT.
- ///<
- OUT BOOLEAN SlowMode; ///< 1T or 2T CMD mode (slow access mode)
- ///< FALSE = 1T
- ///< TRUE = 2T
- OUT UINT8 TrwtTO; ///< DCT TrwtTO (busclocks)
- OUT UINT8 Twrrd; ///< DCT Twrrd (busclocks)
- OUT UINT8 Twrwr; ///< DCT Twrwr (busclocks)
- OUT UINT8 Trdrd; ///< DCT Trdrd (busclocks)
- OUT UINT8 TrwtWB; ///< DCT TrwtWB (busclocks)
- OUT UINT8 TrdrdSD; ///< DCT TrdrdSD (busclocks)
- OUT UINT8 TwrwrSD; ///< DCT TwrwrSD (busclocks)
- OUT UINT8 TwrrdSD; ///< DCT TwrrdSD (busclocks)
- OUT UINT16 MaxRdLat; ///< Max Read Latency
- OUT UINT8 WrDatGrossH; ///< Temporary variables must be removed
- OUT UINT8 DqsRcvEnGrossL; ///< Temporary variables must be removed
-} CH_TIMING_STRUCT;
-
-///
-/// Data for each DCT.
-/// This data structure defines data used to configure each DRAM controller.
-///
-typedef struct _DCT_STRUCT {
- OUT UINT8 Dct; ///< Current Dct
- OUT CH_TIMING_STRUCT Timings; ///< Channel Timing structure
- OUT CH_DEF_STRUCT *ChData; ///< Pointed to a dynamically allocated array of Channel structures
- OUT UINT8 ChannelCount; ///< Number of channel per this DCT
-} DCT_STRUCT;
-
-
-///
-/// Data Structure defining each Die.
-/// This data structure contains information that is used to configure each Die.
-///
-typedef struct _DIE_STRUCT {
-
- /// Advanced:
-
- OUT UINT8 NodeId; ///< Node ID of current controller
- OUT UINT8 SocketId; ///< Socket ID of this Die
- OUT UINT8 DieId; ///< ID of this die relative to the socket
- OUT PCI_ADDR PciAddr; ///< Pci bus and device number of this controller.
- OUT AGESA_STATUS ErrCode; ///< Current error condition of Node
- ///< 0x0 = AGESA_SUCCESS
- ///< 0x1 = AGESA_UNSUPPORTED
- ///< 0x2 = AGESA_BOUNDS_CHK
- ///< 0x3 = AGESA_ALERT
- ///< 0x4 = AGESA_WARNING
- ///< 0x5 = AGESA_ERROR
- ///< 0x6 = AGESA_CRITICAL
- ///< 0x7 = AGESA_FATAL
- ///<
- OUT BOOLEAN ErrStatus[EsbEOL]; ///< Error Status bit Field
- ///<
- OUT BOOLEAN Status[SbEOL]; ///< Status bit Field
- ///<
- OUT UINT32 NodeMemSize; ///< Base[47:16], total DRAM size controlled by both DCT0 and DCT1 of this Node.
- ///<
- OUT UINT32 NodeSysBase; ///< Base[47:16] (system address) DRAM base address of this Node.
- ///<
- OUT UINT32 NodeHoleBase; ///< If not zero, Base[47:16] (system address) of dram hole for HW remapping. Dram hole exists on this Node
- ///<
- OUT UINT32 NodeSysLimit; ///< Base[47:16] (system address) DRAM limit address of this Node.
- ///<
- OUT UINT32 DimmPresent; ///< For each bit n 0..7, 1 = DIMM n is present.
- ///< DIMM# Select Signal
- ///< 0 MA0_CS_L[0, 1]
- ///< 1 MB0_CS_L[0, 1]
- ///< 2 MA1_CS_L[0, 1]
- ///< 3 MB1_CS_L[0, 1]
- ///< 4 MA2_CS_L[0, 1]
- ///< 5 MB2_CS_L[0, 1]
- ///< 6 MA3_CS_L[0, 1]
- ///< 7 MB3_CS_L[0, 1]
- ///<
- OUT UINT32 DimmValid; ///< For each bit n 0..7, 1 = DIMM n is valid and is / will be configured
- OUT UINT32 RegDimmPresent; ///< For each bit n 0..7, 1 = DIMM n is registered DIMM
- OUT UINT32 LrDimmPresent; ///< For each bit n 0..7, 1 = DIMM n is Load Reduced DIMM
- OUT UINT32 DimmEccPresent; ///< For each bit n 0..7, 1 = DIMM n is ECC capable.
- OUT UINT32 DimmParPresent; ///< For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable.
- ///<
- OUT UINT16 DimmTrainFail; ///< Bitmap showing which dimms failed training
- OUT UINT16 ChannelTrainFail; ///< Bitmap showing the channel information about failed Chip Selects
- ///< 0 in any bit field indicates Channel 0
- ///< 1 in any bit field indicates Channel 1
- OUT UINT8 Dct; ///< Need to be removed
- ///< DCT pointer
- OUT BOOLEAN GangedMode; ///< Ganged mode
- ///< 0 = disabled
- ///< 1 = enabled
- OUT CPU_LOGICAL_ID LogicalCpuid; ///< The logical CPUID of the node
- ///<
- OUT UINT16 HostBiosSrvc1; ///< UINT16 sized general purpose field for use by host BIOS. Scratch space.
- ///<
- OUT UINT32 HostBiosSrvc2; ///< UINT32 sized general purpose field for use by host BIOS. Scratch space.
- ///<
- OUT UINT8 MLoad; ///< Need to be removed
- ///< Number of devices loading MAA bus
- ///<
- OUT UINT8 MaxAsyncLat; ///< Legacy wrapper
- ///<
- OUT UINT8 ChbD3Rcvrdly; ///< Legacy wrapper
- ///<
- OUT UINT16 ChaMaxRdLat; ///< Max Read Latency (ns) for DCT 0
- ///<
- OUT UINT8 ChbD3BcRcvrdly; ///< CHB DIMM 3 Check UINT8 Receiver Enable Delay
-
- OUT DCT_STRUCT *DctData; ///< Pointed to a dynamically allocated array of DCT_STRUCTs
- OUT UINT8 DctCount; ///< Number of DCTs per this Die
- OUT UINT8 Reserved[16]; ///< Reserved
-} DIE_STRUCT;
-
-/**********************************************************************
- * S3 Support structure
- **********************************************************************/
-/// AmdInitResume, AmdS3LateRestore, and AmdS3Save param structure
-typedef struct {
- OUT UINT32 Signature; ///< "ASTR" for AMD Suspend-To-RAM
- OUT UINT16 Version; ///< S3 Params version number
- IN OUT UINT32 Flags; ///< Indicates operation
- IN OUT VOID *NvStorage; ///< Pointer to memory critical save state data
- IN OUT UINT32 NvStorageSize; ///< Size in bytes of the NvStorage region
- IN OUT VOID *VolatileStorage; ///< Pointer to remaining AMD save state data
- IN OUT UINT32 VolatileStorageSize; ///< Size in bytes of the VolatileStorage region
-} AMD_S3_PARAMS;
-
-///===============================================================================
-/// MEM_PARAMETER_STRUCT
-/// This data structure is used to pass wrapper parameters to the memory configuration code
-///
-typedef struct _MEM_PARAMETER_STRUCT {
-
- // Basic (Return parameters)
- // (This section contains the outbound parameters from the memory init code)
-
- OUT BOOLEAN GStatus[GsbEOL]; ///< Global Status bitfield.
- ///<
- OUT UINT32 HoleBase; ///< If not zero Base[47:16] (system address) of sub 4GB dram hole for HW remapping.
- ///<
- OUT UINT32 Sub4GCacheTop; ///< If not zero, the 32-bit top of cacheable memory.
- ///<
- OUT UINT32 SysLimit; ///< Limit[47:16] (system address).
- ///<
-
- OUT DIMM_VOLTAGE DDR3Voltage; ///< Find support voltage and send back to platform BIOS.
- ///< 0 = 1.5v
- ///< 1 = 1.35v
- ///< 2 = 1.2v
- ///< 0xFF = Mixed 1.5V and 1.2V in the system. 1.5V dimms get excluded
- ///< from the system.
- ///<
-
- OUT struct _MEM_DATA_STRUCT *MemData; ///< Access to global memory init data.
-
- // Advanced (Optional parameters)
- // Optional (all defaults values will be initialized by the
- // 'AmdMemInitDataStructDef' based on AMD defaults. It is up
- // to the IBV/OEM to change the defaults after initialization
- // but prior to the main entry to the memory code):
-
- // Memory Map/Mgt.
-
- IN UINT16 BottomIo; ///< Bottom of 32-bit IO space (8-bits).
- ///< NV_BOTTOM_IO[7:0]=Addr[31:24]
- ///<
- IN BOOLEAN MemHoleRemapping; ///< Memory Hole Remapping (1-bit).
- ///< FALSE = disable
- ///< TRUE = enable
-
-
- // Dram Timing
-
- IN USER_MEMORY_TIMING_MODE UserTimingMode; ///< User Memclock Mode.
- ///< @BldCfgItem{BLDCFG_TIMING_MODE_SELECT}
-
- IN MEMORY_BUS_SPEED MemClockValue; ///< Memory Clock Value.
- ///< @BldCfgItem{BLDCFG_MEMORY_CLOCK_SELECT}
-
-
- // Dram Configuration
-
- IN BOOLEAN EnableBankIntlv; ///< Dram Bank (chip-select) Interleaving (1-bit).
- ///< - FALSE =disable (default)
- ///< - TRUE = enable
- ///<
- ///< @BldCfgItem{BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING}
-
- IN BOOLEAN EnableNodeIntlv; ///< Node Memory Interleaving (1-bit).
- ///< - FALSE = disable (default)
- ///< - TRUE = enable
- ///<
- ///< @BldCfgItem{BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING}
-
- IN BOOLEAN EnableChannelIntlv; ///< Channel Interleaving (1-bit).
- ///< - FALSE = disable (default)
- ///< - TRUE = enable
- ///<
- ///< @BldCfgItem{BLDCFG_MEMORY_CHANNEL_INTERLEAVING}
- // ECC
-
- IN BOOLEAN EnableEccFeature; ///< enable ECC error to go into MCE.
- ///< - FALSE = disable (default)
- ///< - TRUE = enable
- ///<
- ///< @BldCfgItem{BLDCFG_ENABLE_ECC_FEATURE}
- // Dram Power
-
- IN BOOLEAN EnablePowerDown; ///< CKE based power down mode (1-bit).
- ///< - FALSE =disable (default)
- ///< - TRUE =enable
- ///<
- ///< @BldCfgItem{BLDCFG_MEMORY_POWER_DOWN}
-
- // Online Spare
-
- IN BOOLEAN EnableOnLineSpareCtl; ///< Chip Select Spare Control bit 0.
- ///< - FALSE = disable Spare (default)
- ///< - TRUE = enable Spare
- ///<
- ///< @BldCfgItem{BLDCFG_ONLINE_SPARE}
-
- IN UINT8 *TableBasedAlterations; ///< Desired modifications to register settings.
-
- IN PSO_TABLE *PlatformMemoryConfiguration;
- ///< A table that contains platform specific settings.
- ///< For example, MemClk routing, the number of DIMM slots per channel, ....
- ///< AGESA initializes this pointer with DefaultPlatformMemoryConfiguration that
- ///< contains default conservative settings. Platform BIOS can either tweak
- ///< DefaultPlatformMemoryConfiguration or reassign this pointer to its own table.
- ///<
- IN BOOLEAN EnableParity; ///< Parity control.
- ///< - TRUE = enable
- ///< - FALSE = disable (default)
- ///<
- ///< @BldCfgItem{BLDCFG_MEMORY_PARITY_ENABLE}
-
- IN BOOLEAN EnableBankSwizzle; ///< BankSwizzle control.
- ///< - FALSE = disable
- ///< - TRUE = enable (default)
- ///<
- ///< @BldCfgItem{BLDCFG_BANK_SWIZZLE}
-
- ///<
-
- IN BOOLEAN EnableMemClr; ///< Memory Clear functionality control.
- ///< - FALSE = disable
- ///< - TRUE = enable (default)
- ///<
-
- // Uma Configuration
-
- IN UMA_MODE UmaMode; ///< Uma Mode
- ///< 0 = None
- ///< 1 = Specified
- ///< 2 = Auto
- IN OUT UINT32 UmaSize; ///< The size of shared graphics dram (16-bits)
- ///< NV_UMA_Size[31:0]=Addr[47:16]
- ///<
- OUT UINT32 UmaBase; ///< The allocated Uma base address (32-bits)
- ///< NV_UMA_Base[31:0]=Addr[47:16]
- ///<
-
- /// Memory Restore Feature
-
- IN BOOLEAN MemRestoreCtl; ///< Memory context restore control
- ///< FALSE = perform memory init as normal (AMD default)
- ///< TRUE = restore memory context and skip training. This requires
- ///< MemContext is valid before AmdInitPost
- ///<
- IN BOOLEAN SaveMemContextCtl; ///< Control switch to save memory context at the end of MemAuto
- ///< TRUE = AGESA will setup MemContext block before exit AmdInitPost
- ///< FALSE = AGESA will not setup MemContext block. Platform is
- ///< expected to call S3Save later in POST if it wants to
- ///< use memory context restore feature.
- ///<
- IN OUT AMD_S3_PARAMS MemContext; ///< Memory context block describes the data that platform needs to
- ///< save and restore for memory context restore feature to work.
- ///< It uses the subset of S3Save block to save/restore. Hence platform
- ///< may save only S3 block and uses it for both S3 resume and
- ///< memory context restore.
- ///< - If MemRestoreCtl is TRUE, platform needs to pass in MemContext
- ///< before AmdInitPost.
- ///< - If SaveMemContextCtl is TRUE, platform needs to save MemContext
- ///< right after AmdInitPost.
- ///<
-} MEM_PARAMETER_STRUCT;
-
-
-///
-/// Function definition.
-/// This data structure passes function pointers to the memory configuration code.
-/// The wrapper can use this structure with customized versions.
-///
-typedef struct _MEM_FUNCTION_STRUCT {
-
- // PUBLIC required Internal functions
-
- IN OUT BOOLEAN (*amdMemGetPsCfgU) ( VOID *pMemData); ///< Proc for Unbuffered DIMMs, platform specific
- IN OUT BOOLEAN (*amdMemGetPsCfgR) (VOID *pMemData); ///< Proc for Registered DIMMs, platform specific
-
- // PUBLIC optional functions
-
- IN OUT VOID (*amdMemEccInit) (VOID *pMemData); ///< NB proc for ECC feature
- IN OUT VOID (*amdMemChipSelectInterleaveInit) (VOID *pMemData); ///< NB proc for CS interleave feature
- IN OUT VOID (*amdMemDctInterleavingInit) (VOID *pMemData); ///< NB proc for Channel interleave feature
- IN OUT VOID (*amdMemMctInterleavingInit) (VOID *pMemData); ///< NB proc for Node interleave feature
- IN OUT VOID (*amdMemParallelTraining) (VOID *pMemData); ///< NB proc for parallel training feature
- IN OUT VOID (*amdMemEarlySampleSupport) (VOID *pMemData); ///< NB code for early sample support feature
- IN OUT VOID (*amdMemMultiPartInitSupport) (VOID *pMemData); ///< NB code for 'multi-part'
- IN OUT VOID (*amdMemOnlineSpareSupport) (VOID *pMemData); ///< NB code for On-Line Spare feature
- IN OUT VOID (*amdMemUDimmInit) (VOID *pMemData); ///< NB code for UDIMMs
- IN OUT VOID (*amdMemRDimmInit) (VOID *pMemData); ///< NB code for RDIMMs
- IN OUT VOID (*amdMemLrDimmInit) (VOID *pMemData); ///< NB code for LRDIMMs
-
- IN OUT UINT32 Reserved[100]; ///< Reserved for later function definition
-} MEM_FUNCTION_STRUCT;
-
-///
-/// Socket Structure
-///
-///
-typedef struct _MEM_SOCKET_STRUCT {
- OUT VOID *ChannelPtr[MAX_CHANNELS_PER_SOCKET]; ///< Pointers to each channels training data
-
- OUT VOID *TimingsPtr[MAX_CHANNELS_PER_SOCKET]; ///< Pointers to each channels timing data
-} MEM_SOCKET_STRUCT;
-
-///
-/// Contains all data relevant to Memory Initialization.
-///
-typedef struct _MEM_DATA_STRUCT {
- IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
-
- IN MEM_PARAMETER_STRUCT *ParameterListPtr; ///< List of input Parameters
-
- OUT MEM_FUNCTION_STRUCT FunctionList; ///< List of function Pointers
-
- IN OUT AGESA_STATUS (*GetPlatformCfg[MAX_PLATFORM_TYPES]) (struct _MEM_DATA_STRUCT *MemData, UINT8 SocketID, CH_DEF_STRUCT *CurrentChannel); ///< look-up platform info
-
- IN OUT BOOLEAN (*ErrorHandling)(struct _DIE_STRUCT *MCTPtr, UINT8 DCT, UINT16 ChipSelMask, AMD_CONFIG_PARAMS *StdHeader); ///< Error Handling
-
-
- OUT MEM_SOCKET_STRUCT SocketList[MAX_SOCKETS_SUPPORTED]; ///< Socket list for memory code.
- ///< SocketList is a shortcut for IBVs to retrieve training
- ///< and timing data for each channel indexed by socket/channel,
- ///< eliminating their need to parse die/dct/channel etc.
- ///< It contains pointers to the populated data structures for
- ///< each channel and skips the channel structures that are
- ///< unpopulated. In the case of channels sharing the same DCT,
- ///< the pTimings pointers will point to the same DCT Timing data.
-
- OUT DIE_STRUCT *DiesPerSystem; ///< Pointed to an array of DIE_STRUCTs
- OUT UINT8 DieCount; ///< Number of MCTs in the system.
-
- IN SPD_DEF_STRUCT *SpdDataStructure; ///< Pointer to SPD Data structure
-
- IN OUT struct _PLATFORM_CONFIGURATION *PlatFormConfig; ///< Platform profile/build option config structure
-
- IN OUT BOOLEAN IsFlowControlSupported; ///< Indicates if flow control is supported
-
- OUT UINT32 TscRate; ///< The rate at which the TSC increments in megahertz.
-
-} MEM_DATA_STRUCT;
-
-///
-/// Uma Structure
-///
-///
-typedef struct _UMA_INFO {
- OUT UINT64 UmaBase; ///< UmaBase[63:0] = Addr[63:0]
- OUT UINT32 UmaSize; ///< UmaSize[31:0] = Addr[31:0]
- OUT UINT32 UmaAttributes; ///< Indicate the attribute of Uma
- OUT UINT8 UmaMode; ///< Indicate the mode of Uma
- OUT UINT16 MemClock; ///< Indicate memory running speed in MHz
- OUT UINT8 Reserved[3]; ///< Reserved for future usage
-} UMA_INFO;
-
-// AGESA MEMORY ERRORS
-
-// AGESA_ALERT Memory Errors
-#define MEM_ALERT_USER_TMG_MODE_OVERRULED 0x04010000 ///< TIMING_MODE_SPECIFIC is requested but
- ///< cannot be applied to current configurations.
-#define MEM_ALERT_ORG_MISMATCH_DIMM 0x04010100 ///< DIMM organization miss-match
-#define MEM_ALERT_BK_INT_DIS 0x04010200 ///< Bank interleaving disable for internal issue
-
-// AGESA_ERROR Memory Errors
-#define MEM_ERROR_NO_DQS_POS_RD_WINDOW 0x04010300 ///< No DQS Position window for RD DQS
-#define MEM_ERROR_SMALL_DQS_POS_RD_WINDOW 0x04020300 ///< Small DQS Position window for RD DQS
-#define MEM_ERROR_NO_DQS_POS_WR_WINDOW 0x04030300 ///< No DQS Position window for WR DQS
-#define MEM_ERROR_SMALL_DQS_POS_WR_WINDOW 0x04040300 ///< Small DQS Position window for WR DQS
-#define MEM_ERROR_ECC_DIS 0x04010400 ///< ECC has been disabled as a result of an internal issue
-#define MEM_ERROR_DIMM_SPARING_NOT_ENABLED 0x04010500 ///< DIMM sparing has not been enabled for an internal issues
-#define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE 0x04050300 ///< Receive Enable value is too large
-#define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW 0x04060300 ///< There is no DQS receiver enable window
-#define MEM_ERROR_DRAM_ENABLED_TIME_OUT 0x04010600 ///< Time out when polling DramEnabled bit
-#define MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT 0x04010700 ///< Time out when polling DctAccessDone bit
-#define MEM_ERROR_SEND_CTRL_WORD_TIME_OUT 0x04010800 ///< Time out when polling SendCtrlWord bit
-#define MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT 0x04010900 ///< Time out when polling PrefDramTrainMode bit
-#define MEM_ERROR_ENTER_SELF_REF_TIME_OUT 0x04010A00 ///< Time out when polling EnterSelfRef bit
-#define MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT 0x04010B00 ///< Time out when polling FreqChgInProg bit
-#define MEM_ERROR_EXIT_SELF_REF_TIME_OUT 0x04020A00 ///< Time out when polling ExitSelfRef bit
-#define MEM_ERROR_SEND_MRS_CMD_TIME_OUT 0x04010C00 ///< Time out when polling SendMrsCmd bit
-#define MEM_ERROR_SEND_ZQ_CMD_TIME_OUT 0x04010D00 ///< Time out when polling SendZQCmd bit
-#define MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT 0x04010E00 ///< Time out when polling DctExtraAccessDone bit
-#define MEM_ERROR_MEM_CLR_BUSY_TIME_OUT 0x04010F00 ///< Time out when polling MemClrBusy bit
-#define MEM_ERROR_MEM_CLEARED_TIME_OUT 0x04020F00 ///< Time out when polling MemCleared bit
-#define MEM_ERROR_FLUSH_WR_TIME_OUT 0x04011000 ///< Time out when polling FlushWr bit
-#define MEM_ERROR_MAX_LAT_NO_WINDOW 0x04070300 ///< Fail to find pass during Max Rd Latency training
-#define MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL 0x04080300 ///< Fail to launch training code on an AP
-#define MEM_ERROR_PARALLEL_TRAINING_TIME_OUT 0x04090300 ///< Fail to finish parallel training
-#define MEM_ERROR_NO_ADDRESS_MAPPING 0x04011100 ///< No address mapping found for a dimm
-#define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT 0x040A0300 ///< There is no DQS receiver enable window and the value is equal to the largest value
-#define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE 0x040B0300 ///< Receive Enable value is too large and is 1 less than limit
-#define MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR 0x04011200 ///< SPD Checksum error for NV_SPDCHK_RESTRT
-#define MEM_ERROR_NO_CHIPSELECT 0x04011300 ///< No chipselects found
-#define MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM 0x04011500 ///< Unbuffered dimm is not supported at 333MHz
-#define MEM_ERROR_WL_PRE_OUT_OF_RANGE 0x040C0300 ///< Returned PRE value during write levelizzation was out of range
-
-// AGESA_WARNING Memory Errors
-#define MEM_WARNING_UNSUPPORTED_QRDIMM 0x04011600 ///< QR DIMMs detected but not supported
-#define MEM_WARNING_UNSUPPORTED_UDIMM 0x04021600 ///< U DIMMs detected but not supported
-#define MEM_WARNING_UNSUPPORTED_SODIMM 0x04031600 ///< SO-DIMMs detected but not supported
-#define MEM_WARNING_UNSUPPORTED_X4DIMM 0x04041600 ///< x4 DIMMs detected but not supported
-#define MEM_WARNING_UNSUPPORTED_RDIMM 0x04051600 ///< R DIMMs detected but not supported
-#define MEM_WARNING_UNSUPPORTED_LRDIMM 0x04061600 ///< LR DIMMs detected but not supported
-#define MEM_WARNING_EMP_NOT_SUPPORTED 0x04011700 ///< Processor is not capable for EMP
-#define MEM_WARNING_EMP_CONFLICT 0x04021700 ///< EMP cannot be enabled if channel interleaving,
-#define MEM_WARNING_EMP_NOT_ENABLED 0x04031700 ///< Memory size is not power of two.
-#define MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED 0x04011800 ///< Performance has been enabled, but battery life is preferred.
- ///< bank interleaving, or bank swizzle is enabled.
-#define MEM_WARNING_NO_SPDTRC_FOUND 0x04011900 ///< No Trc timing value found in SPD of a dimm.
-#define MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED 0x04012000 ///< Node Interleaveing Requested, but could not be enabled
-#define MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED 0x04012100 ///< Channel Interleaveing Requested, but could not be enabled
-#define MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED 0x04012200 ///< Bank Interleaveing Requested, but could not be enabled
-#define MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED 0x04012300 ///< Voltage 1.35 determined, but could not be supported
-
-// AGESA_FATAL Memory Errors
-#define MEM_ERROR_MINIMUM_MODE 0x04011A00 ///< Running in minimum mode
-#define MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM 0x04011B00 ///< DIMM modules are miss-matched
-#define MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM 0x04011C00 ///< No DIMMs have been found
-#define MEM_ERROR_MISMATCH_DIMM_CLOCKS 0x04011D00 ///< DIMM clocks miss-matched
-#define MEM_ERROR_NO_CYC_TIME 0x04011E00 ///< No cycle time found
-#define MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS 0x04011F00 ///< Heap allocation error with dynamic storing of trained timings
-#define MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs 0x04021F00 ///< Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT
-#define MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV 0x04031F00 ///< Heap allocation error with REMOTE_TRAINING_ENV
-#define MEM_ERROR_HEAP_ALLOCATE_FOR_SPD 0x04041F00 ///< Heap allocation error for SPD data
-#define MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA 0x04051F00 ///< Heap allocation error for RECEIVED_DATA during parallel training
-#define MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS 0x04061F00 ///< Heap allocation error for S3 "SPECIAL_CASE_REGISTER"
-#define MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA 0x04071F00 ///< Heap allocation error for Training Data
-#define MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK 0x04081F00 ///< Heap allocation error for DIMM Identify "MEM_NB_BLOCK
-#define MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM 0x04022300 ///< No Constructor for DIMM Identify
-
-// AGESA_CRITICAL Memory Errors
-#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3 0x04091F00 ///< Heap allocation error for DMI table for DDR3
-#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2 0x040A1F00 ///< Heap allocation error for DMI table for DDR2
-#define MEM_ERROR_UNSUPPORTED_DIMM_CONFIG 0x04011400 ///< Dimm population is not supported
-
-
-
-/*----------------------------------------------------------------------------
- *
- * END OF MEMORY-SPECIFIC DATA STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-
-/*----------------------------------------------------------------------------
- *
- * CPU RELATED DEFINITIONS
- *
- *----------------------------------------------------------------------------
- */
-
-// CPU Event definitions.
-
-// Defines used to filter CPU events based on functional blocks
-#define CPU_EVENT_PM_EVENT_MASK 0xFF00FF00
-#define CPU_EVENT_PM_EVENT_CLASS 0x08000400
-
-//================================================================
-// CPU General events
-// Heap allocation (AppFunction = 01h)
-#define CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT 0x08000100
-#define CPU_ERROR_HEAP_IS_ALREADY_INITIALIZED 0x08010100
-#define CPU_ERROR_HEAP_IS_FULL 0x08020100
-#define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED 0x08030100
-#define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT 0x08040100
-// BrandId (AppFunction = 02h)
-#define CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE 0x08000200
-// Micro code patch (AppFunction = 03h)
-#define CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED 0x08000300
-// Power management (AppFunction = 04h)
-#define CPU_EVENT_PM_PSTATE_OVERCURRENT 0x08000400
-#define CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT 0x08010400
-#define CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE 0x08020400
-#define CPU_ERROR_PM_NB_PSTATE_MISMATCH 0x08030400
-// BIST (AppFunction = 05h)
-#define CPU_EVENT_BIST_ERROR 0x08000500
-
-//=================================================================
-// CPU Feature events
-// Execution cache (AppFunction = 21h)
-// AGESA_CACHE_SIZE_REDUCED 2101
-// AGESA_CACHE_REGIONS_ACROSS_1MB 2102
-// AGESA_CACHE_REGIONS_ACROSS_4GB 2103
-// AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY 2104
-// AGESA_CACHE_START_ADDRESS_LESS_D0000 2105
-// AGESA_THREE_CACHE_REGIONS_ABOVE_1MB 2106
-// AGESA_DEALLOCATE_CACHE_REGIONS 2107
-#define CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR 0x08002100
-// Core Leveling (AppFunction = 22h)
-#define CPU_WARNING_ADJUSTED_LEVELING_MODE 0x08002200
-// HT Assist (AppFunction = 23h)
-#define CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG 0x08002300
-
-// CPU Build Configuration structures and definitions
-
-/// Build Configuration structure for BLDCFG_AP_MTRR_SETTINGS
-typedef struct {
- IN UINT32 MsrAddr; ///< Fixed-Sized MTRR address
- IN UINT64 MsrData; ///< MTRR Settings
-} AP_MTRR_SETTINGS;
-
-#define AMD_AP_MTRR_FIX64k_00000 0x00000250
-#define AMD_AP_MTRR_FIX16k_80000 0x00000258
-#define AMD_AP_MTRR_FIX16k_A0000 0x00000259
-#define AMD_AP_MTRR_FIX4k_C0000 0x00000268
-#define AMD_AP_MTRR_FIX4k_C8000 0x00000269
-#define AMD_AP_MTRR_FIX4k_D0000 0x0000026A
-#define AMD_AP_MTRR_FIX4k_D8000 0x0000026B
-#define AMD_AP_MTRR_FIX4k_E0000 0x0000026C
-#define AMD_AP_MTRR_FIX4k_E8000 0x0000026D
-#define AMD_AP_MTRR_FIX4k_F0000 0x0000026E
-#define AMD_AP_MTRR_FIX4k_F8000 0x0000026F
-#define CPU_LIST_TERMINAL 0xFFFFFFFF
-
-/************************************************************************
- *
- * AGESA interface Call-Out function parameter structures
- *
- ***********************************************************************/
-
-/// Parameters structure for interface call-out AgesaAllocateBuffer
-typedef struct {
- IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
- IN OUT UINT32 BufferLength; ///< Size of buffer to allocate
- IN UINT32 BufferHandle; ///< Identifier or name for the buffer
- OUT VOID *BufferPointer; ///< location of the created buffer
-} AGESA_BUFFER_PARAMS;
-
-/// Parameters structure for interface call-out AgesaRunCodeOnAp
-typedef struct {
- IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
- IN UINT32 FunctionNumber; ///< Index of the procedure to execute
- IN VOID *RelatedDataBlock; ///< Location of data structure the procedure will use
- IN UINT32 RelatedBlockLength; ///< Size of the related data block
-} AP_EXE_PARAMS;
-
-/// Parameters structure for the interface call-out AgesaReadSpd & AgesaReadSpdRecovery
-typedef struct {
- IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
- IN UINT8 SocketId; ///< Address of SPD - socket ID
- IN UINT8 MemChannelId; ///< Address of SPD - memory channel ID
- IN UINT8 DimmId; ///< Address of SPD - DIMM ID
- IN OUT UINT8 *Buffer; ///< Location where to place the SPD content
- IN OUT MEM_DATA_STRUCT *MemData; ///< Location of the MemData structure, for reference
-} AGESA_READ_SPD_PARAMS;
-
-/// Buffer Handles
-typedef enum {
- AMD_DMI_INFO_BUFFER_HANDLE = 0x000D000, ///< Assign 0x000D000 buffer handle to DMI function
- AMD_PSTATE_DATA_BUFFER_HANDLE, ///< Assign 0x000D001 buffer handle to Pstate data
- AMD_PSTATE_ACPI_BUFFER_HANDLE, ///< Assign 0x000D002 buffer handle to Pstate table
- AMD_BRAND_ID_BUFFER_HANDLE, ///< Assign 0x000D003 buffer handle to Brand ID
- AMD_ACPI_SLIT_BUFFER_HANDLE, ///< Assign 0x000D004 buffer handle to SLIT function
- AMD_SRAT_INFO_BUFFER_HANDLE, ///< Assign 0x000D005 buffer handle to SRAT function
- AMD_WHEA_BUFFER_HANDLE, ///< Assign 0x000D006 buffer handle to WHEA function
- AMD_S3_INFO_BUFFER_HANDLE, ///< Assign 0x000D007 buffer handle to S3 function
- AMD_S3_NB_INFO_BUFFER_HANDLE, ///< Assign 0x000D008 buffer handle to S3 NB device info
- AMD_ACPI_ALIB_BUFFER_HANDLE ///< Assign 0x000D009 buffer handle to ALIB SSDT table
-} AMD_BUFFER_HANDLE;
-/************************************************************************
- *
- * AGESA interface Call-Out function prototypes
- *
- ***********************************************************************/
-
-VOID
-AgesaDoReset (
- IN UINTN ResetType,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-AgesaAllocateBuffer (
- IN UINTN FcnData,
- IN OUT AGESA_BUFFER_PARAMS *AllocParams
- );
-
-AGESA_STATUS
-AgesaDeallocateBuffer (
- IN UINTN FcnData,
- IN OUT AGESA_BUFFER_PARAMS *DeallocParams
- );
-
-AGESA_STATUS
-AgesaLocateBuffer (
- IN UINTN FcnData,
- IN OUT AGESA_BUFFER_PARAMS *LocateParams
- );
-
-AGESA_STATUS
-AgesaReadSpd (
- IN UINTN FcnData,
- IN OUT AGESA_READ_SPD_PARAMS *ReadSpd
- );
-
-AGESA_STATUS
-AgesaReadSpdRecovery (
- IN UINTN FcnData,
- IN OUT AGESA_READ_SPD_PARAMS *ReadSpd
- );
-
-AGESA_STATUS
-AgesaHookBeforeDramInitRecovery (
- IN UINTN FcnData,
- IN OUT MEM_DATA_STRUCT *MemData
- );
-
-AGESA_STATUS
-AgesaRunFcnOnAp (
- IN UINTN ApicIdOfCore,
- IN AP_EXE_PARAMS *LaunchApParams
- );
-
-AGESA_STATUS
-AgesaHookBeforeDramInit (
- IN UINTN FcnData,
- IN OUT MEM_DATA_STRUCT *MemData
- );
-
-AGESA_STATUS
-AgesaHookBeforeDQSTraining (
- IN UINTN FcnData,
- IN OUT MEM_DATA_STRUCT *MemData
- );
-
-AGESA_STATUS
-AgesaHookBeforeExitSelfRefresh (
- IN UINTN FcnData,
- IN OUT MEM_DATA_STRUCT *MemData
- );
-
-AGESA_STATUS
-AgesaPcieSlotResetControl (
- IN UINTN FcnData,
- IN PCIe_SLOT_RESET_INFO *ResetInfo
- );
-
-/************************************************************************
- *
- * AGESA interface structure definition and function prototypes
- *
- ***********************************************************************/
-
-/**********************************************************************
- * Platform Configuration: The parameters in boot branch function
- **********************************************************************/
-
-/// The possible platform control flow settings.
-typedef enum {
- Nfcm, ///< Normal Flow Control Mode.
- UmaDr, ///< UMA using Display Refresh flow control.
- UmaIfcm, ///< UMA using Isochronous Flow Control.
- Ifcm, ///< Isochronous Flow Control Mode (other than for UMA).
- Iommu, ///< An IOMMU is in use in the system.
- MaxControlFlow ///< Not a control flow mode, use for limit checking.
-} PLATFORM_CONTROL_FLOW;
-
-/// Platform Deemphasis Levels.
-///
-/// The deemphasis level is set for the receiver, based on link characterization. The DCV level is
-/// set based on the level of the far transmitter.
-typedef enum {
- DeemphasisLevelNone, ///< No Deemphasis.
- DeemphasisLevelMinus3, ///< Minus 3 db deemphasis.
- DeemphasisLevelMinus6, ///< Minus 6 db deemphasis.
- DeemphasisLevelMinus8, ///< Minus 8 db deemphasis.
- DeemphasisLevelMinus11, ///< Minus 11 db deemphasis.
- DeemphasisLevelMinus11pre8, ///< Minus 11, Minus 8 precursor db deemphasis.
- DcvLevelNone = 16, ///< No DCV Deemphasis.
- DcvLevelMinus2, ///< Minus 2 db DCV deemphasis.
- DcvLevelMinus3, ///< Minus 3 db DCV deemphasis.
- DcvLevelMinus5, ///< Minus 5 db DCV deemphasis.
- DcvLevelMinus6, ///< Minus 6 db DCV deemphasis.
- DcvLevelMinus7, ///< Minus 7 db DCV deemphasis.
- DcvLevelMinus8, ///< Minus 8 db DCV deemphasis.
- DcvLevelMinus9, ///< Minus 9 db DCV deemphasis.
- DcvLevelMinus11, ///< Minus 11 db DCV deemphasis.
- MaxPlatformDeemphasisLevel ///< Not a deemphasis level, use for limit checking.
-} PLATFORM_DEEMPHASIS_LEVEL;
-
-/// Provide Deemphasis Levels for HT Links.
-///
-/// For each CPU to CPU or CPU to IO device HT link, the list of Deemphasis Levels will
-/// be checked for a match. The item matches for a Socket, Link if the link frequency is
-/// is in the inclusive range HighFreq:LoFreq.
-/// AGESA does not set deemphasis in IO devices, only in processors.
-
-typedef struct {
- // Match fields
- IN UINT8 Socket; ///< One Socket on which this Link is located
- IN UINT8 Link; ///< The Link on this Processor.
- IN UINT8 LoFreq; ///< If the link is set to this frequency or greater, apply these levels, and
- IN UINT8 HighFreq; ///< If the link is set to this frequency or less, apply these levels.
- // Value fields
- IN PLATFORM_DEEMPHASIS_LEVEL ReceiverDeemphasis; ///< The deemphasis level for this link
- IN PLATFORM_DEEMPHASIS_LEVEL DcvDeemphasis; ///< The DCV, or far transmitter deemphasis level.
-} CPU_HT_DEEMPHASIS_LEVEL;
-
-/// The possible platform power policy settings.
-typedef enum {
- Performance, ///< Optimize for performance.
- BatteryLife, ///< Optimize for battery life.
- MaxPowerPolicy ///< Not a power policy mode, use for limit checking.
-} PLATFORM_POWER_POLICY;
-
-/// Platform performance settings for optimized settings.
-/// Several configuration settings for the processor depend upon other parts and
-/// general designer choices for the system. The determination of these data points
-/// is not standard for all platforms, so the host environment needs to provide these
-/// to specify how the system is to be configured.
-typedef struct {
- IN PLATFORM_CONTROL_FLOW PlatformControlFlowMode; ///< The platform's control flow mode for optimum platform performance.
- ///< @BldCfgItem{BLDCFG_PLATFORM_CONTROL_FLOW_MODE}
- IN BOOLEAN UseHtAssist; ///< HyperTransport link traffic optimization.
- ///< @BldCfgItem{BLDCFG_USE_HT_ASSIST}
- IN BOOLEAN UseAtmMode; ///< HyperTransport link traffic optimization.
- ///< @BldCfgItem{BLDCFG_USE_ATM_MODE}
- IN BOOLEAN Use32ByteRefresh; ///< Display Refresh traffic generates 32 byte requests.
- ///< @BldCfgItem{BLDCFG_USE_32_BYTE_REFRESH}
- IN BOOLEAN UseVariableMctIsocPriority; ///< The Memory controller will be set to Variable Isoc Priority.
- ///< @BldCfgItem{BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY}
- IN PLATFORM_POWER_POLICY PlatformPowerPolicy; ///< The platform's desired power policy
- ///< @BldCfgItem{BLDCFG_PLATFORM_POWER_POLICY_MODE}
-} PERFORMANCE_PROFILE;
-
-/// Platform settings that describe the voltage regulator modules of the system.
-/// Many power management settings are dependent upon the characteristics of the
-/// on-board voltage regulator module (VRM). The host environment needs to provide
-/// these to specify how the system is to be configured.
-typedef struct {
- IN UINT32 CurrentLimit; ///< Vrm Current Limit.
- ///< @BldCfgItem{BLDCFG_VRM_CURRENT_LIMIT}
- ///< @BldCfgItem{BLDCFG_VRM_NB_CURRENT_LIMIT}
- IN UINT32 LowPowerThreshold; ///< Vrm Low Power Threshold.
- ///< @BldCfgItem{BLDCFG_VRM_LOW_POWER_THRESHOLD}
- ///< @BldCfgItem{BLDCFG_VRM_NB_LOW_POWER_THRESHOLD}
- IN UINT32 SlewRate; ///< Vrm Slew Rate.
- ///< @BldCfgItem{BLDCFG_VRM_SLEW_RATE}
- ///< @BldCfgItem{BLDCFG_VRM_NB_SLEW_RATE}
- IN UINT32 AdditionalDelay; ///< Vrm Additional Delay.
- ///< @BldCfgItem{BLDCFG_VRM_ADDITIONAL_DELAY}
- ///< @BldCfgItem{BLDCFG_VRM_NB_ADDITIONAL_DELAY}
- IN BOOLEAN HiSpeedEnable; ///< Select high speed VRM.
- ///< @BldCfgItem{BLDCFG_VRM_HIGH_SPEED_ENABLE}
- ///< @BldCfgItem{BLDCFG_VRM_NB_HIGH_SPEED_ENABLE}
- IN UINT32 InrushCurrentLimit; ///< Vrm Inrush Current Limit.
- ///< @BldCfgItem{BLDCFG_VRM_INRUSH_CURRENT_LIMIT}
- ///< @BldCfgItem{BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT}
-} PLATFORM_VRM_CONFIGURATION;
-
-/// The VRM types to characterize.
-typedef enum {
- CoreVrm, ///< VDD plane.
- NbVrm, ///< VDDNB plane.
- MaxVrmType ///< Not a valid VRM type, use for limit checking.
-} PLATFORM_VRM_TYPE;
-
-
-/// Build Option/Configuration Boolean Structure.
-typedef struct {
- IN AMD_CODE_HEADER VersionString; ///< AMD embedded code version string
-
- //Build Option Area
- IN BOOLEAN OptionUDimms; ///< @ref BLDOPT_REMOVE_UDIMMS_SUPPORT "BLDOPT_REMOVE_UDIMMS_SUPPORT"
- IN BOOLEAN OptionRDimms; ///< @ref BLDOPT_REMOVE_RDIMMS_SUPPORT "BLDOPT_REMOVE_RDIMMS_SUPPORT"
- IN BOOLEAN OptionLrDimms; ///< @ref BLDOPT_REMOVE_LRDIMMS_SUPPORT "BLDOPT_REMOVE_LRDIMMS_SUPPORT"
- IN BOOLEAN OptionEcc; ///< @ref BLDOPT_REMOVE_ECC_SUPPORT "BLDOPT_REMOVE_ECC_SUPPORT"
- IN BOOLEAN OptionBankInterleave; ///< @ref BLDOPT_REMOVE_BANK_INTERLEAVE "BLDOPT_REMOVE_BANK_INTERLEAVE"
- IN BOOLEAN OptionDctInterleave; ///< @ref BLDOPT_REMOVE_DCT_INTERLEAVE "BLDOPT_REMOVE_DCT_INTERLEAVE"
- IN BOOLEAN OptionNodeInterleave; ///< @ref BLDOPT_REMOVE_NODE_INTERLEAVE "BLDOPT_REMOVE_NODE_INTERLEAVE"
- IN BOOLEAN OptionParallelTraining; ///< @ref BLDOPT_REMOVE_PARALLEL_TRAINING "BLDOPT_REMOVE_PARALLEL_TRAINING"
- IN BOOLEAN OptionOnlineSpare; ///< @ref BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT "BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT"
- IN BOOLEAN OptionMemRestore; ///< @ref BLDOPT_REMOVE_MEM_RESTORE_SUPPORT "BLDOPT_REMOVE_MEM_RESTORE_SUPPORT"
- IN BOOLEAN OptionMultisocket; ///< @ref BLDOPT_REMOVE_MULTISOCKET_SUPPORT "BLDOPT_REMOVE_MULTISOCKET_SUPPORT"
- IN BOOLEAN OptionAcpiPstates; ///< @ref BLDOPT_REMOVE_ACPI_PSTATES "BLDOPT_REMOVE_ACPI_PSTATES"
- IN BOOLEAN OptionSrat; ///< @ref BLDOPT_REMOVE_SRAT "BLDOPT_REMOVE_SRAT"
- IN BOOLEAN OptionSlit; ///< @ref BLDOPT_REMOVE_SLIT "BLDOPT_REMOVE_SLIT"
- IN BOOLEAN OptionWhea; ///< @ref BLDOPT_REMOVE_WHEA "BLDOPT_REMOVE_WHEA"
- IN BOOLEAN OptionDmi; ///< @ref BLDOPT_REMOVE_DMI "BLDOPT_REMOVE_DMI"
- IN BOOLEAN OptionEarlySamples; ///< @ref BLDOPT_REMOVE_EARLY_SAMPLES "BLDOPT_REMOVE_EARLY_SAMPLES"
- IN BOOLEAN OptionAddrToCsTranslator; ///< ADDR_TO_CS_TRANSLATOR
-
- //Build Configuration Area
- IN UINT64 CfgPciMmioAddress; ///< Pci Mmio Base Address to use for PCI Config accesses.
- ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCI_MMIO_BASE}
- IN UINT32 CfgPciMmioSize; ///< Pci Mmio region Size.
- ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCI_MMIO_SIZE}
- IN PLATFORM_VRM_CONFIGURATION CfgPlatVrmCfg[MaxVrmType]; ///< Several configuration settings for the voltage regulator modules.
- IN UINT32 CfgPlatNumIoApics; ///< The number of IO APICS for the platform.
- IN UINT32 CfgMemInitPstate; ///< Memory Init Pstate.
- IN PLATFORM_C1E_MODES CfgPlatformC1eMode; ///< Select the C1e Mode that will used.
- IN UINT32 CfgPlatformC1eOpData; ///< An IO port or additional C1e setup data, depends on C1e mode.
- IN UINT32 CfgPlatformC1eOpData1; ///< An IO port or additional C1e setup data, depends on C1e mode.
- IN UINT32 CfgPlatformC1eOpData2; ///< An IO port or additional C1e setup data, depends on C1e mode.
- IN PLATFORM_CSTATE_MODES CfgPlatformCStateMode; ///< Select the C-State Mode that will used.
- IN UINT32 CfgPlatformCStateOpData; ///< An IO port or additional C-State setup data, depends on C-State mode.
- IN UINT16 CfgPlatformCStateIoBaseAddress; ///< Specifies I/O ports that can be used to allow CPU to enter CStates
- IN PLATFORM_CPB_MODES CfgPlatformCpbMode; ///< Enable or disable core performance boost
- IN UINT32 CfgCoreLevelingMode; ///< Apply any downcoring or core count leveling as specified.
- IN PERFORMANCE_PROFILE CfgPerformanceProfile; ///< The platform's control flow mode and platform performance settings.
- IN CPU_HT_DEEMPHASIS_LEVEL *CfgPlatformDeemphasisList; ///< Deemphasis levels for the platform's HT links.
-
- IN UINT32 CfgAmdPlatformType; ///< Designate the platform as a Server, Desktop, or Mobile.
- IN UINT32 CfgAmdPstateCapValue; ///< Amd pstate ceiling enabling deck
-
- IN MEMORY_BUS_SPEED CfgMemoryBusFrequencyLimit; ///< Memory Bus Frequency Limit.
- ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT}
- IN BOOLEAN CfgMemoryModeUnganged; ///< Memory Mode Unganged.
- ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_MODE_UNGANGED}
- IN BOOLEAN CfgMemoryQuadRankCapable; ///< Memory Quad Rank Capable.
- ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_QUAD_RANK_CAPABLE}
- IN QUANDRANK_TYPE CfgMemoryQuadrankType; ///< Memory Quadrank Type.
- ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_QUADRANK_TYPE}
- IN BOOLEAN CfgMemoryRDimmCapable; ///< Memory RDIMM Capable.
- IN BOOLEAN CfgMemoryLRDimmCapable; ///< Memory LRDIMM Capable.
- IN BOOLEAN CfgMemoryUDimmCapable; ///< Memory UDIMM Capable.
- IN BOOLEAN CfgMemorySODimmCapable; ///< Memory SODimm Capable.
- ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_SODIMM_CAPABLE}
- IN BOOLEAN CfgMemoryEnableBankInterleaving; ///< Memory Enable Bank Interleaving.
- IN BOOLEAN CfgMemoryEnableNodeInterleaving; ///< Memory Enable Node Interleaving.
- IN BOOLEAN CfgMemoryChannelInterleaving; ///< Memory Channel Interleaving.
- IN BOOLEAN CfgMemoryPowerDown; ///< Memory Power Down.
- IN POWER_DOWN_MODE CfgPowerDownMode; ///< Power Down Mode.
- IN BOOLEAN CfgOnlineSpare; ///< Online Spare.
- IN BOOLEAN CfgMemoryParityEnable; ///< Memory Parity Enable.
- IN BOOLEAN CfgBankSwizzle; ///< Bank Swizzle.
- IN USER_MEMORY_TIMING_MODE CfgTimingModeSelect; ///< Timing Mode Select.
- IN MEMORY_BUS_SPEED CfgMemoryClockSelect; ///< Memory Clock Select.
- IN BOOLEAN CfgDqsTrainingControl; ///< Dqs Training Control.
- ///< Build-time customizable only - @BldCfgItem{BLDCFG_DQS_TRAINING_CONTROL}
- IN BOOLEAN CfgIgnoreSpdChecksum; ///< Ignore Spd Checksum.
- ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGNORE_SPD_CHECKSUM}
- IN BOOLEAN CfgUseBurstMode; ///< Use Burst Mode.
- ///< Build-time customizable only - @BldCfgItem{BLDCFG_USE_BURST_MODE}
- IN BOOLEAN CfgMemoryAllClocksOn; ///< Memory All Clocks On.
- ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_ALL_CLOCKS_ON}
- IN BOOLEAN CfgEnableEccFeature; ///< Enable ECC Feature.
- IN BOOLEAN CfgEccRedirection; ///< ECC Redirection.
- ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_REDIRECTION}
- IN UINT16 CfgScrubDramRate; ///< Scrub Dram Rate.
- ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DRAM_RATE}
- IN UINT16 CfgScrubL2Rate; ///< Scrub L2Rate.
- ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L2_RATE}
- IN UINT16 CfgScrubL3Rate; ///< Scrub L3Rate.
- ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L3_RATE}
- IN UINT16 CfgScrubIcRate; ///< Scrub Ic Rate.
- ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_IC_RATE}
- IN UINT16 CfgScrubDcRate; ///< Scrub Dc Rate.
- ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DC_RATE}
- IN BOOLEAN CfgEccSyncFlood; ///< ECC Sync Flood.
- ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYNC_FLOOD}
- IN UINT16 CfgEccSymbolSize; ///< ECC Symbol Size.
- ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYMBOL_SIZE}
- IN UINT64 CfgHeapDramAddress; ///< Heap contents will be temporarily stored in this address during the transition.
- ///< Build-time customizable only - @BldCfgItem{BLDCFG_HEAP_DRAM_ADDRESS}
- IN BOOLEAN CfgNodeMem1GBAlign; ///< Node Mem 1GB boundary Alignment
- IN BOOLEAN CfgS3LateRestore; ///< S3 Late Restore
- IN BOOLEAN CfgAcpiPstateIndependent; ///< PSD method dependent/Independent
- IN AP_MTRR_SETTINGS *CfgApMtrrSettingsList; ///< The AP's MTRR settings before final halt
- ///< Build-time customizable only - @BldCfgItem{BLDCFG_AP_MTRR_SETTINGS_LIST}
- IN UMA_MODE CfgUmaMode; ///< Uma Mode
- IN UINT32 CfgUmaSize; ///< Uma Size [31:0]=Addr[47:16]
- IN BOOLEAN CfgUmaAbove4G; ///< Uma Above 4G Support
- IN UMA_ALIGNMENT CfgUmaAlignment; ///< Uma alignment
- IN BOOLEAN CfgProcessorScopeInSb; ///< ACPI Processor Object in \\_SB scope
- IN CHAR8 CfgProcessorScopeName0; ///< OEM specific 1st character of processor scope name.
- IN CHAR8 CfgProcessorScopeName1; ///< OEM specific 2nd character of processor scope name.
- IN UINT8 CfgGnbHdAudio; ///< GNB HD Audio
- IN UINT8 CfgAbmSupport; ///< Abm Support
- IN UINT8 CfgDynamicRefreshRate; ///< DRR Dynamic Refresh Rate
- IN UINT16 CfgLcdBackLightControl; ///< LCD Backlight Control
- IN UINT8 CfgGnb3dStereoPinIndex; ///< 3D Stereo Pin ID.
- IN UINT32 CfgTempPcieMmioBaseAddress; ///< Temp pcie MMIO base Address
- ///< Build-time customizable only - @BldCfgItem{BLDCFG_TEMP_PCIE_MMIO_BASE_ADDRESS}
- IN UINT32 CfgGnbIGPUSSID; ///< Gnb internal GPU SSID
- ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGPU_SUBSYSTEM_ID}
- IN UINT32 CfgGnbHDAudioSSID; ///< Gnb HD Audio SSID
- ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID}
- IN UINT32 CfgGnbPcieSSID; ///< Gnb PCIe SSID
- ///< Build-time customizable only - @BldCfgItem{BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID}
- IN UINT16 CfgLvdsSpreadSpectrum; ///< Lvds Spread Spectrum
- ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM}
- IN UINT16 CfgLvdsSpreadSpectrumRate; ///< Lvds Spread Spectrum Rate
- ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE}
- IN BOOLEAN Reserved; ///< reserved...
-} BUILD_OPT_CFG;
-
-/// A structure containing platform specific operational characteristics. This
-/// structure is initially populated by the initializer with a copy of the same
-/// structure that was created at build time using the build configuration controls.
-typedef struct _PLATFORM_CONFIGURATION {
- IN PERFORMANCE_PROFILE PlatformProfile; ///< Several configuration settings for the processor.
- IN CPU_HT_DEEMPHASIS_LEVEL *PlatformDeemphasisList; ///< Deemphasis levels for the platform's HT links.
- ///< @BldCfgItem{BLDCFG_PLATFORM_DEEMPHASIS_LIST}.
- ///< @n @e Examples: See @ref DeemphasisExamples "Deemphasis List Examples".
- IN UINT8 CoreLevelingMode; ///< Indicates how to balance the number of cores per processor.
- ///< @BldCfgItem{BLDCFG_CORE_LEVELING_MODE}
- IN PLATFORM_C1E_MODES C1eMode; ///< Specifies the method of C1e enablement - Disabled, HW, or message based.
- ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_MODE}
- IN UINT32 C1ePlatformData; ///< If C1eMode is HW, specifies the P_LVL3 I/O port of the platform.
- ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA}
- IN UINT32 C1ePlatformData1; ///< If C1eMode is SW, specifies the address of chipset's SMI command port.
- ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA1}
- IN UINT32 C1ePlatformData2; ///< If C1eMode is SW, specifies the unique number used by the SMI handler to identify SMI source.
- ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA2}
- IN PLATFORM_CSTATE_MODES CStateMode; ///< Specifies the method of C-State enablement - Disabled, or C6.
- ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_MODE}
- IN UINT32 CStatePlatformData; ///< This element specifies some pertinent data needed for the operation of the Cstate feature
- ///< If CStateMode is CStateModeC6, this item is reserved
- ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_OPDATA}
- IN UINT16 CStateIoBaseAddress; ///< This item specifies a free block of 8 consecutive bytes of I/O ports that
- ///< can be used to allow the CPU to enter Cstates.
- ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS}
- IN PLATFORM_CPB_MODES CpbMode; ///< Specifies the method of core performance boost enablement - Disabled, or Auto.
- ///< @BldCfgItem{BLDCFG_PLATFORM_CPB_MODE}
- IN BOOLEAN UserOptionDmi; ///< When set to TRUE, the DMI data table is generated.
- IN BOOLEAN UserOptionPState; ///< When set to TRUE, the PState data tables are generated.
- IN BOOLEAN UserOptionSrat; ///< When set to TRUE, the SRAT data table is generated.
- IN BOOLEAN UserOptionSlit; ///< When set to TRUE, the SLIT data table is generated.
- IN BOOLEAN UserOptionWhea; ///< When set to TRUE, the WHEA data table is generated.
- IN UINT32 PowerCeiling; ///< P-State Ceiling Enabling Deck - Max power milli-watts.
- IN BOOLEAN ForcePstateIndependent; ///< P-State _PSD independence or dependence.
- ///< @BldCfgItem{BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT}
- IN UINT32 NumberOfIoApics; ///< Number of I/O APICs in the system
- ///< @BldCfgItem{BLDCFG_PLATFORM_NUM_IO_APICS}
- IN PLATFORM_VRM_CONFIGURATION VrmProperties[MaxVrmType]; ///< Several configuration settings for the voltage regulator modules.
- IN BOOLEAN ProcessorScopeInSb; ///< ACPI Processor Object in \\_SB scope
- ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_IN_SB}
- IN CHAR8 ProcessorScopeName0; ///< OEM specific 1st character of processor scope name.
- ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_NAME0}
- IN CHAR8 ProcessorScopeName1; ///< OEM specific 2nd character of processor scope name.
- ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_NAME1}
- IN UINT8 GnbHdAudio; ///< Control GFX HD Audio controller(Used for HDMI and DP display output),
- ///< essentially it enables function 1 of graphics device.
- ///< @li 0 = HD Audio disable
- ///< @li 1 = HD Audio enable
- ///< @BldCfgItem{BLDCFG_CFG_GNB_HD_AUDIO}
- IN UINT8 AbmSupport; ///< Automatic adjust LVDS/eDP Back light level support.It is
- ///< characteristic specific to display panel which used by platform design.
- ///< @li 0 = ABM support disabled
- ///< @li 1 = ABM support enabled
- ///< @BldCfgItem{BLDCFG_CFG_ABM_SUPPORT}
- IN UINT8 DynamicRefreshRate; ///< Adjust refresh rate on LVDS/eDP.
- ///< @BldCfgItem{BLDCFG_CFG_DYNAMIC_REFRESH_RATE}
- IN UINT16 LcdBackLightControl; ///< The PWM frequency to LCD backlight control.
- ///< If equal to 0 backlight not controlled by iGPU
- ///< @BldCfgItem{BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL}
-} PLATFORM_CONFIGURATION;
-
-
-/**********************************************************************
- * Structures for: AmdInitLate
- **********************************************************************/
-#define PROC_VERSION_LENGTH 48
-#define MAX_DIMMS_PER_SOCKET 16
-
-/* Interface Parameter Structures */
-/// DMI Type4 - Processor ID
-typedef struct {
- OUT UINT32 ProcIdLsd; ///< Lower half of 64b ID
- OUT UINT32 ProcIdMsd; ///< Upper half of 64b ID
-} TYPE4_PROC_ID;
-
-/// DMI Type 4 - Processor information
-typedef struct {
- OUT UINT8 T4ProcType; ///< CPU Type
- OUT UINT8 T4ProcFamily; ///< Family 1
- OUT TYPE4_PROC_ID T4ProcId; ///< Id
- OUT UINT8 T4Voltage; ///< Voltage
- OUT UINT16 T4ExternalClock; ///< External clock
- OUT UINT16 T4MaxSpeed; ///< Max speed
- OUT UINT16 T4CurrentSpeed; ///< Current speed
- OUT UINT8 T4Status; ///< Status
- OUT UINT8 T4ProcUpgrade; ///< Up grade
- OUT UINT8 T4CoreCount; ///< Core count
- OUT UINT8 T4CoreEnabled; ///< Core Enable
- OUT UINT8 T4ThreadCount; ///< Thread count
- OUT UINT16 T4ProcCharacteristics; ///< Characteristics
- OUT UINT16 T4ProcFamily2; ///< Family 2
- OUT CHAR8 T4ProcVersion[PROC_VERSION_LENGTH]; ///< Cpu version
-} TYPE4_DMI_INFO;
-
-/// DMI Type 7 - Cache information
-typedef struct _TYPE7_DMI_INFO {
- OUT UINT16 T7CacheCfg; ///< Cache cfg
- OUT UINT16 T7MaxCacheSize; ///< Max size
- OUT UINT16 T7InstallSize; ///< Install size
- OUT UINT16 T7SupportedSramType; ///< Supported Sram Type
- OUT UINT16 T7CurrentSramType; ///< Current type
- OUT UINT8 T7CacheSpeed; ///< Speed
- OUT UINT8 T7ErrorCorrectionType; ///< ECC type
- OUT UINT8 T7SystemCacheType; ///< Cache type
- OUT UINT8 T7Associativity; ///< Associativity
-} TYPE7_DMI_INFO;
-
-/// DMI Type 16 offset 04h - Location
-typedef enum {
- OtherLocation = 0x01, ///< Assign 01 to Other
- UnknownLocation, ///< Assign 02 to Unknown
- SystemboardOrMotherboard, ///< Assign 03 to systemboard or motherboard
- IsaAddonCard, ///< Assign 04 to ISA add-on card
- EisaAddonCard, ///< Assign 05 to EISA add-on card
- PciAddonCard, ///< Assign 06 to PCI add-on card
- McaAddonCard, ///< Assign 07 to MCA add-on card
- PcmciaAddonCard, ///< Assign 08 to PCMCIA add-on card
- ProprietaryAddonCard, ///< Assign 09 to proprietary add-on card
- NuBus, ///< Assign 0A to NuBus
- Pc98C20AddonCard, ///< Assign 0A0 to PC-98/C20 add-on card
- Pc98C24AddonCard, ///< Assign 0A1 to PC-98/C24 add-on card
- Pc98EAddoncard, ///< Assign 0A2 to PC-98/E add-on card
- Pc98LocalBusAddonCard ///< Assign 0A3 to PC-98/Local bus add-on card
-} DMI_T16_LOCATION;
-
-/// DMI Type 16 offset 05h - Memory Error Correction
-typedef enum {
- OtherUse = 0x01, ///< Assign 01 to Other
- UnknownUse, ///< Assign 02 to Unknown
- SystemMemory, ///< Assign 03 to system memory
- VideoMemory, ///< Assign 04 to video memory
- FlashMemory, ///< Assign 05 to flash memory
- NonvolatileRam, ///< Assign 06 to non-volatile RAM
- CacheMemory ///< Assign 07 to cache memory
-} DMI_T16_USE;
-
-/// DMI Type 16 offset 07h - Maximum Capacity
-typedef enum {
- Dmi16OtherErrCorrection = 0x01, ///< Assign 01 to Other
- Dmi16UnknownErrCorrection, ///< Assign 02 to Unknown
- Dmi16NoneErrCorrection, ///< Assign 03 to None
- Dmi16Parity, ///< Assign 04 to parity
- Dmi16SingleBitEcc, ///< Assign 05 to Single-bit ECC
- Dmi16MultiBitEcc, ///< Assign 06 to Multi-bit ECC
- Dmi16Crc ///< Assign 07 to CRC
-} DMI_T16_ERROR_CORRECTION;
-
-/// DMI Type 16 - Physical Memory Array
-typedef struct {
- OUT DMI_T16_LOCATION Location; ///< The physical location of the Memory Array,
- ///< whether on the system board or an add-in board.
- OUT DMI_T16_USE Use; ///< Identifies the function for which the array
- ///< is used.
- OUT DMI_T16_ERROR_CORRECTION MemoryErrorCorrection; ///< The primary hardware error correction or
- ///< detection method supported by this memory array.
- OUT UINT32 MaximumCapacity; ///< The maximum memory capacity, in kilobytes,
- ///< for the array.
- OUT UINT16 NumberOfMemoryDevices; ///< The number of slots or sockets available
- ///< for memory devices in this array.
-} TYPE16_DMI_INFO;
-
-/// DMI Type 17 offset 0Eh - Form Factor
-typedef enum {
- OtherFormFactor = 0x01, ///< Assign 01 to Other
- UnknowFormFactor, ///< Assign 02 to Unknown
- SimmFormFactor, ///< Assign 03 to SIMM
- SipFormFactor, ///< Assign 04 to SIP
- ChipFormFactor, ///< Assign 05 to Chip
- DipFormFactor, ///< Assign 06 to DIP
- ZipFormFactor, ///< Assign 07 to ZIP
- ProprietaryCardFormFactor, ///< Assign 08 to Proprietary Card
- DimmFormFactorFormFactor, ///< Assign 09 to DIMM
- TsopFormFactor, ///< Assign 10 to TSOP
- RowOfChipsFormFactor, ///< Assign 11 to Row of chips
- RimmFormFactor, ///< Assign 12 to RIMM
- SodimmFormFactor, ///< Assign 13 to SODIMM
- SrimmFormFactor, ///< Assign 14 to SRIMM
- FbDimmFormFactor ///< Assign 15 to FB-DIMM
-} DMI_T17_FORM_FACTOR;
-
-/// DMI Type 17 offset 12h - Memory Type
-typedef enum {
- OtherMemType = 0x01, ///< Assign 01 to Other
- UnknownMemType, ///< Assign 02 to Unknown
- DramMemType, ///< Assign 03 to DRAM
- EdramMemType, ///< Assign 04 to EDRAM
- VramMemType, ///< Assign 05 to VRAM
- SramMemType, ///< Assign 06 to SRAM
- RamMemType, ///< Assign 07 to RAM
- RomMemType, ///< Assign 08 to ROM
- FlashMemType, ///< Assign 09 to Flash
- EepromMemType, ///< Assign 10 to EEPROM
- FepromMemType, ///< Assign 11 to FEPROM
- EpromMemType, ///< Assign 12 to EPROM
- CdramMemType, ///< Assign 13 to CDRAM
- ThreeDramMemType, ///< Assign 14 to 3DRAM
- SdramMemType, ///< Assign 15 to SDRAM
- SgramMemType, ///< Assign 16 to SGRAM
- RdramMemType, ///< Assign 17 to RDRAM
- DdrMemType, ///< Assign 18 to DDR
- Ddr2MemType, ///< Assign 19 to DDR2
- Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM
- Ddr3MemType = 0x18, ///< Assign 24 to DDR3
- Fbd2MemType ///< Assign 25 to FBD2
-} DMI_T17_MEMORY_TYPE;
-
-/// DMI Type 17 offset 13h - Type Detail
-typedef struct {
- OUT UINT16 Reserved1:1; ///< Reserved
- OUT UINT16 Other:1; ///< Other
- OUT UINT16 Unknown:1; ///< Unknown
- OUT UINT16 FastPaged:1; ///< Fast-Paged
- OUT UINT16 StaticColumn:1; ///< Static column
- OUT UINT16 PseudoStatic:1; ///< Pseudo-static
- OUT UINT16 Rambus:1; ///< RAMBUS
- OUT UINT16 Synchronous:1; ///< Synchronous
- OUT UINT16 Cmos:1; ///< CMOS
- OUT UINT16 Edo:1; ///< EDO
- OUT UINT16 WindowDram:1; ///< Window DRAM
- OUT UINT16 CacheDram:1; ///< Cache Dram
- OUT UINT16 NonVolatile:1; ///< Non-volatile
- OUT UINT16 Reserved2:3; ///< Reserved
-} DMI_T17_TYPE_DETAIL;
-
-/// DMI Type 17 - Memory Device
-typedef struct {
- OUT UINT16 TotalWidth; ///< Total Width, in bits, of this memory device, including any check or error-correction bits.
- OUT UINT16 DataWidth; ///< Data Width, in bits, of this memory device.
- OUT UINT16 MemorySize; ///< The size of the memory device.
- OUT DMI_T17_FORM_FACTOR FormFactor; ///< The implementation form factor for this memory device.
- OUT UINT8 DeviceSet; ///< Identifies when the Memory Device is one of a set of
- ///< Memory Devices that must be populated with all devices of
- ///< the same type and size, and the set to which this device belongs.
- OUT CHAR8 DeviceLocator[8]; ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
- OUT CHAR8 BankLocator[10]; ///< The string number of the string that identifies the physically labeled bank where the memory device is located.
- OUT DMI_T17_MEMORY_TYPE MemoryType; ///< The type of memory used in this device.
- OUT DMI_T17_TYPE_DETAIL TypeDetail; ///< Additional detail on the memory device type
- OUT UINT16 Speed; ///< Identifies the speed of the device, in megahertz (MHz).
- OUT UINT64 ManufacturerIdCode; ///< Manufacturer ID code.
- OUT CHAR8 SerialNumber[9]; ///< Serial Number.
- OUT CHAR8 PartNumber[19]; ///< Part Number.
- OUT UINT8 Attributes; ///< Bits 7-4: Reserved, Bits 3-0: rank.
- OUT UINT32 ExtSize; ///< Extended Size.
- OUT UINT16 ConfigSpeed; ///< Configured memory clock speed
-} TYPE17_DMI_INFO;
-
-/// Memory DMI Type 17 and 20 - for memory use
-typedef struct {
- OUT UINT16 TotalWidth; ///< Total Width, in bits, of this memory device, including any check or error-correction bits.
- OUT UINT16 DataWidth; ///< Data Width, in bits, of this memory device.
- OUT UINT16 MemorySize; ///< The size of the memory device.
- OUT DMI_T17_FORM_FACTOR FormFactor; ///< The implementation form factor for this memory device.
- OUT UINT8 DeviceLocator; ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
- OUT UINT8 BankLocator; ///< The string number of the string that identifies the physically labeled bank where the memory device is located.
- OUT UINT16 Speed; ///< Identifies the speed of the device, in megahertz (MHz).
- OUT UINT64 ManufacturerIdCode; ///< Manufacturer ID code.
- OUT UINT8 SerialNumber[4]; ///< Serial Number.
- OUT UINT8 PartNumber[18]; ///< Part Number.
- OUT UINT8 Attributes; ///< Bits 7-4: Reserved, Bits 3-0: rank.
- OUT UINT32 ExtSize; ///< Extended Size.
- OUT UINT8 Socket:3; ///< Socket ID
- OUT UINT8 Channel:2; ///< Channel ID
- OUT UINT8 Dimm:2; ///< DIMM ID
- OUT UINT8 DimmPresent:1; ///< Dimm Present
- OUT UINT32 StartingAddr; ///< The physical address, in kilobytes, of a range
- ///< of memory mapped to the referenced Memory Device.
- OUT UINT32 EndingAddr; ///< The handle, or instance number, associated with
- ///< the Memory Device structure to which this address
- ///< range is mapped.
- OUT UINT16 ConfigSpeed; ///< Configured memory clock speed
-} MEM_DMI_INFO;
-
-/// DMI Type 19 - Memory Array Mapped Address
-typedef struct {
- OUT UINT32 StartingAddr; ///< The physical address, in kilobytes,
- ///< of a range of memory mapped to the
- ///< specified physical memory array.
- OUT UINT32 EndingAddr; ///< The physical ending address of the
- ///< last kilobyte of a range of addresses
- ///< mapped to the specified physical memory array.
- OUT UINT16 MemoryArrayHandle; ///< The handle, or instance number, associated
- ///< with the physical memory array to which this
- ///< address range is mapped.
- OUT UINT8 PartitionWidth; ///< Identifies the number of memory devices that
- ///< form a single row of memory for the address
- ///< partition defined by this structure.
-} TYPE19_DMI_INFO;
-
-///DMI Type 20 - Memory Device Mapped Address
-typedef struct {
- OUT UINT32 StartingAddr; ///< The physical address, in kilobytes, of a range
- ///< of memory mapped to the referenced Memory Device.
- OUT UINT32 EndingAddr; ///< The handle, or instance number, associated with
- ///< the Memory Device structure to which this address
- ///< range is mapped.
- OUT UINT16 MemoryDeviceHandle; ///< The handle, or instance number, associated with
- ///< the Memory Device structure to which this address
- ///< range is mapped.
- OUT UINT16 MemoryArrayMappedAddressHandle; ///< The handle, or instance number, associated
- ///< with the Memory Array Mapped Address structure to
- ///< which this device address range is mapped.
- OUT UINT8 PartitionRowPosition; ///< Identifies the position of the referenced Memory
- ///< Device in a row of the address partition.
- OUT UINT8 InterleavePosition; ///< The position of the referenced Memory Device in
- ///< an interleave.
- OUT UINT8 InterleavedDataDepth; ///< The maximum number of consecutive rows from the
- ///< referenced Memory Device that are accessed in a
- ///< single interleaved transfer.
-} TYPE20_DMI_INFO;
-
-/// Collection of pointers to the DMI records
-typedef struct {
- OUT TYPE4_DMI_INFO T4[MAX_SOCKETS_SUPPORTED]; ///< Type 4 struc
- OUT TYPE7_DMI_INFO T7L1[MAX_SOCKETS_SUPPORTED]; ///< Type 7 struc 1
- OUT TYPE7_DMI_INFO T7L2[MAX_SOCKETS_SUPPORTED]; ///< Type 7 struc 2
- OUT TYPE7_DMI_INFO T7L3[MAX_SOCKETS_SUPPORTED]; ///< Type 7 struc 3
- OUT TYPE16_DMI_INFO T16; ///< Type 16 struc
- OUT TYPE17_DMI_INFO T17[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 17 struc
- OUT TYPE19_DMI_INFO T19; ///< Type 19 struc
- OUT TYPE20_DMI_INFO T20[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 20 struc
-} DMI_INFO;
-
-/**********************************************************************
- * Interface call: AllocateExecutionCache
- **********************************************************************/
-#define MAX_CACHE_REGIONS 3
-
-/// AllocateExecutionCache sub param structure for cached memory region
-typedef struct {
- IN OUT UINT32 ExeCacheStartAddr; ///< Start address
- IN OUT UINT32 ExeCacheSize; ///< Size
-} EXECUTION_CACHE_REGION;
-
-/**********************************************************************
- * Interface call: AmdGetAvailableExeCacheSize
- **********************************************************************/
-/// Get available Cache remain
-typedef struct {
- IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
- OUT UINT32 AvailableExeCacheSize; ///< Remain size
-} AMD_GET_EXE_SIZE_PARAMS;
-
-AGESA_STATUS
-AmdGetAvailableExeCacheSize (
- IN OUT AMD_GET_EXE_SIZE_PARAMS *AmdGetExeSizeParams
- );
-
-/// Selection type for core leveling
-typedef enum {
- CORE_LEVEL_LOWEST, ///< Level to lowest common denominator
- CORE_LEVEL_TWO, ///< Level to 2 cores
- CORE_LEVEL_POWER_OF_TWO, ///< Level to 1,2,4 or 8
- CORE_LEVEL_NONE, ///< Do no leveling
- CORE_LEVEL_COMPUTE_UNIT, ///< Level cores to one core per compute unit
- CORE_LEVEL_ONE, ///< Level to 1 core
- CORE_LEVEL_THREE, ///< Level to 3 cores
- CORE_LEVEL_FOUR, ///< Level to 4 cores
- CORE_LEVEL_FIVE, ///< Level to 5 cores
- CORE_LEVEL_SIX, ///< Level to 6 cores
- CORE_LEVEL_SEVEN, ///< Level to 7 cores
- CORE_LEVEL_EIGHT, ///< Level to 8 cores
- CORE_LEVEL_NINE, ///< Level to 9 cores
- CORE_LEVEL_TEN, ///< Level to 10 cores
- CORE_LEVEL_ELEVEN, ///< Level to 11 cores
- CORE_LEVEL_TWELVE, ///< Level to 12 cores
- CORE_LEVEL_THIRTEEN, ///< Level to 13 cores
- CORE_LEVEL_FOURTEEN, ///< Level to 14 cores
- CORE_LEVEL_FIFTEEN, ///< Level to 15 cores
- CoreLevelModeMax ///< Used for bounds checking
-} CORE_LEVELING_TYPE;
-
-
-
-
-
-/************************************************************************
- *
- * AGESA Basic Level interface structure definition and function prototypes
- *
- ***********************************************************************/
-
-/**********************************************************************
- * Interface call: AmdCreateStruct
- **********************************************************************/
-AGESA_STATUS
-AmdCreateStruct (
- IN OUT AMD_INTERFACE_PARAMS *InterfaceParams
- );
-
-/**********************************************************************
- * Interface call: AmdReleaseStruct
- **********************************************************************/
-AGESA_STATUS
-AmdReleaseStruct (
- IN OUT AMD_INTERFACE_PARAMS *InterfaceParams
- );
-
-/**********************************************************************
- * Interface call: AmdInitReset
- **********************************************************************/
-/// AmdInitReset param structure
-typedef struct {
- IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
- IN EXECUTION_CACHE_REGION CacheRegion[3]; ///< The cached memory region
- IN AMD_HT_RESET_INTERFACE HtConfig; ///< The interface for Ht Recovery
-} AMD_RESET_PARAMS;
-
-AGESA_STATUS
-AmdInitReset (
- IN OUT AMD_RESET_PARAMS *ResetParams
- );
-
-
-/**********************************************************************
- * Interface call: AmdInitEarly
- **********************************************************************/
-/// InitEarly param structure
-///
-/// Provide defaults or customizations to each service performed in AmdInitEarly.
-///
-typedef struct {
- IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
- IN EXECUTION_CACHE_REGION CacheRegion[3]; ///< Execution Map Interface
- IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
- IN AMD_HT_INTERFACE HtConfig; ///< HyperTransport Interface
- IN GNB_CONFIGURATION GnbConfig; ///< GNB configuration
-} AMD_EARLY_PARAMS;
-
-AGESA_STATUS
-AmdInitEarly (
- IN OUT AMD_EARLY_PARAMS *EarlyParams
- );
-
-
-/**********************************************************************
- * Interface call: AmdInitPost
- **********************************************************************/
-/// AmdInitPost param structure
-typedef struct {
- IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
- IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
- IN MEM_PARAMETER_STRUCT MemConfig; ///< Memory post param
-} AMD_POST_PARAMS;
-
-AGESA_STATUS
-AmdInitPost (
- IN OUT AMD_POST_PARAMS *PostParams ///< Amd Cpu init param
- );
-
-
-/**********************************************************************
- * Interface call: AmdInitEnv
- **********************************************************************/
-/// AmdInitEnv param structure
-typedef struct {
- IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
- IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
- IN GNB_ENV_CONFIGURATION GnbEnvConfiguration; ///< platform operational characteristics.
-} AMD_ENV_PARAMS;
-
-AGESA_STATUS
-AmdInitEnv (
- IN OUT AMD_ENV_PARAMS *EnvParams
- );
-
-
-/**********************************************************************
- * Interface call: AmdInitMid
- **********************************************************************/
-/// AmdInitMid param structure
-typedef struct {
- IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
- IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
-} AMD_MID_PARAMS;
-
-AGESA_STATUS
-AmdInitMid (
- IN OUT AMD_MID_PARAMS *MidParams
- );
-
-
-/**********************************************************************
- * Interface call: AmdInitLate
- **********************************************************************/
-/// AmdInitLate param structure
-typedef struct {
- IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
- IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
- OUT DMI_INFO *DmiTable; ///< DMI Interface
- OUT VOID *AcpiPState; ///< Acpi Pstate SSDT Table
- OUT VOID *AcpiSrat; ///< SRAT Table
- OUT VOID *AcpiSlit; ///< SLIT Table
- OUT VOID *AcpiWheaMce; ///< WHEA MCE Table
- OUT VOID *AcpiWheaCmc; ///< WHEA CMC Table
- OUT VOID *AcpiAlib; ///< ACPI SSDT table with ALIB implementation
-} AMD_LATE_PARAMS;
-
-AGESA_STATUS
-AmdInitLate (
- IN OUT AMD_LATE_PARAMS *LateParams
- );
-
-/**********************************************************************
- * Interface call: AmdInitRecovery
- **********************************************************************/
-/// CPU Recovery Parameters
-typedef struct {
- IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
- IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
-} AMD_CPU_RECOVERY_PARAMS;
-
-/// AmdInitRecovery param structure
-typedef struct {
- IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
- IN MEM_PARAMETER_STRUCT MemConfig; ///< Memory post param
- IN EXECUTION_CACHE_REGION CacheRegion[3]; ///< The cached memory region. And the max cache region is 3
- IN AMD_CPU_RECOVERY_PARAMS CpuRecoveryParams; ///< Params for CPU related recovery init.
-} AMD_RECOVERY_PARAMS;
-
-AGESA_STATUS
-AmdInitRecovery (
- IN OUT AMD_RECOVERY_PARAMS *RecoveryParams
- );
-
-/**********************************************************************
- * Interface call: AmdInitResume
- **********************************************************************/
-/// AmdInitResume param structure
-typedef struct {
- IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
- IN PLATFORM_CONFIGURATION PlatformConfig; ///< Platform operational characteristics
- IN AMD_S3_PARAMS S3DataBlock; ///< Save state data
-} AMD_RESUME_PARAMS;
-
-AGESA_STATUS
-AmdInitResume (
- IN AMD_RESUME_PARAMS *ResumeParams
- );
-
-
-/**********************************************************************
- * Interface call: AmdS3LateRestore
- **********************************************************************/
-/// AmdS3LateRestore param structure
-typedef struct {
- IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
- IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
- IN AMD_S3_PARAMS S3DataBlock; ///< Save state data
-} AMD_S3LATE_PARAMS;
-
-AGESA_STATUS
-AmdS3LateRestore (
- IN OUT AMD_S3LATE_PARAMS *S3LateParams
- );
-
-
-/**********************************************************************
- * Interface call: AmdS3Save
- **********************************************************************/
-/// AmdS3Save param structure
-typedef struct {
- IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
- IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
- OUT AMD_S3_PARAMS S3DataBlock; ///< Standard header
-} AMD_S3SAVE_PARAMS;
-
-AGESA_STATUS
-AmdS3Save (
- IN OUT AMD_S3SAVE_PARAMS *AmdS3SaveParams
- );
-
-
-/**********************************************************************
- * Interface call: AmdLateRunApTask
- **********************************************************************/
-/**
- * Entry point for AP tasking.
- */
-AGESA_STATUS
-AmdLateRunApTask (
- IN AP_EXE_PARAMS *AmdApExeParams
-);
-
-//
-// General Services API
-//
-
-/**********************************************************************
- * Interface service call: AmdGetApicId
- **********************************************************************/
-/// Request the APIC ID of a particular core.
-
-typedef struct {
- IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
- IN UINT8 Socket; ///< The Core's Socket.
- IN UINT8 Core; ///< The Core id.
- OUT BOOLEAN IsPresent; ///< The Core is present, and ApicAddress is valid.
- OUT UINT8 ApicAddress; ///< The Core's APIC ID.
-} AMD_APIC_PARAMS;
-
-/**
- * Get a specified Core's APIC ID.
- */
-AGESA_STATUS
-AmdGetApicId (
- IN OUT AMD_APIC_PARAMS *AmdParamApic
-);
-
-/**********************************************************************
- * Interface service call: AmdGetPciAddress
- **********************************************************************/
-/// Request the PCI Address of a Processor Module (that is, its Northbridge)
-
-typedef struct {
- IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
- IN UINT8 Socket; ///< The Processor's socket
- IN UINT8 Module; ///< The Module in that Processor
- OUT BOOLEAN IsPresent; ///< The Core is present, and PciAddress is valid.
- OUT PCI_ADDR PciAddress; ///< The Processor's PCI Config Space address (Function 0, Register 0)
-} AMD_GET_PCI_PARAMS;
-
-/**
- * Get Processor Module's PCI Config Space address.
- */
-AGESA_STATUS
-AmdGetPciAddress (
- IN OUT AMD_GET_PCI_PARAMS *AmdParamGetPci
-);
-
-/**********************************************************************
- * Interface service call: AmdIdentifyCore
- **********************************************************************/
-/// Request the identity (Socket, Module, Core) of the current Processor Core
-
-typedef struct {
- IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
- OUT UINT8 Socket; ///< The current Core's Socket
- OUT UINT8 Module; ///< The current Core's Processor Module
- OUT UINT8 Core; ///< The current Core's core id.
-} AMD_IDENTIFY_PARAMS;
-
-/**
- * "Who am I" for the current running core.
- */
-AGESA_STATUS
-AmdIdentifyCore (
- IN OUT AMD_IDENTIFY_PARAMS *AmdParamIdentify
-);
-
-/**********************************************************************
- * Interface service call: AmdReadEventLog
- **********************************************************************/
-/// An Event Log Entry.
-typedef struct {
- IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
- OUT UINT32 EventClass; ///< The severity of this event, matches AGESA_STATUS.
- OUT UINT32 EventInfo; ///< The unique event identifier, zero means "no event".
- OUT UINT32 DataParam1; ///< Data specific to the Event.
- OUT UINT32 DataParam2; ///< Data specific to the Event.
- OUT UINT32 DataParam3; ///< Data specific to the Event.
- OUT UINT32 DataParam4; ///< Data specific to the Event.
-} EVENT_PARAMS;
-
-/**
- * Read an Event from the Event Log.
- */
-AGESA_STATUS
-AmdReadEventLog (
- IN EVENT_PARAMS *Event
-);
-
-/**********************************************************************
- * Interface service call: AmdIdentifyDimm
- **********************************************************************/
-/// Request the identity of dimm from system address
-
-typedef struct {
- IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
- IN UINT64 MemoryAddress; ///< System Address that needs to be translated to dimm identification.
- OUT UINT8 SocketId; ///< The socket on which the targeted address locates.
- OUT UINT8 MemChannelId; ///< The channel on which the targeted address locates.
- OUT UINT8 DimmId; ///< The dimm on which the targeted address locates.
-} AMD_IDENTIFY_DIMM;
-
-/**
- * Get the dimm identification for the address.
- */
-AGESA_STATUS
-AmdIdentifyDimm (
- IN OUT AMD_IDENTIFY_DIMM *AmdDimmIdentify
-);
-
-/// Data structure for the Mapping Item between Unified ID for IDS Setup Option
-/// and the option value.
-///
-typedef struct {
- IN UINT16 IdsNvId; ///< Unified ID for IDS Setup Option.
- OUT UINT16 IdsNvValue; ///< The value of IDS Setup Option.
-} IDS_NV_ITEM;
-
-/// Data Structure for IDS CallOut Function
-typedef struct {
- IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
- IN IDS_NV_ITEM *IdsNvPtr; ///< Memory Pointer of IDS NV Table
- IN OUT UINTN Reserved; ///< reserved
-} IDS_CALLOUT_STRUCT;
-
-AGESA_STATUS
-AmdIdsRunApTaskLate (
- IN AP_EXE_PARAMS *AmdApExeParams
- );
-
-
-#define AGESA_IDS_DFT_VAL 0xFFFF ///< Default value of every uninitlized NV item, the action for it will be ignored
-#define AGESA_IDS_NV_END 0xFFFF ///< Flag specify end of option structure
-/// WARNING: Don't change the comment below, it used as signature for script
-/// AGESA IDS NV ID Definitions
-typedef enum {
- AGESA_IDS_EXT_ID_START = 0x0000,///< 0x0000 specify the start of external NV id
-
- AGESA_IDS_NV_UCODE, ///< 0x0001 Enable or disable microcode patching
-
- AGESA_IDS_NV_TARGET_PSTATE, ///< 0x0002 Set the P-state required to be activated
- AGESA_IDS_NV_POSTPSTATE, ///< 0x0003 Set the P-state required to be activated through POST
-
- AGESA_IDS_NV_BANK_INTERLEAVE, ///< 0x0004 Enable or disable Bank Interleave
- AGESA_IDS_NV_CHANNEL_INTERLEAVE, ///< 0x0005 Enable or disable Channel Interleave
- AGESA_IDS_NV_NODE_INTERLEAVE, ///< 0x0006 Enable or disable Node Interleave
- AGESA_IDS_NV_MEMHOLE, ///< 0x0007 Enables or disable memory hole
-
- AGESA_IDS_NV_SCRUB_REDIRECTION, ///< 0x0008 Enable or disable a write to dram with corrected data
- AGESA_IDS_NV_DRAM_SCRUB, ///< 0x0009 Set the rate of background scrubbing for DRAM
- AGESA_IDS_NV_DCACHE_SCRUB, ///< 0x000A Set the rate of background scrubbing for the DCache.
- AGESA_IDS_NV_L2_SCRUB, ///< 0x000B Set the rate of background scrubbing for the L2 cache
- AGESA_IDS_NV_L3_SCRUB, ///< 0x000C Set the rate of background scrubbing for the L3 cache
- AGESA_IDS_NV_ICACHE_SCRUB, ///< 0x000D Set the rate of background scrubbing for the Icache
- AGESA_IDS_NV_SYNC_ON_ECC_ERROR, ///< 0x000E Enable or disable the sync flood on un-correctable ECC error
- AGESA_IDS_NV_ECC_SYMBOL_SIZE, ///< 0x000F Set ECC symbol size
-
- AGESA_IDS_NV_ALL_MEMCLKS, ///< 0x0010 Enable or disable all memory clocks enable
- AGESA_IDS_NV_DCT_GANGING_MODE, ///< 0x0011 Set the Ganged mode
- AGESA_IDS_NV_DRAM_BURST_LENGTH32, ///< 0x0012 Set the DRAM Burst Length 32
- AGESA_IDS_NV_MEMORY_POWER_DOWN, ///< 0x0013 Enable or disable Memory power down mode
- AGESA_IDS_NV_MEMORY_POWER_DOWN_MODE, ///< 0x0014 Set the Memory power down mode
- AGESA_IDS_NV_DLL_SHUT_DOWN, ///< 0x0015 Enable or disable DLLShutdown
- AGESA_IDS_NV_ONLINE_SPARE, ///< 0x0016 Enable or disable the Dram controller to designate a DIMM bank as a spare for logical swap
-
- AGESA_IDS_NV_HT_ASSIST, ///< 0x0017 Enable or Disable HT Assist
- AGESA_IDS_NV_ATMMODE, ///< 0x0018 Enable or Disable ATM mode
-
- AGESA_IDS_NV_HDTOUT, ///< 0x0019 Enable or disable HDTOUT feature
-
- AGESA_IDS_NV_HTLINKSOCKET, ///< 0x001A HT Link Socket
- AGESA_IDS_NV_HTLINKPORT, ///< 0x001B HT Link Port
- AGESA_IDS_NV_HTLINKFREQ, ///< 0x001C HT Link Frequency
- AGESA_IDS_NV_HTLINKWIDTHIN, ///< 0x001D HT Link In Width
- AGESA_IDS_NV_HTLINKWIDTHOUT, ///< 0x001E HT Link Out Width
-
- AGESA_IDS_NV_GNBHDAUDIOEN, ///< 0x001F Enable or disable GNB HD Audio
-
- AGESA_IDS_NV_CPB_EN, ///< 0x0020 Core Performance Boost
-
- AGESA_IDS_NV_HTC_EN, ///< 0x0021 HTC Enable
- AGESA_IDS_NV_HTC_OVERRIDE, ///< 0x0022 HTC Override
- AGESA_IDS_NV_HTC_PSTATE_LIMIT, ///< 0x0023 HTC P-state limit select
- AGESA_IDS_NV_HTC_TEMP_HYS, ///< 0x0024 HTC Temperature Hysteresis
- AGESA_IDS_NV_HTC_ACT_TEMP, ///< 0x0025 HTC Activation Temp
-
- AGESA_IDS_NV_POWER_POLICY, ///< 0x0026 Select Platform Power Policy
- AGESA_IDS_EXT_ID_END, ///< 0x0027 specify the end of external NV ID
-} IDS_EX_NV_ID;
-
-
-#define IDS_NUM_EXT_NV_ITEM (AGESA_IDS_EXT_ID_END - AGESA_IDS_EXT_ID_START + 1)
-
-#endif // _AGESA_H_
diff --git a/src/vendorcode/amd/agesa/AMD.h b/src/vendorcode/amd/agesa/AMD.h
deleted file mode 100644
index f788da8..0000000
--- a/src/vendorcode/amd/agesa/AMD.h
+++ /dev/null
@@ -1,482 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Agesa structures and definitions
- *
- * Contains AMD AGESA core interface
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Include
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-#ifndef _AMD_H_
-#define _AMD_H_
-
-#define AGESA_REVISION "Arch2008"
-#define AGESA_ID "AGESA"
-
-#define Int16FromChar(a,b) ((a) << 0 | (b) << 8)
-#define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)
-//
-//
-// AGESA Types and Definitions
-//
-//
-#define LAST_ENTRY 0xFFFFFFFF
-#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D')
-#define IOCF8 0xCF8
-#define IOCFC 0xCFC
-
-/// The return status for all AGESA public services.
-///
-/// Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
-/// will have log entries with more detail.
-///
-typedef enum {
- AGESA_SUCCESS = 0, ///< The service completed normally. Info may be logged.
- AGESA_UNSUPPORTED, ///< The dispatcher or create struct had an unimplemented function requested.
- ///< Not logged.
- AGESA_BOUNDS_CHK, ///< A dynamic parameter was out of range and the service was not provided.
- ///< Example, memory address not installed, heap buffer handle not found.
- ///< Not Logged.
- // AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
- AGESA_ALERT, ///< An observed condition, but no loss of function.
- ///< See log. Example, HT CRC.
- AGESA_WARNING, ///< Possible or minor loss of function. See Log.
- AGESA_ERROR, ///< Significant loss of function, boot may be possible. See Log.
- AGESA_CRITICAL, ///< Continue boot only to notify user. See Log.
- AGESA_FATAL, ///< Halt booting. See Log, however Fatal errors pertaining to heap problems
- ///< may not be able to reliably produce log events.
- AgesaStatusMax ///< Not a status, for limit checking.
-} AGESA_STATUS;
-
-/// For checking whether a status is at or above the mandatory log level.
-#define AGESA_STATUS_LOG_LEVEL AGESA_ALERT
-
-/**
- * Callout method to the host environment.
- *
- * Callout using a dispatch with appropriate thunk layer, which is determined by the host environment.
- *
- * @param[in] Function The specific callout function being invoked.
- * @param[in] FcnData Function specific data item.
- * @param[in,out] ConfigPtr Reference to Callout params.
- */
-typedef AGESA_STATUS (*CALLOUT_ENTRY) (
- IN UINT32 Function,
- IN UINTN FcnData,
- IN OUT VOID *ConfigPtr
- );
-
-typedef AGESA_STATUS (*IMAGE_ENTRY) (VOID *ConfigPtr);
-typedef AGESA_STATUS (*MODULE_ENTRY) (VOID *ConfigPtr);
-
-///This allocation type is used by the AmdCreateStruct entry point
-typedef enum {
- PreMemHeap = 0, ///< Create heap in cache.
- PostMemDram, ///< Create heap in memory.
- ByHost ///< Create heap by Host.
-} ALLOCATION_METHOD;
-
-/// These width descriptors are used by the library function, and others, to specify the data size
-typedef enum ACCESS_WIDTH {
- AccessWidth8 = 1, ///< Access width is 8 bits.
- AccessWidth16, ///< Access width is 16 bits.
- AccessWidth32, ///< Access width is 32 bits.
- AccessWidth64, ///< Access width is 64 bits.
-
- AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data.
- AccessS3SaveWidth16, ///< Save 16 bits data.
- AccessS3SaveWidth32, ///< Save 32 bits data.
- AccessS3SaveWidth64, ///< Save 64 bits data.
-} ACCESS_WIDTH;
-
-/// AGESA struct name
-typedef enum {
- // AGESA BASIC FUNCTIONS
- AMD_INIT_RECOVERY = 0x00020000, ///< AmdInitRecovery entry point handle
- AMD_CREATE_STRUCT, ///< AmdCreateStruct handle
- AMD_INIT_EARLY, ///< AmdInitEarly entry point handle
- AMD_INIT_ENV, ///< AmdInitEnv entry point handle
- AMD_INIT_LATE, ///< AmdInitLate entry point handle
- AMD_INIT_MID, ///< AmdInitMid entry point handle
- AMD_INIT_POST, ///< AmdInitPost entry point handle
- AMD_INIT_RESET, ///< AmdInitReset entry point handle
- AMD_INIT_RESUME, ///< AmdInitResume entry point handle
- AMD_RELEASE_STRUCT, ///< AmdReleaseStruct handle
- AMD_S3LATE_RESTORE, ///< AmdS3LateRestore entry point handle
- AMD_S3_SAVE, ///< AmdS3Save entry point handle
- AMD_GET_APIC_ID, ///< AmdGetApicId entry point handle
- AMD_GET_PCI_ADDRESS, ///< AmdGetPciAddress entry point handle
- AMD_IDENTIFY_CORE, ///< AmdIdentifyCore general service handle
- AMD_READ_EVENT_LOG, ///< AmdReadEventLog general service handle
- AMD_GET_EXECACHE_SIZE, ///< AmdGetAvailableExeCacheSize general service handle
- AMD_LATE_RUN_AP_TASK, ///< AmdLateRunApTask entry point handle
- AMD_IDENTIFY_DIMMS ///< AmdIdentifyDimm general service handle
-} AGESA_STRUCT_NAME;
-
- /* ResetType constant values */
-#define WARM_RESET_WHENEVER 1
-#define COLD_RESET_WHENEVER 2
-#define WARM_RESET_IMMEDIATELY 3
-#define COLD_RESET_IMMEDIATELY 4
-
-
-// AGESA Structures
-
-/// The standard header for all AGESA services.
-/// For internal AGESA naming conventions, see @ref amdconfigparamname .
-typedef struct {
- IN UINT32 ImageBasePtr; ///< The AGESA Image base address.
- IN UINT32 Func; ///< The service desired
- IN UINT32 AltImageBasePtr; ///< Alternate Image location
- IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA
- IN UINT8 HeapStatus; ///< For heap status from boot time slide.
- IN UINT64 HeapBasePtr; ///< Location of the heap
- IN OUT UINT8 Reserved[7]; ///< This space is reserved for future use.
-} AMD_CONFIG_PARAMS;
-
-
-/// Create Struct Interface.
-typedef struct {
- IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
- IN AGESA_STRUCT_NAME AgesaFunctionName; ///< The service to init
- IN ALLOCATION_METHOD AllocationMethod; ///< How to handle buffer allocation
- IN OUT UINT32 NewStructSize; ///< The size of the allocated data, in for ByHost, else out only.
- IN OUT VOID *NewStructPtr; ///< The struct for the service.
- ///< The struct to init for ByHost allocation,
- ///< the initialized struct on return.
-} AMD_INTERFACE_PARAMS;
-
-#define FUNC_0 0 // bit-placed for PCI address creation
-#define FUNC_1 1
-#define FUNC_2 2
-#define FUNC_3 3
-#define FUNC_4 4
-#define FUNC_5 5
-#define FUNC_6 6
-#define FUNC_7 7
-
-/// AGESA Binary module header structure
-typedef struct {
- IN UINT32 Signature; ///< Binary Signature
- IN CHAR8 CreatorID[8]; ///< 8 characters ID
- IN CHAR8 Version[12]; ///< 12 characters version
- IN UINT32 ModuleInfoOffset; ///< Offset of module
- IN UINT32 EntryPointAddress; ///< Entry address
- IN UINT32 ImageBase; ///< Image base
- IN UINT32 RelocTableOffset; ///< Relocate Table offset
- IN UINT32 ImageSize; ///< Size
- IN UINT16 Checksum; ///< Checksum
- IN UINT8 ImageType; ///< Type
- IN UINT8 V_Reserved; ///< Reserved
-} AMD_IMAGE_HEADER;
-/// AGESA Binary module header structure
-typedef struct _AMD_MODULE_HEADER {
- IN UINT32 ModuleHeaderSignature; ///< Module signature
- IN CHAR8 ModuleIdentifier[8]; ///< 8 characters ID
- IN CHAR8 ModuleVersion[12]; ///< 12 characters version
- IN VOID *ModuleDispatcher; ///< A pointer point to dispatcher
- IN struct _AMD_MODULE_HEADER *NextBlock; ///< Next module header link
-} AMD_MODULE_HEADER;
-
-// AMD_CODE_HEADER Signatures.
-#define AGESA_CODE_SIGNATURE {'!', '!', 'A', 'G', 'E', 'S', 'A', ' '}
-#define CIMXNB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'}
-#define CIMXSB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'}
-
-/// AGESA_CODE_SIGNATURE
-typedef struct {
- IN CHAR8 Signature[8]; ///< code header Signature
- IN CHAR8 ComponentName[8]; ///< 8 character name of the code module
- IN CHAR8 Version[12]; ///< 12 character version string
- IN CHAR8 TerminatorNull; ///< null terminated string
- IN CHAR8 VerReserved[7]; ///< reserved space
-} AMD_CODE_HEADER;
-
-/// Extended PCI address format
-typedef struct {
- IN OUT UINT32 Register:12; ///< Register offset
- IN OUT UINT32 Function:3; ///< Function number
- IN OUT UINT32 Device:5; ///< Device number
- IN OUT UINT32 Bus:8; ///< Bus number
- IN OUT UINT32 Segment:4; ///< Segment
-} EXT_PCI_ADDR;
-
-/// Union type for PCI address
-typedef union _PCI_ADDR {
- IN UINT32 AddressValue; ///< Formal address
- IN EXT_PCI_ADDR Address; ///< Extended address
-} PCI_ADDR;
-
-// SBDFO - Segment Bus Device Function Offset
-// 31:28 Segment (4-bits)
-// 27:20 Bus (8-bits)
-// 19:15 Device (5-bits)
-// 14:12 Function(3-bits)
-// 11:00 Offset (12-bits)
-
-#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \
- (((UINT32)(Dev)) << 15) | (((UINT32)(Fun)) << 12) | ((UINT32)(Off)))
-#define ILLEGAL_SBDFO 0xFFFFFFFF
-
-/// CPUID data received registers format
-typedef struct {
- OUT UINT32 EAX_Reg; ///< CPUID instruction result in EAX
- OUT UINT32 EBX_Reg; ///< CPUID instruction result in EBX
- OUT UINT32 ECX_Reg; ///< CPUID instruction result in ECX
- OUT UINT32 EDX_Reg; ///< CPUID instruction result in EDX
-} CPUID_DATA;
-
-/// HT frequency for external callbacks
-typedef enum {
- HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks
- HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks
- HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks
- HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks
- HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks
- HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks
- HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks
- HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks
- HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks
- HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks
- HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks
- HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks
- HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks
- HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks
- HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks
- HT_FREQUENCY_3200M = 19, ///< HT speed 3200 for external callbacks
- HT_FREQUENCY_MAX ///< Limit check.
-} HT_FREQUENCIES;
-// The minimum HT3 frequency
-#define HT3_FREQUENCY_MIN HT_FREQUENCY_1200M
-
-#ifndef BIT0
- #define BIT0 0x0000000000000001ull
-#endif
-#ifndef BIT1
- #define BIT1 0x0000000000000002ull
-#endif
-#ifndef BIT2
- #define BIT2 0x0000000000000004ull
-#endif
-#ifndef BIT3
- #define BIT3 0x0000000000000008ull
-#endif
-#ifndef BIT4
- #define BIT4 0x0000000000000010ull
-#endif
-#ifndef BIT5
- #define BIT5 0x0000000000000020ull
-#endif
-#ifndef BIT6
- #define BIT6 0x0000000000000040ull
-#endif
-#ifndef BIT7
- #define BIT7 0x0000000000000080ull
-#endif
-#ifndef BIT8
- #define BIT8 0x0000000000000100ull
-#endif
-#ifndef BIT9
- #define BIT9 0x0000000000000200ull
-#endif
-#ifndef BIT10
- #define BIT10 0x0000000000000400ull
-#endif
-#ifndef BIT11
- #define BIT11 0x0000000000000800ull
-#endif
-#ifndef BIT12
- #define BIT12 0x0000000000001000ull
-#endif
-#ifndef BIT13
- #define BIT13 0x0000000000002000ull
-#endif
-#ifndef BIT14
- #define BIT14 0x0000000000004000ull
-#endif
-#ifndef BIT15
- #define BIT15 0x0000000000008000ull
-#endif
-#ifndef BIT16
- #define BIT16 0x0000000000010000ull
-#endif
-#ifndef BIT17
- #define BIT17 0x0000000000020000ull
-#endif
-#ifndef BIT18
- #define BIT18 0x0000000000040000ull
-#endif
-#ifndef BIT19
- #define BIT19 0x0000000000080000ull
-#endif
-#ifndef BIT20
- #define BIT20 0x0000000000100000ull
-#endif
-#ifndef BIT21
- #define BIT21 0x0000000000200000ull
-#endif
-#ifndef BIT22
- #define BIT22 0x0000000000400000ull
-#endif
-#ifndef BIT23
- #define BIT23 0x0000000000800000ull
-#endif
-#ifndef BIT24
- #define BIT24 0x0000000001000000ull
-#endif
-#ifndef BIT25
- #define BIT25 0x0000000002000000ull
-#endif
-#ifndef BIT26
- #define BIT26 0x0000000004000000ull
-#endif
-#ifndef BIT27
- #define BIT27 0x0000000008000000ull
-#endif
-#ifndef BIT28
- #define BIT28 0x0000000010000000ull
-#endif
-#ifndef BIT29
- #define BIT29 0x0000000020000000ull
-#endif
-#ifndef BIT30
- #define BIT30 0x0000000040000000ull
-#endif
-#ifndef BIT31
- #define BIT31 0x0000000080000000ull
-#endif
-#ifndef BIT32
- #define BIT32 0x0000000100000000ull
-#endif
-#ifndef BIT33
- #define BIT33 0x0000000200000000ull
-#endif
-#ifndef BIT34
- #define BIT34 0x0000000400000000ull
-#endif
-#ifndef BIT35
- #define BIT35 0x0000000800000000ull
-#endif
-#ifndef BIT36
- #define BIT36 0x0000001000000000ull
-#endif
-#ifndef BIT37
- #define BIT37 0x0000002000000000ull
-#endif
-#ifndef BIT38
- #define BIT38 0x0000004000000000ull
-#endif
-#ifndef BIT39
- #define BIT39 0x0000008000000000ull
-#endif
-#ifndef BIT40
- #define BIT40 0x0000010000000000ull
-#endif
-#ifndef BIT41
- #define BIT41 0x0000020000000000ull
-#endif
-#ifndef BIT42
- #define BIT42 0x0000040000000000ull
-#endif
-#ifndef BIT43
- #define BIT43 0x0000080000000000ull
-#endif
-#ifndef BIT44
- #define BIT44 0x0000100000000000ull
-#endif
-#ifndef BIT45
- #define BIT45 0x0000200000000000ull
-#endif
-#ifndef BIT46
- #define BIT46 0x0000400000000000ull
-#endif
-#ifndef BIT47
- #define BIT47 0x0000800000000000ull
-#endif
-#ifndef BIT48
- #define BIT48 0x0001000000000000ull
-#endif
-#ifndef BIT49
- #define BIT49 0x0002000000000000ull
-#endif
-#ifndef BIT50
- #define BIT50 0x0004000000000000ull
-#endif
-#ifndef BIT51
- #define BIT51 0x0008000000000000ull
-#endif
-#ifndef BIT52
- #define BIT52 0x0010000000000000ull
-#endif
-#ifndef BIT53
- #define BIT53 0x0020000000000000ull
-#endif
-#ifndef BIT54
- #define BIT54 0x0040000000000000ull
-#endif
-#ifndef BIT55
- #define BIT55 0x0080000000000000ull
-#endif
-#ifndef BIT56
- #define BIT56 0x0100000000000000ull
-#endif
-#ifndef BIT57
- #define BIT57 0x0200000000000000ull
-#endif
-#ifndef BIT58
- #define BIT58 0x0400000000000000ull
-#endif
-#ifndef BIT59
- #define BIT59 0x0800000000000000ull
-#endif
-#ifndef BIT60
- #define BIT60 0x1000000000000000ull
-#endif
-#ifndef BIT61
- #define BIT61 0x2000000000000000ull
-#endif
-#ifndef BIT62
- #define BIT62 0x4000000000000000ull
-#endif
-#ifndef BIT63
- #define BIT63 0x8000000000000000ull
-#endif
-
-#endif // _AMD_H_
diff --git a/src/vendorcode/amd/agesa/Dispatcher.h b/src/vendorcode/amd/agesa/Dispatcher.h
deleted file mode 100644
index fd6aaa8..0000000
--- a/src/vendorcode/amd/agesa/Dispatcher.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Pushhigh Interface
- *
- * Contains interface to Pushhigh entry
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Legacy
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _DISPATCHER_H_
-#define _DISPATCHER_H_
-
-// AGESA function prototypes
-AGESA_STATUS CALLCONV AmdAgesaDispatcher ( IN OUT VOID *ConfigPtr );
-AGESA_STATUS CALLCONV AmdAgesaCallout ( IN UINT32 Func, IN UINT32 Data, IN OUT VOID *ConfigPtr );
-
-#endif // _DISPATCHER_H_
diff --git a/src/vendorcode/amd/agesa/Include/AdvancedApi.h b/src/vendorcode/amd/agesa/Include/AdvancedApi.h
deleted file mode 100644
index 573650a..0000000
--- a/src/vendorcode/amd/agesa/Include/AdvancedApi.h
+++ /dev/null
@@ -1,168 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Advanced API Interface for HT, Memory and CPU
- *
- * Contains additional declarations need to use HT, Memory and CPU Advanced interface, such as
- * would be required by the basic interface implementations.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Include
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-#ifndef _ADVANCED_API_H_
-#define _ADVANCED_API_H_
-
-/*----------------------------------------------------------------------------
- * HT FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-/**
- * A constructor for the HyperTransport input structure.
- *
- * Sets inputs to valid, basic level, defaults.
- *
- * @param[in] StdHeader Opaque handle to standard config header
- * @param[in] AmdHtInterface HT Interface structure to initialize.
- *
- * @retval AGESA_SUCCESS Constructors are not allowed to fail
-*/
-AGESA_STATUS
-AmdHtInterfaceConstructor (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN AMD_HT_INTERFACE *AmdHtInterface
- );
-
-/**
- * The top level external interface for Hypertransport Initialization.
- *
- * Create our initial internal state, initialize the coherent fabric,
- * initialize the non-coherent chains, and perform any required fabric tuning or
- * optimization.
- *
- * @param[in] StdHeader Opaque handle to standard config header
- * @param[in] PlatformConfiguration The platform configuration options.
- * @param[in] AmdHtInterface HT Interface structure.
- *
- * @retval AGESA_SUCCESS Only information events logged.
- * @retval AGESA_ALERT Sync Flood or CRC error logged.
- * @retval AGESA_WARNING Example: expected capability not found
- * @retval AGESA_ERROR logged events indicating some devices may not be available
- * @retval AGESA_FATAL Mixed Family or MP capability mismatch
- *
- */
-AGESA_STATUS
-AmdHtInitialize (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN PLATFORM_CONFIGURATION *PlatformConfiguration,
- IN AMD_HT_INTERFACE *AmdHtInterface
- );
-
-/*----------------------------------------------------------------------------
- * HT Recovery FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-/**
- * A constructor for the HyperTransport input structure.
- *
- */
-AGESA_STATUS
-AmdHtResetConstructor (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface
- );
-
-/**
- * Initialize HT at Reset for both Normal and Recovery.
- *
- */
-AGESA_STATUS
-AmdHtInitReset (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface
- );
-
-/**
- * Initialize the Node and Socket maps for an AP Core.
- *
- */
-AGESA_STATUS
-AmdHtInitRecovery (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-///----------------------------------------------------------------------------
-/// MEMORY FUNCTIONS PROTOTYPE
-///
-///----------------------------------------------------------------------------
-
-AGESA_STATUS
-AmdMemRecovery (
- IN OUT MEM_DATA_STRUCT *MemPtr
- );
-
-AGESA_STATUS
-AmdMemAuto (
- IN OUT MEM_DATA_STRUCT *MemPtr
- );
-
-VOID
-AmdMemInitDataStructDef (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT PLATFORM_CONFIGURATION *PlatFormConfig
- );
-
-VOID
-memDefRet (
- VOID
- );
-
-BOOLEAN
-memDefTrue (
- VOID
- );
-
-BOOLEAN
-memDefFalse (
- VOID
- );
-#endif // _ADVANCED_API_H_
diff --git a/src/vendorcode/amd/agesa/Include/BrazosInstall.h b/src/vendorcode/amd/agesa/Include/BrazosInstall.h
deleted file mode 100644
index 6753965..0000000
--- a/src/vendorcode/amd/agesa/Include/BrazosInstall.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build options for a Brazos platform solution
- *
- * This file generates the defaults tables for the "Brazos" platform solution
- * set of processors. The documented build options are imported from a user
- * controlled file for processing.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Core
- * @e \$Revision: 40817 $ @e \$Date: 2010-10-28 03:28:12 +0800 (Thu, 28 Oct 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "CreateStruct.h"
-#include "cpuFeatures.h"
-#include "Table.h"
-#include "CommonReturns.h"
-#include "cpuEarlyInit.h"
-#include "cpuLateInit.h"
-#include "GnbInterface.h"
-
-/*****************************************************************************
- * Define the RELEASE VERSION string
- *
- * The Release Version string should identify the next planned release.
- * When a branch is made in preparation for a release, the release manager
- * should change/confirm that the branch version of this file contains the
- * string matching the desired version for the release. The trunk version of
- * the file should always contain a trailing 'X'. This will make sure that a
- * development build from trunk will not be confused for a released version.
- * The release manager will need to remove the trailing 'X' and update the
- * version string as appropriate for the release. The trunk copy of this file
- * should also be updated/incremented for the next expected version, + trailing 'X'
- ****************************************************************************/
- // This is the delivery package title, "BrazosPI"
- // This string MUST be exactly 8 characters long
-#define AGESA_PACKAGE_STRING {'O', 'n', 't', 'a', 'r', 'o', 'P', 'I'}
-
- // This is the release version number of the AGESA component
- // This string MUST be exactly 12 characters long
-#define AGESA_VERSION_STRING {'V', '1', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
-
-
-// The Brazos solution is defined to be family 0x14 in the FT1 socket.
-#define INSTALL_FT1_SOCKET_SUPPORT TRUE
-#define INSTALL_FAMILY_14_SUPPORT TRUE
-
-
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE (0)
-#define DFLT_SCRUB_L2_RATE (0)
-#define DFLT_SCRUB_L3_RATE (0)
-#define DFLT_SCRUB_IC_RATE (0)
-#define DFLT_SCRUB_DC_RATE (0)
-#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
-#define DFLT_VRM_SLEW_RATE (5000)
-
-
-// Instantiate all solution relevant data.
-#include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/Include/CommonReturns.h b/src/vendorcode/amd/agesa/Include/CommonReturns.h
deleted file mode 100644
index 9912edc..0000000
--- a/src/vendorcode/amd/agesa/Include/CommonReturns.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Common Return routines.
- *
- * Routines which do nothing, returning a result (preferably some version of zero) which
- * is consistent with "do nothing" or "default". Useful for function pointer tables.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Common
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _COMMON_RETURNS_H_
-#define _COMMON_RETURNS_H_
-
-
-/**
-* Return True
-*
-* @retval True Default case, no special action
-*/
-BOOLEAN
-CommonReturnTrue (void);
-
-/**
-* Return False.
-*
-* @retval FALSE Default case, no special action
-*/
-BOOLEAN
-CommonReturnFalse (void);
-
-/**
- * Return (UINT8)zero.
- *
- *
- * @retval zero None, or only case zero.
- */
-UINT8
-CommonReturnZero8 (void);
-
-/**
- * Return (UINT32)zero.
- *
- *
- * @retval zero None, or only case zero.
- */
-UINT32
-CommonReturnZero32 (void);
-
-/**
- * Return (UINT64)zero.
- *
- *
- * @retval zero None, or only case zero.
- */
-UINT64
-CommonReturnZero64 (void);
-
-/**
- * Return NULL
- *
- * @retval NULL pointer to nothing
- */
-VOID *
-CommonReturnNULL (void);
-
-/**
-* Return AGESA_SUCCESS.
-*
-* @retval AGESA_SUCCESS Success.
-*/
-AGESA_STATUS
-CommonReturnAgesaSuccess (void);
-
-/**
- * Do Nothing.
- *
- */
-VOID
-CommonVoid (void);
-
-/**
- * ASSERT if this routine is called.
- *
- */
-VOID
-CommonAssert (void);
-
-#endif // _COMMON_RETURNS_H_
diff --git a/src/vendorcode/amd/agesa/Include/DanNiInstall.h b/src/vendorcode/amd/agesa/Include/DanNiInstall.h
deleted file mode 100644
index c56f90c..0000000
--- a/src/vendorcode/amd/agesa/Include/DanNiInstall.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build options for a Danube + Nile platform solution
- *
- * This file generates the defaults tables for the "DanNi" platform solution
- * set of processors. The documented build options are imported from a user
- * controlled file for processing.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Core
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "CreateStruct.h"
-#include "cpuFeatures.h"
-#include "Table.h"
-#include "CommonReturns.h"
-#include "cpuEarlyInit.h"
-#include "cpuLateInit.h"
-#include "GnbInterfaceStub.h"
-
-/*****************************************************************************
- * Define the RELEASE VERSION string
- *
- * The Release Version string should identify the next planned release.
- * When a branch is made in preparation for a release, the release manager
- * should change/confirm that the branch version of this file contains the
- * string matching the desired version for the release. The trunk version of
- * the file should always contain a trailing 'X'. This will make sure that a
- * development build from trunk will not be confused for a released version.
- * The release manager will need to remove the trailing 'X' and update the
- * version string as appropriate for the release. The trunk copy of this file
- * should also be updated/incremented for the next expected version, + trailing 'X'
- ****************************************************************************/
- // This is the delivery package title, "DanNiPI "
- // This string MUST be exactly 8 characters long
-#define AGESA_PACKAGE_STRING {'D', 'a', 'n', 'N', 'i', 'P', 'I', ' '}
-
- // This is the release version number of the AGESA component
- // This string MUST be exactly 12 characters long
-#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '5', '.', '0', 'X', ' ', ' ', ' '}
-
-
-// The DanNi solution is defined to be family 0x10 in the S1g4 and ASB2 sockets.
-#define INSTALL_S1G4_SOCKET_SUPPORT TRUE
-#define INSTALL_ASB2_SOCKET_SUPPORT TRUE
-#define INSTALL_FAMILY_10_SUPPORT TRUE
-
-#ifdef BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT
- #if BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT == TRUE
- #undef INSTALL_S1G4_SOCKET_SUPPORT
- #define INSTALL_S1G4_SOCKET_SUPPORT FALSE
- #endif
-#endif
-
-#ifdef BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT
- #if BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT == TRUE
- #undef INSTALL_ASB2_SOCKET_SUPPORT
- #define INSTALL_ASB2_SOCKET_SUPPORT FALSE
- #endif
-#endif
-
-
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE (0)
-#define DFLT_SCRUB_L2_RATE (0x10)
-#define DFLT_SCRUB_L3_RATE (0x10)
-#define DFLT_SCRUB_IC_RATE (0)
-#define DFLT_SCRUB_DC_RATE (0x12)
-#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
-#define DFLT_VRM_SLEW_RATE (5000)
-
-
-// Instantiate all solution relevant data.
-#include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/Include/DanubeInstall.h b/src/vendorcode/amd/agesa/Include/DanubeInstall.h
deleted file mode 100644
index f2c91c4..0000000
--- a/src/vendorcode/amd/agesa/Include/DanubeInstall.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build options for a Danube platform solution
- *
- * This file generates the defaults tables for the "Danube" platform solution
- * set of processors. The documented build options are imported from a user
- * controlled file for processing.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Core
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "CreateStruct.h"
-#include "cpuFeatures.h"
-#include "Table.h"
-#include "CommonReturns.h"
-#include "cpuEarlyInit.h"
-#include "cpuLateInit.h"
-#include "GnbInterfaceStub.h"
-
-/*****************************************************************************
- * Define the RELEASE VERSION string
- *
- * The Release Version string should identify the next planned release.
- * When a branch is made in preparation for a release, the release manager
- * should change/confirm that the branch version of this file contains the
- * string matching the desired version for the release. The trunk version of
- * the file should always contain a trailing 'X'. This will make sure that a
- * development build from trunk will not be confused for a released version.
- * The release manager will need to remove the trailing 'X' and update the
- * version string as appropriate for the release. The trunk copy of this file
- * should also be updated/incremented for the next expected version, + trailing 'X'
- ****************************************************************************/
- // This is the delivery package title, "DanNiPI "
- // This string MUST be exactly 8 characters long
-#define AGESA_PACKAGE_STRING {'D', 'a', 'n', 'N', 'i', 'P', 'I', ' '}
-
- // This is the release version number of the AGESA component
- // This string MUST be exactly 12 characters long
-#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '5', '.', '0', 'X', ' ', ' ', ' '}
-
-
-// The Danube solution is defined to be family 0x10 in the S1g4 socket.
-#define INSTALL_S1G4_SOCKET_SUPPORT TRUE
-#define INSTALL_FAMILY_10_SUPPORT TRUE
-
-
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE (0)
-#define DFLT_SCRUB_L2_RATE (0x10)
-#define DFLT_SCRUB_L3_RATE (0)
-#define DFLT_SCRUB_IC_RATE (0)
-#define DFLT_SCRUB_DC_RATE (0x12)
-#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
-#define DFLT_VRM_SLEW_RATE (5000)
-
-
-// Instantiate all solution relevant data.
-#include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/Include/DevTestInstall.h b/src/vendorcode/amd/agesa/Include/DevTestInstall.h
deleted file mode 100644
index 9874551..0000000
--- a/src/vendorcode/amd/agesa/Include/DevTestInstall.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build options for a DevTest platform solution
- *
- * This file generates the defaults tables for the "DevTest" platform solution
- * set of processors. The documented build options are imported from a user
- * controlled file for processing.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Core
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "CreateStruct.h"
-#include "cpuFeatures.h"
-#include "Table.h"
-#include "CommonReturns.h"
-#include "cpuEarlyInit.h"
-#include "cpuLateInit.h"
-#include "GnbInterfaceStub.h"
-
-/*****************************************************************************
- * Define the RELEASE VERSION string
- *
- * The Release Version string should identify the next planned release.
- * When a branch is made in preparation for a release, the release manager
- * should change/confirm that the branch version of this file contains the
- * string matching the desired version for the release. The trunk version of
- * the file should always contain a trailing 'X'. This will make sure that a
- * development build from trunk will not be confused for a released version.
- * The release manager will need to remove the trailing 'X' and update the
- * version string as appropriate for the release. The trunk copy of this file
- * should also be updated/incremented for the next expected version, + trailing 'X'
- ****************************************************************************/
- // This is the delivery package title, "DevTest "
- // This string MUST be exactly 8 characters long
-#define AGESA_PACKAGE_STRING {'D', 'e', 'v', 'T', 'e', 's', 't', ' '}
-
- // This is the release version number of the AGESA component
- // This string MUST be exactly 12 characters long
-#define AGESA_VERSION_STRING {'V', '0', '.', '1', '.', '2', '.', '3', 'X', ' ', ' ', ' '}
-
-
-// The DevTest solution is defined to be everything that AGESA supports.
-#define INSTALL_C32_SOCKET_SUPPORT TRUE
-#define INSTALL_G34_SOCKET_SUPPORT TRUE
-#define INSTALL_S1G4_SOCKET_SUPPORT TRUE
-#define INSTALL_ASB2_SOCKET_SUPPORT TRUE
-#define INSTALL_FS1_SOCKET_SUPPORT TRUE
-#define INSTALL_FM1_SOCKET_SUPPORT TRUE
-#define INSTALL_FT1_SOCKET_SUPPORT TRUE
-#define INSTALL_AM3_SOCKET_SUPPORT TRUE
-#define INSTALL_FAMILY_10_SUPPORT TRUE
-#define INSTALL_FAMILY_12_SUPPORT TRUE
-#define INSTALL_FAMILY_14_SUPPORT TRUE
-#define INSTALL_FAMILY_15_SUPPORT TRUE
-
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE (0xFF)
-#define DFLT_SCRUB_L2_RATE (0x10)
-#define DFLT_SCRUB_L3_RATE (0x10)
-#define DFLT_SCRUB_IC_RATE (0)
-#define DFLT_SCRUB_DC_RATE (0x12)
-#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
-#define DFLT_VRM_SLEW_RATE (2500)
-
-
-// Instantiate all solution relevant data.
-#include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/Include/DragonInstall.h b/src/vendorcode/amd/agesa/Include/DragonInstall.h
deleted file mode 100644
index ee45b72..0000000
--- a/src/vendorcode/amd/agesa/Include/DragonInstall.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build options for a Dragon platform solution
- *
- * This file generates the defaults tables for the "Dragon" platform solution
- * set of processors. The documented build options are imported from a user
- * controlled file for processing.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Core
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "CreateStruct.h"
-#include "cpuFeatures.h"
-#include "Table.h"
-#include "CommonReturns.h"
-#include "cpuEarlyInit.h"
-#include "cpuLateInit.h"
-#include "GnbInterfaceStub.h"
-
-/*****************************************************************************
- * Define the RELEASE VERSION string
- *
- * The Release Version string should identify the next planned release.
- * When a branch is made in preparation for a release, the release manager
- * should change/confirm that the branch version of this file contains the
- * string matching the desired version for the release. The trunk version of
- * the file should always contain a trailing 'X'. This will make sure that a
- * development build from trunk will not be confused for a released version.
- * The release manager will need to remove the trailing 'X' and update the
- * version string as appropriate for the release. The trunk copy of this file
- * should also be updated/incremented for the next expected version, + trailing 'X'
- ****************************************************************************/
- // This is the delivery package title, "DragonPI"
- // This string MUST be exactly 8 characters long
-#define AGESA_PACKAGE_STRING {'D', 'r', 'a', 'g', 'o', 'n', 'P', 'I'}
-
- // This is the release version number of the AGESA component
- // This string MUST be exactly 12 characters long
-#define AGESA_VERSION_STRING {'V', '0', '.', '1', '.', '2', '.', '3', 'X', ' ', ' ', ' '}
-
-
-// The Danube solution is defined to be family 0x10 in the AM3 socket.
-#define INSTALL_AM3_SOCKET_SUPPORT TRUE
-#define INSTALL_FAMILY_10_SUPPORT TRUE
-
-
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE (0)
-#define DFLT_SCRUB_L2_RATE (0)
-#define DFLT_SCRUB_L3_RATE (0)
-#define DFLT_SCRUB_IC_RATE (0)
-#define DFLT_SCRUB_DC_RATE (0)
-#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
-#define DFLT_VRM_SLEW_RATE (2500)
-
-
-// Instantiate all solution relevant data.
-#include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/Include/Filecode.h b/src/vendorcode/amd/agesa/Include/Filecode.h
deleted file mode 100644
index 9ba1b29..0000000
--- a/src/vendorcode/amd/agesa/Include/Filecode.h
+++ /dev/null
@@ -1,849 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Collectively assign unique filecodes for assert and debug to each source file.
- *
- * Publish values for decorated filenames, which can be used for
- * ASSERT and debug support using a preprocessor define like:
- * @n <tt> \#define FILECODE MY_C_FILENAME_FILECODE </tt> @n
- * This file serves as a reference for debugging to associate the code and filename.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Include
- * @e \$Revision: 40742 $ @e \$Date: 2010-10-27 04:04:08 +0800 (Wed, 27 Oct 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _FILECODE_H_
-#define _FILECODE_H_
-
-#define UNASSIGNED_FILE_FILECODE (0xFFFF)
-
-/// For debug use in any Platform's options C file.
-/// Can be reused for platforms and image builds, since only one options file can be built.
-#define PLATFORM_SPECIFIC_OPTIONS_FILECODE (0xBBBB)
-
-
-#define PROC_GNB_COMMON_GNBLIBFEATURES_FILECODE (0xA001)
-#define PROC_GNB_GFX_FAMILY_0X12_F12GFXSERVICES_FILECODE (0xA002)
-#define PROC_GNB_GFX_FAMILY_0X14_F14GFXSERVICES_FILECODE (0xA003)
-#define PROC_GNB_GFX_GFXCONFIGDATA_FILECODE (0xA004)
-#define PROC_GNB_GFX_GFXDEBUGBAR_FILECODE (0xA005)
-#define PROC_GNB_GFX_GFXGMCINIT_FILECODE (0xA006)
-#define PROC_GNB_GFX_GFXINITATENVPOST_FILECODE (0xA010)
-#define PROC_GNB_GFX_GFXINITATMIDPOST_FILECODE (0xA011)
-#define PROC_GNB_GFX_GFXINITATPOST_FILECODE (0xA012)
-#define PROC_GNB_GFX_GFXINTEGRATEDINFOTABLEINIT_FILECODE (0xA013)
-#define PROC_GNB_GFX_GFXLIB_FILECODE (0xA014)
-#define PROC_GNB_GFX_GFXREGISTERACC_FILECODE (0xA015)
-#define PROC_GNB_GFX_GFXSTRAPSINIT_FILECODE (0xA016)
-#define PROC_GNB_GNBINITATEARLY_FILECODE (0xA017)
-#define PROC_GNB_GNBINITATENV_FILECODE (0xA020)
-#define PROC_GNB_GNBINITATLATE_FILECODE (0xA021)
-#define PROC_GNB_GNBINITATMID_FILECODE (0xA022)
-#define PROC_GNB_GNBINITATPOST_FILECODE (0xA023)
-#define PROC_GNB_GNBINITATRESET_FILECODE (0xA024)
-#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIB_FILECODE (0xA025)
-#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBCPUACC_FILECODE (0xA026)
-#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBHEAP_FILECODE (0xA027)
-#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBIOACC_FILECODE (0xA028)
-#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBMEMACC_FILECODE (0xA029)
-#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCI_FILECODE (0xA02A)
-#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCIACC_FILECODE (0xA030)
-#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXCARDINFO_FILECODE (0xA031)
-#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXENUMCONNECTORS_FILECODE (0xA032)
-#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXPOWERPLAYTABLE_FILECODE (0xA033)
-#define PROC_GNB_MODULES_GNBNBINITLIBV1_GNBNBINITLIBV1_FILECODE (0xA034)
-#define PROC_GNB_MODULES_GNBPCIEALIBV1_PCIEALIB_FILECODE (0xA035)
-#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGDATA_FILECODE (0xA036)
-#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGLIB_FILECODE (0xA037)
-#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIEINPUTPARSER_FILECODE (0xA038)
-#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIEMAPTOPOLOGY_FILECODE (0xA039)
-#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPM_FILECODE (0xA03A)
-#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMBLACKLIST_FILECODE (0xA03B)
-#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMEXITLATENCY_FILECODE (0xA03C)
-#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPHYSERVICES_FILECODE (0xA03D)
-#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPIFSERVICES_FILECODE (0xA03E)
-#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTREGACC_FILECODE (0xA03F)
-#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTSERVICES_FILECODE (0xA041)
-#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPOWERMGMT_FILECODE (0xA043)
-#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIESBLINK_FILECODE (0xA044)
-#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIESILICONSERVICES_FILECODE (0xA045)
-#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETIMER_FILECODE (0xA046)
-#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETOPOLOGYSERVICES_FILECODE (0xA047)
-#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEUTILITYLIB_FILECODE (0xA048)
-#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEWRAPPERREGACC_FILECODE (0xA049)
-#define PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIETRAINING_FILECODE (0xA04A)
-#define PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIEWORKAROUNDS_FILECODE (0xA04B)
-#define PROC_GNB_NB_FAMILY_0X12_F12NBPOWERGATE_FILECODE (0xA04C)
-#define PROC_GNB_NB_FAMILY_0X12_F12NBSERVICES_FILECODE (0xA04D)
-#define PROC_GNB_NB_FAMILY_0X12_F12NBSMU_FILECODE (0xA04E)
-#define PROC_GNB_NB_FAMILY_0X14_F14NBLCLKNCLKRATIO_FILECODE (0xA04F)
-#define PROC_GNB_NB_FAMILY_0X14_F14NBPOWERGATE_FILECODE (0xA050)
-#define PROC_GNB_NB_FAMILY_0X14_F14NBSERVICES_FILECODE (0xA051)
-#define PROC_GNB_NB_FAMILY_0X14_F14NBSMU_FILECODE (0xA052)
-#define PROC_GNB_NB_FEATURE_NBFUSETABLE_FILECODE (0xA053)
-#define PROC_GNB_NB_FEATURE_NBLCLKDPM_FILECODE (0xA054)
-#define PROC_GNB_NB_FAMILY_0X12_F12NBLCLKDPM_FILECODE (0xA055)
-#define PROC_GNB_NB_FAMILY_0X14_F14NBLCLKDPM_FILECODE (0xA056)
-#define PROC_GNB_NB_NBCONFIGDATA_FILECODE (0xA060)
-#define PROC_GNB_NB_NBINIT_FILECODE (0xA061)
-#define PROC_GNB_NB_NBINITATEARLY_FILECODE (0xA062)
-#define PROC_GNB_NB_NBINITATENV_FILECODE (0xA063)
-#define PROC_GNB_NB_NBINITATLATEPOST_FILECODE (0xA070)
-#define PROC_GNB_NB_NBINITATPOST_FILECODE (0xA071)
-#define PROC_GNB_NB_NBINITATRESET_FILECODE (0xA072)
-#define PROC_GNB_NB_NBPOWERMGMT_FILECODE (0xA073)
-#define PROC_GNB_NB_NBSMULIB_FILECODE (0xA074)
-#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIEALIB_FILECODE (0xA075)
-#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXCONFIG_FILECODE (0xA076)
-#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXSERVICES_FILECODE (0xA077)
-#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIEPHYSERVICES_FILECODE (0xA078)
-#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIEPIFSERVICES_FILECODE (0xA079)
-#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIEWRAPPERSERVICES_FILECODE (0xA07A)
-#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIEALIB_FILECODE (0xA07D)
-#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIECOMPLEXCONFIG_FILECODE (0xA07E)
-#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIECOMPLEXSERVICES_FILECODE (0xA07F)
-#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIEPHYSERVICES_FILECODE (0xA080)
-#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIEPIFSERVICES_FILECODE (0xA081)
-#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIEWRAPPERSERVICES_FILECODE (0xA082)
-#define PROC_GNB_PCIE_FEATURE_PCIEPOWERGATE_FILECODE (0xA083)
-#define PROC_GNB_PCIE_PCIEINIT_FILECODE (0xA084)
-#define PROC_GNB_PCIE_PCIEINITATEARLYPOST_FILECODE (0xA085)
-#define PROC_GNB_PCIE_PCIEINITATENV_FILECODE (0xA086)
-#define PROC_GNB_PCIE_PCIEINITATLATEPOST_FILECODE (0xA087)
-#define PROC_GNB_PCIE_PCIEINITATPOST_FILECODE (0xA088)
-#define PROC_GNB_PCIE_PCIELATEINIT_FILECODE (0xA089)
-#define PROC_GNB_PCIE_PCIEMISCLIB_FILECODE (0xA08A)
-#define PROC_GNB_PCIE_PCIEPORTINIT_FILECODE (0xA08B)
-#define PROC_GNB_PCIE_PCIEPORTLATEINIT_FILECODE (0xA08C)
-#define PROC_GNB_MODULES_GNBCABLESAFE_GNBCABLESAFE_FILECODE (0xA08D)
-#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGENV_FILECODE (0xA08E)
-#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGPOST_FILECODE (0xA08F)
-
-#define PROC_RECOVERY_GNB_GNBRECOVERY_FILECODE (0xAE01)
-#define PROC_RECOVERY_GNB_NBINITRECOVERY_FILECODE (0xAE02)
-
-// FCH
-#define PROC_COMMON_AMDFCH_FILECODE (0xB000)
-#define PROC_FCH_AZALIA_AZALIA_FILECODE (0xB001)
-#define PROC_FCH_AZALIA_AZALIARESET_FILECODE (0xB002)
-#define PROC_FCH_COMMON_ACPILIB_FILECODE (0xB010)
-#define PROC_FCH_COMMON_AMDSBLIB_FILECODE (0xB011)
-#define PROC_FCH_COMMON_FCHCOMMON_FILECODE (0xB012)
-#define PROC_FCH_COMMON_FCHCOMMONSMM_FILECODE (0xB013)
-#define PROC_FCH_COMMON_MEMLIB_FILECODE (0xB014)
-#define PROC_FCH_COMMON_PCILIB_FILECODE (0xB015)
-#define PROC_FCH_COMMON_SBPELIB_FILECODE (0xB016)
-#define PROC_FCH_GEC_FAMILY_HUDSON2_GEC_FILECODE (0xB020)
-#define PROC_FCH_GEC_FAMILY_HUDSON2_GECRESET_FILECODE (0xB021)
-#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HWACPI_FILECODE (0xB030)
-#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HWACPIRESET_FILECODE (0xB031)
-#define PROC_FCH_HWM_FAMILY_HUDSON2_HWM_FILECODE (0xB032)
-#define PROC_FCH_HWM_FAMILY_HUDSON2_HWMRESET_FILECODE (0xB033)
-#define PROC_FCH_IDE_IDE_FILECODE (0xB040)
-#define PROC_FCH_IMC_FAMILY_HUDSON2_IMC_FILECODE (0xB050)
-#define PROC_FCH_IMC_FAMILY_HUDSON2_IMCLIB_FILECODE (0xB051)
-#define PROC_FCH_IMC_FAMILY_HUDSON2_IMCRESET_FILECODE (0xB052)
-#define PROC_FCH_IMC_FAMILY_HUDSON2_SBEC_FILECODE (0xB053)
-#define PROC_FCH_IMC_FAMILY_HUDSON2_SBECRESET_FILECODE (0xB054)
-#define PROC_FCH_INTERFACE_INITRESETDEF_FILECODE (0xB060)
-#define PROC_FCH_INTERFACE_INITENVDEF_FILECODE (0xB061)
-#define PROC_FCH_INTERFACE_FCHINITRESET_FILECODE (0xB062)
-#define PROC_FCH_INTERFACE_FCHINITENV_FILECODE (0xB063)
-#define PROC_FCH_INTERFACE_FCHINITLATE_FILECODE (0xB064)
-#define PROC_FCH_INTERFACE_FCHINITMID_FILECODE (0xB065)
-#define PROC_FCH_INTERFACE_FCHINITS3_FILECODE (0xB066)
-#define PROC_FCH_INTERFACE_FCHTASKLAUNCHER_FILECODE (0xB067)
-#define PROC_FCH_IR_IR_FILECODE (0xB070)
-#define PROC_FCH_PCIB_PCIB_FILECODE (0xB080)
-#define PROC_FCH_PCIB_PCIBRESET_FILECODE (0xB081)
-#define PROC_FCH_PCIE_FAMILY_HUDSON2_AB_FILECODE (0xB090)
-#define PROC_FCH_PCIE_FAMILY_HUDSON2_ABRESET_FILECODE (0xB091)
-#define PROC_FCH_PCIE_FAMILY_HUDSON2_GPP_FILECODE (0xB092)
-#define PROC_FCH_PCIE_FAMILY_HUDSON2_GPPHP_FILECODE (0xB093)
-#define PROC_FCH_PCIE_FAMILY_HUDSON2_GPPLIB_FILECODE (0xB094)
-#define PROC_FCH_PCIE_FAMILY_HUDSON2_GPPRESET_FILECODE (0xB095)
-#define PROC_FCH_PCIE_FAMILY_HUDSON2_PCIE_FILECODE (0xB096)
-#define PROC_FCH_PCIE_FAMILY_HUDSON2_PCIERESET_FILECODE (0xB097)
-#define PROC_FCH_SATA_FAMILY_HUDSON2_AHCI_FILECODE (0xB0A0)
-#define PROC_FCH_SATA_FAMILY_HUDSON2_AHCILIB_FILECODE (0xB0A1)
-#define PROC_FCH_SATA_FAMILY_HUDSON2_IDE2AHCI_FILECODE (0xB0A2)
-#define PROC_FCH_SATA_FAMILY_HUDSON2_IDE2AHCILIB_FILECODE (0xB0A3)
-#define PROC_FCH_SATA_FAMILY_HUDSON2_RAID_FILECODE (0xB0A4)
-#define PROC_FCH_SATA_FAMILY_HUDSON2_RAIDLIB_FILECODE (0xB0A5)
-#define PROC_FCH_SATA_FAMILY_HUDSON2_SATA_FILECODE (0xB0A6)
-#define PROC_FCH_SATA_FAMILY_HUDSON2_SATAIDE_FILECODE (0xB0A7)
-#define PROC_FCH_SATA_FAMILY_HUDSON2_SATAIDELIB_FILECODE (0xB0A8)
-#define PROC_FCH_SATA_FAMILY_HUDSON2_SATALIB_FILECODE (0xB0A9)
-#define PROC_FCH_SATA_FAMILY_HUDSON2_SATARESET_FILECODE (0xB0AA)
-#define PROC_FCH_SBUSB_FAMILY_HUDSON2_EHCI_FILECODE (0xB0B0)
-#define PROC_FCH_SBUSB_FAMILY_HUDSON2_EHCIRESET_FILECODE (0xB0B1)
-#define PROC_FCH_SBUSB_FAMILY_HUDSON2_OHCI_FILECODE (0xB0B2)
-#define PROC_FCH_SBUSB_FAMILY_HUDSON2_OHCIRESET_FILECODE (0xB0B3)
-#define PROC_FCH_SBUSB_FAMILY_HUDSON2_USB_FILECODE (0xB0B4)
-#define PROC_FCH_SBUSB_FAMILY_HUDSON2_USBRESET_FILECODE (0xB0B5)
-#define PROC_FCH_SBUSB_FAMILY_HUDSON2_XHCI_FILECODE (0xB0B6)
-#define PROC_FCH_SBUSB_FAMILY_HUDSON2_XHCIRESET_FILECODE (0xB0B7)
-#define PROC_FCH_SD_SD_FILECODE (0xB0C0)
-#define PROC_FCH_SPI_LPC_FILECODE (0xB0D0)
-#define PROC_FCH_SPI_LPCRESET_FILECODE (0xB0D1)
-#define PROC_FCH_SPI_SPI_FILECODE (0xB0D2)
-#define PROC_FCH_SPI_SPIRESET_FILECODE (0xB0D3)
-
-#define UEFI_DXE_AMDSBDXE_AMDSBDXE_FILECODE (0xB200)
-#define UEFI_DXE_AMDSBWHEA_AMDSBWHEA_FILECODE (0xB210)
-#define UEFI_DXE_AMDSBWHEA_BERTTABLE_FILECODE (0xB211)
-#define UEFI_DXE_AMDSBWHEA_EINJTABLE_FILECODE (0xB212)
-#define UEFI_DXE_AMDSBWHEA_ERSTTABLE_FILECODE (0xB213)
-#define UEFI_DXE_AMDSBWHEA_HESTTABLE_FILECODE (0xB214)
-#define UEFI_DXE_CF9RESET_CF9RESET_FILECODE (0xB220)
-#define UEFI_DXE_CF9RESET_IA32_IA32CF9RESET_FILECODE (0xB221)
-#define UEFI_DXE_CF9RESET_X64_X64CF9RESET_FILECODE (0xB222)
-#define UEFI_DXE_LEGACYINTERRUPT_LEGACYINTERRUPT_FILECODE (0xB230)
-#define UEFI_DXE_SMMCONTROL_SMMCONTROL_FILECODE (0xB240)
-#define UEFI_LIBRARY_DECCAN_FCHSMMLIB_FCHDXECOMMON_FILECODE (0xB250)
-#define UEFI_LIBRARY_DECCAN_FCHSMMLIB_FCHSMMLIB_FILECODE (0xB251)
-#define UEFI_LIBRARY_DECCAN_FCHDXELIB_FCHDXELIB_FILECODE (0xB252)
-#define UEFI_PEI_AMDSBPEI_AMDSBPEI_FILECODE (0xB260)
-#define UEFI_PEI_AMDSBPEI_SBRESET_FILECODE (0xB261)
-#define UEFI_PEI_AMDSBPEI_SBSTALL_FILECODE (0xB262)
-#define UEFI_PEI_SMBUS_SMBUS_FILECODE (0xB270)
-#define UEFI_SMM_AMDSBSMM_AMDSBSMM_FILECODE (0xB280)
-#define UEFI_SMM_AMDSBSMM_GECSMI_FILECODE (0xB281)
-#define UEFI_SMM_AMDSBSMM_GPESMI_FILECODE (0xB282)
-#define UEFI_SMM_AMDSBSMM_IOTRAPSMI_FILECODE (0xB283)
-#define UEFI_SMM_AMDSBSMM_MISCSMI_FILECODE (0xB284)
-#define UEFI_SMM_AMDSBSMM_PERIODICTIMERSMI_FILECODE (0xB285)
-#define UEFI_SMM_AMDSBSMM_POWERBUTTONSMI_FILECODE (0xB286)
-#define UEFI_SMM_AMDSBSMM_SWSMI_FILECODE (0xB287)
-#define UEFI_SMM_AMDSBSMM_SXSMI_FILECODE (0xB288)
-#define UEFI_DXE_SMBUS_SMBUSLIGHT_FILECODE (0xB2A0)
-#define UEFI_SMM_AMDSBSMMDISPATCHER_AMDSBSMMDISPATCHER_FILECODE (0xB290)
-#define UEFI_SMM_AMDSBSMMGECROMDISPATCHER_AMDSBSMMGECROMDISPATCHER_FILECODE (0xB291)
-#define UEFI_SMM_AMDSBSMMGPEDISPATCHER_AMDSBSMMGPEDISPATCHER_FILECODE (0xB292)
-#define UEFI_SMM_AMDSBSMMIOTRAPDISPATCHER_AMDSBSMMIOTRAPDISPATCHER_FILECODE (0xB293)
-#define UEFI_SMM_AMDSBSMMMISCDISPATCHER_AMDSBSMMMISCDISPATCHER_FILECODE (0xB294)
-#define UEFI_SMM_AMDSBSMMPERIODICALDISPATCHER_AMDSBSMMPERIODICALDISPATCHER_FILECODE (0xB295)
-#define UEFI_SMM_AMDSBSMMPWRBTNDISPATCHER_AMDSBSMMPWRBTNDISPATCHER_FILECODE (0xB296)
-#define UEFI_SMM_AMDSBSMMSWDISPATCHER_AMDSBSMMSWDISPATCHER_FILECODE (0xB297)
-#define UEFI_SMM_AMDSBSMMSXDISPATCHER_AMDSBSMMSXDISPATCHER_FILECODE (0xB298)
-#define UEFI_SMM_AMDSBSMMUSBDISPATCHER_AMDSBSMMUSBDISPATCHER_FILECODE (0xB299)
-
-#define LIB_AMDLIB_FILECODE (0xC001)
-
-#define LEGACY_PROC_AGESACALLOUTS_FILECODE (0xC010)
-#define LEGACY_PROC_HOBTRANSFER_FILECODE (0xC011)
-#define LEGACY_PROC_DISPATCHER_FILECODE (0xC012)
-
-#define UEFI_DXE_AMDAGESADXEDRIVER_AMDAGESADXEDRIVER_FILECODE (0xC120)
-
-#define UEFI_PEI_AMDINITPOSTPEIM_AMDINITPOSTPEIM_FILECODE (0xC140)
-#define UEFI_PEI_AMDPROCESSORINITPEIM_AMDPROCESSORINITPEIM_FILECODE (0xC141)
-#define UEFI_PEI_AMDRESETMANAGER_AMDRESETMANAGER_FILECODE (0xC142)
-#define UEFI_PROC_HOBTRANSFERUEFI_FILECODE (0xC162)
-
-#define PROC_COMMON_AMDINITEARLY_FILECODE (0xC020)
-#define PROC_COMMON_AMDINITENV_FILECODE (0xC021)
-#define PROC_COMMON_AMDINITLATE_FILECODE (0xC022)
-#define PROC_COMMON_AMDINITMID_FILECODE (0xC023)
-#define PROC_COMMON_AMDINITPOST_FILECODE (0xC024)
-#define PROC_COMMON_AMDINITRECOVERY_FILECODE (0xC025)
-#define PROC_COMMON_AMDINITRESET_FILECODE (0xC026)
-#define PROC_COMMON_AMDINITRESUME_FILECODE (0xC027)
-#define PROC_COMMON_AMDS3LATERESTORE_FILECODE (0xC028)
-#define PROC_COMMON_AMDS3SAVE_FILECODE (0xC029)
-#define PROC_COMMON_AMDLATERUNAPTASK_FILECODE (0xC02A)
-
-#define PROC_COMMON_COMMONRETURNS_FILECODE (0xC0C0)
-#define PROC_COMMON_CREATESTRUCT_FILECODE (0xC0D0)
-#define PROC_COMMON_COMMONINITS_FILECODE (0xC0F0)
-#define PROC_COMMON_S3RESTORESTATE_FILECODE (0xC0F8)
-#define PROC_COMMON_S3SAVESTATE_FILECODE (0xC0F9)
-
-#define PROC_CPU_CPUAPICUTILITIES_FILECODE (0xC401)
-#define PROC_CPU_CPUBRANDID_FILECODE (0xC402)
-#define PROC_CPU_TABLE_FILECODE (0xC403)
-#define PROC_CPU_CPUEARLYINIT_FILECODE (0xC405)
-#define PROC_CPU_CPUEVENTLOG_FILECODE (0xC406)
-#define PROC_CPU_CPUFAMILYTRANSLATION_FILECODE (0xC407)
-#define PROC_CPU_CPUGENERALSERVICES_FILECODE (0xC408)
-#define PROC_CPU_CPUINITEARLYTABLE_FILECODE (0xC409)
-#define PROC_CPU_CPULATEINIT_FILECODE (0xC40A)
-#define PROC_CPU_CPUMICROCODEPATCH_FILECODE (0xC40B)
-#define PROC_CPU_CPUWARMRESET_FILECODE (0xC40C)
-#define PROC_CPU_HEAPMANAGER_FILECODE (0xC40D)
-#define PROC_CPU_CPUBIST_FILECODE (0xC40E)
-
-#define PROC_CPU_CPUPOSTINIT_FILECODE (0xC420)
-#define PROC_CPU_CPUPOWERMGMT_FILECODE (0xC430)
-#define PROC_CPU_CPUPOWERMGMTMULTISOCKET_FILECODE (0xC431)
-#define PROC_CPU_CPUPOWERMGMTSINGLESOCKET_FILECODE (0xC432)
-#define PROC_CPU_S3_FILECODE (0xC460)
-
-// Family 10h
-#define PROC_CPU_FAMILY_0X10_CPUCOMMONF10UTILITIES_FILECODE (0xC801)
-#define PROC_CPU_FAMILY_0X10_CPUF10BRANDID_FILECODE (0xC802)
-#define PROC_CPU_FAMILY_0X10_CPUF10CACHEDEFAULTS_FILECODE (0xC803)
-#define PROC_CPU_FAMILY_0X10_CPUF10CACHEFLUSHONHALT_FILECODE (0xC804)
-#define PROC_CPU_FAMILY_0X10_CPUF10DMI_FILECODE (0xC805)
-#define PROC_CPU_FAMILY_0X10_CPUF10EARLYINIT_FILECODE (0xC806)
-#define PROC_CPU_FAMILY_0X10_CPUF10FEATURELEVELING_FILECODE (0xC807)
-#define PROC_CPU_FAMILY_0X10_CPUF10HTPHYTABLES_FILECODE (0xC808)
-#define PROC_CPU_FAMILY_0X10_CPUF10MSRTABLES_FILECODE (0xC809)
-#define PROC_CPU_FAMILY_0X10_CPUF10PCITABLES_FILECODE (0xC80A)
-#define PROC_CPU_FAMILY_0X10_CPUF10POWERCHECK_FILECODE (0xC80B)
-#define PROC_CPU_FAMILY_0X10_CPUF10POWERMGMTSYSTEMTABLES_FILECODE (0xC80C)
-#define PROC_CPU_FAMILY_0X10_CPUF10POWERPLANE_FILECODE (0xC80D)
-#define PROC_CPU_FAMILY_0X10_CPUF10SOFTWARETHERMAL_FILECODE (0xC80E)
-#define PROC_CPU_FAMILY_0X10_CPUF10UTILITIES_FILECODE (0xC80F)
-#define PROC_CPU_FAMILY_0X10_CPUF10WHEAINITDATATABLES_FILECODE (0xC810)
-#define PROC_CPU_FAMILY_0X10_CPUF10PSTATE_FILECODE (0xC811)
-#define PROC_CPU_FAMILY_0X10_CPUF10CPB_FILECODE (0xC812)
-#define PROC_CPU_FAMILY_0X10_CPUF10WORKAROUNDSTABLE_FILECODE (0xC813)
-#define PROC_CPU_FAMILY_0X10_F10PMNBCOFVIDINIT_FILECODE (0xC820)
-#define PROC_CPU_FAMILY_0X10_F10SINGLELINKPCITABLES_FILECODE (0xC821)
-#define PROC_CPU_FAMILY_0X10_F10MULTILINKPCITABLES_FILECODE (0xC822)
-#define PROC_CPU_FAMILY_0X10_F10PMNBPSTATEINIT_FILECODE (0xC823)
-#define PROC_CPU_FAMILY_0X10_F10PMASYMBOOSTINIT_FILECODE (0xC824)
-#define PROC_CPU_FAMILY_0X10_F10INITEARLYTABLE_FILECODE (0xC825)
-#define PROC_CPU_FAMILY_0X10_F10PMDUALPLANEONLYSUPPORT_FILECODE (0xC826)
-#define PROC_CPU_FAMILY_0X10_F10IOCSTATE_FILECODE (0xC827)
-#define PROC_CPU_FAMILY_0X10_REVC_F10REVCUTILITIES_FILECODE (0xC830)
-#define PROC_CPU_FAMILY_0X10_REVC_F10REVCHWC1E_FILECODE (0xC831)
-#define PROC_CPU_FAMILY_0X10_REVC_F10REVCSWC1E_FILECODE (0xC832)
-#define PROC_CPU_FAMILY_0X10_REVC_F10REVCPCITABLES_FILECODE (0xC833)
-#define PROC_CPU_FAMILY_0X10_REVC_F10REVCMSRTABLES_FILECODE (0xC834)
-#define PROC_CPU_FAMILY_0X10_REVC_F10REVCHTPHYTABLES_FILECODE (0xC835)
-#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLHTPHYTABLES_FILECODE (0xC836)
-#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLLOGICALIDTABLES_FILECODE (0xC837)
-#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMICROCODEPATCHTABLES_FILECODE (0xC838)
-#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMSRTABLES_FILECODE (0xC839)
-#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLEQUIVALENCETABLE_FILECODE (0xC83A)
-#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLPCITABLES_FILECODE (0xC83B)
-#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLCACHEFLUSHONHALT_FILECODE (0xC83C)
-#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAHTPHYTABLES_FILECODE (0xC83D)
-#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DALOGICALIDTABLES_FILECODE (0xC83E)
-#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMICROCODEPATCHTABLES_FILECODE (0xC83F)
-#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMSRTABLES_FILECODE (0xC840)
-#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAEQUIVALENCETABLE_FILECODE (0xC841)
-#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAPCITABLES_FILECODE (0xC842)
-#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DACACHEFLUSHONHALT_FILECODE (0xC843)
-#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBHTPHYTABLES_FILECODE (0xC844)
-#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBLOGICALIDTABLES_FILECODE (0xC845)
-#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMICROCODEPATCHTABLES_FILECODE (0xC846)
-#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMSRTABLES_FILECODE (0xC847)
-#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBEQUIVALENCETABLE_FILECODE (0xC848)
-#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBPCITABLES_FILECODE (0xC849)
-#define PROC_CPU_FAMILY_0X10_REVD_F10REVDUTILITIES_FILECODE (0xC850)
-#define PROC_CPU_FAMILY_0X10_REVD_F10REVDMSGBASEDC1E_FILECODE (0xC851)
-#define PROC_CPU_FAMILY_0X10_REVD_F10REVDHTASSIST_FILECODE (0xC852)
-#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYHTPHYTABLES_FILECODE (0xC853)
-#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYINITEARLYTABLE_FILECODE (0xC854)
-#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYLOGICALIDTABLES_FILECODE (0xC855)
-#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMICROCODEPATCHTABLES_FILECODE (0xC856)
-#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMSRTABLES_FILECODE (0xC857)
-#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYEQUIVALENCETABLE_FILECODE (0xC858)
-#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYPCITABLES_FILECODE (0xC859)
-#define PROC_CPU_FAMILY_0X10_REVE_F10REVEUTILITIES_FILECODE (0xC860)
-#define PROC_CPU_FAMILY_0X10_REVE_F10REVEMSRTABLES_FILECODE (0xC861)
-#define PROC_CPU_FAMILY_0X10_REVE_F10REVEPCITABLES_FILECODE (0xC862)
-#define PROC_CPU_FAMILY_0X10_REVE_F10REVEHTPHYTABLES_FILECODE (0xC863)
-#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHEQUIVALENCETABLE_FILECODE (0xC864)
-#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHHTPHYTABLES_FILECODE (0xC865)
-#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHLOGICALIDTABLES_FILECODE (0xC866)
-#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHMICROCODEPATCHTABLES_FILECODE (0xC867)
-
-// Family 12h
-#define PROC_CPU_FAMILY_0X12_CPUCOMMONF12UTILITIES_FILECODE (0xC901)
-#define PROC_CPU_FAMILY_0X12_CPUF12BRANDID_FILECODE (0xC902)
-#define PROC_CPU_FAMILY_0X12_CPUF12CACHEDEFAULTS_FILECODE (0xC903)
-#define PROC_CPU_FAMILY_0X12_CPUF12DMI_FILECODE (0xC904)
-#define PROC_CPU_FAMILY_0X12_CPUF12MSRTABLES_FILECODE (0xC905)
-#define PROC_CPU_FAMILY_0X12_CPUF12EARLYNBPSTATEINIT_FILECODE (0xC906)
-#define PROC_CPU_FAMILY_0X12_CPUF12PCITABLES_FILECODE (0xC907)
-#define PROC_CPU_FAMILY_0X12_CPUF12POWERCHECK_FILECODE (0xC908)
-#define PROC_CPU_FAMILY_0X12_CPUF12POWERMGMTSYSTEMTABLES_FILECODE (0xC909)
-#define PROC_CPU_FAMILY_0X12_CPUF12POWERPLANE_FILECODE (0xC90A)
-#define PROC_CPU_FAMILY_0X12_CPUF12SOFTWARETHERMAL_FILECODE (0xC90B)
-#define PROC_CPU_FAMILY_0X12_CPUF12UTILITIES_FILECODE (0xC90C)
-#define PROC_CPU_FAMILY_0X12_CPUF12WHEAINITDATATABLES_FILECODE (0xC90D)
-#define PROC_CPU_FAMILY_0X12_CPUF12PSTATE_FILECODE (0xC90E)
-#define PROC_CPU_FAMILY_0X12_F12C6STATE_FILECODE (0xC90F)
-#define PROC_CPU_FAMILY_0X12_F12CPB_FILECODE (0xC910)
-#define PROC_CPU_FAMILY_0X12_F12IOCSTATE_FILECODE (0xC911)
-#define PROC_CPU_FAMILY_0X12_LN_F12LNLOGICALIDTABLES_FILECODE (0xC921)
-#define PROC_CPU_FAMILY_0X12_LN_F12LNMICROCODEPATCHTABLES_FILECODE (0xC922)
-#define PROC_CPU_FAMILY_0X12_LN_F12LNEQUIVALENCETABLE_FILECODE (0xC923)
-#define PROC_CPU_FAMILY_0X12_CPUF12PERCOREPCITABLES_FILECODE (0xC924)
-#define PROC_CPU_FAMILY_0X12_LN_F12LNEARLYSAMPLES_FILECODE (0xC925)
-
-// Family 14h
-#define PROC_CPU_FAMILY_0X14_CPUCOMMONF14UTILITIES_FILECODE (0xCA01)
-#define PROC_CPU_FAMILY_0X14_CPUF14BRANDID_FILECODE (0xCA02)
-#define PROC_CPU_FAMILY_0X14_CPUF14CACHEDEFAULTS_FILECODE (0xCA03)
-#define PROC_CPU_FAMILY_0X14_CPUF14DMI_FILECODE (0xCA04)
-#define PROC_CPU_FAMILY_0X14_CPUF14MSRTABLES_FILECODE (0xCA05)
-#define PROC_CPU_FAMILY_0X14_CPUF14PCITABLES_FILECODE (0xCA06)
-#define PROC_CPU_FAMILY_0X14_CPUF14POWERCHECK_FILECODE (0xCA07)
-#define PROC_CPU_FAMILY_0X14_CPUF14POWERMGMTSYSTEMTABLES_FILECODE (0xCA08)
-#define PROC_CPU_FAMILY_0X14_CPUF14POWERPLANE_FILECODE (0xCA09)
-#define PROC_CPU_FAMILY_0X14_CPUF14SOFTWARETHERMAL_FILECODE (0xCA0A)
-#define PROC_CPU_FAMILY_0X14_CPUF14UTILITIES_FILECODE (0xCA0B)
-#define PROC_CPU_FAMILY_0X14_CPUF14WHEAINITDATATABLES_FILECODE (0xCA0C)
-#define PROC_CPU_FAMILY_0X14_CPUF14PSTATE_FILECODE (0xCA0D)
-#define PROC_CPU_FAMILY_0X14_F14C6STATE_FILECODE (0xCA0E)
-#define PROC_CPU_FAMILY_0X14_F14IOCSTATE_FILECODE (0xCA0F)
-#define PROC_CPU_FAMILY_0X14_ON_F14ONLOGICALIDTABLES_FILECODE (0xCA21)
-#define PROC_CPU_FAMILY_0X14_ON_F14ONMICROCODEPATCHTABLES_FILECODE (0xCA22)
-#define PROC_CPU_FAMILY_0X14_ON_F14ONEQUIVALENCETABLE_FILECODE (0xCA23)
-#define PROC_CPU_FAMILY_0X14_ON_F14ONINITEARLYTABLE_FILECODE (0xCA24)
-#define PROC_CPU_FAMILY_0X14_CPUF14PERCOREPCITABLES_FILECODE (0xCA25)
-#define PROC_CPU_FAMILY_0X14_ON_F14ONEARLYSAMPLES_FILECODE (0xCA26)
-
-// Family 15h
-#define PROC_CPU_FAMILY_0X15_CPUCOMMONF15UTILITIES_FILECODE (0xCB01)
-#define PROC_CPU_FAMILY_0X15_CPUF15BRANDID_FILECODE (0xCB02)
-#define PROC_CPU_FAMILY_0X15_CPUF15CACHEDEFAULTS_FILECODE (0xCB03)
-#define PROC_CPU_FAMILY_0X15_CPUF15CACHEFLUSHONHALT_FILECODE (0xCB04)
-#define PROC_CPU_FAMILY_0X15_CPUF15COREAFTERRESET_FILECODE (0xCB05)
-#define PROC_CPU_FAMILY_0X15_CPUF15DMI_FILECODE (0xCB06)
-#define PROC_CPU_FAMILY_0X15_CPUF15FEATURELEVELING_FILECODE (0xCB07)
-#define PROC_CPU_FAMILY_0X15_CPUF15HTPHYTABLES_FILECODE (0xCB08)
-#define PROC_CPU_FAMILY_0X15_CPUF15MSRTABLES_FILECODE (0xCB09)
-#define PROC_CPU_FAMILY_0X15_CPUF15NBAFTERRESET_FILECODE (0xCB0A)
-#define PROC_CPU_FAMILY_0X15_CPUF15PCITABLES_FILECODE (0xCB0B)
-#define PROC_CPU_FAMILY_0X15_CPUF15POWERCHECK_FILECODE (0xCB0C)
-#define PROC_CPU_FAMILY_0X15_CPUF15POWERMGMTSYSTEMTABLES_FILECODE (0xCB0D)
-#define PROC_CPU_FAMILY_0X15_CPUF15POWERPLANE_FILECODE (0xCB0E)
-#define PROC_CPU_FAMILY_0X15_CPUF15SOFTWARETHERMAL_FILECODE (0xCB0F)
-#define PROC_CPU_FAMILY_0X15_CPUF15UTILITIES_FILECODE (0xCB10)
-#define PROC_CPU_FAMILY_0X15_CPUF15WHEAINITDATATABLES_FILECODE (0xCB11)
-#define PROC_CPU_FAMILY_0X15_CPUF15PSTATE_FILECODE (0xCB12)
-#define PROC_CPU_FAMILY_0X15_F15PMNBCOFVIDINIT_FILECODE (0xCB13)
-#define PROC_CPU_FAMILY_0X15_F15SINGLELINKPCITABLES_FILECODE (0xCB14)
-#define PROC_CPU_FAMILY_0X15_F15MULTILINKPCITABLES_FILECODE (0xCB15)
-#define PROC_CPU_FAMILY_0X15_F15C6STATE_FILECODE (0xCB16)
-#define PROC_CPU_FAMILY_0X15_F15CPB_FILECODE (0xCB17)
-#define PROC_CPU_FAMILY_0X15_F15INITEARLYTABLE_FILECODE (0xCB18)
-#define PROC_CPU_FAMILY_0X15_F15LOWPWRPSTATE_FILECODE (0xCB19)
-#define PROC_CPU_FAMILY_0X15_CPUF15WORKAROUNDSTABLE_FILECODE (0xCB1A)
-#define PROC_CPU_FAMILY_0X15_F15IOCSTATE_FILECODE (0xCB1B)
-#define PROC_CPU_FAMILY_0X15_OR_F15ORHTASSIST_FILECODE (0xCB30)
-#define PROC_CPU_FAMILY_0X15_OR_F15ORMSGBASEDC1E_FILECODE (0xCB31)
-#define PROC_CPU_FAMILY_0X15_OR_F15ORLOGICALIDTABLES_FILECODE (0xCB32)
-#define PROC_CPU_FAMILY_0X15_OR_F15ORMICROCODEPATCHTABLES_FILECODE (0xCB33)
-#define PROC_CPU_FAMILY_0X15_OR_F15ORMSRTABLES_FILECODE (0xCB34)
-#define PROC_CPU_FAMILY_0X15_OR_F15ORSHAREDMSRTABLE_FILECODE (0xCB35)
-#define PROC_CPU_FAMILY_0X15_OR_F15OREQUIVALENCETABLE_FILECODE (0xCB36)
-#define PROC_CPU_FAMILY_0X15_OR_F15ORPCITABLES_FILECODE (0xCB37)
-
-
-
-#define PROC_CPU_FEATURE_CPUCACHEFLUSHONHALT_FILECODE (0xDC01)
-#define PROC_CPU_FEATURE_CPUCACHEINIT_FILECODE (0xDC02)
-#define PROC_CPU_FEATURE_CPUDMI_FILECODE (0xDC10)
-#define PROC_CPU_FEATURE_CPUFEATURELEVELING_FILECODE (0xDC20)
-#define PROC_CPU_FEATURE_CPUHTASSIST_FILECODE (0xDC30)
-#define PROC_CPU_FEATURE_CPUPSTATEGATHER_FILECODE (0xDC41)
-#define PROC_CPU_FEATURE_CPUPSTATELEVELING_FILECODE (0xDC42)
-#define PROC_CPU_FEATURE_CPUPSTATETABLES_FILECODE (0xDC43)
-#define PROC_CPU_FEATURE_CPUSLIT_FILECODE (0xDC50)
-#define PROC_CPU_FEATURE_CPUSRAT_FILECODE (0xDC60)
-#define PROC_CPU_FEATURE_CPUWHEA_FILECODE (0xDC70)
-#define PROC_CPU_FEATURE_CPUHWC1E_FILECODE (0xDC80)
-#define PROC_CPU_FEATURE_CPUSWC1E_FILECODE (0xDC81)
-#define PROC_CPU_FEATURE_CPUC6STATE_FILECODE (0xDC82)
-#define PROC_CPU_FEATURE_CPUCPB_FILECODE (0xDC83)
-#define PROC_CPU_FEATURE_CPULOWPWRPSTATE_FILECODE (0xDC84)
-#define PROC_CPU_FEATURE_CPUIOCSTATE_FILECODE (0xDC85)
-#define PROC_CPU_FEATURE_CPUFEATURES_FILECODE (0xDC90)
-#define PROC_CPU_FEATURE_CPUMSGBASEDC1E_FILECODE (0xDCA0)
-#define PROC_CPU_FEATURE_CPUCORELEVELING_FILECODE (0xDCB0)
-#define PROC_CPU_FEATURE_PRESERVEMAILBOX_FILECODE (0xDCC0)
-
-#define PROC_RECOVERY_CPU_CPURECOVERY_FILECODE (0xDE01)
-
-#define PROC_HT_FEATURES_HTFEATSETS_FILECODE (0xE001)
-#define PROC_HT_FEATURES_HTFEATDYNAMICDISCOVERY_FILECODE (0xE002)
-#define PROC_HT_FEATURES_HTFEATGANGING_FILECODE (0xE003)
-#define PROC_HT_FEATURES_HTFEATNONCOHERENT_FILECODE (0xE004)
-#define PROC_HT_FEATURES_HTFEATOPTIMIZATION_FILECODE (0xE005)
-#define PROC_HT_FEATURES_HTFEATROUTING_FILECODE (0xE006)
-#define PROC_HT_FEATURES_HTFEATSUBLINKS_FILECODE (0xE007)
-#define PROC_HT_FEATURES_HTFEATTRAFFICDISTRIBUTION_FILECODE (0xE008)
-#define PROC_HT_FEATURES_HTIDS_FILECODE (0xE009)
-#define PROC_HT_HTFEAT_FILECODE (0xE021)
-#define PROC_HT_HTINTERFACE_FILECODE (0xE022)
-#define PROC_HT_HTINTERFACECOHERENT_FILECODE (0xE023)
-#define PROC_HT_HTINTERFACEGENERAL_FILECODE (0xE024)
-#define PROC_HT_HTINTERFACENONCOHERENT_FILECODE (0xE025)
-#define PROC_HT_HTMAIN_FILECODE (0xE026)
-#define PROC_HT_HTNOTIFY_FILECODE (0xE027)
-#define PROC_HT_HTGRAPH_HTGRAPH_FILECODE (0xE028)
-#define PROC_HT_HTNB_FILECODE (0xE081)
-#define PROC_HT_NBCOMMON_HTNBCOHERENT_FILECODE (0xE082)
-#define PROC_HT_NBCOMMON_HTNBNONCOHERENT_FILECODE (0xE083)
-#define PROC_HT_NBCOMMON_HTNBOPTIMIZATION_FILECODE (0xE084)
-#define PROC_HT_NBCOMMON_HTNBUTILITIES_FILECODE (0xE085)
-#define PROC_HT_FAM10_HTNBFAM10_FILECODE (0xE0C1)
-#define PROC_HT_FAM10_HTNBCOHERENTFAM10_FILECODE (0xE0C2)
-#define PROC_HT_FAM10_HTNBNONCOHERENTFAM10_FILECODE (0xE0C3)
-#define PROC_HT_FAM10_HTNBOPTIMIZATIONFAM10_FILECODE (0xE0C4)
-#define PROC_HT_FAM10_HTNBSYSTEMFAM10_FILECODE (0xE0C5)
-#define PROC_HT_FAM10_HTNBUTILITIESFAM10_FILECODE (0xE0C6)
-#define PROC_HT_FAM12_HTNBFAM12_FILECODE (0xE101)
-#define PROC_HT_FAM12_HTNBUTILITIESFAM12_FILECODE (0xE102)
-#define PROC_HT_FAM14_HTNBFAM14_FILECODE (0xE141)
-#define PROC_HT_FAM14_HTNBUTILITIESFAM14_FILECODE (0xE142)
-#define PROC_HT_FAM15_HTNBFAM15_FILECODE (0xE181)
-#define PROC_HT_FAM15_HTNBCOHERENTFAM15_FILECODE (0xE182)
-#define PROC_HT_FAM15_HTNBNONCOHERENTFAM15_FILECODE (0xE183)
-#define PROC_HT_FAM15_HTNBOPTIMIZATIONFAM15_FILECODE (0xE184)
-#define PROC_HT_FAM15_HTNBSYSTEMFAM15_FILECODE (0xE185)
-#define PROC_HT_FAM15_HTNBUTILITIESFAM15_FILECODE (0xE186)
-
-#define PROC_RECOVERY_HT_HTINITRECOVERY_FILECODE (0xE302)
-#define PROC_RECOVERY_HT_HTINITRESET_FILECODE (0xE301)
-
-#define PROC_IDS_CONTROL_IDSCTRL_FILECODE (0xE801)
-#define PROC_IDS_CONTROL_IDSLIB_FILECODE (0xE802)
-#define PROC_IDS_DEBUG_IDSDEBUG_FILECODE (0xE803)
-#define PROC_IDS_PERF_IDSPERF_FILECODE (0xE804)
-#define PROC_IDS_FAMILY_0X10_IDSF10ALLSERVICE_FILECODE (0xE805)
-#define PROC_IDS_FAMILY_0X10_BL_IDSF10BLSERVICE_FILECODE (0xE806)
-#define PROC_IDS_FAMILY_0X10_DA_IDSF10DASERVICE_FILECODE (0xE807)
-#define PROC_IDS_FAMILY_0X10_HY_IDSF10HYSERVICE_FILECODE (0xE808)
-#define PROC_IDS_FAMILY_0X10_RB_IDSF10RBSERVICE_FILECODE (0xE809)
-#define PROC_IDS_FAMILY_0X12_IDSF12ALLSERVICE_FILECODE (0xE80A)
-#define PROC_IDS_FAMILY_0X14_IDSF14ALLSERVICE_FILECODE (0xE80B)
-#define PROC_IDS_FAMILY_0X15_IDSF15ALLSERVICE_FILECODE (0xE80C)
-
-#define PROC_IDS_DEBUG_IDSIDTTABLE_FILECODE (0xE80D)
-#define PROC_IDS_CONTROL_IDSNVTOCMOS_FILECODE (0xE80E)
-
-///0xE820 ~ 0xE840 is reserved for ids extend module
-
-#define PROC_MEM_ARDK_MA_FILECODE (0xF001)
-#define PROC_MEM_ARDK_DR_MARDR2_FILECODE (0xF002)
-#define PROC_MEM_ARDK_DR_MARDR3_FILECODE (0xF003)
-#define PROC_MEM_ARDK_HY_MARHY3_FILECODE (0xF004)
-#define PROC_MEM_ARDK_LN_MASLN3_FILECODE (0xF005)
-#define PROC_MEM_ARDK_DR_MAUDR3_FILECODE (0xF006)
-#define PROC_MEM_ARDK_HY_MAUHY3_FILECODE (0xF007)
-#define PROC_MEM_ARDK_LN_MAULN3_FILECODE (0xF008)
-#define PROC_MEM_ARDK_DA_MAUDA3_FILECODE (0xF009)
-#define PROC_MEM_ARDK_DA_MASDA2_FILECODE (0xF00A)
-#define PROC_MEM_ARDK_DA_MASDA3_FILECODE (0xF00B)
-#define PROC_MEM_ARDK_NI_MASNI3_FILECODE (0xF00C)
-#define PROC_MEM_ARDK_C32_MARC32_3_FILECODE (0xF00D)
-#define PROC_MEM_ARDK_C32_MAUC32_3_FILECODE (0xF00E)
-#define PROC_MEM_ARDK_NI_MAUNI3_FILECODE (0xF00F)
-#define PROC_MEM_ARDK_ON_MASON3_FILECODE (0xF010)
-#define PROC_MEM_ARDK_ON_MAUON3_FILECODE (0xF011)
-#define PROC_MEM_ARDK_PH_MASPH3_FILECODE (0xF012)
-#define PROC_MEM_ARDK_PH_MAUPH3_FILECODE (0xF013)
-#define PROC_MEM_ARDK_OR_MAROR3_FILECODE (0xF014)
-#define PROC_MEM_ARDK_OR_MAUOR3_FILECODE (0xF017)
-#define PROC_MEM_ARDK_RB_MASRB3_FILECODE (0xF018)
-#define PROC_MEM_ARDK_RB_MAURB3_FILECODE (0xF019)
-
-#define PROC_MEM_FEAT_CHINTLV_MFCHI_FILECODE (0xF081)
-#define PROC_MEM_FEAT_CSINTLV_MFCSI_FILECODE (0xF082)
-#define PROC_MEM_FEAT_ECC_MFECC_FILECODE (0xF083)
-#define PROC_MEM_FEAT_ECC_MFEMP_FILECODE (0xF085)
-#define PROC_MEM_FEAT_EXCLUDIMM_MFDIMMEXCLUD_FILECODE (0xF086)
-#define PROC_MEM_FEAT_IDENDIMM_MFIDENDIMM_FILECODE (0xF088)
-#define PROC_MEM_FEAT_INTLVRN_MFINTLVRN_FILECODE (0xF089)
-#define PROC_MEM_FEAT_LVDDR3_MFLVDDR3_FILECODE (0xF08A)
-#define PROC_MEM_FEAT_MEMCLR_MFMEMCLR_FILECODE (0xF08B)
-#define PROC_MEM_FEAT_NDINTLV_MFNDI_FILECODE (0xF08C)
-#define PROC_MEM_FEAT_ODTHERMAL_MFODTHERMAL_FILECODE (0xF08D)
-#define PROC_MEM_FEAT_OLSPARE_MFSPR_FILECODE (0xF08E)
-#define PROC_MEM_FEAT_PARTRN_MFPARALLELTRAINING_FILECODE (0xF08F)
-#define PROC_MEM_FEAT_PARTRN_MFSTANDARDTRAINING_FILECODE (0xF091)
-#define PROC_MEM_FEAT_S3_MFS3_FILECODE (0xF092)
-#define PROC_MEM_FEAT_TABLE_MFTDS_FILECODE (0xF093)
-
-#define PROC_MEM_MAIN_MDEF_FILECODE (0xF101)
-#define PROC_MEM_MAIN_MINIT_FILECODE (0xF102)
-#define PROC_MEM_MAIN_MM_FILECODE (0xF103)
-#define PROC_MEM_FEAT_DMI_MFDMI_FILECODE (0xF104)
-#define PROC_MEM_MAIN_MMECC_FILECODE (0xF105)
-#define PROC_MEM_MAIN_MMEXCLUDEDIMM_FILECODE (0xF106)
-#define PROC_MEM_MAIN_DR_MMFLOWDR_FILECODE (0xF107)
-#define PROC_MEM_MAIN_HY_MMFLOWHY_FILECODE (0xF108)
-#define PROC_MEM_MAIN_LN_MMFLOWLN_FILECODE (0xF109)
-#define PROC_MEM_MAIN_ON_MMFLOWON_FILECODE (0xF10A)
-#define PROC_MEM_MAIN_MMNODEINTERLEAVE_FILECODE (0xF10B)
-#define PROC_MEM_MAIN_MMONLINESPARE_FILECODE (0xF10C)
-#define PROC_MEM_MAIN_MMPARALLELTRAINING_FILECODE (0xF10D)
-#define PROC_MEM_MAIN_MMSTANDARDTRAINING_FILECODE (0xF10E)
-#define PROC_MEM_MAIN_MUC_FILECODE (0xF10F)
-#define PROC_MEM_MAIN_MMMEMCLR_FILECODE (0xF110)
-#define PROC_MEM_MAIN_DA_MMFLOWDA_FILECODE (0xF111)
-#define PROC_MEM_MAIN_MMFLOW_FILECODE (0xF112)
-#define PROC_MEM_MAIN_MERRHDL_FILECODE (0xF113)
-#define PROC_MEM_MAIN_C32_MMFLOWC32_FILECODE (0xF114)
-#define PROC_MEM_MAIN_MMLVDDR3_FILECODE (0xF115)
-#define PROC_MEM_MAIN_MMUMAALLOC_FILECODE (0xF116)
-#define PROC_MEM_MAIN_MMMEMRESTORE_FILECODE (0xF117)
-#define PROC_MEM_MAIN_MMCONDITIONALPSO_FILECODE (0xF118)
-#define PROC_MEM_MAIN_OR_MMFLOWOR_FILECODE (0xF119)
-#define PROC_MEM_MAIN_RB_MMFLOWRB_FILECODE (0xF11A)
-#define PROC_MEM_MAIN_PH_MMFLOWPH_FILECODE (0xF11B)
-
-#define PROC_MEM_NB_DR_MNDR_FILECODE (0XF213)
-#define PROC_MEM_NB_DR_MNFLOWDR_FILECODE (0XF214)
-#define PROC_MEM_NB_DR_MNIDENDIMMDR_FILECODE (0XF216)
-#define PROC_MEM_NB_DR_MNMCTDR_FILECODE (0XF217)
-#define PROC_MEM_NB_DR_MNDCTDR_FILECODE (0XF218)
-#define PROC_MEM_NB_DR_MNOTDR_FILECODE (0XF219)
-#define PROC_MEM_NB_DR_MNPARTRAINDR_FILECODE (0XF21A)
-#define PROC_MEM_NB_DR_MNPROTODR_FILECODE (0XF21C)
-#define PROC_MEM_NB_DR_MNS3DR_FILECODE (0XF21D)
-#define PROC_MEM_NB_DR_MNREGDR_FILECODE (0XF21E)
-#define PROC_MEM_NB_RB_MNRB_FILECODE (0XF220)
-#define PROC_MEM_NB_RB_MNFLOWRB_FILECODE (0XF221)
-#define PROC_MEM_NB_RB_MNS3RB_FILECODE (0XF222)
-#define PROC_MEM_NB_RB_MNIDENDIMMRB_FILECODE (0XF223)
-#define PROC_MEM_NB_HY_MNFLOWHY_FILECODE (0XF233)
-#define PROC_MEM_NB_HY_MNHY_FILECODE (0XF235)
-#define PROC_MEM_NB_HY_MNIDENDIMMHY_FILECODE (0XF236)
-#define PROC_MEM_NB_HY_MNMCTHY_FILECODE (0XF237)
-#define PROC_MEM_NB_HY_MNDCTHY_FILECODE (0XF238)
-#define PROC_MEM_NB_HY_MNOTHY_FILECODE (0XF239)
-#define PROC_MEM_NB_HY_MNPARTRAINHY_FILECODE (0XF23A)
-#define PROC_MEM_NB_HY_MNPHYHY_FILECODE (0XF23B)
-#define PROC_MEM_NB_HY_MNPROTOHY_FILECODE (0XF23C)
-#define PROC_MEM_NB_HY_MNS3HY_FILECODE (0XF23D)
-#define PROC_MEM_NB_HY_MNREGHY_FILECODE (0XF23E)
-#define PROC_MEM_NB_ON_MNON_FILECODE (0xF240)
-#define PROC_MEM_NB_ON_MNREGON_FILECODE (0xF241)
-#define PROC_MEM_NB_ON_MNDCTON_FILECODE (0xF242)
-#define PROC_MEM_NB_ON_MNIDENDIMMON_FILECODE (0xF244)
-#define PROC_MEM_NB_ON_MNMCTON_FILECODE (0xF245)
-#define PROC_MEM_NB_ON_MNOTON_FILECODE (0xF246)
-#define PROC_MEM_NB_ON_MNPHYON_FILECODE (0xF247)
-#define PROC_MEM_NB_ON_MNS3ON_FILECODE (0xF248)
-#define PROC_MEM_NB_ON_MNFLOWON_FILECODE (0xF249)
-#define PROC_MEM_NB_ON_MNPROTOON_FILECODE (0xF24A)
-#define PROC_MEM_NB_LN_MNDCTLN_FILECODE (0XF252)
-#define PROC_MEM_NB_LN_MNFLOWLN_FILECODE (0XF253)
-#define PROC_MEM_NB_LN_MNIDENDIMMLN_FILECODE (0XF254)
-#define PROC_MEM_NB_LN_MNMCTLN_FILECODE (0XF255)
-#define PROC_MEM_NB_LN_MNOTLN_FILECODE (0XF256)
-#define PROC_MEM_NB_LN_MNPHYLN_FILECODE (0XF257)
-#define PROC_MEM_NB_LN_MNPROTOLN_FILECODE (0XF258)
-#define PROC_MEM_NB_LN_MNLN_FILECODE (0XF259)
-#define PROC_MEM_NB_LN_MNS3LN_FILECODE (0XF25A)
-#define PROC_MEM_NB_LN_MNREGLN_FILECODE (0XF25B)
-#define PROC_MEM_NB_DA_MNDA_FILECODE (0XF260)
-#define PROC_MEM_NB_DA_MNFLOWDA_FILECODE (0XF261)
-#define PROC_MEM_NB_DA_MNIDENDIMMDA_FILECODE (0XF263)
-#define PROC_MEM_NB_DA_MNMCTDA_FILECODE (0XF264)
-#define PROC_MEM_NB_DA_MNDCTDA_FILECODE (0XF265)
-#define PROC_MEM_NB_DA_MNOTDA_FILECODE (0XF266)
-#define PROC_MEM_NB_DA_MNPARTRAINDA_FILECODE (0XF267)
-#define PROC_MEM_NB_DA_MNPROTODA_FILECODE (0XF269)
-#define PROC_MEM_NB_DA_MNS3DA_FILECODE (0XF26A)
-#define PROC_MEM_NB_DA_MNREGDA_FILECODE (0XF26B)
-#define PROC_MEM_NB_C32_MNC32_FILECODE (0XF26C)
-#define PROC_MEM_NB_C32_MNDCTC32_FILECODE (0XF26D)
-#define PROC_MEM_NB_C32_MNFLOWC32_FILECODE (0XF26E)
-#define PROC_MEM_NB_C32_MNIDENDIMMC32_FILECODE (0XF26F)
-#define PROC_MEM_NB_C32_MNMCTC32_FILECODE (0XF270)
-#define PROC_MEM_NB_C32_MNOTC32_FILECODE (0XF271)
-#define PROC_MEM_NB_C32_MNPARTRAINC32_FILECODE (0XF272)
-#define PROC_MEM_NB_C32_MNPHYC32_FILECODE (0XF273)
-#define PROC_MEM_NB_C32_MNPROTOC32_FILECODE (0XF274)
-#define PROC_MEM_NB_C32_MNS3C32_FILECODE (0XF275)
-#define PROC_MEM_NB_C32_MNREGC32_FILECODE (0XF277)
-#define PROC_MEM_NB_MN_FILECODE (0XF27C)
-#define PROC_MEM_NB_MNDCT_FILECODE (0XF27D)
-#define PROC_MEM_NB_MNPHY_FILECODE (0XF27E)
-#define PROC_MEM_NB_MNMCT_FILECODE (0XF27F)
-#define PROC_MEM_NB_MNS3_FILECODE (0XF280)
-#define PROC_MEM_NB_MNFLOW_FILECODE (0XF281)
-#define PROC_MEM_NB_MNFEAT_FILECODE (0XF282)
-#define PROC_MEM_NB_MNTRAIN2_FILECODE (0XF283)
-#define PROC_MEM_NB_MNTRAIN3_FILECODE (0XF284)
-#define PROC_MEM_NB_MNREG_FILECODE (0XF285)
-#define PROC_MEM_NB_NI_MNNI_FILECODE (0XF286)
-#define PROC_MEM_NB_NI_MNS3NI_FILECODE (0XF287)
-#define PROC_MEM_NB_NI_MNFLOWNI_FILECODE (0XF288)
-#define PROC_MEM_NB_PH_MNFLOWPH_FILECODE (0XF289)
-#define PROC_MEM_NB_PH_MNPH_FILECODE (0XF28A)
-#define PROC_MEM_NB_PH_MNS3PH_FILECODE (0XF28B)
-#define PROC_MEM_NB_PH_MNIDENDIMMPH_FILECODE (0XF28C)
-#define PROC_MEM_NB_OR_MNFLOWOR_FILECODE (0XF290)
-#define PROC_MEM_NB_OR_MNOR_FILECODE (0XF291)
-#define PROC_MEM_NB_OR_MNIDENDIMMOR_FILECODE (0XF292)
-#define PROC_MEM_NB_OR_MNMCTOR_FILECODE (0XF293)
-#define PROC_MEM_NB_OR_MNDCTOR_FILECODE (0XF294)
-#define PROC_MEM_NB_OR_MNOTOR_FILECODE (0XF295)
-#define PROC_MEM_NB_OR_MNPARTRAINOR_FILECODE (0XF296)
-#define PROC_MEM_NB_OR_MNPHYOR_FILECODE (0XF297)
-#define PROC_MEM_NB_OR_MNPROTOOR_FILECODE (0XF298)
-#define PROC_MEM_NB_OR_MNS3OR_FILECODE (0XF299)
-#define PROC_MEM_NB_OR_MNREGOR_FILECODE (0XF29A)
-
-#define PROC_MEM_PS_MP_FILECODE (0XF401)
-#define PROC_MEM_PS_DR_MPRDR3_FILECODE (0XF402)
-#define PROC_MEM_PS_HY_MPRHY3_FILECODE (0XF403)
-#define PROC_MEM_PS_LN_MPRLN3_FILECODE (0XF404)
-#define PROC_MEM_PS_DR_MPSDR3_FILECODE (0XF405)
-#define PROC_MEM_PS_HY_MPSHY3_FILECODE (0XF406)
-#define PROC_MEM_PS_LN_MPSLN3_FILECODE (0XF407)
-#define PROC_MEM_PS_DR_MPUDR3_FILECODE (0XF408)
-#define PROC_MEM_PS_HY_MPUHY3_FILECODE (0XF409)
-#define PROC_MEM_PS_LN_MPULN3_FILECODE (0XF40A)
-#define PROC_MEM_PS_DA_MPUDA3_FILECODE (0XF40B)
-#define PROC_MEM_PS_DA_MPSDA2_FILECODE (0XF40C)
-#define PROC_MEM_PS_DA_MPSDA3_FILECODE (0XF40D)
-#define PROC_MEM_PS_DR_MPRDR2_FILECODE (0XF40E)
-#define PROC_MEM_PS_DR_MPUDR2_FILECODE (0XF40F)
-#define PROC_MEM_PS_C32_MPRC32_3_FILECODE (0XF410)
-#define PROC_MEM_PS_C32_MPUC32_3_FILECODE (0XF411)
-#define PROC_MEM_PS_NI_MPSNI3_FILECODE (0XF412)
-#define PROC_MEM_PS_NI_MPUNI3_FILECODE (0XF413)
-#define PROC_MEM_PS_ON_MPSON3_FILECODE (0XF414)
-#define PROC_MEM_PS_ON_MPUON3_FILECODE (0XF415)
-#define PROC_MEM_PS_PH_MPSPH3_FILECODE (0XF416)
-#define PROC_MEM_PS_PH_MPUPH3_FILECODE (0XF417)
-#define PROC_MEM_PS_RB_MPSRB3_FILECODE (0XF418)
-#define PROC_MEM_PS_RB_MPURB3_FILECODE (0XF419)
-#define PROC_MEM_PS_OR_AM3_MPUORA3_FILECODE (0XF41A)
-#define PROC_MEM_PS_OR_AM3_MPSORA3_FILECODE (0XF41B)
-#define PROC_MEM_PS_OR_C32_MPRORC3_FILECODE (0XF41C)
-#define PROC_MEM_PS_OR_C32_MPUORC3_FILECODE (0XF41D)
-#define PROC_MEM_PS_OR_C32_MPLORC3_FILECODE (0XF41E)
-#define PROC_MEM_PS_OR_G34_MPRORG3_FILECODE (0XF41F)
-#define PROC_MEM_PS_OR_G34_MPUORG3_FILECODE (0XF420)
-#define PROC_MEM_PS_OR_G34_MPLORG3_FILECODE (0XF421)
-#define PROC_MEM_PS_MPRTT_FILECODE (0XF422)
-#define PROC_MEM_PS_MPMAXFREQ_FILECODE (0XF423)
-#define PROC_MEM_PS_MPODTPAT_FILECODE (0XF424)
-#define PROC_MEM_PS_MPSAO_FILECODE (0XF425)
-#define PROC_MEM_PS_MPMR0_FILECODE (0XF426)
-#define PROC_MEM_PS_MPRC2IBT_FILECODE (0XF427)
-#define PROC_MEM_PS_MPRC10OPSPD_FILECODE (0XF428)
-#define PROC_MEM_PS_MPLRIBT_FILECODE (0XF429)
-#define PROC_MEM_PS_MPLRNPR_FILECODE (0XF42A)
-#define PROC_MEM_PS_MPLRNLR_FILECODE (0XF42B)
-#define PROC_MEM_PS_OR_MPOR3_FILECODE (0XF42C)
-
-#define PROC_MEM_TECH_MT_FILECODE (0XF501)
-#define PROC_MEM_TECH_MTHDI_FILECODE (0XF502)
-#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0XF504)
-#define PROC_MEM_TECH_MTTECC_FILECODE (0XF505)
-#define PROC_MEM_TECH_MTTHRC_FILECODE (0XF506)
-#define PROC_MEM_TECH_MTTML_FILECODE (0XF507)
-#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0XF509)
-#define PROC_MEM_TECH_MTTSRC_FILECODE (0XF50B)
-#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0XF50C)
-#define PROC_MEM_TECH_DDR2_MT2_FILECODE (0XF541)
-#define PROC_MEM_TECH_DDR2_MTOT2_FILECODE (0XF543)
-#define PROC_MEM_TECH_DDR2_MTSPD2_FILECODE (0XF544)
-#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0XF581)
-#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0XF583)
-#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0XF584)
-#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0XF585)
-#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0XF586)
-#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0XF587)
-#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0XF588)
-#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0XF589)
-
-#define PROC_RECOVERY_MEM_MRDEF_FILECODE (0XF801)
-#define PROC_RECOVERY_MEM_MRINIT_FILECODE (0XF802)
-#define PROC_RECOVERY_MEM_MRM_FILECODE (0XF803)
-#define PROC_RECOVERY_MEM_MRUC_FILECODE (0XF804)
-#define PROC_RECOVERY_MEM_NB_DR_MRNDR_FILECODE (0XF812)
-#define PROC_RECOVERY_MEM_NB_DR_MRNMCTDR_FILECODE (0XF813)
-#define PROC_RECOVERY_MEM_NB_HY_MRNDCTHY_FILECODE (0XF821)
-#define PROC_RECOVERY_MEM_NB_HY_MRNHY_FILECODE (0XF822)
-#define PROC_RECOVERY_MEM_NB_HY_MRNMCTHY_FILECODE (0XF823)
-#define PROC_RECOVERY_MEM_NB_HY_MRNPROTOHY_FILECODE (0XF825)
-#define PROC_RECOVERY_MEM_NB_LN_MRNDCTLN_FILECODE (0XF831)
-#define PROC_RECOVERY_MEM_NB_LN_MRNMCTLN_FILECODE (0XF832)
-#define PROC_RECOVERY_MEM_NB_LN_MRNLN_FILECODE (0XF833)
-#define PROC_RECOVERY_MEM_NB_DA_MRNDA_FILECODE (0XF842)
-#define PROC_RECOVERY_MEM_NB_DA_MRNMCTDA_FILECODE (0XF843)
-#define PROC_RECOVERY_MEM_NB_NI_MRNNI_FILECODE (0XF845)
-#define PROC_RECOVERY_MEM_NB_C32_MRNC32_FILECODE (0XF851)
-#define PROC_RECOVERY_MEM_NB_C32_MRNMCTC32_FILECODE (0XF852)
-#define PROC_RECOVERY_MEM_NB_C32_MRNPROTOC32_FILECODE (0XF853)
-#define PROC_RECOVERY_MEM_NB_ON_MRNDCTON_FILECODE (0xF861)
-#define PROC_RECOVERY_MEM_NB_ON_MRNMCTON_FILECODE (0xF862)
-#define PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE (0xF863)
-#define PROC_RECOVERY_MEM_NB_PH_MRNPH_FILECODE (0xF871)
-#define PROC_RECOVERY_MEM_NB_RB_MRNRB_FILECODE (0xF881)
-#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE (0XF8C1)
-#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE (0XF8C2)
-#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE (0XF8C3)
-#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE (0XF8C4)
-#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE (0XF8C5)
-#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE (0XF8C6)
-#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE (0XF8C7)
-#define PROC_RECOVERY_MEM_NB_MRN_FILECODE (0XF8C8)
-#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE (0XF8C9)
-#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE (0XF8CA)
-#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE (0XF8CB)
-#define PROC_RECOVERY_MEM_TECH_MRTTHRC_FILECODE (0XF8CC)
-#define PROC_RECOVERY_MEM_NB_OR_MRNDCTOR_FILECODE (0XF8CD)
-#define PROC_RECOVERY_MEM_NB_OR_MRNOR_FILECODE (0XF8CE)
-#define PROC_RECOVERY_MEM_NB_OR_MRNMCTOR_FILECODE (0XF8CF)
-#define PROC_RECOVERY_MEM_NB_OR_MRNPROTOOR_FILECODE (0XF8D0)
-#define PROC_RECOVERY_MEM_PS_MRP_FILECODE (0XF8E0)
-#define PROC_RECOVERY_MEM_PS_MRPRTT_FILECODE (0XF8E1)
-#define PROC_RECOVERY_MEM_PS_MRPODTPAT_FILECODE (0XF8E2)
-#define PROC_RECOVERY_MEM_PS_MRPSAO_FILECODE (0XF8E3)
-#define PROC_RECOVERY_MEM_PS_MRPMR0_FILECODE (0XF8E4)
-#define PROC_RECOVERY_MEM_PS_MRPRC2IBT_FILECODE (0XF8E5)
-#define PROC_RECOVERY_MEM_PS_MRPRC10OPSPD_FILECODE (0XF8E6)
-#define PROC_RECOVERY_MEM_PS_MRPLRIBT_FILECODE (0XF8E7)
-#define PROC_RECOVERY_MEM_PS_MRPLRNPR_FILECODE (0XF8E8)
-#define PROC_RECOVERY_MEM_PS_MRPLRNLR_FILECODE (0XF8E9)
-#define PROC_RECOVERY_MEM_PS_OR_MRPOR3_FILECODE (0XF8EA)
-#define PROC_RECOVERY_MEM_PS_OR_AM3_MRPSORA3_FILECODE (0XF8EB)
-#define PROC_RECOVERY_MEM_PS_OR_AM3_MRPUORA3_FILECODE (0XF8EC)
-#define PROC_RECOVERY_MEM_PS_OR_C32_MRPUORC3_FILECODE (0XF8ED)
-#define PROC_RECOVERY_MEM_PS_OR_C32_MRPRORC3_FILECODE (0XF8EE)
-#define PROC_RECOVERY_MEM_PS_OR_C32_MRPLORC3_FILECODE (0XF8EF)
-#define PROC_RECOVERY_MEM_PS_OR_G34_MRPUORG3_FILECODE (0XF8F0)
-#define PROC_RECOVERY_MEM_PS_OR_G34_MRPRORG3_FILECODE (0XF8F1)
-#define PROC_RECOVERY_MEM_PS_OR_G34_MRPLORG3_FILECODE (0XF8F2)
-
-#endif // _FILECODE_H_
diff --git a/src/vendorcode/amd/agesa/Include/GeneralServices.h b/src/vendorcode/amd/agesa/Include/GeneralServices.h
deleted file mode 100644
index 14ba10e..0000000
--- a/src/vendorcode/amd/agesa/Include/GeneralServices.h
+++ /dev/null
@@ -1,203 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * General Services
- *
- * Provides Services similar to the external General Services API, except
- * suited to use within AGESA components. Socket, Core and PCI identification.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Common
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _GENERAL_SERVICES_H_
-#define _GENERAL_SERVICES_H_
-
-/*----------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-#define NUMBER_OF_EVENT_DATA_PARAMS 4
-
-/**
- * AMD Device id for MMIO check.
- */
-#define AMD_DEV_VEN_ID 0x1022
-#define AMD_DEV_VEN_ID_ADDRESS 0
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *----------------------------------------------------------------------------------------
- */
-
-/**
- * An AGESA Event Log entry.
- */
-typedef struct {
- AGESA_STATUS EventClass; ///< The severity of the event, its associated AGESA_STATUS.
- UINT32 EventInfo; ///< Uniquely identifies the event.
- UINT32 DataParam1; ///< Event specific additional data
- UINT32 DataParam2; ///< Event specific additional data
- UINT32 DataParam3; ///< Event specific additional data
- UINT32 DataParam4; ///< Event specific additional data
-} AGESA_EVENT;
-
-/*----------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *----------------------------------------------------------------------------------------
- */
-
-/**
- * Get a specified Core's APIC ID.
- *
- * @param[in] StdHeader Header for library and services.
- * @param[in] Socket The Core's Socket.
- * @param[in] Core The Core id.
- * @param[out] ApicAddress The Core's APIC ID.
- * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
- *
- * @retval TRUE The core is present, APIC Id valid
- * @retval FALSE The core is not present, APIC Id not valid.
- */
-BOOLEAN
-GetApicId (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN UINT32 Socket,
- IN UINT32 Core,
- OUT UINT8 *ApicAddress,
- OUT AGESA_STATUS *AgesaStatus
-);
-
-/**
- * Get Processor Module's PCI Config Space address.
- *
- * @param[in] StdHeader Header for library and services.
- * @param[in] Socket The Core's Socket.
- * @param[in] Module The Module in that Processor
- * @param[out] PciAddress The Processor's PCI Config Space address (Function 0, Register 0)
- * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
- *
- * @retval TRUE The core is present, PCI Address valid
- * @retval FALSE The core is not present, PCI Address not valid.
- */
-BOOLEAN
-GetPciAddress (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN UINT32 Socket,
- IN UINT32 Module,
- OUT PCI_ADDR *PciAddress,
- OUT AGESA_STATUS *AgesaStatus
-);
-
-/**
- * "Who am I" for the current running core.
- *
- * @param[in] StdHeader Header for library and services.
- * @param[out] Socket The current Core's Socket
- * @param[out] Module The current Core's Processor Module
- * @param[out] Core The current Core's core id.
- * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
- *
- */
-VOID
-IdentifyCore (
- IN AMD_CONFIG_PARAMS *StdHeader,
- OUT UINT32 *Socket,
- OUT UINT32 *Module,
- OUT UINT32 *Core,
- OUT AGESA_STATUS *AgesaStatus
-);
-
-/**
- * A boolean function determine executed CPU is BSP core.
- */
-BOOLEAN
-IsBsp (
- IN OUT AMD_CONFIG_PARAMS *StdHeader,
- OUT AGESA_STATUS *AgesaStatus
- );
-
-/**
- * This function logs AGESA events into the event log.
- */
-VOID
-PutEventLog (
- IN AGESA_STATUS EventClass,
- IN UINT32 EventInfo,
- IN UINT32 DataParam1,
- IN UINT32 DataParam2,
- IN UINT32 DataParam3,
- IN UINT32 DataParam4,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * This function gets event logs from the circular buffer.
- */
-AGESA_STATUS
-GetEventLog (
- OUT AGESA_EVENT *EventRecord,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * This function gets event logs from the circular buffer without flushing the entry.
- */
-BOOLEAN
-PeekEventLog (
- OUT AGESA_EVENT *EventRecord,
- IN UINT16 Index,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * This routine programs the registers necessary to get the PCI MMIO mechanism
- * up and functioning.
- */
-VOID
-InitializePciMmio (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif // _GENERAL_SERVICES_H_
diff --git a/src/vendorcode/amd/agesa/Include/GnbInterface.h b/src/vendorcode/amd/agesa/Include/GnbInterface.h
deleted file mode 100644
index 761cf3a..0000000
--- a/src/vendorcode/amd/agesa/Include/GnbInterface.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * GNB API definition.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 37658 $ @e \$Date: 2010-09-09 15:25:38 +0800 (Thu, 09 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _GNBINTERFACE_H_
-#define _GNBINTERFACE_H_
-
-AGESA_STATUS
-GnbInitAtReset (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-GnbInitAtEarly (
- IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr
- );
-
-AGESA_STATUS
-GnbInitAtPost (
- IN OUT AMD_POST_PARAMS *PostParamsPtr
- );
-
-VOID
-GnbInitDataStructAtEnvDef (
- IN OUT GNB_ENV_CONFIGURATION *GnbEnvConfigPtr,
- IN AMD_ENV_PARAMS *EnvParamsPtr
- );
-
-AGESA_STATUS
-GnbInitAtEnv (
- IN AMD_ENV_PARAMS *EnvParamsPtr
- );
-
-AGESA_STATUS
-GnbInitAtMid (
- IN OUT AMD_MID_PARAMS *MidParamsPtr
- );
-
-AGESA_STATUS
-GnbInitAtLate (
- IN OUT AMD_LATE_PARAMS *LateParamsPtr
- );
-
-AGESA_STATUS
-GnbInitAtPostAfterDram (
- IN OUT AMD_POST_PARAMS *PostParamsPtr
- );
-
-AGESA_STATUS
-AmdGnbRecovery (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Include/GnbInterfaceStub.h b/src/vendorcode/amd/agesa/Include/GnbInterfaceStub.h
deleted file mode 100644
index 0b3ff08..0000000
--- a/src/vendorcode/amd/agesa/Include/GnbInterfaceStub.h
+++ /dev/null
@@ -1,232 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- *
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 37658 $ @e \$Date: 2010-09-09 15:25:38 +0800 (Thu, 09 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init GNB at Reset Stub
- *
- *
- *
- * @param[in] StdHeader Standard configuration header
- * @retval AGESA_STATUS Always succeeds
- */
-
-AGESA_STATUS
-GnbInitAtReset (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
-
- return AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init GNB at Early Stub
- *
- *
- *
- * @param[in,out] EarlyParamsPtr Pointer to early configuration params.
- * @retval AGESA_STATUS Always succeeds
- */
-
-AGESA_STATUS
-GnbInitAtEarly (
- IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr
- )
-{
- return AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Default constructor of GNB configuration at Env
- *
- *
- *
- * @param[in] GnbEnvConfigPtr Pointer to gnb env configuration params.
- * @param[in] EnvParamsPtr Pointer to env configuration params.
- */
-VOID
-GnbInitDataStructAtEnvDef (
- IN OUT GNB_ENV_CONFIGURATION *GnbEnvConfigPtr,
- IN AMD_ENV_PARAMS *EnvParamsPtr
- )
-{
-
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init GNB at Env
- *
- *
- *
- * @param[in] EnvParamsPtr Pointer to env configuration params.
-* @retval AGESA_STATUS Always succeeds
- */
-
-AGESA_STATUS
-GnbInitAtEnv (
- IN AMD_ENV_PARAMS *EnvParamsPtr
- )
-{
-
- return AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init GNB at Post
- *
- *
- *
- * @param[in,out] PostParamsPtr Pointer to Post configuration params.
- * @retval AGESA_STATUS Always succeeds
- */
-
-AGESA_STATUS
-GnbInitAtPost (
- IN OUT AMD_POST_PARAMS *PostParamsPtr
- )
-{
-
- return AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init GNB at Mid post
- *
- *
- *
- * @param[in,out] MidParamsPtr Pointer to mid configuration params.
- * @retval AGESA_STATUS Always succeeds
- */
-
-AGESA_STATUS
-GnbInitAtMid (
- IN OUT AMD_MID_PARAMS *MidParamsPtr
- )
-{
-
- return AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init GNB at Late post
- *
- *
- *
- * @param[in,out] LateParamsPtr Pointer to late configuration params.
- * @retval AGESA_STATUS Always succeeds
- */
-
-AGESA_STATUS
-GnbInitAtLate (
- IN OUT AMD_LATE_PARAMS *LateParamsPtr
- )
-{
-
- return AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * AmdGnbRecovery
- *
- *
- *
- * @param[in] StdHeader Standard configuration header
- * @retval AGESA_STATUS Always succeeds
- */
-AGESA_STATUS
-AmdGnbRecovery (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- return AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init GNB at Post after DRAM init
- *
- *
- *
- * @param[in] PostParamsPtr Pointer to post configuration parameters
- * @retval Initialization status.
- */
-
-AGESA_STATUS
-GnbInitAtPostAfterDram (
- IN OUT AMD_POST_PARAMS *PostParamsPtr
- )
-{
- return AGESA_SUCCESS;
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Include/Ids.h b/src/vendorcode/amd/agesa/Include/Ids.h
deleted file mode 100644
index cbd0b13..0000000
--- a/src/vendorcode/amd/agesa/Include/Ids.h
+++ /dev/null
@@ -1,927 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD IDS Routines
- *
- * Contains AMD AGESA Integrated Debug Macros
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: IDS
- * @e \$Revision: 38634 $ @e \$Date: 2010-09-27 21:39:01 +0800 (Mon, 27 Sep 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
- /* Macros to aid debugging */
- /* These definitions expand to zero (0) bytes of code when disabled */
-
-#ifndef _IDS_H_
-#define _IDS_H_
-
-#undef FALSE
-#undef TRUE
-#define FALSE 0
-#define TRUE 1
-// Proto type for optionsids.h
-typedef UINT32 IDS_STATUS; ///< Status of IDS function.
-#define IDS_SUCCESS ((IDS_STATUS) 0x00000000) ///< IDS Function is Successful.
-#define IDS_UNSUPPORTED ((IDS_STATUS) 0xFFFFFFFF) ///< IDS Function is not existed.
-
-#define IDS_STRINGIZE(a) #a ///< for define stringize macro
-/**
- * IDS Option Hook Points
- *
- * These are the values to indicate hook point in AGESA for IDS Options.
- *
- */
-typedef enum { //vv- for debug reference only
- IDS_INIT_EARLY_BEFORE, ///< 00 Option Hook Point before AGESA function AMD_INIT_EARLY.
- ///< IDS Object is initialized.
- ///< Override CPU Core Leveling Mode.
- ///< Set P-State in Post
- IDS_INIT_EARLY_AFTER, ///< 01 Option Hook Point after AGESA function AMD_INIT_EARLY.
- IDS_INIT_LATE_BEFORE, ///< 02 Option Hook Point before AGESA function AMD_INIT_LATE.
- ///< It will be used to control the following tables.
- ///< ACPI P-State Table (_PSS, XPSS, _PCT, _PSD, _PPC)
- ///< ACPI SRAT Table
- ///< ACPI SLIT Table
- ///< ACPI WHEA Table
- ///< DMI Table
- IDS_INIT_LATE_AFTER, ///< 03 Option Hook Point after AGESA function AMD_INIT_LATE.
- IDS_INIT_MID_BEFORE, ///< 04 Option Hook Point before AGESA function AMD_INIT_MID.
- IDS_INIT_MID_AFTER, ///< 05 Option Hook Point after AGESA function AMD_INIT_MID.
- IDS_INIT_POST_BEFORE, ///< 06 Option Hook Point before AGESA function AMD_INIT_POST.
- ///< Control Interleaving and DRAM memory hole
- ///< Override the setting of ECC Control
- ///< Override the setting of Online Spare Rank
- IDS_INIT_POST_AFTER, ///< 07 Option Hook Point after AGESA function AMD_INIT_POST.
- IDS_INIT_RESET_BEFORE, ///< 08 Option Hook Point before AGESA function AMD_INIT_RESET.
- IDS_INIT_RESET_AFTER, ///< 09 Option Hook Point after AGESA function AMD_INIT_RESET.
- IDS_INIT_POST_MID, ///< 0a Option Hook Point after AGESA function AMD_INIT_POST.
- IDS_BEFORE_S3_SAVE, ///< 0b override any settings before S3 save.
- IDS_BEFORE_S3_RESTORE, ///< 0c override any settings before S3 restore
- IDS_AFTER_S3_SAVE, ///< 0d Override any settings after S3 save
- IDS_AFTER_S3_RESTORE, ///< 0e Override any settings after S3 restore
- IDS_BEFORE_DQS_TRAINING, ///< 0f override any settings before DQS training
- IDS_BEFORE_DRAM_INIT, ///< 10 override any settings before Dram initialization
- IDS_BEFORE_MEM_FREQ_CHG, ///< 11 override settings before MemClk frequency change
- IDS_BEFORE_WARM_RESET , ///< 12 Override PCI or MSR Registers Before Warm Reset
- IDS_BEFORE_MEM_INIT, ///< 13 Override PCI or MSR Registers Before Memory Init
- IDS_BEFORE_PCI_INIT, ///< 14 Override PCI or MSR Registers Before PCI Init
- IDS_BEFORE_OS, ///< 15 Override PCI or MSR Registers Before booting to OS
- IDS_UCODE, ///< 16 Enable or Disable microcode patching
- IDS_BEFORE_AP_EARLY_HALT, ///< 17 Option Hook Point before AP early halt
-
- IDS_PLATFORM_RSVD1 = 0x38, ///< from 0x38 to 0x3f will reserved for platform used
- IDS_PLATFORM_RSVD2 = 0x39, ///< from 0x38 to 0x3f will reserved for platform used
- IDS_PLATFORM_RSVD3 = 0x3a, ///< from 0x38 to 0x3f will reserved for platform used
- IDS_PLATFORM_RSVD4 = 0x3b, ///< from 0x38 to 0x3f will reserved for platform used
- IDS_PLATFORM_RSVD5 = 0x3c, ///< from 0x38 to 0x3f will reserved for platform used
- IDS_PLATFORM_RSVD6 = 0x3d, ///< from 0x38 to 0x3f will reserved for platform used
- IDS_PLATFORM_RSVD7 = 0x3e, ///< from 0x38 to 0x3f will reserved for platform used
- IDS_PLATFORM_RSVD8 = 0x3f, ///< from 0x38 to 0x3f will reserved for platform used
-
- // All the above timing point is used by BVM, their value should never be changed
- IDS_HT_CONTROL, ///< 40 Override the setting of HT Link Control
- IDS_HT_TRISTATE, ///< 41 Enable or Disable HT Tri-state during an LDTSTP#
- IDS_INIT_DRAM_TABLE, ///< 42 Generate override table for Dram Timing
- ///< Dram Controller, Drive Strength and DQS Timing
- IDS_GET_DRAM_TABLE, ///< 43 Generate override table for Dram Timing
- IDS_GANGING_MODE, ///< 44 override Memory Mode Unganged
- IDS_POWERDOWN_MODE, ///< 45 override Power Down Mode
- IDS_BURST_LENGTH32, ///< 46 override Burst Length32
- IDS_ALL_MEMORY_CLOCK, ///< 47 override All Memory Clks Enable
- IDS_ECC, ///< 48 override ECC parameter
- IDS_ECCSYMBOLSIZE, ///< 49 override ECC symbol size
- IDS_CPU_Early_Override, ///< 4a override CPU early parameter
- IDS_CACHE_FLUSH_HLT, ///< 4b override Cache Flush Hlt
- IDS_CHANNEL_INTERLEAVE, ///< 4c override Channel Interleave
- IDS_MEM_ERROR_RECOVERY, ///< 4d override memory error recovery
- IDS_MEM_RETRAIN_TIMES, ///< 4e override memory retrain times
- IDS_MEM_SIZE_OVERLAY, ///< 4f Override the syslimit
- IDS_HT_ASSIST, ///< 50 Override Probe Filter
- IDS_CHECK_NEGATIVE_WL, ///< 51 Check for negative write leveling result
- IDS_DLL_SHUT_DOWN, ///< 52 Check for Dll Shut Down
- IDS_POR_MEM_FREQ, ///< 53 Entry to enable/disable MemClk frequency enforcement
- IDS_PHY_DLL_STANDBY_CTRL, ///< 54 Enable/Disable Phy DLL standby feature
- IDS_PLATFORMCFG_OVERRIDE, ///< 55 Hook for Override PlatformConfig structure
- IDS_LOADCARD_ERROR_RECOVERY, ///< 56 Special error handling for load card support
- IDS_MEM_IGNORE_ERROR, ///< 57 Ignore error and do not do fatal exit in memory
- IDS_GNB_SMU_SERVICE_CONFIG, ///< 58 Config GNB SMU service
- IDS_GNB_ORBDYNAMIC_WAKE, ///< 59 config GNB dynamic wake
- IDS_GNB_PLATFORMCFG_OVERRIDE, ///< 5a override ids gnb platform config
- IDS_GNB_LCLK_DPM_EN, ///< 5b override GNB LCLK DPM configuration
- IDS_GNB_LCLK_DEEP_SLEEP, ///< 5c override GNB LCLK DPM deep sleep
- IDS_GNB_CLOCK_GATING, ///< 5d Override GNB Clock gating config
- IDS_NB_PSTATE_DIDVID, ///< 5e Override NB P-state settings
- IDS_CPB_CTRL, ///< 5f Config the Core peformance boost feature
- IDS_HTC_CTRL, ///< 60 Hook for Hardware Thermal Control
- IDS_CC6_WORKAROUND, ///< 61 Hook for skip CC6 work around
- IDS_MEM_MR0, ///< 62 Hook for override Memory Mr0 register
- IDS_REG_TABLE, ///< 63 Hook for add IDS register table to the loop
- IDS_NBBUFFERALLOCATIONATEARLY, ///< 64 Hook for override North bridge bufer allocation
- IDS_BEFORE_S3_SPECIAL, ///< 65 Hook to bypass S3 special functions
- IDS_SET_PCI_REGISTER_ENTRY, ///< 66 Hook to SetRegisterForPciEntry
- IDS_ERRATUM463_WORKAROUND, ///< 67 Hook to Erratum 463 workaround
- IDS_BEFORE_MEMCLR, ///< 68 Hook before set Memclr bit
- IDS_OVERRIDE_IO_CSTATE, ///< 69 Hook for override io C-state setting
- IDS_NBPSDIS_OVERRIDE, ///< 6a Hook for override NB pstate disable setting
- IDS_NBPS_REG_OVERRIDE, ///< 6b Hook for override Memory NBps reg
- IDS_LOW_POWER_PSTATE, ///< 6c Hook for disalbe Low power_Pstates feature
- IDS_CST_CREATE, ///< 6d Hook for create _CST
- IDS_CST_SIZE, ///< 6e Hook for get _CST size
- IDS_ENFORCE_VDDIO, ///< 6f Hook to override VDDIO
- IDS_SKIP_PERFORMANCE_OPT, ///< 70 Hook to skip performance optimization
- IDS_INIT_MEM_REG_TABLE, ///< 71 Hook for init memory register table
- IDS_SKIP_FUSED_MAX_RATE ///< 72 Hook to skip fused max rate cap
-} AGESA_IDS_OPTION;
-
-#include "OptionsIds.h"
-#include "Filecode.h"
-
-/* Initialize IDS controls */
-#ifndef IDSOPT_IDS_ENABLED
- #define IDSOPT_IDS_ENABLED FALSE
-#endif
-
-#ifndef IDSOPT_CONTROL_ENABLED
- #define IDSOPT_CONTROL_ENABLED FALSE
-#endif
-
-#ifndef IDSOPT_TRACING_ENABLED
- #define IDSOPT_TRACING_ENABLED FALSE
-#endif
-
-#ifndef IDSOPT_TRACE_USER_OPTIONS
- #define IDSOPT_TRACE_USER_OPTIONS TRUE
-#endif
-
-#ifndef IDSOPT_PERF_ANALYSIS
- #define IDSOPT_PERF_ANALYSIS FALSE
-#endif
-
-#ifndef IDSOPT_HEAP_CHECKING
- #define IDSOPT_HEAP_CHECKING FALSE
-#endif
-
-#ifndef IDSOPT_ASSERT_ENABLED
- #define IDSOPT_ASSERT_ENABLED FALSE
-#endif
-
-#ifndef IDSOPT_ERROR_TRAP_ENABLED
- #define IDSOPT_ERROR_TRAP_ENABLED FALSE
-#endif
-
-#ifndef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
- #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE
-#endif
-
-#ifndef IDSOPT_DEBUG_CODE_ENABLED
- #define IDSOPT_DEBUG_CODE_ENABLED FALSE
-#endif
-
-#ifndef IDSOPT_C_OPTIMIZATION_DISABLED
- #define IDSOPT_C_OPTIMIZATION_DISABLED FALSE
-#endif
-
-#if IDSOPT_IDS_ENABLED == FALSE
- #undef IDSOPT_CONTROL_ENABLED
- #undef IDSOPT_TRACING_ENABLED
- #undef IDSOPT_PERF_ANALYSIS
- #undef IDSOPT_HEAP_CHECKING
- #undef IDSOPT_ASSERT_ENABLED
- #undef IDSOPT_ERROR_TRAP_ENABLED
- #undef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
- #undef IDSOPT_DEBUG_CODE_ENABLED
- #undef IDSOPT_TRACE_USER_OPTIONS
-
- #define IDSOPT_CONTROL_ENABLED FALSE
- #define IDSOPT_TRACING_ENABLED FALSE
- #define IDSOPT_PERF_ANALYSIS FALSE
- #define IDSOPT_HEAP_CHECKING FALSE
- #define IDSOPT_ASSERT_ENABLED FALSE
- #define IDSOPT_ERROR_TRAP_ENABLED FALSE
- #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE
- #define IDSOPT_DEBUG_CODE_ENABLED FALSE
- #define IDSOPT_TRACE_USER_OPTIONS FALSE
-#endif
-
-/**
- * Make a Progress Report to the User.
- *
- * This Macro is always enabled. The default action is to write the TestPoint value
- * to an I/O port. The I/O port is 8 bits in size and the default address is 0x80.
- * IBVs can change AGESA's default port by defining IDS_DEBUG_PORT to desired port
- * in OptionsIds.h in their build tip.
- *
- * @param[in] TestPoint The value for display indicating progress
- * @param[in,out] StdHeader Pointer of AMD_CONFIG_PARAMS
- *
- **/
-
-#define AGESA_TESTPOINT(TestPoint, StdHeader)
-
-#ifndef IDS_DEBUG_PORT
- #define IDS_DEBUG_PORT 0x80
-#endif
-
-/**
- * @def STOP_HERE
- * (macro) - Causes program to halt. This is @b only for use during active debugging .
- *
- * Causes the program to halt and display the file number of the source of the
- * halt (displayed in decimal).
- *
- **/
-#if IDSOPT_IDS_ENABLED == TRUE
- #ifdef STOP_CODE
- #undef STOP_CODE
- #endif
- #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \
- ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
- (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
- #define STOP_HERE
-#else
- #define STOP_HERE
-#endif
-
-/**
- * @def ASSERT
- * Test an assertion that the given statement is True.
- *
- * The statement is evaluated to a boolean value. If the statement is True,
- * then no action is taken (no error). If the statement is False, a error stop
- * is generated to halt the program. Used for testing for fatal errors that
- * must be resolved before production. This is used to do parameter checks,
- * bounds checking, range checks and 'sanity' checks.
- *
- * @param[in] conditional Assert that evaluating this conditional results in TRUE.
- *
- **/
-#ifndef ASSERT
- #if IDSOPT_ASSERT_ENABLED == TRUE
- #ifdef STOP_CODE
- #undef STOP_CODE
- #endif
- #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \
- ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
- (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
-
- #define ASSERT(conditional)
- #else
- #define ASSERT(conditional)
- #endif
-#endif
-
-#if IDSOPT_CAR_CORRUPTION_CHECK_ENABLED == TRUE
- #undef IDSOPT_ERROR_TRAP_ENABLED
- #define IDSOPT_ERROR_TRAP_ENABLED TRUE
- #define IDS_CAR_CORRUPTION_CHECK(StdHeader)
-#else
- #define IDS_CAR_CORRUPTION_CHECK(StdHeader)
-#endif
-/**
- * @def DEBUG_CODE
- * Make the code active when IDSOPT_DEBUG_CODE_ENABLED enable
- *
- */
-#ifndef DEBUG_CODE
- #if IDSOPT_DEBUG_CODE_ENABLED == TRUE
- #define DEBUG_CODE(Code)
- #else
- #define DEBUG_CODE(Code)
- #endif
-#endif
-
-/**
- * @def IDS_ERROR_TRAP
- * Trap AGESA Error events with stop code display.
- *
- * Works similarly to use of "ASSERT (FALSE);"
- *
- */
-#if IDSOPT_ERROR_TRAP_ENABLED == TRUE
- #ifdef STOP_CODE
- #undef STOP_CODE
- #endif
- #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \
- ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
- (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
-
- #define IDS_ERROR_TRAP
-#else
- #define IDS_ERROR_TRAP
-#endif
-
-///give the extended Macro default value
-#ifndef __IDS_EXTENDED__
- #define IDS_EXTENDED_HOOK(idsoption, dataptr, idsnvptr, stdheader) IDS_SUCCESS
- #define IDS_INITIAL_F10_PM_STEP
- #define IDS_INITIAL_F12_PM_STEP
- #define IDS_INITIAL_F14_PM_STEP
- #define IDS_INITIAL_F15_PM_STEP
- #define IDS_EXTENDED_GET_DATA_EARLY(data, StdHeader)
- #define IDS_EXTENDED_GET_DATA_LATE(data, StdHeader)
- #define IDS_EXTENDED_HEAP_SIZE 0
- #define IDS_EXT_INCLUDE_F10(file)
- #define IDS_EXT_INCLUDE_F12(file)
- #define IDS_EXT_INCLUDE_F14(file)
- #define IDS_EXT_INCLUDE_F15(file)
- #define IDS_EXT_INCLUDE(file)
-#endif
-
-#ifndef IDS_NUM_NV_ITEM
- #define IDS_NUM_NV_ITEM (IDS_NUM_EXT_NV_ITEM)
-#endif
-
-#if IDSOPT_CONTROL_ENABLED == TRUE
- #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader)
-
- #define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader)
-#else
- #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader)
-
- #define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader)
-#endif
-
-/**
- * Macro to add a *skip* hook for IDS options
- *
- * The default minimal action is to do nothing and there is no any code to increase.
- * For debug environments, IDS dispatcher function will be called to perform
- * the detailed action and to skip AGESA code if necessary.
- *
- * @param[in] IdsOption IDS Option ID for this hook point
- * @param[in, out] DataPtr Data Pointer to override
- * @param[in, out] StdHeader Pointer of AMD_CONFIG_PARAMS
- *
- *
- **/
-
-#if IDSOPT_CONTROL_ENABLED == TRUE
- #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader)
-#else
- #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader)
-#endif
-
-/**
- * Macro to add a heap manager routine
- *
- * when memory is allocated the heap manager actually allocates two extra dwords of data,
- * one dword buffer before the actual memory, and one dword afterwards.
- * a complete heap walk and check to be performed at any time.
- * it would ASSERT if the heap is corrupt
- *
- * @param[in] StdHeader Pointer of AMD_CONFIG_PARAMS
- *
- *
- **/
-
-// Heap debug feature
-#define SENTINEL_BEFORE_VALUE 0x64616548 // "Head"
-#define SENTINEL_AFTER_VALUE 0x6C696154 // "Tail"
-#if IDSOPT_IDS_ENABLED == TRUE
- #if IDSOPT_HEAP_CHECKING == TRUE
- #define SIZE_OF_SENTINEL 0
- #define NUM_OF_SENTINEL 0
- #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte)
- #define SET_SENTINEL_AFTER(NodePtr)
- #define Heap_Check(stdheader)
- #else
- #define SIZE_OF_SENTINEL 0
- #define NUM_OF_SENTINEL 0
- #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte)
- #define SET_SENTINEL_AFTER(NodePtr)
- #define Heap_Check(stdheader)
- #endif
-#else
- #define SIZE_OF_SENTINEL 0
- #define NUM_OF_SENTINEL 0
- #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte)
- #define SET_SENTINEL_AFTER(NodePtr)
- #define Heap_Check(stdheader)
-#endif
-
-
- //Note a is from 0 to 63
-#define DEBUG_PRINT_SHIFT(a) ((UINT64)1 << a)
-//If you change the Bitmap definition below, please change the Hash in ParseFilter of hdtout2008.pl accordingly
-//Memory Masks
-#define MEM_SETREG DEBUG_PRINT_SHIFT (0)
-#define MEM_GETREG DEBUG_PRINT_SHIFT (1)
-#define MEM_FLOW DEBUG_PRINT_SHIFT (2)
-#define MEM_STATUS DEBUG_PRINT_SHIFT (3)
-#define MEMORY_TRACE_RSV1 DEBUG_PRINT_SHIFT (4)
-#define MEMORY_TRACE_RSV2 DEBUG_PRINT_SHIFT (5)
-#define MEMORY_TRACE_RSV3 DEBUG_PRINT_SHIFT (6)
-#define MEMORY_TRACE_RSV4 DEBUG_PRINT_SHIFT (7)
-#define MEMORY_TRACE_RSV5 DEBUG_PRINT_SHIFT (8)
-#define MEMORY_TRACE_RSV6 DEBUG_PRINT_SHIFT (9)
-
-
-
-//CPU Masks
-#define CPU_TRACE DEBUG_PRINT_SHIFT (10)
-#define CPU_TRACE_RSV1 DEBUG_PRINT_SHIFT (11)
-#define CPU_TRACE_RSV2 DEBUG_PRINT_SHIFT (12)
-#define CPU_TRACE_RSV3 DEBUG_PRINT_SHIFT (13)
-#define CPU_TRACE_RSV4 DEBUG_PRINT_SHIFT (14)
-#define CPU_TRACE_RSV5 DEBUG_PRINT_SHIFT (15)
-#define CPU_TRACE_RSV6 DEBUG_PRINT_SHIFT (16)
-#define CPU_TRACE_RSV7 DEBUG_PRINT_SHIFT (17)
-#define CPU_TRACE_RSV8 DEBUG_PRINT_SHIFT (18)
-#define CPU_TRACE_RSV9 DEBUG_PRINT_SHIFT (19)
-
-//GNB Masks
-#define GNB_TRACE DEBUG_PRINT_SHIFT (20)
-#define PCIE_MISC DEBUG_PRINT_SHIFT (21)
-#define PCIE_PORTREG_TRACE DEBUG_PRINT_SHIFT (22)
-#define PCIE_HOSTREG_TRACE DEBUG_PRINT_SHIFT (23)
-#define GNB_TRACE_RSV2 DEBUG_PRINT_SHIFT (24)
-#define NB_MISC DEBUG_PRINT_SHIFT (25)
-#define GNB_TRACE_RSV3 DEBUG_PRINT_SHIFT (26)
-#define GFX_MISC DEBUG_PRINT_SHIFT (27)
-#define NB_SMUREG_TRACE DEBUG_PRINT_SHIFT (28)
-#define GNB_TRACE_RSV1 DEBUG_PRINT_SHIFT (29)
-
-//HT Masks
-#define HT_TRACE DEBUG_PRINT_SHIFT (30)
-#define HT_TRACE_RSV1 DEBUG_PRINT_SHIFT (31)
-#define HT_TRACE_RSV2 DEBUG_PRINT_SHIFT (32)
-#define HT_TRACE_RSV3 DEBUG_PRINT_SHIFT (33)
-#define HT_TRACE_RSV4 DEBUG_PRINT_SHIFT (34)
-#define HT_TRACE_RSV5 DEBUG_PRINT_SHIFT (35)
-#define HT_TRACE_RSV6 DEBUG_PRINT_SHIFT (36)
-#define HT_TRACE_RSV7 DEBUG_PRINT_SHIFT (37)
-#define HT_TRACE_RSV8 DEBUG_PRINT_SHIFT (38)
-#define HT_TRACE_RSV9 DEBUG_PRINT_SHIFT (39)
-
-//FCH Masks
-#define FCH_TRACE DEBUG_PRINT_SHIFT (40)
-#define FCH_TRACE_RSV1 DEBUG_PRINT_SHIFT (41)
-#define FCH_TRACE_RSV2 DEBUG_PRINT_SHIFT (42)
-#define FCH_TRACE_RSV3 DEBUG_PRINT_SHIFT (43)
-#define FCH_TRACE_RSV4 DEBUG_PRINT_SHIFT (44)
-#define FCH_TRACE_RSV5 DEBUG_PRINT_SHIFT (45)
-#define FCH_TRACE_RSV6 DEBUG_PRINT_SHIFT (46)
-#define FCH_TRACE_RSV7 DEBUG_PRINT_SHIFT (47)
-#define FCH_TRACE_RSV8 DEBUG_PRINT_SHIFT (48)
-#define FCH_TRACE_RSV9 DEBUG_PRINT_SHIFT (49)
-
-//Other Masks
-#define MAIN_FLOW DEBUG_PRINT_SHIFT (50)
-#define EVENT_LOG DEBUG_PRINT_SHIFT (51)
-#define PERFORMANCE_ANALYSE DEBUG_PRINT_SHIFT (52)
-
-//Ids Masks
-#define IDS_TRACE DEBUG_PRINT_SHIFT (53)
-#define IDS_REG DEBUG_PRINT_SHIFT (54)
-#define IDS_TRACE_RSV2 DEBUG_PRINT_SHIFT (55)
-#define IDS_TRACE_RSV3 DEBUG_PRINT_SHIFT (56)
-
-//S3
-#define S3_TRACE DEBUG_PRINT_SHIFT (57)
-
-
-//Reserved
-#define TRACE_RSV1 DEBUG_PRINT_SHIFT (58)
-#define TRACE_RSV2 DEBUG_PRINT_SHIFT (59)
-#define TRACE_RSV3 DEBUG_PRINT_SHIFT (60)
-#define TRACE_RSV4 DEBUG_PRINT_SHIFT (61)
-#define TRACE_RSV5 DEBUG_PRINT_SHIFT (62)
-#define TRACE_RSV6 DEBUG_PRINT_SHIFT (63)
-
-#define GNB_TRACE_DEFAULT 0
-
-#define GNB_TRACE_REG 0
-
-#define GNB_TRACE_ALL 0
-
-#define CPU_TRACE_ALL 0
-
-#define MEMORY_TRACE_ALL 0
-
-#define HT_TRACE_ALL 0
-
-#define FCH_TRACE_ALL 0
-
-#define IDS_TRACE_ALL 0
-
-#define OTHER_TRACE_ALL 0
-
-#define TRACE_MASK_ALL (0ull)
-#ifndef IDS_DEBUG_PRINT_MASK
- #define IDS_DEBUG_PRINT_MASK 0
-#endif
-
-
-/**
- * Macro to add HDT OUT
- *
- * The default minimal action is to do nothing and there is no any code to increase.
- * For debug environments, the debug information can be displayed in HDT or other
- * devices.
- *
- **/
-#if IDSOPT_IDS_ENABLED == TRUE
- #if IDSOPT_TRACING_ENABLED == TRUE
- #define IDS_HDT_CONSOLE_INIT(x)
- #define IDS_HDT_CONSOLE_EXIT(x)
- #define IDS_HDT_CONSOLE_S3_EXIT(x)
- #define IDS_HDT_CONSOLE_S3_AP_EXIT(x)
-
- #if IDSOPT_C_OPTIMIZATION_DISABLED == TRUE
- #ifdef __GNUC__
- #define IDS_HDT_CONSOLE(f, s, ...)
- #else
- #define IDS_HDT_CONSOLE(f, s, ...)
- #endif
- #else
- #pragma warning(disable: 4127)
- #ifdef __GNUC__
- #define IDS_HDT_CONSOLE(f, s, ...)
- #else
- #define IDS_HDT_CONSOLE(f, s, ...)
- #endif
- #endif
-
- #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x)
- #define IDS_HDT_CONSOLE_ASSERT(x)
- #define IDS_FUNCLIST_ADDR NULL
- #define IDS_FUNCLIST_EXTERN()
- #define IDS_TIMEOUT_CTL(t)
- #define IDS_HDT_CONSOLE_DEBUG_CODE(Code)
- #define CONSOLE(s, ...)
- #else
- #define IDS_HDT_CONSOLE_INIT(x)
- #define IDS_HDT_CONSOLE_EXIT(x)
- #define IDS_HDT_CONSOLE_S3_EXIT(x)
- #define IDS_HDT_CONSOLE_S3_AP_EXIT(x)
- #define IDS_HDT_CONSOLE(f, s, ...)
- #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x)
- #define IDS_HDT_CONSOLE_ASSERT(x)
- #define IDS_FUNCLIST_ADDR NULL
- #define IDS_FUNCLIST_EXTERN()
- #define IDS_TIMEOUT_CTL(t)
- #define IDS_HDT_CONSOLE_DEBUG_CODE(Code)
- #define CONSOLE(s, ...)
- #endif
-#else
- #define IDS_HDT_CONSOLE_INIT(x)
- #define IDS_HDT_CONSOLE_EXIT(x)
- #define IDS_HDT_CONSOLE_S3_EXIT(x)
- #define IDS_HDT_CONSOLE_S3_AP_EXIT(x)
- #define IDS_HDT_CONSOLE(f, s, ...)
- #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x)
- #define IDS_HDT_CONSOLE_ASSERT(x)
- #define IDS_FUNCLIST_ADDR NULL
- #define IDS_FUNCLIST_EXTERN()
- #define IDS_TIMEOUT_CTL(t)
- #define IDS_HDT_CONSOLE_DEBUG_CODE(Code)
- #define CONSOLE(s, ...)
-#endif
-
-#define IDS_TRACE_SHOW_BLD_OPT_CFG IDSOPT_TRACE_USER_OPTIONS
-
-#if IDSOPT_PERF_ANALYSIS == TRUE
- #define IDS_PERF_TIMESTAMP(StdHeader, TestPoint)
- #define IDS_PERF_ANALYSE(StdHeader)
- #define IDS_PERF_TIME_MEASURE(StdHeader)
-#else
- #define IDS_PERF_TIMESTAMP(StdHeader, TestPoint)
- #define IDS_PERF_ANALYSE(StdHeader)
- #define IDS_PERF_TIME_MEASURE(StdHeader)
-#endif
-
-///For IDS feat use
-#define IDS_FAMILY_ALL 0x0ull
-#define IDS_BSP_ONLY TRUE
-#define IDS_ALL_CORES FALSE
-
-#define IDS_LATE_RUN_AP_TASK_ID PROC_IDS_CONTROL_IDSLIB_FILECODE
-
-#define IDS_CALLOUT_INIT 0x00 ///< The function data of IDS callout function of initialization.
-
-#define IDS_CALLOUT_GNB_PPFUSE_OVERRIDE 0x00 ///< The function data of IDS callout function of GNB pp fuse table.
-#define IDS_CALLOUT_GNB_INTEGRATED_TABLE_CONFIG 0x00 ///< The function data of IDS callout function of GNB integrated table.
-#define IDS_CALLOUT_GNB_NB_POWERGATE_CONFIG 0x00 ///< The function data of IDS callout function of GNB NB power gate config.
-#define IDS_CALLOUT_GNB_PCIE_POWERGATE_CONFIG 0x00 ///< The function data of IDS callout function of GNB PCIE power gateconfig.
-#define IDS_CALLOUT_GNB_PCIE_PLATFORM_CONFIG 0x00 ///< The function data of IDS callout function of GNB pcie platform config.
-#define IDS_CALLOUT_GNB_PCIE_PHY_CONFIG 0x00 ///< The function data of IDS callout function of GNB pcie PHY config.
-#define IDS_CALLOUT_GNB_GMM_REGISTER_OVERRIDE 0x00 ///< The function data of IDS callout function of GNB GMM register override
-
-/// Function entry for HDT script to call
-typedef struct _SCRIPT_FUNCTION {
- UINT32 FuncAddr; ///< Function address in ROM
- CHAR8 FuncName[40]; ///< Function name
-} SCRIPT_FUNCTION;
-
-/// Data Structure for Mem ECC parameter override
-typedef struct {
- IN BOOLEAN CfgEccRedirection; ///< ECC Redirection
- IN UINT16 CfgScrubDramRate; ///< Scrub Dram Rate
- IN UINT16 CfgScrubL2Rate; ///< Scrub L2Rate
- IN UINT16 CfgScrubL3Rate; ///< Scrub L3Rate
- IN UINT16 CfgScrubIcRate; ///< Scrub Ic Rate
- IN UINT16 CfgScrubDcRate; ///< Scrub Dc Rate
- IN BOOLEAN CfgEccSyncFlood; ///< ECC Sync Flood
-} ECC_OVERRIDE_STRUCT;
-
-
-
-
-/**
- * AGESA Test Points
- *
- * These are the values displayed to the user to indicate progress through boot.
- * These can be used in a debug environment to stop the debugger at a specific
- * test point:
- * For SimNow!, this command
- * bi 81 w vb 49
- * will stop the debugger on one of the TracePoints (49 is the TP value in this example).
- *
- */
-typedef enum {
- StartProcessorTestPoints, ///< 00 Entry used for range testing for @b Processor related TPs
-
- // Memory test points
- TpProcMemBeforeMemDataInit, ///< 01 .. Memory structure initialization (Public interface)
- TpProcMemBeforeSpdProcessing, ///< 02 .. SPD Data processing (Public interface)
- TpProcMemAmdMemAuto, ///< 03 .. Memory configuration (Public interface)
- TpProcMemDramInit, ///< 04 .. DRAM initialization
- TpProcMemSPDChecking, ///< 05 ..
- TpProcMemModeChecking, ///< 06 ..
- TpProcMemSpeedTclConfig, ///< 07 .. Speed and TCL configuration
- TpProcMemSpdTiming, ///< 08 ..
- TpProcMemDramMapping, ///< 09 ..
- TpProcMemPlatformSpecificConfig, ///< 0A ..
- TPProcMemPhyCompensation, ///< 0B ..
- TpProcMemStartDcts, ///< 0C ..
- TpProcMemBeforeDramInit, ///< 0D .. (Public interface)
- TpProcMemPhyFenceTraining, ///< 0E ..
- TpProcMemSynchronizeDcts, ///< 0F ..
- TpProcMemSystemMemoryMapping, ///< 10 ..
- TpProcMemMtrrConfiguration, ///< 11 ..
- TpProcMemDramTraining, ///< 12 ..
- TpProcMemBeforeAnyTraining, ///< 13 .. (Public interface)
- TpProcMemWriteLevelizationTraining, ///< 14 ..
- TpProcMemWlFirstPass, ///< 15 .. Below 800Mhz first pass start
- TpProcMemWlSecondPass, ///< 16 .. Above 800Mhz second pass start
- TpProcMemWlDimmConfig, ///< 17 .. Target DIMM configured
- TpProcMemWlPrepDimms, ///< 18 .. Prepare DIMMS for WL
- TpProcMemWlConfigDimms, ///< 19 .. Configure DIMMS for WL
- TpProcMemReceiverEnableTraining, ///< 1A ..
- TpProcMemRcvrStartSweep, ///< 1B .. Start sweep loop
- TpProcMemRcvrSetDelay, ///< 1C .. Set receiver Delay
- TpProcMemRcvrWritePattern, ///< 1D .. Write test pattern
- TpProcMemRcvrReadPattern, ///< 1E .. Read test pattern
- TpProcMemRcvrTestPattern, ///< 1F .. Compare test pattern
- TpProcMemRcvrCalcLatency, ///< 20 .. Calculate MaxRdLatency per channel
- TpProcMemReceiveDqsTraining, ///< 21 ..
- TpProcMemRcvDqsSetDelay, ///< 22 .. Set Write Data delay
- TpProcMemRcvDqsWritePattern, ///< 23 .. Write test pattern
- TpProcMemRcvDqsStartSweep, ///< 24 .. Start read sweep
- TpProcMemRcvDqsSetRcvDelay, ///< 25 .. Set Receive DQS delay
- TpProcMemRcvDqsReadPattern, ///< 26 .. Read Test pattern
- TpProcMemRcvDqsTstPattern, ///< 27 .. Compare Test pattern
- TpProcMemRcvDqsResults, ///< 28 .. Update results
- TpProcMemRcvDqsFindWindow, ///< 29 .. Start Find passing window
- TpProcMemTransmitDqsTraining, ///< 2A ..
- TpProcMemTxDqStartSweep, ///< 2B .. Start write sweep
- TpProcMemTxDqSetDelay, ///< 2C .. Set Transmit DQ delay
- TpProcMemTxDqWritePattern, ///< 2D .. Write test pattern
- TpProcMemTxDqReadPattern, ///< 2E .. Read Test pattern
- TpProcMemTxDqTestPattern, ///< 2F .. Compare Test pattern
- TpProcMemTxDqResults, ///< 30 .. Update results
- TpProcMemTxDqFindWindow, ///< 31 .. Start Find passing window
- TpProcMemMaxRdLatencyTraining, ///< 32 ..
- TpProcMemMaxRdLatStartSweep, ///< 33 .. Start sweep
- TpProcMemMaxRdLatSetDelay, ///< 34 .. Set delay
- TpProcMemMaxRdLatWritePattern, ///< 35 .. Write test pattern
- TpProcMemMaxRdLatReadPattern, ///< 36 .. Read Test pattern
- TpProcMemMaxRdLatTestPattern, ///< 37 .. Compare Test pattern
- TpProcMemOnlineSpareInit, ///< 38 .. Online Spare init
- TpProcMemBankInterleaveInit, ///< 39 .. Bank Interleave Init
- TpProcMemNodeInterleaveInit, ///< 3A .. Node Interleave Init
- TpProcMemChannelInterleaveInit, ///< 3B .. Channel Interleave Init
- TpProcMemEccInitialization, ///< 3C .. ECC initialization
- TpProcMemPlatformSpecificInit, ///< 3D .. Platform Specific Init
- TpProcMemBeforeAgesaReadSpd, ///< 3E .. Before callout for "AgesaReadSpd"
- TpProcMemAfterAgesaReadSpd, ///< 3F .. After callout for "AgesaReadSpd"
- TpProcMemBeforeAgesaHookBeforeDramInit, ///< 40 .. Before optional callout "AgesaHookBeforeDramInit"
- TpProcMemAfterAgesaHookBeforeDramInit, ///< 41 .. After optional callout "AgesaHookBeforeDramInit"
- TpProcMemBeforeAgesaHookBeforeDQSTraining, ///< 42 .. Before optional callout "AgesaHookBeforeDQSTraining"
- TpProcMemAfterAgesaHookBeforeDQSTraining, ///< 43 .. After optional callout "AgesaHookBeforeDQSTraining"
- TpProcMemBeforeAgesaHookBeforeExitSelfRef, ///< 44 .. Before optional callout "AgesaHookBeforeDramInit"
- TpProcMemAfterAgesaHookBeforeExitSelfRef, ///< 45 .. After optional callout "AgesaHookBeforeDramInit"
- TpProcMemAfterMemDataInit, ///< 46 .. After MemDataInit
- TpProcMemInitializeMCT, ///< 47 .. Before InitializeMCT
- TpProcMemLvDdr3, ///< 48 .. Before LV DDR3
- TpProcMemInitMCT, ///< 49 .. Before InitMCT
- TpProcMemOtherTiming, ///< 4A.. Before OtherTiming
- TpProcMemUMAMemTyping, ///< 4B .. Before UMAMemTyping
- TpProcMemSetDqsEccTmgs, ///< 4C .. Before SetDqsEccTmgs
- TpProcMemMemClr, ///< 4D .. Before MemClr
- TpProcMemOnDimmThermal, ///< 4E .. Before On DIMM Thermal
- TpProcMemDmi, ///< 4F .. Before DMI
- TpProcMemEnd, ///< 50 .. End of memory code
-
- // CPU test points
- TpProcCpuEntryDmi, ///< 51 .. Entry point CreateDmiRecords
- TpProcCpuEntryPstate, ///< 52 .. Entry point GenerateSsdt
- TpProcCpuEntryPstateLeveling, ///< 53 .. Entry point PStateLeveling
- TpProcCpuEntryPstateGather, ///< 54 .. Entry point PStateGatherData
- TpProcCpuEntryWhea, ///< 55 .. Entry point CreateAcpiWhea
- TpProcCpuEntrySrat, ///< 56 .. Entry point CreateAcpiSrat
- TpProcCpuEntrySlit, ///< 57 .. Entry point CreateAcpiSlit
- TpProcCpuProcessRegisterTables, ///< 58 .. Register table processing
- TpProcCpuSetBrandID, ///< 59 .. Set brand ID
- TpProcCpuLocalApicInit, ///< 5A .. Initialize local APIC
- TpProcCpuLoadUcode, ///< 5B .. Load microcode patch
- TpProcCpuBeforePMFeatureInit, ///< 5C .. BeforePM feature dispatch point
- TpProcCpuPowerMgmtInit, ///< 5D .. Power Management table processing
- TpProcCpuEarlyFeatureInit, ///< 5E .. Early feature dispatch point
- TpProcCpuCoreLeveling, ///< 5F .. Core Leveling
- TpProcCpuApMtrrSync, ///< 60 .. AP MTRR sync up
- TpProcCpuPostFeatureInit, ///< 61 .. POST feature dispatch point
- TpProcCpuFeatureLeveling, ///< 62 .. CPU Feature Leveling
- TpProcCpuBeforeAllocateWheaBuffer, ///< 63 .. Before the WHEA init code calls out to allocate a buffer
- TpProcCpuAfterAllocateWheaBuffer, ///< 64 .. After the WHEA init code calls out to allocate a buffer
- TpProcCpuBeforeAllocateSratBuffer, ///< 65 .. Before the SRAT init code calls out to allocate a buffer
- TpProcCpuAfterAllocateSratBuffer, ///< 66 .. After the SRAT init code calls out to allocate a buffer
- TpProcCpuBeforeLocateSsdtBuffer, ///< 67 .. Before the P-state init code calls out to locate a buffer
- TpProcCpuAfterLocateSsdtBuffer, ///< 68 .. After the P-state init code calls out to locate a buffer
- TpProcCpuBeforeAllocateSsdtBuffer, ///< 69 .. Before the P-state init code calls out to allocate a buffer
- TpProcCpuAfterAllocateSsdtBuffer, ///< 6A .. After the P-state init code calls out to allocate a buffer
-
- // HT test points
- TpProcHtEntry = 0x71, ///< 71 .. Coherent Discovery begin (Public interface)
- TpProcHtTopology, ///< 72 .. Topology match, routing, begin
- TpProcHtManualNc, ///< 73 .. Manual Non-coherent Init begin
- TpProcHtAutoNc, ///< 74 .. Automatic Non-coherent init begin
- TpProcHtOptGather, ///< 75 .. Optimization: Gather begin
- TpProcHtOptRegang, ///< 76 .. Optimization: Regang begin
- TpProcHtOptLinks, ///< 77 .. Optimization: Link Begin
- TpProcHtOptSubLinks, ///< 78 .. Optimization: Sublinks begin
- TpProcHtOptFinish, ///< 79 .. Optimization: Set begin
- TpProcHtTrafficDist, ///< 7A .. Traffic Distribution begin
- TpProcHtTuning, ///< 7B .. Misc Tuning Begin
- TpProcHtDone, ///< 7C .. HT Init complete
- TpProcHtApMapEntry, ///< 7D .. AP HT: Init Maps begin
- TpProcHtApMapDone, ///< 7E .. AP HT: Complete
-
- StartNbTestPoints = 0x90, ///< 90 Entry used for range testing for @b NorthBridge related TPs
- TpNbxxx, ///< 91 .
- EndNbTestPoints, ///< 92 End of TP range for NB
-
- StartSbTestPoints = 0xB0, ///< B0 Entry used for range testing for @b SouthBridge related TPs
- TpSbxxx, ///< B1 .
- EndSbTestPoints, ///< B2 End of TP range for SB
-
- // Interface test points
- TpIfAmdInitResetEntry = 0xC0, ///< C0 .. Entry to AmdInitReset
- TpIfAmdInitResetExit, ///< C1 .. Exiting from AmdInitReset
- TpIfAmdInitRecoveryEntry, ///< C2 .. Entry to AmdInitRecovery
- TpIfAmdInitRecoveryExit, ///< C3 .. Exiting from AmdInitRecovery
- TpIfAmdInitEarlyEntry, ///< C4 .. Entry to AmdInitEarly
- TpIfAmdInitEarlyExit, ///< C5 .. Exiting from AmdInitEarly
- TpIfAmdInitPostEntry, ///< C6 .. Entry to AmdInitPost
- TpIfAmdInitPostExit, ///< C7 .. Exiting from AmdInitPost
- TpIfAmdInitEnvEntry, ///< C8 .. Entry to AmdInitEnv
- TpIfAmdInitEnvExit, ///< C9 .. Exiting from AmdInitEnv
- TpIfAmdInitMidEntry, ///< CA .. Entry to AmdInitMid
- TpIfAmdInitMidExit, ///< CB .. Exiting from AmdInitMid
- TpIfAmdInitLateEntry, ///< CC .. Entry to AmdInitLate
- TpIfAmdInitLateExit, ///< CD .. Exiting from AmdInitLate
- TpIfAmdS3SaveEntry, ///< CE .. Entry to AmdS3Save
- TpIfAmdS3SaveExit, ///< CF .. Exiting from AmdS3Save
- TpIfAmdInitResumeEntry, ///< D0 .. Entry to AmdInitResume
- TpIfAmdInitResumeExit, ///< D1 .. Exiting from AmdInitResume
- TpIfAmdS3LateRestoreEntry, ///< D2 .. Entry to AmdS3LateRestore
- TpIfAmdS3LateRestoreExit, ///< D3 .. Exiting from AmdS3LateRestore
- TpIfAmdLateRunApTaskEntry, ///< D4 .. Entry to AmdS3LateRestore
- TpIfAmdLateRunApTaskExit, ///< D5 .. Exiting from AmdS3LateRestore
- TpIfAmdReadEventLogEntry, ///< D6 .. Entry to AmdReadEventLog
- TpIfAmdReadEventLogExit, ///< D7 .. Exiting from AmdReadEventLog
- TpIfAmdGetApicIdEntry, ///< D8 .. Entry to AmdGetApicId
- TpIfAmdGetApicIdExit, ///< D9 .. Exiting from AmdGetApicId
- TpIfAmdGetPciAddressEntry, ///< DA .. Entry to AmdGetPciAddress
- TpIfAmdGetPciAddressExit, ///< DB .. Exiting from AmdGetPciAddress
- TpIfAmdIdentifyCoreEntry, ///< DC .. Entry to AmdIdentifyCore
- TpIfAmdIdentifyCoreExit, ///< DD .. Exiting from AmdIdentifyCore
- TpIfBeforeRunApFromIds, ///< DE .. After IDS calls out to run code on an AP
- TpIfAfterRunApFromIds, ///< DF .. After IDS calls out to run code on an AP
- TpIfBeforeGetIdsData, ///< E0 .. Before IDS calls out to get IDS data
- TpIfAfterGetIdsData, ///< E1 .. After IDS calls out to get IDS data
- TpIfBeforeAllocateHeapBuffer, ///< E2 .. Before the heap manager calls out to allocate a buffer
- TpIfAfterAllocateHeapBuffer, ///< E3 .. After the heap manager calls out to allocate a buffer
- TpIfBeforeDeallocateHeapBuffer, ///< E4 .. Before the heap manager calls out to deallocate a buffer
- TpIfAfterDeallocateHeapBuffer, ///< E5 .. After the heap manager calls out to deallocate a buffer
- TpIfBeforeLocateHeapBuffer, ///< E6 .. Before the heap manager calls out to locate a buffer
- TpIfAfterLocateHeapBuffer, ///< E7 .. After the heap manager calls out to locate a buffer
- TpIfBeforeRunApFromAllAps, ///< E8 .. Before the BSP calls out to run code on an AP
- TpIfAfterRunApFromAllAps, ///< E9 .. After the BSP calls out to run code on an AP
- TpIfBeforeRunApFromAllCore0s, ///< EA .. Before the BSP calls out to run code on an AP
- TpIfAfterRunApFromAllCore0s, ///< EB .. After the BSP calls out to run code on an AP
- TpIfBeforeAllocateS3SaveBuffer, ///< EC .. Before the S3 save code calls out to allocate a buffer
- TpIfAfterAllocateS3SaveBuffer, ///< ED .. After the S3 save code calls out to allocate a buffer
- TpIfBeforeAllocateMemoryS3SaveBuffer, ///< EE .. Before the memory S3 save code calls out to allocate a buffer
- TpIfAfterAllocateMemoryS3SaveBuffer, ///< EF .. After the memory S3 save code calls out to allocate a buffer
- TpIfBeforeLocateS3PciBuffer, ///< F0 .. Before the memory code calls out to locate a buffer
- TpIfAfterLocateS3PciBuffer, ///< F1 .. After the memory code calls out to locate a buffer
- TpIfBeforeLocateS3CPciBuffer, ///< F2 .. Before the memory code calls out to locate a buffer
- TpIfAfterLocateS3CPciBuffer, ///< F3 .. After the memory code calls out to locate a buffer
- TpIfBeforeLocateS3MsrBuffer, ///< F4 .. Before the memory code calls out to locate a buffer
- TpIfAfterLocateS3MsrBuffer, ///< F5 .. After the memory code calls out to locate a buffer
- TpIfBeforeLocateS3CMsrBuffer, ///< F6 .. Before the memory code calls out to locate a buffer
- TpIfAfterLocateS3CMsrBuffer, ///< F7 .. After the memory code calls out to locate a buffer
- TpPerfUnit, ///< F8 .. The Unit of performance measure.
- EndAgesaTps = 0xFF, ///< Last defined AGESA TP
-} AGESA_TP;
-
-///Ids Feat description
-typedef enum {
- IDS_FEAT_UCODE_UPDATE = 0x0000, ///< Feat for Ucode Update
- IDS_FEAT_TARGET_PSTATE, ///< Feat for Target Pstate
- IDS_FEAT_POSTPSTATE, ///< Feat for Post Pstate
- IDS_FEAT_ECC_CTRL, ///< Feat for Ecc Control
- IDS_FEAT_ECC_SYMBOL_SIZE, ///< Feat for Ecc symbol size
- IDS_FEAT_DCT_ALLMEMCLK, ///< Feat for all memory clock
- IDS_FEAT_DCT_GANGMODE, ///< Feat for Dct gang mode
- IDS_FEAT_DCT_BURSTLENGTH, ///< Feat for dct burst length
- IDS_FEAT_DCT_POWERDOWN, ///< Feat for dct power down
- IDS_FEAT_DCT_DLLSHUTDOWN, ///< Feat for dct dll shut down
- IDS_FEAT_PROBE_FILTER, ///< Feat for probe filter
- IDS_FEAT_HDTOUT, ///< Feat for hdt out
- IDS_FEAT_HT_SETTING, ///< Feat for Ht setting
- IDS_FEAT_GNB_PLATFORMCFG, ///< Feat for override GNB platform config
- IDS_FEAT_CPB_CTRL, ///< Feat for Config the Core peformance boost feature
- IDS_FEAT_HTC_CTRL, ///< Feat for Hardware Thermal Control
- IDS_FEAT_MEMORY_MAPPING, ///< Feat for Memory Mapping
- IDS_FEAT_POWER_POLICY, ///< Feat for Power Policy
- IDS_FEAT_END = 0xFF ///< End of Common feat
-} IDS_FEAT;
-
-typedef IDS_STATUS IDS_COMMON_FUNC (
- IN OUT VOID *DataPtr,
- IN OUT AMD_CONFIG_PARAMS *StdHeader,
- IN IDS_NV_ITEM *IdsNvPtr
- );
-
-typedef IDS_COMMON_FUNC *PIDS_COMMON_FUNC;
-
-/// Data Structure of IDS Feature block
-typedef struct _IDS_FEAT_STRUCT {
- IDS_FEAT IdsFeat; ///< Ids Feat ID
- BOOLEAN IsBsp; ///< swith for Bsp check
- AGESA_IDS_OPTION IdsOption; ///< IDS option
- UINT64 CpuFamily; ///<
- PIDS_COMMON_FUNC pf_idsoption; ///<pointer to function
-} IDS_FEAT_STRUCT;
-
-
-/// Data Structure of IDS option
-typedef struct _IDS_OPTION_STRUCT {
- AGESA_IDS_OPTION idsoption; ///< IDS option
- PIDS_COMMON_FUNC pf_idsoption; ///<pointer to function
-} IDS_OPTION_STRUCT;
-
-/// Data Structure of IDS option table
-typedef struct _IDS_OPTION_STRUCT_TBL {
- UINT8 version; ///<Version of IDS option table
- UINT16 size; ///<Size of IDS option table
- CONST IDS_OPTION_STRUCT *pIdsOptionStruct; ///<pointer to array of structure
-} IDS_OPTION_STRUCT_TBL;
-
-#endif // _IDS_H_
diff --git a/src/vendorcode/amd/agesa/Include/IdsHt.h b/src/vendorcode/amd/agesa/Include/IdsHt.h
deleted file mode 100644
index 02be40b..0000000
--- a/src/vendorcode/amd/agesa/Include/IdsHt.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD IDS HyperTransport Definitions
- *
- * Contains AMD AGESA Integrated Debug HT related items.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: IDS
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _IDS_HT_H_
-#define _IDS_HT_H_
-
-// Frequency equates for call backs which take an actual frequency setting
-#define HT_FREQUENCY_200M 0
-#define HT_FREQUENCY_400M 2
-#define HT_FREQUENCY_600M 4
-#define HT_FREQUENCY_800M 5
-#define HT_FREQUENCY_1000M 6
-#define HT_FREQUENCY_1200M 7
-#define HT_FREQUENCY_1400M 8
-#define HT_FREQUENCY_1600M 9
-#define HT_FREQUENCY_1800M 10
-#define HT_FREQUENCY_2000M 11
-#define HT_FREQUENCY_2200M 12
-#define HT_FREQUENCY_2400M 13
-#define HT_FREQUENCY_2600M 14
-#define HT_FREQUENCY_2800M 17
-#define HT_FREQUENCY_3000M 18
-#define HT_FREQUENCY_3200M 19
-#define HT_FREQUENCY_3600M 20
-
-/**
- * HT IDS: HT Link Port Override params.
- *
- * Provide an absolute override of HT Link Port settings. No checking is done that
- * the settings obey limits or capabilities, this responsibility rests with the user.
- *
- * Rules for values of structure items:
- * - Socket
- * - HT_LIST_TERMINAL == end of port override list, rest of item is not accessed
- * - HT_LIST_MATCH_ANY == Match Any Socket
- * - 0 .. 7 == The matching socket
- * - Link
- * - HT_LIST_MATCH_ANY == Match Any package link (that is not the internal links)
- * - HT_LIST_MATCH_INTERNAL_LINK == Match the internal links
- * - 0 .. 7 == The matching package link. 0 .. 3 are the ganged links or sublink 0's, 4 .. 7 are the sublink1's.
- * - Frequency
- * - HT_LIST_TERMINAL == Do not override the frequency, AUTO setting
- * - HT_FREQUENCY_200M .. HT_FREQUENCY_3600M = The frequency value to use
- * - Widthin
- * - HT_LIST_TERMINAL == Do not override the width, AUTO setting
- * - 2, 4, 8, 16, 32 == The width value to use
- * - Widthout
- * - HT_LIST_TERMINAL == Do not override the width, AUTO setting
- * - 2, 4, 8, 16, 32 == The width value to use
- */
-typedef struct {
- // Match Fields
- UINT8 Socket; ///< The Socket which this port is on.
- UINT8 Link; ///< The port for this package link on that socket.
- // Override fields
- UINT8 Frequency; ///< Absolutely override the port's frequency.
- UINT8 WidthIn; ///< Absolutely override the port's width.
- UINT8 WidthOut; ///< Absolutely override the port's width.
-} HTIDS_PORT_OVERRIDE;
-
-/**
- * A list of port overrides to search.
- */
-typedef HTIDS_PORT_OVERRIDE *HTIDS_PORT_OVERRIDE_LIST;
-VOID
-HtIdsGetPortOverride (
- IN BOOLEAN IsSourcePort,
- IN OUT PORT_DESCRIPTOR *Port0,
- IN OUT PORT_DESCRIPTOR *Port1,
- IN OUT HTIDS_PORT_OVERRIDE_LIST *PortOverrideList,
- IN STATE_DATA *State
- );
-
-typedef
-VOID
-F_HtIdsGetPortOverride (
- IN BOOLEAN IsSourcePort,
- IN OUT PORT_DESCRIPTOR *Port0,
- IN OUT PORT_DESCRIPTOR *Port1,
- IN OUT HTIDS_PORT_OVERRIDE_LIST *PortOverrideList,
- IN STATE_DATA *State
- );
-typedef F_HtIdsGetPortOverride* PF_HtIdsGetPortOverride;
-#endif // _IDS_HT_H
diff --git a/src/vendorcode/amd/agesa/Include/LynxInstall.h b/src/vendorcode/amd/agesa/Include/LynxInstall.h
deleted file mode 100644
index 02338f9..0000000
--- a/src/vendorcode/amd/agesa/Include/LynxInstall.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build options for a Lynx platform solution
- *
- * This file generates the defaults tables for the "Lynx" platform solution
- * set of processors. The documented build options are imported from a user
- * controlled file for processing.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Core
- * @e \$Revision: 37651 $ @e \$Date: 2010-09-09 07:05:06 +0800 (Thu, 09 Sep 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "CreateStruct.h"
-#include "cpuFeatures.h"
-#include "Table.h"
-#include "CommonReturns.h"
-#include "cpuEarlyInit.h"
-#include "cpuLateInit.h"
-#include "GnbInterface.h"
-
-/*****************************************************************************
- * Define the RELEASE VERSION string
- *
- * The Release Version string should identify the next planned release.
- * When a branch is made in preparation for a release, the release manager
- * should change/confirm that the branch version of this file contains the
- * string matching the desired version for the release. The trunk version of
- * the file should always contain a trailing 'X'. This will make sure that a
- * development build from trunk will not be confused for a released version.
- * The release manager will need to remove the trailing 'X' and update the
- * version string as appropriate for the release. The trunk copy of this file
- * should also be updated/incremented for the next expected version, + trailing 'X'
- ****************************************************************************/
- // This is the delivery package title, "LlanoPI "
- // This string MUST be exactly 8 characters long
-#define AGESA_PACKAGE_STRING {'L', 'l', 'a', 'n', 'o', 'P', 'I', ' '}
-
- // This is the release version number of the AGESA component
- // This string MUST be exactly 12 characters long
-#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '6', '.', '0', 'X', ' ', ' ', ' '}
-
-
-// The Lynx solution is defined to be family 0x12 in the FM1 socket.
-#define INSTALL_FM1_SOCKET_SUPPORT TRUE
-#define INSTALL_FAMILY_12_SUPPORT TRUE
-
-
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE (0)
-#define DFLT_SCRUB_L2_RATE (0)
-#define DFLT_SCRUB_L3_RATE (0)
-#define DFLT_SCRUB_IC_RATE (0)
-#define DFLT_SCRUB_DC_RATE (0)
-#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
-#define DFLT_VRM_SLEW_RATE (5000)
-
-
-// Instantiate all solution relevant data.
-#include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/Include/MaranelloInstall.h b/src/vendorcode/amd/agesa/Include/MaranelloInstall.h
deleted file mode 100644
index 881f32b..0000000
--- a/src/vendorcode/amd/agesa/Include/MaranelloInstall.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build options for a Maranello platform solution
- *
- * This file generates the defaults tables for the "Maranello" platform solution
- * set of processors. The documented build options are imported from a user
- * controlled file for processing.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Core
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "CreateStruct.h"
-#include "cpuFeatures.h"
-#include "Table.h"
-#include "CommonReturns.h"
-#include "cpuEarlyInit.h"
-#include "cpuLateInit.h"
-#include "GnbInterfaceStub.h"
-
-/*****************************************************************************
- * Define the RELEASE VERSION string
- *
- * The Release Version string should identify the next planned release.
- * When a branch is made in preparation for a release, the release manager
- * should change/confirm that the branch version of this file contains the
- * string matching the desired version for the release. The trunk version of
- * the file should always contain a trailing 'X'. This will make sure that a
- * development build from trunk will not be confused for a released version.
- * The release manager will need to remove the trailing 'X' and update the
- * version string as appropriate for the release. The trunk copy of this file
- * should also be updated/incremented for the next expected version, + trailing 'X'
- ****************************************************************************/
- // This is the delivery package title, "MarG34PI"
- // This string MUST be exactly 8 characters long
-#define AGESA_PACKAGE_STRING {'O', 'r', 'o', 'c', 'h', 'i', 'P', 'I'}
-
- // This is the release version number of the AGESA component
- // This string MUST be exactly 12 characters long
-#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '6', '.', '0', 'X', ' ', ' ', ' '}
-
-
-
-// The Maranello solution is defined to be families 0x10 and 0x15 in the G34 socket.
-#define INSTALL_G34_SOCKET_SUPPORT TRUE
-#define INSTALL_FAMILY_10_SUPPORT TRUE
-#define INSTALL_FAMILY_15_SUPPORT TRUE
-
-#ifdef BLDOPT_REMOVE_FAMILY_10_SUPPORT
- #if BLDOPT_REMOVE_FAMILY_10_SUPPORT == TRUE
- #undef INSTALL_FAMILY_10_SUPPORT
- #define INSTALL_FAMILY_10_SUPPORT FALSE
- #endif
-#endif
-
-#ifdef BLDOPT_REMOVE_FAMILY_15_SUPPORT
- #if BLDOPT_REMOVE_FAMILY_15_SUPPORT == TRUE
- #undef INSTALL_FAMILY_15_SUPPORT
- #define INSTALL_FAMILY_15_SUPPORT FALSE
- #endif
-#endif
-
-
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE (0xFF)
-#define DFLT_SCRUB_L2_RATE (0x10)
-#define DFLT_SCRUB_L3_RATE (0x10)
-#define DFLT_SCRUB_IC_RATE (0)
-#define DFLT_SCRUB_DC_RATE (0x12)
-#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
-#define DFLT_VRM_SLEW_RATE (2500)
-
-
-// Instantiate all solution relevant data.
-#include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/Include/NileInstall.h b/src/vendorcode/amd/agesa/Include/NileInstall.h
deleted file mode 100644
index dac582e..0000000
--- a/src/vendorcode/amd/agesa/Include/NileInstall.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build options for a Nile platform solution
- *
- * This file generates the defaults tables for the "Nile" platform solution
- * set of processors. The documented build options are imported from a user
- * controlled file for processing.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Core
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "CreateStruct.h"
-#include "cpuFeatures.h"
-#include "Table.h"
-#include "CommonReturns.h"
-#include "cpuEarlyInit.h"
-#include "cpuLateInit.h"
-#include "GnbInterfaceStub.h"
-
-/*****************************************************************************
- * Define the RELEASE VERSION string
- *
- * The Release Version string should identify the next planned release.
- * When a branch is made in preparation for a release, the release manager
- * should change/confirm that the branch version of this file contains the
- * string matching the desired version for the release. The trunk version of
- * the file should always contain a trailing 'X'. This will make sure that a
- * development build from trunk will not be confused for a released version.
- * The release manager will need to remove the trailing 'X' and update the
- * version string as appropriate for the release. The trunk copy of this file
- * should also be updated/incremented for the next expected version, + trailing 'X'
- ****************************************************************************/
- // This is the delivery package title, "DanNiPI "
- // This string MUST be exactly 8 characters long
-#define AGESA_PACKAGE_STRING {'D', 'a', 'n', 'N', 'i', 'P', 'I', ' '}
-
- // This is the release version number of the AGESA component
- // This string MUST be exactly 12 characters long
-#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '5', '.', '0', 'X', ' ', ' ', ' '}
-
-
-// The Nile solution is defined to be family 0x10 in the ASB2 socket.
-#define INSTALL_ASB2_SOCKET_SUPPORT TRUE
-#define INSTALL_FAMILY_10_SUPPORT TRUE
-
-
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE (0)
-#define DFLT_SCRUB_L2_RATE (0)
-#define DFLT_SCRUB_L3_RATE (0)
-#define DFLT_SCRUB_IC_RATE (0)
-#define DFLT_SCRUB_DC_RATE (0)
-#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
-#define DFLT_VRM_SLEW_RATE (5000)
-
-
-// Instantiate all solution relevant data.
-#include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/Include/OptionC6Install.h b/src/vendorcode/amd/agesa/Include/OptionC6Install.h
deleted file mode 100644
index a7cc69f..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionC6Install.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: C6 C-state
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Options
- * @e \$Revision: 37456 $ @e \$Date: 2010-09-04 04:17:05 +0800 (Sat, 04 Sep 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_C6_STATE_INSTALL_H_
-#define _OPTION_C6_STATE_INSTALL_H_
-
-#include "cpuC6State.h"
-
-/* This option is designed to be included into the platform solution install
- * file. The platform solution install file will define the options status.
- * Check to validate the definition
- */
-#define OPTION_C6_STATE_FEAT
-#define F12_C6_STATE_SUPPORT
-#define F14_C6_STATE_SUPPORT
-#define F15_C6_STATE_SUPPORT
-
-#if OPTION_C6_STATE == TRUE
- #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
- #ifdef OPTION_FAMILY12H
- #if OPTION_FAMILY12H == TRUE
- #if OPTION_FAMILY12H_LN == TRUE
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
- #undef OPTION_C6_STATE_FEAT
- #define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
- extern CONST C6_FAMILY_SERVICES ROMDATA F12C6Support;
- #undef F12_C6_STATE_SUPPORT
- #define F12_C6_STATE_SUPPORT {AMD_FAMILY_12_LN, &F12C6Support},
-
- #if OPTION_EARLY_SAMPLES == TRUE
- extern F_F12_ES_C6_INIT F12C6A0Workaround;
-
- CONST F12_ES_C6_SUPPORT ROMDATA F12EarlySampleC6Support =
- {
- F12C6A0Workaround
- };
- #else
- CONST F12_ES_C6_SUPPORT ROMDATA F12EarlySampleC6Support =
- {
- (PF_F12_ES_C6_INIT) CommonVoid
- };
- #endif
-
- #endif
- #endif
- #endif
-
- #ifdef OPTION_FAMILY14H
- #if OPTION_FAMILY14H == TRUE
- #if OPTION_FAMILY14H_ON == TRUE
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
- #undef OPTION_C6_STATE_FEAT
- #define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
- extern CONST C6_FAMILY_SERVICES ROMDATA F14C6Support;
- #undef F14_C6_STATE_SUPPORT
- #define F14_C6_STATE_SUPPORT {AMD_FAMILY_14_ON, &F14C6Support},
-
- #if OPTION_EARLY_SAMPLES == TRUE
- extern F_F14_ES_IS_C6_SUPPORTED F14IsC6DisabledEarlySample;
- extern F_F14_ES_C6_INIT F14C6A0Workaround;
-
- CONST F14_ES_C6_SUPPORT ROMDATA F14EarlySampleC6Support =
- {
- F14IsC6DisabledEarlySample,
- F14C6A0Workaround
- };
- #else
- CONST F14_ES_C6_SUPPORT ROMDATA F14EarlySampleC6Support =
- {
- (PF_F14_ES_IS_C6_SUPPORTED) CommonVoid,
- (PF_F14_ES_C6_INIT) CommonVoid
- };
- #endif
-
- #endif
- #endif
- #endif
-
- #ifdef OPTION_FAMILY15H
- #if OPTION_FAMILY15H == TRUE
- #if OPTION_FAMILY15H_OR == TRUE
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
- #undef OPTION_C6_STATE_FEAT
- #define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
- extern CONST C6_FAMILY_SERVICES ROMDATA F15C6Support;
- #undef F15_C6_STATE_SUPPORT
- #define F15_C6_STATE_SUPPORT {AMD_FAMILY_15_OR, &F15C6Support},
- #endif
- #endif
- #endif
- #endif
-#endif
-
-CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA C6FamilyServiceArray[] =
-{
- F12_C6_STATE_SUPPORT
- F14_C6_STATE_SUPPORT
- F15_C6_STATE_SUPPORT
- {0, NULL}
-};
-
-CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA C6FamilyServiceTable =
-{
- (sizeof (C6FamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
- &C6FamilyServiceArray[0]
-};
-
-#endif // _OPTION_C6_STATE_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionCpbInstall.h b/src/vendorcode/amd/agesa/Include/OptionCpbInstall.h
deleted file mode 100644
index 45f8498..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionCpbInstall.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: Core Performance Boost
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Options
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_CPB_INSTALL_H_
-#define _OPTION_CPB_INSTALL_H_
-
-#include "cpuCpb.h"
-
-/* This option is designed to be included into the platform solution install
- * file. The platform solution install file will define the options status.
- * Check to validate the definition
- */
-#define OPTION_CPB_FEAT
-#define F10_CPB_SUPPORT
-#define F12_CPB_SUPPORT
-#define F15_CPB_SUPPORT
-
-#if OPTION_CPB == TRUE
- #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
- // Family 10h
- #ifdef OPTION_FAMILY10H
- #if OPTION_FAMILY10H == TRUE
- #if OPTION_FAMILY10H_PH == TRUE
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
- #undef OPTION_CPB_FEAT
- #define OPTION_CPB_FEAT &CpuFeatureCpb,
- extern CONST CPB_FAMILY_SERVICES ROMDATA F10CpbSupport;
- #undef F10_CPB_SUPPORT
- #define F10_CPB_SUPPORT {AMD_FAMILY_10_PH, &F10CpbSupport},
- #endif
- #endif
- #endif
-
- // Family 12h
- #ifdef OPTION_FAMILY12H
- #if OPTION_FAMILY12H == TRUE
- #if OPTION_FAMILY12H_LN == TRUE
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
- #undef OPTION_CPB_FEAT
- #define OPTION_CPB_FEAT &CpuFeatureCpb,
- extern CONST CPB_FAMILY_SERVICES ROMDATA F12CpbSupport;
- #undef F12_CPB_SUPPORT
- #define F12_CPB_SUPPORT {AMD_FAMILY_12_LN, &F12CpbSupport},
- #endif
- #endif
- #endif
-
- // Family 15h
- #ifdef OPTION_FAMILY15H
- #if OPTION_FAMILY15H == TRUE
- #if OPTION_FAMILY15H_OR == TRUE
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
- #undef OPTION_CPB_FEAT
- #define OPTION_CPB_FEAT &CpuFeatureCpb,
- extern CONST CPB_FAMILY_SERVICES ROMDATA F15CpbSupport;
- #undef F15_CPB_SUPPORT
- #define F15_CPB_SUPPORT {AMD_FAMILY_15_OR, &F15CpbSupport},
- #endif
- #endif
- #endif
-
- #endif
-#endif
-
-CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpbFamilyServiceArray[] =
-{
- F10_CPB_SUPPORT
- F12_CPB_SUPPORT
- F15_CPB_SUPPORT
- {0, NULL}
-};
-
-CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CpbFamilyServiceTable =
-{
- (sizeof (CpbFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
- &CpbFamilyServiceArray[0]
-};
-
-#endif // _OPTION_CPB_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionCpuCacheFlushOnHaltInstall.h b/src/vendorcode/amd/agesa/Include/OptionCpuCacheFlushOnHaltInstall.h
deleted file mode 100644
index 87aea08..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionCpuCacheFlushOnHaltInstall.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: CPU Cache Flush On Halt
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Options
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
-#define _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
-
-#include "cpuPostInit.h"
-
-/* This option is designed to be included into the platform solution install
- * file. The platform solution install file will define the options status.
- * Check to validate the definition
- */
-#define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
-#define F10_BL_CPU_CFOH_SUPPORT
-#define F10_DA_CPU_CFOH_SUPPORT
-#define F10_CPU_CFOH_SUPPORT
-#define F15_OR_CPU_CFOH_SUPPORT
-
-#if OPTION_CPU_CFOH == TRUE
- #if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
- #ifdef OPTION_FAMILY10H
- #if OPTION_FAMILY10H == TRUE
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt;
- #undef OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
- #define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT &CpuFeatureCacheFlushOnHalt,
-
- #if OPTION_FAMILY10H_BL == TRUE
- extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10BlCacheFlushOnHalt;
- #undef F10_BL_CPU_CFOH_SUPPORT
- #define F10_BL_CPU_CFOH_SUPPORT {AMD_FAMILY_10_BL, &F10BlCacheFlushOnHalt},
- #endif
-
- #if OPTION_FAMILY10H_DA == TRUE
- extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10DaCacheFlushOnHalt;
- #undef F10_DA_CPU_CFOH_SUPPORT
- #define F10_DA_CPU_CFOH_SUPPORT {AMD_FAMILY_10_DA, &F10DaCacheFlushOnHalt},
- #endif
-
- #if (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_HY == TRUE) || (OPTION_FAMILY10H_PH == TRUE)
- extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10CacheFlushOnHalt;
- #undef F10_CPU_CFOH_SUPPORT
- #define F10_CPU_CFOH_SUPPORT {AMD_FAMILY_10_RB | AMD_FAMILY_10_HY | AMD_FAMILY_10_PH, &F10CacheFlushOnHalt},
- #endif
- #endif
- #endif
-
- #ifdef OPTION_FAMILY15H
- #if OPTION_FAMILY15H == TRUE
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt;
- #undef OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
- #define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT &CpuFeatureCacheFlushOnHalt,
-
- #if OPTION_FAMILY15H_OR == TRUE
- extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F15CacheFlushOnHalt;
- #undef F15_OR_CPU_CFOH_SUPPORT
- #define F15_OR_CPU_CFOH_SUPPORT {AMD_FAMILY_15_OR, &F15CacheFlushOnHalt},
- #endif
- #endif
- #endif
- #endif
-#endif
-
-CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CacheFlushOnHaltFamilyServiceArray[] =
-{
- F10_BL_CPU_CFOH_SUPPORT
- F10_DA_CPU_CFOH_SUPPORT
- F10_CPU_CFOH_SUPPORT
- F15_OR_CPU_CFOH_SUPPORT
- {0, NULL}
-};
-CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CacheFlushOnHaltFamilyServiceTable =
-{
- (sizeof (CacheFlushOnHaltFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
- &CacheFlushOnHaltFamilyServiceArray[0]
-};
-
-#endif // _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionCpuCoreLevelingInstall.h b/src/vendorcode/amd/agesa/Include/OptionCpuCoreLevelingInstall.h
deleted file mode 100644
index b49bef1..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionCpuCoreLevelingInstall.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: CPU Core Leveling
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Options
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_CPU_CORELEVELING_INSTALL_H_
-#define _OPTION_CPU_CORELEVELING_INSTALL_H_
-
-
-/* This option is designed to be included into the platform solution install
- * file. The platform solution install file will define the options status.
- * Check to validate the definition
- */
-#define OPTION_CPU_CORE_LEVELING_FEAT
-#define F10_REVE_CPU_CORELEVELING_SUPPORT
-#define F10_REVD_CPU_CORELEVELING_SUPPORT
-#define F10_REVC_CPU_CORELEVELING_SUPPORT
-#define F15_CPU_CORELEVELING_SUPPORT
-
-#if OPTION_CPU_CORELEVLING == TRUE
- #if (AGESA_ENTRY_INIT_EARLY == TRUE)
- // Family 10h
- #if OPTION_FAMILY10H == TRUE
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling;
- #undef OPTION_CPU_CORE_LEVELING_FEAT
- #define OPTION_CPU_CORE_LEVELING_FEAT &CpuFeatureCoreLeveling,
- #if OPTION_FAMILY10H == TRUE
- #if OPTION_FAMILY10H_HY == TRUE
- extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevDCoreLeveling;
- #undef F10_REVD_CPU_CORELEVELING_SUPPORT
- #define F10_REVD_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_HY, &F10RevDCoreLeveling},
- #endif
-
- #if (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE)
- extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevCCoreLeveling;
- #undef F10_REVC_CPU_CORELEVELING_SUPPORT
- #define F10_REVC_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_RB | AMD_FAMILY_10_BL | AMD_FAMILY_10_DA, &F10RevCCoreLeveling},
- #endif
-
- #if (OPTION_FAMILY10H_PH == TRUE)
- extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevECoreLeveling;
- #undef F10_REVE_CPU_CORELEVELING_SUPPORT
- #define F10_REVE_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_PH, &F10RevECoreLeveling},
- #endif
- #endif
- #endif
- // Family 15h
- #if OPTION_FAMILY15H == TRUE
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling;
- #undef OPTION_CPU_CORE_LEVELING_FEAT
- #define OPTION_CPU_CORE_LEVELING_FEAT &CpuFeatureCoreLeveling,
-
- extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F15CoreLeveling;
- #undef F15_CPU_CORELEVELING_SUPPORT
- #define F15_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_15, &F15CoreLeveling},
- #endif
- #endif
-#endif
-
-CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CoreLevelingFamilyServiceArray[] =
-{
- F10_REVE_CPU_CORELEVELING_SUPPORT
- F10_REVD_CPU_CORELEVELING_SUPPORT
- F10_REVC_CPU_CORELEVELING_SUPPORT
- F15_CPU_CORELEVELING_SUPPORT
- {0, NULL}
-};
-CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CoreLevelingFamilyServiceTable =
-{
- (sizeof (CoreLevelingFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
- &CoreLevelingFamilyServiceArray[0]
-};
-
-#endif // _OPTION_CPU_CORELEVELING_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionCpuFamiliesInstall.h b/src/vendorcode/amd/agesa/Include/OptionCpuFamiliesInstall.h
deleted file mode 100644
index 44c1796..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionCpuFamiliesInstall.h
+++ /dev/null
@@ -1,406 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of all appropriate CPU family specific support.
- *
- * This file generates the defaults tables for all family specific
- * combinations.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Core
- * @e \$Revision: 37640 $ @e \$Date: 2010-09-08 23:01:59 +0800 (Wed, 08 Sep 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/* Default all CPU Specific Service members to off. They
- will be enabled as needed by cross referencing families
- with entry points in the family / model install files. */
-#define GET_PSTATE_POWER FALSE
-#define GET_PSTATE_FREQ FALSE
-#define DISABLE_PSTATE FALSE
-#define TRANSITION_PSTATE FALSE
-#define PROC_IDD_MAX FALSE
-#define GET_TSC_RATE FALSE
-#define PSTATE_TRANSITION_LATENCY FALSE
-#define GET_PSTATE_REGISTER_INFO FALSE
-#define GET_PSTATE_MAX_STATE FALSE
-#define SET_PSTATE_LEVELING_REG FALSE
-#define GET_NB_FREQ FALSE
-#define IS_NBCOF_INIT_NEEDED FALSE
-#define AP_INITIAL_LAUNCH FALSE
-#define GET_AP_MAILBOX_FROM_HW FALSE
-#define SET_AP_CORE_NUMBER FALSE
-#define GET_AP_CORE_NUMBER FALSE
-#define TRANSFER_AP_CORE_NUMBER FALSE
-#define ID_POSITION_INITIAL_APICID FALSE
-#define SAVE_FEATURES FALSE
-#define WRITE_FEATURES FALSE
-#define SET_DOWN_CORE_REG FALSE
-#define SET_WARM_RESET_FLAG FALSE
-#define GET_WARM_RESET_FLAG FALSE
-#define USES_REGISTER_TABLES FALSE
-#define BASE_FAMILY_PCI FALSE
-#define MODEL_SPECIFIC_PCI FALSE
-#define BASE_FAMILY_MSR FALSE
-#define MODEL_SPECIFIC_MSR FALSE
-#define BRAND_STRING1 FALSE
-#define BRAND_STRING2 FALSE
-#define BASE_FAMILY_HT_PCI FALSE
-#define MODEL_SPECIFIC_HT_PCI FALSE
-#define BASE_FAMILY_WORKAROUNDS FALSE
-#define GET_PATCHES FALSE
-#define GET_PATCHES_EQUIVALENCE_TABLE FALSE
-#define GET_CACHE_INFO FALSE
-#define GET_SYSTEM_PM_TABLE FALSE
-#define GET_WHEA_INIT FALSE
-#define GET_CFOH_REG FALSE
-#define GET_PLATFORM_TYPE_SPECIFIC_INFO FALSE
-#define IS_NB_PSTATE_ENABLED FALSE
-
-/*
- * Pull in family specific services based on entry point
- */
-#if AGESA_ENTRY_INIT_RESET == TRUE
- #undef ID_POSITION_INITIAL_APICID
- #define ID_POSITION_INITIAL_APICID TRUE
- #undef GET_AP_MAILBOX_FROM_HW
- #define GET_AP_MAILBOX_FROM_HW TRUE
- #undef SET_WARM_RESET_FLAG
- #define SET_WARM_RESET_FLAG TRUE
- #undef GET_WARM_RESET_FLAG
- #define GET_WARM_RESET_FLAG TRUE
- #undef GET_CACHE_INFO
- #define GET_CACHE_INFO TRUE
- #undef GET_AP_CORE_NUMBER
- #define GET_AP_CORE_NUMBER TRUE
- #undef TRANSFER_AP_CORE_NUMBER
- #define TRANSFER_AP_CORE_NUMBER TRUE
-#endif
-
-#if AGESA_ENTRY_INIT_RECOVERY == TRUE
- #undef ID_POSITION_INITIAL_APICID
- #define ID_POSITION_INITIAL_APICID TRUE
- #undef USES_REGISTER_TABLES
- #define USES_REGISTER_TABLES TRUE
- #undef BASE_FAMILY_PCI
- #define BASE_FAMILY_PCI TRUE
- #undef MODEL_SPECIFIC_PCI
- #define MODEL_SPECIFIC_PCI TRUE
- #undef BASE_FAMILY_MSR
- #define BASE_FAMILY_MSR TRUE
- #undef MODEL_SPECIFIC_MSR
- #define MODEL_SPECIFIC_MSR TRUE
- #undef GET_CACHE_INFO
- #define GET_CACHE_INFO TRUE
- #undef GET_PLATFORM_TYPE_SPECIFIC_INFO
- #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
- #undef IS_NB_PSTATE_ENABLED
- #define IS_NB_PSTATE_ENABLED TRUE
- #undef GET_PATCHES
- #define GET_PATCHES TRUE
- #undef GET_PATCHES_EQUIVALENCE_TABLE
- #define GET_PATCHES_EQUIVALENCE_TABLE TRUE
-#endif
-
-#if AGESA_ENTRY_INIT_EARLY == TRUE
- #undef TRANSITION_PSTATE
- #define TRANSITION_PSTATE TRUE
- #undef DISABLE_PSTATE
- #define DISABLE_PSTATE TRUE
- #undef PROC_IDD_MAX
- #define PROC_IDD_MAX TRUE
- #undef GET_TSC_RATE
- #define GET_TSC_RATE TRUE
- #undef GET_NB_FREQ
- #define GET_NB_FREQ TRUE
- #undef IS_NBCOF_INIT_NEEDED
- #define IS_NBCOF_INIT_NEEDED TRUE
- #undef AP_INITIAL_LAUNCH
- #define AP_INITIAL_LAUNCH TRUE
- #undef GET_AP_MAILBOX_FROM_HW
- #define GET_AP_MAILBOX_FROM_HW TRUE
- #undef SET_AP_CORE_NUMBER
- #define SET_AP_CORE_NUMBER TRUE
- #undef GET_AP_CORE_NUMBER
- #define GET_AP_CORE_NUMBER TRUE
- #undef TRANSFER_AP_CORE_NUMBER
- #define TRANSFER_AP_CORE_NUMBER TRUE
- #undef ID_POSITION_INITIAL_APICID
- #define ID_POSITION_INITIAL_APICID TRUE
- #undef SET_DOWN_CORE_REG
- #define SET_DOWN_CORE_REG TRUE
- #undef SET_WARM_RESET_FLAG
- #define SET_WARM_RESET_FLAG TRUE
- #undef GET_WARM_RESET_FLAG
- #define GET_WARM_RESET_FLAG TRUE
- #undef USES_REGISTER_TABLES
- #define USES_REGISTER_TABLES TRUE
- #undef BASE_FAMILY_PCI
- #define BASE_FAMILY_PCI TRUE
- #undef MODEL_SPECIFIC_PCI
- #define MODEL_SPECIFIC_PCI TRUE
- #undef BASE_FAMILY_MSR
- #define BASE_FAMILY_MSR TRUE
- #undef MODEL_SPECIFIC_MSR
- #define MODEL_SPECIFIC_MSR TRUE
- #undef BRAND_STRING1
- #define BRAND_STRING1 TRUE
- #undef BRAND_STRING2
- #define BRAND_STRING2 TRUE
- #undef BASE_FAMILY_HT_PCI
- #define BASE_FAMILY_HT_PCI TRUE
- #undef MODEL_SPECIFIC_HT_PCI
- #define MODEL_SPECIFIC_HT_PCI TRUE
- #undef BASE_FAMILY_WORKAROUNDS
- #define BASE_FAMILY_WORKAROUNDS TRUE
- #undef GET_PATCHES
- #define GET_PATCHES TRUE
- #undef GET_PATCHES_EQUIVALENCE_TABLE
- #define GET_PATCHES_EQUIVALENCE_TABLE TRUE
- #undef GET_SYSTEM_PM_TABLE
- #define GET_SYSTEM_PM_TABLE TRUE
- #undef GET_CACHE_INFO
- #define GET_CACHE_INFO TRUE
- #undef GET_PLATFORM_TYPE_SPECIFIC_INFO
- #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
- #undef IS_NB_PSTATE_ENABLED
- #define IS_NB_PSTATE_ENABLED TRUE
-#endif
-
-#if AGESA_ENTRY_INIT_POST == TRUE
- #undef ID_POSITION_INITIAL_APICID
- #define ID_POSITION_INITIAL_APICID TRUE
- #undef GET_PSTATE_POWER
- #define GET_PSTATE_POWER TRUE
- #undef GET_PSTATE_FREQ
- #define GET_PSTATE_FREQ TRUE
- #undef TRANSITION_PSTATE
- #define TRANSITION_PSTATE TRUE
- #undef PROC_IDD_MAX
- #define PROC_IDD_MAX TRUE
- #undef GET_AP_CORE_NUMBER
- #define GET_AP_CORE_NUMBER TRUE
- #undef GET_PSTATE_REGISTER_INFO
- #define GET_PSTATE_REGISTER_INFO TRUE
- #undef GET_PSTATE_MAX_STATE
- #define GET_PSTATE_MAX_STATE TRUE
- #undef SET_PSTATE_LEVELING_REG
- #define SET_PSTATE_LEVELING_REG TRUE
- #undef SET_WARM_RESET_FLAG
- #define SET_WARM_RESET_FLAG TRUE
- #undef GET_WARM_RESET_FLAG
- #define GET_WARM_RESET_FLAG TRUE
- #undef SAVE_FEATURES
- #define SAVE_FEATURES TRUE
- #undef WRITE_FEATURES
- #define WRITE_FEATURES TRUE
- #undef GET_CFOH_REG
- #define GET_CFOH_REG TRUE
- #undef IS_NB_PSTATE_ENABLED
- #define IS_NB_PSTATE_ENABLED TRUE
-#endif
-
-#if AGESA_ENTRY_INIT_ENV == TRUE
-#endif
-
-#if AGESA_ENTRY_INIT_MID == TRUE
-#endif
-
-#if AGESA_ENTRY_INIT_LATE == TRUE
- #undef GET_AP_CORE_NUMBER
- #define GET_AP_CORE_NUMBER TRUE
- #undef GET_PSTATE_FREQ
- #define GET_PSTATE_FREQ TRUE
- #undef TRANSITION_PSTATE
- #define TRANSITION_PSTATE TRUE
- #undef PSTATE_TRANSITION_LATENCY
- #define PSTATE_TRANSITION_LATENCY TRUE
- #undef GET_WHEA_INIT
- #define GET_WHEA_INIT TRUE
- #undef GET_PLATFORM_TYPE_SPECIFIC_INFO
- #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
- #undef GET_TSC_RATE
- #define GET_TSC_RATE TRUE
- #undef BRAND_STRING1
- #define BRAND_STRING1 TRUE
- #undef BRAND_STRING2
- #define BRAND_STRING2 TRUE
-#endif
-
-#if AGESA_ENTRY_INIT_S3SAVE == TRUE
-#endif
-
-#if AGESA_ENTRY_INIT_RESUME == TRUE
- #undef GET_CFOH_REG
- #define GET_CFOH_REG TRUE
-#endif
-
-#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
-#endif
-
-#if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
- #undef ID_POSITION_INITIAL_APICID
- #define ID_POSITION_INITIAL_APICID TRUE
-#endif
-
-/*
- * Initialize PCI MMIO mask to 0
- */
-#define FAMILY_MMIO_BASE_MASK (0ull)
-
-
-/*
- * Initialize all families to disabled
- */
-#define OPT_F10_TABLE
-#define OPT_F12_TABLE
-#define OPT_F14_TABLE
-#define OPT_F15_TABLE
-
-#define OPT_F10_ID_TABLE
-#define OPT_F12_ID_TABLE
-#define OPT_F14_ID_TABLE
-#define OPT_F15_ID_TABLE
-
-
-/*
- * Install family specific support
- */
-#if (OPTION_FAMILY10H == TRUE)
- #include "OptionFamily10hInstall.h"
-#endif
-
-#if (OPTION_FAMILY12H == TRUE)
- #include "OptionFamily12hInstall.h"
-#endif
-
-#if (OPTION_FAMILY14H == TRUE)
- #include "OptionFamily14hInstall.h"
-#endif
-
-#if (OPTION_FAMILY15H == TRUE)
- #include "OptionFamily15hInstall.h"
-#endif
-
-
-/*
- * Process PCI MMIO mask
- */
-
-// If size is 0, but base is not, break the build.
-#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE == 0)
- #error BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
-#endif
-
-// If base is 0, but size is not, break the build.
-#if (CFG_PCI_MMIO_BASE == 0) && (CFG_PCI_MMIO_SIZE != 0)
- #error BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
-#endif
-
-#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE != 0)
- // Both are non-zero, begin further processing.
-
- // Heap runs from 4MB to 8MB. Disallow any addresses below 8MB.
- #if (CFG_PCI_MMIO_BASE < 0x800000)
- #error BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
- #endif
-
- // Break the build if the address is too high for the enabled families.
- #if ((CFG_PCI_MMIO_BASE & FAMILY_MMIO_BASE_MASK) != 0)
- #error BLDCFG: Invalid PCI MMIO base address for the installed CPU families
- #endif
-
- // If the size parameter is not valid, break the build.
- #if (CFG_PCI_MMIO_SIZE != 1) && (CFG_PCI_MMIO_SIZE != 2) && (CFG_PCI_MMIO_SIZE != 4) && (CFG_PCI_MMIO_SIZE != 8) && (CFG_PCI_MMIO_SIZE != 16)
- #if (CFG_PCI_MMIO_SIZE != 32) && (CFG_PCI_MMIO_SIZE != 64) && (CFG_PCI_MMIO_SIZE != 128) && (CFG_PCI_MMIO_SIZE != 256)
- #error BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
- #endif
- #endif
-
- #define PCI_MMIO_ALIGNMENT ((0x100000 * CFG_PCI_MMIO_SIZE) - 1)
- // If the base is not aligned according to size, break the build.
- #if ((CFG_PCI_MMIO_BASE & PCI_MMIO_ALIGNMENT) != 0)
- #error BLDCFG: Invalid PCI MMIO base -- must be properly aligned according to MMIO size
- #endif
- #undef PCI_MMIO_ALIGNMENT
-#endif
-
-/*
- * Process sockets / modules
- */
-#ifndef ADVCFG_PLATFORM_SOCKETS
- #error BLDOPT Set Family supported sockets.
-#endif
-#ifndef ADVCFG_PLATFORM_MODULES
- #error BLDOPT Set Family supported modules.
-#endif
-
-CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration =
-{
- ADVCFG_PLATFORM_SOCKETS,
- ADVCFG_PLATFORM_MODULES
-};
-
-/*
- * Instantiate global data needed for processor identification
- */
-CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpuSupportedFamiliesArray[] =
-{
- OPT_F10_TABLE
- OPT_F12_TABLE
- OPT_F14_TABLE
- OPT_F15_TABLE
-};
-
-CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CpuSupportedFamiliesTable =
-{
- (sizeof (CpuSupportedFamiliesArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
- &CpuSupportedFamiliesArray[0]
-};
-
-
-CONST CPU_LOGICAL_ID_FAMILY_XLAT ROMDATA CpuSupportedFamilyIdArray[] =
-{
- OPT_F10_ID_TABLE
- OPT_F12_ID_TABLE
- OPT_F14_ID_TABLE
- OPT_F15_ID_TABLE
-};
-
-CONST CPU_FAMILY_ID_XLAT_TABLE ROMDATA CpuSupportedFamilyIdTable =
-{
- (sizeof (CpuSupportedFamilyIdArray) / sizeof (CPU_LOGICAL_ID_FAMILY_XLAT)),
- CpuSupportedFamilyIdArray
-};
diff --git a/src/vendorcode/amd/agesa/Include/OptionCpuFeaturesInstall.h b/src/vendorcode/amd/agesa/Include/OptionCpuFeaturesInstall.h
deleted file mode 100644
index 63cd55e..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionCpuFeaturesInstall.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of multiple CPU features.
- *
- * Aggregates enabled CPU features into a list for the dispatcher to process.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Options
- * @e \$Revision: 37157 $ @e \$Date: 2010-09-01 03:24:07 +0800 (Wed, 01 Sep 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_CPU_FEATURES_INSTALL_H_
-#define _OPTION_CPU_FEATURES_INSTALL_H_
-
-#include "OptionHwC1eInstall.h"
-#include "OptionMsgBasedC1eInstall.h"
-#include "OptionSwC1eInstall.h"
-#include "OptionHtAssistInstall.h"
-#include "OptionCpuCoreLevelingInstall.h"
-#include "OptionIoCstateInstall.h"
-#include "OptionC6Install.h"
-#include "OptionCpbInstall.h"
-#include "OptionCpuCacheFlushOnHaltInstall.h"
-#include "OptionLowPwrPstateInstall.h"
-#include "OptionPreserveMailboxInstall.h"
-
-CONST CPU_FEATURE_DESCRIPTOR* ROMDATA SupportedCpuFeatureList[] =
-{
- OPTION_HW_C1E_FEAT
- OPTION_MSG_BASED_C1E_FEAT
- OPTION_SW_C1E_FEAT
- OPTION_HT_ASSIST_FEAT
- OPTION_CPU_CORE_LEVELING_FEAT
- OPTION_IO_CSTATE_FEAT
- OPTION_C6_STATE_FEAT
- OPTION_CPB_FEAT
- OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
- OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT // this function should be run before creating ACPI objects and after Pstate initialization
- OPTION_PRESERVE_MAILBOX_FEAT
- NULL
-};
-
-
-#endif // _OPTION_CPU_FEATURES_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionDmi.h b/src/vendorcode/amd/agesa/Include/OptionDmi.h
deleted file mode 100644
index 216e871..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionDmi.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD DMI option API.
- *
- * Contains structures and values used to control the DMI option code.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: OPTION
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_DMI_H_
-#define _OPTION_DMI_H_
-
-/*----------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *----------------------------------------------------------------------------------------
- */
-
-typedef AGESA_STATUS OPTION_DMI_FEATURE (
- IN OUT AMD_CONFIG_PARAMS *StdHeader,
- IN OUT DMI_INFO **DmiPtr
- );
-
-typedef AGESA_STATUS OPTION_DMI_RELEASE_BUFFER (
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-#define DMI_STRUCT_VERSION 0x01
-
-/// DMI option configuration. Determine the item of structure when compiling.
-typedef struct {
- UINT16 OptDmiVersion; ///< Dmi version.
- OPTION_DMI_FEATURE *DmiFeature; ///< Feature main routine, otherwise dummy.
- OPTION_DMI_RELEASE_BUFFER *DmiReleaseBuffer; ///< Release buffer
- UINT16 NumEntries; ///< Number of entry.
- VOID *((*FamilyList)[]); ///< Family service.
-} OPTION_DMI_CONFIGURATION;
-
-/*----------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *----------------------------------------------------------------------------------------
- */
-
-
-#endif // _OPTION_DMI_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionDmiInstall.h b/src/vendorcode/amd/agesa/Include/OptionDmiInstall.h
deleted file mode 100644
index 87f27e7..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionDmiInstall.h
+++ /dev/null
@@ -1,194 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: DMI
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Options
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_DMI_INSTALL_H_
-#define _OPTION_DMI_INSTALL_H_
-
-#include "cpuLateInit.h"
-
-/* This option is designed to be included into the platform solution install
- * file. The platform solution install file will define the options status.
- * Check to validate the definition
- */
-#if AGESA_ENTRY_INIT_LATE == TRUE
- #ifndef OPTION_DMI
- #error BLDOPT: Option not defined: "OPTION_DMI"
- #endif
- #if OPTION_DMI == TRUE
- OPTION_DMI_FEATURE GetDmiInfoMain;
- OPTION_DMI_RELEASE_BUFFER ReleaseDmiBuffer;
- #define USER_DMI_OPTION &GetDmiInfoMain
- #define USER_DMI_RELEASE_BUFFER &ReleaseDmiBuffer
-
- // This additional check keeps AP launch routines from being unnecessarily included
- // in single socket systems.
- #if OPTION_MULTISOCKET == TRUE
- #undef AGESA_ENTRY_LATE_RUN_AP_TASK
- #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE
- #define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info},
- #else
- #define CPU_DMI_AP_GET_TYPE4_TYPE7
- #endif
-
- // Family 10
- #ifdef OPTION_FAMILY10H
- #if OPTION_FAMILY10H == TRUE
- extern PROC_FAMILY_TABLE ProcFamily10DmiTable;
- #define FAM10_DMI_SUPPORT FAM10_ENABLED,
- #define FAM10_DMI_TABLE &ProcFamily10DmiTable,
- #else
- #define FAM10_DMI_SUPPORT
- #define FAM10_DMI_TABLE
- #endif
- #else
- #define FAM10_DMI_SUPPORT
- #define FAM10_DMI_TABLE
- #endif
-
- // Family 12
- #ifdef OPTION_FAMILY12H
- #if OPTION_FAMILY12H == TRUE
- extern PROC_FAMILY_TABLE ProcFamily12DmiTable;
- #define FAM12_DMI_SUPPORT FAM12_ENABLED,
- #define FAM12_DMI_TABLE &ProcFamily12DmiTable,
- #else
- #define FAM12_DMI_SUPPORT
- #define FAM12_DMI_TABLE
- #endif
- #else
- #define FAM12_DMI_SUPPORT
- #define FAM12_DMI_TABLE
- #endif
-
- // Family 14
- #ifdef OPTION_FAMILY14H
- #if OPTION_FAMILY14H == TRUE
- extern PROC_FAMILY_TABLE ProcFamily14DmiTable;
- #define FAM14_DMI_SUPPORT FAM14_ENABLED,
- #define FAM14_DMI_TABLE &ProcFamily14DmiTable,
- #else
- #define FAM14_DMI_SUPPORT
- #define FAM14_DMI_TABLE
- #endif
- #else
- #define FAM14_DMI_SUPPORT
- #define FAM14_DMI_TABLE
- #endif
-
- // Family 15
- #ifdef OPTION_FAMILY15H
- #if OPTION_FAMILY15H == TRUE
- extern PROC_FAMILY_TABLE ProcFamily15DmiTable;
- #define FAM15_DMI_SUPPORT FAM15_ENABLED,
- #define FAM15_DMI_TABLE &ProcFamily15DmiTable,
- #else
- #define FAM15_DMI_SUPPORT
- #define FAM15_DMI_TABLE
- #endif
- #else
- #define FAM15_DMI_SUPPORT
- #define FAM15_DMI_TABLE
- #endif
-
- #else
- OPTION_DMI_FEATURE GetDmiInfoStub;
- OPTION_DMI_RELEASE_BUFFER ReleaseDmiBufferStub;
- #define USER_DMI_OPTION GetDmiInfoStub
- #define USER_DMI_RELEASE_BUFFER ReleaseDmiBufferStub
- #define FAM10_DMI_SUPPORT
- #define FAM10_DMI_TABLE
- #define FAM12_DMI_SUPPORT
- #define FAM12_DMI_TABLE
- #define FAM14_DMI_SUPPORT
- #define FAM14_DMI_TABLE
- #define FAM15_DMI_SUPPORT
- #define FAM15_DMI_TABLE
- #define CPU_DMI_AP_GET_TYPE4_TYPE7
- #endif
-#else
- OPTION_DMI_FEATURE GetDmiInfoStub;
- OPTION_DMI_RELEASE_BUFFER ReleaseDmiBufferStub;
- #define USER_DMI_OPTION GetDmiInfoStub
- #define USER_DMI_RELEASE_BUFFER ReleaseDmiBufferStub
- #define FAM10_DMI_SUPPORT
- #define FAM10_DMI_TABLE
- #define FAM12_DMI_SUPPORT
- #define FAM12_DMI_TABLE
- #define FAM14_DMI_SUPPORT
- #define FAM14_DMI_TABLE
- #define FAM15_DMI_SUPPORT
- #define FAM15_DMI_TABLE
- #define CPU_DMI_AP_GET_TYPE4_TYPE7
-#endif
-
-/// DMI supported families enum
-typedef enum {
- FAM10_DMI_SUPPORT ///< Conditionally define F10 support
- FAM12_DMI_SUPPORT ///< Conditionally define F12 support
- FAM14_DMI_SUPPORT ///< Conditionally define F14 support
- FAM15_DMI_SUPPORT ///< Conditionally define F15 support
- NUM_DMI_FAMILIES ///< Number of installed families
-} AGESA_DMI_SUPPORTED_FAM;
-
-/* Declare the Family List. An array of pointers to tables that each describe a family */
-CONST PROC_FAMILY_TABLE ROMDATA *ProcTables[] = {
- FAM10_DMI_TABLE
- FAM12_DMI_TABLE
- FAM14_DMI_TABLE
- FAM15_DMI_TABLE
- NULL
-};
-
-/* Declare the instance of the DMI option configuration structure */
-CONST OPTION_DMI_CONFIGURATION ROMDATA OptionDmiConfiguration = {
- DMI_STRUCT_VERSION,
- USER_DMI_OPTION,
- USER_DMI_RELEASE_BUFFER,
- NUM_DMI_FAMILIES,
- (VOID *((*)[])) &ProcTables // Compiler says array size must match struct decl
-};
-
-#endif // _OPTION_DMI_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionFamily10hInstall.h b/src/vendorcode/amd/agesa/Include/OptionFamily10hInstall.h
deleted file mode 100644
index 4b4347f..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionFamily10hInstall.h
+++ /dev/null
@@ -1,1996 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of family 10h support
- *
- * This file generates the defaults tables for family 10h processors.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Core
- * @e \$Revision: 37150 $ @e \$Date: 2010-08-31 23:53:37 +0800 (Tue, 31 Aug 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_FAMILY_10H_INSTALL_H_
-#define _OPTION_FAMILY_10H_INSTALL_H_
-
-/*
- * Common Family 10h routines
- */
-extern F_CPU_DISABLE_PSTATE F10DisablePstate;
-extern F_CPU_TRANSITION_PSTATE F10TransitionPstate;
-extern F_CPU_GET_TSC_RATE F10GetTscRate;
-extern F_CPU_GET_NB_FREQ F10GetCurrentNbFrequency;
-extern F_CPU_AP_INITIAL_LAUNCH F10LaunchApCore;
-extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F10GetApMailboxFromHardware;
-extern F_CPU_SET_AP_CORE_NUMBER F10SetApCoreNumber;
-extern F_CPU_GET_AP_CORE_NUMBER F10GetApCoreNumber;
-extern F_CPU_TRANSFER_AP_CORE_NUMBER F10TransferApCoreNumber;
-extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F10CpuAmdCoreIdPositionInInitialApicId;
-extern F_CPU_SAVE_FEATURES F10SaveFeatures;
-extern F_CPU_WRITE_FEATURES F10WriteFeatures;
-extern F_CPU_SET_WARM_RESET_FLAG F10SetAgesaWarmResetFlag;
-extern F_CPU_GET_WARM_RESET_FLAG F10GetAgesaWarmResetFlag;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10BrandIdString1;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10BrandIdString2;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10CacheInfo;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10SysPmTable;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10WheaInitData;
-extern F_CPU_SET_CFOH_REG SetF10CacheFlushOnHaltRegister;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetEmptyArray;
-extern F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO F10GetPlatformTypeSpecificInfo;
-extern F_NEXT_LINK_HAS_HTFPY_FEATS F10NextLinkHasHtPhyFeats;
-extern F_SET_HT_PHY_REGISTER F10SetHtPhyRegister;
-extern F_GET_NEXT_HT_LINK_FEATURES F10GetNextHtLinkFeatures;
-extern CONST REGISTER_TABLE ROMDATA F10PciRegisterTable;
-extern CONST REGISTER_TABLE ROMDATA F10MsrRegisterTable;
-extern CONST REGISTER_TABLE ROMDATA F10HtPhyRegisterTable;
-extern CONST REGISTER_TABLE ROMDATA F10MultiLinkPciRegisterTable;
-extern CONST REGISTER_TABLE ROMDATA F10SingleLinkPciRegisterTable;
-extern CONST REGISTER_TABLE ROMDATA F10WorkaroundsTable;
-extern F_GET_EARLY_INIT_TABLE GetF10EarlyInitOnCoreTable;
-
-
-/*
- * Install family 10h model 5 support
- */
-#ifdef OPTION_FAMILY10H_BL
- #if OPTION_FAMILY10H_BL == TRUE
- extern CONST REGISTER_TABLE ROMDATA F10RevCPciRegisterTable;
- extern CONST REGISTER_TABLE ROMDATA F10RevCMsrRegisterTable;
- extern CONST REGISTER_TABLE ROMDATA F10RevCHtPhyRegisterTable;
- extern CONST REGISTER_TABLE ROMDATA F10BlPciRegisterTable;
- extern CONST REGISTER_TABLE ROMDATA F10BlMsrRegisterTable;
- extern CONST REGISTER_TABLE ROMDATA F10BlHtPhyRegisterTable;
- extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10BlMicroCodePatchesStruct;
- extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10BlMicrocodeEquivalenceTable;
- extern F_CPU_GET_IDD_MAX F10CommonRevCGetProcIddMax;
- extern F_CPU_GET_NB_PSTATE_INFO F10CommonRevCGetNbPstateInfo;
- extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevCGetNbCofVidUpdate;
- extern F_IS_NB_PSTATE_ENABLED F10CommonRevCIsNbPstateEnabled;
- extern F_CPU_NUMBER_OF_BRANDSTRING_CORES F10CommonRevCGetNumberOfCoresForBrandstring;
-
- #if USES_REGISTER_TABLES == TRUE
- CONST REGISTER_TABLE ROMDATA *F10BlRegisterTables[] =
- {
- #if BASE_FAMILY_PCI == TRUE
- &F10PciRegisterTable,
- #endif
- #if MODEL_SPECIFIC_PCI == TRUE
- &F10SingleLinkPciRegisterTable,
- #endif
- #if MODEL_SPECIFIC_PCI == TRUE
- &F10RevCPciRegisterTable,
- #endif
- #if MODEL_SPECIFIC_PCI == TRUE
- &F10BlPciRegisterTable,
- #endif
- #if BASE_FAMILY_MSR == TRUE
- &F10MsrRegisterTable,
- #endif
- #if MODEL_SPECIFIC_MSR == TRUE
- &F10RevCMsrRegisterTable,
- #endif
- #if MODEL_SPECIFIC_MSR == TRUE
- &F10BlMsrRegisterTable,
- #endif
- #if MODEL_SPECIFIC_HT_PCI == TRUE
- &F10HtPhyRegisterTable,
- #endif
- #if MODEL_SPECIFIC_HT_PCI == TRUE
- &F10RevCHtPhyRegisterTable,
- #endif
- #if MODEL_SPECIFIC_HT_PCI == TRUE
- &F10BlHtPhyRegisterTable,
- #endif
- #if BASE_FAMILY_WORKAROUNDS == TRUE
- &F10WorkaroundsTable,
- #endif
- // the end.
- NULL
- };
- #endif
-
- #if USES_REGISTER_TABLES == TRUE
- CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10BlTableEntryTypeDescriptors[] =
- {
- {MsrRegister, SetRegisterForMsrEntry},
- {PciRegister, SetRegisterForPciEntry},
- {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
- {HtPhyRegister, SetRegisterForHtPhyEntry},
- {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
- {DeemphasisRegister, SetRegisterForDeemphasisEntry},
- {ProfileFixup, SetRegisterForPerformanceProfileEntry},
- {HtHostPciRegister, SetRegisterForHtHostEntry},
- {HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid},
- {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
- {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
- {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
- {HtPhyProfileRegister, SetRegisterForHtPhyProfileEntry},
- // End
- {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
- };
- #endif
-
- CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10BlServices =
- {
- 0,
- #if DISABLE_PSTATE == TRUE
- F10DisablePstate,
- #else
- (PF_CPU_DISABLE_PSTATE) CommonAssert,
- #endif
- #if TRANSITION_PSTATE == TRUE
- F10TransitionPstate,
- #else
- (PF_CPU_TRANSITION_PSTATE) CommonAssert,
- #endif
- #if PROC_IDD_MAX == TRUE
- F10CommonRevCGetProcIddMax,
- #else
- (PF_CPU_GET_IDD_MAX) CommonAssert,
- #endif
- #if GET_TSC_RATE == TRUE
- F10GetTscRate,
- #else
- (PF_CPU_GET_TSC_RATE) CommonAssert,
- #endif
- #if GET_NB_FREQ == TRUE
- F10GetCurrentNbFrequency,
- #else
- (PF_CPU_GET_NB_FREQ) CommonAssert,
- #endif
- #if GET_NB_FREQ == TRUE
- F10CommonRevCGetNbPstateInfo,
- #else
- (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
- #endif
- #if IS_NBCOF_INIT_NEEDED == TRUE
- F10CommonRevCGetNbCofVidUpdate,
- #else
- (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
- #endif
- #if AP_INITIAL_LAUNCH == TRUE
- F10LaunchApCore,
- #else
- (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
- #endif
- #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
- F10CommonRevCGetNumberOfCoresForBrandstring,
- #else
- (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
- #endif
- #if GET_AP_MAILBOX_FROM_HW == TRUE
- F10GetApMailboxFromHardware,
- #else
- (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
- #endif
- #if SET_AP_CORE_NUMBER == TRUE
- F10SetApCoreNumber,
- #else
- (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
- #endif
- #if GET_AP_CORE_NUMBER == TRUE
- F10GetApCoreNumber,
- #else
- (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
- #endif
- #if TRANSFER_AP_CORE_NUMBER == TRUE
- F10TransferApCoreNumber,
- #else
- (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
- #endif
- #if ID_POSITION_INITIAL_APICID == TRUE
- F10CpuAmdCoreIdPositionInInitialApicId,
- #else
- (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
- #endif
- #if SAVE_FEATURES == TRUE
- F10SaveFeatures,
- #else
- (PF_CPU_SAVE_FEATURES) CommonAssert,
- #endif
- #if WRITE_FEATURES == TRUE
- F10WriteFeatures,
- #else
- (PF_CPU_WRITE_FEATURES) CommonAssert,
- #endif
- #if SET_WARM_RESET_FLAG == TRUE
- F10SetAgesaWarmResetFlag,
- #else
- (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
- #endif
- #if GET_WARM_RESET_FLAG == TRUE
- F10GetAgesaWarmResetFlag,
- #else
- (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
- #endif
- #if BRAND_STRING1 == TRUE
- GetF10BrandIdString1,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if BRAND_STRING2 == TRUE
- GetF10BrandIdString2,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_PATCHES == TRUE
- GetF10BlMicroCodePatchesStruct,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
- GetF10BlMicrocodeEquivalenceTable,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_CACHE_INFO == TRUE
- GetF10CacheInfo,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_SYSTEM_PM_TABLE == TRUE
- GetF10SysPmTable,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_WHEA_INIT == TRUE
- GetF10WheaInitData,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
- F10GetPlatformTypeSpecificInfo,
- #else
- (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
- #endif
- #if IS_NB_PSTATE_ENABLED == TRUE
- F10CommonRevCIsNbPstateEnabled,
- #else
- (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
- #endif
- #if (BASE_FAMILY_HT_PCI == TRUE)
- F10NextLinkHasHtPhyFeats,
- #else
- (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
- #endif
- #if (BASE_FAMILY_HT_PCI == TRUE)
- F10SetHtPhyRegister,
- #else
- (PF_SET_HT_PHY_REGISTER) CommonAssert,
- #endif
- #if BASE_FAMILY_PCI == TRUE
- F10GetNextHtLinkFeatures,
- #else
- (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
- #endif
- #if USES_REGISTER_TABLES == TRUE
- (REGISTER_TABLE **) F10BlRegisterTables,
- #else
- NULL,
- #endif
- #if USES_REGISTER_TABLES == TRUE
- (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10BlTableEntryTypeDescriptors,
- #else
- NULL,
- #endif
- NULL,
- NULL,
- InitCacheDisabled,
- #if AGESA_ENTRY_INIT_EARLY == TRUE
- GetF10EarlyInitOnCoreTable
- #else
- (PF_GET_EARLY_INIT_TABLE) CommonVoid
- #endif
- };
-
- #define BL_SOCKETS 1
- #define BL_MODULES 1
- #define BL_RECOVERY_SOCKETS 1
- #define BL_RECOVERY_MODULES 1
- extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10BlLogicalIdAndRev;
- #define OPT_F10_BL_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10BlLogicalIdAndRev,
- #ifndef ADVCFG_PLATFORM_SOCKETS
- #define ADVCFG_PLATFORM_SOCKETS BL_SOCKETS
- #else
- #if ADVCFG_PLATFORM_SOCKETS < BL_SOCKETS
- #undef ADVCFG_PLATFORM_SOCKETS
- #define ADVCFG_PLATFORM_SOCKETS BL_SOCKETS
- #endif
- #endif
- #ifndef ADVCFG_PLATFORM_MODULES
- #define ADVCFG_PLATFORM_MODULES BL_MODULES
- #else
- #if ADVCFG_PLATFORM_MODULES < BL_MODULES
- #undef ADVCFG_PLATFORM_MODULES
- #define ADVCFG_PLATFORM_MODULES BL_MODULES
- #endif
- #endif
-
- #if GET_PATCHES == TRUE
- #define F10_BL_UCODE_C6
- #define F10_BL_UCODE_C8
-
- // If a patch is required for recovery mode to function properly, add a
- // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
- #if AGESA_ENTRY_INIT_EARLY == TRUE
- #if OPTION_AM3_SOCKET_SUPPORT == TRUE
- extern CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c6;
- #undef F10_BL_UCODE_C6
- #define F10_BL_UCODE_C6 &CpuF10MicrocodePatch010000c6,
- #endif
- #if (OPTION_S1G4_SOCKET_SUPPORT == TRUE) || (OPTION_AM3_SOCKET_SUPPORT == TRUE) || (OPTION_ASB2_SOCKET_SUPPORT == TRUE)
- extern CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c8;
- #undef F10_BL_UCODE_C8
- #define F10_BL_UCODE_C8 &CpuF10MicrocodePatch010000c8,
- #endif
- #endif
-
- CONST MICROCODE_PATCHES ROMDATA *CpuF10BlMicroCodePatchArray[] =
- {
- F10_BL_UCODE_C6
- F10_BL_UCODE_C8
- NULL
- };
-
- CONST UINT8 ROMDATA CpuF10BlNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF10BlMicroCodePatchArray) / sizeof (CpuF10BlMicroCodePatchArray[0])) - 1);
- #endif
-
- #define OPT_F10_BL_CPU {AMD_FAMILY_10_BL, &cpuF10BlServices},
- #else
- #define OPT_F10_BL_CPU
- #define OPT_F10_BL_ID
- #endif
-#else
- #define OPT_F10_BL_CPU
- #define OPT_F10_BL_ID
-#endif
-
-/*
- * Install family 10h model 6 support
- */
-#ifdef OPTION_FAMILY10H_DA
- #if OPTION_FAMILY10H_DA == TRUE
- extern CONST REGISTER_TABLE ROMDATA F10RevCPciRegisterTable;
- extern CONST REGISTER_TABLE ROMDATA F10RevCMsrRegisterTable;
- extern CONST REGISTER_TABLE ROMDATA F10RevCHtPhyRegisterTable;
- extern CONST REGISTER_TABLE ROMDATA F10DaPciRegisterTable;
- extern CONST REGISTER_TABLE ROMDATA F10DaMsrRegisterTable;
- extern CONST REGISTER_TABLE ROMDATA F10DaHtPhyRegisterTable;
- extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10DaMicroCodePatchesStruct;
- extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10DaMicrocodeEquivalenceTable;
- extern F_CPU_GET_IDD_MAX F10CommonRevCGetProcIddMax;
- extern F_CPU_GET_NB_PSTATE_INFO F10CommonRevCGetNbPstateInfo;
- extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevCGetNbCofVidUpdate;
- extern F_CPU_SET_CFOH_REG SetF10DaCacheFlushOnHaltRegister;
- extern F_IS_NB_PSTATE_ENABLED F10CommonRevCIsNbPstateEnabled;
- extern F_CPU_NUMBER_OF_BRANDSTRING_CORES F10CommonRevCGetNumberOfCoresForBrandstring;
-
- #if USES_REGISTER_TABLES == TRUE
- CONST REGISTER_TABLE ROMDATA *F10DaRegisterTables[] =
- {
- #if BASE_FAMILY_PCI == TRUE
- &F10PciRegisterTable,
- #endif
- #if MODEL_SPECIFIC_PCI == TRUE
- &F10SingleLinkPciRegisterTable,
- #endif
- #if MODEL_SPECIFIC_PCI == TRUE
- &F10RevCPciRegisterTable,
- #endif
- #if MODEL_SPECIFIC_PCI == TRUE
- &F10DaPciRegisterTable,
- #endif
- #if BASE_FAMILY_MSR == TRUE
- &F10MsrRegisterTable,
- #endif
- #if MODEL_SPECIFIC_MSR == TRUE
- &F10RevCMsrRegisterTable,
- #endif
- #if MODEL_SPECIFIC_MSR == TRUE
- &F10DaMsrRegisterTable,
- #endif
- #if MODEL_SPECIFIC_HT_PCI == TRUE
- &F10HtPhyRegisterTable,
- #endif
- #if MODEL_SPECIFIC_HT_PCI == TRUE
- &F10RevCHtPhyRegisterTable,
- #endif
- #if MODEL_SPECIFIC_HT_PCI == TRUE
- &F10DaHtPhyRegisterTable,
- #endif
- #if BASE_FAMILY_WORKAROUNDS == TRUE
- &F10WorkaroundsTable,
- #endif
- // the end.
- NULL
- };
- #endif
-
- #if USES_REGISTER_TABLES == TRUE
- CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10DaTableEntryTypeDescriptors[] =
- {
- {MsrRegister, SetRegisterForMsrEntry},
- {PciRegister, SetRegisterForPciEntry},
- {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
- {HtPhyRegister, SetRegisterForHtPhyEntry},
- {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
- {DeemphasisRegister, SetRegisterForDeemphasisEntry},
- {ProfileFixup, SetRegisterForPerformanceProfileEntry},
- {HtHostPciRegister, SetRegisterForHtHostEntry},
- {HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid},
- {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
- {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
- {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
- {HtPhyProfileRegister, SetRegisterForHtPhyProfileEntry},
- // End
- {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
- };
- #endif
-
- CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10DaServices =
- {
- 0,
- #if DISABLE_PSTATE == TRUE
- F10DisablePstate,
- #else
- (PF_CPU_DISABLE_PSTATE) CommonAssert,
- #endif
- #if TRANSITION_PSTATE == TRUE
- F10TransitionPstate,
- #else
- (PF_CPU_TRANSITION_PSTATE) CommonAssert,
- #endif
- #if PROC_IDD_MAX == TRUE
- F10CommonRevCGetProcIddMax,
- #else
- (PF_CPU_GET_IDD_MAX) CommonAssert,
- #endif
- #if GET_TSC_RATE == TRUE
- F10GetTscRate,
- #else
- (PF_CPU_GET_TSC_RATE) CommonAssert,
- #endif
- #if GET_NB_FREQ == TRUE
- F10GetCurrentNbFrequency,
- #else
- (PF_CPU_GET_NB_FREQ) CommonAssert,
- #endif
- #if GET_NB_FREQ == TRUE
- F10CommonRevCGetNbPstateInfo,
- #else
- (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
- #endif
- #if IS_NBCOF_INIT_NEEDED == TRUE
- F10CommonRevCGetNbCofVidUpdate,
- #else
- (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
- #endif
- #if AP_INITIAL_LAUNCH == TRUE
- F10LaunchApCore,
- #else
- (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
- #endif
- #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
- F10CommonRevCGetNumberOfCoresForBrandstring,
- #else
- (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
- #endif
- #if GET_AP_MAILBOX_FROM_HW == TRUE
- F10GetApMailboxFromHardware,
- #else
- (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
- #endif
- #if SET_AP_CORE_NUMBER == TRUE
- F10SetApCoreNumber,
- #else
- (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
- #endif
- #if GET_AP_CORE_NUMBER == TRUE
- F10GetApCoreNumber,
- #else
- (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
- #endif
- #if TRANSFER_AP_CORE_NUMBER == TRUE
- F10TransferApCoreNumber,
- #else
- (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
- #endif
- #if ID_POSITION_INITIAL_APICID == TRUE
- F10CpuAmdCoreIdPositionInInitialApicId,
- #else
- (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
- #endif
- #if SAVE_FEATURES == TRUE
- F10SaveFeatures,
- #else
- (PF_CPU_SAVE_FEATURES) CommonAssert,
- #endif
- #if WRITE_FEATURES == TRUE
- F10WriteFeatures,
- #else
- (PF_CPU_WRITE_FEATURES) CommonAssert,
- #endif
- #if SET_WARM_RESET_FLAG == TRUE
- F10SetAgesaWarmResetFlag,
- #else
- (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
- #endif
- #if GET_WARM_RESET_FLAG == TRUE
- F10GetAgesaWarmResetFlag,
- #else
- (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
- #endif
- #if BRAND_STRING1 == TRUE
- GetF10BrandIdString1,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if BRAND_STRING2 == TRUE
- GetF10BrandIdString2,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_PATCHES == TRUE
- GetF10DaMicroCodePatchesStruct,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
- GetF10DaMicrocodeEquivalenceTable,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_CACHE_INFO == TRUE
- GetF10CacheInfo,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_SYSTEM_PM_TABLE == TRUE
- GetF10SysPmTable,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_WHEA_INIT == TRUE
- GetF10WheaInitData,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
- F10GetPlatformTypeSpecificInfo,
- #else
- (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
- #endif
- #if IS_NB_PSTATE_ENABLED == TRUE
- F10CommonRevCIsNbPstateEnabled,
- #else
- (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
- #endif
- #if (BASE_FAMILY_HT_PCI == TRUE)
- F10NextLinkHasHtPhyFeats,
- #else
- (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
- #endif
- #if (BASE_FAMILY_HT_PCI == TRUE)
- F10SetHtPhyRegister,
- #else
- (PF_SET_HT_PHY_REGISTER) CommonAssert,
- #endif
- #if BASE_FAMILY_PCI == TRUE
- F10GetNextHtLinkFeatures,
- #else
- (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
- #endif
- #if USES_REGISTER_TABLES == TRUE
- (REGISTER_TABLE **) F10DaRegisterTables,
- #else
- NULL,
- #endif
- #if USES_REGISTER_TABLES == TRUE
- (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10DaTableEntryTypeDescriptors,
- #else
- NULL,
- #endif
- NULL,
- NULL,
- InitCacheDisabled,
- #if AGESA_ENTRY_INIT_EARLY == TRUE
- GetF10EarlyInitOnCoreTable
- #else
- (PF_GET_EARLY_INIT_TABLE) CommonVoid
- #endif
- };
-
- #define DA_SOCKETS 1
- #define DA_MODULES 1
- #define DA_RECOVERY_SOCKETS 1
- #define DA_RECOVERY_MODULES 1
- extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10DaLogicalIdAndRev;
- #define OPT_F10_DA_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10DaLogicalIdAndRev,
- #ifndef ADVCFG_PLATFORM_SOCKETS
- #define ADVCFG_PLATFORM_SOCKETS DA_SOCKETS
- #else
- #if ADVCFG_PLATFORM_SOCKETS < DA_SOCKETS
- #undef ADVCFG_PLATFORM_SOCKETS
- #define ADVCFG_PLATFORM_SOCKETS DA_SOCKETS
- #endif
- #endif
- #ifndef ADVCFG_PLATFORM_MODULES
- #define ADVCFG_PLATFORM_MODULES DA_MODULES
- #else
- #if ADVCFG_PLATFORM_MODULES < DA_MODULES
- #undef ADVCFG_PLATFORM_MODULES
- #define ADVCFG_PLATFORM_MODULES DA_MODULES
- #endif
- #endif
-
- #if GET_PATCHES == TRUE
- #define F10_DA_UCODE_C7
- #define F10_DA_UCODE_C8
-
- // If a patch is required for recovery mode to function properly, add a
- // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
- #if AGESA_ENTRY_INIT_EARLY == TRUE
- #if (OPTION_S1G3_SOCKET_SUPPORT == TRUE) || (OPTION_AM3_SOCKET_SUPPORT == TRUE)
- extern CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c7;
- #undef F10_DA_UCODE_C7
- #define F10_DA_UCODE_C7 &CpuF10MicrocodePatch010000c7,
- #endif
- #if (OPTION_S1G4_SOCKET_SUPPORT == TRUE) || (OPTION_AM3_SOCKET_SUPPORT == TRUE) || (OPTION_ASB2_SOCKET_SUPPORT == TRUE)
- extern CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c8;
- #undef F10_DA_UCODE_C8
- #define F10_DA_UCODE_C8 &CpuF10MicrocodePatch010000c8,
- #endif
- #endif
-
- CONST MICROCODE_PATCHES ROMDATA *CpuF10DaMicroCodePatchArray[] =
- {
- F10_DA_UCODE_C7
- F10_DA_UCODE_C8
- NULL
- };
-
- CONST UINT8 ROMDATA CpuF10DaNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF10DaMicroCodePatchArray) / sizeof (CpuF10DaMicroCodePatchArray[0])) - 1);
- #endif
-
- #define OPT_F10_DA_CPU {AMD_FAMILY_10_DA, &cpuF10DaServices},
- #else
- #define OPT_F10_DA_CPU
- #define OPT_F10_DA_ID
- #endif
-#else
- #define OPT_F10_DA_CPU
- #define OPT_F10_DA_ID
-#endif
-
-/*
- * Install family 10h models 8 & 9 support
- */
-#ifdef OPTION_FAMILY10H_HY
- #if OPTION_FAMILY10H_HY == TRUE
- extern CONST REGISTER_TABLE ROMDATA F10HyPciRegisterTable;
- extern CONST REGISTER_TABLE ROMDATA F10HyMsrRegisterTable;
- extern CONST REGISTER_TABLE ROMDATA F10HyHtPhyRegisterTable;
- extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10HyMicroCodePatchesStruct;
- extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10HyMicrocodeEquivalenceTable;
- extern F_CPU_GET_IDD_MAX F10CommonRevDGetProcIddMax;
- extern F_CPU_GET_NB_PSTATE_INFO F10CommonRevDGetNbPstateInfo;
- extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevDGetNbCofVidUpdate;
- extern CONST PACKAGE_HTLINK_MAP_ITEM ROMDATA HtFam10RevDPackageLinkMap[];
- extern F_CPU_NUMBER_OF_BRANDSTRING_CORES F10CommonRevDGetNumberOfCoresForBrandstring;
- extern F_GET_EARLY_INIT_TABLE GetF10HyEarlyInitOnCoreTable;
-
- #if USES_REGISTER_TABLES == TRUE
- CONST REGISTER_TABLE ROMDATA *F10HyRegisterTables[] =
- {
- #if BASE_FAMILY_PCI == TRUE
- &F10PciRegisterTable,
- #endif
- #if MODEL_SPECIFIC_PCI == TRUE
- &F10MultiLinkPciRegisterTable,
- #endif
- #if MODEL_SPECIFIC_PCI == TRUE
- &F10HyPciRegisterTable,
- #endif
- #if BASE_FAMILY_MSR == TRUE
- &F10MsrRegisterTable,
- #endif
- #if MODEL_SPECIFIC_MSR == TRUE
- &F10HyMsrRegisterTable,
- #endif
- #if MODEL_SPECIFIC_HT_PCI == TRUE
- &F10HtPhyRegisterTable,
- #endif
- #if MODEL_SPECIFIC_HT_PCI == TRUE
- &F10HyHtPhyRegisterTable,
- #endif
- #if BASE_FAMILY_WORKAROUNDS == TRUE
- &F10WorkaroundsTable,
- #endif
- // the end.
- NULL
- };
- #endif
-
- #if USES_REGISTER_TABLES == TRUE
- CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10HyTableEntryTypeDescriptors[] =
- {
- {MsrRegister, SetRegisterForMsrEntry},
- {PciRegister, SetRegisterForPciEntry},
- {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
- {HtPhyRegister, SetRegisterForHtPhyEntry},
- {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
- {DeemphasisRegister, SetRegisterForDeemphasisEntry},
- {HtPhyFreqRegister, SetRegisterForHtPhyFreqEntry},
- {ProfileFixup, SetRegisterForPerformanceProfileEntry},
- {HtHostPciRegister, SetRegisterForHtHostEntry},
- {HtTokenPciRegister, SetRegisterForHtLinkTokenEntry},
- {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
- {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
- {TokenPciRegister, SetRegisterForTokenPciEntry},
- {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
- {HtLinkPciRegister, SetRegisterForHtLinkPciEntry},
- // End
- {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
- };
- #endif
-
- CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10HyServices =
- {
- 0,
- #if DISABLE_PSTATE == TRUE
- F10DisablePstate,
- #else
- (PF_CPU_DISABLE_PSTATE) CommonAssert,
- #endif
- #if TRANSITION_PSTATE == TRUE
- F10TransitionPstate,
- #else
- (PF_CPU_TRANSITION_PSTATE) CommonAssert,
- #endif
- #if PROC_IDD_MAX == TRUE
- F10CommonRevDGetProcIddMax,
- #else
- (PF_CPU_GET_IDD_MAX) CommonAssert,
- #endif
- #if GET_TSC_RATE == TRUE
- F10GetTscRate,
- #else
- (PF_CPU_GET_TSC_RATE) CommonAssert,
- #endif
- #if GET_NB_FREQ == TRUE
- F10GetCurrentNbFrequency,
- #else
- (PF_CPU_GET_NB_FREQ) CommonAssert,
- #endif
- #if GET_NB_FREQ == TRUE
- F10CommonRevDGetNbPstateInfo,
- #else
- (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
- #endif
- #if IS_NBCOF_INIT_NEEDED == TRUE
- F10CommonRevDGetNbCofVidUpdate,
- #else
- (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
- #endif
- #if AP_INITIAL_LAUNCH == TRUE
- F10LaunchApCore,
- #else
- (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
- #endif
- #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
- F10CommonRevDGetNumberOfCoresForBrandstring,
- #else
- (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
- #endif
- #if GET_AP_MAILBOX_FROM_HW == TRUE
- F10GetApMailboxFromHardware,
- #else
- (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
- #endif
- #if SET_AP_CORE_NUMBER == TRUE
- F10SetApCoreNumber,
- #else
- (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
- #endif
- #if GET_AP_CORE_NUMBER == TRUE
- F10GetApCoreNumber,
- #else
- (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
- #endif
- #if TRANSFER_AP_CORE_NUMBER == TRUE
- F10TransferApCoreNumber,
- #else
- (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
- #endif
- #if ID_POSITION_INITIAL_APICID == TRUE
- F10CpuAmdCoreIdPositionInInitialApicId,
- #else
- (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
- #endif
- #if SAVE_FEATURES == TRUE
- F10SaveFeatures,
- #else
- (PF_CPU_SAVE_FEATURES) CommonAssert,
- #endif
- #if WRITE_FEATURES == TRUE
- F10WriteFeatures,
- #else
- (PF_CPU_WRITE_FEATURES) CommonAssert,
- #endif
- #if SET_WARM_RESET_FLAG == TRUE
- F10SetAgesaWarmResetFlag,
- #else
- (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
- #endif
- #if GET_WARM_RESET_FLAG == TRUE
- F10GetAgesaWarmResetFlag,
- #else
- (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
- #endif
- #if BRAND_STRING1 == TRUE
- GetF10BrandIdString1,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if BRAND_STRING2 == TRUE
- GetF10BrandIdString2,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_PATCHES == TRUE
- GetF10HyMicroCodePatchesStruct,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
- GetF10HyMicrocodeEquivalenceTable,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_CACHE_INFO == TRUE
- GetF10CacheInfo,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_SYSTEM_PM_TABLE == TRUE
- GetF10SysPmTable,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_WHEA_INIT == TRUE
- GetF10WheaInitData,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
- F10GetPlatformTypeSpecificInfo,
- #else
- (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
- #endif
- #if IS_NB_PSTATE_ENABLED == TRUE
- (PF_IS_NB_PSTATE_ENABLED) CommonReturnFalse,
- #else
- (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
- #endif
- #if (BASE_FAMILY_HT_PCI == TRUE)
- F10NextLinkHasHtPhyFeats,
- #else
- (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
- #endif
- #if (BASE_FAMILY_HT_PCI == TRUE)
- F10SetHtPhyRegister,
- #else
- (PF_SET_HT_PHY_REGISTER) CommonAssert,
- #endif
- #if BASE_FAMILY_PCI == TRUE
- F10GetNextHtLinkFeatures,
- #else
- (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
- #endif
- #if USES_REGISTER_TABLES == TRUE
- (REGISTER_TABLE **) F10HyRegisterTables,
- #else
- NULL,
- #endif
- #if USES_REGISTER_TABLES == TRUE
- (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10HyTableEntryTypeDescriptors,
- #else
- NULL,
- #endif
- #if MODEL_SPECIFIC_HT_PCI == TRUE
- (PACKAGE_HTLINK_MAP) &HtFam10RevDPackageLinkMap,
- #else
- NULL,
- #endif
- NULL,
- InitCacheDisabled,
- #if AGESA_ENTRY_INIT_EARLY == TRUE
- #if OPTION_C32_SOCKET_SUPPORT == TRUE
- GetF10HyEarlyInitOnCoreTable
- #else
- GetF10EarlyInitOnCoreTable
- #endif
- #else
- (PF_GET_EARLY_INIT_TABLE) CommonVoid
- #endif
- };
-
- #define HY_SOCKETS 8
- #if (OPTION_G34_SOCKET_SUPPORT == TRUE)
- #define HY_MODULES 2
- #else
- #define HY_MODULES 1
- #endif
- #define HY_RECOVERY_SOCKETS 1
- #define HY_RECOVERY_MODULES 1
- extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10HyLogicalIdAndRev;
- #define OPT_F10_HY_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10HyLogicalIdAndRev,
- #ifndef ADVCFG_PLATFORM_SOCKETS
- #define ADVCFG_PLATFORM_SOCKETS HY_SOCKETS
- #else
- #if ADVCFG_PLATFORM_SOCKETS < HY_SOCKETS
- #undef ADVCFG_PLATFORM_SOCKETS
- #define ADVCFG_PLATFORM_SOCKETS HY_SOCKETS
- #endif
- #endif
- #ifndef ADVCFG_PLATFORM_MODULES
- #define ADVCFG_PLATFORM_MODULES HY_MODULES
- #else
- #if ADVCFG_PLATFORM_MODULES < HY_MODULES
- #undef ADVCFG_PLATFORM_MODULES
- #define ADVCFG_PLATFORM_MODULES HY_MODULES
- #endif
- #endif
-
- #if GET_PATCHES == TRUE
- #define F10_HY_UCODE_C4
- #define F10_HY_UCODE_C5
-
- // If a patch is required for recovery mode to function properly, add a
- // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
- #if AGESA_ENTRY_INIT_EARLY == TRUE
- #if OPTION_C32_SOCKET_SUPPORT == TRUE
- extern CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c5;
- #undef F10_HY_UCODE_C5
- #define F10_HY_UCODE_C5 &CpuF10MicrocodePatch010000c5,
- #endif
- #if (OPTION_C32_SOCKET_SUPPORT == TRUE) || (OPTION_G34_SOCKET_SUPPORT == TRUE)
- extern CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c4;
- #undef F10_HY_UCODE_C4
- #define F10_HY_UCODE_C4 &CpuF10MicrocodePatch010000c4,
- #endif
- #endif
-
- CONST MICROCODE_PATCHES ROMDATA *CpuF10HyMicroCodePatchArray[] =
- {
- F10_HY_UCODE_C4
- F10_HY_UCODE_C5
- NULL
- };
-
- CONST UINT8 ROMDATA CpuF10HyNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF10HyMicroCodePatchArray) / sizeof (CpuF10HyMicroCodePatchArray[0])) - 1);
- #endif
-
- #define OPT_F10_HY_CPU {AMD_FAMILY_10_HY, &cpuF10HyServices},
- #else
- #define OPT_F10_HY_CPU
- #define OPT_F10_HY_ID
- #endif
-#else
- #define OPT_F10_HY_CPU
- #define OPT_F10_HY_ID
-#endif
-
-/*
- * Install family 10h model 10 support
- */
-#ifdef OPTION_FAMILY10H_PH
- #if OPTION_FAMILY10H_PH == TRUE
- extern CONST REGISTER_TABLE ROMDATA F10RevEPciRegisterTable;
- extern CONST REGISTER_TABLE ROMDATA F10RevEMsrRegisterTable;
- extern CONST REGISTER_TABLE ROMDATA F10RevEHtPhyRegisterTable;
- extern CONST REGISTER_TABLE ROMDATA F10PhPciRegisterTable;
- extern CONST REGISTER_TABLE ROMDATA F10PhMsrRegisterTable;
- extern CONST REGISTER_TABLE ROMDATA F10PhHtPhyRegisterTable;
- extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10PhMicroCodePatchesStruct;
- extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10PhMicrocodeEquivalenceTable;
- extern F_CPU_GET_IDD_MAX F10CommonRevEGetProcIddMax;
- extern F_CPU_GET_NB_PSTATE_INFO F10CommonRevEGetNbPstateInfo;
- extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevEGetNbCofVidUpdate;
- extern F_CPU_NUMBER_OF_BRANDSTRING_CORES F10CommonRevEGetNumberOfCoresForBrandstring;
-
- #if USES_REGISTER_TABLES == TRUE
- CONST REGISTER_TABLE ROMDATA *F10PhRegisterTables[] =
- {
- #if BASE_FAMILY_PCI == TRUE
- &F10PciRegisterTable,
- #endif
- #if MODEL_SPECIFIC_PCI == TRUE
- &F10SingleLinkPciRegisterTable,
- #endif
- #if MODEL_SPECIFIC_PCI == TRUE
- &F10RevEPciRegisterTable,
- #endif
- #if BASE_FAMILY_MSR == TRUE
- &F10MsrRegisterTable,
- #endif
- #if MODEL_SPECIFIC_MSR == TRUE
- &F10RevEMsrRegisterTable,
- #endif
- #if MODEL_SPECIFIC_HT_PCI == TRUE
- &F10HtPhyRegisterTable,
- #endif
- #if MODEL_SPECIFIC_HT_PCI == TRUE
- &F10RevEHtPhyRegisterTable,
- #endif
- #if MODEL_SPECIFIC_HT_PCI == TRUE
- &F10PhHtPhyRegisterTable,
- #endif
- #if BASE_FAMILY_WORKAROUNDS == TRUE
- &F10WorkaroundsTable,
- #endif
- // the end.
- NULL
- };
- #endif
-
- #if USES_REGISTER_TABLES == TRUE
- CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10PhTableEntryTypeDescriptors[] =
- {
- {MsrRegister, SetRegisterForMsrEntry},
- {PciRegister, SetRegisterForPciEntry},
- {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
- {HtPhyRegister, SetRegisterForHtPhyEntry},
- {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
- {DeemphasisRegister, SetRegisterForDeemphasisEntry},
- {ProfileFixup, SetRegisterForPerformanceProfileEntry},
- {HtHostPciRegister, SetRegisterForHtHostEntry},
- {HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid},
- {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
- {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
- {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
- {HtPhyProfileRegister, SetRegisterForHtPhyProfileEntry},
- // End
- {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
- };
- #endif
-
- CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10PhServices =
- {
- 0,
- #if DISABLE_PSTATE == TRUE
- F10DisablePstate,
- #else
- (PF_CPU_DISABLE_PSTATE) CommonAssert,
- #endif
- #if TRANSITION_PSTATE == TRUE
- F10TransitionPstate,
- #else
- (PF_CPU_TRANSITION_PSTATE) CommonAssert,
- #endif
- #if PROC_IDD_MAX == TRUE
- F10CommonRevEGetProcIddMax,
- #else
- (PF_CPU_GET_IDD_MAX) CommonAssert,
- #endif
- #if GET_TSC_RATE == TRUE
- F10GetTscRate,
- #else
- (PF_CPU_GET_TSC_RATE) CommonAssert,
- #endif
- #if GET_NB_FREQ == TRUE
- F10GetCurrentNbFrequency,
- #else
- (PF_CPU_GET_NB_FREQ) CommonAssert,
- #endif
- #if GET_NB_FREQ == TRUE
- F10CommonRevEGetNbPstateInfo,
- #else
- (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
- #endif
- #if IS_NBCOF_INIT_NEEDED == TRUE
- F10CommonRevEGetNbCofVidUpdate,
- #else
- (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
- #endif
- #if AP_INITIAL_LAUNCH == TRUE
- F10LaunchApCore,
- #else
- (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
- #endif
- #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
- F10CommonRevEGetNumberOfCoresForBrandstring,
- #else
- (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
- #endif
- #if GET_AP_MAILBOX_FROM_HW == TRUE
- F10GetApMailboxFromHardware,
- #else
- (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
- #endif
- #if SET_AP_CORE_NUMBER == TRUE
- F10SetApCoreNumber,
- #else
- (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
- #endif
- #if GET_AP_CORE_NUMBER == TRUE
- F10GetApCoreNumber,
- #else
- (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
- #endif
- #if TRANSFER_AP_CORE_NUMBER == TRUE
- F10TransferApCoreNumber,
- #else
- (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
- #endif
- #if ID_POSITION_INITIAL_APICID == TRUE
- F10CpuAmdCoreIdPositionInInitialApicId,
- #else
- (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
- #endif
- #if SAVE_FEATURES == TRUE
- F10SaveFeatures,
- #else
- (PF_CPU_SAVE_FEATURES) CommonAssert,
- #endif
- #if WRITE_FEATURES == TRUE
- F10WriteFeatures,
- #else
- (PF_CPU_WRITE_FEATURES) CommonAssert,
- #endif
- #if SET_WARM_RESET_FLAG == TRUE
- F10SetAgesaWarmResetFlag,
- #else
- (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
- #endif
- #if GET_WARM_RESET_FLAG == TRUE
- F10GetAgesaWarmResetFlag,
- #else
- (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
- #endif
- #if BRAND_STRING1 == TRUE
- GetF10BrandIdString1,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if BRAND_STRING2 == TRUE
- GetF10BrandIdString2,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_PATCHES == TRUE
- GetF10PhMicroCodePatchesStruct,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
- GetF10PhMicrocodeEquivalenceTable,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_CACHE_INFO == TRUE
- GetF10CacheInfo,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_SYSTEM_PM_TABLE == TRUE
- GetF10SysPmTable,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_WHEA_INIT == TRUE
- GetF10WheaInitData,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
- F10GetPlatformTypeSpecificInfo,
- #else
- (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
- #endif
- #if IS_NB_PSTATE_ENABLED == TRUE
- (PF_IS_NB_PSTATE_ENABLED) CommonReturnFalse,
- #else
- (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
- #endif
- #if (BASE_FAMILY_HT_PCI == TRUE)
- F10NextLinkHasHtPhyFeats,
- #else
- (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
- #endif
- #if (BASE_FAMILY_HT_PCI == TRUE)
- F10SetHtPhyRegister,
- #else
- (PF_SET_HT_PHY_REGISTER) CommonAssert,
- #endif
- #if BASE_FAMILY_PCI == TRUE
- F10GetNextHtLinkFeatures,
- #else
- (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
- #endif
- #if USES_REGISTER_TABLES == TRUE
- (REGISTER_TABLE **) F10PhRegisterTables,
- #else
- NULL,
- #endif
- #if USES_REGISTER_TABLES == TRUE
- (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10PhTableEntryTypeDescriptors,
- #else
- NULL,
- #endif
- NULL,
- NULL,
- InitCacheDisabled,
- #if AGESA_ENTRY_INIT_EARLY == TRUE
- GetF10EarlyInitOnCoreTable
- #else
- (PF_GET_EARLY_INIT_TABLE) CommonVoid
- #endif
- };
-
- #define PH_SOCKETS 1
- #define PH_MODULES 1
- #define PH_RECOVERY_SOCKETS 1
- #define PH_RECOVERY_MODULES 1
- extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10PhLogicalIdAndRev;
- #define OPT_F10_PH_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10PhLogicalIdAndRev,
- #ifndef ADVCFG_PLATFORM_SOCKETS
- #define ADVCFG_PLATFORM_SOCKETS PH_SOCKETS
- #else
- #if ADVCFG_PLATFORM_SOCKETS < PH_SOCKETS
- #undef ADVCFG_PLATFORM_SOCKETS
- #define ADVCFG_PLATFORM_SOCKETS PH_SOCKETS
- #endif
- #endif
- #ifndef ADVCFG_PLATFORM_MODULES
- #define ADVCFG_PLATFORM_MODULES PH_MODULES
- #else
- #if ADVCFG_PLATFORM_MODULES < PH_MODULES
- #undef ADVCFG_PLATFORM_MODULES
- #define ADVCFG_PLATFORM_MODULES PH_MODULES
- #endif
- #endif
-
- #if GET_PATCHES == TRUE
- #define F10_PH_UCODE_BF
-
- // If a patch is required for recovery mode to function properly, add a
- // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
- #if AGESA_ENTRY_INIT_EARLY == TRUE
- #if OPTION_AM3_SOCKET_SUPPORT == TRUE
- extern CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000bf;
- #undef F10_PH_UCODE_BF
- #define F10_PH_UCODE_BF &CpuF10MicrocodePatch010000bf,
- #endif
- #endif
-
- CONST MICROCODE_PATCHES ROMDATA *CpuF10PhMicroCodePatchArray[] =
- {
- F10_PH_UCODE_BF
- NULL
- };
-
- CONST UINT8 ROMDATA CpuF10PhNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF10PhMicroCodePatchArray) / sizeof (CpuF10PhMicroCodePatchArray[0])) - 1);
- #endif
-
- #define OPT_F10_PH_CPU {AMD_FAMILY_10_PH, &cpuF10PhServices},
- #else
- #define OPT_F10_PH_CPU
- #define OPT_F10_PH_ID
- #endif
-#else
- #define OPT_F10_PH_CPU
- #define OPT_F10_PH_ID
-#endif
-
-
-/*
- * Install family 10h model 4 support
- */
-#ifdef OPTION_FAMILY10H_RB
- #if OPTION_FAMILY10H_RB == TRUE
- extern CONST REGISTER_TABLE ROMDATA F10RevCPciRegisterTable;
- extern CONST REGISTER_TABLE ROMDATA F10RevCMsrRegisterTable;
- extern CONST REGISTER_TABLE ROMDATA F10RevCHtPhyRegisterTable;
- extern CONST REGISTER_TABLE ROMDATA F10RbPciRegisterTable;
- extern CONST REGISTER_TABLE ROMDATA F10RbMsrRegisterTable;
- extern CONST REGISTER_TABLE ROMDATA F10RbHtPhyRegisterTable;
- extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10RbMicroCodePatchesStruct;
- extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10RbMicrocodeEquivalenceTable;
- extern F_CPU_GET_IDD_MAX F10CommonRevCGetProcIddMax;
- extern F_CPU_GET_NB_PSTATE_INFO F10CommonRevCGetNbPstateInfo;
- extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevCGetNbCofVidUpdate;
- extern F_IS_NB_PSTATE_ENABLED F10CommonRevCIsNbPstateEnabled;
- extern F_CPU_NUMBER_OF_BRANDSTRING_CORES F10CommonRevCGetNumberOfCoresForBrandstring;
-
- #if USES_REGISTER_TABLES == TRUE
- CONST REGISTER_TABLE ROMDATA *F10RbRegisterTables[] =
- {
- #if BASE_FAMILY_PCI == TRUE
- &F10PciRegisterTable,
- #endif
- #if MODEL_SPECIFIC_PCI == TRUE
- &F10MultiLinkPciRegisterTable,
- &F10SingleLinkPciRegisterTable,
- #endif
- #if MODEL_SPECIFIC_PCI == TRUE
- &F10RevCPciRegisterTable,
- #endif
- #if MODEL_SPECIFIC_PCI == TRUE
- &F10RbPciRegisterTable,
- #endif
- #if BASE_FAMILY_MSR == TRUE
- &F10MsrRegisterTable,
- #endif
- #if MODEL_SPECIFIC_MSR == TRUE
- &F10RevCMsrRegisterTable,
- #endif
- #if MODEL_SPECIFIC_MSR == TRUE
- &F10RbMsrRegisterTable,
- #endif
- #if MODEL_SPECIFIC_HT_PCI == TRUE
- &F10HtPhyRegisterTable,
- #endif
- #if MODEL_SPECIFIC_HT_PCI == TRUE
- &F10RevCHtPhyRegisterTable,
- #endif
- #if MODEL_SPECIFIC_HT_PCI == TRUE
- &F10RbHtPhyRegisterTable,
- #endif
- #if BASE_FAMILY_WORKAROUNDS == TRUE
- &F10WorkaroundsTable,
- #endif
- // the end.
- NULL
- };
- #endif
-
- #if USES_REGISTER_TABLES == TRUE
- CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10RbTableEntryTypeDescriptors[] =
- {
- {MsrRegister, SetRegisterForMsrEntry},
- {PciRegister, SetRegisterForPciEntry},
- {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
- {HtPhyRegister, SetRegisterForHtPhyEntry},
- {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
- {DeemphasisRegister, SetRegisterForDeemphasisEntry},
- {ProfileFixup, SetRegisterForPerformanceProfileEntry},
- {HtHostPciRegister, SetRegisterForHtHostEntry},
- {HtTokenPciRegister, SetRegisterForHtLinkTokenEntry},
- {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
- {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
- {TokenPciRegister, SetRegisterForTokenPciEntry},
- {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
- {HtPhyProfileRegister, SetRegisterForHtPhyProfileEntry},
- // End
- {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
- };
- #endif
-
- CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10RbServices =
- {
- 0,
- #if DISABLE_PSTATE == TRUE
- F10DisablePstate,
- #else
- (PF_CPU_DISABLE_PSTATE) CommonAssert,
- #endif
- #if TRANSITION_PSTATE == TRUE
- F10TransitionPstate,
- #else
- (PF_CPU_TRANSITION_PSTATE) CommonAssert,
- #endif
- #if PROC_IDD_MAX == TRUE
- F10CommonRevCGetProcIddMax,
- #else
- (PF_CPU_GET_IDD_MAX) CommonAssert,
- #endif
- #if GET_TSC_RATE == TRUE
- F10GetTscRate,
- #else
- (PF_CPU_GET_TSC_RATE) CommonAssert,
- #endif
- #if GET_NB_FREQ == TRUE
- F10GetCurrentNbFrequency,
- #else
- (PF_CPU_GET_NB_FREQ) CommonAssert,
- #endif
- #if GET_NB_FREQ == TRUE
- F10CommonRevCGetNbPstateInfo,
- #else
- (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
- #endif
- #if IS_NBCOF_INIT_NEEDED == TRUE
- F10CommonRevCGetNbCofVidUpdate,
- #else
- (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
- #endif
- #if AP_INITIAL_LAUNCH == TRUE
- F10LaunchApCore,
- #else
- (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
- #endif
- #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
- F10CommonRevCGetNumberOfCoresForBrandstring,
- #else
- (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
- #endif
- #if GET_AP_MAILBOX_FROM_HW == TRUE
- F10GetApMailboxFromHardware,
- #else
- (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
- #endif
- #if SET_AP_CORE_NUMBER == TRUE
- F10SetApCoreNumber,
- #else
- (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
- #endif
- #if GET_AP_CORE_NUMBER == TRUE
- F10GetApCoreNumber,
- #else
- (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
- #endif
- #if TRANSFER_AP_CORE_NUMBER == TRUE
- F10TransferApCoreNumber,
- #else
- (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
- #endif
- #if ID_POSITION_INITIAL_APICID == TRUE
- F10CpuAmdCoreIdPositionInInitialApicId,
- #else
- (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
- #endif
- #if SAVE_FEATURES == TRUE
- F10SaveFeatures,
- #else
- (PF_CPU_SAVE_FEATURES) CommonAssert,
- #endif
- #if WRITE_FEATURES == TRUE
- F10WriteFeatures,
- #else
- (PF_CPU_WRITE_FEATURES) CommonAssert,
- #endif
- #if SET_WARM_RESET_FLAG == TRUE
- F10SetAgesaWarmResetFlag,
- #else
- (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
- #endif
- #if GET_WARM_RESET_FLAG == TRUE
- F10GetAgesaWarmResetFlag,
- #else
- (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
- #endif
- #if BRAND_STRING1 == TRUE
- GetF10BrandIdString1,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if BRAND_STRING2 == TRUE
- GetF10BrandIdString2,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_PATCHES == TRUE
- GetF10RbMicroCodePatchesStruct,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
- GetF10RbMicrocodeEquivalenceTable,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_CACHE_INFO == TRUE
- GetF10CacheInfo,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_SYSTEM_PM_TABLE == TRUE
- GetF10SysPmTable,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_WHEA_INIT == TRUE
- GetF10WheaInitData,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
- F10GetPlatformTypeSpecificInfo,
- #else
- (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
- #endif
- #if IS_NB_PSTATE_ENABLED == TRUE
- F10CommonRevCIsNbPstateEnabled,
- #else
- (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
- #endif
- #if (BASE_FAMILY_HT_PCI == TRUE)
- F10NextLinkHasHtPhyFeats,
- #else
- (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
- #endif
- #if (BASE_FAMILY_HT_PCI == TRUE)
- F10SetHtPhyRegister,
- #else
- (PF_SET_HT_PHY_REGISTER) CommonAssert,
- #endif
- #if BASE_FAMILY_PCI == TRUE
- F10GetNextHtLinkFeatures,
- #else
- (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
- #endif
- #if USES_REGISTER_TABLES == TRUE
- (REGISTER_TABLE **) F10RbRegisterTables,
- #else
- NULL,
- #endif
- #if USES_REGISTER_TABLES == TRUE
- (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10RbTableEntryTypeDescriptors,
- #else
- NULL,
- #endif
- NULL,
- NULL,
- InitCacheDisabled,
- #if AGESA_ENTRY_INIT_EARLY == TRUE
- GetF10EarlyInitOnCoreTable
- #else
- (PF_GET_EARLY_INIT_TABLE) CommonVoid
- #endif
- };
-
- #define RB_SOCKETS 8
- #define RB_MODULES 1
- #define RB_RECOVERY_SOCKETS 1
- #define RB_RECOVERY_MODULES 1
- extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10RbLogicalIdAndRev;
- #define OPT_F10_RB_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10RbLogicalIdAndRev,
- #ifndef ADVCFG_PLATFORM_SOCKETS
- #define ADVCFG_PLATFORM_SOCKETS RB_SOCKETS
- #else
- #if ADVCFG_PLATFORM_SOCKETS < RB_SOCKETS
- #undef ADVCFG_PLATFORM_SOCKETS
- #define ADVCFG_PLATFORM_SOCKETS RB_SOCKETS
- #endif
- #endif
- #ifndef ADVCFG_PLATFORM_MODULES
- #define ADVCFG_PLATFORM_MODULES RB_MODULES
- #else
- #if ADVCFG_PLATFORM_MODULES < RB_MODULES
- #undef ADVCFG_PLATFORM_MODULES
- #define ADVCFG_PLATFORM_MODULES RB_MODULES
- #endif
- #endif
-
- #if GET_PATCHES == TRUE
- #define F10_RB_UCODE_85
- #define F10_RB_UCODE_C6
- #define F10_RB_UCODE_C8
-
- // If a patch is required for recovery mode to function properly, add a
- // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
- #if AGESA_ENTRY_INIT_EARLY == TRUE
- #if OPTION_AM3_SOCKET_SUPPORT == TRUE
- extern CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch01000085;
- extern CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c6;
- extern CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c8;
- #undef F10_RB_UCODE_85
- #define F10_RB_UCODE_85 &CpuF10MicrocodePatch01000085,
- #undef F10_RB_UCODE_C6
- #define F10_RB_UCODE_C6 &CpuF10MicrocodePatch010000c6,
- #undef F10_RB_UCODE_C8
- #define F10_RB_UCODE_C8 &CpuF10MicrocodePatch010000c8,
- #endif
- #endif
-
- CONST MICROCODE_PATCHES ROMDATA *CpuF10RbMicroCodePatchArray[] =
- {
- F10_RB_UCODE_85
- F10_RB_UCODE_C6
- F10_RB_UCODE_C8
- NULL
- };
-
- CONST UINT8 ROMDATA CpuF10RbNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF10RbMicroCodePatchArray) / sizeof (CpuF10RbMicroCodePatchArray[0])) - 1);
- #endif
-
- #define OPT_F10_RB_CPU {AMD_FAMILY_10_RB, &cpuF10RbServices},
- #else
- #define OPT_F10_RB_CPU
- #define OPT_F10_RB_ID
- #endif
-#else
- #define OPT_F10_RB_CPU
- #define OPT_F10_RB_ID
-#endif
-
-
-/*
- * Install unknown family 10h support
- */
-
-#if USES_REGISTER_TABLES == TRUE
- CONST REGISTER_TABLE ROMDATA *F10UnknownRegisterTables[] =
- {
- #if BASE_FAMILY_PCI == TRUE
- &F10PciRegisterTable,
- #endif
- #if BASE_FAMILY_MSR == TRUE
- &F10MsrRegisterTable,
- #endif
- #if BASE_FAMILY_HT_PCI == TRUE
- &F10HtPhyRegisterTable,
- #endif
- #if OPTION_MULTISOCKET == TRUE
- #if MODEL_SPECIFIC_PCI == TRUE
- &F10MultiLinkPciRegisterTable,
- #endif
- #endif
- #if OPTION_MULTISOCKET == FALSE
- #if MODEL_SPECIFIC_PCI == TRUE
- &F10SingleLinkPciRegisterTable,
- #endif
- #endif
- #if BASE_FAMILY_WORKAROUNDS == TRUE
- &F10WorkaroundsTable,
- #endif
- // the end.
- NULL
- };
-#endif
-
-#if USES_REGISTER_TABLES == TRUE
- CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10UnknownTableEntryTypeDescriptors[] =
- {
- {MsrRegister, SetRegisterForMsrEntry},
- {PciRegister, SetRegisterForPciEntry},
- {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
- {HtPhyRegister, SetRegisterForHtPhyEntry},
- {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
- {DeemphasisRegister, SetRegisterForDeemphasisEntry},
- {ProfileFixup, SetRegisterForPerformanceProfileEntry},
- {HtHostPciRegister, SetRegisterForHtHostEntry},
- {HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid},
- {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
- {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
- {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
- // End
- {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
- };
-#endif
-
-
-CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10UnknownServices =
-{
- 0,
- #if DISABLE_PSTATE == TRUE
- F10DisablePstate,
- #else
- (PF_CPU_DISABLE_PSTATE) CommonAssert,
- #endif
- #if TRANSITION_PSTATE == TRUE
- F10TransitionPstate,
- #else
- (PF_CPU_TRANSITION_PSTATE) CommonAssert,
- #endif
- #if PROC_IDD_MAX == TRUE
- (PF_CPU_GET_IDD_MAX) CommonReturnFalse,
- #else
- (PF_CPU_GET_IDD_MAX) CommonAssert,
- #endif
- #if GET_TSC_RATE == TRUE
- F10GetTscRate,
- #else
- (PF_CPU_GET_TSC_RATE) CommonAssert,
- #endif
- #if GET_NB_FREQ == TRUE
- F10GetCurrentNbFrequency,
- #else
- (PF_CPU_GET_NB_FREQ) CommonAssert,
- #endif
- #if GET_NB_FREQ == TRUE
- (PF_CPU_GET_NB_PSTATE_INFO) CommonReturnFalse,
- #else
- (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
- #endif
- #if IS_NBCOF_INIT_NEEDED == TRUE
- (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonReturnFalse,
- #else
- (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
- #endif
- #if AP_INITIAL_LAUNCH == TRUE
- F10LaunchApCore,
- #else
- (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
- #endif
- #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
- (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonReturnZero8,
- #else
- (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
- #endif
- #if GET_AP_MAILBOX_FROM_HW == TRUE
- F10GetApMailboxFromHardware,
- #else
- (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
- #endif
- #if SET_AP_CORE_NUMBER == TRUE
- F10SetApCoreNumber,
- #else
- (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
- #endif
- #if GET_AP_CORE_NUMBER == TRUE
- F10GetApCoreNumber,
- #else
- (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
- #endif
- #if TRANSFER_AP_CORE_NUMBER == TRUE
- F10TransferApCoreNumber,
- #else
- (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
- #endif
- #if ID_POSITION_INITIAL_APICID == TRUE
- F10CpuAmdCoreIdPositionInInitialApicId,
- #else
- (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
- #endif
- #if SAVE_FEATURES == TRUE
- F10SaveFeatures,
- #else
- (PF_CPU_SAVE_FEATURES) CommonAssert,
- #endif
- #if WRITE_FEATURES == TRUE
- F10WriteFeatures,
- #else
- (PF_CPU_WRITE_FEATURES) CommonAssert,
- #endif
- #if SET_WARM_RESET_FLAG == TRUE
- F10SetAgesaWarmResetFlag,
- #else
- (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
- #endif
- #if GET_WARM_RESET_FLAG == TRUE
- F10GetAgesaWarmResetFlag,
- #else
- (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
- #endif
- #if BRAND_STRING1 == TRUE
- GetF10BrandIdString1,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if BRAND_STRING2 == TRUE
- GetF10BrandIdString2,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_PATCHES == TRUE
- GetEmptyArray,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
- GetEmptyArray,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_CACHE_INFO == TRUE
- GetF10CacheInfo,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_SYSTEM_PM_TABLE == TRUE
- GetF10SysPmTable,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_WHEA_INIT == TRUE
- GetF10WheaInitData,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
- F10GetPlatformTypeSpecificInfo,
- #else
- (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
- #endif
- #if IS_NB_PSTATE_ENABLED == TRUE
- (PF_IS_NB_PSTATE_ENABLED) CommonReturnFalse,
- #else
- (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
- #endif
- #if (BASE_FAMILY_HT_PCI == TRUE)
- F10NextLinkHasHtPhyFeats,
- #else
- (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
- #endif
- #if (BASE_FAMILY_HT_PCI == TRUE)
- F10SetHtPhyRegister,
- #else
- (PF_SET_HT_PHY_REGISTER) CommonVoid,
- #endif
- #if BASE_FAMILY_PCI == TRUE
- F10GetNextHtLinkFeatures,
- #else
- (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
- #endif
- #if USES_REGISTER_TABLES == TRUE
- (REGISTER_TABLE **) F10UnknownRegisterTables,
- #else
- NULL,
- #endif
- #if USES_REGISTER_TABLES == TRUE
- (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10UnknownTableEntryTypeDescriptors,
- #else
- NULL,
- #endif
- NULL,
- NULL,
- InitCacheDisabled,
- #if AGESA_ENTRY_INIT_EARLY == TRUE
- GetF10EarlyInitOnCoreTable
- #else
- (PF_GET_EARLY_INIT_TABLE) CommonVoid
- #endif
-};
-
-// Family 10h maximum base address is 48 bits. Limit BLDCFG to 48 bits, if appropriate.
-#if (FAMILY_MMIO_BASE_MASK < 0xFFFF000000000000ull)
- #undef FAMILY_MMIO_BASE_MASK
- #define FAMILY_MMIO_BASE_MASK (0xFFFF000000000000ull)
-#endif
-
-#undef OPT_F10_ID_TABLE
-#define OPT_F10_ID_TABLE {0x10, {AMD_FAMILY_10, AMD_F10_UNKNOWN}, F10LogicalIdTable, (sizeof (F10LogicalIdTable) / sizeof (F10LogicalIdTable[0]))},
-#define OPT_F10_UNKNOWN_CPU {AMD_FAMILY_10, &cpuF10UnknownServices},
-
-#undef OPT_F10_TABLE
-#define OPT_F10_TABLE OPT_F10_BL_CPU OPT_F10_DA_CPU OPT_F10_HY_CPU OPT_F10_PH_CPU OPT_F10_RB_CPU OPT_F10_UNKNOWN_CPU
-
-#if OPTION_G34_SOCKET_SUPPORT == TRUE
- extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayG34;
- extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayG34;
- #define F10_G34_BRANDSTRING1 &F10BrandIdString1ArrayG34,
- #define F10_G34_BRANDSTRING2 &F10BrandIdString2ArrayG34,
-#else
- #define F10_G34_BRANDSTRING1
- #define F10_G34_BRANDSTRING2
-#endif
-#if OPTION_C32_SOCKET_SUPPORT == TRUE
- extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayC32;
- extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayC32;
- #define F10_C32_BRANDSTRING1 &F10BrandIdString1ArrayC32,
- #define F10_C32_BRANDSTRING2 &F10BrandIdString2ArrayC32,
-#else
- #define F10_C32_BRANDSTRING1
- #define F10_C32_BRANDSTRING2
-#endif
-#if OPTION_S1G3_SOCKET_SUPPORT == TRUE
- extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayS1g3;
- extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayS1g3;
- #define F10_S1G3_BRANDSTRING1 &F10BrandIdString1ArrayS1g3,
- #define F10_S1G3_BRANDSTRING2 &F10BrandIdString2ArrayS1g3,
-#else
- #define F10_S1G3_BRANDSTRING1
- #define F10_S1G3_BRANDSTRING2
-#endif
-#if OPTION_S1G4_SOCKET_SUPPORT == TRUE
- extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayS1g4;
- extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayS1g4;
- #define F10_S1G4_BRANDSTRING1 &F10BrandIdString1ArrayS1g4,
- #define F10_S1G4_BRANDSTRING2 &F10BrandIdString2ArrayS1g4,
-#else
- #define F10_S1G4_BRANDSTRING1
- #define F10_S1G4_BRANDSTRING2
-#endif
-#if OPTION_ASB2_SOCKET_SUPPORT == TRUE
- extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayAsb2;
- extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayAsb2;
- #define F10_ASB2_BRANDSTRING1 &F10BrandIdString1ArrayAsb2,
- #define F10_ASB2_BRANDSTRING2 &F10BrandIdString2ArrayAsb2,
-#else
- #define F10_ASB2_BRANDSTRING1
- #define F10_ASB2_BRANDSTRING2
-#endif
-#if OPTION_AM3_SOCKET_SUPPORT == TRUE
- extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayAm3;
- extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayAm3;
- #define F10_AM3_BRANDSTRING1 &F10BrandIdString1ArrayAm3,
- #define F10_AM3_BRANDSTRING2 &F10BrandIdString2ArrayAm3,
-#else
- #define F10_AM3_BRANDSTRING1
- #define F10_AM3_BRANDSTRING2
-#endif
-
-#if BRAND_STRING1 == TRUE
- CONST CPU_BRAND_TABLE ROMDATA *F10BrandIdString1Tables[] =
- {
- F10_G34_BRANDSTRING1
- F10_C32_BRANDSTRING1
- F10_S1G3_BRANDSTRING1
- F10_S1G4_BRANDSTRING1
- F10_ASB2_BRANDSTRING1
- F10_AM3_BRANDSTRING1
- };
-
- CONST UINT8 F10BrandIdString1TableCount = (sizeof (F10BrandIdString1Tables) / sizeof (F10BrandIdString1Tables[0]));
-#endif
-
-#if BRAND_STRING2 == TRUE
- CONST CPU_BRAND_TABLE ROMDATA *F10BrandIdString2Tables[] =
- {
- F10_G34_BRANDSTRING2
- F10_C32_BRANDSTRING2
- F10_S1G3_BRANDSTRING2
- F10_S1G4_BRANDSTRING2
- F10_ASB2_BRANDSTRING2
- F10_AM3_BRANDSTRING2
- };
-
- CONST UINT8 F10BrandIdString2TableCount = (sizeof (F10BrandIdString2Tables) / sizeof (F10BrandIdString2Tables[0]));
-#endif
-
-CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY ROMDATA F10LogicalIdTable[] =
-{
- OPT_F10_BL_ID
- OPT_F10_DA_ID
- OPT_F10_HY_ID
- OPT_F10_PH_ID
- OPT_F10_RB_ID
-};
-
-#endif // _OPTION_FAMILY_10H_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionFamily12hEarlySample.h b/src/vendorcode/amd/agesa/Include/OptionFamily12hEarlySample.h
deleted file mode 100644
index e475a18..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionFamily12hEarlySample.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Family 12h 'early sample' support
- *
- * This file defines the required structures for family 12h pre-production processors.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Core
- * @e \$Revision: 37456 $ @e \$Date: 2010-09-04 04:17:05 +0800 (Sat, 04 Sep 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_FAMILY_12H_EARLY_SAMPLE_H_
-#define _OPTION_FAMILY_12H_EARLY_SAMPLE_H_
-
-
-/*---------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *---------------------------------------------------------------------------------------
- */
-/**
- * Return the appropriate values of certain NB P-state related registers.
- *
- * @param[in,out] FCRxFE00_6000 The value of FCRxFE006000.
- * @param[in,out] FCRxFE00_6002 The value of FCRxFE006002.
- * @param[in,out] FCRxFE00_7006 The value of FCRxFE007006.
- * @param[in,out] FCRxFE00_7009 The value of FCRxFE007009.
- * @param[in] MainPll The main PLL frequency.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- */
-typedef VOID F_F12_ES_NB_PSTATE_INIT (
- IN OUT VOID *FCRxFE00_6000,
- IN OUT VOID *FCRxFE00_6002,
- IN OUT VOID *FCRxFE00_7006,
- IN OUT VOID *FCRxFE00_7009,
- IN UINT32 MainPll,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_F12_ES_NB_PSTATE_INIT *PF_F12_ES_NB_PSTATE_INIT;
-
-/**
- * Return the appropriate value of a certain NB P-state related register.
- *
- * @param[in,out] FCRxFE00_6000 The value of FCRxFE006000.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- */
-typedef VOID F_F12_ES_POWER_PLANE_INIT (
- IN OUT VOID *FCRxFE00_6000,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_F12_ES_POWER_PLANE_INIT *PF_F12_ES_POWER_PLANE_INIT;
-
-/**
- * Implements an early sample workaround required for C6
- *
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- */
-typedef VOID F_F12_ES_C6_INIT (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_F12_ES_C6_INIT *PF_F12_ES_C6_INIT;
-
-
-/// Hook points in the core functionality necessary for
-/// providing support for pre-production CPUs.
-typedef struct {
- PF_F12_ES_POWER_PLANE_INIT F12PowerPlaneInitHook; ///< Allows for override of a certain processor register value during power plane init
- PF_F12_ES_NB_PSTATE_INIT F12NbPstateInitHook; ///< Allows for override of certain processor register values for proper NB P-state init
-} F12_ES_CORE_SUPPORT;
-
-/// Hook points in the C6 feature necessary for
-/// providing support for pre-production CPUs.
-typedef struct {
- PF_F12_ES_C6_INIT F12InitializeC6; ///< Hook for erratum 453 workaround
-} F12_ES_C6_SUPPORT;
-
-
-/*---------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *---------------------------------------------------------------------------------------
- */
-
-
-#endif // _OPTION_FAMILY_12H_EARLY_SAMPLE_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionFamily12hInstall.h b/src/vendorcode/amd/agesa/Include/OptionFamily12hInstall.h
deleted file mode 100644
index 63e8b27..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionFamily12hInstall.h
+++ /dev/null
@@ -1,665 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of family 12h support
- *
- * This file generates the defaults tables for family 12h processors.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Core
- * @e \$Revision: 37456 $ @e \$Date: 2010-09-04 04:17:05 +0800 (Sat, 04 Sep 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_FAMILY_12H_INSTALL_H_
-#define _OPTION_FAMILY_12H_INSTALL_H_
-
-
-#include "OptionFamily12hEarlySample.h"
-
-/*
- * Common Family 12h routines
- */
-extern F_CPU_DISABLE_PSTATE F12DisablePstate;
-extern F_CPU_TRANSITION_PSTATE F12TransitionPstate;
-extern F_CPU_GET_TSC_RATE F12GetTscRate;
-extern F_CPU_GET_NB_FREQ F12GetCurrentNbFrequency;
-extern F_CPU_GET_NB_PSTATE_INFO F12GetNbPstateInfo;
-extern F_CPU_IS_NBCOF_INIT_NEEDED F12GetNbCofVidUpdate;
-extern F_CPU_AP_INITIAL_LAUNCH F12LaunchApCore;
-extern F_CPU_GET_IDD_MAX F12GetProcIddMax;
-extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F12GetApMailboxFromHardware;
-extern F_CPU_GET_AP_CORE_NUMBER F12GetApCoreNumber;
-extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F12CpuAmdCoreIdPositionInInitialApicId;
-extern F_CPU_SET_DOWN_CORE_REGISTER F12SetDownCoreRegister;
-extern F_CPU_SET_WARM_RESET_FLAG F12SetAgesaWarmResetFlag;
-extern F_CPU_GET_WARM_RESET_FLAG F12GetAgesaWarmResetFlag;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12BrandIdString1;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12BrandIdString2;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12CacheInfo;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12SysPmTable;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12WheaInitData;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetEmptyArray;
-extern F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO F12GetPlatformTypeSpecificInfo;
-extern CONST REGISTER_TABLE ROMDATA F12PciRegisterTable;
-extern CONST REGISTER_TABLE ROMDATA F12PerCorePciRegisterTable;
-extern CONST REGISTER_TABLE ROMDATA F12MsrRegisterTable;
-extern F_CPU_NUMBER_OF_BRANDSTRING_CORES F12GetNumberOfCoresForBrandstring;
-extern F_GET_EARLY_INIT_TABLE GetCommonEarlyInitOnCoreTable;
-extern F_IS_NB_PSTATE_ENABLED F12IsNbPstateEnabled;
-#if OPTION_EARLY_SAMPLES == TRUE
- extern CONST REGISTER_TABLE ROMDATA F12EarlySampleMsrRegisterTable;
-#endif
-
-/*
- * Install family 12h model 0 support
- */
-
-#ifdef OPTION_FAMILY12H_LN
- #if OPTION_FAMILY12H_LN == TRUE
- extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12LnMicroCodePatchesStruct;
- extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12LnMicrocodeEquivalenceTable;
-
- #if USES_REGISTER_TABLES == TRUE
- CONST REGISTER_TABLE ROMDATA *F12LnRegisterTables[] =
- {
- #if BASE_FAMILY_PCI == TRUE
- &F12PciRegisterTable,
- #endif
- #if BASE_FAMILY_PCI == TRUE
- &F12PerCorePciRegisterTable,
- #endif
- #if BASE_FAMILY_MSR == TRUE
- &F12MsrRegisterTable,
- #if OPTION_EARLY_SAMPLES == TRUE
- &F12EarlySampleMsrRegisterTable,
- #endif
- #endif
- // the end.
- NULL
- };
- #endif
-
- #if USES_REGISTER_TABLES == TRUE
- CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F12LnTableEntryTypeDescriptors[] =
- {
- {MsrRegister, SetRegisterForMsrEntry},
- {PciRegister, SetRegisterForPciEntry},
- {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
- {ProfileFixup, (PF_DO_TABLE_ENTRY)CommonVoid},
- // End
- {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
- };
- #endif
-
- CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF12LnServices =
- {
- 0,
- #if DISABLE_PSTATE == TRUE
- F12DisablePstate,
- #else
- (PF_CPU_DISABLE_PSTATE) CommonAssert,
- #endif
- #if TRANSITION_PSTATE == TRUE
- F12TransitionPstate,
- #else
- (PF_CPU_TRANSITION_PSTATE) CommonAssert,
- #endif
- #if PROC_IDD_MAX == TRUE
- F12GetProcIddMax,
- #else
- (PF_CPU_GET_IDD_MAX) CommonAssert,
- #endif
- #if GET_TSC_RATE == TRUE
- F12GetTscRate,
- #else
- (PF_CPU_GET_TSC_RATE) CommonAssert,
- #endif
- #if GET_NB_FREQ == TRUE
- F12GetCurrentNbFrequency,
- #else
- (PF_CPU_GET_NB_FREQ) CommonAssert,
- #endif
- #if GET_NB_FREQ == TRUE
- F12GetNbPstateInfo,
- #else
- (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
- #endif
- #if IS_NBCOF_INIT_NEEDED == TRUE
- F12GetNbCofVidUpdate,
- #else
- (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
- #endif
- #if AP_INITIAL_LAUNCH == TRUE
- F12LaunchApCore,
- #else
- (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
- #endif
- #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
- F12GetNumberOfCoresForBrandstring,
- #else
- (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
- #endif
- #if GET_AP_MAILBOX_FROM_HW == TRUE
- F12GetApMailboxFromHardware,
- #else
- (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
- #endif
- #if SET_AP_CORE_NUMBER == TRUE
- (PF_CPU_SET_AP_CORE_NUMBER) CommonVoid,
- #else
- (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
- #endif
- #if GET_AP_CORE_NUMBER == TRUE
- F12GetApCoreNumber,
- #else
- (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
- #endif
- #if TRANSFER_AP_CORE_NUMBER == TRUE
- (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid,
- #else
- (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
- #endif
- #if ID_POSITION_INITIAL_APICID == TRUE
- F12CpuAmdCoreIdPositionInInitialApicId,
- #else
- (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
- #endif
- #if SAVE_FEATURES == TRUE
- (PF_CPU_SAVE_FEATURES) CommonVoid,
- #else
- (PF_CPU_SAVE_FEATURES) CommonAssert,
- #endif
- #if WRITE_FEATURES == TRUE
- (PF_CPU_WRITE_FEATURES) CommonVoid,
- #else
- (PF_CPU_WRITE_FEATURES) CommonAssert,
- #endif
- #if SET_WARM_RESET_FLAG == TRUE
- F12SetAgesaWarmResetFlag,
- #else
- (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
- #endif
- #if GET_WARM_RESET_FLAG == TRUE
- F12GetAgesaWarmResetFlag,
- #else
- (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
- #endif
- #if BRAND_STRING1 == TRUE
- GetF12BrandIdString1,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if BRAND_STRING2 == TRUE
- GetF12BrandIdString2,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_PATCHES == TRUE
- GetF12LnMicroCodePatchesStruct,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
- GetF12LnMicrocodeEquivalenceTable,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_CACHE_INFO == TRUE
- GetF12CacheInfo,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_SYSTEM_PM_TABLE == TRUE
- GetF12SysPmTable,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_WHEA_INIT == TRUE
- GetF12WheaInitData,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
- F12GetPlatformTypeSpecificInfo,
- #else
- (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
- #endif
- #if IS_NB_PSTATE_ENABLED == TRUE
- F12IsNbPstateEnabled,
- #else
- (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
- #endif
- #if (BASE_FAMILY_HT_PCI == TRUE)
- (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
- #else
- (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
- #endif
- #if (BASE_FAMILY_HT_PCI == TRUE)
- (PF_SET_HT_PHY_REGISTER) CommonVoid,
- #else
- (PF_SET_HT_PHY_REGISTER) CommonAssert,
- #endif
- #if BASE_FAMILY_PCI == TRUE
- (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
- #else
- (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
- #endif
- #if USES_REGISTER_TABLES == TRUE
- (REGISTER_TABLE **) F12LnRegisterTables,
- #else
- NULL,
- #endif
- #if USES_REGISTER_TABLES == TRUE
- (TABLE_ENTRY_TYPE_DESCRIPTOR *) F12LnTableEntryTypeDescriptors,
- #else
- NULL,
- #endif
- #if MODEL_SPECIFIC_HT_PCI == TRUE
- NULL,
- #else
- NULL,
- #endif
- NULL,
- InitCacheDisabled,
- #if AGESA_ENTRY_INIT_EARLY == TRUE
- GetCommonEarlyInitOnCoreTable
- #else
- (PF_GET_EARLY_INIT_TABLE) CommonVoid
- #endif
- };
-
- #define LN_SOCKETS 1
- #define LN_MODULES 1
- #define LN_RECOVERY_SOCKETS 1
- #define LN_RECOVERY_MODULES 1
- extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF12LnLogicalIdAndRev;
- #define OPT_F12_LN_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF12LnLogicalIdAndRev,
- #ifndef ADVCFG_PLATFORM_SOCKETS
- #define ADVCFG_PLATFORM_SOCKETS LN_SOCKETS
- #else
- #if ADVCFG_PLATFORM_SOCKETS < LN_SOCKETS
- #undef ADVCFG_PLATFORM_SOCKETS
- #define ADVCFG_PLATFORM_SOCKETS LN_SOCKETS
- #endif
- #endif
- #ifndef ADVCFG_PLATFORM_MODULES
- #define ADVCFG_PLATFORM_MODULES LN_MODULES
- #else
- #if ADVCFG_PLATFORM_MODULES < LN_MODULES
- #undef ADVCFG_PLATFORM_MODULES
- #define ADVCFG_PLATFORM_MODULES LN_MODULES
- #endif
- #endif
-
- #if GET_PATCHES == TRUE
- #define F12_LN_UCODE_02
-
- // If a patch is required for recovery mode to function properly, add a
- // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
- #if AGESA_ENTRY_INIT_EARLY == TRUE
- #if OPTION_EARLY_SAMPLES == TRUE
- extern CONST MICROCODE_PATCHES ROMDATA CpuF12MicrocodePatch03000002;
- #undef F12_LN_UCODE_02
- #define F12_LN_UCODE_02 &CpuF12MicrocodePatch03000002,
- #endif
- #endif
-
- CONST MICROCODE_PATCHES ROMDATA *CpuF12LnMicroCodePatchArray[] =
- {
- F12_LN_UCODE_02
- NULL
- };
-
- CONST UINT8 ROMDATA CpuF12LnNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF12LnMicroCodePatchArray) / sizeof (CpuF12LnMicroCodePatchArray[0])) - 1);
- #endif
-
- #if OPTION_EARLY_SAMPLES == TRUE
- extern F_F12_ES_NB_PSTATE_INIT F12NbPstateInitEarlySampleHook;
- extern F_F12_ES_POWER_PLANE_INIT F12PowerPlaneInitEarlySampleHook;
-
- CONST F12_ES_CORE_SUPPORT ROMDATA F12EarlySampleCoreSupport =
- {
- #if AGESA_ENTRY_INIT_EARLY == TRUE
- F12PowerPlaneInitEarlySampleHook,
- #else
- (PF_F12_ES_POWER_PLANE_INIT) CommonAssert,
- #endif
- #if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_RECOVERY == TRUE)
- F12NbPstateInitEarlySampleHook
- #else
- (PF_F12_ES_NB_PSTATE_INIT) CommonAssert
- #endif
- };
- #else
- CONST F12_ES_CORE_SUPPORT ROMDATA F12EarlySampleCoreSupport =
- {
- #if AGESA_ENTRY_INIT_EARLY == TRUE
- (PF_F12_ES_POWER_PLANE_INIT) CommonVoid,
- #else
- (PF_F12_ES_POWER_PLANE_INIT) CommonAssert,
- #endif
- #if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_RECOVERY == TRUE)
- (PF_F12_ES_NB_PSTATE_INIT) CommonVoid
- #else
- (PF_F12_ES_NB_PSTATE_INIT) CommonAssert
- #endif
- };
- #endif
-
- #define OPT_F12_LN_CPU {AMD_FAMILY_12_LN, &cpuF12LnServices},
- #else // OPTION_FAMILY12H_LN == TRUE
- #define OPT_F12_LN_CPU
- #define OPT_F12_LN_ID
- #endif // OPTION_FAMILY12H_LN == TRUE
-#else // defined (OPTION_FAMILY12H_LN)
- #define OPT_F12_LN_CPU
- #define OPT_F12_LN_ID
-#endif // defined (OPTION_FAMILY12H_LN)
-
-
-/*
- * Install unknown family 12h support
- */
-
-#if USES_REGISTER_TABLES == TRUE
- CONST REGISTER_TABLE ROMDATA *F12UnknownRegisterTables[] =
- {
- #if BASE_FAMILY_PCI == TRUE
- &F12PciRegisterTable,
- #endif
- #if BASE_FAMILY_PCI == TRUE
- &F12PerCorePciRegisterTable,
- #endif
- #if BASE_FAMILY_MSR == TRUE
- &F12MsrRegisterTable,
- #endif
- // the end.
- NULL
- };
-#endif
-
-#if USES_REGISTER_TABLES == TRUE
- CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F12UnknownTableEntryTypeDescriptors[] =
- {
- {MsrRegister, SetRegisterForMsrEntry},
- {PciRegister, SetRegisterForPciEntry},
- {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
- {ProfileFixup, (PF_DO_TABLE_ENTRY)CommonVoid},
- // End
- {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
- };
-#endif
-
-CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF12UnknownServices =
-{
- 0,
- #if DISABLE_PSTATE == TRUE
- F12DisablePstate,
- #else
- (PF_CPU_DISABLE_PSTATE) CommonAssert,
- #endif
- #if TRANSITION_PSTATE == TRUE
- F12TransitionPstate,
- #else
- (PF_CPU_TRANSITION_PSTATE) CommonAssert,
- #endif
- #if PROC_IDD_MAX == TRUE
- F12GetProcIddMax,
- #else
- (PF_CPU_GET_IDD_MAX) CommonAssert,
- #endif
- #if GET_TSC_RATE == TRUE
- F12GetTscRate,
- #else
- (PF_CPU_GET_TSC_RATE) CommonAssert,
- #endif
- #if GET_NB_FREQ == TRUE
- F12GetCurrentNbFrequency,
- #else
- (PF_CPU_GET_NB_FREQ) CommonAssert,
- #endif
- #if GET_NB_FREQ == TRUE
- F12GetNbPstateInfo,
- #else
- (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
- #endif
- #if IS_NBCOF_INIT_NEEDED == TRUE
- F12GetNbCofVidUpdate,
- #else
- (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
- #endif
- #if AP_INITIAL_LAUNCH == TRUE
- F12LaunchApCore,
- #else
- (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
- #endif
- #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
- F12GetNumberOfCoresForBrandstring,
- #else
- (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
- #endif
- #if GET_AP_MAILBOX_FROM_HW == TRUE
- F12GetApMailboxFromHardware,
- #else
- (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
- #endif
- #if SET_AP_CORE_NUMBER == TRUE
- (PF_CPU_SET_AP_CORE_NUMBER) CommonVoid,
- #else
- (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
- #endif
- #if GET_AP_CORE_NUMBER == TRUE
- F12GetApCoreNumber,
- #else
- (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
- #endif
- #if TRANSFER_AP_CORE_NUMBER == TRUE
- (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid,
- #else
- (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
- #endif
- #if ID_POSITION_INITIAL_APICID == TRUE
- F12CpuAmdCoreIdPositionInInitialApicId,
- #else
- (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
- #endif
- #if SAVE_FEATURES == TRUE
- (PF_CPU_SAVE_FEATURES) CommonVoid,
- #else
- (PF_CPU_SAVE_FEATURES) CommonAssert,
- #endif
- #if WRITE_FEATURES == TRUE
- (PF_CPU_WRITE_FEATURES) CommonVoid,
- #else
- (PF_CPU_WRITE_FEATURES) CommonAssert,
- #endif
- #if SET_WARM_RESET_FLAG == TRUE
- F12SetAgesaWarmResetFlag,
- #else
- (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
- #endif
- #if GET_WARM_RESET_FLAG == TRUE
- F12GetAgesaWarmResetFlag,
- #else
- (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
- #endif
- #if BRAND_STRING1 == TRUE
- GetF12BrandIdString1,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if BRAND_STRING2 == TRUE
- GetF12BrandIdString2,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_PATCHES == TRUE
- GetEmptyArray,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
- GetEmptyArray,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_CACHE_INFO == TRUE
- GetF12CacheInfo,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_SYSTEM_PM_TABLE == TRUE
- GetF12SysPmTable,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_WHEA_INIT == TRUE
- GetF12WheaInitData,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
- F12GetPlatformTypeSpecificInfo,
- #else
- (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
- #endif
- #if IS_NB_PSTATE_ENABLED == TRUE
- F12IsNbPstateEnabled,
- #else
- (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
- #endif
- #if (BASE_FAMILY_HT_PCI == TRUE)
- (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
- #else
- (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonAssert,
- #endif
- #if (BASE_FAMILY_HT_PCI == TRUE)
- (PF_SET_HT_PHY_REGISTER) CommonVoid,
- #else
- (PF_SET_HT_PHY_REGISTER) CommonAssert,
- #endif
- #if BASE_FAMILY_PCI == TRUE
- (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
- #else
- (PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert,
- #endif
- #if USES_REGISTER_TABLES == TRUE
- (REGISTER_TABLE **) F12UnknownRegisterTables,
- #else
- NULL,
- #endif
- #if USES_REGISTER_TABLES == TRUE
- (TABLE_ENTRY_TYPE_DESCRIPTOR *) F12UnknownTableEntryTypeDescriptors,
- #else
- NULL,
- #endif
- #if MODEL_SPECIFIC_HT_PCI == TRUE
- NULL,
- #else
- NULL,
- #endif
- NULL,
- InitCacheDisabled,
- #if AGESA_ENTRY_INIT_EARLY == TRUE
- GetCommonEarlyInitOnCoreTable
- #else
- (PF_GET_EARLY_INIT_TABLE) CommonVoid
- #endif
-};
-
- // Family 12h maximum base address is 40 bits. Limit BLDCFG to 40 bits, if appropriate.
-#if (FAMILY_MMIO_BASE_MASK < 0xFFFFFF0000000000ull)
- #undef FAMILY_MMIO_BASE_MASK
- #define FAMILY_MMIO_BASE_MASK (0xFFFFFF0000000000ull)
-#endif
-
-#undef OPT_F12_ID_TABLE
-#define OPT_F12_ID_TABLE {0x12, {AMD_FAMILY_12, AMD_F12_UNKNOWN}, F12LogicalIdTable, (sizeof (F12LogicalIdTable) / sizeof (F12LogicalIdTable[0]))},
-#define OPT_F12_UNKNOWN_CPU {AMD_FAMILY_12, &cpuF12UnknownServices},
-
-#undef OPT_F12_TABLE
-#define OPT_F12_TABLE OPT_F12_LN_CPU OPT_F12_UNKNOWN_CPU
-
-#if OPTION_FS1_SOCKET_SUPPORT == TRUE
- #define F12_FS1_BRANDSTRING1 NULL,
- #define F12_FS1_BRANDSTRING2 NULL,
-#else
- #define F12_FS1_BRANDSTRING1
- #define F12_FS1_BRANDSTRING2
-#endif
-#if OPTION_FM1_SOCKET_SUPPORT == TRUE
- #define F12_FM1_BRANDSTRING1 NULL,
- #define F12_FM1_BRANDSTRING2 NULL,
-#else
- #define F12_FM1_BRANDSTRING1
- #define F12_FM1_BRANDSTRING2
-#endif
-#if OPTION_FP1_SOCKET_SUPPORT == TRUE
- #define F12_FP1_BRANDSTRING1 NULL,
- #define F12_FP1_BRANDSTRING2 NULL,
-#else
- #define F12_FP1_BRANDSTRING1
- #define F12_FP1_BRANDSTRING2
-#endif
-
-#if BRAND_STRING1 == TRUE
- CONST CPU_BRAND_TABLE ROMDATA *F12BrandIdString1Tables[] =
- {
- F12_FS1_BRANDSTRING1
- F12_FM1_BRANDSTRING1
- F12_FP1_BRANDSTRING1
- };
-
- CONST UINT8 F12BrandIdString1TableCount = (sizeof (F12BrandIdString1Tables) / sizeof (F12BrandIdString1Tables[0]));
-#endif
-
-#if BRAND_STRING2 == TRUE
- CONST CPU_BRAND_TABLE ROMDATA *F12BrandIdString2Tables[] =
- {
- F12_FS1_BRANDSTRING2
- F12_FM1_BRANDSTRING2
- F12_FP1_BRANDSTRING2
- };
-
- CONST UINT8 F12BrandIdString2TableCount = (sizeof (F12BrandIdString2Tables) / sizeof (F12BrandIdString2Tables[0]));
-#endif
-
-CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY ROMDATA F12LogicalIdTable[] =
-{
- OPT_F12_LN_ID
-};
-
-#endif // _OPTION_FAMILY_12H_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionFamily14hEarlySample.h b/src/vendorcode/amd/agesa/Include/OptionFamily14hEarlySample.h
deleted file mode 100644
index ef042bd..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionFamily14hEarlySample.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Family 14h 'early sample' support
- *
- * This file defines the required structures for family 14h pre-production processors.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Core
- * @e \$Revision: 37018 $ @e \$Date: 2010-08-28 05:46:16 +0800 (Sat, 28 Aug 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_FAMILY_14H_EARLY_SAMPLE_H_
-#define _OPTION_FAMILY_14H_EARLY_SAMPLE_H_
-
-
-/*---------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *---------------------------------------------------------------------------------------
- */
-/**
- * Return the correct early init table pointer.
- *
- * @param[in,out] Table The early init table pointer.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- */
-typedef VOID F_F14_ES_GET_EARLY_INIT_TABLE (
- IN OUT CONST VOID **Table,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_F14_ES_GET_EARLY_INIT_TABLE *PF_F14_ES_GET_EARLY_INIT_TABLE;
-
-/**
- * Return the appropriate values of certain NB P-state related registers.
- *
- * @param[in,out] FCRxFE00_6000 The value of FCRxFE006000.
- * @param[in,out] FCRxFE00_6002 The value of FCRxFE006002.
- * @param[in,out] FCRxFE00_7006 The value of FCRxFE007006.
- * @param[in,out] FCRxFE00_7009 The value of FCRxFE007009.
- * @param[in] MainPll The main PLL frequency.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- */
-typedef VOID F_F14_ES_NB_PSTATE_INIT (
- IN OUT VOID *FCRxFE00_6000,
- IN OUT VOID *FCRxFE00_6002,
- IN OUT VOID *FCRxFE00_7006,
- IN OUT VOID *FCRxFE00_7009,
- IN UINT32 MainPll,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_F14_ES_NB_PSTATE_INIT *PF_F14_ES_NB_PSTATE_INIT;
-
-/**
- * Return the appropriate value of a certain NB P-state related register.
- *
- * @param[in,out] FCRxFE00_6000 The value of FCRxFE006000.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- */
-typedef VOID F_F14_ES_POWER_PLANE_INIT (
- IN OUT VOID *FCRxFE00_6000,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_F14_ES_POWER_PLANE_INIT *PF_F14_ES_POWER_PLANE_INIT;
-
-/**
- * Returns whether or not the processor should enable the C6 feature.
- *
- * @param[in,out] IsEnabled Whether or not to enable C6
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- */
-typedef VOID F_F14_ES_IS_C6_SUPPORTED (
- IN OUT BOOLEAN *IsEnabled,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_F14_ES_IS_C6_SUPPORTED *PF_F14_ES_IS_C6_SUPPORTED;
-
-/**
- * Implements an early sample workaround required for C6
- *
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- */
-typedef VOID F_F14_ES_C6_INIT (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_F14_ES_C6_INIT *PF_F14_ES_C6_INIT;
-
-
-/// Hook points in the core functionality necessary for
-/// providing support for pre-production CPUs.
-typedef struct {
- PF_F14_ES_GET_EARLY_INIT_TABLE F14GetEarlyInitTableHook; ///< Early init table pointer override
- PF_F14_ES_POWER_PLANE_INIT F14PowerPlaneInitHook; ///< Allows for override of a certain processor register value during power plane init
- PF_F14_ES_NB_PSTATE_INIT F14NbPstateInitHook; ///< Allows for override of certain processor register values for proper NB P-state init
-} F14_ES_CORE_SUPPORT;
-
-/// Hook points in the C6 feature necessary for
-/// providing support for pre-production CPUs.
-typedef struct {
- PF_F14_ES_IS_C6_SUPPORTED F14IsC6SupportedHook; ///< C6 enablement override
- PF_F14_ES_C6_INIT F14InitializeC6; ///< Hook for erratum 453 workaround
-} F14_ES_C6_SUPPORT;
-
-
-/*---------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *---------------------------------------------------------------------------------------
- */
-
-
-#endif // _OPTION_FAMILY_14H_EARLY_SAMPLE_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionFamily14hInstall.h b/src/vendorcode/amd/agesa/Include/OptionFamily14hInstall.h
deleted file mode 100644
index 38a287d..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionFamily14hInstall.h
+++ /dev/null
@@ -1,661 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of family 14h support
- *
- * This file generates the default tables for family 14h processors.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Core
- * @e \$Revision: 37854 $ @e \$Date: 2010-09-14 06:35:39 +0800 (Tue, 14 Sep 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_FAMILY_14H_INSTALL_H_
-#define _OPTION_FAMILY_14H_INSTALL_H_
-
-
-#include "OptionFamily14hEarlySample.h"
-
-/*
- * Common Family 14h routines
- */
-extern F_CPU_DISABLE_PSTATE F14DisablePstate;
-extern F_CPU_TRANSITION_PSTATE F14TransitionPstate;
-extern F_CPU_GET_TSC_RATE F14GetTscRate;
-extern F_CPU_GET_NB_FREQ F14GetCurrentNbFrequency;
-extern F_CPU_GET_NB_PSTATE_INFO F14GetNbPstateInfo;
-extern F_CPU_IS_NBCOF_INIT_NEEDED F14GetNbCofVidUpdate;
-extern F_CPU_AP_INITIAL_LAUNCH F14LaunchApCore;
-extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F14GetApMailboxFromHardware;
-extern F_CPU_GET_AP_CORE_NUMBER F14GetApCoreNumber;
-extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F14CpuAmdCoreIdPositionInInitialApicId;
-extern F_CPU_SET_WARM_RESET_FLAG F14SetAgesaWarmResetFlag;
-extern F_CPU_GET_WARM_RESET_FLAG F14GetAgesaWarmResetFlag;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14BrandIdString1;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14BrandIdString2;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14CacheInfo;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14SysPmTable;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14WheaInitData;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetEmptyArray;
-extern F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO F14GetPlatformTypeSpecificInfo;
-extern F_CPU_GET_IDD_MAX F14GetProcIddMax;
-extern CONST REGISTER_TABLE ROMDATA F14PciRegisterTable;
-extern CONST REGISTER_TABLE ROMDATA F14PerCorePciRegisterTable;
-extern CONST REGISTER_TABLE ROMDATA F14MsrRegisterTable;
-extern F_CPU_NUMBER_OF_BRANDSTRING_CORES F14GetNumberOfCoresForBrandstring;
-extern F_GET_EARLY_INIT_TABLE GetF14OnEarlyInitOnCoreTable;
-extern F_IS_NB_PSTATE_ENABLED F14IsNbPstateEnabled;
-#if OPTION_EARLY_SAMPLES == TRUE
- extern CONST REGISTER_TABLE ROMDATA F14EarlySampleMsrRegisterTable;
-#endif
-
-
-/*
- * Install family 14h model 0 support
- */
-#ifdef OPTION_FAMILY14H_ON
- #if OPTION_FAMILY14H_ON == TRUE
- extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14OnMicroCodePatchesStruct;
- extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14OnMicrocodeEquivalenceTable;
-
- #if USES_REGISTER_TABLES == TRUE
- CONST REGISTER_TABLE ROMDATA *F14OnRegisterTables[] =
- {
- #if BASE_FAMILY_PCI == TRUE
- &F14PciRegisterTable,
- #endif
- #if BASE_FAMILY_PCI == TRUE
- &F14PerCorePciRegisterTable,
- #endif
- #if BASE_FAMILY_MSR == TRUE
- &F14MsrRegisterTable,
- #if OPTION_EARLY_SAMPLES == TRUE
- &F14EarlySampleMsrRegisterTable,
- #endif
- #endif
- // the end.
- NULL
- };
- #endif
-
- #if USES_REGISTER_TABLES == TRUE
- CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F14OnTableEntryTypeDescriptors[] =
- {
- {MsrRegister, SetRegisterForMsrEntry},
- {PciRegister, SetRegisterForPciEntry},
- {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
- // End
- {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
- };
- #endif
-
- CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF14OnServices =
- {
- 0,
- #if DISABLE_PSTATE == TRUE
- F14DisablePstate,
- #else
- (PF_CPU_DISABLE_PSTATE) CommonAssert,
- #endif
- #if TRANSITION_PSTATE == TRUE
- F14TransitionPstate,
- #else
- (PF_CPU_TRANSITION_PSTATE) CommonAssert,
- #endif
- #if PROC_IDD_MAX == TRUE
- F14GetProcIddMax,
- #else
- (PF_CPU_GET_IDD_MAX) CommonAssert,
- #endif
- #if GET_TSC_RATE == TRUE
- F14GetTscRate,
- #else
- (PF_CPU_GET_TSC_RATE) CommonAssert,
- #endif
- #if GET_NB_FREQ == TRUE
- F14GetCurrentNbFrequency,
- #else
- (PF_CPU_GET_NB_FREQ) CommonAssert,
- #endif
- #if GET_NB_FREQ == TRUE
- F14GetNbPstateInfo,
- #else
- (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
- #endif
- #if IS_NBCOF_INIT_NEEDED == TRUE
- F14GetNbCofVidUpdate,
- #else
- (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
- #endif
- #if AP_INITIAL_LAUNCH == TRUE
- F14LaunchApCore,
- #else
- (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
- #endif
- #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
- F14GetNumberOfCoresForBrandstring,
- #else
- (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
- #endif
- #if GET_AP_MAILBOX_FROM_HW == TRUE
- F14GetApMailboxFromHardware,
- #else
- (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
- #endif
- #if SET_AP_CORE_NUMBER == TRUE
- (PF_CPU_SET_AP_CORE_NUMBER) CommonVoid,
- #else
- (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
- #endif
- #if GET_AP_CORE_NUMBER == TRUE
- F14GetApCoreNumber,
- #else
- (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
- #endif
- #if TRANSFER_AP_CORE_NUMBER == TRUE
- (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid,
- #else
- (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
- #endif
- #if ID_POSITION_INITIAL_APICID == TRUE
- F14CpuAmdCoreIdPositionInInitialApicId,
- #else
- (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
- #endif
- #if SAVE_FEATURES == TRUE
- (PF_CPU_SAVE_FEATURES) CommonVoid,
- #else
- (PF_CPU_SAVE_FEATURES) CommonAssert,
- #endif
- #if WRITE_FEATURES == TRUE
- (PF_CPU_WRITE_FEATURES) CommonVoid,
- #else
- (PF_CPU_WRITE_FEATURES) CommonAssert,
- #endif
- #if SET_WARM_RESET_FLAG == TRUE
- F14SetAgesaWarmResetFlag,
- #else
- (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
- #endif
- #if GET_WARM_RESET_FLAG == TRUE
- F14GetAgesaWarmResetFlag,
- #else
- (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
- #endif
- #if BRAND_STRING1 == TRUE
- GetF14BrandIdString1,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if BRAND_STRING2 == TRUE
- GetF14BrandIdString2,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_PATCHES == TRUE
- GetF14OnMicroCodePatchesStruct,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
- GetF14OnMicrocodeEquivalenceTable,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_CACHE_INFO == TRUE
- GetF14CacheInfo,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_SYSTEM_PM_TABLE == TRUE
- GetF14SysPmTable,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_WHEA_INIT == TRUE
- GetF14WheaInitData,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
- F14GetPlatformTypeSpecificInfo,
- #else
- (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
- #endif
- #if IS_NB_PSTATE_ENABLED == TRUE
- F14IsNbPstateEnabled,
- #else
- (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
- #endif
- #if (BASE_FAMILY_HT_PCI == TRUE)
- (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
- #else
- (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
- #endif
- #if (BASE_FAMILY_HT_PCI == TRUE)
- (PF_SET_HT_PHY_REGISTER) CommonVoid,
- #else
- (PF_SET_HT_PHY_REGISTER) CommonAssert,
- #endif
- #if BASE_FAMILY_PCI == TRUE
- (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
- #else
- (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
- #endif
- #if USES_REGISTER_TABLES == TRUE
- (REGISTER_TABLE **) F14OnRegisterTables,
- #else
- NULL,
- #endif
- #if USES_REGISTER_TABLES == TRUE
- (TABLE_ENTRY_TYPE_DESCRIPTOR *) F14OnTableEntryTypeDescriptors,
- #else
- NULL,
- #endif
- #if MODEL_SPECIFIC_HT_PCI == TRUE
- NULL,
- #else
- NULL,
- #endif
- NULL,
- InitCacheDisabled,
- #if AGESA_ENTRY_INIT_EARLY == TRUE
- GetF14OnEarlyInitOnCoreTable
- #else
- (PF_GET_EARLY_INIT_TABLE) CommonVoid
- #endif
- };
-
- #define ON_SOCKETS 1
- #define ON_MODULES 1
- #define ON_RECOVERY_SOCKETS 1
- #define ON_RECOVERY_MODULES 1
- extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF14OnLogicalIdAndRev;
- #define OPT_F14_ON_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF14OnLogicalIdAndRev,
- #ifndef ADVCFG_PLATFORM_SOCKETS
- #define ADVCFG_PLATFORM_SOCKETS ON_SOCKETS
- #else
- #if ADVCFG_PLATFORM_SOCKETS < ON_SOCKETS
- #undef ADVCFG_PLATFORM_SOCKETS
- #define ADVCFG_PLATFORM_SOCKETS ON_SOCKETS
- #endif
- #endif
- #ifndef ADVCFG_PLATFORM_MODULES
- #define ADVCFG_PLATFORM_MODULES ON_MODULES
- #else
- #if ADVCFG_PLATFORM_MODULES < ON_MODULES
- #undef ADVCFG_PLATFORM_MODULES
- #define ADVCFG_PLATFORM_MODULES ON_MODULES
- #endif
- #endif
-
- #if GET_PATCHES == TRUE
- #define F14_ON_UCODE_0B
- #define F14_ON_UCODE_1A
- #define F14_ON_UCODE_25
-
- // If a patch is required for recovery mode to function properly, add a
- // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
- #if AGESA_ENTRY_INIT_EARLY == TRUE
- #if OPTION_EARLY_SAMPLES == TRUE
- extern CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch0500000B;
- #undef F14_ON_UCODE_0B
- #define F14_ON_UCODE_0B &CpuF14MicrocodePatch0500000B,
-
- extern CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch0500001A;
- #undef F14_ON_UCODE_1A
- #define F14_ON_UCODE_1A &CpuF14MicrocodePatch0500001A,
- #endif
- extern CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch05000025;
- #undef F14_ON_UCODE_25
- #define F14_ON_UCODE_25 &CpuF14MicrocodePatch05000025,
- #endif
-
- CONST MICROCODE_PATCHES ROMDATA *CpuF14OnMicroCodePatchArray[] =
- {
- F14_ON_UCODE_0B
- F14_ON_UCODE_1A
- F14_ON_UCODE_25
- NULL
- };
-
- CONST UINT8 ROMDATA CpuF14OnNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF14OnMicroCodePatchArray) / sizeof (CpuF14OnMicroCodePatchArray[0])) - 1);
- #endif
-
- #if OPTION_EARLY_SAMPLES == TRUE
- extern F_F14_ES_GET_EARLY_INIT_TABLE GetF14OnEarlySampleEarlyInitTable;
- extern F_F14_ES_NB_PSTATE_INIT F14NbPstateInitEarlySampleHook;
- extern F_F14_ES_POWER_PLANE_INIT F14PowerPlaneInitEarlySampleHook;
-
- CONST F14_ES_CORE_SUPPORT ROMDATA F14EarlySampleCoreSupport =
- {
- #if AGESA_ENTRY_INIT_EARLY == TRUE
- GetF14OnEarlySampleEarlyInitTable,
- F14PowerPlaneInitEarlySampleHook,
- #else
- (PF_F14_ES_GET_EARLY_INIT_TABLE) CommonAssert,
- (PF_F14_ES_POWER_PLANE_INIT) CommonAssert,
- #endif
- #if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_RECOVERY == TRUE)
- F14NbPstateInitEarlySampleHook
- #else
- (PF_F14_ES_NB_PSTATE_INIT) CommonAssert
- #endif
- };
- #else
- CONST F14_ES_CORE_SUPPORT ROMDATA F14EarlySampleCoreSupport =
- {
- #if AGESA_ENTRY_INIT_EARLY == TRUE
- (PF_F14_ES_GET_EARLY_INIT_TABLE) CommonVoid,
- (PF_F14_ES_POWER_PLANE_INIT) CommonVoid,
- #else
- (PF_F14_ES_GET_EARLY_INIT_TABLE) CommonAssert,
- (PF_F14_ES_POWER_PLANE_INIT) CommonAssert,
- #endif
- #if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_RECOVERY == TRUE)
- (PF_F14_ES_NB_PSTATE_INIT) CommonVoid
- #else
- (PF_F14_ES_NB_PSTATE_INIT) CommonAssert
- #endif
- };
- #endif
-
- #define OPT_F14_ON_CPU {AMD_FAMILY_14_ON, &cpuF14OnServices},
- #else // OPTION_FAMILY14H_ON == TRUE
- #define OPT_F14_ON_CPU
- #define OPT_F14_ON_ID
- #endif // OPTION_FAMILY14H_ON == TRUE
-#else // defined (OPTION_FAMILY14H_ON)
- #define OPT_F14_ON_CPU
- #define OPT_F14_ON_ID
-#endif // defined (OPTION_FAMILY14H_ON)
-
-/*
- * Install unknown family 14h support
- */
-
-#if USES_REGISTER_TABLES == TRUE
- CONST REGISTER_TABLE ROMDATA *F14UnknownRegisterTables[] =
- {
- #if BASE_FAMILY_PCI == TRUE
- &F14PciRegisterTable,
- #endif
- #if BASE_FAMILY_PCI == TRUE
- &F14PerCorePciRegisterTable,
- #endif
- #if BASE_FAMILY_MSR == TRUE
- &F14MsrRegisterTable,
- #endif
- // the end.
- NULL
- };
-#endif
-
-#if USES_REGISTER_TABLES == TRUE
- CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F14UnknownTableEntryTypeDescriptors[] =
- {
- {MsrRegister, SetRegisterForMsrEntry},
- {PciRegister, SetRegisterForPciEntry},
- {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
- // End
- {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
- };
-#endif
-
-CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF14UnknownServices =
-{
- 0,
- #if DISABLE_PSTATE == TRUE
- F14DisablePstate,
- #else
- (PF_CPU_DISABLE_PSTATE) CommonAssert,
- #endif
- #if TRANSITION_PSTATE == TRUE
- F14TransitionPstate,
- #else
- (PF_CPU_TRANSITION_PSTATE) CommonAssert,
- #endif
- #if PROC_IDD_MAX == TRUE
- (PF_CPU_GET_IDD_MAX) F14GetProcIddMax,
- #else
- (PF_CPU_GET_IDD_MAX) CommonAssert,
- #endif
- #if GET_TSC_RATE == TRUE
- F14GetTscRate,
- #else
- (PF_CPU_GET_TSC_RATE) CommonAssert,
- #endif
- #if GET_NB_FREQ == TRUE
- F14GetCurrentNbFrequency,
- #else
- (PF_CPU_GET_NB_FREQ) CommonAssert,
- #endif
- #if GET_NB_FREQ == TRUE
- F14GetNbPstateInfo,
- #else
- (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
- #endif
- #if IS_NBCOF_INIT_NEEDED == TRUE
- F14GetNbCofVidUpdate,
- #else
- (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
- #endif
- #if AP_INITIAL_LAUNCH == TRUE
- F14LaunchApCore,
- #else
- (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
- #endif
- #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
- F14GetNumberOfCoresForBrandstring,
- #else
- (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
- #endif
- #if GET_AP_MAILBOX_FROM_HW == TRUE
- F14GetApMailboxFromHardware,
- #else
- (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
- #endif
- #if SET_AP_CORE_NUMBER == TRUE
- (PF_CPU_SET_AP_CORE_NUMBER) CommonVoid,
- #else
- (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
- #endif
- #if GET_AP_CORE_NUMBER == TRUE
- F14GetApCoreNumber,
- #else
- (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
- #endif
- #if TRANSFER_AP_CORE_NUMBER == TRUE
- (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid,
- #else
- (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
- #endif
- #if ID_POSITION_INITIAL_APICID == TRUE
- F14CpuAmdCoreIdPositionInInitialApicId,
- #else
- (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
- #endif
- #if SAVE_FEATURES == TRUE
- (PF_CPU_SAVE_FEATURES) CommonVoid,
- #else
- (PF_CPU_SAVE_FEATURES) CommonAssert,
- #endif
- #if WRITE_FEATURES == TRUE
- (PF_CPU_WRITE_FEATURES) CommonVoid,
- #else
- (PF_CPU_WRITE_FEATURES) CommonAssert,
- #endif
- #if SET_WARM_RESET_FLAG == TRUE
- F14SetAgesaWarmResetFlag,
- #else
- (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
- #endif
- #if GET_WARM_RESET_FLAG == TRUE
- F14GetAgesaWarmResetFlag,
- #else
- (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
- #endif
- #if BRAND_STRING1 == TRUE
- GetF14BrandIdString1,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if BRAND_STRING2 == TRUE
- GetF14BrandIdString2,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_PATCHES == TRUE
- GetEmptyArray,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
- GetEmptyArray,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_CACHE_INFO == TRUE
- GetF14CacheInfo,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_SYSTEM_PM_TABLE == TRUE
- GetF14SysPmTable,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_WHEA_INIT == TRUE
- GetF14WheaInitData,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
- F14GetPlatformTypeSpecificInfo,
- #else
- (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
- #endif
- #if IS_NB_PSTATE_ENABLED == TRUE
- F14IsNbPstateEnabled,
- #else
- (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
- #endif
- #if (BASE_FAMILY_HT_PCI == TRUE)
- (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
- #else
- (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonVoid,
- #endif
- #if (BASE_FAMILY_HT_PCI == TRUE)
- (PF_SET_HT_PHY_REGISTER) CommonVoid,
- #else
- (PF_SET_HT_PHY_REGISTER) CommonVoid,
- #endif
- #if BASE_FAMILY_PCI == TRUE
- (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
- #else
- (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
- #endif
- #if USES_REGISTER_TABLES == TRUE
- (REGISTER_TABLE **) F14UnknownRegisterTables,
- #else
- NULL,
- #endif
- #if USES_REGISTER_TABLES == TRUE
- (TABLE_ENTRY_TYPE_DESCRIPTOR *) F14UnknownTableEntryTypeDescriptors,
- #else
- NULL,
- #endif
- #if MODEL_SPECIFIC_HT_PCI == TRUE
- NULL,
- #else
- NULL,
- #endif
- NULL,
- InitCacheDisabled,
- #if AGESA_ENTRY_INIT_EARLY == TRUE
- GetF14OnEarlyInitOnCoreTable
- #else
- (PF_GET_EARLY_INIT_TABLE) CommonVoid
- #endif
-};
-
- // Family 14h maximum base address is 40 bits. Limit BLDCFG to 40 bits, if appropriate.
-#if (FAMILY_MMIO_BASE_MASK < 0xFFFFFF0000000000ull)
- #undef FAMILY_MMIO_BASE_MASK
- #define FAMILY_MMIO_BASE_MASK (0xFFFFFF0000000000ull)
-#endif
-
-#undef OPT_F14_ID_TABLE
-#define OPT_F14_ID_TABLE {0x14, {AMD_FAMILY_14, AMD_F14_UNKNOWN}, F14LogicalIdTable, (sizeof (F14LogicalIdTable) / sizeof (F14LogicalIdTable[0]))},
-#define OPT_F14_UNKNOWN_CPU {AMD_FAMILY_14, &cpuF14UnknownServices},
-
-#undef OPT_F14_TABLE
-#define OPT_F14_TABLE OPT_F14_ON_CPU OPT_F14_UNKNOWN_CPU
-
-#if OPTION_FT1_SOCKET_SUPPORT == TRUE
- extern CONST CPU_BRAND_TABLE ROMDATA F14OnBrandIdString1ArrayFt1;
- extern CONST CPU_BRAND_TABLE ROMDATA F14OnBrandIdString2ArrayFt1;
- #define F14_FT1_BRANDSTRING1 &F14OnBrandIdString1ArrayFt1,
- #define F14_FT1_BRANDSTRING2 &F14OnBrandIdString2ArrayFt1,
-#else
- #define F14_FT1_BRANDSTRING1
- #define F14_FT1_BRANDSTRING2
-#endif
-
-#if BRAND_STRING1 == TRUE
- CONST CPU_BRAND_TABLE ROMDATA *F14BrandIdString1Tables[] =
- {
- F14_FT1_BRANDSTRING1
- };
-
- CONST UINT8 F14BrandIdString1TableCount = (sizeof (F14BrandIdString1Tables) / sizeof (F14BrandIdString1Tables[0]));
-#endif
-
-#if BRAND_STRING2 == TRUE
- CONST CPU_BRAND_TABLE ROMDATA *F14BrandIdString2Tables[] =
- {
- F14_FT1_BRANDSTRING2
- };
-
- CONST UINT8 F14BrandIdString2TableCount = (sizeof (F14BrandIdString2Tables) / sizeof (F14BrandIdString2Tables[0]));
-#endif
-
-CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY ROMDATA F14LogicalIdTable[] =
-{
- OPT_F14_ON_ID
-};
-
-#endif // _OPTION_FAMILY_14H_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionFamily15hInstall.h b/src/vendorcode/amd/agesa/Include/OptionFamily15hInstall.h
deleted file mode 100644
index b05bfe3..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionFamily15hInstall.h
+++ /dev/null
@@ -1,717 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of family 15h support
- *
- * This file generates the defaults tables for family 15h processors.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Core
- * @e \$Revision: 37150 $ @e \$Date: 2010-08-31 23:53:37 +0800 (Tue, 31 Aug 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_FAMILY_15H_INSTALL_H_
-#define _OPTION_FAMILY_15H_INSTALL_H_
-
-/*
- * Pull in family specific services based on entry point
- */
-
-/*
- * Common Family 15h routines
- */
-extern F_GET_EARLY_INIT_TABLE GetF15EarlyInitOnCoreTable;
-extern F_IS_NB_PSTATE_ENABLED F15IsNbPstateEnabled;
-
-/*
- * Install family 15h model 0 support
- */
-#ifdef OPTION_FAMILY15H_OR
- #if OPTION_FAMILY15H_OR == TRUE
- extern F_CPU_GET_IDD_MAX F15GetProcIddMax;
- extern F_CPU_GET_NB_PSTATE_INFO F15GetNbPstateInfo;
- extern F_CPU_IS_NBCOF_INIT_NEEDED F15CommonGetNbCofVidUpdate;
- extern F_CPU_DISABLE_PSTATE F15DisablePstate;
- extern F_CPU_TRANSITION_PSTATE F15TransitionPstate;
- extern F_CPU_GET_TSC_RATE F15GetTscRate;
- extern F_CPU_GET_NB_FREQ F15GetCurrentNbFrequency;
- extern F_CPU_AP_INITIAL_LAUNCH F15LaunchApCore;
- extern F_CPU_NUMBER_OF_BRANDSTRING_CORES F15CommonGetNumberOfCoresForBrandstring;
- extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F15GetApMailboxFromHardware;
- extern F_CPU_SET_AP_CORE_NUMBER F15SetApCoreNumber;
- extern F_CPU_GET_AP_CORE_NUMBER F15GetApCoreNumber;
- extern F_CPU_TRANSFER_AP_CORE_NUMBER F15TransferApCoreNumber;
- extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F15CpuAmdCoreIdPositionInInitialApicId;
- extern F_CPU_SAVE_FEATURES F15SaveFeatures;
- extern F_CPU_WRITE_FEATURES F15WriteFeatures;
- extern F_CPU_SET_WARM_RESET_FLAG F15SetAgesaWarmResetFlag;
- extern F_CPU_GET_WARM_RESET_FLAG F15GetAgesaWarmResetFlag;
- extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15CacheInfo;
- extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15SysPmTable;
- extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15WheaInitData;
- extern F_CPU_SET_CFOH_REG SetF15CacheFlushOnHaltRegister;
- extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetEmptyArray;
- extern F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO F15GetPlatformTypeSpecificInfo;
- extern F_NEXT_LINK_HAS_HTFPY_FEATS F15NextLinkHasHtPhyFeats;
- extern F_SET_HT_PHY_REGISTER F15SetHtPhyRegister;
- extern F_GET_NEXT_HT_LINK_FEATURES F15GetNextHtLinkFeatures;
- extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15OrMicroCodePatchesStruct;
- extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15OrMicrocodeEquivalenceTable;
- extern CONST REGISTER_TABLE ROMDATA F15OrPciRegisterTable;
- extern CONST REGISTER_TABLE ROMDATA F15OrMsrRegisterTable;
- extern CONST REGISTER_TABLE ROMDATA F15OrSharedMsrRegisterTable;
- extern CONST REGISTER_TABLE ROMDATA F15OrHtPhyRegisterTable;
- extern CONST REGISTER_TABLE ROMDATA F15PciRegisterTable;
- extern CONST REGISTER_TABLE ROMDATA F15MsrRegisterTable;
- extern CONST REGISTER_TABLE ROMDATA F15HtPhyRegisterTable;
- extern CONST REGISTER_TABLE ROMDATA F15MultiLinkPciRegisterTable;
- extern CONST REGISTER_TABLE ROMDATA F15SingleLinkPciRegisterTable;
- extern CONST REGISTER_TABLE ROMDATA F15WorkaroundsTable;
- extern CONST PACKAGE_HTLINK_MAP_ITEM ROMDATA HtFam15PackageLinkMap[];
-
- /**
- * Core Pair and core pair primary determination table.
- *
- * The two fields from the core pair hardware register can be used to determine whether
- * even number cores are primary or all cores are primary. It can be extended if it is
- * decided to have other configs as well. The other logically possible value sets are BitMapMapping,
- * but they are currently not supported by the processor.
- */
- CONST CORE_PAIR_MAP ROMDATA HtFam15CorePairMapping[] =
- {
- {1, 1, EvenCoresMapping}, ///< 1 Compute Unit with 2 cores
- {3, 3, EvenCoresMapping}, ///< 2 Compute Units both with 2 Cores
- {7, 7, EvenCoresMapping}, ///< 3 Compute Units all with 2 Cores
- {0xF, 0xF, EvenCoresMapping}, ///< 4 Compute Units all with 2 Cores
- {1, 0, AllCoresMapping}, ///< 1 Compute Unit with 1 core
- {3, 0, AllCoresMapping}, ///< 2 Compute Units both with 1 Core
- {7, 0, AllCoresMapping}, ///< 3 Compute Units all with 1 Core
- {0xF, 0, AllCoresMapping}, ///< 4 Compute Units all with 1 Core
- {HT_LIST_TERMINAL, HT_LIST_TERMINAL, MaxComputeUnitMapping} ///< End
- };
-
-
- #if USES_REGISTER_TABLES == TRUE
- CONST REGISTER_TABLE ROMDATA *F15OrRegisterTables[] =
- {
- #if BASE_FAMILY_PCI == TRUE
- &F15PciRegisterTable,
- #endif
- #if MODEL_SPECIFIC_PCI == TRUE
- &F15MultiLinkPciRegisterTable,
- #endif
- #if MODEL_SPECIFIC_PCI == TRUE
- &F15OrPciRegisterTable,
- #endif
- #if BASE_FAMILY_MSR == TRUE
- &F15MsrRegisterTable,
- #endif
- #if MODEL_SPECIFIC_MSR == TRUE
- &F15OrMsrRegisterTable,
- #endif
- #if MODEL_SPECIFIC_MSR == TRUE
- &F15OrSharedMsrRegisterTable,
- #endif
- #if MODEL_SPECIFIC_HT_PCI == TRUE
- &F15HtPhyRegisterTable,
- #endif
- #if MODEL_SPECIFIC_HT_PCI == TRUE
- &F15OrHtPhyRegisterTable,
- #endif
- #if BASE_FAMILY_WORKAROUNDS == TRUE
- &F15WorkaroundsTable,
- #endif
- // the end.
- NULL
- };
- #endif
-
- #if USES_REGISTER_TABLES == TRUE
- CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F15OrTableEntryTypeDescriptors[] =
- {
- {MsrRegister, SetRegisterForMsrEntry},
- {PciRegister, SetRegisterForPciEntry},
- {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
- {HtPhyRegister, SetRegisterForHtPhyEntry},
- {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
- {DeemphasisRegister, SetRegisterForDeemphasisEntry},
- {HtPhyFreqRegister, SetRegisterForHtPhyFreqEntry},
- {ProfileFixup, SetRegisterForPerformanceProfileEntry},
- {HtHostPciRegister, SetRegisterForHtHostEntry},
- {HtHostPerfPciRegister, SetRegisterForHtHostPerfEntry},
- {HtTokenPciRegister, SetRegisterForHtLinkTokenEntry},
- {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
- {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
- {CompUnitCountsPciRegister, SetRegisterForComputeUnitCountsEntry},
- {TokenPciRegister, SetRegisterForTokenPciEntry},
- {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
- {HtLinkPciRegister, SetRegisterForHtLinkPciEntry},
- // End
- {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
- };
- #endif
-
- CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF15OrServices =
- {
- 0,
- #if DISABLE_PSTATE == TRUE
- F15DisablePstate,
- #else
- (PF_CPU_DISABLE_PSTATE) CommonAssert,
- #endif
- #if TRANSITION_PSTATE == TRUE
- F15TransitionPstate,
- #else
- (PF_CPU_TRANSITION_PSTATE) CommonAssert,
- #endif
- #if PROC_IDD_MAX == TRUE
- F15GetProcIddMax,
- #else
- (PF_CPU_GET_IDD_MAX) CommonAssert,
- #endif
- #if GET_TSC_RATE == TRUE
- F15GetTscRate,
- #else
- (PF_CPU_GET_TSC_RATE) CommonAssert,
- #endif
- #if GET_NB_FREQ == TRUE
- F15GetCurrentNbFrequency,
- #else
- (PF_CPU_GET_NB_FREQ) CommonAssert,
- #endif
- #if GET_NB_FREQ == TRUE
- F15GetNbPstateInfo,
- #else
- (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
- #endif
- #if IS_NBCOF_INIT_NEEDED == TRUE
- F15CommonGetNbCofVidUpdate,
- #else
- (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
- #endif
- #if AP_INITIAL_LAUNCH == TRUE
- F15LaunchApCore,
- #else
- (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
- #endif
- #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
- F15CommonGetNumberOfCoresForBrandstring,
- #else
- (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
- #endif
- #if GET_AP_MAILBOX_FROM_HW == TRUE
- F15GetApMailboxFromHardware,
- #else
- (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
- #endif
- #if SET_AP_CORE_NUMBER == TRUE
- F15SetApCoreNumber,
- #else
- (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
- #endif
- #if GET_AP_CORE_NUMBER == TRUE
- F15GetApCoreNumber,
- #else
- (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
- #endif
- #if TRANSFER_AP_CORE_NUMBER == TRUE
- F15TransferApCoreNumber,
- #else
- (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
- #endif
- #if ID_POSITION_INITIAL_APICID == TRUE
- F15CpuAmdCoreIdPositionInInitialApicId,
- #else
- (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
- #endif
- #if SAVE_FEATURES == TRUE
- // F15SaveFeatures,
- (PF_CPU_SAVE_FEATURES) CommonVoid,
- #else
- (PF_CPU_SAVE_FEATURES) CommonAssert,
- #endif
- #if WRITE_FEATURES == TRUE
- // F15WriteFeatures,
- (PF_CPU_WRITE_FEATURES) CommonVoid,
- #else
- (PF_CPU_WRITE_FEATURES) CommonAssert,
- #endif
- #if SET_WARM_RESET_FLAG == TRUE
- F15SetAgesaWarmResetFlag,
- #else
- (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
- #endif
- #if GET_WARM_RESET_FLAG == TRUE
- F15GetAgesaWarmResetFlag,
- #else
- (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
- #endif
- #if BRAND_STRING1 == TRUE
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if BRAND_STRING2 == TRUE
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_PATCHES == TRUE
- GetF15OrMicroCodePatchesStruct,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
- GetF15OrMicrocodeEquivalenceTable,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_CACHE_INFO == TRUE
- GetF15CacheInfo,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_SYSTEM_PM_TABLE == TRUE
- GetF15SysPmTable,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_WHEA_INIT == TRUE
- GetF15WheaInitData,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
- F15GetPlatformTypeSpecificInfo,
- #else
- (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
- #endif
- #if IS_NB_PSTATE_ENABLED == TRUE
- F15IsNbPstateEnabled,
- #else
- (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
- #endif
- #if (BASE_FAMILY_HT_PCI == TRUE)
- F15NextLinkHasHtPhyFeats,
- #else
- (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
- #endif
- #if (BASE_FAMILY_HT_PCI == TRUE)
- F15SetHtPhyRegister,
- #else
- (PF_SET_HT_PHY_REGISTER) CommonAssert,
- #endif
- #if BASE_FAMILY_PCI == TRUE
- F15GetNextHtLinkFeatures,
- #else
- (PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert,
- #endif
- #if USES_REGISTER_TABLES == TRUE
- (REGISTER_TABLE **) F15OrRegisterTables,
- #else
- NULL,
- #endif
- #if USES_REGISTER_TABLES == TRUE
- (TABLE_ENTRY_TYPE_DESCRIPTOR *) F15OrTableEntryTypeDescriptors,
- #else
- NULL,
- #endif
- #if MODEL_SPECIFIC_HT_PCI == TRUE
- (PACKAGE_HTLINK_MAP) &HtFam15PackageLinkMap,
- #else
- NULL,
- #endif
- (CORE_PAIR_MAP *) &HtFam15CorePairMapping,
- InitCacheEnabled,
- #if AGESA_ENTRY_INIT_EARLY == TRUE
- GetF15EarlyInitOnCoreTable
- #else
- (PF_GET_EARLY_INIT_TABLE) CommonVoid
- #endif
- };
-
- #define OR_SOCKETS 8
- #define OR_MODULES 2
- #define OR_RECOVERY_SOCKETS 1
- #define OR_RECOVERY_MODULES 1
- extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF15OrLogicalIdAndRev;
- #define OPT_F15_OR_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF15OrLogicalIdAndRev,
- #ifndef ADVCFG_PLATFORM_SOCKETS
- #define ADVCFG_PLATFORM_SOCKETS OR_SOCKETS
- #else
- #if ADVCFG_PLATFORM_SOCKETS < OR_SOCKETS
- #undef ADVCFG_PLATFORM_SOCKETS
- #define ADVCFG_PLATFORM_SOCKETS OR_SOCKETS
- #endif
- #endif
- #ifndef ADVCFG_PLATFORM_MODULES
- #define ADVCFG_PLATFORM_MODULES OR_MODULES
- #else
- #if ADVCFG_PLATFORM_MODULES < OR_MODULES
- #undef ADVCFG_PLATFORM_MODULES
- #define ADVCFG_PLATFORM_MODULES OR_MODULES
- #endif
- #endif
-
- #if GET_PATCHES == TRUE
- #define F15_OR_UCODE_09
-
- #if AGESA_ENTRY_INIT_EARLY == TRUE
- #if OPTION_EARLY_SAMPLES == TRUE
- extern CONST MICROCODE_PATCHES_4K ROMDATA CpuF15OrMicrocodePatch06000009;
- #undef F15_OR_UCODE_09
- #define F15_OR_UCODE_09 &CpuF15OrMicrocodePatch06000009,
- #endif
- #endif
-
- CONST MICROCODE_PATCHES_4K ROMDATA *CpuF15OrMicroCodePatchArray[] =
- {
- F15_OR_UCODE_09
- NULL
- };
-
- CONST UINT8 ROMDATA CpuF15OrNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF15OrMicroCodePatchArray) / sizeof (CpuF15OrMicroCodePatchArray[0])) - 1);
- #endif
-
- #define OPT_F15_OR_CPU {AMD_FAMILY_15_OR, &cpuF15OrServices},
-
- #else // OPTION_FAMILY15H_OR == TRUE
- #define OPT_F15_OR_CPU
- #define OPT_F15_OR_ID
- #endif // OPTION_FAMILY15H_OR == TRUE
-#else // defined (OPTION_FAMILY15H_OR)
- #define OPT_F15_OR_CPU
- #define OPT_F15_OR_ID
-#endif // defined (OPTION_FAMILY15H_OR)
-
-/*
- * Install unknown family 15h support
- */
-
-
-#if USES_REGISTER_TABLES == TRUE
- CONST REGISTER_TABLE ROMDATA *F15UnknownRegisterTables[] =
- {
- #if BASE_FAMILY_PCI == TRUE
- &F15PciRegisterTable,
- #endif
- #if BASE_FAMILY_MSR == TRUE
- &F15MsrRegisterTable,
- #endif
- #if BASE_FAMILY_HT_PCI == TRUE
- &F15HtPhyRegisterTable,
- #endif
- #if OPTION_MULTISOCKET == TRUE
- #if MODEL_SPECIFIC_PCI == TRUE
- &F15MultiLinkPciRegisterTable,
- #endif
- #endif
- #if OPTION_MULTISOCKET == FALSE
- #if MODEL_SPECIFIC_PCI == TRUE
- &F15SingleLinkPciRegisterTable,
- #endif
- #endif
- #if BASE_FAMILY_WORKAROUNDS == TRUE
- &F15WorkaroundsTable,
- #endif
- // the end.
- NULL
- };
-#endif
-
-#if USES_REGISTER_TABLES == TRUE
- CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F15UnknownTableEntryTypeDescriptors[] =
- {
- {MsrRegister, SetRegisterForMsrEntry},
- {PciRegister, SetRegisterForPciEntry},
- {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
- {HtPhyRegister, SetRegisterForHtPhyEntry},
- {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
- {DeemphasisRegister, SetRegisterForDeemphasisEntry},
- {ProfileFixup, SetRegisterForPerformanceProfileEntry},
- {HtHostPciRegister, SetRegisterForHtHostEntry},
- {HtHostPerfPciRegister, SetRegisterForHtHostPerfEntry},
- {HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid},
- {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
- {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
- {CompUnitCountsPciRegister, SetRegisterForComputeUnitCountsEntry},
- {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
- // End
- {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
- };
-#endif
-
-
-CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF15UnknownServices =
-{
- 0,
- #if DISABLE_PSTATE == TRUE
- F15DisablePstate,
- #else
- (PF_CPU_DISABLE_PSTATE) CommonAssert,
- #endif
- #if TRANSITION_PSTATE == TRUE
- F15TransitionPstate,
- #else
- (PF_CPU_TRANSITION_PSTATE) CommonAssert,
- #endif
- #if PROC_IDD_MAX == TRUE
- (PF_CPU_GET_IDD_MAX) CommonReturnFalse,
- #else
- (PF_CPU_GET_IDD_MAX) CommonAssert,
- #endif
- #if GET_TSC_RATE == TRUE
- F15GetTscRate,
- #else
- (PF_CPU_GET_TSC_RATE) CommonAssert,
- #endif
- #if GET_NB_FREQ == TRUE
- F15GetCurrentNbFrequency,
- #else
- (PF_CPU_GET_NB_FREQ) CommonAssert,
- #endif
- #if GET_NB_FREQ == TRUE
- F15GetNbPstateInfo,
- #else
- (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
- #endif
- #if IS_NBCOF_INIT_NEEDED == TRUE
- (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonReturnFalse,
- #else
- (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
- #endif
- #if AP_INITIAL_LAUNCH == TRUE
- F15LaunchApCore,
- #else
- (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
- #endif
- #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
- (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonVoid,
- #else
- (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
- #endif
- #if GET_AP_MAILBOX_FROM_HW == TRUE
- F15GetApMailboxFromHardware,
- #else
- (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
- #endif
- #if SET_AP_CORE_NUMBER == TRUE
- F15SetApCoreNumber,
- #else
- (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
- #endif
- #if GET_AP_CORE_NUMBER == TRUE
- F15GetApCoreNumber,
- #else
- (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
- #endif
- #if TRANSFER_AP_CORE_NUMBER == TRUE
- F15TransferApCoreNumber,
- #else
- (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
- #endif
- #if ID_POSITION_INITIAL_APICID == TRUE
- F15CpuAmdCoreIdPositionInInitialApicId,
- #else
- (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
- #endif
- #if SAVE_FEATURES == TRUE
- // F15SaveFeatures,
- (PF_CPU_SAVE_FEATURES) CommonVoid,
- #else
- (PF_CPU_SAVE_FEATURES) CommonAssert,
- #endif
- #if WRITE_FEATURES == TRUE
- // F15WriteFeatures,
- (PF_CPU_WRITE_FEATURES) CommonVoid,
- #else
- (PF_CPU_WRITE_FEATURES) CommonAssert,
- #endif
- #if SET_WARM_RESET_FLAG == TRUE
- F15SetAgesaWarmResetFlag,
- #else
- (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
- #endif
- #if GET_WARM_RESET_FLAG == TRUE
- F15GetAgesaWarmResetFlag,
- #else
- (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
- #endif
- #if BRAND_STRING1 == TRUE
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if BRAND_STRING2 == TRUE
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_PATCHES == TRUE
- GetEmptyArray,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
- GetEmptyArray,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_CACHE_INFO == TRUE
- GetF15CacheInfo,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_SYSTEM_PM_TABLE == TRUE
- GetF15SysPmTable,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_WHEA_INIT == TRUE
- GetF15WheaInitData,
- #else
- (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
- #endif
- #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
- F15GetPlatformTypeSpecificInfo,
- #else
- (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
- #endif
- #if IS_NB_PSTATE_ENABLED == TRUE
- F15IsNbPstateEnabled,
- #else
- (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
- #endif
- #if (BASE_FAMILY_HT_PCI == TRUE)
- F15NextLinkHasHtPhyFeats,
- #else
- (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
- #endif
- #if (BASE_FAMILY_HT_PCI == TRUE)
- F15SetHtPhyRegister,
- #else
- (PF_SET_HT_PHY_REGISTER) CommonVoid,
- #endif
- #if BASE_FAMILY_PCI == TRUE
- F15GetNextHtLinkFeatures,
- #else
- (PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert,
- #endif
- #if USES_REGISTER_TABLES == TRUE
- (REGISTER_TABLE **) F15UnknownRegisterTables,
- #else
- NULL,
- #endif
- #if USES_REGISTER_TABLES == TRUE
- (TABLE_ENTRY_TYPE_DESCRIPTOR *) F15UnknownTableEntryTypeDescriptors,
- #else
- NULL,
- #endif
- NULL,
- NULL,
- InitCacheEnabled,
- #if AGESA_ENTRY_INIT_EARLY == TRUE
- GetF15EarlyInitOnCoreTable
- #else
- (PF_GET_EARLY_INIT_TABLE) CommonVoid
- #endif
-};
-
-// Family 15h maximum base address is 48 bits. Limit BLDCFG to 48 bits, if appropriate.
-#if (FAMILY_MMIO_BASE_MASK < 0xFFFF000000000000ull)
- #undef FAMILY_MMIO_BASE_MASK
- #define FAMILY_MMIO_BASE_MASK (0xFFFF000000000000ull)
-#endif
-
-
-#undef OPT_F15_ID_TABLE
-#define OPT_F15_ID_TABLE {0x15, {AMD_FAMILY_15, AMD_F15_UNKNOWN}, F15LogicalIdTable, (sizeof (F15LogicalIdTable) / sizeof (F15LogicalIdTable[0]))},
-#define OPT_F15_UNKNOWN_CPU {AMD_FAMILY_15, &cpuF15UnknownServices},
-
-#undef OPT_F15_TABLE
-#define OPT_F15_TABLE OPT_F15_OR_CPU OPT_F15_UNKNOWN_CPU
-
-
-#if OPTION_G34_SOCKET_SUPPORT == TRUE
- #define F15_G34_BRANDSTRING1 NULL,
- #define F15_G34_BRANDSTRING2 NULL,
-#else
- #define F15_G34_BRANDSTRING1
- #define F15_G34_BRANDSTRING2
-#endif
-#if OPTION_C32_SOCKET_SUPPORT == TRUE
- #define F15_C32_BRANDSTRING1 NULL,
- #define F15_C32_BRANDSTRING2 NULL,
-#else
- #define F15_C32_BRANDSTRING1
- #define F15_C32_BRANDSTRING2
-#endif
-#if OPTION_AM3_SOCKET_SUPPORT == TRUE
- #define F15_AM3_BRANDSTRING1 NULL,
- #define F15_AM3_BRANDSTRING2 NULL,
-#else
- #define F15_AM3_BRANDSTRING1
- #define F15_AM3_BRANDSTRING2
-#endif
-
-#if BRAND_STRING1 == TRUE
- CONST CPU_BRAND_TABLE ROMDATA *F15BrandIdString1Tables[] =
- {
- F15_G34_BRANDSTRING1
- F15_C32_BRANDSTRING1
- F15_AM3_BRANDSTRING1
- };
-
- CONST UINT8 F15BrandIdString1TableCount = (sizeof (F15BrandIdString1Tables) / sizeof (F15BrandIdString1Tables[0]));
-#endif
-
-#if BRAND_STRING2 == TRUE
- CONST CPU_BRAND_TABLE ROMDATA *F15BrandIdString2Tables[] =
- {
- F15_G34_BRANDSTRING2
- F15_C32_BRANDSTRING2
- F15_AM3_BRANDSTRING2
- };
-
- CONST UINT8 F15BrandIdString2TableCount = (sizeof (F15BrandIdString2Tables) / sizeof (F15BrandIdString2Tables[0]));
-#endif
-
-CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY ROMDATA F15LogicalIdTable[] =
-{
- OPT_F15_OR_ID
-};
-
-#endif // _OPTION_FAMILY_15H_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionGfxRecovery.h b/src/vendorcode/amd/agesa/Include/OptionGfxRecovery.h
deleted file mode 100644
index e7d921e..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionGfxRecovery.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD GFX Recovery option API.
- *
- * Contains structures and values used to control the GfxRecovery option code.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: OPTION
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_GFX_RECOVERY_H_
-#define _OPTION_GFX_RECOVERY_H_
-
-/*----------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *----------------------------------------------------------------------------------------
- */
-
-typedef AGESA_STATUS OPTION_GFX_RECOVERY_FEATURE (
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-#define GFX_RECOVERY_STRUCT_VERSION 0x01
-
-/// The Option Configuration of GFX Recovery
-typedef struct {
- UINT16 OptGfxRecoveryVersion; ///< The version number of GFX Recovery
- OPTION_GFX_RECOVERY_FEATURE *GfxRecoveryFeature; ///< The Option Feature of GFX Recovery
-} OPTION_GFX_RECOVERY_CONFIGURATION;
-
-/*----------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *----------------------------------------------------------------------------------------
- */
-
-
-#endif // _OPTION_GFX_RECOVERY_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionGfxRecoveryInstall.h b/src/vendorcode/amd/agesa/Include/OptionGfxRecoveryInstall.h
deleted file mode 100644
index d271cd0..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionGfxRecoveryInstall.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: GfxRecovery
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Options
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_GFX_RECOVERY_INSTALL_H_
-#define _OPTION_GFX_RECOVERY_INSTALL_H_
-
-/* This option is designed to be included into the platform solution install
- * file. The platform solution install file will define the options status.
- * Check to validate the definition
- */
-
-
-#endif // _OPTION_GFX_RECOVERY_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionGnb.h b/src/vendorcode/amd/agesa/Include/OptionGnb.h
deleted file mode 100644
index 5f3fbd6..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionGnb.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD ALIB option API.
- *
- * Contains structures and values used to control the ALIB option code.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: OPTION
- * @e \$Revision: 40151 $ @e \$Date: 2010-10-20 06:38:17 +0800 (Wed, 20 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_GNB_H_
-#define _OPTION_GNB_H_
-
-/*----------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *----------------------------------------------------------------------------------------
- */
-
-
-typedef AGESA_STATUS OPTION_GNB_FEATURE (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// The Option Configuration of ALIB
-typedef struct {
- UINT64 Type; ///< Type
- OPTION_GNB_FEATURE *GnbFeature; ///< The GNB Feature
-} OPTION_GNB_CONFIGURATION;
-
-/// The Build time options configuration
-typedef struct {
- BOOLEAN IgfxModeAsPcieEp; ///< Itegrated Gfx mode Pcie EP or Legacy
- BOOLEAN LclkDeepSleepEn; ///< Default for LCLK deep sleep
- BOOLEAN LclkDpmEn; ///< Default for LCLK DPM
- BOOLEAN GmcPowerGateStutterOnly; ///< Force GMC power gate to stutter only
- BOOLEAN SmuSclkClockGatingEnable;///< Control SMU SCLK gating
- BOOLEAN PcieAspmBlackListEnable; ///< Control Pcie Aspm Black List
-} GNB_BUILD_OPTIONS;
-
-/*----------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *----------------------------------------------------------------------------------------
- */
-
-#endif // _OPTION_GNB_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionGnbInstall.h b/src/vendorcode/amd/agesa/Include/OptionGnbInstall.h
deleted file mode 100644
index d8acee7..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionGnbInstall.h
+++ /dev/null
@@ -1,449 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: GNB
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Options
- * @e \$Revision: 40151 $ @e \$Date: 2010-10-20 06:38:17 +0800 (Wed, 20 Oct 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_GNB_INSTALL_H_
-#define _OPTION_GNB_INSTALL_H_
-
-#include "S3SaveState.h"
-/* This option is designed to be included into the platform solution install
- * file. The platform solution install file will define the options status.
- * Check to validate the definition
- */
-
-#define GNB_TYPE_LN OPTION_FAMILY12H
-#define GNB_TYPE_ON OPTION_FAMILY14H
-#define GNB_TYPE_KR FALSE
-#define GNB_TYPE_TN FALSE
-
-#ifndef CFG_IGFX_AS_PCIE_EP
- #define CFG_IGFX_AS_PCIE_EP TRUE
-#endif
-
-#ifndef CFG_LCLK_DEEP_SLEEP_EN
- #if (GNB_TYPE_ON == TRUE)
- #define CFG_LCLK_DEEP_SLEEP_EN TRUE
- #else
- #define CFG_LCLK_DEEP_SLEEP_EN FALSE
- #endif
-#endif
-
-#ifndef CFG_LCLK_DPM_EN
- #if (GNB_TYPE_ON == TRUE)
- #define CFG_LCLK_DPM_EN TRUE
- #else
- #define CFG_LCLK_DPM_EN FALSE
- #endif
-#endif
-
-#ifndef CFG_GMC_POWER_GATE_STUTTER_ONLY
- #define CFG_GMC_POWER_GATE_STUTTER_ONLY FALSE
-#endif
-
-#ifndef CFG_SMU_SCLK_CLOCK_GATING_ENABLE
- #if (GNB_TYPE_ON == TRUE)
- #define CFG_SMU_SCLK_CLOCK_GATING_ENABLE TRUE
- #else
- #define CFG_SMU_SCLK_CLOCK_GATING_ENABLE FALSE
- #endif
-#endif
-
-#ifndef CFG_PCIE_ASPM_BLACK_LIST_ENABLE
- #define CFG_PCIE_ASPM_BLACK_LIST_ENABLE TRUE
-#endif
-
-GNB_BUILD_OPTIONS GnbBuildOptions = {
- CFG_IGFX_AS_PCIE_EP,
- CFG_LCLK_DEEP_SLEEP_EN,
- CFG_LCLK_DPM_EN,
- CFG_GMC_POWER_GATE_STUTTER_ONLY,
- CFG_SMU_SCLK_CLOCK_GATING_ENABLE,
- CFG_PCIE_ASPM_BLACK_LIST_ENABLE
-};
-
-
-
-#if (AGESA_ENTRY_INIT_EARLY == TRUE)
-//---------------------------------------------------------------------------------------------------
- #ifndef OPTION_NB_EARLY_INIT
- #define OPTION_NB_EARLY_INIT TRUE
- #endif
- #if (OPTION_NB_EARLY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
- OPTION_GNB_FEATURE NbInitAtEarly;
- #define OPTION_NBINITATEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtEarly},
- #else
- #define OPTION_NBINITATEARLY_ENTRY
- #endif
-//---------------------------------------------------------------------------------------------------
-// SMU init
- #ifndef OPTION_SMU
- #define OPTION_SMU TRUE
- #endif
- #if (OPTION_SMU == TRUE) && (GNB_TYPE_LN == TRUE)
- OPTION_GNB_FEATURE F12NbSmuInitFeature;
- #define OPTION_F12NBSMUINITFEATURE_ENTRY {AMD_FAMILY_LN, F12NbSmuInitFeature},
- #else
- #define OPTION_F12NBSMUINITFEATURE_ENTRY
- #endif
- #if (OPTION_SMU == TRUE) && (GNB_TYPE_ON == TRUE)
- OPTION_GNB_FEATURE F14NbSmuInitFeature;
- #define OPTION_F14NBSMUINITFEATURE_ENTRY {AMD_FAMILY_ON, F14NbSmuInitFeature},
- #else
- #define OPTION_F14NBSMUINITFEATURE_ENTRY
- #endif
- #if (OPTION_SMU == TRUE) && (GNB_TYPE_KR == TRUE)
- OPTION_GNB_FEATURE KRNbSmuInitFeature;
- #define OPTION_KRNBSMUINITFEATURE_ENTRY {AMD_FAMILY_KR, KRNbSmuInitFeature},
- #else
- #define OPTION_KRNBSMUINITFEATURE_ENTRY
- #endif
-//---------------------------------------------------------------------------------------------------
- #ifndef OPTION_PCIE_CONFIG_INIT
- #define OPTION_PCIE_CONFIG_INIT TRUE
- #endif
- #if (OPTION_PCIE_CONFIG_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
- OPTION_GNB_FEATURE PcieConfigurationInit;
- #define OPTION_PCIECONFIGURATIONINIT_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieConfigurationInit},
- #else
- #define OPTION_PCIECONFIGURATIONINIT_ENTRY
- #endif
-//---------------------------------------------------------------------------------------------------
- #ifndef OPTION_PCIE_EARLY_INIT
- #define OPTION_PCIE_EARLY_INIT TRUE
- #endif
- #if (OPTION_PCIE_EARLY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
- OPTION_GNB_FEATURE PcieInitAtEarly;
- #define OPTION_PCIEINITATEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtEarly},
- #else
- #define OPTION_PCIEINITATEARLY_ENTRY
- #endif
-//---------------------------------------------------------------------------------------------------
- OPTION_GNB_CONFIGURATION GnbEarlyFeatureTable[] = {
- OPTION_NBINITATEARLY_ENTRY
- OPTION_F12NBSMUINITFEATURE_ENTRY
- OPTION_F14NBSMUINITFEATURE_ENTRY
- OPTION_KRNBSMUINITFEATURE_ENTRY
- OPTION_PCIECONFIGURATIONINIT_ENTRY
- OPTION_PCIEINITATEARLY_ENTRY
- {0, NULL}
- };
-
-#endif
-
-#if (AGESA_ENTRY_INIT_POST == TRUE)
-//---------------------------------------------------------------------------------------------------
- #ifndef OPTION_GFX_CONFIG_POST_INIT
- #define OPTION_GFX_CONFIG_POST_INIT TRUE
- #endif
- #if (OPTION_GFX_CONFIG_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
- OPTION_GNB_FEATURE GfxConfigPostInterface;
- #define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxConfigPostInterface},
- #else
- #define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY
- #endif
-//---------------------------------------------------------------------------------------------------
- #ifndef OPTION_GFX_POST_INIT
- #define OPTION_GFX_POST_INIT TRUE
- #endif
- #if (OPTION_GFX_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
- OPTION_GNB_FEATURE GfxInitAtPost;
- #define OPTION_GFXINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtPost},
- #else
- #define OPTION_GFXINITATPOST_ENTRY
- #endif
-//---------------------------------------------------------------------------------------------------
- #ifndef OPTION_NB_POST_INIT
- #define OPTION_NB_POST_INIT TRUE
- #endif
- #if (OPTION_NB_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
- OPTION_GNB_FEATURE NbInitAtPost;
- #define OPTION_NBINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtPost},
- #else
- #define OPTION_NBINITATPOST_ENTRY
- #endif
-//---------------------------------------------------------------------------------------------------
- #ifndef OPTION_PCIE_POST_INIT
- #define OPTION_PCIE_POST_INIT TRUE
- #endif
- #if (OPTION_PCIE_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
- OPTION_GNB_FEATURE PcieInitAtPost;
- #define OPTION_PCIEINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtPost},
- #else
- #define OPTION_PCIEINITATPOST_ENTRY
- #endif
-//---------------------------------------------------------------------------------------------------
- OPTION_GNB_CONFIGURATION GnbPostFeatureTable[] = {
- OPTION_GFXCONFIGPOSTINTERFACE_ENTRY
- OPTION_GFXINITATPOST_ENTRY
- {0, NULL}
- };
-
- OPTION_GNB_CONFIGURATION GnbPostAfterDramFeatureTable[] = {
- OPTION_NBINITATPOST_ENTRY
- OPTION_PCIEINITATPOST_ENTRY
- {0, NULL}
- };
-#endif
-
-#if (AGESA_ENTRY_INIT_ENV == TRUE)
-//---------------------------------------------------------------------------------------------------
- #ifndef OPTION_FUSE_TABLE_INIT
- #define OPTION_FUSE_TABLE_INIT TRUE
- #endif
- #if (OPTION_FUSE_TABLE_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
- OPTION_GNB_FEATURE NbFuseTableFeature;
- #define OPTION_NBFUSETABLEFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbFuseTableFeature},
- #else
- #define OPTION_NBFUSETABLEFEATURE_ENTRY
- #endif
-//---------------------------------------------------------------------------------------------------
- #ifndef OPTION_NB_ENV_INIT
- #define OPTION_NB_ENV_INIT TRUE
- #endif
- #if (OPTION_NB_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
- OPTION_GNB_FEATURE NbInitAtEnv;
- #define OPTION_NBINITATENVT_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtEnv},
- #else
- #define OPTION_NBINITATENVT_ENTRY
- #endif
-//---------------------------------------------------------------------------------------------------
- #ifndef OPTION_GFX_CONFIG_ENV_INIT
- #define OPTION_GFX_CONFIG_ENV_INIT TRUE
- #endif
- #if (OPTION_GFX_CONFIG_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
- OPTION_GNB_FEATURE GfxConfigEnvInterface;
- #define OPTION_GFXCONFIGENVINTERFACE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxConfigEnvInterface},
- #else
- #define OPTION_GFXCONFIGENVINTERFACE_ENTRY
- #endif
-
-//---------------------------------------------------------------------------------------------------
- #ifndef OPTION_GFX_ENV_INIT
- #define OPTION_GFX_ENV_INIT TRUE
- #endif
- #if (OPTION_GFX_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
- OPTION_GNB_FEATURE GfxInitAtEnvPost;
- #define OPTION_GFXINITATENVPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtEnvPost},
- #else
- #define OPTION_GFXINITATENVPOST_ENTRY
- #endif
-//---------------------------------------------------------------------------------------------------
- #ifndef OPTION_POWER_GATE
- #define OPTION_POWER_GATE TRUE
- #endif
- #if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_LN == TRUE)
- OPTION_GNB_FEATURE F12NbPowerGateFeature;
- #define OPTION_F12NBPOWERGATEFEATURE_ENTRY {AMD_FAMILY_LN, F12NbPowerGateFeature},
- #else
- #define OPTION_F12NBPOWERGATEFEATURE_ENTRY
- #endif
- #if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_ON == TRUE)
- OPTION_GNB_FEATURE F14NbPowerGateFeature;
- #define OPTION_F14NBPOWERGATEFEATURE_ENTRY {AMD_FAMILY_ON, F14NbPowerGateFeature},
- #else
- #define OPTION_F14NBPOWERGATEFEATURE_ENTRY
- #endif
- #if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_KR == TRUE)
- OPTION_GNB_FEATURE KRNbPowerGateFeature;
- #define OPTION_KRNBPOWERGATEFEATURE_ENTRY {AMD_FAMILY_KR, KRNbPowerGateFeature},
- #else
- #define OPTION_KRNBPOWERGATEFEATURE_ENTRY
- #endif
-//---------------------------------------------------------------------------------------------------
- #ifndef OPTION_PCIE_ENV_INIT
- #define OPTION_PCIE_ENV_INIT TRUE
- #endif
- #if (OPTION_PCIE_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
- OPTION_GNB_FEATURE PcieInitAtEnv;
- #define OPTION_PCIEINITATENV_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtEnv},
- #else
- #define OPTION_PCIEINITATENV_ENTRY
- #endif
-//---------------------------------------------------------------------------------------------------
-
- OPTION_GNB_CONFIGURATION GnbEnvFeatureTable[] = {
- OPTION_NBFUSETABLEFEATURE_ENTRY
- OPTION_NBINITATENVT_ENTRY
- OPTION_PCIEINITATENV_ENTRY
- OPTION_GFXCONFIGENVINTERFACE_ENTRY
- OPTION_GFXINITATENVPOST_ENTRY
- OPTION_F12NBPOWERGATEFEATURE_ENTRY
- OPTION_F14NBPOWERGATEFEATURE_ENTRY
- OPTION_KRNBPOWERGATEFEATURE_ENTRY
- {0, NULL}
- };
-#endif
-
-#if (AGESA_ENTRY_INIT_MID == TRUE)
-//---------------------------------------------------------------------------------------------------
- #ifndef OPTOIN_GNB_CABLESAFE
- #define OPTOIN_GNB_CABLESAFE TRUE
- #endif
- #if (OPTOIN_GNB_CABLESAFE == TRUE) && (GNB_TYPE_LN == TRUE)
- OPTION_GNB_FEATURE GnbCableSafeEntry;
- #define OPTION_GNBCABLESAFEENTRY_ENTRY {AMD_FAMILY_LN, GnbCableSafeEntry},
- #else
- #define OPTION_GNBCABLESAFEENTRY_ENTRY
- #endif
-//---------------------------------------------------------------------------------------------------
- #ifndef OPTOIN_NB_LCLK_NCLK_RATIO
- #define OPTOIN_NB_LCLK_NCLK_RATIO TRUE
- #endif
- #if (OPTOIN_NB_LCLK_NCLK_RATIO == TRUE) && (GNB_TYPE_ON == TRUE)
- OPTION_GNB_FEATURE F14NbLclkNclkRatioFeature;
- #define OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY {AMD_FAMILY_ON, F14NbLclkNclkRatioFeature},
- #else
- #define OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY
- #endif
- #if (OPTOIN_NB_LCLK_NCLK_RATIO == TRUE) && (GNB_TYPE_KR == TRUE)
- OPTION_GNB_FEATURE KRNbLclkNclkRatioFeature;
- #define OPTION_KRNBLCLKNCLKRATIOFEATURE_ENTRY {AMD_FAMILY_KR, KRNbLclkNclkRatioFeature},
- #else
- #define OPTION_KRNBLCLKNCLKRATIOFEATURE_ENTRY
- #endif
-//---------------------------------------------------------------------------------------------------
- #ifndef OPTION_NB_LCLK_DPM_INIT
- #define OPTION_NB_LCLK_DPM_INIT TRUE
- #endif
- #if (OPTION_NB_LCLK_DPM_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
- OPTION_GNB_FEATURE NbLclkDpmFeature;
- #define OPTION_NBLCLKDPMFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbLclkDpmFeature},
- #else
- #define OPTION_NBLCLKDPMFEATURE_ENTRY
- #endif
-//---------------------------------------------------------------------------------------------------
- #ifndef OPTION_PCIE_POWER_GATE
- #define OPTION_PCIE_POWER_GATE TRUE
- #endif
- #if (OPTION_PCIE_POWER_GATE == TRUE) && (GNB_TYPE_LN == TRUE)
- OPTION_GNB_FEATURE PciePowerGateFeature;
- #define OPTION_PCIEPOWERGATEFEATURE_ENTRY {AMD_FAMILY_LN, PciePowerGateFeature},
- #else
- #define OPTION_PCIEPOWERGATEFEATURE_ENTRY
- #endif
-//---------------------------------------------------------------------------------------------------
- #ifndef OPTION_GFX_MID_INIT
- #define OPTION_GFX_MID_INIT TRUE
- #endif
- #if (OPTION_GFX_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
- OPTION_GNB_FEATURE GfxInitAtMidPost;
- #define OPTION_GFXINITATMIDPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtMidPost},
- #else
- #define OPTION_GFXINITATMIDPOST_ENTRY
- #endif
-//---------------------------------------------------------------------------------------------------
- #ifndef OPTION_GFX_INTEGRATED_TABLE_INIT
- #define OPTION_GFX_INTEGRATED_TABLE_INIT TRUE
- #endif
- #if (OPTION_GFX_INTEGRATED_TABLE_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
- OPTION_GNB_FEATURE GfxIntegratedInfoTableEntry;
- #define OPTION_GFXINTEGRATEDINFOTABLE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxIntegratedInfoTableEntry},
- #else
- #define OPTION_GFXINTEGRATEDINFOTABLE_ENTRY
- #endif
-//---------------------------------------------------------------------------------------------------
- #ifndef OPTION_PCIe_MID_INIT
- #define OPTION_PCIe_MID_INIT TRUE
- #endif
- #if (OPTION_PCIe_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
- OPTION_GNB_FEATURE PcieInitAtMid;
- #define OPTION_PCIEINITATMID_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtMid},
- #else
- #define OPTION_PCIEINITATMID_ENTRY
- #endif
-//---------------------------------------------------------------------------------------------------
- #ifndef OPTION_NB_MID_INIT
- #define OPTION_NB_MID_INIT TRUE
- #endif
- #if (OPTION_NB_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
- OPTION_GNB_FEATURE NbInitAtLatePost;
- #define OPTION_NBINITATLATEPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtLatePost},
- #else
- #define OPTION_NBINITATLATEPOST_ENTRY
- #endif
-//---------------------------------------------------------------------------------------------------
- OPTION_GNB_CONFIGURATION GnbMidFeatureTable[] = {
- OPTION_GFXINITATMIDPOST_ENTRY
- OPTION_GFXINTEGRATEDINFOTABLE_ENTRY
- OPTION_GNBCABLESAFEENTRY_ENTRY
- OPTION_PCIEINITATMID_ENTRY
- OPTION_NBINITATLATEPOST_ENTRY
- OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY
- OPTION_KRNBLCLKNCLKRATIOFEATURE_ENTRY
- OPTION_NBLCLKDPMFEATURE_ENTRY
- OPTION_PCIEPOWERGATEFEATURE_ENTRY
- {0, NULL}
- };
-#endif
-
-#if (AGESA_ENTRY_INIT_LATE == TRUE)
-//---------------------------------------------------------------------------------------------------
- #ifndef OPTION_ALIB
- #define OPTION_ALIB FALSE
- #endif
- #if (OPTION_ALIB == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
- OPTION_GNB_FEATURE PcieAlibFeature;
- #define OPTION_PCIEALIBFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieAlibFeature},
- #else
- #define OPTION_PCIEALIBFEATURE_ENTRY
- #endif
-//---------------------------------------------------------------------------------------------------
- OPTION_GNB_CONFIGURATION GnbLateFeatureTable[] = {
- OPTION_PCIEALIBFEATURE_ENTRY
- {0, NULL}
- };
-#endif
-
-#if (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
- S3_DISPATCH_FUNCTION NbSmuServiceRequestS3Script;
- S3_DISPATCH_FUNCTION PcieLateRestoreS3Script;
- S3_DISPATCH_FUNCTION NbSmuIndirectWriteS3Script;
- #define GNB_S3_DISPATCH_FUNCTION_TABLE \
- {S3DispatchGnbSmuIndirectWrite, NbSmuIndirectWriteS3Script}, \
- {S3DispatchGnbSmuServiceRequest, NbSmuServiceRequestS3Script}, \
- {S3DispatchGnbPcieLateRestore, PcieLateRestoreS3Script},
-#endif
-
-#endif // _OPTION_GNB_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionHtAssistInstall.h b/src/vendorcode/amd/agesa/Include/OptionHtAssistInstall.h
deleted file mode 100644
index 171e9ea..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionHtAssistInstall.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: HT Assist
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Options
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_HT_ASSIST_INSTALL_H_
-#define _OPTION_HT_ASSIST_INSTALL_H_
-
-#include "cpuHtAssist.h"
-
-/* This option is designed to be included into the platform solution install
- * file. The platform solution install file will define the options status.
- * Check to validate the definition
- */
-#define OPTION_HT_ASSIST_FEAT
-#define F10_HT_ASSIST_SUPPORT
-#define F15_HT_ASSIST_SUPPORT
-#define HT_ASSIST_AP_DISABLE_CACHE
-#define HT_ASSIST_AP_ENABLE_CACHE
-
-#if (OPTION_HT_ASSIST == TRUE || OPTION_ATM_MODE == TRUE)
- #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)
- #ifdef OPTION_FAMILY10H
- #if OPTION_FAMILY10H == TRUE
- #if OPTION_FAMILY10H_HY == TRUE
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHtAssist;
- #undef OPTION_HT_ASSIST_FEAT
- #define OPTION_HT_ASSIST_FEAT &CpuFeatureHtAssist,
- extern CONST HT_ASSIST_FAMILY_SERVICES ROMDATA F10HtAssist;
- #undef F10_HT_ASSIST_SUPPORT
- #define F10_HT_ASSIST_SUPPORT {AMD_FAMILY_10_HY, &F10HtAssist},
- #endif
- #endif
- #endif
-
- #ifdef OPTION_FAMILY15H
- #if OPTION_FAMILY15H == TRUE
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHtAssist;
- #undef OPTION_HT_ASSIST_FEAT
- #define OPTION_HT_ASSIST_FEAT &CpuFeatureHtAssist,
- extern CONST HT_ASSIST_FAMILY_SERVICES ROMDATA F15HtAssist;
- #undef F15_HT_ASSIST_SUPPORT
- #define F15_HT_ASSIST_SUPPORT {AMD_FAMILY_15, &F15HtAssist},
- #endif
- #endif
-
- CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA HtAssistFamilyServiceArray[] =
- {
- F10_HT_ASSIST_SUPPORT
- F15_HT_ASSIST_SUPPORT
- {0, NULL}
- };
- CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA HtAssistFamilyServiceTable =
- {
- (sizeof (HtAssistFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
- &HtAssistFamilyServiceArray[0]
- };
-
- #undef AGESA_ENTRY_LATE_RUN_AP_TASK
- #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE
- #undef HT_ASSIST_AP_DISABLE_CACHE
- #define HT_ASSIST_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches},
- #undef HT_ASSIST_AP_ENABLE_CACHE
- #define HT_ASSIST_AP_ENABLE_CACHE {AP_LATE_TASK_ENABLE_CACHE, (IMAGE_ENTRY) EnableAllCaches},
- #endif
-#endif
-
-#endif // _OPTION_HT_ASSIST_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionHtInstall.h b/src/vendorcode/amd/agesa/Include/OptionHtInstall.h
deleted file mode 100644
index 637f069..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionHtInstall.h
+++ /dev/null
@@ -1,301 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: Ht
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Options
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_HT_INSTALL_H_
-#define _OPTION_HT_INSTALL_H_
-
-#include "Topology.h"
-#include "htFeat.h"
-#include "htInterface.h"
-#include "htNb.h"
-#include "htTopologies.h"
-/*
- * Advanced Option only, hardware socket naming is the preferred method.
- */
-#ifdef BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP
- #define CFG_SYSTEM_PHYSICAL_SOCKET_MAP (BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP)
-#else
- #define CFG_SYSTEM_PHYSICAL_SOCKET_MAP (NULL)
-#endif
-
-/*
- * OPTION_IS_RECOVERY_HT is true if Basic API is being used.
- */
-#ifndef OPTION_IS_RECOVERY_HT
- #define OPTION_IS_RECOVERY_HT TRUE
-#endif
-
-/* This option is designed to be included into the platform solution install
- * file. The platform solution install file will define the options status.
- * Check to validate the definition.
- */
-
-#ifndef OPTION_MULTISOCKET
- #error BLDOPT: Option not defined: "OPTION_MULTISOCKET"
-#endif
-
-/*
- * Based on user level options, set Ht internal options.
- * For now, Family 10h support will assume single module. For multi module,
- * this will have to be changed to not set non-coherent only.
- */
-#define OPTION_HT_NON_COHERENT_ONLY FALSE
-
-#if ((OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE) || (OPTION_FAMILY16H == TRUE))
-/* Fusion Families do not need a non-coherent only option. */
-#else
- // Process Family 10h and 15h by socket, applying the MultiSocket option where it is allowable.
- #if OPTION_G34_SOCKET_SUPPORT == FALSE
- // Hydra has coherent support, other Family 10h should follow MultiSocket support.
- #if OPTION_MULTISOCKET == FALSE
- #undef OPTION_HT_NON_COHERENT_ONLY
- #define OPTION_HT_NON_COHERENT_ONLY TRUE
- #endif
- #endif
-#endif
-
-/*
- * Macros will generate the correct item reference based on options
- */
-#if AGESA_ENTRY_INIT_EARLY == TRUE
- // Select the interface and features
- #if ((OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE) || (OPTION_FAMILY16H == TRUE))
- #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
- #define INTERNAL_HT_OPTION_FEATURES &HtFeaturesNone
- #define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceMapsOnly
- #else
- // Family 10h and 15h
- #if OPTION_HT_NON_COHERENT_ONLY == FALSE
- #define INTERNAL_HT_OPTION_FEATURES &HtFeaturesDefault
- #define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceDefault
- #else
- #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
- #define INTERNAL_HT_OPTION_FEATURES &HtFeaturesNonCoherentOnly
- #define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceNonCoherentOnly
- #endif
- #endif
- // Select Northbridge components
- #if OPTION_FAMILY10H == TRUE
- #if OPTION_HT_NON_COHERENT_ONLY == TRUE
- #define INTERNAL_HT_OPTION_FAM10_NB &HtFam10NbNonCoherentOnly, &HtFam10RevDNbNonCoherentOnly,
- #else
- #define INTERNAL_HT_OPTION_FAM10_NB &HtFam10NbDefault, &HtFam10RevDNbDefault,
- #endif
- #else
- #define INTERNAL_HT_OPTION_FAM10_NB
- #endif
- #if OPTION_FAMILY12H == TRUE
- #define INTERNAL_HT_OPTION_FAM12_NB &HtFam12Nb,
- #else
- #define INTERNAL_HT_OPTION_FAM12_NB
- #endif
- #if OPTION_FAMILY14H == TRUE
- #define INTERNAL_HT_OPTION_FAM14_NB &HtFam14Nb,
- #else
- #define INTERNAL_HT_OPTION_FAM14_NB
- #endif
- #if OPTION_FAMILY15H == TRUE
- #if OPTION_HT_NON_COHERENT_ONLY == TRUE
- #define INTERNAL_HT_OPTION_FAM15_NB &HtFam15NbNonCoherentOnly,
- #else
- #define INTERNAL_HT_OPTION_FAM15_NB &HtFam15NbDefault,
- #endif
- #else
- #define INTERNAL_HT_OPTION_FAM15_NB
- #endif
-
- #define INTERNAL_ONLY_NB_LIST_ITEM INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS,
- #ifndef INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS
- #undef INTERNAL_ONLY_NB_LIST_ITEM
- #define INTERNAL_ONLY_NB_LIST_ITEM
- #endif
-
- /* Install the correct set of northbridge implementations. Each item provides its own comma, the last item
- * is ok to have a comma because the final item (NULL) is added below.
- */
- #define INTERNAL_HT_OPTION_SUPPORTED_NBS \
- INTERNAL_ONLY_NB_LIST_ITEM \
- INTERNAL_HT_OPTION_FAM10_NB \
- INTERNAL_HT_OPTION_FAM15_NB \
- INTERNAL_HT_OPTION_FAM12_NB \
- INTERNAL_HT_OPTION_FAM14_NB
-
-#else
- // Not Init Early
- #define INTERNAL_HT_OPTION_FEATURES NULL
- #define INTERNAL_HT_OPTION_INTERFACE NULL
- #define INTERNAL_HT_OPTION_SUPPORTED_NBS NULL
- #define HT_OPTIONS_PLATFORM NULL
- #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
-#endif
-
-#ifdef AGESA_ENTRY_INIT_EARLY
- #if AGESA_ENTRY_INIT_EARLY == TRUE
-
- extern HT_FEATURES HtFeaturesDefault;
- extern HT_FEATURES HtFeaturesNonCoherentOnly;
- extern HT_FEATURES HtFeaturesNone;
- extern HT_INTERFACE HtInterfaceDefault;
- extern HT_INTERFACE HtInterfaceNonCoherentOnly;
- extern HT_INTERFACE HtInterfaceMapsOnly;
- extern HT_INTERFACE HtInterfaceNone;
- extern NORTHBRIDGE HtFam10NbDefault;
- extern NORTHBRIDGE HtFam10RevDNbDefault;
- extern NORTHBRIDGE HtFam10NbNonCoherentOnly;
- extern NORTHBRIDGE HtFam10RevDNbNonCoherentOnly;
- extern NORTHBRIDGE HtFam12Nb;
- extern NORTHBRIDGE HtFam14Nb;
- extern NORTHBRIDGE HtFam10NbNone;
- extern NORTHBRIDGE HtFam15NbDefault;
- extern NORTHBRIDGE HtFam15NbNonCoherentOnly;
-
- CONST VOID * CONST ROMDATA HtInstalledFamilyNorthbridgeList[] = {
- INTERNAL_HT_OPTION_SUPPORTED_NBS
- NULL
- };
-
- STATIC CONST AMD_HT_INTERFACE ROMDATA HtOptionsPlatform =
- {
- CFG_STARTING_BUSNUM, CFG_MAXIMUM_BUSNUM, CFG_ALLOCATED_BUSNUM,
- (MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST,
- (DEVICE_CAP_OVERRIDE *)CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST,
- (CPU_TO_CPU_PCB_LIMITS *)CFG_HTFABRIC_LIMITS_LIST,
- (IO_PCB_LIMITS *)CFG_HTCHAIN_LIMITS_LIST,
- (OVERRIDE_BUS_NUMBERS *)CFG_BUS_NUMBERS_LIST,
- (IGNORE_LINK *)CFG_IGNORE_LINK_LIST,
- (SKIP_REGANG *)CFG_LINK_SKIP_REGANG_LIST,
- (UINT8 **)CFG_ADDITIONAL_TOPOLOGIES_LIST,
- (SYSTEM_PHYSICAL_SOCKET_MAP *)CFG_SYSTEM_PHYSICAL_SOCKET_MAP
- };
- #ifndef HT_OPTIONS_PLATFORM
- #define HT_OPTIONS_PLATFORM &HtOptionsPlatform
- #endif
-
- /**
- * A list of all the supported topologies.
- *
- */
- #ifndef INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES
- CONST UINT8 *CONST ROMDATA AmdTopolist[] =
- {
- amdHtTopologySingleNode,
- amdHtTopologyDualNode,
- amdHtTopologyThreeLine,
- amdHtTopologyTriangle,
- amdHtTopologyFourLine,
- amdHtTopologyFourStar,
- amdHtTopologyFourDegenerate,
- amdHtTopologyFourSquare,
- amdHtTopologyFourKite,
- amdHtTopologyFourFully,
- amdHtTopologyFiveFully,
- amdHtTopologyFiveTwistedLadder,
- amdHtTopologySixFully,
- amdHtTopologySixDoubloonLower,
- amdHtTopologySixDoubloonUpper,
- amdHtTopologySixTwistedLadder,
- amdHtTopologySevenFully,
- amdHtTopologySevenTwistedLadder,
- amdHtTopologyEightFully,
- amdHtTopologyEightDoubloon,
- amdHtTopologyEightTwistedLadder,
- amdHtTopologyEightStraightLadder,
- amdHtTopologySixTwinTriangles,
- amdHtTopologyEightTwinFullyFourWays,
- NULL
- };
- #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES AmdTopolist
- #endif
-
- /**
- * Declare the instance of the Ht option configuration structure
- */
- CONST OPTION_HT_CONFIGURATION ROMDATA OptionHtConfiguration = {
- OPTION_IS_RECOVERY_HT,
- CFG_SET_HTCRC_SYNC_FLOOD,
- CFG_USE_UNIT_ID_CLUMPING,
- HT_OPTIONS_PLATFORM,
- INTERNAL_HT_OPTION_INTERFACE,
- INTERNAL_HT_OPTION_FEATURES,
- &HtInstalledFamilyNorthbridgeList,
- INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES
- };
-
- #endif
-#endif
-
-#ifndef OPTION_HT_INIIT_RESET_ENTRY
-
- #define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset
-
- #if (OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE)
- #undef OPTION_HT_INIIT_RESET_ENTRY
- #define OPTION_HT_INIIT_RESET_ENTRY NULL
- #endif
-
- #if ((OPTION_FAMILY10H == TRUE) || (OPTION_FAMILY15H == TRUE))
- #undef OPTION_HT_INIIT_RESET_ENTRY
- #define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset
- #endif
-
-#endif
-
-#ifdef AGESA_ENTRY_INIT_RESET
- #if AGESA_ENTRY_INIT_RESET == TRUE
-
- CONST AMD_HT_RESET_INTERFACE ROMDATA HtOptionResetDefaults = {
- (MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST,
- 0 // Unused by options
- };
-
- CONST OPTION_HT_INIT_RESET ROMDATA HtOptionInitReset = {
- OPTION_HT_INIIT_RESET_ENTRY
- };
- #endif
-
-#endif
-
-#endif // _OPTION_HT_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionHwC1eInstall.h b/src/vendorcode/amd/agesa/Include/OptionHwC1eInstall.h
deleted file mode 100644
index 745914f..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionHwC1eInstall.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: HW C1e
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Options
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_HW_C1E_INSTALL_H_
-#define _OPTION_HW_C1E_INSTALL_H_
-
-#include "cpuHwC1e.h"
-
-/* This option is designed to be included into the platform solution install
- * file. The platform solution install file will define the options status.
- * Check to validate the definition
- */
-#define OPTION_HW_C1E_FEAT
-#define F10_HW_C1E_SUPPORT
-#if AGESA_ENTRY_INIT_EARLY == TRUE
- #ifdef OPTION_FAMILY10H
- #if OPTION_FAMILY10H == TRUE
- #if (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE) || (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_PH == TRUE)
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHwC1e;
- #undef OPTION_HW_C1E_FEAT
- #define OPTION_HW_C1E_FEAT &CpuFeatureHwC1e,
- extern CONST HW_C1E_FAMILY_SERVICES ROMDATA F10HwC1e;
- #undef F10_HW_C1E_SUPPORT
- #define F10_HW_C1E_SUPPORT {(AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_RB | AMD_FAMILY_10_PH), &F10HwC1e},
- #endif
- #endif
- #endif
- CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA HwC1eFamilyServiceArray[] =
- {
- F10_HW_C1E_SUPPORT
- {0, NULL}
- };
- CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA HwC1eFamilyServiceTable =
- {
- (sizeof (HwC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
- &HwC1eFamilyServiceArray[0]
- };
-#endif
-
-#endif // _OPTION_HW_C1E_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionIdsInstall.h b/src/vendorcode/amd/agesa/Include/OptionIdsInstall.h
deleted file mode 100644
index 11de68e..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionIdsInstall.h
+++ /dev/null
@@ -1,417 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * IDS Option Install File
- *
- * This file generates the defaults tables for family 10h model 5 processors.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Core
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _OPTION_IDS_INSTALL_H_
-#define _OPTION_IDS_INSTALL_H_
-#include "Ids.h"
-#include "IdsHt.h"
-#include "IdsLib.h"
-#ifdef __IDS_EXTENDED__
- #include OPTION_IDS_EXT_INSTALL_FILE
-#endif
-
-#define IDS_LATE_RUN_AP_TASK
-
-#define M_HTIDS_PORT_OVERRIDE_HOOK (PF_HtIdsGetPortOverride)CommonVoid
-#if (IDSOPT_IDS_ENABLED == TRUE)
- #if (IDSOPT_CONTROL_ENABLED == TRUE)
- // Check for all families which include HT Features.
- #if (OPTION_FAMILY10H == TRUE) && (AGESA_ENTRY_INIT_POST == TRUE)
- #undef M_HTIDS_PORT_OVERRIDE_HOOK
- #define M_HTIDS_PORT_OVERRIDE_HOOK HtIdsGetPortOverride
- #endif
- #endif
-#endif // OPTION_IDS_LEVEL
-CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride = M_HTIDS_PORT_OVERRIDE_HOOK;
-
-#if (IDSOPT_IDS_ENABLED == TRUE)
- #if (AGESA_ENTRY_INIT_LATE == TRUE)
- #undef IDS_LATE_RUN_AP_TASK
- #define IDS_LATE_RUN_AP_TASK
- #endif
-#endif // OPTION_IDS_LEVEL
-
-#if (IDSOPT_TRACING_ENABLED == TRUE)
- #if (AGESA_ENTRY_INIT_POST == TRUE)
- #include <mu.h>
- CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
- { (UINT32) (UINT64) MemUWriteCachelines, "WriteCl(PhyAddrLo,BufferAddr,ClCnt)"},
- { (UINT32) (UINT64) MemUReadCachelines, "ReadCl(BufferAddr,PhyAddrLo,ClCnt)"},
- { (UINT32) (UINT64) MemUFlushPattern, "FlushCl(PhyAddrLo,ClCnt)"}
- };
- #elif (AGESA_ENTRY_INIT_RECOVERY == TRUE)
- #include <mru.h>
- CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
- { (UINT32) (UINT64) MemRecUWrite1CL, "Write1Cl(PhyAddrLo,BufferAddr)"},
- { (UINT32) (UINT64) MemRecURead1CL, "Read1Cl(BufferAddr,PhyAddrLo)"},
- { (UINT32) (UINT64) MemRecUFlushPattern, "Flush1Cl(PhyAddrLo)"}
- };
- #else
- CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
- { (UINT32) (UINT64) CommonReturnFalse, "DefRet()"},
- { (UINT32) (UINT64) CommonReturnFalse, "DefRet()"},
- { (UINT32) (UINT64) CommonReturnFalse, "DefRet()"}
- };
- #endif
-#endif
-
-
-///Ids Feat Options
-#if (IDSOPT_IDS_ENABLED == TRUE)
- #if (IDSOPT_CONTROL_ENABLED == TRUE)
-
- #ifndef OPTION_IDS_EXTEND_FEATS
- #define OPTION_IDS_EXTEND_FEATS
- #endif
-
- #define OPTION_IDS_FEAT_ECCCTRL\
- OPTION_IDS_FEAT_ECCCTRL_F10 \
- OPTION_IDS_FEAT_ECCCTRL_F12 \
- OPTION_IDS_FEAT_ECCCTRL_F15
-
- #define OPTION_IDS_FEAT_GNB_PLATFORMCFG\
- OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 \
- OPTION_IDS_FEAT_GNB_PLATFORMCFGF14
-
- #define OPTION_IDS_FEAT_CPB_CTRL\
- OPTION_IDS_FEAT_CPB_CTRL_F12
-
- #define OPTION_IDS_FEAT_HTC_CTRL\
- OPTION_IDS_FEAT_HTC_CTRL_F15
-
- #define OPTION_IDS_FEAT_MEMORY_MAPPING\
- OPTION_IDS_FEAT_MEMORY_MAPPING_F15
-
- #define OPTION_IDS_FEAT_HT_ASSIST\
- OPTION_IDS_FEAT_HT_ASSIST_F10HY \
- OPTION_IDS_FEAT_HT_ASSIST_F15
-
- #define OPTION_IDS_FEAT_ECCSYMBOLSIZE\
- OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 \
- OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15
-
-/*----------------------------------------------------------------------------
- * Family 10 feat blocks
- *
- *----------------------------------------------------------------------------
- */
- #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10
- #define OPTION_IDS_FEAT_ECCCTRL_F10
- #ifdef OPTION_FAMILY10H
- #if OPTION_FAMILY10H == TRUE
-//Ecc symbol size
- extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccSymbolSizeBlockF10;
- #undef OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10
- #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 &IdsFeatEccSymbolSizeBlockF10,
-
-//ECC scrub control
- extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF10;
- #undef OPTION_IDS_FEAT_ECCCTRL_F10
- #define OPTION_IDS_FEAT_ECCCTRL_F10 &IdsFeatEccCtrlBlockF10,
- #endif
- #endif
-
- //Misc Features
- #define OPTION_IDS_FEAT_HT_ASSIST_F10HY
- #ifdef OPTION_FAMILY10H_HY
- #if OPTION_FAMILY10H_HY == TRUE
- #undef OPTION_IDS_FEAT_HT_ASSIST_F10HY
- extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtAssistBlockPlatformCfgF10Hy;
-
- #define OPTION_IDS_FEAT_HT_ASSIST_F10HY \
- &IdsFeatHtAssistBlockPlatformCfgF10Hy,
- #endif
- #endif
-/*----------------------------------------------------------------------------
- * Family 12 feat blocks
- *
- *----------------------------------------------------------------------------
- */
- #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF12
- #define OPTION_IDS_FEAT_ECCCTRL_F12
- #define OPTION_IDS_FEAT_CPB_CTRL_F12
- #ifdef OPTION_FAMILY12H
- #if OPTION_FAMILY12H == TRUE
- extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF12;
- #undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF12
- #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 &IdsFeatGnbPlatformCfgBlockF12,
-
- //ECC scrub control
- extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF12;
- #undef OPTION_IDS_FEAT_ECCCTRL_F12
- #define OPTION_IDS_FEAT_ECCCTRL_F12 &IdsFeatEccCtrlBlockF12,
-
- #undef OPTION_IDS_FEAT_CPB_CTRL_F12
- extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatCpbCtrlBlockF12;
- #define OPTION_IDS_FEAT_CPB_CTRL_F12 &IdsFeatCpbCtrlBlockF12,
-
- #endif
- #endif
-
-/*----------------------------------------------------------------------------
- * Family 14 feat blocks
- *
- *----------------------------------------------------------------------------
- */
- #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF14
- #ifdef OPTION_FAMILY14H
- #if OPTION_FAMILY14H == TRUE
- extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF14;
- #undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF14
- #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF14 &IdsFeatGnbPlatformCfgBlockF14,
- #endif
- #endif
-
-/*----------------------------------------------------------------------------
- * Family 15 feat blocks
- *
- *----------------------------------------------------------------------------
- */
- #define OPTION_IDS_FEAT_HTC_CTRL_F15
- #define OPTION_IDS_FEAT_MEMORY_MAPPING_F15
- #define OPTION_IDS_FEAT_HT_ASSIST_F15
- #define OPTION_IDS_FEAT_ECCCTRL_F15
- #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15
- #ifdef OPTION_FAMILY15H
- #if OPTION_FAMILY15H == TRUE
- extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtcControlBlockF15;
- extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtcControlLateBlockF15;
- #undef OPTION_IDS_FEAT_HTC_CTRL_F15
- #define OPTION_IDS_FEAT_HTC_CTRL_F15\
- &IdsFeatHtcControlBlockF15,\
- &IdsFeatHtcControlLateBlockF15,
-
- extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingPostBeforeBlockF15;
- extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingChIntlvBlockF15;
- #undef OPTION_IDS_FEAT_MEMORY_MAPPING_F15
- #define OPTION_IDS_FEAT_MEMORY_MAPPING_F15\
- &IdsFeatMemoryMappingPostBeforeBlockF15,\
- &IdsFeatMemoryMappingChIntlvBlockF15,
-
- extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtAssistBlockPlatformCfgF15;
- #undef OPTION_IDS_FEAT_HT_ASSIST_F15
- #define OPTION_IDS_FEAT_HT_ASSIST_F15\
- &IdsFeatHtAssistBlockPlatformCfgF15,
-
- extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF15;
- #undef OPTION_IDS_FEAT_ECCCTRL_F15
- #define OPTION_IDS_FEAT_ECCCTRL_F15 &IdsFeatEccCtrlBlockF15,
-
- extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccSymbolSizeBlockF15;
- #undef OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15
- #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15 &IdsFeatEccSymbolSizeBlockF15,
-
- #endif
- #endif
-
-
-
- CONST IDS_FEAT_STRUCT ROMDATA IdsFeatUcodeBlock =
- {
- IDS_FEAT_UCODE_UPDATE,
- IDS_ALL_CORES,
- IDS_UCODE,
- IDS_FAMILY_ALL,
- IdsSubUCode
- };
-
- CONST IDS_FEAT_STRUCT ROMDATA IdsFeatPowerPolicyBlock =
- {
- IDS_FEAT_POWER_POLICY,
- IDS_ALL_CORES,
- IDS_PLATFORMCFG_OVERRIDE,
- IDS_FAMILY_ALL,
- IdsSubPowerPolicyOverride
- };
-
- CONST IDS_FEAT_STRUCT ROMDATA IdsFeatTargetPstateBlock =
- {
- IDS_FEAT_TARGET_PSTATE,
- IDS_BSP_ONLY,
- IDS_INIT_LATE_AFTER,
- IDS_FAMILY_ALL,
- IdsSubTargetPstate
- };
-
- CONST IDS_FEAT_STRUCT ROMDATA IdsFeatPostPstateBlock =
- {
- IDS_FEAT_POSTPSTATE,
- IDS_ALL_CORES,
- IDS_CPU_Early_Override,
- IDS_FAMILY_ALL,
- IdsSubPostPState
- };
-
- //Dram controller Features
- CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctAllMemClkBlock =
- {
- IDS_FEAT_DCT_ALLMEMCLK,
- IDS_BSP_ONLY,
- IDS_ALL_MEMORY_CLOCK,
- IDS_FAMILY_ALL,
- IdsSubAllMemClkEn
- };
-
- CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctGangModeBlock =
- {
- IDS_FEAT_DCT_GANGMODE,
- IDS_BSP_ONLY,
- IDS_GANGING_MODE,
- IDS_FAMILY_ALL,
- IdsSubGangingMode
- };
-
- CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctBurstLengthBlock =
- {
- IDS_FEAT_DCT_BURSTLENGTH,
- IDS_BSP_ONLY,
- IDS_BURST_LENGTH32,
- AMD_FAMILY_10,
- IdsSubBurstLength32
- };
-
- CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownCtrlBlock =
- {
- IDS_FEAT_DCT_POWERDOWN,
- IDS_BSP_ONLY,
- IDS_INIT_POST_BEFORE,
- IDS_FAMILY_ALL,
- IdsSubPowerDownCtrl
- };
-
- CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctDllShutDownBlock =
- {
- IDS_FEAT_DCT_DLLSHUTDOWN,
- IDS_BSP_ONLY,
- IDS_DLL_SHUT_DOWN,
- IDS_FAMILY_ALL,
- IdsSubDllShutDownSR
- };
-
-
- CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownModeBlock =
- {
- IDS_FEAT_DCT_POWERDOWN,
- IDS_BSP_ONLY,
- IDS_POWERDOWN_MODE,
- IDS_FAMILY_ALL,
- IdsSubPowerDownMode
- };
-
- CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHdtOutBlock =
- {
- IDS_FEAT_HDTOUT,
- IDS_BSP_ONLY,
- IDS_INIT_EARLY_BEFORE,
- IDS_FAMILY_ALL,
- IdsSubHdtOut
- };
-
- CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtSettingBlock =
- {
- IDS_FEAT_HT_SETTING,
- IDS_BSP_ONLY,
- IDS_HT_CONTROL,
- IDS_FAMILY_ALL,
- IdsSubHtLinkControl
- };
-
- CONST IDS_FEAT_STRUCT* ROMDATA IdsCommonFeats[] =
- {
- &IdsFeatUcodeBlock,
- &IdsFeatPowerPolicyBlock,
-
- &IdsFeatTargetPstateBlock,
-
- &IdsFeatPostPstateBlock,
-
- OPTION_IDS_FEAT_ECCSYMBOLSIZE
-
- OPTION_IDS_FEAT_ECCCTRL
-
- &IdsFeatDctAllMemClkBlock,
-
- &IdsFeatDctGangModeBlock,
-
- &IdsFeatDctBurstLengthBlock,
-
- &IdsFeatDctPowerDownCtrlBlock,
-
- &IdsFeatDctPowerDownModeBlock,
-
- &IdsFeatDctPowerDownModeBlock,
-
- OPTION_IDS_FEAT_HT_ASSIST
-
- &IdsFeatHdtOutBlock,
-
- &IdsFeatHtSettingBlock,
-
- OPTION_IDS_FEAT_GNB_PLATFORMCFG
-
- OPTION_IDS_FEAT_CPB_CTRL
-
- OPTION_IDS_FEAT_HTC_CTRL
-
- OPTION_IDS_FEAT_MEMORY_MAPPING
-
- OPTION_IDS_EXTEND_FEATS
-
- NULL
- };
- #else
- CONST IDS_FEAT_STRUCT* ROMDATA IdsCommonFeats[] =
- {
- NULL
- };
- #endif//IDSOPT_CONTROL_ENABLED
-#else
- CONST IDS_FEAT_STRUCT* ROMDATA IdsCommonFeats[] =
- {
- NULL
- };
-#endif// IDSOPT_IDS_ENABLED
-
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Include/OptionIoCstateInstall.h b/src/vendorcode/amd/agesa/Include/OptionIoCstateInstall.h
deleted file mode 100644
index f15682f..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionIoCstateInstall.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: IO C-state
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Options
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_IO_CSTATE_INSTALL_H_
-#define _OPTION_IO_CSTATE_INSTALL_H_
-
-#include "cpuIoCstate.h"
-
-/* This option is designed to be included into the platform solution install
- * file. The platform solution install file will define the options status.
- * Check to validate the definition
- */
-
-#define OPTION_IO_CSTATE_FEAT
-#define F10_IO_CSTATE_SUPPORT
-#define F12_IO_CSTATE_SUPPORT
-#define F14_IO_CSTATE_SUPPORT
-#define F15_IO_CSTATE_SUPPORT
-
-#if OPTION_IO_CSTATE == TRUE
- #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
- #ifdef OPTION_FAMILY10H
- #if OPTION_FAMILY10H == TRUE
- #if OPTION_FAMILY10H_PH == TRUE
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
- #undef OPTION_IO_CSTATE_FEAT
- #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
- extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F10IoCstateSupport;
- #undef F10_IO_CSTATE_SUPPORT
- #define F10_IO_CSTATE_SUPPORT {AMD_FAMILY_10_PH, &F10IoCstateSupport},
- #endif
- #endif
- #endif
-
- #ifdef OPTION_FAMILY12H
- #if OPTION_FAMILY12H == TRUE
- #if OPTION_FAMILY12H_LN == TRUE
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
- #undef OPTION_IO_CSTATE_FEAT
- #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
- extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F12IoCstateSupport;
- #undef F12_IO_CSTATE_SUPPORT
- #define F12_IO_CSTATE_SUPPORT {AMD_FAMILY_12_LN, &F12IoCstateSupport},
- #endif
- #endif
- #endif
-
- #ifdef OPTION_FAMILY14H
- #if OPTION_FAMILY14H == TRUE
- #if OPTION_FAMILY14H_ON == TRUE
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
- #undef OPTION_IO_CSTATE_FEAT
- #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
- extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F14IoCstateSupport;
- #undef F14_IO_CSTATE_SUPPORT
- #define F14_IO_CSTATE_SUPPORT {AMD_FAMILY_14_ON, &F14IoCstateSupport},
- #endif
- #endif
- #endif
-
- #ifdef OPTION_FAMILY15H
- #if OPTION_FAMILY15H == TRUE
- #if OPTION_FAMILY15H_OR == TRUE
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
- #undef OPTION_IO_CSTATE_FEAT
- #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
- extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F15IoCstateSupport;
- #undef F15_IO_CSTATE_SUPPORT
- #define F15_IO_CSTATE_SUPPORT {AMD_FAMILY_15_OR, &F15IoCstateSupport},
- #endif
- #endif
- #endif
-
- #endif
-#endif
-
-CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA IoCstateFamilyServiceArray[] =
-{
- F10_IO_CSTATE_SUPPORT
- F12_IO_CSTATE_SUPPORT
- F14_IO_CSTATE_SUPPORT
- F15_IO_CSTATE_SUPPORT
- {0, NULL}
-};
-
-CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA IoCstateFamilyServiceTable =
-{
- (sizeof (IoCstateFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
- &IoCstateFamilyServiceArray[0]
-};
-
-#endif // _OPTION_IO_CSTATE_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionLowPwrPstateInstall.h b/src/vendorcode/amd/agesa/Include/OptionLowPwrPstateInstall.h
deleted file mode 100644
index 6e03fea..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionLowPwrPstateInstall.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: Low Power Pstate for PROCHOT_L Throttling.
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Options
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_LOW_PWR_PSTATE_INSTALL_H_
-#define _OPTION_LOW_PWR_PSTATE_INSTALL_H_
-
-#include "cpuLowPwrPstate.h"
-
-/* This option is designed to be included into the platform solution install
- * file. The platform solution install file will define the options status.
- * Check to validate the definition
- */
-#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT
-#define F15_LOW_PWR_PSTATE_SUPPORT
-
-#if OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT == TRUE
- #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
- // Family 15h
- #ifdef OPTION_FAMILY15H
- #if OPTION_FAMILY15H == TRUE
- #if OPTION_FAMILY15H_OR == TRUE
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureLowPwrPstate;
- #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT
- #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT &CpuFeatureLowPwrPstate,
- extern CONST LOW_PWR_PSTATE_FAMILY_SERVICES ROMDATA F15LowPwrPstateSupport;
- #undef F15_LOW_PWR_PSTATE_SUPPORT
- #define F15_LOW_PWR_PSTATE_SUPPORT {AMD_FAMILY_15_OR, &F15LowPwrPstateSupport},
- #endif
- #endif
- #endif
- #endif
-#endif
-
-CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA LowPwrPstateFamilyServiceArray[] =
-{
- F15_LOW_PWR_PSTATE_SUPPORT
- {0, NULL}
-};
-
-CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA LowPwrPstateFamilyServiceTable =
-{
- (sizeof (LowPwrPstateFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
- &LowPwrPstateFamilyServiceArray[0]
-};
-
-#endif // _OPTION_LOW_PWR_PSTATE_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionMemory.h b/src/vendorcode/amd/agesa/Include/OptionMemory.h
deleted file mode 100644
index 1d4c08f..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionMemory.h
+++ /dev/null
@@ -1,342 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Memory option API.
- *
- * Contains structures and values used to control the Memory option code.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: OPTION
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_MEMORY_H_
-#define _OPTION_MEMORY_H_
-
-/* Memory Includes */
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "ma.h"
-#include "mp.h"
-/*----------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-#define MAX_FF_TYPES 6 ///< Maximum number of DDR Form factors (UDIMMs, RDIMMMs, SODIMMS) supported
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *----------------------------------------------------------------------------------------
- */
-
-/*
-* STANDARD MEMORY FEATURE FUNCTION POINTER
-*/
-
-typedef BOOLEAN OPTION_MEM_FEATURE_NB (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-typedef BOOLEAN MEM_TECH_FEAT (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-typedef UINT8 MEM_TABLE_FEAT (
- IN OUT MEM_TABLE_ALIAS **MTPtr
- );
-
-#define MEM_FEAT_BLOCK_NB_STRUCT_VERSION 0x01
-
-/**
- * MEMORY FEATURE BLOCK - This structure serves as a vector table for standard
- * memory feature implementation functions. It contains vectors for all of the
- * features that are supported by the various Northbridge devices supported by
- * AGESA.
- */
-typedef struct _MEM_FEAT_BLOCK_NB {
- UINT16 OptMemFeatVersion; ///< Version of memory feature block.
- OPTION_MEM_FEATURE_NB *OnlineSpare; ///< Online spare support.
- OPTION_MEM_FEATURE_NB *InterleaveBanks; ///< Bank (Chip select) interleaving support.
- OPTION_MEM_FEATURE_NB *UndoInterleaveBanks; ///< Undo Bank (Chip Select) interleaving.
- OPTION_MEM_FEATURE_NB *CheckInterleaveNodes; ///< Check for Node interleaving support.
- OPTION_MEM_FEATURE_NB *InterleaveNodes; ///< Node interleaving support.
- OPTION_MEM_FEATURE_NB *InterleaveChannels; ///< Channel interleaving support.
- OPTION_MEM_FEATURE_NB *InterleaveRegion; ///< Interleave Region support.
- OPTION_MEM_FEATURE_NB *CheckEcc; ///< Check for ECC support.
- OPTION_MEM_FEATURE_NB *InitEcc; ///< ECC support.
- OPTION_MEM_FEATURE_NB *Training; ///< Choose the type of training (Parallel, standard or hardcoded).
- OPTION_MEM_FEATURE_NB *LvDdr3; ///< Low voltage DDR3 dimm support
- OPTION_MEM_FEATURE_NB *OnDimmThermal; ///< On-Dimm thermal management
- MEM_TECH_FEAT *DramInit; ///< Choose the type of Dram init (hardware based or software based).
- OPTION_MEM_FEATURE_NB *ExcludeDIMM; ///< Exclude a dimm.
- OPTION_MEM_FEATURE_NB *InitEarlySampleSupport; ///< Initialize early sample support.
- OPTION_MEM_FEATURE_NB *InitCPG; ///< Continuous pattern generation.
- OPTION_MEM_FEATURE_NB *InitHwRxEn; ///< Hardware Receiver Enable Training Initilization.
-} MEM_FEAT_BLOCK_NB;
-
-typedef AGESA_STATUS MEM_MAIN_FLOW_CONTROL (
- IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
- );
-
-typedef BOOLEAN OPTION_MEM_FEATURE_MAIN (
- IN MEM_MAIN_DATA_BLOCK *MMPtr
- );
-
-typedef BOOLEAN MEM_NB_CONSTRUCTOR (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN MEM_FEAT_BLOCK_NB *FeatPtr,
- IN MEM_SHARED_DATA *mmSharedPtr, ///< Pointer to Memory scratchpad
- IN UINT8 NodeID
- );
-
-typedef BOOLEAN MEM_TECH_CONSTRUCTOR (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-typedef VOID MEM_INITIALIZER (
- IN OUT MEM_DATA_STRUCT *MemPtr
- );
-
-typedef AGESA_STATUS MEM_PLATFORM_CFG (
- IN struct _MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN CH_DEF_STRUCT *CurrentChannel
- );
-
-typedef BOOLEAN MEM_IDENDIMM_CONSTRUCTOR (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- );
-
-typedef VOID MEM_TECH_TRAINING_FEAT (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Pass
- );
-
-typedef BOOLEAN MEM_RESUME_CONSTRUCTOR (
- IN OUT VOID *S3NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- );
-
-typedef AGESA_STATUS MEM_PLAT_SPEC_CFG (
- IN struct _MEM_DATA_STRUCT *MemData,
- IN OUT CH_DEF_STRUCT *CurrentChannel,
- IN OUT MEM_PS_BLOCK *PsPtr
- );
-
-typedef AGESA_STATUS MEM_FLOW_CFG (
- IN OUT MEM_MAIN_DATA_BLOCK *MemData
- );
-
-#define MEM_FEAT_BLOCK_MAIN_STRUCT_VERSION 0x01
-
-/**
- * MAIN FEATURE BLOCK - This structure serves as vector table for memory features
- * that shared between all northbridge devices.
- */
-typedef struct _MEM_FEAT_BLOCK_MAIN {
- UINT16 OptMemFeatVersion; ///< Version of main feature block.
- OPTION_MEM_FEATURE_MAIN *Training; ///< Training features.
- OPTION_MEM_FEATURE_MAIN *ExcludeDIMM; ///< Exclude a dimm.
- OPTION_MEM_FEATURE_MAIN *OnlineSpare; ///< On-line spare.
- OPTION_MEM_FEATURE_MAIN *InterleaveNodes; ///< Node interleave.
- OPTION_MEM_FEATURE_MAIN *InitEcc; ///< Initialize ECC on all nodes if they all support it.
- OPTION_MEM_FEATURE_MAIN *MemClr; ///< Memory Clear.
- OPTION_MEM_FEATURE_MAIN *MemDmi; ///< Memory DMI Support.
- OPTION_MEM_FEATURE_MAIN *LvDDR3; ///< Low voltage DDR3 support.
- OPTION_MEM_FEATURE_MAIN *UmaAllocation; ///< Uma Allocation.
- OPTION_MEM_FEATURE_MAIN *MemSave; ///< Memory Context Save
- OPTION_MEM_FEATURE_MAIN *MemRestore; ///< Memory Context Restore
-} MEM_FEAT_BLOCK_MAIN;
-
-#define MEM_NB_SUPPORT_STRUCT_VERSION 0x01
-#define MEM_TECH_FEAT_BLOCK_STRUCT_VERSION 0x01
-#define MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION 0x01
-#define MEM_TECH_LRDIMM_STRUCT_VERSION 0x01
-/**
- * MEMORY TECHNOLOGY FEATURE BLOCK - This structure serves as a vector table for standard
- * memory feature implementation functions. It contains vectors for all of the
- * features that are supported by the various Technology features supported by
- * AGESA.
- */
-typedef struct _MEM_TECH_FEAT_BLOCK {
- UINT16 OptMemTechFeatVersion; ///< Version of memory Tech feature block.
- MEM_TECH_FEAT *EnterHardwareTraining; ///<Enter HW WL Training
- MEM_TECH_FEAT *SwWLTraining; ///<SW Write Levelization training
- MEM_TECH_FEAT *HwBasedWLTrainingPart1; ///<HW based write levelization Training Part 1
- MEM_TECH_FEAT *HwBasedDQSReceiverEnableTrainingPart1; ///<HW based DQS receiver Enabled Training Part 1
- MEM_TECH_FEAT *HwBasedWLTrainingPart2; ///<HW based write levelization Training Part 2
- MEM_TECH_FEAT *HwBasedDQSReceiverEnableTrainingPart2; ///<HW based DQS receiver Enabled Training Part 2
- MEM_TECH_FEAT *TrainExitHwTrn; ///<Exit HW WL Training
- MEM_TECH_FEAT *NonOptimizedSWDQSRecEnTrainingPart1; ///< Non-Optimized Software based receiver Enable Training part 1
- MEM_TECH_FEAT *OptimizedSwDqsRecEnTrainingPart1; ///< Optimized Software based receiver Enable Training part 1
- MEM_TECH_FEAT *NonOptimizedSRdWrPosTraining; ///< Non-Optimized Rd Wr Position training
- MEM_TECH_FEAT *OptimizedSRdWrPosTraining; ///< Optimized Rd Wr Position training
- MEM_TECH_FEAT *MaxRdLatencyTraining; ///< MaxReadLatency Training
-} MEM_TECH_FEAT_BLOCK;
-
-/**
- * MEMORY TECHNOLOGY LRDIMM BLOCK - This structure serves as a vector table for standard
- * memory feature implementation functions. It contains vectors for all of the
- * features that are supported by the various LRDIMM features supported by
- * AGESA.
- */
-typedef struct _MEM_TECH_LRDIMM {
- UINT16 OptMemTechLrdimmVersion; ///< Version of memory Tech feature block.
- MEM_TECH_FEAT *MemTInitializeLrdimm; ///< LRDIMM initialization
-} MEM_TECH_LRDIMM;
-/**
- * MEMORY NORTHBRIDGE SUPPORT STRUCT - This structure groups the Northbridge dependent
- * options together in a list to provide a single access point for all code to use
- * and to ensure that everything corresponding to the same NB type is grouped together.
- *
- * The Technology Block pointers are not included in this structure because DRAM technology
- * needs to be decoupled from the northbridge type.
- *
- */
-typedef struct _MEM_NB_SUPPORT {
- UINT16 MemNBSupportVersion; ///< Version of northbridge support.
- MEM_NB_CONSTRUCTOR *MemConstructNBBlock; ///< NorthBridge block constructor.
- MEM_INITIALIZER *MemNInitDefaults; ///< Default value initialization for MEM_DATA_STRUCT.
- MEM_FEAT_BLOCK_NB *MemFeatBlock; ///< Memory feature block.
- MEM_RESUME_CONSTRUCTOR *MemS3ResumeConstructNBBlock; ///< S3 memory initialization northbridge block constructor.
- MEM_IDENDIMM_CONSTRUCTOR *MemIdentifyDimmConstruct; ///< Constructor for address to dimm identification.
-} MEM_NB_SUPPORT;
-
-/*
- * MEMORY Non-Training FEATURES - This structure serves as a vector table for standard
- * memory non-training feature implementation functions. It contains vectors for all of the
- * features that are supported by the various Technology devices supported by
- * AGESA.
- */
-
-/**
- * MAIN TRAINING SEQUENCE LIST - This structure serves as vector table for memory features
- * that shared between all northbridge devices.
- */
-typedef struct _MEM_FEAT_TRAIN_SEQ {
- UINT16 OptMemTrainingSequenceListVersion; ///< Version of main feature block.
- OPTION_MEM_FEATURE_NB *TrainingSequence; ///< Training Sequence function.
- OPTION_MEM_FEATURE_NB *TrainingSequenceEnabled; ///< Enable function.
- MEM_TECH_FEAT_BLOCK *MemTechFeatBlock; ///< Memory feature block.
-} MEM_FEAT_TRAIN_SEQ;
-
-/**
- * PLATFORM SPECIFIC CONFIGURATION BLOCK - This structure groups various PSC table
- * entries which are used by PSC engine
- */
-typedef struct _MEM_PSC_TABLE_BLOCK {
- PSC_TBL_ENTRY **TblEntryOfMaxFreq; ///< Table entry of MaxFreq.
- PSC_TBL_ENTRY **TblEntryOfDramTerm; ///< Table entry of Dram Term.
- PSC_TBL_ENTRY **TblEntryOfODTPattern; ///< Table entry of ODT Pattern.
- PSC_TBL_ENTRY **TblEntryOfSAO; ///< Table entry of Slow access mode, AddrTmg and ODC..
- PSC_TBL_ENTRY **TblEntryOfMR0WR; ///< Table entry of MR0[WR].
- PSC_TBL_ENTRY **TblEntryOfMR0CL; ///< Table entry of MR0[CL].
- PSC_TBL_ENTRY **TblEntryOfRC2IBT; ///< Table entry of RC2 IBT.
- PSC_TBL_ENTRY **TblEntryOfRC10OpSpeed; ///< Table entry of RC10[operating speed].
- PSC_TBL_ENTRY **TblEntryOfLRIBT;///< Table entry of LRDIMM IBT
- PSC_TBL_ENTRY **TblEntryOfLRNPR; ///< Table entry of LRDIMM F0RC13[NumPhysicalRanks].
- PSC_TBL_ENTRY **TblEntryOfLRNLR; ///< Table entry of LRDIMM F0RC13[NumLogicalRanks].
- PSC_TBL_ENTRY **TblEntryOfGen; ///< Table entry of CLKDis map and CKE, ODT as well as ChipSel tri-state map.
-} MEM_PSC_TABLE_BLOCK;
-
-typedef BOOLEAN MEM_PSC_FLOW (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN MEM_PSC_TABLE_BLOCK *EntryOfTables
- );
-
-/**
- * PLATFORM SPECIFIC CONFIGURATION FLOW BLOCK - Pointers to the sub-engines of platform
- * specific configuration.
- */
-typedef struct _MEM_PSC_FLOW_BLOCK {
- MEM_PSC_TABLE_BLOCK *EntryOfTables; ///<Entry of NB specific MEM_PSC_TABLE_BLOCK
- MEM_PSC_FLOW *MaxFrequency; ///< Sub-engine which performs "Max Frequency" value extraction.
- MEM_PSC_FLOW *DramTerm; ///< Sub-engine which performs "Dram Term" value extraction.
- MEM_PSC_FLOW *ODTPattern; ///< Sub-engine which performs "ODT Pattern" value extraction.
- MEM_PSC_FLOW *SAO; ///< Sub-engine which performs "Slow access mode, AddrTmg and ODC" value extraction.
- MEM_PSC_FLOW *MR0WrCL; ///< Sub-engine which performs "MR0[WR] and MR0[CL]" value extraction.
- MEM_PSC_FLOW *RC2IBT; ///< Sub-engine "RC2 IBT" value extraction.
- MEM_PSC_FLOW *RC10OpSpeed; ///< Sub-engine "RC10[operating speed]" value extraction.
- MEM_PSC_FLOW *LRIBT; ///< Sub-engine "LRDIMM IBT" value extraction.
- MEM_PSC_FLOW *LRNPR; ///< Sub-engine "LRDIMM F0RC13[NumPhysicalRanks]" value extraction.
- MEM_PSC_FLOW *LRNLR; ///< Sub-engine "LRDIMM F0RC13[NumLogicalRanks]" value extraction.
-} MEM_PSC_FLOW_BLOCK;
-
-/*----------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *----------------------------------------------------------------------------------------
- */
-/* Feature Default Return */
-BOOLEAN MemFDefRet (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN MemMDefRet (
- IN MEM_MAIN_DATA_BLOCK *MMPtr
- );
-/* Table Feature Default Return */
-UINT8 MemFTableDefRet (
- IN OUT MEM_TABLE_ALIAS **MTPtr
- );
-/* S3 Feature Default Return */
-BOOLEAN MemFS3DefConstructorRet (
- IN OUT VOID *S3NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- );
-
-BOOLEAN
-MemProcessConditionalOverrides (
- IN PSO_TABLE *PlatformMemoryConfiguration,
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 PsoAction,
- IN UINT8 Dimm
- );
-
-#endif // _OPTION_MEMORY_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/Include/OptionMemoryInstall.h
deleted file mode 100644
index 2f41757..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionMemoryInstall.h
+++ /dev/null
@@ -1,4051 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: Memory
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Options
- * @e \$Revision: 37402 $ @e \$Date: 2010-09-03 05:36:02 +0800 (Fri, 03 Sep 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_MEMORY_INSTALL_H_
-#define _OPTION_MEMORY_INSTALL_H_
-
-/*-------------------------------------------------------------------------------
- * This option file is designed to be included into the platform solution install
- * file. The platform solution install file will define the options status.
- * Check to validate the definition
- */
-
-/*----------------------------------------------------------------------------------
- * FEATURE BLOCK FUNCTIONS
- *
- * This section defines function names that depend upon options that are selected
- * in the platform solution install file.
- */
-BOOLEAN MemFDefRet (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- return FALSE;
-}
-
-BOOLEAN MemMDefRet (
- IN MEM_MAIN_DATA_BLOCK *MMPtr
- )
-{
- return TRUE;
-}
-
-BOOLEAN MemMDefRetFalse (
- IN MEM_MAIN_DATA_BLOCK *MMPtr
- )
-{
- return FALSE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the northbridge block for dimm identification translator
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
- * @param[in,out] NodeID - ID of current node to construct
- * @return TRUE - This is the correct constructor for the targeted node.
- * @return FALSE - This isn't the correct constructor for the targeted node.
- */
-BOOLEAN MemNIdentifyDimmConstructorRetDef (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- )
-{
- return FALSE;
-}
-/*----------------------------------------------------------------------------------
- * TABLE FEATURE BLOCK FUNCTIONS
- *
- * This section defines function names that depend upon options that are selected
- * in the platform solution install file.
- */
-UINT8 MemFTableDefRet (
- IN OUT MEM_TABLE_ALIAS **MTPtr
- )
-{
- return 0;
-}
-/*----------------------------------------------------------------------------------
- * FEATURE S3 BLOCK FUNCTIONS
- *
- * This section defines function names that depend upon options that are selected
- * in the platform solution install file.
- */
-BOOLEAN MemFS3DefConstructorRet (
- IN OUT VOID *S3NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- )
-{
- return TRUE;
-}
-
-#if (OPTION_MEMCTLR_DR == TRUE)
- #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
- #if (OPTION_S3_MEM_SUPPORT == TRUE)
- extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockDr;
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemS3ResumeConstructNBBlockDr
- #else
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemFS3DefConstructorRet
- #endif
- #else
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemFS3DefConstructorRet
- #endif
- #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
- extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorDr;
- #define MEM_IDENDIMM_DR MemNIdentifyDimmConstructorDr
- #else
- #define MEM_IDENDIMM_DR MemNIdentifyDimmConstructorRetDef
- #endif
-#endif
-
-#if (OPTION_MEMCTLR_DA == TRUE || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE)
- #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
- #if (OPTION_S3_MEM_SUPPORT == TRUE)
- #if (OPTION_MEMCTLR_Ni == TRUE)
- extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockNi;
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemS3ResumeConstructNBBlockNi
- #else
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemFS3DefConstructorRet
- #endif
- #if (OPTION_MEMCTLR_DA == TRUE)
- extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockDA;
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemS3ResumeConstructNBBlockDA
- #else
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemFS3DefConstructorRet
- #endif
- #if (OPTION_MEMCTLR_PH == TRUE)
- extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockPh;
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemS3ResumeConstructNBBlockPh
- #else
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemFS3DefConstructorRet
- #endif
- #if (OPTION_MEMCTLR_RB == TRUE)
- extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockRb;
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemS3ResumeConstructNBBlockRb
- #else
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemFS3DefConstructorRet
- #endif
- #endif
- #else
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemFS3DefConstructorRet
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemFS3DefConstructorRet
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemFS3DefConstructorRet
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemFS3DefConstructorRet
- #endif
- #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
- extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorDA;
- #define MEM_IDENDIMM_DA MemNIdentifyDimmConstructorDA
- extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorRb;
- #define MEM_IDENDIMM_RB MemNIdentifyDimmConstructorRb
- extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorPh;
- #define MEM_IDENDIMM_PH MemNIdentifyDimmConstructorPh
- #else
- #define MEM_IDENDIMM_DA MemNIdentifyDimmConstructorRetDef
- #define MEM_IDENDIMM_RB MemNIdentifyDimmConstructorRetDef
- #define MEM_IDENDIMM_PH MemNIdentifyDimmConstructorRetDef
- #endif
-#endif
-
-#if (OPTION_MEMCTLR_OR == TRUE)
- #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
- #if (OPTION_S3_MEM_SUPPORT == TRUE)
- extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockOr;
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemS3ResumeConstructNBBlockOr
- #else
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemFS3DefConstructorRet
- #endif
- #else
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemFS3DefConstructorRet
- #endif
- #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
- extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorOr;
- #define MEM_IDENDIMM_OR MemNIdentifyDimmConstructorOr
- #else
- #define MEM_IDENDIMM_OR MemNIdentifyDimmConstructorRetDef
- #endif
-#endif
-
-#if (OPTION_MEMCTLR_HY == TRUE)
- #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
- #if (OPTION_S3_MEM_SUPPORT == TRUE)
- extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockHy;
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemS3ResumeConstructNBBlockHy
- #else
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemFS3DefConstructorRet
- #endif
- #else
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemFS3DefConstructorRet
- #endif
- #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
- extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorHy;
- #define MEM_IDENDIMM_HY MemNIdentifyDimmConstructorHy
- #else
- #define MEM_IDENDIMM_HY MemNIdentifyDimmConstructorRetDef
- #endif
-#endif
-
-#if (OPTION_MEMCTLR_C32 == TRUE)
- #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
- #if (OPTION_S3_MEM_SUPPORT == TRUE)
- extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockC32;
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemS3ResumeConstructNBBlockC32
- #else
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemFS3DefConstructorRet
- #endif
- #else
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemFS3DefConstructorRet
- #endif
- #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
- extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorC32;
- #define MEM_IDENDIMM_C32 MemNIdentifyDimmConstructorC32
- #else
- #define MEM_IDENDIMM_C32 MemNIdentifyDimmConstructorRetDef
- #endif
-#endif
-
-#if (OPTION_MEMCTLR_LN == TRUE)
- #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
- #if (OPTION_S3_MEM_SUPPORT == TRUE)
- extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockLN;
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN MemS3ResumeConstructNBBlockLN
- #else
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN MemFS3DefConstructorRet
- #endif
- #else
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN MemFS3DefConstructorRet
- #endif
- #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
- extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorLN;
- #define MEM_IDENDIMM_LN MemNIdentifyDimmConstructorLN
- #else
- #define MEM_IDENDIMM_LN MemNIdentifyDimmConstructorRetDef
- #endif
-#endif
-
-#if (OPTION_MEMCTLR_ON == TRUE)
- #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
- #if (OPTION_S3_MEM_SUPPORT == TRUE)
- extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockON;
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON MemS3ResumeConstructNBBlockON
- #else
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON MemFS3DefConstructorRet
- #endif
- #else
- #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON MemFS3DefConstructorRet
- #endif
- #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
- extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorON;
- #define MEM_IDENDIMM_ON MemNIdentifyDimmConstructorON
- #else
- #define MEM_IDENDIMM_ON MemNIdentifyDimmConstructorRetDef
- #endif
-#endif
-
-/*----------------------------------------------------------------------------------
- * NORTHBRIDGE BLOCK CONSTRUCTOR AND INITIALIZER FUNCTION DEFAULT ASSIGNMENTS
- *
- *----------------------------------------------------------------------------------
-*/
-#define MEM_NB_SUPPORT_DR
-#define MEM_NB_SUPPORT_RB
-#define MEM_NB_SUPPORT_DA
-#define MEM_NB_SUPPORT_Ni
-#define MEM_NB_SUPPORT_PH
-#define MEM_NB_SUPPORT_HY
-#define MEM_NB_SUPPORT_LN
-#define MEM_NB_SUPPORT_OR
-#define MEM_NB_SUPPORT_C32
-#define MEM_NB_SUPPORT_ON
-#define MEM_NB_SUPPORT_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0, 0, 0 }
-
-#if (AGESA_ENTRY_INIT_POST == TRUE)
- /*----------------------------------------------------------------------------------
- * FLOW CONTROL FUNCTION
- *
- * This section selects the function that controls the memory initialization sequence
- * based upon the number of processor families that the BIOS will support.
- */
-
- #if (OPTION_MEMCTLR_DR == TRUE)
- extern MEM_FLOW_CFG MemMFlowDr;
- #define MEM_MAIN_FLOW_CONTROL_PTR_Dr MemMFlowDr,
- #else
- extern MEM_FLOW_CFG MemMFlowDef;
- #define MEM_MAIN_FLOW_CONTROL_PTR_Dr MemMFlowDef,
- #endif
- #if (OPTION_MEMCTLR_DA == TRUE)
- extern MEM_FLOW_CFG MemMFlowDA;
- #define MEM_MAIN_FLOW_CONTROL_PTR_DA MemMFlowDA,
- #else
- extern MEM_FLOW_CFG MemMFlowDef;
- #define MEM_MAIN_FLOW_CONTROL_PTR_DA MemMFlowDef,
- #endif
- #if (OPTION_MEMCTLR_HY == TRUE)
- extern MEM_FLOW_CFG MemMFlowHy;
- #define MEM_MAIN_FLOW_CONTROL_PTR_Hy MemMFlowHy,
- #else
- extern MEM_FLOW_CFG MemMFlowDef;
- #define MEM_MAIN_FLOW_CONTROL_PTR_Hy MemMFlowDef,
- #endif
- #if (OPTION_MEMCTLR_OR == TRUE)
- extern MEM_FLOW_CFG MemMFlowOr;
- #define MEM_MAIN_FLOW_CONTROL_PTR_OR MemMFlowOr,
- #else
- extern MEM_FLOW_CFG MemMFlowDef;
- #define MEM_MAIN_FLOW_CONTROL_PTR_OR MemMFlowDef,
- #endif
- #if (OPTION_MEMCTLR_LN == TRUE)
- extern MEM_FLOW_CFG MemMFlowLN;
- #define MEM_MAIN_FLOW_CONTROL_PTR_LN MemMFlowLN,
- #else
- extern MEM_FLOW_CFG MemMFlowDef;
- #define MEM_MAIN_FLOW_CONTROL_PTR_LN MemMFlowDef,
- #endif
- #if (OPTION_MEMCTLR_C32 == TRUE)
- extern MEM_FLOW_CFG MemMFlowC32;
- #define MEM_MAIN_FLOW_CONTROL_PTR_C32 MemMFlowC32,
- #else
- extern MEM_FLOW_CFG MemMFlowDef;
- #define MEM_MAIN_FLOW_CONTROL_PTR_C32 MemMFlowDef,
- #endif
- #if (OPTION_MEMCTLR_ON == TRUE)
- extern MEM_FLOW_CFG MemMFlowON;
- #define MEM_MAIN_FLOW_CONTROL_PTR_ON MemMFlowON,
- #else
- extern MEM_FLOW_CFG MemMFlowDef;
- #define MEM_MAIN_FLOW_CONTROL_PTR_ON MemMFlowDef,
- #endif
- #if (OPTION_MEMCTLR_Ni == TRUE)
- extern MEM_FLOW_CFG MemMFlowDA;
- #define MEM_MAIN_FLOW_CONTROL_PTR_Ni MemMFlowDA,
- #else
- extern MEM_FLOW_CFG MemMFlowDef;
- #define MEM_MAIN_FLOW_CONTROL_PTR_Ni MemMFlowDef,
- #endif
- #if (OPTION_MEMCTLR_RB == TRUE)
- extern MEM_FLOW_CFG MemMFlowRb;
- #define MEM_MAIN_FLOW_CONTROL_PTR_RB MemMFlowRb,
- #else
- extern MEM_FLOW_CFG MemMFlowDef;
- #define MEM_MAIN_FLOW_CONTROL_PTR_RB MemMFlowDef,
- #endif
- #if (OPTION_MEMCTLR_PH == TRUE)
- extern MEM_FLOW_CFG MemMFlowPh;
- #define MEM_MAIN_FLOW_CONTROL_PTR_PH MemMFlowPh,
- #else
- extern MEM_FLOW_CFG MemMFlowDef;
- #define MEM_MAIN_FLOW_CONTROL_PTR_PH MemMFlowDef,
- #endif
-
- MEM_FLOW_CFG* memFlowControlInstalled[] = {
- MEM_MAIN_FLOW_CONTROL_PTR_Dr
- MEM_MAIN_FLOW_CONTROL_PTR_DA
- MEM_MAIN_FLOW_CONTROL_PTR_RB
- MEM_MAIN_FLOW_CONTROL_PTR_PH
- MEM_MAIN_FLOW_CONTROL_PTR_Hy
- MEM_MAIN_FLOW_CONTROL_PTR_OR
- MEM_MAIN_FLOW_CONTROL_PTR_LN
- MEM_MAIN_FLOW_CONTROL_PTR_C32
- MEM_MAIN_FLOW_CONTROL_PTR_ON
- MEM_MAIN_FLOW_CONTROL_PTR_Ni
- NULL
- };
-
- #if (OPTION_ONLINE_SPARE == TRUE)
- extern OPTION_MEM_FEATURE_MAIN MemMOnlineSpare;
- #define MEM_MAIN_FEATURE_ONLINE_SPARE MemMOnlineSpare
- extern OPTION_MEM_FEATURE_NB MemFOnlineSpare;
- #define MEM_FEATURE_ONLINE_SPARE MemFOnlineSpare
- #else
- #define MEM_MAIN_FEATURE_ONLINE_SPARE MemMDefRet
- #define MEM_FEATURE_ONLINE_SPARE MemFDefRet
- #endif
-
- #if (OPTION_MEM_RESTORE == TRUE)
- extern OPTION_MEM_FEATURE_MAIN MemMContextSave;
- extern OPTION_MEM_FEATURE_MAIN MemMContextRestore;
- #define MEM_MAIN_FEATURE_MEM_SAVE MemMContextSave
- #define MEM_MAIN_FEATURE_MEM_RESTORE MemMContextRestore
- #else
- #define MEM_MAIN_FEATURE_MEM_SAVE MemMDefRet
- #define MEM_MAIN_FEATURE_MEM_RESTORE MemMDefRetFalse
- #endif
-
- #if (OPTION_BANK_INTERLEAVE == TRUE)
- extern OPTION_MEM_FEATURE_NB MemFInterleaveBanks;
- #define MEM_FEATURE_BANK_INTERLEAVE MemFInterleaveBanks
- extern OPTION_MEM_FEATURE_NB MemFUndoInterleaveBanks;
- #define MEM_FEATURE_UNDO_BANK_INTERLEAVE MemFUndoInterleaveBanks
- #else
- #define MEM_FEATURE_BANK_INTERLEAVE MemFDefRet
- #define MEM_FEATURE_UNDO_BANK_INTERLEAVE MemFDefRet
- #endif
-
- #if (OPTION_NODE_INTERLEAVE == TRUE)
- extern OPTION_MEM_FEATURE_MAIN MemMInterleaveNodes;
- #define MEM_MAIN_FEATURE_NODE_INTERLEAVE MemMInterleaveNodes
- extern OPTION_MEM_FEATURE_NB MemFCheckInterleaveNodes;
- extern OPTION_MEM_FEATURE_NB MemFInterleaveNodes;
- #define MEM_FEATURE_NODE_INTERLEAVE_CHECK MemFCheckInterleaveNodes
- #define MEM_FEATURE_NODE_INTERLEAVE MemFInterleaveNodes
- #else
- #define MEM_FEATURE_NODE_INTERLEAVE_CHECK MemFDefRet
- #define MEM_FEATURE_NODE_INTERLEAVE MemFDefRet
- #define MEM_MAIN_FEATURE_NODE_INTERLEAVE MemMDefRet
- #endif
-
- #if (OPTION_DCT_INTERLEAVE == TRUE)
- extern OPTION_MEM_FEATURE_NB MemFInterleaveChannels;
- #define MEM_FEATURE_CHANNEL_INTERLEAVE MemFInterleaveChannels
- #else
- #define MEM_FEATURE_CHANNEL_INTERLEAVE MemFDefRet
- #endif
-
- #if (OPTION_ECC == TRUE)
- extern OPTION_MEM_FEATURE_MAIN MemMEcc;
- #define MEM_MAIN_FEATURE_ECC MemMEcc
- extern OPTION_MEM_FEATURE_NB MemFCheckECC;
- extern OPTION_MEM_FEATURE_NB MemFInitECC;
- #define MEM_FEATURE_CK_ECC MemFCheckECC
- #define MEM_FEATURE_ECC MemFInitECC
- #define MEM_FEATURE_ECCX8 MemMDefRet
- #else
- #define MEM_MAIN_FEATURE_ECC MemMDefRet
- #define MEM_FEATURE_CK_ECC MemFDefRet
- #define MEM_FEATURE_ECC MemFDefRet
- #define MEM_FEATURE_ECCX8 MemMDefRet
- #endif
-
- #if (OPTION_EMP == TRUE)
- extern OPTION_MEM_FEATURE_NB MemFInitEMP;
- #define MEM_FEATURE_EMP MemFInitEMP
- #else
- #define MEM_FEATURE_EMP MemFDefRet
- #endif
-
- extern OPTION_MEM_FEATURE_MAIN MemMMctMemClr;
- #define MEM_MAIN_FEATURE_MEM_CLEAR MemMMctMemClr
-
- #if (OPTION_DMI == TRUE)
- #if (OPTION_DDR3 == TRUE)
- extern OPTION_MEM_FEATURE_MAIN MemFDMISupport3;
- #define MEM_MAIN_FEATURE_MEM_DMI MemFDMISupport3
- #else
- extern OPTION_MEM_FEATURE_MAIN MemFDMISupport2;
- #define MEM_MAIN_FEATURE_MEM_DMI MemFDMISupport2
- #endif
- #else
- #define MEM_MAIN_FEATURE_MEM_DMI MemMDefRet
- #endif
-
- #if (OPTION_DDR3 == TRUE)
- extern OPTION_MEM_FEATURE_NB MemFOnDimmThermal;
- extern OPTION_MEM_FEATURE_MAIN MemMLvDdr3;
- extern OPTION_MEM_FEATURE_NB MemFLvDdr3;
- #define MEM_FEATURE_ONDIMMTHERMAL MemFOnDimmThermal
- #define MEM_MAIN_FEATURE_LVDDR3 MemMLvDdr3
- #define MEM_FEATURE_LVDDR3 MemFLvDdr3
- #else
- #define MEM_FEATURE_ONDIMMTHERMAL MemFDefRet
- #define MEM_MAIN_FEATURE_LVDDR3 MemMDefRet
- #define MEM_FEATURE_LVDDR3 MemFDefRet
- #endif
-
- extern OPTION_MEM_FEATURE_NB MemFInterleaveRegion;
- #define MEM_FEATURE_REGION_INTERLEAVE MemFInterleaveRegion
-
- extern OPTION_MEM_FEATURE_MAIN MemMUmaAlloc;
- #define MEM_MAIN_FEATURE_UMAALLOC MemMUmaAlloc
-
- #if (OPTION_PARALLEL_TRAINING == TRUE)
- extern OPTION_MEM_FEATURE_MAIN MemMParallelTraining;
- #define MEM_MAIN_FEATURE_TRAINING MemMParallelTraining
- #else
- extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
- #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining
- #endif
-
- #if (OPTION_DIMM_EXCLUDE == TRUE)
- extern OPTION_MEM_FEATURE_MAIN MemMRASExcludeDIMM;
- #define MEM_MAIN_FEATURE_DIMM_EXCLUDE MemMRASExcludeDIMM
- extern OPTION_MEM_FEATURE_NB MemFRASExcludeDIMM;
- #define MEM_FEATURE_DIMM_EXCLUDE MemFRASExcludeDIMM
- #else
- #define MEM_FEATURE_DIMM_EXCLUDE MemFDefRet
- #define MEM_MAIN_FEATURE_DIMM_EXCLUDE MemMDefRet
- #endif
-
- /*----------------------------------------------------------------------------------
- * TECHNOLOGY BLOCK CONSTRUCTOR FUNCTION ASSIGNMENTS
- *
- *----------------------------------------------------------------------------------
- */
- #if OPTION_DDR2 == TRUE
- extern MEM_TECH_CONSTRUCTOR MemConstructTechBlock2;
- #define MEM_TECH_CONSTRUCTOR_DDR2 MemConstructTechBlock2,
- #if (OPTION_HW_DRAM_INIT == TRUE)
- extern MEM_TECH_FEAT MemTDramInitHw;
- #define MEM_TECH_FEATURE_HW_DRAMINIT MemTDramInitHw
- #else
- #define MEM_TECH_FEATURE_HW_DRAMINIT MemTFeatDef
- #endif
- #if (OPTION_SW_DRAM_INIT == TRUE)
- #define MEM_TECH_FEATURE_SW_DRAMINIT MemTFeatDef
- #else
- #define MEM_TECH_FEATURE_SW_DRAMINIT MemTFeatDef
- #endif
- #else
- #define MEM_TECH_CONSTRUCTOR_DDR2
- #endif
- #if OPTION_DDR3 == TRUE
- extern MEM_TECH_CONSTRUCTOR MemConstructTechBlock3;
- #define MEM_TECH_CONSTRUCTOR_DDR3 MemConstructTechBlock3,
- #if (OPTION_HW_DRAM_INIT == TRUE)
- extern MEM_TECH_FEAT MemTDramInitHw;
- #define MEM_TECH_FEATURE_HW_DRAMINIT MemTDramInitHw
- #else
- #define MEM_TECH_FEATURE_HW_DRAMINIT MemTFeatDef
- #endif
- #if (OPTION_SW_DRAM_INIT == TRUE)
- extern MEM_TECH_FEAT MemTDramInitSw3;
- #define MEM_TECH_FEATURE_SW_DRAMINIT MemTDramInitSw3
- #else
- #define MEM_TECH_FEATURE_SW_DRAMINIT MemTFeatDef
- #endif
- #else
- #define MEM_TECH_CONSTRUCTOR_DDR3
- #endif
-
- /*---------------------------------------------------------------------------------------------------
- * FEATURE BLOCKS
- *
- * This section instantiates a feature block structure for each memory controller installed
- * by the platform solution install file.
- *---------------------------------------------------------------------------------------------------
- */
-
- /*---------------------------------------------------------------------------------------------------
- * DEERHOUND FEATURE BLOCK
- *---------------------------------------------------------------------------------------------------
- */
- #if (OPTION_MEMCTLR_DR == TRUE)
- #if OPTION_DDR2
- #undef MEM_TECH_FEATURE_DRAMINIT
- #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
- #endif
- #if OPTION_DDR3
- #undef MEM_TECH_FEATURE_DRAMINIT
- #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
- #endif
-
- #undef MEM_TECH_FEATURE_CPG
- #define MEM_TECH_FEATURE_CPG MemFDefRet
-
- #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
- extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb;
- #undef MEM_TECH_FEATURE_HWRXEN
- #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb
- #else
- extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
- #undef MEM_TECH_FEATURE_HWRXEN
- #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb
- #endif
-
- #undef MEM_MAIN_FEATURE_TRAINING
- #undef MEM_FEATURE_TRAINING
- extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
- #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining
- extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
- #define MEM_FEATURE_TRAINING MemFStandardTraining
-
- MEM_FEAT_BLOCK_NB MemFeatBlockDr = {
- MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
- MEM_FEATURE_ONLINE_SPARE,
- MEM_FEATURE_BANK_INTERLEAVE,
- MEM_FEATURE_UNDO_BANK_INTERLEAVE,
- MEM_FEATURE_NODE_INTERLEAVE_CHECK,
- MEM_FEATURE_NODE_INTERLEAVE,
- MEM_FEATURE_CHANNEL_INTERLEAVE,
- MemFDefRet,
- MEM_FEATURE_CK_ECC,
- MEM_FEATURE_ECC,
- MEM_FEATURE_TRAINING,
- MEM_FEATURE_LVDDR3,
- MemFDefRet,
- MEM_TECH_FEATURE_DRAMINIT,
- MEM_FEATURE_DIMM_EXCLUDE,
- MemFDefRet,
- MEM_TECH_FEATURE_CPG,
- MEM_TECH_FEATURE_HWRXEN
- };
-
- #undef MEM_NB_SUPPORT_DR
- extern MEM_NB_CONSTRUCTOR MemConstructNBBlockDR;
- extern MEM_INITIALIZER MemNInitDefaultsDR;
-
-
- #define MEM_NB_SUPPORT_DR { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockDR, MemNInitDefaultsDR, &MemFeatBlockDr, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR, MEM_IDENDIMM_DR },
- #endif // OPTION_MEMCTRL_DR
-
- /*---------------------------------------------------------------------------------------------------
- * DASHOUND FEATURE BLOCK
- *---------------------------------------------------------------------------------------------------
- */
- #if (OPTION_MEMCTLR_DA == TRUE || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE)
- #if OPTION_DDR2
- #undef MEM_TECH_FEATURE_DRAMINIT
- #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
- #endif
- #if OPTION_DDR3
- #undef MEM_TECH_FEATURE_DRAMINIT
- #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
- #endif
-
- #undef MEM_TECH_FEATURE_CPG
- #define MEM_TECH_FEATURE_CPG MemFDefRet
-
- #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
- extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb;
- #undef MEM_TECH_FEATURE_HWRXEN
- #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb
- #else
- extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
- #undef MEM_TECH_FEATURE_HWRXEN
- #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb
- #endif
-
- #undef MEM_MAIN_FEATURE_TRAINING
- #undef MEM_FEATURE_TRAINING
- extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
- #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining
- extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
- #define MEM_FEATURE_TRAINING MemFStandardTraining
-
- #if (OPTION_MEMCTLR_Ni == TRUE)
- MEM_FEAT_BLOCK_NB MemFeatBlockNi = {
- MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
- MemFDefRet,
- MEM_FEATURE_BANK_INTERLEAVE,
- MEM_FEATURE_UNDO_BANK_INTERLEAVE,
- MemFDefRet,
- MemFDefRet,
- MEM_FEATURE_CHANNEL_INTERLEAVE,
- MEM_FEATURE_REGION_INTERLEAVE,
- MEM_FEATURE_CK_ECC,
- MEM_FEATURE_ECC,
- MEM_FEATURE_TRAINING,
- MEM_FEATURE_LVDDR3,
- MemFDefRet,
- MEM_TECH_FEATURE_DRAMINIT,
- MEM_FEATURE_DIMM_EXCLUDE,
- MemFDefRet,
- MEM_TECH_FEATURE_CPG,
- MEM_TECH_FEATURE_HWRXEN
- };
-
- #undef MEM_NB_SUPPORT_Ni
- extern MEM_NB_CONSTRUCTOR MemConstructNBBlockNi;
- extern MEM_INITIALIZER MemNInitDefaultsNi;
-
- #define MEM_NB_SUPPORT_Ni { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockNi, MemNInitDefaultsNi, &MemFeatBlockNi, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni, MEM_IDENDIMM_DA },
- #endif
-
- #if (OPTION_MEMCTLR_PH == TRUE)
- MEM_FEAT_BLOCK_NB MemFeatBlockPh = {
- MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
- MemFDefRet,
- MEM_FEATURE_BANK_INTERLEAVE,
- MEM_FEATURE_UNDO_BANK_INTERLEAVE,
- MemFDefRet,
- MemFDefRet,
- MEM_FEATURE_CHANNEL_INTERLEAVE,
- MEM_FEATURE_REGION_INTERLEAVE,
- MEM_FEATURE_CK_ECC,
- MEM_FEATURE_ECC,
- MEM_FEATURE_TRAINING,
- MEM_FEATURE_LVDDR3,
- MemFDefRet,
- MEM_TECH_FEATURE_DRAMINIT,
- MEM_FEATURE_DIMM_EXCLUDE,
- MemFDefRet,
- MEM_TECH_FEATURE_CPG,
- MEM_TECH_FEATURE_HWRXEN
- };
-
- #undef MEM_NB_SUPPORT_PH
- extern MEM_NB_CONSTRUCTOR MemConstructNBBlockPh;
- extern MEM_INITIALIZER MemNInitDefaultsPh;
-
- #define MEM_NB_SUPPORT_PH { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockPh, MemNInitDefaultsPh, &MemFeatBlockPh, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH, MEM_IDENDIMM_PH },
- #endif
-
- #if (OPTION_MEMCTLR_RB == TRUE)
- MEM_FEAT_BLOCK_NB MemFeatBlockRb = {
- MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
- MemFDefRet,
- MEM_FEATURE_BANK_INTERLEAVE,
- MEM_FEATURE_UNDO_BANK_INTERLEAVE,
- MemFDefRet,
- MemFDefRet,
- MEM_FEATURE_CHANNEL_INTERLEAVE,
- MEM_FEATURE_REGION_INTERLEAVE,
- MEM_FEATURE_CK_ECC,
- MEM_FEATURE_ECC,
- MEM_FEATURE_TRAINING,
- MEM_FEATURE_LVDDR3,
- MemFDefRet,
- MEM_TECH_FEATURE_DRAMINIT,
- MEM_FEATURE_DIMM_EXCLUDE,
- MemFDefRet,
- MEM_TECH_FEATURE_CPG,
- MEM_TECH_FEATURE_HWRXEN
- };
-
- #undef MEM_NB_SUPPORT_RB
- extern MEM_NB_CONSTRUCTOR MemConstructNBBlockRb;
- extern MEM_INITIALIZER MemNInitDefaultsRb;
-
- #define MEM_NB_SUPPORT_RB { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockRb, MemNInitDefaultsRb, &MemFeatBlockRb, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB, MEM_IDENDIMM_RB },
- #endif
-
- #if (OPTION_MEMCTLR_DA == TRUE)
- MEM_FEAT_BLOCK_NB MemFeatBlockDA = {
- MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
- MemFDefRet,
- MEM_FEATURE_BANK_INTERLEAVE,
- MEM_FEATURE_UNDO_BANK_INTERLEAVE,
- MemFDefRet,
- MemFDefRet,
- MEM_FEATURE_CHANNEL_INTERLEAVE,
- MEM_FEATURE_REGION_INTERLEAVE,
- MEM_FEATURE_CK_ECC,
- MEM_FEATURE_ECC,
- MEM_FEATURE_TRAINING,
- MEM_FEATURE_LVDDR3,
- MemFDefRet,
- MEM_TECH_FEATURE_DRAMINIT,
- MEM_FEATURE_DIMM_EXCLUDE,
- MemFDefRet,
- MEM_TECH_FEATURE_CPG,
- MEM_TECH_FEATURE_HWRXEN
- };
-
- #undef MEM_NB_SUPPORT_DA
- extern MEM_NB_CONSTRUCTOR MemConstructNBBlockDA;
- extern MEM_INITIALIZER MemNInitDefaultsDA;
-
- #define MEM_NB_SUPPORT_DA { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockDA, MemNInitDefaultsDA, &MemFeatBlockDA, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA, MEM_IDENDIMM_DA },
- #endif
- #endif // OPTION_MEMCTRL_DA
-
- /*---------------------------------------------------------------------------------------------------
- * HYDRA FEATURE BLOCK
- *---------------------------------------------------------------------------------------------------
- */
- #if (OPTION_MEMCTLR_HY == TRUE)
- #if OPTION_DDR2
- #undef MEM_TECH_FEATURE_DRAMINIT
- #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
- #endif
- #if OPTION_DDR3
- #undef MEM_TECH_FEATURE_DRAMINIT
- #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
- #endif
-
- #undef MEM_TECH_FEATURE_CPG
- #define MEM_TECH_FEATURE_CPG MemFDefRet
-
- #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
- extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb;
- #undef MEM_TECH_FEATURE_HWRXEN
- #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb
- #else
- extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
- #undef MEM_TECH_FEATURE_HWRXEN
- #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb
- #endif
-
-
- #undef MEM_MAIN_FEATURE_TRAINING
- #undef MEM_FEATURE_TRAINING
- extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
- #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining
- extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
- #define MEM_FEATURE_TRAINING MemFStandardTraining
-
- MEM_FEAT_BLOCK_NB MemFeatBlockHy = {
- MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
- MEM_FEATURE_ONLINE_SPARE,
- MEM_FEATURE_BANK_INTERLEAVE,
- MEM_FEATURE_UNDO_BANK_INTERLEAVE,
- MEM_FEATURE_NODE_INTERLEAVE_CHECK,
- MEM_FEATURE_NODE_INTERLEAVE,
- MEM_FEATURE_CHANNEL_INTERLEAVE,
- MemFDefRet,
- MEM_FEATURE_CK_ECC,
- MEM_FEATURE_ECC,
- MEM_FEATURE_TRAINING,
- MEM_FEATURE_LVDDR3,
- MEM_FEATURE_ONDIMMTHERMAL,
- MEM_TECH_FEATURE_DRAMINIT,
- MEM_FEATURE_DIMM_EXCLUDE,
- MemFDefRet,
- MEM_TECH_FEATURE_CPG,
- MEM_TECH_FEATURE_HWRXEN
- };
-
- #undef MEM_NB_SUPPORT_HY
- extern MEM_NB_CONSTRUCTOR MemConstructNBBlockHY;
- extern MEM_INITIALIZER MemNInitDefaultsHY;
- #define MEM_NB_SUPPORT_HY { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockHY, MemNInitDefaultsHY, &MemFeatBlockHy, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY, MEM_IDENDIMM_HY },
- #endif // OPTION_MEMCTRL_HY
- /*---------------------------------------------------------------------------------------------------
- * LLANO FEATURE BLOCK
- *---------------------------------------------------------------------------------------------------
- */
- #if (OPTION_MEMCTLR_LN == TRUE)
- #if OPTION_DDR2
- #undef MEM_TECH_FEATURE_DRAMINIT
- #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
- #endif
- #if OPTION_DDR3
- #undef MEM_TECH_FEATURE_DRAMINIT
- #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
- #endif
-
- #if (OPTION_EARLY_SAMPLES == TRUE)
- extern OPTION_MEM_FEATURE_NB MemNInitEarlySampleSupportLN;
- #define MEM_EARLY_SAMPLE_SUPPORT MemNInitEarlySampleSupportLN
- #else
- #define MEM_EARLY_SAMPLE_SUPPORT MemFDefRet
- #endif
-
- #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE)
- extern OPTION_MEM_FEATURE_NB MemNInitCPGClientNb;
- #undef MEM_TECH_FEATURE_CPG
- #define MEM_TECH_FEATURE_CPG MemNInitCPGClientNb
- #else
- #undef MEM_TECH_FEATURE_CPG
- #define MEM_TECH_FEATURE_CPG MemFDefRet
- #endif
-
- #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
- extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb;
- #undef MEM_TECH_FEATURE_HWRXEN
- #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb
- #else
- extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
- #undef MEM_TECH_FEATURE_HWRXEN
- #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb
- #endif
-
- #undef MEM_MAIN_FEATURE_TRAINING
- #undef MEM_FEATURE_TRAINING
- extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
- #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining
- extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
- #define MEM_FEATURE_TRAINING MemFStandardTraining
-
- MEM_FEAT_BLOCK_NB MemFeatBlockLn = {
- MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
- MemFDefRet,
- MEM_FEATURE_BANK_INTERLEAVE,
- MEM_FEATURE_UNDO_BANK_INTERLEAVE,
- MemFDefRet,
- MemFDefRet,
- MEM_FEATURE_CHANNEL_INTERLEAVE,
- MEM_FEATURE_REGION_INTERLEAVE,
- MEM_FEATURE_CK_ECC,
- MemFDefRet,
- MEM_FEATURE_TRAINING,
- MEM_FEATURE_LVDDR3,
- MEM_FEATURE_ONDIMMTHERMAL,
- MEM_TECH_FEATURE_DRAMINIT,
- MEM_FEATURE_DIMM_EXCLUDE,
- MEM_EARLY_SAMPLE_SUPPORT,
- MEM_TECH_FEATURE_CPG,
- MEM_TECH_FEATURE_HWRXEN
- };
- #undef MEM_NB_SUPPORT_LN
- extern MEM_NB_CONSTRUCTOR MemConstructNBBlockLN;
- extern MEM_INITIALIZER MemNInitDefaultsLN;
- #define MEM_NB_SUPPORT_LN { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockLN, MemNInitDefaultsLN, &MemFeatBlockLn, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN, MEM_IDENDIMM_LN },
-
- #endif // OPTION_MEMCTRL_LN
-
- /*---------------------------------------------------------------------------------------------------
- * ONTARIO FEATURE BLOCK
- *---------------------------------------------------------------------------------------------------
- */
- #if (OPTION_MEMCTLR_ON == TRUE)
- #if OPTION_DDR2
- #undef MEM_TECH_FEATURE_DRAMINIT
- #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
- #endif
- #if OPTION_DDR3
- #undef MEM_TECH_FEATURE_DRAMINIT
- #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
- #endif
-
- #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE)
- extern OPTION_MEM_FEATURE_NB MemNInitCPGClientNb;
- #undef MEM_TECH_FEATURE_CPG
- #define MEM_TECH_FEATURE_CPG MemNInitCPGClientNb
- #else
- #undef MEM_TECH_FEATURE_CPG
- #define MEM_TECH_FEATURE_CPG MemFDefRet
- #endif
-
- #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
- extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb;
- #undef MEM_TECH_FEATURE_HWRXEN
- #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb
- #else
- extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
- #undef MEM_TECH_FEATURE_HWRXEN
- #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb
- #endif
-
- #undef MEM_MAIN_FEATURE_TRAINING
- #undef MEM_FEATURE_TRAINING
- extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
- #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining
- extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
- #define MEM_FEATURE_TRAINING MemFStandardTraining
-
- #if (OPTION_EARLY_SAMPLES == TRUE)
- extern OPTION_MEM_FEATURE_NB MemNInitEarlySampleSupportON;
- #define MEM_EARLY_SAMPLE_SUPPORT MemNInitEarlySampleSupportON
- #else
- #define MEM_EARLY_SAMPLE_SUPPORT MemFDefRet
- #endif
-
- MEM_FEAT_BLOCK_NB MemFeatBlockOn = {
- MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
- MemFDefRet,
- MEM_FEATURE_BANK_INTERLEAVE,
- MEM_FEATURE_UNDO_BANK_INTERLEAVE,
- MemFDefRet,
- MemFDefRet,
- MemFDefRet,
- MemFDefRet,
- MemFDefRet,
- MemFDefRet,
- MEM_FEATURE_TRAINING,
- MEM_FEATURE_LVDDR3,
- MEM_FEATURE_ONDIMMTHERMAL,
- MEM_TECH_FEATURE_DRAMINIT,
- MEM_FEATURE_DIMM_EXCLUDE,
- MEM_EARLY_SAMPLE_SUPPORT,
- MEM_TECH_FEATURE_CPG,
- MEM_TECH_FEATURE_HWRXEN
- };
-
- #undef MEM_NB_SUPPORT_ON
- extern MEM_NB_CONSTRUCTOR MemConstructNBBlockON;
- extern MEM_INITIALIZER MemNInitDefaultsON;
- #define MEM_NB_SUPPORT_ON { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockON, MemNInitDefaultsON, &MemFeatBlockOn, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON, MEM_IDENDIMM_ON },
-
- #endif // OPTION_MEMCTRL_ON
-
- /*---------------------------------------------------------------------------------------------------
- * OROCHI FEATURE BLOCK
- *---------------------------------------------------------------------------------------------------
- */
- #if (OPTION_MEMCTLR_OR == TRUE)
- #if OPTION_DDR2
- #undef MEM_TECH_FEATURE_DRAMINIT
- #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
- #endif
- #if OPTION_DDR3
- #undef MEM_MAIN_FEATURE_LVDDR3
- extern OPTION_MEM_FEATURE_MAIN MemMLvDdr3PerformanceEnhPre;
- #define MEM_MAIN_FEATURE_LVDDR3 MemMLvDdr3PerformanceEnhPre
- #undef MEM_TECH_FEATURE_DRAMINIT
- #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
- #endif
-
- #if (OPTION_EARLY_SAMPLES == TRUE)
- extern OPTION_MEM_FEATURE_NB MemNInitEarlySampleSupportOr;
- #define MEM_EARLY_SAMPLE_SUPPORT MemNInitEarlySampleSupportOr
- #else
- #define MEM_EARLY_SAMPLE_SUPPORT MemFDefRet
- #endif
-
- #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE)
- extern OPTION_MEM_FEATURE_NB MemNInitCPGUnb;
- #undef MEM_TECH_FEATURE_CPG
- #define MEM_TECH_FEATURE_CPG MemNInitCPGUnb
- #else
- #undef MEM_TECH_FEATURE_CPG
- #define MEM_TECH_FEATURE_CPG MemFDefRet
- #endif
-
- #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
- extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb;
- #undef MEM_TECH_FEATURE_HWRXEN
- #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb
- #else
- extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
- #undef MEM_TECH_FEATURE_HWRXEN
- #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb
- #endif
-
-
- #undef MEM_MAIN_FEATURE_TRAINING
- #undef MEM_FEATURE_TRAINING
- extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
- #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining
- extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
- #define MEM_FEATURE_TRAINING MemFStandardTraining
-
- MEM_FEAT_BLOCK_NB MemFeatBlockOr = {
- MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
- MEM_FEATURE_ONLINE_SPARE,
- MEM_FEATURE_BANK_INTERLEAVE,
- MEM_FEATURE_UNDO_BANK_INTERLEAVE,
- MEM_FEATURE_NODE_INTERLEAVE_CHECK,
- MEM_FEATURE_NODE_INTERLEAVE,
- MEM_FEATURE_CHANNEL_INTERLEAVE,
- MemFDefRet,
- MEM_FEATURE_CK_ECC,
- MEM_FEATURE_ECC,
- MEM_FEATURE_TRAINING,
- MEM_FEATURE_LVDDR3,
- MEM_FEATURE_ONDIMMTHERMAL,
- MEM_TECH_FEATURE_DRAMINIT,
- MEM_FEATURE_DIMM_EXCLUDE,
- MEM_EARLY_SAMPLE_SUPPORT,
- MEM_TECH_FEATURE_CPG,
- MEM_TECH_FEATURE_HWRXEN
- };
-
- #undef MEM_NB_SUPPORT_OR
- extern MEM_NB_CONSTRUCTOR MemConstructNBBlockOR;
- extern MEM_INITIALIZER MemNInitDefaultsOR;
- #define MEM_NB_SUPPORT_OR { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockOR, MemNInitDefaultsOR, &MemFeatBlockOr, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR, MEM_IDENDIMM_OR },
- #endif // OPTION_MEMCTRL_OR
-
- /*---------------------------------------------------------------------------------------------------
- * C32 FEATURE BLOCK
- *---------------------------------------------------------------------------------------------------
- */
- #if (OPTION_MEMCTLR_C32 == TRUE)
- #if OPTION_DDR2
- #undef MEM_TECH_FEATURE_DRAMINIT
- #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
- #endif
- #if OPTION_DDR3
- #undef MEM_TECH_FEATURE_DRAMINIT
- #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
- #endif
-
- #undef MEM_TECH_FEATURE_CPG
- #define MEM_TECH_FEATURE_CPG MemFDefRet
-
- #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
- extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb;
- #undef MEM_TECH_FEATURE_HWRXEN
- #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb
- #else
- extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
- #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb
- #endif
-
- #undef MEM_MAIN_FEATURE_TRAINING
- #undef MEM_FEATURE_TRAINING
- extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
- #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining
- extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
- #define MEM_FEATURE_TRAINING MemFStandardTraining
-
- MEM_FEAT_BLOCK_NB MemFeatBlockC32 = {
- MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
- MEM_FEATURE_ONLINE_SPARE,
- MEM_FEATURE_BANK_INTERLEAVE,
- MEM_FEATURE_UNDO_BANK_INTERLEAVE,
- MEM_FEATURE_NODE_INTERLEAVE_CHECK,
- MEM_FEATURE_NODE_INTERLEAVE,
- MEM_FEATURE_CHANNEL_INTERLEAVE,
- MemFDefRet,
- MEM_FEATURE_CK_ECC,
- MEM_FEATURE_ECC,
- MEM_FEATURE_TRAINING,
- MEM_FEATURE_LVDDR3,
- MEM_FEATURE_ONDIMMTHERMAL,
- MEM_TECH_FEATURE_DRAMINIT,
- MEM_FEATURE_DIMM_EXCLUDE,
- MemFDefRet,
- MEM_TECH_FEATURE_CPG,
- MEM_TECH_FEATURE_HWRXEN
- };
-
- #undef MEM_NB_SUPPORT_C32
- extern MEM_NB_CONSTRUCTOR MemConstructNBBlockC32;
- extern MEM_INITIALIZER MemNInitDefaultsC32;
- #define MEM_NB_SUPPORT_C32 { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockC32, MemNInitDefaultsC32, &MemFeatBlockC32, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32, MEM_IDENDIMM_C32 },
- #endif // OPTION_MEMCTRL_C32
-
- /*---------------------------------------------------------------------------------------------------
- * MAIN FEATURE BLOCK
- *---------------------------------------------------------------------------------------------------
- */
- MEM_FEAT_BLOCK_MAIN MemFeatMain = {
- MEM_FEAT_BLOCK_MAIN_STRUCT_VERSION,
- MEM_MAIN_FEATURE_TRAINING,
- MEM_MAIN_FEATURE_DIMM_EXCLUDE,
- MEM_MAIN_FEATURE_ONLINE_SPARE,
- MEM_MAIN_FEATURE_NODE_INTERLEAVE,
- MEM_MAIN_FEATURE_ECC,
- MEM_MAIN_FEATURE_MEM_CLEAR,
- MEM_MAIN_FEATURE_MEM_DMI,
- MEM_MAIN_FEATURE_LVDDR3,
- MEM_MAIN_FEATURE_UMAALLOC,
- MEM_MAIN_FEATURE_MEM_SAVE,
- MEM_MAIN_FEATURE_MEM_RESTORE
- };
-
-
- /*---------------------------------------------------------------------------------------------------
- * Technology Training SPECIFIC CONFIGURATION
- *
- *
- *---------------------------------------------------------------------------------------------------
- */
- #define MEM_TECH_TRAINING_FEAT_NULL_TERNMIATOR 0
- #if OPTION_MEMCTLR_DR
- extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDr;
- #if OPTION_DDR2
- #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
- #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
- #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTDqsTrainRcvrEnHwPass1
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTDqsTrainRcvrEnHwPass2
- #else
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTTrainRcvrEnSwPass1
- #else
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #endif
- #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #else
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTTrainDQSEdgeDetectSw
- #else
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #endif
- #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #else
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #endif
- #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
- #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTTrainMaxLatency
- #else
- #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
- #endif
- MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2Dr = {
- MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
- TECH_TRAIN_ENTER_HW_TRN_DDR2,
- TECH_TRAIN_SW_WL_DDR2,
- TECH_TRAIN_HW_WL_P1_DDR2,
- TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_HW_WL_P2_DDR2,
- TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
- TECH_TRAIN_EXIT_HW_TRN_DDR2,
- TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
- TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
- TECH_TRAIN_MAX_RD_LAT_DDR2
- };
- extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb;
- #define NB_TRAIN_FLOW_DDR2 MemNDQSTiming2Nb
- extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb;
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceDr, &memTechTrainingFeatSequenceDDR2Dr },
- #else
- #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
- #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
- #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
- #if OPTION_DDR3
- #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
- #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining
- #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
- #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining
- #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
- #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1
- #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2
- #else
- #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
- #endif
- #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
- #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
- #else
- #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
- #endif
- #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTDqsTrainRcvrEnHwPass1
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTDqsTrainRcvrEnHwPass2
- #else
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1
- #else
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #endif
- #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1
- #else
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw
- #else
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #endif
- #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw
- #else
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #endif
- #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
- #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency
- #else
- #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
- #endif
- extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
- #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb
- extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
- extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDr;
- MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3Dr = {
- MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
- TECH_TRAIN_ENTER_HW_TRN_DDR3,
- TECH_TRAIN_SW_WL_DDR3,
- TECH_TRAIN_HW_WL_P1_DDR3,
- TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_HW_WL_P2_DDR3,
- TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
- TECH_TRAIN_EXIT_HW_TRN_DDR3,
- TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
- TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
- TECH_TRAIN_MAX_RD_LAT_DDR3
- };
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceDr, &memTechTrainingFeatSequenceDDR3Dr },
- #else
- #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
- #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
- #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
- #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
- #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
- #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
- #else
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
-
- #if (OPTION_MEMCTLR_DA || OPTION_MEMCTLR_Ni || OPTION_MEMCTLR_PH || OPTION_MEMCTLR_RB)
- #if OPTION_DDR2
- #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
- #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
- #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTDqsTrainRcvrEnHwPass1
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTDqsTrainRcvrEnHwPass2
- #else
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTTrainRcvrEnSwPass1
- #else
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #endif
- #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #else
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTTrainDQSEdgeDetectSw
- #else
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #endif
- #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #else
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #endif
- #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
- #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTTrainMaxLatency
- #else
- #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
- #endif
- MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2DA = {
- MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
- TECH_TRAIN_ENTER_HW_TRN_DDR2,
- TECH_TRAIN_SW_WL_DDR2,
- TECH_TRAIN_HW_WL_P1_DDR2,
- TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_HW_WL_P2_DDR2,
- TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
- TECH_TRAIN_EXIT_HW_TRN_DDR2,
- TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
- TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
- TECH_TRAIN_MAX_RD_LAT_DDR2
- };
- MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2PH = {
- MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
- TECH_TRAIN_ENTER_HW_TRN_DDR2,
- TECH_TRAIN_SW_WL_DDR2,
- TECH_TRAIN_HW_WL_P1_DDR2,
- TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_HW_WL_P2_DDR2,
- TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
- TECH_TRAIN_EXIT_HW_TRN_DDR2,
- TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
- TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
- TECH_TRAIN_MAX_RD_LAT_DDR2
- };
- MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2Rb = {
- MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
- TECH_TRAIN_ENTER_HW_TRN_DDR2,
- TECH_TRAIN_SW_WL_DDR2,
- TECH_TRAIN_HW_WL_P1_DDR2,
- TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_HW_WL_P2_DDR2,
- TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
- TECH_TRAIN_EXIT_HW_TRN_DDR2,
- TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
- TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
- TECH_TRAIN_MAX_RD_LAT_DDR2
- };
- MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2Ni = {
- MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
- TECH_TRAIN_ENTER_HW_TRN_DDR2,
- TECH_TRAIN_SW_WL_DDR2,
- TECH_TRAIN_HW_WL_P1_DDR2,
- TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_HW_WL_P2_DDR2,
- TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
- TECH_TRAIN_EXIT_HW_TRN_DDR2,
- TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
- TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
- TECH_TRAIN_MAX_RD_LAT_DDR2
- };
- extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb;
- #define NB_TRAIN_FLOW_DDR2 MemNDQSTiming2Nb
- extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb;
- #if (OPTION_MEMCTLR_DA)
- extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDA
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceDA, &memTechTrainingFeatSequenceDDR2DA },
- #else
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
- #if (OPTION_MEMCTLR_PH)
- extern OPTION_MEM_FEATURE_NB memNEnableTrainSequencePh
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequencePh, &memTechTrainingFeatSequenceDDR2PH },
- #else
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
- #if (OPTION_MEMCTLR_RB)
- extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceRb
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceRb, &memTechTrainingFeatSequenceDDR2Rb },
- #else
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
-
- #if (OPTION_MEMCTLR_Ni)
- extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceNi
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceNi, &memTechTrainingFeatSequenceDDR2Ni },
- #else
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
- #else
- #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
- #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
- #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
- #if OPTION_DDR3
- #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
- #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining
- #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
- #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining
- #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
- #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1
- #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2
- #else
- #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
- #endif
- #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
- #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
- #else
- #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
- #endif
- #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTDqsTrainRcvrEnHwPass1
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTDqsTrainRcvrEnHwPass2
- #else
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1
- #else
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #endif
- #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1
- #else
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw
- #else
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #endif
- #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw
- #else
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #endif
- #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
- #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency
- #else
- #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
- #endif
- MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3DA = {
- MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
- TECH_TRAIN_ENTER_HW_TRN_DDR3,
- TECH_TRAIN_SW_WL_DDR3,
- TECH_TRAIN_HW_WL_P1_DDR3,
- TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_HW_WL_P2_DDR3,
- TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
- TECH_TRAIN_EXIT_HW_TRN_DDR3,
- TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
- TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
- TECH_TRAIN_MAX_RD_LAT_DDR3
- };
- MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3Ph = {
- MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
- TECH_TRAIN_ENTER_HW_TRN_DDR3,
- TECH_TRAIN_SW_WL_DDR3,
- TECH_TRAIN_HW_WL_P1_DDR3,
- TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_HW_WL_P2_DDR3,
- TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
- TECH_TRAIN_EXIT_HW_TRN_DDR3,
- TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
- TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
- TECH_TRAIN_MAX_RD_LAT_DDR3
- };
- MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3Rb = {
- MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
- TECH_TRAIN_ENTER_HW_TRN_DDR3,
- TECH_TRAIN_SW_WL_DDR3,
- TECH_TRAIN_HW_WL_P1_DDR3,
- TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_HW_WL_P2_DDR3,
- TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
- TECH_TRAIN_EXIT_HW_TRN_DDR3,
- TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
- TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
- TECH_TRAIN_MAX_RD_LAT_DDR3
- };
- MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3Ni = {
- MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
- TECH_TRAIN_ENTER_HW_TRN_DDR3,
- TECH_TRAIN_SW_WL_DDR3,
- TECH_TRAIN_HW_WL_P1_DDR3,
- TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_HW_WL_P2_DDR3,
- TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
- TECH_TRAIN_EXIT_HW_TRN_DDR3,
- TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
- TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
- TECH_TRAIN_MAX_RD_LAT_DDR3
- };
- extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
- #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb
- extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
- #if (OPTION_MEMCTLR_DA)
- extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDA;
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceDA, &memTechTrainingFeatSequenceDDR3DA },
- #else
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
- #if (OPTION_MEMCTLR_PH)
- extern OPTION_MEM_FEATURE_NB memNEnableTrainSequencePh;
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequencePh, &memTechTrainingFeatSequenceDDR3Ph },
- #else
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
- #if (OPTION_MEMCTLR_RB)
- extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceRb;
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceRb, &memTechTrainingFeatSequenceDDR3Rb },
- #else
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
- #if (OPTION_MEMCTLR_Ni)
- extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceNi;
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceNi, &memTechTrainingFeatSequenceDDR3Ni },
- #else
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
- #else
- #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
- #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
- #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
- #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
- #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
- #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
- #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
- #else
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
-
- #if OPTION_MEMCTLR_HY
- extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceHy;
- #if OPTION_DDR2
- #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
- #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
- #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTDqsTrainRcvrEnHwPass1
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTDqsTrainRcvrEnHwPass2
- #else
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTTrainRcvrEnSwPass1
- #else
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #endif
- #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #else
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTTrainDQSEdgeDetectSw
- #else
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #endif
- #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #else
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #endif
- #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
- #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTTrainMaxLatency
- #else
- #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
- #endif
- MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2Hy = {
- MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
- TECH_TRAIN_ENTER_HW_TRN_DDR2,
- TECH_TRAIN_SW_WL_DDR2,
- TECH_TRAIN_HW_WL_P1_DDR2,
- TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_HW_WL_P2_DDR2,
- TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
- TECH_TRAIN_EXIT_HW_TRN_DDR2,
- TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
- TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
- TECH_TRAIN_MAX_RD_LAT_DDR2
- };
- extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb;
- #define NB_TRAIN_FLOW_DDR2 MemNDQSTiming2Nb
- extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb;
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceHy, &memTechTrainingFeatSequenceDDR2Hy },
- #else
- #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
- #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
- #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
- #if OPTION_DDR3
- #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
- #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining
- #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
- #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining
- #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
- #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1
- #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2
- #else
- #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
- #endif
- #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
- #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
- #else
- #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
- #endif
- #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
- #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
- #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
- #endif
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
- #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
- #endif
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
- #else
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1
- #else
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #endif
- #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1
- #else
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw
- #else
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #endif
- #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw
- #else
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #endif
- #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
- #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency
- #else
- #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
- #endif
- MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3Hy = {
- MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
- TECH_TRAIN_ENTER_HW_TRN_DDR3,
- TECH_TRAIN_SW_WL_DDR3,
- TECH_TRAIN_HW_WL_P1_DDR3,
- TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_HW_WL_P2_DDR3,
- TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
- TECH_TRAIN_EXIT_HW_TRN_DDR3,
- TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
- TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
- TECH_TRAIN_MAX_RD_LAT_DDR3
- };
- extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
- #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb
- extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceHy, &memTechTrainingFeatSequenceDDR3Hy },
- #else
- #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
- #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
- #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
- #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
- #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
- #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
- #else
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
-
- #if OPTION_MEMCTLR_C32
- extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceC32;
- #if OPTION_DDR2
- #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
- #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
- #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTDqsTrainRcvrEnHwPass1
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTDqsTrainRcvrEnHwPass2
- #else
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTTrainRcvrEnSwPass1
- #else
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #endif
- #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #else
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTTrainDQSEdgeDetectSw
- #else
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #endif
- #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #else
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #endif
- #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
- #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTTrainMaxLatency
- #else
- #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
- #endif
- MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2C32 = {
- MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
- TECH_TRAIN_ENTER_HW_TRN_DDR2,
- TECH_TRAIN_SW_WL_DDR2,
- TECH_TRAIN_HW_WL_P1_DDR2,
- TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_HW_WL_P2_DDR2,
- TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
- TECH_TRAIN_EXIT_HW_TRN_DDR2,
- TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
- TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
- TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
- TECH_TRAIN_MAX_RD_LAT_DDR2
- };
- extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb;
- #define NB_TRAIN_FLOW_DDR2 MemNDQSTiming2Nb
- extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb;
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32 {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceC32, &memTechTrainingFeatSequenceDDR2C32 },
- #else
- #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
- #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
- #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32 { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
- #if OPTION_DDR3
- #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
- #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining
- #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
- #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining
- #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
- #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1
- #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2
- #else
- #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
- #endif
- #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
- #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
- #else
- #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
- #endif
- #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
- #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
- #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
- #endif
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTDqsTrainRcvrEnHwPass1
- #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
- #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
- #endif
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTDqsTrainRcvrEnHwPass2
- #else
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1
- #else
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #endif
- #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1
- #else
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw
- #else
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #endif
- #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw
- #else
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #endif
- #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
- #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency
- #else
- #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
- #endif
- MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3C32 = {
- MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
- TECH_TRAIN_ENTER_HW_TRN_DDR3,
- TECH_TRAIN_SW_WL_DDR3,
- TECH_TRAIN_HW_WL_P1_DDR3,
- TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_HW_WL_P2_DDR3,
- TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
- TECH_TRAIN_EXIT_HW_TRN_DDR3,
- TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
- TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
- TECH_TRAIN_MAX_RD_LAT_DDR3
- };
- extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
- #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb
- extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceC32, &memTechTrainingFeatSequenceDDR3C32 },
- #else
- #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
- #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
- #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
- #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
- #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
- #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
- #else
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32 { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
-
-
- #if OPTION_MEMCTLR_LN
- #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
- #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
- #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_LN { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceLN;
- #if OPTION_DDR3
- #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
- #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
- #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
- #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTrainingClient3
- #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
- #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1
- #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2
- #else
- #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
- #endif
- #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
- #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTDqsTrainRcvrEnHwPass1
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTDqsTrainRcvrEnHwPass2
- #else
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1
- #else
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #endif
- #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1
- #else
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw
- #else
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #endif
- #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw
- #else
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #endif
- #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
- #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency
- #else
- #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
- #endif
- MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3LN = {
- MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
- TECH_TRAIN_ENTER_HW_TRN_DDR3,
- TECH_TRAIN_SW_WL_DDR3,
- TECH_TRAIN_HW_WL_P1_DDR3,
- TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_HW_WL_P2_DDR3,
- TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
- TECH_TRAIN_EXIT_HW_TRN_DDR3,
- TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
- TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
- TECH_TRAIN_MAX_RD_LAT_DDR3
- };
- extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
- #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb
- extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_LN {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceLN, &memTechTrainingFeatSequenceDDR3LN },
- #else
- #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
- #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
- #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
- #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
- #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
- #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_LN { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
- #else
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_LN { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_LN { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
-
-
- #if OPTION_MEMCTLR_OR
- extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceOr;
- #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
- #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
- #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #if OPTION_DDR3
- #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
- #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining
- #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
- #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining
- #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
- #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1
- #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2
- #else
- #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
- #endif
- #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
- #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
- #else
- #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
- #endif
- #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
- #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
- #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
- #endif
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTDqsTrainRcvrEnHwPass1
- #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
- #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
- #endif
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTDqsTrainRcvrEnHwPass2
- #else
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #else
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #endif
- #undef TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3
- #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #else
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw
- #else
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #endif
- #undef TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3
- #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw
- #else
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #endif
- #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
- #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency
- #else
- #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
- #endif
- MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3OR = {
- MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
- TECH_TRAIN_ENTER_HW_TRN_DDR3,
- TECH_TRAIN_SW_WL_DDR3,
- TECH_TRAIN_HW_WL_P1_DDR3,
- TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_HW_WL_P2_DDR3,
- TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
- TECH_TRAIN_EXIT_HW_TRN_DDR3,
- TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
- TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
- TECH_TRAIN_MAX_RD_LAT_DDR3
- };
- extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
- #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb
- extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceOr, &memTechTrainingFeatSequenceDDR3OR },
- #else
- #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
- #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
- #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
- #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
- #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
- #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
- #else
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
-
-
- #if OPTION_MEMCTLR_ON
- extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceON;
- #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
- #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
- #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
- #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_ON { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #if OPTION_DDR3
- #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
- #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
- #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
- #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTrainingClient3
- #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
- #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1
- #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2
- #else
- #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
- #endif
- #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
- #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTDqsTrainRcvrEnHwPass1
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTDqsTrainRcvrEnHwPass2
- #else
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1
- #else
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #endif
- #undef TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3
- #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1
- #else
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #endif
- #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw
- #else
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #endif
- #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw
- #else
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #endif
- #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
- #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency
- #else
- #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
- #endif
- MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3ON = {
- MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
- TECH_TRAIN_ENTER_HW_TRN_DDR3,
- TECH_TRAIN_SW_WL_DDR3,
- TECH_TRAIN_HW_WL_P1_DDR3,
- TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_HW_WL_P2_DDR3,
- TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
- TECH_TRAIN_EXIT_HW_TRN_DDR3,
- TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
- TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
- TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
- TECH_TRAIN_MAX_RD_LAT_DDR3
- };
- extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
- #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb
- extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceON, &memTechTrainingFeatSequenceDDR3ON },
- #else
- #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
- #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
- #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
- #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
- #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
- #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
- #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
- #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
- #else
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_ON { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
- #endif
-
- #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0 }
- MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = {
- MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR
- MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA
- MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY
- MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_LN
- MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32
- MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_ON
- MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni
- MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR
- MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH
- MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB
- MEM_TECH_ENABLE_TRAINING_SEQUENCE_END
- };
-
- MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = {
- MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR
- MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA
- MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY
- MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_LN
- MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32
- MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON
- MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni
- MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR
- MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH
- MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB
- MEM_TECH_ENABLE_TRAINING_SEQUENCE_END
- };
- /*---------------------------------------------------------------------------------------------------
- * NB TRAINING FLOW CONTROL
- *
- *
- *---------------------------------------------------------------------------------------------------
- */
- OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = { // Training flow control
- NB_TRAIN_FLOW_DDR2,
- NB_TRAIN_FLOW_DDR3,
- };
- /*---------------------------------------------------------------------------------------------------
- * TECHNOLOGY BLOCK
- *
- *
- *---------------------------------------------------------------------------------------------------
- */
- MEM_TECH_CONSTRUCTOR* memTechInstalled[] = { // Types of technology installed
- MEM_TECH_CONSTRUCTOR_DDR2
- MEM_TECH_CONSTRUCTOR_DDR3
- NULL
- };
- /*---------------------------------------------------------------------------------------------------
- * PLATFORM SPECIFIC BLOCK FORM FACTOR DEFINITION
- *
- *
- *---------------------------------------------------------------------------------------------------
- */
- #if OPTION_MEMCTLR_HY
- #if OPTION_UDIMMS
- #if OPTION_DDR2
- #define PLAT_SP_HY_FF_UDIMM2 MemPConstructPsUDef,
- #else
- #define PLAT_SP_HY_FF_UDIMM2 MemPConstructPsUDef,
- #endif
- #if OPTION_DDR3
- #define PLAT_SP_HY_FF_UDIMM3 MemPConstructPsUHy3,
- #else
- #define PLAT_SP_HY_FF_UDIMM3 MemPConstructPsUDef,
- #endif
- #else
- #define PLAT_SP_HY_FF_UDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_HY_FF_UDIMM3 MemPConstructPsUDef,
- #endif
- #if OPTION_RDIMMS
- #if OPTION_DDR2
- #define PLAT_SP_HY_FF_RDIMM2 MemPConstructPsUDef,
- #else
- #define PLAT_SP_HY_FF_RDIMM2 MemPConstructPsUDef,
- #endif
- #if OPTION_DDR3
- #define PLAT_SP_HY_FF_RDIMM3 MemPConstructPsRHy3,
- #else
- #define PLAT_SP_HY_FF_RDIMM3 MemPConstructPsUDef,
- #endif
- #else
- #define PLAT_SP_HY_FF_RDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_HY_FF_RDIMM3 MemPConstructPsUDef,
- #endif
- #if OPTION_SODIMMS
- #if OPTION_DDR2
- #define PLAT_SP_HY_FF_SDIMM2 MemPConstructPsUDef,
- #else
- #define PLAT_SP_HY_FF_SDIMM2 MemPConstructPsUDef,
- #endif
- #if OPTION_DDR3
- #define PLAT_SP_HY_FF_SDIMM3 MemPConstructPsSHy3,
- #else
- #define PLAT_SP_HY_FF_SDIMM3 MemPConstructPsUDef,
- #endif
- #else
- #define PLAT_SP_HY_FF_SDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_HY_FF_SDIMM3 MemPConstructPsUDef,
- #endif
- #else
- #define PLAT_SP_HY_FF_SDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_HY_FF_RDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_HY_FF_UDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_HY_FF_SDIMM3 MemPConstructPsUDef,
- #define PLAT_SP_HY_FF_RDIMM3 MemPConstructPsUDef,
- #define PLAT_SP_HY_FF_UDIMM3 MemPConstructPsUDef,
- #endif
- MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledHy[MAX_FF_TYPES] = {
- PLAT_SP_HY_FF_UDIMM2
- PLAT_SP_HY_FF_RDIMM2
- PLAT_SP_HY_FF_SDIMM2
- PLAT_SP_HY_FF_UDIMM3
- PLAT_SP_HY_FF_RDIMM3
- PLAT_SP_HY_FF_SDIMM3
- };
-
- #if OPTION_MEMCTLR_DR
- #if OPTION_UDIMMS
- #if OPTION_DDR2
- extern MEM_PLAT_SPEC_CFG MemPConstructPsUDr2;
- #define PLAT_SP_DR_FF_UDIMM2 MemPConstructPsUDr2,
- #else
- #define PLAT_SP_DR_FF_UDIMM2 MemPConstructPsUDef,
- #endif
- #if OPTION_DDR3
- #define PLAT_SP_DR_FF_UDIMM3 MemPConstructPsUDr3,
- #else
- #define PLAT_SP_DR_FF_UDIMM3 MemPConstructPsUDef,
- #endif
- #else
- #define PLAT_SP_DR_FF_UDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_DR_FF_UDIMM3 MemPConstructPsUDef,
- #endif
- #if OPTION_RDIMMS
- #if OPTION_DDR2
- extern MEM_PLAT_SPEC_CFG MemPConstructPsRDr2;
- #define PLAT_SP_DR_FF_RDIMM2 MemPConstructPsRDr2,
- #else
- #define PLAT_SP_DR_FF_RDIMM2 MemPConstructPsUDef,
- #endif
- #if OPTION_DDR3
- #define PLAT_SP_DR_FF_RDIMM3 MemPConstructPsRDr3,
- #else
- #define PLAT_SP_DR_FF_RDIMM3 MemPConstructPsUDef,
- #endif
- #else
- #define PLAT_SP_DR_FF_RDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_DR_FF_RDIMM3 MemPConstructPsUDef,
- #endif
- #if OPTION_SODIMMS
- #if OPTION_DDR2
- #define PLAT_SP_DR_FF_SDIMM2 MemPConstructPsUDef,
- #else
- #define PLAT_SP_DR_FF_SDIMM2 MemPConstructPsUDef,
- #endif
- #if OPTION_DDR3
- #define PLAT_SP_DR_FF_SDIMM3 MemPConstructPsSDr3,
- #else
- #define PLAT_SP_DR_FF_SDIMM3 MemPConstructPsUDef,
- #endif
- #else
- #define PLAT_SP_DR_FF_SDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_DR_FF_SDIMM3 MemPConstructPsUDef,
- #endif
- #else
- #define PLAT_SP_DR_FF_SDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_DR_FF_RDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_DR_FF_UDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_DR_FF_SDIMM3 MemPConstructPsUDef,
- #define PLAT_SP_DR_FF_RDIMM3 MemPConstructPsUDef,
- #define PLAT_SP_DR_FF_UDIMM3 MemPConstructPsUDef,
- #endif
- MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDR[MAX_FF_TYPES] = {
- PLAT_SP_DR_FF_UDIMM2
- PLAT_SP_DR_FF_RDIMM2
- PLAT_SP_DR_FF_SDIMM2
- PLAT_SP_DR_FF_UDIMM3
- PLAT_SP_DR_FF_RDIMM3
- PLAT_SP_DR_FF_SDIMM3
- };
-
- #if (OPTION_MEMCTLR_DA == TRUE)
- #if OPTION_UDIMMS
- #if OPTION_DDR2
- #define PLAT_SP_DA_FF_UDIMM2 MemPConstructPsUDef,
- #else
- #define PLAT_SP_DA_FF_UDIMM2 MemPConstructPsUDef,
- #endif
- #if OPTION_DDR3
- #define PLAT_SP_DA_FF_UDIMM3 MemPConstructPsUDA3,
- #else
- #define PLAT_SP_DA_FF_UDIMM3 MemPConstructPsUDef,
- #endif
- #else
- #define PLAT_SP_DA_FF_UDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_DA_FF_UDIMM3 MemPConstructPsUDef,
- #endif
- #if OPTION_RDIMMS
- #if OPTION_DDR2
- #define PLAT_SP_DA_FF_RDIMM2 MemPConstructPsUDef,
- #else
- #define PLAT_SP_DA_FF_RDIMM2 MemPConstructPsUDef,
- #endif
- #if OPTION_DDR3
- #define PLAT_SP_DA_FF_RDIMM3 MemPConstructPsUDef,
- #else
- #define PLAT_SP_DA_FF_RDIMM3 MemPConstructPsUDef,
- #endif
- #else
- #define PLAT_SP_DA_FF_RDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_DA_FF_RDIMM3 MemPConstructPsUDef,
- #endif
- #if OPTION_SODIMMS
- #if OPTION_DDR2
- #define PLAT_SP_DA_FF_SDIMM2 MemPConstructPsSDA2,
- #else
- #define PLAT_SP_DA_FF_SDIMM2 MemPConstructPsUDef,
- #endif
- #if OPTION_DDR3
- #define PLAT_SP_DA_FF_SDIMM3 MemPConstructPsSDA3,
- #else
- #define PLAT_SP_DA_FF_SDIMM3 MemPConstructPsUDef,
- #endif
- #else
- #define PLAT_SP_DA_FF_SDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_DA_FF_SDIMM3 MemPConstructPsUDef,
- #endif
- #else
- #define PLAT_SP_DA_FF_SDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_DA_FF_RDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_DA_FF_UDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_DA_FF_SDIMM3 MemPConstructPsUDef,
- #define PLAT_SP_DA_FF_RDIMM3 MemPConstructPsUDef,
- #define PLAT_SP_DA_FF_UDIMM3 MemPConstructPsUDef,
- #endif
- MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDA[MAX_FF_TYPES] = {
- PLAT_SP_DA_FF_UDIMM2
- PLAT_SP_DA_FF_RDIMM2
- PLAT_SP_DA_FF_SDIMM2
- PLAT_SP_DA_FF_UDIMM3
- PLAT_SP_DA_FF_RDIMM3
- PLAT_SP_DA_FF_SDIMM3
- };
-
- #if (OPTION_MEMCTLR_Ni == TRUE)
- #define PLAT_SP_NI_FF_SDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_NI_FF_RDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_NI_FF_UDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_NI_FF_SDIMM3 MemPConstructPsSNi3,
- #define PLAT_SP_NI_FF_RDIMM3 MemPConstructPsUDef,
- #define PLAT_SP_NI_FF_UDIMM3 MemPConstructPsUNi3,
- #else
- #define PLAT_SP_NI_FF_SDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_NI_FF_RDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_NI_FF_UDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_NI_FF_SDIMM3 MemPConstructPsUDef,
- #define PLAT_SP_NI_FF_RDIMM3 MemPConstructPsUDef,
- #define PLAT_SP_NI_FF_UDIMM3 MemPConstructPsUDef,
- #endif
- MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledNi[MAX_FF_TYPES] = {
- PLAT_SP_NI_FF_UDIMM2
- PLAT_SP_NI_FF_RDIMM2
- PLAT_SP_NI_FF_SDIMM2
- PLAT_SP_NI_FF_UDIMM3
- PLAT_SP_NI_FF_RDIMM3
- PLAT_SP_NI_FF_SDIMM3
- };
-
- #if (OPTION_MEMCTLR_PH == TRUE)
- #define PLAT_SP_PH_FF_SDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_PH_FF_RDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_PH_FF_UDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_PH_FF_SDIMM3 MemPConstructPsSPh3,
- #define PLAT_SP_PH_FF_RDIMM3 MemPConstructPsUDef,
- #define PLAT_SP_PH_FF_UDIMM3 MemPConstructPsUPh3,
- #else
- #define PLAT_SP_PH_FF_SDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_PH_FF_RDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_PH_FF_UDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_PH_FF_SDIMM3 MemPConstructPsUDef,
- #define PLAT_SP_PH_FF_RDIMM3 MemPConstructPsUDef,
- #define PLAT_SP_PH_FF_UDIMM3 MemPConstructPsUDef,
- #endif
- MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledPh[MAX_FF_TYPES] = {
- PLAT_SP_PH_FF_UDIMM2
- PLAT_SP_PH_FF_RDIMM2
- PLAT_SP_PH_FF_SDIMM2
- PLAT_SP_PH_FF_UDIMM3
- PLAT_SP_PH_FF_RDIMM3
- PLAT_SP_PH_FF_SDIMM3
- };
-
- #if (OPTION_MEMCTLR_RB == TRUE)
- #define PLAT_SP_RB_FF_SDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_RB_FF_RDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_RB_FF_UDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_RB_FF_SDIMM3 MemPConstructPsSRb3,
- #define PLAT_SP_RB_FF_RDIMM3 MemPConstructPsUDef,
- #define PLAT_SP_RB_FF_UDIMM3 MemPConstructPsURb3,
- #else
- #define PLAT_SP_RB_FF_SDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_RB_FF_RDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_RB_FF_UDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_RB_FF_SDIMM3 MemPConstructPsUDef,
- #define PLAT_SP_RB_FF_RDIMM3 MemPConstructPsUDef,
- #define PLAT_SP_RB_FF_UDIMM3 MemPConstructPsUDef,
- #endif
- MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledRb[MAX_FF_TYPES] = {
- PLAT_SP_RB_FF_UDIMM2
- PLAT_SP_RB_FF_RDIMM2
- PLAT_SP_RB_FF_SDIMM2
- PLAT_SP_RB_FF_UDIMM3
- PLAT_SP_RB_FF_RDIMM3
- PLAT_SP_RB_FF_SDIMM3
- };
-
- #if OPTION_MEMCTLR_LN
- #if OPTION_UDIMMS
- #if OPTION_DDR3
- #define PLAT_SP_LN_FF_UDIMM3 MemPConstructPsULN3,
- #else
- #define PLAT_SP_LN_FF_UDIMM3 MemPConstructPsUDef,
- #endif
- #else
- #define PLAT_SP_LN_FF_UDIMM3 MemPConstructPsUDef,
- #endif
- #if OPTION_SODIMMS
- #if OPTION_DDR3
- #define PLAT_SP_LN_FF_SDIMM3 MemPConstructPsSLN3,
- #else
- #define PLAT_SP_LN_FF_SDIMM3 MemPConstructPsUDef,
- #endif
- #else
- #define PLAT_SP_LN_FF_SDIMM3 MemPConstructPsUDef,
- #endif
- #else
- #define PLAT_SP_LN_FF_SDIMM3 MemPConstructPsUDef,
- #define PLAT_SP_LN_FF_UDIMM3 MemPConstructPsUDef,
- #endif
- MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledLN[] = {
- PLAT_SP_LN_FF_SDIMM3
- PLAT_SP_LN_FF_UDIMM3
- NULL
- };
-
- #if OPTION_MEMCTLR_C32
- #if OPTION_UDIMMS
- #if OPTION_DDR2
- #define PLAT_SP_C32_FF_UDIMM2 MemPConstructPsUDef,
- #else
- #define PLAT_SP_C32_FF_UDIMM2 MemPConstructPsUDef,
- #endif
- #if OPTION_DDR3
- #define PLAT_SP_C32_FF_UDIMM3 MemPConstructPsUC32_3,
- #else
- #define PLAT_SP_C32_FF_UDIMM3 MemPConstructPsUDef,
- #endif
- #else
- #define PLAT_SP_C32_FF_UDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_C32_FF_UDIMM3 MemPConstructPsUDef,
- #endif
- #if OPTION_RDIMMS
- #if OPTION_DDR2
- #define PLAT_SP_C32_FF_RDIMM2 MemPConstructPsUDef,
- #else
- #define PLAT_SP_C32_FF_RDIMM2 MemPConstructPsUDef,
- #endif
- #if OPTION_DDR3
- #define PLAT_SP_C32_FF_RDIMM3 MemPConstructPsRC32_3,
- #else
- #define PLAT_SP_C32_FF_RDIMM3 MemPConstructPsUDef,
- #endif
- #else
- #define PLAT_SP_C32_FF_RDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_C32_FF_RDIMM3 MemPConstructPsUDef,
- #endif
- #if OPTION_SODIMMS
- #define PLAT_SP_C32_FF_SDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_C32_FF_SDIMM3 MemPConstructPsUDef,
- #endif
- #else
- #define PLAT_SP_C32_FF_SDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_C32_FF_RDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_C32_FF_UDIMM2 MemPConstructPsUDef,
- #define PLAT_SP_C32_FF_SDIMM3 MemPConstructPsUDef,
- #define PLAT_SP_C32_FF_RDIMM3 MemPConstructPsUDef,
- #define PLAT_SP_C32_FF_UDIMM3 MemPConstructPsUDef,
- #endif
- MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledC32[MAX_FF_TYPES] = {
- PLAT_SP_C32_FF_UDIMM2
- PLAT_SP_C32_FF_RDIMM2
- PLAT_SP_C32_FF_SDIMM2
- PLAT_SP_C32_FF_UDIMM3
- PLAT_SP_C32_FF_RDIMM3
- PLAT_SP_C32_FF_SDIMM3
- };
-
- #if OPTION_MEMCTLR_ON
- #if OPTION_UDIMMS
- #if OPTION_DDR3
- #define PLAT_SP_ON_FF_UDIMM3 MemPConstructPsUON3,
- #else
- #define PLAT_SP_ON_FF_UDIMM3 MemPConstructPsUDef,
- #endif
- #else
- #define PLAT_SP_ON_FF_UDIMM3 MemPConstructPsUDef,
- #endif
- #if OPTION_SODIMMS
- #if OPTION_DDR3
- #define PLAT_SP_ON_FF_SDIMM3 MemPConstructPsSON3,
- #else
- #define PLAT_SP_ON_FF_SDIMM3 MemPConstructPsUDef,
- #endif
- #else
- #define PLAT_SP_ON_FF_SDIMM3 MemPConstructPsUDef,
- #endif
- #else
- #define PLAT_SP_ON_FF_SDIMM3 MemPConstructPsUDef,
- #define PLAT_SP_ON_FF_UDIMM3 MemPConstructPsUDef,
- #endif
- MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledON[] = {
- PLAT_SP_ON_FF_SDIMM3
- PLAT_SP_ON_FF_UDIMM3
- NULL
- };
-
- /*---------------------------------------------------------------------------------------------------
- * PLATFORM-SPECIFIC CONFIGURATION
- *
- *
- *---------------------------------------------------------------------------------------------------
- */
-
- #if OPTION_MEMCTLR_DR
- #if OPTION_UDIMMS
- #if OPTION_DDR2
- #define PSC_DR_UDIMM_DDR2 //MemAGetPsCfgUDr2
- #else
- #define PSC_DR_UDIMM_DDR2
- #endif
- #if OPTION_DDR3
- #define PSC_DR_UDIMM_DDR3 MemAGetPsCfgUDr3,
- #else
- #define PSC_DR_UDIMM_DDR3
- #endif
- #endif
- #if OPTION_RDIMMS
- #if OPTION_DDR2
- #define PSC_DR_RDIMM_DDR2 MemAGetPsCfgRDr2,
- #else
- #define PSC_DR_RDIMM_DDR2
- #endif
- #if OPTION_DDR3
- #define PSC_DR_RDIMM_DDR3 MemAGetPsCfgRDr3,
- #else
- #define PSC_DR_RDIMM_DDR3
- #endif
- #endif
- #if OPTION_SODIMMS
- #if OPTION_DDR2
- #define PSC_DR_SODIMM_DDR2 //MemAGetPsCfgSDr2
- #else
- #define PSC_DR_SODIMM_DDR2
- #endif
- #if OPTION_DDR3
- #define PSC_DR_SODIMM_DDR3 //MemAGetPsCfgSDr3
- #else
- #define PSC_DR_SODIMM_DDR3
- #endif
- #endif
- #endif
-
- #if (OPTION_MEMCTLR_DA == TRUE || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE)
- #if OPTION_MEMCTLR_Ni
- #define PSC_NI_UDIMM_DDR2
- #define PSC_NI_UDIMM_DDR3 MemAGetPsCfgUNi3,
- #define PSC_NI_RDIMM_DDR2
- #define PSC_NI_RDIMM_DDR3
- #define PSC_NI_SODIMM_DDR2
- #define PSC_NI_SODIMM_DDR3 MemAGetPsCfgSNi3,
- #endif
- #if OPTION_MEMCTLR_PH
- #define PSC_PH_UDIMM_DDR2
- #define PSC_PH_UDIMM_DDR3 MemAGetPsCfgUPh3,
- #define PSC_PH_RDIMM_DDR2
- #define PSC_PH_RDIMM_DDR3
- #define PSC_PH_SODIMM_DDR2
- #define PSC_PH_SODIMM_DDR3 MemAGetPsCfgSPh3,
- #endif
- #if OPTION_MEMCTLR_RB
- #define PSC_RB_UDIMM_DDR2
- #define PSC_RB_UDIMM_DDR3 MemAGetPsCfgURb3,
- #define PSC_RB_RDIMM_DDR2
- #define PSC_RB_RDIMM_DDR3
- #define PSC_RB_SODIMM_DDR2
- #define PSC_RB_SODIMM_DDR3 MemAGetPsCfgSRb3,
- #endif
- #if OPTION_MEMCTLR_DA
- #if OPTION_UDIMMS
- #if OPTION_DDR2
- #define PSC_DA_UDIMM_DDR2 //MemAGetPsCfgUDr2
- #else
- #define PSC_DA_UDIMM_DDR2
- #endif
- #if OPTION_DDR3
- #define PSC_DA_UDIMM_DDR3 MemAGetPsCfgUDA3,
- #else
- #define PSC_DA_UDIMM_DDR3
- #endif
- #endif
- #if OPTION_RDIMMS
- #if OPTION_DDR2
- #define PSC_DA_RDIMM_DDR2
- #else
- #define PSC_DA_RDIMM_DDR2
- #endif
- #if OPTION_DDR3
- #define PSC_DA_RDIMM_DDR3
- #else
- #define PSC_DA_RDIMM_DDR3
- #endif
- #endif
- #if OPTION_SODIMMS
- #if OPTION_DDR2
- #define PSC_DA_SODIMM_DDR2 MemAGetPsCfgSDA2,
- #else
- #define PSC_DA_SODIMM_DDR2
- #endif
- #if OPTION_DDR3
- #define PSC_DA_SODIMM_DDR3 MemAGetPsCfgSDA3,
- #else
- #define PSC_DA_SODIMM_DDR3
- #endif
- #endif
- #endif
- #endif
-
- #if OPTION_MEMCTLR_HY
- #if OPTION_UDIMMS
- #if OPTION_DDR2
- #define PSC_HY_UDIMM_DDR2 //MemAGetPsCfgUDr2,
- #else
- #define PSC_HY_UDIMM_DDR2
- #endif
- #if OPTION_DDR3
- #define PSC_HY_UDIMM_DDR3 MemAGetPsCfgUHy3,
- #else
- #define PSC_HY_UDIMM_DDR3
- #endif
- #endif
- #if OPTION_RDIMMS
- #if OPTION_DDR2
- #define PSC_HY_RDIMM_DDR2
- #else
- #define PSC_HY_RDIMM_DDR2
- #endif
- #if OPTION_DDR3
- #define PSC_HY_RDIMM_DDR3 MemAGetPsCfgRHy3,
- #else
- #define PSC_HY_RDIMM_DDR3
- #endif
- #endif
- #if OPTION_SODIMMS
- #if OPTION_DDR2
- #define PSC_HY_SODIMM_DDR2 //MemAGetPsCfgSHy2,
- #else
- #define PSC_HY_SODIMM_DDR2
- #endif
- #if OPTION_DDR3
- #define PSC_HY_SODIMM_DDR3 //MemAGetPsCfgSHy3,
- #else
- #define PSC_HY_SODIMM_DDR3
- #endif
- #endif
- #endif
-
- #if OPTION_MEMCTLR_C32
- #if OPTION_UDIMMS
- #if OPTION_DDR2
- #define PSC_C32_UDIMM_DDR2 //MemAGetPsCfgUDr2,
- #else
- #define PSC_C32_UDIMM_DDR2
- #endif
- #if OPTION_DDR3
- #define PSC_C32_UDIMM_DDR3 MemAGetPsCfgUC32_3,
- #else
- #define PSC_C32_UDIMM_DDR3
- #endif
- #endif
- #if OPTION_RDIMMS
- #if OPTION_DDR2
- #define PSC_C32_RDIMM_DDR2
- #else
- #define PSC_C32_RDIMM_DDR2
- #endif
- #if OPTION_DDR3
- #define PSC_C32_RDIMM_DDR3 MemAGetPsCfgRC32_3,
- #else
- #define PSC_C32_RDIMM_DDR3
- #endif
- #endif
- #if OPTION_SODIMMS
- #if OPTION_DDR2
- #define PSC_C32_SODIMM_DDR2 //MemAGetPsCfgSC32_2,
- #else
- #define PSC_C32_SODIMM_DDR2
- #endif
- #if OPTION_DDR3
- #define PSC_C32_SODIMM_DDR3 //MemAGetPsCfgSC32_3,
- #else
- #define PSC_C32_SODIMM_DDR3
- #endif
- #endif
- #endif
-
- #if OPTION_MEMCTLR_LN
- #if OPTION_UDIMMS
- #if OPTION_DDR2
- #define PSC_LN_UDIMM_DDR2 //MemAGetPsCfgULN2,
- #else
- #define PSC_LN_UDIMM_DDR2
- #endif
- #if OPTION_DDR3
- #define PSC_LN_UDIMM_DDR3 MemAGetPsCfgULN3,
- #else
- #define PSC_LN_UDIMM_DDR3
- #endif
- #endif
- #if OPTION_RDIMMS
- #if OPTION_DDR2
- #define PSC_LN_RDIMM_DDR2
- #else
- #define PSC_LN_RDIMM_DDR2
- #endif
- #if OPTION_DDR3
- #define PSC_LN_RDIMM_DDR3 //MemAGetPsCfgRLN3,
- #else
- #define PSC_LN_RDIMM_DDR3
- #endif
- #endif
- #if OPTION_SODIMMS
- #if OPTION_DDR2
- #define PSC_LN_SODIMM_DDR2 //MemAGetPsCfgSLN2,
- #else
- #define PSC_LN_SODIMM_DDR2
- #endif
- #if OPTION_DDR3
- #define PSC_LN_SODIMM_DDR3 MemAGetPsCfgSLN3,
- #else
- #define PSC_LN_SODIMM_DDR3
- #endif
- #endif
- #endif
-
- #if OPTION_MEMCTLR_OR
- #if OPTION_UDIMMS
- #if OPTION_DDR2
- #define PSC_OR_UDIMM_DDR2 //MemAGetPsCfgUOr2,
- #else
- #define PSC_OR_UDIMM_DDR2
- #endif
- #if OPTION_DDR3
- #define PSC_OR_UDIMM_DDR3 //MemAGetPsCfgUOr3,
- #else
- #define PSC_OR_UDIMM_DDR3
- #endif
- #endif
- #if OPTION_RDIMMS
- #if OPTION_DDR2
- #define PSC_OR_RDIMM_DDR2
- #else
- #define PSC_OR_RDIMM_DDR2
- #endif
- #if OPTION_DDR3
- #define PSC_OR_RDIMM_DDR3 //MemAGetPsCfgROr3,
- #else
- #define PSC_OR_RDIMM_DDR3
- #endif
- #endif
- #if OPTION_SODIMMS
- #if OPTION_DDR2
- #define PSC_OR_SODIMM_DDR2 //MemAGetPsCfgSOr2,
- #else
- #define PSC_OR_SODIMM_DDR2
- #endif
- #if OPTION_DDR3
- #define PSC_OR_SODIMM_DDR3 //MemAGetPsCfgSOr3,
- #else
- #define PSC_OR_SODIMM_DDR3
- #endif
- #endif
- #endif
-
- #if OPTION_MEMCTLR_ON
- #if OPTION_UDIMMS
- #if OPTION_DDR2
- #define PSC_ON_UDIMM_DDR2 //MemAGetPsCfgUON2,
- #else
- #define PSC_ON_UDIMM_DDR2
- #endif
- #if OPTION_DDR3
- #define PSC_ON_UDIMM_DDR3 MemAGetPsCfgUON3,
- #else
- #define PSC_ON_UDIMM_DDR3
- #endif
- #endif
- #if OPTION_RDIMMS
- #if OPTION_DDR2
- #define PSC_ON_RDIMM_DDR2
- #else
- #define PSC_ON_RDIMM_DDR2
- #endif
- #if OPTION_DDR3
- #define PSC_ON_RDIMM_DDR3 //MemAGetPsCfgRON3,
- #else
- #define PSC_ON_RDIMM_DDR3
- #endif
- #endif
- #if OPTION_SODIMMS
- #if OPTION_DDR2
- #define PSC_ON_SODIMM_DDR2 //MemAGetPsCfgSON2,
- #else
- #define PSC_ON_SODIMM_DDR2
- #endif
- #if OPTION_DDR3
- #define PSC_ON_SODIMM_DDR3 MemAGetPsCfgSON3,
- #else
- #define PSC_ON_SODIMM_DDR3
- #endif
- #endif
- #endif
-
- /*----------------------------------------------------------------------
- * DEFAULT PSCFG DEFINITIONS
- *
- *----------------------------------------------------------------------
- */
-
- #ifndef PSC_DR_UDIMM_DDR2
- #define PSC_DR_UDIMM_DDR2
- #endif
- #ifndef PSC_DR_RDIMM_DDR2
- #define PSC_DR_RDIMM_DDR2
- #endif
- #ifndef PSC_DR_SODIMM_DDR2
- #define PSC_DR_SODIMM_DDR2
- #endif
- #ifndef PSC_DR_UDIMM_DDR3
- #define PSC_DR_UDIMM_DDR3
- #endif
- #ifndef PSC_DR_RDIMM_DDR3
- #define PSC_DR_RDIMM_DDR3
- #endif
- #ifndef PSC_DR_SODIMM_DDR3
- #define PSC_DR_SODIMM_DDR3
- #endif
- #ifndef PSC_RB_UDIMM_DDR2
- #define PSC_RB_UDIMM_DDR2
- #endif
- #ifndef PSC_RB_RDIMM_DDR2
- #define PSC_RB_RDIMM_DDR2
- #endif
- #ifndef PSC_RB_SODIMM_DDR2
- #define PSC_RB_SODIMM_DDR2
- #endif
- #ifndef PSC_RB_UDIMM_DDR3
- #define PSC_RB_UDIMM_DDR3
- #endif
- #ifndef PSC_RB_RDIMM_DDR3
- #define PSC_RB_RDIMM_DDR3
- #endif
- #ifndef PSC_RB_SODIMM_DDR3
- #define PSC_RB_SODIMM_DDR3
- #endif
- #ifndef PSC_DA_UDIMM_DDR2
- #define PSC_DA_UDIMM_DDR2
- #endif
- #ifndef PSC_DA_RDIMM_DDR2
- #define PSC_DA_RDIMM_DDR2
- #endif
- #ifndef PSC_DA_SODIMM_DDR2
- #define PSC_DA_SODIMM_DDR2
- #endif
- #ifndef PSC_DA_UDIMM_DDR3
- #define PSC_DA_UDIMM_DDR3
- #endif
- #ifndef PSC_DA_RDIMM_DDR3
- #define PSC_DA_RDIMM_DDR3
- #endif
- #ifndef PSC_DA_SODIMM_DDR3
- #define PSC_DA_SODIMM_DDR3
- #endif
- #ifndef PSC_NI_UDIMM_DDR2
- #define PSC_NI_UDIMM_DDR2
- #endif
- #ifndef PSC_NI_RDIMM_DDR2
- #define PSC_NI_RDIMM_DDR2
- #endif
- #ifndef PSC_NI_SODIMM_DDR2
- #define PSC_NI_SODIMM_DDR2
- #endif
- #ifndef PSC_NI_UDIMM_DDR3
- #define PSC_NI_UDIMM_DDR3
- #endif
- #ifndef PSC_NI_RDIMM_DDR3
- #define PSC_NI_RDIMM_DDR3
- #endif
- #ifndef PSC_NI_SODIMM_DDR3
- #define PSC_NI_SODIMM_DDR3
- #endif
- #ifndef PSC_PH_UDIMM_DDR2
- #define PSC_PH_UDIMM_DDR2
- #endif
- #ifndef PSC_PH_RDIMM_DDR2
- #define PSC_PH_RDIMM_DDR2
- #endif
- #ifndef PSC_PH_SODIMM_DDR2
- #define PSC_PH_SODIMM_DDR2
- #endif
- #ifndef PSC_PH_UDIMM_DDR3
- #define PSC_PH_UDIMM_DDR3
- #endif
- #ifndef PSC_PH_RDIMM_DDR3
- #define PSC_PH_RDIMM_DDR3
- #endif
- #ifndef PSC_PH_SODIMM_DDR3
- #define PSC_PH_SODIMM_DDR3
- #endif
- #ifndef PSC_HY_UDIMM_DDR2
- #define PSC_HY_UDIMM_DDR2
- #endif
- #ifndef PSC_HY_RDIMM_DDR2
- #define PSC_HY_RDIMM_DDR2
- #endif
- #ifndef PSC_HY_SODIMM_DDR2
- #define PSC_HY_SODIMM_DDR2
- #endif
- #ifndef PSC_HY_UDIMM_DDR3
- #define PSC_HY_UDIMM_DDR3
- #endif
- #ifndef PSC_HY_RDIMM_DDR3
- #define PSC_HY_RDIMM_DDR3
- #endif
- #ifndef PSC_HY_SODIMM_DDR3
- #define PSC_HY_SODIMM_DDR3
- #endif
- #ifndef PSC_LN_UDIMM_DDR2
- #define PSC_LN_UDIMM_DDR2
- #endif
- #ifndef PSC_LN_RDIMM_DDR2
- #define PSC_LN_RDIMM_DDR2
- #endif
- #ifndef PSC_LN_SODIMM_DDR2
- #define PSC_LN_SODIMM_DDR2
- #endif
- #ifndef PSC_LN_UDIMM_DDR3
- #define PSC_LN_UDIMM_DDR3
- #endif
- #ifndef PSC_LN_RDIMM_DDR3
- #define PSC_LN_RDIMM_DDR3
- #endif
- #ifndef PSC_LN_SODIMM_DDR3
- #define PSC_LN_SODIMM_DDR3
- #endif
- #ifndef PSC_OR_UDIMM_DDR2
- #define PSC_OR_UDIMM_DDR2
- #endif
- #ifndef PSC_OR_RDIMM_DDR2
- #define PSC_OR_RDIMM_DDR2
- #endif
- #ifndef PSC_OR_SODIMM_DDR2
- #define PSC_OR_SODIMM_DDR2
- #endif
- #ifndef PSC_OR_UDIMM_DDR3
- #define PSC_OR_UDIMM_DDR3
- #endif
- #ifndef PSC_OR_RDIMM_DDR3
- #define PSC_OR_RDIMM_DDR3
- #endif
- #ifndef PSC_OR_SODIMM_DDR3
- #define PSC_OR_SODIMM_DDR3
- #endif
- #ifndef PSC_C32_UDIMM_DDR3
- #define PSC_C32_UDIMM_DDR3
- #endif
- #ifndef PSC_C32_RDIMM_DDR3
- #define PSC_C32_RDIMM_DDR3
- #endif
- #ifndef PSC_ON_UDIMM_DDR2
- #define PSC_ON_UDIMM_DDR2
- #endif
- #ifndef PSC_ON_RDIMM_DDR2
- #define PSC_ON_RDIMM_DDR2
- #endif
- #ifndef PSC_ON_SODIMM_DDR2
- #define PSC_ON_SODIMM_DDR2
- #endif
- #ifndef PSC_ON_UDIMM_DDR3
- #define PSC_ON_UDIMM_DDR3
- #endif
- #ifndef PSC_ON_RDIMM_DDR3
- #define PSC_ON_RDIMM_DDR3
- #endif
- #ifndef PSC_ON_SODIMM_DDR3
- #define PSC_ON_SODIMM_DDR3
- #endif
-
- MEM_PLATFORM_CFG* memPlatformTypeInstalled[] = {
- PSC_DR_UDIMM_DDR2
- PSC_DR_RDIMM_DDR2
- PSC_DR_SODIMM_DDR2
- PSC_DR_UDIMM_DDR3
- PSC_DR_RDIMM_DDR3
- PSC_DR_SODIMM_DDR3
- PSC_RB_UDIMM_DDR3
- PSC_RB_SODIMM_DDR3
- PSC_DA_SODIMM_DDR2
- PSC_DA_UDIMM_DDR3
- PSC_DA_SODIMM_DDR3
- PSC_NI_UDIMM_DDR3
- PSC_NI_SODIMM_DDR3
- PSC_PH_UDIMM_DDR3
- PSC_PH_SODIMM_DDR3
- PSC_HY_UDIMM_DDR3
- PSC_HY_RDIMM_DDR3
- PSC_HY_SODIMM_DDR3
- PSC_LN_UDIMM_DDR3
- PSC_LN_RDIMM_DDR3
- PSC_LN_SODIMM_DDR3
- PSC_OR_UDIMM_DDR3
- PSC_OR_RDIMM_DDR3
- PSC_OR_SODIMM_DDR3
- PSC_C32_UDIMM_DDR3
- PSC_C32_RDIMM_DDR3
- PSC_ON_UDIMM_DDR3
- PSC_ON_RDIMM_DDR3
- PSC_ON_SODIMM_DDR3
- NULL
- };
- CONST UINTN SIZE_OF_PLATFORM = (sizeof (memPlatformTypeInstalled) / sizeof (MEM_PLATFORM_CFG*));
- #if SIZE_OF_PLATFORM > MAX_PLATFORM_TYPES
- #error Size of memPlatformTypeInstalled array larger than MAX_PLATFORM_TYPES
- #endif
-
- /*---------------------------------------------------------------------------------------------------
- * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION
- *
- *
- *---------------------------------------------------------------------------------------------------
- */
- #define MEM_PSC_FLOW_BLOCK_END NULL
- #define PSC_TBL_END NULL
- #define MEM_PSC_FLOW_DEFTRUE (BOOLEAN (*) (MEM_NB_BLOCK*, MEM_PSC_TABLE_BLOCK *)) memDefTrue
-
- #if OPTION_MEMCTLR_OR
- #if OPTION_UDIMMS
- #if OPTION_AM3_SOCKET_SUPPORT
- extern PSC_TBL_ENTRY MaxFreqTblEntUAM3;
- #define PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3 &MaxFreqTblEntUAM3,
- extern PSC_TBL_ENTRY DramTermTblEntUAM3;
- #define PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3 &DramTermTblEntUAM3,
- extern PSC_TBL_ENTRY OdtPat1DTblEntUAM3;
- #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 &OdtPat1DTblEntUAM3,
- extern PSC_TBL_ENTRY OdtPat2DTblEntUAM3;
- #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3 &OdtPat2DTblEntUAM3,
- extern PSC_TBL_ENTRY OdtPat3DTblEntUAM3;
- #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 &OdtPat3DTblEntUAM3,
- extern PSC_TBL_ENTRY SAOTblEntUAM3;
- #define PSC_TBL_OR_UDIMM3_SAO_AM3 &SAOTblEntUAM3,
- extern PSC_TBL_ENTRY ClkDisMapEntUAM3;
- #define PSC_TBL_OR_UDIMM3_CLK_DIS_AM3 &ClkDisMapEntUAM3,
- #endif
- #if OPTION_C32_SOCKET_SUPPORT
- extern PSC_TBL_ENTRY MaxFreqTblEntUC32;
- #define PSC_TBL_OR_UDIMM3_MAX_FREQ_C32 &MaxFreqTblEntUC32,
- extern PSC_TBL_ENTRY DramTermTblEntUC32;
- #define PSC_TBL_OR_UDIMM3_DRAM_TERM_C32 &DramTermTblEntUC32,
- extern PSC_TBL_ENTRY OdtPat1DTblEntUC32;
- #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 &OdtPat1DTblEntUC32,
- extern PSC_TBL_ENTRY OdtPat2DTblEntUC32;
- #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32 &OdtPat2DTblEntUC32,
- extern PSC_TBL_ENTRY OdtPat3DTblEntUC32;
- #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 &OdtPat3DTblEntUC32,
- extern PSC_TBL_ENTRY SAOTblEntUC32;
- #define PSC_TBL_OR_UDIMM3_SAO_C32 &SAOTblEntUC32,
- extern PSC_TBL_ENTRY ClkDisMapEntUC32;
- #define PSC_TBL_OR_UDIMM3_CLK_DIS_C32 &ClkDisMapEntUC32,
- extern PSC_TBL_ENTRY ClkDisMap3DEntUC32;
- #define PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32 &ClkDisMap3DEntUC32,
- #endif
- #if OPTION_G34_SOCKET_SUPPORT
- extern PSC_TBL_ENTRY MaxFreqTblEntUG34;
- #define PSC_TBL_OR_UDIMM3_MAX_FREQ_G34 &MaxFreqTblEntUG34,
- extern PSC_TBL_ENTRY DramTermTblEntUG34;
- #define PSC_TBL_OR_UDIMM3_DRAM_TERM_G34 &DramTermTblEntUG34,
- extern PSC_TBL_ENTRY OdtPat1DTblEntUG34;
- #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 &OdtPat1DTblEntUG34,
- extern PSC_TBL_ENTRY OdtPat2DTblEntUG34;
- #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34 &OdtPat2DTblEntUG34,
- extern PSC_TBL_ENTRY OdtPat3DTblEntUG34;
- #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 &OdtPat3DTblEntUG34,
- extern PSC_TBL_ENTRY SAOTblEntUG34;
- #define PSC_TBL_OR_UDIMM3_SAO_G34 &SAOTblEntUG34,
- extern PSC_TBL_ENTRY ClkDisMapEntUG34;
- #define PSC_TBL_OR_UDIMM3_CLK_DIS_G34 &ClkDisMapEntUG34,
- #endif
- #endif
- #if OPTION_RDIMMS
- #if OPTION_C32_SOCKET_SUPPORT
- extern PSC_TBL_ENTRY MaxFreqTblEntRC32;
- #define PSC_TBL_OR_RDIMM3_MAX_FREQ_C32 &MaxFreqTblEntRC32,
- extern PSC_TBL_ENTRY DramTermTblEntRC32;
- #define PSC_TBL_OR_RDIMM3_DRAM_TERM_C32 &DramTermTblEntRC32,
- extern PSC_TBL_ENTRY OdtPat1DTblEntRC32;
- #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 &OdtPat1DTblEntRC32,
- extern PSC_TBL_ENTRY OdtPat2DTblEntRC32;
- #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32 &OdtPat2DTblEntRC32,
- extern PSC_TBL_ENTRY OdtPat3DTblEntRC32;
- #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 &OdtPat3DTblEntRC32,
- extern PSC_TBL_ENTRY SAOTblEntRC32;
- #define PSC_TBL_OR_RDIMM3_SAO_C32 &SAOTblEntRC32,
- extern PSC_TBL_ENTRY RC2IBTTblEntRC32;
- #define PSC_TBL_OR_RDIMM3_RC2IBT_C32 &RC2IBTTblEntRC32,
- extern PSC_TBL_ENTRY RC10OpSpdTblEntRC32;
- #define PSC_TBL_OR_RDIMM3_RC10OPSPD_C32 &RC10OpSpdTblEntRC32,
- extern PSC_TBL_ENTRY ClkDisMapEntRC32;
- #define PSC_TBL_OR_RDIMM3_CLK_DIS_C32 &ClkDisMapEntRC32,
- #endif
- #if OPTION_G34_SOCKET_SUPPORT
- extern PSC_TBL_ENTRY MaxFreqTblEntRG34;
- #define PSC_TBL_OR_RDIMM3_MAX_FREQ_G34 &MaxFreqTblEntRG34,
- extern PSC_TBL_ENTRY DramTermTblEntRG34;
- #define PSC_TBL_OR_RDIMM3_DRAM_TERM_G34 &DramTermTblEntRG34,
- extern PSC_TBL_ENTRY OdtPat1DTblEntRG34;
- #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 &OdtPat1DTblEntRG34,
- extern PSC_TBL_ENTRY OdtPat2DTblEntRG34;
- #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34 &OdtPat2DTblEntRG34,
- extern PSC_TBL_ENTRY OdtPat3DTblEntRG34;
- #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 &OdtPat3DTblEntRG34,
- extern PSC_TBL_ENTRY SAOTblEntRG34;
- #define PSC_TBL_OR_RDIMM3_SAO_G34 &SAOTblEntRG34,
- extern PSC_TBL_ENTRY RC2IBTTblEntRG34;
- #define PSC_TBL_OR_RDIMM3_RC2IBT_G34 &RC2IBTTblEntRG34,
- extern PSC_TBL_ENTRY RC10OpSpdTblEntRG34;
- #define PSC_TBL_OR_RDIMM3_RC10OPSPD_G34 &RC10OpSpdTblEntRG34,
- extern PSC_TBL_ENTRY ClkDisMapEntRG34;
- #define PSC_TBL_OR_RDIMM3_CLK_DIS_G34 &ClkDisMapEntRG34,
- #endif
- #endif
- //#if OPTION_SODIMMS
- //#endif
- //#if OPTION_LRDIMMS
- // #if OPTION_C32_SOCKET_SUPPORT
- // extern PSC_TBL_ENTRY MaxFreqTblEntLRC32;
- // #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32 &MaxFreqTblEntLRC32,
- // extern PSC_TBL_ENTRY DramTermTblEntLRC32;
- // #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32 &DramTermTblEntLRC32,
- // extern PSC_TBL_ENTRY OdtPat1DTblEntRC32;
- // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32 &OdtPat1DTblEntLRC32,
- // extern PSC_TBL_ENTRY OdtPat2DTblEntRC32;
- // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32 &OdtPat2DTblEntLRC32,
- // extern PSC_TBL_ENTRY OdtPat3DTblEntRC32;
- // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32 &OdtPat3DTblEntLRC32,
- // extern PSC_TBL_ENTRY SAOTblEntRC32;
- // #define PSC_TBL_OR_LRDIMM3_SAO_C32 &SAOTblEntLRC32,
- // extern PSC_TBL_ENTRY IBTTblEntLRC32;
- // #define PSC_TBL_OR_LRDIMM3_IBT_C32 &IBTTblEntLRC32,
- // extern PSC_TBL_ENTRY ClkDisMapEntLRC32;
- // #define PSC_TBL_OR_LRDIMM3_CLK_DIS_C32 &ClkDisMapEntLRC32,
- // #endif
- // #if OPTION_G34_SOCKET_SUPPORT
- // extern PSC_TBL_ENTRY MaxFreqTblEntLRG34;
- // #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34 &MaxFreqTblEntLRG34,
- // extern PSC_TBL_ENTRY DramTermTblEntLRG34;
- // #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34 &DramTermTblEntLRG34,
- // extern PSC_TBL_ENTRY OdtPat1DTblEntRG34;
- // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34 &OdtPat1DTblEntLRG34,
- // extern PSC_TBL_ENTRY OdtPat2DTblEntRG34;
- // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34 &OdtPat2DTblEntLRG34,
- // extern PSC_TBL_ENTRY OdtPat3DTblEntRG34;
- // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34 &OdtPat3DTblEntLRG34,
- // extern PSC_TBL_ENTRY SAOTblEntRG34;
- // #define PSC_TBL_OR_LRDIMM3_SAO_G34 &SAOTblEntLRG34,
- // extern PSC_TBL_ENTRY IBTTblEntLRG34;
- // #define PSC_TBL_OR_LRDIMM3_IBT_G34 &IBTTblEntLRG34,
- // extern PSC_TBL_ENTRY ClkDisMapEntLRG34;
- // #define PSC_TBL_OR_LRDIMM3_CLK_DIS_G34 &ClkDisMapEntLRG34,
- // #endif
- //#endif
- extern PSC_TBL_ENTRY MR0WrTblEntry;
- #define PSC_TBL_OR_MR0_WR &MR0WrTblEntry,
- extern PSC_TBL_ENTRY MR0CLTblEntry;
- #define PSC_TBL_OR_MR0_CL &MR0CLTblEntry,
- extern PSC_TBL_ENTRY OrDdr3CKETriEnt;
- #define PSC_TBL_OR_CKE_TRI &OrDdr3CKETriEnt,
- extern PSC_TBL_ENTRY OrDdr3ODTTri3DEnt;
- #define PSC_TBL_OR_ODT_TRI_3D &OrDdr3ODTTri3DEnt,
- extern PSC_TBL_ENTRY OrDdr3ODTTriEnt;
- #define PSC_TBL_OR_ODT_TRI &OrDdr3ODTTriEnt,
- extern PSC_TBL_ENTRY OrUDdr3CSTriEnt;
- #define PSC_TBL_OR_UDIMM3_CS_TRI &OrUDdr3CSTriEnt,
- extern PSC_TBL_ENTRY OrDdr3CSTriEnt;
- #define PSC_TBL_OR_CS_TRI &OrDdr3CSTriEnt,
- extern PSC_TBL_ENTRY OrLRDdr3ODTTri3DEnt;
- #define PSC_TBL_OR_LRDIMM3_ODT_TRI_3D &OrLRDdr3ODTTri3DEnt,
- extern PSC_TBL_ENTRY OrLRDdr3ODTTriEnt;
- #define PSC_TBL_OR_LRDIMM3_ODT_TRI &OrLRDdr3ODTTriEnt,
-
- #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3
- #define PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_C32
- #define PSC_TBL_OR_UDIMM3_MAX_FREQ_C32
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_G34
- #define PSC_TBL_OR_UDIMM3_MAX_FREQ_G34
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3
- #define PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_C32
- #define PSC_TBL_OR_UDIMM3_DRAM_TERM_C32
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_G34
- #define PSC_TBL_OR_UDIMM3_DRAM_TERM_G34
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3
- #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32
- #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34
- #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3
- #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32
- #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34
- #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3
- #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32
- #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34
- #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_SAO_AM3
- #define PSC_TBL_OR_UDIMM3_SAO_AM3
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_SAO_C32
- #define PSC_TBL_OR_UDIMM3_SAO_C32
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_SAO_G34
- #define PSC_TBL_OR_UDIMM3_SAO_G34
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3
- #define PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_C32
- #define PSC_TBL_OR_RDIMM3_MAX_FREQ_C32
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_G34
- #define PSC_TBL_OR_RDIMM3_MAX_FREQ_G34
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3
- #define PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_C32
- #define PSC_TBL_OR_RDIMM3_DRAM_TERM_C32
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_G34
- #define PSC_TBL_OR_RDIMM3_DRAM_TERM_G34
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3
- #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32
- #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34
- #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3
- #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32
- #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34
- #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3
- #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32
- #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34
- #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_SAO_AM3
- #define PSC_TBL_OR_RDIMM3_SAO_AM3
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_SAO_C32
- #define PSC_TBL_OR_RDIMM3_SAO_C32
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_SAO_G34
- #define PSC_TBL_OR_RDIMM3_SAO_G34
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_AM3
- #define PSC_TBL_OR_RDIMM3_RC2IBT_AM3
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_C32
- #define PSC_TBL_OR_RDIMM3_RC2IBT_C32
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_G34
- #define PSC_TBL_OR_RDIMM3_RC2IBT_G34
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3
- #define PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_C32
- #define PSC_TBL_OR_RDIMM3_RC10OPSPD_C32
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_G34
- #define PSC_TBL_OR_RDIMM3_RC10OPSPD_G34
- #endif
- #ifndef PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32
- #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32
- #endif
- #ifndef PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34
- #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34
- #endif
- #ifndef PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32
- #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32
- #endif
- #ifndef PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34
- #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34
- #endif
- #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32
- #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32
- #endif
- #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34
- #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34
- #endif
- #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32
- #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32
- #endif
- #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34
- #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34
- #endif
- #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32
- #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32
- #endif
- #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34
- #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34
- #endif
- #ifndef PSC_TBL_OR_LRDIMM3_SAO_C32
- #define PSC_TBL_OR_LRDIMM3_SAO_C32
- #endif
- #ifndef PSC_TBL_OR_LRDIMM3_SAO_G34
- #define PSC_TBL_OR_LRDIMM3_SAO_G34
- #endif
- #ifndef PSC_TBL_OR_LRDIMM3_IBT_C32
- #define PSC_TBL_OR_LRDIMM3_IBT_C32
- #endif
- #ifndef PSC_TBL_OR_LRDIMM3_IBT_G34
- #define PSC_TBL_OR_LRDIMM3_IBT_G34
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_AM3
- #define PSC_TBL_OR_UDIMM3_CLK_DIS_AM3
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_C32
- #define PSC_TBL_OR_UDIMM3_CLK_DIS_C32
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32
- #define PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32
- #endif
- #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_G34
- #define PSC_TBL_OR_UDIMM3_CLK_DIS_G34
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_CLK_DIS_C32
- #define PSC_TBL_OR_RDIMM3_CLK_DIS_C32
- #endif
- #ifndef PSC_TBL_OR_RDIMM3_CLK_DIS_G34
- #define PSC_TBL_OR_RDIMM3_CLK_DIS_G34
- #endif
- #ifndef PSC_TBL_OR_LRDIMM3_CLK_DIS_C32
- #define PSC_TBL_OR_LRDIMM3_CLK_DIS_C32
- #endif
- #ifndef PSC_TBL_OR_LRDIMM3_CLK_DIS_G34
- #define PSC_TBL_OR_LRDIMM3_CLK_DIS_G34
- #endif
-
- PSC_TBL_ENTRY* memPSCTblMaxFreqArrayOR[] = {
- PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3
- PSC_TBL_OR_UDIMM3_MAX_FREQ_C32
- PSC_TBL_OR_UDIMM3_MAX_FREQ_G34
- PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3
- PSC_TBL_OR_RDIMM3_MAX_FREQ_C32
- PSC_TBL_OR_RDIMM3_MAX_FREQ_G34
- PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32
- PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34
- PSC_TBL_END
- };
-
- PSC_TBL_ENTRY* memPSCTblDramTermArrayOR[] = {
- PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3
- PSC_TBL_OR_UDIMM3_DRAM_TERM_C32
- PSC_TBL_OR_UDIMM3_DRAM_TERM_G34
- PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3
- PSC_TBL_OR_RDIMM3_DRAM_TERM_C32
- PSC_TBL_OR_RDIMM3_DRAM_TERM_G34
- PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32
- PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34
- PSC_TBL_END
- };
-
- PSC_TBL_ENTRY* memPSCTblODTPatArrayOR[] = {
- PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3
- PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3
- PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3
- PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3
- PSC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3
- PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3
- PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32
- PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32
- PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32
- PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32
- PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32
- PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32
- PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32
- PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32
- PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32
- PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34
- PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34
- PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34
- PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34
- PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34
- PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34
- PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34
- PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34
- PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34
- PSC_TBL_END
- };
-
- PSC_TBL_ENTRY* memPSCTblSAOArrayOR[] = {
- PSC_TBL_OR_UDIMM3_SAO_AM3
- PSC_TBL_OR_UDIMM3_SAO_C32
- PSC_TBL_OR_UDIMM3_SAO_G34
- PSC_TBL_OR_RDIMM3_SAO_AM3
- PSC_TBL_OR_RDIMM3_SAO_C32
- PSC_TBL_OR_RDIMM3_SAO_G34
- PSC_TBL_OR_LRDIMM3_SAO_C32
- PSC_TBL_OR_LRDIMM3_SAO_G34
- PSC_TBL_END
- };
-
- PSC_TBL_ENTRY* memPSCTblMR0WRArrayOR[] = {
- PSC_TBL_OR_MR0_WR
- PSC_TBL_END
- };
-
- PSC_TBL_ENTRY* memPSCTblMR0CLArrayOR[] = {
- PSC_TBL_OR_MR0_CL
- PSC_TBL_END
- };
-
- PSC_TBL_ENTRY* memPSCTblRC2IBTArrayOR[] = {
- PSC_TBL_OR_RDIMM3_RC2IBT_AM3
- PSC_TBL_OR_RDIMM3_RC2IBT_C32
- PSC_TBL_OR_RDIMM3_RC2IBT_G34
- PSC_TBL_END
- };
-
- PSC_TBL_ENTRY* memPSCTblRC10OPSPDArrayOR[] = {
- PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3
- PSC_TBL_OR_RDIMM3_RC10OPSPD_C32
- PSC_TBL_OR_RDIMM3_RC10OPSPD_G34
- PSC_TBL_END
- };
-
- PSC_TBL_ENTRY* memPSCTblLRIBTArrayOR[] = {
- PSC_TBL_OR_LRDIMM3_IBT_C32
- PSC_TBL_OR_LRDIMM3_IBT_G34
- PSC_TBL_END
- };
-
- PSC_TBL_ENTRY* memPSCTblGenArrayOR[] = {
- PSC_TBL_OR_UDIMM3_CLK_DIS_AM3
- PSC_TBL_OR_UDIMM3_CLK_DIS_C32
- PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32
- PSC_TBL_OR_UDIMM3_CLK_DIS_G34
- PSC_TBL_OR_RDIMM3_CLK_DIS_C32
- PSC_TBL_OR_RDIMM3_CLK_DIS_G34
- PSC_TBL_OR_LRDIMM3_CLK_DIS_C32
- PSC_TBL_OR_LRDIMM3_CLK_DIS_G34
- PSC_TBL_OR_CKE_TRI
- PSC_TBL_OR_ODT_TRI_3D
- PSC_TBL_OR_ODT_TRI
- PSC_TBL_OR_LRDIMM3_ODT_TRI_3D
- PSC_TBL_OR_LRDIMM3_ODT_TRI
- PSC_TBL_OR_UDIMM3_CS_TRI
- PSC_TBL_OR_CS_TRI
- PSC_TBL_END
- };
-
- MEM_PSC_TABLE_BLOCK memPSCTblBlockOr = {
- (PSC_TBL_ENTRY **)&memPSCTblMaxFreqArrayOR,
- (PSC_TBL_ENTRY **)&memPSCTblDramTermArrayOR,
- (PSC_TBL_ENTRY **)&memPSCTblODTPatArrayOR,
- (PSC_TBL_ENTRY **)&memPSCTblSAOArrayOR,
- (PSC_TBL_ENTRY **)&memPSCTblMR0WRArrayOR,
- (PSC_TBL_ENTRY **)&memPSCTblMR0CLArrayOR,
- (PSC_TBL_ENTRY **)&memPSCTblRC2IBTArrayOR,
- (PSC_TBL_ENTRY **)&memPSCTblRC10OPSPDArrayOR,
- (PSC_TBL_ENTRY **)&memPSCTblLRIBTArrayOR,
- NULL,
- NULL,
- (PSC_TBL_ENTRY **)&memPSCTblGenArrayOR
- };
-
- extern MEM_PSC_FLOW MemPGetMaxFreqSupported;
- #define PSC_FLOW_OR_MAX_FREQ MemPGetMaxFreqSupported
- extern MEM_PSC_FLOW MemPGetRttNomWr;
- #define PSC_FLOW_OR_DRAM_TERM MemPGetRttNomWr
- extern MEM_PSC_FLOW MemPGetODTPattern;
- #define PSC_FLOW_OR_ODT_PATTERN MemPGetODTPattern
- extern MEM_PSC_FLOW MemPGetSAO;
- #define PSC_FLOW_OR_SAO MemPGetSAO
- extern MEM_PSC_FLOW MemPGetMR0WrCL;
- #define PSC_FLOW_OR_MR0_WRCL MemPGetMR0WrCL
- #if OPTION_RDIMMS
- extern MEM_PSC_FLOW MemPGetRC2IBT;
- #define PSC_FLOW_OR_RC2_IBT MemPGetRC2IBT
- extern MEM_PSC_FLOW MemPGetRC10OpSpd;
- #define PSC_FLOW_OR_RC10_OPSPD MemPGetRC10OpSpd
- #endif
- //#if OPTION_LRDIMMS
- //extern MEM_PSC_FLOW MemPGetLRIBT;
- //#define PSC_FLOW_OR_LR_IBT MemPGetLRIBT
- //extern MEM_PSC_FLOW MemPGetLRNPR;
- //#define PSC_FLOW_OR_LR_NPR MemPGetLRNPR
- //extern MEM_PSC_FLOW MemPGetLRNLR;
- //#define PSC_FLOW_OR_LR_NLR MemPGetLRNLR
- //#endif
- #ifndef PSC_FLOW_OR_MAX_FREQ
- #define PSC_FLOW_OR_MAX_FREQ MEM_PSC_FLOW_DEFTRUE
- #endif
- #ifndef PSC_FLOW_OR_DRAM_TERM
- #define PSC_FLOW_OR_DRAM_TERM MEM_PSC_FLOW_DEFTRUE
- #endif
- #ifndef PSC_FLOW_OR_ODT_PATTERN
- #define PSC_FLOW_OR_ODT_PATTERN MEM_PSC_FLOW_DEFTRUE
- #endif
- #ifndef PSC_FLOW_OR_SAO
- #define PSC_FLOW_OR_SAO MEM_PSC_FLOW_DEFTRUE
- #endif
- #ifndef PSC_FLOW_OR_MR0_WRCL
- #define PSC_FLOW_OR_MR0_WRCL MEM_PSC_FLOW_DEFTRUE
- #endif
- #ifndef PSC_FLOW_OR_RC2_IBT
- #define PSC_FLOW_OR_RC2_IBT MEM_PSC_FLOW_DEFTRUE
- #endif
- #ifndef PSC_FLOW_OR_RC10_OPSPD
- #define PSC_FLOW_OR_RC10_OPSPD MEM_PSC_FLOW_DEFTRUE
- #endif
- #ifndef PSC_FLOW_OR_LR_IBT
- #define PSC_FLOW_OR_LR_IBT MEM_PSC_FLOW_DEFTRUE
- #endif
- #ifndef PSC_FLOW_OR_LR_NPR
- #define PSC_FLOW_OR_LR_NPR MEM_PSC_FLOW_DEFTRUE
- #endif
- #ifndef PSC_FLOW_OR_LR_NLR
- #define PSC_FLOW_OR_LR_NLR MEM_PSC_FLOW_DEFTRUE
- #endif
- MEM_PSC_FLOW_BLOCK memPlatSpecFlowOR = {
- &memPSCTblBlockOr,
- PSC_FLOW_OR_MAX_FREQ,
- PSC_FLOW_OR_DRAM_TERM,
- PSC_FLOW_OR_ODT_PATTERN,
- PSC_FLOW_OR_SAO,
- PSC_FLOW_OR_MR0_WRCL,
- PSC_FLOW_OR_RC2_IBT,
- PSC_FLOW_OR_RC10_OPSPD,
- PSC_FLOW_OR_LR_IBT,
- PSC_FLOW_OR_LR_NPR,
- PSC_FLOW_OR_LR_NLR
- };
- #define MEM_PSC_FLOW_BLOCK_OR &memPlatSpecFlowOR,
- #else
- #define MEM_PSC_FLOW_BLOCK_OR
- #endif
-
-
- MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[] = {
- MEM_PSC_FLOW_BLOCK_OR
- MEM_PSC_FLOW_BLOCK_END
- };
-
- /*---------------------------------------------------------------------------------------------------
- *
- * LRDIMM CONTROL
- *
- *---------------------------------------------------------------------------------------------------
- */
- #if (OPTION_LRDIMMS == TRUE)
- #if (OPTION_MEMCTLR_OR == TRUE)
- extern MEM_TECH_FEAT MemTLrdimmConstructor3;
- #define MEM_TECH_FEATURE_LRDIMM_INIT &MemTLrdimmConstructor3
- #else //#if (OPTION_MEMCTLR_OR == FALSE)
- #define MEM_TECH_FEATURE_LRDIMM_INIT MemTFeatDef
- #endif
- #else //#if (OPTION_LRDIMMS == FALSE)
- #define MEM_TECH_FEATURE_LRDIMM_INIT MemTFeatDef
- #endif
- MEM_TECH_LRDIMM memLrdimmSupported = {
- MEM_TECH_LRDIMM_STRUCT_VERSION,
- MEM_TECH_FEATURE_LRDIMM_INIT
- };
-#else
- /*---------------------------------------------------------------------------------------------------
- * MAIN FLOW CONTROL
- *
- *
- *---------------------------------------------------------------------------------------------------
- */
- MEM_FLOW_CFG* memFlowControlInstalled[] = {
- NULL
- };
- /*---------------------------------------------------------------------------------------------------
- * NB TRAINING FLOW CONTROL
- *
- *
- *---------------------------------------------------------------------------------------------------
- */
- OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = { // Training flow control
- NULL
- };
- /*---------------------------------------------------------------------------------------------------
- * DEFAULT TECHNOLOGY BLOCK
- *
- *
- *---------------------------------------------------------------------------------------------------
- */
- MEM_TECH_CONSTRUCTOR* memTechInstalled[] = { // Types of technology installed
- NULL
- };
-
- /*---------------------------------------------------------------------------------------------------
- * DEFAULT TECHNOLOGY MAP
- *
- *
- *---------------------------------------------------------------------------------------------------
- */
- UINT8 MemoryTechnologyMap[MAX_SOCKETS_SUPPORTED] = {0, 0, 0, 0, 0, 0, 0, 0};
-
- /*---------------------------------------------------------------------------------------------------
- * DEFAULT MAIN FEATURE BLOCK
- *---------------------------------------------------------------------------------------------------
- */
- MEM_FEAT_BLOCK_MAIN MemFeatMain = {
- NULL
- };
-
- /*---------------------------------------------------------------------------------------------------
- * DEFAULT NORTHBRIDGE SUPPORT LIST
- *
- *
- *---------------------------------------------------------------------------------------------------
- */
- #if (OPTION_MEMCTLR_DR == TRUE)
- #undef MEM_NB_SUPPORT_DR
- #define MEM_NB_SUPPORT_DR { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR, MEM_IDENDIMM_DR },
- #endif
- #if (OPTION_MEMCTLR_RB == TRUE)
- #undef MEM_NB_SUPPORT_RB
- #define MEM_NB_SUPPORT_RB { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB, MEM_IDENDIMM_RB },
- #endif
- #if (OPTION_MEMCTLR_DA == TRUE)
- #undef MEM_NB_SUPPORT_DA
- #define MEM_NB_SUPPORT_DA { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA, MEM_IDENDIMM_DA },
- #endif
- #if (OPTION_MEMCTLR_PH == TRUE)
- #undef MEM_NB_SUPPORT_PH
- #define MEM_NB_SUPPORT_PH { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH, MEM_IDENDIMM_PH },
- #endif
- #if (OPTION_MEMCTLR_HY == TRUE)
- #undef MEM_NB_SUPPORT_HY
- #define MEM_NB_SUPPORT_HY { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY, MEM_IDENDIMM_HY },
- #endif
- #if (OPTION_MEMCTLR_C32 == TRUE)
- #undef MEM_NB_SUPPORT_C32
- #define MEM_NB_SUPPORT_C32 { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32, MEM_IDENDIMM_C32 },
- #endif
- #if (OPTION_MEMCTLR_LN == TRUE)
- #undef MEM_NB_SUPPORT_LN
- #define MEM_NB_SUPPORT_LN { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN, MEM_IDENDIMM_LN },
- #endif
- #if (OPTION_MEMCTLR_ON == TRUE)
- #undef MEM_NB_SUPPORT_ON
- #define MEM_NB_SUPPORT_ON { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON, MEM_IDENDIMM_ON },
- #endif
- #if (OPTION_MEMCTLR_OR == TRUE)
- #undef MEM_NB_SUPPORT_OR
- #define MEM_NB_SUPPORT_OR { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR, MEM_IDENDIMM_OR },
- #endif
- /*---------------------------------------------------------------------------------------------------
- * DEFAULT Technology Training
- *
- *
- *---------------------------------------------------------------------------------------------------
- */
- #if OPTION_DDR2
- MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR2 = {
- NULL
- };
- MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = {
- NULL
- };
- #endif
- #if OPTION_DDR3
- MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR3 = {
- NULL
- };
- MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = {
- NULL
- };
- #endif
- /*---------------------------------------------------------------------------------------------------
- * DEFAULT Platform Specific list
- *
- *
- *---------------------------------------------------------------------------------------------------
- */
- #if (OPTION_MEMCTLR_DR == TRUE)
- MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDr[MAX_FF_TYPES] = {
- NULL
- };
- #endif
- #if (OPTION_MEMCTLR_RB == TRUE)
- MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledRb[MAX_FF_TYPES] = {
- NULL
- };
- #endif
- #if (OPTION_MEMCTLR_DA == TRUE)
- MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDA[MAX_FF_TYPES] = {
- NULL
- };
- #endif
- #if (OPTION_MEMCTLR_Ni == TRUE)
- MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledNi[MAX_FF_TYPES] = {
- NULL
- };
- #endif
- #if (OPTION_MEMCTLR_PH == TRUE)
- MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledPh[MAX_FF_TYPES] = {
- NULL
- };
- #endif
- #if (OPTION_MEMCTLR_LN == TRUE)
- MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledLN[MAX_FF_TYPES] = {
- NULL
- };
- #endif
- #if (OPTION_MEMCTLR_HY == TRUE)
- MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledHy[MAX_FF_TYPES] = {
- NULL
- };
- #endif
- #if (OPTION_MEMCTLR_OR == TRUE)
- MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledOr[MAX_FF_TYPES] = {
- NULL
- };
- #endif
- #if (OPTION_MEMCTLR_C32 == TRUE)
- MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledC32[MAX_FF_TYPES] = {
- NULL
- };
- #endif
- #if (OPTION_MEMCTLR_ON == TRUE)
- MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledON[MAX_FF_TYPES] = {
- NULL
- };
- #endif
- /*----------------------------------------------------------------------
- * DEFAULT PSCFG DEFINITIONS
- *
- *----------------------------------------------------------------------
- */
- MEM_PLATFORM_CFG* memPlatformTypeInstalled[] = {
- NULL
- };
-
- /*----------------------------------------------------------------------
- * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION
- *
- *----------------------------------------------------------------------
- */
- MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[] = {
- NULL
- };
-
- MEM_TECH_LRDIMM memLrdimmSupported = {
- MEM_TECH_LRDIMM_STRUCT_VERSION,
- NULL
- };
-#endif
-
-/*---------------------------------------------------------------------------------------------------
- * NORTHBRIDGE SUPPORT LIST
- *
- *
- *---------------------------------------------------------------------------------------------------
- */
-MEM_NB_SUPPORT memNBInstalled[] = {
- MEM_NB_SUPPORT_RB
- MEM_NB_SUPPORT_DA
- MEM_NB_SUPPORT_Ni
- MEM_NB_SUPPORT_PH
- MEM_NB_SUPPORT_HY
- MEM_NB_SUPPORT_LN
- MEM_NB_SUPPORT_OR
- MEM_NB_SUPPORT_C32
- MEM_NB_SUPPORT_ON
- MEM_NB_SUPPORT_END
-};
-
-#endif // _OPTION_MEMORY_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionMemoryRecovery.h b/src/vendorcode/amd/agesa/Include/OptionMemoryRecovery.h
deleted file mode 100644
index 443a3ca..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionMemoryRecovery.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Memory option API.
- *
- * Contains structures and values used to control the Memory option code.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: OPTION
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_MEMORY_RECOVERY_H_
-#define _OPTION_MEMORY_RECOVERY_H_
-
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-
-typedef BOOLEAN MEM_REC_NB_CONSTRUCTOR (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- );
-
-typedef VOID MEM_REC_TECH_CONSTRUCTOR (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-#endif // _OPTION_MEMORY_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionMemoryRecoveryInstall.h b/src/vendorcode/amd/agesa/Include/OptionMemoryRecoveryInstall.h
deleted file mode 100644
index 2019947..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionMemoryRecoveryInstall.h
+++ /dev/null
@@ -1,602 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: Memory
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Options
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_MEMORY_RECOVERY_INSTALL_H_
-#define _OPTION_MEMORY_RECOVERY_INSTALL_H_
-
-#if (AGESA_ENTRY_INIT_RECOVERY == TRUE)
-
- #define MEM_REC_NB_SUPPORT_OR
-
- #if (OPTION_MEMCTLR_DR == TRUE)
- extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockDR;
- #define MEM_REC_NB_SUPPORT_DR MemRecConstructNBBlockDR,
- #else
- #define MEM_REC_NB_SUPPORT_DR
- #endif
- #if (OPTION_MEMCTLR_RB == TRUE)
- extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockRb;
- #define MEM_REC_NB_SUPPORT_RB MemRecConstructNBBlockRb,
- #else
- #define MEM_REC_NB_SUPPORT_RB
- #endif
- #if (OPTION_MEMCTLR_DA == TRUE)
- extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockDA;
- #define MEM_REC_NB_SUPPORT_DA MemRecConstructNBBlockDA,
- #else
- #define MEM_REC_NB_SUPPORT_DA
- #endif
- #if (OPTION_MEMCTLR_NI == TRUE)
- extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockNi;
- #define MEM_REC_NB_SUPPORT_NI MemRecConstructNBBlockNi,
- #else
- #define MEM_REC_NB_SUPPORT_NI
- #endif
- #if (OPTION_MEMCTLR_PH == TRUE)
- extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockPh;
- #define MEM_REC_NB_SUPPORT_PH MemRecConstructNBBlockPh,
- #else
- #define MEM_REC_NB_SUPPORT_PH
- #endif
- #if (OPTION_MEMCTLR_HY == TRUE)
- extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockHY;
- #define MEM_REC_NB_SUPPORT_HY MemRecConstructNBBlockHY,
- #else
- #define MEM_REC_NB_SUPPORT_HY
- #endif
- #if (OPTION_MEMCTLR_C32 == TRUE)
- extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockC32;
- #define MEM_REC_NB_SUPPORT_C32 MemRecConstructNBBlockC32,
- #else
- #define MEM_REC_NB_SUPPORT_C32
- #endif
- #if (OPTION_MEMCTLR_LN == TRUE)
- extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockLN;
- #define MEM_REC_NB_SUPPORT_LN MemRecConstructNBBlockLN,
- #else
- #define MEM_REC_NB_SUPPORT_LN
- #endif
- #if (OPTION_MEMCTLR_ON == TRUE)
- extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockON;
- #define MEM_REC_NB_SUPPORT_ON MemRecConstructNBBlockON,
- #else
- #define MEM_REC_NB_SUPPORT_ON
- #endif
-
- MEM_REC_NB_CONSTRUCTOR* MemRecNBInstalled[] = {
- MEM_REC_NB_SUPPORT_DR
- MEM_REC_NB_SUPPORT_RB
- MEM_REC_NB_SUPPORT_DA
- MEM_REC_NB_SUPPORT_PH
- MEM_REC_NB_SUPPORT_HY
- MEM_REC_NB_SUPPORT_C32
- MEM_REC_NB_SUPPORT_LN
- MEM_REC_NB_SUPPORT_OR
- MEM_REC_NB_SUPPORT_ON
- MEM_REC_NB_SUPPORT_NI
- NULL
- };
-
- #define MEM_REC_TECH_CONSTRUCTOR_DDR2
- #if (OPTION_DDR3 == TRUE)
- extern MEM_REC_TECH_CONSTRUCTOR MemRecConstructTechBlock3;
- #define MEM_REC_TECH_CONSTRUCTOR_DDR3 MemRecConstructTechBlock3,
- #else
- #define MEM_REC_TECH_CONSTRUCTOR_DDR3
- #endif
-
- MEM_REC_TECH_CONSTRUCTOR* MemRecTechInstalled[] = {
- MEM_REC_TECH_CONSTRUCTOR_DDR3
- MEM_REC_TECH_CONSTRUCTOR_DDR2
- NULL
- };
-
- #if OPTION_MEMCTLR_DR
- #define PSC_REC_DR_UDIMM_DDR2
- #define PSC_REC_DR_UDIMM_DDR3 MemRecNGetPsCfgUDIMM3Nb,
- #define PSC_REC_DR_RDIMM_DDR2
- #define PSC_REC_DR_RDIMM_DDR3 MemRecNGetPsCfgRDIMM3Nb,
- #define PSC_REC_DR_SODIMM_DDR2
- #define PSC_REC_DR_SODIMM_DDR3 MemRecNGetPsCfgSODIMM3Nb,
- #endif
- #if ((OPTION_MEMCTLR_DA == TRUE) || (OPTION_MEMCTLR_Ni == TRUE) || (OPTION_MEMCTLR_PH == TRUE) || (OPTION_MEMCTLR_RB == TRUE))
- #define PSC_REC_DA_UDIMM_DDR3 MemRecNGetPsCfgUDIMM3Nb,
- #define PSC_REC_DA_SODIMM_DDR2
- #define PSC_REC_DA_SODIMM_DDR3 MemRecNGetPsCfgSODIMM3Nb,
- #endif
- #if OPTION_MEMCTLR_HY
- #define PSC_REC_HY_UDIMM_DDR3 MemRecNGetPsCfgUDIMM3Nb,
- #define PSC_REC_HY_RDIMM_DDR3 MemRecNGetPsCfgRDIMM3Nb,
- #endif
- #if OPTION_MEMCTLR_C32
- #define PSC_REC_C32_UDIMM_DDR3 MemRecNGetPsCfgUDIMM3Nb,
- #define PSC_REC_C32_RDIMM_DDR3 MemRecNGetPsCfgRDIMM3Nb,
- #endif
- #if OPTION_MEMCTLR_OR
- #define PSC_REC_OR_UDIMM_DDR3 //MemRecNGetPsCfgUDIMM3OR,
- #define PSC_REC_OR_RDIMM_DDR3 //MemRecNGetPsCfgRDIMM3OR,
- #endif
-
- #ifndef PSC_REC_DR_UDIMM_DDR2
- #define PSC_REC_DR_UDIMM_DDR2
- #endif
- #ifndef PSC_REC_DR_UDIMM_DDR3
- #define PSC_REC_DR_UDIMM_DDR3
- #endif
- #ifndef PSC_REC_DR_RDIMM_DDR2
- #define PSC_REC_DR_RDIMM_DDR2
- #endif
- #ifndef PSC_REC_DR_RDIMM_DDR3
- #define PSC_REC_DR_RDIMM_DDR3
- #endif
- #ifndef PSC_REC_DR_SODIMM_DDR2
- #define PSC_REC_DR_SODIMM_DDR2
- #endif
- #ifndef PSC_REC_DR_SODIMM_DDR3
- #define PSC_REC_DR_SODIMM_DDR3
- #endif
- #ifndef PSC_REC_DA_UDIMM_DDR3
- #define PSC_REC_DA_UDIMM_DDR3
- #endif
- #ifndef PSC_REC_DA_SODIMM_DDR2
- #define PSC_REC_DA_SODIMM_DDR2
- #endif
- #ifndef PSC_REC_DA_SODIMM_DDR3
- #define PSC_REC_DA_SODIMM_DDR3
- #endif
- #ifndef PSC_REC_HY_UDIMM_DDR3
- #define PSC_REC_HY_UDIMM_DDR3
- #endif
- #ifndef PSC_REC_HY_RDIMM_DDR3
- #define PSC_REC_HY_RDIMM_DDR3
- #endif
- #ifndef PSC_REC_C32_UDIMM_DDR3
- #define PSC_REC_C32_UDIMM_DDR3
- #endif
- #ifndef PSC_REC_C32_RDIMM_DDR3
- #define PSC_REC_C32_RDIMM_DDR3
- #endif
- #ifndef PSC_REC_OR_UDIMM_DDR3
- #define PSC_REC_OR_UDIMM_DDR3
- #endif
- #ifndef PSC_REC_OR_RDIMM_DDR3
- #define PSC_REC_OR_RDIMM_DDR3
- #endif
-
- MEM_PLATFORM_CFG* memRecPlatformTypeInstalled[] = {
- PSC_REC_DR_UDIMM_DDR2
- PSC_REC_DR_RDIMM_DDR2
- PSC_REC_DR_SODIMM_DDR2
- PSC_REC_DR_UDIMM_DDR3
- PSC_REC_DR_RDIMM_DDR3
- PSC_REC_DR_SODIMM_DDR3
- PSC_REC_DA_SODIMM_DDR2
- PSC_REC_DA_UDIMM_DDR3
- PSC_REC_DA_SODIMM_DDR3
- PSC_REC_HY_UDIMM_DDR3
- PSC_REC_HY_RDIMM_DDR3
- PSC_REC_C32_UDIMM_DDR3
- PSC_REC_C32_RDIMM_DDR3
- PSC_REC_OR_UDIMM_DDR3
- PSC_REC_OR_RDIMM_DDR3
- NULL
- };
-
- /*---------------------------------------------------------------------------------------------------
- * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION
- *
- *
- *---------------------------------------------------------------------------------------------------
- */
- #define MEM_PSC_REC_FLOW_BLOCK_END NULL
- #define PSC_REC_TBL_END NULL
- #define MEM_REC_PSC_FLOW_DEFTRUE (BOOLEAN (*) (MEM_NB_BLOCK*, MEM_PSC_TABLE_BLOCK *)) memDefTrue
-
- #if OPTION_MEMCTLR_OR
- #if OPTION_UDIMMS
- #if OPTION_AM3_SOCKET_SUPPORT
- extern PSC_TBL_ENTRY RecDramTermTblEntUAM3;
- #define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_AM3 &RecDramTermTblEntUAM3,
- extern PSC_TBL_ENTRY RecOdtPat1DTblEntUAM3;
- #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 &RecOdtPat1DTblEntUAM3,
- extern PSC_TBL_ENTRY RecOdtPat2DTblEntUAM3;
- #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3 &RecOdtPat2DTblEntUAM3,
- extern PSC_TBL_ENTRY RecOdtPat3DTblEntUAM3;
- #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 &RecOdtPat3DTblEntUAM3,
- extern PSC_TBL_ENTRY RecSAOTblEntUAM3;
- #define PSC_REC_TBL_OR_UDIMM3_SAO_AM3 &RecSAOTblEntUAM3,
- #endif
- #if OPTION_C32_SOCKET_SUPPORT
- extern PSC_TBL_ENTRY RecDramTermTblEntUC32;
- #define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_C32 &RecDramTermTblEntUC32,
- extern PSC_TBL_ENTRY RecOdtPat1DTblEntUC32;
- #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 &RecOdtPat1DTblEntUC32,
- extern PSC_TBL_ENTRY RecOdtPat2DTblEntUC32;
- #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_C32 &RecOdtPat2DTblEntUC32,
- extern PSC_TBL_ENTRY RecOdtPat3DTblEntUC32;
- #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 &RecOdtPat3DTblEntUC32,
- extern PSC_TBL_ENTRY RecSAOTblEntUC32;
- #define PSC_REC_TBL_OR_UDIMM3_SAO_C32 &RecSAOTblEntUC32,
- #endif
- #if OPTION_G34_SOCKET_SUPPORT
- extern PSC_TBL_ENTRY RecDramTermTblEntUG34;
- #define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_G34 &RecDramTermTblEntUG34,
- extern PSC_TBL_ENTRY RecOdtPat1DTblEntUG34;
- #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 &RecOdtPat1DTblEntUG34,
- extern PSC_TBL_ENTRY RecOdtPat2DTblEntUG34;
- #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_G34 &RecOdtPat2DTblEntUG34,
- extern PSC_TBL_ENTRY RecOdtPat3DTblEntUG34;
- #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 &RecOdtPat3DTblEntUG34,
- extern PSC_TBL_ENTRY RecSAOTblEntUG34;
- #define PSC_REC_TBL_OR_UDIMM3_SAO_G34 &RecSAOTblEntUG34,
- #endif
- #endif
- #if OPTION_RDIMMS
- #if OPTION_C32_SOCKET_SUPPORT
- extern PSC_TBL_ENTRY RecDramTermTblEntRC32;
- #define PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_C32 &RecDramTermTblEntRC32,
- extern PSC_TBL_ENTRY RecOdtPat1DTblEntRC32;
- #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 &RecOdtPat1DTblEntRC32,
- extern PSC_TBL_ENTRY RecOdtPat2DTblEntRC32;
- #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_C32 &RecOdtPat2DTblEntRC32,
- extern PSC_TBL_ENTRY RecOdtPat3DTblEntRC32;
- #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 &RecOdtPat3DTblEntRC32,
- extern PSC_TBL_ENTRY RecSAOTblEntRC32;
- #define PSC_REC_TBL_OR_RDIMM3_SAO_C32 &RecSAOTblEntRC32,
- extern PSC_TBL_ENTRY RecRC2IBTTblEntRC32;
- #define PSC_REC_TBL_OR_RDIMM3_RC2IBT_C32 &RecRC2IBTTblEntRC32,
- #endif
- #if OPTION_G34_SOCKET_SUPPORT
- extern PSC_TBL_ENTRY RecDramTermTblEntRG34;
- #define PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_G34 &RecDramTermTblEntRG34,
- extern PSC_TBL_ENTRY RecOdtPat1DTblEntRG34;
- #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 &RecOdtPat1DTblEntRG34,
- extern PSC_TBL_ENTRY RecOdtPat2DTblEntRG34;
- #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_G34 &RecOdtPat2DTblEntRG34,
- extern PSC_TBL_ENTRY RecOdtPat3DTblEntRG34;
- #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 &RecOdtPat3DTblEntRG34,
- extern PSC_TBL_ENTRY RecSAOTblEntRG34;
- #define PSC_REC_TBL_OR_RDIMM3_SAO_G34 &RecSAOTblEntRG34,
- extern PSC_TBL_ENTRY RecRC2IBTTblEntRG34;
- #define PSC_REC_TBL_OR_RDIMM3_RC2IBT_G34 &RecRC2IBTTblEntRG34,
- #endif
- #endif
- //#if OPTION_SODIMMS
- //#endif
- //#if OPTION_LRDIMMS
- //#endif
- extern PSC_TBL_ENTRY RecMR0WrTblEntry;
- #define PSC_REC_TBL_OR_MR0_WR &RecMR0WrTblEntry,
- extern PSC_TBL_ENTRY RecMR0CLTblEntry;
- #define PSC_REC_TBL_OR_MR0_CL &RecMR0CLTblEntry,
-
- #ifndef PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_AM3
- #define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_AM3
- #endif
- #ifndef PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_C32
- #define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_C32
- #endif
- #ifndef PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_G34
- #define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_G34
- #endif
- #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3
- #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3
- #endif
- #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_C32
- #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_C32
- #endif
- #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_G34
- #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_G34
- #endif
- #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3
- #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3
- #endif
- #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_C32
- #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_C32
- #endif
- #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_G34
- #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_G34
- #endif
- #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3
- #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3
- #endif
- #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_C32
- #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_C32
- #endif
- #ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_G34
- #define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_G34
- #endif
- #ifndef PSC_REC_TBL_OR_UDIMM3_SAO_AM3
- #define PSC_REC_TBL_OR_UDIMM3_SAO_AM3
- #endif
- #ifndef PSC_REC_TBL_OR_UDIMM3_SAO_C32
- #define PSC_REC_TBL_OR_UDIMM3_SAO_C32
- #endif
- #ifndef PSC_REC_TBL_OR_UDIMM3_SAO_G34
- #define PSC_REC_TBL_OR_UDIMM3_SAO_G34
- #endif
- #ifndef PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_AM3
- #define PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_AM3
- #endif
- #ifndef PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_C32
- #define PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_C32
- #endif
- #ifndef PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_G34
- #define PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_G34
- #endif
- #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3
- #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3
- #endif
- #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_C32
- #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_C32
- #endif
- #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_G34
- #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_G34
- #endif
- #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3
- #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3
- #endif
- #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_C32
- #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_C32
- #endif
- #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_G34
- #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_G34
- #endif
- #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3
- #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3
- #endif
- #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_C32
- #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_C32
- #endif
- #ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_G34
- #define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_G34
- #endif
- #ifndef PSC_REC_TBL_OR_RDIMM3_SAO_AM3
- #define PSC_REC_TBL_OR_RDIMM3_SAO_AM3
- #endif
- #ifndef PSC_REC_TBL_OR_RDIMM3_SAO_C32
- #define PSC_REC_TBL_OR_RDIMM3_SAO_C32
- #endif
- #ifndef PSC_REC_TBL_OR_RDIMM3_SAO_G34
- #define PSC_REC_TBL_OR_RDIMM3_SAO_G34
- #endif
- #ifndef PSC_REC_TBL_OR_RDIMM3_RC2IBT_AM3
- #define PSC_REC_TBL_OR_RDIMM3_RC2IBT_AM3
- #endif
- #ifndef PSC_REC_TBL_OR_RDIMM3_RC2IBT_C32
- #define PSC_REC_TBL_OR_RDIMM3_RC2IBT_C32
- #endif
- #ifndef PSC_REC_TBL_OR_RDIMM3_RC2IBT_G34
- #define PSC_REC_TBL_OR_RDIMM3_RC2IBT_G34
- #endif
- #ifndef PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_AM3
- #define PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_AM3
- #endif
- #ifndef PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_C32
- #define PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_C32
- #endif
- #ifndef PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_G34
- #define PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_G34
- #endif
-
- PSC_TBL_ENTRY* memRecPSCTblDramTermArrayOR[] = {
- PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_AM3
- PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_C32
- PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_G34
- PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_AM3
- PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_C32
- PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_G34
- PSC_REC_TBL_END
- };
-
- PSC_TBL_ENTRY* memRecPSCTblODTPatArrayOR[] = {
- PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3
- PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3
- PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3
- PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3
- PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3
- PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3
- PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_C32
- PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_C32
- PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_C32
- PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_C32
- PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_C32
- PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_C32
- PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_G34
- PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_G34
- PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_G34
- PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_G34
- PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_G34
- PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_G34
- PSC_REC_TBL_END
- };
-
- PSC_TBL_ENTRY* memRecPSCTblSAOArrayOR[] = {
- PSC_REC_TBL_OR_UDIMM3_SAO_AM3
- PSC_REC_TBL_OR_UDIMM3_SAO_C32
- PSC_REC_TBL_OR_UDIMM3_SAO_G34
- PSC_REC_TBL_OR_RDIMM3_SAO_AM3
- PSC_REC_TBL_OR_RDIMM3_SAO_C32
- PSC_REC_TBL_OR_RDIMM3_SAO_G34
- PSC_REC_TBL_END
- };
-
- PSC_TBL_ENTRY* memRecPSCTblMR0WRArrayOR[] = {
- PSC_REC_TBL_OR_MR0_WR
- PSC_REC_TBL_END
- };
-
- PSC_TBL_ENTRY* memRecPSCTblMR0CLArrayOR[] = {
- PSC_REC_TBL_OR_MR0_CL
- PSC_REC_TBL_END
- };
-
- PSC_TBL_ENTRY* memRecPSCTblRC2IBTArrayOR[] = {
- PSC_REC_TBL_OR_RDIMM3_RC2IBT_AM3
- PSC_REC_TBL_OR_RDIMM3_RC2IBT_C32
- PSC_REC_TBL_OR_RDIMM3_RC2IBT_G34
- PSC_REC_TBL_END
- };
-
- MEM_PSC_TABLE_BLOCK memRecPSCTblBlockOr = {
- NULL,
- (PSC_TBL_ENTRY **)&memRecPSCTblDramTermArrayOR,
- (PSC_TBL_ENTRY **)&memRecPSCTblODTPatArrayOR,
- (PSC_TBL_ENTRY **)&memRecPSCTblSAOArrayOR,
- (PSC_TBL_ENTRY **)&memRecPSCTblMR0WRArrayOR,
- (PSC_TBL_ENTRY **)&memRecPSCTblMR0CLArrayOR,
- (PSC_TBL_ENTRY **)&memRecPSCTblRC2IBTArrayOR,
- NULL,
- NULL,
- NULL,
- NULL,
- NULL
- };
-
- extern MEM_PSC_FLOW MemPRecGetRttNomWr;
- #define PSC_REC_FLOW_OR_DRAM_TERM MemPRecGetRttNomWr
- extern MEM_PSC_FLOW MemPRecGetODTPattern;
- #define PSC_REC_FLOW_OR_ODT_PATTERN MemPRecGetODTPattern
- extern MEM_PSC_FLOW MemPRecGetSAO;
- #define PSC_REC_FLOW_OR_SAO MemPRecGetSAO
- extern MEM_PSC_FLOW MemPRecGetMR0WrCL;
- #define PSC_REC_FLOW_OR_MR0_WRCL MemPRecGetMR0WrCL
- #if OPTION_RDIMMS
- extern MEM_PSC_FLOW MemPRecGetRC2IBT;
- #define PSC_REC_FLOW_OR_RC2_IBT MemPRecGetRC2IBT
- #endif
- //#if OPTION_LRDIMMS
- extern MEM_PSC_FLOW MemPRecGetLRIBT;
- #define PSC_REC_FLOW_OR_LR_IBT MemPRecGetLRIBT
- extern MEM_PSC_FLOW MemPRecGetLRNPR;
- #define PSC_REC_FLOW_OR_LR_NPR MemPRecGetLRNPR
- extern MEM_PSC_FLOW MemPRecGetLRNLR;
- #define PSC_REC_FLOW_OR_LR_NLR MemPRecGetLRNLR
- //#endif
- #ifndef PSC_REC_FLOW_OR_DRAM_TERM
- #define PSC_REC_FLOW_OR_DRAM_TERM MEM_REC_PSC_FLOW_DEFTRUE
- #endif
- #ifndef PSC_REC_FLOW_OR_ODT_PATTERN
- #define PSC_REC_FLOW_OR_ODT_PATTERN MEM_REC_PSC_FLOW_DEFTRUE
- #endif
- #ifndef PSC_REC_FLOW_OR_SAO
- #define PSC_REC_FLOW_OR_SAO MEM_REC_PSC_FLOW_DEFTRUE
- #endif
- #ifndef PSC_REC_FLOW_OR_MR0_WRCL
- #define PSC_REC_FLOW_OR_MR0_WRCL MEM_REC_PSC_FLOW_DEFTRUE
- #endif
- #ifndef PSC_REC_FLOW_OR_RC2_IBT
- #define PSC_REC_FLOW_OR_RC2_IBT MEM_REC_PSC_FLOW_DEFTRUE
- #endif
- #ifndef PSC_REC_FLOW_OR_LR_IBT
- #define PSC_REC_FLOW_OR_LR_IBT MEM_REC_PSC_FLOW_DEFTRUE
- #endif
- #ifndef PSC_REC_FLOW_OR_LR_NPR
- #define PSC_REC_FLOW_OR_LR_NPR MEM_REC_PSC_FLOW_DEFTRUE
- #endif
- #ifndef PSC_REC_FLOW_OR_LR_NLR
- #define PSC_REC_FLOW_OR_LR_NLR MEM_REC_PSC_FLOW_DEFTRUE
- #endif
- MEM_PSC_FLOW_BLOCK memRecPlatSpecFlowOR = {
- &memRecPSCTblBlockOr,
- NULL,
- PSC_REC_FLOW_OR_DRAM_TERM,
- PSC_REC_FLOW_OR_ODT_PATTERN,
- PSC_REC_FLOW_OR_SAO,
- PSC_REC_FLOW_OR_MR0_WRCL,
- PSC_REC_FLOW_OR_RC2_IBT,
- NULL,
- PSC_REC_FLOW_OR_LR_IBT,
- PSC_REC_FLOW_OR_LR_NPR,
- PSC_REC_FLOW_OR_LR_NLR
- };
- #define MEM_PSC_REC_FLOW_BLOCK_OR &memRecPlatSpecFlowOR,
- #else
- #define MEM_PSC_REC_FLOW_BLOCK_OR
- #endif
-
- MEM_PSC_FLOW_BLOCK* memRecPlatSpecFlowArray[] = {
- MEM_PSC_REC_FLOW_BLOCK_OR
- MEM_PSC_REC_FLOW_BLOCK_END
- };
-
-#else
- /*---------------------------------------------------------------------------------------------------
- * DEFAULT TECHNOLOGY BLOCK
- *
- *
- *---------------------------------------------------------------------------------------------------
- */
- MEM_TECH_CONSTRUCTOR* MemRecTechInstalled[] = { // Types of technology installed
- NULL
- };
- /*---------------------------------------------------------------------------------------------------
- * DEFAULT NORTHBRIDGE SUPPORT LIST
- *
- *
- *---------------------------------------------------------------------------------------------------
- */
- MEM_NB_SUPPORT MemRecNBInstalled[] = {
- NULL
- };
- /*----------------------------------------------------------------------
- * DEFAULT PSCFG DEFINITIONS
- *
- *----------------------------------------------------------------------
- */
- MEM_PLATFORM_CFG* memRecPlatformTypeInstalled[] = {
- NULL
- };
- /*----------------------------------------------------------------------
- * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION
- *
- *----------------------------------------------------------------------
- */
- MEM_PSC_FLOW_BLOCK* memRecPlatSpecFlowArray[] = {
- NULL
- };
-#endif
-#endif // _OPTION_MEMORY_RECOVERY_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionMsgBasedC1eInstall.h b/src/vendorcode/amd/agesa/Include/OptionMsgBasedC1eInstall.h
deleted file mode 100644
index b1d91d9..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionMsgBasedC1eInstall.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: Message-Based C1e
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Options
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_MSG_BASED_C1E_INSTALL_H_
-#define _OPTION_MSG_BASED_C1E_INSTALL_H_
-
-#include "cpuMsgBasedC1e.h"
-
-/* This option is designed to be included into the platform solution install
- * file. The platform solution install file will define the options status.
- * Check to validate the definition
- */
-#define OPTION_MSG_BASED_C1E_FEAT
-#define F10_MSG_BASED_C1E_SUPPORT
-#define F15_MSG_BASED_C1E_SUPPORT
-#if OPTION_MSG_BASED_C1E == TRUE
- #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
-
- #ifdef OPTION_FAMILY10H
- #if OPTION_FAMILY10H == TRUE
- #if OPTION_FAMILY10H_HY == TRUE
- #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE)
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureMsgBasedC1e;
- #undef OPTION_MSG_BASED_C1E_FEAT
- #define OPTION_MSG_BASED_C1E_FEAT &CpuFeatureMsgBasedC1e,
- #endif
- #endif
- #endif
- #endif
-
- #ifdef OPTION_FAMILY15H
- #if OPTION_FAMILY15H == TRUE
- #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE || OPTION_AM3_SOCKET_SUPPORT == TRUE)
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureMsgBasedC1e;
- #undef OPTION_MSG_BASED_C1E_FEAT
- #define OPTION_MSG_BASED_C1E_FEAT &CpuFeatureMsgBasedC1e,
- #endif
- #endif
- #endif
-
- #ifdef OPTION_FAMILY10H
- #if OPTION_FAMILY10H == TRUE
- #if OPTION_FAMILY10H_HY == TRUE
- #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE)
- extern CONST MSG_BASED_C1E_FAMILY_SERVICES ROMDATA F10MsgBasedC1e;
- #undef F10_MSG_BASED_C1E_SUPPORT
- #define F10_MSG_BASED_C1E_SUPPORT {AMD_FAMILY_10_HY, &F10MsgBasedC1e},
- #endif
- #endif
- #endif
- #endif
-
- #ifdef OPTION_FAMILY15H
- #if OPTION_FAMILY15H == TRUE
- #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE || OPTION_AM3_SOCKET_SUPPORT == TRUE)
- extern CONST MSG_BASED_C1E_FAMILY_SERVICES ROMDATA F15MsgBasedC1e;
- #undef F15_MSG_BASED_C1E_SUPPORT
- #define F15_MSG_BASED_C1E_SUPPORT {AMD_FAMILY_15, &F15MsgBasedC1e},
- #endif
- #endif
- #endif
-
- CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA MsgBasedC1eFamilyServiceArray[] =
- {
- F10_MSG_BASED_C1E_SUPPORT
- F15_MSG_BASED_C1E_SUPPORT
- {0, NULL}
- };
- CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA MsgBasedC1eFamilyServiceTable =
- {
- (sizeof (MsgBasedC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
- &MsgBasedC1eFamilyServiceArray[0]
- };
- #endif
-#endif
-#endif // _OPTION_MSG_BASED_C1E_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionMultiSocket.h b/src/vendorcode/amd/agesa/Include/OptionMultiSocket.h
deleted file mode 100644
index 1e3fd14..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionMultiSocket.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Multi-socket option API.
- *
- * Contains structures and values used to control the multi-socket option code.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: OPTION
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_MULTISOCKET_H_
-#define _OPTION_MULTISOCKET_H_
-
-/*----------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *----------------------------------------------------------------------------------------
- */
-
-/**
- * This function loops through all possible socket locations, gathering the number
- * of power management steps each populated socket requires, and returns the
- * highest number.
- *
- * @param[out] NumSystemSteps Maximum number of system steps required
- * @param[in] StdHeader Config handle for library and services
- *
- */
-typedef VOID OPTION_MULTISOCKET_PM_STEPS (
- OUT UINT8 *NumSystemSteps,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * This function loops through all possible socket locations, starting core 0 of
- * each populated socket to perform the passed in AP_TASK. After starting all
- * other core 0s, the BSC will perform the AP_TASK as well. This must be run by
- * the system BSC only.
- *
- * @param[in] TaskPtr Function descriptor
- * @param[in] StdHeader Config handle for library and services
- * @param[in] ConfigParams AMD entry point's CPU parameter structure
- *
- */
-typedef VOID OPTION_MULTISOCKET_PM_CORE0_TASK (
- IN VOID *TaskPtr,
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN VOID *ConfigParams
- );
-
-/**
- * This function loops through all possible socket locations, comparing the
- * maximum NB frequencies to determine the slowest. This function also
- * determines if all coherent NB frequencies are equivalent.
- *
- * @param[in] NbPstate NB P-state number to check (0 = fastest)
- * @param[in] PlatformConfig Platform profile/build option config structure.
- * @param[out] SystemNbCofNumerator NB frequency numerator for the system in MHz
- * @param[out] SystemNbCofDenominator NB frequency denominator for the system
- * @param[out] SystemNbCofsMatch Whether or not all NB frequencies are equivalent
- * @param[out] NbPstateIsEnabledOnAllCPUs Whether or not NbPstate is valid on all CPUs
- * @param[in] StdHeader Config handle for library and services
- *
- * @retval TRUE At least one processor has NbPstate enabled.
- * @retval FALSE NbPstate is disabled on all CPUs
- */
-typedef BOOLEAN OPTION_MULTISOCKET_PM_NB_COF (
- IN UINT32 NbPstate,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- OUT UINT32 *SystemNbCofNumerator,
- OUT UINT32 *SystemNbCofDenominator,
- OUT BOOLEAN *SystemNbCofsMatch,
- OUT BOOLEAN *NbPstateIsEnabledOnAllCPUs,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * This function loops through all possible socket locations, checking whether
- * any populated sockets require NB COF VID programming.
- *
- * @param[in] StdHeader Config handle for library and services
- *
- */
-typedef BOOLEAN OPTION_MULTISOCKET_PM_NB_COF_UPDATE (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * This function loops through all possible socket locations, collecting any
- * power management initialization errors that may have occurred. These errors
- * are transferred from the core 0s of the socket in which the errors occurred
- * to the BSC's heap. The BSC's heap is then searched for the most severe error
- * that occurred, and returns it. This function must be called by the BSC only.
- *
- * @param[in] StdHeader Config handle for library and services
- *
- */
-typedef AGESA_STATUS OPTION_MULTISOCKET_PM_GET_EVENTS (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#define MULTISOCKET_STRUCT_VERSION 0x01
-
-/**
- * Provide build configuration of cpu multi-socket or single socket support.
- *
- */
-typedef struct {
- UINT16 OptMultiSocketVersion; ///< Table version
- OPTION_MULTISOCKET_PM_STEPS *GetNumberOfSystemPmSteps; ///< Method: Get number of power mgt tasks
- OPTION_MULTISOCKET_PM_CORE0_TASK *BscRunCodeOnAllSystemCore0s; ///< Method: Perform tasks on Core 0 of each processor
- OPTION_MULTISOCKET_PM_NB_COF *GetSystemNbPstateSettings; ///< Method: Find the limiting Northbridge frequency in the system.
- OPTION_MULTISOCKET_PM_NB_COF_UPDATE *GetSystemNbCofVidUpdate; ///< Method: Determine if any Northbridges in the system need to update their COF/VID.
- OPTION_MULTISOCKET_PM_GET_EVENTS *BscRetrievePmEarlyInitErrors; ///< Method: Gathers error information from all Core 0s.
-} OPTION_MULTISOCKET_CONFIGURATION;
-
-/*----------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *----------------------------------------------------------------------------------------
- */
-
-
-#endif // _OPTION_MULTISOCKET_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionMultiSocketInstall.h b/src/vendorcode/amd/agesa/Include/OptionMultiSocketInstall.h
deleted file mode 100644
index 188212e..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionMultiSocketInstall.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: Multiple Socket Support
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Options
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_MULTISOCKET_INSTALL_H_
-#define _OPTION_MULTISOCKET_INSTALL_H_
-
-/* This option is designed to be included into the platform solution install
- * file. The platform solution install file will define the options status.
- * Check to validate the definition
- */
-#ifndef OPTION_MULTISOCKET
- #error BLDOPT: Option not defined: "OPTION_MULTISOCKET"
-#endif
-
-#if OPTION_MULTISOCKET == TRUE
- OPTION_MULTISOCKET_PM_STEPS GetNumberOfSystemPmStepsPtrMulti;
- #define GET_NUM_PM_STEPS GetNumberOfSystemPmStepsPtrMulti
- OPTION_MULTISOCKET_PM_CORE0_TASK RunCodeOnAllSystemCore0sMulti;
- #define CORE0_PM_TASK RunCodeOnAllSystemCore0sMulti
- OPTION_MULTISOCKET_PM_NB_COF GetSystemNbCofMulti;
- #define GET_SYS_NB_COF GetSystemNbCofMulti
- OPTION_MULTISOCKET_PM_NB_COF_UPDATE GetSystemNbCofVidUpdateMulti;
- #define GET_SYS_NB_COF_UPDATE GetSystemNbCofVidUpdateMulti
- OPTION_MULTISOCKET_PM_GET_EVENTS GetEarlyPmErrorsMulti;
- #define GET_EARLY_PM_ERRORS GetEarlyPmErrorsMulti
-#else
- OPTION_MULTISOCKET_PM_STEPS GetNumberOfSystemPmStepsPtrSingle;
- #define GET_NUM_PM_STEPS GetNumberOfSystemPmStepsPtrSingle
- OPTION_MULTISOCKET_PM_CORE0_TASK RunCodeOnAllSystemCore0sSingle;
- #define CORE0_PM_TASK RunCodeOnAllSystemCore0sSingle
- OPTION_MULTISOCKET_PM_NB_COF GetSystemNbCofSingle;
- #define GET_SYS_NB_COF GetSystemNbCofSingle
- OPTION_MULTISOCKET_PM_NB_COF_UPDATE GetSystemNbCofVidUpdateSingle;
- #define GET_SYS_NB_COF_UPDATE GetSystemNbCofVidUpdateSingle
- OPTION_MULTISOCKET_PM_GET_EVENTS GetEarlyPmErrorsSingle;
- #define GET_EARLY_PM_ERRORS GetEarlyPmErrorsSingle
-#endif
-
-/* Declare the instance of the DMI option configuration structure */
-OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration = {
- MULTISOCKET_STRUCT_VERSION,
- GET_NUM_PM_STEPS,
- CORE0_PM_TASK,
- GET_SYS_NB_COF,
- GET_SYS_NB_COF_UPDATE,
- GET_EARLY_PM_ERRORS
-};
-
-#endif // _OPTION_MULTISOCKET_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionPreserveMailboxInstall.h b/src/vendorcode/amd/agesa/Include/OptionPreserveMailboxInstall.h
deleted file mode 100644
index bd7d3f4..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionPreserveMailboxInstall.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: Preserve Mailbox
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Options
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_PRESERVE_MAILBOX_INSTALL_H_
-#define _OPTION_PRESERVE_MAILBOX_INSTALL_H_
-
-#include "PreserveMailbox.h"
-
-/* This option is designed to be included into the platform solution install
- * file. The platform solution install file will define the options status.
- * Check to validate the definition
- */
-#define OPTION_PRESERVE_MAILBOX_FEAT
-#define F10_PRESERVE_MAILBOX_SUPPORT
-#define F15_PRESERVE_MAILBOX_SUPPORT
-
-#if ((AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE))
- #if ((OPTION_FAMILY10H == TRUE) || (OPTION_FAMILY15H == TRUE))
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePreserveAroundMailbox;
- #undef OPTION_PRESERVE_MAILBOX_FEAT
- #define OPTION_PRESERVE_MAILBOX_FEAT &CpuFeaturePreserveAroundMailbox,
- #endif
- #if OPTION_FAMILY10H == TRUE
- CONST PCI_ADDR ROMDATA F10PreserveMailboxRegisters [] = {
- MAKE_SBDFO (0, 0, 0, 3, 0x168),
- MAKE_SBDFO (0, 0, 0, 3, 0x170),
- ILLEGAL_SBDFO
- };
- CONST PRESERVE_MAILBOX_FAMILY_SERVICES ROMDATA F10PreserveMailboxServices = {
- 0,
- TRUE,
- (PCI_ADDR *)&F10PreserveMailboxRegisters
- };
- #undef F10_PRESERVE_MAILBOX_SUPPORT
- #define F10_PRESERVE_MAILBOX_SUPPORT {AMD_FAMILY_10, &F10PreserveMailboxServices},
- #endif
- #if OPTION_FAMILY15H == TRUE
- CONST PCI_ADDR ROMDATA F15PreserveMailboxRegisters [] = {
- MAKE_SBDFO (0, 0, 0, 3, 0x168),
- MAKE_SBDFO (0, 0, 0, 3, 0x170),
- ILLEGAL_SBDFO
- };
- CONST PRESERVE_MAILBOX_FAMILY_SERVICES ROMDATA F15PreserveMailboxServices = {
- 0,
- TRUE,
- (PCI_ADDR *)&F15PreserveMailboxRegisters
- };
- #undef F15_PRESERVE_MAILBOX_SUPPORT
- #define F15_PRESERVE_MAILBOX_SUPPORT {AMD_FAMILY_15, &F15PreserveMailboxServices},
- #endif
- CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PreserveMailboxFamilyServiceArray[] =
- {
- F10_PRESERVE_MAILBOX_SUPPORT
- F15_PRESERVE_MAILBOX_SUPPORT
- {0, NULL}
- };
- CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PreserveMailboxFamilyServiceTable =
- {
- (sizeof (PreserveMailboxFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
- &PreserveMailboxFamilyServiceArray[0]
- };
-#endif
-
-#endif // _OPTION_PRESERVE_MAILBOX_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionPstate.h b/src/vendorcode/amd/agesa/Include/OptionPstate.h
deleted file mode 100644
index 27e1478..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionPstate.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD ACPI PState option API.
- *
- * Contains structures and values used to control the PStates option code.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: OPTION
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_PSTATE_H_
-#define _OPTION_PSTATE_H_
-
-#include "cpuPstateTables.h"
-
-/*----------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *----------------------------------------------------------------------------------------
- */
-
-typedef AGESA_STATUS OPTION_SSDT_FEATURE (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN OUT VOID **AcpiPstatePtr
- );
-
-typedef UINT32 OPTION_ACPI_FEATURE (
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN PSTATE_LEVELING *PStateLevelingBuffer,
- IN OUT VOID **AcpiPStatePtr,
- IN UINT8 LocalApicId,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-typedef AGESA_STATUS OPTION_PSTATE_GATHER (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr
- );
-
-typedef AGESA_STATUS OPTION_PSTATE_LEVELING (
- IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#define PSTATE_STRUCT_VERSION 0x01
-
-/// Indirection vectors for POST/PEI PState code
-typedef struct {
- UINT16 OptPstateVersion; ///< revision of this structure
- OPTION_PSTATE_GATHER *PstateGather; ///< vector for data gathering routine
- OPTION_PSTATE_LEVELING *PstateLeveling; ///< vector for leveling routine
-} OPTION_PSTATE_POST_CONFIGURATION;
-
-/// Indirection vectors for LATE/DXE PState code
-typedef struct {
- UINT16 OptPstateVersion; ///< revision of this structure
- OPTION_SSDT_FEATURE *SsdtFeature; ///< vector for routine to generate SSDT
- OPTION_ACPI_FEATURE *PstateFeature; ///< vector for routine to generate ACPI PState Objects
- OPTION_ACPI_FEATURE *CstateFeature; ///< vector for routine to generate ACPI CState Objects
- BOOLEAN CfgPstatePpc; ///< boolean for creating _PPC method
- BOOLEAN CfgPstatePct; ///< boolean for creating _PCT method
- BOOLEAN CfgPstatePsd; ///< boolean for creating _PSD method
- BOOLEAN CfgPstatePss; ///< boolean for creating _PSS method
- BOOLEAN CfgPstateXpss; ///< boolean for creating _XPSS method
-} OPTION_PSTATE_LATE_CONFIGURATION;
-
-/*----------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *----------------------------------------------------------------------------------------
- */
-
-#endif // _OPTION_PSTATE_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionPstateInstall.h b/src/vendorcode/amd/agesa/Include/OptionPstateInstall.h
deleted file mode 100644
index 11ae4d3..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionPstateInstall.h
+++ /dev/null
@@ -1,243 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: PState
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Options
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_PSTATE_INSTALL_H_
-#define _OPTION_PSTATE_INSTALL_H_
-
-#include "cpuPstateTables.h"
-
-/* This option is designed to be included into the platform solution install
- * file. The platform solution install file will define the options status.
- * Check to validate the definition
- */
-
-#define F10_PSTATE_SERVICE_SUPPORT
-#define F12_PSTATE_SERVICE_SUPPORT
-#define F14_PSTATE_SERVICE_SUPPORT
-#define F15_PSTATE_SERVICE_SUPPORT
-
-#if ((AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE))
- //
- //Define Pstate CPU Family service
- //
- #ifdef OPTION_FAMILY10H
- #if OPTION_FAMILY10H == TRUE
- extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F10PstateServices;
- #undef F10_PSTATE_SERVICE_SUPPORT
- #define F10_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_10, &F10PstateServices},
- #endif
- #endif
-
- #ifdef OPTION_FAMILY12H
- #if OPTION_FAMILY12H == TRUE
- extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F12PstateServices;
- #undef F12_PSTATE_SERVICE_SUPPORT
- #define F12_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_12, &F12PstateServices},
- #endif
- #endif
-
- #ifdef OPTION_FAMILY14H
- #if OPTION_FAMILY14H == TRUE
- extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F14PstateServices;
- #undef F14_PSTATE_SERVICE_SUPPORT
- #define F14_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_14, &F14PstateServices},
- #endif
- #endif
-
- #ifdef OPTION_FAMILY15H
- #if OPTION_FAMILY15H == TRUE
- extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F15PstateServices;
- #undef F15_PSTATE_SERVICE_SUPPORT
- #define F15_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_15, &F15PstateServices},
- #endif
- #endif
- //
- //Define ACPI Pstate objects.
- //
- #ifndef OPTION_ACPI_PSTATES
- #error BLDOPT: Option not defined: "OPTION_ACPI_PSTATES"
- #endif
- #if (OPTION_ACPI_PSTATES == TRUE)
- OPTION_SSDT_FEATURE GenerateSsdt;
- #define USER_SSDT_MAIN GenerateSsdt
- #ifndef OPTION_MULTISOCKET
- #error BLDOPT: Option not defined: "OPTION_MULTISOCKET"
- #endif
-
- OPTION_ACPI_FEATURE CreatePStateAcpiTables;
- OPTION_PSTATE_GATHER PStateGatherMain;
- #if ((OPTION_MULTISOCKET == TRUE) && (AGESA_ENTRY_INIT_POST == TRUE))
- OPTION_PSTATE_LEVELING PStateLevelingMain;
- #define USER_PSTATE_OPTION_LEVEL PStateLevelingMain
- #else
- OPTION_PSTATE_LEVELING PStateLevelingStub;
- #define USER_PSTATE_OPTION_LEVEL PStateLevelingStub
- #endif
- #if AGESA_ENTRY_INIT_LATE == TRUE
- #define USER_PSTATE_OPTION_MAIN CreatePStateAcpiTables
- #else
- OPTION_ACPI_FEATURE CreateAcpiTablesStub;
- #define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub
- #endif
- #if AGESA_ENTRY_INIT_POST == TRUE
- #define USER_PSTATE_OPTION_GATHER PStateGatherMain
- #else
- OPTION_PSTATE_GATHER PStateGatherStub;
- #define USER_PSTATE_OPTION_GATHER PStateGatherStub
- #endif
- #if CFG_ACPI_PSTATES_PPC == TRUE
- #define USER_PSTATE_CFG_PPC TRUE
- #else
- #define USER_PSTATE_CFG_PPC FALSE
- #endif
- #if CFG_ACPI_PSTATES_PCT == TRUE
- #define USER_PSTATE_CFG_PCT TRUE
- #else
- #define USER_PSTATE_CFG_PCT FALSE
- #endif
- #if CFG_ACPI_PSTATES_PSD == TRUE
- #define USER_PSTATE_CFG_PSD TRUE
- #else
- #define USER_PSTATE_CFG_PSD FALSE
- #endif
- #if CFG_ACPI_PSTATES_PSS == TRUE
- #define USER_PSTATE_CFG_PSS TRUE
- #else
- #define USER_PSTATE_CFG_PSS FALSE
- #endif
- #if CFG_ACPI_PSTATES_XPSS == TRUE
- #define USER_PSTATE_CFG_XPSS TRUE
- #else
- #define USER_PSTATE_CFG_XPSS FALSE
- #endif
-
- #if OPTION_IO_CSTATE == TRUE
- OPTION_ACPI_FEATURE CreateCStateAcpiTables;
- #define USER_CSTATE_OPTION_MAIN CreateCStateAcpiTables
- #else
- OPTION_ACPI_FEATURE CreateAcpiTablesStub;
- #define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub
- #endif
- #else
- OPTION_SSDT_FEATURE GenerateSsdtStub;
- OPTION_ACPI_FEATURE CreateAcpiTablesStub;
- OPTION_PSTATE_GATHER PStateGatherStub;
- OPTION_PSTATE_LEVELING PStateLevelingStub;
- #define USER_SSDT_MAIN GenerateSsdtStub
- #define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub
- #define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub
- #define USER_PSTATE_OPTION_GATHER PStateGatherStub
- #define USER_PSTATE_OPTION_LEVEL PStateLevelingStub
- #define USER_PSTATE_CFG_PPC FALSE
- #define USER_PSTATE_CFG_PCT FALSE
- #define USER_PSTATE_CFG_PSD FALSE
- #define USER_PSTATE_CFG_PSS FALSE
- #define USER_PSTATE_CFG_XPSS FALSE
-
- // If ACPI Objects are disabled for PStates, we still need to check
- // whether ACPI Objects are enabled for CStates
- #if OPTION_IO_CSTATE == TRUE
- OPTION_SSDT_FEATURE GenerateSsdt;
- OPTION_PSTATE_GATHER PStateGatherMain;
- OPTION_ACPI_FEATURE CreateCStateAcpiTables;
- #undef USER_SSDT_MAIN
- #define USER_SSDT_MAIN GenerateSsdt
- #undef USER_PSTATE_OPTION_GATHER
- #define USER_PSTATE_OPTION_GATHER PStateGatherMain
- #undef USER_CSTATE_OPTION_MAIN
- #define USER_CSTATE_OPTION_MAIN CreateCStateAcpiTables
- #endif
- #endif
-#else
- OPTION_SSDT_FEATURE GenerateSsdtStub;
- OPTION_ACPI_FEATURE CreateAcpiTablesStub;
- OPTION_PSTATE_GATHER PStateGatherStub;
- OPTION_PSTATE_LEVELING PStateLevelingStub;
- #define USER_SSDT_MAIN GenerateSsdtStub
- #define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub
- #define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub
- #define USER_PSTATE_OPTION_GATHER PStateGatherStub
- #define USER_PSTATE_OPTION_LEVEL PStateLevelingStub
- #define USER_PSTATE_CFG_PPC FALSE
- #define USER_PSTATE_CFG_PCT FALSE
- #define USER_PSTATE_CFG_PSD FALSE
- #define USER_PSTATE_CFG_PSS FALSE
- #define USER_PSTATE_CFG_XPSS FALSE
-#endif
-
-/* Declare the instance of the PSTATE option configuration structure */
-OPTION_PSTATE_POST_CONFIGURATION OptionPstatePostConfiguration = {
- PSTATE_STRUCT_VERSION,
- USER_PSTATE_OPTION_GATHER,
- USER_PSTATE_OPTION_LEVEL
-};
-
-OPTION_PSTATE_LATE_CONFIGURATION OptionPstateLateConfiguration = {
- PSTATE_STRUCT_VERSION,
- USER_SSDT_MAIN,
- USER_PSTATE_OPTION_MAIN,
- USER_CSTATE_OPTION_MAIN,
- USER_PSTATE_CFG_PPC,
- USER_PSTATE_CFG_PCT,
- USER_PSTATE_CFG_PSD,
- USER_PSTATE_CFG_PSS,
- USER_PSTATE_CFG_XPSS
-};
-
-CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PstateCpuFamilyServiceArray[] =
-{
- F10_PSTATE_SERVICE_SUPPORT
- F12_PSTATE_SERVICE_SUPPORT
- F14_PSTATE_SERVICE_SUPPORT
- F15_PSTATE_SERVICE_SUPPORT
- {0, NULL}
-};
-CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PstateFamilyServiceTable =
-{
- (sizeof (PstateCpuFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
- &PstateCpuFamilyServiceArray[0]
-};
-#endif // _OPTION_PSTATE_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionS3ScriptInstall.h b/src/vendorcode/amd/agesa/Include/OptionS3ScriptInstall.h
deleted file mode 100644
index 2804cae..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionS3ScriptInstall.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: S3SCRIPT
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Options
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_S3SCRIPT_INSTALL_H_
-#define _OPTION_S3SCRIPT_INSTALL_H_
-
-#include "S3SaveState.h"
-/* This option is designed to be included into the platform solution install
- * file. The platform solution install file will define the options status.
- * Check to validate the definition
- */
-#ifndef OPTION_S3SCRIPT
- #define OPTION_S3SCRIPT FALSE //if not define assume PI not use script
-#endif
-
-#if (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_ENV == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE)
- #if OPTION_S3SCRIPT == TRUE
- #define P_S3_SCRIPT_INIT S3ScriptInitState
- #endif
-#endif
-
-#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
- #if OPTION_S3SCRIPT == TRUE
- #define P_S3_SCRIPT_RESTORE S3ScriptRestoreState
- #endif
-#endif
-
-#ifndef P_S3_SCRIPT_INIT
- #define P_S3_SCRIPT_INIT S3ScriptInitStateStub
-#endif
-
-#ifndef P_S3_SCRIPT_RESTORE
- #define P_S3_SCRIPT_RESTORE S3ScriptInitStateStub
- #undef GNB_S3_DISPATCH_FUNCTION_TABLE
-#endif
-
-#ifndef GNB_S3_DISPATCH_FUNCTION_TABLE
- #define GNB_S3_DISPATCH_FUNCTION_TABLE
-#endif
-
-/* Declare the instance of the S3SCRIPT option configuration structure */
-S3_SCRIPT_CONFIGURATION OptionS3ScriptConfiguration = {
- P_S3_SCRIPT_INIT,
- P_S3_SCRIPT_RESTORE
-};
-
-S3_DISPATCH_FUNCTION_ENTRY S3DispatchFunctionTable [] = {
- GNB_S3_DISPATCH_FUNCTION_TABLE
- {0, NULL}
-};
-#endif // _OPTION_S3SCRIPT_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionSlit.h b/src/vendorcode/amd/agesa/Include/OptionSlit.h
deleted file mode 100644
index b6c2a5b..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionSlit.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD SLIT option API.
- *
- * Contains structures and values used to control the SLIT option code.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: OPTION
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_SLIT_H_
-#define _OPTION_SLIT_H_
-
-/*----------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *----------------------------------------------------------------------------------------
- */
-
-/**
- * Create the ACPI System Locality Distance Information Table.
- *
- */
-typedef AGESA_STATUS OPTION_SLIT_FEATURE (
- IN OUT AMD_CONFIG_PARAMS *StdHeader,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN OUT VOID **SlitPtr
- );
-
-/**
- * Clean up DRAM used during SLIT creation.
- *
- */
-typedef AGESA_STATUS OPTION_SLIT_RELEASE_BUFFER (
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-#define SLIT_STRUCT_VERSION 0x01
-
-/// The Option Configuration of SLIT
-typedef struct {
- UINT16 OptSlitVersion; ///< The version number of SLIT
- OPTION_SLIT_FEATURE *SlitFeature; ///< The Option Feature of SLIT
- OPTION_SLIT_RELEASE_BUFFER *SlitReleaseBuffer; ///< Release buffer
-} OPTION_SLIT_CONFIGURATION;
-
-/*----------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *----------------------------------------------------------------------------------------
- */
-
-
-#endif // _OPTION_SLIT_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionSlitInstall.h b/src/vendorcode/amd/agesa/Include/OptionSlitInstall.h
deleted file mode 100644
index c8d1c3d..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionSlitInstall.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: SLIT
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Options
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_SLIT_INSTALL_H_
-#define _OPTION_SLIT_INSTALL_H_
-
-/* This option is designed to be included into the platform solution install
- * file. The platform solution install file will define the options status.
- * Check to validate the definition
- */
-#if AGESA_ENTRY_INIT_LATE == TRUE
- #ifndef OPTION_SLIT
- #error BLDOPT: Option not defined: "OPTION_SLIT"
- #endif
- #if OPTION_SLIT == TRUE
- OPTION_SLIT_FEATURE GetAcpiSlitMain;
- OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBuffer;
- #define USER_SLIT_OPTION GetAcpiSlitMain
- #define USER_SLIT_RELEASE_BUFFER ReleaseSlitBuffer
- #else
- OPTION_SLIT_FEATURE GetAcpiSlitStub;
- OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub;
- #define USER_SLIT_OPTION GetAcpiSlitStub
- #define USER_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub
- #endif
-#else
- OPTION_SLIT_FEATURE GetAcpiSlitStub;
- OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub;
- #define USER_SLIT_OPTION GetAcpiSlitStub
- #define USER_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub
-#endif
-/* Declare the instance of the SLIT option configuration structure */
-OPTION_SLIT_CONFIGURATION OptionSlitConfiguration = {
- SLIT_STRUCT_VERSION,
- USER_SLIT_OPTION,
- USER_SLIT_RELEASE_BUFFER
-};
-
-#endif // _OPTION_SLIT_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionSrat.h b/src/vendorcode/amd/agesa/Include/OptionSrat.h
deleted file mode 100644
index 9d7c266..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionSrat.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD SRAT option API.
- *
- * Contains structures and values used to control the SRAT option code.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: OPTION
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_SRAT_H_
-#define _OPTION_SRAT_H_
-
-/*----------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *----------------------------------------------------------------------------------------
- */
-
-typedef AGESA_STATUS OPTION_SRAT_FEATURE (
- IN OUT AMD_CONFIG_PARAMS *StdHeader,
- IN OUT VOID **SratPtr
- );
-
-#define SRAT_STRUCT_VERSION 0x01
-
-/// The Option Configuration of SRAT
-typedef struct {
- UINT16 OptSratVersion; ///< The version number of SRAT
- OPTION_SRAT_FEATURE *SratFeature; ///< The Option Feature of SRAT
-} OPTION_SRAT_CONFIGURATION;
-
-/*----------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *----------------------------------------------------------------------------------------
- */
-
-
-#endif // _OPTION_SRAT_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionSratInstall.h b/src/vendorcode/amd/agesa/Include/OptionSratInstall.h
deleted file mode 100644
index adb8b3c..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionSratInstall.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: SRAT
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Options
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_SRAT_INSTALL_H_
-#define _OPTION_SRAT_INSTALL_H_
-
-/* This option is designed to be included into the platform solution install
- * file. The platform solution install file will define the options status.
- * Check to validate the definition
- */
-#if AGESA_ENTRY_INIT_LATE == TRUE
- #ifndef OPTION_SRAT
- #error BLDOPT: Option not defined: "OPTION_SRAT"
- #endif
- #if OPTION_SRAT == TRUE
- OPTION_SRAT_FEATURE GetAcpiSratMain;
- #define USER_SRAT_OPTION GetAcpiSratMain
- #else
- OPTION_SRAT_FEATURE GetAcpiSratStub;
- #define USER_SRAT_OPTION GetAcpiSratStub
- #endif
-#else
- OPTION_SRAT_FEATURE GetAcpiSratStub;
- #define USER_SRAT_OPTION GetAcpiSratStub
-#endif
-
-/* Declare the instance of the WHEA option configuration structure */
-OPTION_SRAT_CONFIGURATION OptionSratConfiguration = {
- SRAT_STRUCT_VERSION,
- USER_SRAT_OPTION
-};
-
-#endif // _OPTION_WHEA_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionSwC1eInstall.h b/src/vendorcode/amd/agesa/Include/OptionSwC1eInstall.h
deleted file mode 100644
index f8d8a06..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionSwC1eInstall.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: SW C1e
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Options
- * @e \$Revision: 37157 $ @e \$Date: 2010-09-01 03:24:07 +0800 (Wed, 01 Sep 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_SW_C1E_INSTALL_H_
-#define _OPTION_SW_C1E_INSTALL_H_
-
-#include "cpuSwC1e.h"
-
-/* This option is designed to be included into the platform solution install
- * file. The platform solution install file will define the options status.
- * Check to validate the definition
- */
-#define OPTION_SW_C1E_FEAT
-#define F10_SW_C1E_SUPPORT
-#if AGESA_ENTRY_INIT_EARLY == TRUE
- #ifdef OPTION_FAMILY10H
- #if OPTION_FAMILY10H == TRUE
- #if (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE) || (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_PH == TRUE)
- extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureSwC1e;
- #undef OPTION_SW_C1E_FEAT
- #define OPTION_SW_C1E_FEAT &CpuFeatureSwC1e,
- extern CONST SW_C1E_FAMILY_SERVICES ROMDATA F10SwC1e;
- #undef F10_SW_C1E_SUPPORT
- #define F10_SW_C1E_SUPPORT {(AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_RB | AMD_FAMILY_10_PH), &F10SwC1e},
- #endif
- #endif
- #endif
- CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA SwC1eFamilyServiceArray[] =
- {
- F10_SW_C1E_SUPPORT
- {0, NULL}
- };
- CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA SwC1eFamilyServiceTable =
- {
- (sizeof (SwC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
- &SwC1eFamilyServiceArray[0]
- };
-#endif
-
-#endif // _OPTION_SW_C1E_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionWhea.h b/src/vendorcode/amd/agesa/Include/OptionWhea.h
deleted file mode 100644
index 2451030..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionWhea.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD WHEA option API.
- *
- * Contains structures and values used to control the WHEA option code.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: OPTION
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_WHEA_H_
-#define _OPTION_WHEA_H_
-
-/*----------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *----------------------------------------------------------------------------------------
- */
-
-typedef AGESA_STATUS OPTION_WHEA_FEATURE (
- IN OUT AMD_CONFIG_PARAMS *StdHeader,
- IN OUT VOID **WheaMcePtr,
- IN OUT VOID **WheaCmcPtr
- );
-
-#define WHEA_STRUCT_VERSION 0x01
-
-/// The Option Configuration of WHEA
-typedef struct {
- UINT16 OptWheaVersion; ///< The version number of WHEA
- OPTION_WHEA_FEATURE *WheaFeature; ///< The Option Feature of WHEA
-} OPTION_WHEA_CONFIGURATION;
-
-/*----------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *----------------------------------------------------------------------------------------
- */
-
-
-#endif // _OPTION_WHEA_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionWheaInstall.h b/src/vendorcode/amd/agesa/Include/OptionWheaInstall.h
deleted file mode 100644
index 3ec55d2..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionWheaInstall.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build option: WHEA
- *
- * Contains AMD AGESA install macros and test conditions. Output is the
- * defaults tables reflecting the User's build options selection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Options
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_WHEA_INSTALL_H_
-#define _OPTION_WHEA_INSTALL_H_
-
-/* This option is designed to be included into the platform solution install
- * file. The platform solution install file will define the options status.
- * Check to validate the definition
- */
-#if AGESA_ENTRY_INIT_LATE == TRUE
- #ifndef OPTION_WHEA
- #error BLDOPT: Option not defined: "OPTION_WHEA"
- #endif
- #if OPTION_WHEA == TRUE
- OPTION_WHEA_FEATURE GetAcpiWheaMain;
- #define USER_WHEA_OPTION GetAcpiWheaMain
- #else
- OPTION_WHEA_FEATURE GetAcpiWheaStub;
- #define USER_WHEA_OPTION GetAcpiWheaStub
- #endif
-
-#else
- OPTION_WHEA_FEATURE GetAcpiWheaStub;
- #define USER_WHEA_OPTION GetAcpiWheaStub
-#endif
-
-/* Declare the instance of the WHEA option configuration structure */
-OPTION_WHEA_CONFIGURATION OptionWheaConfiguration = {
- WHEA_STRUCT_VERSION,
- USER_WHEA_OPTION
-};
-
-#endif // _OPTION_WHEA_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/Include/Options.h b/src/vendorcode/amd/agesa/Include/Options.h
deleted file mode 100644
index c2fddff..0000000
--- a/src/vendorcode/amd/agesa/Include/Options.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AGESA options structures
- *
- * Contains options control structures for the AGESA build options
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Core
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-#ifndef _OPTIONS_H_
-#define _OPTIONS_H_
-
-/**
- * Provide topology limits for loops and runtime, based on supported families.
- */
-typedef struct {
- UINT32 PlatformNumberOfSockets; ///< The limit to the number of processors based on
- ///< supported families and other build options.
- UINT32 PlatformNumberOfModules; ///< The limit to the number of modules in a processor, based
- ///< on supported families.
-} OPTIONS_CONFIG_TOPOLOGY;
-
-/**
- * Dispatch Table.
- *
- * The push high dispatcher uses this table to find what entries are currently in the build image.
- */
-typedef struct {
- UINT32 FunctionId; ///< The function id specified.
- IMAGE_ENTRY EntryPoint; ///< The corresponding entry point to call.
-} DISPATCH_TABLE;
-
-#ifdef BLDCFG_PLATFORM_POWER_POLICY_MODE
- #define CFG_PLATFORM_POWER_POLICY_MODE (BLDCFG_PLATFORM_POWER_POLICY_MODE)
-#else
- #define CFG_PLATFORM_POWER_POLICY_MODE (Performance)
-#endif
-
-#ifdef BLDCFG_PCI_MMIO_BASE
- #define CFG_PCI_MMIO_BASE (BLDCFG_PCI_MMIO_BASE)
-#else
- #define CFG_PCI_MMIO_BASE (0)
-#endif
-
-#ifdef BLDCFG_PCI_MMIO_SIZE
- #define CFG_PCI_MMIO_SIZE (BLDCFG_PCI_MMIO_SIZE)
-#else
- #define CFG_PCI_MMIO_SIZE (0)
-#endif
-
-#ifdef BLDCFG_AP_MTRR_SETTINGS_LIST
- #define CFG_AP_MTRR_SETTINGS_LIST (BLDCFG_AP_MTRR_SETTINGS_LIST)
-#else
- #define CFG_AP_MTRR_SETTINGS_LIST (NULL)
-#endif
-
-#endif // _OPTIONS_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionsHt.h b/src/vendorcode/amd/agesa/Include/OptionsHt.h
deleted file mode 100644
index 25b1684..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionsHt.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD HyperTransport option API.
- *
- * Contains option pre-compile logic. This file is used by the options
- * installer and internally by the HT code initializers.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: OPTION
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _OPTION_HT_H_
-#define _OPTION_HT_H_
-
-/*----------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *----------------------------------------------------------------------------------------
- */
-
-/**
- * Provide HT build option results
- */
-typedef struct {
- CONST BOOLEAN IsUsingRecoveryHt; ///< Manual BUID Swap List processing should assume that HT Recovery was used.
- CONST BOOLEAN IsSetHtCrcFlood; ///< Enable setting of HT CRC Flood.
- ///< Build-time only customizable - @BldCfgItem{BLDCFG_SET_HTCRC_SYNC_FLOOD}
- CONST BOOLEAN IsUsingUnitIdClumping; ///< Enable automatically HT Spec compliant Unit Id Clumping.
- ///< Build-time only customizable - @BldCfgItem{BLDCFG_USE_UNIT_ID_CLUMPING}
- CONST AMD_HT_INTERFACE *HtOptionPlatformDefaults; ///< A set of build time options for HT constructor.
- CONST VOID *HtOptionInternalInterface; ///< Use this internal interface initializer.
- CONST VOID *HtOptionInternalFeatures; ///< Use this internal feature set initializer.
- CONST VOID *HtOptionFamilyNorthbridgeList; ///< Use this list of northbridge initializers.
- CONST UINT8 *CONST *HtOptionBuiltinTopologies; ///< Use this list of built-in topologies.
-} OPTION_HT_CONFIGURATION;
-
-typedef AGESA_STATUS
-F_OPTION_HT_INIT_RESET (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface
- );
-
-typedef F_OPTION_HT_INIT_RESET *PF_OPTION_HT_INIT_RESET;
-
-/**
- * Provide HT reset initialization build option results
- */
-typedef struct {
- PF_OPTION_HT_INIT_RESET HtInitReset; ///< Method: HT reset initialization.
-} OPTION_HT_INIT_RESET;
-
-/*----------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *----------------------------------------------------------------------------------------
- */
-
-#endif // _OPTION_HT_H_
diff --git a/src/vendorcode/amd/agesa/Include/OptionsPage.h b/src/vendorcode/amd/agesa/Include/OptionsPage.h
deleted file mode 100644
index 1287e5b..0000000
--- a/src/vendorcode/amd/agesa/Include/OptionsPage.h
+++ /dev/null
@@ -1,375 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Create outline and references for Build Configuration and Options Component mainpage documentation.
- *
- * Design guides, maintenance guides, and general documentation, are
- * collected using this file onto the documentation mainpage.
- * This file contains doxygen comment blocks, only.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Documentation
- * @e \$Revision: 35380 $ @e \$Date: 2010-07-22 00:37:18 +0800 (Thu, 22 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/**
- * @page optionmain Build Configuration and Options Documentation
- *
- * Additional documentation for the Build Configuration and Options component consists of
- *
- * - Introduction and Overview to Build Options
- * - @subpage platforminstall "Platform Build Options"
- * - @subpage bldcfg "Build Configuration Item Cross Reference"
- * - @subpage examplecustomizations "Customization Examples"
- * - Maintenance Guides:
- * - For debug of the Options system, use compiler options
- * @n <tt> /P /EP /C /FAs </tt> @n
- * PreProcessor output is produced in an .i file in the directory where the project
- * file is located.
- * - Design Guides:
- * - add here >>>
- *
- */
-
-/**
- * @page platforminstall Platform Build Options.
- *
- * Build options are boolean constants. The purpose of build options is to remove code
- * from the build to reduce the overall code size present in the ROM image. Unless
- * otherwise specified, the default action is to include all options. If a build option is
- * not specifically listed as disabled, then it is included into the build.
- *
- * The documented build options are imported from a user controlled file for
- * processing. The build options for all platform solutions are listed below:
- *
- * @anchor BLDOPT_REMOVE_UDIMMS_SUPPORT
- * @li @e BLDOPT_REMOVE_UDIMMS_SUPPORT @n
- * If unbuffered DIMMs are NOT expected to be required in the system, the code that
- * handles unbuffered DIMMs can be removed from the build.
- *
- * @anchor BLDOPT_REMOVE_RDIMMS_SUPPORT
- * @li @e BLDOPT_REMOVE_RDIMMS_SUPPORT @n
- * If registered DIMMs are NOT expected to be required in the system, the code
- * that handles registered DIMMs can be removed from the build.
- *
- * @anchor BLDOPT_REMOVE_LRDIMMS_SUPPORT
- * @li @e BLDOPT_REMOVE_LRDIMMS_SUPPORT @n
- * If Load Reduced DIMMs are NOT expected to be required in the system, the code
- * that handles Load Reduced DIMMs can be removed from the build.
- *
- * @note The above three options operate independently from each other; however, at
- * least one of the unbuffered , registered or load reduced DIMM options must be present in the build.
- *
- * @anchor BLDOPT_REMOVE_ECC_SUPPORT
- * @li @e BLDOPT_REMOVE_ECC_SUPPORT @n
- * Use this option to remove the code for Error Checking & Correction.
- *
- * @anchor BLDOPT_REMOVE_BANK_INTERLEAVE
- * @li @e BLDOPT_REMOVE_BANK_INTERLEAVE @n
- * Interleaving is a mechanism to do performance fine tuning. This option
- * interleaves memory between banks on a DIMM.
- *
- * @anchor BLDOPT_REMOVE_DCT_INTERLEAVE
- * @li @e BLDOPT_REMOVE_DCT_INTERLEAVE @n
- * Interleaving is a mechanism to do performance fine tuning. This option
- * interleaves memory from two DRAM controllers.
- *
- * @anchor BLDOPT_REMOVE_NODE_INTERLEAVE
- * @li @e BLDOPT_REMOVE_NODE_INTERLEAVE @n
- * Interleaving is a mechanism to do performance fine tuning. This option
- * interleaves memory from two HyperTransport nodes.
- *
- * @anchor BLDOPT_REMOVE_PARALLEL_TRAINING
- * @li @e BLDOPT_REMOVE_PARALLEL_TRAINING @n
- * For multi-socket systems, training memory in parallel can reduce the time
- * needed to boot.
- *
- * @anchor BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT
- * @li @e BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT @n
- * Online Spare support is removed by this option.
- *
- * @anchor BLDOPT_REMOVE_MULTISOCKET_SUPPORT
- * @li @e BLDOPT_REMOVE_MULTISOCKET_SUPPORT @n
- * Many systems use only a single socket and may benefit in code space to remove
- * this code. However, certain processors have multiple HyperTransport nodes
- * within a single socket. For these processors, the multi-node support is
- * required and this option has no effect.
- *
- * @anchor BLDOPT_REMOVE_ACPI_PSTATES
- * @li @e BLDOPT_REMOVE_ACPI_PSTATES @n
- * This option removes the code that generates the ACPI tables used in power
- * management.
- *
- * @anchor BLDOPT_REMOVE_SRAT
- * @li @e BLDOPT_REMOVE_SRAT @n
- * This option removes the code that generates the SRAT tables used in performance
- * tuning.
- *
- * @anchor BLDOPT_REMOVE_SLIT
- * @li @e BLDOPT_REMOVE_SLIT @n
- * This option removes the code that generates the SLIT tables used in performance
- * tuning.
- *
- * @anchor BLDOPT_REMOVE_WHEA
- * @li @e BLDOPT_REMOVE_WHEA @n
- * This option removes the code that generates the WHEA tables used in error
- * handling and reporting.
- *
- * @anchor BLDOPT_REMOVE_DMI
- * @li @e BLDOPT_REMOVE_DMI @n
- * This option removes the code that generates the DMI tables used in system
- * management.
- *
- * @anchor BLDOPT_REMOVE_DQS_TRAINING
- * @li @e BLDOPT_REMOVE_DQS_TRAINING @n
- * This option removes the code used in memory performance tuning.
- *
- * @anchor BLDOPT_REMOVE_EARLY_SAMPLES
- * @li @e BLDOPT_REMOVE_EARLY_SAMPLES @n
- * Special support for Early Samples is included. Default setting is FALSE.
- *
- * @anchor BLDOPT_REMOVE_HT_ASSIST
- * @li @e BLDOPT_REMOVE_HT_ASSIST @n
- * This option removes the code which implements the HT Assist feature.
- *
- * @anchor BLDOPT_REMOVE_ATM_MODE
- * @li @e BLDOPT_REMOVE_ATM_MODE @n
- * This option removes the code which implements the ATM feature.
- *
- * @anchor BLDOPT_REMOVE_MSG_BASED_C1E
- * @li @e BLDOPT_REMOVE_MSG_BASED_C1E @n
- * This option removes the code which implements the Message Based C1e feature.
- *
- * @anchor BLDOPT_REMOVE_C6_STATE
- * @li @e BLDOPT_REMOVE_C6_STATE @n
- * This option removes the code which implements the C6 C-state feature.
- *
- * @anchor BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
- * @li @e BLDOPT_REMOVE_MEM_RESTORE_SUPPORT @n
- * This option removes the memory context restore feature.
- *
- * @anchor BLDOPT_REMOVE_FAMILY_10_SUPPORT
- * @li @e BLDOPT_REMOVE_FAMILY_10_SUPPORT @n
- * If the package contains support for family 10h processors, remove that support.
- *
- * @anchor BLDOPT_REMOVE_FAMILY_12_SUPPORT
- * @li @e BLDOPT_REMOVE_FAMILY_12_SUPPORT @n
- * If the package contains support for family 10h processors, remove that support.
- *
- * @anchor BLDOPT_REMOVE_FAMILY_14_SUPPORT
- * @li @e BLDOPT_REMOVE_FAMILY_14_SUPPORT @n
- * If the package contains support for family 14h processors, remove that support.
- *
- * @anchor BLDOPT_REMOVE_FAMILY_15_SUPPORT
- * @li @e BLDOPT_REMOVE_FAMILY_15_SUPPORT @n
- * If the package contains support for family 15h processors, remove that support.
- *
- * @anchor BLDOPT_REMOVE_AM3_SOCKET_SUPPORT
- * @li @e BLDOPT_REMOVE_AM3_SOCKET_SUPPORT @n
- * This option removes the code which implements support for processors packaged for AM3 sockets.
- *
- * @anchor BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT
- * @li @e BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT @n
- * This option removes the code which implements support for processors packaged for ASB2 sockets.
- *
- * @anchor BLDOPT_REMOVE_C32_SOCKET_SUPPORT
- * @li @e BLDOPT_REMOVE_C32_SOCKET_SUPPORT @n
- * This option removes the code which implements support for processors packaged for C32 sockets.
- *
- * @anchor BLDOPT_REMOVE_FM1_SOCKET_SUPPORT
- * @li @e BLDOPT_REMOVE_FM1_SOCKET_SUPPORT @n
- * This option removes the code which implements support for processors packaged for FM1 sockets.
- *
- * @anchor BLDOPT_REMOVE_FP1_SOCKET_SUPPORT
- * @li @e BLDOPT_REMOVE_FP1_SOCKET_SUPPORT @n
- * This option removes the code which implements support for processors packaged for FP1 sockets.
- *
- * @anchor BLDOPT_REMOVE_FS1_SOCKET_SUPPORT
- * @li @e BLDOPT_REMOVE_FS1_SOCKET_SUPPORT @n
- * This option removes the code which implements support for processors packaged for FS1 sockets.
- *
- * @anchor BLDOPT_REMOVE_FT1_SOCKET_SUPPORT
- * @li @e BLDOPT_REMOVE_FT1_SOCKET_SUPPORT @n
- * This option removes the code which implements support for processors packaged for FT1 sockets.
- *
- * @anchor BLDOPT_REMOVE_G34_SOCKET_SUPPORT
- * @li @e BLDOPT_REMOVE_G34_SOCKET_SUPPORT @n
- * This option removes the code which implements support for processors packaged for G34 sockets.
- *
- * @anchor BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT
- * @li @e BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT @n
- * This option removes the code which implements support for processors packaged for S1G3 sockets.
- *
- * @anchor BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT
- * @li @e BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT @n
- * This option removes the code which implements support for processors packaged for S1G4 sockets.
- */
-
-/**
- * @page examplecustomizations Customization Examples
- *
- * The Addendum \<plat\>Options.c file for each platform contains the minimum required
- * customizations for that platform. That is, it contains settings which would be needed
- * to boot a SimNow! bsd for that platform.
- * However, each individual product based on that platform will have customizations necessary for
- * that hardware. Since the actual customizations needed vary so much, they are not included in
- * the \<plat\>Options.c. This section provides examples of useful customizations that you can use or
- * modify to suit your needs.
- *
- * @par
- *
- * Source for the examples shown can be found at Addendum\\Examples. @n
- *
- * - @ref DeemphasisExamples "Deemphasis List Examples"
- * - @ref FrequencyLimitExamples "Frequency Limit Examples"
- * - @ref PerfPerWattHt "A performance-per-watt optimization Example"
- *
- * @anchor DeemphasisExamples
- * @par Deemphasis List Examples
- *
- * These examples customize PLATFORM_CONFIGURATION.PlatformDeemphasisList.
- * Source for the deemphasis list examples can be found in DeemphasisExamples.c. @n
- * @dontinclude DeemphasisExamples.c
- * <ul>
- * <li>
- * The following deemphasis list provides an example for a 2P MCM Max Performance configuration.
- * High Speed HT frequencies are supported. There is only one non-coherent chain. Note the technique of
- * putting specified link matches before all uses of match any. It often works well to specify the non-coherent links
- * and use match any for the coherent links.
- * @skip DinarDeemphasisList
- * @until {
- * The non-coherent chain can run up to 2600 MHz. The chain is located on Socket 0, package Link 2.
- * @until {
- * @line }
- * @line {
- * @line }
- * The coherent links can run up to 3200 MHz.
- * @until HT_FREQUENCY_MAX
- * @line }
- * end of list:
- * @until }
- * Make this list the build time customized deemphasis list.
- * @line define
- *
- * </li><li>
- *
- * The following deemphasis list provides an example for a 4P MCM Max Performance configuration.
- * This system has a backplane with connectors for CPU cards and an IO board. So trace lengths are long.
- * There can be one to four IO Chains, depending on the IO board.
- * @skipline DoubloonDeemphasisList
- * @until DoubloonDeemphasisList
- *
- * </li><li>
- *
- * The following deemphasis list further illustrates complex coherent system deemphasis. This is the same
- * Dinar system as in an earlier example, but this time all the coherent links are explicitly customized (as
- * might be needed if each link has unique characterization). For this example, we skip the non-coherent chains.
- * (A real system would have to include them, see example above.)
- * @skip DinarPerLinkDeemphasisList
- * @until {
- * Provide deemphasis settings for the 16 bit, ganged, links, Socket 0 links 0, 1 and Socket 1 links 1 and 2.
- * Provide entries to customize all HT3 frequencies at which the links may run. This example covers all HT3 speeds.
- * @until {
- * @until DcvLevelMinus6
- * @until DcvLevelMinus6
- * @until DcvLevelMinus6
- * @until DcvLevelMinus6
- * Link 3 on both sockets connects different internal die: sublink 0 connects the internal node zeroes, and
- * sublink 1 connects the internal node ones. So the link is unganged and both sublinks must be specifically
- * customized.
- * @until {
- * @until DcvLevelMinus6
- * @until DcvLevelMinus6
- * @until DcvLevelMinus6
- * @until DcvLevelMinus6
- * end of list:
- * @until define
- *
- * </ul>
- *
- * @anchor FrequencyLimitExamples
- * @par Frequency Limit Examples
- *
- * These examples customize AMD_HT_INTERFACE.CpuToCpuPcbLimitsList and AMD_HT_INTERFACE.IoPcbLimitsList.
- * Source for the frequency limit examples can be found in FrequencyLimitExamples.c. @n
- * @dontinclude FrequencyLimitExamples.c
- * <ul>
- * <li>
- * The following list provides an example for limiting all coherent links to non-extended frequencies,
- * that is, to 2600 MHz or less.
- * @skipline NonExtendedCpuToCpuLimitList
- * @until {
- * Provide the limit customization. Match links from any socket, any package link, to any socket, any package link. Width is not limited.
- * @until HT_FREQUENCY_LIMIT_2600M
- * End of list:
- * @until ;
- * Customize the build to use this cpu to cpu frequency limit.
- * @until NonExtendedCpuToCpuLimitList
- * @n </li>
- * <li>
- * The following list provides an example for limiting all coherent links to HT 1 frequencies,
- * that is, to 1000 MHz or less. This is sometimes useful for test and debug.
- * @skipline Ht1CpuToCpuLimitList
- * @until Ht1CpuToCpuLimitList
- * @n </li>
- * <li>
- * The following list provides an example for limiting all non-coherent links to 2400 MHz or less.
- * The chain is matched by host processor Socket and package Link. The depth can be used to select a particular device
- * to device link on the chain. In this example, the chain consists of a single cave device and depth can be set to match any.
- * @skipline No2600MhzIoLimitList
- * @until No2600MhzIoLimitList
- * @n </li>
- * <li>
- * The following list provides an example for limiting all non-coherent links to the minimum HT 3 frequency,
- * that is, to 1200 MHz or less. This can be useful for test and debug.
- * @skipline MinHt3IoLimitList
- * @until MinHt3IoLimitList
- * @n </li>
- *
- * </ul>
- *
- * @anchor PerfPerWattHt
- * @par Performance-per-Watt Optimization Example
- *
- * This example customizes AMD_HT_INTERFACE.SkipRegangList.
- * Source for the Performance-per-watt Optimization example can be found in PerfPerWatt.c. @n
- * @dontinclude PerfPerWatt.c
- * To implement a performance-per-watt optimization for MCM processors, use the skip regang structure shown. @n
- * @skipline PerfPerWatt
- * @until PerfPerWatt
- *
- */
diff --git a/src/vendorcode/amd/agesa/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/Include/PlatformInstall.h
deleted file mode 100644
index 31a311b..0000000
--- a/src/vendorcode/amd/agesa/Include/PlatformInstall.h
+++ /dev/null
@@ -1,2599 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build options for a combination of package type, processor, and features.
- *
- * This file generates the defaults tables for the all platform solution
- * combinations. The documented build options are imported from a user
- * controlled file for processing.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Core
- * @e \$Revision: 41504 $ @e \$Date: 2010-11-05 21:59:13 +0800 (Fri, 05 Nov 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*****************************************************************************
- *
- * Start processing the user options: First, set default settings
- *
- ****************************************************************************/
-
-/* Available options for image builds.
- *
- * As part of the image build for each image, define the options below to select the
- * AGESA entry points included in that image. Turn these on in your option c file, not
- * here.
- */
-// #define AGESA_ENTRY_INIT_RESET TRUE
-// #define AGESA_ENTRY_INIT_RECOVERY TRUE
-// #define AGESA_ENTRY_INIT_EARLY TRUE
-// #define AGESA_ENTRY_INIT_POST TRUE
-// #define AGESA_ENTRY_INIT_ENV TRUE
-// #define AGESA_ENTRY_INIT_MID TRUE
-// #define AGESA_ENTRY_INIT_LATE TRUE
-// #define AGESA_ENTRY_INIT_S3SAVE TRUE
-// #define AGESA_ENTRY_INIT_RESUME TRUE
-// #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
-// #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
-
-/* Defaults for private/internal build control settings */
-/* Available options for image builds.
- *
- * As part of the image build for each image, define the options below to select the
- * AGESA entry points included in that image.
- */
-
-VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
- //ModuleHeaderSignature
- // Remove 'DOM$' as temp solution before update BinUtil.exe ,
- '0000',
- //ModuleIdentifier[8]
- AGESA_ID,
- //ModuleVersion[12]
- AGESA_VERSION_STRING,
- //ModuleDispatcher
- NULL,//(VOID *)(UINT64)((MODULE_ENTRY)AmdAgesaDispatcher),
- //NextBlock
- NULL
-};
-
-/* Process user desired AGESA entry points */
-#ifndef AGESA_ENTRY_INIT_RESET
- #define AGESA_ENTRY_INIT_RESET FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_RECOVERY
- #define AGESA_ENTRY_INIT_RECOVERY FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_EARLY
- #define AGESA_ENTRY_INIT_EARLY FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_POST
- #define AGESA_ENTRY_INIT_POST FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_ENV
- #define AGESA_ENTRY_INIT_ENV FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_MID
- #define AGESA_ENTRY_INIT_MID FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_LATE
- #define AGESA_ENTRY_INIT_LATE FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_S3SAVE
- #define AGESA_ENTRY_INIT_S3SAVE FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_RESUME
- #define AGESA_ENTRY_INIT_RESUME FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_LATE_RESTORE
- #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE
-#endif
-
-#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES
- #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE
-#endif
-
-/* Default the late AP entry point to off. It can be enabled
- by any family that may need the late AP functionality, or
- by any feature code that may need it. The IBVs no longer
- have control over this entry point. */
-#ifdef AGESA_ENTRY_LATE_RUN_AP_TASK
- #undef AGESA_ENTRY_LATE_RUN_AP_TASK
-#endif
-#define AGESA_ENTRY_LATE_RUN_AP_TASK FALSE
-
-
-
-/* Process solution defined socket / family installations
- *
- * As part of the release package for each image, define the options below to select the
- * AGESA processor support included in that image.
- */
-
-/* Default sockets to off */
-#define OPTION_G34_SOCKET_SUPPORT FALSE
-#define OPTION_C32_SOCKET_SUPPORT FALSE
-#define OPTION_S1G3_SOCKET_SUPPORT FALSE
-#define OPTION_S1G4_SOCKET_SUPPORT FALSE
-#define OPTION_ASB2_SOCKET_SUPPORT FALSE
-#define OPTION_FS1_SOCKET_SUPPORT FALSE
-#define OPTION_FM1_SOCKET_SUPPORT FALSE
-#define OPTION_FP1_SOCKET_SUPPORT FALSE
-#define OPTION_FT1_SOCKET_SUPPORT FALSE
-#define OPTION_AM3_SOCKET_SUPPORT FALSE
-
-/* Default families to off */
-#define OPTION_FAMILY10H FALSE
-#define OPTION_FAMILY12H FALSE
-#define OPTION_FAMILY14H FALSE
-#define OPTION_FAMILY15H FALSE
-
-
-/* Enable the appropriate socket support */
-#ifdef INSTALL_G34_SOCKET_SUPPORT
- #if INSTALL_G34_SOCKET_SUPPORT == TRUE
- #undef OPTION_G34_SOCKET_SUPPORT
- #define OPTION_G34_SOCKET_SUPPORT TRUE
- #endif
-#endif
-
-#ifdef INSTALL_C32_SOCKET_SUPPORT
- #if INSTALL_C32_SOCKET_SUPPORT == TRUE
- #undef OPTION_C32_SOCKET_SUPPORT
- #define OPTION_C32_SOCKET_SUPPORT TRUE
- #endif
-#endif
-
-#ifdef INSTALL_S1G3_SOCKET_SUPPORT
- #if INSTALL_S1G3_SOCKET_SUPPORT == TRUE
- #undef OPTION_S1G3_SOCKET_SUPPORT
- #define OPTION_S1G3_SOCKET_SUPPORT TRUE
- #endif
-#endif
-
-#ifdef INSTALL_S1G4_SOCKET_SUPPORT
- #if INSTALL_S1G4_SOCKET_SUPPORT == TRUE
- #undef OPTION_S1G4_SOCKET_SUPPORT
- #define OPTION_S1G4_SOCKET_SUPPORT TRUE
- #endif
-#endif
-
-#ifdef INSTALL_ASB2_SOCKET_SUPPORT
- #if INSTALL_ASB2_SOCKET_SUPPORT == TRUE
- #undef OPTION_ASB2_SOCKET_SUPPORT
- #define OPTION_ASB2_SOCKET_SUPPORT TRUE
- #endif
-#endif
-
-#ifdef INSTALL_FS1_SOCKET_SUPPORT
- #if INSTALL_FS1_SOCKET_SUPPORT == TRUE
- #undef OPTION_FS1_SOCKET_SUPPORT
- #define OPTION_FS1_SOCKET_SUPPORT TRUE
- #endif
-#endif
-
-#ifdef INSTALL_FM1_SOCKET_SUPPORT
- #if INSTALL_FM1_SOCKET_SUPPORT == TRUE
- #undef OPTION_FM1_SOCKET_SUPPORT
- #define OPTION_FM1_SOCKET_SUPPORT TRUE
- #endif
-#endif
-
-#ifdef INSTALL_FP1_SOCKET_SUPPORT
- #if INSTALL_FP1_SOCKET_SUPPORT == TRUE
- #undef OPTION_FP1_SOCKET_SUPPORT
- #define OPTION_FP1_SOCKET_SUPPORT TRUE
- #endif
-#endif
-
-#ifdef INSTALL_FT1_SOCKET_SUPPORT
- #if INSTALL_FT1_SOCKET_SUPPORT == TRUE
- #undef OPTION_FT1_SOCKET_SUPPORT
- #define OPTION_FT1_SOCKET_SUPPORT TRUE
- #endif
-#endif
-
-#ifdef INSTALL_AM3_SOCKET_SUPPORT
- #if INSTALL_AM3_SOCKET_SUPPORT == TRUE
- #undef OPTION_AM3_SOCKET_SUPPORT
- #define OPTION_AM3_SOCKET_SUPPORT TRUE
- #endif
-#endif
-
-
-/* Enable the appropriate family support */
-// F10 is supported in G34, C32, S1g4, ASB2, S1g3, & AM3
-#ifdef INSTALL_FAMILY_10_SUPPORT
- #if INSTALL_FAMILY_10_SUPPORT == TRUE
- #undef OPTION_FAMILY10H
- #define OPTION_FAMILY10H TRUE
- #endif
-#endif
-
-// F12 is supported in FP1, FS1, & FM1
-#ifdef INSTALL_FAMILY_12_SUPPORT
- #if INSTALL_FAMILY_12_SUPPORT == TRUE
- #undef OPTION_FAMILY12H
- #define OPTION_FAMILY12H TRUE
- #endif
-#endif
-
-// F14 is supported in FT1
-#ifdef INSTALL_FAMILY_14_SUPPORT
- #if INSTALL_FAMILY_14_SUPPORT == TRUE
- #undef OPTION_FAMILY14H
- #define OPTION_FAMILY14H TRUE
- #endif
-#endif
-
-// F15 is supported in G34, C32, & AM3
-#ifdef INSTALL_FAMILY_15_SUPPORT
- #if INSTALL_FAMILY_15_SUPPORT == TRUE
- #undef OPTION_FAMILY15H
- #define OPTION_FAMILY15H TRUE
- #endif
-#endif
-
-
-/* Turn off families not required by socket designations */
-#if (OPTION_FAMILY10H == TRUE)
- #if (OPTION_G34_SOCKET_SUPPORT == FALSE) && (OPTION_C32_SOCKET_SUPPORT == FALSE) && (OPTION_S1G3_SOCKET_SUPPORT == FALSE) && (OPTION_S1G4_SOCKET_SUPPORT == FALSE) && (OPTION_ASB2_SOCKET_SUPPORT == FALSE) && (OPTION_AM3_SOCKET_SUPPORT == FALSE)
- #undef OPTION_FAMILY10H
- #define OPTION_FAMILY10H FALSE
- #endif
-#endif
-
-#if (OPTION_FAMILY12H == TRUE)
- #if (OPTION_FS1_SOCKET_SUPPORT == FALSE) && (OPTION_FM1_SOCKET_SUPPORT == FALSE) && (OPTION_FP1_SOCKET_SUPPORT == FALSE)
- #undef OPTION_FAMILY12H
- #define OPTION_FAMILY12H FALSE
- #endif
-#endif
-
-#if (OPTION_FAMILY14H == TRUE)
- #if (OPTION_FT1_SOCKET_SUPPORT == FALSE)
- #undef OPTION_FAMILY14H
- #define OPTION_FAMILY14H FALSE
- #endif
-#endif
-
-#if (OPTION_FAMILY15H == TRUE)
- #if (OPTION_G34_SOCKET_SUPPORT == FALSE) && (OPTION_C32_SOCKET_SUPPORT == FALSE) && (OPTION_AM3_SOCKET_SUPPORT == FALSE)
- #undef OPTION_FAMILY15H
- #define OPTION_FAMILY15H FALSE
- #endif
-#endif
-
-
-/* Check for invalid combinations of socket/family */
-#if (OPTION_G34_SOCKET_SUPPORT == TRUE)
- #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H == FALSE)
- #error No G34 supported families included in the build
- #endif
-#endif
-
-#if (OPTION_C32_SOCKET_SUPPORT == TRUE)
- #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H == FALSE)
- #error No C32 supported families included in the build
- #endif
-#endif
-
-#if (OPTION_S1G3_SOCKET_SUPPORT == TRUE)
- #if (OPTION_FAMILY10H == FALSE)
- #error No S1G3 supported families included in the build
- #endif
-#endif
-
-#if (OPTION_S1G4_SOCKET_SUPPORT == TRUE)
- #if (OPTION_FAMILY10H == FALSE)
- #error No S1G4 supported families included in the build
- #endif
-#endif
-
-#if (OPTION_ASB2_SOCKET_SUPPORT == TRUE)
- #if (OPTION_FAMILY10H == FALSE)
- #error No ASB2 supported families included in the build
- #endif
-#endif
-
-#if (OPTION_FS1_SOCKET_SUPPORT == TRUE)
- #if (OPTION_FAMILY12H == FALSE)
- #error No FS1 supported families included in the build
- #endif
-#endif
-
-#if (OPTION_FM1_SOCKET_SUPPORT == TRUE)
- #if (OPTION_FAMILY12H == FALSE)
- #error No FM1 supported families included in the build
- #endif
-#endif
-
-#if (OPTION_FP1_SOCKET_SUPPORT == TRUE)
- #if (OPTION_FAMILY12H == FALSE)
- #error No FP1 supported families included in the build
- #endif
-#endif
-
-#if (OPTION_FT1_SOCKET_SUPPORT == TRUE)
- #if (OPTION_FAMILY14H == FALSE)
- #error No FT1 supported families included in the build
- #endif
-#endif
-
-#if (OPTION_AM3_SOCKET_SUPPORT == TRUE)
- #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H == FALSE)
- #error No AM3 supported families included in the build
- #endif
-#endif
-
-
-/* Process AGESA private data
- *
- * Turn on appropriate CPU models and memory controllers,
- * as well as some other memory controls.
- */
-
-/* Default all models to off */
-#define OPTION_FAMILY10H_BL FALSE
-#define OPTION_FAMILY10H_DA FALSE
-#define OPTION_FAMILY10H_HY FALSE
-#define OPTION_FAMILY10H_PH FALSE
-#define OPTION_FAMILY10H_RB FALSE
-#define OPTION_FAMILY12H_LN FALSE
-#define OPTION_FAMILY14H_ON FALSE
-#define OPTION_FAMILY15H_OR FALSE
-
-/* Default all memory controllers to off */
-#define OPTION_MEMCTLR_DR FALSE
-#define OPTION_MEMCTLR_HY FALSE
-#define OPTION_MEMCTLR_OR FALSE
-#define OPTION_MEMCTLR_C32 FALSE
-#define OPTION_MEMCTLR_DA FALSE
-#define OPTION_MEMCTLR_LN FALSE
-#define OPTION_MEMCTLR_ON FALSE
-#define OPTION_MEMCTLR_Ni FALSE
-#define OPTION_MEMCTLR_PH FALSE
-#define OPTION_MEMCTLR_RB FALSE
-
-/* Default all memory controls to off */
-#define OPTION_HW_WRITE_LEV_TRAINING FALSE
-#define OPTION_SW_WRITE_LEV_TRAINING FALSE
-#define OPTION_CONTINOUS_PATTERN_GENERATION FALSE
-#define OPTION_HW_DQS_REC_EN_TRAINING FALSE
-#define OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING FALSE
-#define OPTION_OPT_SW_DQS_REC_EN_TRAINING FALSE
-#define OPTION_NON_OPT_SW_RD_WR_POS_TRAINING FALSE
-#define OPTION_OPT_SW_RD_WR_POS_TRAINING FALSE
-#define OPTION_MAX_RD_LAT_TRAINING FALSE
-#define OPTION_HW_DRAM_INIT FALSE
-#define OPTION_SW_DRAM_INIT FALSE
-#define OPTION_S3_MEM_SUPPORT FALSE
-#define OPTION_ADDR_TO_CS_TRANSLATOR FALSE
-
-/* Defaults for public user options */
-#define OPTION_UDIMMS FALSE
-#define OPTION_RDIMMS FALSE
-#define OPTION_SODIMMS FALSE
-#define OPTION_LRDIMMS FALSE
-#define OPTION_DDR2 FALSE
-#define OPTION_DDR3 FALSE
-#define OPTION_ECC FALSE
-#define OPTION_BANK_INTERLEAVE FALSE
-#define OPTION_DCT_INTERLEAVE FALSE
-#define OPTION_NODE_INTERLEAVE FALSE
-#define OPTION_PARALLEL_TRAINING FALSE
-#define OPTION_ONLINE_SPARE FALSE
-#define OPTION_MEM_RESTORE FALSE
-#define OPTION_DIMM_EXCLUDE FALSE
-
-/* Default all CPU controls to off */
-#define OPTION_MULTISOCKET FALSE
-#define OPTION_SRAT FALSE
-#define OPTION_SLIT FALSE
-#define OPTION_HT_ASSIST FALSE
-#define OPTION_ATM_MODE FALSE
-#define OPTION_CPU_CORELEVLING FALSE
-#define OPTION_MSG_BASED_C1E FALSE
-#define OPTION_CPU_CFOH FALSE
-#define OPTION_C6_STATE FALSE
-#define OPTION_IO_CSTATE FALSE
-#define OPTION_CPB FALSE
-#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT FALSE
-#define OPTION_S3SCRIPT FALSE
-#define OPTION_GFX_RECOVERY FALSE
-
-/* Enable all private controls based on socket/family enables */
-#if (OPTION_G34_SOCKET_SUPPORT == TRUE)
- #if (OPTION_FAMILY10H == TRUE)
- #undef OPTION_FAMILY10H_HY
- #define OPTION_FAMILY10H_HY TRUE
- #undef OPTION_MEMCTLR_HY
- #define OPTION_MEMCTLR_HY TRUE
- #undef OPTION_HW_WRITE_LEV_TRAINING
- #define OPTION_HW_WRITE_LEV_TRAINING TRUE
- #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
- #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
- #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
- #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
- #undef OPTION_MAX_RD_LAT_TRAINING
- #define OPTION_MAX_RD_LAT_TRAINING TRUE
- #undef OPTION_SW_DRAM_INIT
- #define OPTION_SW_DRAM_INIT TRUE
- #undef OPTION_S3_MEM_SUPPORT
- #define OPTION_S3_MEM_SUPPORT TRUE
- #undef OPTION_MULTISOCKET
- #define OPTION_MULTISOCKET TRUE
- #undef OPTION_SRAT
- #define OPTION_SRAT TRUE
- #undef OPTION_SLIT
- #define OPTION_SLIT TRUE
- #undef OPTION_HT_ASSIST
- #define OPTION_HT_ASSIST TRUE
- #undef OPTION_CPU_CORELEVLING
- #define OPTION_CPU_CORELEVLING TRUE
- #undef OPTION_MSG_BASED_C1E
- #define OPTION_MSG_BASED_C1E TRUE
- #undef OPTION_CPU_CFOH
- #define OPTION_CPU_CFOH TRUE
- #undef OPTION_UDIMMS
- #define OPTION_UDIMMS TRUE
- #undef OPTION_RDIMMS
- #define OPTION_RDIMMS TRUE
- #undef OPTION_SODIMMS
- #define OPTION_SODIMMS TRUE
- #undef OPTION_DDR3
- #define OPTION_DDR3 TRUE
- #undef OPTION_ECC
- #define OPTION_ECC TRUE
- #undef OPTION_BANK_INTERLEAVE
- #define OPTION_BANK_INTERLEAVE TRUE
- #undef OPTION_DCT_INTERLEAVE
- #define OPTION_DCT_INTERLEAVE TRUE
- #undef OPTION_NODE_INTERLEAVE
- #define OPTION_NODE_INTERLEAVE TRUE
- #undef OPTION_PARALLEL_TRAINING
- #define OPTION_PARALLEL_TRAINING TRUE
- #undef OPTION_MEM_RESTORE
- #define OPTION_MEM_RESTORE TRUE
- #undef OPTION_ONLINE_SPARE
- #define OPTION_ONLINE_SPARE TRUE
- #undef OPTION_DIMM_EXCLUDE
- #define OPTION_DIMM_EXCLUDE TRUE
- #endif
- #if (OPTION_FAMILY15H == TRUE)
- #undef OPTION_FAMILY15H_OR
- #define OPTION_FAMILY15H_OR TRUE
- #undef OPTION_MEMCTLR_OR
- #define OPTION_MEMCTLR_OR TRUE
- #undef OPTION_HW_WRITE_LEV_TRAINING
- #define OPTION_HW_WRITE_LEV_TRAINING TRUE
- #undef OPTION_CONTINOUS_PATTERN_GENERATION
- #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
- #undef OPTION_HW_DQS_REC_EN_TRAINING
- #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
- #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
- #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
- #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
- #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
- #undef OPTION_MAX_RD_LAT_TRAINING
- #define OPTION_MAX_RD_LAT_TRAINING TRUE
- #undef OPTION_SW_DRAM_INIT
- #define OPTION_SW_DRAM_INIT TRUE
- #undef OPTION_S3_MEM_SUPPORT
- #define OPTION_S3_MEM_SUPPORT TRUE
- #undef OPTION_MULTISOCKET
- #define OPTION_MULTISOCKET TRUE
- #undef OPTION_C6_STATE
- #define OPTION_C6_STATE TRUE
- #undef OPTION_IO_CSTATE
- #define OPTION_IO_CSTATE TRUE
- #undef OPTION_CPB
- #define OPTION_CPB TRUE
- #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
- #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE
- #undef OPTION_SRAT
- #define OPTION_SRAT TRUE
- #undef OPTION_SLIT
- #define OPTION_SLIT TRUE
- #undef OPTION_HT_ASSIST
- #define OPTION_HT_ASSIST TRUE
- #undef OPTION_ATM_MODE
- #define OPTION_ATM_MODE TRUE
- #undef OPTION_CPU_CORELEVLING
- #define OPTION_CPU_CORELEVLING TRUE
- #undef OPTION_MSG_BASED_C1E
- #define OPTION_MSG_BASED_C1E TRUE
- #undef OPTION_CPU_CFOH
- #define OPTION_CPU_CFOH TRUE
- #undef OPTION_UDIMMS
- #define OPTION_UDIMMS TRUE
- #undef OPTION_RDIMMS
- #define OPTION_RDIMMS TRUE
- #undef OPTION_SODIMMS
- #define OPTION_SODIMMS TRUE
- #undef OPTION_LRDIMMS
- #define OPTION_LRDIMMS TRUE
- #undef OPTION_DDR3
- #define OPTION_DDR3 TRUE
- #undef OPTION_ECC
- #define OPTION_ECC TRUE
- #undef OPTION_BANK_INTERLEAVE
- #define OPTION_BANK_INTERLEAVE TRUE
- #undef OPTION_DCT_INTERLEAVE
- #define OPTION_DCT_INTERLEAVE TRUE
- #undef OPTION_NODE_INTERLEAVE
- #define OPTION_NODE_INTERLEAVE TRUE
- #undef OPTION_MEM_RESTORE
- #define OPTION_MEM_RESTORE TRUE
- #undef OPTION_ONLINE_SPARE
- #define OPTION_ONLINE_SPARE TRUE
- #undef OPTION_DIMM_EXCLUDE
- #define OPTION_DIMM_EXCLUDE TRUE
- #endif
-#endif
-
-#if (OPTION_C32_SOCKET_SUPPORT == TRUE)
- #if (OPTION_FAMILY10H == TRUE)
- #undef OPTION_FAMILY10H_HY
- #define OPTION_FAMILY10H_HY TRUE
- #undef OPTION_MEMCTLR_C32
- #define OPTION_MEMCTLR_C32 TRUE
- #undef OPTION_HW_WRITE_LEV_TRAINING
- #define OPTION_HW_WRITE_LEV_TRAINING TRUE
- #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
- #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
- #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
- #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
- #undef OPTION_MAX_RD_LAT_TRAINING
- #define OPTION_MAX_RD_LAT_TRAINING TRUE
- #undef OPTION_SW_DRAM_INIT
- #define OPTION_SW_DRAM_INIT TRUE
- #undef OPTION_S3_MEM_SUPPORT
- #define OPTION_S3_MEM_SUPPORT TRUE
- #undef OPTION_ADDR_TO_CS_TRANSLATOR
- #define OPTION_ADDR_TO_CS_TRANSLATOR FALSE
- #undef OPTION_MULTISOCKET
- #define OPTION_MULTISOCKET TRUE
- #undef OPTION_SRAT
- #define OPTION_SRAT TRUE
- #undef OPTION_SLIT
- #define OPTION_SLIT TRUE
- #undef OPTION_HT_ASSIST
- #define OPTION_HT_ASSIST TRUE
- #undef OPTION_CPU_CORELEVLING
- #define OPTION_CPU_CORELEVLING TRUE
- #undef OPTION_MSG_BASED_C1E
- #define OPTION_MSG_BASED_C1E TRUE
- #undef OPTION_CPU_CFOH
- #define OPTION_CPU_CFOH TRUE
- #undef OPTION_UDIMMS
- #define OPTION_UDIMMS TRUE
- #undef OPTION_RDIMMS
- #define OPTION_RDIMMS TRUE
- #undef OPTION_SODIMMS
- #define OPTION_SODIMMS TRUE
- #undef OPTION_DDR3
- #define OPTION_DDR3 TRUE
- #undef OPTION_ECC
- #define OPTION_ECC TRUE
- #undef OPTION_BANK_INTERLEAVE
- #define OPTION_BANK_INTERLEAVE TRUE
- #undef OPTION_DCT_INTERLEAVE
- #define OPTION_DCT_INTERLEAVE TRUE
- #undef OPTION_NODE_INTERLEAVE
- #define OPTION_NODE_INTERLEAVE TRUE
- #undef OPTION_PARALLEL_TRAINING
- #define OPTION_PARALLEL_TRAINING TRUE
- #undef OPTION_MEM_RESTORE
- #define OPTION_MEM_RESTORE TRUE
- #undef OPTION_ONLINE_SPARE
- #define OPTION_ONLINE_SPARE TRUE
- #undef OPTION_DIMM_EXCLUDE
- #define OPTION_DIMM_EXCLUDE TRUE
- #endif
- #if (OPTION_FAMILY15H == TRUE)
- #undef OPTION_FAMILY15H_OR
- #define OPTION_FAMILY15H_OR TRUE
- #undef OPTION_MEMCTLR_OR
- #define OPTION_MEMCTLR_OR TRUE
- #undef OPTION_HW_WRITE_LEV_TRAINING
- #define OPTION_HW_WRITE_LEV_TRAINING TRUE
- #undef OPTION_CONTINOUS_PATTERN_GENERATION
- #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
- #undef OPTION_HW_DQS_REC_EN_TRAINING
- #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
- #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
- #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
- #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
- #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
- #undef OPTION_MAX_RD_LAT_TRAINING
- #define OPTION_MAX_RD_LAT_TRAINING TRUE
- #undef OPTION_SW_DRAM_INIT
- #define OPTION_SW_DRAM_INIT TRUE
- #undef OPTION_S3_MEM_SUPPORT
- #define OPTION_S3_MEM_SUPPORT TRUE
- #undef OPTION_ADDR_TO_CS_TRANSLATOR
- #define OPTION_ADDR_TO_CS_TRANSLATOR TRUE
- #undef OPTION_MULTISOCKET
- #define OPTION_MULTISOCKET TRUE
- #undef OPTION_C6_STATE
- #define OPTION_C6_STATE TRUE
- #undef OPTION_IO_CSTATE
- #define OPTION_IO_CSTATE TRUE
- #undef OPTION_CPB
- #define OPTION_CPB TRUE
- #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
- #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE
- #undef OPTION_SRAT
- #define OPTION_SRAT TRUE
- #undef OPTION_SLIT
- #define OPTION_SLIT TRUE
- #undef OPTION_HT_ASSIST
- #define OPTION_HT_ASSIST TRUE
- #undef OPTION_ATM_MODE
- #define OPTION_ATM_MODE TRUE
- #undef OPTION_CPU_CORELEVLING
- #define OPTION_CPU_CORELEVLING TRUE
- #undef OPTION_MSG_BASED_C1E
- #define OPTION_MSG_BASED_C1E TRUE
- #undef OPTION_CPU_CFOH
- #define OPTION_CPU_CFOH TRUE
- #undef OPTION_UDIMMS
- #define OPTION_UDIMMS TRUE
- #undef OPTION_RDIMMS
- #define OPTION_RDIMMS TRUE
- #undef OPTION_SODIMMS
- #define OPTION_SODIMMS TRUE
- #undef OPTION_LRDIMMS
- #define OPTION_LRDIMMS TRUE
- #undef OPTION_DDR3
- #define OPTION_DDR3 TRUE
- #undef OPTION_ECC
- #define OPTION_ECC TRUE
- #undef OPTION_BANK_INTERLEAVE
- #define OPTION_BANK_INTERLEAVE TRUE
- #undef OPTION_DCT_INTERLEAVE
- #define OPTION_DCT_INTERLEAVE TRUE
- #undef OPTION_NODE_INTERLEAVE
- #define OPTION_NODE_INTERLEAVE TRUE
- #undef OPTION_MEM_RESTORE
- #define OPTION_MEM_RESTORE TRUE
- #undef OPTION_ONLINE_SPARE
- #define OPTION_ONLINE_SPARE TRUE
- #undef OPTION_DIMM_EXCLUDE
- #define OPTION_DIMM_EXCLUDE TRUE
- #endif
-#endif
-
-#if (OPTION_S1G3_SOCKET_SUPPORT == TRUE)
- #if (OPTION_FAMILY10H == TRUE)
- #undef OPTION_FAMILY10H_BL
- #define OPTION_FAMILY10H_BL TRUE
- #undef OPTION_FAMILY10H_DA
- #define OPTION_FAMILY10H_DA TRUE
- #undef OPTION_MEMCTLR_DA
- #define OPTION_MEMCTLR_DA TRUE
- #undef OPTION_HW_WRITE_LEV_TRAINING
- #define OPTION_HW_WRITE_LEV_TRAINING TRUE
- #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
- #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
- #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
- #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
- #undef OPTION_MAX_RD_LAT_TRAINING
- #define OPTION_MAX_RD_LAT_TRAINING TRUE
- #undef OPTION_SW_DRAM_INIT
- #define OPTION_SW_DRAM_INIT TRUE
- #undef OPTION_S3_MEM_SUPPORT
- #define OPTION_S3_MEM_SUPPORT TRUE
- #undef OPTION_CPU_CORELEVLING
- #define OPTION_CPU_CORELEVLING TRUE
- #undef OPTION_CPU_CFOH
- #define OPTION_CPU_CFOH TRUE
- #undef OPTION_UDIMMS
- #define OPTION_UDIMMS TRUE
- #undef OPTION_SODIMMS
- #define OPTION_SODIMMS TRUE
- #undef OPTION_DDR3
- #define OPTION_DDR3 TRUE
- #undef OPTION_ECC
- #define OPTION_ECC TRUE
- #undef OPTION_BANK_INTERLEAVE
- #define OPTION_BANK_INTERLEAVE TRUE
- #undef OPTION_DCT_INTERLEAVE
- #define OPTION_DCT_INTERLEAVE TRUE
- #undef OPTION_NODE_INTERLEAVE
- #define OPTION_NODE_INTERLEAVE TRUE
- #undef OPTION_PARALLEL_TRAINING
- #define OPTION_PARALLEL_TRAINING TRUE
- #undef OPTION_MEM_RESTORE
- #define OPTION_MEM_RESTORE TRUE
- #undef OPTION_ONLINE_SPARE
- #define OPTION_ONLINE_SPARE TRUE
- #undef OPTION_DIMM_EXCLUDE
- #define OPTION_DIMM_EXCLUDE TRUE
- #endif
-#endif
-
-#if (OPTION_S1G4_SOCKET_SUPPORT == TRUE)
- #if (OPTION_FAMILY10H == TRUE)
- #undef OPTION_FAMILY10H_BL
- #define OPTION_FAMILY10H_BL TRUE
- #undef OPTION_FAMILY10H_DA
- #define OPTION_FAMILY10H_DA TRUE
- #undef OPTION_MEMCTLR_DA
- #define OPTION_MEMCTLR_DA TRUE
- #undef OPTION_HW_WRITE_LEV_TRAINING
- #define OPTION_HW_WRITE_LEV_TRAINING TRUE
- #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
- #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
- #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
- #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
- #undef OPTION_MAX_RD_LAT_TRAINING
- #define OPTION_MAX_RD_LAT_TRAINING TRUE
- #undef OPTION_SW_DRAM_INIT
- #define OPTION_SW_DRAM_INIT TRUE
- #undef OPTION_S3_MEM_SUPPORT
- #define OPTION_S3_MEM_SUPPORT TRUE
- #undef OPTION_CPU_CORELEVLING
- #define OPTION_CPU_CORELEVLING TRUE
- #undef OPTION_CPU_CFOH
- #define OPTION_CPU_CFOH TRUE
- #undef OPTION_UDIMMS
- #define OPTION_UDIMMS TRUE
- #undef OPTION_SODIMMS
- #define OPTION_SODIMMS TRUE
- #undef OPTION_DDR3
- #define OPTION_DDR3 TRUE
- #undef OPTION_ECC
- #define OPTION_ECC TRUE
- #undef OPTION_BANK_INTERLEAVE
- #define OPTION_BANK_INTERLEAVE TRUE
- #undef OPTION_DCT_INTERLEAVE
- #define OPTION_DCT_INTERLEAVE TRUE
- #undef OPTION_NODE_INTERLEAVE
- #define OPTION_NODE_INTERLEAVE TRUE
- #undef OPTION_MEM_RESTORE
- #define OPTION_MEM_RESTORE TRUE
- #undef OPTION_DIMM_EXCLUDE
- #define OPTION_DIMM_EXCLUDE TRUE
- #endif
-#endif
-
-#if (OPTION_ASB2_SOCKET_SUPPORT == TRUE)
- #if (OPTION_FAMILY10H == TRUE)
- #undef OPTION_FAMILY10H_BL
- #define OPTION_FAMILY10H_BL TRUE
- #undef OPTION_FAMILY10H_DA
- #define OPTION_FAMILY10H_DA TRUE
- #undef OPTION_MEMCTLR_Ni
- #define OPTION_MEMCTLR_Ni TRUE
- #undef OPTION_HW_WRITE_LEV_TRAINING
- #define OPTION_HW_WRITE_LEV_TRAINING TRUE
- #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
- #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
- #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
- #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
- #undef OPTION_MAX_RD_LAT_TRAINING
- #define OPTION_MAX_RD_LAT_TRAINING TRUE
- #undef OPTION_SW_DRAM_INIT
- #define OPTION_SW_DRAM_INIT TRUE
- #undef OPTION_S3_MEM_SUPPORT
- #define OPTION_S3_MEM_SUPPORT TRUE
- #undef OPTION_CPU_CORELEVLING
- #define OPTION_CPU_CORELEVLING TRUE
- #undef OPTION_CPU_CFOH
- #define OPTION_CPU_CFOH TRUE
- #undef OPTION_UDIMMS
- #define OPTION_UDIMMS TRUE
- #undef OPTION_SODIMMS
- #define OPTION_SODIMMS TRUE
- #undef OPTION_DDR3
- #define OPTION_DDR3 TRUE
- #undef OPTION_ECC
- #define OPTION_ECC TRUE
- #undef OPTION_BANK_INTERLEAVE
- #define OPTION_BANK_INTERLEAVE TRUE
- #undef OPTION_DCT_INTERLEAVE
- #define OPTION_DCT_INTERLEAVE TRUE
- #undef OPTION_NODE_INTERLEAVE
- #define OPTION_NODE_INTERLEAVE TRUE
- #undef OPTION_MEM_RESTORE
- #define OPTION_MEM_RESTORE TRUE
- #undef OPTION_DIMM_EXCLUDE
- #define OPTION_DIMM_EXCLUDE TRUE
- #endif
-#endif
-
-#if (OPTION_FS1_SOCKET_SUPPORT == TRUE)
- #if (OPTION_FAMILY12H == TRUE)
- #undef OPTION_FAMILY12H_LN
- #define OPTION_FAMILY12H_LN TRUE
- #undef OPTION_MEMCTLR_LN
- #define OPTION_MEMCTLR_LN TRUE
- #undef OPTION_HW_WRITE_LEV_TRAINING
- #define OPTION_HW_WRITE_LEV_TRAINING TRUE
- #undef OPTION_CONTINOUS_PATTERN_GENERATION
- #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
- #undef OPTION_HW_DQS_REC_EN_TRAINING
- #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
- #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
- #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
- #undef OPTION_MAX_RD_LAT_TRAINING
- #define OPTION_MAX_RD_LAT_TRAINING TRUE
- #undef OPTION_SW_DRAM_INIT
- #define OPTION_SW_DRAM_INIT TRUE
- #undef OPTION_S3_MEM_SUPPORT
- #define OPTION_S3_MEM_SUPPORT TRUE
- #undef OPTION_GFX_RECOVERY
- #define OPTION_GFX_RECOVERY TRUE
- #undef OPTION_C6_STATE
- #define OPTION_C6_STATE TRUE
- #undef OPTION_IO_CSTATE
- #define OPTION_IO_CSTATE TRUE
- #undef OPTION_CPB
- #define OPTION_CPB TRUE
- #undef OPTION_S3SCRIPT
- #define OPTION_S3SCRIPT TRUE
- #undef OPTION_UDIMMS
- #define OPTION_UDIMMS TRUE
- #undef OPTION_SODIMMS
- #define OPTION_SODIMMS TRUE
- #undef OPTION_DDR3
- #define OPTION_DDR3 TRUE
- #undef OPTION_BANK_INTERLEAVE
- #define OPTION_BANK_INTERLEAVE TRUE
- #undef OPTION_DCT_INTERLEAVE
- #define OPTION_DCT_INTERLEAVE TRUE
- #undef OPTION_MEM_RESTORE
- #define OPTION_MEM_RESTORE TRUE
- #undef OPTION_DIMM_EXCLUDE
- #define OPTION_DIMM_EXCLUDE TRUE
- #endif
-#endif
-
-#if (OPTION_FM1_SOCKET_SUPPORT == TRUE)
- #if (OPTION_FAMILY12H == TRUE)
- #undef OPTION_FAMILY12H_LN
- #define OPTION_FAMILY12H_LN TRUE
- #undef OPTION_MEMCTLR_LN
- #define OPTION_MEMCTLR_LN TRUE
- #undef OPTION_HW_WRITE_LEV_TRAINING
- #define OPTION_HW_WRITE_LEV_TRAINING TRUE
- #undef OPTION_CONTINOUS_PATTERN_GENERATION
- #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
- #undef OPTION_HW_DQS_REC_EN_TRAINING
- #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
- #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
- #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
- #undef OPTION_MAX_RD_LAT_TRAINING
- #define OPTION_MAX_RD_LAT_TRAINING TRUE
- #undef OPTION_SW_DRAM_INIT
- #define OPTION_SW_DRAM_INIT TRUE
- #undef OPTION_S3_MEM_SUPPORT
- #define OPTION_S3_MEM_SUPPORT TRUE
- #undef OPTION_GFX_RECOVERY
- #define OPTION_GFX_RECOVERY TRUE
- #undef OPTION_C6_STATE
- #define OPTION_C6_STATE TRUE
- #undef OPTION_IO_CSTATE
- #define OPTION_IO_CSTATE TRUE
- #undef OPTION_CPB
- #define OPTION_CPB TRUE
- #undef OPTION_S3SCRIPT
- #define OPTION_S3SCRIPT TRUE
- #undef OPTION_UDIMMS
- #define OPTION_UDIMMS TRUE
- #undef OPTION_SODIMMS
- #define OPTION_SODIMMS TRUE
- #undef OPTION_DDR3
- #define OPTION_DDR3 TRUE
- #undef OPTION_BANK_INTERLEAVE
- #define OPTION_BANK_INTERLEAVE TRUE
- #undef OPTION_DCT_INTERLEAVE
- #define OPTION_DCT_INTERLEAVE TRUE
- #undef OPTION_MEM_RESTORE
- #define OPTION_MEM_RESTORE TRUE
- #undef OPTION_DIMM_EXCLUDE
- #define OPTION_DIMM_EXCLUDE TRUE
- #endif
-#endif
-
-#if (OPTION_FP1_SOCKET_SUPPORT == TRUE)
- #if (OPTION_FAMILY12H == TRUE)
- #undef OPTION_FAMILY12H_LN
- #define OPTION_FAMILY12H_LN TRUE
- #undef OPTION_MEMCTLR_LN
- #define OPTION_MEMCTLR_LN TRUE
- #undef OPTION_HW_WRITE_LEV_TRAINING
- #define OPTION_HW_WRITE_LEV_TRAINING TRUE
- #undef OPTION_CONTINOUS_PATTERN_GENERATION
- #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
- #undef OPTION_HW_DQS_REC_EN_TRAINING
- #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
- #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
- #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
- #undef OPTION_MAX_RD_LAT_TRAINING
- #define OPTION_MAX_RD_LAT_TRAINING TRUE
- #undef OPTION_SW_DRAM_INIT
- #define OPTION_SW_DRAM_INIT TRUE
- #undef OPTION_S3_MEM_SUPPORT
- #define OPTION_S3_MEM_SUPPORT TRUE
- #undef OPTION_ADDR_TO_CS_TRANSLATOR
- #define OPTION_ADDR_TO_CS_TRANSLATOR TRUE
- #undef OPTION_GFX_RECOVERY
- #define OPTION_GFX_RECOVERY TRUE
- #undef OPTION_C6_STATE
- #define OPTION_C6_STATE TRUE
- #undef OPTION_IO_CSTATE
- #define OPTION_IO_CSTATE TRUE
- #undef OPTION_CPB
- #define OPTION_CPB TRUE
- #undef OPTION_S3SCRIPT
- #define OPTION_S3SCRIPT TRUE
- #undef OPTION_UDIMMS
- #define OPTION_UDIMMS TRUE
- #undef OPTION_SODIMMS
- #define OPTION_SODIMMS TRUE
- #undef OPTION_DDR3
- #define OPTION_DDR3 TRUE
- #undef OPTION_BANK_INTERLEAVE
- #define OPTION_BANK_INTERLEAVE TRUE
- #undef OPTION_DCT_INTERLEAVE
- #define OPTION_DCT_INTERLEAVE TRUE
- #undef OPTION_MEM_RESTORE
- #define OPTION_MEM_RESTORE TRUE
- #undef OPTION_ONLINE_SPARE
- #define OPTION_ONLINE_SPARE TRUE
- #undef OPTION_DIMM_EXCLUDE
- #define OPTION_DIMM_EXCLUDE TRUE
- #endif
-#endif
-
-#if (OPTION_FT1_SOCKET_SUPPORT == TRUE)
- #if (OPTION_FAMILY14H == TRUE)
- #undef OPTION_FAMILY14H_ON
- #define OPTION_FAMILY14H_ON TRUE
- #undef OPTION_MEMCTLR_ON
- #define OPTION_MEMCTLR_ON TRUE
- #undef OPTION_HW_WRITE_LEV_TRAINING
- #define OPTION_HW_WRITE_LEV_TRAINING TRUE
- #undef OPTION_CONTINOUS_PATTERN_GENERATION
- #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
- #undef OPTION_MAX_RD_LAT_TRAINING
- #define OPTION_MAX_RD_LAT_TRAINING TRUE
- #undef OPTION_HW_DQS_REC_EN_TRAINING
- #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
- #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
- #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
- #undef OPTION_SW_DRAM_INIT
- #define OPTION_SW_DRAM_INIT TRUE
- #undef OPTION_S3_MEM_SUPPORT
- #define OPTION_S3_MEM_SUPPORT TRUE
- #undef OPTION_GFX_RECOVERY
- #define OPTION_GFX_RECOVERY TRUE
- #undef OPTION_C6_STATE
- #define OPTION_C6_STATE TRUE
- #undef OPTION_IO_CSTATE
- #define OPTION_IO_CSTATE TRUE
- #undef OPTION_S3SCRIPT
- #define OPTION_S3SCRIPT TRUE
- #undef OPTION_UDIMMS
- #define OPTION_UDIMMS TRUE
- #undef OPTION_SODIMMS
- #define OPTION_SODIMMS TRUE
- #undef OPTION_DDR3
- #define OPTION_DDR3 TRUE
- #undef OPTION_BANK_INTERLEAVE
- #define OPTION_BANK_INTERLEAVE TRUE
- #undef OPTION_MEM_RESTORE
- #define OPTION_MEM_RESTORE TRUE
- #undef OPTION_DIMM_EXCLUDE
- #define OPTION_DIMM_EXCLUDE TRUE
- #endif
-#endif
-
-#if (OPTION_AM3_SOCKET_SUPPORT == TRUE)
- #if (OPTION_FAMILY10H == TRUE)
- #undef OPTION_FAMILY10H_BL
- #define OPTION_FAMILY10H_BL TRUE
- #undef OPTION_FAMILY10H_DA
- #define OPTION_FAMILY10H_DA TRUE
- #undef OPTION_FAMILY10H_PH
- #define OPTION_FAMILY10H_PH TRUE
- #undef OPTION_FAMILY10H_RB
- #define OPTION_FAMILY10H_RB TRUE
- #undef OPTION_MEMCTLR_RB
- #define OPTION_MEMCTLR_RB TRUE
- #undef OPTION_MEMCTLR_DA
- #define OPTION_MEMCTLR_DA TRUE
- #undef OPTION_MEMCTLR_PH
- #define OPTION_MEMCTLR_PH TRUE
- #undef OPTION_HW_WRITE_LEV_TRAINING
- #define OPTION_HW_WRITE_LEV_TRAINING TRUE
- #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
- #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
- #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
- #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
- #undef OPTION_MAX_RD_LAT_TRAINING
- #define OPTION_MAX_RD_LAT_TRAINING TRUE
- #undef OPTION_SW_DRAM_INIT
- #define OPTION_SW_DRAM_INIT TRUE
- #undef OPTION_S3_MEM_SUPPORT
- #define OPTION_S3_MEM_SUPPORT TRUE
- #undef OPTION_CPU_CORELEVLING
- #define OPTION_CPU_CORELEVLING TRUE
- #undef OPTION_CPU_CFOH
- #define OPTION_CPU_CFOH TRUE
- #undef OPTION_IO_CSTATE
- #define OPTION_IO_CSTATE TRUE
- #undef OPTION_CPB
- #define OPTION_CPB TRUE
- #undef OPTION_UDIMMS
- #define OPTION_UDIMMS TRUE
- #undef OPTION_SODIMMS
- #define OPTION_SODIMMS TRUE
- #undef OPTION_DDR3
- #define OPTION_DDR3 TRUE
- #undef OPTION_ECC
- #define OPTION_ECC TRUE
- #undef OPTION_BANK_INTERLEAVE
- #define OPTION_BANK_INTERLEAVE TRUE
- #undef OPTION_DCT_INTERLEAVE
- #define OPTION_DCT_INTERLEAVE TRUE
- #undef OPTION_NODE_INTERLEAVE
- #define OPTION_NODE_INTERLEAVE TRUE
- #undef OPTION_PARALLEL_TRAINING
- #define OPTION_PARALLEL_TRAINING TRUE
- #undef OPTION_MEM_RESTORE
- #define OPTION_MEM_RESTORE TRUE
- #undef OPTION_ONLINE_SPARE
- #define OPTION_ONLINE_SPARE TRUE
- #undef OPTION_DIMM_EXCLUDE
- #define OPTION_DIMM_EXCLUDE TRUE
- #endif
- #if (OPTION_FAMILY15H == TRUE)
- #undef OPTION_FAMILY15H_OR
- #define OPTION_FAMILY15H_OR TRUE
- #undef OPTION_MEMCTLR_OR
- #define OPTION_MEMCTLR_OR TRUE
- #undef OPTION_HW_WRITE_LEV_TRAINING
- #define OPTION_HW_WRITE_LEV_TRAINING TRUE
- #undef OPTION_CONTINOUS_PATTERN_GENERATION
- #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
- #undef OPTION_HW_DQS_REC_EN_TRAINING
- #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
- #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
- #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
- #undef OPTION_MAX_RD_LAT_TRAINING
- #define OPTION_MAX_RD_LAT_TRAINING TRUE
- #undef OPTION_SW_DRAM_INIT
- #define OPTION_SW_DRAM_INIT TRUE
- #undef OPTION_C6_STATE
- #define OPTION_C6_STATE TRUE
- #undef OPTION_IO_CSTATE
- #define OPTION_IO_CSTATE TRUE
- #undef OPTION_CPB
- #define OPTION_CPB TRUE
- #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
- #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE
- #undef OPTION_S3_MEM_SUPPORT
- #define OPTION_S3_MEM_SUPPORT TRUE
- #undef OPTION_ADDR_TO_CS_TRANSLATOR
- #define OPTION_ADDR_TO_CS_TRANSLATOR TRUE
- #undef OPTION_CPU_CORELEVLING
- #define OPTION_CPU_CORELEVLING TRUE
- #undef OPTION_CPU_CFOH
- #define OPTION_CPU_CFOH TRUE
- #undef OPTION_MSG_BASED_C1E
- #define OPTION_MSG_BASED_C1E TRUE
- #undef OPTION_UDIMMS
- #define OPTION_UDIMMS TRUE
- #undef OPTION_RDIMMS
- #define OPTION_RDIMMS TRUE
- #undef OPTION_LRDIMMS
- #define OPTION_LRDIMMS TRUE
- #undef OPTION_SODIMMS
- #define OPTION_SODIMMS TRUE
- #undef OPTION_DDR3
- #define OPTION_DDR3 TRUE
- #undef OPTION_ECC
- #define OPTION_ECC TRUE
- #undef OPTION_BANK_INTERLEAVE
- #define OPTION_BANK_INTERLEAVE TRUE
- #undef OPTION_DCT_INTERLEAVE
- #define OPTION_DCT_INTERLEAVE TRUE
- #undef OPTION_NODE_INTERLEAVE
- #define OPTION_NODE_INTERLEAVE TRUE
- #undef OPTION_MEM_RESTORE
- #define OPTION_MEM_RESTORE TRUE
- #undef OPTION_ONLINE_SPARE
- #define OPTION_ONLINE_SPARE TRUE
- #undef OPTION_DIMM_EXCLUDE
- #define OPTION_DIMM_EXCLUDE TRUE
- #endif
-#endif
-
-#if (OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE)
- #undef GNB_SUPPORT
- #define GNB_SUPPORT TRUE
-#endif
-
-#define OPTION_ACPI_PSTATES TRUE
-#define OPTION_WHEA TRUE
-#define OPTION_DMI TRUE
-#define OPTION_EARLY_SAMPLES FALSE
-#define CFG_ACPI_PSTATES_PPC TRUE
-#define CFG_ACPI_PSTATES_PCT TRUE
-#define CFG_ACPI_PSTATES_PSD TRUE
-#define CFG_ACPI_PSTATES_PSS TRUE
-#define CFG_ACPI_PSTATES_XPSS TRUE
-#define CFG_ACPI_PSTATE_PSD_INDPX FALSE
-#define CFG_VRM_HIGH_SPEED_ENABLE FALSE
-#define CFG_VRM_NB_HIGH_SPEED_ENABLE FALSE
-#define OPTION_ALIB TRUE
-/*---------------------------------------------------------------------------
- * Processing the options: Second, process the user's selections
- *--------------------------------------------------------------------------*/
-#ifdef BLDOPT_REMOVE_MULTISOCKET_SUPPORT
- #if BLDOPT_REMOVE_MULTISOCKET_SUPPORT == TRUE
- #undef OPTION_MULTISOCKET
- #define OPTION_MULTISOCKET FALSE
- #endif
-#endif
-#ifdef BLDOPT_REMOVE_ECC_SUPPORT
- #if BLDOPT_REMOVE_ECC_SUPPORT == TRUE
- #undef OPTION_ECC
- #define OPTION_ECC FALSE
- #endif
-#endif
-#ifdef BLDOPT_REMOVE_UDIMMS_SUPPORT
- #if BLDOPT_REMOVE_UDIMMS_SUPPORT == TRUE
- #undef OPTION_UDIMMS
- #define OPTION_UDIMMS FALSE
- #endif
-#endif
-#ifdef BLDOPT_REMOVE_RDIMMS_SUPPORT
- #if BLDOPT_REMOVE_RDIMMS_SUPPORT == TRUE
- #undef OPTION_RDIMMS
- #define OPTION_RDIMMS FALSE
- #endif
-#endif
-#ifdef BLDOPT_REMOVE_SODIMMS_SUPPORT
- #if BLDOPT_REMOVE_SODIMMS_SUPPORT == TRUE
- #undef OPTION_SODIMMS
- #define OPTION_SODIMMS FALSE
- #endif
-#endif
-#ifdef BLDOPT_REMOVE_LRDIMMS_SUPPORT
- #if BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE
- #undef OPTION_LRDIMMS
- #define OPTION_LRDIMMS FALSE
- #endif
-#endif
-#ifdef BLDOPT_REMOVE_BANK_INTERLEAVE
- #if BLDOPT_REMOVE_BANK_INTERLEAVE == TRUE
- #undef OPTION_BANK_INTERLEAVE
- #define OPTION_BANK_INTERLEAVE FALSE
- #endif
-#endif
-#ifdef BLDOPT_REMOVE_DCT_INTERLEAVE
- #if BLDOPT_REMOVE_DCT_INTERLEAVE == TRUE
- #undef OPTION_DCT_INTERLEAVE
- #define OPTION_DCT_INTERLEAVE FALSE
- #endif
-#endif
-#ifdef BLDOPT_REMOVE_NODE_INTERLEAVE
- #if BLDOPT_REMOVE_NODE_INTERLEAVE == TRUE
- #undef OPTION_NODE_INTERLEAVE
- #define OPTION_NODE_INTERLEAVE FALSE
- #endif
-#endif
-#ifdef BLDOPT_REMOVE_PARALLEL_TRAINING
- #if BLDOPT_REMOVE_PARALLEL_TRAINING == TRUE
- #undef OPTION_PARALLEL_TRAINING
- #define OPTION_PARALLEL_TRAINING FALSE
- #endif
-#endif
-#ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT
- #if BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE
- #undef OPTION_ONLINE_SPARE
- #define OPTION_ONLINE_SPARE FALSE
- #endif
-#endif
-#ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
- #if BLDOPT_REMOVE_MEM_RESTORE_SUPPORT == TRUE
- #undef OPTION_MEM_RESTORE
- #define OPTION_MEM_RESTORE FALSE
- #endif
-#endif
-#ifdef BLDOPT_REMOVE_ACPI_PSTATES
- #if BLDOPT_REMOVE_ACPI_PSTATES == TRUE
- #undef OPTION_ACPI_PSTATES
- #define OPTION_ACPI_PSTATES FALSE
- #endif
-#endif
-#ifdef BLDOPT_REMOVE_SRAT
- #if BLDOPT_REMOVE_SRAT == TRUE
- #undef OPTION_SRAT
- #define OPTION_SRAT FALSE
- #endif
-#endif
-#ifdef BLDOPT_REMOVE_SLIT
- #if BLDOPT_REMOVE_SLIT == TRUE
- #undef OPTION_SLIT
- #define OPTION_SLIT FALSE
- #endif
-#endif
-#ifdef BLDOPT_REMOVE_WHEA
- #if BLDOPT_REMOVE_WHEA == TRUE
- #undef OPTION_WHEA
- #define OPTION_WHEA FALSE
- #endif
-#endif
-#ifdef BLDOPT_REMOVE_DMI
- #if BLDOPT_REMOVE_DMI == TRUE
- #undef OPTION_DMI
- #define OPTION_DMI FALSE
- #endif
-#endif
-#ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR
- #if BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR == TRUE
- #undef OPTION_ADDR_TO_CS_TRANSLATOR
- #define OPTION_ADDR_TO_CS_TRANSLATOR FALSE
- #endif
-#endif
-
-#ifdef BLDOPT_REMOVE_HT_ASSIST
- #if BLDOPT_REMOVE_HT_ASSIST == TRUE
- #undef OPTION_HT_ASSIST
- #define OPTION_HT_ASSIST FALSE
- #endif
-#endif
-
-#ifdef BLDOPT_REMOVE_ATM_MODE
- #if BLDOPT_REMOVE_ATM_MODE == TRUE
- #undef OPTION_ATM_MODE
- #define OPTION_ATM_MODE FALSE
- #endif
-#endif
-
-#ifdef BLDOPT_REMOVE_MSG_BASED_C1E
- #if BLDOPT_REMOVE_MSG_BASED_C1E == TRUE
- #undef OPTION_MSG_BASED_C1E
- #define OPTION_MSG_BASED_C1E FALSE
- #endif
-#endif
-
-#ifdef BLDOPT_REMOVE_C6_STATE
- #if BLDOPT_REMOVE_C6_STATE == TRUE
- #undef OPTION_C6_STATE
- #define OPTION_C6_STATE FALSE
- #endif
-#endif
-
-#ifdef BLDOPT_REMOVE_GFX_RECOVERY
- #if BLDOPT_REMOVE_GFX_RECOVERY == TRUE
- #undef OPTION_GFX_RECOVERY
- #define OPTION_GFX_RECOVERY FALSE
- #endif
-#endif
-
-#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PPC
- #if BLDCFG_REMOVE_ACPI_PSTATES_PPC == TRUE
- #undef CFG_ACPI_PSTATES_PPC
- #define CFG_ACPI_PSTATES_PPC FALSE
- #endif
-#endif
-
-#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PCT
- #if BLDCFG_REMOVE_ACPI_PSTATES_PCT == TRUE
- #undef CFG_ACPI_PSTATES_PCT
- #define CFG_ACPI_PSTATES_PCT FALSE
- #endif
-#endif
-
-#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSD
- #if BLDCFG_REMOVE_ACPI_PSTATES_PSD == TRUE
- #undef CFG_ACPI_PSTATES_PSD
- #define CFG_ACPI_PSTATES_PSD FALSE
- #endif
-#endif
-
-#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSS
- #if BLDCFG_REMOVE_ACPI_PSTATES_PSS == TRUE
- #undef CFG_ACPI_PSTATES_PSS
- #define CFG_ACPI_PSTATES_PSS FALSE
- #endif
-#endif
-
-#ifdef BLDCFG_REMOVE_ACPI_PSTATES_XPSS
- #if BLDCFG_REMOVE_ACPI_PSTATES_XPSS == TRUE
- #undef CFG_ACPI_PSTATES_XPSS
- #define CFG_ACPI_PSTATES_XPSS FALSE
- #endif
-#endif
-
-#ifdef BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT
- #if BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT == TRUE
- #undef CFG_ACPI_PSTATE_PSD_INDPX
- #define CFG_ACPI_PSTATE_PSD_INDPX TRUE
- #endif
-#endif
-
-#ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE
- #if BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE
- #undef CFG_VRM_HIGH_SPEED_ENABLE
- #define CFG_VRM_HIGH_SPEED_ENABLE TRUE
- #endif
-#endif
-
-#ifdef BLDCFG_VRM_NB_HIGH_SPEED_ENABLE
- #if BLDCFG_VRM_NB_HIGH_SPEED_ENABLE == TRUE
- #undef CFG_VRM_NB_HIGH_SPEED_ENABLE
- #define CFG_VRM_NB_HIGH_SPEED_ENABLE TRUE
- #endif
-#endif
-
-#ifdef BLDCFG_STARTING_BUSNUM
- #define CFG_STARTING_BUSNUM (BLDCFG_STARTING_BUSNUM)
-#else
- #define CFG_STARTING_BUSNUM (0)
-#endif
-
-#ifdef BLDCFG_AMD_PLATFORM_TYPE
- #define CFG_AMD_PLATFORM_TYPE BLDCFG_AMD_PLATFORM_TYPE
-#else
- #define CFG_AMD_PLATFORM_TYPE 0
-#endif
-
-CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
-
-#ifdef BLDCFG_MAXIMUM_BUSNUM
- #define CFG_MAXIMUM_BUSNUM (BLDCFG_MAXIMUM_BUSNUM)
-#else
- #define CFG_MAXIMUM_BUSNUM (0xF8)
-#endif
-
-#ifdef BLDCFG_ALLOCATED_BUSNUM
- #define CFG_ALLOCATED_BUSNUM (BLDCFG_ALLOCATED_BUSNUM)
-#else
- #define CFG_ALLOCATED_BUSNUM (0x20)
-#endif
-
-#ifdef BLDCFG_BUID_SWAP_LIST
- #define CFG_BUID_SWAP_LIST (BLDCFG_BUID_SWAP_LIST)
-#else
- #define CFG_BUID_SWAP_LIST (NULL)
-#endif
-
-#ifdef BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST
- #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST)
-#else
- #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (NULL)
-#endif
-
-#ifdef BLDCFG_HTFABRIC_LIMITS_LIST
- #define CFG_HTFABRIC_LIMITS_LIST (BLDCFG_HTFABRIC_LIMITS_LIST)
-#else
- #define CFG_HTFABRIC_LIMITS_LIST (NULL)
-#endif
-
-#ifdef BLDCFG_HTCHAIN_LIMITS_LIST
- #define CFG_HTCHAIN_LIMITS_LIST (BLDCFG_HTCHAIN_LIMITS_LIST)
-#else
- #define CFG_HTCHAIN_LIMITS_LIST (NULL)
-#endif
-
-#ifdef BLDCFG_BUS_NUMBERS_LIST
- #define CFG_BUS_NUMBERS_LIST (BLDCFG_BUS_NUMBERS_LIST)
-#else
- #define CFG_BUS_NUMBERS_LIST (NULL)
-#endif
-
-#ifdef BLDCFG_IGNORE_LINK_LIST
- #define CFG_IGNORE_LINK_LIST (BLDCFG_IGNORE_LINK_LIST)
-#else
- #define CFG_IGNORE_LINK_LIST (NULL)
-#endif
-
-#ifdef BLDCFG_LINK_SKIP_REGANG_LIST
- #define CFG_LINK_SKIP_REGANG_LIST (BLDCFG_LINK_SKIP_REGANG_LIST)
-#else
- #define CFG_LINK_SKIP_REGANG_LIST (NULL)
-#endif
-
-#ifdef BLDCFG_SET_HTCRC_SYNC_FLOOD
- #define CFG_SET_HTCRC_SYNC_FLOOD (BLDCFG_SET_HTCRC_SYNC_FLOOD)
-#else
- #define CFG_SET_HTCRC_SYNC_FLOOD (FALSE)
-#endif
-
-#ifdef BLDCFG_USE_UNIT_ID_CLUMPING
- #define CFG_USE_UNIT_ID_CLUMPING (BLDCFG_USE_UNIT_ID_CLUMPING)
-#else
- #define CFG_USE_UNIT_ID_CLUMPING (FALSE)
-#endif
-
-#ifdef BLDCFG_ADDITIONAL_TOPOLOGIES_LIST
- #define CFG_ADDITIONAL_TOPOLOGIES_LIST (BLDCFG_ADDITIONAL_TOPOLOGIES_LIST)
-#else
- #define CFG_ADDITIONAL_TOPOLOGIES_LIST (NULL)
-#endif
-
-#ifdef BLDCFG_USE_HT_ASSIST
- #define CFG_USE_HT_ASSIST (BLDCFG_USE_HT_ASSIST)
-#else
- #define CFG_USE_HT_ASSIST (TRUE)
-#endif
-
-#ifdef BLDCFG_USE_ATM_MODE
- #define CFG_USE_ATM_MODE (BLDCFG_USE_ATM_MODE)
-#else
- #define CFG_USE_ATM_MODE (TRUE)
-#endif
-
-#ifdef BLDCFG_PLATFORM_CONTROL_FLOW_MODE
- #define CFG_PLATFORM_CONTROL_FLOW_MODE (BLDCFG_PLATFORM_CONTROL_FLOW_MODE)
-#else
- #define CFG_PLATFORM_CONTROL_FLOW_MODE (Nfcm)
-#endif
-
-#ifdef BLDCFG_PLATFORM_DEEMPHASIS_LIST
- #define CFG_PLATFORM_DEEMPHASIS_LIST (BLDCFG_PLATFORM_DEEMPHASIS_LIST)
-#else
- #define CFG_PLATFORM_DEEMPHASIS_LIST (NULL)
-#endif
-
-#ifdef BLDCFG_VRM_ADDITIONAL_DELAY
- #define CFG_VRM_ADDITIONAL_DELAY (BLDCFG_VRM_ADDITIONAL_DELAY)
-#else
- #define CFG_VRM_ADDITIONAL_DELAY (0)
-#endif
-
-#ifdef BLDCFG_VRM_CURRENT_LIMIT
- #define CFG_VRM_CURRENT_LIMIT BLDCFG_VRM_CURRENT_LIMIT
-#else
- #define CFG_VRM_CURRENT_LIMIT 0
-#endif
-
-#ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD
- #define CFG_VRM_LOW_POWER_THRESHOLD BLDCFG_VRM_LOW_POWER_THRESHOLD
-#else
- #define CFG_VRM_LOW_POWER_THRESHOLD 0
-#endif
-
-#ifdef BLDCFG_VRM_SLEW_RATE
- #define CFG_VRM_SLEW_RATE BLDCFG_VRM_SLEW_RATE
-#else
- #define CFG_VRM_SLEW_RATE DFLT_VRM_SLEW_RATE
-#endif
-
-#ifdef BLDCFG_VRM_INRUSH_CURRENT_LIMIT
- #define CFG_VRM_INRUSH_CURRENT_LIMIT BLDCFG_VRM_INRUSH_CURRENT_LIMIT
-#else
- #define CFG_VRM_INRUSH_CURRENT_LIMIT 0
-#endif
-
-#ifdef BLDCFG_VRM_NB_ADDITIONAL_DELAY
- #define CFG_VRM_NB_ADDITIONAL_DELAY (BLDCFG_VRM_NB_ADDITIONAL_DELAY)
-#else
- #define CFG_VRM_NB_ADDITIONAL_DELAY (0)
-#endif
-
-#ifdef BLDCFG_VRM_NB_CURRENT_LIMIT
- #define CFG_VRM_NB_CURRENT_LIMIT BLDCFG_VRM_NB_CURRENT_LIMIT
-#else
- #define CFG_VRM_NB_CURRENT_LIMIT (0)
-#endif
-
-#ifdef BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
- #define CFG_VRM_NB_LOW_POWER_THRESHOLD BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
-#else
- #define CFG_VRM_NB_LOW_POWER_THRESHOLD (0)
-#endif
-
-#ifdef BLDCFG_VRM_NB_SLEW_RATE
- #define CFG_VRM_NB_SLEW_RATE BLDCFG_VRM_NB_SLEW_RATE
-#else
- #define CFG_VRM_NB_SLEW_RATE DFLT_VRM_SLEW_RATE
-#endif
-
-#ifdef BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT
- #define CFG_VRM_NB_INRUSH_CURRENT_LIMIT BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT
-#else
- #define CFG_VRM_NB_INRUSH_CURRENT_LIMIT (0)
-#endif
-
-
-#ifdef BLDCFG_PLAT_NUM_IO_APICS
- #define CFG_PLAT_NUM_IO_APICS BLDCFG_PLAT_NUM_IO_APICS
-#else
- #define CFG_PLAT_NUM_IO_APICS 0
-#endif
-
-#ifdef BLDCFG_MEM_INIT_PSTATE
- #define CFG_MEM_INIT_PSTATE BLDCFG_MEM_INIT_PSTATE
-#else
- #define CFG_MEM_INIT_PSTATE 0
-#endif
-
-#ifdef BLDCFG_PLATFORM_C1E_MODE
- #define CFG_C1E_MODE BLDCFG_PLATFORM_C1E_MODE
-#else
- #define CFG_C1E_MODE C1eModeDisabled
-#endif
-
-#ifdef BLDCFG_PLATFORM_C1E_OPDATA
- #define CFG_C1E_OPDATA BLDCFG_PLATFORM_C1E_OPDATA
-#else
- #define CFG_C1E_OPDATA 0
-#endif
-
-#ifdef BLDCFG_PLATFORM_C1E_OPDATA1
- #define CFG_C1E_OPDATA1 BLDCFG_PLATFORM_C1E_OPDATA1
-#else
- #define CFG_C1E_OPDATA1 0
-#endif
-
-#ifdef BLDCFG_PLATFORM_C1E_OPDATA2
- #define CFG_C1E_OPDATA2 BLDCFG_PLATFORM_C1E_OPDATA2
-#else
- #define CFG_C1E_OPDATA2 0
-#endif
-
-#ifdef BLDCFG_PLATFORM_CSTATE_MODE
- #define CFG_CSTATE_MODE BLDCFG_PLATFORM_CSTATE_MODE
-#else
- #define CFG_CSTATE_MODE CStateModeDisabled
-#endif
-
-#ifdef BLDCFG_PLATFORM_CSTATE_OPDATA
- #define CFG_CSTATE_OPDATA BLDCFG_PLATFORM_CSTATE_OPDATA
-#else
- #define CFG_CSTATE_OPDATA 0
-#endif
-
-#ifdef BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
- #define CFG_CSTATE_IO_BASE_ADDRESS BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
-#else
- #define CFG_CSTATE_IO_BASE_ADDRESS 0
-#endif
-
-#ifdef BLDCFG_PLATFORM_CPB_MODE
- #define CFG_CPB_MODE BLDCFG_PLATFORM_CPB_MODE
-#else
- #define CFG_CPB_MODE CpbModeAuto
-#endif
-
-#ifdef BLDCFG_CORE_LEVELING_MODE
- #define CFG_CORE_LEVELING_MODE BLDCFG_CORE_LEVELING_MODE
-#else
- #define CFG_CORE_LEVELING_MODE 0
-#endif
-
-#ifdef BLDCFG_AMD_PSTATE_CAP_VALUE
- #define CFG_AMD_PSTATE_CAP_VALUE BLDCFG_AMD_PSTATE_CAP_VALUE
-#else
- #define CFG_AMD_PSTATE_CAP_VALUE 0
-#endif
-
-#ifdef BLDCFG_HEAP_DRAM_ADDRESS
- #define CFG_HEAP_DRAM_ADDRESS BLDCFG_HEAP_DRAM_ADDRESS
-#else
- #define CFG_HEAP_DRAM_ADDRESS AMD_HEAP_RAM_ADDRESS
-#endif
-
-#ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
- #define CFG_MEMORY_BUS_FREQUENCY_LIMIT BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
-#else
- #define CFG_MEMORY_BUS_FREQUENCY_LIMIT DDR800_FREQUENCY
-#endif
-
-#ifdef BLDCFG_MEMORY_MODE_UNGANGED
- #define CFG_MEMORY_MODE_UNGANGED BLDCFG_MEMORY_MODE_UNGANGED
-#else
- #define CFG_MEMORY_MODE_UNGANGED TRUE
-#endif
-
-#ifdef BLDCFG_MEMORY_QUAD_RANK_CAPABLE
- #define CFG_MEMORY_QUAD_RANK_CAPABLE BLDCFG_MEMORY_QUAD_RANK_CAPABLE
-#else
- #define CFG_MEMORY_QUAD_RANK_CAPABLE TRUE
-#endif
-
-#ifdef BLDCFG_MEMORY_QUADRANK_TYPE
- #define CFG_MEMORY_QUADRANK_TYPE BLDCFG_MEMORY_QUADRANK_TYPE
-#else
- #define CFG_MEMORY_QUADRANK_TYPE DFLT_MEMORY_QUADRANK_TYPE
-#endif
-
-#ifdef BLDCFG_MEMORY_RDIMM_CAPABLE
- #define CFG_MEMORY_RDIMM_CAPABLE BLDCFG_MEMORY_RDIMM_CAPABLE
-#else
- #define CFG_MEMORY_RDIMM_CAPABLE TRUE
-#endif
-
-#ifdef BLDCFG_MEMORY_LRDIMM_CAPABLE
- #define CFG_MEMORY_LRDIMM_CAPABLE BLDCFG_MEMORY_LRDIMM_CAPABLE
-#else
- #define CFG_MEMORY_LRDIMM_CAPABLE TRUE
-#endif
-
-#ifdef BLDCFG_MEMORY_UDIMM_CAPABLE
- #define CFG_MEMORY_UDIMM_CAPABLE BLDCFG_MEMORY_UDIMM_CAPABLE
-#else
- #define CFG_MEMORY_UDIMM_CAPABLE TRUE
-#endif
-
-#ifdef BLDCFG_MEMORY_SODIMM_CAPABLE
- #define CFG_MEMORY_SODIMM_CAPABLE BLDCFG_MEMORY_SODIMM_CAPABLE
-#else
- #define CFG_MEMORY_SODIMM_CAPABLE FALSE
-#endif
-
-#ifdef BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
- #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
-#else
- #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
-#endif
-
-#ifdef BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
- #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
-#else
- #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
-#endif
-
-#ifdef BLDCFG_MEMORY_CHANNEL_INTERLEAVING
- #define CFG_MEMORY_CHANNEL_INTERLEAVING BLDCFG_MEMORY_CHANNEL_INTERLEAVING
-#else
- #define CFG_MEMORY_CHANNEL_INTERLEAVING TRUE
-#endif
-
-#ifdef BLDCFG_MEMORY_POWER_DOWN
- #define CFG_MEMORY_POWER_DOWN BLDCFG_MEMORY_POWER_DOWN
-#else
- #define CFG_MEMORY_POWER_DOWN FALSE
-#endif
-
-#ifdef BLDCFG_POWER_DOWN_MODE
- #define CFG_POWER_DOWN_MODE BLDCFG_POWER_DOWN_MODE
-#else
- #define CFG_POWER_DOWN_MODE POWER_DOWN_MODE_AUTO
-#endif
-
-#ifdef BLDCFG_ONLINE_SPARE
- #define CFG_ONLINE_SPARE BLDCFG_ONLINE_SPARE
-#else
- #define CFG_ONLINE_SPARE FALSE
-#endif
-
-#ifdef BLDCFG_MEMORY_PARITY_ENABLE
- #define CFG_MEMORY_PARITY_ENABLE BLDCFG_MEMORY_PARITY_ENABLE
-#else
- #define CFG_MEMORY_PARITY_ENABLE FALSE
-#endif
-
-#ifdef BLDCFG_BANK_SWIZZLE
- #define CFG_BANK_SWIZZLE BLDCFG_BANK_SWIZZLE
-#else
- #define CFG_BANK_SWIZZLE TRUE
-#endif
-
-#ifdef BLDCFG_TIMING_MODE_SELECT
- #define CFG_TIMING_MODE_SELECT BLDCFG_TIMING_MODE_SELECT
-#else
- #define CFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
-#endif
-
-#ifdef BLDCFG_MEMORY_CLOCK_SELECT
- #define CFG_MEMORY_CLOCK_SELECT BLDCFG_MEMORY_CLOCK_SELECT
-#else
- #define CFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY
-#endif
-
-#ifdef BLDCFG_DQS_TRAINING_CONTROL
- #define CFG_DQS_TRAINING_CONTROL BLDCFG_DQS_TRAINING_CONTROL
-#else
- #define CFG_DQS_TRAINING_CONTROL TRUE
-#endif
-
-#ifdef BLDCFG_IGNORE_SPD_CHECKSUM
- #define CFG_IGNORE_SPD_CHECKSUM BLDCFG_IGNORE_SPD_CHECKSUM
-#else
- #define CFG_IGNORE_SPD_CHECKSUM FALSE
-#endif
-
-#ifdef BLDCFG_USE_BURST_MODE
- #define CFG_USE_BURST_MODE BLDCFG_USE_BURST_MODE
-#else
- #define CFG_USE_BURST_MODE FALSE
-#endif
-
-#ifdef BLDCFG_MEMORY_ALL_CLOCKS_ON
- #define CFG_MEMORY_ALL_CLOCKS_ON BLDCFG_MEMORY_ALL_CLOCKS_ON
-#else
- #define CFG_MEMORY_ALL_CLOCKS_ON FALSE
-#endif
-
-#ifdef BLDCFG_ENABLE_ECC_FEATURE
- #define CFG_ENABLE_ECC_FEATURE BLDCFG_ENABLE_ECC_FEATURE
-#else
- #define CFG_ENABLE_ECC_FEATURE TRUE
-#endif
-
-#ifdef BLDCFG_ECC_REDIRECTION
- #define CFG_ECC_REDIRECTION BLDCFG_ECC_REDIRECTION
-#else
- #define CFG_ECC_REDIRECTION FALSE
-#endif
-
-#ifdef BLDCFG_SCRUB_DRAM_RATE
- #define CFG_SCRUB_DRAM_RATE BLDCFG_SCRUB_DRAM_RATE
-#else
- #define CFG_SCRUB_DRAM_RATE DFLT_SCRUB_DRAM_RATE
-#endif
-
-#ifdef BLDCFG_SCRUB_L2_RATE
- #define CFG_SCRUB_L2_RATE BLDCFG_SCRUB_L2_RATE
-#else
- #define CFG_SCRUB_L2_RATE DFLT_SCRUB_L2_RATE
-#endif
-
-#ifdef BLDCFG_SCRUB_L3_RATE
- #define CFG_SCRUB_L3_RATE BLDCFG_SCRUB_L3_RATE
-#else
- #define CFG_SCRUB_L3_RATE DFLT_SCRUB_L3_RATE
-#endif
-
-#ifdef BLDCFG_SCRUB_IC_RATE
- #define CFG_SCRUB_IC_RATE BLDCFG_SCRUB_IC_RATE
-#else
- #define CFG_SCRUB_IC_RATE DFLT_SCRUB_IC_RATE
-#endif
-
-#ifdef BLDCFG_SCRUB_DC_RATE
- #define CFG_SCRUB_DC_RATE BLDCFG_SCRUB_DC_RATE
-#else
- #define CFG_SCRUB_DC_RATE DFLT_SCRUB_DC_RATE
-#endif
-
-#ifdef BLDCFG_ECC_SYNC_FLOOD
- #define CFG_ECC_SYNC_FLOOD BLDCFG_ECC_SYNC_FLOOD
-#else
- #define CFG_ECC_SYNC_FLOOD 0
-#endif
-
-#ifdef BLDCFG_ECC_SYMBOL_SIZE
- #define CFG_ECC_SYMBOL_SIZE BLDCFG_ECC_SYMBOL_SIZE
-#else
- #define CFG_ECC_SYMBOL_SIZE 0
-#endif
-
-#ifdef BLDCFG_1GB_ALIGN
- #define CFG_1GB_ALIGN BLDCFG_1GB_ALIGN
-#else
- #define CFG_1GB_ALIGN FALSE
-#endif
-
-#ifdef BLDCFG_UMA_ALLOCATION_MODE
- #define CFG_UMA_MODE BLDCFG_UMA_ALLOCATION_MODE
-#else
- #define CFG_UMA_MODE UMA_AUTO
-#endif
-
-#ifdef BLDCFG_UMA_ALLOCATION_SIZE
- #define CFG_UMA_SIZE BLDCFG_UMA_ALLOCATION_SIZE
-#else
- #define CFG_UMA_SIZE 0
-#endif
-
-#ifdef BLDCFG_UMA_ABOVE4G_SUPPORT
- #define CFG_UMA_ABOVE4G BLDCFG_UMA_ABOVE4G_SUPPORT
-#else
- #define CFG_UMA_ABOVE4G FALSE
-#endif
-
-#ifdef BLDCFG_UMA_ALIGNMENT
- #define CFG_UMA_ALIGNMENT BLDCFG_UMA_ALIGNMENT
-#else
- #define CFG_UMA_ALIGNMENT NO_UMA_ALIGNED
-#endif
-
-#ifdef BLDCFG_PROCESSOR_SCOPE_IN_SB
- #define CFG_PROCESSOR_SCOPE_IN_SB BLDCFG_PROCESSOR_SCOPE_IN_SB
-#else
- #define CFG_PROCESSOR_SCOPE_IN_SB FALSE
-#endif
-
-#ifdef BLDCFG_S3_LATE_RESTORE
- #define CFG_S3_LATE_RESTORE BLDCFG_S3_LATE_RESTORE
-#else
- #define CFG_S3_LATE_RESTORE TRUE
-#endif
-
-#ifdef BLDCFG_USE_32_BYTE_REFRESH
- #define CFG_USE_32_BYTE_REFRESH (BLDCFG_USE_32_BYTE_REFRESH)
-#else
- #define CFG_USE_32_BYTE_REFRESH (FALSE)
-#endif
-
-#ifdef BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY
- #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
-#else
- #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (FALSE)
-#endif
-
-#ifdef BLDCFG_PROCESSOR_SCOPE_NAME0
- #define CFG_PROCESSOR_SCOPE_NAME0 BLDCFG_PROCESSOR_SCOPE_NAME0
-#else
- #define CFG_PROCESSOR_SCOPE_NAME0 SCOPE_NAME_VALUE
-#endif
-
-#ifdef BLDCFG_PROCESSOR_SCOPE_NAME1
- #define CFG_PROCESSOR_SCOPE_NAME1 BLDCFG_PROCESSOR_SCOPE_NAME1
-#else
- #define CFG_PROCESSOR_SCOPE_NAME1 SCOPE_NAME_VALUE1
-#endif
-
-#ifdef BLDCFG_CFG_GNB_HD_AUDIO
- #define CFG_GNB_HD_AUDIO BLDCFG_CFG_GNB_HD_AUDIO
-#else
- #define CFG_GNB_HD_AUDIO TRUE
-#endif
-
-#ifdef BLDCFG_CFG_ABM_SUPPORT
- #define CFG_ABM_SUPPORT BLDCFG_CFG_ABM_SUPPORT
-#else
- #define CFG_ABM_SUPPORT FALSE
-#endif
-
-#ifdef BLDCFG_CFG_DYNAMIC_REFRESH_RATE
- #define CFG_DINAMIC_REFRESH_RATE BLDCFG_CFG_DYNAMIC_REFRESH_RATE
-#else
- #define CFG_DYNAMIC_REFRESH_RATE 0
-#endif
-
-#ifdef BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
- #define CFG_LCD_BACK_LIGHT_CONTROL BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
-#else
- #define CFG_LCD_BACK_LIGHT_CONTROL 0
-#endif
-
-#ifdef BLDCFG_STEREO_3D_PINOUT
- #define CFG_GNB_STEREO_3D_PINOUT BLDCFG_STEREO_3D_PINOUT
-#else
- #define CFG_GNB_STEREO_3D_PINOUT 0
-#endif
-
-#ifdef BLDCFG_IGPU_SUBSYSTEM_ID
- #define CFG_GNB_IGPU_SSID BLDCFG_IGPU_SUBSYSTEM_ID
-#else
- #define CFG_GNB_IGPU_SSID 0
-#endif
-
-#ifdef BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID
- #define CFG_GNB_HDAUDIO_SSID BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID
-#else
- #define CFG_GNB_HDAUDIO_SSID 0
-#endif
-
-#ifdef BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
- #define CFG_GNB_PCIE_SSID BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
-#else
- #define CFG_GNB_PCIE_SSID 0x12341022
-#endif
-
-#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM
- #define CFG_GFX_LVDS_SPREAD_SPECTRUM BLDCFG_GFX_LVDS_SPREAD_SPECTRUM
-#else
- #define CFG_GFX_LVDS_SPREAD_SPECTRUM 0
-#endif
-
-#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE
- #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE
-#else
- #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE 0
-#endif
-
-#ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
- #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
-#else
- #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000
-#endif
-
-#ifdef BLDOPT_REMOVE_EARLY_SAMPLES
- #if BLDOPT_REMOVE_EARLY_SAMPLES == TRUE
- #undef OPTION_EARLY_SAMPLES
- #define OPTION_EARLY_SAMPLES FALSE
- #else
- #undef OPTION_EARLY_SAMPLES
- #define OPTION_EARLY_SAMPLES TRUE
- #endif
-#endif
-
-#ifdef BLDOPT_REMOVE_ALIB
- #if BLDOPT_REMOVE_ALIB == TRUE
- #undef OPTION_ALIB
- #define OPTION_ALIB FALSE
- #else
- #undef OPTION_ALIB
- #define OPTION_ALIB TRUE
- #endif
-#endif
-
-/*---------------------------------------------------------------------------
- * Processing the options: Third, perform the option cross checks
- *--------------------------------------------------------------------------*/
-// Assure that at least one type of memory support is included
-#if OPTION_UDIMMS == FALSE
- #if OPTION_RDIMMS == FALSE
- #if OPTION_SODIMMS == FALSE
- #if OPTION_LRDIMMS == FALSE
- #error BLDOPT: No DIMM support selected. Either BLDOPT_REMOVE_UDIMMS_SUPPORT or BLDOPT_REMOVE_RDIMMS_SUPPORT or BLDOPT_REMOVE_SODIMMS_SUPPORT or BLDOPT_REMOVE_LRDIMMS_SUPPORT must be FALSE.
- #endif
- #endif
- #endif
-#endif
-// Ensure at least one dimm type is capable
-#if CFG_MEMORY_RDIMM_CAPABLE == FALSE
- #if CFG_MEMORY_UDIMM_CAPABLE == FALSE
- #if CFG_MEMORY_SODIMM_CAPABLE == FALSE
- #if CFG_MEMORY_LRDIMM_CAPABLE == FALSE
- #error BLDCFG: No dimm type is capable
- #endif
- #endif
- #endif
-#endif
-// Check LRDIMM CODE and LRDIMM CFG item
-#if CFG_MEMORY_LRDIMM_CAPABLE == FALSE
- #if BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE
- #error Warning: LRDIMM capability is false, but LRIDMM support code included
- #endif
-#endif
-// Turn off multi-socket based features if only one node...
-#if OPTION_MULTISOCKET == FALSE
- #undef OPTION_PARALLEL_TRAINING
- #define OPTION_PARALLEL_TRAINING FALSE
- #undef OPTION_NODE_INTERLEAVE
- #define OPTION_NODE_INTERLEAVE FALSE
-#endif
-// Ensure that at least one write leveling option is selected
-#if OPTION_DDR3 == TRUE
- #if OPTION_HW_WRITE_LEV_TRAINING == FALSE
- #if OPTION_SW_WRITE_LEV_TRAINING == FALSE
- #error No Write leveling option selected for DDR3
- #endif
- #endif
- #if OPTION_SW_DRAM_INIT == FALSE
- #error Software dram init must be enabled for DDR3 dimms
- #endif
-#endif
-// Ensure at least one DQS receiver training option is selected
-#if OPTION_HW_DQS_REC_EN_TRAINING == FALSE
- #if OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == FALSE
- #if OPTION_OPT_SW_DQS_REC_EN_TRAINING == FALSE
- #error No DQS receiver training option has been slected
- #endif
- #endif
-#endif
-// Ensure at least one Rd Wr position training option has been selected
-#if OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == FALSE
- #if OPTION_OPT_SW_RD_WR_POS_TRAINING == FALSE
- #error No Rd Wr position training option has been selected
- #endif
-#endif
-// Ensure at least one dram init option has been selected
-#if OPTION_HW_DRAM_INIT == FALSE
- #if OPTION_SW_DRAM_INIT == FALSE
- #error No Dram init option has been selected
- #endif
-#endif
-// Ensure the frequency limit is valid
-#if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1866_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 933)
- #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1600_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 800)
- #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1333_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 667)
- #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1066_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 533)
- #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR800_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 400)
- #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR667_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 333)
- #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR533_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 266)
- #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR400_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 200)
- #error BLDCFG: Unsupported memory bus frequency
- #endif
- #endif
- #endif
- #endif
- #endif
- #endif
- #endif
-#endif
-// Ensure timing mode is valid
-#if CFG_TIMING_MODE_SELECT != TIMING_MODE_SPECIFIC
- #if CFG_TIMING_MODE_SELECT != TIMING_MODE_LIMITED
- #if CFG_TIMING_MODE_SELECT != TIMING_MODE_AUTO
- #error BLDCFG: Invalid timing mode is set
- #endif
- #endif
-#endif
-// Ensure the scrub rate is valid
-#if ((CFG_SCRUB_DRAM_RATE > 0x16) && (CFG_SCRUB_DRAM_RATE != 0xFF))
- #error BLDCFG: Unsupported dram scrub rate set
-#endif
-#if CFG_SCRUB_L2_RATE > 0x16
- #error BLDCFG: Unsupported L2 scrubber rate set
-#endif
-#if CFG_SCRUB_L3_RATE > 0x16
- #error BLDCFG: unsupported L3 scrubber rate set
-#endif
-#if CFG_SCRUB_IC_RATE > 0x16
- #error BLDCFG: Unsupported Instruction cache scrub rate set
-#endif
-#if CFG_SCRUB_DC_RATE > 0x16
- #error BLDCFG: Unsupported Dcache scrub rate set
-#endif
-// Ensure Quad rank dimm type is valid
-#if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_UNBUFFERED
- #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_REGISTERED
- #error BLDCFG: Invalid quad rank dimm type set
- #endif
-#endif
-// Ensure ECC symbol size is valid
-#if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_USE_BKDG
- #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X4
- #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X8
- #error BLDCFG: Invalid Ecc symbol size set
- #endif
- #endif
-#endif
-// Ensure power down mode is valid
-#if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHIP_SELECT
- #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHANNEL
- #error BLDCFG: Invalid power down mode set
- #endif
-#endif
-
-/*****************************************************************************
- *
- * Process the option logic, setting local control variables
- *
- ****************************************************************************/
-#if OPTION_ACPI_PSTATES == TRUE
- #define OPTFCN_ACPI_TABLES CreateAcpiTablesMain
- #define OPTFCN_GATHER_DATA PStateGatherData
- #if OPTION_MULTISOCKET == TRUE
- #define OPTFCN_PSTATE_LEVELING PStateLeveling
- #else
- #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess
- #endif
-#else
- #define OPTFCN_ACPI_TABLES CommonReturnAgesaSuccess
- #define OPTFCN_GATHER_DATA CommonReturnAgesaSuccess
- #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess
-#endif
-
-
-/*****************************************************************************
- *
- * Include the structure definitions for the defaults table structures
- *
- ****************************************************************************/
-#include "Options.h"
-#include "OptionCpuFamiliesInstall.h"
-#include "OptionsHt.h"
-#include "OptionHtInstall.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "OptionMemoryInstall.h"
-#include "OptionMemoryRecovery.h"
-#include "OptionMemoryRecoveryInstall.h"
-#include "OptionCpuFeaturesInstall.h"
-#include "OptionDmi.h"
-#include "OptionDmiInstall.h"
-#include "OptionPstate.h"
-#include "OptionPstateInstall.h"
-#include "OptionWhea.h"
-#include "OptionWheaInstall.h"
-#include "OptionSrat.h"
-#include "OptionSratInstall.h"
-#include "OptionSlit.h"
-#include "OptionSlitInstall.h"
-#include "OptionMultiSocket.h"
-#include "OptionMultiSocketInstall.h"
-#include "OptionIdsInstall.h"
-#include "OptionGfxRecovery.h"
-#include "OptionGfxRecoveryInstall.h"
-#include "OptionGnb.h"
-#include "OptionGnbInstall.h"
-#include "OptionS3ScriptInstall.h"
-
-
-/*****************************************************************************
- *
- * Generate the output structures (defaults tables)
- *
- ****************************************************************************/
-BUILD_OPT_CFG UserOptions = {
- { // AGESA version string
- AGESA_CODE_SIGNATURE, // code header Signature
- AGESA_PACKAGE_STRING, // 8 character ID
- AGESA_VERSION_STRING, // 12 character version string
- 0 // null string terminator
- },
- //Build Option Area
- OPTION_UDIMMS, //UDIMMS
- OPTION_RDIMMS, //RDIMMS
- OPTION_LRDIMMS, //LRDIMMS
- OPTION_ECC, //ECC
- OPTION_BANK_INTERLEAVE, //BANK_INTERLEAVE
- OPTION_DCT_INTERLEAVE, //DCT_INTERLEAVE
- OPTION_NODE_INTERLEAVE, //NODE_INTERLEAVE
- OPTION_PARALLEL_TRAINING, //PARALLEL_TRAINING
- OPTION_ONLINE_SPARE, //ONLINE_SPARE
- OPTION_MEM_RESTORE, //MEM CONTEXT RESTORE
- OPTION_MULTISOCKET, //MULTISOCKET
- OPTION_ACPI_PSTATES, //ACPI_PSTATES
- OPTION_SRAT, //SRAT
- OPTION_SLIT, //SLIT
- OPTION_WHEA, //WHEA
- OPTION_DMI, //DMI
- OPTION_EARLY_SAMPLES, //EARLY_SAMPLES
- OPTION_ADDR_TO_CS_TRANSLATOR, //ADDR_TO_CS_TRANSLATOR
-
- //Build Configuration Area
- CFG_PCI_MMIO_BASE,
- CFG_PCI_MMIO_SIZE,
- {
- // CoreVrm
- {
- CFG_VRM_CURRENT_LIMIT, // VrmCurrentLimit
- CFG_VRM_LOW_POWER_THRESHOLD, // VrmLowPowerThershold
- CFG_VRM_SLEW_RATE, // VrmSlewRate
- CFG_VRM_ADDITIONAL_DELAY, // VrmAdditionalDelay
- CFG_VRM_HIGH_SPEED_ENABLE, // VrmHiSpeedEnable
- CFG_VRM_INRUSH_CURRENT_LIMIT // VrmInrushCurrentLimit
- },
- // NbVrm
- {
- CFG_VRM_NB_CURRENT_LIMIT, // VrmNbCurrentLimit
- CFG_VRM_NB_LOW_POWER_THRESHOLD, // VrmNbLowPowerThershold
- CFG_VRM_NB_SLEW_RATE, // VrmNbSlewRate
- CFG_VRM_NB_ADDITIONAL_DELAY, // VrmNbAdditionalDelay
- CFG_VRM_NB_HIGH_SPEED_ENABLE, // VrmNbHiSpeedEnable
- CFG_VRM_NB_INRUSH_CURRENT_LIMIT // VrmNbInrushCurrentLimit
- }
- },
- CFG_PLAT_NUM_IO_APICS, //PlatformApicIoNumber
- CFG_MEM_INIT_PSTATE, //MemoryInitPstate
- CFG_C1E_MODE, //C1eMode
- CFG_C1E_OPDATA, //C1ePlatformData
- CFG_C1E_OPDATA1, //C1ePlatformData1
- CFG_C1E_OPDATA2, //C1ePlatformData2
- CFG_CSTATE_MODE, //CStateMode
- CFG_CSTATE_OPDATA, //CStatePlatformData
- CFG_CSTATE_IO_BASE_ADDRESS, //CStateIoBaseAddress
- CFG_CPB_MODE, //CpbMode
- CFG_CORE_LEVELING_MODE, //CoreLevelingCofig
- {
- CFG_PLATFORM_CONTROL_FLOW_MODE, // The platform's control flow mode.
- CFG_USE_HT_ASSIST, // CfgUseHtAssist
- CFG_USE_ATM_MODE, // CfgUseAtmMode
- CFG_USE_32_BYTE_REFRESH, // Display Refresh uses 32 byte packets.
- CFG_USE_VARIABLE_MCT_ISOC_PRIORITY, // The Memory controller will be set to Variable Isoc Priority.
- CFG_PLATFORM_POWER_POLICY_MODE // The platform's power policy mode.
- },
- (CPU_HT_DEEMPHASIS_LEVEL *)CFG_PLATFORM_DEEMPHASIS_LIST, // Deemphasis settings
- CFG_AMD_PLATFORM_TYPE, //AmdPlatformType
- CFG_AMD_PSTATE_CAP_VALUE, // Amd pstate ceiling enabling deck
-
- CFG_MEMORY_BUS_FREQUENCY_LIMIT, // CfgMemoryBusFrequencyLimit
- CFG_MEMORY_MODE_UNGANGED, // CfgMemoryModeUnganged
- CFG_MEMORY_QUAD_RANK_CAPABLE, // CfgMemoryQuadRankCapable
- CFG_MEMORY_QUADRANK_TYPE, // CfgMemoryQuadrankType
- CFG_MEMORY_RDIMM_CAPABLE, // CfgMemoryRDimmCapable
- CFG_MEMORY_LRDIMM_CAPABLE, // CfgMemoryLRDimmCapable
- CFG_MEMORY_UDIMM_CAPABLE, // CfgMemoryUDimmCapable
- CFG_MEMORY_SODIMM_CAPABLE, // CfgMemorySodimmCapable
- CFG_MEMORY_ENABLE_BANK_INTERLEAVING, // CfgMemoryEnableBankInterleaving
- CFG_MEMORY_ENABLE_NODE_INTERLEAVING, // CfgMemoryEnableNodeInterleaving
- CFG_MEMORY_CHANNEL_INTERLEAVING, // CfgMemoryChannelInterleaving
- CFG_MEMORY_POWER_DOWN, // CfgMemoryPowerDown
- CFG_POWER_DOWN_MODE, // CfgPowerDownMode
- CFG_ONLINE_SPARE, // CfgOnlineSpare
- CFG_MEMORY_PARITY_ENABLE, // CfgMemoryParityEnable
- CFG_BANK_SWIZZLE, // CfgBankSwizzle
- CFG_TIMING_MODE_SELECT, // CfgTimingModeSelect
- CFG_MEMORY_CLOCK_SELECT, // CfgMemoryClockSelect
- CFG_DQS_TRAINING_CONTROL, // CfgDqsTrainingControl
- CFG_IGNORE_SPD_CHECKSUM, // CfgIgnoreSpdChecksum
- CFG_USE_BURST_MODE, // CfgUseBurstMode
- CFG_MEMORY_ALL_CLOCKS_ON, // CfgMemoryAllClocksOn
- CFG_ENABLE_ECC_FEATURE, // CfgEnableEccFeature
- CFG_ECC_REDIRECTION, // CfgEccRedirection
- CFG_SCRUB_DRAM_RATE, // CfgScrubDramRate
- CFG_SCRUB_L2_RATE, // CfgScrubL2Rate
- CFG_SCRUB_L3_RATE, // CfgScrubL3Rate
- CFG_SCRUB_IC_RATE, // CfgScrubIcRate
- CFG_SCRUB_DC_RATE, // CfgScrubDcRate
- CFG_ECC_SYNC_FLOOD, // CfgEccSyncFlood
- CFG_ECC_SYMBOL_SIZE, // CfgEccSymbolSize
- CFG_HEAP_DRAM_ADDRESS, // CfgHeapDramAddress
- CFG_1GB_ALIGN, // CfgNodeMem1GBAlign
- CFG_S3_LATE_RESTORE, // CfgS3LateRestore
- CFG_ACPI_PSTATE_PSD_INDPX, // CfgAcpiPstateIndependent
- (AP_MTRR_SETTINGS *) CFG_AP_MTRR_SETTINGS_LIST, // CfgApMtrrSettingsList
- CFG_UMA_MODE, // CfgUmaMode
- CFG_UMA_SIZE, // CfgUmaSize
- CFG_UMA_ABOVE4G, // CfgUmaAbove4G
- CFG_UMA_ALIGNMENT, // CfgUmaAlignment
- CFG_PROCESSOR_SCOPE_IN_SB, // CfgProcessorScopeInSb
- CFG_PROCESSOR_SCOPE_NAME0, // CfgProcessorScopeName0
- CFG_PROCESSOR_SCOPE_NAME1, // CfgProcessorScopeName1
- CFG_GNB_HD_AUDIO, // CfgGnbHdAudio
- CFG_ABM_SUPPORT, // CfgAbmSupport
- CFG_DYNAMIC_REFRESH_RATE, // CfgDynamicRefreshRate
- CFG_LCD_BACK_LIGHT_CONTROL, // CfgLcdBackLightControl
- CFG_GNB_STEREO_3D_PINOUT, // CfgGnb3dStereoPinIndex
- CFG_TEMP_PCIE_MMIO_BASE_ADDRESS, // CfgTempPcieMmioBaseAddress
- CFG_GNB_IGPU_SSID, // CfgGnbIGPUSSID
- CFG_GNB_HDAUDIO_SSID, // CfgGnbHDAudioSSID
- CFG_GNB_PCIE_SSID, // CfgGnbPcieSSID
- CFG_GFX_LVDS_SPREAD_SPECTRUM, // CfgLvdsSpreadSpectrum
- CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE, // CfgLvdsSpreadSpectrumRate
-
- 0, //reserved...
-};
-
-CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] =
-{
- #if AGESA_ENTRY_INIT_RESET == TRUE
- { AMD_INIT_RESET,
- sizeof (AMD_RESET_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitResetConstructor,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_INIT_RESET_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_RECOVERY == TRUE
- { AMD_INIT_RECOVERY,
- sizeof (AMD_RECOVERY_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_INIT_POST_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_EARLY == TRUE
- { AMD_INIT_EARLY,
- sizeof (AMD_EARLY_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitEarlyInitializer,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_INIT_EARLY_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_ENV == TRUE
- { AMD_INIT_ENV,
- sizeof (AMD_ENV_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitEnvInitializer,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_INIT_ENV_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_LATE == TRUE
- { AMD_INIT_LATE,
- sizeof (AMD_LATE_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitLateInitializer,
- (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor,
- AMD_INIT_LATE_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_MID == TRUE
- { AMD_INIT_MID,
- sizeof (AMD_MID_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitMidInitializer,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_INIT_MID_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_POST == TRUE
- { AMD_INIT_POST,
- sizeof (AMD_POST_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitPostInitializer,
- (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor,
- AMD_INIT_POST_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_RESUME == TRUE
- { AMD_INIT_RESUME,
- sizeof (AMD_RESUME_PARAMS),
- (PF_AGESA_FUNCTION) AmdInitResumeInitializer,
- (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor,
- AMD_INIT_RESUME_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
- { AMD_S3LATE_RESTORE,
- sizeof (AMD_S3LATE_PARAMS),
- (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_S3_LATE_RESTORE_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_INIT_S3SAVE == TRUE
- { AMD_S3_SAVE,
- sizeof (AMD_S3SAVE_PARAMS),
- (PF_AGESA_FUNCTION) AmdS3SaveInitializer,
- (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor,
- AMD_S3_SAVE_HANDLE
- },
- #endif
-
- #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
- { AMD_LATE_RUN_AP_TASK,
- sizeof (AP_EXE_PARAMS),
- (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer,
- (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
- AMD_LATE_RUN_AP_TASK_HANDLE
- },
- #endif
- { 0, NULL }
-};
-
-CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0])));
-
-CONST DISPATCH_TABLE ROMDATA DispatchTable[] =
-{
- { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct },
- { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct },
-
- #if AGESA_ENTRY_INIT_RESET == TRUE
- { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset },
- #endif
-
- #if AGESA_ENTRY_INIT_RECOVERY == TRUE
- { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery },
- #endif
-
- #if AGESA_ENTRY_INIT_EARLY == TRUE
- { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly },
- #endif
-
- #if AGESA_ENTRY_INIT_POST == TRUE
- { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost },
- #endif
-
- #if AGESA_ENTRY_INIT_ENV == TRUE
- { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv },
- #endif
-
- #if AGESA_ENTRY_INIT_MID == TRUE
- { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid },
- #endif
-
- #if AGESA_ENTRY_INIT_LATE == TRUE
- { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate },
- #endif
-
- #if AGESA_ENTRY_INIT_S3SAVE == TRUE
- { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save },
- #endif
-
- #if AGESA_ENTRY_INIT_RESUME == TRUE
- { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume },
- #endif
-
- #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
- { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore },
- #endif
-
- #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
- { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId },
- { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress },
- { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore },
- { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog },
- { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm },
- { AMD_GET_EXECACHE_SIZE, (IMAGE_ENTRY)AmdGetAvailableExeCacheSize },
- #endif
-
- #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
- { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask },
- #endif
- { 0, NULL }
-};
-
-CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] =
-{
- IDS_LATE_RUN_AP_TASK
- // Get DMI info
- CPU_DMI_AP_GET_TYPE4_TYPE7
- // Probe filter enable
- HT_ASSIST_AP_DISABLE_CACHE
- HT_ASSIST_AP_ENABLE_CACHE
-
- { 0, NULL }
-};
-
-#if AGESA_ENTRY_INIT_RESET == TRUE
- #if IDSOPT_IDS_ENABLED == TRUE
- #if IDSOPT_TRACING_ENABLED == TRUE
- #define MAKE_DBG_STR(x, y) MAKE_AS_A_STRING(x : y)
- CONST CHAR8 *BldOptDebugOutput[] = {
- #if IDS_TRACE_SHOW_BLD_OPT_CFG == TRUE
- //Build Option Area
- MAKE_DBG_STR (\nOptUDIMM, OPTION_UDIMMS)
- MAKE_DBG_STR (\nOptRDIMM, OPTION_RDIMMS)
- MAKE_DBG_STR (\nOptLRDIMM, OPTION_LRDIMMS)
- MAKE_DBG_STR (\nOptECC, OPTION_ECC)
- MAKE_DBG_STR (\nOptCsIntlv, OPTION_BANK_INTERLEAVE)
- MAKE_DBG_STR (\nOptDctIntlv, OPTION_DCT_INTERLEAVE)
- MAKE_DBG_STR (\nOptNodeIntlv, OPTION_NODE_INTERLEAVE)
- //MAKE_DBG_STR (\nOptParallelTraining, OPTION_PARALLEL_TRAINING)
- MAKE_DBG_STR (\nOptOnlineSpare, OPTION_ONLINE_SPARE)
- MAKE_DBG_STR (\nOptAddr2CsTranslator, OPTION_ADDR_TO_CS_TRANSLATOR)
- MAKE_DBG_STR (\nOptMemRestore, OPTION_MEM_RESTORE)
- MAKE_DBG_STR (\nOptMultiSocket, OPTION_MULTISOCKET)
- MAKE_DBG_STR (\nOptPstates, OPTION_ACPI_PSTATES)
- MAKE_DBG_STR (\nOptSRAT, OPTION_SRAT)
- MAKE_DBG_STR (\nOptSLIT, OPTION_SLIT)
- MAKE_DBG_STR (\nOptWHEA, OPTION_WHEA)
- MAKE_DBG_STR (\nOptDMI, OPTION_DMI)
- MAKE_DBG_STR (\nOptEarlySamples, OPTION_EARLY_SAMPLES),
-
- //Build Configuration Area
- // CoreVrm
- MAKE_DBG_STR (\nVrmCurrentLimit , CFG_VRM_CURRENT_LIMIT)
- MAKE_DBG_STR (\nVrmLowPowerThreshold , CFG_VRM_LOW_POWER_THRESHOLD)
- MAKE_DBG_STR (\nVrmSlewRate , CFG_VRM_SLEW_RATE)
- MAKE_DBG_STR (\nVrmAdditionalDelay , CFG_VRM_ADDITIONAL_DELAY)
- MAKE_DBG_STR (\nVrmHiSpeedEnable , CFG_VRM_HIGH_SPEED_ENABLE)
- MAKE_DBG_STR (\nVrmInrushCurrentLimit, CFG_VRM_INRUSH_CURRENT_LIMIT)
- // NbVrm
- MAKE_DBG_STR (\nNbVrmCurrentLimit , CFG_VRM_NB_CURRENT_LIMIT)
- MAKE_DBG_STR (\nNbVrmLowPowerThreshold , CFG_VRM_NB_LOW_POWER_THRESHOLD)
- MAKE_DBG_STR (\nNbVrmSlewRate , CFG_VRM_NB_SLEW_RATE)
- MAKE_DBG_STR (\nNbVrmAdditionalDelay , CFG_VRM_NB_ADDITIONAL_DELAY)
- MAKE_DBG_STR (\nNbVrmHiSpeedEnable , CFG_VRM_NB_HIGH_SPEED_ENABLE)
- MAKE_DBG_STR (\nNbVrmInrushCurrentLimit, CFG_VRM_NB_INRUSH_CURRENT_LIMIT),
-
- MAKE_DBG_STR (\nNumIoApics , CFG_PLAT_NUM_IO_APICS)
- MAKE_DBG_STR (\nMemInitPstate , CFG_MEM_INIT_PSTATE)
- MAKE_DBG_STR (\nC1eMode , CFG_C1E_MODE)
- MAKE_DBG_STR (\nC1eOpData , CFG_C1E_OPDATA)
- MAKE_DBG_STR (\nC1eOpdata1 , CFG_C1E_OPDATA1)
- MAKE_DBG_STR (\nC1eOpdata2 , CFG_C1E_OPDATA2)
- MAKE_DBG_STR (\nCStateMode , CFG_CSTATE_MODE)
- MAKE_DBG_STR (\nCStateOpData , CFG_CSTATE_OPDATA)
- MAKE_DBG_STR (\nCStateIoBaseAddr , CFG_CSTATE_IO_BASE_ADDRESS)
- MAKE_DBG_STR (\nCpbMode , CFG_CPB_MODE)
- MAKE_DBG_STR (\nCoreLevelingMode , CFG_CORE_LEVELING_MODE),
-
- MAKE_DBG_STR (\nControlFlowMode , CFG_PLATFORM_CONTROL_FLOW_MODE)
- MAKE_DBG_STR (\nUseHtAssist , CFG_USE_HT_ASSIST)
- MAKE_DBG_STR (\nUseAtmMode , CFG_USE_ATM_MODE)
- MAKE_DBG_STR (\nUse32ByteRefresh , CFG_USE_32_BYTE_REFRESH)
- MAKE_DBG_STR (\nUseVarMctIsocPriority , CFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
- MAKE_DBG_STR (\nPowerPolicy , CFG_PLATFORM_POWER_POLICY_MOD)
-
- MAKE_DBG_STR (\nDeemphasisList , CFG_PLATFORM_DEEMPHASIS_LIST)
-
- MAKE_DBG_STR (\nPciMmioAddr , CFG_PCI_MMIO_BASE)
- MAKE_DBG_STR (\nPciMmioSize , CFG_PCI_MMIO_SIZE)
- MAKE_DBG_STR (\nPlatformType , CFG_AMD_PLATFORM_TYPE)
- MAKE_DBG_STR (\nPstateCapValue , CFG_AMD_PSTATE_CAP_VALUE),
-
- MAKE_DBG_STR (\nMemBusFreqLimit , CFG_MEMORY_BUS_FREQUENCY_LIMIT)
- MAKE_DBG_STR (\nTimingModeSelect , CFG_TIMING_MODE_SELECT)
- MAKE_DBG_STR (\nMemoryClockSelect , CFG_MEMORY_CLOCK_SELECT)
-
- MAKE_DBG_STR (\nMemUnganged , CFG_MEMORY_MODE_UNGANGED)
- MAKE_DBG_STR (\nQRCap , CFG_MEMORY_QUAD_RANK_CAPABLE)
- MAKE_DBG_STR (\nQRType , CFG_MEMORY_QUADRANK_TYPE)
- MAKE_DBG_STR (\nRDimmCap , CFG_MEMORY_RDIMM_CAPABLE)
- MAKE_DBG_STR (\nLRDimmCap , CFG_MEMORY_LRDIMM_CAPABLE)
- MAKE_DBG_STR (\nUDimmCap , CFG_MEMORY_UDIMM_CAPABLE)
- MAKE_DBG_STR (\nSODimmCap , CFG_MEMORY_SODIMM_CAPABLE)
- MAKE_DBG_STR (\nDqsTrainingControl , CFG_DQS_TRAINING_CONTROL)
- MAKE_DBG_STR (\nIgnoreSpdChecksum , CFG_IGNORE_SPD_CHECKSUM)
- MAKE_DBG_STR (\nUseBurstMode , CFG_USE_BURST_MODE)
- MAKE_DBG_STR (\nAllMemClkOn , CFG_MEMORY_ALL_CLOCKS_ON),
-
- MAKE_DBG_STR (\nPowerDownEn , CFG_MEMORY_POWER_DOWN)
- MAKE_DBG_STR (\nPowerDownMode , CFG_POWER_DOWN_MODE)
- MAKE_DBG_STR (\nOnlineSpare , CFG_ONLINE_SPARE)
- MAKE_DBG_STR (\nAddrParityEn , CFG_MEMORY_PARITY_ENABLE)
- MAKE_DBG_STR (\nBankSwizzle , CFG_BANK_SWIZZLE)
- MAKE_DBG_STR (\nCsIntlvEn , CFG_MEMORY_ENABLE_BANK_INTERLEAVING)
- MAKE_DBG_STR (\nNodeIntlvEn , CFG_MEMORY_ENABLE_NODE_INTERLEAVING)
- MAKE_DBG_STR (\nDctIntlvEn , CFG_MEMORY_CHANNEL_INTERLEAVING),
-
- MAKE_DBG_STR (\nUmaMode , CFG_UMA_MODE)
- MAKE_DBG_STR (\nUmaSize , CFG_UMA_SIZE)
- MAKE_DBG_STR (\nUmaAbove4G , CFG_UMA_ABOVE4G)
- MAKE_DBG_STR (\nUmaAlignment , CFG_UMA_ALIGNMENT)
-
- MAKE_DBG_STR (\nEccEn , CFG_ENABLE_ECC_FEATURE)
- MAKE_DBG_STR (\nEccRedirect , CFG_ECC_REDIRECTION)
- MAKE_DBG_STR (\nScrubDramRate , CFG_SCRUB_DRAM_RATE)
- MAKE_DBG_STR (\nScrubL2Rate , CFG_SCRUB_L2_RATE)
- MAKE_DBG_STR (\nScrubL3Rate , CFG_SCRUB_L3_RATE)
- MAKE_DBG_STR (\nScrubIcRate , CFG_SCRUB_IC_RATE)
- MAKE_DBG_STR (\nScrubDcRate , CFG_SCRUB_DC_RATE)
- MAKE_DBG_STR (\nEccSyncFlood , CFG_ECC_SYNC_FLOOD)
- MAKE_DBG_STR (\nEccSymbolSize , CFG_ECC_SYMBOL_SIZE)
- MAKE_DBG_STR (\nHeapDramAddress , CFG_HEAP_DRAM_ADDRESS)
- MAKE_DBG_STR (\nNodeMem1GBAlign , CFG_1GB_ALIGN),
-
- MAKE_DBG_STR (\nS3LateRestore , CFG_S3_LATE_RESTORE)
- MAKE_DBG_STR (\nAcpiPstateIndependent , CFG_ACPI_PSTATE_PSD_INDPX)
-
- MAKE_DBG_STR (\nApMtrrSettingsList , CFG_AP_MTRR_SETTINGS_LIST)
-
- MAKE_DBG_STR (\nProcessorScopeInSb , CFG_PROCESSOR_SCOPE_IN_SB)
- MAKE_DBG_STR (\nProcessorScopeName0 , CFG_PROCESSOR_SCOPE_NAME0)
- MAKE_DBG_STR (\nProcessorScopeName1 , CFG_PROCESSOR_SCOPE_NAME1)
- MAKE_DBG_STR (\nGnbHdAudio , CFG_GNB_HD_AUDIO)
- MAKE_DBG_STR (\nAbmSupport , CFG_ABM_SUPPORT)
- MAKE_DBG_STR (\nDynamicRefreshRate , CFG_DYNAMIC_REFRESH_RATE)
- MAKE_DBG_STR (\nLcdBackLightControl , CFG_LCD_BACK_LIGHT_CONTROL)
- MAKE_DBG_STR (\nGnb3dStereoPinIndex , CFG_GNB_STEREO_3D_PINOUT)
- MAKE_DBG_STR (\nTempPcieMmioBaseAddress, CFG_TEMP_PCIE_MMIO_BASE_ADDRESS),
- MAKE_DBG_STR (\nCfgGnbIGPUSSID , CFG_GNB_IGPU_SSID),
- MAKE_DBG_STR (\nCfgGnbHDAudioSSID , CFG_GNB_HDAUDIO_SSID),
- MAKE_DBG_STR (\nCfgGnbPcieSSID , CFG_GNB_PCIE_SSID),
-
- MAKE_DBG_STR (\nCfgLvdsSpreadSpectrum , CFG_GFX_LVDS_SPREAD_SPECTRUM),
- MAKE_DBG_STR (\nCfgLvdsSpreadSpectrumRate , CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE),
- #endif
- NULL
- };
- #endif
- #endif
-#endif
diff --git a/src/vendorcode/amd/agesa/Include/PlatformMemoryConfiguration.h b/src/vendorcode/amd/agesa/Include/PlatformMemoryConfiguration.h
deleted file mode 100644
index 85c14d9..0000000
--- a/src/vendorcode/amd/agesa/Include/PlatformMemoryConfiguration.h
+++ /dev/null
@@ -1,314 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Platform Specific Memory Configuration
- *
- * Contains Definitions and Macros for control of AGESA Memory code on a per platform basis
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: OPTION
- * @e \$Revision: 35415 $ @e \$Date: 2010-07-22 06:10:32 +0800 (Thu, 22 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _PLATFORM_MEMORY_CONFIGURATION_H_
-#define _PLATFORM_MEMORY_CONFIGURATION_H_
-
-/*----------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *----------------------------------------------------------------------------------------
- */
-#ifndef PSO_ENTRY
- #define PSO_ENTRY UINT8
-#endif
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *----------------------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------------------
- * PLATFORM SPECIFIC MEMORY DEFINITIONS
- *----------------------------------------------------------------------------------------
- */
-///
-/// Memory Speed and DIMM Population Masks
-///
-///< DDR Speed Masks
-///< Specifies the DDR Speed on a memory channel
-///
-#define ANY_SPEED 0xFFFFFFFF
-#define DDR400 ((UINT32) 1 << (DDR400_FREQUENCY / 66))
-#define DDR533 ((UINT32) 1 << (DDR533_FREQUENCY / 66))
-#define DDR667 ((UINT32) 1 << (DDR667_FREQUENCY / 66))
-#define DDR800 ((UINT32) 1 << (DDR800_FREQUENCY / 66))
-#define DDR1066 ((UINT32) 1 << (DDR1066_FREQUENCY / 66))
-#define DDR1333 ((UINT32) 1 << (DDR1333_FREQUENCY / 66))
-#define DDR1600 ((UINT32) 1 << (DDR1600_FREQUENCY / 66))
-#define DDR1866 ((UINT32) 1 << (DDR1866_FREQUENCY / 66))
-///
-///< DIMM POPULATION MASKS
-///< Specifies the DIMM Population on a channel (can be added together to specify configuration).
-///< ex. SR_DIMM0 + SR_DIMM1 : Single Rank Dimm in slot 0 AND Slot 1
-///< SR_DIMM0 + DR_DIMM0 + SR_DIMM1 +DR_DIMM1 : Single OR Dual rank in Slot 0 AND Single OR Dual rank in Slot 1
-///
-#define ANY_ 0xFF ///< Any dimm configuration the current channel
-#define SR_DIMM0 0x0001 ///< Single rank dimm in slot 0 on the current channel
-#define SR_DIMM1 0x0010 ///< Single rank dimm in slot 1 on the current channel
-#define SR_DIMM2 0x0100 ///< Single rank dimm in slot 2 on the current channel
-#define SR_DIMM3 0x1000 ///< Single rank dimm in slot 3 on the current channel
-#define DR_DIMM0 0x0002 ///< Dual rank dimm in slot 0 on the current channel
-#define DR_DIMM1 0x0020 ///< Dual rank dimm in slot 1 on the current channel
-#define DR_DIMM2 0x0200 ///< Dual rank dimm in slot 2 on the current channel
-#define DR_DIMM3 0x2000 ///< Dual rank dimm in slot 3 on the current channel
-#define QR_DIMM0 0x0004 ///< Quad rank dimm in slot 0 on the current channel
-#define QR_DIMM1 0x0040 ///< Quad rank dimm in slot 1 on the current channel
-#define QR_DIMM2 0x0400 ///< Quad rank dimm in slot 2 on the current channel
-#define QR_DIMM3 0x4000 ///< Quad rank dimm in slot 3 on the current channel
-#define ANY_DIMM0 0x000F ///< Any Dimm combination in slot 0 on the current channel
-#define ANY_DIMM1 0x00F0 ///< Any Dimm combination in slot 1 on the current channel
-#define ANY_DIMM2 0x0F00 ///< Any Dimm combination in slot 2 on the current channel
-#define ANY_DIMM3 0xF000 ///< Any Dimm combination in slot 3 on the current channel
-///
-///< Number of Dimms on the current channel
-///< This is a mask used to indicate the number of dimms in a channel
-///< They can be added to indicate multiple conditions (i.e 1 OR 2 Dimms)
-///
-#define ANY_NUM 0xFF ///< Any number of Dimms
-#define NO_DIMM 0x00 ///< No Dimms present
-#define ONE_DIMM 0x01 ///< One dimm Poulated on the current channel
-#define TWO_DIMM 0x02 ///< Two dimms Poulated on the current channel
-#define THREE_DIMM 0x04 ///< Three dimms Poulated on the current channel
-#define FOUR_DIMM 0x08 ///< Four dimms Poulated on the current channel
-
-/*----------------------------------------------------------------------------------------
- *
- * Platform Specific Override Definitions for Socket, Channel and Dimm
- * This indicates where a platform override will be applied.
- *
- *----------------------------------------------------------------------------------------
- */
-///
-///< SOCKET MASKS
-///< Indicates associated processor sockets to apply override settings
-///
-#define ANY_SOCKET 0xFF ///< Apply to all sockets
-#define SOCKET0 0x01 ///< Apply to socket 0
-#define SOCKET1 0x02 ///< Apply to socket 1
-#define SOCKET2 0x04 ///< Apply to socket 2
-#define SOCKET3 0x08 ///< Apply to socket 3
-#define SOCKET4 0x10 ///< Apply to socket 4
-#define SOCKET5 0x20 ///< Apply to socket 5
-#define SOCKET6 0x40 ///< Apply to socket 6
-#define SOCKET7 0x80 ///< Apply to socket 7
-///
-///< CHANNEL MASKS
-///< Indicates Memory channels where override should be applied
-///
-#define ANY_CHANNEL 0xFF ///< Apply to all Memory channels
-#define CHANNEL_A 0x01 ///< Apply to Channel A
-#define CHANNEL_B 0x02 ///< Apply to Channel B
-#define CHANNEL_C 0x04 ///< Apply to Channel C
-#define CHANNEL_D 0x08 ///< Apply to Channel D
-///
-/// DIMM MASKS
-/// Indicates Dimm Slots where override should be applied
-///
-#define ALL_DIMMS 0xFF ///< Apply to all dimm slots
-#define DIMM0 0x01 ///< Apply to Dimm Slot 0
-#define DIMM1 0x02 ///< Apply to Dimm Slot 1
-#define DIMM2 0x04 ///< Apply to Dimm Slot 2
-#define DIMM3 0x08 ///< Apply to Dimm Slot 3
-///
-/// REGISTER ACCESS MASKS
-/// Not supported as an at this time
-///
-#define ACCESS_NB0 0x0
-#define ACCESS_NB1 0x1
-#define ACCESS_NB2 0x2
-#define ACCESS_NB3 0x3
-#define ACCESS_NB4 0x4
-#define ACCESS_PHY 0x5
-#define ACCESS_DCT_XT 0x6
-
-/*----------------------------------------------------------------------------------------
- *
- * Platform Specific Overriding Table Definitions
- *
- *----------------------------------------------------------------------------------------
- */
-
-#define PSO_END 0 ///< Table End
-#define PSO_CKE_TRI 1 ///< CKE Tristate Map
-#define PSO_ODT_TRI 2 ///< ODT Tristate Map
-#define PSO_CS_TRI 3 ///< CS Tristate Map
-#define PSO_MAX_DIMMS 4 ///< Max Dimms per channel
-#define PSO_CLK_SPEED 5 ///< Clock Speed
-#define PSO_DIMM_TYPE 6 ///< Dimm Type
-#define PSO_MEMCLK_DIS 7 ///< MEMCLK Disable Map
-#define PSO_MAX_CHNLS 8 ///< Max Channels per Socket
-#define PSO_BUS_SPEED 9 ///< Max Memory Bus Speed
-#define PSO_MAX_CHIPSELS 10 ///< Max Chipsel per Channel
-#define PSO_MEM_TECH 11 ///< Channel Memory Type
-#define PSO_WL_SEED 12 ///< DDR3 Write Levelization Seed delay
-#define PSO_RXEN_SEED 13 ///< Hardwared based RxEn seed
-#define PSO_NO_LRDIMM_CS67_ROUTING 14 ///< CS6 and CS7 are not Routed to all Memoy slots on a channel for LRDIMMs
-
-/*----------------------------------
- * CONDITIONAL PSO SPECIFIC ENTRIES
- *---------------------------------*/
-// Condition Types
-#define CONDITIONAL_PSO_MIN 100 ///< Start of Conditional Entry Types
-#define PSO_CONDITION_AND 100 ///< And Block - Start of Conditional block
-#define PSO_CONDITION_LOC 101 ///< Location - Specify Socket, Channel, Dimms to be affected
-#define PSO_CONDITION_SPD 102 ///< SPD - Specify a specific SPD value on a Dimm on the channel
-#define PSO_CONDITION_REG 103 // Reserved
-#define PSO_CONDITION_MAX 103 ///< End Of Condition Entry Types
-// Action Types
-#define PSO_ACTION_MIN 120 ///< Start of Action Entry Types
-#define PSO_ACTION_ODT 120 ///< ODT values to override
-#define PSO_ACTION_ADDRTMG 121 ///< Address/Timing values to override
-#define PSO_ACTION_ODCCONTROL 122 ///< ODC Control values to override
-#define PSO_ACTION_SLEWRATE 123 ///< Slew Rate value to override
-#define PSO_ACTION_REG 124 // Reserved
-#define PSO_ACTION_SPEEDLIMIT 125 ///< Memory Bus speed Limit based on configuration
-#define PSO_ACTION_MAX 125 ///< End of Action Entry Types
-#define CONDITIONAL_PSO_MAX 139 ///< End of Conditional Entry Types
-
-/*----------------------------------------------------------------------------------------
- * CONDITIONAL OVERRIDE TABLE MACROS
- *----------------------------------------------------------------------------------------
- */
-#define MEMCLK_DIS_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \
- PSO_MEMCLK_DIS, 10, SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map
-
-#define CKE_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map) \
- PSO_CKE_TRI, 4, SocketID, ChannelID, Bit0Map, Bit1Map
-
-#define ODT_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map) \
- PSO_ODT_TRI, 6, SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map
-
-#define CS_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \
- PSO_CS_TRI, 10, SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map
-
-#define NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) \
- PSO_MAX_DIMMS, 3, SocketID, ChannelID, NumberOfDimmSlotsPerChannel
-
-#define NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) \
- PSO_MAX_CHIPSELS, 3, SocketID, ChannelID, NumberOfChipSelectsPerChannel
-
-#define NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) \
- PSO_MAX_CHNLS, 3, SocketID, ANY_CHANNEL, NumberOfChannelsPerSocket
-
-#define OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, TimingMode, BusSpeed) \
- PSO_BUS_SPEED, 10, SocketID, ChannelID, TimingMode, (TimingMode >> 8), (TimingMode >> 16), (TimingMode >> 24), \
- BusSpeed, (BusSpeed >> 8), (BusSpeed >> 16), (BusSpeed >> 24)
-
-#define DRAM_TECHNOLOGY(SocketID, MemTechType) \
- PSO_MEM_TECH, 6, SocketID, ANY_CHANNEL, MemTechType, (MemTechType >> 8), (MemTechType >> 16), (MemTechType >> 24)
-
-#define WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
- Byte6Seed, Byte7Seed, ByteEccSeed) \
- PSO_WL_SEED, 11, SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
- Byte6Seed, Byte7Seed, ByteEccSeed
-
-#define HW_RXEN_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
- Byte6Seed, Byte7Seed, ByteEccSeed) \
- PSO_RXEN_SEED, 20, SocketID, ChannelID, Byte0Seed, (Byte0Seed >> 8), Byte1Seed, (Byte1Seed >> 8), Byte2Seed, (Byte2Seed >> 8), \
- Byte3Seed, (Byte3Seed >> 8), Byte4Seed, (Byte4Seed >> 8), Byte5Seed, (Byte5Seed >> 8), Byte6Seed, (Byte6Seed >> 8), \
- Byte7Seed, (Byte7Seed >> 8), ByteEccSeed, (ByteEccSeed >> 8)
-
-#define NO_LRDIMM_CS67_ROUTING(SocketID, ChannelID) \
- PSO_NO_LRDIMM_CS67_ROUTING, 3, SocketID, ChannelID, TRUE
-
-
-/*----------------------------------------------------------------------------------------
- * CONDITIONAL OVERRIDE TABLE MACROS
- *----------------------------------------------------------------------------------------
- */
-#define CONDITION_AND \
- PSO_CONDITION_AND, 0
-
-#define COND_LOC(SocketMsk, ChannelMsk, DimmMsk) \
- PSO_CONDITION_LOC, 3, SocketMsk, ChannelMsk, DimmMsk
-
-#define COND_SPD(Byte, Mask, Value) \
- PSO_CONDITION_SPD, 3, Byte, Mask, Value
-
-#define COND_REG(Access, Offset, Mask, Value) \
- PSO_CONDITION_REG, 11, Access, (Offset & 0x0FF), (Offset >> 8), \
- ((Mask) & 0x0FF), (((Mask) >> 8) & 0x0FF), (((Mask) >> 16) & 0x0FF), (((Mask) >> 24) & 0x0FF), \
- ((Value) & 0x0FF), (((Value) >> 8) & 0x0FF), (((Value) >> 16) & 0x0FF), (((Value) >> 24) & 0x0FF)
-
-#define ACTION_ODT(Frequency, Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt) \
- PSO_ACTION_ODT, 9, \
- ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), ((Frequency >> 24)& 0x0FF), \
- Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt
-
-#define ACTION_ADDRTMG(Frequency, DimmConfig, AddrTmg) \
- PSO_ACTION_ADDRTMG, 10, \
- ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
- ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
- (AddrTmg & 0x0FF), ((AddrTmg >> 8)& 0x0FF), ((AddrTmg >> 16)& 0x0FF), ((AddrTmg >> 24)& 0x0FF)
-
-#define ACTION_ODCCTRL(Frequency, DimmConfig, OdcCtrl) \
- PSO_ACTION_ODCCONTROL, 10, \
- ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
- ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
- (OdcCtrl & 0x0FF), ((OdcCtrl >> 8)& 0x0FF), ((OdcCtrl >> 16)& 0x0FF), ((OdcCtrl >> 24)& 0x0FF)
-
-#define ACTION_SLEWRATE(Frequency, DimmConfig, SlewRate) \
- PSO_ACTION_SLEWRATE, 10, \
- ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
- ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
- (SlewRate & 0x0FF), ((SlewRate >> 8)& 0x0FF), ((SlewRate >> 16)& 0x0FF), ((SlewRate >> 24)& 0x0FF)
-
-#define ACTION_SPEEDLIMIT(DimmConfig, Dimms, SpeedLimit15, SpeedLimit135, SpeedLimit125) \
- PSO_ACTION_SPEEDLIMIT, 9, \
- ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), Dimms, \
- (SpeedLimit15 & 0x0FF), ((SpeedLimit15 >> 8)& 0x0FF), \
- (SpeedLimit135 & 0x0FF), ((SpeedLimit135 >> 8)& 0x0FF), \
- (SpeedLimit125 & 0x0FF), ((SpeedLimit125 >> 8)& 0x0FF)
-
-/*----------------------------------------------------------------------------------------
- * END OF CONDITIONAL OVERRIDE TABLE MACROS
- *----------------------------------------------------------------------------------------
- */
-
-#endif // _PLATFORM_MEMORY_CONFIGURATION_H_
diff --git a/src/vendorcode/amd/agesa/Include/SabineInstall.h b/src/vendorcode/amd/agesa/Include/SabineInstall.h
deleted file mode 100644
index 99838e3..0000000
--- a/src/vendorcode/amd/agesa/Include/SabineInstall.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build options for a Sabine platform solution
- *
- * This file generates the defaults tables for the "Sabine" platform solution
- * set of processors. The documented build options are imported from a user
- * controlled file for processing.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Core
- * @e \$Revision: 37651 $ @e \$Date: 2010-09-09 07:05:06 +0800 (Thu, 09 Sep 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "CreateStruct.h"
-#include "cpuFeatures.h"
-#include "Table.h"
-#include "CommonReturns.h"
-#include "cpuEarlyInit.h"
-#include "cpuLateInit.h"
-#include "GnbInterface.h"
-
-/*****************************************************************************
- * Define the RELEASE VERSION string
- *
- * The Release Version string should identify the next planned release.
- * When a branch is made in preparation for a release, the release manager
- * should change/confirm that the branch version of this file contains the
- * string matching the desired version for the release. The trunk version of
- * the file should always contain a trailing 'X'. This will make sure that a
- * development build from trunk will not be confused for a released version.
- * The release manager will need to remove the trailing 'X' and update the
- * version string as appropriate for the release. The trunk copy of this file
- * should also be updated/incremented for the next expected version, + trailing 'X'
- ****************************************************************************/
- // This is the delivery package title, "LlanoPI "
- // This string MUST be exactly 8 characters long
-#define AGESA_PACKAGE_STRING {'L', 'l', 'a', 'n', 'o', 'P', 'I', ' '}
-
- // This is the release version number of the AGESA component
- // This string MUST be exactly 12 characters long
-#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '6', '.', '0', 'X', ' ', ' ', ' '}
-
-
-// The Sabine solution is defined to be family 0x12 in the FS1 and FP1 sockets.
-#define INSTALL_FS1_SOCKET_SUPPORT TRUE
-#define INSTALL_FP1_SOCKET_SUPPORT TRUE
-#define INSTALL_FAMILY_12_SUPPORT TRUE
-
-#ifdef BLDOPT_REMOVE_FS1_SOCKET_SUPPORT
- #if BLDOPT_REMOVE_FS1_SOCKET_SUPPORT == TRUE
- #undef INSTALL_FS1_SOCKET_SUPPORT
- #define INSTALL_FS1_SOCKET_SUPPORT FALSE
- #endif
-#endif
-
-#ifdef BLDOPT_REMOVE_FP1_SOCKET_SUPPORT
- #if BLDOPT_REMOVE_FP1_SOCKET_SUPPORT == TRUE
- #undef INSTALL_FP1_SOCKET_SUPPORT
- #define INSTALL_FP1_SOCKET_SUPPORT FALSE
- #endif
-#endif
-
-
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE (0)
-#define DFLT_SCRUB_L2_RATE (0)
-#define DFLT_SCRUB_L3_RATE (0)
-#define DFLT_SCRUB_IC_RATE (0)
-#define DFLT_SCRUB_DC_RATE (0)
-#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
-#define DFLT_VRM_SLEW_RATE (5000)
-
-
-// Instantiate all solution relevant data.
-#include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/Include/SanMarinoInstall.h b/src/vendorcode/amd/agesa/Include/SanMarinoInstall.h
deleted file mode 100644
index e0b4c59..0000000
--- a/src/vendorcode/amd/agesa/Include/SanMarinoInstall.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build options for a SanMarino platform solution
- *
- * This file generates the defaults tables for the "San Marino" platform solution
- * set of processors. The documented build options are imported from a user
- * controlled file for processing.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Core
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "CreateStruct.h"
-#include "cpuFeatures.h"
-#include "Table.h"
-#include "CommonReturns.h"
-#include "cpuEarlyInit.h"
-#include "cpuLateInit.h"
-#include "GnbInterfaceStub.h"
-
-/*****************************************************************************
- * Define the RELEASE VERSION string
- *
- * The Release Version string should identify the next planned release.
- * When a branch is made in preparation for a release, the release manager
- * should change/confirm that the branch version of this file contains the
- * string matching the desired version for the release. The trunk version of
- * the file should always contain a trailing 'X'. This will make sure that a
- * development build from trunk will not be confused for a released version.
- * The release manager will need to remove the trailing 'X' and update the
- * version string as appropriate for the release. The trunk copy of this file
- * should also be updated/incremented for the next expected version, + trailing 'X'
- ****************************************************************************/
- // This is the delivery package title, "OrochiPI"
- // This string MUST be exactly 8 characters long
-#define AGESA_PACKAGE_STRING {'O', 'r', 'o', 'c', 'h', 'i', 'P', 'I'}
-
- // This is the release version number of the AGESA component
- // This string MUST be exactly 12 characters long
-#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '6', '.', '0', 'X', ' ', ' ', ' '}
-
-
-// The San Marino solution is defined to be families 0x10 and 0x15 in the C32 socket.
-#define INSTALL_C32_SOCKET_SUPPORT TRUE
-#define INSTALL_FAMILY_10_SUPPORT TRUE
-#define INSTALL_FAMILY_15_SUPPORT TRUE
-
-#ifdef BLDOPT_REMOVE_FAMILY_10_SUPPORT
- #if BLDOPT_REMOVE_FAMILY_10_SUPPORT == TRUE
- #undef INSTALL_FAMILY_10_SUPPORT
- #define INSTALL_FAMILY_10_SUPPORT FALSE
- #endif
-#endif
-
-#ifdef BLDOPT_REMOVE_FAMILY_15_SUPPORT
- #if BLDOPT_REMOVE_FAMILY_15_SUPPORT == TRUE
- #undef INSTALL_FAMILY_15_SUPPORT
- #define INSTALL_FAMILY_15_SUPPORT FALSE
- #endif
-#endif
-
-
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE (0xFF)
-#define DFLT_SCRUB_L2_RATE (0x10)
-#define DFLT_SCRUB_L3_RATE (0x10)
-#define DFLT_SCRUB_IC_RATE (0)
-#define DFLT_SCRUB_DC_RATE (0x12)
-#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
-#define DFLT_VRM_SLEW_RATE (2500)
-
-
-// Instantiate all solution relevant data.
-#include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/Include/ScorpiusInstall.h b/src/vendorcode/amd/agesa/Include/ScorpiusInstall.h
deleted file mode 100644
index f3d3cc0..0000000
--- a/src/vendorcode/amd/agesa/Include/ScorpiusInstall.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build options for a Scorpius platform solution
- *
- * This file generates the defaults tables for the "Scorpius" platform solution
- * set of processors. The documented build options are imported from a user
- * controlled file for processing.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Core
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "CreateStruct.h"
-#include "cpuFeatures.h"
-#include "Table.h"
-#include "CommonReturns.h"
-#include "cpuEarlyInit.h"
-#include "cpuLateInit.h"
-#include "GnbInterfaceStub.h"
-
-/*****************************************************************************
- * Define the RELEASE VERSION string
- *
- * The Release Version string should identify the next planned release.
- * When a branch is made in preparation for a release, the release manager
- * should change/confirm that the branch version of this file contains the
- * string matching the desired version for the release. The trunk version of
- * the file should always contain a trailing 'X'. This will make sure that a
- * development build from trunk will not be confused for a released version.
- * The release manager will need to remove the trailing 'X' and update the
- * version string as appropriate for the release. The trunk copy of this file
- * should also be updated/incremented for the next expected version, + trailing 'X'
- ****************************************************************************/
- // This is the delivery package title, "OrochiPI"
- // This string MUST be exactly 8 characters long
-#define AGESA_PACKAGE_STRING {'O', 'r', 'o', 'c', 'h', 'i', 'P', 'I'}
-
- // This is the release version number of the AGESA component
- // This string MUST be exactly 12 characters long
-#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '6', '.', '0', 'X', ' ', ' ', ' '}
-
-
-// The Scorpius solution is defined to be families 0x10 and 0x15 in the AM3 socket.
-#define INSTALL_AM3_SOCKET_SUPPORT TRUE
-#define INSTALL_FAMILY_10_SUPPORT TRUE
-#define INSTALL_FAMILY_15_SUPPORT TRUE
-
-#ifdef BLDOPT_REMOVE_FAMILY_10_SUPPORT
- #if BLDOPT_REMOVE_FAMILY_10_SUPPORT == TRUE
- #undef INSTALL_FAMILY_10_SUPPORT
- #define INSTALL_FAMILY_10_SUPPORT FALSE
- #endif
-#endif
-
-#ifdef BLDOPT_REMOVE_FAMILY_15_SUPPORT
- #if BLDOPT_REMOVE_FAMILY_15_SUPPORT == TRUE
- #undef INSTALL_FAMILY_15_SUPPORT
- #define INSTALL_FAMILY_15_SUPPORT FALSE
- #endif
-#endif
-
-
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE (0)
-#define DFLT_SCRUB_L2_RATE (0)
-#define DFLT_SCRUB_L3_RATE (0)
-#define DFLT_SCRUB_IC_RATE (0)
-#define DFLT_SCRUB_DC_RATE (0)
-#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
-#define DFLT_VRM_SLEW_RATE (2500)
-
-
-// Instantiate all solution relevant data.
-#include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/Include/TigrisInstall.h b/src/vendorcode/amd/agesa/Include/TigrisInstall.h
deleted file mode 100644
index 77404e0..0000000
--- a/src/vendorcode/amd/agesa/Include/TigrisInstall.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Install of build options for a Tigris platform solution
- *
- * This file generates the defaults tables for the "Tigris" platform solution
- * set of processors. The documented build options are imported from a user
- * controlled file for processing.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Core
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "CreateStruct.h"
-#include "cpuFeatures.h"
-#include "Table.h"
-#include "CommonReturns.h"
-#include "cpuEarlyInit.h"
-#include "cpuLateInit.h"
-#include "GnbInterfaceStub.h"
-
-/*****************************************************************************
- * Define the RELEASE VERSION string
- *
- * The Release Version string should identify the next planned release.
- * When a branch is made in preparation for a release, the release manager
- * should change/confirm that the branch version of this file contains the
- * string matching the desired version for the release. The trunk version of
- * the file should always contain a trailing 'X'. This will make sure that a
- * development build from trunk will not be confused for a released version.
- * The release manager will need to remove the trailing 'X' and update the
- * version string as appropriate for the release. The trunk copy of this file
- * should also be updated/incremented for the next expected version, + trailing 'X'
- ****************************************************************************/
- // This is the delivery package title, "TigrisPI"
- // This string MUST be exactly 8 characters long
-#define AGESA_PACKAGE_STRING {'T', 'i', 'g', 'r', 'i', 's', 'P', 'I'}
-
- // This is the release version number of the AGESA component
- // This string MUST be exactly 12 characters long
-#define AGESA_VERSION_STRING {'V', '0', '.', '1', '.', '2', '.', '3', 'X', ' ', ' ', ' '}
-
-
-// The Tigris solution is defined to be family 0x10 in the S1g3 socket.
-#define INSTALL_S1G3_SOCKET_SUPPORT TRUE
-#define INSTALL_FAMILY_10_SUPPORT TRUE
-
-
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
-#define DFLT_SCRUB_DRAM_RATE (0)
-#define DFLT_SCRUB_L2_RATE (0)
-#define DFLT_SCRUB_L3_RATE (0)
-#define DFLT_SCRUB_IC_RATE (0)
-#define DFLT_SCRUB_DC_RATE (0)
-#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
-#define DFLT_VRM_SLEW_RATE (5000)
-
-
-// Instantiate all solution relevant data.
-#include "PlatformInstall.h"
-
diff --git a/src/vendorcode/amd/agesa/Include/Topology.h b/src/vendorcode/amd/agesa/Include/Topology.h
deleted file mode 100644
index 73c324e..0000000
--- a/src/vendorcode/amd/agesa/Include/Topology.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Topology interface definitions.
- *
- * Contains AMD AGESA internal interface for topology related data which
- * is consumed by code other than HyperTransport init (and produced by
- * HyperTransport init.)
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Core
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _TOPOLOGY_H_
-#define _TOPOLOGY_H_
-
-// Defines for limiting data structure maximum allocation and limit checking.
-#define MAX_NODES 8
-#define MAX_SOCKETS MAX_NODES
-#define MAX_DIES 2
-
-// Defines useful with package link
-#define HT_LIST_MATCH_INTERNAL_LINK_0 0xFA
-#define HT_LIST_MATCH_INTERNAL_LINK_1 0xFB
-#define HT_LIST_MATCH_INTERNAL_LINK_2 0xFC
-
-/**
- * Hop Count Table.
- * This is a heap data structure. The Hops array is filled as a size x size matrix.
- * The unused space, if any, is all at the end.
- */
-typedef struct {
- UINT8 Size; ///< The row and column size of actual hop count data */
- UINT8 Hops[MAX_NODES * MAX_NODES]; ///< Room for a dynamic two dimensional array of [size][size] */
-} HOP_COUNT_TABLE;
-
-/**
- * Socket and Module to Node Map Item.
- * Provide the Node Id and core id range for each module in each processor.
- */
-typedef struct {
- UINT8 Node; ///< The module's Node id.
- UINT8 LowCore; ///< The lowest processor core id for this module.
- UINT8 HighCore; ///< The highest processor core id for this module.
- UINT8 EnabledComputeUnits; ///< The value of Enabled for this processor module.
- UINT8 DualCoreComputeUnits; ///< The value of DualCore for this processor module.
-} SOCKET_DIE_TO_NODE_ITEM;
-
-/**
- * Socket and Module to Node Map.
- * This type is a pointer to the actual map, it can be used for a struct item or
- * for typecasting a heap buffer pointer.
- */
-typedef SOCKET_DIE_TO_NODE_ITEM (*SOCKET_DIE_TO_NODE_MAP)[MAX_SOCKETS][MAX_DIES];
-
-/**
- * Node id to Socket Die Map Item.
- */
-typedef struct {
- UINT8 Socket; ///< socket of the processor containing the Node.
- UINT8 Die; ///< the module in the processor which is Node.
-} NODE_TO_SOCKET_DIE_ITEM;
-
-/**
- * Node id to Socket Die Map.
- */
-typedef NODE_TO_SOCKET_DIE_ITEM (*NODE_TO_SOCKET_DIE_MAP)[MAX_NODES];
-
-/**
- * Provide AP core with socket and node context at start up.
- * This information is posted to the AP cores using a register as a mailbox.
- */
-typedef struct {
- UINT32 Node:4; ///< The node id of Core's node.
- UINT32 Socket:4; ///< The socket of this Core's node.
- UINT32 Module:2; ///< The internal module number for Core's node.
- UINT32 ModuleType:2; ///< Single Module = 0, Multi-module = 1.
- UINT32 :20; ///< Reserved
-} AP_MAIL_INFO_FIELDS;
-
-/**
- * AP info fields can be written and read to a register.
- */
-typedef union {
- UINT32 Info; ///< Just a number for register access, or opaque passing.
- AP_MAIL_INFO_FIELDS Fields; ///< access to the info fields.
-} AP_MAIL_INFO;
-
-/**
- * Provide AP core with system degree and system core number at start up.
- * This information is posted to the AP cores using a register as a mailbox.
- */
-typedef struct {
- UINT32 SystemDegree:3; ///< The number of connected links
- UINT32 :3; ///< Reserved
- UINT32 HeapIndex:6; ///< The zero-based system core number
- UINT32 :20; ///< Reserved
-} AP_MAIL_EXT_INFO_FIELDS;
-
-/**
- * AP info fields can be written and read to a register.
- */
-typedef union {
- UINT32 Info; ///< Just a number for register access, or opaque passing.
- AP_MAIL_EXT_INFO_FIELDS Fields; ///< access to the info fields.
-} AP_MAIL_EXT_INFO;
-
-/**
- * AP Info mailbox set.
- */
-typedef struct {
- AP_MAIL_INFO ApMailInfo; ///< The AP mail info
- AP_MAIL_EXT_INFO ApMailExtInfo; ///< The extended AP mail info
-} AP_MAILBOXES;
-
-/**
- * Provide a northbridge to package mapping for link assignments.
- *
- */
-typedef struct {
- UINT8 Link; ///< The Node's link
- UINT8 Module; ///< The internal module position of Node
- UINT8 PackageLink; ///< The corresponding package link
-} PACKAGE_HTLINK_MAP_ITEM;
-
-/**
- * A Processor's complete set of link assignments
- */
-typedef PACKAGE_HTLINK_MAP_ITEM (*PACKAGE_HTLINK_MAP)[];
-
-#endif // _TOPOLOGY_H_
diff --git a/src/vendorcode/amd/agesa/Include/gcc-intrin.h b/src/vendorcode/amd/agesa/Include/gcc-intrin.h
deleted file mode 100644
index 58438b9..0000000
--- a/src/vendorcode/amd/agesa/Include/gcc-intrin.h
+++ /dev/null
@@ -1,630 +0,0 @@
-/*
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-
-#if defined (__GNUC__)
-
-/* I/O intrin functions. */
-static __inline__ __attribute__((always_inline)) unsigned char __inbyte(unsigned short Port)
-{
- unsigned char value;
-
- __asm__ __volatile__ (
- "in %%dx, %%al"
- : "=a" (value)
- : "d" (Port)
- );
-
- return value;
-}
-
-static __inline__ __attribute__((always_inline)) unsigned short __inword(unsigned short Port)
-{
- unsigned short value;
-
- __asm__ __volatile__ (
- "in %%dx, %%ax"
- : "=a" (value)
- : "d" (Port)
- );
-
- return value;
-}
-
-static __inline__ __attribute__((always_inline)) unsigned long __indword(unsigned short Port)
-{
- unsigned long value;
-
- __asm__ __volatile__ (
- "in %%dx, %%eax"
- : "=a" (value)
- : "d" (Port)
- );
- return value;
-
-}
-
-static __inline__ __attribute__((always_inline)) void __outbyte(unsigned short Port,unsigned char Data)
-{
- __asm__ __volatile__ (
- "out %%al, %%dx"
- :
- : "a" (Data), "d" (Port)
- );
-}
-
-static __inline__ __attribute__((always_inline)) void __outword(unsigned short Port,unsigned short Data)
-{
- __asm__ __volatile__ (
- "out %%ax, %%dx"
- :
- : "a" (Data), "d" (Port)
- );
-}
-
-static __inline__ __attribute__((always_inline)) void __outdword(unsigned short Port,unsigned long Data)
-{
- __asm__ __volatile__ (
- "out %%eax, %%dx"
- :
- : "a" (Data), "d" (Port)
- );
-}
-
-static __inline__ __attribute__((always_inline)) void __inbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count)
-{
- __asm__ __volatile__ (
- "cld ; rep ; insb "
- : "=D" (Buffer), "=c" (Count)
- : "d"(Port), "0"(Buffer), "1" (Count)
- );
-}
-
-static __inline__ __attribute__((always_inline)) void __inwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count)
-{
- __asm__ __volatile__ (
- "cld ; rep ; insw "
- : "=D" (Buffer), "=c" (Count)
- : "d"(Port), "0"(Buffer), "1" (Count)
- );
-}
-
-static __inline__ __attribute__((always_inline)) void __indwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count)
-{
- __asm__ __volatile__ (
- "cld ; rep ; insl "
- : "=D" (Buffer), "=c" (Count)
- : "d"(Port), "0"(Buffer), "1" (Count)
- );
-}
-
-static __inline__ __attribute__((always_inline)) void __outbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count)
-{
- __asm__ __volatile__ (
- "cld ; rep ; outsb "
- : "=S" (Buffer), "=c" (Count)
- : "d"(Port), "0"(Buffer), "1" (Count)
- );
-}
-
-static __inline__ __attribute__((always_inline)) void __outwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count)
-{
- __asm__ __volatile__ (
- "cld ; rep ; outsw "
- : "=S" (Buffer), "=c" (Count)
- : "d"(Port), "0"(Buffer), "1" (Count)
- );
-}
-
-static __inline__ __attribute__((always_inline)) void __outdwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count)
-{
- __asm__ __volatile__ (
- "cld ; rep ; outsl "
- : "=S" (Buffer), "=c" (Count)
- : "d"(Port), "0"(Buffer), "1" (Count)
- );
-}
-
-static __inline__ __attribute__((always_inline)) unsigned long __readdr0(void)
-{
- unsigned long value;
- __asm__ __volatile__ (
- "mov %%dr0, %[value]"
- : [value] "=a" (value)
- );
- return value;
-}
-
-static __inline__ __attribute__((always_inline)) unsigned long __readdr1(void)
-{
- unsigned long value;
- __asm__ __volatile__ (
- "mov %%dr1, %[value]"
- : [value] "=a" (value)
- );
- return value;
-}
-
-static __inline__ __attribute__((always_inline)) unsigned long __readdr2(void)
-{
- unsigned long value;
- __asm__ __volatile__ (
- "mov %%dr2, %[value]"
- : [value] "=a" (value)
- );
- return value;
-}
-
-static __inline__ __attribute__((always_inline)) unsigned long __readdr3(void)
-{
- unsigned long value;
- __asm__ __volatile__ (
- "mov %%dr3, %[value]"
- : [value] "=a" (value)
- );
- return value;
-}
-
-static __inline__ __attribute__((always_inline)) unsigned long __readdr7(void)
-{
- unsigned long value;
- __asm__ __volatile__ (
- "mov %%dr7, %[value]"
- : [value] "=a" (value)
- );
- return value;
-}
-
-static __inline__ __attribute__((always_inline)) unsigned long __readdr(unsigned long reg)
-{
- switch (reg){
- case 0:
- return __readdr0 ();
- break;
-
- case 1:
- return __readdr1 ();
- break;
-
- case 2:
- return __readdr2 ();
- break;
-
- case 3:
- return __readdr3 ();
- break;
-
- case 7:
- return __readdr7 ();
- break;
-
- default:
- return -1;
- }
-}
-
-static __inline__ __attribute__((always_inline)) void __writedr0(unsigned long Data)
-{
- __asm__ __volatile__ (
- "mov %%eax, %%dr0"
- :
- : "a" (Data)
- );
-}
-
-static __inline__ __attribute__((always_inline)) void __writedr1(unsigned long Data)
-{
- __asm__ __volatile__ (
- "mov %%eax, %%dr1"
- :
- : "a" (Data)
- );
-}
-
-static __inline__ __attribute__((always_inline)) void __writedr2(unsigned long Data)
-{
- __asm__ __volatile__ (
- "mov %%eax, %%dr2"
- :
- : "a" (Data)
- );
-}
-
-static __inline__ __attribute__((always_inline)) void __writedr3(unsigned long Data)
-{
- __asm__ __volatile__ (
- "mov %%eax, %%dr3"
- :
- : "a" (Data)
- );
-}
-
-static __inline__ __attribute__((always_inline)) void __writedr7(unsigned long Data)
-{
- __asm__ __volatile__ (
- "mov %%eax, %%dr7"
- :
- : "a" (Data)
- );
-}
-
-static __inline__ __attribute__((always_inline)) void __writedr(unsigned long reg, unsigned long Data)
-{
- switch (reg){
- case 0:
- __writedr0 (Data);
- break;
-
- case 1:
- __writedr1 (Data);
- break;
-
- case 2:
- __writedr2 (Data);
- break;
-
- case 3:
- __writedr3 (Data);
- break;
-
- case 7:
- __writedr7 (Data);
- break;
-
- default:
- ;
- }
-}
-
-static __inline__ __attribute__((always_inline)) unsigned long __readcr0(void)
-{
- unsigned long value;
- __asm__ __volatile__ (
- "mov %%cr0, %[value]"
- : [value] "=a" (value));
- return value;
-}
-
-static __inline__ __attribute__((always_inline)) unsigned long __readcr2(void)
-{
- unsigned long value;
- __asm__ __volatile__ (
- "mov %%cr2, %[value]"
- : [value] "=a" (value));
- return value;
-}
-
-static __inline__ __attribute__((always_inline)) unsigned long __readcr3(void)
-{
- unsigned long value;
- __asm__ __volatile__ (
- "mov %%cr3, %[value]"
- : [value] "=a" (value));
- return value;
-}
-
-static __inline__ __attribute__((always_inline)) unsigned long __readcr4(void)
-{
- unsigned long value;
- __asm__ __volatile__ (
- "mov %%cr4, %[value]"
- : [value] "=a" (value));
- return value;
-}
-
-static __inline__ __attribute__((always_inline)) unsigned long __readcr8(void)
-{
- unsigned long value;
- __asm__ __volatile__ (
- "mov %%cr8, %[value]"
- : [value] "=a" (value));
- return value;
-}
-
-static __inline__ __attribute__((always_inline)) unsigned long __readcr(unsigned long reg)
-{
- switch (reg){
- case 0:
- return __readcr0 ();
- break;
-
- case 2:
- return __readcr2 ();
- break;
-
- case 3:
- return __readcr3 ();
- break;
-
- case 4:
- return __readcr4 ();
- break;
-
- case 8:
- return __readcr8 ();
- break;
-
- default:
- return -1;
- }
-}
-
-static __inline__ __attribute__((always_inline)) void __writecr0(unsigned long Data)
-{
- __asm__ __volatile__ (
- "mov %%eax, %%cr0"
- :
- : "a" (Data)
- );
-}
-
-static __inline__ __attribute__((always_inline)) void __writecr2(unsigned long Data)
-{
- __asm__ __volatile__ (
- "mov %%eax, %%cr2"
- :
- : "a" (Data)
- );
-}
-
-static __inline__ __attribute__((always_inline)) void __writecr3(unsigned long Data)
-{
- __asm__ __volatile__ (
- "mov %%eax, %%cr3"
- :
- : "a" (Data)
- );
-}
-
-static __inline__ __attribute__((always_inline)) void __writecr4(unsigned long Data)
-{
- __asm__ __volatile__ (
- "mov %%eax, %%cr4"
- :
- : "a" (Data)
- );
-}
-
-static __inline__ __attribute__((always_inline)) void __writecr8(unsigned long Data)
-{
- __asm__ __volatile__ (
- "mov %%eax, %%cr8"
- :
- : "a" (Data)
- );
-}
-
-static __inline__ __attribute__((always_inline)) void __writecr(unsigned long reg, unsigned long Data)
-{
- switch (reg){
- case 0:
- __writecr0 (Data);
- break;
-
- case 2:
- __writecr2 (Data);
- break;
-
- case 3:
- __writecr3 (Data);
- break;
-
- case 4:
- __writecr4 (Data);
- break;
-
- case 8:
- __writecr8 (Data);
- break;
-
- default:
- ;
- }
-}
-
-static __inline__ __attribute__((always_inline)) UINT64 __readmsr(UINT32 msr)
-{
- UINT64 retval;
- __asm__ __volatile__(
- "rdmsr\n\t"
- : "=A" (retval)
- : "c" (msr)
- );
- return retval;
-}
-
-static __inline__ __attribute__((always_inline)) void __writemsr (UINT32 msr, UINT64 Value)
-{
- __asm__ __volatile__ (
- "wrmsr\n\t"
- :
- : "c" (msr), "A" (Value)
- );
-}
-
-static __inline__ __attribute__((always_inline)) UINT64 __rdtsc(void)
-{
- UINT64 retval;
- __asm__ __volatile__ (
- "rdtsc"
- : "=A" (retval));
- return retval;
-}
-
-static __inline__ __attribute__((always_inline)) void __cpuid(int CPUInfo[], const int InfoType)
-{
- __asm__ __volatile__(
- "cpuid"
- :"=a" (CPUInfo[0]), "=b" (CPUInfo[1]), "=c" (CPUInfo[2]), "=d" (CPUInfo[3])
- : "a" (InfoType)
- );
-}
-
-
-static __inline__ __attribute__((always_inline)) void _disable(void)
-{
- __asm__ __volatile__ ("cli");
-}
-
-
-static __inline__ __attribute__((always_inline)) void _enable(void)
-{
- __asm__ __volatile__ ("sti");
-}
-
-
-static __inline__ __attribute__((always_inline)) void __halt(void)
-{
- __asm__ __volatile__ ("hlt");
-}
-
-
-static __inline__ __attribute__((always_inline)) void __debugbreak(void)
-{
- __asm__ __volatile__ ("int3");
-}
-
-
-static __inline__ __attribute__((always_inline)) void __wbinvd(void)
-{
- __asm__ __volatile__ ("wbinvd");
-}
-
-
-static __inline__ __attribute__((always_inline)) void __lidt(void *Source)
-{
- __asm__ __volatile__("lidt %0" : : "m"(*(short*)Source));
-}
-
-static __inline__ __attribute__((always_inline)) void __writefsbyte(const unsigned long Offset, const unsigned char Data)
-{
- __asm__("movb %b[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data));
-}
-
-static __inline__ __attribute__((always_inline)) void __writefsword(const unsigned long Offset, const unsigned short Data)
-{
- __asm__("movw %w[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data));
-}
-
-static __inline__ __attribute__((always_inline)) void __writefsdword(const unsigned long Offset, const unsigned long Data)
-{
- __asm__("movl %k[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data));
-}
-
-static __inline__ __attribute__((always_inline)) unsigned char __readfsbyte(const unsigned long Offset)
-{
- unsigned char value;
- __asm__("movb %%fs:%a[Offset], %b[value]" : [value] "=q" (value) : [Offset] "irm" (Offset));
- return value;
-}
-
-static __inline__ __attribute__((always_inline)) unsigned short __readfsword(const unsigned long Offset)
-{
- unsigned short value;
- __asm__("movw %%fs:%a[Offset], %w[value]" : [value] "=q" (value) : [Offset] "irm" (Offset));
- return value;
-}
-
-static __inline__ __attribute__((always_inline)) unsigned long long __readfsdword(unsigned long long Offset)
-{
- unsigned long long value;
- __asm__("movl %%fs:%a[Offset], %k[value]" : [value] "=q" (value) : [Offset] "irm" (Offset));
- return value;
-}
-
-#ifdef __SSE3__
-typedef long long __v2di __attribute__ ((__vector_size__ (16)));
-typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
-
-static __inline__ __attribute__((always_inline)) void _mm_stream_si128_fs2 (void *__A, __m128i __B)
-{
- __asm__(".byte 0x64"); // fs prefix
- __builtin_ia32_movntdq ((__v2di *)__A, (__v2di)__B);
-}
-
-static __inline__ __attribute__((always_inline)) void _mm_stream_si128_fs (void *__A, void *__B)
-{
- __m128i data;
- data = (__m128i) __builtin_ia32_lddqu ((char const *)__B);
- _mm_stream_si128_fs2 (__A, data);
-}
-
-static __inline__ __attribute__((always_inline)) void _mm_clflush_fs (void *__A)
-{
- __asm__(".byte 0x64"); // fs prefix
- __builtin_ia32_clflush (__A);
-}
-
-static __inline __attribute__(( __always_inline__)) void _mm_mfence (void)
-{
- __builtin_ia32_mfence ();
-}
-
-static __inline __attribute__(( __always_inline__)) void _mm_sfence (void)
-{
- __builtin_ia32_sfence ();
-}
-#endif
-
-static __inline__ __attribute__((always_inline)) void __stosb(unsigned char *dest, unsigned char data, size_t count)
-{
- __asm__ __volatile__ (
- "cld ; rep ; stosb "
- : "=D" (dest), "=c" (count)
- : "a"(data), "0"(dest), "1" (count)
- );
-}
-
-static __inline__ __attribute__((always_inline)) void __movsb(unsigned char *dest, unsigned char *data, size_t count)
-{
- __asm__ __volatile__ (
- "cld ; rep ; movsb "
- : "=D" (dest), "=S"(data), "=c" (count)
- : "S"(data), "0"(dest), "1" (count)
- );
-}
-
-static __inline__ __attribute__((always_inline))
-void debug_point ( unsigned short Port, unsigned long Data )
-{
- __outdword (Port, Data);
- __asm__ __volatile__ (".word 0xfeeb");
-
-}
-
-static __inline__ __attribute__((always_inline))
-void delay_point ( unsigned short Port, unsigned long Data, unsigned long delayTime )
-{
- UINTN Index;
- Index = 0;
- __outdword (Port, Data);
- while (Index < delayTime * 600000) {
- __outdword (0xE0, 0);
- Index ++;
- }
-}
-#endif // defined (__GNUC__)
diff --git a/src/vendorcode/amd/agesa/Legacy/PlatformMemoryConfiguration.inc b/src/vendorcode/amd/agesa/Legacy/PlatformMemoryConfiguration.inc
deleted file mode 100644
index 8664323..0000000
--- a/src/vendorcode/amd/agesa/Legacy/PlatformMemoryConfiguration.inc
+++ /dev/null
@@ -1,402 +0,0 @@
-; ****************************************************************************
-; *
-; * @file
-; *
-; * AMD Platform Specific Memory Configuration
-; *
-; * Contains AMD AGESA Memory Configuration Override Interface
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Include
-; * @e \$Revision: 22910 $ @e \$Date: 2009-11-27 04:50:20 -0600 (Fri, 27 Nov 2009) $
-;
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
-IFNDEF PSO_ENTRY
- PSO_ENTRY TEXTEQU <UINT8>; < Platform Configuration Table Entry
-ENDIF
-; *****************************************************************************************
-; *
-; * PLATFORM SPECIFIC MEMORY DEFINITIONS
-; *
-; *****************************************************************************************
-; */
-;
-; < Memory Speed and DIMM Population Masks
-;
-; < DDR Speed Masks
-;
-ANY_SPEED EQU 0FFFFFFFFh
-DDR400 EQU ( 1 SHL (DDR400_FREQUENCY / 66))
-DDR533 EQU ( 1 SHL (DDR533_FREQUENCY / 66))
-DDR667 EQU ( 1 SHL (DDR667_FREQUENCY / 66))
-DDR800 EQU ( 1 SHL (DDR800_FREQUENCY / 66))
-DDR1066 EQU ( 1 SHL (DDR1066_FREQUENCY / 66))
-DDR1333 EQU ( 1 SHL (DDR1333_FREQUENCY / 66))
-DDR1600 EQU ( 1 SHL (DDR1600_FREQUENCY / 66))
-DDR1866 EQU ( 1 SHL (DDR1866_FREQUENCY / 66))
-; <
-; < DIMM POPULATION MASKS
-;
-ANY_ EQU 0FFh
-SR_DIMM0 EQU 0001h
-SR_DIMM1 EQU 0010h
-SR_DIMM2 EQU 0100h
-SR_DIMM3 EQU 1000h
-DR_DIMM0 EQU 0002h
-DR_DIMM1 EQU 0020h
-DR_DIMM2 EQU 0200h
-DR_DIMM3 EQU 2000h
-QR_DIMM0 EQU 0004h
-QR_DIMM1 EQU 0040h
-QR_DIMM2 EQU 0400h
-QR_DIMM3 EQU 4000h
-ANY_DIMM0 EQU 000Fh
-ANY_DIMM1 EQU 00F0h
-ANY_DIMM2 EQU 0F00h
-ANY_DIMM3 EQU 0F000h
-;
-; Number of Dimms
-;
-ANY_NUM EQU 0FFh
-NO_DIMM EQU 00h
-ONE_DIMM EQU 01h
-TWO_DIMM EQU 02h
-THREE_DIMM EQU 04h
-FOUR_DIMM EQU 08h
-; *****************************************************************************************
-; *
-; * Platform Specific Override Definitions for Socket, Channel and Dimm
-; * This indicates where a platform override will be applied.
-; *
-; *****************************************************************************************
-;
-; SOCKET MASKS
-;
-ANY_SOCKET EQU 0FFh
-SOCKET0 EQU 01h
-SOCKET1 EQU 02h
-SOCKET2 EQU 04h
-SOCKET3 EQU 08h
-SOCKET4 EQU 10h
-SOCKET5 EQU 20h
-SOCKET6 EQU 40h
-SOCKET7 EQU 80h
-;
-; CHANNEL MASKS
-;
-ANY_CHANNEL EQU 0FFh
-CHANNEL_A EQU 01h
-CHANNEL_B EQU 02h
-CHANNEL_C EQU 04h
-CHANNEL_D EQU 08h
-;
-; DIMM MASKS
-;
-ALL_DIMMS EQU 0FFh
-DIMM0 EQU 01h
-DIMM1 EQU 02h
-DIMM2 EQU 04h
-DIMM3 EQU 08h
-;
-; REGISTER ACCESS MASKS
-;
-ACCESS_NB0 EQU 0h
-ACCESS_NB1 EQU 01h
-ACCESS_NB2 EQU 02h
-ACCESS_NB3 EQU 03h
-ACCESS_NB4 EQU 04h
-ACCESS_PHY EQU 05h
-ACCESS_DCT_XT EQU 06h
-; *****************************************************************************************
-; *
-; * Platform Specific Overriding Table Definitions
-; *
-; *****************************************************************************************
-PSO_END EQU 0 ; < Table End
-PSO_CKE_TRI EQU 1 ; < CKE Tristate Map
-PSO_ODT_TRI EQU 2 ; < ODT Tristate Map
-PSO_CS_TRI EQU 3 ; < CS Tristate Map
-PSO_MAX_DIMMS EQU 4 ; < Max Dimms per channel
-PSO_CLK_SPEED EQU 5 ; < Clock Speed
-PSO_DIMM_TYPE EQU 6 ; < Dimm Type
-PSO_MEMCLK_DIS EQU 7 ; < MEMCLK Disable Map
-PSO_MAX_CHNLS EQU 8 ; < Max Channels per Socket
-PSO_BUS_SPEED EQU 9 ; < Max Memory Bus Speed
-PSO_MAX_CHIPSELS EQU 10 ; < Max Chipsel per Channel
-PSO_MEM_TECH EQU 11 ; < Channel Memory Type
-PSO_WL_SEED EQU 12 ; < DDR3 Write Levelization Seed delay
-PSO_RXEN_SEED EQU 13 ; < Hardwared based RxEn seed
-PSO_NO_LRDIMM_CS67_ROUTING EQU 14 ; < CS6 and CS7 are not Routed to all Memoy slots on a channel for LRDIMMs
-; **********************************
-; * CONDITIONAL PSO SPECIFIC ENTRIES
-; **********************************
-; Condition Types
-CONDITIONAL_PSO_MIN EQU 100 ; < Start of Conditional Entry Types
-PSO_CONDITION_AND EQU 100 ; < And Block - Start of Conditional block
-PSO_CONDITION_LOC EQU 101 ; < Location - Specify Socket, Channel, Dimms to be affected
-PSO_CONDITION_SPD EQU 102 ; < SPD - Specify a specific SPD value on a Dimm on the channel
-PSO_CONDITION_REG EQU 103 ; Reserved
-PSO_CONDITION_MAX EQU 103 ; < End Of Condition Entry Types
-; Action Types
-PSO_ACTION_MIN EQU 120 ; < Start of Action Entry Types
-PSO_ACTION_ODT EQU 120 ; < ODT values to override
-PSO_ACTION_ADDRTMG EQU 121 ; < Address/Timing values to override
-PSO_ACTION_ODCCONTROL EQU 122 ; < ODC Control values to override
-PSO_ACTION_SLEWRATE EQU 123 ; < Slew Rate value to override
-PSO_ACTION_REG EQU 124 ; Reserved
-PSO_ACTION_SPEEDLIMIT EQU 125 ; < Memory Bus speed Limit based on configuration
-PSO_ACTION_MAX EQU 125 ; < End of Action Entry Types
-CONDITIONAL_PSO_MAX EQU 139 ; < End of Conditional Entry Types
-; *****************************************************************************************
-; *
-; * CONDITIONAL OVERRIDE TABLE MACROS
-; *
-; *****************************************************************************************
-MEMCLK_DIS_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ, Bit4Map:REQ, Bit5Map:REQ, Bit6Map:REQ, Bit7Map:REQ
- DB PSO_MEMCLK_DIS
- DB 10
- DB SocketID
- DB ChannelID
- DB Bit0Map
- DB Bit1Map
- DB Bit2Map
- DB Bit3Map
- DB Bit4Map
- DB Bit5Map
- DB Bit6Map
- DB Bit7Map
-ENDM
-
-CKE_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ
- DB PSO_CKE_TRI
- DB 4
- DB SocketID
- DB ChannelID
- DB Bit0Map
- DB Bit1Map
-ENDM
-
-ODT_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ
- DB PSO_ODT_TRI
- DB 6
- DB SocketID
- DB ChannelID
- DB Bit0Map
- DB Bit1Map
- DB Bit2Map
- DB Bit3Map
-ENDM
-
-CS_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ, Bit4Map:REQ, Bit5Map:REQ, Bit6Map:REQ, Bit7Map:REQ
- DB PSO_CS_TRI
- DB 10
- DB SocketID
- DB ChannelID
- DB Bit0Map
- DB Bit1Map
- DB Bit2Map
- DB Bit3Map
- DB Bit4Map
- DB Bit5Map
- DB Bit6Map
- DB Bit7Map
-ENDM
-
-NUMBER_OF_DIMMS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfDimmSlotsPerChannel:REQ
- DB PSO_MAX_DIMMS
- DB 3
- DB SocketID
- DB ChannelID
- DB NumberOfDimmSlotsPerChannel
-ENDM
-
-NUMBER_OF_CHIP_SELECTS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfChipSelectsPerChannel:REQ
- DB PSO_MAX_CHIPSELS
- DB 3
- DB SocketID
- DB ChannelID
- DB NumberOfChipSelectsPerChannel
-ENDM
-
-NUMBER_OF_CHANNELS_SUPPORTED MACRO SocketID:REQ, NumberOfChannelsPerSocket:REQ
- DB PSO_MAX_CHNLS
- DB 3
- DB SocketID
- DB ANY_CHANNEL
- DB NumberOfChannelsPerSocket
-ENDM
-
-OVERRIDE_DDR_BUS_SPEED MACRO SocketID:REQ, ChannelID:REQ, TimingMode:REQ, BusSpeed:REQ
- PSO_BUS_SPEED
- DB 10
- DB SocketID
- DB ChannelID
- DD TimingMode
- DD BusSpeed
-ENDM
-
-DRAM_TECHNOLOGY MACRO SocketID:REQ, MemTechType:REQ
- DB PSO_MEM_TECH
- DB 6
- DB SocketID
- DB ANY_CHANNEL
- DD MemTechType
-ENDM
-
-WRITE_LEVELING_SEED MACRO SocketID:REQ, ChannelID:REQ, Byte0Seed:REQ, Byte1Seed:REQ, Byte2Seed:REQ, Byte3Seed:REQ, Byte4Seed:REQ, Byte5Seed:REQ, \
-Byte6Seed:REQ, Byte7Seed:REQ, ByteEccSeed:REQ
- DB PSO_WL_SEED
- DB 11
- DB SocketID
- DB ChannelID
- DB Byte0Seed
- DB Byte1Seed
- DB Byte2Seed
- DB Byte3Seed
- DB Byte4Seed
- DB Byte5Seed
- DB Byte6Seed
- DB Byte7Seed
- DB ByteEccSeed
-ENDM
-
-HW_RXEN_SEED MACRO SocketID:REQ, ChannelID:REQ, Byte0Seed:REQ, Byte1Seed:REQ, Byte2Seed:REQ, Byte3Seed:REQ, Byte4Seed:REQ, Byte5Seed:REQ, \
-Byte6Seed:REQ, Byte7Seed:REQ, ByteEccSeed:REQ
- DB PSO_RXEN_SEED
- DB 20
- DB SocketID
- DB ChannelID
- DW Byte0Seed
- DW Byte1Seed
- DW Byte2Seed
- DW Byte3Seed
- DW Byte4Seed
- DW Byte5Seed
- DW Byte6Seed
- DW Byte7Seed
- DW ByteEccSeed
-ENDM
-
-NO_LRDIMM_CS67_ROUTING MACRO SocketID:REQ, ChannelID:REQ
- DB PSO_NO_LRDIMM_CS67_ROUTING
- DB 3
- DB SocketID
- DB ChannelID
- DB 1
-ENDM
-
-
-; *****************************************************************************************
-; *
-; * CONDITIONAL OVERRIDE TABLE MACROS
-; *
-; *****************************************************************************************
-CONDITION_AND MACRO
- DB PSO_CONDITION_AND
- DB 0
-ENDM
-
-COND_LOC MACRO SocketMsk:REQ, ChannelMsk:REQ, DimmMsk:REQ
- DB PSO_CONDITION_LOC
- DB 3
- DB SocketMsk
- DB ChannelMsk
- DB DimmMsk
-ENDM
-
-COND_SPD MACRO Byte:REQ, Mask:REQ, Value:REQ
- DB PSO_CONDITION_SPD
- DB 3
- DB Byte
- DB Mask
- DB Value
-ENDM
-
-COND_REG MACRO Access:REQ, Offset:REQ, Mask:REQ, Value:REQ
- DB PSO_CONDITION_REG
- DB 11
- DB Access
- DW Offset
- DD Mask
- DD Value
-ENDM
-
-ACTION_ODT MACRO Frequency:REQ, Dimms:REQ, QrDimms:REQ, DramOdt:REQ, QrDramOdt:REQ, DramDynOdt:REQ
- DB PSO_ACTION_ODT
- DB 9
- DD Frequency
- DB Dimms
- DB QrDimms
- DB DramOdt
- DB QrDramOdt
- DB DramDynOdt
-ENDM
-
-ACTION_ADDRTMG MACRO Frequency:REQ, DimmConfig:REQ, AddrTmg:REQ
- DB PSO_ACTION_ADDRTMG
- DB 10
- DD Frequency
- DW DimmConfig
- DD AddrTmg
-ENDM
-
-ACTION_ODCCTRL MACRO Frequency:REQ, DimmConfig:REQ, OdcCtrl:REQ
- DB PSO_ACTION_ODCCONTROL
- DB 10
- DD Frequency
- DW DimmConfig
- DD OdcCtrl
-ENDM
-
-ACTION_SLEWRATE MACRO Frequency:REQ, DimmConfig:REQ, SlewRate:REQ
- DB PSO_ACTION_SLEWRATE
- DB 10
- DD Frequency
- DW DimmConfig
- DD SlewRate
-ENDM
-
-ACTION_SPEEDLIMIT MACRO DimmConfig:REQ, Dimms:REQ, SpeedLimit15:REQ, SpeedLimit135:REQ, SpeedLimit125:REQ
- DB PSO_ACTION_SPEEDLIMIT
- DB 9
- DW DimmConfig
- DB Dimms
- DW SpeedLimit15
- DW SpeedLimit135
- DW SpeedLimit125
-ENDM
-
-; *****************************************************************************************
-; *
-; * END OF CONDITIONAL OVERRIDE TABLE MACROS
-; *
-; *****************************************************************************************
diff --git a/src/vendorcode/amd/agesa/Legacy/Proc/Dispatcher.c b/src/vendorcode/amd/agesa/Legacy/Proc/Dispatcher.c
deleted file mode 100644
index fed63ed..0000000
--- a/src/vendorcode/amd/agesa/Legacy/Proc/Dispatcher.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD binary block interface
- *
- * Contains the block entry function dispatcher
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Legacy
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Dispatcher.h"
-#include "Options.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE LEGACY_PROC_DISPATCHER_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-extern CONST DISPATCH_TABLE DispatchTable[];
-extern AMD_MODULE_HEADER mCpuModuleID;
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * The Dispatcher is the entry point into the AGESA software. It takes a function
- * number as entry parameter in order to invoke the published function
- *
- * @param[in,out] ConfigPtr
- *
- * @return AGESA Status.
- *
- */
-AGESA_STATUS
-CALLCONV
-AmdAgesaDispatcher (
- IN OUT VOID *ConfigPtr
- )
-{
- AGESA_STATUS Status;
- IMAGE_ENTRY ImageEntry;
- MODULE_ENTRY ModuleEntry;
- DISPATCH_TABLE *Entry;
- UINT32 ImageStart;
- UINT32 ImageEnd;
- AMD_IMAGE_HEADER* AltImagePtr;
-
- Status = AGESA_UNSUPPORTED;
- ImageEntry = NULL;
- ModuleEntry = NULL;
- ImageStart = 0xFFF00000;
- ImageEnd = 0xFFFFFFFF;
- AltImagePtr = NULL;
-
- Entry = (DISPATCH_TABLE *) DispatchTable;
- while (Entry->FunctionId != 0) {
- if ((((AMD_CONFIG_PARAMS *) ConfigPtr)->Func) == Entry->FunctionId) {
- Status = Entry->EntryPoint (ConfigPtr);
- break;
- }
- Entry++;
- }
-
- // 2. Try next dispatcher if possible, and we have not already got status back
- if ((mCpuModuleID.NextBlock != NULL) && (Status == AGESA_UNSUPPORTED)) {
- ModuleEntry = (MODULE_ENTRY) (UINT64) mCpuModuleID.NextBlock->ModuleDispatcher;
- if (ModuleEntry != NULL) {
- Status = (*ModuleEntry) (ConfigPtr);
- }
- }
-
- // 3. If not this image specific function, see if we can find alternative image instead
- if (Status == AGESA_UNSUPPORTED) {
- if ((((AMD_CONFIG_PARAMS *)ConfigPtr)->AltImageBasePtr != 0xFFFFFFFF ) || (((AMD_CONFIG_PARAMS *)ConfigPtr)->AltImageBasePtr != 0)) {
- ImageStart = ((AMD_CONFIG_PARAMS *)ConfigPtr)->AltImageBasePtr;
- ImageEnd = ImageStart + 4;
- // Locate/test image base that matches this component
- AltImagePtr = LibAmdLocateImage ((VOID *) (UINT64)ImageStart, (VOID *) (UINT64)ImageEnd, 4096, AGESA_ID);
- if (AltImagePtr != NULL) {
- //Invoke alternative Image
- ImageEntry = (IMAGE_ENTRY) ((UINT64) AltImagePtr + AltImagePtr->EntryPointAddress);
- Status = (*ImageEntry) (ConfigPtr);
- }
- }
- }
-
- return (Status);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * The host environment interface of callout.
- *
- * @param[in] Func
- * @param[in] Data
- * @param[in,out] ConfigPtr
- *
- * @return The AGESA Status returned from the callout.
- *
- */
-AGESA_STATUS
-CALLCONV
-AmdAgesaCallout (
- IN UINT32 Func,
- IN UINT32 Data,
- IN OUT VOID *ConfigPtr
- )
-{
- UINT32 Result;
- Result = AGESA_UNSUPPORTED;
- if (((AMD_CONFIG_PARAMS *) ConfigPtr)->CalloutPtr == NULL) {
- return Result;
- }
-
- Result = (((AMD_CONFIG_PARAMS *) ConfigPtr)->CalloutPtr) (Func, Data, ConfigPtr);
- return (Result);
-}
diff --git a/src/vendorcode/amd/agesa/Legacy/Proc/Legacy.bat b/src/vendorcode/amd/agesa/Legacy/Proc/Legacy.bat
deleted file mode 100644
index 0b79a98..0000000
--- a/src/vendorcode/amd/agesa/Legacy/Proc/Legacy.bat
+++ /dev/null
@@ -1,286 +0,0 @@
- at echo off
-echo *****************************************************************************
-echo *
-echo * Copyright (c) 2011, Advanced Micro Devices, Inc.
-echo * All rights reserved.
-echo *
-echo * Redistribution and use in source and binary forms, with or without
-echo * modification, are permitted provided that the following conditions are met:
-echo * * Redistributions of source code must retain the above copyright
-echo * notice, this list of conditions and the following disclaimer.
-echo * * Redistributions in binary form must reproduce the above copyright
-echo * notice, this list of conditions and the following disclaimer in the
-echo * documentation and/or other materials provided with the distribution.
-echo * * Neither the name of Advanced Micro Devices, Inc. nor the names of
-echo * its contributors may be used to endorse or promote products derived
-echo * from this software without specific prior written permission.
-echo *
-echo * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-echo * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-echo * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-echo * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-echo * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-echo * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-echo * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-echo * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-echo * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-echo * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-echo *
-echo * ***************************************************************************
-
-
-goto Begin
-:Documentation
-echo off
-echo **************************************************************************
-echo * Legacy.Bat
-echo * This batchfile establishes the build environment for an AGESA(TM)
-echo * legacy build.
-echo *
-echo * Syntax:
-echo * Legacy.bat Solution [DevTipPath] [DevKey] [DoxKey] [Release^|Debug] [Internal]
-echo * Parameters:
-echo * %% 1 Solution name. This is the AMD Platform Solution name that
-echo * identifies the delivery package. No default, this
-echo * parameter MUST be specified. This parameter MUST
-echo * be specified before the DevTip Path parameter.
-echo * %% 2 Path to the platform specific build directory. This is
-echo * where the options file %%Solution%%Options.c is located,
-echo * which contains the platform specific build option settings.
-echo * If left blank, the default %%Solution%%Options.c file from
-echo * the AGESA\Addendum directory is used.
-echo * %% 3 Developer's key - open an interactive MSVS window. This parameter is
-echo * optional, but when used it requires the first two parameters.
-echo * %% 4 Documentation Key - requests a compilation of the DOxygen
-echo * documentation files. key is "DOX". This parameter is
-echo * optional, but when used it requires the first two parameters.
-echo * %% 5 Build Configuration. There are two choices, "Release" and "Debug".
-echo * Debug is the default choice if not specified. This parameter is
-echo * optional, but when used it requires the first two parameters.
-echo * %% 6 Internal solution file select - choose a internal solution file.This parameter
-echo * is optional, but when used it requires the first two parameters.
-echo * NOTE: The paths MUST have a trailing '\' character.
-echo *
-echo * The AGESA build environment requires the following environment
-echo * variables MUST be defined for proper operation:
-echo * $(AGESA_ROOT) - identifies the directory where the AGESA code
-echo * is located. The top most dir; where AGESA.h is located.
-echo * This must be the full path, eg D:\myPlatform\AGESA\
-echo * **** This var is expected to be set by the caller ****
-echo *
-echo * $(Solution) - identifies the Platform Solution being targeted
-echo * $(AGESA_OptsDir) - identifies the directory where the platform
-echo * options and customization files are located.
-echo * This must be the full path
-echo *
-echo * Optional build environment variables
-echo *
-echo * set AGESA_B1_ADDRESS=0xFFF?????
-echo * Sets the B1 image base address in the ROM (otherwise 0xFFFD0000).
-echo * set AGESA_B2_ADDRESS=0xFFF?????
-echo * Sets the B2 image base address in the ROM (otherwise 0xFFFA0000).
-echo *
-echo * NOTE: The paths MUST have a trailing '\' character.
-echo **************************************************************************
-goto Exit
-
-:Begin
-rem Clear working vars...
-set DevKey=
-set DoxKey=
-set Solution=
-set Configuration=
-
-rem set default to external file prefix none
-set SolutionType=
-
-rem Validate the AGESA_ROOT variable
-IF "%AGESA_ROOT%"=="" goto Else001
- rem User has set a path for Agesa_Root, verify that path...
- IF EXIST %AGESA_ROOT%Agesa.h goto EndIf002
- rem Try adding trailing '\'
- set AGESA_ROOT=%AGESA_ROOT%\
- IF EXIST %AGESA_ROOT%Agesa.h goto EndIf003
- echo Build ERROR: Environment variable AGESA_ROOT is invalid,
- echo Build ERROR: Could not find file Agesa.h at: %AGESA_ROOT%
- pause
- goto Documentation
- :EndIf003
- :EndIf002
- goto EndIf001
-:Else001
- echo Build ERROR: Required environment variable missing: AGESA_ROOT
- pause
- goto Documentation
-:EndIf001
-
-rem Start processing the input parameters...
-:DoLoop
- rem Switch (%1)
- IF /I "%1"=="DevKey" goto Case001
- IF /I "%1"=="Maranello" goto Case002
- IF /I "%1"=="DevTest" goto Case002
- IF /I "%1"=="Danube" goto Case002
- IF /I "%1"=="DanNi" goto Case002
- IF /I "%1"=="Nile" goto Case002
- IF /I "%1"=="Dragon" goto Case002
- IF /I "%1"=="SanMarino" goto Case002
- IF /I "%1"=="Scorpius" goto Case002
- IF /I "%1"=="Sabine" goto Case002
- IF /I "%1"=="Lynx" goto Case002
- IF /I "%1"=="Brazos" goto Case002
- IF /I "%1"=="DOX" goto Case009
- IF /I "%1"=="Debug" goto Case011
- IF /I "%1"=="Release" goto Case011
- IF /I "%1"=="Internal" goto Case012
- IF "%1"=="" goto Case006
- goto Case004
- :Case001
- rem Case 1: Special command param
- set DevKey=DevKey
- goto EndSwitch
- :Case002
- rem Case 2: Solution name parameter
- rem Set the Platform Solution name for the build environment
- rem Validation of the names was done by the IF's at the top of DoLoop
- set Solution=%1
- goto EndSwitch
- :Case004
- rem Case 4: Path param, check for validity
- rem Check if parameter matches the default
- rem Check for shortcut versions of the default. Also
- rem checking for missing trailing '\'
- IF /I "%1"=="Addendum" goto Then040
- IF /I "%1"=="Addendum\" goto Then040
- IF /I "%1"=="..\Addendum" goto Then040
- IF /I "%1"=="..\Addendum\" goto Then040
- IF /I "%1"=="..\..\Addendum" goto Then040
- IF /I "%1"=="..\..\Addendum\" goto Then040
- goto Else040
- :Then040
- set AGESA_OptsDir=%AGESA_ROOT%Addendum\
- Echo Build WARNING: User selected the default options path.
- goto EndIf040
- :Else040
- set AGESA_OptsDir=%1
- rem Non-default path given,
- rem Validate the AGESA_OptsDir parameter ( %%1 = %1 )...
- IF /I "%Solution%"=="" goto Else042
- IF EXIST %AGESA_OptsDir%%Solution%Options.c goto EndIf044
- rem Check if param was missing trailing '\'...
- set AGESA_OptsDir=%AGESA_OptsDir%\
- IF EXIST %AGESA_OptsDir%%Solution%Options.c goto EndIf045
- rem If using the default, assume the release file is in place.
- rem Could not find options file, post an error
- Echo Build ERROR: Path to AGESA options file is not valid...
- Echo . . Could not find options file: %AGESA_OptsDir%%Solution%Options.c
- set AGESA_OptsDir=
- set Solution=
- exit /B 5
- :EndIf045
- :EndIf044
- goto EndIf042
- :Else042
- rem Else042 - parameter ordering error, need to specify solution before tip path
- Echo Build ERROR: The 'Solution' name was not recognized or
- Echo The Solution must be specified before the Development tip path
- Echo . . . Legacy.bat Solution [DevTipPath] [DevKey] [DoxKey]
- exit /B 4
- :EndIf042
- :EndIf040
- goto EndSwitch
- :Case006
- rem Case 6: Parameter is blank, end of list
- rem Validate the required Environment Variables
- IF /I "%Solution%"=="" goto Else066
- IF NOT "%AGESA_OptsDir%"=="" goto Else060
- Rem No path param specified. Use the default file shipped with the AGESA package...
- Echo Build WARNING: Using default options file.
- set AGESA_OptsDir=%AGESA_ROOT%Addendum\
- goto EndIf060
- :Else060
- rem Else060 - tip path may have been set by caller prior to call,
- rem Validate the AGESA_OptsDir parameter ( %%AGESA_OptsDir = %AGESA_OptsDir% )...
- IF EXIST %AGESA_OptsDir%%Solution%Options.c goto EndIf061
- rem Check if param was missing trailing '\'...
- set AGESA_OptsDir=%AGESA_OptsDir%\
- IF EXIST %AGESA_OptsDir%%Solution%Options.c goto EndIf062
- rem If using the default, assume the release file is in place.
- rem Could not find options file, post an error
- Echo Build ERROR: Path to AGESA options file is not valid...
- Echo . . Could not find options file: %AGESA_OptsDir%%Solution%Options.c
- set AGESA_OptsDir=
- set Solution=
- exit /B 4
- :EndIf062
- :EndIf061
- :EndIf060
- goto EndIf066
- :Else066
- rem Else066 - parameter missing error, need to specify 'solution'
- Echo Build ERROR: The Platform Solution name must be specified:
- Echo . . . Legacy.bat Solution [DevTipPath] [DevKey] [DoxKey]
- exit /B 4
- :EndIf066
- goto EndDo
- :Case009
- rem Case 9: Documentation generation key
- set DoxKey=DoxKey
- goto EndSwitch
- :Case011
- rem Case 11: Build Configuration
- set Configuration=%1
- goto EndSwitch
- :Case012
- rem Case 12: Select Internal solution file prefix
- set SolutionType=%1
- goto EndSwitch
- :EndSwitch
- SHIFT
- goto DoLoop
-:EndDo
-
-rem # Ensure that Microsoft Visual Studio 2005 is installed on this machine.
-IF NOT "%VS80COMNTOOLS%"=="" goto EndIf95
-echo ---------------------------------------------------------------------
-echo - Building AGESA ARCH2008 requires Microsoft Visual Studio 2005 -
-echo - Install Visual Studio 2005 and confirm environment -
-echo - variable VS80COMNTOOLS is present. -
-echo ---------------------------------------------------------------------
-pause
-exit
-:EndIf95
-
-rem set the Visual Studio 32-bit development environment
-call "%VS80COMNTOOLS%vsvars32.bat"
-
-rem Launch the documentation generator if selected by the user
-IF NOT "%DoxKey%"=="DoxKey" goto EndIf100
- devenv %AGESA_ROOT%Proc\AgesaDoc.sln /Rebuild "Release|Win32"
-:EndIf100
-
-rem Use the default build configuration if none was specified.
-IF NOT "%Configuration%"=="" goto EndIf110
- set Configuration=Debug
-:EndIf110
-
-rem Check image bases
-IF NOT "%AGESA_B1_ADDRESS%"=="" goto EndIf120
- set AGESA_B1_ADDRESS=0xFFFD0000
-:EndIf120
-IF NOT "%AGESA_B2_ADDRESS%"=="" goto EndIf130
- set AGESA_B2_ADDRESS=0xFFFA0000
-:EndIf130
-
-rem Check if the 'secret' developers' key was used, open an interactive VS window
-IF NOT "%DevKey%"=="DevKey" goto Else140
- set DevKey=
- rem This is the command to open an interactive development window ...
- start /NORMAL devenv.exe %AGESA_ROOT%Legacy\Proc\%Solution%%SolutionType%Legacy.sln /ProjectConfig "%Configuration%|Win32"
- goto EndIf140
-:Else140
- rem Else140 - This is the command to perform a background or automated build ...
- devenv %AGESA_ROOT%Legacy\Proc\%Solution%%SolutionType%Legacy.sln /Rebuild "%Configuration%|Win32"
-:EndIf140
-:Exit
-exit /B 0
diff --git a/src/vendorcode/amd/agesa/Legacy/Proc/agesaCallouts.c b/src/vendorcode/amd/agesa/Legacy/Proc/agesaCallouts.c
deleted file mode 100644
index ffb712e..0000000
--- a/src/vendorcode/amd/agesa/Legacy/Proc/agesaCallouts.c
+++ /dev/null
@@ -1,397 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU AGESA Callout Functions
- *
- * Contains code to set / get useful platform information.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Common
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Dispatcher.h"
-#include "cpuServices.h"
-#include "Ids.h"
-#include "Filecode.h"
-
-#define FILECODE LEGACY_PROC_AGESACALLOUTS_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S - (AGESA ONLY)
- *----------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * Call the host environment interface to do the warm or cold reset.
- *
- * @param[in] ResetType Warm or Cold Reset is requested
- * @param[in,out] StdHeader Config header
- *
- */
-VOID
-AgesaDoReset (
- IN UINTN ResetType,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_STATUS Status;
- WARM_RESET_REQUEST Request;
-
- // Clear warm request bit and set state bits to the current post stage
- GetWarmResetFlag (StdHeader, &Request);
- Request.RequestBit = FALSE;
- Request.StateBits = Request.PostStage;
- SetWarmResetFlag (StdHeader, &Request);
-
- Status = AmdAgesaCallout (AGESA_DO_RESET, (UINT32)ResetType, (VOID *) StdHeader);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * Call the host environment interface to allocate buffer in main system memory.
- *
- * @param[in] FcnData
- * @param[in,out] AllocParams Heap manager parameters
- *
- * @return The AGESA Status returned from the callout.
- *
- */
-AGESA_STATUS
-AgesaAllocateBuffer (
- IN UINTN FcnData,
- IN OUT AGESA_BUFFER_PARAMS *AllocParams
- )
-{
- AGESA_STATUS Status;
-
- Status = AmdAgesaCallout (AGESA_ALLOCATE_BUFFER, (UINT32)FcnData, (VOID *) AllocParams);
-
- return Status;
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Call the host environment interface to deallocate buffer in main system memory.
- *
- * @param[in] FcnData
- * @param[in,out] DeallocParams Heap Manager parameters
- *
- * @return The AGESA Status returned from the callout.
- */
-AGESA_STATUS
-AgesaDeallocateBuffer (
- IN UINTN FcnData,
- IN OUT AGESA_BUFFER_PARAMS *DeallocParams
- )
-{
- AGESA_STATUS Status;
-
- Status = AmdAgesaCallout (AGESA_DEALLOCATE_BUFFER, (UINT32)FcnData, (VOID *) DeallocParams);
-
- return Status;
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * Call the host environment interface to Locate buffer Pointer in main system memory
- *
- * @param[in] FcnData
- * @param[in,out] LocateParams Heap manager parameters
- *
- * @return The AGESA Status returned from the callout.
- *
- */
-AGESA_STATUS
-AgesaLocateBuffer (
- IN UINTN FcnData,
- IN OUT AGESA_BUFFER_PARAMS *LocateParams
- )
-{
- AGESA_STATUS Status;
-
- Status = AmdAgesaCallout (AGESA_LOCATE_BUFFER, (UINT32)FcnData, (VOID *) LocateParams);
-
- return Status;
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Call the host environment interface to launch APs
- *
- * @param[in] ApicIdOfCore
- * @param[in,out] LaunchApParams
- *
- * @return The AGESA Status returned from the callout.
- *
- */
-AGESA_STATUS
-AgesaRunFcnOnAp (
- IN UINTN ApicIdOfCore,
- IN AP_EXE_PARAMS *LaunchApParams
- )
-{
- AGESA_STATUS Status;
-
- Status = AmdAgesaCallout (AGESA_RUNFUNC_ONAP, (UINT32)ApicIdOfCore, (VOID *) LaunchApParams);
-
- return Status;
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Call the host environment interface to read an SPD's content.
- *
- * @param[in] FcnData
- * @param[in,out] ReadSpd
- *
- * @return The AGESA Status returned from the callout.
- *
- */
-AGESA_STATUS
-AgesaReadSpd (
- IN UINTN FcnData,
- IN OUT AGESA_READ_SPD_PARAMS *ReadSpd
- )
-{
- AGESA_STATUS Status;
-
- Status = AmdAgesaCallout (AGESA_READ_SPD, (UINT32)FcnData, ReadSpd);
-
- return Status;
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Call the host environment interface to read an SPD's content.
- *
- * @param[in] FcnData
- * @param[in,out] ReadSpd
- *
- * @return The AGESA Status returned from the callout.
- *
- */
-AGESA_STATUS
-AgesaReadSpdRecovery (
- IN UINTN FcnData,
- IN OUT AGESA_READ_SPD_PARAMS *ReadSpd
- )
-{
- AGESA_STATUS Status;
-
- Status = AmdAgesaCallout (AGESA_READ_SPD_RECOVERY, (UINT32)FcnData, ReadSpd);
-
- return Status;
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Call the host environment interface to provide a user hook opportunity.
- *
- * @param[in] FcnData
- * @param[in,out] MemData
- *
- * @return The AGESA Status returned from the callout.
- *
- */
-AGESA_STATUS
-AgesaHookBeforeDramInitRecovery (
- IN UINTN FcnData,
- IN OUT MEM_DATA_STRUCT *MemData
- )
-{
- AGESA_STATUS Status;
-
- Status = AmdAgesaCallout (AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, (UINT32)FcnData, MemData);
-
- return Status;
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Call the host environment interface to provide a user hook opportunity.
- *
- * @param[in] FcnData
- * @param[in,out] MemData
- *
- * @return The AGESA Status returned from the callout.
- *
- */
-AGESA_STATUS
-AgesaHookBeforeDramInit (
- IN UINTN FcnData,
- IN OUT MEM_DATA_STRUCT *MemData
- )
-{
- AGESA_STATUS Status;
-
- Status = AmdAgesaCallout (AGESA_HOOKBEFORE_DRAM_INIT, (UINT32)FcnData, MemData);
-
- return Status;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Call the host environment interface to provide a user hook opportunity.
- *
- * @param[in] FcnData
- * @param[in,out] MemData
- *
- * @return The AGESA Status returned from the callout.
- *
- */
-AGESA_STATUS
-AgesaHookBeforeDQSTraining (
- IN UINTN FcnData,
- IN OUT MEM_DATA_STRUCT *MemData
- )
-{
- AGESA_STATUS Status;
-
- Status = AmdAgesaCallout (AGESA_HOOKBEFORE_DQS_TRAINING, (UINT32)FcnData, MemData);
-
- return Status;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Call the host environment interface to provide a user hook opportunity.
- *
- * @param[in] FcnData
- * @param[in,out] MemData
- *
- * @return The AGESA Status returned from the callout.
- *
- */
-AGESA_STATUS
-AgesaHookBeforeExitSelfRefresh (
- IN UINTN FcnData,
- IN OUT MEM_DATA_STRUCT *MemData
- )
-{
- AGESA_STATUS Status;
-
- Status = AmdAgesaCallout (AGESA_HOOKBEFORE_EXIT_SELF_REF, (UINT32)FcnData, MemData);
-
- return Status;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Call the host environment interface to provide a user hook opportunity.
- *
- * @param[in] Data
- * @param[in,out] IdsCalloutData
- *
- * @return The AGESA Status returned from the callout.
- *
- */
-
-
-AGESA_STATUS
-AgesaGetIdsData (
- IN UINTN Data,
- IN OUT IDS_CALLOUT_STRUCT *IdsCalloutData
- )
-{
- AGESA_STATUS Status;
-
- Status = AmdAgesaCallout (AGESA_GET_IDS_INIT_DATA, (UINT32)Data, IdsCalloutData);
-
- return Status;
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * PCIE slot reset control
- *
- *
- *
- * @param[in] FcnData Function data
- * @param[in] ResetInfo Reset information
- * @retval Status Agesa status
- */
-
-AGESA_STATUS
-AgesaPcieSlotResetControl (
- IN UINTN FcnData,
- IN PCIe_SLOT_RESET_INFO *ResetInfo
- )
-{
- AGESA_STATUS Status;
- Status = AmdAgesaCallout (AGESA_GNB_PCIE_SLOT_RESET, (UINT32) FcnData, ResetInfo);
- return Status;
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Legacy/Proc/arch2008.asm b/src/vendorcode/amd/agesa/Legacy/Proc/arch2008.asm
deleted file mode 100644
index d307906..0000000
--- a/src/vendorcode/amd/agesa/Legacy/Proc/arch2008.asm
+++ /dev/null
@@ -1,2674 +0,0 @@
-;*****************************************************************************
-; AMD Generic Encapsulated Software Architecture
-;
-; Workfile: arch2008.asm $Revision: 37157 $ $Date: 2010-09-01 03:24:07 +0800 (Wed, 01 Sep 2010) $
-;
-; Description: ARCH2008.ASM - AGESA Architecture 2008 Wrapper Template
-;
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
- .XLIST
- INCLUDE agesa.inc
- INCLUDE acwrapg.inc ; Necessary support file as part of wrapper, including but not limited to segment start/end macros.
- INCLUDE acwrap.inc ; IBVs may specify host BIOS-specific include files required when building.
- INCLUDE cpcarmac.inc
- INCLUDE bridge32.inc
- .LIST
- .586p
- .mmx
-
-
-;----------------------------------------------------------------------------
-; Local definitions
-;----------------------------------------------------------------------------
-
-sOemCallout STRUCT
- FuncName DD ? ; Call out function name
- FuncPtr DW ? ; Call out function pointer
-sOemCallout ENDS
-
-sOemEventHandler STRUCT
- ClassCode DD ? ; AGESA event log sub-class code
- FuncPtr DW ? ; Event handler function pointer
-sOemEventHandler ENDS
-
-;; A typical legacy BIOS implementation may require the E000 and F000 segments
-;; to be cached.
-EXE_CACHE_REGION_BASE_0 EQU 0E0000h
-EXE_CACHE_REGION_SIZE_0 EQU 20000h
-
-;; In this sample implementation, the B1 and B2 images are placed next to each
-;; other in the BIOS ROM to help with the maximization of cached code.
-EXE_CACHE_REGION_BASE_1 EQU AGESA_B1_ADDRESS
-EXE_CACHE_REGION_SIZE_1 EQU 40000h
-
-;; The third region is not needed in our example.
-EXE_CACHE_REGION_BASE_2 EQU 0
-EXE_CACHE_REGION_SIZE_2 EQU 0
-
-
-;----------------------------------------------------------------------------
-; PERSISTENT SEGMENT
-; This segment is required to be present throughout all BIOS execution.
-;----------------------------------------------------------------------------
-
-AMD_PERSISTENT_START
-
-
-;----------------------------------------------------------------------------
-; Instantiate the global descriptor table
-;----------------------------------------------------------------------------
-
-AMD_BRIDGE_32_GDT AMD_GDT ; Instantiate the global descriptor table
- ; required by the push-high mechanism.
-
-
-;----------------------------------------------------------------------------
-; Declare the external routines required in the persistent segment
-;----------------------------------------------------------------------------
-
-;+-------------------------------------------------------------------------
-;
-; AmdDfltRet
-;
-; Entry:
-; None
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; Near stub procedure. Simply perform a retn instruction.
-;
-EXTERN AmdDfltRet:NEAR
-
-
-;+-------------------------------------------------------------------------
-;
-; AmdDfltRetFar
-;
-; Entry:
-; None
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; Far stub procedure. Simply perform a retf instruction.
-;
-EXTERN AmdDfltRetFar:FAR
-
-
-;----------------------------------------------------------------------------
-; Declare the optional external routines in the persistent segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; myModuleTypeMismatchHandler (Example)
-;
-; Entry:
-; ESI - Pointer to the EVENT_PARAMS structure of the failure.
-; [ESI].DataParam1 - Socket
-; [ESI].DataParam2 - DCT
-; [ESI].DataParam3 - Channel
-; [ESI].DataParam4 - 0x00000000
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure can be used to react to a memory module type
-; mismatch error discovered by the AGESA code. Actions taken
-; may include, but are not limited to:
-; Logging the event to NV for display later
-; Reset, excluding the mismatch on subsequent reboot
-; Do nothing
-;
-; Dependencies:
-; None
-;
-EXTERN myModuleTypeMismatchHandler(AmdDfltRet):NEAR
-
-;+---------------------------------------------------------------------------
-;
-; oemPlatformConfigInit (Optional)
-;
-; Entry:
-; EDI - 32-bit flat pointer to the PLATFORM_CONFIGURATION to be
-; passed in to the next AGESA entry point.
-;
-; typedef struct {
-; IN PERFORMANCE_PROFILE PlatformProfile;
-; IN CPU_HT_DEEMPHASIS_LEVEL *PlatformDeemphasisList;
-; IN UINT8 CoreLevelingMode;
-; IN PLATFORM_C1E_MODES C1eMode;
-; IN UINT32 C1ePlatformData;
-; IN UINT32 C1ePlatformData1;
-; IN UINT32 C1ePlatformData2;
-; IN BOOLEAN UserOptionDmi;
-; IN BOOLEAN UserOptionPState;
-; IN BOOLEAN UserOptionSrat;
-; IN BOOLEAN UserOptionSlit;
-; IN BOOLEAN UserOptionWhea;
-; IN UINT32 PowerCeiling;
-; IN BOOLEAN PstateIndependent;
-; } PLATFORM_CONFIGURATION;
-;
-; typedef struct {
-; IN UINT8 Socket;
-; IN UINT8 Link;
-; IN UINT8 LoFreq;
-; IN UINT8 HighFreq;
-; IN PLATFORM_DEEMPHASIS_LEVEL ReceiverDeemphasis;
-; IN PLATFORM_DEEMPHASIS_LEVEL DcvDeemphasis;
-; } CPU_HT_DEEMPHASIS_LEVEL;
-;
-; typedef struct {
-; IN PLATFORM_CONTROL_FLOW PlatformControlFlowMode;
-; IN BOOLEAN UseHtAssist;
-; IN BOOLEAN UseAtmMode;
-; IN BOOLEAN Use32ByteRefresh;
-; IN BOOLEAN UseVariableMctIsocPriority;
-; } PERFORMANCE_PROFILE;
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; Provide a single hook routine to modify the parameters of a
-; PLATFORM_CONFIGURATION structure before any entry point that
-; has such a structure as an input.
-;
-; Dependencies:
-; None
-;
-; Example:
-; If your platform is running in UMA mode, the following code
-; may be added:
-; mov (PLATFORM_CONFIGURATION PTR [edi]).PlatformProfile.PlatformControlFlowMode, UmaDr
-;
-EXTERN oemPlatformConfigInit(AmdDfltRetFar):FAR
-
-;+---------------------------------------------------------------------------
-;
-; oemCallout (Optional)
-;
-; Entry:
-; ECX - Callout function number
-; EDX - Function-specific UINTN
-; ESI - Pointer to function specific data
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; The default call out router function which resides in the same
-; segment as the push-high bridge code.
-;
-; Dependencies:
-; None
-;
-EXTERN oemCallout(AmdDfltRet):NEAR
-
-
-;----------------------------------------------------------------------------
-; Define the sample wrapper routines for the persistent segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; AmdBridge32
-;
-; Entry:
-; EDX - A Real Mode FAR pointer using seg16:Offset16 format that
-; points to a local host environment call-out router. If
-; this pointer is not equal to zero, then this pointer is
-; used as the call-out router instead of the standard
-; OemCallout. This may be useful when the call-out router
-; is not located in the same segment as the AmdBridge32 and
-; AmdCallout16 routines.
-; ESI - A Flat Mode pointer (32-bit address) that points to the
-; configuration block (AMD_CONFIG_PARAMS) for the AGESA
-; software function.
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; Execute an AGESA software function through the Push-High interface.
-;
-; Dependencies:
-; This procedure requires a stack. The host environment must use the
-; provided service function to establish the stack environment prior
-; to making the call to this procedure.
-;
-AmdBridge32 PROC FAR PUBLIC
- AMD_BRIDGE_32 AMD_GDT ; use the macro for the body
- ret
-AmdBridge32 ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdEnableStack
-;
-; Entry:
-; BX - Return address
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-; SS:ESP - Points to the private stack location for this processor core.
-; ECX - Upon success, contains this processor core's stack size in bytes.
-;
-; Modified:
-; EAX, ECX, EDX, EDI, ESI, ESP, DS, ES
-;
-; Purpose:
-; This procedure is used to establish the stack within the host environment.
-;
-; Dependencies:
-; The host environment must use this procedure and not rely on any other
-; sources to create the stack region.
-;
-AmdEnableStack PROC NEAR PUBLIC
- AMD_ENABLE_STACK
- ;; EAX = AGESA_SUCCESS, The stack space has been allocated for this core.
- ;; EAX = AGESA_WARNING, The stack has already been set up. SS:ESP is set
- ;; to stack top, and ECX is the stack size in bytes.
- jmp bx
-AmdEnableStack ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdDisableStack
-;
-; Entry:
-; BX - Return address
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; EAX, ECX, EDX, ESI, ESP
-;
-; Purpose:
-; This procedure is used to remove the pre-memory stack from within the
-; host environment.
-; The exit state for the BSP is described as follows:
-; Memory region 00000-9FFFF MTRRS are set as WB memory.
-; Processor Cache is enabled (CD bit is cleared).
-; MTRRs used for execution cache are kept.
-; Cache content is flushed (invalidated without write-back).
-; Any family-specific clean-up done.
-; The exit state for the APs is described as follows:
-; Memory region 00000-9FFFF MTRRS are set as WB memory.
-; Memory region A0000-DFFFF MTRRS are set as UC IO.
-; Memory region E0000-FFFFF MTRRS are set as UC memory.
-; MTRRs used for execution cache are cleared.
-; Processor Cache is disabled (CD bit is set).
-; Top-of-Memory (TOM) set to the system top of memory as determined
-; by the memory initialization routines.
-; System lock command is enabled.
-; Any family-specific clean-up done.
-;
-; Dependencies:
-; The host environment must use this procedure and not rely on any other
-; sources to break down the stack region.
-; If executing in 16-bit code, the host environment must establish the
-; "Big Real" mode of 32-bit addressing of data.
-;
-AmdDisableStack PROC NEAR PUBLIC
- AMD_DISABLE_STACK
- ;; EAX = AGESA_SUCCESS, The stack space has been disabled for this core.
- jmp bx
-AmdDisableStack ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdCallout16
-;
-; Entry:
-; [esp+8] - Func
-; [esp+12] - Data
-; [esp+16] - Configuration Block
-; [esp+4] - Return address to AGESA
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; Execute callback from the push-high interface.
-;
-; Dependencies:
-; None
-;
-AmdCallout16 PROC FAR PUBLIC ; declare the procedure
- AMD_CALLOUT_16 oemCallout ; use the macro for the body
- ret
-AmdCallout16 ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdProcessAgesaErrors (Optional)
-;
-; Entry:
-; AL - Heap status of the AGESA entry point that was just invoked.
-; EBX - AGESA image base address.
-; EDX - Segment / Offset of the appropriate callout router function.
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure is used to handle any errors that may have occurred
-; during an AGESA entry point.
-;
-; Dependencies:
-; None
-;
-AmdProcessAgesaErrors PROC FAR PUBLIC
- LOCAL localCpuInterfaceBlock:EVENT_PARAMS
-
- pushad
- xor edi, edi
- mov di, ss
- shl edi, 4
- lea esi, localCpuInterfaceBlock
- add esi, edi
-
- ; Fill default config block
- mov (EVENT_PARAMS PTR [esi]).StdHeader.Func, AMD_READ_EVENT_LOG
- mov (EVENT_PARAMS PTR [esi]).StdHeader.ImageBasePtr, ebx
- mov (EVENT_PARAMS PTR [esi]).StdHeader.AltImageBasePtr, 0
- mov (EVENT_PARAMS PTR [esi]).StdHeader.HeapStatus, al
- mov edi, SEG AmdCallout16
- shl edi, 4
- add edi, OFFSET AmdCallout16
- mov (EVENT_PARAMS PTR [esi]).StdHeader.CalloutPtr, edi
-
- ; Flush the event log searching for, and handling all monitored events
- xor eax, eax
- .while (eax == 0)
- push edx
- call AmdBridge32
- pop edx
- .if (eax == AGESA_SUCCESS)
- mov eax, (EVENT_PARAMS PTR [esi]).EventInfo
- .if (eax != 0)
- lea di, cs:AgesaEventTable
-
-loopThruTable:
- cmp di, OFFSET cs:AgesaEventTableEnd
- jae unhandledEvent
-
- cmp eax, cs:[di].sOemEventHandler.ClassCode
- je FoundMatch
- add di, SIZEOF sOemEventHandler
- jmp loopThruTable
-
-FoundMatch:
- mov bx, cs:[di].sOemEventHandler.FuncPtr
- call bx
-
-unhandledEvent:
- xor eax, eax
- .else
- mov al, 1
- .endif
- .endif
- .endw
- popad
- ret
-
-AmdProcessAgesaErrors ENDP
-
-
-;----------------------------------------------------------------------------
-; Define the error handler table
-;----------------------------------------------------------------------------
-
-AgesaEventTable LABEL BYTE
- ;; Add entries as desired
- ;;---------
- ;; EXAMPLE
- ;;---------
- sOemEventHandler <MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM, OFFSET myModuleTypeMismatchHandler>
-AgesaEventTableEnd LABEL BYTE
-
-
-AMD_PERSISTENT_END
-
-
-
-
-;----------------------------------------------------------------------------
-; RECOVERY SEGMENT
-; This segment resides in the classic 'boot-block,' and is used
-; for recovery.
-;----------------------------------------------------------------------------
-
-AMD_RECOVERY_START
-
-
-;----------------------------------------------------------------------------
-; Declare the external routines required in the recovery segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; myReadSPDRecovery (Required for proper recovery mode operation)
-;
-; Entry:
-; ESI - Pointer to an AGESA_READ_SPD_PARAMS structure.
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT8 SocketId;
-; IN UINT8 MemChannelId;
-; IN UINT8 DimmId;
-; IN OUT UINT8 *Buffer;
-; IN OUT MEM_DATA_STRUCT *MemData;
-; } AGESA_READ_SPD_PARAMS;
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS Indicates the SPD block for the indicated
-; DIMM was read successfully.
-; AGESA_BOUNDS_CHK The specified DIMM is not present.
-; AGESA_UNSUPPORTED This is a required function, so this
-; value being returned causes a critical
-; error response value from the AGESA
-; software function and no memory initialized.
-; AGESA_ERROR The DIMM SPD read process has generated
-; communication errors.
-;
-; Modified:
-; None
-;
-; Purpose:
-; This call out reads a block of memory SPD data and places it
-; into the provided buffer.
-;
-; Dependencies:
-; None
-;
-EXTERN myReadSPDRecovery:NEAR
-
-
-;----------------------------------------------------------------------------
-; Define the sample wrapper routines for the recovery segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitResetWrapper
-;
-; Entry:
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; A minimal initialization of the processor core is performed. This
-; procedure must be called by all processor cores. The code path
-; separates the BSP from the APs and performs a separate and appropriate
-; list of tasks for each class of core.
-; For the BSP, the following actions are performed:
-; Internal heap sub-system initialization
-; Primary non-coherent HyperTransportT link initialization
-; Return to the host environment to test for Recovery Mode.
-; The AP processor cores do not participate in the recovery process.
-; However, they execute this routine after being released to execute
-; by the BSP during the main boot process. Their actions include the
-; following:
-; Internal heap sub-system initialization
-; Proceed to a wait loop waiting for commands from the BSP
-;
-; For the cache regions, up to three regions of execution cache can be
-; allocated following the following rules:
-; 1. Once a region is allocated, it cannot be de-allocated. However, it
-; can be expanded.
-; 2. At most, two of the three regions can be located above 1 MByte. A
-; region failing this rule is ignored.
-; 3. All region addresses must be at or above the 0x000D0000 linear
-; address. A region failing this rule is ignored.
-; 4. The address is aligned on a 32-KByte boundary. Starting addresses
-; is rounded down to the nearest 32-Kbyte boundary.
-; 5. The execution cache size must be a multiple of 32 KByte. Size is
-; rounded up to the next multiple of 32 KByte.
-; 6. A region must not span either the 1-MByte boundary or the 4-GByte
-; boundary. Allocated size is truncated to not span the boundary.
-; 7. The granted cached execution regions, address, and size are calculated
-; based on the available cache resources of the processor core.
-; Allocations are made up to the limit of cache available on the
-; installed processor.
-; Warning: Enabling instruction cache outside of this interface can cause
-; data corruption.
-;
-; Dependencies:
-; This procedure is expected to be executed soon after a system reset
-; for the main boot path or resume path of execution.
-;
-; This procedure requires a stack.
-;
-; Because the heap system is not yet operational at the point of the
-; interface call, the host environment must allocate the storage for
-; the AMD_RESET_PARAMS structure before making the first call to
-; AmdCreateStruct. This is the ByHost method of allocation.
-;
-AmdInitResetWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
- local localResetParams:AMD_RESET_PARAMS
-
- pushad
-
- ; Prepare for the call to initialize the input parameters for AmdInitReset
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B1_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- ; Use the 'ByHost' allocation method because the heap has not been initialized as of yet.
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_RESET
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, ByHost
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, sizeof AMD_RESET_PARAMS
- lea edx, localResetParams
- add edx, eax
- push edx
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr, edx
- mov dx, SEG AmdCalloutRouterRecovery
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterRecovery
- push edx
- call AmdBridge32
- pop edx
- pop esi
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- ; Allocate the execution cache to maximize the amount of code in ROM that is cached.
- ; Placing the B1 and B2 images near one another is a good way to ensure the AGESA code
- ; is cached.
- mov (AMD_RESET_PARAMS ptr [esi]).CacheRegion.ExeCacheStartAddr, EXE_CACHE_REGION_BASE_0
- mov (AMD_RESET_PARAMS ptr [esi]).CacheRegion.ExeCacheSize, EXE_CACHE_REGION_SIZE_0
- mov (AMD_RESET_PARAMS ptr [esi + sizeof EXECUTION_CACHE_REGION]).CacheRegion.ExeCacheStartAddr, EXE_CACHE_REGION_BASE_1
- mov (AMD_RESET_PARAMS ptr [esi + sizeof EXECUTION_CACHE_REGION]).CacheRegion.ExeCacheSize, EXE_CACHE_REGION_SIZE_1
- mov (AMD_RESET_PARAMS ptr [esi + (2 * sizeof EXECUTION_CACHE_REGION)]).CacheRegion.ExeCacheStartAddr, EXE_CACHE_REGION_BASE_2
- mov (AMD_RESET_PARAMS ptr [esi + (2 * sizeof EXECUTION_CACHE_REGION)]).CacheRegion.ExeCacheSize, EXE_CACHE_REGION_SIZE_2
-
- ; Call in to the AmdInitReset entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS Early initialization completed successfully.
- ;; AGESA_WARNING One or more of the execution cache allocation
- ;; rules were violated, but an adjustment was made
- ;; and space was allocated.
- ;; AGESA_ERROR One or more of the execution cache allocation rules
- ;; were violated, which resulted in a requested cache
- ;; region to not be allocated.
- ;; The storage space allocated for the AMD_RESET_PARAMS
- ;; structure is insufficient.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_RESET_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B1_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
-
- ;; Here are what the MTRRs should look like based off of the CacheRegions specified above:
-
- ;; Fixed-Range MTRRs
- ;; Name Address Value
- ;; ---------------- -------- ----------------
- ;; MTRRfix4k_E0000 0000026C 0505050505050505
- ;; MTRRfix4k_E8000 0000026D 0505050505050505
- ;; MTRRfix4k_F0000 0000026E 0505050505050505
- ;; MTRRfix4k_F8000 0000026F 0505050505050505
- ;; MTRRdefType 000002FF 0000000000000C00
- ;;
- ;; Variable-Range MTRRs and IO Range
- ;; MTRRphysBase(n) MTRRphysMask(n)
- ;; ----------------- -----------------
- ;; n=0 0000000000000000 0000000000000000
- ;; n=1 0000000000000000 0000000000000000
- ;; n=2 0000000000000000 0000000000000000
- ;; n=3 0000000000000000 0000000000000000
- ;; n=4 0000000000000000 0000000000000000
- ;; n=5 Heap Base (Varies by core) 0000FFFFFFFF0800
- ;; n=6 AGESA_B1_ADDRESS | 6 0000FFFFFFFC0800
- ;; n=7 0000000000000000 0000000000000000
-
-
- ;; Because the allocation method is 'ByHost,' the call to AMD_RELEASE_STRUCT is
- ;; not necessary. Stack space reclamation is left up to the host BIOS.
-
- popad
- ret
-
-
-AmdInitResetWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitRecoveryWrapper
-;
-; Entry:
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; Perform a minimum initialization of the processor and memory to
-; support a recovery mode flash ROM update.
-; For the BSP, the following actions are performed:
-; Configuration of CPU core for recovery process
-; Minimal initialization of some memory
-; The AP processor cores do not participate in the recovery process.
-; No actions or tasks are performed by the AP cores for this time point.
-;
-; Dependencies:
-; This procedure requires a stack. The host environment must use one of
-; the provided service functions to establish the stack environment prior
-; to making the call to this procedure.
-;
-AmdInitRecoveryWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitRecovery
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B1_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_RECOVERY
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterRecovery
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterRecovery
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
-
- ; Call in to the AmdInitRecovery entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
- ;; AGESA_WARNING One or more of the allocation rules were violated,
- ;; but an adjustment was made and space was allocated.
- ;; AGESA_ERROR One or more of the allocation rules were violated,
- ;; which resulted in a requested cache region to not be
- ;; allocated.
- ;; AGESA_FATAL No memory was found in the system.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_RECOVERY_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B1_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdInitRecovery
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
- popad
- ret
-AmdInitRecoveryWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdCalloutRouterRecovery
-;
-; Entry:
-; ECX - Callout function number
-; EDX - Function-specific UINTN
-; ESI - Pointer to function specific data
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; The call out router function for AmdInitReset and
-; AmdInitRecovery.
-;
-; Dependencies:
-; None
-;
-AmdCalloutRouterRecovery PROC FAR PUBLIC USES ECX EBX ESI BX DI DS ES
- xor ax, ax
- mov ds, ax
- mov es, ax
- lea di, cs:CalloutRouterTableRecovery
- mov eax, AGESA_UNSUPPORTED
-
-loopThruTable:
- cmp di, OFFSET cs:CalloutRouterTableRecoveryEnd
- jae amdCpuCalloutExit ; exit with AGESA_UNSUPPORTED
- cmp ecx, cs:[di].sOemCallout.FuncName
- je FoundMatch
- add di, SIZEOF sOemCallout
- jmp loopThruTable
-
-FoundMatch:
- mov bx, cs:[di].sOemCallout.FuncPtr
- call bx
-
-amdCpuCalloutExit:
- ret
-AmdCalloutRouterRecovery ENDP
-
-
-;----------------------------------------------------------------------------
-; Define the callout dispatch table for the recovery segment
-;----------------------------------------------------------------------------
-
-CalloutRouterTableRecovery LABEL BYTE
- ;; Standard B1 implementations only need the SPD reader call out function to be implemented.
- sOemCallout <AGESA_READ_SPD, OFFSET myReadSPDRecovery>
-CalloutRouterTableRecoveryEnd LABEL BYTE
-
-
-AMD_RECOVERY_END
-
-
-
-;----------------------------------------------------------------------------
-; PRE-MEMORY SEGMENT
-; This segment must be uncompressed in the ROM image.
-;----------------------------------------------------------------------------
-
-AMD_PREMEM_START
-
-
-;----------------------------------------------------------------------------
-; Declare the external routines required in the recovery segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; myReadSPDPremem (Required)
-;
-; Entry:
-; ESI - Pointer to an AGESA_READ_SPD_PARAMS structure
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT8 SocketId;
-; IN UINT8 MemChannelId;
-; IN UINT8 DimmId;
-; IN OUT UINT8 *Buffer;
-; IN OUT MEM_DATA_STRUCT *MemData;
-; } AGESA_READ_SPD_PARAMS;
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS Indicates the SPD block for the indicated
-; DIMM was read successfully.
-; AGESA_BOUNDS_CHK The specified DIMM is not present.
-; AGESA_UNSUPPORTED This is a required function, so this
-; value being returned causes a critical
-; error response value from the AGESA
-; software function and no memory initialized.
-; AGESA_ERROR The DIMM SPD read process has generated
-; communication errors.
-;
-; Modified:
-; None
-;
-; Purpose:
-; This call out reads a block of memory SPD data and places it
-; into the provided buffer.
-;
-; Dependencies:
-; None
-;
-EXTERN myReadSPDPremem:NEAR
-
-;+-------------------------------------------------------------------------
-;
-; AmdDfltRetPremem
-;
-; Entry:
-; None
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; Near stub procedure in the prememory segment. Simply perform a
-; retn instruction.
-;
-EXTERN AmdDfltRetPremem:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; myDoReset (Required)
-;
-; Entry:
-; EDX - Reset type
-; 1 - Warm reset whenever
-; 2 - Cold reset whenever
-; 3 - Warm reset immediately
-; 4 - Cold reset immediately
-; ESI - Pointer to an AMD_CONFIG_PARAMS structure.
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_UNSUPPORTED This is a required function, so this
-; value being returned causes a critical
-; error response value from the AGESA
-; software function.
-;
-; Modified:
-; None
-;
-; Purpose:
-; This host environment function must initiate the specified type
-; of system reset.
-;
-; Implementation of this function by the host environment is
-; REQUIRED. Some host environments may record this as a request
-; allowing other elements in the system to perform some additional
-; tasks before the actual reset is issued.
-;
-; Dependencies:
-; The AMD processor contains 3 bits (BiosRstDet[2:0]) in a PCI
-; register (F0x6C Link Initialization Control Register) that
-; indicate the reset status. These bits are reserved for use by
-; the AGESA software and should not be modified by the host
-; environment.
-;
-EXTERN myDoReset:NEAR
-
-
-;+---------------------------------------------------------------------------
-;
-; myGetNonVolatileS3Context (Required for proper S3 operation)
-;
-; Entry:
-; None
-;
-; Exit:
-; EBX - Pointer to the non-volatile S3 context block
-; ECX - Size in bytes of the non-volatile S3 context block
-;
-; Modified:
-; None
-;
-; Purpose:
-; The host environment must return the pointer to the data
-; saved during the mySaveNonVolatileS3Context routine.
-;
-; Dependencies:
-; None
-;
-EXTERN myGetNonVolatileS3Context:NEAR
-
-
-;----------------------------------------------------------------------------
-; Declare the optional external routines in the prememory segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; myAgesaHookBeforeExitSelfRefresh (Optional)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - 44h
-; ESI - Pointer to a data structure containing the memory information
-;
-; Exit:
-; After returning control to AGESA, AGESA will display: - AGESA_TESTPOINT - 45h
-; EAX - Contains the AGESA_STATUS return code
-; AGESA_SUCCESS The function has completed successfully
-; AGESA_UNSUPPORTED This function is not implemented by the host environment
-; AGESA_WARNING A non-critical issue has occued in the host environment
-;
-; Modified:
-; None
-;
-; Purpose:
-; General purpose hook called before the exiting self refresh
-; This procedure is called once per channel
-;
-; Implementation of this function is optional for the host environment
-; This call-out is an opportunity for the host environment to make dynamic
-; modifications to the memory timing settings specific to the board or host
-; environment before exiting self refresh on S3 resume
-;
-; Dependencies:
-; This procedure is called before the exit self refresh bit is set in the resume
-; sequence. The host environment must initiate the OS restart process. This procedure
-; requires a stack. The host environment must establish the stack environment prior
-; to making the call to this procedure
-;
-EXTERN myAgesaHookBeforeExitSelfRefresh(AmdDfltRetPremem):NEAR
-
-
-;+---------------------------------------------------------------------------
-;
-; myHookBeforeDramInit (Optional)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - 40h
-; ESI - Pointer to a data structure containing the memory information
-;
-; Exit:
-; After returning control to AGESA, AGESA will display - AGESA_TESTPOINT - 41h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_UNSUPPORTED This function is not implemented by the host environment
-;
-; Modified:
-; None
-;
-; Purpose:
-; General-purpose hook called before the DRAM_Init bit is set. Called
-; once per MCT
-;
-; Implementation of this function is optional for the host environment
-; This call-out is an opportunity for the host environment to make
-; dynamic modifications to the memory timing settings specific to the
-; board or host environment
-;
-; Dependencies:
-; None
-;
-EXTERN myHookBeforeDramInit(AmdDfltRetPremem):NEAR
-
-
-;+---------------------------------------------------------------------------
-;
-; myHookBeforeDQSTraining (Optional)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - 42h
-; ESI - Pointer to a data structure containing the memory information.
-;
-; Exit:
-; After returning control to AGESA, AGESA will display - AGESA_TESTPOINT - 43h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_UNSUPPORTED This function is not implemented by the
-; host environment.
-;
-; Modified:
-; None
-;
-; Purpose:
-; General-purpose hook called just before the memory training processes
-; begin. Called once per MCT.
-;
-; Implementation of this function is optional for the host environment.
-; This call-out is an opportunity for the host environment to make
-; dynamic modifications to the memory timing settings specific to the
-; board or host environment.
-;
-; The host environment may also use this call-out for some board-
-; specific features that should be activated at this time point,
-; such as:
-; Low voltage DIMMs-the host environment should set the recommended
-; voltages found in the memory data structure for each memory
-; channel. This needs to occur before training begins.
-;
-; Dependencies:
-; None
-;
-EXTERN myHookBeforeDQSTraining(AmdDfltRetPremem):NEAR
-
-
-;----------------------------------------------------------------------------
-; Define the sample wrapper routines for the prememory segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitEarlyWrapper
-;
-; Entry:
-; On Entry to "AmdInitEarly" AGESA will display AGESA_TESTPOINT - C4h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitEarly" AGESA will display AGESA_TESTPOINT - C5h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; A full initialization of the processor is performed. Action details
-; differ for the BSP and AP processor cores.
-; For the BSP, the following actions are performed:
-; Full HyperTransportT link initialization, coherent and non-coherent
-; Processor register loading
-; Microcode patch load
-; Errata workaround processing
-; Launch all processor cores
-; Configure the processor power management capabilities
-; Request a warm reset if needed
-; For the AP, the following actions are performed:
-; Processor register loading
-; Microcode patch load
-; Errata workaround processing
-; Configure the processor power management capabilities
-;
-; Dependencies:
-; This procedure is expected to be called before main memory initialization
-; and before the system warm reset. Prior to this, the basic configuration
-; done by the AmdInitReset routine must be completed.
-;
-; This procedure requires a stack. The host environment must use one of the
-; provided service functions to establish the stack environment prior to
-; making the call to this procedure.
-;
-; The processes performed at this time point require communication between
-; processor cores.
-;
-; The host environment must recognize that all processor cores are running
-; in parallel and avoid activities that might interfere with the core-to-core
-; communication, such as modifying the MTRR settings or writing to the APIC
-; registers.
-;
-AmdInitEarlyWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitEarly
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_EARLY
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPremem
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPremem
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, (SIZEOF AMD_CONFIG_PARAMS + (3 * (SIZEOF EXECUTION_CACHE_REGION)))
- call oemPlatformConfigInit
-
- ; Call in to the AmdInitEarly entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
- ;; AGESA_ALERT An HyperTransportT link CRC error was observed.
- ;; AGESA_WARNING One of more of the allocation rules were violated,
- ;; but an adjustment was made and space was allocated.
- ;; Or a HyperTransport device does not have the expected
- ;; capabilities, or unusable redundant HyperTransport
- ;; links were found.
- ;; AGESA_ERROR One or more of the allocation rules were violated, which
- ;; resulted in a requested cache region to not be allocated.
- ;; Or, a HyperTransport device failed to initialize.
- ;; AGESA_CRITICAL An illegal or unsupported mixture of processor types was
- ;; found, or the processors installed were found to have an
- ;; insufficient MP capability rating for this platform.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_EARLY_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdInitEarly
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
-
- popad
- ret
-AmdInitEarlyWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitPostWrapper
-;
-; Entry:
-; On Entry to "AmdInitPost" AGESA will display AGESA_TESTPOINT - C6h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitPost" AGESA will display AGESA_TESTPOINT - C7h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; The main system memory is located, initialized, and brought on-line.
-; The processor(s) are prepared for full operation and control by the
-; host environment. Action details differ for the BSP and AP processor
-; cores.
-; For the BSP, the following actions are performed:
-; Full memory initialization and configuration. BSP is the master for
-; this process and may delegate some tasks to APs.
-; AP collection of data for use later.
-; Transfer the HOBs including the artifact data out of the pre-memory
-; cache storage into a temporary holding buffer in the main memory.
-; Check the BIST status of the BSP
-; Shut down the APs.
-; Prepare for the host environment to begin main boot activity.
-; Disable the pre-memory stack.
-; For the APs, the following actions are performed:
-; Report core identity information.
-; Execute indicated memory initialization processes as directed.
-; Check the BIST status of the AP
-; Disable the pre-memory stack.
-; Prepare to halt, giving control to host environment.
-; The entire range of system memory is enabled for Write-Back cache.
-; The fixed MTRRs and the variable MTRRs[7:6] are not changed in order
-; to leave in place any flash ROM region currently set for Write-Protect
-; execution cache.
-;
-; Dependencies:
-; This procedure is called after the host environment has determined that
-; a normal boot to operating system should be performed after any system
-; warm reset is completed and after the configuration done by AmdInitEarly
-; has completed.
-;
-; This procedure requires a stack. The host environment must use one of the
-; provided service functions to establish the stack environment prior to
-; making the call to this procedure.
-;
-; The processes performed at this time point require communication between
-; processor cores. The host environment must recognize that all processor
-; cores are running in parallel and avoid activities that might interfere
-; with the core-to-core communication, such as modifying the MTRR settings
-; or writing to the APIC registers.
-;
-AmdInitPostWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitPost
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_POST
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPremem
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPremem
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, SIZEOF AMD_CONFIG_PARAMS
- call oemPlatformConfigInit
-
- ; Call in to the AmdInitPost entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
- ;; AGESA_ALERT A BIST error was found on one of the cores.
- ;; AGESA_WARNING HT Assist feature is running sub-optimally.
- ;; AGESA_FATAL Memory initialization failed.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_POST_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdInitPost
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
-
- popad
- ret
-AmdInitPostWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitResumeWrapper
-;
-; Entry:
-; On Entry to "AmdInitResume" AGESA will display AGESA_TESTPOINT - D0h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitResume" AGESA will display AGESA_TESTPOINT - D1h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure initializes or re-initializes the silicon components
-; for the resume boot path. For the processor, main memory is brought
-; out of self-refresh mode. This procedure will use the context data
-; in the NvStorage area of the input structure to re-start the main
-; memory. The host environment must fill the AMD_S3_PARAMS NvStorage
-; and VolatileStorage pointers and related size elements to describe
-; the location of the context data. Note that for this procedure, the
-; two data areas do not need to be contained in one buffer zone, they
-; can be anywhere in the accessible memory address space. If the host
-; environment uses a non-volatile storage device accessed on the system
-; address bus such as flashROM, then the context data does not need to
-; be moved prior to this call. If the host environment uses a non-
-; volatile storage device not located on the system address bus (e.g.
-; CMOS or SSEPROM) then the host environment must transfer the context
-; data to a buffer in main memory prior to calling this procedure.
-;
-; Dependencies:
-; The host environment must have determined that the system should take
-; the resume path prior to calling this procedure. The configuration
-; done by AmdInitEarly and any necessary warm reset must be complete.
-; After this procedure, execution proceeds to general system restoration.
-;
-; This procedure requires a stack. The host environment must use one of
-; the provided service functions to establish the stack environment prior
-; to making the call to this procedure.
-;
-AmdInitResumeWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitResume
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_RESUME
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPremem
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPremem
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, (SIZEOF AMD_CONFIG_PARAMS + SIZEOF AMD_S3_PARAMS)
- call oemPlatformConfigInit
-
- call myGetNonVolatileS3Context
- mov (AMD_RESUME_PARAMS ptr [esi]).S3DataBlock.NvStorage, ebx
- mov (AMD_RESUME_PARAMS ptr [esi]).S3DataBlock.NvStorageSize, ecx
-
- ; Call in to the AmdInitResume entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS Re-initialization has been completed successfully.
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_RESUME_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
-
- ; Allow AGESA to free the space used by AmdInitResume
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
-
- popad
- ret
-AmdInitResumeWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdCalloutRouterPremem
-;
-; Entry:
-; ECX - Callout function number
-; EDX - Function-specific UINTN
-; ESI - Pointer to function specific data
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; The call out router function for AmdInitEarly,
-; AmdInitPost, and AmdInitResume.
-;
-; Dependencies:
-; None
-;
-AmdCalloutRouterPremem PROC FAR PUBLIC USES ECX EBX ESI BX DI DS ES
- xor ax, ax
- mov ds, ax
- mov es, ax
- lea di, cs:CalloutRouterTablePremem
- mov eax, AGESA_UNSUPPORTED
-
-loopThruTable:
- cmp di, OFFSET cs:CalloutRouterTablePrememEnd
- jae amdCpuCalloutExit ; exit with AGESA_UNSUPPORTED
- cmp ecx, cs:[di].sOemCallout.FuncName
- je FoundMatch
- add di, SIZEOF sOemCallout
- jmp loopThruTable
-
-FoundMatch:
- mov bx, cs:[di].sOemCallout.FuncPtr
- call bx
-
-amdCpuCalloutExit:
- ret
-AmdCalloutRouterPremem ENDP
-
-
-;----------------------------------------------------------------------------
-; Define the callout dispatch table for the prememory segment
-;----------------------------------------------------------------------------
-
-CalloutRouterTablePremem LABEL BYTE
- ;; Add entries as desired.
- sOemCallout <AGESA_READ_SPD, OFFSET myReadSPDPremem>
- sOemCallout <AGESA_HOOKBEFORE_DRAM_INIT, OFFSET myHookBeforeDramInit>
- sOemCallout <AGESA_HOOKBEFORE_DQS_TRAINING, OFFSET myHookBeforeDQSTraining>
- sOemCallout <AGESA_HOOKBEFORE_EXIT_SELF_REF, OFFSET myAgesaHookBeforeExitSelfRefresh>
- sOemCallout <AGESA_DO_RESET, OFFSET myDoReset>
-CalloutRouterTablePrememEnd LABEL BYTE
-
-
-
-AMD_PREMEM_END
-
-
-;----------------------------------------------------------------------------
-; POST SEGMENT
-; This segment may be decompressed and run from system RAM.
-;----------------------------------------------------------------------------
-
-AMD_POST_START
-
-
-;----------------------------------------------------------------------------
-; Declare the external routines required in the POST segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; myAllocateBuffer (Required)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - E2h
-; ESI - Pointer to an AGESA_BUFFER_PARAMS structure.
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT32 BufferLength;
-; IN UINT32 BufferHandle;
-; OUT VOID *BufferPointer;
-; } AGESA_BUFFER_PARAMS;
-;
-; Exit:
-; After this hook, AGESA will display - AGESA_TESTPOINT - E3h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The requested size of memory has been
-; successfully allocated.
-; AGESA_UNSUPPORTED This is a required function, so this
-; value being returned causes a critical
-; error response value from the AGESA
-; software function.
-; AGESA_ERROR Less than the requested amount of memory
-; was allocated.
-;
-; Modified:
-; EAX
-;
-; Purpose:
-; This function is used after main memory has been initialized
-; and the host environment has taken control of memory allocation.
-; This function must allocate a buffer of the requested size or
-; larger. This function is required to be implemented by the host
-; environment.
-;
-; Dependencies:
-; The following call-outs must work together in the host system.
-; Parameters of the same name have the same function and must be
-; treated the same in each function:
-; AgesaAllocateBuffer
-; AgesaDeallocateBuffer
-; AgesaLocateBuffer
-; AgesaRunFcnOnAp
-; The host environment may need to reserve a location in the buffer
-; to store any host environment specific value(s). The returned
-; pointer must not include this reserved space. The host environment
-; on the AgesaDeallocateBuffer call needs to account for the reserved
-; space. This reserved space may be an identifier or the "handle"
-; used to identify the specific memory block.
-;
-EXTERN myAllocateBuffer:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; myDeallocateBuffer (Required)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - E4h
-; ESI - Pointer to an AGESA_BUFFER_PARAMS structure.
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT32 BufferLength;
-; IN UINT32 BufferHandle;
-; OUT VOID *BufferPointer;
-; } AGESA_BUFFER_PARAMS;
-;
-; Exit:
-; After this hook, AGESA will display - AGESA_TESTPOINT - E5h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_BOUNDS_CHK The BufferHandle is invalid. The AGESA
-; software continues with its function.
-; AGESA_UNSUPPORTED This is a required function, so this
-; value being returned causes a critical
-; error response value from the AGESA
-; software function.
-;
-; Modified:
-; EAX
-;
-; Purpose:
-; This function is used after main memory has been initialized
-; and the host environment has taken control of memory allocation.
-; This function releases a valid working buffer. This function is
-; required for the host environment to implement.
-;
-; Dependencies:
-; The following call-outs must work together in the host system.
-; Parameters of the same name have the same function and must be
-; treated the same in each function:
-; AgesaAllocateBuffer
-; AgesaDeallocateBuffer
-; AgesaLocateBuffer
-; AgesaRunFcnOnAp
-;
-EXTERN myDeallocateBuffer:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; myLocateBuffer (Required)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - E6h
-; ESI - Pointer to an AGESA_BUFFER_PARAMS structure.
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT32 BufferLength;
-; IN UINT32 BufferHandle;
-; OUT VOID *BufferPointer;
-; } AGESA_BUFFER_PARAMS;
-;
-; Exit:
-; After this hook, AGESA will display - AGESA_TESTPOINT - E7h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_BOUNDS_CHK The presented handle is invalid or the
-; buffer could not be located.
-;
-; Modified:
-; EAX
-;
-; Purpose:
-; This function is used after main memory has been initialized
-; and the host environment has taken control of memory allocation.
-; This function must locate the buffer related to the indicated
-; handle and return the address of the buffer and its length.
-; This function is required to be implemented in the host
-; environment.
-;
-; Dependencies:
-; The following call-outs must work together in the host system.
-; Parameters of the same name have the same function and must be
-; treated the same in each function:
-; AgesaAllocateBuffer
-; AgesaDeallocateBuffer
-; AgesaLocateBuffer
-; AgesaRunFcnOnAp
-;
-EXTERN myLocateBuffer:NEAR
-
-
-;+---------------------------------------------------------------------------
-;
-; myRunFuncOnAp (Required)
-;
-; Entry:
-; EDX - Local APIC ID of the target core.
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; The host environment must route execution to the target AP and
-; have that AP call the AmdLateRunApTaskWrapper routine defined
-; above.
-;
-; Dependencies:
-; None
-;
-EXTERN myRunFuncOnAp:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; mySaveNonVolatileS3Context (Required for proper S3 operation)
-;
-; Entry:
-; EBX - Pointer to the non-volatile S3 context block
-; ECX - Size in bytes of the non-volatile S3 context block
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; The host environment must save the non-volatile data to an area
-; that will not lose context while in the ACPI S3 sleep state, but
-; cannot be placed in system RAM. This data will need to be
-; available during the call to AmdInitResume.
-;
-; Dependencies:
-; None
-;
-EXTERN mySaveNonVolatileS3Context:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; mySaveVolatileS3Context (Required for proper S3 operation)
-;
-; Entry:
-; EBX - Pointer to the volatile S3 context block
-; ECX - Size in bytes of the volatile S3 context block
-;
-; Exit:
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; The host environment must save the volatile data to an area
-; that will not lose context while in the ACPI S3 sleep state.
-; This data will need to be available during the call to
-; AmdS3LateRestore.
-;
-; Dependencies:
-; None
-;
-EXTERN mySaveVolatileS3Context:NEAR
-
-;+---------------------------------------------------------------------------
-;
-; myGetVolatileS3Context (Required for proper S3 operation)
-;
-; Entry:
-; None
-;
-; Exit:
-; EBX - Pointer to the volatile S3 context block
-; ECX - Size in bytes of the volatile S3 context block
-;
-; Modified:
-; None
-;
-; Purpose:
-; The host environment must return the pointer to the data
-; saved during the mySaveVolatileS3Context routine.
-;
-; Dependencies:
-; None
-;
-EXTERN myGetVolatileS3Context:NEAR
-
-
-;----------------------------------------------------------------------------
-; Define the sample wrapper routines for the POST segment
-;----------------------------------------------------------------------------
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitEnvWrapper
-;
-; Entry:
-; On Entry to "AmdInitEnv" AGESA will display AGESA_TESTPOINT - C8h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitEnv" AGESA will display AGESA_TESTPOINT - C9h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure uses the AgesaAllocateBuffer call-out to acquire
-; permanent buffer space for the UEFI Hand-Off Blocks (HOBs). This
-; is also known as, or includes, artifact data being used by the
-; AGESA software. Upon entry to this procedure, the data is being
-; held in a temporary memory location and it must be moved to a
-; location controlled and protected by the host environment.
-;
-; These actions are performed by the BSP. The APs are not assigned
-; any tasks at this time point.
-;
-; Dependencies:
-; This procedure must be called after full memory is initialized and
-; the host environment has taken control of main memory allocation.
-; This procedure should be called before the PCI enumeration takes
-; place and as soon as possible after the host environment memory
-; allocation sub-system has started.
-;
-; This procedure requires a stack. The host environment must use one
-; of the provided service functions to establish the stack environment
-; prior to making the call to this procedure.
-;
-AmdInitEnvWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitEnv
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_ENV
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, SIZEOF AMD_CONFIG_PARAMS
- call oemPlatformConfigInit
-
- ; Call in to the AmdInitEnv entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
- ;; AGESA_ERROR The artifact data could not be found or the host
- ;; environment failed to allocate sufficient buffer space.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_ENV_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdInitEnv
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
-
- popad
- ret
-AmdInitEnvWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitMidWrapper
-;
-; Entry:
-; On Entry to "AmdInitMid" AGESA will display AGESA_TESTPOINT - CAh
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitMid" AGESA will display AGESA_TESTPOINT - CBh
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure call performs special configuration requirements for
-; the graphics display hardware.
-;
-; These actions are performed by the BSP. The APs are not assigned any
-; tasks at this time point.
-;
-; Dependencies:
-; This procedure must be called after PCI enumeration has allocated
-; resources, but before the video BIOS call is performed.
-;
-; This procedure requires a stack. The host environment must use one
-; of the provided service functions to establish the stack environment
-; prior to making the call to this procedure.
-;
-AmdInitMidWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitMid
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_MID
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, SIZEOF AMD_CONFIG_PARAMS
- call oemPlatformConfigInit
-
- ; Call in to the AmdInitMid entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_MID_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdInitMid
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
-
- popad
- ret
-
-AmdInitMidWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdInitLateWrapper
-;
-; Entry:
-; On Entry to "AmdInitLate" AGESA will display AGESA_TESTPOINT - CCh
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdInitLate" AGESA will display AGESA_TESTPOINT - CDh
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; The main purpose of this function is to generate informational
-; data tables used by the operating system. The individual tables
-; can be selected for generation through the user selection entries
-; on the input parameters.
-;
-; This routine uses the Call-Out AgesaAllocateBuffer to allocate a
-; buffer of the proper size to contain the data.
-;
-; The code path separates the BSP from the APs and perform a separate
-; and appropriate list of tasks for each class of core.
-; For the BSP, the following actions are performed:
-; Allocate buffer space for the tables.
-; Generate the table contents.
-; Make sure that the CPU is in a known good power state before
-; proceeding to boot the OS.
-; For the APs, the following actions are performed:
-; Final register settings preparing for entry to OS.
-; Establish the final PState for entry to OS.
-;
-; Dependencies:
-; This routine is expected to be executed late in the boot sequence
-; after main memory has been initialized, after PCI enumeration has
-; completed, after the host environment ACPI sub-system has started,
-; after the host environment has taken control of the APs, but just
-; before the start of OS boot.
-;
-; The host environment must provide the required call-outs listed in
-; the "Required Call-Out Procedures" section of the AGESA interface
-; specification to provide the buffer space in main memory and execute
-; code on the APs. The host environment must register the created ACPI
-; table in the main ACPI pointer tables. This may require moving the
-; generated tables to another location in memory.
-;
-; This procedure requires a stack. The host environment must establish
-; the stack environment prior to making the call to this procedure.
-; Some functions depend upon the preservation of the heap data across
-; the shift from pre-memory environment to a post-memory environment.
-; If that data was not preserved, then those functions cannot complete
-; and an error is returned.
-;
-AmdInitLateWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdInitLate
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_LATE
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, SIZEOF AMD_CONFIG_PARAMS
- call oemPlatformConfigInit
-
- ; Call in to the AmdInitLate entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS The function has completed successfully.
- ;; AGESA_ALERT
- ;; AGESA_ERROR The system could not allocate the needed amount of
- ;; buffer space; or could not locate the artifact data block in
- ;; memory. Likely cause: the host environment may not have preserved
- ;; the data properly.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_LATE_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- push es
- mov ax, SEG AmdAcpiSratPointer
- mov es, ax
-
- mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiSrat
- mov es:AmdAcpiSratPointer, ebx
- mov eax, DWORD PTR [ebx + 4]
- mov es:AmdAcpiSratSize, eax
-
- mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiSlit
- mov es:AmdAcpiSlitPointer, ebx
- mov eax, DWORD PTR [ebx + 4]
- mov es:AmdAcpiSlitSize, eax
-
- mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiPState
- mov es:AmdAcpiSsdtPointer, ebx
- mov eax, DWORD PTR [ebx + 4]
- mov es:AmdAcpiSsdtSize, eax
-
- xor eax, eax
-
- mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiWheaMce
- mov es:AmdAcpiWheaMcePointer, ebx
- mov ax, WORD PTR [ebx]
- mov es:AmdAcpiWheaMceSize, eax
-
- mov ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiWheaMce
- mov es:AmdAcpiWheaCmcPointer, ebx
- mov ax, WORD PTR [ebx]
- mov es:AmdAcpiWheaCmcSize, eax
-
- mov eax, (AMD_LATE_PARAMS ptr [esi]).DmiTable
- mov es:AmdDmiInfoPointer, eax
- pop es
-
-
- ; Allow AGESA to free the space used by AmdInitLate
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
- popad
- ret
-
-AmdInitLateWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdS3SaveWrapper
-;
-; Entry:
-; On Entry to "AmdS3Save" AGESA will display AGESA_TESTPOINT - CEh
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Entry to "AmdS3Save" AGESA will display AGESA_TESTPOINT - CFh
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure saves critical registers and/or configuration
-; information for preservation across a system suspend mode. All
-; actions needed to prepare the processor for suspend mode is
-; performed, however this procedure does NOT initiate the suspend
-; process. The host environment is expected to perform that duty.
-;
-; These actions are performed by the BSP. The APs are not assigned
-; any tasks at this time point.
-;
-; The initializer routine will NULL out the save area pointers and
-; sizes. This procedure will determine the size of storage needed
-; for all the processor context, and make a call out to the environment
-; for allocation of one buffer to store all of the data. Upon exit, the
-; pointers and sizes within the AMD_S3_PARAMS structure will be updated
-; with the appropriate addresses within the buffer that was allocated.
-; The host environment is expected to then transfer the data pointed to
-; by NvStorage to a non-volatile storage area, and the data pointed to
-; by VolatileStorage to either a non-volatile storage area or system
-; RAM that retains its content across suspend.
-;
-; Dependencies:
-; The host environment must initiate the suspend process.
-;
-; This procedure requires a stack. The host environment must establish
-; the stack environment prior to making the call to this procedure.
-;
-AmdS3SaveWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdS3Save
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_S3_SAVE
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, (SIZEOF AMD_CONFIG_PARAMS + SIZEOF AMD_S3_PARAMS)
- call oemPlatformConfigInit
-
- ; Call in to the AmdS3Save entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS All suspend duties have been completed successfully.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_S3SAVE_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- mov ecx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.NvStorageSize
- .if (ecx != 0)
- mov ebx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.NvStorage
- call mySaveNonVolatileS3Context
- .endif
-
- mov ecx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.VolatileStorageSize
- .if (ecx != 0)
- mov ebx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.VolatileStorage
- call mySaveVolatileS3Context
- .endif
-
- ; Allow AGESA to free the space used by AmdS3Save
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
- popad
- ret
-
-AmdS3SaveWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdS3LateRestoreWrapper
-;
-; Entry:
-; On Entry to "AmdS3LateRestore" AGESA will display AGESA_TESTPOINT - D2h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; On Exit from "AmdS3LateRestore" AGESA will display AGESA_TESTPOINT - D3h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This procedure restores the processor state, reloads critical
-; silicon component registers, and performs any re-initialization
-; required by the silicon. This procedure will use the context data
-; in the VolatileStorage area of the input structure to restore the
-; processor registers.
-;
-; The host environment must fill the AMD_S3_PARAMS NvStorage and
-; VolatileStorage pointers and related size elements to describe
-; the location of the context data. Note that for this procedure,
-; the two data areas do not need to be contained in one buffer zone,
-; they can be anywhere in the accessible memory address space. If
-; the host environment uses a non-volatile storage device accessed
-; on the system address bus such as flashROM, then the context data
-; does not need to be moved prior to this call. If the host
-; environment uses a non-volatile storage device not located on the
-; system address bus (e.g. CMOS or SSEPROM) then the host environment
-; must transfer the context data to a buffer in main memory prior to
-; calling this procedure.
-;
-; These actions are performed by the BSP. The APs are not assigned
-; any tasks at this time point.
-;
-; Dependencies:
-; This procedure is called late in the resume sequence, after the
-; PCI control space is restored and just before resuming operating
-; system execution.
-;
-; The host environment must initiate the OS restart process.
-;
-; This procedure requires a stack. The host environment must establish
-; the stack environment prior to making the call to this procedure.
-;
-AmdS3LateRestoreWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdS3LateRestore
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_S3LATE_RESTORE
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- mov edi, esi
- add edi, (SIZEOF AMD_CONFIG_PARAMS + SIZEOF AMD_S3_PARAMS)
- call oemPlatformConfigInit
-
- call myGetVolatileS3Context
- mov (AMD_S3LATE_PARAMS ptr [esi]).S3DataBlock.VolatileStorage, ebx
- mov (AMD_S3LATE_PARAMS ptr [esi]).S3DataBlock.VolatileStorageSize, ecx
-
- ; Call in to the AmdS3LateRestore entry point
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- ;; AGESA_SUCCESS All resume processes have been completed successfully.
-
- .if (eax != AGESA_SUCCESS)
- mov al, (AMD_S3LATE_PARAMS ptr [esi]).StdHeader.HeapStatus
- mov ebx, AGESA_B2_ADDRESS
- call AmdProcessAgesaErrors
- .endif
-
- ; Allow AGESA to free the space used by AmdS3LateRestore
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
- popad
- ret
-AmdS3LateRestoreWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdLateRunApTaskWrapper
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - D4h
-; DS - 0000 with 4 gigabyte access
-; ES - 0000 with 4 gigabyte access
-;
-; Exit:
-; After this hook, AGESA will display - AGESA_TESTPOINT - D5h
-; None
-;
-; Modified:
-; None
-;
-; Purpose:
-; This entry point is tightly connected with the "AgesaRunFcnOnAp"
-; call out. The AGESA software will call the call-out "AgesaRunFcnOnAp";
-; the host environment will then call this entry point to have the AP
-; execute the requested function. This is needed late in the Post and
-; Resume branches for running an AP task since the AGESA software has
-; relinquished control of the APs to the host environment.
-;
-; Dependencies:
-; The host environment must implement the"AgesaRunFcnOnAp" call-out
-; and route execution to the target AP.
-;
-AmdLateRunApTaskWrapper PROC NEAR PUBLIC
- local localCfgBlock:AMD_INTERFACE_PARAMS
-
- pushad
-
- ; Prepare for the call to create and initialize the input parameters for AmdLateRunApTask
- xor eax, eax
- mov ax, ss
- shl eax, 4
- lea esi, localCfgBlock
- add esi, eax
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
- mov edx, SEG AmdCallout16
- shl edx, 4
- add edx, OFFSET AmdCallout16
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
-
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_LATE_RUN_AP_TASK
- mov (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
- mov (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
- push esi
- mov dx, SEG AmdCalloutRouterPost
- shl edx, 16
- mov dx, OFFSET AmdCalloutRouterPost
- push edx
- call AmdBridge32
- pop edx
-
- mov esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
-
- ; The structure has been initialized. Now modify the default settings as desired.
-
- push es
- mov ax, SEG AmdRunCodeOnApDataPointer
- mov es, ax
- mov eax, es:AmdRunCodeOnApDataPointer
- mov (AP_EXE_PARAMS PTR [esi]).RelatedDataBlock, eax
- mov eax, es:AmdRunCodeOnApDataSize
- mov (AP_EXE_PARAMS PTR [esi]).RelatedBlockLength, eax
- mov eax, es:AmdRunCodeOnApFunction
- mov (AP_EXE_PARAMS PTR [esi]).FunctionNumber, eax
- pop es
-
- ; Call in to the AmdLateRunApTask dispatcher
- push edx
- call AmdBridge32
- pop edx
-
- ;; EAX = AGESA_STATUS
- push es
- mov bx, SEG AmdRunCodeOnApStatus
- mov es, bx
- mov es:AmdRunCodeOnApStatus, eax
- pop es
-
- ; Allow AGESA to free the space used by AmdLateRunApTask
- pop esi
- mov (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
- call AmdBridge32
-
- popad
- ret
-
-AmdLateRunApTaskWrapper ENDP
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdRunFuncOnAp (Required)
-;
-; Entry:
-; Prior to this hook, AGESA will display - AGESA_TESTPOINT - E8h
-; EDX - Local APIC ID of the target core.
-; ESI - Pointer to an AP_EXE_PARAMS structure.
-;
-; typedef struct {
-; IN OUT AMD_CONFIG_PARAMS StdHeader;
-; IN UINT32 FunctionNumber;
-; IN VOID *RelatedDataBlock;
-; IN UINT32 RelatedDataBlockLength;
-; } AP_EXE_PARAMS;
-;
-; Exit:
-; After this hook, AGESA will display - AGESA_TESTPOINT - E9h
-; EAX - Contains the AGESA_STATUS return code.
-; AGESA_SUCCESS The function has completed successfully.
-; AGESA_UNSUPPORTED This is a required function, so this value
-; being returned causes a critical error
-; response value from the AGESAT software
-; function and no memory initialized.
-; AGESA_WARNING The AP did not respond.
-;
-; Modified:
-; EAX
-;
-; Purpose:
-; This function is used after main memory has been initialized
-; and the host environment has taken control of AP task dispatching.
-; This function must cause the indicated function code to be executed
-; upon the specified Application Processor. This procedure must be
-; executed in 32-bit mode. This function is required to be implemented
-; in the host environment.
-;
-; Dependencies:
-; The host environment must route execution to the target AP and
-; have that AP call the"AmdLateRunApTask" entry point.
-;
-AmdRunFuncOnAp PROC NEAR PUBLIC
-
- push es
- mov ax, SEG AmdRunCodeOnApDataPointer
- mov es, ax
- mov eax, (AP_EXE_PARAMS PTR [esi]).RelatedDataBlock
- mov es:AmdRunCodeOnApDataPointer, eax
- mov eax, (AP_EXE_PARAMS PTR [esi]).RelatedBlockLength
- mov es:AmdRunCodeOnApDataSize, eax
- mov eax, (AP_EXE_PARAMS PTR [esi]).FunctionNumber
- mov es:AmdRunCodeOnApFunction, eax
- mov eax, AGESA_UNSUPPORTED
- mov es:AmdRunCodeOnApStatus, eax
- pop es
-
- call myRunFuncOnAp
-
- push es
- mov ax, SEG AmdRunCodeOnApStatus
- mov es, ax
- mov eax, es:AmdRunCodeOnApStatus
- pop es
- ret
-AmdRunFuncOnAp ENDP
-
-
-
-;+---------------------------------------------------------------------------
-;
-; AmdCalloutRouterPost
-;
-; Entry:
-; ECX - Callout function number
-; EDX - Function-specific UINTN
-; ESI - Pointer to function specific data
-;
-; Exit:
-; EAX - Contains the AGESA_STATUS return code.
-;
-; Modified:
-; None
-;
-; Purpose:
-; The call out router function for AmdInitEnv,
-; AmdInitMid, AmdInitLate, AmdS3Save, and
-; AmdS3LateRestore.
-;
-; Dependencies:
-; None
-;
-AmdCalloutRouterPost PROC FAR PUBLIC USES ECX EBX ESI BX DI DS ES
- xor ax, ax
- mov ds, ax
- mov es, ax
- lea di, cs:CalloutRouterTablePost
- mov eax, AGESA_UNSUPPORTED
-
-loopThruTable:
- cmp di, OFFSET cs:CalloutRouterTablePostEnd
- jae amdCpuCalloutExit ; exit with AGESA_UNSUPPORTED
- cmp ecx, cs:[di].sOemCallout.FuncName
- je FoundMatch
- add di, SIZEOF sOemCallout
- jmp loopThruTable
-
-FoundMatch:
- mov bx, cs:[di].sOemCallout.FuncPtr
- call bx
-
-amdCpuCalloutExit:
- ret
-AmdCalloutRouterPost ENDP
-
-
-;----------------------------------------------------------------------------
-; Define the callout dispatch table for the POST segment
-;----------------------------------------------------------------------------
-
-CalloutRouterTablePost LABEL BYTE
- ;; Add entries as desired.
- sOemCallout <AGESA_ALLOCATE_BUFFER, OFFSET myAllocateBuffer>
- sOemCallout <AGESA_DEALLOCATE_BUFFER, OFFSET myDeallocateBuffer>
- sOemCallout <AGESA_LOCATE_BUFFER, OFFSET myLocateBuffer>
- sOemCallout <AGESA_RUNFUNC_ONAP, OFFSET AmdRunFuncOnAp>
-CalloutRouterTablePostEnd LABEL BYTE
-
-AMD_POST_END
-
-
-;----------------------------------------------------------------------------
-; CPU DATA SEGMENT
-; This segment must be writable, and present at the time that
-; AmdInitLate is run.
-;----------------------------------------------------------------------------
-
-CPU_DATASEG_START
-
- ;; Data used to store pointers for later use by the host environment.
- PUBLIC AmdAcpiSratPointer
- PUBLIC AmdAcpiSratSize
- PUBLIC AmdAcpiSlitPointer
- PUBLIC AmdAcpiSlitSize
- PUBLIC AmdAcpiSsdtPointer
- PUBLIC AmdAcpiSsdtSize
- PUBLIC AmdAcpiWheaMcePointer
- PUBLIC AmdAcpiWheaMceSize
- PUBLIC AmdAcpiWheaCmcPointer
- PUBLIC AmdAcpiWheaCmcSize
- PUBLIC AmdDmiInfoPointer
- AmdAcpiSratPointer DWORD ?
- AmdAcpiSratSize DWORD ?
- AmdAcpiSlitPointer DWORD ?
- AmdAcpiSlitSize DWORD ?
- AmdAcpiSsdtPointer DWORD ?
- AmdAcpiSsdtSize DWORD ?
- AmdAcpiWheaMcePointer DWORD ?
- AmdAcpiWheaMceSize DWORD ?
- AmdAcpiWheaCmcPointer DWORD ?
- AmdAcpiWheaCmcSize DWORD ?
- AmdDmiInfoPointer DWORD ?
-
- ;; Data used for communication between the AP and the BSP.
- PUBLIC AmdRunCodeOnApDataPointer
- PUBLIC AmdRunCodeOnApDataSize
- PUBLIC AmdRunCodeOnApFunction
- PUBLIC AmdRunCodeOnApStatus
- AmdRunCodeOnApDataPointer DWORD ?
- AmdRunCodeOnApDataSize DWORD ?
- AmdRunCodeOnApFunction DWORD ?
- AmdRunCodeOnApStatus DWORD ?
-
-CPU_DATASEG_END
-
-
-END
diff --git a/src/vendorcode/amd/agesa/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/Legacy/Proc/hobTransfer.c
deleted file mode 100644
index d205b54..0000000
--- a/src/vendorcode/amd/agesa/Legacy/Proc/hobTransfer.c
+++ /dev/null
@@ -1,394 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Hob Transfer functions.
- *
- * Contains code that copy Heap to temp memory or main memory.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "GeneralServices.h"
-#include "cpuServices.h"
-#include "cpuCacheInit.h"
-#include "cpuFamilyTranslation.h"
-#include "heapManager.h"
-#include "cpuLateInit.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE LEGACY_PROC_HOBTRANSFER_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P U B L I C F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-extern BUILD_OPT_CFG UserOptions;
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * CopyHeapToTempRamAtPost
- *
- * This function copies BSP heap content to RAM
- *
- * @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct.
- *
- * @retval AGESA_STATUS
- *
- */
-AGESA_STATUS
-CopyHeapToTempRamAtPost (
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 *BaseAddressInCache;
- UINT8 *BaseAddressInTempMem;
- UINT8 *Source;
- UINT8 *Destination;
- UINT8 AlignTo16ByteInCache;
- UINT8 AlignTo16ByteInTempMem;
- UINT8 Ignored;
- UINT32 SizeOfNodeData;
- UINT32 TotalSize;
- UINT32 HeapRamFixMtrr;
- UINT32 HeapRamVariableMtrr;
- UINT32 HeapInCacheOffset;
- UINT64 MsrData;
- UINT64 VariableMtrrBase;
- UINT64 VariableMtrrMask;
- UINTN AmdHeapRamAddress;
- AGESA_STATUS IgnoredStatus;
- BUFFER_NODE *HeapInCache;
- BUFFER_NODE *HeapInTempMem;
- HEAP_MANAGER *HeapManagerInCache;
- HEAP_MANAGER *HeapManagerInTempMem;
- CACHE_INFO *CacheInfoPtr;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
-
- AmdHeapRamAddress = (UINTN) UserOptions.CfgHeapDramAddress;
- //
- //If the user define address above 1M, Mem Init has already set
- //whole available memory as WB cacheable.
- //
- if (AmdHeapRamAddress < 0x100000) {
- // Region below 1MB
- // Fixed MTTR region
- // turn on modification bit
- LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
- MsrData |= 0x80000;
- LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
-
- if (AmdHeapRamAddress >= 0xC0000) {
- //
- // 0xC0000 ~ 0xFFFFF
- //
- HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX4k_C0000 + (((AmdHeapRamAddress >> 16) & 0x3) * 2));
- MsrData = AMD_MTRR_FIX4K_UC_DRAM;
- LibAmdMsrWrite (HeapRamFixMtrr, &MsrData, StdHeader);
- LibAmdMsrWrite ((HeapRamFixMtrr + 1), &MsrData, StdHeader);
- } else if (AmdHeapRamAddress >= 0x80000) {
- //
- // 0x80000~0xBFFFF
- //
- HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX16k_80000 + ((AmdHeapRamAddress >> 17) & 0x1));
- MsrData = AMD_MTRR_FIX16K_UC_DRAM;
- LibAmdMsrWrite (HeapRamFixMtrr, &MsrData, StdHeader);
- } else {
- //
- // 0x0 ~ 0x7FFFF
- //
- LibAmdMsrRead (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader);
- MsrData = MsrData & (~(0xFF << (8 * ((AmdHeapRamAddress >> 16) & 0x7))));
- MsrData = MsrData | (AMD_MTRR_FIX64K_UC_DRAM << (8 * ((AmdHeapRamAddress >> 16) & 0x7)));
- LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader);
- }
-
- // Turn on MTTR enable bit and turn off modification bit
- LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
- MsrData |= 0x40000;
- MsrData &= 0xFFFFFFFFFFF7FFFF;
- LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
- } else {
- // Region above 1MB
- // Variable MTTR region
- // Get family specific cache Info
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
- FamilySpecificServices->GetCacheInfo (FamilySpecificServices, &CacheInfoPtr, &Ignored, StdHeader);
-
- // Find an empty MTRRphysBase/MTRRphysMask
- for (HeapRamVariableMtrr = AMD_MTRR_VARIABLE_HEAP_BASE;
- HeapRamVariableMtrr >= AMD_MTRR_VARIABLE_BASE0;
- HeapRamVariableMtrr--) {
- LibAmdMsrRead (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader);
- LibAmdMsrRead ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader);
- if ((VariableMtrrBase == 0) && (VariableMtrrMask == 0)) {
- break;
- }
- }
- if (HeapRamVariableMtrr < AMD_MTRR_VARIABLE_BASE0) {
- // All variable MTRR is used.
- ASSERT (FALSE);
- }
-
- // Set variable MTRR base and mask
- // If the address ranges of two or more MTRRs overlap
- // and if at least one of the memory types is UC, the UC memory type is used.
- VariableMtrrBase = (UINT64) (AmdHeapRamAddress & CacheInfoPtr->HeapBaseMask);
- VariableMtrrMask = CacheInfoPtr->VariableMtrrHeapMask & AMD_HEAP_MTRR_MASK;
- LibAmdMsrWrite (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader);
- LibAmdMsrWrite ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader);
- }
- // Copying Heap content
- if (IsBsp (StdHeader, &IgnoredStatus)) {
- TotalSize = sizeof (HEAP_MANAGER);
- SizeOfNodeData = 0;
- AlignTo16ByteInTempMem = 0;
- BaseAddressInCache = (UINT8 *) StdHeader->HeapBasePtr;
- HeapManagerInCache = (HEAP_MANAGER *) BaseAddressInCache;
- HeapInCacheOffset = HeapManagerInCache->FirstActiveBufferOffset;
- HeapInCache = (BUFFER_NODE *) (BaseAddressInCache + HeapInCacheOffset);
-
- BaseAddressInTempMem = (UINT8 *) UserOptions.CfgHeapDramAddress;
- HeapManagerInTempMem = (HEAP_MANAGER *) BaseAddressInTempMem;
- HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize);
-
- // copy heap from cache to temp memory.
- // only heap with persist great than HEAP_LOCAL_CACHE will be copied.
- // Note: Only copy heap with persist greater than HEAP_LOCAL_CACHE.
- while (HeapInCacheOffset != AMD_HEAP_INVALID_HEAP_OFFSET) {
- if (HeapInCache->Persist > HEAP_LOCAL_CACHE) {
- AlignTo16ByteInCache = HeapInCache->PadSize;
- AlignTo16ByteInTempMem = (UINT8) ((0x10 - (((UINTN) (VOID *) HeapInTempMem + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL) & 0xF)) & 0xF);
- SizeOfNodeData = HeapInCache->BufferSize - AlignTo16ByteInCache;
- TotalSize = (UINT32) (TotalSize + sizeof (BUFFER_NODE) + SizeOfNodeData + AlignTo16ByteInTempMem);
- Source = (UINT8 *) HeapInCache + sizeof (BUFFER_NODE) + AlignTo16ByteInCache;
- Destination = (UINT8 *) HeapInTempMem + sizeof (BUFFER_NODE) + AlignTo16ByteInTempMem;
- LibAmdMemCopy (HeapInTempMem, HeapInCache, sizeof (BUFFER_NODE), StdHeader);
- LibAmdMemCopy (Destination, Source, SizeOfNodeData, StdHeader);
- HeapInTempMem->OffsetOfNextNode = TotalSize;
- HeapInTempMem->BufferSize = SizeOfNodeData + AlignTo16ByteInTempMem;
- HeapInTempMem->PadSize = AlignTo16ByteInTempMem;
- HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize);
- }
- HeapInCacheOffset = HeapInCache->OffsetOfNextNode;
- HeapInCache = (BUFFER_NODE *) (BaseAddressInCache + HeapInCacheOffset);
- }
- // initialize heap manager
- if (TotalSize == sizeof (HEAP_MANAGER)) {
- // heap is empty
- HeapManagerInTempMem->UsedSize = sizeof (HEAP_MANAGER);
- HeapManagerInTempMem->FirstActiveBufferOffset = AMD_HEAP_INVALID_HEAP_OFFSET;
- HeapManagerInTempMem->FirstFreeSpaceOffset = sizeof (HEAP_MANAGER);
- } else {
- // heap is NOT empty
- HeapManagerInTempMem->UsedSize = TotalSize;
- HeapManagerInTempMem->FirstActiveBufferOffset = sizeof (HEAP_MANAGER);
- HeapManagerInTempMem->FirstFreeSpaceOffset = TotalSize;
- HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize - SizeOfNodeData - AlignTo16ByteInTempMem - sizeof (BUFFER_NODE));
- HeapInTempMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET;
- HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize);
- }
- // heap signature
- HeapManagerInCache->Signature = 0x00000000;
- HeapManagerInTempMem->Signature = HEAP_SIGNATURE_VALID;
- // Free space node
- HeapInTempMem->BufferSize = (UINT32) (AMD_HEAP_SIZE_PER_CORE - TotalSize);
- HeapInTempMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET;
- }
- return AGESA_SUCCESS;
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * CopyHeapToMainRamAtPost
- *
- * This function copies Temp Ram heap content to Main Ram
- *
- * @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct.
- *
- * @retval AGESA_STATUS
- *
- */
-AGESA_STATUS
-CopyHeapToMainRamAtPost (
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 *BaseAddressInTempMem;
- UINT8 *BaseAddressInMainMem;
- UINT8 *Source;
- UINT8 *Destination;
- UINT8 AlignTo16ByteInTempMem;
- UINT8 AlignTo16ByteInMainMem;
- UINT8 Ignored;
- UINT32 SizeOfNodeData;
- UINT32 TotalSize;
- UINT32 HeapInTempMemOffset;
- UINT32 HeapRamVariableMtrr;
- UINT64 VariableMtrrBase;
- UINT64 VariableMtrrMask;
- AGESA_STATUS IgnoredStatus;
- BUFFER_NODE *HeapInTempMem;
- BUFFER_NODE *HeapInMainMem;
- HEAP_MANAGER *HeapManagerInTempMem;
- HEAP_MANAGER *HeapManagerInMainMem;
- AGESA_BUFFER_PARAMS AgesaBuffer;
- CACHE_INFO *CacheInfoPtr;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
-
- if (IsBsp (StdHeader, &IgnoredStatus)) {
- TotalSize = sizeof (HEAP_MANAGER);
- SizeOfNodeData = 0;
- AlignTo16ByteInMainMem = 0;
- BaseAddressInTempMem = (UINT8 *) StdHeader->HeapBasePtr;
- HeapManagerInTempMem = (HEAP_MANAGER *) StdHeader->HeapBasePtr;
- HeapInTempMemOffset = HeapManagerInTempMem->FirstActiveBufferOffset;
- HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + HeapInTempMemOffset);
-
- AgesaBuffer.StdHeader = *StdHeader;
- AgesaBuffer.BufferHandle = AMD_HEAP_IN_MAIN_MEMORY_HANDLE;
- AgesaBuffer.BufferLength = AMD_HEAP_SIZE_PER_CORE;
- if (AgesaAllocateBuffer (0, &AgesaBuffer) != AGESA_SUCCESS) {
- return AGESA_ERROR;
- }
- BaseAddressInMainMem = (UINT8 *) AgesaBuffer.BufferPointer;
- HeapManagerInMainMem = (HEAP_MANAGER *) BaseAddressInMainMem;
- HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize);
- LibAmdMemFill (BaseAddressInMainMem, 0x00, AMD_HEAP_SIZE_PER_CORE, StdHeader);
- // copy heap from temp memory to main memory.
- // only heap with persist great than HEAP_TEMP_MEM will be copied.
- // Note: Only copy heap buffers with persist greater than HEAP_TEMP_MEM.
- while (HeapInTempMemOffset != AMD_HEAP_INVALID_HEAP_OFFSET) {
- if (HeapInTempMem->Persist > HEAP_TEMP_MEM) {
- AlignTo16ByteInTempMem = HeapInTempMem->PadSize;
- AlignTo16ByteInMainMem = (UINT8) ((0x10 - (((UINTN) (VOID *) HeapInMainMem + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL) & 0xF)) & 0xF);
- SizeOfNodeData = HeapInTempMem->BufferSize - AlignTo16ByteInTempMem;
- TotalSize = (UINT32) (TotalSize + sizeof (BUFFER_NODE) + SizeOfNodeData + AlignTo16ByteInMainMem);
- Source = (UINT8 *) HeapInTempMem + sizeof (BUFFER_NODE) + AlignTo16ByteInTempMem;
- Destination = (UINT8 *) HeapInMainMem + sizeof (BUFFER_NODE) + AlignTo16ByteInMainMem;
- LibAmdMemCopy (HeapInMainMem, HeapInTempMem, sizeof (BUFFER_NODE), StdHeader);
- LibAmdMemCopy (Destination, Source, SizeOfNodeData, StdHeader);
- HeapInMainMem->OffsetOfNextNode = TotalSize;
- HeapInMainMem->BufferSize = SizeOfNodeData + AlignTo16ByteInMainMem;
- HeapInMainMem->PadSize = AlignTo16ByteInMainMem;
- HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize);
- }
- HeapInTempMemOffset = HeapInTempMem->OffsetOfNextNode;
- HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + HeapInTempMemOffset);
- }
- // initialize heap manager
- if (TotalSize == sizeof (HEAP_MANAGER)) {
- // heap is empty
- HeapManagerInMainMem->UsedSize = sizeof (HEAP_MANAGER);
- HeapManagerInMainMem->FirstActiveBufferOffset = AMD_HEAP_INVALID_HEAP_OFFSET;
- HeapManagerInMainMem->FirstFreeSpaceOffset = sizeof (HEAP_MANAGER);
- } else {
- // heap is NOT empty
- HeapManagerInMainMem->UsedSize = TotalSize;
- HeapManagerInMainMem->FirstActiveBufferOffset = sizeof (HEAP_MANAGER);
- HeapManagerInMainMem->FirstFreeSpaceOffset = TotalSize;
- HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize - SizeOfNodeData - AlignTo16ByteInMainMem - sizeof (BUFFER_NODE));
- HeapInMainMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET;
- HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize);
- }
- // heap signature
- HeapManagerInTempMem->Signature = 0x00000000;
- HeapManagerInMainMem->Signature = HEAP_SIGNATURE_VALID;
- // Free space node
- HeapInMainMem->BufferSize = AMD_HEAP_SIZE_PER_CORE - TotalSize;
- HeapInMainMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET;
- }
- // if address of heap in temp memory is above 1M, then we must used one variable MTRR.
- if (StdHeader->HeapBasePtr >= 0x100000) {
- // Find out which variable MTRR was used in CopyHeapToTempRamAtPost.
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
- FamilySpecificServices->GetCacheInfo (FamilySpecificServices, &CacheInfoPtr, &Ignored, StdHeader);
- for (HeapRamVariableMtrr = AMD_MTRR_VARIABLE_HEAP_BASE;
- HeapRamVariableMtrr >= AMD_MTRR_VARIABLE_BASE0;
- HeapRamVariableMtrr--) {
- LibAmdMsrRead (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader);
- LibAmdMsrRead ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader);
- if ((VariableMtrrBase == (UINT64) (StdHeader->HeapBasePtr & CacheInfoPtr->HeapBaseMask)) &&
- (VariableMtrrMask == (UINT64) (CacheInfoPtr->VariableMtrrHeapMask & AMD_HEAP_MTRR_MASK))) {
- break;
- }
- }
- if (HeapRamVariableMtrr >= AMD_MTRR_VARIABLE_BASE0) {
- // Clear variable MTRR which set in CopyHeapToTempRamAtPost.
- VariableMtrrBase = 0;
- VariableMtrrMask = 0;
- LibAmdMsrWrite (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader);
- LibAmdMsrWrite ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader);
- }
- }
- return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/Legacy/agesa.inc b/src/vendorcode/amd/agesa/Legacy/agesa.inc
deleted file mode 100644
index 65dd0ef..0000000
--- a/src/vendorcode/amd/agesa/Legacy/agesa.inc
+++ /dev/null
@@ -1,2547 +0,0 @@
-; ****************************************************************************
-; *
-; * @file
-; *
-; * Agesa structures and definitions
-; *
-; * Contains AMD AGESA core interface
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Include
-; * @e \$Revision: 41505 $ @e \$Date: 2010-11-05 22:06:20 +0800 (Fri, 05 Nov 2010) $
-;
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
-INCLUDE amd.inc
-UINT64 TEXTEQU <QWORD>
-UINT32 TEXTEQU <DWORD>
-UINT16 TEXTEQU <WORD>
-UINT8 TEXTEQU <BYTE>
-CHAR8 TEXTEQU <BYTE>
-BOOLEAN TEXTEQU <BYTE>
-POINTER TEXTEQU <DWORD>
-
- ; AGESA Types and Definitions
-
-
-
- ; AGESA BASIC CALLOUTS
- AGESA_MEM_RELEASE EQU 00028000h
-
- ; AGESA ADVANCED CALLOUTS, Processor
- AGESA_CHECK_UMA EQU 00028100h
- AGESA_DO_RESET EQU 00028101h
- AGESA_ALLOCATE_BUFFER EQU 00028102h
- AGESA_DEALLOCATE_BUFFER EQU 00028103h
- AGESA_LOCATE_BUFFER EQU 00028104h
- AGESA_RUNFUNC_ONAP EQU 00028105h
-
- ; AGESA ADVANCED CALLOUTS, HyperTransport
-
- ; AGESA ADVANCED CALLOUTS, Memory
- AGESA_READ_SPD EQU 00028140h
- AGESA_HOOKBEFORE_DRAM_INIT EQU 00028141h
- AGESA_HOOKBEFORE_DQS_TRAINING EQU 00028142h
- AGESA_READ_SPD_RECOVERY EQU 00028143h
- AGESA_HOOKBEFORE_EXIT_SELF_REF EQU 00028144h
- AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY EQU 00028145h
-
- ; AGESA IDS CALLOUTS
- AGESA_GET_IDS_INIT_DATA EQU 00028200h
-
- ; AGESA GNB CALLOUTS
- AGESA_GNB_PCIE_SLOT_RESET EQU 00028301h
-; ------------------------------------------------------------------------
-
- ; HyperTransport Interface
-
-
-
-; -----------------------------------------------------------------------------
- ; HT DEFINITIONS AND MACROS
-
-; -----------------------------------------------------------------------------
-
-
- ; Width equates for call backs
- HT_WIDTH_8_BITS EQU 8
- HT_WIDTH_16_BITS EQU 16
- HT_WIDTH_4_BITS EQU 4
- HT_WIDTH_2_BITS EQU 2
- HT_WIDTH_NO_LIMIT EQU HT_WIDTH_16_BITS
-
- ; Frequency Limit equates for call backs which take a frequency supported mask.
- HT_FREQUENCY_LIMIT_200M EQU 1
- HT_FREQUENCY_LIMIT_400M EQU 7
- HT_FREQUENCY_LIMIT_600M EQU 1Fh
- HT_FREQUENCY_LIMIT_800M EQU 3Fh
- HT_FREQUENCY_LIMIT_1000M EQU 7Fh
- HT_FREQUENCY_LIMIT_HT1_ONLY EQU 7Fh
- HT_FREQUENCY_LIMIT_1200M EQU 0FFh
- HT_FREQUENCY_LIMIT_1400M EQU 1FFh
- HT_FREQUENCY_LIMIT_1600M EQU 3FFh
- HT_FREQUENCY_LIMIT_1800M EQU 7FFh
- HT_FREQUENCY_LIMIT_2000M EQU 0FFFh
- HT_FREQUENCY_LIMIT_2200M EQU 1FFFh
- HT_FREQUENCY_LIMIT_2400M EQU 3FFFh
- HT_FREQUENCY_LIMIT_2600M EQU 7FFFh
- HT_FREQUENCY_LIMIT_2800M EQU 27FFFh
- HT_FREQUENCY_LIMIT_3000M EQU 67FFFh
- HT_FREQUENCY_LIMIT_3200M EQU 0E7FFFh
- HT_FREQUENCY_LIMIT_3600M EQU 1E7FFFh
- HT_FREQUENCY_LIMIT_MAX EQU HT_FREQUENCY_LIMIT_3600M
- HT_FREQUENCY_NO_LIMIT EQU 0FFFFFFFFh
-
- ; Unit ID Clumping special values
- HT_CLUMPING_DISABLE EQU 00000000h
- HT_CLUMPING_NO_LIMIT EQU 0FFFFFFFFh
-
- HT_LIST_TERMINAL EQU 0FFh
- HT_LIST_MATCH_ANY EQU 0FEh
- HT_LIST_MATCH_INTERNAL_LINK EQU 0FDh
-
- ; Event Notify definitions
-
- ; Event definitions.
-
- ; Coherent subfunction events
- HT_EVENT_COH_EVENTS EQU 10001000h
- HT_EVENT_COH_NO_TOPOLOGY EQU 10011000h
- HT_EVENT_COH_OBSOLETE000 EQU 10021000h
- HT_EVENT_COH_PROCESSOR_TYPE_MIX EQU 10031000h
- HT_EVENT_COH_NODE_DISCOVERED EQU 10041000h
- HT_EVENT_COH_MPCAP_MISMATCH EQU 10051000h
-
- ; Non-coherent subfunction events
- HT_EVENT_NCOH_EVENTS EQU 10002000h
- HT_EVENT_NCOH_BUID_EXCEED EQU 10012000h
- HT_EVENT_NCOH_OBSOLETE000 EQU 10022000h
- HT_EVENT_NCOH_BUS_MAX_EXCEED EQU 10032000h
- HT_EVENT_NCOH_CFG_MAP_EXCEED EQU 10042000h
- HT_EVENT_NCOH_DEVICE_FAILED EQU 10052000h
- HT_EVENT_NCOH_AUTO_DEPTH EQU 10062000h
-
- ; Optimization subfunction events
- HT_EVENT_OPT_EVENTS EQU 10003000h
- HT_EVENT_OPT_REQUIRED_CAP_RETRY EQU 10013000h
- HT_EVENT_OPT_REQUIRED_CAP_GEN3 EQU 10023000h
- HT_EVENT_OPT_UNUSED_LINKS EQU 10033000h
- HT_EVENT_OPT_LINK_PAIR_EXCEED EQU 10043000h
-
- ; HW Fault events
- HT_EVENT_HW_EVENTS EQU 10004000h
- HT_EVENT_HW_SYNCFLOOD EQU 10014000h
- HT_EVENT_HW_HTCRC EQU 10024000h
-
- ; The Recovery HT component uses 0x10005000 for events.
- ; For consistency, we avoid that range here.
-
- HT_MAX_NC_BUIDS EQU 32
-; ----------------------------------------------------------------------------
- ; HT TYPEDEFS, STRUCTURES, ENUMS
-
-; ----------------------------------------------------------------------------
-MATCHED EQU 0 ; < The link matches the requested customization.
-POWERED_OFF EQU 1 ; < Power the link off.
-UNMATCHED EQU 2 ; < The link should be processed according to normal defaults.
-MaxFinalLinkState EQU 3 ; < Not a final link state, use for limit checking.
-FINAL_LINK_STATE TEXTEQU <DWORD>
-
- ; Swap a device from its current id to a new one.
-
-BUID_SWAP_ITEM STRUCT
- FromId UINT8 ? ; < The device responding to FromId,
- ToId UINT8 ? ; < will be moved to ToId.
-BUID_SWAP_ITEM ENDS
-
-
- ; Each Non-coherent chain may have a list of device swaps. After performing the swaps,
- ; the final in order list of device ids is provided. (There can be more swaps than devices.)
- ; The unused entries in both are filled with 0xFF.
-
-BUID_SWAP_LIST STRUCT
- Swaps BUID_SWAP_ITEM (HT_MAX_NC_BUIDS) DUP ({}) ; < The BUID Swaps to perform
- FinalIds UINT8 (HT_MAX_NC_BUIDS) DUP (?) ; < The ordered final BUIDs, resulting from the swaps
-BUID_SWAP_LIST ENDS
-
-
- ; Control Manual Initialization of Non-Coherent Chains
-
- ; This interface is checked every time a non-coherent chain is
- ; processed. BUID assignment may be controlled explicitly on a
- ; non-coherent chain. Provide a swap list. Swaps controls the
- ; BUID assignment and FinalIds provides the device to device
- ; Linking. Device orientation can be detected automatically, or
- ; explicitly. See interface documentation for more details.
-
- ; If a manual swap list is not supplied,
- ; automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
- ; based on each device's unit count.
-
-MANUAL_BUID_SWAP_LIST STRUCT
- ; Match fields
- Socket UINT8 ? ; < The Socket on which this chain is located
- Link UINT8 ? ; < The Link on the host for this chain
- ; Override fields
- SwapList BUID_SWAP_LIST {} ; < The swap list
-MANUAL_BUID_SWAP_LIST ENDS
-
-
- ; Override options for DEVICE_CAP_OVERRIDE.
-
- ; Specify which override actions should be performed. For Checks, 1 means to check the item
- ; and 0 means to skip the check. For the override options, 1 means to apply the override and
- ; 0 means to ignore the override.
-
-DEVICE_CAP_OVERRIDE_OPTIONS STRUCT
- IsCheckDevVenId UINT32 ?
-; IN UINT32 IsCheckDevVenId:1; ; < Check Match on Device/Vendor id
-; IN UINT32 IsCheckRevision:1; ; < Check Match on device Revision
-; IN UINT32 IsOverrideWidthIn:1; ; < Override Width In
-; IN UINT32 IsOverrideWidthOut:1; ; < Override Width Out
-; IN UINT32 IsOverrideFreq:1; ; < Override Frequency
-; IN UINT32 IsOverrideClumping:1; ; < Override Clumping
-; IN UINT32 IsDoCallout:1; ; < Make the optional callout
-DEVICE_CAP_OVERRIDE_OPTIONS ENDS
-
- ; Override capabilities of a device.
-
- ; This interface is checked once for every Link on every IO device.
- ; Provide the width and frequency capability if needed for this device.
- ; This is used along with device capabilities, the limit interfaces, and northbridge
- ; limits to compute the default settings. The components of the device's PCI config
- ; address are provided, so its settings can be consulted if need be.
- ; The optional callout is a catch all.
-
-DEVICE_CAP_OVERRIDE STRUCT
- ; Match fields
- HostSocket UINT8 ? ; < The Socket on which this chain is located.
- HostLink UINT8 ? ; < The Link on the host for this chain.
- Depth UINT8 ? ; < The Depth in the I/O chain from the Host.
- DevVenId UINT32 ? ; < The Device's PCI Vendor + Device ID (offset 0x00).
- Revision UINT8 ? ; < The Device's PCI Revision field (offset 0x08).
- Link UINT8 ? ; < The Device's Link number (0 or 1).
- Options DEVICE_CAP_OVERRIDE_OPTIONS {} ; < The options for this device override.
- ; Override fields
- LinkWidthIn UINT8 ? ; < modify to change the Link Width In.
- LinkWidthOut UINT8 ? ; < modify to change the Link Width Out.
- FreqCap UINT32 ? ; < modify to change the Link's frequency capability.
- Clumping UINT32 ? ; < modify to change Unit ID clumping support.
- Callout CALLOUT_ENTRY ? ; < optional call for really complex cases, or NULL.
-DEVICE_CAP_OVERRIDE ENDS
-
- ; Callout param struct for override capabilities of a device.
-
- ; If the optional callout is implemented this param struct is passed to it.
-
-DEVICE_CAP_CALLOUT_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < The header
- ; Match fields
- HostSocket UINT8 ? ; < The Socket on which this chain is located.
- HostLink UINT8 ? ; < The Link on the host for this chain.
- Depth UINT8 ? ; < The Depth in the I/O chain from the Host.
- DevVenId UINT32 ? ; < The Device's PCI Vendor + Device ID (offset 0x00).
- Revision UINT8 ? ; < The Device's PCI Revision field (offset 0x08).
- Link UINT8 ? ; < The Device's Link number (0 or 1).
- PciAddress PCI_ADDR {} ; < The Device's PCI Address.
- ; Override fields
- LinkWidthIn POINTER ? ; < modify to change the Link Width In.
- LinkWidthOut POINTER ? ; < modify to change the Link Width Out.
- FreqCap POINTER ? ; < modify to change the Link's frequency capability.
- Clumping POINTER ? ; < modify to change Unit ID clumping support.
-DEVICE_CAP_CALLOUT_PARAMS ENDS
-
- ; Limits for CPU to CPU Links.
-
- ; For each coherent connection this interface is checked once.
- ; Provide the frequency and width if needed for this Link (usually based on board
- ; restriction). This is used with CPU device capabilities and northbridge limits
- ; to compute the default settings.
-
-CPU_TO_CPU_PCB_LIMITS STRUCT
- ; Match fields
- SocketA UINT8 ? ; < One Socket on which this Link is located
- LinkA UINT8 ? ; < The Link on this Node
- SocketB UINT8 ? ; < The other Socket on which this Link is located
- LinkB UINT8 ? ; < The Link on that Node
- ; Limit fields
- ABLinkWidthLimit UINT8 ? ; < modify to change the Link Width A->B
- BALinkWidthLimit UINT8 ? ; < modify to change the Link Width B-<A
- PcbFreqCap UINT32 ? ; < modify to change the Link's frequency capability
-CPU_TO_CPU_PCB_LIMITS ENDS
-
- ; Get limits for non-coherent Links.
-
- ; For each non-coherent connection this interface is checked once.
- ; Provide the frequency and width if needed for this Link (usually based on board
- ; restriction). This is used with device capabilities, device overrides, and northbridge limits
- ; to compute the default settings.
-
-IO_PCB_LIMITS STRUCT
- ; Match fields
- HostSocket UINT8 ? ; < The Socket on which this Link is located
- HostLink UINT8 ? ; < The Link about to be initialized
- Depth UINT8 ? ; < The Depth in the I/O chain from the Host
- ; Limit fields
- DownstreamLinkWidthLimit UINT8 ? ; < modify to change the Link Width going away from processor
- UpstreamLinkWidthLimit UINT8 ? ; < modify to change the Link Width moving toward processor
- PcbFreqCap UINT32 ? ; < modify to change the Link's frequency capability
-IO_PCB_LIMITS ENDS
-
- ; Manually control bus number assignment.
-
- ; This interface is checked every time a non-coherent chain is processed.
- ; If a system can not use the auto Bus numbering feature for non-coherent chain bus
- ; assignments, this interface can provide explicit control. For each chain, provide
- ; the bus number range to use.
-
-OVERRIDE_BUS_NUMBERS STRUCT
- ; Match fields
- Socket UINT8 ? ; < The Socket on which this chain is located
- Link UINT8 ? ; < The Link on the host for this chain
- ; Override fields
- SecBus UINT8 ? ; < Secondary Bus number for this non-coherent chain
- SubBus UINT8 ? ; < Subordinate Bus number
-OVERRIDE_BUS_NUMBERS ENDS
-
-
- ; Ignore a Link.
-
- ; This interface is checked every time a coherent Link is found and then every
- ; time a non-coherent Link from a CPU is found.
- ; Any coherent or non-coherent Link from a CPU can be ignored and not used
- ; for discovery or initialization. Useful for connection based systems.
- ; (Note: not checked for IO device to IO Device Links.)
-
-IGNORE_LINK STRUCT
- ; Match fields
- Socket UINT8 ? ; < The Socket on which this Link is located
- Link UINT8 ? ; < The Link about to be initialized
- ; Customization fields
- LinkState FINAL_LINK_STATE ? ; < The link may be left unitialized, or powered off.
-IGNORE_LINK ENDS
-
-
- ; Skip reganging of subLinks.
-
- ; This interface is checked whenever two subLinks are both connected to the same CPUs.
- ; Normally, unganged sublinks between the same two CPUs are reganged.
- ; Provide a matching structure to leave the Links unganged.
-
-SKIP_REGANG STRUCT
- ; Match fields
- SocketA UINT8 ? ; < One Socket on which this Link is located
- LinkA UINT8 ? ; < The Link on this Node
- SocketB UINT8 ? ; < The other Socket on which this Link is located
- LinkB UINT8 ? ; < The Link on that Node
- ; Customization fields
- LinkState FINAL_LINK_STATE ? ; < The paired sublink may be active, or powered off.
-SKIP_REGANG ENDS
-
- ; The System Socket layout, which sockets are physically connected.
-
- ; The hardware method for Socket naming is preferred. Use this software method only
- ; if required.
-
-SYSTEM_PHYSICAL_SOCKET_MAP STRUCT
- CurrentSocket UINT8 ? ; < The socket from which this connection originates.
- CurrentLink UINT8 ? ; < The Link from the source socket connects to another socket.
- TargetSocket UINT8 ? ; < The target socket which is connected on that link.
-SYSTEM_PHYSICAL_SOCKET_MAP ENDS
-
-; ----------------------------------------------------------------------------
-
- ; This is the input structure for AmdHtInitialize.
-
-AMD_HT_INTERFACE STRUCT
- ; Basic level customization
- AutoBusStart UINT8 ? ; < For automatic bus number assignment, starting bus number usually zero.
- AutoBusMax UINT8 ? ; < For automatic bus number assignment, do not assign above max.
- AutoBusIncrement UINT8 ? ; < For automatic bus number assignment, each chain gets this many busses.
-
- ; Advanced Level Customization
- ManualBuidSwapList POINTER ? ; < Provide Manual Swap List, if any.
- DeviceCapOverrideList POINTER ? ; < Provide Device Overrides, if any.
- CpuToCpuPcbLimitsList POINTER ? ; < Provide CPU PCB Limits, if any.
- IoPcbLimitsList POINTER ? ; < Provide IO PCB Limits, if any.
- OverrideBusNumbersList POINTER ? ; < Provide manual Bus Number assignment, if any.
- ; < Use either auto bus numbering or override bus
- ; < numbers, not both.
-
- IgnoreLinkList POINTER ? ; < Provide links to ignore, if any.
- SkipRegangList POINTER ? ; < Provide links to remain unganged, if any.
-
- ; Expert Level Customization
- Topolist POINTER ? ; < Use this topology list in addition to the built in, if not NULL.
- SystemPhysicalSocketMap POINTER ?
- ; < The hardware socket naming method is preferred,
- ; < If it can't be used, this provides a software method.
-AMD_HT_INTERFACE ENDS
-
-; -----------------------------------------------------------------------------
-
- ; HT Recovery Interface
-
-
-
-; -----------------------------------------------------------------------------
-; * HT Recovery DEFINITIONS AND MACROS
-; *
-; *-----------------------------------------------------------------------------
-;
-
- ; BBHT subfunction events
- HT_EVENT_BB_EVENTS EQU 10005000h
- HT_EVENT_BB_BUID_EXCEED EQU 10015000h
- HT_EVENT_BB_DEVICE_FAILED EQU 10055000h
- HT_EVENT_BB_AUTO_DEPTH EQU 10065000h
-
-; ----------------------------------------------------------------------------
-; * HT Recovery TYPEDEFS, STRUCTURES, ENUMS
-; *
-; *----------------------------------------------------------------------------
-;
-
-
- ; The Interface structure to Recovery HT.
-
-AMD_HT_RESET_INTERFACE STRUCT
- ManualBuidSwapList POINTER ? ; < Option to manually control SB link init
- Depth UINT32 ? ; < If auto init was used this is set to the depth of the chain,
- ; < else, for manual init unmodified.
-AMD_HT_RESET_INTERFACE ENDS
-
-; ---------------------------------------------------------------------------
-; CPU Feature related info
-; ---------------------------------------------------------------------------
- ; Build Configuration values for BLDCFG_PLATFORM_C1E_MODE
- C1eModeDisabled EQU 0 ; < Disabled
- C1eModeHardware EQU 1 ; < Hardware method
- C1eModeMsgBased EQU 2 ; < Message-based method
- C1eModeSoftwareDeprecated EQU 3 ; < Deprecated software SMI method
- C1eModeHardwareSoftwareDeprecated EQU 4 ; < Hardware or Deprecated software SMI method
- MaxC1eMode EQU 5 ; < Not a valid value, used for verifying input
-PLATFORM_C1E_MODES TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_PLATFORM_CSTATE_MODE
- CStateModeDisabled EQU 0 ; < Disabled
- CStateModeC6 EQU 1 ; < C6 State
- MaxCStateMode EQU 2 ; < Not a valid value, used for verifying input
-PLATFORM_CSTATE_MODES TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_PLATFORM_CPB_MODE
- CpbModeAuto EQU 0 ; < Auto
- CpbModeDisabled EQU 1 ; < Disabled
- MaxCpbMode EQU 2 ; < Not a valid value, used for verifying input
-PLATFORM_CPB_MODES TEXTEQU <DWORD>
-
-
-;----------------------------------------------------------------------------
-; GNB PCIe configuration info
-;----------------------------------------------------------------------------
-
-GNB_EVENT_INVALID_CONFIGURATION EQU 20010000h ; User configuration invalid
-GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION EQU 20010001h ; Requested lane allocation for PCIe port can not be supported
-GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION EQU 20010002h ; Requested incorrect PCIe port device address
-GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION EQU 20010003h ; Incorrect parameter in DDI link configuration
-GNB_EVENT_INVALID_LINK_WIDTH_CONFIGURATION EQU 20010004h ; Invalid with for PCIe port or DDI link
-GNB_EVENT_INVALID_LANES_CONFIGURATION EQU 20010005h ; Lane double subscribe lanes
-GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION EQU 20010006h ; Requested lane allocation for DDI link(s) can not be supported
-GNB_EVENT_LINK_TRAINING_FAIL EQU 20020000h ; PCIe Link training fail
-GNB_EVENT_BROKEN_LANE_RECOVERY EQU 20030000h ; Broken lane workaround applied to recover link training
-GNB_EVENT_GEN2_SUPPORT_RECOVERY EQU 20040000h ; Scale back to GEN1 to recover link training
-
-DESCRIPTOR_TERMINATE_LIST EQU 80000000h
-
-PCIe_PORT_MISC_CONTROL STRUCT
- LinkComplianceMode UINT8 ?
- ;IN UINT8 LinkComplianceMode :1; ;< Force port into compliance mode (device will not be trained, port output compliance pattern)
-PCIe_PORT_MISC_CONTROL ENDS
-
-PCIe_PORT_DATA STRUCT
- PortPresent UINT8 ? ; < Enable PCIe port for initialization.
- ChannelType UINT8 ? ; < Channel type.
- ; 0 - "lowLoss",
- ; 1 - "highLoss",
- ; 2 - "mob0db",
- ; 3 - "mob3db",
- ; 4 - "extnd6db"
- ; 5 - "extnd8db"
- ;
- DeviceNumber UINT8 ? ; < Device number for port. Available device numbers may very on different CPUs.
- FunctionNumber UINT8 ? ; < Reserved for future use
- LinkSpeedCapability UINT8 ? ; < Advertised Gen Capability
- ; 0 - Maximum supported by silicon
- ; 1 - Gen1
- ; 2 - Gen2
- ; 3 - Gen3
- ;
- LinkAspm UINT8 ? ; < ASPM control. (see OemPcieLinkAspm for additional option to control ASPM)
- ; 0 - Disabled
- ; 1 - L0s only
- ; 2 - L1 only
- ; 2 - L0s and L1
- ;
- LinkHotplug UINT8 ? ; < Hotplug control.
- ; 0 - Disabled
- ; 1 - Basic
- ; 2 - Server
- ; 3 - Enhanced
- ;
- ResetId UINT8 ? ; < Arbitrary number greater than 0 assigned by platform firmware for GPIO
- ; identification which control reset for given port.
- ; Each port with unique GPIO should have unique ResetId assigned.
- ; All ports use same GPIO to control reset should have same ResetId assigned.
- ; see AgesaPcieSlotResetControl
- ;
- MiscControls PCIe_PORT_MISC_CONTROL {} ; < Misc extended controls
-PCIe_PORT_DATA ENDS
-
-;DDI channel lane mapping
-
-CHANNEL_MAPPING STRUCT ;
- Lane0 UINT8 ? ;
- ;IN UINT8 Lane0 :2; ;
- ;IN UINT8 Lane1 :2; ///< Lane 1 mapping (see "Lane 0 mapping")
- ;IN UINT8 Lane2 :2; ///< Lane 2 mapping (see "Lane 0 mapping")
- ;IN UINT8 Lane3 :2; ///< Lane 3 mapping (see "Lane 0 mapping")
-CHANNEL_MAPPING ENDS ;
-
-CONN_CHANNEL_MAPPING UNION
- ChannelMappingValue UINT8 ? ; < Raw lane mapping
- ChannelMapping CHANNEL_MAPPING {} ;
-CONN_CHANNEL_MAPPING ENDS ;
-
-; DDI Configuration
-PCIe_DDI_DATA STRUCT
- ConnectorType UINT8 ? ; < Display Connector Type
- ; 0 - DP
- ; 1 - eDP
- ; 2 - Single Link DVI
- ; 3 - Dual Link DVI
- ; 4 - HDMI
- ; 5 - Travis DP-to-VGA
- ; 6 - Travis DP-to-LVDS
- ; 7 - Hudson-2 NutMeg DP-to-VGA
- ; 8 - Single Link DVI-I
- ; 9 - CRT (VGA)
- ; 10 - LVDS
- ; 11 - VBIOS auto detect connector type
- AuxIndex UINT8 ? ; < Indicates which AUX or DDC Line is used
- ; 0 - AUX1
- ; 1 - AUX2
- ; 2 - AUX3
- ; 3 - AUX4
- ; 4 - AUX5
- ; 5 - AUX6
- ;
- HdpIndex UINT8 ? ; < Indicates which HDP pin is used
- ; 0 - HDP1
- ; 1 - HDP2
- ; 2 - HDP3
- ; 3 - HDP4
- ; 4 - HDP5
- ; 5 - HDP6
- Mapping CONN_CHANNEL_MAPPING (2) DUP ({}) ;< Set specific mapping of lanes to connector pins
- ;Mapping[0] define mapping for group of 4 lanes starting at PCIe_ENGINE_DATA.StartLane
- ;Mapping[1] define mapping for group of 4 lanes ending at PCIe_ENGINE_DATA.EndLane (only
- ;applicable for Dual DDI link)
- ;if Mapping[x] set to 0 than default mapping assumed
-
-PCIe_DDI_DATA ENDS
-
-
-; Engine Configuration
-PCIe_ENGINE_DATA STRUCT
- EngineType UINT8 ? ; < Engine type
- ; 0 - Ignore engine configuration
- ; 1 - PCIe port
- ; 2 - DDI
- StartLane UINT16 ? ; < Start lane number (in reversed configuration StartLane > EndLane).
- EndLane UINT16 ? ; < End lane number (in reversed configuration StartLane > EndLane).
-PCIe_ENGINE_DATA ENDS
-
-; PCIe port descriptor
-PCIe_PORT_DESCRIPTOR STRUCT
- Flags UINT32 ? ; < Descriptor flags
- ; Bit31 - last descriptor in complex
- EngineData PCIe_ENGINE_DATA {} ; < Engine data
- Port PCIe_PORT_DATA {} ; < PCIe port specific configuration info
-PCIe_PORT_DESCRIPTOR ENDS
-
-; DDI descriptor
-PCIe_DDI_DESCRIPTOR STRUCT
- Flags UINT32 ? ; < Descriptor flags
- EngineData PCIe_ENGINE_DATA {} ; < Engine data
- Ddi PCIe_DDI_DATA {} ; < DDI port specific configuration info
-PCIe_DDI_DESCRIPTOR ENDS
-
-; Slot Reset Info
-PCIe_SLOT_RESET_INFO STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < AGESA Standard Header
- ResetId UINT8 ? ; < Slot reset ID as specified in PCIe_PORT_DESCRIPTOR
- ResetControl UINT8 ? ; < Reset control as defined by PCIE_RESET_CONTROL
-PCIe_SLOT_RESET_INFO ENDS
-
-
-; PCIe Complex descriptor
-PCIe_COMPLEX_DESCRIPTOR STRUCT
- Flags UINT32 ? ; < Descriptor flags
- ; Bit31 - last descriptor in topology
- ;
- ;
- SocketId UINT32 ? ; < Socket Id
- PciePortList POINTER ? ;< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
- DdiLinkList POINTER ? ;< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
- Reserved POINTER ? ;< Reserved for future use
-PCIe_COMPLEX_DESCRIPTOR ENDS
-
- AssertSlotReset EQU 0
- DeassertSlotReset EQU 1
-PCIE_RESET_CONTROL TEXTEQU <DWORD>
-
- PcieUnusedEngine EQU 0
- PciePortEngine EQU 1
- PcieDdiEngine EQU 2
- MaxPcieEngine EQU 3 ; < Not a valid value, used for verifying input
-PCIE_ENGINE_TYPE TEXTEQU <DWORD>
-
- PcieGenMaxSupported EQU 0
- PcieGen1 EQU 1
- PcieGen2 EQU 2
- MaxPcieGen EQU 3 ; < Not a valid value, used for verifying input
-PCIE_LINK_SPEED_CAP TEXTEQU <DWORD>
-
- PsppDisabled EQU 0
- PsppPerformance EQU 1
- PsppBalanceHigh EQU 2
- PsppBalanceLow EQU 3
- PsppPowerSaving EQU 4
- MaxPspp EQU 5 ; < Not a valid value, used for verifying input
-PCIE_PSPP_POLICY TEXTEQU <DWORD>
-
- ConnectorTypeDP EQU 0
- ConnectorTypeEDP EQU 1
- ConnectorTypeSingleLinkDVI EQU 2
- ConnectorTypeDualLinkDVI EQU 3
- ConnectorTypeHDMI EQU 4
- ConnectorTypeTravisDpToVga EQU 5
- ConnectorTypeTravisDpToLvds EQU 6
- ConnectorTypeNutmegDpToVga EQU 7
- ConnectorTypeSingleLinkDviI EQU 8
- ConnectorTypeCrt EQU 9
- ConnectorTypeLvds EQU 10
- ConnectorTypeAutoDetect EQU 11
- MaxConnectorType EQU 12 ; < Not a valid value, used for verifying input
-PCIE_CONNECTOR_TYPE TEXTEQU <DWORD>
-
- ChannelTypeLowLoss EQU 0
- ChannelTypeHighLoss EQU 1
- ChannelTypeMob0db EQU 2
- ChannelTypeMob3db EQU 3
- ChannelTypeExt6db EQU 4
- ChannelTypeExt8db EQU 5
- MaxChannelType EQU 6 ; < Not a valid value, used for verifying input
-PCIE_CHANNEL_TYPE TEXTEQU <DWORD>
-
- AspmDisabled EQU 0
- AspmL0s EQU 1
- AspmL1 EQU 2
- AspmL0sL1 EQU 3
- MaxAspm EQU 4 ; < Not a valid value, used for verifying input
-PCIE_ASPM_TYPE TEXTEQU <DWORD>
-
- HotplugDisabled EQU 0
- HotplugBasic EQU 1
- HotplugServer EQU 2
- HotplugEnhanced EQU 3
- HotplugInboard EQU 4
- MaxHotplug EQU 5 ; < Not a valid value, used for verifying input
-PCIE_HOTPLUG_TYPE TEXTEQU <DWORD>
-
- PortDisabled EQU 0
- PortEnabled EQU 1
-PCIE_PORT_ENABLE TEXTEQU <DWORD>
-
- Aux1 EQU 0
- Aux2 EQU 1
- Aux3 EQU 2
- Aux4 EQU 3
- Aux5 EQU 4
- Aux6 EQU 5
- MaxAux EQU 6 ; < Not a valid value, used for verifying input
-PCIE_AUX_TYPE TEXTEQU <DWORD>
-
- Hdp1 EQU 0
- Hdp2 EQU 1
- Hdp3 EQU 2
- Hdp4 EQU 3
- Hdp5 EQU 4
- Hdp6 EQU 5
- MaxHdp EQU 6 ; < Not a valid value, used for verifying input
-PCIE_HDP_TYPE TEXTEQU <DWORD>
-
-;----------------------------------------------------------------------------
-; GNB configuration info
-;----------------------------------------------------------------------------
-;
-
-; Configuration settings for GNB.
-GNB_ENV_CONFIGURATION STRUCT
- Gnb3dStereoPinIndex UINT8 ? ;< 3D Stereo Pin ID.
- ; @li 0 = Stereo 3D is disabled (default).
- ; @li 1 = Use processor pin HPD1.
- ; @li 2 = Use processor pin HPD2
- ; @li 3 = Use processor pin HPD3
- ; @li 4 = Use processor pin HPD4
- ; @li 5 = Use processor pin HPD5
- ; @li 6 = Use processor pin HPD6
- LvdsSpreadSpectrum UINT16 ? ; Spread spectrum value in 0.01 %
- LvdsSpreadSpectrumRate UINT16 ? ; Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz
-GNB_ENV_CONFIGURATION ENDS
-
-; GNB configuration info
-GNB_CONFIGURATION STRUCT
- PcieComplexList POINTER ? ; Pointer to array of PCIe_COMPLEX_DESCRIPTOR structures describe PCIe topology on each processor package or NULL.
- ; Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST
- ;
- ;
- ;
- ; Topology organization definition assume PCIe_COMPLEX_DESCRIPTOR defined first following
- ; PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR for given PCIe_COMPLEX_DESCRIPTOR
- ; defined in arbitrary sequence:
- ; Example of topology definition for single socket system:
- ; PlatfromTopology LABEL DWORD
- ;
- ; Port0_2 PCIe_PORT_DESCRIPTOR <>;
- ; Port0_3 PCIe_PORT_DESCRIPTOR <DESCRIPTOR_TERMINATE_LIST> ;
- ; ...
- ; Ddi0_A PCIe_DDI_DESCRIPTOR <>;
- ; Ddi0_B PCIe_DDI_DESCRIPTOR <DESCRIPTOR_TERMINATE_LIST,>;
- ; ...
- ; Cpu0 PCIe_COMPLEX_DESCRIPTOR <DESCRIPTOR_TERMINATE_LIST, 0, Port0_2, Ddi0_A>
- ;
- ;
- PsppPolicy UINT8 ? ;< PSPP (PCIe Speed Power Policy)
- ; @li @b 0 - Disabled
- ; @li @b 1 - Performance
- ; @li @b 2 - Balance-High
- ; @li @b 3 - Balance-Low
- ; @li @b 4 - Power Saving
- ;
-GNB_CONFIGURATION ENDS
-
-
-; ---------------------------------------------------------------------------
-
-; MEMORY-SPECIFIC DATA STRUCTURES
-
-; ---------------------------------------------------------------------------
-
-
- ; AGESA MAXIMIUM VALUES
-
- ; These Max values are used to define array sizes and associated loop
- ; counts in the code. They reflect the maximum values that AGESA
- ; currently supports and does not necessarily reflect the hardware
- ; capabilities of configuration.
-
-
- MAX_SOCKETS_SUPPORTED EQU 8 ; < Max number of sockets in system
- MAX_CHANNELS_PER_SOCKET EQU 4 ; < Max Channels per sockets
- MAX_DIMMS_PER_CHANNEL EQU 4 ; < Max DIMMs on a memory channel (independent of platform)
- NUMBER_OF_DELAY_TABLES EQU 9 ; < Number of tables defined in CH_DEF_STRUCT.
- ; < Eg: UINT16 *RcvEnDlys;
- ; < UINT8 *WrDqsDlys;
- ; < UINT8 *RdDqsDlys;
- ; < UINT8 *WrDatDlys;
- ; < UINT8 *RdDqsMinDlys;
- ; < UINT8 *RdDqsMaxDlys;
- ; < UINT8 *WrDatMinDlys;
- ; < UINT8 *WrDatMaxDlys;
- NUMBER_OF_FAILURE_MASK_TABLES EQU 1 ; < Number of failure mask tables
- MAX_PLATFORM_TYPES EQU 16 ; < Platform types per system
-
- MCT_TRNG_KEEPOUT_START EQU 00004000h ; < base [39:8]
- MCT_TRNG_KEEPOUT_END EQU 00007FFFh ; < base [39:8]
-
- UMA_ATTRIBUTE_INTERLEAVE EQU 80000000h ; < Uma Region is interleaved
- UMA_ATTRIBUTE_ON_DCT0 EQU 40000000h ; < UMA resides on memory that belongs to DCT0
- UMA_ATTRIBUTE_ON_DCT1 EQU 20000000h ; < UMA resides on memory that belongs to DCT1
-
- PSO_TABLE TEXTEQU <UINT8>; < Platform Configuration Table
-
- ; AGESA DEFINITIONS
-
- ; Many of these are derived from the platform and hardware specific definitions
-
- ; EccSymbolSize override value
- ECCSYMBOLSIZE_USE_BKDG EQU 0 ; < Use BKDG Recommended Value
- ECCSYMBOLSIZE_FORCE_X4 EQU 4 ; < Force to x4
- ECCSYMBOLSIZE_FORCE_X8 EQU 8 ; < Force to x8
- ; CPU Package Type
- PT_L1 EQU 0 ; < L1 Package type
- PT_M2 EQU 1 ; < AM Package type
- PT_S1 EQU 2 ; < S1 Package type
-
- ; Structures use to pass system Logical CPU-ID
-CPU_LOGICAL_ID STRUCT
- Family UINT64 ? ; < Indicates logical ID Family
- Revision UINT64 ? ; < Indicates logical ID Family
-CPU_LOGICAL_ID ENDS
-
- ; Build Configuration values for BLDCFG_AMD_PLATFORM_TYPE
-
- AMD_PLATFORM_SERVER EQU 8000h ; < Server
- AMD_PLATFORM_DESKTOP EQU 10000h ; < Desktop
- AMD_PLATFORM_MOBILE EQU 20000h ; < Mobile
-AMD_PLATFORM_TYPE TEXTEQU <DWORD>
-
- ; Dram technology type
-
- DDR2_TECHNOLOGY EQU 0 ; < DDR2 technology
- DDR3_TECHNOLOGY EQU 1 ; < DDR3 technology
-TECHNOLOGY_TYPE TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT & BLDCFG_MEMORY_CLOCK_SELECT
-
- DDR400_FREQUENCY EQU 200 ; < DDR 400
- DDR533_FREQUENCY EQU 266 ; < DDR 533
- DDR667_FREQUENCY EQU 333 ; < DDR 667
- DDR800_FREQUENCY EQU 400 ; < DDR 800
- DDR1066_FREQUENCY EQU 533 ; < DDR 1066
- DDR1333_FREQUENCY EQU 667 ; < DDR 1333
- DDR1600_FREQUENCY EQU 800 ; < DDR 1600
- DDR1866_FREQUENCY EQU 933 ; < DDR 1866
- UNSUPPORTED_DDR_FREQUENCY EQU 934 ; < Highest limit of DDR frequency
-MEMORY_BUS_SPEED TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_MEMORY_QUADRANK_TYPE
-
- QUADRANK_REGISTERED EQU 0
- QUADRANK_UNBUFFERED EQU 1
-QUANDRANK_TYPE TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_TIMING_MODE_SELECT
-
- TIMING_MODE_AUTO EQU 0 ; < Use best rate possible
- TIMING_MODE_LIMITED EQU 1 ; < Set user top limit
- TIMING_MODE_SPECIFIC EQU 2 ; < Set user specified speed
-USER_MEMORY_TIMING_MODE TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_POWER_DOWN_MODE
-
- POWER_DOWN_BY_CHANNEL EQU 0
- POWER_DOWN_BY_CHIP_SELECT EQU 1
- POWER_DOWN_AUTO EQU 2
-POWER_DOWN_MODE TEXTEQU <DWORD>
-
- ; Low voltage support
-
- VOLT1_5 EQU 0 ; < 1.5 Volt
- VOLT1_35 EQU 1 ; < 1.35 Volt
- VOLT1_25 EQU 2 ; < 1.25 Volt
- VOLT_UNSUPPORTED EQU 0xFF ; < No common voltage found
-DIMM_VOLTAGE TEXTEQU <DWORD>
-
- ; UMA Mode
-
- UMA_NONE EQU 0 ; < UMA None
- UMA_SPECIFIED EQU 1 ; < UMA Specified
- UMA_AUTO EQU 2 ; < UMA Auto
-UMA_MODE TEXTEQU <DWORD>
-
- ; Build Configuration values for BLDCFG_UMA_ALIGNMENT
-
- NO_UMA_ALIGNED EQU 00FFFFFFh
- UMA_128MB_ALIGNED EQU 00FFF800h
- UMA_256MB_ALIGNED EQU 00FFF000h
- UMA_512MB_ALIGNED EQU 00FFE000h
-UMA_ALIGNMENT TEXTEQU <DWORD>
- ; ===============================================================================
- ; Global MCT Configuration Status Word (GStatus)
- ; ===============================================================================
-
- GsbMTRRshort EQU 0 ; < Ran out of MTRRs while mapping memory
- GsbAllECCDimms EQU 1 ; < All banks of all Nodes are ECC capable
- GsbDramECCDis EQU 2 ; < Dram ECC requested but not enabled.
- GsbSoftHole EQU 3 ; < A Node Base gap was created
- GsbHWHole EQU 4 ; < A HW dram remap was created
- GsbNodeIntlv EQU 5 ; < Node Memory interleaving was enabled
- GsbSpIntRemapHole EQU 6 ; < Special condition for Node Interleave and HW remapping
- GsbEnDIMMSpareNW EQU 7 ; < Indicates that DIMM Spare can be used without a warm reset
-
- GsbEOL EQU 8 ; < End of list
-GLOBAL_STATUS_FIELD TEXTEQU <DWORD>
-
-; ===============================================================================
- ; Local Error Status (DIE_STRUCT.ErrStatus[31:0])
-; ===============================================================================
-
- EsbNoDimms EQU 0 ; < No DIMMs
- EsbSpdChkSum EQU 1 ; < SPD Checksum fail
- EsbDimmMismatchM EQU 2 ; < dimm module type(buffer) mismatch
- EsbDimmMismatchT EQU 3 ; < dimm CL/T mismatch
- EsbDimmMismatchO EQU 4 ; < dimm organization mismatch (128-bit)
- EsbNoTrcTrfc EQU 5 ; < SPD missing Trc or Trfc info
- EsbNoCycTime EQU 6 ; < SPD missing byte 23 or 25
- EsbBkIntDis EQU 7 ; < Bank interleave requested but not enabled
- EsbDramECCDis EQU 8 ; < Dram ECC requested but not enabled
- EsbSpareDis EQU 9 ; < Online spare requested but not enabled
- EsbMinimumMode EQU 10 ; < Running in Minimum Mode
- EsbNoRcvrEn EQU 11 ; < No DQS Receiver Enable pass window found
- EsbSmallRcvr EQU 12 ; < DQS Rcvr En pass window too small (far right of dynamic range)
- EsbNoDqsPos EQU 13 ; < No DQS-DQ passing positions
- EsbSmallDqs EQU 14 ; < DQS-DQ passing window too small
- EsbDCBKScrubDis EQU 15 ; < DCache scrub requested but not enabled
-
- EsbEMPNotSupported EQU 16 ; < Processor is not capable for EMP.
- EsbEMPConflict EQU 17 ; < EMP requested but cannot be enabled since
- ; < channel interleaving, bank interleaving, or bank swizzle is enabled.
- EsbEMPDis EQU 18 ; < EMP requested but cannot be enabled since
- ; < memory size of each DCT is not a power of two.
-
- EsbEOL EQU 19 ; < End of list
-ERROR_STATUS_FIELD TEXTEQU <DWORD>
-
-; ===============================================================================
- ; Local Configuration Status (DIE_STRUCT.Status[31:0])
-; ===============================================================================
-
- SbRegistered EQU 0 ; < All DIMMs are Registered
- SbEccDimms EQU 1 ; < All banks ECC capable
- SbParDimms EQU 2 ; < All banks Addr/CMD Parity capable
- SbDiagClks EQU 3 ; < Jedec ALL slots clock enable diag mode
- Sb128bitmode EQU 4 ; < DCT in 128-bit mode operation
- Sb64MuxedMode EQU 5 ; < DCT in 64-bit mux'ed mode.
- Sb2TMode EQU 6 ; < 2T CMD timing mode is enabled.
- SbSWNodeHole EQU 7 ; < Remapping of Node Base on this Node to create a gap.
- SbHWHole EQU 8 ; < Memory Hole created on this Node using HW remapping.
- SbOver400Mhz EQU 9 ; < DCT freq greater than or equal to 400MHz flag
- SbDQSPosPass2 EQU 10 ; < Used for TrainDQSPos DIMM0/1, when freq greater than or equal to 400MHz
- SbDQSRcvLimit EQU 11 ; < Used for DQSRcvEnTrain to know we have reached the upper bound.
- SbExtConfig EQU 12 ; < Indicate the default setting for extended PCI configuration support
- SbLrdimms EQU 13 ; < All DIMMs are LRDIMMs
- SbEOL EQU 14 ; < End of list
-LOCAL_STATUS_FIELD TEXTEQU <DWORD>
-
-
-; < CPU MSR Register definitions ------------------------------------------
- SYS_CFG EQU 0C0010010h
- TOP_MEM EQU 0C001001Ah
- TOP_MEM2 EQU 0C001001Dh
- HWCR EQU 0C0010015h
- NB_CFG EQU 0C001001Fh
-
- FS_BASE EQU 0C0000100h
- IORR0_BASE EQU 0C0010016h
- IORR0_MASK EQU 0C0010017h
- BU_CFG EQU 0C0011023h
- BU_CFG2 EQU 0C001102Ah
- COFVID_STAT EQU 0C0010071h
- TSC EQU 10h
-
-; ===============================================================================
- ; SPD Data for each DIMM
-; ===============================================================================
-SPD_DEF_STRUCT STRUCT
- DimmPresent BOOLEAN ? ; < Indicates that the DIMM is present and Data is valid
- Data UINT8 (256) DUP (?) ; < Buffer for 256 Bytes of SPD data from DIMM
-SPD_DEF_STRUCT ENDS
-
-; ===============================================================================
- ; Channel Definition Structure
- ; This data structure defines entries that are specific to the channel initialization
-; ===============================================================================
-CH_DEF_STRUCT STRUCT
- ChannelID UINT8 ? ; < Physical channel ID of a socket(0 = CH A, 1 = CH B, 2 = CH C, 3 = CH D)
- TechType TECHNOLOGY_TYPE ? ; < Technology type of this channel
- ChDimmPresent UINT8 ? ; < For each bit n 0..7, 1 = DIMM n is present.
- ; < DIMM# Select Signal
- ; < 0 MA0_CS_L[0, 1]
- ; < 1 MB0_CS_L[0, 1]
- ; < 2 MA1_CS_L[0, 1]
- ; < 3 MB1_CS_L[0, 1]
- ; < 4 MA2_CS_L[0, 1]
- ; < 5 MB2_CS_L[0, 1]
- ; < 6 MA3_CS_L[0, 1]
- ; < 7 MB3_CS_L[0, 1]
-
- DCTPtr POINTER ? ; < Pointer to the DCT data of this channel.
- MCTPtr POINTER ? ; < Pointer to the node data of this channel.
- SpdPtr POINTER ? ; < Pointer to the SPD data for this channel. (Setup by NB Constructor)
- DimmSpdPtr POINTER (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Array of pointers to
- ; < SPD Data for each Dimm. (Setup by Tech Block Constructor)
- ChDimmValid UINT8 ? ; < For each bit n 0..3, 1 = DIMM n is valid and is/will be configured where 4..7 are reserved.
- RegDimmPresent UINT8 ? ; < For each bit n 0..3, 1 = DIMM n is a registered DIMM where 4..7 are reserved.
- LrDimmPresent UINT8 ? ; < For each bit n 0..3, 1 = DIMM n is Load Reduced DIMM where 4..7 are reserved.
- SODimmPresent UINT8 ? ; < For each bit n 0..3, 1 = DIMM n is a SO-DIMM where 4..7 are reserved.
- Loads UINT8 ? ; < Number of devices loading bus
- Dimms UINT8 ? ; < Number of DIMMs loading Channel
- Ranks UINT8 ? ; < Number of ranks loading Channel DATA
- SlowMode BOOLEAN ? ; < 1T or 2T CMD mode (slow access mode)
- ; < FALSE = 1T
- ; < TRUE = 2T
- ; < The following pointers will be pointed to dynamically allocated buffers.
- ; < Each buffer is two dimensional (RowCount x ColumnCount) and is lay-outed as in below.
- ; < Example: If DIMM and Byte based training, then
- ; < XX is a value in Hex
- ; < BYTE 0, BYTE 1, BYTE 2, BYTE 3, BYTE 4, BYTE 5, BYTE 6, BYTE 7, ECC BYTE
- ; < Row1 - Logical DIMM0 XX XX XX XX XX XX XX XX XX
- ; < Row2 - Logical DIMM1 XX XX XX XX XX XX XX XX XX
- RcvEnDlys POINTER ? ; < DQS Receiver Enable Delays
- WrDqsDlys POINTER ? ; < Write DQS delays (only valid for DDR3)
- RdDqsDlys POINTER ? ; < Read Dqs delays
- WrDatDlys POINTER ? ; < Write Data delays
- RdDqsMinDlys POINTER ? ; < Minimum Window for Read DQS
- RdDqsMaxDlys POINTER ? ; < Maximum Window for Read DQS
- WrDatMinDlys POINTER ? ; < Minimum Window for Write data
- WrDatMaxDlys POINTER ? ; < Maximum Window for Write data
- RowCount UINT8 ? ; < Number of rows of the allocated buffer.
- ColumnCount UINT8 ? ; < Number of columns of the allocated buffer.
-
- FailingBitMask POINTER ? ; < Table of masks to Track Failing bits
- DctOdcCtl UINT32 ? ; < Output Driver Strength (see BKDG FN2:Offset 9Ch, index 00h)
- DctAddrTmg UINT32 ? ; < Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h)
- PhyRODTCSLow UINT32 ? ; < Phy Read ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 180h)
- PhyRODTCSHigh UINT32 ? ; < Phy Read ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 181h)
- PhyWODTCSLow UINT32 ? ; < Phy Write ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 182h)
- PhyWODTCSHigh UINT32 ? ; < Phy Write ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 183)
- PhyWLODT UINT8 (4) DUP (?) ; < Write Levelization ODT Pattern for Dimm 0-3 (see BKDG FN2:Offset 9Ch, index 0x8[11:8])
- DctEccDqsLike UINT16 ? ; < DCT DQS ECC UINT8 like...
- DctEccDqsScale UINT8 ? ; < DCT DQS ECC UINT8 scale
- PtrPatternBufA UINT16 ? ; < Ptr on stack to aligned DQS testing pattern
- PtrPatternBufB UINT16 ? ; < Ptr on stack to aligned DQS testing pattern
- ByteLane UINT8 ? ; < Current UINT8 Lane (0..7)
- Direction UINT8 ? ; < Current DQS-DQ training write direction (0=read, 1=write)
- Pattern UINT8 ? ; < Current pattern
- DqsDelay UINT8 ? ; < Current DQS delay value
- HostBiosSrvc1 UINT16 ? ; < UINT16 sized general purpose field for use by host BIOS. Scratch space.
- HostBiosSrvc2 UINT32 ? ; < UINT32 sized general purpose field for use by host BIOS. Scratch space.
- DctMaxRdLat UINT16 ? ; < Max Read Latency (ns) for the DCT
- DIMMValidCh UINT8 ? ; < DIMM# in CH
- MaxCh UINT8 ? ; < Max number of CH in system
- Dct UINT8 ? ; < Dct pointer
- WrDatGrossH UINT8 ? ; < Write Data Gross delay high value
- DqsRcvEnGrossL UINT8 ? ; < DQS Receive Enable Gross Delay low
-
- TrwtWB UINT8 ? ; < Non-SPD timing value for TrwtWB
- CurrRcvrDctADelay UINT8 ? ; < for keep current RcvrEnDly
- T1000 UINT16 ? ; < get the T1000 figure (cycle time (ns) * 1K)
- DqsRcvEnPass UINT8 ? ; < for TrainRcvrEn UINT8 lane pass flag
- DqsRcvEnSaved UINT8 ? ; < for TrainRcvrEn UINT8 lane saved flag
- SeedPass1Remainder UINT8 ? ; < for Phy assisted DQS receiver enable training
-
- ClToNbFlag UINT8 ? ; < is used to restore ClLinesToNbDis bit after memory
- NodeSysBase UINT32 ? ; < for channel interleave usage
- RefRawCard UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Array of rawcards detected
- CtrlWrd02 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 2 values per DIMM
- CtrlWrd03 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 3 values per DIMM
- CtrlWrd04 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 4 values per DIMM
- CtrlWrd05 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 5 values per DIMM
- CtrlWrd08 UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Control Word 8 values per DIMM
-
- CsPresentDCT UINT16 ? ; < For each bit n 0..7, 1 = Chip-select n is present
- DimmMirrorPresent UINT8 ? ; < For each bit n 0..7, 1 = DIMM n is OnDimmMirror capable
- DimmSpdCse UINT8 ? ; < For each bit n 0..7, 1 = DIMM n SPD checksum error
- DimmExclude UINT8 ? ; < For each bit n 0..7, 1 = DIMM n gets excluded
- DimmYr06 UINT8 ? ; < Bitmap indicating which Dimms have a manufacturer's year code <= 2006
- DimmWk2406 UINT8 ? ; < Bitmap indicating which Dimms have a manufacturer's week code <= 24 of 2006 (June)
- DimmPlPresent UINT8 ? ; < Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.
- DimmQrPresent UINT8 ? ; < QuadRank DIMM present?
- DimmDrPresent UINT8 ? ; < Bitmap indicating that Dual Rank Dimms are present
- DimmSRPresent UINT8 ? ; < Bitmap indicating that Single Rank Dimms are present
- Dimmx4Present UINT8 ? ; < For each bit n 0..3, 1 = DIMM n contains x4 data devices. where 4..7 are reserved.
- Dimmx8Present UINT8 ? ; < For each bit n 0..3, 1 = DIMM n contains x8 data devices. where 4..7 are reserved.
- Dimmx16Present UINT8 ? ; < For each bit n 0..3, 1 = DIMM n contains x16 data devices. where 4..7 are reserved.
- LrdimmPhysicalRanks UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Number of Physical Ranks for LRDIMMs
- LrDimmLogicalRanks UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Number of LRDIMM Logical ranks in this configuration
- LrDimmRankMult UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?) ; < Rank Multipication factor per dimm.
-
- MemClkDisMap POINTER ? ; < This pointer will be set to point to an array that describes
- ; < the routing of M[B,A]_CLK pins to the DIMMs' ranks. AGESA will
- ; < base on this array to disable unused MemClk to save power.
- ; <
- ; < The array must have 8 entries. Each entry, which associates with
- ; < one MemClkDis bit, is a bitmap of 8 CS that that MemClk is routed to.
- ; < Example:
- ; < BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package
- ; < is like below:
- ; < Bit AM3/S1g3 pin name
- ; < 0 M[B,A]_CLK_H/L[0]
- ; < 1 M[B,A]_CLK_H/L[1]
- ; < 2 M[B,A]_CLK_H/L[2]
- ; < 3 M[B,A]_CLK_H/L[3]
- ; < 4 M[B,A]_CLK_H/L[4]
- ; < 5 M[B,A]_CLK_H/L[5]
- ; < 6 M[B,A]_CLK_H/L[6]
- ; < 7 M[B,A]_CLK_H/L[7]
- ; < And platform has the following routing:
- ; < CS0 M[B,A]_CLK_H/L[4]
- ; < CS1 M[B,A]_CLK_H/L[2]
- ; < CS2 M[B,A]_CLK_H/L[3]
- ; < CS3 M[B,A]_CLK_H/L[5]
- ; < Then MemClkDisMap should be pointed to the following array:
- ; < CLK_2 CLK_3 CLK_4 CLK_5
- ; < 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00
- ; < Each entry of the array is the bitmask of 8 chip selects.
-
- CKETriMap POINTER ? ; < This pointer will be set to point to an array that describes
- ; < the routing of CKE pins to the DIMMs' ranks.
- ; < The array must have 2 entries. Each entry, which associates with
- ; < one CKE pin, is a bitmap of 8 CS that that CKE is routed to.
- ; < AGESA will base on this array to disable unused CKE pins to save power.
-
- ODTTriMap POINTER ? ; < This pointer will be set to point to an array that describes
- ; < the routing of ODT pins to the DIMMs' ranks.
- ; < The array must have 4 entries. Each entry, which associates with
- ; < one ODT pin, is a bitmap of 8 CS that that ODT is routed to.
- ; < AGESA will base on this array to disable unused ODT pins to save power.
-
- ChipSelTriMap POINTER ? ; < This pointer will be set to point to an array that describes
- ; < the routing of chip select pins to the DIMMs' ranks.
- ; < The array must have 8 entries. Each entry is a bitmap of 8 CS.
- ; < AGESA will base on this array to disable unused Chip select pins to save power.
-
- ExtendTmp BOOLEAN ? ; < If extended temperature is supported on all dimms on a channel.
-
- Reserved UINT8 (100) DUP (?) ; < Reserved
-CH_DEF_STRUCT ENDS
-
-; ===============================================================================
- ; DCT Channel Timing Parameters
- ; This data structure sets timings that are specific to the channel
-; ===============================================================================
-CH_TIMING_STRUCT STRUCT
- DctDimmValid UINT16 ? ; < For each bit n 0..3, 1=DIMM n is valid and is/will be configured where 4..7 are reserved.
- DimmMirrorPresent UINT16 ? ; < For each bit n 0..3, 1=DIMM n is OnDimmMirror capable where 4..7 are reserved.
- DimmSpdCse UINT16 ? ; < For each bit n 0..3, 1=DIMM n SPD checksum error where 4..7 are reserved.
- DimmExclude UINT16 ? ; < For each bit n 0..3, 1 = DIMM n gets excluded because of no common voltage is found
- CsPresent UINT16 ? ; < For each bit n 0..7, 1=Chip-select n is present
- CsEnabled UINT16 ? ; < For each bit n 0..7, 1=Chip-select n is enabled
- CsTestFail UINT16 ? ; < For each bit n 0..7, 1=Chip-select n is present but disabled
- CsTrainFail UINT16 ? ; < Bitmap showing which chipselects failed training
- DIMM1KPage UINT16 ? ; < For each bit n 0..3, 1=DIMM n contains 1K page devices. where 4..7 are reserved.
- DimmQrPresent UINT16 ? ; < QuadRank DIMM present?
- DimmDrPresent UINT16 ? ; < Bitmap indicating that Dual Rank Dimms are present
- DimmSRPresent UINT8 ? ; < Bitmap indicating that Single Rank Dimms are present
- Dimmx4Present UINT16 ? ; < For each bit n 0..3, 1=DIMM n contains x4 data devices. where 4..7 are reserved.
- Dimmx8Present UINT16 ? ; < For each bit n 0..3, 1=DIMM n contains x8 data devices. where 4..7 are reserved.
- Dimmx16Present UINT16 ? ; < For each bit n 0..3, 1=DIMM n contains x16 data devices. where 4..7 are reserved.
-
- DIMMTrcd UINT16 ? ; < Minimax Trcd*40 (ns) of DIMMs
- DIMMTrp UINT16 ? ; < Minimax Trp*40 (ns) of DIMMs
- DIMMTrtp UINT16 ? ; < Minimax Trtp*40 (ns) of DIMMs
- DIMMTras UINT16 ? ; < Minimax Tras*40 (ns) of DIMMs
- DIMMTrc UINT16 ? ; < Minimax Trc*40 (ns) of DIMMs
- DIMMTwr UINT16 ? ; < Minimax Twr*40 (ns) of DIMMs
- DIMMTrrd UINT16 ? ; < Minimax Trrd*40 (ns) of DIMMs
- DIMMTwtr UINT16 ? ; < Minimax Twtr*40 (ns) of DIMMs
- DIMMTfaw UINT16 ? ; < Minimax Tfaw*40 (ns) of DIMMs
- TargetSpeed UINT16 ? ; < Target DRAM bus speed in MHz
- Speed UINT16 ? ; < DRAM bus speed in MHz
- ; < 400 (MHz)
- ; < 533 (MHz)
- ; < 667 (MHz)
- ; < 800 (MHz)
- ; < and so on...
- CasL UINT8 ? ; < CAS latency DCT setting (busclocks)
- Trcd UINT8 ? ; < DCT Trcd (busclocks)
- Trp UINT8 ? ; < DCT Trp (busclocks)
- Trtp UINT8 ? ; < DCT Trtp (busclocks)
- Tras UINT8 ? ; < DCT Tras (busclocks)
- Trc UINT8 ? ; < DCT Trc (busclocks)
- Twr UINT8 ? ; < DCT Twr (busclocks)
- Trrd UINT8 ? ; < DCT Trrd (busclocks)
- Twtr UINT8 ? ; < DCT Twtr (busclocks)
- Tfaw UINT8 ? ; < DCT Tfaw (busclocks)
- Trfc0 UINT8 ? ; < DCT Logical DIMM0 Trfc
- ; < 0 = 75ns (for 256Mb devs)
- ; < 1 = 105ns (for 512Mb devs)
- ; < 2 = 127.5ns (for 1Gb devs)
- ; < 3 = 195ns (for 2Gb devs)
- ; < 4 = 327.5ns (for 4Gb devs)
- Trfc1 UINT8 ? ; < DCT Logical DIMM1 Trfc (see Trfc0 for format)
- Trfc2 UINT8 ? ; < DCT Logical DIMM2 Trfc (see Trfc0 for format)
- Trfc3 UINT8 ? ; < DCT Logical DIMM3 Trfc (see Trfc0 for format)
- DctMemSize UINT32 ? ; < Base[47:16], total DRAM size controlled by this DCT.
- SlowMode BOOLEAN ? ; < 1T or 2T CMD mode (slow access mode)
- ; < FALSE = 1T
- ; < TRUE = 2T
- TrwtTO UINT8 ? ; < DCT TrwtTO (busclocks)
- Twrrd UINT8 ? ; < DCT Twrrd (busclocks)
- Twrwr UINT8 ? ; < DCT Twrwr (busclocks)
- Trdrd UINT8 ? ; < DCT Trdrd (busclocks)
- TrwtWB UINT8 ? ; < DCT TrwtWB (busclocks)
- TrdrdSD UINT8 ? ; < DCT TrdrdSD (busclocks)
- TwrwrSD UINT8 ? ; < DCT TwrwrSD (busclocks)
- TwrrdSD UINT8 ? ; < DCT TwrrdSD (busclocks)
- MaxRdLat UINT16 ? ; < Max Read Latency
- WrDatGrossH UINT8 ? ; < Temporary variables must be removed
- DqsRcvEnGrossL UINT8 ? ; < Temporary variables must be removed
-CH_TIMING_STRUCT ENDS
-
-; ===============================================================================
- ; Data for each DCT
- ; This data structure defines data used to configure each DRAM controller
-; ===============================================================================
-DCT_STRUCT STRUCT
- Dct UINT8 ? ; < Current Dct
- Timings CH_TIMING_STRUCT {} ; < Channel Timing structure
- ChData POINTER ? ; < Pointed to a dynamically allocated array of Channel structures
- ChannelCount UINT8 ? ; < Number of channel per this DCT
-DCT_STRUCT ENDS
-
-
-; ===============================================================================
- ; Data Structure defining each Die
- ; This data structure contains information that is used to configure each Die
-; ===============================================================================
-DIE_STRUCT STRUCT
-
- ; Advanced:
-
- NodeId UINT8 ? ; < Node ID of current controller
- SocketId UINT8 ? ; < Socket ID of this Die
- DieId UINT8 ? ; < ID of this die relative to the socket
- PciAddr PCI_ADDR {} ; < Pci bus and device number of this controller.
- ErrCode AGESA_STATUS ? ; < Current error condition of Node
- ; < 0x0 = AGESA_SUCCESS
- ; < 0x1 = AGESA_UNSUPPORTED
- ; < 0x2 = AGESA_BOUNDS_CHK
- ; < 0x3 = AGESA_ALERT
- ; < 0x4 = AGESA_WARNING
- ; < 0x5 = AGESA_ERROR
- ; < 0x6 = AGESA_CRITICAL
- ; < 0x7 = AGESA_FATAL
- ; <
- ErrStatus BOOLEAN (EsbEOL) DUP (?) ; < Error Status bit Field
- Status BOOLEAN (SbEOL) DUP (?) ; < Status bit Field
- NodeMemSize UINT32 ? ; < Base[47:16], total DRAM size controlled by both DCT0 and DCT1 of this Node.
- NodeSysBase UINT32 ? ; < Base[47:16] (system address) DRAM base address of this Node.
- NodeHoleBase UINT32 ? ; < If not zero, Base[47:16] (system address) of dram hole for HW remapping. Dram hole exists on this Node
- NodeSysLimit UINT32 ? ; < Base[47:16] (system address) DRAM limit address of this Node.
- DimmPresent UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is present.
- ; < DIMM# Select Signal
- ; < 0 MA0_CS_L[0, 1]
- ; < 1 MB0_CS_L[0, 1]
- ; < 2 MA1_CS_L[0, 1]
- ; < 3 MB1_CS_L[0, 1]
- ; < 4 MA2_CS_L[0, 1]
- ; < 5 MB2_CS_L[0, 1]
- ; < 6 MA3_CS_L[0, 1]
- ; < 7 MB3_CS_L[0, 1]
- DimmValid UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is valid and is / will be configured
- RegDimmPresent UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is registered DIMM
- LrDimmPresent UINT32 ? ; < For each bit n 0..3, 1 = DIMM n is Load Reduced DIMM where 4..7 are reserved.
- DimmEccPresent UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is ECC capable.
- DimmParPresent UINT32 ? ; < For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable.
- DimmTrainFail UINT16 ? ; < Bitmap showing which dimms failed training
- ChannelTrainFail UINT16 ? ; < Bitmap showing the channel information about failed Chip Selects
- ; < 0 in any bit field indicates Channel 0
- ; < 1 in any bit field indicates Channel 1
- Dct UINT8 ? ; < Need to be removed
- ; < DCT pointer
- GangedMode BOOLEAN ? ; < Ganged mode
- ; < 0 = disabled
- ; < 1 = enabled
- LogicalCpuid CPU_LOGICAL_ID {} ; < The logical CPUID of the node
- HostBiosSrvc1 UINT16 ? ; < UINT16 sized general purpose field for use by host BIOS. Scratch space.
- HostBiosSrvc2 UINT32 ? ; < UINT32 sized general purpose field for use by host BIOS. Scratch space.
- MLoad UINT8 ? ; < Need to be removed
- ; < Number of devices loading MAA bus
- MaxAsyncLat UINT8 ? ; < Legacy wrapper
- ChbD3Rcvrdly UINT8 ? ; < Legacy wrapper
- ChaMaxRdLat UINT16 ? ; < Max Read Latency (ns) for DCT 0
- ChbD3BcRcvrdly UINT8 ? ; < CHB DIMM 3 Check UINT8 Receiver Enable Delay
-
- DctData POINTER ? ; < Pointed to a dynamically allocated array of DCT_STRUCTs
- DctCount UINT8 ? ; < Number of DCTs per this Die
- Reserved UINT8 (16) DUP (?) ; < Reserved
-DIE_STRUCT ENDS
-
-; *********************************************************************
-; * S3 Support structure
-; *********************************************************************
- ; AmdInitResume, AmdS3LateRestore, and AmdS3Save param structure
-AMD_S3_PARAMS STRUCT
- Signature UINT32 ? ; < "ASTR" for AMD Suspend-To-RAM
- Version UINT16 ? ; < S3 Params version number
- Flags UINT32 ? ; < Indicates operation
- NvStorage POINTER ? ; < Pointer to memory critical save state data
- NvStorageSize UINT32 ? ; < Size in bytes of the NvStorage region
- VolatileStorage POINTER ? ; < Pointer to remaining AMD save state data
- VolatileStorageSize UINT32 ? ; < Size in bytes of the VolatileStorage region
-AMD_S3_PARAMS ENDS
-
-; ===============================================================================
- ; MEM_PARAMETER_STRUCT
- ; This data structure is used to pass wrapper parameters to the memory configuration code
-; ===============================================================================
-MEM_PARAMETER_STRUCT STRUCT
-
- ; Basic (Return parameters)
- ; (This section contains the outbound parameters from the memory init code)
-
- GStatus BOOLEAN (GsbEOL) DUP (?) ; < Global Status bitfield
- HoleBase UINT32 ? ; < If not zero Base[47:16] (system address) of sub 4GB dram hole for HW remapping.
- Sub4GCacheTop UINT32 ? ; < If not zero, the 32-bit top of cacheable memory.
- SysLimit UINT32 ? ; < Limit[47:16] (system address)
- DDR3Voltage DIMM_VOLTAGE ? ; < Find support voltage and send back to platform BIOS.
- ; < 0 = 1.5v
- ; < 1 = 1.35v
- ; < 2 = 1.2v
- ; < 0xFF = Mixed 1.5V and 1.2V in the system. 1.5V dimms get excluded
- ; < from the system.
- ; <
-
- MemData POINTER ? ; < Pointer to MEM_DATA_STRUCT
- ; Advanced (Optional parameters)
- ; Optional (all defaults values will be initialized by the
- ; 'AmdMemInitDataStructDef' based on AMD defaults. It is up
- ; to the IBV/OEM to change the defaults after initialization
- ; but prior to the main entry to the memory code):
-
- ; Memory Map/Mgt.
-
- BottomIo UINT16 ? ; < Bottom of 32-bit IO space (8-bits)
- ; < NV_BOTTOM_IO[7:0]=Addr[31:24]
- MemHoleRemapping BOOLEAN ? ; < Memory Hole Remapping (1-bit)
- ; < FALSE = disable
- ; < TRUE = enable
-
-
- ; Dram Timing
-
- UserTimingMode USER_MEMORY_TIMING_MODE ? ; < User Memclock Mode
-
- MemClockValue MEMORY_BUS_SPEED ? ; < Memory Clock Value
-
- ; Dram Configuration
-
- EnableBankIntlv BOOLEAN ? ; < Dram Bank (chip-select) Interleaving (1-bit)
- ; < FALSE =disable (AMD default)
- ; < TRUE =enable
- EnableNodeIntlv BOOLEAN ? ; < Node Memory Interleaving (1-bit)
- ; < FALSE = disable (AMD default)
- ; < TRUE = enable
- EnableChannelIntlv BOOLEAN ? ; < Channel Interleaving (1-bit)
- ; < FALSE = disable (AMD default)
- ; < TRUE = enable
- ; ECC
-
- EnableEccFeature BOOLEAN ? ; < enable ECC error to go into MCE
- ; < FALSE = disable (AMD default)
- ; < TRUE = enable
- ; Dram Power
-
- EnablePowerDown BOOLEAN ? ; < CKE based power down mode (1-bit)
- ; < FALSE =disable (AMD default)
- ; < TRUE =enable
- ; Online Spare
-
- EnableOnLineSpareCtl BOOLEAN ? ; < Chip Select Spare Control bit 0:
- ; < FALSE = disable Spare (AMD default)
- ; < TRUE = enable Spare
- TableBasedAlterations POINTER ? ; < Point to an array of data bytes describing desired modifications to register settings.
-
- PlatformMemoryConfiguration POINTER ?
- ; < Points to a table that contains platform specific settings
- ; < (i.e. MemClk routing, the number of DIMM slots per channel,...)
- ; < AGESA initializes this pointer with DefaultPlatformMemoryConfiguration that
- ; < contains default conservative settings. Platform BIOS can either tweak
- ; < DefaultPlatformMemoryConfiguration or reassign this pointer to its own table.
- ; <
- EnableParity BOOLEAN ? ; < Parity control
- ; < TRUE = enable
- ; < FALSE = disable (AMD default)
- EnableBankSwizzle BOOLEAN ? ; < BankSwizzle control
- ; < FALSE = disable
- ; < TRUE = enable (AMD default)
- EnableMemClr BOOLEAN ? ; < Memory Clear functionality control
- ; < FALSE = disable
- ; < TRUE = enable (AMD default)
- ; Uma Configuration
-
- UmaMode UMA_MODE ? ; < Uma Mode
- ; < 0 = None
- ; < 1 = Specified
- ; < 2 = Auto
- UmaSize UINT32 ? ; < The size of shared graphics dram (16-bits)
- ; < NV_UMA_Size[31:0]=Addr[47:16]
- ; <
- UmaBase UINT32 ? ; < The allocated Uma base address (32-bits)
- ; < NV_UMA_Base[31:0]=Addr[47:16]
- ; <
-
- ; Memory Restore Feature
-
- MemRestoreCtl BOOLEAN ? ; < Memory context restore control
- ; < FALSE = perform memory init as normal (AMD default)
- ; < TRUE = restore memory context and skip training. This requires
- ; < MemContext is valid before AmdInitPost
- SaveMemContextCtl BOOLEAN ? ; < Control switch to save memory context at the end of MemAuto
- ; < TRUE = AGESA will setup MemContext block before exit AmdInitPost
- ; < FALSE = AGESA will not setup MemContext block. Platform is
- ; < expected to call S3Save later in POST if it wants to
- ; < use memory context restore feature.
- MemContext AMD_S3_PARAMS {} ; < Memory context block describes the data that platform needs to
- ; < save and restore for memory context restore feature to work.
- ; < It uses the subset of S3Save block to save/restore. Hence platform
- ; < may save only S3 block and uses it for both S3 resume and
- ; < memory context restore.
- ; < - If MemRestoreCtl is TRUE, platform needs to pass in MemContext
- ; < before AmdInitPost.
- ; < - If SaveMemContextCtl is TRUE, platform needs to save MemContext
- ; < right after AmdInitPost.
-MEM_PARAMETER_STRUCT ENDS
-
-
-; ===============================================================================
- ; Function definition
- ; This data structure passes function pointers to the memory configuration code.
- ; The wrapper can use this structure with customized versions
-; ================================================================================
-MEM_FUNCTION_STRUCT STRUCT
-
- ; PUBLIC required Internal functions
-
- amdMemGetPsCfgU POINTER ? ; < Proc for Unbuffered DIMMs, platform specific
- amdMemGetPsCfgR POINTER ? ; < Proc for Registered DIMMs, platform specific
-
- ; PUBLIC optional functions
-
- amdMemEccInit POINTER ? ; < NB proc for ECC feature
- amdMemChipSelectInterleaveInit POINTER ? ; < NB proc for CS interleave feature
- amdMemDctInterleavingInit POINTER ? ; < NB proc for Channel interleave feature
- amdMemMctInterleavingInit POINTER ? ; < NB proc for Node interleave feature
- amdMemParallelTraining POINTER ? ; < NB proc for parallel training feature
- amdMemEarlySampleSupport POINTER ? ; < NB code for early sample support feature
- amdMemMultiPartInitSupport POINTER ? ; < NB code for 'multi-part'
- amdMemOnlineSpareSupport POINTER ? ; < NB code for On-Line Spare feature
- amdMemUDimmInit POINTER ? ; < NB code for UDIMMs
- amdMemRDimmInit POINTER ? ; < NB code for RDIMMs
- amdMemLrDimmInit POINTER ? ; < NB code for LRDIMMs
-
- Reserved UINT32 (100) DUP (?) ; < Reserved for later function definition
-MEM_FUNCTION_STRUCT ENDS
-
-; ===============================================================================
- ; Socket Structure
-
-; ===============================================================================
-MEM_SOCKET_STRUCT STRUCT
- ChannelPtr POINTER (MAX_CHANNELS_PER_SOCKET) DUP (?) ; < Pointers to each channels training data
-
- TimingsPtr POINTER (MAX_CHANNELS_PER_SOCKET) DUP (?) ; < Pointers to each channels timing data
-
-MEM_SOCKET_STRUCT ENDS
-
-; ===============================================================================
- ; MEM_DATA_STRUCT
-; ===============================================================================
-MEM_DATA_STRUCT STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < AGESA Standard Header
-
- ParameterListPtr POINTER ? ; < List of input Parameters
-
- FunctionList MEM_FUNCTION_STRUCT {} ; < List of function Pointers
-
- GetPlatformCfg POINTER (MAX_PLATFORM_TYPES) DUP (?) ; < look-up platform info
-
- ErrorHandling POINTER ? ; < Error Handling
-
- ; SocketList is a shortcut for IBVs to retrieve training
- ; and timing data for each channel indexed by socket/channel,
- ; eliminating their need to parse die/dct/channel etc.
- ; It contains pointers to the populated data structures for
- ; each channel and skips the channel structures that are
- ; unpopulated. In the case of channels sharing the same DCT,
- ; the pTimings pointers will point to the same DCT Timing data.
-
- SocketList MEM_SOCKET_STRUCT (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Socket list for memory code
-
- DiesPerSystem POINTER ? ; < Pointed to an array of DIE_STRUCTs
- DieCount UINT8 ? ; < Number of MCTs in the system.
-
- SpdDataStructure POINTER ? ; < Pointer to SPD Data structure
-
- PlatFormConfig POINTER ? ; < Pointer to Platform profile/build option config structure
-
- IsFlowControlSupported BOOLEAN ? ; < Indicates if flow control is supported
-
- TscRate UINT32 ? ; < The rate at which the TSC increments in megahertz.
-
-MEM_DATA_STRUCT ENDS
-
-; ===============================================================================
-; UMA_INFO_STRUCT
-; ===============================================================================
-UMA_INFO STRUCT
- UmaBase UINT64 ? ; < UmaBase[63:0] = Addr[63:0]
- UmaSize UINT32 ? ; < UmaSize[31:0] = Addr[31:0]
- UmaAttributes UINT32 ? ; < Indicate the attribute of Uma
- UmaMode UINT8 ? ; < Indicate the mode of Uma
- MemClock UINT16 ? ; < Indicate memory running speed in MHz
- Reserved UINT8 (3) DUP (?) ; < Reserved for future usage
-UMA_INFO ENDS
-
- ; AGESA MEMORY ERRORS
-
- ; AGESA_ALERT Memory Errors
-MEM_ALERT_USER_TMG_MODE_OVERRULED EQU 04010000h ; < TIMING_MODE_SPECIFIC is requested but
- ; < cannot be applied to current configurations.
-MEM_ALERT_ORG_MISMATCH_DIMM EQU 04010100h ; < DIMM organization miss-match
-MEM_ALERT_BK_INT_DIS EQU 04010200h ; < Bank interleaving disable for internal issue
-
- ; AGESA_ERROR Memory Errors
-MEM_ERROR_NO_DQS_POS_RD_WINDOW EQU 04010300h ; < No DQS Position window for RD DQS
-MEM_ERROR_SMALL_DQS_POS_RD_WINDOW EQU 04020300h ; < Small DQS Position window for RD DQS
-MEM_ERROR_NO_DQS_POS_WR_WINDOW EQU 04030300h ; < No DQS Position window for WR DQS
-MEM_ERROR_SMALL_DQS_POS_WR_WINDOW EQU 04040300h ; < Small DQS Position window for WR DQS
-MEM_ERROR_ECC_DIS EQU 04010400h ; < ECC has been disabled as a result of an internal issue
-MEM_ERROR_DIMM_SPARING_NOT_ENABLED EQU 04010500h ; < DIMM sparing has not been enabled for an internal issues
-MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE EQU 04050300h ; < Receive Enable value is too large
-MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW EQU 04060300h ; < There is no DQS receiver enable window
-MEM_ERROR_DRAM_ENABLED_TIME_OUT EQU 04010600h ; < Time out when polling DramEnabled bit
-MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT EQU 04010700h ; < Time out when polling DctAccessDone bit
-MEM_ERROR_SEND_CTRL_WORD_TIME_OUT EQU 04010800h ; < Time out when polling SendCtrlWord bit
-MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT EQU 04010900h ; < Time out when polling PrefDramTrainMode bit
-MEM_ERROR_ENTER_SELF_REF_TIME_OUT EQU 04010A00h ; < Time out when polling EnterSelfRef bit
-MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT EQU 04010B00h ; < Time out when polling FreqChgInProg bit
-MEM_ERROR_EXIT_SELF_REF_TIME_OUT EQU 04020A00h ; < Time out when polling ExitSelfRef bit
-MEM_ERROR_SEND_MRS_CMD_TIME_OUT EQU 04010C00h ; < Time out when polling SendMrsCmd bit
-MEM_ERROR_SEND_ZQ_CMD_TIME_OUT EQU 04010D00h ; < Time out when polling SendZQCmd bit
-MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT EQU 04010E00h ; < Time out when polling DctExtraAccessDone bit
-MEM_ERROR_MEM_CLR_BUSY_TIME_OUT EQU 04010F00h ; < Time out when polling MemClrBusy bit
-MEM_ERROR_MEM_CLEARED_TIME_OUT EQU 04020F00h ; < Time out when polling MemCleared bit
-MEM_ERROR_FLUSH_WR_TIME_OUT EQU 04011000h ; < Time out when polling FlushWr bit
-MEM_ERROR_MAX_LAT_NO_WINDOW EQU 04070300h ; < Fail to find pass during Max Rd Latency training
-MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL EQU 04080300h ; < Fail to launch training code on an AP
-MEM_ERROR_PARALLEL_TRAINING_TIME_OUT EQU 04090300h ; < Fail to finish parallel training
-MEM_ERROR_NO_ADDRESS_MAPPING EQU 04011100h ; < No address mapping found for a dimm
-MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT EQU 040A0300h ; < There is no DQS receiver enable window and the value is equal to the largest value
-MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE EQU 040B0300h ; < Receive Enable value is too large and is 1 less than limit
-MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR EQU 04011200h ; < SPD Checksum error for NV_SPDCHK_RESTRT
-MEM_ERROR_NO_CHIPSELECT EQU 04011300h ; < No chipselects found
-MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM EQU 04011500h ; < Unbuffered dimm is not supported at 333MHz
-MEM_ERROR_WL_PRE_OUT_OF_RANGE EQU 040C0300h ; < Returned PRE value during write levelization was out of range
-
- ; AGESA_WARNING Memory Errors
- MEM_WARNING_UNSUPPORTED_QRDIMM EQU 04011600h ; < QR DIMMs detected but not supported
- MEM_WARNING_UNSUPPORTED_UDIMM EQU 04021600h ; < U DIMMs detected but not supported
- MEM_WARNING_UNSUPPORTED_SODIMM EQU 04031600h ; < SO-DIMMs detected but not supported
- MEM_WARNING_UNSUPPORTED_X4DIMM EQU 04041600h ; < x4 DIMMs detected but not supported
- MEM_WARNING_UNSUPPORTED_RDIMM EQU 04051600h ; < R DIMMs detected but not supported
- MEM_WARNING_UNSUPPORTED_LRDIMM EQU 04061600h ; < LR DIMMs detected but not supported
-
- MEM_WARNING_EMP_NOT_SUPPORTED EQU 04011700h ; < Processor is not capable for EMP
- MEM_WARNING_EMP_CONFLICT EQU 04021700h ; < EMP cannot be enabled if channel interleaving,
- ; < bank interleaving, or bank swizzle is enabled.
- MEM_WARNING_EMP_NOT_ENABLED EQU 04031700h ; < Memory size is not power of two.
- MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED EQU 04011800h ; < Performance has been enabled, but battery life is preferred.
- MEM_WARNING_NO_SPDTRC_FOUND EQU 04011900h ; < No Trc timing value found in SPD of a dimm.
- MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED EQU 04012000h ; < Node Interleaveing Requested, but could not be enabled
- MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED EQU 04012100h ; < Channel Interleaveing Requested, but could not be enabled
- MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED EQU 04012200h ; < Bank Interleaveing Requested, but could not be enabled
- MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED EQU 04012300h ; < Voltage 1.35 determined, but could not be supported
-
- ; AGESA_FATAL Memory Errors
- MEM_ERROR_MINIMUM_MODE EQU 04011A00h ; < Running in minimum mode
- MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM EQU 04011B00h ; < DIMM modules are miss-matched
- MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM EQU 04011C00h ; < No DIMMs have been found on system
- MEM_ERROR_MISMATCH_DIMM_CLOCKS EQU 04011D00h ; < DIMM clocks miss-matched
- MEM_ERROR_NO_CYC_TIME EQU 04011E00h ; < No cycle time found
- MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS EQU 04011F00h ; < Heap allocation error with dynamic storing of trained timings
- MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs EQU 04021F00h ; < Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT
- MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV EQU 04031F00h ; < Heap allocation error with REMOTE_TRAINING_ENV
- MEM_ERROR_HEAP_ALLOCATE_FOR_SPD EQU 04041F00h ; < Heap allocation error for SPD data
- MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA EQU 04051F00h ; < Heap allocation error for RECEIVED_DATA during parallel training
- MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS EQU 04061F00h ; < Heap allocation error for S3 "SPECIAL_CASE_REGISTER"
- MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA EQU 04071F00h ; < Heap allocation error for Training Data
- MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK EQU 04081F00h ; < Heap allocation error for DIMM Identify "MEM_NB_BLOCK
- MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM EQU 04022300h ; < No Constructor for DIMM Identify
-
-
- ; AGESA_CRITICAL Memory Errors
- MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3 EQU 04091F00h ; < Heap allocation error for DMI table for DDR3
- MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2 EQU 040A1F00h ; < Heap allocation error for DMI table for DDR2
- MEM_ERROR_UNSUPPORTED_DIMM_CONFIG EQU 04011400h ; < Dimm population is not supported
-
-
-; ----------------------------------------------------------------------------
-; *
-; * END OF MEMORY-SPECIFIC DATA STRUCTURES
-; *
-; *----------------------------------------------------------------------------
-;
-
-
-; ----------------------------------------------------------------------------
-; *
-; * CPU RELATED DEFINITIONS
-; *
-; *----------------------------------------------------------------------------
-;
-
-; CPU Event definitions.
-
-; Defines used to filter CPU events based on functional blocks
-CPU_EVENT_PM_EVENT_MASK EQU 0FF00FF00h
-CPU_EVENT_PM_EVENT_CLASS EQU 008000400h
-
-;================================================================
-; CPU General events
-; Heap allocation (AppFunction = 01h)
-CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT EQU 008000100h
-CPU_ERROR_HEAP_IS_ALREADY_INITIALIZED EQU 008010100h
-CPU_ERROR_HEAP_IS_FULL EQU 008020100h
-CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED EQU 008030100h
-CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT EQU 008040100h
-; BrandId (AppFunction = 02h)
-CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE EQU 008000200h
-; Micro code patch (AppFunction = 03h)
-CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED EQU 008000300h
-; Power management (AppFunction = 04h)
-CPU_EVENT_PM_PSTATE_OVERCURRENT EQU 008000400h
-CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT EQU 008010400h
-CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE EQU 008020400h
-CPU_ERROR_PM_NB_PSTATE_MISMATCH EQU 008030400h
-; BIST (AppFunction = 05h)
-CPU_EVENT_BIST_ERROR EQU 008000500h
-;=================================================================
-; CPU Feature events
-; Execution cache (AppFunction = 21h)
-; AGESA_CACHE_SIZE_REDUCED 2101
-; AGESA_CACHE_REGIONS_ACROSS_1MB 2102
-; AGESA_CACHE_REGIONS_ACROSS_4GB 2103
-; AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY 2104
-; AGESA_CACHE_START_ADDRESS_LESS_D0000 2105
-; AGESA_THREE_CACHE_REGIONS_ABOVE_1MB 2106
-; AGESA_DEALLOCATE_CACHE_REGIONS 2107
-CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR EQU 008002100h
-; Core Leveling (AppFunction = 22h)
-CPU_WARNING_ADJUSTED_LEVELING_MODE EQU 008002200h
-; HT Assist (AppFunction = 23h)
-CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG EQU 008002300h
-
-; CPU Build Configuration structures and definitions
-
-; Build Configuration values for BLDGCFG_AP_MTRR_SETTINGS
-AP_MTRR_SETTINGS STRUCT
- MsrAddr UINT32 ? ; < Fixed-Sized MTRR address
- MsrData UINT64 ? ; < MTRR Settings
-AP_MTRR_SETTINGS ENDS
-
-AMD_AP_MTRR_FIX64k_00000 EQU 000000250h
-AMD_AP_MTRR_FIX16k_80000 EQU 000000258h
-AMD_AP_MTRR_FIX16k_A0000 EQU 000000259h
-AMD_AP_MTRR_FIX4k_C0000 EQU 000000268h
-AMD_AP_MTRR_FIX4k_C8000 EQU 000000269h
-AMD_AP_MTRR_FIX4k_D0000 EQU 00000026Ah
-AMD_AP_MTRR_FIX4k_D8000 EQU 00000026Bh
-AMD_AP_MTRR_FIX4k_E0000 EQU 00000026Ch
-AMD_AP_MTRR_FIX4k_E8000 EQU 00000026Dh
-AMD_AP_MTRR_FIX4k_F0000 EQU 00000026Eh
-AMD_AP_MTRR_FIX4k_F8000 EQU 00000026Fh
-CPU_LIST_TERMINAL EQU 0FFFFFFFFh
-
-; ***********************************************************************
-; *
-; * AGESA interface Call-Out function parameter structures
-; *
-; **********************************************************************
-
- ; Parameters structure for interface call-out AgesaAllocateBuffer
-AGESA_BUFFER_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- BufferLength UINT32 ? ; < Size of buffer to allocate
- BufferHandle UINT32 ? ; < Identifier or name for the buffer
- BufferPointer POINTER ? ; < location of the created buffer
-AGESA_BUFFER_PARAMS ENDS
-
- ; Parameters structure for interface call-out AgesaRunCodeOnAp
-AP_EXE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- FunctionNumber UINT32 ? ; < Index of the procedure to execute
- RelatedDataBlock POINTER ? ; < Location of data structure the procedure will use
- RelatedBlockLength UINT32 ? ; < Size of the related data block
-AP_EXE_PARAMS ENDS
-
- ; Parameters structure for the interface call-out AgesaReadSpd & AgesaReadSpdRecovery
-AGESA_READ_SPD_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < standard header
- SocketId UINT8 ? ; < Address of SPD - socket ID
- MemChannelId UINT8 ? ; < Address of SPD - memory channel ID
- DimmId UINT8 ? ; < Address of SPD - DIMM ID
- Buffer POINTER ? ; < Location where to place the SPD content
- MemData POINTER ? ; < Location of the MemData structure, for reference
-AGESA_READ_SPD_PARAMS ENDS
-
- ; Buffer Handles
- AMD_DMI_INFO_BUFFER_HANDLE EQU 000D000h ; < Assign 0x000D000 buffer handle to DMI function
- AMD_PSTATE_DATA_BUFFER_HANDLE EQU 000D001h ; < Assign 0x000D001 buffer handle to Pstate data
- AMD_PSTATE_ACPI_BUFFER_HANDLE EQU 000D002h ; < Assign 0x000D002 buffer handle to Pstate table
- AMD_BRAND_ID_BUFFER_HANDLE EQU 000D003h ; < Assign 0x000D003 buffer handle to Brand ID
- AMD_ACPI_SLIT_BUFFER_HANDLE EQU 000D004h ; < Assign 0x000D004 buffer handle to SLIT function
- AMD_SRAT_INFO_BUFFER_HANDLE EQU 000D005h ; < Assign 0x000D005 buffer handle to SRAT function
- AMD_WHEA_BUFFER_HANDLE EQU 000D006h ; < Assign 0x000D006 buffer handle to WHEA function
- AMD_S3_INFO_BUFFER_HANDLE EQU 000D007h ; < Assign 0x000D007 buffer handle to S3 function
- AMD_S3_NB_INFO_BUFFER_HANDLE EQU 000D008h ; < Assign 0x000D008 buffer handle to S3 NB device info
- AMD_ACPI_ALIB_BUFFER_HANDLE EQU 000D009h ; < Assign 0x000D009 buffer handle to ALIB SSDT table
-AMD_BUFFER_HANDLE TEXTEQU <DWORD>
-; ***********************************************************************
-; *
-; * AGESA interface Call-Out function prototypes
-; *
-; **********************************************************************
-
-; ***********************************************************************
-; *
-; * AGESA interface structure definition and function prototypes
-; *
-; **********************************************************************
-
-; *********************************************************************
-; * Platform Configuration: The parameters in boot branch function
-; *********************************************************************
-
-; The possible platform control flow settings.
- Nfcm EQU 0 ; < Normal Flow Control Mode.
- UmaDr EQU 1 ; < UMA using Display Refresh flow control.
- UmaIfcm EQU 2 ; < UMA using Isochronous Flow Control.
- Ifcm EQU 3 ; < Isochronous Flow Control Mode (other than for UMA).
- Iommu EQU 4 ; < An IOMMU is in use in the system.
- MaxControlFlow EQU 5 ; < Not a control flow mode, use for limit checking.
-PLATFORM_CONTROL_FLOW TEXTEQU <DWORD>
-
-; Platform Deemphasis Levels.
- DeemphasisLevelNone EQU 0 ; < No Deemphasis.
- DeemphasisLevelMinus3 EQU 1 ; < Minus 3 db deemphasis.
- DeemphasisLevelMinus6 EQU 2 ; < Minus 6 db deemphasis.
- DeemphasisLevelMinus8 EQU 3 ; < Minus 8 db deemphasis.
- DeemphasisLevelMinus11 EQU 4 ; < Minus 11 db deemphasis.
- DeemphasisLevelMinus11pre8 EQU 5 ; < Minus 11, Minus 8 precursor db deemphasis.
- DcvLevelNone EQU 16 ; < No DCV Deemphasis.
- DcvLevelMinus2 EQU 17 ; < Minus 2 db DCV deemphasis.
- DcvLevelMinus3 EQU 18 ; < Minus 3 db DCV deemphasis.
- DcvLevelMinus5 EQU 19 ; < Minus 5 db DCV deemphasis.
- DcvLevelMinus6 EQU 20 ; < Minus 6 db DCV deemphasis.
- DcvLevelMinus7 EQU 21 ; < Minus 7 db DCV deemphasis.
- DcvLevelMinus8 EQU 22 ; < Minus 8 db DCV deemphasis.
- DcvLevelMinus9 EQU 23 ; < Minus 9 db DCV deemphasis.
- DcvLevelMinus11 EQU 24 ; < Minus 11 db DCV deemphasis.
- MaxPlatformDeemphasisLevel EQU 25 ; < Not a deemphasis level, use for limit checking.
-PLATFORM_DEEMPHASIS_LEVEL TEXTEQU <DWORD>
-
-; Provide Deemphasis Levels for HT Links.
-;
-; For each CPU to CPU or CPU to IO device HT link, the list of Deemphasis Levels will
-; be checked for a match. The item matches for a Socket, Link if the link frequency is
-; is in the inclusive range HighFreq:LoFreq.
-; AGESA does not set deemphasis in IO devices, only in processors.
-
-CPU_HT_DEEMPHASIS_LEVEL STRUCT
- ; Match fields
- Socket UINT8 ? ; < One Socket on which this Link is located
- Link UINT8 ? ; < The Link on this Processor.
- LoFreq UINT8 ? ; < If the link is set to this frequency or greater, apply these levels, and
- HighFreq UINT8 ? ; < If the link is set to this frequency or less, apply these levels.
- ; Value fields
- ReceiverDeemphasis PLATFORM_DEEMPHASIS_LEVEL ? ; < The deemphasis level for this link
- DcvDeemphasis PLATFORM_DEEMPHASIS_LEVEL ? ; < The DCV, or far transmitter deemphasis level.
-CPU_HT_DEEMPHASIS_LEVEL ENDS
-
-; The possible platform power policy settings.
- Performance EQU 0 ; < Optimize for performance.
- BatteryLife EQU 1 ; < Optimize for battery life.
- MaxPowerPolicy EQU 2 ; < Not a power policy mode, use for limit checking.
-PLATFORM_POWER_POLICY TEXTEQU <DWORD>
-
-; Platform performance settings for optimized settings.
-; Several configuration settings for the processor depend upon other parts and
-; general designer choices for the system. The determination of these data points
-; is not standard for all platforms, so the host environment needs to provide these
-; to specify how the system is to be configured.
-PERFORMANCE_PROFILE STRUCT
- PlatformControlFlowMode PLATFORM_CONTROL_FLOW ? ; < The platform's control flow mode for optimum platform performance.
- UseHtAssist BOOLEAN ? ; < HyperTransport link traffic optimization.
- UseAtmMode BOOLEAN ? ; < HyperTransport link traffic optimization.
- Use32ByteRefresh BOOLEAN ? ; < Display Refresh traffic generates 32 byte requests.
- UseVariableMctIsocPriority BOOLEAN ? ; < The Memory controller will be set to Variable Isoc Priority.
- PlatformPowerPolicy PLATFORM_POWER_POLICY ? ; < The platform's desired power policy
-PERFORMANCE_PROFILE ENDS
-
-; Platform settings that describe the voltage regulator modules of the system.
-; Many power management settings are dependent upon the characteristics of the
-; on-board voltage regulator module (VRM). The host environment needs to provide
-; these to specify how the system is to be configured.
-PLATFORM_VRM_CONFIGURATION STRUCT
- CurrentLimit UINT32 ? ; < Vrm Current Limit.
- LowPowerThreshold UINT32 ? ; < Vrm Low Power Threshold.
- SlewRate UINT32 ? ; < Vrm Slew Rate.
- AdditionalDelay UINT32 ? ; < Vrm Additional Delay.
- HiSpeedEnable BOOLEAN ? ; < Select high speed VRM.
- InrushCurrentLimit UINT32 ? ; < Vrm Inrush Current Limit.
-PLATFORM_VRM_CONFIGURATION ENDS
-
-; The VRM types to characterize.
- CoreVrm EQU 0 ; < VDD plane.
- NbVrm EQU 1 ; < VDDNB plane.
- MaxVrmType EQU 2 ; < Not a valid VRM type, use for limit checking.
-PLATFORM_VRM_TYPE TEXTEQU <DWORD>
-
-; Build Option/Configuration Boolean Structure
-BUILD_OPT_CFG STRUCT
- ; Build Option Area
- VersionString AMD_CODE_HEADER {} ; < AMD embedded code version string
- OptionUDimms BOOLEAN ? ; < UDIMMS
- OptionRDimms BOOLEAN ? ; < RDIMMS
- OptionLrDimms BOOLEAN ? ; < LRDIMMS
- OptionEcc BOOLEAN ? ; < ECC
- OptionBankInterleave BOOLEAN ? ; < BANK_INTERLEAVE
- OptionDctInterleave BOOLEAN ? ; < DCT_INTERLEAVE
- OptionNodeInterleave BOOLEAN ? ; < NODE_INTERLEAVE
- OptionParallelTraining BOOLEAN ? ; < PARALLEL_TRAINING
- OptionOnlineSpare BOOLEAN ? ; < ONLINE_SPARE
- OptionMemRestore BOOLEAN ? ; < MEM CONTEXT RESTORE
- OptionMultisocket BOOLEAN ? ; < MULTISOCKET
- OptionAcpiPstates BOOLEAN ? ; < ACPI_PSTATES
- OptionSrat BOOLEAN ? ; < SRAT
- OptionSlit BOOLEAN ? ; < SLIT
- OptionWhea BOOLEAN ? ; < WHEA
- OptionDmi BOOLEAN ? ; < DMI
- OptionEarlySamples BOOLEAN ? ; < EARLY_SAMPLES
- OptionAddrToCsTranslator BOOLEAN ? ; < ADDR_TO_CS_TRANSLATOR
-
- ; Build Configuration Area
- CfgPciMmioAddress UINT64 ? ; < PciMmioBase
- CfgPciMmioSize UINT32 ? ; < PciMmioSize
- CfgPlatVrmCfg PLATFORM_VRM_CONFIGURATION (MaxVrmType) DUP ({}) ; < Several configuration settings for the voltage regulator modules.
- CfgPlatNumIoApics UINT32 ? ; < PlatformApicIoNumber
- CfgMemInitPstate UINT32 ? ; < MemoryInitPstate
- CfgPlatformC1eMode PLATFORM_C1E_MODES ? ; < PlatformC1eMode
- CfgPlatformC1eOpData UINT32 ? ; < PlatformC1eOpData
- CfgPlatformC1eOpData1 UINT32 ? ; < PlatformC1eOpData1
- CfgPlatformC1eOpData2 UINT32 ? ; < PlatformC1eOpData2
- CfgPlatformCStateMode PLATFORM_CSTATE_MODES ? ; < PlatformCStateMode
- CfgPlatformCStateOpData UINT32 ? ; < PlatformCStateOpData
- CfgPlatformCStateIoBaseAddress UINT16 ? ; < PlatformCStateIoBaseAddress
- CfgPlatformCpbMode PLATFORM_CPB_MODES ? ; < PlatformCpbMode
- CfgCoreLevelingMode UINT32 ? ; < CoreLevelingCofig
- CfgPerformanceProfile PERFORMANCE_PROFILE {} ; < The platform's control flow mode and platform performance settings.
- CfgPlatformDeemphasisList POINTER ? ; < HT Deemphasis
- CfgAmdPlatformType UINT32 ? ; < AmdPlatformType
- CfgAmdPstateCapValue UINT32 ? ; < Amd pstate ceiling enabling deck
-
- CfgMemoryBusFrequencyLimit MEMORY_BUS_SPEED ? ; < Memory Bus Frequency Limit
- CfgMemoryModeUnganged BOOLEAN ? ; < Memory Mode Unganged
- CfgMemoryQuadRankCapable BOOLEAN ? ; < Memory Quad Rank Capable
- CfgMemoryQuadrankType QUANDRANK_TYPE ? ; < Memory Quadrank Type
- CfgMemoryRDimmCapable BOOLEAN ? ; < Memory RDIMM Capable
- CfgMemoryLRDimmCapable BOOLEAN ? ; < Memory LRDIMM Capable
- CfgMemoryUDimmCapable BOOLEAN ? ; < Memory UDIMM Capable
- CfgMemorySODimmCapable BOOLEAN ? ; < Memory SODimm Capable
- CfgMemoryEnableBankInterleaving BOOLEAN ? ; < Memory Enable Bank Interleaving
- CfgMemoryEnableNodeInterleaving BOOLEAN ? ; < Memory Enable Node Interleaving
- CfgMemoryChannelInterleaving BOOLEAN ? ; < Memory Channel Interleaving
- CfgMemoryPowerDown BOOLEAN ? ; < Memory Power Down
- CfgPowerDownMode POWER_DOWN_MODE ? ; < Power Down Mode
- CfgOnlineSpare BOOLEAN ? ; < Online Spare
- CfgMemoryParityEnable BOOLEAN ? ; < Memory Parity Enable
- CfgBankSwizzle BOOLEAN ? ; < Bank Swizzle
- CfgTimingModeSelect USER_MEMORY_TIMING_MODE ? ; < Timing Mode Select
- CfgMemoryClockSelect MEMORY_BUS_SPEED ? ; < Memory Clock Select
- CfgDqsTrainingControl BOOLEAN ? ; < Dqs Training Control
- CfgIgnoreSpdChecksum BOOLEAN ? ; < Ignore Spd Checksum
- CfgUseBurstMode BOOLEAN ? ; < Use Burst Mode
- CfgMemoryAllClocksOn BOOLEAN ? ; < Memory All Clocks On
- CfgEnableEccFeature BOOLEAN ? ; < Enable ECC Feature
- CfgEccRedirection BOOLEAN ? ; < ECC Redirection
- CfgScrubDramRate UINT16 ? ; < Scrub Dram Rate
- CfgScrubL2Rate UINT16 ? ; < Scrub L2Rate
- CfgScrubL3Rate UINT16 ? ; < Scrub L3Rate
- CfgScrubIcRate UINT16 ? ; < Scrub Ic Rate
- CfgScrubDcRate UINT16 ? ; < Scrub Dc Rate
- CfgEccSyncFlood BOOLEAN ? ; < ECC Sync Flood
- CfgEccSymbolSize UINT16 ? ; < ECC Symbol Size
- CfgHeapDramAddress UINT64 ? ; < Heap contents will be temporarily stored in this address during the transition
- CfgNodeMem1GBAlign BOOLEAN ? ; < Node Mem 1GB boundary Alignment
- CfgS3LateRestore BOOLEAN ? ; < S3 Late Restore
- CfgAcpiPstateIndependent BOOLEAN ? ; < PSD method dependent/Independent
- CfgApMtrrSettingsList POINTER ? ; < The AP's MTRR settings before final halt
- CfgUmaMode UMA_MODE ? ; < Uma Mode
- CfgUmaSize UINT32 ? ; < Uma Size [31:0]=Addr[47:16]
- CfgUmaAbove4G BOOLEAN ? ; < Uma Above 4G Support
- CfgUmaAlignment UMA_ALIGNMENT ? ; < Uma alignment
- CfgProcessorScopeInSb BOOLEAN ? ; < ACPI Processor Object in \_SB scope
- CfgProcessorScopeName0 CHAR8 ? ; < OEM specific 1st character of processor scope name.
- CfgProcessorScopeName1 CHAR8 ? ; < OEM specific 2nd character of processor scope name.
- CfgGnbHdAudio UINT8 ? ; < Gnb HD Audio Enable
- CfgAbmSupport UINT8 ? ; < ABM support
- CfgDynamicRefreshRate UINT8 ? ; < Dynamic refresh rate
- CfgLcdBackLightControl UINT16 ? ; < Lcd back light control
- CfgGnb3dStereoPinIndex UINT8 ? ; < 3D Stereo Pin ID
- CfgTempPcieMmioBaseAddress UINT32 ? ; < Temp pcie MMIO base address
- CfgGnbIGPUSSID UINT32 ? ; < Gnb internal GPU SSID
- CfgGnbHDAudioSSID UINT32 ? ; < Gnb HD Audio SSID
- CfgGnbPcieSSID UINT32 ? ; < Gnb PCIe SSID
- CfgLvdsSpreadSpectrum UINT16 ? ; < Lvds Spread Spectrum. Build-time customizable only
- CfgLvdsSpreadSpectrumRate UINT16 ? ; < Lvds Spread Spectrum Rate. Build-time customizable only
- Reserved BOOLEAN ? ; < reserved...
-BUILD_OPT_CFG ENDS
-
- ; A structure containing platform specific operational characteristics. This
- ; structure is initially populated by the initializer with a copy of the same
- ; structure that was created at build time using the build configuration controls.
-PLATFORM_CONFIGURATION STRUCT
- PlatformProfile PERFORMANCE_PROFILE {} ; < Several configuration settings for the processor.
- PlatformDeemphasisList POINTER ? ; < Deemphasis levels for the platform's HT links.
- CoreLevelingMode UINT8 ? ; < Indicates how to balance the number of cores per processor.
- C1eMode PLATFORM_C1E_MODES ? ; < Specifies the method of C1e enablement - Disabled, HW, or message based.
- C1ePlatformData UINT32 ? ; < If C1eMode is HW, specifies the P_LVL3 I/O port of the platform.
- C1ePlatformData1 UINT32 ? ; < If C1eMode is SW, specifies the address of chipset's SMI command port.
- C1ePlatformData2 UINT32 ? ; < If C1eMode is SW, specifies the unique number used by the SMI handler to identify SMI source.
- CStateMode PLATFORM_CSTATE_MODES ? ; < Specifies the method of C-State enablement - Disabled, or C6.
- CStatePlatformData UINT32 ? ; < This element specifies some pertinent data needed for the operation of the Cstate feature
- ; < If CStateMode is CStateModeC6, this item is reserved
- CStateIoBaseAddress UINT16 ? ; < This item specifies a free block of 8 consecutive bytes of I/O ports that
- ; < can be used to allow the CPU to enter Cstates.
- CpbMode PLATFORM_CPB_MODES ? ; < Specifies the method of core performance boost enablement - Disabled, or Auto.
- UserOptionDmi BOOLEAN ? ; < When set to TRUE, the DMI data table is generated.
- UserOptionPState BOOLEAN ? ; < When set to TRUE, the PState data tables are generated.
- UserOptionSrat BOOLEAN ? ; < When set to TRUE, the SRAT data table is generated.
- UserOptionSlit BOOLEAN ? ; < When set to TRUE, the SLIT data table is generated.
- UserOptionWhea BOOLEAN ? ; < When set to TRUE, the WHEA data table is generated.
- PowerCeiling UINT32 ? ; < P-State Ceiling Enabling Deck - Max power milli-watts.
- ForcePstateIndependent BOOLEAN ? ; < P-State _PSD independence or dependence.
- NumberOfIoApics UINT32 ? ; < Number of I/O APICs in the system
- VrmProperties PLATFORM_VRM_CONFIGURATION (MaxVrmType) DUP ({}) ; < Several configuration settings for the voltage regulator modules.
- ProcessorScopeInSb BOOLEAN ? ; < ACPI Processor Object in \_SB scope
- ProcessorScopeName0 CHAR8 ? ; < OEM specific 1st character of processor scope name.
- ProcessorScopeName1 CHAR8 ? ; < OEM specific 2nd character of processor scope name.
- GnbHdAudio UINT8 ? ; < Control GFX HD Audio controller(Used for HDMI and DP display output),
- ; < essentially it enables function 1 of graphics device.
- ; < @li 0 = HD Audio disable
- ; < @li 1 = HD Audio enable
- AbmSupport UINT8 ? ; < Automatic adjust LVDS/eDP Back light level support.It is
- ; < characteristic specific to display panel which used by platform design.
- ; < @li 0 = ABM support disabled
- ; < @li 1 = ABM support enabled
- DynamicRefreshRate UINT8 ? ; < Adjust refresh rate on LVDS/eDP.
- LcdBackLightControl UINT16 ? ; < The PWM frequency to LCD backlight control.
- ; < If equal to 0 backlight not controlled by iGPU.
-PLATFORM_CONFIGURATION ENDS
-
-
-; *********************************************************************
-; * Structures for: AmdInitLate
-; *********************************************************************
- PROC_VERSION_LENGTH EQU 48
- MAX_DIMMS_PER_SOCKET EQU 16
-
-
- ; Interface Parameter Structures
- ; DMI Type4 - Processor ID
-TYPE4_PROC_ID STRUCT
- ProcIdLsd UINT32 ? ; < Lower half of 64b ID
- ProcIdMsd UINT32 ? ; < Upper half of 64b ID
-TYPE4_PROC_ID ENDS
-
- ; DMI Type 4 - Processor information
-TYPE4_DMI_INFO STRUCT
- T4ProcType UINT8 ? ; < CPU Type
- T4ProcFamily UINT8 ? ; < Family 1
- T4ProcId TYPE4_PROC_ID {} ; < Id
- T4Voltage UINT8 ? ; < Voltage
- T4ExternalClock UINT16 ? ; < External clock
- T4MaxSpeed UINT16 ? ; < Max speed
- T4CurrentSpeed UINT16 ? ; < Current speed
- T4Status UINT8 ? ; < Status
- T4ProcUpgrade UINT8 ? ; < Up grade
- T4CoreCount UINT8 ? ; < Core count
- T4CoreEnabled UINT8 ? ; < Core Enable
- T4ThreadCount UINT8 ? ; < Thread count
- T4ProcCharacteristics UINT16 ? ; < Characteristics
- T4ProcFamily2 UINT16 ? ; < Family 2
- T4ProcVersion CHAR8 (PROC_VERSION_LENGTH) DUP (?) ; < Cpu version
-TYPE4_DMI_INFO ENDS
-
- ; DMI Type 7 - Cache information
-TYPE7_DMI_INFO STRUCT
- T7CacheCfg UINT16 ? ; < Cache cfg
- T7MaxCacheSize UINT16 ? ; < Max size
- T7InstallSize UINT16 ? ; < Install size
- T7SupportedSramType UINT16 ? ; < Supported Sram Type
- T7CurrentSramType UINT16 ? ; < Current type
- T7CacheSpeed UINT8 ? ; < Speed
- T7ErrorCorrectionType UINT8 ? ; < ECC type
- T7SystemCacheType UINT8 ? ; < Cache type
- T7Associativity UINT8 ? ; < Associativity
-TYPE7_DMI_INFO ENDS
-
- ; DMI Type 16 offset 04h - Location
-
- OtherLocation EQU 01h ; < Assign 01 to Other
- UnknownLocation EQU 2 ; < Assign 02 to Unknown
- SystemboardOrMotherboard EQU 3 ; < Assign 03 to systemboard or motherboard
- IsaAddonCard EQU 4 ; < Assign 04 to ISA add-on card
- EisaAddonCard EQU 5 ; < Assign 05 to EISA add-on card
- PciAddonCard EQU 6 ; < Assign 06 to PCI add-on card
- McaAddonCard EQU 7 ; < Assign 07 to MCA add-on card
- PcmciaAddonCard EQU 8 ; < Assign 08 to PCMCIA add-on card
- ProprietaryAddonCard EQU 9 ; < Assign 09 to proprietary add-on card
- NuBus EQU 10 ; < Assign 0A to NuBus
- Pc98C20AddonCard EQU 11 ; < Assign 0A0 to PC-98/C20 add-on card
- Pc98C24AddonCard EQU 12 ; < Assign 0A1 to PC-98/C24 add-on card
- Pc98EAddoncard EQU 13 ; < Assign 0A2 to PC-98/E add-on card
- Pc98LocalBusAddonCard EQU 14 ; < Assign 0A3 to PC-98/Local bus add-on card
-DMI_T16_LOCATION TEXTEQU <DWORD> ;} DMI_T16_LOCATION;
-
- ; DMI Type 16 offset 05h - Memory Error Correction
-
- OtherUse EQU 01h ; < Assign 01 to Other
- UnknownUse EQU 2 ; < Assign 02 to Unknown
- SystemMemory EQU 3 ; < Assign 03 to system memory
- VideoMemory EQU 4 ; < Assign 04 to video memory
- FlashMemory EQU 5 ; < Assign 05 to flash memory
- NonvolatileRam EQU 6 ; < Assign 06 to non-volatile RAM
- CacheMemory EQU 7 ; < Assign 07 to cache memory
-DMI_T16_USE TEXTEQU <DWORD> ;} DMI_T16_USE;
-
- ; DMI Type 16 offset 07h - Maximum Capacity
-
- Dmi16OtherErrCorrection EQU 01h ; < Assign 01 to Other
- Dmi16UnknownErrCorrection EQU 2 ; < Assign 02 to Unknown
- Dmi16NoneErrCorrection EQU 3 ; < Assign 03 to None
- Dmi16Parity EQU 4 ; < Assign 04 to parity
- Dmi16SingleBitEcc EQU 5 ; < Assign 05 to Single-bit ECC
- Dmi16MultiBitEcc EQU 6 ; < Assign 06 to Multi-bit ECC
- Dmi16Crc EQU 7 ; < Assign 07 to CRC
-DMI_T16_ERROR_CORRECTION TEXTEQU <DWORD> ;} DMI_T16_ERROR_CORRECTION;
-
- ; DMI Type 16 - Physical Memory Array
-TYPE16_DMI_INFO STRUCT
- Location DMI_T16_LOCATION ? ; < The physical location of the Memory Array,
- ; < whether on the system board or an add-in board.
- Use DMI_T16_USE ? ; < Identifies the function for which the array
- ; < is used.
- MemoryErrorCorrection DMI_T16_ERROR_CORRECTION ? ; < The primary hardware error correction or
- ; < detection method supported by this memory array.
- MaximumCapacity UINT32 ? ; < The maximum memory capacity, in kilobytes,
- ; < for the array.
- NumberOfMemoryDevices UINT16 ? ; < The number of slots or sockets available
- ; < for memory devices in this array.
-TYPE16_DMI_INFO ENDS
-
- ; DMI Type 17 offset 0Eh - Form Factor
- OtherFormFactor EQU 01h ; < Assign 01 to Other
- UnknowFormFactor EQU 2 ; < Assign 02 to Unknown
- SimmFormFactor EQU 3 ; < Assign 03 to SIMM
- SipFormFactor EQU 4 ; < Assign 04 to SIP
- ChipFormFactor EQU 5 ; < Assign 05 to Chip
- DipFormFactor EQU 6 ; < Assign 06 to DIP
- ZipFormFactor EQU 7 ; < Assign 07 to ZIP
- ProprietaryCardFormFactor EQU 8 ; < Assign 08 to Proprietary Card
- DimmFormFactorFormFactor EQU 9 ; < Assign 09 to DIMM
- TsopFormFactor EQU 10 ; < Assign 10 to TSOP
- RowOfChipsFormFactor EQU 11 ; < Assign 11 to Row of chips
- RimmFormFactor EQU 12 ; < Assign 12 to RIMM
- SodimmFormFactor EQU 13 ; < Assign 13 to SODIMM
- SrimmFormFactor EQU 14 ; < Assign 14 to SRIMM
- FbDimmFormFactor EQU 15 ; < Assign 15 to FB-DIMM
-DMI_T17_FORM_FACTOR TEXTEQU <DWORD>
-
- ; DMI Type 17 offset 12h - Memory Type
- OtherMemType EQU 01h ; < Assign 01 to Other
- UnknownMemType EQU 2 ; < Assign 02 to Unknown
- DramMemType EQU 3 ; < Assign 03 to DRAM
- EdramMemType EQU 4 ; < Assign 04 to EDRAM
- VramMemType EQU 5 ; < Assign 05 to VRAM
- SramMemType EQU 6 ; < Assign 06 to SRAM
- RamMemType EQU 7 ; < Assign 07 to RAM
- RomMemType EQU 8 ; < Assign 08 to ROM
- FlashMemType EQU 9 ; < Assign 09 to Flash
- EepromMemType EQU 10 ; < Assign 10 to EEPROM
- FepromMemType EQU 11 ; < Assign 11 to FEPROM
- EpromMemType EQU 12 ; < Assign 12 to EPROM
- CdramMemType EQU 13 ; < Assign 13 to CDRAM
- ThreeDramMemType EQU 14 ; < Assign 14 to 3DRAM
- SdramMemType EQU 15 ; < Assign 15 to SDRAM
- SgramMemType EQU 16 ; < Assign 16 to SGRAM
- RdramMemType EQU 17 ; < Assign 17 to RDRAM
- DdrMemType EQU 18 ; < Assign 18 to DDR
- Ddr2MemType EQU 19 ; < Assign 19 to DDR2
- Ddr2FbdimmMemType EQU 20 ; < Assign 20 to DDR2 FB-DIMM
- Ddr3MemType EQU 24 ; < Assign 24 to DDR3
- Fbd2MemType EQU 25 ; < Assign 25 to FBD2
-DMI_T17_MEMORY_TYPE TEXTEQU <DWORD>
-
- ; DMI Type 17 offset 13h - Type Detail
-DMI_T17_TYPE_DETAIL STRUCT
- Reserved1 UINT16 ?
-; OUT UINT16 Reserved1:1; ; < Reserved
-; OUT UINT16 Other:1; ; < Other
-; OUT UINT16 Unknown:1; ; < Unknown
-; OUT UINT16 FastPaged:1; ; < Fast-Paged
-; OUT UINT16 StaticColumn:1; ; < Static column
-; OUT UINT16 PseudoStatic:1; ; < Pseudo-static
-; OUT UINT16 Rambus:1; ; < RAMBUS
-; OUT UINT16 Synchronous:1; ; < Synchronous
-; OUT UINT16 Cmos:1; ; < CMOS
-; OUT UINT16 Edo:1; ; < EDO
-; OUT UINT16 WindowDram:1; ; < Window DRAM
-; OUT UINT16 CacheDram:1; ; < Cache Dram
-; OUT UINT16 NonVolatile:1; ; < Non-volatile
-; OUT UINT16 Reserved2:3; ; < Reserved
-DMI_T17_TYPE_DETAIL ENDS
-
- ; DMI Type 17 - Memory Device
-TYPE17_DMI_INFO STRUCT
- TotalWidth UINT16 ? ; < Total Width, in bits, of this memory device, including any check or error-correction bits.
- DataWidth UINT16 ? ; < Data Width, in bits, of this memory device.
- MemorySize UINT16 ? ; < The size of the memory device.
- FormFactor DMI_T17_FORM_FACTOR ? ; < The implementation form factor for this memory device.
- DeviceSet UINT8 ? ; < Identifies when the Memory Device is one of a set of
- ; < Memory Devices that must be populated with all devices of
- ; < the same type and size, and the set to which this device belongs.
- DeviceLocator CHAR8 (8) DUP (?) ; < The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
- BankLocator CHAR8 (10) DUP (?) ; < The string number of the string that identifies the physically labeled bank where the memory device is located.
- MemoryType DMI_T17_MEMORY_TYPE ? ; < The type of memory used in this device.
- TypeDetail DMI_T17_TYPE_DETAIL {} ; < Additional detail on the memory device type
- Speed UINT16 ? ; < Identifies the speed of the device, in megahertz (MHz).
- ManufacturerIdCode UINT64 ? ; < Manufacturer ID code.
- SerialNumber CHAR8 (9) DUP (?) ; < Serial Number.
- PartNumber CHAR8 (19) DUP (?) ; < Part Number.
- Attributes UINT8 ? ; < Bits 7-4: Reserved, Bits 3-0: rank.
- ExtSize UINT32 ? ; < Extended Size.
-TYPE17_DMI_INFO ENDS
-
- ; Memory DMI Type 17 and 20 - for memory use
-MEM_DMI_INFO STRUCT
- TotalWidth UINT16 ? ; ///< Total Width, in bits, of this memory device, including any check or error-correction bits.
- DataWidth UINT16 ? ; ///< Data Width, in bits, of this memory device.
- MemorySize UINT16 ? ; ///< The size of the memory device.
- FormFactor DMI_T17_FORM_FACTOR ? ; ///< The implementation form factor for this memory device.
- DeviceLocator UINT8 ? ; ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
- BankLocator UINT8 ? ; ///< The string number of the string that identifies the physically labeled bank where the memory device is located.
- Speed UINT16 ? ; ///< Identifies the speed of the device, in megahertz (MHz).
- ManufacturerIdCode UINT64 ? ; ///< Manufacturer ID code.
- SerialNumber UINT8 (4) DUP (?) ; ///< Serial Number.
- PartNumber UINT8 (18) DUP (?) ; ///< Part Number.
- Attributes UINT8 ? ; ///< Bits 7-4: Reserved, Bits 3-0: rank.
- ExtSize UINT32 ? ; ///< Extended Size.
- Socket UINT8 ?
-; OUT UINT8 Socket:3 ; ///< Socket ID
-; OUT UINT8 Channel:2 ; ///< Channel ID
-; OUT UINT8 Dimm:2 ; ///< DIMM ID
-; OUT UINT8 DimmPresent:1 ; ///< Dimm Present
- StartingAddr UINT32 ? ; ///< The physical address, in kilobytes, of a range
- ; ///< of memory mapped to the referenced Memory Device.
- EndingAddr UINT32 ? ; ///< The handle, or instance number, associated with
- ; ///< the Memory Device structure to which this address
- ; ///< range is mapped.
-MEM_DMI_INFO ENDS
-
- ; DMI Type 19 - Memory Array Mapped Address
-TYPE19_DMI_INFO STRUCT
- StartingAddr UINT32 ? ; < The physical address, in kilobytes,
- ; < of a range of memory mapped to the
- ; < specified physical memory array.
- EndingAddr UINT32 ? ; < The physical ending address of the
- ; < last kilobyte of a range of addresses
- ; < mapped to the specified physical memory array.
- MemoryArrayHandle UINT16 ? ; < The handle, or instance number, associated
- ; < with the physical memory array to which this
- ; < address range is mapped.
- PartitionWidth UINT8 ? ; < Identifies the number of memory devices that
- ; < form a single row of memory for the address
- ; < partition defined by this structure.
-TYPE19_DMI_INFO ENDS
-
-; DMI Type 20 - Memory Device Mapped Address
-TYPE20_DMI_INFO STRUCT
- StartingAddr UINT32 ? ; < The physical address, in kilobytes, of a range
- ; < of memory mapped to the referenced Memory Device.
- EndingAddr UINT32 ? ; < The handle, or instance number, associated with
- ; < the Memory Device structure to which this address
- ; < range is mapped.
- MemoryDeviceHandle UINT16 ? ; < The handle, or instance number, associated with
- ; < the Memory Device structure to which this address
- ; < range is mapped.
- MemoryArrayMappedAddressHandle UINT16 ? ; < The handle, or instance number, associated
- ; < with the Memory Array Mapped Address structure to
- ; < which this device address range is mapped.
- PartitionRowPosition UINT8 ? ; < Identifies the position of the referenced Memory
- ; < Device in a row of the address partition.
- InterleavePosition UINT8 ? ; < The position of the referenced Memory Device in
- ; < an interleave.
- InterleavedDataDepth UINT8 ? ; < The maximum number of consecutive rows from the
- ; < referenced Memory Device that are accessed in a
- ; < single interleaved transfer.
-TYPE20_DMI_INFO ENDS
-
- ; Collection of pointers to the DMI records
-DMI_INFO STRUCT
- T4 TYPE4_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Type 4 struc
- T7L1 TYPE7_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Type 7 struc 1
- T7L2 TYPE7_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Type 7 struc 2
- T7L3 TYPE7_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({}) ; < Type 7 struc 3
- T16 TYPE16_DMI_INFO {} ; < Type 16 struc
- T17 TYPE17_DMI_INFO (MAX_SOCKETS_SUPPORTED * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL) DUP ({}) ; < Type 17 struc
- T19 TYPE19_DMI_INFO {} ; < Type 19 struc
- T20 TYPE20_DMI_INFO (MAX_SOCKETS_SUPPORTED * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL) DUP ({}) ; < Type 20 struc
-DMI_INFO ENDS
-
-
-
-; *********************************************************************
-; * Interface call: AllocateExecutionCache
-; *********************************************************************
- MAX_CACHE_REGIONS EQU 3
-
- ; AllocateExecutionCache sub param structure for cached memory region
-EXECUTION_CACHE_REGION STRUCT
- ExeCacheStartAddr UINT32 ? ; < Start address
- ExeCacheSize UINT32 ? ; < Size
-EXECUTION_CACHE_REGION ENDS
-
-; *********************************************************************
-; * Interface call: AmdGetAvailableExeCacheSize
-; *********************************************************************
- ; Get available Cache remain
-AMD_GET_EXE_SIZE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- AvailableExeCacheSize UINT32 ? ; < Remain size
-AMD_GET_EXE_SIZE_PARAMS ENDS
-
-
-
-
-
-
- ; Selection type for core leveling
- CORE_LEVEL_LOWEST EQU 0 ; < Level to lowest common denominator
- CORE_LEVEL_TWO EQU 1 ; < Level to 2 cores
- CORE_LEVEL_POWER_OF_TWO EQU 2 ; < Level to 1,2,4 or 8
- CORE_LEVEL_NONE EQU 3 ; < Do no leveling
- CORE_LEVEL_COMPUTE_UNIT EQU 4 ; < Level cores to one core per compute unit
- CORE_LEVEL_ONE EQU 5 ; < Level to 1 core
- CORE_LEVEL_THREE EQU 6 ; < Level to 3 cores
- CORE_LEVEL_FOUR EQU 7 ; < Level to 4 cores
- CORE_LEVEL_FIVE EQU 8 ; < Level to 5 cores
- CORE_LEVEL_SIX EQU 9 ; < Level to 6 cores
- CORE_LEVEL_SEVEN EQU 10 ; < Level to 7 cores
- CORE_LEVEL_EIGHT EQU 11 ; < Level to 8 cores
- CORE_LEVEL_NINE EQU 12 ; < Level to 9 cores
- CORE_LEVEL_TEN EQU 13 ; < Level to 10 cores
- CORE_LEVEL_ELEVEN EQU 14 ; < Level to 11 cores
- CORE_LEVEL_TWELVE EQU 15 ; < Level to 12 cores
- CORE_LEVEL_THIRTEEN EQU 16 ; < Level to 13 cores
- CORE_LEVEL_FOURTEEN EQU 17 ; < Level to 14 cores
- CORE_LEVEL_FIFTEEN EQU 18 ; < Level to 15 cores
- CoreLevelModeMax EQU 19 ; < Used for bounds checking
-CORE_LEVELING_TYPE TEXTEQU <DWORD>
-
-
-; ***********************************************************************
-; *
-; * AGESA Basic Level interface structure definition and function prototypes
-; *
-; **********************************************************************
-
-; *********************************************************************
-; * Interface call: AmdCreateStruct
-; *********************************************************************
-
-; *********************************************************************
-; * Interface call: AmdReleaseStruct
-; *********************************************************************
-
-; *********************************************************************
-; * Interface call: AmdInitReset
-; *********************************************************************
- ; AmdInitReset param structure
-AMD_RESET_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- CacheRegion EXECUTION_CACHE_REGION (3) DUP ({}) ; < The cached memory region
- HtConfig AMD_HT_RESET_INTERFACE {} ; < The interface for Ht Recovery
-AMD_RESET_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitEarly
-; *********************************************************************
- ; InitEarly param structure
-
- ; Provide defaults or customizations to each service performed in AmdInitEarly.
-
-AMD_EARLY_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < The standard header
- CacheRegion EXECUTION_CACHE_REGION (3) DUP ({}) ; < Execution Map Interface
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- HtConfig AMD_HT_INTERFACE {} ; < HyperTransport Interface
- GnbConfig GNB_CONFIGURATION {} ; < GNB configuration
-AMD_EARLY_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitPost
-; *********************************************************************
- ; AmdInitPost param structure
-AMD_POST_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- MemConfig MEM_PARAMETER_STRUCT {} ; < Memory post param
-AMD_POST_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitEnv
-; *********************************************************************
- ; AmdInitEnv param structure
-AMD_ENV_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- GnbEnvConfiguration GNB_ENV_CONFIGURATION {} ; < platform operational characteristics.
-AMD_ENV_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitMid
-; *********************************************************************
- ; AmdInitMid param structure
-AMD_MID_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
-AMD_MID_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitLate
-; *********************************************************************
- ; AmdInitLate param structure
-AMD_LATE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- DmiTable POINTER ? ; < DMI Interface
- AcpiPState POINTER ? ; < Acpi Pstate SSDT Table
- AcpiSrat POINTER ? ; < SRAT Table
- AcpiSlit POINTER ? ; < SLIT Table
- AcpiWheaMce POINTER ? ; < WHEA MCE Table
- AcpiWheaCmc POINTER ? ; < WHEA CMC Table
- AcpiAlib POINTER ? ; < ALIB Table
-AMD_LATE_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdInitRecovery
-; *********************************************************************
- ; CPU Recovery Parameters
-AMD_CPU_RECOVERY_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard Header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics
-AMD_CPU_RECOVERY_PARAMS ENDS
-
- ; AmdInitRecovery param structure
-AMD_RECOVERY_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- MemConfig MEM_PARAMETER_STRUCT {} ; < Memory post param
- CacheRegion EXECUTION_CACHE_REGION (3) DUP ({}) ; < The cached memory region. And the max cache region is 3
- CpuRecoveryParams AMD_CPU_RECOVERY_PARAMS {} ; < Params for CPU related recovery init.
-AMD_RECOVERY_PARAMS ENDS
-
-
-; *********************************************************************
-; * Interface call: AmdInitResume
-; *********************************************************************
- ; AmdInitResume param structure
-AMD_RESUME_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < Platform operational characteristics
- S3DataBlock AMD_S3_PARAMS {} ; < Save state data
-AMD_RESUME_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdS3LateRestore
-; *********************************************************************
- ; AmdS3LateRestore param structure
-AMD_S3LATE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- S3DataBlock AMD_S3_PARAMS {} ; < Save state data
-AMD_S3LATE_PARAMS ENDS
-
-; *********************************************************************
-; * Interface call: AmdS3Save
-; *********************************************************************
- ; AmdS3Save param structure
-AMD_S3SAVE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Standard header
- PlatformConfig PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
- S3DataBlock AMD_S3_PARAMS {} ; < Standard header
-AMD_S3SAVE_PARAMS ENDS
-
- ; General Services API
-
-
-; *********************************************************************
-; * Interface service call: AmdGetApicId
-; *********************************************************************
- ; Request the APIC ID of a particular core.
-
-AMD_APIC_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services.
- Socket UINT8 ? ; < The Core's Socket.
- Core UINT8 ? ; < The Core id.
- IsPresent BOOLEAN ? ; < The Core is present, and ApicAddress is valid.
- ApicAddress UINT8 ? ; < The Core's APIC ID.
-AMD_APIC_PARAMS ENDS
-
-; *********************************************************************
-; * Interface service call: AmdGetPciAddress
-; *********************************************************************
- ; Request the PCI Address of a Processor Module (that is, its Northbridge)
-
-AMD_GET_PCI_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services.
- Socket UINT8 ? ; < The Processor's socket
- Module UINT8 ? ; < The Module in that Processor
- IsPresent BOOLEAN ? ; < The Core is present, and PciAddress is valid.
- PciAddress PCI_ADDR {} ; < The Processor's PCI Config Space address (Function 0, Register 0)
-AMD_GET_PCI_PARAMS ENDS
-
-; *********************************************************************
-; * Interface service call: AmdIdentifyCore
-; *********************************************************************
- ; Request the identity (Socket, Module, Core) of the current Processor Core
-
-AMD_IDENTIFY_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services.
- Socket UINT8 ? ; < The current Core's Socket
- Module UINT8 ? ; < The current Core's Processor Module
- Core UINT8 ? ; < The current Core's core id.
-AMD_IDENTIFY_PARAMS ENDS
-
-; *********************************************************************
-; * Interface service call: AmdReadEventLog
-; *********************************************************************
- ; An Event Log Entry.
-EVENT_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services.
- EventClass UINT32 ? ; < The severity of this event, matches AGESA_STATUS.
- EventInfo UINT32 ? ; < The unique event identifier, zero means "no event".
- DataParam1 UINT32 ? ; < Data specific to the Event.
- DataParam2 UINT32 ? ; < Data specific to the Event.
- DataParam3 UINT32 ? ; < Data specific to the Event.
- DataParam4 UINT32 ? ; < Data specific to the Event.
-EVENT_PARAMS ENDS
-
-; *********************************************************************
-; * Interface service call: AmdIdentifyDimm
-; *********************************************************************
- ; Request the identity of dimm from system address
-
-AMD_IDENTIFY_DIMM STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Header for library and services.
- MemoryAddress UINT64 ? ; < System Address that needs to be translated to dimm identification.
- SocketId UINT8 ? ; < The socket on which the targeted address locates.
- MemChannelId UINT8 ? ; < The channel on which the targeted address locates.
- DimmId UINT8 ? ; < The dimm on which the targeted address locates.
-AMD_IDENTIFY_DIMM ENDS
-
- ; Data structure for the Mapping Item between Unified ID for IDS Setup Option
- ; and the option value.
-
-IDS_NV_ITEM STRUCT
- IdsNvId UINT16 ? ; < Unified ID for IDS Setup Option.
- IdsNvValue UINT16 ? ; < The value of IDS Setup Option.
-IDS_NV_ITEM ENDS
-
- ; Data Structure for IDS CallOut Function
-IDS_CALLOUT_STRUCT STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < The Standard Header for AGESA Service
- IdsNvPtr POINTER ? ; < Memory Pointer of IDS NV Table
- Reserved UINT32 ? ; < reserved
-IDS_CALLOUT_STRUCT ENDS
-
- AGESA_IDS_DFT_VAL EQU 0FFFFh; < Default value of every uninitlized NV item, the action for it will be ignored
- AGESA_IDS_NV_END EQU 0FFFFh; < Flag specify end of option structure
-; WARNING: Don't change the comment below, it used as signature for script
-; AGESA IDS NV ID Definitions
- AGESA_IDS_EXT_ID_START EQU 0000h; < specify the start of external NV id
-
- AGESA_IDS_NV_UCODE EQU 0001h; < Enable or disable microcode patching
-
- AGESA_IDS_NV_TARGET_PSTATE EQU 0002h; < Set the P-state required to be activated
- AGESA_IDS_NV_POSTPSTATE EQU 0003h; < Set the P-state required to be activated through POST
-
- AGESA_IDS_NV_BANK_INTERLEAVE EQU 0004h; < Enable or disable Bank Interleave
- AGESA_IDS_NV_CHANNEL_INTERLEAVE EQU 0005h; < Enable or disable Channel Interleave
- AGESA_IDS_NV_NODE_INTERLEAVE EQU 0006h; < Enable or disable Node Interleave
- AGESA_IDS_NV_MEMHOLE EQU 0007h; < Enables or disable memory hole
-
- AGESA_IDS_NV_SCRUB_REDIRECTION EQU 0008h; < Enable or disable a write to dram with corrected data
- AGESA_IDS_NV_DRAM_SCRUB EQU 0009h; < Set the rate of background scrubbing for DRAM
- AGESA_IDS_NV_DCACHE_SCRUB EQU 000Ah; < Set the rate of background scrubbing for the DCache.
- AGESA_IDS_NV_L2_SCRUB EQU 000Bh; < Set the rate of background scrubbing for the L2 cache
- AGESA_IDS_NV_L3_SCRUB EQU 000Ch; < Set the rate of background scrubbing for the L3 cache
- AGESA_IDS_NV_ICACHE_SCRUB EQU 000Dh; < Set the rate of background scrubbing for the Icache
- AGESA_IDS_NV_SYNC_ON_ECC_ERROR EQU 000Eh; < Enable or disable the sync flood on un-correctable ECC error
- AGESA_IDS_NV_ECC_SYMBOL_SIZE EQU 000Fh; < Set ECC symbol size
-
- AGESA_IDS_NV_ALL_MEMCLKS EQU 0010h; < Enable or disable all memory clocks enable
- AGESA_IDS_NV_DCT_GANGING_MODE EQU 0011h; < Set the Ganged mode
- AGESA_IDS_NV_DRAM_BURST_LENGTH32 EQU 0012h; < Set the DRAM Burst Length 32
- AGESA_IDS_NV_MEMORY_POWER_DOWN EQU 0013h; < Enable or disable Memory power down mode
- AGESA_IDS_NV_MEMORY_POWER_DOWN_MODE EQU 0014h; < Set the Memory power down mode
- AGESA_IDS_NV_DLL_SHUT_DOWN EQU 0015h; < Enable or disable DLLShutdown
- AGESA_IDS_NV_ONLINE_SPARE EQU 0016h; < Enable or disable the Dram controller to designate a DIMM bank as a spare for logical swap
-
- AGESA_IDS_NV_HT_ASSIST EQU 0017h; < Enable or Disable HT Assist
- AGESA_IDS_NV_ATMMODE EQU 0018h; < Enable or Disable ATM mode
-
- AGESA_IDS_NV_HDTOUT EQU 0019h; < Enable or disable HDTOUT feature
-
- AGESA_IDS_NV_HTLINKSOCKET EQU 001Ah; < HT Link Socket
- AGESA_IDS_NV_HTLINKPORT EQU 001Bh; < HT Link Port
- AGESA_IDS_NV_HTLINKFREQ EQU 001Ch; < HT Link Frequency
- AGESA_IDS_NV_HTLINKWIDTHIN EQU 001Dh; < HT Link In Width
- AGESA_IDS_NV_HTLINKWIDTHOUT EQU 001Eh; < HT Link Out Width
-
- AGESA_IDS_NV_GNBHDAUDIOEN EQU 001Fh; < Enable or disable GNB HD Audio
-
- AGESA_IDS_NV_CPB_EN EQU 0020h; < Core Performance Boost
-
- AGESA_IDS_NV_HTC_EN EQU 0021h; < HTC Enable
- AGESA_IDS_NV_HTC_OVERRIDE EQU 0022h; < HTC Override
- AGESA_IDS_NV_HTC_PSTATE_LIMIT EQU 0023h; < HTC P-state limit select
- AGESA_IDS_NV_HTC_TEMP_HYS EQU 0024h; < HTC Temperature Hysteresis
- AGESA_IDS_NV_HTC_ACT_TEMP EQU 0025h; < HTC Activation Temp
-
- AGESA_IDS_NV_POWER_POLICY EQU 0026h; < Select Platform Power Policy
- AGESA_IDS_EXT_ID_END EQU 0027h; < specify the end of external NV ID
-
- IDS_EX_NV_ID TEXTEQU <DWORD>
diff --git a/src/vendorcode/amd/agesa/Legacy/amd.inc b/src/vendorcode/amd/agesa/Legacy/amd.inc
deleted file mode 100644
index b716202..0000000
--- a/src/vendorcode/amd/agesa/Legacy/amd.inc
+++ /dev/null
@@ -1,461 +0,0 @@
-; ****************************************************************************
-; *
-; * @file
-; *
-; * Agesa structures and definitions
-; *
-; * Contains AMD AGESA core interface
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Include
-; * @e \$Revision: 33891 $ @e \$Date: 2010-06-26 00:22:54 +0800 (Sat, 26 Jun 2010) $
-;
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
-
-UINT64 TEXTEQU <QWORD>
-UINT32 TEXTEQU <DWORD>
-UINT16 TEXTEQU <WORD>
-UINT8 TEXTEQU <BYTE>
-CHAR8 TEXTEQU <BYTE>
-BOOLEAN TEXTEQU <BYTE>
-POINTER TEXTEQU <DWORD>
-
- ; AGESA Types and Definitions
-
- AGESA_REVISION EQU "Arch2008"
- AGESA_ID EQU "AGESA"
-
- LAST_ENTRY EQU 0FFFFFFFFh
- IMAGE_SIGNATURE EQU 'DMA$'
- IOCF8 EQU 0CF8h
- IOCFC EQU 0CFCh
-
- ; The return status for all AGESA public services.
-
- ; Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
- ; will have log entries with more detail.
-
- AGESA_SUCCESS EQU 0 ; < The service completed normally. Info may be logged.
- AGESA_UNSUPPORTED EQU 1 ; < The dispatcher or create struct had an unimplemented function requested.
- ; < Not logged.
- AGESA_BOUNDS_CHK EQU 2 ; < A dynamic parameter was out of range and the service was not provided.
- ; < Example, memory address not installed, heap buffer handle not found.
- ; < Not Logged.
- ; AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
- AGESA_ALERT EQU 3 ; < An observed condition, but no loss of function.
- ; < See log. Example, HT CRC.
- AGESA_WARNING EQU 4 ; < Possible or minor loss of function. See Log.
- AGESA_ERROR EQU 5 ; < Significant loss of function, boot may be possible. See Log.
- AGESA_CRITICAL EQU 6 ; < Continue boot only to notify user. See Log.
- AGESA_FATAL EQU 7 ; < Halt booting. See Log.
- AgesaStatusMax EQU 8 ; < Not a status, use for limit checking.
-AGESA_STATUS TEXTEQU <DWORD>
-
-; For checking whether a status is at or above the mandatory log level.
-AGESA_STATUS_LOG_LEVEL EQU AGESA_ALERT
-
- CALLOUT_ENTRY TEXTEQU <POINTER>
- IMAGE_ENTRY TEXTEQU <POINTER>
- MODULE_ENTRY TEXTEQU <POINTER>
-
-; This allocation type is used by the AmdCreateStruct entry point
- PreMemHeap EQU 0 ; < Create heap in cache.
- PostMemDram EQU 1 ; < Create heap in memory.
- ByHost EQU 2 ; < Create heap by Host.
-ALLOCATION_METHOD TEXTEQU <DWORD>
-
- ; These width descriptors are used by the library function, and others, to specify the data size
- AccessWidth8 EQU 1 ; < Access width is 8 bits.
- AccessWidth16 EQU 2 ; < Access width is 16 bits.
- AccessWidth32 EQU 3 ; < Access width is 32 bits.
- AccessWidth64 EQU 4 ; < Access width is 64 bits.
-
- AccessS3SaveWidth8 EQU 81h ; < Save 8 bits data.
- AccessS3SaveWidth16 EQU 130 ; < Save 16 bits data.
- AccessS3SaveWidth32 EQU 131 ; < Save 32 bits data.
- AccessS3SaveWidth64 EQU 132 ; < Save 64 bits data.
-ACCESS_WIDTH TEXTEQU <DWORD>
-
- ; AGESA struct name
-
- ; AGESA BASIC FUNCTIONS
- AMD_INIT_RECOVERY EQU 00020000h
- AMD_CREATE_STRUCT EQU 00020001h
- AMD_INIT_EARLY EQU 00020002h
- AMD_INIT_ENV EQU 00020003h
- AMD_INIT_LATE EQU 00020004h
- AMD_INIT_MID EQU 00020005h
- AMD_INIT_POST EQU 00020006h
- AMD_INIT_RESET EQU 00020007h
- AMD_INIT_RESUME EQU 00020008h
- AMD_RELEASE_STRUCT EQU 00020009h
- AMD_S3LATE_RESTORE EQU 0002000Ah
- AMD_S3_SAVE EQU 0002000Bh
- AMD_GET_APIC_ID EQU 0002000Ch
- AMD_GET_PCI_ADDRESS EQU 0002000Dh
- AMD_IDENTIFY_CORE EQU 0002000Eh
- AMD_READ_EVENT_LOG EQU 0002000Fh
- AMD_GET_EXECACHE_SIZE EQU 00020010h
- AMD_LATE_RUN_AP_TASK EQU 00020011h
- AMD_IDENTIFY_DIMMS EQU 00020012h
-AGESA_STRUCT_NAME TEXTEQU <DWORD>
-
-
- ; ResetType constant values
- WARM_RESET_WHENEVER EQU 1
- COLD_RESET_WHENEVER EQU 2
- WARM_RESET_IMMEDIATELY EQU 3
- COLD_RESET_IMMEDIATELY EQU 4
-
-
- ; AGESA Structures
-
- ; The standard header for all AGESA services.
-AMD_CONFIG_PARAMS STRUCT
- ImageBasePtr UINT32 ? ; < The AGESA Image base address.
- Func UINT32 ? ; < The service desired, @sa dispatch.h.
- AltImageBasePtr UINT32 ? ; < Alternate Image location
- CalloutPtr CALLOUT_ENTRY ? ; < For Callout from AGESA
- HeapStatus UINT8 ? ; < For heap status from boot time slide.
- HeapBasePtr UINT64 ? ; < Location of the heap
- Reserved UINT8 (7) DUP (?) ; < This space is reserved for future use.
-AMD_CONFIG_PARAMS ENDS
-
-
- ; Create Struct Interface.
-AMD_INTERFACE_PARAMS STRUCT
- StdHeader AMD_CONFIG_PARAMS {} ; < Config header
- AgesaFunctionName AGESA_STRUCT_NAME ? ; < The service to init, @sa dispatch.h
- AllocationMethod ALLOCATION_METHOD ? ; < How to handle buffer allocation
- NewStructSize UINT32 ? ; < The size of the allocated data, in for ByHost, else out only.
- NewStructPtr POINTER ? ; < The struct for the service.
- ; < The struct to init for ByHost allocation,
- ; < the initialized struct on return.
-AMD_INTERFACE_PARAMS ENDS
-
- FUNC_0 EQU 0 ; bit-placed for PCI address creation
- FUNC_1 EQU 1
- FUNC_2 EQU 2
- FUNC_3 EQU 3
- FUNC_4 EQU 4
- FUNC_5 EQU 5
- FUNC_6 EQU 6
- FUNC_7 EQU 7
-
- ; AGESA Binary module header structure
-AMD_IMAGE_HEADER STRUCT
- Signature UINT32 ? ; < Binary Signature
- CreatorID CHAR8 (8) DUP (?) ; < 8 characters ID
- Version CHAR8 (12) DUP (?) ; < 12 characters version
- ModuleInfoOffset UINT32 ? ; < Offset of module
- EntryPointAddress UINT32 ? ; < Entry address
- ImageBase UINT32 ? ; < Image base
- RelocTableOffset UINT32 ? ; < Relocate Table offset
- ImageSize UINT32 ? ; < Size
- Checksum UINT16 ? ; < Checksum
- ImageType UINT8 ? ; < Type
- V_Reserved UINT8 ? ; < Reserved
-AMD_IMAGE_HEADER ENDS
- ; AGESA Binary module header structure
-AMD_MODULE_HEADER STRUCT
- ModuleHeaderSignature UINT32 ? ; < Module signature
- ModuleIdentifier CHAR8 (8) DUP (?) ; < 8 characters ID
- ModuleVersion CHAR8 (12) DUP (?) ; < 12 characters version
- ModuleDispatcher POINTER ? ; < A pointer point to dispatcher
- NextBlock POINTER ? ; < Next module header link
-AMD_MODULE_HEADER ENDS
-
-; AMD_CODE_HEADER Signatures.
-AGESA_CODE_SIGNATURE TEXTEQU <'!', '!', 'A', 'G', 'E', 'S', 'A', ' '>
-CIMXNB_CODE_SIGNATURE TEXTEQU <'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'>
-CIMXSB_CODE_SIGNATURE TEXTEQU <'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'>
-
-; AGESA_CODE_SIGNATURE
-AMD_CODE_HEADER STRUCT
- Signature CHAR8 (8) DUP (?) ; < code header Signature
- ComponentName CHAR8 (8) DUP (?) ; < 8 character name of the code module
- Version CHAR8 (12) DUP (?) ; < 12 character version string
- TerminatorNull CHAR8 ? ; < null terminated string
- VerReserved CHAR8 (7) DUP (?) ; < reserved space
-AMD_CODE_HEADER ENDS
-
- ; Extended PCI address format
-EXT_PCI_ADDR STRUCT
- Register UINT32 ?
-; IN OUT UINT32 Register:12; ; < Register offset
-; IN OUT UINT32 Function:3; ; < Function number
-; IN OUT UINT32 Device:5; ; < Device number
-; IN OUT UINT32 Bus:8; ; < Bus number
-; IN OUT UINT32 Segment:4; ; < Segment
-EXT_PCI_ADDR ENDS
-
- ; Union type for PCI address
-PCI_ADDR UNION
- AddressValue UINT32 ? ; < Formal address
- Address EXT_PCI_ADDR {} ; < Extended address
-PCI_ADDR ENDS
-
- ; SBDFO - Segment Bus Device Function Offset
- ; 31:28 Segment (4-bits)
- ; 27:20 Bus (8-bits)
- ; 19:15 Device (5-bits)
- ; 14:12 Function(3-bits)
- ; 11:00 Offset (12-bits)
-
-
-
- ILLEGAL_SBDFO EQU 0FFFFFFFFh
-
- ; CPUID data received registers format
-CPUID_DATA STRUCT
- EAX_Reg UINT32 ? ; < CPUID instruction result in EAX
- EBX_Reg UINT32 ? ; < CPUID instruction result in EBX
- ECX_Reg UINT32 ? ; < CPUID instruction result in ECX
- EDX_Reg UINT32 ? ; < CPUID instruction result in EDX
-CPUID_DATA ENDS
-
- ; HT frequency for external callbacks
-;typedef enum {
- HT_FREQUENCY_200M EQU 0 ; < HT speed 200 for external callbacks
- HT_FREQUENCY_400M EQU 2 ; < HT speed 400 for external callbacks
- HT_FREQUENCY_600M EQU 4 ; < HT speed 600 for external callbacks
- HT_FREQUENCY_800M EQU 5 ; < HT speed 800 for external callbacks
- HT_FREQUENCY_1000M EQU 6 ; < HT speed 1000 for external callbacks
- HT_FREQUENCY_1200M EQU 7 ; < HT speed 1200 for external callbacks
- HT_FREQUENCY_1400M EQU 8 ; < HT speed 1400 for external callbacks
- HT_FREQUENCY_1600M EQU 9 ; < HT speed 1600 for external callbacks
- HT_FREQUENCY_1800M EQU 10 ; < HT speed 1800 for external callbacks
- HT_FREQUENCY_2000M EQU 11 ; < HT speed 2000 for external callbacks
- HT_FREQUENCY_2200M EQU 12 ; < HT speed 2200 for external callbacks
- HT_FREQUENCY_2400M EQU 13 ; < HT speed 2400 for external callbacks
- HT_FREQUENCY_2600M EQU 14 ; < HT speed 2600 for external callbacks
- HT_FREQUENCY_2800M EQU 17 ; < HT speed 2800 for external callbacks
- HT_FREQUENCY_3000M EQU 18 ; < HT speed 3000 for external callbacks
- HT_FREQUENCY_3200M EQU 19 ; < HT speed 3200 for external callbacks
- HT_FREQUENCY_MAX EQU 20 ; < Limit Check.
-HT_FREQUENCIES TEXTEQU <DWORD> ;} HT_FREQUENCIES;
-
-HT3_FREQUENCY_MIN EQU HT_FREQUENCY_1200M
-
-IFNDEF BIT0
- BIT0 EQU 0000000000000001h
-ENDIF
-IFNDEF BIT1
- BIT1 EQU 0000000000000002h
-ENDIF
-IFNDEF BIT2
- BIT2 EQU 0000000000000004h
-ENDIF
-IFNDEF BIT3
- BIT3 EQU 0000000000000008h
-ENDIF
-IFNDEF BIT4
- BIT4 EQU 0000000000000010h
-ENDIF
-IFNDEF BIT5
- BIT5 EQU 0000000000000020h
-ENDIF
-IFNDEF BIT6
- BIT6 EQU 0000000000000040h
-ENDIF
-IFNDEF BIT7
- BIT7 EQU 0000000000000080h
-ENDIF
-IFNDEF BIT8
- BIT8 EQU 0000000000000100h
-ENDIF
-IFNDEF BIT9
- BIT9 EQU 0000000000000200h
-ENDIF
-IFNDEF BIT10
- BIT10 EQU 0000000000000400h
-ENDIF
-IFNDEF BIT11
- BIT11 EQU 0000000000000800h
-ENDIF
-IFNDEF BIT12
- BIT12 EQU 0000000000001000h
-ENDIF
-IFNDEF BIT13
- BIT13 EQU 0000000000002000h
-ENDIF
-IFNDEF BIT14
- BIT14 EQU 0000000000004000h
-ENDIF
-IFNDEF BIT15
- BIT15 EQU 0000000000008000h
-ENDIF
-IFNDEF BIT16
- BIT16 EQU 0000000000010000h
-ENDIF
-IFNDEF BIT17
- BIT17 EQU 0000000000020000h
-ENDIF
-IFNDEF BIT18
- BIT18 EQU 0000000000040000h
-ENDIF
-IFNDEF BIT19
- BIT19 EQU 0000000000080000h
-ENDIF
-IFNDEF BIT20
- BIT20 EQU 0000000000100000h
-ENDIF
-IFNDEF BIT21
- BIT21 EQU 0000000000200000h
-ENDIF
-IFNDEF BIT22
- BIT22 EQU 0000000000400000h
-ENDIF
-IFNDEF BIT23
- BIT23 EQU 0000000000800000h
-ENDIF
-IFNDEF BIT24
- BIT24 EQU 0000000001000000h
-ENDIF
-IFNDEF BIT25
- BIT25 EQU 0000000002000000h
-ENDIF
-IFNDEF BIT26
- BIT26 EQU 0000000004000000h
-ENDIF
-IFNDEF BIT27
- BIT27 EQU 0000000008000000h
-ENDIF
-IFNDEF BIT28
- BIT28 EQU 0000000010000000h
-ENDIF
-IFNDEF BIT29
- BIT29 EQU 0000000020000000h
-ENDIF
-IFNDEF BIT30
- BIT30 EQU 0000000040000000h
-ENDIF
-IFNDEF BIT31
- BIT31 EQU 0000000080000000h
-ENDIF
-IFNDEF BIT32
- BIT32 EQU 0000000100000000h
-ENDIF
-IFNDEF BIT33
- BIT33 EQU 0000000200000000h
-ENDIF
-IFNDEF BIT34
- BIT34 EQU 0000000400000000h
-ENDIF
-IFNDEF BIT35
- BIT35 EQU 0000000800000000h
-ENDIF
-IFNDEF BIT36
- BIT36 EQU 0000001000000000h
-ENDIF
-IFNDEF BIT37
- BIT37 EQU 0000002000000000h
-ENDIF
-IFNDEF BIT38
- BIT38 EQU 0000004000000000h
-ENDIF
-IFNDEF BIT39
- BIT39 EQU 0000008000000000h
-ENDIF
-IFNDEF BIT40
- BIT40 EQU 0000010000000000h
-ENDIF
-IFNDEF BIT41
- BIT41 EQU 0000020000000000h
-ENDIF
-IFNDEF BIT42
- BIT42 EQU 0000040000000000h
-ENDIF
-IFNDEF BIT43
- BIT43 EQU 0000080000000000h
-ENDIF
-IFNDEF BIT44
- BIT44 EQU 0000100000000000h
-ENDIF
-IFNDEF BIT45
- BIT45 EQU 0000200000000000h
-ENDIF
-IFNDEF BIT46
- BIT46 EQU 0000400000000000h
-ENDIF
-IFNDEF BIT47
- BIT47 EQU 0000800000000000h
-ENDIF
-IFNDEF BIT48
- BIT48 EQU 0001000000000000h
-ENDIF
-IFNDEF BIT49
- BIT49 EQU 0002000000000000h
-ENDIF
-IFNDEF BIT50
- BIT50 EQU 0004000000000000h
-ENDIF
-IFNDEF BIT51
- BIT51 EQU 0008000000000000h
-ENDIF
-IFNDEF BIT52
- BIT52 EQU 0010000000000000h
-ENDIF
-IFNDEF BIT53
- BIT53 EQU 0020000000000000h
-ENDIF
-IFNDEF BIT54
- BIT54 EQU 0040000000000000h
-ENDIF
-IFNDEF BIT55
- BIT55 EQU 0080000000000000h
-ENDIF
-IFNDEF BIT56
- BIT56 EQU 0100000000000000h
-ENDIF
-IFNDEF BIT57
- BIT57 EQU 0200000000000000h
-ENDIF
-IFNDEF BIT58
- BIT58 EQU 0400000000000000h
-ENDIF
-IFNDEF BIT59
- BIT59 EQU 0800000000000000h
-ENDIF
-IFNDEF BIT60
- BIT60 EQU 1000000000000000h
-ENDIF
-IFNDEF BIT61
- BIT61 EQU 2000000000000000h
-ENDIF
-IFNDEF BIT62
- BIT62 EQU 4000000000000000h
-ENDIF
-IFNDEF BIT63
- BIT63 EQU 8000000000000000h
-ENDIF
-
diff --git a/src/vendorcode/amd/agesa/Legacy/bridge32.inc b/src/vendorcode/amd/agesa/Legacy/bridge32.inc
deleted file mode 100644
index 8685c6c..0000000
--- a/src/vendorcode/amd/agesa/Legacy/bridge32.inc
+++ /dev/null
@@ -1,577 +0,0 @@
-; ****************************************************************************
-; *
-; * @file
-; *
-; * Agesa structures and definitions
-; *
-; * Contains AMD AGESA core interface
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Include
-; * @e \$Revision: 23714 $ @e \$Date: 2009-12-10 07:28:37 +0800 (Thu, 10 Dec 2009) $
-;
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
-PARAM1 textequ <[bp+8]>
-PARAM2 textequ <[bp+12]>
-PARAM3 textequ <[bp+16]>
-RETAddress textequ <[bp+4]>
-
-AMD_PRIVATE_PARAMS STRUCT
- Gate16_CS DW ? ; Segment of AMD_BRIDGE_32 and AMD_CALLOUT_16
- Gate16_SS DW ? ; RM stack segment
- Router_Seg DW ? ; Segment of oem router
- Router_Off DW ? ; Offset of oem router
-AMD_PRIVATE_PARAMS ENDS
-
-; OEM may pre-define the GDT and selector offsets. If they do not, use our defaults.
-IFNDEF AGESA_SELECTOR_GDT
- AGESA_SELECTOR_GDT EQU 00h
-ENDIF
-IFNDEF AGESA_SELECTOR_CODE16
- AGESA_SELECTOR_CODE16 EQU 08h
-ENDIF
-IFNDEF AGESA_SELECTOR_DATA16
- AGESA_SELECTOR_DATA16 EQU 10h
-ENDIF
-IFNDEF AGESA_SELECTOR_CODE32
- AGESA_SELECTOR_CODE32 EQU 18h
-ENDIF
-IFNDEF AGESA_SELECTOR_DATA32
- AGESA_SELECTOR_DATA32 EQU 20h
-ENDIF
-
-
-AMD_BRIDGE_32_GDT MACRO GDT_Name:REQ
-
- GDT_Name LABEL BYTE
- DD 000000000h, 000000000h ; NULL descriptor
- DD 00000ffffh, 000009b00h ; 16-bit code, fixed up
- DD 00000ffffh, 000009300h ; 16-bit data, fixed up
- DD 00000ffffh, 000CF9B00h ; 32-bit protected mode code
- DD 00000ffffh, 000CF9300h ; 32-bit protected mode data
- GDT_Length EQU ($-GDT_Name)
-
-ENDM
-
-;+-------------------------------------------------------------------------
-;
-; AMD_BRIDGE_32 - Execute Agesa through Pushhigh interface
-;
-; Processing:
-; The following steps are taken:
-; 1) Enter 32bit Protected Mode (PM32)
-; 2) Run AGESA code
-; 3) Restore Real Mode (RM)
-;
-; Entry:
-; [big real mode] : ds, es set to base 0 limit 4G segment
-; EDX - if not 0, provides a FAR PTR to oem router (Seg | Offset)
-; ESI - configuration block pointer
-;
-; Exit:
-; EAX - return value
-; ESI - configuration block pointer
-; ds, es, fs, gs - Set to 4GB segment limit for Big Real Mode
-;
-; Modified:
-; None
-;
-
-AMD_BRIDGE_32 MACRO GDT_Name
-
- local copyGDT
- local flushTo16PM
- local agesaReturnAddress
- local leave32bitPM
- local flush2RM
-
- push gs
- push fs
- push ebx
- push ecx
- push edi
- mov eax, esp
- push eax
- movzx esp, sp
-;
-; Do not use any locals here, BP will be changed frequently during RM->PM32->RM
-;
- pushf
- cli ; Disable interrupts during AGESA
- cld ; Need known direction flag during AGESA
-
-;
-; Save the FAR PTR input parameter
-;
- mov gs, dx ; Offset
- shr edx, 16
- mov fs, dx ; Segment
-;
-; Determine where our binary file is and get entry point
-;
- mov edx, (AMD_CONFIG_PARAMS PTR [esi]).ImageBasePtr
- add edx, (AMD_IMAGE_HEADER PTR [edx]).EntryPointAddress
-;
-; Figure out the return address we will use after calling AGESA
-; and store it in ebx until we have our stack set up properly
-;
- mov ebx, cs
- shl ebx, 4
- add ebx, OFFSET agesaReturnAddress
-;
-; Save our current RM stack AND entry EBP
-;
- push ebp
-; push esp
- push ss
-
-;
-; BEGIN --- STACK MUST BE BALANCED AT THIS POINT --- BEGIN
-;
-; Copy the GDT onto the stack for modification
-;
- mov cx, GDT_Length
- sub sp, cx
- mov bp, sp
- lea di, GDT_Name
-copyGDT:
- mov al, cs:[di]
- mov [bp], al
- inc di
- inc bp
- loop copyGDT
-;
-; Patch 16-bit code and data descriptors on stack. We will
-; fix up CS and SS for PM16 during the callout if applicable.
-;
- mov bp, sp
-
- mov eax, cs
- shl eax, 4
- mov [bp+AGESA_SELECTOR_CODE16+2], ax
- shr eax, 16
- mov [bp+AGESA_SELECTOR_CODE16+4], al
-
- mov eax, ss
- shl eax, 4
- mov [bp+AGESA_SELECTOR_DATA16+2], ax
- shr eax, 16
- mov [bp+AGESA_SELECTOR_DATA16+4], al
-;
-; Need to place Length and Address on GDT
-;
- mov eax, ss
- shl eax, 4
- add eax, esp
- push eax
- push WORD PTR (GDT_Length-1)
-;
-; Load the GDT
-;
- mov bp, sp
- lgdt FWORD PTR [bp]
-;
-; TABLE 1
-;
-; Place PRIVATE DATA on stack DIRECTLY following GDT
-; During this routine, stack data is critical. If
-; order is changed or additional added, bad things
-; will happen!
-;
-; HIGHEST PHYSICAL ADDRESS
-;
-; | ... |
-; ------------------------
-; | old RM SP |
-; | old RM SS |
-; ------------------------ sp + SIZEOF AMD_PRIVATE_PARAMS + (SIZEOF GDT_LENGTH + 6 {size, address})
-; | GDT_DATA32 |
-; | ... |
-; | GDT_NULL |
-; | GDT Addr, Length |
-; ------------------------ sp + SIZEOF AMD_PRIVATE_PARAMS
-; | Priv.Gate16_SS |
-; | Priv.Gate16_CS |
-; ------------------------ sp
-; ------ THEN PUSH -------
-; | Return to 16-bit CS |
-; | Return to 16-bit Off |
-; | ... |
-;
-; LOWEST PHYSICAL ADDRESS
-;
- mov edi, esp
- sub edi, SIZEOF AMD_PRIVATE_PARAMS
- mov ax, cs
- mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_CS, ax
- mov ax, ss
- mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_SS, ax
- mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Off, gs
- mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Seg, fs
-
- mov esp, edi
-;
-; Save an address for returning to 16 bit real mode on stack,
-; we'll use it in a far ret after turning off CR0.PE so that
-; we can take our address off and force a far jump. Be sure
-; no unexpected data is on the stack after this!
-;
- mov ax, cs
- push cs
- lea ax, flush2RM
- push ax
-;
-; Convert ss:esp to "flat"
-;
-
- mov ax, sp
- push ax
- mov eax, ss
- shl eax, 4
- add eax, esp
- mov esp, eax ; Load the zero based ESP
-
-;
-; Set CR0.PE
-;
- mov eax, CR0 ; Get CPU control word 0
- or al, 01 ; Enable CPU protected mode
- mov CR0, eax ; Write back to CPU control word 0
- jmp flushTo16PM
-
-flushTo16PM:
-;
-; 16-bit protected mode
-;
- mov ax, AGESA_SELECTOR_DATA32
- mov ds, ax
- mov es, ax
- mov fs, ax
- mov gs, ax
- mov ss, ax
-;
-; Push our parameters RIGHT TO LEFT, and then return address
-;
- push esi ; AGESA configuration block pointer (data)
- push ebx ; after AGESA return offset (32PM flat) - consumed by dispatcher ret
- pushd AGESA_SELECTOR_CODE32 ; AGESA entry selector (32PM flat)
- push edx ; AGESA entry point (32PM flat)
-
- DB 066h
- retf ; <><><> Enter AGESA 32-bit code!!! <><><>
-
-agesaReturnAddress:
-;
-; Returns from the Agesa 32-bit code still PM32
-;
- DB 0EAh
- DD OFFSET leave32bitPM
- DW AGESA_SELECTOR_CODE16
-
-leave32bitPM:
-;
-; Now in 16-bit PM
-;
- add esp, 4 ; +4 to remove our config block pointer
-;
-; Eax reserve AGESA_STATUS return code, save it
-;
- mov ebx, eax
-;
-; Turn off CR0.PE, restore 64K stack limit
-;
- pop ax
- mov sp, ax
- mov ax, AGESA_SELECTOR_DATA16
- mov ss, ax
-
- mov eax, CR0
- and al, NOT 1 ; Disable protected mode
- mov CR0, eax ; Write back CR0.PE
-;
-; Jump far to enter RM, we saved this address on the stack
-; already. Hopefully stack is balanced through AGESA
-; nor were any params added by pushing them on the stack and
-; not removing them between BEGIN-END comments.
-;
- retf
-
-flush2RM:
-;
-; Set segments registers for big real mode before returning
-;
- xor ax, ax
- mov ds, ax
- mov es, ax
- mov fs, ax
- mov gs, ax
-;
-; Discard GDT, +6 for GDT pointer/size, privates
-;
- add esp, GDT_Length + 6 + SIZEOF AMD_PRIVATE_PARAMS
-;
-; Restore real mode stack and entry EBP
-;
- pop cx
-; mov esp, [esp]
- mov ss, cx
- pop ebp
-;
-; Restore AGESA_STATUS return code to eax
-;
- mov eax, ebx
-;
-; END --- STACK MUST BE BALANCED TO THIS POINT --- END
-;
-
- popf
- pop ebx
- mov esp, ebx
- pop edi
- pop ecx
- pop ebx
- pop fs
- pop gs
- ; EXIT AMD_BRIDGE_32
-ENDM
-;+-------------------------------------------------------------------------
-;
-; AMD_CALLOUT_16 - Execute Callback from Pushhigh interface
-;
-; Processing:
-; The following steps are taken:
-; 1) Enter PM16
-; 2) Setup stack, get private params
-; 3) Enter RM
-; 4) Get 3 params
-; 5) Call oemCallout OR oem router
-; 6) Enter PM32
-; 7) Return to Agesa PH
-;
-; Entry:
-; [32-bit protected mode]
-; [esp+8] Func
-; [esp+12] Data
-; [esp+16] Configuration Block
-; [esp+4] return address to Agesa
-;
-; Exit:
-; [32-bit protected mode]
-;
-; Modified:
-; None
-;
-AMD_CALLOUT_16 MACRO LocalOemCalloutRouter
-;
-; Note that we are still PM32, so MASM may work strangely
-;
-
- push bp ; Save our original SP to access params
- mov bp, sp
- push bx
- push si
- push di
- push cx
- push dx
- push di
-
- DB 066h, 0EAh
- DW OFFSET PM16Entry
- DW AGESA_SELECTOR_CODE16
-
-PM16Entry:
-;
-; PM16 CS, but still PM32 SS, as we need to access our private params
-; before we enter RM.
-;
-; Note: we are working below the stack temporarily, and and it will
-; not affect our ability to get entry params
-;
- xor ecx, ecx
- xor edx, edx
-;
-; SGDT will give us the original location of the GDT on our CAS stack.
-; We need this value because our private parameters are located just
-; below the GDT.
-;
- mov edi, esp
- sub edi, GDT_Length + 6
- sgdt FWORD PTR [edi] ; [edi] = word size, dword address
- mov edi, DWORD PTR [edi+2] ; Get the PM32 address only
- sub edi, SIZEOF AMD_PRIVATE_PARAMS + 6
-;
-; cx = code segment of this code in RM
-; dx = stack segment of CAS in RM
-; fs = code segment of oem router (save for later)
-; gs = offset of oem router (save for later)
-; fs and gs are loaded after switch to real mode because we can't
-; use them as scratch pad registers in protected mode
-;
- mov cx, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_CS
- mov dx, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_SS
-
- mov eax, edi ; Save edi in eax for after RM switch
- mov edi, esp ; Save our current ESP for RM
-
- movzx ebx, dx
- shl ebx, 4
- sub esp, ebx
-
-;
-; We had been accessing the stack in PM32, we will now change to PM16 so we
-; will make the stack segment 64KB limit so SP needs to be fixed made PM16
-; compatible.
-;
- mov bx, AGESA_SELECTOR_DATA16
- mov ss, bx
-
-;
-; Save the RM segment and RM offset of the jump we will need to make in
-; order to enter RM so that code in this segment is relocatable.
-;
-; BEGIN --- Don't unbalance the stack --- BEGIN
-;
- push cx
- pushw OFFSET RMEntry
-
- mov ebx, CR0
- and bl, NOT 1
- mov CR0, ebx ; CR0.PE cleared
-;
-; Far jump to clear segment descriptor cache and enter RM
-;
- retf
-
-RMEntry:
-;
-; We are in RM, setup RM stack
-;
- movzx ebx, dx ; Get RM SS in ebx
- shl ebx, 4 ; Get our stack top on entry in EBP to
- sub ebp, ebx ; access our entry parameters
- sub eax, ebx ; save copy of parameters address
- mov ss, dx ; Set stack segment
-;
-; We are going to figure out the address to use when we return
-; and have to go back into PM32 while we have access to it
-;
- movzx ebx, cx ; Get original CS in ebx
- shl ebx, 4
- add ebx, OFFSET PM32Entry
-;
-; Now we put our data, func, block params into calling convention
-; for our hook
-;
-; ECX = Func
-; EDX = Data
-; ESI = config pointer
-;
- mov ecx, PARAM1 ; Func
- mov edx, PARAM2 ; Data
- mov esi, PARAM3 ; pointer
-
- push ebx ; Save PM32 mode switch address
- push edi ; Save PM32 stack pointer
- pushf
-;
-; Get Router Function Address
-;
- mov edi, eax
- mov ax, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Seg
- mov fs, ax
- mov ax, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Off
- mov gs, ax
-
- mov eax, AGESA_UNSUPPORTED ; Default return value
-;
-; If AMD_BRIDGE_32 EDX == 0 call oemCallout
-; otherwise call FAR PTR EDX
-;
-; Critical:
-; sp+2 - EDI aka PM32 stack address
-; sp+4 - address of PM32Entry in PM32
-;
- mov bx, fs
- shl ebx, 16
- mov bx, gs
-
- .if (ebx == 0)
- call LocalOemCalloutRouter
- .else
-;
-; Make far call to Router function
-;
- push cs
- push offset CalloutReturn
- push ebx
- retf
-CalloutReturn:
- .endif
-;
-; Restore PM32 esp from RM stack
-;
- popf
- pop edi ; Our PM32 stack pointer
- pop edx ; Our PM32 mode switch address
-
- mov ebx, CR0
- or bl, 1 ; CR0.PE set
- mov CR0, ebx
-
- mov ebx, AGESA_SELECTOR_DATA32
- pushd AGESA_SELECTOR_CODE32 ; PM32 selector
- push edx ; PM32 entry point
-
- DB 066h
- retf ; Far jump to enter PM32
-
-PM32Entry:
-;
-; END --- Don't unbalance the stack --- END
-; We are now PM32, so remember MASM is assembling in 16-bit again
-;
- mov ss, bx
- mov ds, bx
- mov es, bx
- mov fs, bx
- mov gs, bx
-
- mov sp, di
- pop di
- pop dx
- pop cx
- pop di
- pop si
- pop bx
- pop bp
- ; EXIT AMD_CALLOUT_16
-ENDM
diff --git a/src/vendorcode/amd/agesa/Lib/IA32/amdlib32.asm b/src/vendorcode/amd/agesa/Lib/IA32/amdlib32.asm
deleted file mode 100644
index ff0f85b..0000000
--- a/src/vendorcode/amd/agesa/Lib/IA32/amdlib32.asm
+++ /dev/null
@@ -1,151 +0,0 @@
-;/**
-; * @file
-; *
-; * Agesa library 32bit
-; *
-; * Contains AMD AGESA Library
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Lib
-; * @e \$Revision: 17071 $ @e \$Date: 2009-07-30 10:13:11 -0700 (Thu, 30 Jul 2009) $
-; */
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
-.586p
-.xmm
-.model flat,C
-ASSUME FS:NOTHING
-.code
-
-;---------------------------------------------------------------------------
-;
-; _mm_clflush_fs - execute clflush instruction for address fs:address32
-; this lets clflush operate beyond 4GB in 32-bit mode
-;
-; void _mm_clflush_fs (void *address32);
-;
-
-_mm_clflush_fs proc public
-
-
-
-
-
-
- mov eax, [esp+8]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- clflush fs:[eax]
-
-
-
- ret
-_mm_clflush_fs ENDP
-
-
-;---------------------------------------------------------------------------
-;
-; _mm_stream_si128_fs - execute movntdq instruction for address fs:address32
-; this lets movntdq operate beyond 4GB in 32-bit mode
-;
-; void _mm_stream_si128_fs (void *dest, void *data)
-;
-_mm_stream_si128_fs proc public
- push esi
- mov esi, [esp+12]
- movdqa xmm0, [esi]
- mov esi, [esp+8]
- movntdq fs:[esi], xmm0
-
-
-
-
-
-
-
- pop esi
- ret
-
-
-
-
-_mm_stream_si128_fs ENDP
-
-
-
-
-;---------------------------------------------------------------------------
-
-
-END
diff --git a/src/vendorcode/amd/agesa/Lib/IA32/ms_shift.asm b/src/vendorcode/amd/agesa/Lib/IA32/ms_shift.asm
deleted file mode 100644
index 3eb5113..0000000
--- a/src/vendorcode/amd/agesa/Lib/IA32/ms_shift.asm
+++ /dev/null
@@ -1,110 +0,0 @@
-;/**
-; * @file
-; *
-; * Agesa library 32bit
-; *
-; * Contains AMD AGESA Library
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Lib
-; * @e \$Revision: 9201 $ @e \$Date: 2008-10-31 03:36:20 -0500 (Fri, 31 Oct 2008) $
-; */
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
-.586p
-.model flat
-ASSUME FS:NOTHING
-.code
-;/*++
-;
-;Routine Description:
-;
-; Shifts a UINT64 to the right.
-;
-;Arguments:
-;
-; EDX:EAX - UINT64 value to be shifted
-; CL - Shift count
-;
-;Returns:
-;
-; EDX:EAX - shifted value
-;
-;--*/
-_aullshr PROC NEAR C PUBLIC
- .if (cl < 64)
- .if (cl >= 32)
- sub cl, 32
- mov eax, edx
- xor edx, edx
- .endif
- shrd eax, edx, cl
- shr edx, cl
- .else
- xor eax, eax
- xor edx, edx
- .endif
- ret
-_aullshr ENDP
-
-;/*++
-;
-;Routine Description:
-;
-; Shifts a UINT64 to the left.
-;
-;Arguments:
-;
-; EDX:EAX - UINT64 value to be shifted
-; CL - Shift count
-;
-;Returns:
-;
-; EDX:EAX - shifted value
-;
-;--*/
-_allshl PROC NEAR C PUBLIC USES CX
- .if (cl < 64)
- .if (cl >= 32)
- sub cl, 32
- mov edx, eax
- xor eax, eax
- .endif
- shld edx, eax, cl
- shl eax, cl
- .else
- xor eax, eax
- xor edx, edx
- .endif
- ret
-_allshl ENDP
-
-END
diff --git a/src/vendorcode/amd/agesa/Lib/IA32/msmemcpy.asm b/src/vendorcode/amd/agesa/Lib/IA32/msmemcpy.asm
deleted file mode 100644
index b74818c..0000000
--- a/src/vendorcode/amd/agesa/Lib/IA32/msmemcpy.asm
+++ /dev/null
@@ -1,84 +0,0 @@
-;/**
-; * @file
-; *
-; * Agesa library 32bit
-; *
-; * Contains AMD AGESA Library
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Lib
-; * @e \$Revision: 9201 $ @e \$Date: 2008-10-31 03:36:20 -0500 (Fri, 31 Oct 2008) $
-; */
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
-.586p
-.model flat
-ASSUME FS:NOTHING
-.code
-; void *memcpy( void *dest, void *src, size_t count );
-;
-; Copy count bytes from src to dest, returning dest.
-; ("c" is not legal as an assembly parameter name, replaced with value.)
-; Assume ES is set appropriately, 32 bit flat.
-;
-public memcpy
-memcpy PROC NEAR C PUBLIC USES ECX EDI ESI dest:DWORD, src:DWORD, count:DWORD
- pushf
- cld ; We will increment through *dest
- mov edi, dest
- mov esi, src
- mov ecx, count
- rep movsb
- mov eax, dest
- popf
- ret
-memcpy ENDP
-
-; void *memset( void *dest, int c, size_t count );
-;
-; At dest, set count bytes to byte value, returning dest.
-; ("c" is not legal as an assembly parameter name, replaced with value.)
-; Assume ES is set appropriately, 32 bit flat.
-;
-public memset
-memset PROC NEAR C PUBLIC USES ECX EDI dest:DWORD, value:DWORD, count:DWORD
- pushf
- cld ; We will increment through *dest
- mov edi, dest
- mov eax, value
- mov ecx, count
- rep stosb
- mov eax, edi
- popf
- ret
-memset ENDP
-
-END
diff --git a/src/vendorcode/amd/agesa/Lib/amdlib.c b/src/vendorcode/amd/agesa/Lib/amdlib.c
deleted file mode 100644
index c3364d3..0000000
--- a/src/vendorcode/amd/agesa/Lib/amdlib.c
+++ /dev/null
@@ -1,1340 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Library
- *
- * Contains interface to the AMD AGESA library
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Lib
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "amdlib.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE LIB_AMDLIB_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-BOOLEAN
-STATIC
-GetPciMmioAddress (
- OUT UINT64 *MmioAddress,
- OUT UINT32 *MmioSize,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-STATIC
-LibAmdGetDataFromPtr (
- IN ACCESS_WIDTH AccessWidth,
- IN VOID *Data,
- IN VOID *DataMask,
- OUT UINT32 *TemData,
- OUT UINT32 *TempDataMask
- );
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-UINT8
-ReadIo8 (
- IN UINT16 Address
- )
-{
- return __inbyte (Address);
-}
-UINT16
-ReadIo16 (
- IN UINT16 Address
- )
-{
- return __inword (Address);
-}
-UINT32
-ReadIo32 (
- IN UINT16 Address
- )
-{
- return __indword (Address);
-}
-VOID
-WriteIo8 (
- IN UINT16 Address,
- IN UINT8 Data
- )
-{
- __outbyte (Address, Data);
-}
-VOID
-WriteIo16 (
- IN UINT16 Address,
- IN UINT16 Data
- )
-{
- __outword (Address, Data);
-}
-VOID
-WriteIo32 (
- IN UINT16 Address,
- IN UINT32 Data
- )
-{
- __outdword (Address, Data);
-}
-STATIC
-UINT64 SetFsBase (
- UINT64 address
- )
-{
- UINT64 hwcr;
- hwcr = __readmsr (0xC0010015);
- __writemsr (0xC0010015, hwcr | 1 << 17);
- __writemsr (0xC0000100, address);
- return hwcr;
-}
-STATIC
-VOID
-RestoreHwcr (
- UINT64
- value
- )
-{
- __writemsr (0xC0010015, value);
-}
-UINT8
-Read64Mem8 (
- IN UINT64 Address
- )
-{
- UINT8 dataRead;
- UINT64 hwcrSave;
- if ((Address >> 32) == 0) {
- return *(volatile UINT8 *) (UINTN) Address;
- }
- hwcrSave = SetFsBase (Address);
- dataRead = __readfsbyte (0);
- RestoreHwcr (hwcrSave);
- return dataRead;
-}
-UINT16
-Read64Mem16 (
- IN UINT64 Address
- )
-{
- UINT16 dataRead;
- UINT64 hwcrSave;
- if ((Address >> 32) == 0) {
- return *(volatile UINT16 *) (UINTN) Address;
- }
- hwcrSave = SetFsBase (Address);
- dataRead = __readfsword (0);
- RestoreHwcr (hwcrSave);
- return dataRead;
-}
-UINT32
-Read64Mem32 (
- IN UINT64 Address
- )
-{
- UINT32 dataRead;
- UINT64 hwcrSave;
- if ((Address >> 32) == 0) {
- return *(volatile UINT32 *) (UINTN) Address;
- }
- hwcrSave = SetFsBase (Address);
- dataRead = __readfsdword (0);
- RestoreHwcr (hwcrSave);
- return dataRead;
- }
-VOID
-Write64Mem8 (
- IN UINT64 Address,
- IN UINT8 Data
- )
-{
- if ((Address >> 32) == 0){
- *(volatile UINT8 *) (UINTN) Address = Data;
- }
- else {
- UINT64 hwcrSave;
- hwcrSave = SetFsBase (Address);
- __writefsbyte (0, Data);
- RestoreHwcr (hwcrSave);
- }
-}
-VOID
-Write64Mem16 (
- IN UINT64 Address,
- IN UINT16 Data
- )
-{
- if ((Address >> 32) == 0){
- *(volatile UINT16 *) (UINTN) Address = Data;
- }
- else {
- UINT64 hwcrSave;
- hwcrSave = SetFsBase (Address);
- __writefsword (0, Data);
- RestoreHwcr (hwcrSave);
- }
-}
-VOID
-Write64Mem32 (
- IN UINT64 Address,
- IN UINT32 Data
- )
-{
- if ((Address >> 32) == 0){
- *(volatile UINT32 *) (UINTN) Address = Data;
- }
- else {
- UINT64 hwcrSave;
- hwcrSave = SetFsBase (Address);
- __writefsdword (0, Data);
- RestoreHwcr (hwcrSave);
- }
-}
-VOID
-LibAmdReadCpuReg (
- IN UINT8 RegNum,
- OUT UINT32 *Value
- )
-{
- *Value = 0;
- switch (RegNum){
- case CR4_REG:
- *Value = __readcr4 ();
- break;
- case DR0_REG:
- *Value = __readdr (0);
- break;
- case DR1_REG:
- *Value = __readdr (1);
- break;
- case DR2_REG:
- *Value = __readdr (2);
- break;
- case DR3_REG:
- *Value = __readdr (3);
- break;
- case DR7_REG:
- *Value = __readdr (7);
- break;
- default:
- *Value = -1;
- }
-}
-VOID
-LibAmdWriteCpuReg (
- IN UINT8 RegNum,
- IN UINT32 Value
- )
-{
- switch (RegNum){
- case CR4_REG:
- __writecr4 (Value);
- break;
- case DR0_REG:
- __writedr (0, Value);
- break;
- case DR1_REG:
- __writedr (1, Value);
- break;
- case DR2_REG:
- __writedr (2, Value);
- break;
- case DR3_REG:
- __writedr (3, Value);
- break;
- case DR7_REG:
- __writedr (7, Value);
- break;
- default:
- ;
- }
-}
-VOID
-LibAmdWriteBackInvalidateCache (
- IN VOID
- )
-{
- __wbinvd ();
-}
-VOID
-LibAmdHDTBreakPoint (
- VOID
- )
-{
- __writemsr (0xC001100A, __readmsr (0xC001100A) | 1);
- __debugbreak (); // do you really need icebp? If so, go back to asm code
-}
-UINT8
-LibAmdBitScanForward (
- IN UINT32 value
- )
-{
- UINTN Index;
- for (Index = 0; Index < 32; Index++){
- if (value & (1 << Index)) break;
- }
- return (UINT8) Index;
-}
-UINT8
-LibAmdBitScanReverse (
- IN UINT32 value
-)
-{
- UINTN Index;
- for (Index = 31; Index >= 0; Index--){
- if (value & (1 << Index)) break;
- }
- return (UINT8) Index;
-}
-VOID
-LibAmdMsrRead (
- IN UINT32 MsrAddress,
- OUT UINT64 *Value,
- IN OUT AMD_CONFIG_PARAMS *ConfigPtr
- )
-{
- *Value = __readmsr (MsrAddress);
-}
-VOID
-LibAmdMsrWrite (
- IN UINT32 MsrAddress,
- IN UINT64 *Value,
- IN OUT AMD_CONFIG_PARAMS *ConfigPtr
- )
-{
- __writemsr (MsrAddress, *Value);
-}
-void LibAmdCpuidRead (
- IN UINT32 CpuidFcnAddress,
- OUT CPUID_DATA* Value,
- IN OUT AMD_CONFIG_PARAMS *ConfigPtr
- )
-{
- __cpuid ((int *)Value, CpuidFcnAddress);
-}
-UINT64
-ReadTSC (
- VOID
- )
-{
- return __rdtsc ();
-}
-VOID
-LibAmdSimNowEnterDebugger (
- VOID
- )
-{
- STATIC CONST UINT8 opcode [] = {0x60, // pushad
- 0xBB, 0x02, 0x00, 0x00, 0x00, // mov ebx, 2
- 0xB8, 0x0B, 0xD0, 0xCC, 0xBA, // mov eax, 0xBACCD00B
- 0x0F, 0xA2, // cpuid
- 0x61, // popad
- 0xC3 // ret
- };
- ((VOID (*)(VOID)) (size_t) opcode) (); // call the function
-}
-
-#ifdef __SSE3__
-VOID F10RevDProbeFilterCritical (
- IN PCI_ADDR PciAddress,
- IN UINT32 PciRegister
- )
-{
- UINT64 msrsave;
- msrsave = __readmsr (0xC001001F);
- __writemsr (0xC001001F, msrsave | 1ULL << 46); // EnableCf8ExtCfg
- _mm_mfence ();
- __outdword (0xCF8, PciAddress.AddressValue);
- _mm_mfence ();
- __outdword (0xCFC, PciRegister | 2);
- _mm_mfence ();
- __writemsr (0xC001001F, msrsave);
-}
-
-VOID
-LibAmdCLFlush (
- IN UINT64 Address,
- IN UINT8 Count
- )
-{
- UINT64 hwcrSave;
- UINT8 *address32;
- UINTN Index;
- address32 = 0;
- hwcrSave = SetFsBase (Address);
- for (Index = 0; Index < Count; Index++){
- _mm_mfence ();
- _mm_clflush_fs (&address32 [Index * 64]);
- }
- RestoreHwcr (hwcrSave);
-}
-#endif //__SSE3__
-
-VOID
-IdsOutPort (
- IN UINT32 Addr,
- IN UINT32 Value,
- IN UINT32 Flag
- )
-{
- __outdword ((UINT16) Addr, Value);
-}
-VOID
-StopHere (
- VOID
- )
-{
- VOLATILE UINTN x = 1;
- while (x);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Read IO port
- *
- *
- * @param[in] AccessWidth Access width
- * @param[in] IoAddress IO port address
- * @param[in] Value Pointer to save data
- * @param[in] StdHeader Standard configuration header
- *
- */
-VOID
-LibAmdIoRead (
- IN ACCESS_WIDTH AccessWidth,
- IN UINT16 IoAddress,
- OUT VOID *Value,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- switch (AccessWidth) {
- case AccessWidth8:
- case AccessS3SaveWidth8:
- *(UINT8 *) Value = ReadIo8 (IoAddress);
- break;
- case AccessWidth16:
- case AccessS3SaveWidth16:
- *(UINT16 *) Value = ReadIo16 (IoAddress);
- break;
- case AccessWidth32:
- case AccessS3SaveWidth32:
- *(UINT32 *) Value = ReadIo32 (IoAddress);
- break;
- default:
- ASSERT (FALSE);
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Write IO port
- *
- *
- * @param[in] AccessWidth Access width
- * @param[in] IoAddress IO port address
- * @param[in] Value Pointer to data
- * @param[in] StdHeader Standard configuration header
- *
- */
-VOID
-LibAmdIoWrite (
- IN ACCESS_WIDTH AccessWidth,
- IN UINT16 IoAddress,
- IN VOID *Value,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- switch (AccessWidth) {
- case AccessWidth8:
- case AccessS3SaveWidth8:
- WriteIo8 (IoAddress, *(UINT8 *) Value);
- break;
- case AccessWidth16:
- case AccessS3SaveWidth16:
- WriteIo16 (IoAddress, *(UINT16 *) Value);
- break;
- case AccessWidth32:
- case AccessS3SaveWidth32:
- WriteIo32 (IoAddress, *(UINT32 *) Value);
- break;
- default:
- ASSERT (FALSE);
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * IO read modify write
- *
- *
- * @param[in] AccessWidth Access width
- * @param[in] IoAddress IO address
- * @param[in] Data OR data
- * @param[in] DataMask Mask to be used before data write back to register.
- * @param[in] StdHeader Standard configuration header
- *
- */
-VOID
-LibAmdIoRMW (
- IN ACCESS_WIDTH AccessWidth,
- IN UINT16 IoAddress,
- IN VOID *Data,
- IN VOID *DataMask,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 TempData;
- UINT32 TempMask;
- UINT32 Value;
- LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask);
- LibAmdIoRead (AccessWidth, IoAddress, &Value, StdHeader);
- Value = (Value & (~TempMask)) | TempData;
- LibAmdIoWrite (AccessWidth, IoAddress, &Value, StdHeader);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Poll IO register
- *
- * Poll register until (RegisterValue & DataMask) == Data
- *
- * @param[in] AccessWidth Access width
- * @param[in] IoAddress IO address
- * @param[in] Data Data to compare
- * @param[in] DataMask And mask
- * @param[in] Delay Poll for time in 100ns (not supported)
- * @param[in] StdHeader Standard configuration header
- *
- */
-VOID
-LibAmdIoPoll (
- IN ACCESS_WIDTH AccessWidth,
- IN UINT16 IoAddress,
- IN VOID *Data,
- IN VOID *DataMask,
- IN UINT64 Delay,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 TempData;
- UINT32 TempMask;
- UINT32 Value;
- LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask);
- do {
- LibAmdIoRead (AccessWidth, IoAddress, &Value, StdHeader);
- } while (TempData != (Value & TempMask));
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Read memory/MMIO
- *
- *
- * @param[in] AccessWidth Access width
- * @param[in] MemAddress Memory address
- * @param[in] Value Pointer to data
- * @param[in] StdHeader Standard configuration header
- *
- */
-VOID
-LibAmdMemRead (
- IN ACCESS_WIDTH AccessWidth,
- IN UINT64 MemAddress,
- OUT VOID *Value,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- switch (AccessWidth) {
- case AccessWidth8:
- case AccessS3SaveWidth8:
- *(UINT8 *) Value = Read64Mem8 (MemAddress);
- break;
- case AccessWidth16:
- case AccessS3SaveWidth16:
- *(UINT16 *) Value = Read64Mem16 (MemAddress);
- break;
- case AccessWidth32:
- case AccessS3SaveWidth32:
- *(UINT32 *) Value = Read64Mem32 (MemAddress);
- break;
- default:
- ASSERT (FALSE);
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Write memory/MMIO
- *
- *
- * @param[in] AccessWidth Access width
- * @param[in] MemAddress Memory address
- * @param[in] Value Pointer to data
- * @param[in] StdHeader Standard configuration header
- *
- */
-VOID
-LibAmdMemWrite (
- IN ACCESS_WIDTH AccessWidth,
- IN UINT64 MemAddress,
- IN VOID *Value,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
-
- switch (AccessWidth) {
- case AccessWidth8:
- case AccessS3SaveWidth8:
- Write64Mem8 (MemAddress, *((UINT8 *) Value));
- break;
- case AccessWidth16:
- case AccessS3SaveWidth16:
- Write64Mem16 (MemAddress, *((UINT16 *) Value));
- break;
- case AccessWidth32:
- case AccessS3SaveWidth32:
- Write64Mem32 (MemAddress, *((UINT32 *) Value));
- break;
- default:
- ASSERT (FALSE);
- }
-}
-/*---------------------------------------------------------------------------------------*/
-/**
- * Memory/MMIO read modify write
- *
- *
- * @param[in] AccessWidth Access width
- * @param[in] MemAddress Memory address
- * @param[in] Data OR data
- * @param[in] DataMask Mask to be used before data write back to register.
- * @param[in] StdHeader Standard configuration header
- *
- */
-VOID
-LibAmdMemRMW (
- IN ACCESS_WIDTH AccessWidth,
- IN UINT64 MemAddress,
- IN VOID *Data,
- IN VOID *DataMask,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 TempData;
- UINT32 TempMask;
- UINT32 Value;
- LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask);
- LibAmdMemRead (AccessWidth, MemAddress, &Value, StdHeader);
- Value = (Value & (~TempMask)) | TempData;
- LibAmdMemWrite (AccessWidth, MemAddress, &Value, StdHeader);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Poll Mmio
- *
- * Poll register until (RegisterValue & DataMask) == Data
- *
- * @param[in] AccessWidth Access width
- * @param[in] MemAddress Memory address
- * @param[in] Data Data to compare
- * @param[in] DataMask AND mask
- * @param[in] Delay Poll for time in 100ns (not supported)
- * @param[in] StdHeader Standard configuration header
- *
- */
-VOID
-LibAmdMemPoll (
- IN ACCESS_WIDTH AccessWidth,
- IN UINT64 MemAddress,
- IN VOID *Data,
- IN VOID *DataMask,
- IN UINT64 Delay,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 TempData;
- UINT32 TempMask;
- UINT32 Value;
- LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask);
- do {
- LibAmdMemRead (AccessWidth, MemAddress, &Value, StdHeader);
- } while (TempData != (Value & TempMask));
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Read PCI config space
- *
- *
- * @param[in] AccessWidth Access width
- * @param[in] PciAddress Pci address
- * @param[in] Value Pointer to data
- * @param[in] StdHeader Standard configuration header
- *
- */
-VOID
-LibAmdPciRead (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR PciAddress,
- OUT VOID *Value,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 LegacyPciAccess;
- UINT32 MMIOSize;
- UINT64 RMWrite;
- UINT64 RMWritePrevious;
- UINT64 MMIOAddress;
-
- ASSERT (StdHeader != NULL);
- ASSERT (PciAddress.AddressValue != ILLEGAL_SBDFO);
- if (!GetPciMmioAddress (&MMIOAddress, &MMIOSize, StdHeader)) {
- // We need to convert our "portable" PCI address into a "real" PCI access
- LegacyPciAccess = ((1 << 31) + (PciAddress.Address.Register & 0xFC) + (PciAddress.Address.Function << 8) + (PciAddress.Address.Device << 11) + (PciAddress.Address.Bus << 16) + ((PciAddress.Address.Register & 0xF00) << (24 - 8)));
- if (PciAddress.Address.Register <= 0xFF) {
- LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader);
- LibAmdIoRead (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, StdHeader);
- } else {
- LibAmdMsrRead (NB_CFG, &RMWritePrevious, StdHeader);
- RMWrite = RMWritePrevious | 0x0000400000000000ull;
- LibAmdMsrWrite (NB_CFG, &RMWrite, StdHeader);
- LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader);
- LibAmdIoRead (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, StdHeader);
- LibAmdMsrWrite (NB_CFG, &RMWritePrevious, StdHeader);
- }
- } else {
- // Setup the MMIO address
- ASSERT ((MMIOAddress + MMIOSize) > (MMIOAddress + (PciAddress.AddressValue & 0x0FFFFFFF)));
- MMIOAddress += (PciAddress.AddressValue & 0x0FFFFFFF);
- LibAmdMemRead (AccessWidth, MMIOAddress, Value, StdHeader);
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Write PCI config space
- *
- *
- * @param[in] AccessWidth Access width
- * @param[in] PciAddress Pci address
- * @param[in] Value Pointer to data
- * @param[in] StdHeader Standard configuration header
- *
- */
-VOID
-LibAmdPciWrite (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR PciAddress,
- IN VOID *Value,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 LegacyPciAccess;
- UINT32 MMIOSize;
- UINT64 RMWrite;
- UINT64 RMWritePrevious;
- UINT64 MMIOAddress;
-
- ASSERT (StdHeader != NULL);
- ASSERT (PciAddress.AddressValue != ILLEGAL_SBDFO);
- if (!GetPciMmioAddress (&MMIOAddress, &MMIOSize, StdHeader)) {
- // We need to convert our "portable" PCI address into a "real" PCI access
- LegacyPciAccess = ((1 << 31) + (PciAddress.Address.Register & 0xFC) + (PciAddress.Address.Function << 8) + (PciAddress.Address.Device << 11) + (PciAddress.Address.Bus << 16) + ((PciAddress.Address.Register & 0xF00) << (24 - 8)));
- if (PciAddress.Address.Register <= 0xFF) {
- LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader);
- LibAmdIoWrite (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, StdHeader);
- } else {
- LibAmdMsrRead (NB_CFG, &RMWritePrevious, StdHeader);
- RMWrite = RMWritePrevious | 0x0000400000000000ull;
- LibAmdMsrWrite (NB_CFG, &RMWrite, StdHeader);
- LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader);
- LibAmdIoWrite (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, StdHeader);
- LibAmdMsrWrite (NB_CFG, &RMWritePrevious, StdHeader);
- }
- } else {
- // Setup the MMIO address
- ASSERT ((MMIOAddress + MMIOSize) > (MMIOAddress + (PciAddress.AddressValue & 0x0FFFFFFF)));
- MMIOAddress += (PciAddress.AddressValue & 0x0FFFFFFF);
- LibAmdMemWrite (AccessWidth, MMIOAddress, Value, StdHeader);
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * PCI read modify write
- *
- *
- * @param[in] AccessWidth Access width
- * @param[in] PciAddress Pci address
- * @param[in] Data OR Data
- * @param[in] DataMask Mask to be used before data write back to register.
- * @param[in] StdHeader Standard configuration header
- *
- */
-VOID
-LibAmdPciRMW (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR PciAddress,
- IN VOID *Data,
- IN VOID *DataMask,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 TempData;
- UINT32 TempMask;
- UINT32 Value;
- LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask);
- LibAmdPciRead (AccessWidth, PciAddress, &Value, StdHeader);
- Value = (Value & (~TempMask)) | TempData;
- LibAmdPciWrite (AccessWidth, PciAddress, &Value, StdHeader);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Poll PCI config space register
- *
- * Poll register until (RegisterValue & DataMask) == Data
- *
- * @param[in] AccessWidth Access width
- * @param[in] PciAddress Pci address
- * @param[in] Data Data to compare
- * @param[in] DataMask AND mask
- * @param[in] Delay Poll for time in 100ns (not supported)
- * @param[in] StdHeader Standard configuration header
- *
- */
-VOID
-LibAmdPciPoll (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR PciAddress,
- IN VOID *Data,
- IN VOID *DataMask,
- IN UINT64 Delay,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 TempData;
- UINT32 TempMask;
- UINT32 Value;
- LibAmdGetDataFromPtr (AccessWidth, Data, DataMask, &TempData, &TempMask);
- do {
- LibAmdPciRead (AccessWidth, PciAddress, &Value, StdHeader);
- } while (TempData != (Value & TempMask));
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Get MMIO base address for PCI accesses
- *
- * @param[out] MmioAddress PCI MMIO base address
- * @param[out] MmioSize Size of region in bytes
- * @param[in] StdHeader Standard configuration header
- *
- * @retval TRUE MmioAddress/MmioSize are valid
- */
-BOOLEAN
-STATIC
-GetPciMmioAddress (
- OUT UINT64 *MmioAddress,
- OUT UINT32 *MmioSize,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- BOOLEAN MmioIsEnabled;
- UINT32 EncodedSize;
- UINT64 MsrReg;
-
- ASSERT (StdHeader != NULL);
-
- MmioIsEnabled = FALSE;
- LibAmdMsrRead (MSR_MMIO_Cfg_Base, &MsrReg, StdHeader);
- if ((MsrReg & BIT0) != 0) {
- *MmioAddress = MsrReg & 0xFFFFFFFFFFF00000ull;
- EncodedSize = (UINT32) ((MsrReg & 0x3C) >> 2);
- *MmioSize = ((1 << EncodedSize) * 0x100000);
- MmioIsEnabled = TRUE;
- }
- return MmioIsEnabled;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Read field of PCI config register.
- *
- *
- *
- * @param[in] Address Pci address (register must be DWORD aligned)
- * @param[in] Highbit High bit position of the field in DWORD
- * @param[in] Lowbit Low bit position of the field in DWORD
- * @param[out] Value Pointer to data
- * @param[in] StdHeader Standard configuration header
- */
-VOID
-LibAmdPciReadBits (
- IN PCI_ADDR Address,
- IN UINT8 Highbit,
- IN UINT8 Lowbit,
- OUT UINT32 *Value,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- ASSERT (Highbit < 32 && Lowbit < 32 && Highbit >= Lowbit && (Address.AddressValue & 3) == 0);
-
- LibAmdPciRead (AccessWidth32, Address, Value, StdHeader);
- *Value >>= Lowbit; // Shift
-
- // A 1 << 32 == 1 << 0 due to x86 SHL instruction, so skip if that is the case
-
- if ((Highbit - Lowbit) != 31) {
- *Value &= (((UINT32) 1 << (Highbit - Lowbit + 1)) - 1);
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Write field of PCI config register.
- *
- *
- *
- * @param[in] Address Pci address (register must be DWORD aligned)
- * @param[in] Highbit High bit position of the field in DWORD
- * @param[in] Lowbit Low bit position of the field in DWORD
- * @param[in] Value Pointer to data
- * @param[in] StdHeader Standard configuration header
- */
-VOID
-LibAmdPciWriteBits (
- IN PCI_ADDR Address,
- IN UINT8 Highbit,
- IN UINT8 Lowbit,
- IN UINT32 *Value,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Temp;
- UINT32 Mask;
-
- ASSERT (Highbit < 32 && Lowbit < 32 && Highbit >= Lowbit && (Address.AddressValue & 3) == 0);
-
- // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
-
- if ((Highbit - Lowbit) != 31) {
- Mask = (((UINT32) 1 << (Highbit - Lowbit + 1)) - 1);
- } else {
- Mask = (UINT32) 0xFFFFFFFF;
- }
-
- LibAmdPciRead (AccessWidth32, Address, &Temp, StdHeader);
- Temp &= ~(Mask << Lowbit);
- Temp |= (*Value & Mask) << Lowbit;
- LibAmdPciWrite (AccessWidth32, Address, &Temp, StdHeader);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Locate next capability pointer
- *
- * Given a SBDFO this routine will find the next PCI capabilities list entry.
- * if the end of the list is reached, or if a problem is detected, then ILLEGAL_SBDFO is
- * returned.
- * To start a new search from the head of the list, specify a SBDFO with an offset of zero.
- *
- * @param[in,out] Address Pci address
- * @param[in] StdHeader Standard configuration header
- */
-
-VOID
-LibAmdPciFindNextCap (
- IN OUT PCI_ADDR *Address,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- PCI_ADDR Base;
- UINT32 Offset;
- UINT32 Temp;
- PCI_ADDR TempAddress;
-
- ASSERT (Address != NULL);
- ASSERT (*(UINT32 *) Address != ILLEGAL_SBDFO);
-
- Base.AddressValue = Address->AddressValue;
- Offset = Base.Address.Register;
- Base.Address.Register = 0;
-
- Address->AddressValue = (UINT32) ILLEGAL_SBDFO;
-
- // Verify that the SBDFO points to a valid PCI device SANITY CHECK
- LibAmdPciRead (AccessWidth32, Base, &Temp, StdHeader);
- if (Temp == 0xFFFFFFFF) {
- ASSERT (FALSE);
- return; // There is no device at this address
- }
-
- // Verify that the device supports a capability list
- TempAddress.AddressValue = Base.AddressValue + 0x04;
- LibAmdPciReadBits (TempAddress, 20, 20, &Temp, StdHeader);
- if (Temp == 0) {
- return; // This PCI device does not support capability lists
- }
-
- if (Offset != 0) {
- // If we are continuing on an existing list
- TempAddress.AddressValue = Base.AddressValue + Offset;
- LibAmdPciReadBits (TempAddress, 15, 8, &Temp, StdHeader);
- } else {
- // We are starting on a new list
- TempAddress.AddressValue = Base.AddressValue + 0x34;
- LibAmdPciReadBits (TempAddress, 7, 0, &Temp, StdHeader);
- }
-
- if (Temp == 0) {
- return; // We have reached the end of the capabilities list
- }
-
- // Error detection and recovery- The statement below protects against
- // PCI devices with broken PCI capabilities lists. Detect a pointer
- // that is not uint32 aligned, points into the first 64 reserved DWORDs
- // or points back to itself.
- if (((Temp & 3) != 0) || (Temp == Offset) || (Temp < 0x40)) {
- ASSERT (FALSE);
- return;
- }
-
- Address->AddressValue = Base.AddressValue + Temp;
- return;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Set memory with value
- *
- *
- * @param[in,out] Destination Pointer to memory range
- * @param[in] Value Value to set memory with
- * @param[in] FillLength Size of the memory range
- * @param[in] StdHeader Standard configuration header (Optional)
- */
-VOID
-LibAmdMemFill (
- IN VOID *Destination,
- IN UINT8 Value,
- IN UINTN FillLength,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 *Dest;
- ASSERT (StdHeader != NULL);
- Dest = Destination;
- while ((FillLength--) != 0) {
- *Dest++ = Value;
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Copy memory
- *
- *
- * @param[in,out] Destination Pointer to destination buffer
- * @param[in] Source Pointer to source buffer
- * @param[in] CopyLength buffer length
- * @param[in] StdHeader Standard configuration header (Optional)
- */
-VOID
-LibAmdMemCopy (
- IN VOID *Destination,
- IN VOID *Source,
- IN UINTN CopyLength,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 *Dest;
- UINT8 *SourcePtr;
- ASSERT (StdHeader != NULL);
- Dest = Destination;
- SourcePtr = Source;
- while ((CopyLength--) != 0) {
- *Dest++ = *SourcePtr++;
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Verify checksum of binary image (B1/B2/B3)
- *
- *
- * @param[in] ImagePtr Pointer to image start
- * @retval TRUE Checksum valid
- * @retval FALSE Checksum invalid
- */
-BOOLEAN
-LibAmdVerifyImageChecksum (
- IN VOID *ImagePtr
- )
-{
- // Assume ImagePtr points to the binary start ($AMD)
- // Checksum is on an even boundary in AMD_IMAGE_HEADER
-
- UINT16 Sum;
- UINT32 i;
-
- Sum = 0;
-
- i = ((AMD_IMAGE_HEADER*) ImagePtr)->ImageSize;
-
- while (i > 1) {
- Sum = Sum + *((UINT16 *)ImagePtr);
- ImagePtr = (VOID *) ((UINT8 *)ImagePtr + 2);
- i = i - 2;
- }
- if (i > 0) {
- Sum = Sum + *((UINT8 *) ImagePtr);
- }
-
- return (Sum == 0)?TRUE:FALSE;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Locate AMD binary image that contain specific module
- *
- *
- * @param[in] StartAddress Pointer to start range
- * @param[in] EndAddress Pointer to end range
- * @param[in] Alignment Image address alignment
- * @param[in] ModuleSignature Module signature.
- * @retval NULL if image not found
- * @retval pointer to image header
- */
-VOID *
-LibAmdLocateImage (
- IN VOID *StartAddress,
- IN VOID *EndAddress,
- IN UINT32 Alignment,
- IN CHAR8 ModuleSignature[8]
- )
-
-{
- UINT8 *CurrentPtr;
- AMD_MODULE_HEADER *ModuleHeaderPtr;
- UINT64 *SearchStr;
- UINT64 *InputStr;
-
- CurrentPtr = StartAddress;
- InputStr = (UINT64 *)ModuleSignature;
-
- // Search from start to end incrementing by alignment
- while ((CurrentPtr >= (UINT8 *) StartAddress) && (CurrentPtr < (UINT8 *) EndAddress)) {
- // First find a binary image
- if (*((UINT32 *) CurrentPtr) == IMAGE_SIGNATURE) {
- if (LibAmdVerifyImageChecksum (CurrentPtr)) {
- // If we have a valid image, search module linked list for a match
- ModuleHeaderPtr = (AMD_MODULE_HEADER*) ((UINT8 *)CurrentPtr + ((AMD_IMAGE_HEADER *) CurrentPtr)->ModuleInfoOffset);
- while (ModuleHeaderPtr != NULL) {
- SearchStr = (UINT64 *)&ModuleHeaderPtr->ModuleIdentifier;
- if (*InputStr == *SearchStr) {
- return CurrentPtr;
- }
- ModuleHeaderPtr = (AMD_MODULE_HEADER *)ModuleHeaderPtr->NextBlock;
- }
- }
- }
- CurrentPtr += Alignment;
- }
- return NULL;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns the package type mask for the processor
- *
- *
- * @param[in] StdHeader Standard configuration header (Optional)
- */
-
-// Returns the package type mask for the processor
-UINT32
-LibAmdGetPackageType (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 ProcessorPackageType;
- CPUID_DATA CpuId;
-
- LibAmdCpuidRead (0x80000001, &CpuId, StdHeader);
- ProcessorPackageType = (UINT32) (CpuId.EBX_Reg >> 28) & 0xF; // bit 31:28
- return (UINT32) (1 << ProcessorPackageType);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns the package type mask for the processor
- *
- *
- * @param[in] AccessWidth Access width
- * @param[in] Data data
- * @param[in] DataMask data
- * @param[out] TemData typecast data
- * @param[out] TempDataMask typecast data
- */
-
-
-VOID
-STATIC
-LibAmdGetDataFromPtr (
- IN ACCESS_WIDTH AccessWidth,
- IN VOID *Data,
- IN VOID *DataMask,
- OUT UINT32 *TemData,
- OUT UINT32 *TempDataMask
- )
-{
- switch (AccessWidth) {
- case AccessWidth8:
- case AccessS3SaveWidth8:
- *TemData = (UINT32)*(UINT8 *) Data;
- *TempDataMask = (UINT32)*(UINT8 *) DataMask;
- break;
- case AccessWidth16:
- case AccessS3SaveWidth16:
- *TemData = (UINT32)*(UINT16 *) Data;
- *TempDataMask = (UINT32)*(UINT16 *) DataMask;
- break;
- case AccessWidth32:
- case AccessS3SaveWidth32:
- *TemData = *(UINT32 *) Data;
- *TempDataMask = *(UINT32 *) DataMask;
- break;
- default:
- IDS_ERROR_TRAP;
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns the package type mask for the processor
- *
- *
- * @param[in] AccessWidth Access width
- * @retval Width in number of bytes
- */
-
-
-UINT8
-LibAmdAccessWidth (
- IN ACCESS_WIDTH AccessWidth
- )
-{
- UINT8 Width;
-
- switch (AccessWidth) {
- case AccessWidth8:
- case AccessS3SaveWidth8:
- Width = 1;
- break;
- case AccessWidth16:
- case AccessS3SaveWidth16:
- Width = 2;
- break;
- case AccessWidth32:
- case AccessS3SaveWidth32:
- Width = 4;
- break;
- case AccessWidth64:
- case AccessS3SaveWidth64:
- Width = 8;
- break;
- default:
- Width = 0;
- IDS_ERROR_TRAP;
- }
- return Width;
-}
-
-VOID
-CpuidRead (
- IN UINT32 CpuidFcnAddress,
- OUT CPUID_DATA *Value
- )
-{
- __cpuid ((int *)Value, CpuidFcnAddress);
-}
-
-UINT8
-ReadNumberOfCpuCores(
- VOID
- )
-{
- CPUID_DATA Value;
- CpuidRead (0x80000008, &Value);
- return Value.ECX_Reg & 0xff;
-}
diff --git a/src/vendorcode/amd/agesa/Lib/amdlib.h b/src/vendorcode/amd/agesa/Lib/amdlib.h
deleted file mode 100644
index 83edc68..0000000
--- a/src/vendorcode/amd/agesa/Lib/amdlib.h
+++ /dev/null
@@ -1,421 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Library
- *
- * Contains interface to the AMD AGESA library
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Lib
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _AMD_LIB_H_
-#define _AMD_LIB_H_
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-#define IOCF8 0xCF8
-#define IOCFC 0xCFC
-
-// Reg Values for ReadCpuReg and WriteCpuReg
-#define CR0_REG 0x00
-#define CR4_REG 0x04
-#define DR0_REG 0x10
-#define DR1_REG 0x11
-#define DR2_REG 0x12
-#define DR3_REG 0x13
-#define DR7_REG 0x17
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-#if !defined __GNUC__
-// PROTOTYPES FOR amdlib32.asm
-void _mm_stream_si128_fs (void *__A, void *__B);
-void _mm_store_si128_fs (void *dest, void *data);
-void _mm_clflush_fs (void *address32);
-#endif
-/*---------------------------------------------------------------------------------------
- * L O C A L F U N C T I O N S
- *---------------------------------------------------------------------------------------
- */
-UINT8
-ReadIo8 (
- IN UINT16 Address
- );
-
-UINT16
-ReadIo16 (
- IN UINT16 Address
- );
-
-UINT32
-ReadIo32 (
- IN UINT16 Address
- );
-
-VOID
-WriteIo8 (
- IN UINT16 Address,
- IN UINT8 Data
- );
-
-VOID
-WriteIo16 (
- IN UINT16 Address,
- IN UINT16 Data
- );
-
-VOID
-WriteIo32 (
- IN UINT16 Address,
- IN UINT32 Data
- );
-
-UINT8
-Read64Mem8 (
- IN UINT64 Address
- );
-
-UINT16
-Read64Mem16 (
- IN UINT64 Address
- );
-
-UINT32
-Read64Mem32 (
- IN UINT64 Address
- );
-
-VOID
-Write64Mem8 (
- IN UINT64 Address,
- IN UINT8 Data
- );
-
-VOID
-Write64Mem16 (
- IN UINT64 Address,
- IN UINT16 Data
- );
-
-VOID
-Write64Mem32 (
- IN UINT64 Address,
- IN UINT32 Data
- );
-
-UINT64
-ReadTSC (
- VOID
- );
-
-// MSR
-VOID
-LibAmdMsrRead (
- IN UINT32 MsrAddress,
- OUT UINT64 *Value,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-LibAmdMsrWrite (
- IN UINT32 MsrAddress,
- IN UINT64 *Value,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-// IO
-VOID
-LibAmdIoRead (
- IN ACCESS_WIDTH AccessWidth,
- IN UINT16 IoAddress,
- OUT VOID *Value,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-LibAmdIoWrite (
- IN ACCESS_WIDTH AccessWidth,
- IN UINT16 IoAddress,
- IN VOID *Value,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-LibAmdIoRMW (
- IN ACCESS_WIDTH AccessWidth,
- IN UINT16 IoAddress,
- IN VOID *Data,
- IN VOID *DataMask,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-LibAmdIoPoll (
- IN ACCESS_WIDTH AccessWidth,
- IN UINT16 IoAddress,
- IN VOID *Data,
- IN VOID *DataMask,
- IN UINT64 Delay,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-// Memory or MMIO
-VOID
-LibAmdMemRead (
- IN ACCESS_WIDTH AccessWidth,
- IN UINT64 MemAddress,
- OUT VOID *Value,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-LibAmdMemWrite (
- IN ACCESS_WIDTH AccessWidth,
- IN UINT64 MemAddress,
- IN VOID *Value,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-LibAmdMemRMW (
- IN ACCESS_WIDTH AccessWidth,
- IN UINT64 MemAddress,
- IN VOID *Data,
- IN VOID *DataMask,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-LibAmdMemPoll (
- IN ACCESS_WIDTH AccessWidth,
- IN UINT64 MemAddress,
- IN VOID *Data,
- IN VOID *DataMask,
- IN UINT64 Delay,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-// PCI
-VOID
-LibAmdPciRead (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR PciAddress,
- OUT VOID *Value,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-LibAmdPciWrite (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR PciAddress,
- IN VOID *Value,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-LibAmdPciRMW (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR PciAddress,
- IN VOID *Data,
- IN VOID *DataMask,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-LibAmdPciPoll (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR PciAddress,
- IN VOID *Data,
- IN VOID *DataMask,
- IN UINT64 Delay,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-LibAmdPciReadBits (
- IN PCI_ADDR Address,
- IN UINT8 Highbit,
- IN UINT8 Lowbit,
- OUT UINT32 *Value,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-LibAmdPciWriteBits (
- IN PCI_ADDR Address,
- IN UINT8 Highbit,
- IN UINT8 Lowbit,
- IN UINT32 *Value,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-LibAmdPciFindNextCap (
- IN OUT PCI_ADDR *Address,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-// CPUID
-VOID
-LibAmdCpuidRead (
- IN UINT32 CpuidFcnAddress,
- OUT CPUID_DATA *Value,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-// Utility Functions
-VOID
-LibAmdMemFill (
- IN VOID *Destination,
- IN UINT8 Value,
- IN UINTN FillLength,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-LibAmdMemCopy (
- IN VOID *Destination,
- IN VOID *Source,
- IN UINTN CopyLength,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID *
-LibAmdLocateImage (
- IN VOID *StartAddress,
- IN VOID *EndAddress,
- IN UINT32 Alignment,
- IN CHAR8 ModuleSignature[8]
- );
-
-UINT32
-LibAmdGetPackageType (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-BOOLEAN
-LibAmdVerifyImageChecksum (
- IN VOID *ImagePtr
- );
-
-UINT8
-LibAmdBitScanReverse (
- IN UINT32 value
- );
-UINT8
-LibAmdBitScanForward (
- IN UINT32 value
- );
-
-VOID
-LibAmdReadCpuReg (
- IN UINT8 RegNum,
- OUT UINT32 *Value
- );
-VOID
-LibAmdWriteCpuReg (
- IN UINT8 RegNum,
- IN UINT32 Value
- );
-
-VOID
-LibAmdWriteBackInvalidateCache (
- IN VOID
- );
-
-VOID
-LibAmdSimNowEnterDebugger (VOID);
-
-VOID
-LibAmdHDTBreakPoint (VOID);
-
-UINT8
-LibAmdAccessWidth (
- IN ACCESS_WIDTH AccessWidth
- );
-
-VOID
-LibAmdCLFlush (
- IN UINT64 Address,
- IN UINT8 Count
- );
-
-VOID F10RevDProbeFilterCritical (
- IN PCI_ADDR PciAddress,
- IN UINT32 PciRegister
- );
-VOID
-IdsOutPort (
- IN UINT32 Addr,
- IN UINT32 Value,
- IN UINT32 Flag
- );
-
-VOID
-StopHere (
- VOID
- );
-
-VOID
-CpuidRead (
- IN UINT32 CpuidFcnAddress,
- OUT CPUID_DATA *Value
- );
-
-UINT8
-ReadNumberOfCpuCores(
- VOID
- );
-
-#endif // _AMD_LIB_H_
diff --git a/src/vendorcode/amd/agesa/Lib/helper.c b/src/vendorcode/amd/agesa/Lib/helper.c
deleted file mode 100644
index baf661c..0000000
--- a/src/vendorcode/amd/agesa/Lib/helper.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-// helper.c - these functions are compiled separately because they redefine
-// functions invoked directly by the compiler code generator.
-// The Microsoft tools do not allow such functions to be compiled
-// with the "Enable link-time code generation (/GL)" option. Compile
-// this module without /GL to avoid a build failure LNK1237.
-//
-
-#if defined (_MSC_VER)
-
-#include "Porting.h"
-
-//---------------------------------------------------------------------------
-void *memcpy (void *dest, const void *src, size_t bytes)
- {
- // Rep movsb is faster than a byte loop, but still quite slow
- // for large operations. However, it is a good choice here because
- // this function is intended for use by the compiler only. For
- // large copy operations, call LibAmdMemCopy.
- __movsb (dest, src, bytes);
- return dest;
- }
-
-//---------------------------------------------------------------------------
-
-void *memset (void *dest, int value, size_t bytes)
- {
- // Rep stosb is faster than a byte loop, but still quite slow
- // for large operations. However, it is a good choice here because
- // this function is intended for use by the compiler only. For
- // large fill operations, call LibAmdMemFill.
- __stosb (dest, value, bytes);
- return dest;
- }
-//---------------------------------------------------------------------------
-
-#endif
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Lib/x64/amdlib64.asm b/src/vendorcode/amd/agesa/Lib/x64/amdlib64.asm
deleted file mode 100644
index abc1179..0000000
--- a/src/vendorcode/amd/agesa/Lib/x64/amdlib64.asm
+++ /dev/null
@@ -1,591 +0,0 @@
-;/**
-; * @file
-; *
-; * Agesa library 64bit
-; *
-; * Contains AMD AGESA Library
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: Lib
-; * @e \$Revision: 17071 $ @e \$Date: 2009-07-30 10:13:11 -0700 (Thu, 30 Jul 2009) $
-; */
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
-.code
-;/*++
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write IO byte
-; *
-; * @param[in] CX IO port address
-; * @param[in] DL IO port Value
-; */
-
-PUBLIC WriteIo8
-WriteIo8 PROC
- mov al, dl
- mov dx, cx
- out dx, al
- ret
-WriteIo8 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write IO word
-; *
-; * @param[in] CX IO port address
-; * @param[in] DX IO port Value
-; */
-PUBLIC WriteIo16
-WriteIo16 PROC
- mov ax, dx
- mov dx, cx
- out dx, ax
- ret
-WriteIo16 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write IO dword
-; *
-; * @param[in] CX IO port address
-; * @param[in] EDX IO port Value
-; */
-
-PUBLIC WriteIo32
-WriteIo32 PROC
- mov eax, edx
- mov dx, cx
- out dx, eax
- ret
-WriteIo32 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read IO byte
-; *
-; * @param[in] CX IO port address
-; * @retval AL IO port Value
-; */
-PUBLIC ReadIo8
-ReadIo8 PROC
- mov dx, cx
- in al, dx
- ret
-ReadIo8 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read IO word
-; *
-; * @param[in] CX IO port address
-; * @retval AX IO port Value
-; */
-PUBLIC ReadIo16
-ReadIo16 PROC
- mov dx, cx
- in ax, dx
- ret
-ReadIo16 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read IO dword
-; *
-; * @param[in] CX IO port address
-; * @retval EAX IO port Value
-; */
-PUBLIC ReadIo32
-ReadIo32 PROC
- mov dx, cx
- in eax, dx
- ret
-ReadIo32 ENDP
-
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read MSR
-; *
-; * @param[in] RCX MSR Address
-; * @param[in] RDX Pointer to data
-; * @param[in] R8D ConfigPtr (Optional)
-; */
-PUBLIC LibAmdMsrRead
-LibAmdMsrRead PROC
- push rsi
- mov rsi, rdx
- rdmsr
- mov [rsi], eax
- mov [rsi+4], edx
- pop rsi
- ret
-LibAmdMsrRead ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write MSR
-; *
-; * @param[in] RCX MSR Address
-; * @param[in] RDX Pointer to data
-; * @param[in] R8D ConfigPtr (Optional)
-; */
-PUBLIC LibAmdMsrWrite
-LibAmdMsrWrite PROC
- push rsi
- mov rsi, rdx
- mov eax, [rsi]
- and rax, 0ffffffffh
- mov edx, [rsi+4]
- and rdx, 0ffffffffh
- wrmsr
- pop rsi
- ret
-LibAmdMsrWrite ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read CPUID
-; *
-; * @param[in] RCX CPUID function
-; * @param[in] RDX Pointer to CPUID_DATA to save cpuid data
-; * @param[in] R8D ConfigPtr (Optional)
-; */
-PUBLIC LibAmdCpuidRead
-LibAmdCpuidRead PROC
-
- push rbx
- push rsi
- mov rsi, rdx
- mov rax, rcx
- cpuid
- mov [rsi], eax
- mov [rsi+4], ebx
- mov [rsi+8], ecx
- mov [rsi+12],edx
- pop rsi
- pop rbx
- ret
-
-LibAmdCpuidRead ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read TSC
-; *
-; *
-; * @retval RAX Time stamp counter value
-; */
-
-PUBLIC ReadTSC
-ReadTSC PROC
- rdtsc
- and rax, 0ffffffffh
- shl rdx, 32
- or rax, rdx
- ret
-ReadTSC ENDP
-
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read memory/MMIO byte
-; *
-; * @param[in] RCX - Memory Address
-; * @retval Memory byte at given address
-; */
-PUBLIC Read64Mem8
-Read64Mem8 PROC
-
- xor rax, rax
- mov al, [rcx]
- ret
-
-Read64Mem8 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read memory/MMIO word
-; *
-; * @param[in] RCX - Memory Address
-; * @retval Memory word at given address
-; */
-PUBLIC Read64Mem16
-Read64Mem16 PROC
-
- xor rax, rax
- mov ax, [rcx]
- ret
-
-Read64Mem16 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read memory/MMIO dword
-; *
-; * @param[in] RCX - Memory Address
-; * @retval Memory dword at given address
-; */
-PUBLIC Read64Mem32
-Read64Mem32 PROC
-
- xor rax, rax
- mov eax, [rcx]
- ret
-
-Read64Mem32 ENDP
-
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write memory/MMIO byte
-; *
-; * @param[in] RCX Memory Address
-; * @param[in] DL Value to write
-; */
-
-PUBLIC Write64Mem8
-Write64Mem8 PROC
-
- xor rax, rax
- mov rax, rdx
- mov [rcx], al
- ret
-
-Write64Mem8 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write memory/MMIO word
-; *
-; * @param[in] RCX Memory Address
-; * @param[in] DX Value to write
-; */
-PUBLIC Write64Mem16
-Write64Mem16 PROC
-
- xor rax, rax
- mov rax, rdx
- mov [rcx], ax
- ret
-
-Write64Mem16 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write memory/MMIO dword
-; *
-; * @param[in] RCX Memory Address
-; * @param[in] EDX Value to write
-; */
-PUBLIC Write64Mem32
-Write64Mem32 PROC
-
- xor rax, rax
- mov rax, rdx
- mov [rcx], eax
- ret
-
-Write64Mem32 ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Read various CPU registers
-; *
-; * @param[in] CL Register ID (0/4 - CR0/CR4, 10h/11h/12h/13h/17h - DR0/DR1/DR2/DR3/DR7)
-; * @param[in] RDX Pointer to value
-; */
-
-PUBLIC LibAmdReadCpuReg
-LibAmdReadCpuReg PROC
-
- push rax
- xor rax, rax
-Reg00h:
- cmp cl, 00h
- jne Reg04h
- mov rax, cr0
- jmp RegRead
-Reg04h:
- cmp cl, 04h
- jne Reg10h
- mov rax, cr4
- jmp RegRead
-Reg10h:
- cmp cl, 10h
- jne Reg11h
- mov rax, dr0
- jmp RegRead
-Reg11h:
- cmp cl, 11h
- jne Reg12h
- mov rax, dr1
- jmp RegRead
-Reg12h:
- cmp cl, 12h
- jne Reg13h
- mov rax, dr2
- jmp RegRead
-Reg13h:
- cmp cl, 13h
- jne Reg17h
- mov rax, dr3
- jmp RegRead
-Reg17h:
- cmp cl, 17h
- jne RegRead
- mov rax, dr7
-RegRead:
- mov [rdx], eax
- pop rax
- ret
-LibAmdReadCpuReg ENDP
-
-
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write various CPU registers
-; *
-; * @param[in] CL Register ID (0/4 - CR0/CR4, 10h/11h/12h/13h/17h - DR0/DR1/DR2/DR3/DR7)
-; * @param[in] RDX Value to write
-; */
-
-PUBLIC LibAmdWriteCpuReg
-LibAmdWriteCpuReg PROC
-
- push rax
-Reg00h:
- cmp cl, 00h
- jne Reg04h
- mov rax, cr0
- mov eax, edx
- mov cr0, rax
- jmp Done
-Reg04h:
- cmp cl, 04h
- jne Reg10h
- mov rax, cr4
- mov eax, edx
- mov cr4, rax
- jmp Done
-Reg10h:
- cmp cl, 10h
- jne Reg11h
- mov rax, dr0
- mov eax, edx
- mov dr0, rax
- jmp Done
-Reg11h:
- cmp cl, 11h
- jne Reg12h
- mov rax, dr1
- mov eax, edx
- mov dr1, rax
- jmp Done
-Reg12h:
- cmp cl, 12h
- jne Reg13h
- mov rax, dr2
- mov eax, edx
- mov dr2, rax
- jmp Done
-Reg13h:
- cmp cl, 13h
- jne Reg17h
- mov rax, dr3
- mov eax, edx
- mov dr3, rax
- jmp Done
-Reg17h:
- cmp cl, 17h
- jne Done
- mov rax, dr7
- mov eax, edx
- mov dr7, rax
-Done:
- pop rax
- ret
-LibAmdWriteCpuReg ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Write back invalidate caches using wbinvd.
-; *
-; *
-; *
-; */
-
-PUBLIC LibAmdWriteBackInvalidateCache
-LibAmdWriteBackInvalidateCache PROC
- wbinvd
- ret
-LibAmdWriteBackInvalidateCache ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Stop CPU
-; *
-; *
-; *
-; */
-
-PUBLIC StopHere
-StopHere PROC
-@@:
- jmp short @b
-StopHere ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Enter debugger on SimNow
-; *
-; *
-; *
-; */
-PUBLIC LibAmdSimNowEnterDebugger
-LibAmdSimNowEnterDebugger PROC
- pushfq
- mov rax, 0BACCD00Bh ; Backdoor in SimNow
- mov rbx, 2 ; Select breakpoint feature
- cpuid
-@@:
- jmp short @b
- popfq
- ret
-LibAmdSimNowEnterDebugger ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * IDS IO port write
-; *
-; * @param[in] ECX IO Port Address
-; * @param[in] EDX Value to write
-; * @param[in] R8D IDS flags
-; *
-; */
-
-PUBLIC IdsOutPort
-IdsOutPort PROC
- push rbx
- push rax
-
- mov ebx, r8d
- mov eax, edx
- mov edx, ecx
- out dx, eax
-
- pop rax
- pop rbx
- ret
-IdsOutPort ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Force breakpoint on HDT
-; *
-; *
-; */
-PUBLIC LibAmdHDTBreakPoint
-LibAmdHDTBreakPoint PROC
-
- push rbx
-
- mov rcx, 0C001100Ah ;bit 0 = HDT redirect
- mov rdi, 09C5A203Ah ;Password
- rdmsr
- and rax, 0ffffffffh
- or rax, 1
-
- wrmsr
-
- mov rax, 0B2h ;Marker = B2
- db 0F1h ;ICEBP
-
- pop rbx
- ret
-
-LibAmdHDTBreakPoint ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Find the most right hand side non-zero bit with
-; *
-; * @param[in] ECX Value
-; */
-PUBLIC LibAmdBitScanForward
-LibAmdBitScanForward PROC
- bsf eax, ecx
- jnz nonZeroSource
- mov al,32
-nonZeroSource:
- ret
-LibAmdBitScanForward ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Find the most left hand side non-zero bit.
-; *
-; * @param[in] ECX Value
-; */
-PUBLIC LibAmdBitScanReverse
-LibAmdBitScanReverse PROC
- bsr eax, ecx
- jnz nonZeroSource
- mov al,0FFh
-nonZeroSource:
- ret
-LibAmdBitScanReverse ENDP
-
-;/*---------------------------------------------------------------------------------------*/
-;/**
-; * Flush specified number of cache line
-; *
-; * @param[in] RCX Physical address to be flushed
-; * @param[in] DL number of cachelines to be flushed
-; */
-PUBLIC LibAmdCLFlush
-LibAmdCLFlush PROC
- push rax
- mov rax, rcx
- movzx rcx, dl
- @@:
- mfence
- clflush [rax]
- mfence
- add rax,64
- loop @B
- pop rax
- ret
-LibAmdCLFlush ENDP
-
-END
diff --git a/src/vendorcode/amd/agesa/MainPage.h b/src/vendorcode/amd/agesa/MainPage.h
deleted file mode 100644
index a4a3797..0000000
--- a/src/vendorcode/amd/agesa/MainPage.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Create outline and references for mainpage documentation.
- *
- * Design guides, maintenance guides, and general documentation, are
- * collected using this file onto the documentation mainpage.
- * This file contains doxygen comment blocks, only.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Documentation
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/**
- * @mainpage
- *
- * The design and maintenance documentation for AGESA Sample Code is organized as
- * follows. On this page, you can reference design guides, maintenance guides, and
- * general documentation. Detailed Data Structure, Function, and Interface documentation
- * may be found using the Data Structures or Files tabs. See Related Pages for a
- * Release content summary, and, if this is not a production release, lists of To Do's,
- * Deprecated items, etc.
- *
- * @subpage starthere "Start Here - Initial Porting and Integration."
- *
- * @subpage optionmain "Build Configuration and Options Guides and Documentation."
- *
- * @subpage commonmain "Processor Common Component Guides and Documentation."
- *
- * @subpage cpumain "CPU Component Guides and Documentation."
- *
- * @subpage htmain "HT Component Guides and Documentation."
- *
- * @subpage memmain "MEM Component Guides and Documentation."
- *
- * @subpage gnbmain "GNB Component Documentation."
- *
- * @subpage idsmain "IDS Component Guides and Documentation."
- *
- * @subpage recoverymain "Recovery Component Guides and Documentation."
- *
- */
-
-/**
- * @page starthere Initial Porting and Integration
- *
- * @par Basic Check List
- *
- * <ul>
- * <li> Copy the \<plat\>Options.c file from the Addendum directory to the platform tip build directory.
- * AMD recommends the use of a sub-directory named AGESA to contain these files and the build output files.
- * <li> Copy the OptionsIds.h content in the spec to OptionsIds.h in the platform build tip directory
- * and make changes to enable the IDS support desired. It is highly recommended to set the following for
- * initial integration and development:@n
- * @code
- * #define IDSOPT_IDS_ENABLED TRUE
- * #define IDSOPT_ERROR_TRAP_ENABLED TRUE
- * #define IDSOPT_ASSERT_ENABLED TRUE
- * @endcode
- * <li> Edit and modify the option selections in those two files to meet the needs of the specific platform.
- * <li> Set the environment variable AGESA_ROOT to the root folder of the AGESA code.
- * <li> Set the environment variable AGESA_OptsDir the platform build tip AGESA directory.
- * <li> Generate the doxygen documentation or locate the file arch2008.chm within your AGESA release package.
- * </ul>
- *
- * @par Debugging Using ASSERT and IDS_ERROR_TRAP
- *
- * While AGESA code uses ::ASSERT and ::IDS_ERROR_TRAP to check for internal errors, these macros can also
- * catch and assist debug of wrapper and platform BIOS issues.
- *
- * When an ::ASSERT fails or an ::IDS_ERROR_TRAP is executed, the AGESA code will enter a halt loop and display a
- * Stop Code. A Stop Code is eight hex digits. The first (most significant) four are the FILECODE.
- * FILECODEs can be looked up in Filecode.h to determine which file contains the stop macro. Each file has a
- * unique code value.
- * The least significant digits are the line number in that file.
- * For example, 0210 means the macro is on line two hundred ten.
- * (see ::IdsErrorStop for more details on stop code display.)
- *
- * Enabling ::ASSERT and ::IDS_ERROR_TRAP ensure errors are caught and also provide a useful debug assist.
- * Comments near each macro use will describe the nature of the error and typical wrapper errors or other
- * root causes.
- *
- * After your wrapper consistently executes ::ASSERT and ::IDS_ERROR_TRAP stop free, you can disable them in
- * OptionsIds.h, except for regression testing. IDS is not expected to be enabled in production BIOS builds.
- *
- */
diff --git a/src/vendorcode/amd/agesa/Makefile.inc b/src/vendorcode/amd/agesa/Makefile.inc
deleted file mode 100644
index 3ac671b..0000000
--- a/src/vendorcode/amd/agesa/Makefile.inc
+++ /dev/null
@@ -1,62 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2010 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-#
-
-# AGESA V5 Files
-AGESA_ROOT = src/vendorcode/amd/agesa
-
-AGESA_INC = -Isrc/mainboard/$(MAINBOARDDIR)
-AGESA_INC += -I$(AGESA_ROOT)
-AGESA_INC += -I$(AGESA_ROOT)/Include
-AGESA_INC += -I$(AGESA_ROOT)/Lib
-AGESA_INC += -I$(AGESA_ROOT)/Legacy
-AGESA_INC += -I$(AGESA_ROOT)/Proc/Common
-AGESA_INC += -I$(AGESA_ROOT)/Proc/HT
-AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU
-AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Feature
-AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Family
-AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Family/0x14
-AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Family/0x14/ON
-AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem
-AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/NB/ON
-AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS
-AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Family
-AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Family/0x14
-AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB
-AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Common
-AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Nb
-AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Nb/Family
-AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Nb/Family/0x14
-AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Nb/Feature
-AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/PCIe
-AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/PCIe/Family
-AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14
-AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/PCIe/Feature
-AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Gfx
-AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Gfx/Family
-AGESA_INC += -I$(AGESA_ROOT)/Proc/Recovery/GNB
-AGESA_INC += -I$(AGESA_ROOT)/Proc/Recovery/CPU
-AGESA_INC += -I$(AGESA_ROOT)/Proc/Recovery/Mem
-
-AGESA_CFLAGS =-march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing
-
-export AGESA_ROOT := $(AGESA_ROOT)
-export AGESA_INC := $(AGESA_INC)
-export AGESA_CFLAGS := $(AGESA_CFLAGS)
-CC := $(CC) $(AGESA_INC) $(AGESA_CFLAGS)
-#######################################################################
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Porting.h b/src/vendorcode/amd/agesa/Porting.h
deleted file mode 100644
index 4550c86..0000000
--- a/src/vendorcode/amd/agesa/Porting.h
+++ /dev/null
@@ -1,296 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Describes compiler dependencies - to support several compile time environments
- *
- * Contains compiler environment porting descriptions
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Includes
- * @e \$Revision: 36567 $ @e \$Date: 2010-08-21 02:35:15 +0800 (Sat, 21 Aug 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _PORTING_H_
-#define _PORTING_H_
-
-#if defined (_MSC_VER)
- #include <intrin.h>
- void _disable (void);
- void _enable (void);
- #pragma warning(disable: 4103 4001 4733)
- #pragma intrinsic (_disable, _enable)
- #pragma warning(push)
- // -----------------------------------------------------------------------
- // Define a code_seg MACRO
- //
- #define MAKE_AS_A_STRING(arg) #arg
-
- #define CODE_GROUP(arg) __pragma (code_seg (MAKE_AS_A_STRING (.t##arg)))
-
- #define RDATA_GROUP(arg) __pragma (const_seg (MAKE_AS_A_STRING (.d##arg)))
- #define FUNC_ATTRIBUTE(arg) __declspec(arg)
- //#include <intrin.h> // MS has built-in functions
-
- #if _MSC_VER < 900
- // -----------------------------------------------------------------------
- // Assume MSVC 1.52C (16-bit)
- //
- // NOTE: When using MSVC 1.52C use the following command line:
- //
- // CL.EXE /G3 /AL /O1i /Fa <FILENAME.C>
- //
- // This will produce 32-bit code in USE16 segment that is optimized for code
- // size.
- typedef void VOID;
-
- // Create the universal 32, 16, and 8-bit data types
- typedef unsigned long UINTN;
- typedef long INT32;
- typedef unsigned long UINT32;
- typedef int INT16;
- typedef unsigned int UINT16;
- typedef char INT8;
- typedef unsigned char UINT8;
- typedef char CHAR8;
- typedef unsigned short CHAR16;
-
- /// struct for 16-bit environment handling of 64-bit value
- typedef struct _UINT64 {
- IN OUT UINT32 lo; ///< lower 32-bits of 64-bit value
- IN OUT UINT32 hi; ///< highest 32-bits of 64-bit value
- } UINT64;
-
- // Create the Boolean type
- #define TRUE 1
- #define FALSE 0
- typedef unsigned char BOOLEAN;
-
- #define CONST const
- #define STATIC static
- #define VOLATILE volatile
- #define CALLCONV __pascal
- #define ROMDATA __based( __segname( "_CODE" ) )
- #define _16BYTE_ALIGN __declspec(align(16))
-
- // Force tight packing of structures
- // Note: Entire AGESA (Project / Solution) will be using pragma pack 1
- #pragma warning( disable : 4103 ) // Disable '#pragma pack' in .h warning
- #pragma pack(1)
-
- // Disable WORD->BYTE automatic conversion warnings. Example:
- // BYTE LocalByte;
- // void MyFunc(BYTE val);
- //
- // MyFunc(LocalByte*2+1); // Warning, automatic conversion
- //
- // The problem is any time math is performed on a BYTE, it is converted to a
- // WORD by MSVC 1.52c, and then when it is converted back to a BYTE, a warning
- // is generated. Disable warning C4761
- #pragma warning( disable : 4761 )
-
- #else
- // -----------------------------------------------------------------------
- // Assume a 32-bit MSVC++
- //
- // Disable the following warnings:
- // 4100 - 'identifier' : unreferenced formal parameter
- // 4276 - 'function' : no prototype provided; assumed no parameters
- // 4214 - non standard extension used : bit field types other than int
- // 4001 - nonstandard extension 'single line comment' was used
- // 4142 - benign redefinition of type for following declaration
- // - typedef char INT8
- #if defined (_M_IX86)
- #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306)
-
- #ifndef VOID
- typedef void VOID;
- #endif
- // Create the universal 32, 16, and 8-bit data types
- #ifndef UINTN
- typedef unsigned __w64 UINTN;
- #endif
- typedef __int64 INT64;
- typedef unsigned __int64 UINT64;
- typedef int INT32;
- typedef unsigned int UINT32;
- typedef short INT16;
- typedef unsigned short UINT16;
- typedef char INT8;
- typedef unsigned char UINT8;
- typedef char CHAR8;
- typedef unsigned short CHAR16;
-
- // Create the Boolean type
- #ifndef TRUE
- #define TRUE 1
- #endif
- #ifndef FALSE
- #define FALSE 0
- #endif
- typedef unsigned char BOOLEAN;
-
- // Force tight packing of structures
- // Note: Entire AGESA (Project / Solution) will be using pragma pack 1
- #pragma pack(1)
-
- #define CONST const
- #define STATIC static
- #define VOLATILE volatile
- #define CALLCONV
- #define ROMDATA
- #define _16BYTE_ALIGN __declspec(align(64))
- // 64 bit of compiler
- #else
- #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306 4366)
-
- #ifndef VOID
- typedef void VOID;
- #endif
- // Create the universal 32, 16, and 8-bit data types
- #ifndef UINTN
- typedef unsigned __int64 UINTN;
- #endif
- typedef __int64 INT64;
- typedef unsigned __int64 UINT64;
- typedef int INT32;
- typedef unsigned int UINT32;
- typedef short INT16;
- typedef unsigned short UINT16;
- typedef char INT8;
- typedef unsigned char UINT8;
- typedef char CHAR8;
- typedef unsigned short CHAR16;
-
- // Create the Boolean type
- #ifndef TRUE
- #define TRUE 1
- #endif
- #ifndef FALSE
- #define FALSE 0
- #endif
- typedef unsigned char BOOLEAN;
-
- // Force tight packing of structures
- // Note: Entire AGESA (Project / Solution) will be using pragma pack 1
- #pragma pack(1)
-
- #define CONST const
- #define STATIC static
- #define VOLATILE volatile
- #define CALLCONV
- #define ROMDATA
- #endif
- #endif
- // -----------------------------------------------------------------------
- // End of MS compiler versions
-
-
-#elif defined __GNUC__
-
- #define IN
- #define OUT
- #define STATIC static
- #define VOLATILE volatile
- #define TRUE 1
- #define FALSE 0
- #define CONST const
- #define ROMDATA
- #define CALLCONV
- #define _16BYTE_ALIGN __attribute__ ((aligned (16)))
-
- typedef unsigned char BOOLEAN;
- typedef signed char INT8;
- typedef signed short INT16;
- typedef signed long INT32;
- typedef unsigned char CHAR8;
- typedef unsigned char UINT8;
- typedef unsigned short UINT16;
- typedef unsigned long UINT32;
- typedef unsigned long UINTN;
- typedef unsigned long long UINT64;
- typedef void VOID;
- //typedef unsigned long size_t;
-//typedef unsigned int uintptr_t;
-// Force tight packing of structures
-// Note: Entire AGESA (Project / Solution) will be using pragma pack 1
-#pragma pack(1)
-
-#define CODE_GROUP(arg)
-#define RDATA_GROUP(arg)
-
-#define FUNC_ATTRIBUTE(arg) __attribute__((arg))
-#define MAKE_AS_A_STRING(arg) #arg
-
-// -----------------------------------------------------------------------
-// Common definitions for all compilers
-//
-#include <stddef.h>
-#include "gcc-intrin.h"
-
-#include <assert.h>
-#include <console/console.h>
-#include <console/loglevel.h>
-
-#ifndef NULL
- #define NULL (void *)0
-#endif
-#ifdef ROMDATA
-//#undef ROMDATA
-#endif
-//#define ROMDATA __attribute__ ((section("rom.data"))
-
-#else
- // -----------------------------------------------------------------------
- // Unknown or unsupported compiler
- //
- #error "Unknown compiler in use"
-#endif
-
-
-
-// -----------------------------------------------------------------------
-// Common definitions for all compilers
-//
-
-//Support forward reference construct
-#define AGESA_FORWARD_DECLARATION(x) typedef struct _##x x
-
-
-// The following are use in conformance to the UEFI style guide
-#define IN
-#define OUT
-
-#endif // _PORTING_H_
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10InitEarlyTable.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10InitEarlyTable.c
deleted file mode 100644
index 77d3237..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10InitEarlyTable.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Initialize the Family 10h specific way of running early initialization.
- *
- * Returns the table of initialization steps to perform at
- * AmdInitEarly.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-#include "cpuEarlyInit.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_F10INITEARLYTABLE_FILECODE
-
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-extern F_PERFORM_EARLY_INIT_ON_CORE McaInitializationAtEarly;
-extern F_PERFORM_EARLY_INIT_ON_CORE SetRegistersFromTablesAtEarly;
-extern F_PERFORM_EARLY_INIT_ON_CORE SetBrandIdRegistersAtEarly;
-extern F_PERFORM_EARLY_INIT_ON_CORE LocalApicInitializationAtEarly;
-extern F_PERFORM_EARLY_INIT_ON_CORE LoadMicrocodePatchAtEarly;
-
-CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F10EarlyInitOnCoreTable[] =
-{
- {McaInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION},
- {SetRegistersFromTablesAtEarly, PERFORM_EARLY_ANY_CONDITION},
- {SetBrandIdRegistersAtEarly, PERFORM_EARLY_ANY_CONDITION},
- {LocalApicInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION},
- {LoadMicrocodePatchAtEarly, PERFORM_EARLY_WARM_RESET},
- {NULL, 0}
-};
-
-/*------------------------------------------------------------------------------------*/
-/**
- * Initializer routine that may be invoked at AmdCpuEarly to return the steps that a
- * processor that uses the standard initialization steps should take.
- *
- * @CpuServiceMethod{::F_GET_EARLY_INIT_TABLE}.
- *
- * @param[in] FamilyServices The current Family Specific Services.
- * @param[out] Table Table of appropriate init steps for the executing core.
- * @param[in] EarlyParams Service Interface structure to initialize.
- * @param[in] StdHeader Opaque handle to standard config header.
- *
- */
-VOID
-GetF10EarlyInitOnCoreTable (
- IN CPU_SPECIFIC_SERVICES *FamilyServices,
- OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table,
- IN AMD_CPU_EARLY_PARAMS *EarlyParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- *Table = F10EarlyInitOnCoreTable;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10IoCstate.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10IoCstate.c
deleted file mode 100644
index d6b1443..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10IoCstate.c
+++ /dev/null
@@ -1,294 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 IO C-state feature support functions.
- *
- * Provides the functions necessary to initialize the IO C-state feature.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuFeatures.h"
-#include "cpuIoCstate.h"
-#include "cpuF10PowerMgmt.h"
-#include "cpuLateInit.h"
-#include "cpuRegisters.h"
-#include "cpuServices.h"
-#include "cpuApicUtilities.h"
-#include "cpuFamilyTranslation.h"
-#include "CommonReturns.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-#define FILECODE PROC_CPU_FAMILY_0X10_F10IOCSTATE_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-VOID
-STATIC
-F10InitializeIoCstateOnCore (
- IN VOID *CstateBaseMsr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-extern CPU_FAMILY_SUPPORT_TABLE IoCstateFamilyServiceTable;
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Enable IO Cstate on a family 10h CPU.
- *
- * @param[in] IoCstateServices Pointer to this CPU's IO Cstate family services.
- * @param[in] EntryPoint Timepoint designator.
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @return AGESA_SUCCESS Always succeeds.
- *
- */
-AGESA_STATUS
-STATIC
-F10InitializeIoCstate (
- IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
- IN UINT64 EntryPoint,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 MsrRegister;
- AP_TASK TaskPtr;
-
- if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) {
- // Initialize MSRC001_0073[CstateAddr] on each core to a region of
- // the IO address map with 8 consecutive available addresses.
- MsrRegister = 0;
-
- ((CSTATE_ADDRESS_MSR *) &MsrRegister)->CstateAddr = PlatformConfig->CStateIoBaseAddress;
-
- TaskPtr.FuncAddress.PfApTaskI = F10InitializeIoCstateOnCore;
- TaskPtr.DataTransfer.DataSizeInDwords = 2;
- TaskPtr.DataTransfer.DataPtr = &MsrRegister;
- TaskPtr.DataTransfer.DataTransferFlags = 0;
- TaskPtr.ExeFlags = WAIT_FOR_CORE;
- ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
- }
- return AGESA_SUCCESS;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Enable CState on a family 10h core.
- *
- * @param[in] CstateBaseMsr MSR value to write to C001_0073 as determined by core 0.
- * @param[in] StdHeader Config Handle for library, services.
- *
- */
-VOID
-STATIC
-F10InitializeIoCstateOnCore (
- IN VOID *CstateBaseMsr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- // Initialize MSRC001_0073[CstateAddr] on each core
- LibAmdMsrWrite (MSR_CSTATE_ADDRESS, (UINT64 *) CstateBaseMsr, StdHeader);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns the size of CST object
- *
- * @param[in] IoCstateServices IO Cstate services.
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval CstObjSize Size of CST Object
- *
- */
-UINT32
-STATIC
-F10GetAcpiCstObj (
- IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- return (CST_HEADER_SIZE + CST_BODY_SIZE);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Routine to generate the C-State ACPI objects
- *
- * @param[in] IoCstateServices IO Cstate services.
- * @param[in] LocalApicId Local Apic Id for each core.
- * @param[in, out] **PstateAcpiBufferPtr Pointer to the Acpi Buffer Pointer.
- * @param[in] StdHeader Config Handle for library, services.
- *
- */
-VOID
-STATIC
-F10CreateAcpiCstObj (
- IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
- IN UINT8 LocalApicId,
- IN OUT VOID **PstateAcpiBufferPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 MsrData;
- CST_HEADER_STRUCT *CstHeaderPtr;
- CST_BODY_STRUCT *CstBodyPtr;
-
- // Read from MSR C0010073 to obtain CstateAddr
- LibAmdMsrRead (MSR_CSTATE_ADDRESS, &MsrData, StdHeader);
- ASSERT ((((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr != 0) &&
- (((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr <= 0xFFF8));
-
- // Typecast the pointer
- CstHeaderPtr = (CST_HEADER_STRUCT *) *PstateAcpiBufferPtr;
-
- // Set CST Header
- CstHeaderPtr->NameOpcode = NAME_OPCODE;
- CstHeaderPtr->CstName_a__ = CST_NAME__;
- CstHeaderPtr->CstName_a_C = CST_NAME_C;
- CstHeaderPtr->CstName_a_S = CST_NAME_S;
- CstHeaderPtr->CstName_a_T = CST_NAME_T;
-
- // Typecast the pointer
- CstHeaderPtr++;
- CstBodyPtr = (CST_BODY_STRUCT *) CstHeaderPtr;
-
- // Set CST Body
- CstBodyPtr->PkgOpcode = PACKAGE_OPCODE;
- CstBodyPtr->PkgLength = CST_LENGTH;
- CstBodyPtr->PkgElements = CST_NUM_OF_ELEMENTS;
- CstBodyPtr->BytePrefix = BYTE_PREFIX_OPCODE;
- CstBodyPtr->Count = CST_COUNT;
- CstBodyPtr->PkgOpcode2 = PACKAGE_OPCODE;
- CstBodyPtr->PkgLength2 = CST_PKG_LENGTH;
- CstBodyPtr->PkgElements2 = CST_PKG_ELEMENTS;
- CstBodyPtr->BufferOpcode = BUFFER_OPCODE;
- CstBodyPtr->BufferLength = CST_SUBPKG_LENGTH;
- CstBodyPtr->BufferElements = CST_SUBPKG_ELEMENTS;
- CstBodyPtr->BufferOpcode2 = BUFFER_OPCODE;
- CstBodyPtr->GdrOpcode = GENERIC_REG_DESCRIPTION;
- CstBodyPtr->GdrLength = CST_GDR_LENGTH;
- CstBodyPtr->AddrSpaceId = GDR_ASI_SYSTEM_IO;
- CstBodyPtr->RegBitWidth = 0x08;
- CstBodyPtr->RegBitOffset = 0x00;
- CstBodyPtr->AddressSize = GDR_ASZ_BYTE_ACCESS;
- CstBodyPtr->RegisterAddr = ((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr;
- CstBodyPtr->EndTag = 0x0079;
- CstBodyPtr->BytePrefix2 = BYTE_PREFIX_OPCODE;
- CstBodyPtr->Type = CST_C2_TYPE;
- CstBodyPtr->WordPrefix = WORD_PREFIX_OPCODE;
- CstBodyPtr->Latency = 0x4B;
- CstBodyPtr->DWordPrefix = DWORD_PREFIX_OPCODE;
- CstBodyPtr->Power = 0;
-
- CstBodyPtr++;
-
- //Update the pointer
- *PstateAcpiBufferPtr = CstBodyPtr;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Routine to check whether IO Cstate should be supported.
- *
- * @param[in] IoCstateServices IO Cstate services.
- * @param[in] Socket Zero-based socket number.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval TRUE Support IO Cstate.
- * @retval FALSE Do not support IO Cstate.
- *
- */
-BOOLEAN
-F10IsIoCstateFeatureSupported (
- IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
- IN UINT32 Socket,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 MsrRegister;
- CPUID_DATA CpuId;
- CPU_LOGICAL_ID LogicalId;
-
- GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
- // Only Rev.E processor with CPB enabled and ucode 010000BF or later loaded
- // MSR_C001_0073 can be programmed
- if ((LogicalId.Revision & AMD_F10_Ex) != 0) {
- LibAmdCpuidRead (AMD_CPUID_APM, &CpuId, StdHeader);
- if (((CpuId.EDX_Reg & 0x00000200) >> 9) == 1) {
- LibAmdMsrRead (MSR_PATCH_LEVEL, &MsrRegister, StdHeader);
- if ((MsrRegister & 0xffffffff) >= 0x010000BF) {
- return TRUE;
- }
- }
- }
- return FALSE;
-}
-
-CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F10IoCstateSupport =
-{
- 0,
- F10IsIoCstateFeatureSupported,
- F10InitializeIoCstate,
- F10GetAcpiCstObj,
- F10CreateAcpiCstObj,
- (PF_IO_CSTATE_IS_CSD_GENERATED) CommonReturnFalse
-};
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10MultiLinkPciTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10MultiLinkPciTables.c
deleted file mode 100644
index 18cf367..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10MultiLinkPciTables.c
+++ /dev/null
@@ -1,1527 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 PCI tables from Multi-Link BKDG paragraph recommended settings.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x10
- * @e \$Revision: 37704 $ @e \$Date: 2010-09-10 10:12:39 +0800 (Fri, 10 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_F10MULTILINKPCITABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-// P C I T a b l e s
-// ----------------------
-
-STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10MultiLinkPciRegisters[] =
-{
- // Function 0
-
-// F0x68 - Link Transaction Control
-// bit[14:13], BufPriRel = 02h
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- (AMD_F10_ALL & ~AMD_F10_Dx), // CpuRevision rev C or less.
- },
- AMD_PF_MULTI_LINK, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68), // Address
- 0x00004000, // regData
- 0x00006000, // regMask
- }
- },
- // F0x[F0,D0,B0,90] Link Base Buffer Count Register
- // 27:25 FreeData: 2
- // 24:20 FreeCmd: 8
- // 19:18 RspData: 2
- // 17:16 NpReqData: 2
- // 15:12 ProbeCmd: 9
- // 11:8 RspCmd: 9
- // 7:5 PReq: 2
- // 4:0 NpReqCmd: 4
-{
- HtHostPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM), // platformFeatures
- {
- HT_HOST_FEAT_COHERENT, // link features
- 0x10, // address
- 0x048A9944, // data
- 0x0FFFFFFF // mask
- }
- },
- // F0x[F0,D0,B0,90] Link Base Buffer Count Register
- // 27:25 FreeData: 2
- // 24:20 FreeCmd: 8
- // 19:18 RspData: 1
- // 17:16 NpReqData: 1
- // 15:12 ProbeCmd: 0
- // 11:8 RspCmd: 2
- // 7:5 PReq: 4
- // 4:0 NpReqCmd: 18
- {
- HtHostPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Cx // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM), // platformFeatures
- {
- HT_HOST_FEAT_NONCOHERENT, // link features
- 0x10, // address
- 0x04850292, // data
- 0x0FFFFFFF // mask
- }
- },
- // F0x[F0,D0,B0,90] Link Base Buffer Count Register
- // 27:25 FreeData: 0
- // 24:20 FreeCmd: 8
- // 19:18 RspData: 1
- // 17:16 NpReqData: 1
- // 15:12 ProbeCmd: 0
- // 11:8 RspCmd: 2
- // 7:5 PReq: 6
- // 4:0 NpReqCmd: 16
- {
- HtHostPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Dx // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM), // platformFeatures
- {
- HT_HOST_FEAT_NONCOHERENT, // link features
- 0x10, // address
- 0x008502D0, // data
- 0x0FFFFFFF // mask
- }
- },
- // F0x[F0,D0,B0,90] Link Base Buffer Count Register
- // 27:25 FreeData: 0
- // 24:20 FreeCmd: 8
- // 19:18 RspData: 3
- // 17:16 NpReqData: 2
- // 15:12 ProbeCmd: 8
- // 11:8 RspCmd: 9
- // 7:5 PReq: 2
- // 4:0 NpReqCmd: 4
- {
- HtHostPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU), // platformFeatures
- {
- HT_HOST_FEAT_COHERENT, // link features
- 0x10, // address
- 0x008E8944, // data
- 0x0FFFFFFF // mask
- }
- },
- // F0x[F0,D0,B0,90] Link Base Buffer Count Register
- // 27:25 FreeData: 0
- // 24:20 FreeCmd: 8
- // 19:18 RspData: 1
- // 17:16 NpReqData: 1
- // 15:12 ProbeCmd: 0
- // 11:8 RspCmd: 2
- // 7:5 PReq: 6
- // 4:0 NpReqCmd: 15
- {
- HtHostPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU), // platformFeatures
- {
- HT_HOST_FEAT_NONCOHERENT, // link features
- 0x10, // address
- 0x008502CF, // data
- 0x0FFFFFFF // mask
- }
- },
- // F0x[F4,D4,B4,94] Link Base Buffer Count Register
- // 28:27 IsocRspData: 0
- // 26:25 IsocNpReqData: 0
- // 24:22 IsocRspCmd: 0
- // 21:19 IsocPReq: 0
- // 18:16 IsocNpReqCmd: 0
-{
- HtHostPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM), // platformFeatures
- {
- HT_HOST_FEAT_COHERENT, // link features
- 0x14, // address
- 0x00000000, // data
- 0x1FFF0000 // mask
- }
- },
- // F0x[F4,D4,B4,94] Link Base Buffer Count Register
- // 28:27 IsocRspData: 0
- // 26:25 IsocNpReqData: 0
- // 24:22 IsocRspCmd: 0
- // 21:19 IsocPReq: 0
- // 18:16 IsocNpReqCmd: 0
- {
- HtHostPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM), // platformFeatures
- {
- HT_HOST_FEAT_NONCOHERENT, // link features
- 0x14, // address
- 0x00000000, // data
- 0x1FFF0000 // mask
- }
- },
- // F0x[F4,D4,B4,94] Link Base Buffer Count Register
- // 28:27 IsocRspData: 0
- // 26:25 IsocNpReqData: 1
- // 24:22 IsocRspCmd: 0
- // 21:19 IsocPReq: 0
- // 18:16 IsocNpReqCmd: 1
- {
- HtHostPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU), // platformFeatures
- {
- HT_HOST_FEAT_COHERENT, // link features
- 0x14, // address
- 0x02010000, // data
- 0x1FFF0000 // mask
- }
- },
- // F0x[F4,D4,B4,94] Link Base Buffer Count Register
- // 28:27 IsocRspData: 0
- // 26:25 IsocNpReqData: 0
- // 24:22 IsocRspCmd: 0
- // 21:19 IsocPReq: 0
- // 18:16 IsocNpReqCmd: 1
- {
- HtHostPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU), // platformFeatures
- {
- HT_HOST_FEAT_NONCOHERENT, // link features
- 0x14, // address
- 0x00010000, // data
- 0x1FFF0000 // mask
- }
- },
-
-// Function 3 - Misc. Control
-
-// F3x6C - Data Buffer Control
-// XBAR buffer settings
-// bits[2:0] UpReqDBC = 2
-// bits[5:4] DnReqDBC = 1
-// bits[7:6] DnRspDBC = 1
-// bit[15] DatBuf24 = 1
-// bits[18:16] UpRspDBC = 1
-// bits[30:28] IsocRspDBC = 0
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Cx // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM), // platformFeatures
- {
- MAKE_SBDFO(0, 0, 24, FUNC_3, 0x6C), // Address
- 0x00018052, // regData
- 0x700780F7, // regMask
- }
- },
-// F3x6C - Data Buffer Control
-// XBAR buffer settings
-// bits[2:0] UpReqDBC = 2
-// bits[5:4] DnReqDBC = 1
-// bits[7:6] DnRspDBC = 1
-// bit[15] DatBuf24 = 1
-// bits[18:16] UpRspDBC = 2
-// bits[30:28] IsocRspDBC = 0
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Dx // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM), // platformFeatures
- {
- MAKE_SBDFO(0, 0, 24, FUNC_3, 0x6C), // Address
- 0x00028052, // regData
- 0x700780F7, // regMask
- }
- },
-// F3x6C - Data Buffer Control
-// bits[2:0] UpReqDBC = 2
-// bits[5:4] DnReqDBC = 1
-// bits[7:6] DnRspDBC = 1
-// bit[15] DatBuf24 = 1
-// bits[18:16] UpRspDBC = 1
-// bits[30:28] IsocRspDBC = 1
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU), // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C), // Address
- 0x10018052, // regData
- 0x700780F7, // regMask
- }
- },
-// F3x70 - SRI_to_XBAR Command Buffer Count
-// bits[2:0] UpReqCBC = 3
-// bits[5:4] DnReqCBC = 1
-// bits[7:6] DnRspCBC = 1
-// bits[10:8] UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 1
-// bits[18:16] UpRspCBC = 4
-// bits[22:20] IsocReqCBC = 0
-// bits[26:24] IsocPreqCBC = 0
-// bits[30:28] IsocRspCBC = 0
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Cx // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM), // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70), // Address
- 0x00041153, // regData
- 0x777777F7, // regMask
- }
- },
-// F3x70 - SRI_to_XBAR Command Buffer Count
-// bits[2:0] UpReqCBC = 3
-// bits[5:4] DnReqCBC = 1
-// bits[7:6] DnRspCBC = 1
-// bits[10:8] UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 1
-// bits[18:16] UpRspCBC = 5
-// bits[22:20] IsocReqCBC = 0
-// bits[26:24] IsocPreqCBC = 0
-// bits[30:28] IsocRspCBC = 0
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Dx // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM), // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70), // Address
- 0x00051153, // regData
- 0x777777F7, // regMask
- }
- },
-// F3x70 - SRI_to_XBAR Command Buffer Count
-// bits[2:0] UpReqCBC = 3
-// bits[5:4] DnReqCBC = 1
-// bits[7:6] DnRspCBC = 1
-// bits[10:8] UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 1
-// bits[18:16] UpRspCBC = 5
-// bits[22:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 0
-// bits[30:28] IsocRspCBC = 1
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU), // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70), // Address
- 0x10151153, // regData
- 0x777777F7, // regMask
- }
- },
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// bits[2:0] UpReqCBC = 1
-// bits[6:4] DnReqCBC = 1
-// bits[10:8] UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 1
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 0
-// bits[26:24] IsocPreqCBC = 0
-// bits[30:28] DRReqCBC = 0
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM), // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address
- 0x00081111, // regData
- 0x00FF7777, // regMask
- }
- },
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// bits[2:0] UpReqCBC = 1
-// bits[6:4] DnReqCBC = 1
-// bits[10:8] UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 1
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 0
-// bits[30:28] DRReqCBC = 0
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU), // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address
- 0x00181111, // regData
- 0x00FF7777, // regMask
- }
- },
-// F3x7C - Free List Buffer Count
-// bits[4:0] Xbar2SriFreeListCBC = 20
-// bits[11:8] Sri2XbarFreeXreqCBC = 9
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 9
-// bits[22:20] Sri2XbarFreeRspDBC = 0
-// bits[30:28] Xbar2SriFreeListCBInc = 0
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Cx // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM), // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address
- 0x00090914, // regData
- 0x707FFF1F, // regMask
- }
- },
-// F3x7C - Free List Buffer Count
-// bits[4:0] Xbar2SriFreeListCBC = 24
-// bits[11:8] Sri2XbarFreeXreqCBC = 9
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 9
-// bits[22:20] Sri2XbarFreeRspDBC = 0
-// bits[30:28] Xbar2SriFreeListCBInc = 0
- {
- CoreCountsPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Dx // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM), // platformFeatures
- {
- PERFORMANCE_PROFILE_ALL,
- (CORE_RANGE_0 (COUNT_RANGE_LOW, 4) | COUNT_RANGE_NONE), // 4 or fewer cores.
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address
- 0x00090A18, // regData
- 0x007FFF1F, // regMask
- }
- },
-// F3x7C - Free List Buffer Count
-// bits[4:0] Xbar2SriFreeListCBC = 22
-// bits[11:8] Sri2XbarFreeXreqCBC = 9
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 9
-// bits[22:20] Sri2XbarFreeRspDBC = 0
-// bits[30:28] Xbar2SriFreeListCBInc = 0
- {
- CoreCountsPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Dx // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM), // platformFeatures
- {
- PERFORMANCE_PROFILE_ALL,
- (CORE_RANGE_0 (5, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE), // greater than 4, ex. 6.
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address
- 0x00090A16, // regData
- 0x707FFF1F, // regMask
- }
- },
-// F3x7C - Free List Buffer Count
-// bits[4:0] Xbar2SriFreeListCBC = 23
-// bits[11:8] Sri2XbarFreeXreqCBC = 9
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 9
-// bits[22:20] Sri2XbarFreeRspDBC = 0
-// bits[30:28] Xbar2SriFreeListCBInc = 0
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Cx // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU), // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address
- 0x00090917, // regData
- 0x707FFF1F, // regMask
- }
- },
-// F3x7C - Free List Buffer Count
-// bits[4:0] Xbar2SriFreeListCBC = 23
-// bits[11:8] Sri2XbarFreeXreqCBC = 9
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 9
-// bits[22:20] Sri2XbarFreeRspDBC = 0
-// bits[30:28] Xbar2SriFreeListCBInc = 0
- {
- CoreCountsPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Dx // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU), // platformFeatures
- {
- PERFORMANCE_PROFILE_ALL,
- (CORE_RANGE_0 (COUNT_RANGE_LOW, 4) | COUNT_RANGE_NONE), // 4 or fewer cores.
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address
- 0x00090917, // regData
- 0x007FFF1F, // regMask
- }
- },
-// F3x7C - Free List Buffer Count
-// bits[4:0] Xbar2SriFreeListCBC = 21
-// bits[11:8] Sri2XbarFreeXreqCBC = 9
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 9
-// bits[22:20] Sri2XbarFreeRspDBC = 0
-// bits[30:28] Xbar2SriFreeListCBInc = 0
- {
- CoreCountsPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Dx // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU), // platformFeatures
- {
- PERFORMANCE_PROFILE_ALL,
- (CORE_RANGE_0 (5, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE), // greater than 4, ex. 6.
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address
- 0x00090915, // regData
- 0x707FFF1F, // regMask
- }
- },
-// F3x140 - SRI_to_XCS Token Count
-// bits[1:0] UpReqTok = 1
-// bits[3:2] DnReqTok = 1
-// bits[5:4] UpPreqTokC = 1
-// bits[7:6] DnPreqTok = 1
-// bits[9:8] UpRspTok = 3
-// bits[11:10] DnRspTok = 1
-// bits[13:12] IsocReqTok = 0
-// bits[15:14] IsocPreqTok = 0
-// bits[17:16] IsocRspTok = 0
-// bits[23:20] FreeTok = A
- {
- ProcCountsPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM), // platformFeatures
- {
- PERFORMANCE_PROFILE_ALL,
- (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 1) | PROCESSOR_RANGE_1 (3, COUNT_RANGE_HIGH)), // anything but two.
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
- 0x00A00755, // regData
- 0x00F3FFFF, // regMask
- }
- },
-// F3x140 - SRI_to_XCS Token Count
-// bits[1:0] UpReqTok = 1
-// bits[3:2] DnReqTok = 1
-// bits[5:4] UpPreqTokC = 1
-// bits[7:6] DnPreqTok = 1
-// bits[9:8] UpRspTok = 3
-// bits[11:10] DnRspTok = 1
-// bits[13:12] IsocReqTok = 0
-// bits[15:14] IsocPreqTok = 0
-// bits[17:16] IsocRspTok = 0
-// bits[23:20] FreeTok = 8
- {
- ProcCountsPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM), // platformFeatures
- {
- PERFORMANCE_PROFILE_ALL,
- (PROCESSOR_RANGE_0 (2, 2) | COUNT_RANGE_NONE), // exactly two.
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
- 0x00800755, // regData
- 0x00F3FFFF, // regMask
- }
- },
-// F3x140 - SRI_to_XCS Token Count
-// bits[1:0] UpReqTok = 1
-// bits[3:2] DnReqTok = 1
-// bits[5:4] UpPreqTokC = 1
-// bits[7:6] DnPreqTok = 1
-// bits[9:8] UpRspTok = 3
-// bits[11:10] DnRspTok = 1
-// bits[13:12] IsocReqTok = 1
-// bits[15:14] IsocPreqTok = 0
-// bits[17:16] IsocRspTok = 1
-// bits[23:20] FreeTok = 10
- {
- TokenPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU), // platformFeatures
- {
- PERFORMANCE_PROFILE_ALL,
- (DEGREE_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE), // 2 Socket, half populated.
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
- 0x00A11755, // regData
- 0x00F3FFFF, // regMask
- }
- },
-// F3x140 - SRI_to_XCS Token Count
-// bits[1:0] UpReqTok = 1
-// bits[3:2] DnReqTok = 1
-// bits[5:4] UpPreqTokC = 1
-// bits[7:6] DnPreqTok = 1
-// bits[9:8] UpRspTok = 3
-// bits[11:10] DnRspTok = 1
-// bits[13:12] IsocReqTok = 1
-// bits[15:14] IsocPreqTok = 0
-// bits[17:16] IsocRspTok = 1
-// bits[23:20] FreeTok = 9
- {
- TokenPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU), // platformFeatures
- {
- PERFORMANCE_PROBEFILTER,
- (DEGREE_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE), // 2 Socket, half populated.
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
- 0x00911755, // regData
- 0x00F3FFFF, // regMask
- }
- },
-// F3x140 - SRI_to_XCS Token Count
-// bits[1:0] UpReqTok = 1
-// bits[3:2] DnReqTok = 1
-// bits[5:4] UpPreqTokC = 1
-// bits[7:6] DnPreqTok = 1
-// bits[9:8] UpRspTok = 3
-// bits[11:10] DnRspTok = 1
-// bits[13:12] IsocReqTok = 1
-// bits[15:14] IsocPreqTok = 0
-// bits[17:16] IsocRspTok = 1
-// bits[23:20] FreeTok = 5
- {
- TokenPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU), // platformFeatures
- {
- PERFORMANCE_PROFILE_ALL,
- (DEGREE_RANGE_0 (3, 3) | COUNT_RANGE_NONE), // 2 Socket, fully populated.
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
- 0x00511755, // regData
- 0x00F3FFFF, // regMask
- }
- },
-// F3x140 - SRI_to_XCS Token Count
-// bits[1:0] UpReqTok = 1
-// bits[3:2] DnReqTok = 1
-// bits[5:4] UpPreqTokC = 1
-// bits[7:6] DnPreqTok = 1
-// bits[9:8] UpRspTok = 1
-// bits[11:10] DnRspTok = 1
-// bits[13:12] IsocReqTok = 1
-// bits[15:14] IsocPreqTok = 0
-// bits[17:16] IsocRspTok = 1
-// bits[23:20] FreeTok = 7
- {
- TokenPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU), // platformFeatures
- {
- PERFORMANCE_PROBEFILTER,
- (DEGREE_RANGE_0 (3, 3) | COUNT_RANGE_NONE), // 2 Socket, fully populated.
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
- 0x00711555, // regData
- 0x00F3FFFF, // regMask
- }
- },
-// F3x140 - SRI_to_XCS Token Count
-// bits[1:0] UpReqTok = 1
-// bits[3:2] DnReqTok = 1
-// bits[5:4] UpPreqTokC = 1
-// bits[7:6] DnPreqTok = 1
-// bits[9:8] UpRspTok = 3
-// bits[11:10] DnRspTok = 1
-// bits[13:12] IsocReqTok = 1
-// bits[15:14] IsocPreqTok = ]
-// bits[17:16] IsocRspTok = 1
-// bits[23:20] FreeTok = 8
- {
- TokenPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU), // platformFeatures
- {
- PERFORMANCE_PROFILE_ALL,
- (DEGREE_RANGE_0 (2, 2) | COUNT_RANGE_NONE), // 4 Socket, half populated.
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
- 0x00811755, // regData
- 0x00F3FFFF, // regMask
- }
- },
-// F3x140 - SRI_to_XCS Token Count
-// bits[1:0] UpReqTok = 1
-// bits[3:2] DnReqTok = 1
-// bits[5:4] UpPreqTokC = 1
-// bits[7:6] DnPreqTok = 1
-// bits[9:8] UpRspTok = 3
-// bits[11:10] DnRspTok = 1
-// bits[13:12] IsocReqTok = 1
-// bits[15:14] IsocPreqTok = 0
-// bits[17:16] IsocRspTok = 2
-// bits[23:20] FreeTok = 2
- {
- TokenPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU), // platformFeatures
- {
- PERFORMANCE_PROFILE_ALL,
- (DEGREE_RANGE_0 (4, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE), // 4 Socket, fully populated.
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
- 0x00211755, // regData
- 0x00F3FFFF, // regMask
- }
- },
-// F3x140 - SRI_to_XCS Token Count
-// bits[1:0] UpReqTok = 1
-// bits[3:2] DnReqTok = 1
-// bits[5:4] UpPreqTokC = 1
-// bits[7:6] DnPreqTok = 1
-// bits[9:8] UpRspTok = 1
-// bits[11:10] DnRspTok = 1
-// bits[13:12] IsocReqTok = 1
-// bits[15:14] IsocPreqTok = 0
-// bits[17:16] IsocRspTok = 1
-// bits[23:20] FreeTok = 6
- {
- TokenPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU), // platformFeatures
- {
- PERFORMANCE_PROBEFILTER,
- (DEGREE_RANGE_0 (4, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE), // 4 Socket, fully populated.
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
- 0x00611555, // regData
- 0x00F3FFFF, // regMask
- }
- },
-// F3x140 - SRI_to_XCS Token Count
-// bits[1:0] UpReqTok = 2
-// bits[3:2] DnReqTok = 1
-// bits[5:4] UpPreqTokC = 1
-// bits[7:6] DnPreqTok = 1
-// bits[9:8] UpRspTok = 3
-// bits[11:10] DnRspTok = 1
-// bits[13:12] IsocReqTok = 0
-// bits[15:14] IsocPreqTok = 0
-// bits[17:16] IsocRspTok = 0
-// bits[23:20] FreeTok = 8
- {
- TokenPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C32_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM), // platformFeatures
- {
- PERFORMANCE_PROFILE_ALL,
- (COUNT_RANGE_ALL | COUNT_RANGE_NONE),
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
- 0x00800756, // regData
- 0x00F3FFFF, // regMask
- }
- },
-// F3x140 - SRI_to_XCS Token Count
-// bits[1:0] UpReqTok = 2
-// bits[3:2] DnReqTok = 1
-// bits[5:4] UpPreqTokC = 1
-// bits[7:6] DnPreqTok = 1
-// bits[9:8] UpRspTok = 3
-// bits[11:10] DnRspTok = 1
-// bits[13:12] IsocReqTok = 1
-// bits[15:14] IsocPreqTok = 0
-// bits[17:16] IsocRspTok = 1
-// bits[23:20] FreeTok = 8
- {
- TokenPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C32_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU), // platformFeatures
- {
- PERFORMANCE_PROFILE_ALL,
- (COUNT_RANGE_ALL | COUNT_RANGE_NONE),
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
- 0x00811756, // regData
- 0x00F3FFFF, // regMask
- }
- },
-// F3x144 - MCT to XCS Token Count
-// bits[3:0] RspTok = 3
-// bits[7:4] ProbeTok = 3
- {
- ProfileFixup,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM), // platformFeatures
- {
- PERFORMANCE_PROFILE_ALL,
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
- 0x00000033, // regData
- 0x000000FF, // regMask
- }
- },
-// F3x144 - MCT to XCS Token Count
-// bits[3:0] RspTok = 5
-// bits[7:4] ProbeTok = 1
- {
- ProfileFixup,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM), // platformFeatures
- {
- PERFORMANCE_PROBEFILTER, // Features
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
- 0x00000015, // regData
- 0x000000FF, // regMask
- }
- },
-// F3x144 - MCT to XCS Token Count
-// All non probe filter configs
-// bits[3:0] RspTok = 3
-// bits[7:4] ProbeTok = 3
- {
- ProfileFixup,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU), // platformFeatures
- {
- PERFORMANCE_PROFILE_ALL,
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
- 0x00000033, // regData
- 0x000000FF, // regMask
- }
- },
-// F3x144 - MCT to XCS Token Count
-// bits[3:0] RspTok = 4
-// bits[7:4] ProbeTok = 1
- {
- TokenPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU), // platformFeatures
- {
- PERFORMANCE_PROBEFILTER, // Features
- (DEGREE_RANGE_0 (COUNT_RANGE_LOW, 1) | DEGREE_RANGE_1 (4, COUNT_RANGE_HIGH)), // 2 Socket, half populated, or 4 Socket, fully populated.
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
- 0x00000014, // regData
- 0x000000FF, // regMask
- }
- },
-// F3x144 - MCT to XCS Token Count
-// bits[3:0] RspTok = 5
-// bits[7:4] ProbeTok = 1
- {
- TokenPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU), // platformFeatures
- {
- PERFORMANCE_PROBEFILTER, // Features
- (DEGREE_RANGE_0 (2, 2) | DEGREE_RANGE_1 (3, 3)), // 2 Socket, fully populated, or 4 Socket, half populated.
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
- 0x00000015, // regData
- 0x000000FF, // regMask
- }
- },
-// F3x144 - MCT to XCS Token Count
-// bits[3:0] RspTok = 5
-// bits[7:4] ProbeTok = 1
- {
- ProfileFixup,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C32_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU), // platformFeatures
- {
- PERFORMANCE_PROBEFILTER,
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
- 0x00000015, // regData
- 0x000000FF, // regMask
- }
- },
-// F3x148 - Link to XCS Token Count
-// bits[1:0] ReqTok0 = 2
-// bits[3:2] PReqTok0 = 2
-// bits[5:4] RspTok0 = 2
-// bits[7:6] ProbeTok0 = 2
-// bits[9:8] IsocReqTok0 = 0
-// bits[11:10] IsocPreqTok0 = 0
-// bits[13:12] IsocRspTok0 = 0
-// bits[15:14] FreeTok[1:0] = 0
-// bits[17:16] ReqTok1 = 0
-// bits[19:18] PReqTok1 = 0
-// bits[21:20] RspTok1 = 0
-// bits[23:22] ProbeTok1= 0
-// bits[24] IsocReqTok1 = 0
-// bits[25] IsocPreqTok1 = 0
-// bits[28] IsocRspTok1 = 0
-// bits[31:30] FreeTok[3:2] = 0
- {
- HtTokenPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM), // platformFeatures
- {
- (COUNT_RANGE_ALL | COUNT_RANGE_NONE),
- PERFORMANCE_PROFILE_ALL,
- HT_HOST_FEAT_GANGED,
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
- 0x000000AA, // regData
- 0xD5FFFFFF, // regMask
- }
- },
-// F3x148 - Link to XCS Token Count
-// bits[1:0] ReqTok0 = 1
-// bits[3:2] PReqTok0 = 1
-// bits[5:4] RspTok0 = 1
-// bits[7:6] ProbeTok0 = 1
-// bits[9:8] IsocReqTok0 = 1
-// bits[11:10] IsocPreqTok0 = 0
-// bits[13:12] IsocRspTok0 = 0
-// bits[15:14] FreeTok[1:0] = 0
-// bits[17:16] ReqTok1 = 1
-// bits[19:18] PReqTok1 = 1
-// bits[21:20] RspTok1 = 1
-// bits[23:22] ProbeTok1= 1
-// bits[24] IsocReqTok1 = 0
-// bits[25] IsocPreqTok1 = 0
-// bits[28] IsocRspTok1 = 0
-// bits[31:30] FreeTok[3:2] = 0
- {
- HtTokenPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM), // platformFeatures
- {
- (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE),
- PERFORMANCE_PROFILE_ALL,
- HT_HOST_FEAT_UNGANGED,
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
- 0x00550055, // regData
- 0xD5FFFFFF, // regMask
- }
- },
-// F3x148 - Link to XCS Token Count
-// bits[1:0] ReqTok0 = 1
-// bits[3:2] PReqTok0 = 1
-// bits[5:4] RspTok0 = 1
-// bits[7:6] ProbeTok0 = 1
-// bits[9:8] IsocReqTok0 = 1
-// bits[11:10] IsocPreqTok0 = 0
-// bits[13:12] IsocRspTok0 = 0
-// bits[15:14] FreeTok[1:0] = 0
-// bits[17:16] ReqTok1 = 1
-// bits[19:18] PReqTok1 = 1
-// bits[21:20] RspTok1 = 1
-// bits[23:22] ProbeTok1= 1
-// bits[24] IsocReqTok1 = 0
-// bits[25] IsocPreqTok1 = 0
-// bits[28] IsocRspTok1 = 0
-// bits[31:30] FreeTok[3:2] = 0
- {
- HtTokenPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM), // platformFeatures
- {
- (PROCESSOR_RANGE_0 (3, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),
- PERFORMANCE_PROFILE_ALL,
- HT_HOST_FEAT_UNGANGED,
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
- 0x00550055, // regData
- 0xD5FFFFFF, // regMask
- }
- },
-// F3x148 - Link to XCS Token Count
-// bits[1:0] ReqTok0 = 1
-// bits[3:2] PReqTok0 = 1
-// bits[5:4] RspTok0 = 1
-// bits[7:6] ProbeTok0 = 1
-// bits[9:8] IsocReqTok0 = 0
-// bits[11:10] IsocPreqTok0 = 0
-// bits[13:12] IsocRspTok0 = 0
-// bits[15:14] FreeTok[1:0] = 1
-// bits[17:16] ReqTok1 = 1
-// bits[19:18] PReqTok1 = 1
-// bits[21:20] RspTok1 = 1
-// bits[23:22] ProbeTok1= 1
-// bits[24] IsocReqTok1 = 0
-// bits[25] IsocPreqTok1 = 0
-// bits[28] IsocRspTok1 = 0
-// bits[31:30] FreeTok[3:2] = 0
- {
- HtTokenPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM), // platformFeatures
- {
- (PROCESSOR_RANGE_0 (2, 2) | COUNT_RANGE_NONE),
- PERFORMANCE_PROFILE_ALL,
- HT_HOST_FEAT_UNGANGED,
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
- 0x00554055, // regData
- 0xD5FFFFFF, // regMask
- }
- },
-// F3x148 - Link to XCS Token Count
-// bits[1:0] ReqTok0 = 2
-// bits[3:2] PReqTok0 = 2
-// bits[5:4] RspTok0 = 2
-// bits[7:6] ProbeTok0 = 0
-// bits[9:8] IsocReqTok0 = 1
-// bits[11:10] IsocPreqTok0 = 0
-// bits[13:12] IsocRspTok0 = 0
-// bits[15:14] FreeTok[1:0] = 0
-// bits[17:16] ReqTok1 = 0
-// bits[19:18] PReqTok1 = 0
-// bits[21:20] RspTok1 = 0
-// bits[23:22] ProbeTok1= 0
-// bits[24] IsocReqTok1 = 0
-// bits[25] IsocPreqTok1 = 0
-// bits[28] IsocRspTok1 = 0
-// bits[31:30] FreeTok[3:2] = 0
- {
- HtTokenPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU), // platformFeatures
- {
- (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 2) | COUNT_RANGE_NONE),
- PERFORMANCE_PROFILE_ALL,
- HT_HOST_FEAT_NONCOHERENT,
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
- 0x0000012A, // regData
- 0xD5FFFFFF, // regMask
- }
- },
-// F3x148 - Link to XCS Token Count
-// bits[1:0] ReqTok0 = 2
-// bits[3:2] PReqTok0 = 1
-// bits[5:4] RspTok0 = 2
-// bits[7:6] ProbeTok0 = 2
-// bits[9:8] IsocReqTok0 = 1
-// bits[11:10] IsocPreqTok0 = 0
-// bits[13:12] IsocRspTok0 = 0
-// bits[15:14] FreeTok[1:0] = 0
-// bits[17:16] ReqTok1 = 0
-// bits[19:18] PReqTok1 = 0
-// bits[21:20] RspTok1 = 0
-// bits[23:22] ProbeTok1= 0
-// bits[24] IsocReqTok1 = 0
-// bits[25] IsocPreqTok1 = 0
-// bits[28] IsocRspTok1 = 0
-// bits[31:30] FreeTok[3:2] = 0
- {
- HtTokenPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU), // platformFeatures
- {
- (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 2) | COUNT_RANGE_NONE),
- PERFORMANCE_PROFILE_ALL,
- (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_GANGED),
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
- 0x000001A6, // regData
- 0xD5FFFFFF, // regMask
- }
- },
-// F3x148 - Link to XCS Token Count
-// bits[1:0] ReqTok0 = 2
-// bits[3:2] PReqTok0 = 2
-// bits[5:4] RspTok0 = 2
-// bits[7:6] ProbeTok0 = 1
-// bits[9:8] IsocReqTok0 = 1
-// bits[11:10] IsocPreqTok0 = 0
-// bits[13:12] IsocRspTok0 = 0
-// bits[15:14] FreeTok[1:0] = 0
-// bits[17:16] ReqTok1 = 0
-// bits[19:18] PReqTok1 = 0
-// bits[21:20] RspTok1 = 0
-// bits[23:22] ProbeTok1= 0
-// bits[24] IsocReqTok1 = 0
-// bits[25] IsocPreqTok1 = 0
-// bits[28] IsocRspTok1 = 0
-// bits[31:30] FreeTok[3:2] = 0
- {
- HtTokenPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU), // platformFeatures
- {
- (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 2) | COUNT_RANGE_NONE),
- PERFORMANCE_PROBEFILTER,
- (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_GANGED),
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
- 0x0000016A, // regData
- 0xD5FFFFFF, // regMask
- }
- },
-// F3x148 - Link to XCS Token Count
-// bits[1:0] ReqTok0 = 1
-// bits[3:2] PReqTok0 = 1
-// bits[5:4] RspTok0 = 1
-// bits[7:6] ProbeTok0 = 1
-// bits[9:8] IsocReqTok0 = 1
-// bits[11:10] IsocPreqTok0 = 1
-// bits[13:12] IsocRspTok0 = 0
-// bits[15:14] FreeTok[1:0] = 0
-// bits[17:16] ReqTok1 = 1
-// bits[19:18] PReqTok1 = 1
-// bits[21:20] RspTok1 = 1
-// bits[23:22] ProbeTok1= 1
-// bits[24] IsocReqTok1 = 1
-// bits[25] IsocPreqTok1 = 0
-// bits[28] IsocRspTok1 = 0
-// bits[31:30] FreeTok[3:2] = 0
- {
- HtTokenPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU), // platformFeatures
- {
- (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE),
- PERFORMANCE_PROFILE_ALL,
- (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_UNGANGED),
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
- 0x01550155, // regData
- 0xD5FFFFFF, // regMask
- }
- },
-// F3x148 - Link to XCS Token Count
-// bits[1:0] ReqTok0 = 1
-// bits[3:2] PReqTok0 = 1
-// bits[5:4] RspTok0 = 1
-// bits[7:6] ProbeTok0 = 1
-// bits[9:8] IsocReqTok0 = 1
-// bits[11:10] IsocPreqTok0 = 1
-// bits[13:12] IsocRspTok0 = 0
-// bits[15:14] FreeTok[1:0] = 0
-// bits[17:16] ReqTok1 = 1
-// bits[19:18] PReqTok1 = 1
-// bits[21:20] RspTok1 = 1
-// bits[23:22] ProbeTok1= 1
-// bits[24] IsocReqTok1 = 1
-// bits[25] IsocPreqTok1 = 0
-// bits[28] IsocRspTok1 = 0
-// bits[31:30] FreeTok[3:2] = 0
- {
- HtTokenPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU), // platformFeatures
- {
- (PROCESSOR_RANGE_0 (3, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),
- PERFORMANCE_PROFILE_ALL,
- (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_UNGANGED),
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
- 0x01550155, // regData
- 0xD5FFFFFF, // regMask
- }
- },
-// F3x148 - Link to XCS Token Count
-// bits[1:0] ReqTok0 = 2
-// bits[3:2] PReqTok0 = 2
-// bits[5:4] RspTok0 = 2
-// bits[7:6] ProbeTok0 = 0
-// bits[9:8] IsocReqTok0 = 2
-// bits[11:10] IsocPreqTok0 = 0
-// bits[13:12] IsocRspTok0 = 0
-// bits[15:14] FreeTok[1:0] = 0
-// bits[17:16] ReqTok1 = 0
-// bits[19:18] PReqTok1 = 0
-// bits[21:20] RspTok1 = 0
-// bits[23:22] ProbeTok1= 0
-// bits[24] IsocReqTok1 = 0
-// bits[25] IsocPreqTok1 = 0
-// bits[28] IsocRspTok1 = 0
-// bits[31:30] FreeTok[3:2] = 0
- {
- HtTokenPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU), // platformFeatures
- {
- (PROCESSOR_RANGE_0 (3, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),
- PERFORMANCE_PROFILE_ALL,
- HT_HOST_FEAT_NONCOHERENT,
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
- 0x0000022A, // regData
- 0xD5FFFFFF, // regMask
- }
- },
-// F3x148 - Link to XCS Token Count
-// bits[1:0] ReqTok0 = 1
-// bits[3:2] PReqTok0 = 1
-// bits[5:4] RspTok0 = 1
-// bits[7:6] ProbeTok0 = 1
-// bits[9:8] IsocReqTok0 = 1
-// bits[11:10] IsocPreqTok0 = 0
-// bits[13:12] IsocRspTok0 = 0
-// bits[15:14] FreeTok[1:0] = 1
-// bits[17:16] ReqTok1 = 1
-// bits[19:18] PReqTok1 = 1
-// bits[21:20] RspTok1 = 1
-// bits[23:22] ProbeTok1= 1
-// bits[24] IsocReqTok1 = 1
-// bits[25] IsocPreqTok1 = 0
-// bits[28] IsocRspTok1 = 0
-// bits[31:30] FreeTok[3:2] = 0
- {
- HtTokenPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU), // platformFeatures
- {
- (PROCESSOR_RANGE_0 (2, 2) | COUNT_RANGE_NONE),
- PERFORMANCE_PROFILE_ALL,
- (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_UNGANGED),
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
- 0x01554155, // regData
- 0xD5FFFFFF, // regMask
- }
- },
-// F3x148 - Link to XCS Token Count
-// bits[1:0] ReqTok0 = 2
-// bits[3:2] PReqTok0 = 1
-// bits[5:4] RspTok0 = 2
-// bits[7:6] ProbeTok0 = 2
-// bits[9:8] IsocReqTok0 = 1
-// bits[11:10] IsocPreqTok0 = 0
-// bits[13:12] IsocRspTok0 = 0
-// bits[15:14] FreeTok[1:0] = 0
-// bits[17:16] ReqTok1 = 0
-// bits[19:18] PReqTok1 = 0
-// bits[21:20] RspTok1 = 0
-// bits[23:22] ProbeTok1= 0
-// bits[24] IsocReqTok1 = 0
-// bits[25] IsocPreqTok1 = 0
-// bits[28] IsocRspTok1 = 0
-// bits[31:30] FreeTok[3:2] = 0
- {
- HtTokenPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU), // platformFeatures
- {
- (PROCESSOR_RANGE_0 (3, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),
- PERFORMANCE_PROFILE_ALL,
- (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_GANGED),
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
- 0x000001A6, // regData
- 0xD5FFFFFF, // regMask
- }
- },
-// F3x148 - Link to XCS Token Count
-// bits[1:0] ReqTok0 = 2
-// bits[3:2] PReqTok0 = 1
-// bits[5:4] RspTok0 =1
-// bits[7:6] ProbeTok0 = 2
-// bits[9:8] IsocReqTok0 = 1
-// bits[11:10] IsocPreqTok0 = 0
-// bits[13:12] IsocRspTok0 = 0
-// bits[15:14] FreeTok[1:0] = 0
-// bits[17:16] ReqTok1 = 0
-// bits[19:18] PReqTok1 = 0
-// bits[21:20] RspTok1 = 0
-// bits[23:22] ProbeTok1= 0
-// bits[24] IsocReqTok1 = 0
-// bits[25] IsocPreqTok1 = 0
-// bits[28] IsocRspTok1 = 0
-// bits[31:30] FreeTok[3:2] = 0
- {
- HtTokenPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU), // platformFeatures
- {
- (PROCESSOR_RANGE_0 (3, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),
- PERFORMANCE_PROBEFILTER,
- (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_GANGED),
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
- 0x00000196, // regData
- 0xD5FFFFFF, // regMask
- }
- },
-// F3x148 - Link to XCS Token Count
-// bits[1:0] ReqTok0 = 2
-// bits[3:2] PReqTok0 = 2
-// bits[5:4] RspTok0 = 2
-// bits[7:6] ProbeTok0 = 2
-// bits[9:8] IsocReqTok0 = 0
-// bits[11:10] IsocPreqTok0 = 0
-// bits[13:12] IsocRspTok0 = 0
-// bits[15:14] FreeTok[1:0] = 3
-// bits[17:16] ReqTok1 = 0
-// bits[19:18] PReqTok1 = 0
-// bits[21:20] RspTok1 = 0
-// bits[23:22] ProbeTok1= 0
-// bits[24] IsocReqTok1 = 0
-// bits[25] IsocPreqTok1 = 0
-// bits[28] IsocRspTok1 = 0
-// bits[31:30] FreeTok[3:2] = 0
- {
- HtTokenPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C32_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM), // platformFeatures
- {
- (COUNT_RANGE_ALL | COUNT_RANGE_NONE),
- PERFORMANCE_PROFILE_ALL,
- HT_HOST_FEATURES_ALL,
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
- 0x0000C0AA, // regData
- 0xD5FFFFFF, // regMask
- }
- },
-// F3x148 - Link to XCS Token Count
-// bits[1:0] ReqTok0 = 2
-// bits[3:2] PReqTok0 = 2
-// bits[5:4] RspTok0 = 2
-// bits[7:6] ProbeTok0 = 0
-// bits[9:8] IsocReqTok0 = 1
-// bits[11:10] IsocPreqTok0 = 0
-// bits[13:12] IsocRspTok0 = 0
-// bits[15:14] FreeTok[1:0] = 2
-// bits[17:16] ReqTok1 = 0
-// bits[19:18] PReqTok1 = 0
-// bits[21:20] RspTok1 = 0
-// bits[23:22] ProbeTok1= 0
-// bits[24] IsocReqTok1 = 0
-// bits[25] IsocPreqTok1 = 0
-// bits[28] IsocRspTok1 = 0
-// bits[31:30] FreeTok[3:2] = 0
- {
- HtTokenPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C32_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU), // platformFeatures
- {
- (COUNT_RANGE_ALL | COUNT_RANGE_NONE),
- PERFORMANCE_PROFILE_ALL,
- HT_HOST_FEAT_NONCOHERENT,
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
- 0x0000812A, // regData
- 0xD5FFFFFF, // regMask
- }
- },
-// F3x148 - Link to XCS Token Count
-// bits[1:0] ReqTok0 = 2
-// bits[3:2] PReqTok0 = 2
-// bits[5:4] RspTok0 = 2
-// bits[7:6] ProbeTok0 = 2
-// bits[9:8] IsocReqTok0 = 1
-// bits[11:10] IsocPreqTok0 = 0
-// bits[13:12] IsocRspTok0 = 0
-// bits[15:14] FreeTok[1:0] = 2
-// bits[17:16] ReqTok1 = 0
-// bits[19:18] PReqTok1 = 0
-// bits[21:20] RspTok1 = 0
-// bits[23:22] ProbeTok1= 0
-// bits[24] IsocReqTok1 = 0
-// bits[25] IsocPreqTok1 = 0
-// bits[28] IsocRspTok1 = 0
-// bits[31:30] FreeTok[3:2] = 0
- {
- HtTokenPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C32_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU), // platformFeatures
- {
- (COUNT_RANGE_ALL | COUNT_RANGE_NONE),
- PERFORMANCE_PROFILE_ALL,
- HT_HOST_FEAT_COHERENT,
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
- 0x000081AA, // regData
- 0xD5FFFFFF, // regMask
- }
- },
-};
-
-CONST REGISTER_TABLE ROMDATA F10MultiLinkPciRegisterTable = {
- PrimaryCores,
- (sizeof (F10MultiLinkPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
- F10MultiLinkPciRegisters,
-};
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10PackageType.h b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10PackageType.h
deleted file mode 100644
index 13d6876..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10PackageType.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Package Type Definitions
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F10
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _F10_PACKAGE_TYPE_H_
-#define _F10_PACKAGE_TYPE_H_
-
-
-/*---------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *---------------------------------------------------------------------------------------
- */
-
-// Below equates are defined to cooperate with LibAmdGetPackageType.
-#define PACKAGE_TYPE_FR2_FR5_FR6 (1 << 0)
-#define PACKAGE_TYPE_AM2R2_AM3 (1 << 1)
-#define PACKAGE_TYPE_S1G3_S1G4 (1 << 2)
-#define PACKAGE_TYPE_G34 (1 << 3)
-#define PACKAGE_TYPE_ASB2 (1 << 4)
-#define PACKAGE_TYPE_C32 (1 << 5)
-
-#define PACKAGE_TYPE_FR2 PACKAGE_TYPE_FR2_FR5_FR6
-#define PACKAGE_TYPE_FR5 PACKAGE_TYPE_FR2_FR5_FR6
-#define PACKAGE_TYPE_FR6 PACKAGE_TYPE_FR2_FR5_FR6
-#define PACKAGE_TYPE_S1G3 PACKAGE_TYPE_S1G3_S1G4
-#define PACKAGE_TYPE_S1G4 PACKAGE_TYPE_S1G3_S1G4
-
-/*---------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *---------------------------------------------------------------------------------------
- */
-
-#endif // _F10_PACKAGE_TYPE_H_
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c
deleted file mode 100644
index d45b71c..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c
+++ /dev/null
@@ -1,182 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Asymmetric Boost Initialization
- *
- * Performs the "BIOS Configuration for Asymmetric Boost" as
- * described in the BKDG.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "cpuRegisters.h"
-#include "cpuApicUtilities.h"
-#include "cpuServices.h"
-#include "GeneralServices.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuF10PowerMgmt.h"
-#include "F10PmAsymBoostInit.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_F10PMASYMBOOSTINIT_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-VOID
-STATIC
-SetAsymBoost (
- IN VOID *AsymBoostRegister,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family 10h core 0 entry point for performing the "Asymmetric Boost
- * Configuration" algorithm.
- *
- * The algorithm is as follows:
- * // Determine whether the processor support boost
- * if (CPUID CPUID Fn8000_0007[CPB]==1)&& CPUID Fn8000_0008[NC]==5) {
- * Core0 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore0]
- * Core1 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore1]
- * Core2 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore2]
- * Core3 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore3]
- * Core4 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore4]
- * Core5 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore5]
- * }
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] CpuEarlyParamsPtr Service related parameters (unused).
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-F10PmAsymBoostInit (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AP_TASK TaskPtr;
- UINT32 Core;
- UINT32 Socket;
- UINT32 Module;
- UINT32 PciRegister;
- PCI_ADDR PciAddress;
- CPUID_DATA CpuidData;
- AGESA_STATUS IgnoredSts;
-
- // Check if CPB is supported. if yes, skip boosted p-state.
- LibAmdCpuidRead (AMD_CPUID_APM, &CpuidData, StdHeader);
- if (((CpuidData.EDX_Reg & 0x00000200) >> 9) == 1) {
- LibAmdCpuidRead (CPUID_LONG_MODE_ADDR, &CpuidData, StdHeader);
- if ((CpuidData.ECX_Reg & 0x000000FF) == 5) {
- // get the local node ID
- IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
- GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
- // Read F3x10C [Boost Offset]
- PciAddress.AddressValue = F3x10C_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
-
- TaskPtr.FuncAddress.PfApTaskI = SetAsymBoost;
- TaskPtr.ExeFlags = WAIT_FOR_CORE;
- TaskPtr.DataTransfer.DataTransferFlags = 0;
- TaskPtr.DataTransfer.DataSizeInDwords = 1;
- TaskPtr.DataTransfer.DataPtr = &PciRegister;
- ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
- }
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Set Asymmetric Boost.
- *
- * This function set Asymmetric Boost.
- *
- * @param[in] AsymBoostRegister Contains the value of Asymmetric Boost register
- * @param[in] StdHeader Config handle for library and services
- *
- */
-VOID
-STATIC
-SetAsymBoost (
- IN VOID *AsymBoostRegister,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 ControlByte;
- UINT32 Core;
- UINT32 Ignored;
- UINT64 MsrValue;
- AGESA_STATUS IgnoredSts;
-
- IdentifyCore (StdHeader, &Ignored, &Ignored, &Core, &IgnoredSts);
- ControlByte = (UINT8) ((Core & 0xFF) * 2);
- LibAmdMsrRead (MSR_PSTATE_0, &MsrValue, StdHeader);
- // Bits 5:0
- ((PSTATE_MSR *) &MsrValue)->CpuFid += ((*(UINT32*) AsymBoostRegister >> ControlByte) & 0x3);
- LibAmdMsrWrite (MSR_PSTATE_0, &MsrValue, StdHeader);
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10PmAsymBoostInit.h b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10PmAsymBoostInit.h
deleted file mode 100644
index 38166dc..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10PmAsymBoostInit.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Asymmetric Boost Initialization
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F10
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPU_F10_ASYM_BOOST_H_
-#define _CPU_F10_ASYM_BOOST_H_
-
-
-/*---------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *---------------------------------------------------------------------------------------
- */
-VOID
-F10PmAsymBoostInit (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif // _CPU_F10_ASYM_BOOST_H_
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c
deleted file mode 100644
index 3c959de..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c
+++ /dev/null
@@ -1,246 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Dual-plane Only Support
- *
- * Performs the "BIOS Configuration for Dual-plane Only Support" as
- * described in the BKDG.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "cpuRegisters.h"
-#include "cpuApicUtilities.h"
-#include "cpuServices.h"
-#include "GeneralServices.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuF10PowerMgmt.h"
-#include "F10PmAsymBoostInit.h"
-#include "F10PackageType.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_F10PMDUALPLANEONLYSUPPORT_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-UINT32
-STATIC
-SetPstateMSR (
- IN VOID *CPB,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family 10h core 0 entry point for performing the "Dual-plane Only Support" algorithm.
- *
- * The algorithm is as follows:
- * // Determine whether algorithm applies to this processor
- * if (CPUID Fn8000_0001_EBX[PkgType] == 0001b && (revision C or E) {
- * // Determine whether processor is supported in this infrastructure
- * if ((F3x1FC[DualPlaneOnly] == 1) && (this is a dual-plane platform)) {
- * // Fixup the P-state MSRs
- * for (each core in the system) {
- * if (CPUID Fn8000_0007[CPB]) {
- * Copy MSRC001_0065 as MinPstate;
- * Copy MSRC001_0068 to MSRC001_0065;
- * Copy MinPstate to MSRC001_0068;
- * } else {
- * Copy MSRC001_0068 to MSRC001_0064;
- * Program MSRC001_0068 = 0;
- * } // endif
- * for (each MSR in MSRC001_00[68:64]) {
- * if (value in MSRC001_00[68:64][IddValue] != 0) {
- * Set PstateEn in current MSR to 1;
- * } // endif
- * } // endfor
- * } // endfor
- * Set F3xDC[PstateMaxVal] = lowest-performance enabled P-state;
- * Set F3xA8[PopDownPstate] = lowest-performance enabled P-state;
- * Set F3x64[HtcPstateLimit] = lowest-performance enabled P-state;
- * } // endif
- * } // endif
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] CpuEarlyParamsPtr Service related parameters (unused).
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-F10PmDualPlaneOnlySupport (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AP_TASK TaskPtr;
- UINT32 CPB;
- UINT32 Core;
- UINT32 Socket;
- UINT32 Module;
- UINT32 Pvimode;
- UINT32 LowestPsEn;
- UINT32 PciRegister;
- UINT32 ActiveCores;
- UINT32 ProcessorPackageType;
- PCI_ADDR PciAddress;
- CPUID_DATA CpuidData;
- CPU_LOGICAL_ID LogicalId;
- AGESA_STATUS IgnoredSts;
-
- // get the local node ID
- IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
- GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
-
- // get the package type
- ProcessorPackageType = LibAmdGetPackageType (StdHeader);
- GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
- if (((LogicalId.Revision & (AMD_F10_Cx | AMD_F10_Ex)) != 0) && ((ProcessorPackageType & PACKAGE_TYPE_AM2R2_AM3) != 0)) {
- PciAddress.AddressValue = PRCT_INFO_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- PciAddress.AddressValue = PW_CTL_MISC_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &Pvimode, StdHeader);
- if (((PciRegister & 0x80000000) != 0) && (((POWER_CTRL_MISC_REGISTER *) &Pvimode)->PviMode == 0)) {
- CPB = 0;
- LibAmdCpuidRead (AMD_CPUID_APM, &CpuidData, StdHeader);
- if (((CpuidData.EDX_Reg & 0x00000200) >> 9) == 1) {
- CPB = 1;
- }
-
- TaskPtr.FuncAddress.PfApTaskIO = SetPstateMSR;
- TaskPtr.ExeFlags = TASK_HAS_OUTPUT | WAIT_FOR_CORE;
- TaskPtr.DataTransfer.DataTransferFlags = 0;
- TaskPtr.DataTransfer.DataSizeInDwords = 1;
- TaskPtr.DataTransfer.DataPtr = &CPB;
-
- GetActiveCoresInCurrentSocket (&ActiveCores, StdHeader);
- for (Core = 1; Core < (UINT8) ActiveCores; ++Core) {
- ApUtilRunCodeOnSocketCore ((UINT8)0, (UINT8)Core, &TaskPtr, StdHeader);
- }
- LowestPsEn = ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, (VOID *) CpuEarlyParamsPtr);
-
- PciAddress.AddressValue = CPTC2_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal = LowestPsEn;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
-
- PciAddress.AddressValue = POPUP_PSTATE_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- ((POPUP_PSTATE_REGISTER *) &PciRegister)->PopDownPstate = LowestPsEn;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
-
- PciAddress.AddressValue = HTC_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- ((HTC_REGISTER *) &PciRegister)->HtcPstateLimit = LowestPsEn;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- }
- }
-}
-/*---------------------------------------------------------------------------------------*/
-/**
- * Set P-State MSR.
- *
- * This function set the P-state MSRs per each core in the system.
- *
- * @param[in] CPB Contains the value of Asymmetric Boost register
- * @param[in] StdHeader Config handle for library and services
- *
- * @return Return the lowest-performance enabled P-state
- */
-UINT32
-STATIC
-SetPstateMSR (
- IN VOID *CPB,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 dtemp;
- UINT32 LowestPsEn;
- UINT64 MsrValue;
- UINT64 MinMsrValue;
-
- if (*(UINT32*) CPB != 0) {
- LibAmdMsrRead (MSR_PSTATE_1, &MinMsrValue, StdHeader);
- LibAmdMsrRead (MSR_PSTATE_4, &MsrValue, StdHeader);
- LibAmdMsrWrite (MSR_PSTATE_1, &MsrValue, StdHeader);
- LibAmdMsrWrite (MSR_PSTATE_4, &MinMsrValue, StdHeader);
- } else {
- LibAmdMsrRead (MSR_PSTATE_4, &MsrValue, StdHeader);
- LibAmdMsrWrite (MSR_PSTATE_0, &MsrValue, StdHeader);
- MsrValue = 0;
- LibAmdMsrWrite (MSR_PSTATE_4, &MsrValue, StdHeader);
- }
-
- LowestPsEn = 0;
- for (dtemp = MSR_PSTATE_0; dtemp <= MSR_PSTATE_4; dtemp++) {
- LibAmdMsrRead (dtemp, &MsrValue, StdHeader);
- if (((PSTATE_MSR *) &MsrValue)->IddValue != 0) {
- MsrValue = MsrValue | BIT63;
- LibAmdMsrWrite (dtemp, &MsrValue, StdHeader);
- LowestPsEn = dtemp - MSR_PSTATE_0;
- }
- }
- return (LowestPsEn);
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.h b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.h
deleted file mode 100644
index 4f5e5ea..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 BIOS Configuration for Dual-plane Only Support
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F10
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPU_F10_DUAL_PLANE_ONLY_SUPPORT_H_
-#define _CPU_F10_DUAL_PLANE_ONLY_SUPPORT_H_
-
-
-/*---------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *---------------------------------------------------------------------------------------
- */
-VOID
-F10PmDualPlaneOnlySupport (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif // _CPU_F10_DUAL_PLANE_ONLY_SUPPORT_H_
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
deleted file mode 100644
index 9b99f15..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
+++ /dev/null
@@ -1,300 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 NB COF VID Initialization
- *
- * Performs the "BIOS Northbridge COF and VID Configuration" as
- * described in the BKDG.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "cpuRegisters.h"
-#include "cpuF10PowerMgmt.h"
-#include "cpuApicUtilities.h"
-#include "OptionMultiSocket.h"
-#include "cpuServices.h"
-#include "GeneralServices.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuF10Utilities.h"
-#include "cpuCommonF10Utilities.h"
-#include "F10PmNbCofVidInit.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_F10PMNBCOFVIDINIT_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-/// Structure used for performing the steps outlined in
-/// the NB COFVID configuration sequence
-typedef struct {
- UINT8 NewNbVid; ///< Destination NB VID code
- BOOLEAN NbVidUpdateAll; ///< Status of NbVidUpdateAll
-} NB_COF_VID_INIT_WARM;
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-VOID
-STATIC
-PmNbCofVidInitP0P1Core (
- IN VOID *NewNbVid,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-STATIC
-PmNbCofVidInitWarmCore (
- IN VOID *FunctionData,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family 10h core 0 entry point for performing the "Northbridge COF and
- * VID Configuration" algorithm.
- *
- * The steps are as follows:
- * 1. Determine if the algorithm is necessary by checking if all NB FIDs
- * match in the coherent fabric. If so, check to see if NbCofVidUpdate
- * is zero for all CPUs. If that is also true, no further steps are
- * necessary. If not + cold reset, proceed to step 2. If not + warm
- * reset, proceed to step 8.
- * 2. Determine NewNbVid & NewNbFid.
- * 3. Copy Startup Pstate settings to P0/P1 MSRs on all local cores.
- * 4. Copy NewNbVid to P0 NbVid on all local cores.
- * 5. Transition to P1 on all local cores.
- * 6. Transition to P0 on local core 0 only.
- * 7. Copy NewNbFid to F3xD4[NbFid], set NbFidEn, and issue a warm reset.
- * 8. Update all enabled Pstate MSRs' NbVids according to NbVidUpdateAll
- * on all local cores.
- * 9. Transition to Startup Pstate on all local cores.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] CpuEarlyParamsPtr Service related parameters (unused).
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-F10PmNbCofVidInit (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- BOOLEAN PerformNbCofVidCfg;
- BOOLEAN NotUsed;
- BOOLEAN SystemNbCofsMatch;
- UINT8 NewNbFid;
- UINT8 NewNbVid;
- UINT32 Socket;
- UINT32 Module;
- UINT32 Core;
- UINT32 SystemNbCof;
- UINT32 AndMask;
- UINT32 OrMask;
- UINT32 Ignored;
- UINT32 NewNbVoltage;
- UINT32 FrequencyDivisor;
- WARM_RESET_REQUEST Request;
- AP_TASK TaskPtr;
- PCI_ADDR PciAddress;
- AGESA_STATUS IgnoredSts;
- NB_COF_VID_INIT_WARM FunctionData;
-
- PerformNbCofVidCfg = TRUE;
- OptionMultiSocketConfiguration.GetSystemNbPstateSettings ((UINT32) 0, &CpuEarlyParamsPtr->PlatformConfig, &SystemNbCof, &FrequencyDivisor, &SystemNbCofsMatch, &NotUsed, StdHeader);
- if (SystemNbCofsMatch) {
- if (!OptionMultiSocketConfiguration.GetSystemNbCofVidUpdate (StdHeader)) {
- PerformNbCofVidCfg = FALSE;
- }
- }
- if (PerformNbCofVidCfg) {
- // get the local node ID
- IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
- GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
-
- ASSERT (Core == 0);
-
- // get NewNbVid
- FamilySpecificServices->GetNbPstateInfo (FamilySpecificServices,
- &CpuEarlyParamsPtr->PlatformConfig,
- &PciAddress,
- (UINT32) 0,
- &Ignored,
- &Ignored,
- &NewNbVoltage,
- StdHeader);
- ASSERT (((1550000 - NewNbVoltage) % 12500) == 0);
- NewNbVid = (UINT8) ((1550000 - NewNbVoltage) / 12500);
- ASSERT (NewNbVid < 0x80);
-
- if (!(IsWarmReset (StdHeader))) {
-
- // determine NewNbFid
- NewNbFid = (UINT8) ((SystemNbCof / 200) - 4);
-
- TaskPtr.FuncAddress.PfApTaskI = PmNbCofVidInitP0P1Core;
- TaskPtr.DataTransfer.DataSizeInDwords = 1;
- TaskPtr.DataTransfer.DataPtr = &NewNbVid;
- TaskPtr.DataTransfer.DataTransferFlags = 0;
- TaskPtr.ExeFlags = 0;
- ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
-
- // Transition core 0 to P0 and wait for change to complete
- FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) TRUE, StdHeader);
-
- PciAddress.Address.Register = CPTC0_REG;
- AndMask = 0xFFFFFFFF;
- ((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->NbFid = 0;
- OrMask = 0x00000000;
- ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->NbFid = NewNbFid;
- ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->NbFidEn = 1;
- ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
-
- // warm reset request
- GetWarmResetFlag (StdHeader, &Request);
- Request.RequestBit = TRUE;
- Request.StateBits = Request.PostStage - 1;
- SetWarmResetFlag (StdHeader, &Request);
- } else {
- // warm reset path
-
- FunctionData.NewNbVid = NewNbVid;
- FamilySpecificServices->IsNbCofInitNeeded (FamilySpecificServices, &PciAddress, &FunctionData.NbVidUpdateAll, StdHeader);
-
- TaskPtr.FuncAddress.PfApTaskI = PmNbCofVidInitWarmCore;
- TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (NB_COF_VID_INIT_WARM);
- TaskPtr.DataTransfer.DataPtr = &FunctionData;
- TaskPtr.DataTransfer.DataTransferFlags = 0;
- TaskPtr.ExeFlags = WAIT_FOR_CORE;
- ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
- }
- } // skip whole algorithm
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Cold reset support routine for F10PmNbCofVidInit.
- *
- * This function implements steps 3, 4, & 5 on each core.
- *
- * @param[in] NewNbVid NewNbVid determined by core 0 in step 2.
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-STATIC
-PmNbCofVidInitP0P1Core (
- IN VOID *NewNbVid,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 MsrAddress;
- UINT64 MsrRegister;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
-
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
- LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
- MsrAddress = (UINT32) ((((COFVID_STS_MSR *) &MsrRegister)->StartupPstate) + PS_REG_BASE);
- LibAmdMsrRead (MsrAddress, &MsrRegister, StdHeader);
- LibAmdMsrWrite ((UINT32) (PS_REG_BASE + 1), &MsrRegister, StdHeader);
- ((PSTATE_MSR *) &MsrRegister)->NbVid = *(UINT8 *) NewNbVid;
- LibAmdMsrWrite (PS_REG_BASE, &MsrRegister, StdHeader);
- FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 1, (BOOLEAN) FALSE, StdHeader);
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Warm reset support routine for F10PmNbCofVidInit.
- *
- * This function implements steps 8 & 9 on each core.
- *
- * @param[in] FunctionData Contains NewNbVid determined by core 0 in step
- * 2, and NbVidUpdateAll.
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-STATIC
-PmNbCofVidInitWarmCore (
- IN VOID *FunctionData,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 MsrAddress;
- UINT64 MsrRegister;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
-
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
- for (MsrAddress = PS_REG_BASE; MsrAddress <= PS_MAX_REG; MsrAddress++) {
- LibAmdMsrRead (MsrAddress, &MsrRegister, StdHeader);
- if (((PSTATE_MSR *) &MsrRegister)->IddValue != 0) {
- if ((((PSTATE_MSR *) &MsrRegister)->NbDid == 0) || ((NB_COF_VID_INIT_WARM *) FunctionData)->NbVidUpdateAll) {
- ((PSTATE_MSR *) &MsrRegister)->NbVid = ((NB_COF_VID_INIT_WARM *) FunctionData)->NewNbVid;
- LibAmdMsrWrite (MsrAddress, &MsrRegister, StdHeader);
- }
- }
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10PmNbCofVidInit.h b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10PmNbCofVidInit.h
deleted file mode 100644
index 0375e40..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10PmNbCofVidInit.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 NB COF VID Initialization
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F10
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPU_F10_PM_NB_COF_VID_INIT_H_
-#define _CPU_F10_PM_NB_COF_VID_INIT_H_
-
-
-/*---------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *---------------------------------------------------------------------------------------
- */
-VOID
-F10PmNbCofVidInit (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif // _CPU_F10_PM_NB_COF_VID_INIT_H_
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10PmNbPstateInit.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10PmNbPstateInit.c
deleted file mode 100644
index f69436f..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10PmNbPstateInit.c
+++ /dev/null
@@ -1,188 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 NB Pstate Initialization
- *
- * Performs the action described in F3x1F0[NbPstate] as
- * described in the BKDG.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F10
- * @e \$Revision: 35877 $ @e \$Date: 2010-08-03 12:51:46 +0800 (Tue, 03 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "cpuRegisters.h"
-#include "cpuF10PowerMgmt.h"
-#include "cpuApicUtilities.h"
-#include "GeneralServices.h"
-#include "cpuFamilyTranslation.h"
-#include "F10PmNbPstateInit.h"
-#include "F10PackageType.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_F10PMNBPSTATEINIT_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-/// Structure used for modifying the P-state
-/// MSRs on fuse enable CPUs.
-typedef struct {
- UINT8 NbVid1; ///< Destination NB VID code
- UINT8 NbPstate; ///< Status of NbVidUpdateAll
-} NB_PSTATE_INIT;
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-VOID
-STATIC
-PmNbPstateInitCore (
- IN VOID *NbPstateParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family 10h core 0 entry point for performing the actions described in the
- * description of F3x1F0[NbPstate].
- *
- * If F3x1F0[NbPstate] is non zero, it specifies the highest performance
- * P-state in which to enable NbDid. Each core must loop through their
- * P-state MSRs, enabling NbDid and changing NbVid to a lower voltage.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] CpuEarlyParamsPtr Service related parameters (unused).
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-F10PmNbPstateInit (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Core;
- UINT32 Module;
- UINT32 PciRegister;
- UINT32 Socket;
- AP_TASK TaskPtr;
- PCI_ADDR PciAddress;
- AGESA_STATUS IgnoredSts;
- NB_PSTATE_INIT ApParams;
-
- if (FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, &CpuEarlyParamsPtr->PlatformConfig, StdHeader)) {
- if (CpuEarlyParamsPtr->PlatformConfig.PlatformProfile.PlatformPowerPolicy == BatteryLife) {
- IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
- ASSERT (Core == 0);
- GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = 0x1F0;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- if ((PciRegister & 0x00070000) != 0) {
- ApParams.NbPstate = (UINT8) ((PciRegister & 0x00070000) >> 16);
- ASSERT (ApParams.NbPstate < NM_PS_REG);
-
- PciAddress.Address.Function = FUNC_4;
- PciAddress.Address.Register = 0x1F4;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- ApParams.NbVid1 = (UINT8) ((PciRegister & 0x00003F80) >> 7);
-
- TaskPtr.FuncAddress.PfApTaskI = PmNbPstateInitCore;
- TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (NB_PSTATE_INIT);
- TaskPtr.DataTransfer.DataPtr = &ApParams;
- TaskPtr.DataTransfer.DataTransferFlags = 0;
- TaskPtr.ExeFlags = WAIT_FOR_CORE;
- ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
-
- }
- }
- }
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Support routine for F10PmNbPstateInit.
- *
- * This function modifies NbVid and NbDid on each core.
- *
- * @param[in] NbPstateParams Appropriate NbVid1 and NbPstate as determined by core 0.
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-STATIC
-PmNbPstateInitCore (
- IN VOID *NbPstateParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 MsrAddress;
- UINT64 MsrRegister;
-
- for (MsrAddress = (PS_REG_BASE + ((NB_PSTATE_INIT *) NbPstateParams)->NbPstate); MsrAddress <= PS_MAX_REG; MsrAddress++) {
- LibAmdMsrRead (MsrAddress, &MsrRegister, StdHeader);
- if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
- ((PSTATE_MSR *) &MsrRegister)->NbDid = 1;
- ((PSTATE_MSR *) &MsrRegister)->NbVid = ((NB_PSTATE_INIT *) NbPstateParams)->NbVid1;
- LibAmdMsrWrite (MsrAddress, &MsrRegister, StdHeader);
- }
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10PmNbPstateInit.h b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10PmNbPstateInit.h
deleted file mode 100644
index 3e2e834..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10PmNbPstateInit.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 NB P-State Initialization
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F10
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPU_F10_PM_NB_PSTATE_INIT_H_
-#define _CPU_F10_PM_NB_PSTATE_INIT_H_
-
-
-/*---------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *---------------------------------------------------------------------------------------
- */
-VOID
-F10PmNbPstateInit (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif // _CPU_F10_PM_NB_PSTATE_INIT_H_
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10SingleLinkPciTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10SingleLinkPciTables.c
deleted file mode 100644
index 5363ed2..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/F10SingleLinkPciTables.c
+++ /dev/null
@@ -1,1942 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 PCI tables in Recommended Settings for Single Link Processors.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x10
- * @e \$Revision: 36159 $ @e \$Date: 2010-08-12 11:19:16 +0800 (Thu, 12 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_F10SINGLELINKPCITABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-// P C I T a b l e s
-// ----------------------
-
-STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10SingleLinkPciRegisters[] =
-{
-// F0x68 - Link Transaction Control
-// bit[14:13], BufPriRel = 01b
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_SINGLE_LINK, // platform Features
- {
- MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68), // Address
- 0x00002000, // regData
- 0x00006000, // regMask
- }
- },
-// F0x68 - Link Transaction Control
-// bit[24], DispRefModeEn = 0
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platform Features
- {
- MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68), // Address
- 0x00000000, // regData
- 0x01000000, // regMask
- }
- },
-// F0x68 - Link Transaction Control
-// bit[24], DispRefModeEn = 1 for UMA, but can only set it on the warm reset.
- {
- ProfileFixup,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_UMA, // platform Features
- {
- PERFORMANCE_IS_WARM_RESET,
- MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68), // Address
- 0x01000000, // regData
- 0x01000000, // regMask
- }
- },
- // F0x[F0,D0,B0,90] Link Base Buffer Count Register
- // 27:25 FreeData: 2
- // 24:20 FreeCmd: 8
- // 19:18 RspData: 1
- // 17:16 NpReqData: 1
- // 15:12 ProbeCmd: 0
- // 11:8 RspCmd: 2
- // 7:5 PReq: 4
- // 4:0 NpReqCmd: 18
- {
- HtHostPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM),
- {
- HT_HOST_FEATURES_ALL, // Link Features
- 0x10, // Address
- 0x04850292, // Data
- 0x0FFFFFFF // Mask
- },
- },
- // F0x[F0,D0,B0,90] Link Base Buffer Count Register
- // 27:25 FreeData: 2
- // 24:20 FreeCmd: 8
- // 19:18 RspData: 1
- // 17:16 NpReqData: 1
- // 15:12 ProbeCmd: 0
- // 11:8 RspCmd: 2
- // 7:5 PReq: 4
- // 4:0 NpReqCmd: 18
- {
- HtHostPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA),
- {
- HT_HOST_FEATURES_ALL, // Link Features
- 0x10, // Address
- 0x04850292, // Data
- 0x0FFFFFFF // Mask
- },
- },
- // F0x[F0,D0,B0,90] Link Base Buffer Count Register
- // 27:25 FreeData: 2
- // 24:20 FreeCmd: 8
- // 19:18 RspData: 1
- // 17:16 NpReqData: 1
- // 15:12 ProbeCmd: 0
- // 11:8 RspCmd: 2
- // 7:5 PReq: 3
- // 4:0 NpReqCmd: 11
- {
- HtHostPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM),
- {
- HT_HOST_FEATURES_ALL, // Link Features
- 0x10, // Address
- 0x0485026B, // Data
- 0x0FFFFFFF // Mask
- },
- },
- // F0x[F0,D0,B0,90] Link Base Buffer Count Register
- // 27:25 FreeData: 2
- // 24:20 FreeCmd: 8
- // 19:18 RspData: 1
- // 17:16 NpReqData: 1
- // 15:12 ProbeCmd: 0
- // 11:8 RspCmd: 2
- // 7:5 PReq: 6
- // 4:0 NpReqCmd: 15
- {
- HtHostPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM),
- {
- HT_HOST_FEATURES_ALL, // Link Features
- 0x10, // Address
- 0x008502CF, // Data
- 0x0FFFFFFF // Mask
- },
- },
- // F0x[F4,D4,B4,94] Link Base Buffer Count Register
- // 28:27 IsocRspData: 0
- // 26:25 IsocNpReqData: 0
- // 24:22 IsocRspCmd: 0
- // 21:19 IsocPReq: 0
- // 18:16 IsocNpReqCmd: 0
- {
- HtHostPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM),
- {
- HT_HOST_FEATURES_ALL, // Link Features
- 0x14, // Address
- 0x00000000, // Data
- 0x1FFF0000 // Mask
- },
- },
- // F0x[F4,D4,B4,94] Link Base Buffer Count Register
- // 28:27 IsocRspData: 0
- // 26:25 IsocNpReqData: 0
- // 24:22 IsocRspCmd: 0
- // 21:19 IsocPReq: 0
- // 18:16 IsocNpReqCmd: 0
- {
- HtHostPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA),
- {
- HT_HOST_FEATURES_ALL, // Link Features
- 0x14, // Address
- 0x00000000, // Data
- 0x1FFF0000 // Mask
- },
- },
- // F0x[F4,D4,B4,94] Link Base Buffer Count Register
- // 28:27 IsocRspData: 0
- // 26:25 IsocNpReqData: 0
- // 24:22 IsocRspCmd: 0
- // 21:19 IsocPReq: 1
- // 18:16 IsocNpReqCmd: 7
- {
- HtHostPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM),
- {
- HT_HOST_FEATURES_ALL, // Link Features
- 0x14, // Address
- 0x000F0000, // Data
- 0x1FFF0000 // Mask
- },
- },
- // F0x[F4,D4,B4,94] Link Base Buffer Count Register
- // 28:27 IsocRspData: 0
- // 26:25 IsocNpReqData: 0
- // 24:22 IsocRspCmd: 0
- // 21:19 IsocPReq: 0
- // 18:16 IsocNpReqCmd: 1
- {
- HtHostPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM),
- {
- HT_HOST_FEATURES_ALL, // Link Features
- 0x14, // Address
- 0x00010000, // Data
- 0x1FFF0000 // Mask
- },
- },
-// F0x170 - Link Extended Control Register - Link 0, sublink 0
-// bit[8] LS2En = 1
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_SINGLE_LINK, // platform Features
- {
- MAKE_SBDFO (0, 0, 24, FUNC_0, 0x170), // Address
- 0x00000100, // regData
- 0x00000100, // regMask
- }
- },
-// F2x118 - Memory Controller Configuration Low Register
-// bits[13:12] MctPriIsoc = 10b
-// bits[31:28] MctVarPriCntLmt = 0
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_UMA | AMD_PF_UMA_IFCM), // platform Features
- {
- MAKE_SBDFO (0, 0, 24, FUNC_2, 0x118), // Address
- 0x00002000, // regData
- 0xF0003000, // regMask
- }
- },
-// F2x118 - Memory Controller Configuration Low Register
-// bits[13:12] MctPriIsoc = 11b
-// bits[31:28] MctVarPriCntLmt = 1
- {
- ProfileFixup,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_UMA | AMD_PF_UMA_IFCM), // platform Features
- {
- PERFORMANCE_MCT_ISOC_VARIABLE, // Features
- MAKE_SBDFO (0, 0, 24, FUNC_2, 0x118), // Address
- 0x10003000, // regData
- 0xF0003000, // regMask
- }
- },
-// F2x[1,0]90 - DRAM Configuration Low Register
-// bits [10] BurstLength32 0
-// It is okay to write both channels, if one is disabled, this bit has no effect on that channel.
-// If the channels are ganged for 128 bit operation, the memory init code will resolve any conflict with this setting.
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_UMA | AMD_PF_UMA_IFCM), // platform Features
- {
- MAKE_SBDFO (0, 0, 24, FUNC_2, 0x90), // Address
- 0x00000000, // regData
- 0x00000400, // regMask
- }
- },
-// F2x[1,0]90 - DRAM Configuration Low Register
-// bits [10] BurstLength32 = 0
-// It is okay to write both channels, if one is disabled, this bit has no effect on that channel.
-// If the channels are ganged for 128 bit operation, the memory init code will resolve any conflict with this setting.
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_UMA | AMD_PF_UMA_IFCM), // platform Features
- {
- MAKE_SBDFO (0, 0, 24, FUNC_2, 0x190), // Address
- 0x00000000, // regData
- 0x00000400, // regMask
- }
- },
-// F2x[1,0]90 - DRAM Configuration Low Register
-// bits [10] BurstLength32 = 1
-// It is okay to write both channels, if one is disabled, this bit has no effect on that channel.
-// If the channels are ganged for 128 bit operation, the memory init code will resolve any conflict with this setting.
- {
- ProfileFixup,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_UMA | AMD_PF_UMA_IFCM), // platform Features
- {
- PERFORMANCE_REFRESH_REQUEST_32B,
- MAKE_SBDFO (0, 0, 24, FUNC_2, 0x90), // Address
- 0x00000400, // regData
- 0x00000400, // regMask
- }
- },
-// F2x[1,0]90 - DRAM Configuration Low Register
-// bits [10] BurstLength32 = 1
-// It is okay to write both channels, if one is disabled, this bit has no effect on that channel.
-// If the channels are ganged for 128 bit operation, the memory init code will resolve any conflict with this setting.
- {
- ProfileFixup,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_UMA | AMD_PF_UMA_IFCM), // platform Features
- {
- PERFORMANCE_REFRESH_REQUEST_32B,
- MAKE_SBDFO (0, 0, 24, FUNC_2, 0x190), // Address
- 0x00000400, // regData
- 0x00000400, // regMask
- }
- },
-// F3x6C - Data Buffer Control
-// bits[2:0] UpReqDBC = 2
-// bits[5:4] DnReqDBC = 1
-// bits[7:6] DnRspDBC = 1
-// bit[15] DatBuf24 = 1
-// bits[18:16] UpRspDBC = 1
-// bits[30:28] IsocRspDBC = 0
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM), // platform Features
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C), // Address
- 0x00018052, // regData
- 0x700780F7, // regMask
- }
- },
-// F3x6C - Data Buffer Control
-// bits[2:0] UpReqDBC = 1
-// bits[5:4] DnReqDBC = 1
-// bits[7:6] DnRspDBC = 1
-// bit[15] DatBuf24 = 1
-// bits[18:16] UpRspDBC = 1
-// bits[30:28] IsocRspDBC = 6
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA), // platform Features
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C), // Address
- 0x60018051, // regData
- 0x700780F7, // regMask
- }
- },
-// F3x6C - Data Buffer Control
-// bits[2:0] UpReqDBC = 2
-// bits[5:4] DnReqDBC = 1
-// bits[7:6] DnRspDBC = 1
-// bit[15] DatBuf24 = 1
-// bits[18:16] UpRspDBC = 1
-// bits[30:28] IsocRspDBC = 1
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM), // platform Features
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C), // Address
- 0x10018052, // regData
- 0x700780F7, // regMask
- }
- },
-// F3x6C - Data Buffer Control
-// bits[2:0] UpReqDBC = 1
-// bits[5:4] DnReqDBC = 1
-// bits[7:6] DnRspDBC = 1
-// bit[15] DatBuf24 = 1
-// bits[18:16] UpRspDBC = 1
-// bits[30:28] IsocRspDBC = 6
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM), // platform Features
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C), // Address
- 0x60018051, // regData
- 0x700780F7, // regMask
- }
- },
-// F3x70 - SRI_to_XBAR Command Buffer Count
-// bits[2:0] UpReqCBC = 3
-// bits[5:4] DnReqCBC = 1
-// bits[7:6] DnRspCBC = 1
-// bits[10:8] UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 1
-// bits[18:16] UpRspCBC = 4
-// bits[22:20] IsocReqCBC = 0
-// bits[26:24] IsocPreqCBC = 0
-// bits[30:28] IsocRspCBC = 0
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM), // platform Features
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70), // Address
- 0x00041153, // regData
- 0x777777F7, // regMask
- }
- },
-// F3x70 - SRI_to_XBAR Command Buffer Count
-// bits[2:0] UpReqCBC = 1
-// bits[5:4] DnReqCBC = 1
-// bits[7:6] DnRspCBC = 1
-// bits[10:8] UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 1
-// bits[18:16] UpRspCBC = 2
-// bits[22:20] IsocReqCBC = 2
-// bits[26:24] IsocPreqCBC = 1
-// bits[30:28] IsocRspCBC = 6
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA), // platform Features
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70), // Address
- 0x61221151, // regData
- 0x777777F7, // regMask
- }
- },
-// F3x70 - SRI_to_XBAR Command Buffer Count
-// bits[2:0] UpReqCBC = 1
-// bits[5:4] DnReqCBC = 1
-// bits[7:6] DnRspCBC = 1
-// bits[10:8] UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 1
-// bits[18:16] UpRspCBC = 2
-// bits[22:20] IsocReqCBC = 2
-// bits[26:24] IsocPreqCBC = 1
-// bits[30:28] IsocRspCBC = 6
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM), // platform Features
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70), // Address
- 0x61221151, // regData
- 0x777777F7, // regMask
- }
- },
-// F3x70 - SRI_to_XBAR Command Buffer Count
-// bits[2:0] UpReqCBC = 3
-// bits[5:4] DnReqCBC = 1
-// bits[7:6] DnRspCBC = 1
-// bits[10:8] UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 1
-// bits[18:16] UpRspCBC = 4
-// bits[22:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 1
-// bits[30:28] IsocRspCBC = 1
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM), // platform Features
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70), // Address
- 0x11141153, // regData
- 0x777777F7, // regMask
- }
- },
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// bits[2:0] UpReqCBC = 1
-// bits[6:4] DnReqCBC = 1
-// bits[10:8] UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 1
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 0
-// bits[26:24] IsocPreqCBC = 0
-// bits[31:28] DRReqCBC = 0
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM), // platform Features
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address
- 0x00081111, // regData
- 0xF7FF7777, // regMask
- }
- },
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// No Mct Variable Priority or 32 byte requests.
-// bits[2:0] UpReqCBC = 1
-// bits[6:4] DnReqCBC = 0
-// bits[10:8] UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 0
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 1
-// bits[31:28] DRReqCBC = 9
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA), // platform Features
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address
- 0x91180101, // regData
- 0xF7FF7777, // regMask
- }
- },
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// No Mct Variable Priority or 32 byte requests.
-// bits[2:0] UpReqCBC = 1
-// bits[6:4] DnReqCBC = 0
-// bits[10:8] UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 0
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 1
-// bits[31:28] DRReqCBC = 9
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM), // platform Features
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address
- 0x91180101, // regData
- 0xF7FF7777, // regMask
- }
- },
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// No Mct Variable Priority or 32 byte requests.
-// bits[2:0] UpReqCBC = 1
-// bits[6:4] DnReqCBC = 0
-// bits[10:8] UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 0
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 1
-// bits[31:28] DRReqCBC = 8
- {
- CoreCountsPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA), // platform Features
- {
- PERFORMANCE_PROFILE_ALL, // Features
- (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE), // 5-cores
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address
- 0x81180101, // regData
- 0xF7FF7777, // regMask
- }
- },
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// No Mct Variable Priority or 32 byte requests.
-// bits[2:0] UpReqCBC = 1
-// bits[6:4] DnReqCBC = 0
-// bits[10:8] UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 0
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 1
-// bits[31:28] DRReqCBC = 8
- {
- CoreCountsPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM), // platform Features
- {
- PERFORMANCE_PROFILE_ALL, // Features
- (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE), // 5-cores
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address
- 0x81180101, // regData
- 0xF7FF7777, // regMask
- }
- },
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// No Mct Variable Priority or 32 byte requests.
-// bits[2:0] UpReqCBC = 1
-// bits[6:4] DnReqCBC = 0
-// bits[10:8] UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 0
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 1
-// bits[31:28] DRReqCBC = 7
- {
- CoreCountsPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA), // platform Features
- {
- PERFORMANCE_PROFILE_ALL, // Features
- (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE), // 6-cores
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address
- 0x71180101, // regData
- 0xF7FF7777, // regMask
- }
- },
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// No Mct Variable Priority or 32 byte requests.
-// bits[2:0] UpReqCBC = 1
-// bits[6:4] DnReqCBC = 0
-// bits[10:8] UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 0
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 1
-// bits[31:28] DRReqCBC = 7
- {
- CoreCountsPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM), // platform Features
- {
- PERFORMANCE_PROFILE_ALL, // Features
- (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE), // 6-cores
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address
- 0x71180101, // regData
- 0xF7FF7777, // regMask
- }
- },
-
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// bits[2:0] UpReqCBC = 1
-// bits[6:4] DnReqCBC = 0
-// bits[10:8] UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 0
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 1
-// bits[31:28] DRReqCBC = C
- {
- ProfileFixup,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA), // platform Features
- {
- PERFORMANCE_MCT_ISOC_VARIABLE, // Features
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address
- 0xC1180101, // regData
- 0xF7FF7777, // regMask
- }
- },
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// bits[2:0] UpReqCBC = 1
-// bits[6:4] DnReqCBC = 0
-// bits[10:8] UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 0
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 1
-// bits[31:28] DRReqCBC = C
- {
- ProfileFixup,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM), // platform Features
- {
- PERFORMANCE_MCT_ISOC_VARIABLE, // Features
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address
- 0xC1181111, // regData
- 0xF7FF7777, // regMask
- }
- },
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// bits[2:0] UpReqCBC = 1
-// bits[6:4] DnReqCBC = 0
-// bits[10:8] UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 0
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 1
-// bits[31:28] DRReqCBC = F
- {
- ProfileFixup,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA), // platform Features
- {
- PERFORMANCE_REFRESH_REQUEST_32B, // Features
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address
- 0xF1180101, // regData
- 0xF7FF7777, // regMask
- }
- },
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// bits[2:0] UpReqCBC = 1
-// bits[6:4] DnReqCBC = 0
-// bits[10:8] UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 0
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 1
-// bits[31:28] DRReqCBC = F
- {
- ProfileFixup,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM), // platform Features
- {
- PERFORMANCE_REFRESH_REQUEST_32B, // Features
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address
- 0xF1181111, // regData
- 0xF7FF7777, // regMask
- }
- },
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// bits[2:0] UpReqCBC = 1
-// bits[6:4] DnReqCBC = 0
-// bits[10:8] UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 0
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 1
-// bits[31:28] DRReqCBC = B
- {
- CoreCountsPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA), // platform Features
- {
- PERFORMANCE_REFRESH_REQUEST_32B, // Features
- (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE), // 5-cores
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address
- 0xB1180101, // regData
- 0xF7FF7777, // regMask
- }
- },
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// bits[2:0] UpReqCBC = 1
-// bits[6:4] DnReqCBC = 0
-// bits[10:8] UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 0
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 1
-// bits[31:28] DRReqCBC = B
- {
- CoreCountsPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM), // platform Features
- {
- PERFORMANCE_REFRESH_REQUEST_32B, // Features
- (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE), // 5-cores
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address
- 0xB1180101, // regData
- 0xF7FF7777, // regMask
- }
- },
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// bits[2:0] UpReqCBC = 1
-// bits[6:4] DnReqCBC = 0
-// bits[10:8] UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 0
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 1
-// bits[31:28] DRReqCBC = A
- {
- CoreCountsPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA), // platform Features
- {
- PERFORMANCE_REFRESH_REQUEST_32B, // Features
- (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE), // 6-cores
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address
- 0xA1180101, // regData
- 0xF7FF7777, // regMask
- }
- },
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// bits[2:0] UpReqCBC = 1
-// bits[6:4] DnReqCBC = 0
-// bits[10:8] UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 0
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 1
-// bits[31:28] DRReqCBC = A
- {
- CoreCountsPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM), // platform Features
- {
- PERFORMANCE_REFRESH_REQUEST_32B, // Features
- (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE), // 6-cores
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address
- 0xA1180101, // regData
- 0xF7FF7777, // regMask
- }
- },
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// bits[2:0] UpReqCBC = 1
-// bits[6:4] DnReqCBC = 0
-// bits[10:8] UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 0
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 1
-// bits[31:28] DRReqCBC = E
- {
- CoreCountsPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA), // platform Features
- {
- PERFORMANCE_REFRESH_REQUEST_32B, // Features
- (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE), // 5-cores
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address
- 0xE1180101, // regData
- 0xF7FF7777, // regMask
- }
- },
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// bits[2:0] UpReqCBC = 1
-// bits[6:4] DnReqCBC = 0
-// bits[10:8] UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 0
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 1
-// bits[31:28] DRReqCBC = E
- {
- CoreCountsPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM), // platform Features
- {
- PERFORMANCE_REFRESH_REQUEST_32B, // Features
- (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE), // 5-cores
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address
- 0xE1180101, // regData
- 0xF7FF7777, // regMask
- }
- },
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// bits[2:0] UpReqCBC = 1
-// bits[6:4] DnReqCBC = 0
-// bits[10:8] UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 0
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 1
-// bits[31:28] DRReqCBC = D
- {
- CoreCountsPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA), // platform Features
- {
- PERFORMANCE_REFRESH_REQUEST_32B, // Features
- (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE), // 6-cores
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address
- 0xD1180101, // regData
- 0xF7FF7777, // regMask
- }
- },
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// bits[2:0] UpReqCBC = 1
-// bits[6:4] DnReqCBC = 0
-// bits[10:8] UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 0
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 1
-// bits[26:24] IsocPreqCBC = 1
-// bits[31:28] DRReqCBC = D
- {
- CoreCountsPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM), // platform Features
- {
- PERFORMANCE_REFRESH_REQUEST_32B, // Features
- (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE), // 6-cores
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address
- 0xD1180101, // regData
- 0xF7FF7777, // regMask
- }
- },
-
-// F3x74 - XBAR_to_SRI Command Buffer Count
-// bits[2:0] UpReqCBC = 1
-// bits[6:4] DnReqCBC = 0
-// bits[10:8] UpPreqCBC = 1
-// bits[14:12] DnPreqCBC = 0
-// bits[19:16] ProbeCBC = 8
-// bits[23:20] IsocReqCBC = 8
-// bits[26:24] IsocPreqCBC = 1
-// bits[31:28] DRReqCBC = 0
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM), // platform Features
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address
- 0x01880101, // regData
- 0xF7FF7777, // regMask
- }
- },
-// F3x7C - Free List Buffer Count
-// bits[4:0] Xbar2SriFreeListCBC = 20
-// bits[11:8] Sri2XbarFreeXreqCBC = 9
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 9
-// bits[22:20] Sri2XbarFreeRspDBC = 0
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM), // platform Features
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address
- 0x00090914, // regData
- 0x007FFF1F, // regMask
- }
- },
-// F3x7C - Free List Buffer Count
-// No Mct Variable Priority or 32 byte requests.
-// bits[4:0] Xbar2SriFreeListCBC = 15
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA), // platform Features
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address
- 0x0007080F, // regData
- 0x007FFF1F, // regMask
- }
- },
-// F3x7C - Free List Buffer Count
-// No Mct Variable Priority or 32 byte requests.
-// bits[4:0] Xbar2SriFreeListCBC = 15
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM), // platform Features
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address
- 0x0007080F, // regData
- 0x007FFF1F, // regMask
- }
- },
-// F3x7C - Free List Buffer Count
-// bits[4:0] Xbar2SriFreeListCBC = 12
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
- {
- ProfileFixup,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA), // platform Features
- {
- PERFORMANCE_MCT_ISOC_VARIABLE, // Features
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address
- 0x0007080C, // regData
- 0x007FFF1F, // regMask
- }
- },
-// F3x7C - Free List Buffer Count
-// bits[4:0] Xbar2SriFreeListCBC = 12
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
- {
- ProfileFixup,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM), // platform Features
- {
- PERFORMANCE_MCT_ISOC_VARIABLE, // Features
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address
- 0x0007080C, // regData
- 0x007FFF1F, // regMask
- }
- },
-// F3x7C - Free List Buffer Count
-// bits[4:0] Xbar2SriFreeListCBC = 9
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
- {
- ProfileFixup,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA), // platform Features
- {
- PERFORMANCE_REFRESH_REQUEST_32B, // Features
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address
- 0x00070809, // regData
- 0x007FFF1F, // regMask
- }
- },
-// F3x7C - Free List Buffer Count
-// bits[4:0] Xbar2SriFreeListCBC = 9
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
- {
- ProfileFixup,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM), // platform Features
- {
- PERFORMANCE_REFRESH_REQUEST_32B , // Features
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address
- 0x00070809, // regData
- 0x007FFF1F, // regMask
- }
- },
-// F3x7C - Free List Buffer Count
-// bits[4:0] Xbar2SriFreeListCBC = 17
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM), // platform Features
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address
- 0x00070811, // regData
- 0x007FFF1F, // regMask
- }
- },
-// F3x7C - Free List Buffer Count
-// No Mct Variable Priority or 32 byte requests.
-// bits[4:0] Xbar2SriFreeListCBC = 14
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
- {
- CoreCountsPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA), // platform Features
- {
- PERFORMANCE_PROFILE_ALL,
- (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE), // 5 cores.
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address
- 0x0007080E, // regData
- 0x007FFF1F, // regMask
- }
- },
-// F3x7C - Free List Buffer Count
-// No Mct Variable Priority or 32 byte requests.
-// bits[4:0] Xbar2SriFreeListCBC = 14
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
- {
- CoreCountsPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM), // platform Features
- {
- PERFORMANCE_PROFILE_ALL,
- (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE), // 5 cores.
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address
- 0x0007080E, // regData
- 0x007FFF1F, // regMask
- }
- },
-// F3x7C - Free List Buffer Count
-// No Mct Variable Priority or 32 byte requests.
-// bits[4:0] Xbar2SriFreeListCBC = 13
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
- {
- CoreCountsPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA), // platform Features
- {
- PERFORMANCE_PROFILE_ALL,
- (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE), // 6 cores.
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address
- 0x0007080D, // regData
- 0x007FFF1F, // regMask
- }
- },
-// F3x7C - Free List Buffer Count
-// No Mct Variable Priority or 32 byte requests.
-// bits[4:0] Xbar2SriFreeListCBC = 13
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
- {
- CoreCountsPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM), // platform Features
- {
- PERFORMANCE_PROFILE_ALL,
- (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE), // 6 cores.
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address
- 0x0007080D, // regData
- 0x007FFF1F, // regMask
- }
- },
-// F3x7C - Free List Buffer Count
-// bits[4:0] Xbar2SriFreeListCBC = 11
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
- {
- CoreCountsPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA), // platform Features
- {
- PERFORMANCE_MCT_ISOC_VARIABLE, // Features
- (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE), // 5 cores.
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address
- 0x0007080B, // regData
- 0x007FFF1F, // regMask
- }
- },
-// F3x7C - Free List Buffer Count
-// bits[4:0] Xbar2SriFreeListCBC = 11
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
- {
- CoreCountsPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM), // platform Features
- {
- PERFORMANCE_MCT_ISOC_VARIABLE, // Features
- (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE), // 5 cores.
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address
- 0x0007080B, // regData
- 0x007FFF1F, // regMask
- }
- },
-// F3x7C - Free List Buffer Count
-// bits[4:0] Xbar2SriFreeListCBC = 10
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
- {
- CoreCountsPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA), // platform Features
- {
- PERFORMANCE_MCT_ISOC_VARIABLE, // Features
- (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE), // 6 cores.
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address
- 0x0007080A, // regData
- 0x007FFF1F, // regMask
- }
- },
-// F3x7C - Free List Buffer Count
-// bits[4:0] Xbar2SriFreeListCBC = 10
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
- {
- CoreCountsPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM), // platform Features
- {
- PERFORMANCE_MCT_ISOC_VARIABLE, // Features
- (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE), // 6 cores.
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address
- 0x0007080A, // regData
- 0x007FFF1F, // regMask
- }
- },
-// F3x7C - Free List Buffer Count
-// bits[4:0] Xbar2SriFreeListCBC = 8
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
- {
- CoreCountsPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA), // platform Features
- {
- PERFORMANCE_REFRESH_REQUEST_32B, // Features
- (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE), // 5 cores.
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address
- 0x00070808, // regData
- 0x007FFF1F, // regMask
- }
- },
-// F3x7C - Free List Buffer Count
-// bits[4:0] Xbar2SriFreeListCBC = 8
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
- {
- CoreCountsPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM), // platform Features
- {
- PERFORMANCE_REFRESH_REQUEST_32B , // Features
- (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE), // 5 cores.
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address
- 0x00070808, // regData
- 0x007FFF1F, // regMask
- }
- },
-// F3x7C - Free List Buffer Count
-// bits[4:0] Xbar2SriFreeListCBC = 7
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
- {
- CoreCountsPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA), // platform Features
- {
- PERFORMANCE_REFRESH_REQUEST_32B, // Features
- (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE), // 6 cores.
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address
- 0x00070807, // regData
- 0x007FFF1F, // regMask
- }
- },
-// F3x7C - Free List Buffer Count
-// bits[4:0] Xbar2SriFreeListCBC = 7
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
- {
- CoreCountsPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM), // platform Features
- {
- PERFORMANCE_REFRESH_REQUEST_32B , // Features
- (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE), // 6 cores.
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address
- 0x00070807, // regData
- 0x007FFF1F, // regMask
- }
- },
-// F3x7C - Free List Buffer Count
-// bits[4:0] Xbar2SriFreeListCBC = 16
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
- {
- CoreCountsPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM), // platform Features
- {
- PERFORMANCE_PROFILE_ALL,
- (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE), // 5 cores.
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address
- 0x00070810, // regData
- 0x707FFF1F, // regMask
- }
- },
-// F3x7C - Free List Buffer Count
-// bits[4:0] Xbar2SriFreeListCBC = 15
-// bits[11:8] Sri2XbarFreeXreqCBC = 8
-// bits[15:12] Sri2XbarFreeRspCBC = 0
-// bits[19:16] Sri2XbarFreeXreqDBC = 7
-// bits[22:20] Sri2XbarFreeRspDBC = 0
- {
- CoreCountsPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM), // platform Features
- {
- PERFORMANCE_PROFILE_ALL,
- (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE), // 6 cores.
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address
- 0x0007080F, // regData
- 0x707FFF1F, // regMask
- }
- },
-// F3x7C - Free List Buffer Count
-// bits[4:0] Xbar2SriFreeListCBC = 22, 1-core without L3 cache is 22
- {
- CoreCountsPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_SINGLE_LINK, // platformFeatures
- {
- PERFORMANCE_NO_L3_CACHE,
- (CORE_RANGE_0 (1, 1) | COUNT_RANGE_NONE), // 1 core.
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address
- 0x00000016, // regData
- 0x0000001F, // regMask
- }
- },
-// F3x7C - Free List Buffer Count
-// bits[4:0] Xbar2SriFreeListCBC = 20, 2-core is 20
- {
- CoreCountsPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_SINGLE_LINK, // platformFeatures
- {
- PERFORMANCE_NO_L3_CACHE,
- (CORE_RANGE_0 (2, 2) | COUNT_RANGE_NONE), // 2 core.
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address
- 0x00000014, // regData
- 0x0000001F, // regMask
- }
- },
-// F3x7C - Free List Buffer Count
-// bits[4:0] Xbar2SriFreeListCBC = 18, 3-core without L3 cache is 18.
- {
- CoreCountsPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_SINGLE_LINK, // platformFeatures
- {
- PERFORMANCE_NO_L3_CACHE,
- (CORE_RANGE_0 (3, 3) | COUNT_RANGE_NONE), // 3 core.
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address
- 0x00000012, // regData
- 0x0000001F, // regMask
- }
- },
-// F3x7C - Free List Buffer Count
-// bits[4:0] Xbar2SriFreeListCBC = 14, 4-core without L3 cache is 16.
- {
- CoreCountsPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_SINGLE_LINK, // platformFeatures
- {
- PERFORMANCE_NO_L3_CACHE,
- (CORE_RANGE_0 (4, 4) | COUNT_RANGE_NONE), // 4 core.
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address
- 0x00000010, // regData
- 0x0000001F, // regMask
- }
- },
-// F3x7C - Free List Buffer Count
-// bits[4:0] Xbar2SriFreeListCBC = 14, 5-core without L3 cache is 14.
- {
- CoreCountsPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_SINGLE_LINK, // platformFeatures
- {
- PERFORMANCE_NO_L3_CACHE,
- (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE), // 5 core.
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address
- 0x0000000E, // regData
- 0x0000001F, // regMask
- }
- },
-// F3x7C - Free List Buffer Count
-// bits[4:0] Xbar2SriFreeListCBC = 12, 6-core without L3 cache is 12.
- {
- CoreCountsPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_SINGLE_LINK, // platformFeatures
- {
- PERFORMANCE_NO_L3_CACHE,
- (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE), // 6 core.
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address
- 0x0000000C, // regData
- 0x0000001F, // regMask
- }
- },
-// F3x140 - SRI_to_XCS Token Count
-// bits[1:0] UpReqTok = 2
-// bits[3:2] DnReqTok = 1
-// bits[5:4] UpPreqTokC = 1
-// bits[7:6] DnPreqTok = 1
-// bits[9:8] UpRspTok = 3
-// bits[11:10] DnRspTok = 1
-// bits[13:12] IsocReqTok = 0
-// bits[15:14] IsocPreqTok = 0
-// bits[17:16] IsocRspTok = 0
-// bits[23:20] FreeTok = 8
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM), // platform Features
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
- 0x00800756, // regData
- 0x00F3FFFF, // regMask
- }
- },
-// F3x140 - SRI_to_XCS Token Count
-// bits[1:0] UpReqTok = 2
-// bits[3:2] DnReqTok = 1
-// bits[5:4] UpPreqTokC = 1
-// bits[7:6] DnPreqTok = 1
-// bits[9:8] UpRspTok = 3
-// bits[11:10] DnRspTok = 1
-// bits[13:12] IsocReqTok = 3
-// bits[15:14] IsocPreqTok = 1
-// bits[17:16] IsocRspTok = 3
-// bits[23:20] FreeTok = 12
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA), // platform Features
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
- 0x00C37756, // regData
- 0x00F3FFFF, // regMask
- }
- },
-// F3x140 - SRI_to_XCS Token Count
-// bits[1:0] UpReqTok = 2
-// bits[3:2] DnReqTok = 1
-// bits[5:4] UpPreqTokC = 1
-// bits[7:6] DnPreqTok = 1
-// bits[9:8] UpRspTok = 3
-// bits[11:10] DnRspTok = 1
-// bits[13:12] IsocReqTok = 3
-// bits[15:14] IsocPreqTok = 1
-// bits[17:16] IsocRspTok = 3
-// bits[23:20] FreeTok = 12
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM), // platform Features
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
- 0x00C37756, // regData
- 0x00F3FFFF, // regMask
- }
- },
-// F3x140 - SRI_to_XCS Token Count
-// bits[1:0] UpReqTok = 2
-// bits[3:2] DnReqTok = 1
-// bits[5:4] UpPreqTokC = 1
-// bits[7:6] DnPreqTok = 1
-// bits[9:8] UpRspTok = 2
-// bits[11:10] DnRspTok = 1
-// bits[13:12] IsocReqTok = 3
-// bits[15:14] IsocPreqTok = 1
-// bits[17:16] IsocRspTok = 3
-// bits[23:20] FreeTok = 12
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM), // platform Features
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
- 0x00C37656, // regData
- 0x00F3FFFF, // regMask
- }
- },
-// F3x144 - MCT to XCS Token Count
-// bits[3:0] RspTok = 3
-// bits[7:4] ProbeTok = 3
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM), // platform Features
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
- 0x00000033, // regData
- 0x000000FF, // regMask
- }
- },
-// F3x144 - MCT to XCS Token Count
-// bits[3:0] RspTok = 6
-// bits[7:4] ProbeTok = 3
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA), // platform Features
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
- 0x00000036, // regData
- 0x000000FF, // regMask
- }
- },
-// F3x144 - MCT to XCS Token Count
-// bits[3:0] RspTok = 6
-// bits[7:4] ProbeTok = 3
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM), // platform Features
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
- 0x00000036, // regData
- 0x000000FF, // regMask
- }
- },
-// F3x144 - MCT to XCS Token Count
-// bits[3:0] RspTok = 6
-// bits[7:4] ProbeTok = 3
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM), // platform Features
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
- 0x00000036, // regData
- 0x000000FF, // regMask
- }
- },
-// F3x148 - Link to XCS Token Count
-// bits[1:0] ReqTok0 = 2
-// bits[3:2] PReqTok0 = 2
-// bits[5:4] RspTok0 = 2
-// bits[7:6] ProbeTok0 = 2
-// bits[9:8] IsocReqTok0 = 0
-// bits[11:10] IsocPreqTok0 = 0
-// bits[13:12] IsocRspTok0 = 0
-// bits[15:14] FreeTok[1:0] = 3
-// bits[17:16] ReqTok1 = 0
-// bits[19:18] PReqTok1 = 0
-// bits[21:20] RspTok1 = 0
-// bits[23:22] ProbeTok1= 0
-// bits[24] IsocReqTok1 = 0
-// bits[25] IsocPreqTok1 = 0
-// bits[28] IsocRspTok1 = 0
-// bits[31:30] FreeTok[3:2] = 0
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM), // platform Features
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
- 0x0000C0AA, // regData
- 0xD5FFFFFF, // regMask
- }
- },
-// F3x148 - Link to XCS Token Count
-// bits[1:0] ReqTok0 = 2
-// bits[3:2] PReqTok0 = 2
-// bits[5:4] RspTok0 = 2
-// bits[7:6] ProbeTok0 = 0
-// bits[9:8] IsocReqTok0 = 1
-// bits[11:10] IsocPreqTok0 = 1
-// bits[13:12] IsocRspTok0 = 1
-// bits[15:14] FreeTok[1:0] = 0
-// bits[17:16] ReqTok1 = 0
-// bits[19:18] PReqTok1 = 0
-// bits[21:20] RspTok1 = 0
-// bits[23:22] ProbeTok1= 0
-// bits[24] IsocReqTok1 = 0
-// bits[25] IsocPreqTok1 = 0
-// bits[28] IsocRspTok1 = 0
-// bits[31:30] FreeTok[3:2] = 2
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA), // platform Features
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
- 0x8000152A, // regData
- 0xD5FFFFFF, // regMask
- }
- },
-// F3x148 - Link to XCS Token Count
-// bits[1:0] ReqTok0 = 2
-// bits[3:2] PReqTok0 = 2
-// bits[5:4] RspTok0 = 2
-// bits[7:6] ProbeTok0 = 0
-// bits[9:8] IsocReqTok0 = 1
-// bits[11:10] IsocPreqTok0 = 1
-// bits[13:12] IsocRspTok0 = 1
-// bits[15:14] FreeTok[1:0] = 0
-// bits[17:16] ReqTok1 = 0
-// bits[19:18] PReqTok1 = 0
-// bits[21:20] RspTok1 = 0
-// bits[23:22] ProbeTok1= 0
-// bits[24] IsocReqTok1 = 0
-// bits[25] IsocPreqTok1 = 0
-// bits[28] IsocRspTok1 = 0
-// bits[31:30] FreeTok[3:2] = 2
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM), // platform Features
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
- 0x8000152A, // regData
- 0xD5FFFFFF, // regMask
- }
- },
-// F3x148 - Link to XCS Token Count
-// bits[1:0] ReqTok0 = 2
-// bits[3:2] PReqTok0 = 2
-// bits[5:4] RspTok0 = 2
-// bits[7:6] ProbeTok0 = 2
-// bits[9:8] IsocReqTok0 = 0
-// bits[11:10] IsocPreqTok0 = 0
-// bits[13:12] IsocRspTok0 = 0
-// bits[15:14] FreeTok[1:0] = 3
-// bits[17:16] ReqTok1 = 0
-// bits[19:18] PReqTok1 = 0
-// bits[21:20] RspTok1 = 0
-// bits[23:22] ProbeTok1= 0
-// bits[24] IsocReqTok1 = 0
-// bits[25] IsocPreqTok1 = 0
-// bits[28] IsocRspTok1 = 0
-// bits[31:30] FreeTok[3:2] = 0
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM), // platform Features
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
- 0x0000C0AA, // regData
- 0xD5FFFFFF, // regMask
- }
- },
- // F3x158 - Link to XCS Token Count Registers
- // bits [3:0]LnkToXcsDRToken = 0
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_NFCM | AMD_PF_IFCM | AMD_PF_IOMMU),
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x158), // Address
- 0x00000000,
- 0x0000000F
- }
- },
- // F3x158 - Link to XCS Token Count Registers
- // bits [3:0]LnkToXcsDRToken = 3
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_UMA_IFCM | AMD_PF_UMA),
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x158), // Address
- 0x00000003,
- 0x0000000F
- }
- },
-};
-
-CONST REGISTER_TABLE ROMDATA F10SingleLinkPciRegisterTable = {
- PrimaryCores,
- (sizeof (F10SingleLinkPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
- F10SingleLinkPciRegisters,
-};
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c
deleted file mode 100644
index 4b8db7f..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c
+++ /dev/null
@@ -1,151 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU Cache Flush On Halt Function.
- *
- * Contains code to Level the Feature in a multi-socket system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/Family/0x10/BL
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuServices.h"
-#include "cpuFamilyTranslation.h"
-#include "GeneralServices.h"
-#include "cpuPostInit.h"
-#include "cpuFeatures.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLCACHEFLUSHONHALT_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P U B L I C F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- * Enable BL-C Cpu Cache Flush On Halt Function
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] EntryPoint Timepoint designator.
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Config Handle for library, services.
- */
-VOID
-SetF10BlCacheFlushOnHaltRegister (
- IN CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices,
- IN UINT64 EntryPoint,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 AndMask;
- UINT32 OrMask;
- UINT32 CoreCount;
- PCI_ADDR PciAddress;
- CPU_LOGICAL_ID CpuFamilyRevision;
-
- if ((EntryPoint & CPU_FEAT_AFTER_POST_MTRR_SYNC) != 0) {
- GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = CLOCK_POWER_TIMING_CTRL2_REG;
- if (CpuFamilyRevision.Revision == AMD_F10_BL_C3) {
- // F3xDC[25:19] = 04h
- // F3xDC[18:16] = 111b
- AndMask = 0xFC00FFFF;
- OrMask = 0x00270000;
- } else {
- // F3xDC[25:19] = 28h
- // F3xDC[18:16] = 111b
- AndMask = 0xFC00FFFF;
- OrMask = 0x01470000;
-
- //For BL_C2 single Core, F3xDC[18:16] = 0
- GetActiveCoresInCurrentSocket (&CoreCount, StdHeader);
- if (CoreCount == 1) {
- if (CpuFamilyRevision.Revision == AMD_F10_BL_C2) {
- OrMask = 0x01400000;
- }
- }
- }
-
- // Get the Or Mask value from IDS
- IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, &OrMask, StdHeader);
- ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xDC
- }
-}
-
-CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10BlCacheFlushOnHalt =
-{
- 0,
- SetF10BlCacheFlushOnHaltRegister
-};
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c
deleted file mode 100644
index 2b6dcf3..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 BL Equivalence Table related data
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/Family/0x10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLEQUIVALENCETABLE_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-STATIC CONST UINT16 ROMDATA CpuF10BlMicrocodeEquivalenceTable[] =
-{
- 0x1052, 0x1041,
- 0x1053, 0x1043
-};
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns the appropriate microcode patch equivalent ID table.
- *
- * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[out] BlEquivalenceTablePtr Points to the first entry in the table.
- * @param[out] NumberOfElements Number of valid entries in the table.
- * @param[in] StdHeader Header for library and services.
- *
- */
-VOID
-GetF10BlMicrocodeEquivalenceTable (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- OUT CONST VOID **BlEquivalenceTablePtr,
- OUT UINT8 *NumberOfElements,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- *NumberOfElements = ((sizeof (CpuF10BlMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
- *BlEquivalenceTablePtr = CpuF10BlMicrocodeEquivalenceTable;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlHtPhyTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlHtPhyTables.c
deleted file mode 100644
index 153e3e0..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlHtPhyTables.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 BL PCI tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLHTPHYTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-// HT Phy T a b l e s
-// -------------------------
-STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10BlHtPhyRegisters[] =
-{
-
-//
-// NOTE: This entry is here for making this array not to be empty.
-// This entry should be removed after adding another.
-//
-//
-// Deemphasis Settings
-//
-
-// For BL-C3, also set [7]TxLs23ClkGateEn.
-//deemphasis level DL1[20:16], DL2[12:8], DP1[4:0] PostCur1En[31] PostCur2En[30] PreCur1En[29] MapPostCur2En[6]
-// No deemphasis 00h 00h 00h 0 0 0 0
-// -3dB postcursor 12h 00h 00h 1 0 0 0
-// -6dB postcursor 1Fh 00h 00h 1 0 0 0
-// -8dB postcursor 1Fh 06h 00h 1 1 0 1
-// -11dB postcursor 1Fh 0Dh 00h 1 1 0 1
-// -11dB postcursor with
-// -8dB precursor 1Fh 06h 07h 1 1 1 1
-
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_BL_C3 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL_NONE,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0x00000080, // regData
- 0xE01F1FDF, // regMask
- }
- },
-};
-
-CONST REGISTER_TABLE ROMDATA F10BlHtPhyRegisterTable = {
- PrimaryCores,
- (sizeof (F10BlHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
- F10BlHtPhyRegisters
-};
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c
deleted file mode 100644
index 71ff7fa..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 BL Logical ID Table
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLLOGICALIDTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF10BlLogicalIdAndRevArray[] =
-{
- {
- 0x1052,
- AMD_F10_BL_C2
- },
- {
- 0x1053,
- AMD_F10_BL_C3
- }
-};
-
-VOID
-GetF10BlLogicalIdAndRev (
- OUT CONST CPU_LOGICAL_ID_XLAT **BlIdPtr,
- OUT UINT8 *NumberOfElements,
- OUT UINT64 *LogicalFamily,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- *NumberOfElements = (sizeof (CpuF10BlLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT));
- *BlIdPtr = CpuF10BlLogicalIdAndRevArray;
- *LogicalFamily = AMD_FAMILY_10_BL;
-}
-
-//CONST LOGICAL_ID_TABLE ROMDATA CpuF10BlLogicalIdAndRev =
-//{
-// (sizeof (CpuF10BlLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT)),
-// (CPU_LOGICAL_ID_XLAT *) &CpuF10BlLogicalIdAndRevArray
-//};
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c
deleted file mode 100644
index a6c3056..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 BL PCI tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/Family/0x10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMICROCODEPATCHTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-extern CONST MICROCODE_PATCHES ROMDATA *CpuF10BlMicroCodePatchArray[];
-extern CONST UINT8 ROMDATA CpuF10BlNumberOfMicrocodePatches;
-
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns a table containing the appropriate microcode patches.
- *
- * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[out] BlUcodePtr Points to the first entry in the table.
- * @param[out] NumberOfElements Number of valid entries in the table.
- * @param[in] StdHeader Header for library and services.
- *
- */
-VOID
-GetF10BlMicroCodePatchesStruct (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- OUT CONST VOID **BlUcodePtr,
- OUT UINT8 *NumberOfElements,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- *NumberOfElements = CpuF10BlNumberOfMicrocodePatches;
- *BlUcodePtr = &CpuF10BlMicroCodePatchArray[0];
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlMsrTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlMsrTables.c
deleted file mode 100644
index b894e71..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlMsrTables.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 BL, MSR tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMSRTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10BlMsrRegisters[] =
-{
-// M S R T a b l e s
-// ----------------------
-//
-// NOTE: This entry is here for making this array not to be empty.
-// This entry should be removed after adding another.
-//
-// MSR_LS_CFG (0xC0011020)
-// bit[1] = 0
- {
- MsrRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_GT_B0 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MSR_LS_CFG, // MSR Address
- 0x0000000000000000, // OR Mask
- (1 << 1), // NAND Mask
- }
- }
-};
-
-CONST REGISTER_TABLE ROMDATA F10BlMsrRegisterTable = {
- AllCores,
- (sizeof (F10BlMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
- (TABLE_ENTRY_FIELDS *) &F10BlMsrRegisters,
-};
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlPciTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlPciTables.c
deleted file mode 100644
index 5875acb..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/BL/F10BlPciTables.c
+++ /dev/null
@@ -1,197 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 BL PCI tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "F10PackageType.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLPCITABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-// P C I T a b l e s
-// ----------------------
-
-STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10BlPciRegisters[] =
-{
- // Function 0
-
-// F0x16C - Link Global Extended Control Register, Errata 351
-// bit[15:13] ForceFullT0 = 0
-// bit[5:0] T0Time = 0x14
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_BL_C2 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
- 0x00000014, // regData
- 0x0000E03F, // regMask
- }
- },
-// F0x16C - Link Global Extended Control Register
-// bit[7:6] InLnSt = 0x01
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_BL_C3 // CpuRevision
- },
- AMD_PF_SINGLE_LINK, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
- 0x00000040, // regData
- 0x000000C0, // regMask
- }
- },
-// F0x16C - Link Global Extended Control Register
-// bit[15:13] ForceFullT0 = 6
-// bit[9] RXCalEn = 1
-// bit[5:0] T0Time = 0x26
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_BL_C3 // CpuRevision
- },
- AMD_PF_SINGLE_LINK, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
- 0x0000C226, // regData
- 0x0000E23F, // regMask
- }
- },
-// F0x170 - Link Extended Control Register - Link 0, sublink 0
-// Errata 351 (only need to override single link case.)
-// bit[8] LS2En = 0,
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_BL_C2 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_0, 0x170), // Address
- 0x00000000, // regData
- 0x00000100, // regMask
- }
- },
-
-
-// F3x80 - ACPI Power State Control
-// ACPI FIDVID Change
-// bits[0] CpuPrbEn = 1
-// bits[1] NbLowPwrEn = 1
-// bits[2] NbGateEn = 0
-// bits[3] NbCofChg = 1
-// bits[4] AltVidEn = 0
-// bits[7:5] ClkDivisor = 0
- {
- HtFeatPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_BL_Cx // CpuRevision
- },
- AMD_PF_SINGLE_LINK, // platformFeatures
- {
- HT_HOST_FEATURES_ALL, // link feats
- PACKAGE_TYPE_S1G3_S1G4, // package type
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address
- 0x000B0000, // regData
- 0x00FF0000, // regMask
- }
- },
-// F3xA0 - Power Control Miscellaneous
-// bits[28] NbPstateForce = 1
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_BL_C3 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0), // Address
- 0x10000000, // regData
- 0x10000000, // regMask
- }
- }
-};
-
-CONST REGISTER_TABLE ROMDATA F10BlPciRegisterTable = {
- PrimaryCores,
- (sizeof (F10BlPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
- F10BlPciRegisters,
-};
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c
deleted file mode 100644
index f81615d..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU Cache Flush On Halt Function.
- *
- * Contains code to Level the Feature in a multi-socket system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/Family/0x10/DA
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuServices.h"
-#include "cpuFamilyTranslation.h"
-#include "GeneralServices.h"
-#include "cpuPostInit.h"
-#include "cpuFeatures.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DACACHEFLUSHONHALT_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P U B L I C F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- * Enable DA-C Cpu Cache Flush On Halt Function
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] EntryPoint Timepoint designator.
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Config Handle for library, services.
- */
-VOID
-SetF10DaCacheFlushOnHaltRegister (
- IN CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices,
- IN UINT64 EntryPoint,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 CoreCount;
- UINT32 AndMask;
- UINT32 OrMask;
- PCI_ADDR PciAddress;
- CPU_LOGICAL_ID LogicalId;
-
- if ((EntryPoint & CPU_FEAT_AFTER_POST_MTRR_SYNC) != 0) {
- // F3xDC[25:19] = 04h
- // F3xDC[18:16] = 111b
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = CLOCK_POWER_TIMING_CTRL2_REG;
- AndMask = 0xFC00FFFF;
- OrMask = 0x00270000;
-
- GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
- if (LogicalId.Revision == AMD_F10_DA_C2) {
- //For DA_C2 single Core, F3xDC[18:16] = 0
- GetActiveCoresInCurrentSocket (&CoreCount, StdHeader);
- if (CoreCount == 1) {
- OrMask = 0x00200000;
- }
- }
-
- IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, &OrMask, StdHeader);
- ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xDC
- }
-}
-
-CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10DaCacheFlushOnHalt =
-{
- 0,
- SetF10DaCacheFlushOnHaltRegister
-};
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c
deleted file mode 100644
index 765b6ec..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 DA Equivalence Table related data
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/Family/0x10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DAEQUIVALENCETABLE_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-STATIC CONST UINT16 ROMDATA CpuF10DaMicrocodeEquivalenceTable[] =
-{
- 0x1062, 0x1062,
- 0x1063, 0x1043
-};
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns the appropriate microcode patch equivalent ID table.
- *
- * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[out] DaEquivalenceTablePtr Points to the first entry in the table.
- * @param[out] NumberOfElements Number of valid entries in the table.
- * @param[in] StdHeader Header for library and services.
- *
- */
-VOID
-GetF10DaMicrocodeEquivalenceTable (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- OUT CONST VOID **DaEquivalenceTablePtr,
- OUT UINT8 *NumberOfElements,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- *NumberOfElements = ((sizeof (CpuF10DaMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
- *DaEquivalenceTablePtr = CpuF10DaMicrocodeEquivalenceTable;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaHtPhyTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaHtPhyTables.c
deleted file mode 100644
index c69a608..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaHtPhyTables.c
+++ /dev/null
@@ -1,284 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 DA PCI tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DAHTPHYTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-// HT Phy T a b l e s
-// -------------------------
-STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10DaHtPhyRegisters[] =
-{
-
-//
-// Deemphasis Settings
-//
-
-// For DA, also set [7]TxLs23ClkGateEn.
-//deemphasis level DL1[20:16], DL2[12:8], DP1[4:0] PostCur1En[31] PostCur2En[30] PreCur1En[29] MapPostCur2En[6]
-// No deemphasis 00h 00h 00h 0 0 0 0
-// -3dB postcursor 12h 00h 00h 1 0 0 0
-// -6dB postcursor 1Fh 00h 00h 1 0 0 0
-// -8dB postcursor 1Fh 06h 00h 1 1 0 1
-// -11dB postcursor 1Fh 0Dh 00h 1 1 0 1
-// -11dB postcursor with
-// -8dB precursor 1Fh 06h 07h 1 1 1 1
-
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C2 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL_NONE,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0x00000080, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C2 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL_NONE,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0x00000080, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C2 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__3,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0x80120080, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C2 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__3,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0x80120080, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C2 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__6,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0x801F0080, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C2 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__6,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0x801F0080, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C2 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__8,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0xC01F06C0, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C2 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__8,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0xC01F06C0, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C2 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__11,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0xC01F0DC0, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C2 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__11,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0xC01F0DC0, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C2 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__11_8,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0xE01F06C7, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C2 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__11_8,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0xE01F06C7, // regData
- 0xE01F1FDF, // regMask
- }
- },
-};
-
-CONST REGISTER_TABLE ROMDATA F10DaHtPhyRegisterTable = {
- PrimaryCores,
- (sizeof (F10DaHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
- F10DaHtPhyRegisters
-};
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c
deleted file mode 100644
index 406dec8..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 DA Logical ID Table
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DALOGICALIDTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF10DaLogicalIdAndRevArray[] =
-{
- {
- 0x1062,
- AMD_F10_DA_C2
- },
- {
- 0x1063,
- AMD_F10_DA_C3
- }
-};
-
-VOID
-GetF10DaLogicalIdAndRev (
- OUT CONST CPU_LOGICAL_ID_XLAT **DaIdPtr,
- OUT UINT8 *NumberOfElements,
- OUT UINT64 *LogicalFamily,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- *NumberOfElements = (sizeof (CpuF10DaLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT));
- *DaIdPtr = CpuF10DaLogicalIdAndRevArray;
- *LogicalFamily = AMD_FAMILY_10_DA;
-}
-
-//CONST LOGICAL_ID_TABLE ROMDATA CpuF10DaLogicalIdAndRev =
-//{
-// (sizeof (CpuF10DaLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT)),
-// (CPU_LOGICAL_ID_XLAT *) &CpuF10DaLogicalIdAndRevArray
-//};
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c
deleted file mode 100644
index 51665af..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 DA PCI tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/Family/0x10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMICROCODEPATCHTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-extern CONST MICROCODE_PATCHES ROMDATA *CpuF10DaMicroCodePatchArray[];
-extern CONST UINT8 ROMDATA CpuF10DaNumberOfMicrocodePatches;
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns a table containing the appropriate microcode patches.
- *
- * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[out] DaUcodePtr Points to the first entry in the table.
- * @param[out] NumberOfElements Number of valid entries in the table.
- * @param[in] StdHeader Header for library and services.
- *
- */
-VOID
-GetF10DaMicroCodePatchesStruct (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- OUT CONST VOID **DaUcodePtr,
- OUT UINT8 *NumberOfElements,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- *NumberOfElements = CpuF10DaNumberOfMicrocodePatches;
- *DaUcodePtr = &CpuF10DaMicroCodePatchArray[0];
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaMsrTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaMsrTables.c
deleted file mode 100644
index 82bc49e..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaMsrTables.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 DA, MSR tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMSRTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10DaMsrRegisters[] =
-{
-// M S R T a b l e s
-// ----------------------
-//
-// NOTE: This entry is here for making this array not to be empty.
-// This entry should be removed after adding another.
-//
-// MSR_LS_CFG (0xC0011020)
-// bit[1] = 0
- {
- MsrRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_GT_B0 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MSR_LS_CFG, // MSR Address
- 0x0000000000000000, // OR Mask
- (1 << 1), // NAND Mask
- }
- }
-};
-
-CONST REGISTER_TABLE ROMDATA F10DaMsrRegisterTable = {
- AllCores,
- (sizeof (F10DaMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
- (TABLE_ENTRY_FIELDS *) &F10DaMsrRegisters,
-};
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaPciTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaPciTables.c
deleted file mode 100644
index 1dfd967..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/DA/F10DaPciTables.c
+++ /dev/null
@@ -1,193 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 DA PCI tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "F10PackageType.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DAPCITABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-// P C I T a b l e s
-// ----------------------
-
-STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10DaPciRegisters[] =
-{
-// F0x16C - Link Global Extended Control Register
-// bit[7:6] InLnSt = 0x01
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_DA_ALL // CpuRevision
- },
- AMD_PF_SINGLE_LINK, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
- 0x00000040, // regData
- 0x000000C0, // regMask
- }
- },
-// F0x16C - Link Global Extended Control Register
-// bit[15:13] ForceFullT0 = 6
-// bit[9] RXCalEn = 1
-// bit[5:0] T0Time = 0x26
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_DA_ALL // CpuRevision
- },
- AMD_PF_SINGLE_LINK, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
- 0x0000C226, // regData
- 0x0000E23F, // regMask
- }
- },
-// F3x80 - ACPI Power State Control
-// ACPI FIDVID Change
-// bits[0] CpuPrbEn = 1
-// bits[1] NbLowPwrEn = 1
-// bits[2] NbGateEn = 0
-// bits[3] NbCofChg = 1
-// bits[4] AltVidEn = 0
-// bits[7:5] ClkDivisor = 0
- {
- HtFeatPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_DA_Cx // CpuRevision
- },
- AMD_PF_SINGLE_LINK, // platformFeatures
- {
- HT_HOST_FEATURES_ALL, // link feats
- PACKAGE_TYPE_S1G3_S1G4, // package type
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address
- 0x000B0000, // regData
- 0x00FF0000, // regMask
- }
- },
-// F3xA0 - Power Control Miscellaneous
-// bits[13:11] PllLockTime = 1
-// bits[28] NbPstateForce = 1
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_DA_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0), // Address
- 0x10000800, // regData
- 0x10003800, // regMask
- }
- },
-// F3xD4 - Clock Power/Timing Control 0 Register
-// bits[30:28] NbClkDiv = 5
- {
- HtFeatPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_DA_C2 // CpuRevision
- },
- AMD_PF_SINGLE_LINK, // platformFeatures
- {
- HT_HOST_FEAT_HT3, // link feats
- PACKAGE_TYPE_S1G3_S1G4, // package type
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD4), // Address
- 0x50000000, // regData
- 0x70000000, // regMask
- }
- },
-// F3x188 - NB Extended Configuration Low Register
-// bits[4] EnStpGntOnFlushMaskWakeup = 1
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_DA_Cx // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address
- 0x00000010, // regData
- 0x00000010, // regMask
- }
- }
-};
-
-CONST REGISTER_TABLE ROMDATA F10DaPciRegisterTable = {
- PrimaryCores,
- (sizeof (F10DaPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
- F10DaPciRegisters,
-};
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c
deleted file mode 100644
index 1c190f0..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c
+++ /dev/null
@@ -1,1038 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Microcode patch.
- *
- * Fam10 Microcode Patch rev 01000085 for 1040 or equivalent.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x10/REVC
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-// Patch code 01000085 for 1040 and equivalent
-CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch01000085 =
-{
-0x08,
-0x20,
-0x01,
-0x05,
-0x85,
-0x00,
-0x00,
-0x01,
-0x00,
-0x80,
-0x20,
-0x00,
-0xc1,
-0xb9,
-0x5d,
-0x3d,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x40,
-0x10,
-0x00,
-0x00,
-0x00,
-0xaa,
-0xaa,
-0xaa,
-0x2f,
-0x02,
-0x00,
-0x00,
-0xa0,
-0x09,
-0x00,
-0x00,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xcf,
-0xf8,
-0xff,
-0x2a,
-0xc3,
-0x3f,
-0xd5,
-0xfd,
-0xbc,
-0xff,
-0xff,
-0xb3,
-0x0f,
-0xff,
-0x58,
-0xd5,
-0xf0,
-0x35,
-0x95,
-0x03,
-0x1d,
-0xf8,
-0x63,
-0x7b,
-0x40,
-0x03,
-0xd4,
-0x00,
-0x80,
-0x77,
-0xff,
-0x7f,
-0xfe,
-0xe1,
-0x98,
-0x8a,
-0x54,
-0xfe,
-0xaf,
-0xff,
-0xff,
-0x87,
-0x7f,
-0xa9,
-0x03,
-0xf8,
-0x0f,
-0xfc,
-0xfc,
-0x1b,
-0xfe,
-0x01,
-0x00,
-0xe0,
-0xff,
-0x7b,
-0x1f,
-0xc0,
-0x65,
-0xf4,
-0x0d,
-0xf0,
-0xe0,
-0x8f,
-0xfe,
-0x04,
-0xde,
-0x04,
-0x03,
-0xad,
-0xc3,
-0x2f,
-0xfe,
-0xa9,
-0xfc,
-0x07,
-0x00,
-0x3f,
-0x0f,
-0xff,
-0x15,
-0x00,
-0xb0,
-0x00,
-0xf8,
-0xaf,
-0xe4,
-0x3f,
-0x07,
-0xf8,
-0x79,
-0xf8,
-0xfe,
-0xff,
-0x97,
-0xa7,
-0x1f,
-0xe0,
-0xe7,
-0xe1,
-0xbf,
-0xf1,
-0x00,
-0xfe,
-0x7f,
-0x6f,
-0x80,
-0x03,
-0x4a,
-0x1a,
-0x00,
-0xc8,
-0x1f,
-0xf8,
-0x07,
-0xf0,
-0xfc,
-0x03,
-0xf8,
-0x37,
-0x7f,
-0xe0,
-0x1f,
-0xc0,
-0xf0,
-0x0f,
-0xe0,
-0xdf,
-0xff,
-0x81,
-0x7f,
-0x00,
-0xc3,
-0x3f,
-0x80,
-0x7f,
-0xfc,
-0x7f,
-0x0f,
-0x00,
-0xf8,
-0x0f,
-0xfc,
-0x03,
-0x1b,
-0xfe,
-0x01,
-0xfc,
-0xe0,
-0x3f,
-0xf0,
-0x0f,
-0x6f,
-0xf8,
-0x07,
-0xf0,
-0x80,
-0xff,
-0xc0,
-0x3f,
-0xbf,
-0xe1,
-0x1f,
-0xc0,
-0x00,
-0xfe,
-0xbf,
-0x07,
-0x01,
-0xfc,
-0x07,
-0xfe,
-0xfe,
-0x0d,
-0xff,
-0x00,
-0x07,
-0xf0,
-0x1f,
-0xf8,
-0xf8,
-0x37,
-0xfc,
-0x03,
-0x1f,
-0xc0,
-0x7f,
-0xe0,
-0xe0,
-0xdf,
-0xf0,
-0x0f,
-0x03,
-0x00,
-0xff,
-0xdf,
-0xff,
-0x00,
-0xfe,
-0x03,
-0x00,
-0xff,
-0x86,
-0x7f,
-0xfc,
-0x03,
-0xf8,
-0x0f,
-0x01,
-0xfc,
-0x1b,
-0xfe,
-0xf0,
-0x0f,
-0xe0,
-0x3f,
-0x07,
-0xf0,
-0x6f,
-0xf8,
-0xef,
-0x01,
-0x80,
-0xff,
-0x81,
-0x7f,
-0x00,
-0xff,
-0x3f,
-0x80,
-0x7f,
-0xc3,
-0x07,
-0xfe,
-0x01,
-0xfc,
-0xff,
-0x00,
-0xfe,
-0x0d,
-0x1f,
-0xf8,
-0x07,
-0xf0,
-0xfc,
-0x03,
-0xf8,
-0x37,
-0xff,
-0xf7,
-0x00,
-0xc0,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x1f,
-0xc0,
-0xbf,
-0xfe,
-0x03,
-0xff,
-0x00,
-0x86,
-0x7f,
-0x00,
-0xff,
-0xf8,
-0x0f,
-0xfc,
-0x03,
-0x1b,
-0xfe,
-0x01,
-0xfc,
-0xe0,
-0xff,
-0x7b,
-0x00,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x01,
-0xfc,
-0x07,
-0xfe,
-0xfe,
-0x0d,
-0xff,
-0x00,
-0x00,
-0xf0,
-0xff,
-0x3d,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0xff,
-0x00,
-0xfe,
-0x03,
-0x00,
-0xff,
-0x86,
-0x7f,
-0x1e,
-0x00,
-0xf8,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0x81,
-0x7f,
-0x00,
-0xff,
-0x3f,
-0x80,
-0x7f,
-0xc3,
-0x7f,
-0x0f,
-0x00,
-0xfc,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x1f,
-0xc0,
-0xbf,
-0xfe,
-0xbf,
-0x07,
-0x00,
-0xfc,
-0x07,
-0xfe,
-0x01,
-0x0d,
-0xff,
-0x00,
-0xfe,
-0xf0,
-0x1f,
-0xf8,
-0x07,
-0x37,
-0xfc,
-0x03,
-0xf8,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0xdf,
-0x03,
-0x00,
-0xfe,
-0x03,
-0xff,
-0xff,
-0x86,
-0x7f,
-0x00,
-0x03,
-0xf8,
-0x0f,
-0xfc,
-0xfc,
-0x1b,
-0xfe,
-0x01,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x01,
-0x80,
-0xff,
-0xef,
-0x7f,
-0x00,
-0xff,
-0x81,
-0x80,
-0x7f,
-0xc3,
-0x3f,
-0xfe,
-0x01,
-0xfc,
-0x07,
-0x00,
-0xfe,
-0x0d,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xd7,
-0x00,
-0x80,
-0xfb,
-0xc0,
-0x3f,
-0x80,
-0xff,
-0x1f,
-0xc0,
-0xbf,
-0xe1,
-0x03,
-0xff,
-0x00,
-0xfe,
-0x7f,
-0x00,
-0xff,
-0x86,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0xfd,
-0x6b,
-0x00,
-0xa0,
-0xcf,
-0x56,
-0x0e,
-0x80,
-0xe0,
-0x0f,
-0xe8,
-0x75,
-0xf6,
-0xff,
-0xff,
-0x00,
-0xc3,
-0xbb,
-0x16,
-0xf2,
-0x04,
-0x37,
-0xf8,
-0x13,
-0x0e,
-0x7f,
-0x0c,
-0xb8,
-0xe0,
-0xdc,
-0x35,
-0x00,
-0x60,
-0xff,
-0xff,
-0x1f,
-0x7f,
-0x78,
-0xc7,
-0xa2,
-0x95,
-0xff,
-0xe9,
-0x3f,
-0xdf,
-0xe0,
-0xcf,
-0x2a,
-0x00,
-0xfe,
-0x03,
-0xff,
-0xff,
-0x86,
-0x7f,
-0x00,
-0x00,
-0xf8,
-0xff,
-0x1e,
-0xff,
-0xf2,
-0xbf,
-0xff,
-0xfd,
-0x1f,
-0xfc,
-0x7b,
-0x0f,
-0xc0,
-0x23,
-0xd0,
-0xed,
-0xf5,
-0xe0,
-0xef,
-0x7f,
-0x00,
-0xff,
-0x81,
-0x80,
-0x7f,
-0xc3,
-0x3f,
-0x0f,
-0x00,
-0xfc,
-0x7f,
-0xfe,
-0x03,
-0xf9,
-0x5f,
-0x01,
-0x7e,
-0x1e,
-0xfe,
-0xf0,
-0x0f,
-0xe0,
-0x3f,
-0x07,
-0xf0,
-0x6f,
-0xf8,
-0xc0,
-0x3f,
-0x80,
-0xff,
-0x1f,
-0xc0,
-0xbf,
-0xe1,
-0x4c,
-0x06,
-0x00,
-0xbc,
-0x07,
-0xfe,
-0x01,
-0xfc,
-0xff,
-0x00,
-0xfe,
-0x0d,
-0x1f,
-0xf8,
-0x07,
-0xf0,
-0xfc,
-0x03,
-0xf8,
-0x37,
-0x7f,
-0xe0,
-0x1f,
-0xc0,
-0xf0,
-0x0f,
-0xe0,
-0xdf,
-0xff,
-0xdf,
-0x03,
-0x00,
-0xfe,
-0x03,
-0xff,
-0x00,
-0x86,
-0x7f,
-0x00,
-0xff,
-0xf8,
-0x0f,
-0xfc,
-0x03,
-0x1b,
-0xfe,
-0x01,
-0xfc,
-0xe0,
-0x3f,
-0xf0,
-0x0f,
-0x6f,
-0xf8,
-0x07,
-0xf0,
-0x80,
-0xff,
-0xef,
-0x01,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x01,
-0xfc,
-0x07,
-0xfe,
-0xfe,
-0x0d,
-0xff,
-0x00,
-0x07,
-0xf0,
-0x1f,
-0xf8,
-0xf8,
-0x37,
-0xfc,
-0x03,
-0x00,
-0xc0,
-0xff,
-0xf7,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0xff,
-0x00,
-0xfe,
-0x03,
-0x00,
-0xff,
-0x86,
-0x7f,
-0xfc,
-0x03,
-0xf8,
-0x0f,
-0x01,
-0xfc,
-0x1b,
-0xfe,
-0x7b,
-0x00,
-0xe0,
-0xff,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0x81,
-0x7f,
-0x00,
-0xff,
-0x3f,
-0x80,
-0x7f,
-0xc3,
-0x07,
-0xfe,
-0x01,
-0xfc,
-0xff,
-0x00,
-0xfe,
-0x0d,
-0xff,
-0x3d,
-0x00,
-0xf0,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x1f,
-0xc0,
-0xbf,
-0xfe,
-0x03,
-0xff,
-0x00,
-0x86,
-0x7f,
-0x00,
-0xff,
-0xf8,
-0xff,
-0x1e,
-0x00,
-0xf0,
-0x1f,
-0xf8,
-0x07,
-0x37,
-0xfc,
-0x03,
-0xf8,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x00,
-0xfc,
-0x7f,
-0x0f,
-0x03,
-0xf8,
-0x0f,
-0xfc,
-0xfc,
-0x1b,
-0xfe,
-0x01,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0x07,
-0x00,
-0xfe,
-0xbf,
-0xfe,
-0x01,
-0xfc,
-0x07,
-0x00,
-0xfe,
-0x0d,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0xdf,
-0x03,
-0x00,
-0xff,
-0x03,
-0xff,
-0x00,
-0xfe,
-0x7f,
-0x00,
-0xff,
-0x86,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xef,
-0x01,
-0x80
-};
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c6.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c6.c
deleted file mode 100644
index d8ae5d8..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c6.c
+++ /dev/null
@@ -1,1038 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Microcode patch.
- *
- * Fam10 Microcode Patch rev 010000c6 for 1041 or equivalent.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x10/REVC
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-// Patch code 010000c6 for 1041 and equivalent
-CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c6 =
-{
-0x10,
-0x20,
-0x11,
-0x03,
-0xc6,
-0x00,
-0x00,
-0x01,
-0x00,
-0x80,
-0x20,
-0x00,
-0xb5,
-0x66,
-0x0e,
-0x84,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x41,
-0x10,
-0x00,
-0x00,
-0x00,
-0xaa,
-0xaa,
-0xaa,
-0xa0,
-0x09,
-0x00,
-0x00,
-0xa5,
-0x09,
-0x00,
-0x00,
-0xff,
-0xff,
-0xff,
-0xff,
-0xa1,
-0x09,
-0x00,
-0x00,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0x97,
-0xd1,
-0x7f,
-0x00,
-0x83,
-0x3f,
-0x36,
-0xc0,
-0xa0,
-0x1b,
-0xf8,
-0x13,
-0x0e,
-0xbf,
-0x0c,
-0xb4,
-0xf2,
-0x1f,
-0xf8,
-0xa7,
-0x3c,
-0xfc,
-0x03,
-0xfc,
-0x40,
-0x03,
-0x54,
-0x00,
-0x92,
-0xff,
-0xe0,
-0xbf,
-0xe7,
-0xe1,
-0x1f,
-0xe0,
-0x5f,
-0x9e,
-0xfa,
-0xff,
-0x9f,
-0x87,
-0x7f,
-0x80,
-0x03,
-0xf8,
-0xff,
-0xc6,
-0x01,
-0x0e,
-0xfc,
-0xbd,
-0x00,
-0xa0,
-0x2a,
-0x69,
-0x0e,
-0x40,
-0xbd,
-0x55,
-0xe0,
-0x73,
-0xd0,
-0x0f,
-0xff,
-0x00,
-0xe0,
-0xff,
-0x13,
-0xf2,
-0xc3,
-0xbb,
-0xff,
-0x8b,
-0xf8,
-0xff,
-0x44,
-0x59,
-0x0e,
-0x7f,
-0x34,
-0x00,
-0x00,
-0x5a,
-0xfb,
-0x07,
-0xe0,
-0xfb,
-0xc7,
-0x06,
-0x38,
-0xf0,
-0xfe,
-0x7f,
-0x94,
-0x9b,
-0x1f,
-0xe0,
-0xe7,
-0xe1,
-0x03,
-0xff,
-0x00,
-0xfe,
-0x7f,
-0x00,
-0xff,
-0x86,
-0xff,
-0x1e,
-0x00,
-0xe8,
-0xff,
-0x8c,
-0x07,
-0xf0,
-0xf4,
-0x43,
-0xf9,
-0x3c,
-0x7e,
-0x33,
-0x0e,
-0xc0,
-0xd0,
-0x0f,
-0xe5,
-0xf3,
-0xf7,
-0xcb,
-0x38,
-0x00,
-0x43,
-0x3f,
-0x94,
-0xcf,
-0x1c,
-0x9c,
-0x0c,
-0x00,
-0xf8,
-0x0f,
-0xfc,
-0x03,
-0x1b,
-0xfe,
-0x01,
-0xfc,
-0xe0,
-0x3f,
-0xf0,
-0x0f,
-0x6f,
-0xf8,
-0x07,
-0xf0,
-0x80,
-0xff,
-0xc0,
-0x3f,
-0xbf,
-0xe1,
-0x1f,
-0xc0,
-0x00,
-0xfe,
-0xbf,
-0x07,
-0x03,
-0xf4,
-0xff,
-0xff,
-0xc8,
-0x0f,
-0xef,
-0x52,
-0x4f,
-0xf0,
-0xbf,
-0xe0,
-0xe0,
-0x3a,
-0xfc,
-0x31,
-0x0f,
-0xc0,
-0xd3,
-0xd5,
-0x0c,
-0x70,
-0xe0,
-0xcf,
-0x03,
-0x00,
-0x5c,
-0x56,
-0x7f,
-0x00,
-0xae,
-0x97,
-0x6c,
-0x80,
-0x03,
-0x7f,
-0xfe,
-0x01,
-0x78,
-0x6e,
-0xb1,
-0x01,
-0x0e,
-0xfc,
-0xf9,
-0x07,
-0xe0,
-0xf7,
-0xc7,
-0x06,
-0x38,
-0xf0,
-0x8b,
-0x01,
-0x00,
-0x61,
-0x81,
-0x7f,
-0x00,
-0xff,
-0x3f,
-0x80,
-0x7f,
-0xc3,
-0x07,
-0xfe,
-0x01,
-0xfc,
-0xff,
-0x00,
-0xfe,
-0x0d,
-0x1f,
-0xf8,
-0x07,
-0xf0,
-0xfc,
-0x03,
-0xf8,
-0x37,
-0xff,
-0xf7,
-0x00,
-0xc0,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x1f,
-0xc0,
-0xbf,
-0xfe,
-0x03,
-0xff,
-0x00,
-0x86,
-0x7f,
-0x00,
-0xff,
-0xf8,
-0x0f,
-0xfc,
-0x03,
-0x1b,
-0xfe,
-0x01,
-0xfc,
-0xe0,
-0xff,
-0x7b,
-0x00,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x01,
-0xfc,
-0x07,
-0xfe,
-0xfe,
-0x0d,
-0xff,
-0x00,
-0x00,
-0xf0,
-0xff,
-0x3d,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0xff,
-0x00,
-0xfe,
-0x03,
-0x00,
-0xff,
-0x86,
-0x7f,
-0x1e,
-0x00,
-0xf8,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0x81,
-0x7f,
-0x00,
-0xff,
-0x3f,
-0x80,
-0x7f,
-0xc3,
-0x7f,
-0x0f,
-0x00,
-0xfc,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x1f,
-0xc0,
-0xbf,
-0xfe,
-0xbf,
-0x07,
-0x00,
-0xfc,
-0x07,
-0xfe,
-0x01,
-0x0d,
-0xff,
-0x00,
-0xfe,
-0xf0,
-0x1f,
-0xf8,
-0x07,
-0x37,
-0xfc,
-0x03,
-0xf8,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0xdf,
-0x03,
-0x00,
-0xfe,
-0x03,
-0xff,
-0xff,
-0x86,
-0x7f,
-0x00,
-0x03,
-0xf8,
-0x0f,
-0xfc,
-0xfc,
-0x1b,
-0xfe,
-0x01,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x01,
-0x80,
-0xff,
-0xef,
-0x7f,
-0x00,
-0xff,
-0x81,
-0x80,
-0x7f,
-0xc3,
-0x3f,
-0xfe,
-0x01,
-0xfc,
-0x07,
-0x00,
-0xfe,
-0x0d,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xd7,
-0x00,
-0x80,
-0xfb,
-0xc0,
-0x3f,
-0x80,
-0xff,
-0x1f,
-0xc0,
-0xbf,
-0xe1,
-0x03,
-0xff,
-0x00,
-0xfe,
-0x7f,
-0x00,
-0xff,
-0x86,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0xfd,
-0x6b,
-0x00,
-0xa0,
-0xff,
-0xfe,
-0xff,
-0xcb,
-0xf0,
-0xef,
-0xf5,
-0x7f,
-0x8f,
-0x40,
-0x3f,
-0x00,
-0x83,
-0xbf,
-0xb7,
-0xd7,
-0xfc,
-0x07,
-0xfe,
-0x01,
-0x0d,
-0xff,
-0x00,
-0xfe,
-0xf0,
-0xff,
-0x3d,
-0x00,
-0xe4,
-0x7f,
-0xf9,
-0x0f,
-0x79,
-0xf8,
-0x07,
-0xf8,
-0x80,
-0xff,
-0xc0,
-0x3f,
-0xbf,
-0xe1,
-0x1f,
-0xc0,
-0x00,
-0xfe,
-0x03,
-0xff,
-0xff,
-0x86,
-0x7f,
-0x00,
-0x00,
-0xf0,
-0x32,
-0x19,
-0x07,
-0xf0,
-0x1f,
-0xf8,
-0xf8,
-0x37,
-0xfc,
-0x03,
-0x1f,
-0xc0,
-0x7f,
-0xe0,
-0xe0,
-0xdf,
-0xf0,
-0x0f,
-0x7f,
-0x00,
-0xff,
-0x81,
-0x80,
-0x7f,
-0xc3,
-0x3f,
-0x0f,
-0x00,
-0xfc,
-0x7f,
-0xfc,
-0x03,
-0xf8,
-0x0f,
-0x01,
-0xfc,
-0x1b,
-0xfe,
-0xf0,
-0x0f,
-0xe0,
-0x3f,
-0x07,
-0xf0,
-0x6f,
-0xf8,
-0xc0,
-0x3f,
-0x80,
-0xff,
-0x1f,
-0xc0,
-0xbf,
-0xe1,
-0xbf,
-0x07,
-0x00,
-0xfe,
-0x07,
-0xfe,
-0x01,
-0xfc,
-0xff,
-0x00,
-0xfe,
-0x0d,
-0x1f,
-0xf8,
-0x07,
-0xf0,
-0xfc,
-0x03,
-0xf8,
-0x37,
-0x7f,
-0xe0,
-0x1f,
-0xc0,
-0xf0,
-0x0f,
-0xe0,
-0xdf,
-0xff,
-0xdf,
-0x03,
-0x00,
-0xfe,
-0x03,
-0xff,
-0x00,
-0x86,
-0x7f,
-0x00,
-0xff,
-0xf8,
-0x0f,
-0xfc,
-0x03,
-0x1b,
-0xfe,
-0x01,
-0xfc,
-0xe0,
-0x3f,
-0xf0,
-0x0f,
-0x6f,
-0xf8,
-0x07,
-0xf0,
-0x80,
-0xff,
-0xef,
-0x01,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x01,
-0xfc,
-0x07,
-0xfe,
-0xfe,
-0x0d,
-0xff,
-0x00,
-0x07,
-0xf0,
-0x1f,
-0xf8,
-0xf8,
-0x37,
-0xfc,
-0x03,
-0x00,
-0xc0,
-0xff,
-0xf7,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0xff,
-0x00,
-0xfe,
-0x03,
-0x00,
-0xff,
-0x86,
-0x7f,
-0xfc,
-0x03,
-0xf8,
-0x0f,
-0x01,
-0xfc,
-0x1b,
-0xfe,
-0x7b,
-0x00,
-0xe0,
-0xff,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0x81,
-0x7f,
-0x00,
-0xff,
-0x3f,
-0x80,
-0x7f,
-0xc3,
-0x07,
-0xfe,
-0x01,
-0xfc,
-0xff,
-0x00,
-0xfe,
-0x0d,
-0xff,
-0x3d,
-0x00,
-0xf0,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x1f,
-0xc0,
-0xbf,
-0xfe,
-0x03,
-0xff,
-0x00,
-0x86,
-0x7f,
-0x00,
-0xff,
-0xf8,
-0xff,
-0x1e,
-0x00,
-0xf0,
-0x1f,
-0xf8,
-0x07,
-0x37,
-0xfc,
-0x03,
-0xf8,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x00,
-0xfc,
-0x7f,
-0x0f,
-0x03,
-0xf8,
-0x0f,
-0xfc,
-0xfc,
-0x1b,
-0xfe,
-0x01,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0x07,
-0x00,
-0xfe,
-0xbf,
-0xfe,
-0x01,
-0xfc,
-0x07,
-0x00,
-0xfe,
-0x0d,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0xdf,
-0x03,
-0x00,
-0xff,
-0x03,
-0xff,
-0x00,
-0xfe,
-0x7f,
-0x00,
-0xff,
-0x86,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xef,
-0x01,
-0x80
-};
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c7.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c7.c
deleted file mode 100644
index fe09593..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c7.c
+++ /dev/null
@@ -1,1038 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Microcode patch.
- *
- * Fam10 Microcode Patch rev 010000c7 for 1062 or equivalent.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x10/REVC
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-// Patch code 010000c7 for 1062 and equivalent
-CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c7 =
-{
-0x10,
-0x20,
-0x11,
-0x03,
-0xc7,
-0x00,
-0x00,
-0x01,
-0x00,
-0x80,
-0x20,
-0x00,
-0xb8,
-0x53,
-0x63,
-0x1d,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x62,
-0x10,
-0x00,
-0x00,
-0x00,
-0xaa,
-0xaa,
-0xaa,
-0x9a,
-0x0b,
-0x00,
-0x00,
-0x16,
-0x0c,
-0x00,
-0x00,
-0x55,
-0x03,
-0x00,
-0x00,
-0xff,
-0xff,
-0xff,
-0xff,
-0x51,
-0x03,
-0x00,
-0x00,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0x6f,
-0x58,
-0x39,
-0x00,
-0x81,
-0x3f,
-0xa0,
-0xd7,
-0x04,
-0x00,
-0xfc,
-0xb7,
-0x0f,
-0xff,
-0x58,
-0xf7,
-0x72,
-0xc0,
-0xff,
-0x6f,
-0x3c,
-0xfc,
-0x03,
-0xfc,
-0xc0,
-0x18,
-0xd5,
-0x00,
-0x80,
-0xff,
-0x66,
-0x3c,
-0xeb,
-0xc0,
-0x9f,
-0xd9,
-0x4d,
-0xee,
-0xf8,
-0xff,
-0xff,
-0x83,
-0x7f,
-0xa6,
-0x07,
-0xe8,
-0xff,
-0xff,
-0xe8,
-0x1f,
-0xbe,
-0xb5,
-0x00,
-0x60,
-0x2f,
-0x6a,
-0xbf,
-0xe8,
-0x04,
-0xff,
-0xf5,
-0xf3,
-0xf0,
-0xaf,
-0x7a,
-0x00,
-0xff,
-0xd9,
-0x31,
-0xc0,
-0x83,
-0x3f,
-0xff,
-0x03,
-0x88,
-0xff,
-0x58,
-0xc8,
-0x0f,
-0xef,
-0x35,
-0x00,
-0xd0,
-0x00,
-0xfb,
-0xbf,
-0x85,
-0xff,
-0x03,
-0xd8,
-0x72,
-0xf8,
-0xad,
-0x1c,
-0x80,
-0xfb,
-0x1f,
-0xc0,
-0xe7,
-0xa0,
-0xbe,
-0x71,
-0x00,
-0x86,
-0x7f,
-0x40,
-0xaf,
-0x07,
-0xff,
-0x1e,
-0x00,
-0xf8,
-0x6f,
-0x95,
-0x03,
-0x50,
-0xf4,
-0x03,
-0xf8,
-0x1c,
-0xf8,
-0xff,
-0x3f,
-0x00,
-0xf0,
-0xee,
-0x84,
-0xfc,
-0xfe,
-0xff,
-0xff,
-0x22,
-0xc3,
-0x1f,
-0x51,
-0x96,
-0x50,
-0x16,
-0x0d,
-0x00,
-0xf8,
-0xfe,
-0xfe,
-0x01,
-0x0e,
-0xfc,
-0xb1,
-0x01,
-0xe5,
-0xa6,
-0xff,
-0x1f,
-0x79,
-0xf8,
-0x07,
-0xf8,
-0x80,
-0xff,
-0xc0,
-0x3f,
-0xbf,
-0xe1,
-0x1f,
-0xc0,
-0x00,
-0xfa,
-0xbf,
-0x07,
-0x01,
-0xfc,
-0x3f,
-0xe3,
-0x3e,
-0x0f,
-0xfd,
-0x50,
-0x03,
-0xb0,
-0xdf,
-0x8c,
-0xf9,
-0x3c,
-0xf4,
-0x43,
-0x0e,
-0xc0,
-0xfd,
-0x32,
-0xe5,
-0xf3,
-0xd0,
-0x0f,
-0x03,
-0x00,
-0xfb,
-0x24,
-0xff,
-0x00,
-0xfe,
-0x03,
-0x00,
-0xff,
-0x86,
-0x7f,
-0xfc,
-0x03,
-0xf8,
-0x0f,
-0x01,
-0xfc,
-0x1b,
-0xfe,
-0xf0,
-0x0f,
-0xe0,
-0x3f,
-0x07,
-0xf0,
-0x6f,
-0xf8,
-0xef,
-0x01,
-0x80,
-0xff,
-0xff,
-0xff,
-0x00,
-0xfd,
-0xbb,
-0x14,
-0xf2,
-0xc3,
-0x2f,
-0xf8,
-0x13,
-0xcc,
-0x7f,
-0x0c,
-0xb8,
-0x0e,
-0x74,
-0xf5,
-0x03,
-0xf0,
-0xf8,
-0x33,
-0x03,
-0x1c,
-0x2b,
-0xd7,
-0x00,
-0x00,
-0xeb,
-0xe5,
-0x1f,
-0x80,
-0xc0,
-0x1f,
-0x1b,
-0xe0,
-0x9e,
-0x9b,
-0x7f,
-0x00,
-0x03,
-0x7f,
-0x6c,
-0x80,
-0xf8,
-0x7d,
-0xfe,
-0x01,
-0x0e,
-0xfc,
-0xb1,
-0x01,
-0xe0,
-0x6d,
-0x62,
-0x00,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x01,
-0xfc,
-0x07,
-0xfe,
-0xfe,
-0x0d,
-0xff,
-0x00,
-0x00,
-0xf0,
-0xff,
-0x3d,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0xff,
-0x00,
-0xfe,
-0x03,
-0x00,
-0xff,
-0x86,
-0x7f,
-0x1e,
-0x00,
-0xf8,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0x81,
-0x7f,
-0x00,
-0xff,
-0x3f,
-0x80,
-0x7f,
-0xc3,
-0x7f,
-0x0f,
-0x00,
-0xfc,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x1f,
-0xc0,
-0xbf,
-0xfe,
-0xbf,
-0x07,
-0x00,
-0xfc,
-0x07,
-0xfe,
-0x01,
-0x0d,
-0xff,
-0x00,
-0xfe,
-0xf0,
-0x1f,
-0xf8,
-0x07,
-0x37,
-0xfc,
-0x03,
-0xf8,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0xdf,
-0x03,
-0x00,
-0xfe,
-0x03,
-0xff,
-0xff,
-0x86,
-0x7f,
-0x00,
-0x03,
-0xf8,
-0x0f,
-0xfc,
-0xfc,
-0x1b,
-0xfe,
-0x01,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x01,
-0x80,
-0xff,
-0xef,
-0x7f,
-0x00,
-0xff,
-0x81,
-0x80,
-0x7f,
-0xc3,
-0x3f,
-0xfe,
-0x01,
-0xfc,
-0x07,
-0x00,
-0xfe,
-0x0d,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xd7,
-0x00,
-0x00,
-0xfa,
-0xc0,
-0x3f,
-0x80,
-0xff,
-0x1f,
-0xc0,
-0xbf,
-0xe1,
-0x03,
-0xff,
-0x00,
-0xfe,
-0x7f,
-0x00,
-0xff,
-0x86,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0xfc,
-0x6b,
-0x00,
-0xe0,
-0xfc,
-0xff,
-0x3f,
-0xcb,
-0xf0,
-0x8f,
-0x75,
-0xff,
-0xe5,
-0xff,
-0xff,
-0x2c,
-0xc3,
-0x3f,
-0xd6,
-0xf5,
-0x1c,
-0xf0,
-0xff,
-0x8b,
-0x0f,
-0xff,
-0x00,
-0x3f,
-0xf0,
-0xff,
-0x3d,
-0x00,
-0xe0,
-0xbf,
-0x18,
-0x0f,
-0x3a,
-0xf0,
-0x27,
-0xf6,
-0xd1,
-0x35,
-0xfe,
-0x7f,
-0xe7,
-0xe1,
-0x9f,
-0xe8,
-0x5f,
-0xc6,
-0xff,
-0xff,
-0xeb,
-0x87,
-0x7f,
-0xaf,
-0x00,
-0xf8,
-0xff,
-0x1e,
-0x07,
-0xf0,
-0xbf,
-0xad,
-0x03,
-0x3c,
-0xf8,
-0x13,
-0x1f,
-0xc0,
-0x7f,
-0xf6,
-0x45,
-0xff,
-0xf0,
-0xad,
-0xff,
-0x04,
-0xff,
-0xff,
-0x83,
-0xad,
-0xc3,
-0x2f,
-0x04,
-0x00,
-0x2c,
-0x80,
-0xfe,
-0x03,
-0xf8,
-0xff,
-0xb5,
-0xe8,
-0x1f,
-0xbe,
-0xff,
-0xdf,
-0x65,
-0xfc,
-0x07,
-0x38,
-0x6b,
-0xf8,
-0xee,
-0xbf,
-0x96,
-0xff,
-0x5f,
-0xeb,
-0xff,
-0xe1,
-0xbf,
-0x07,
-0x00,
-0xfe,
-0x07,
-0xfe,
-0xb5,
-0xfc,
-0xbf,
-0x5a,
-0x57,
-0x0e,
-0xbf,
-0xad,
-0x07,
-0xf0,
-0xf4,
-0x13,
-0xf9,
-0x3c,
-0xf8,
-0x80,
-0x3f,
-0x81,
-0xf0,
-0xcb,
-0x60,
-0xeb,
-0xff,
-0xdf,
-0x03,
-0x00,
-0xfe,
-0xb7,
-0xf5,
-0x00,
-0x07,
-0x7f,
-0x62,
-0x80,
-0xf8,
-0x0f,
-0xfc,
-0x03,
-0x1f,
-0xbe,
-0xb5,
-0xe8,
-0x60,
-0x7c,
-0xc0,
-0x9f,
-0x75,
-0xf8,
-0x65,
-0xb0,
-0x00,
-0x04,
-0x90,
-0x00,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x01,
-0xfc,
-0x07,
-0xfe,
-0xfe,
-0x0d,
-0xff,
-0x00,
-0x07,
-0xf0,
-0x1f,
-0xf8,
-0xf8,
-0x37,
-0xfc,
-0x03,
-0x00,
-0xc0,
-0xff,
-0xf7,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0xff,
-0x00,
-0xfe,
-0x03,
-0x00,
-0xff,
-0x86,
-0x7f,
-0xfc,
-0x03,
-0xf8,
-0x0f,
-0x01,
-0xfc,
-0x1b,
-0xfe,
-0x7b,
-0x00,
-0xe0,
-0xff,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0x81,
-0x7f,
-0x00,
-0xff,
-0x3f,
-0x80,
-0x7f,
-0xc3,
-0x07,
-0xfe,
-0x01,
-0xfc,
-0xff,
-0x00,
-0xfe,
-0x0d,
-0xff,
-0x3d,
-0x00,
-0xf0,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x1f,
-0xc0,
-0xbf,
-0xfe,
-0x03,
-0xff,
-0x00,
-0x86,
-0x7f,
-0x00,
-0xff,
-0xf8,
-0xff,
-0x1e,
-0x00,
-0xf0,
-0x1f,
-0xf8,
-0x07,
-0x37,
-0xfc,
-0x03,
-0xf8,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x00,
-0xfc,
-0x7f,
-0x0f,
-0x03,
-0xf8,
-0x0f,
-0xfc,
-0xfc,
-0x1b,
-0xfe,
-0x01,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0x07,
-0x00,
-0xfe,
-0xbf,
-0xfe,
-0x01,
-0xfc,
-0x07,
-0x00,
-0xfe,
-0x0d,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0xdf,
-0x03,
-0x00,
-0xff,
-0x03,
-0xff,
-0x00,
-0xfe,
-0x7f,
-0x00,
-0xff,
-0x86,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xef,
-0x01,
-0x80
-};
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c8.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c8.c
deleted file mode 100644
index 71e27b1..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c8.c
+++ /dev/null
@@ -1,1038 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Microcode patch.
- *
- * Fam10 Microcode Patch rev 010000c8 for 1043 or equivalent.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x10/REVC
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-// Patch code 010000c8 for 1043 and equivalent
-CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c8 =
-{
-0x10,
-0x20,
-0x11,
-0x03,
-0xc8,
-0x00,
-0x00,
-0x01,
-0x00,
-0x80,
-0x20,
-0x00,
-0x6a,
-0x99,
-0x77,
-0xef,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x43,
-0x10,
-0x00,
-0x00,
-0x00,
-0xaa,
-0xaa,
-0xaa,
-0x10,
-0x0c,
-0x00,
-0x00,
-0x55,
-0x03,
-0x00,
-0x00,
-0xff,
-0xff,
-0xff,
-0xff,
-0x51,
-0x03,
-0x00,
-0x00,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0x18,
-0x80,
-0x38,
-0xc0,
-0x83,
-0x37,
-0x80,
-0xff,
-0xb8,
-0xff,
-0xff,
-0x13,
-0x0e,
-0xbf,
-0x0c,
-0xb6,
-0x7a,
-0xc4,
-0xff,
-0x2f,
-0x3c,
-0xfc,
-0x6b,
-0xfd,
-0x40,
-0x03,
-0xd4,
-0x00,
-0x97,
-0xff,
-0xff,
-0xff,
-0xe7,
-0xe1,
-0x1f,
-0xe0,
-0x00,
-0xfe,
-0xbf,
-0xf5,
-0x9f,
-0x87,
-0x7e,
-0x22,
-0x01,
-0xc6,
-0x00,
-0xc4,
-0x7c,
-0x1e,
-0xfa,
-0x01,
-0x00,
-0xe0,
-0xff,
-0x7b,
-0x0e,
-0x40,
-0xbd,
-0x55,
-0xe0,
-0x73,
-0xd0,
-0x0f,
-0xff,
-0x00,
-0xe0,
-0xff,
-0x13,
-0xf2,
-0xc3,
-0xbb,
-0xff,
-0x8b,
-0xf8,
-0xff,
-0x44,
-0x59,
-0x0e,
-0x7f,
-0x34,
-0x00,
-0x70,
-0x59,
-0xfb,
-0x07,
-0xe0,
-0xfb,
-0xc7,
-0x06,
-0x38,
-0xf0,
-0xfe,
-0x7f,
-0x94,
-0x9b,
-0x1f,
-0xe0,
-0xe7,
-0xe1,
-0x03,
-0xff,
-0x00,
-0xfe,
-0x7f,
-0x00,
-0xff,
-0x86,
-0xff,
-0x1e,
-0x00,
-0xe8,
-0xff,
-0x8c,
-0x07,
-0xf0,
-0xf4,
-0x43,
-0xf9,
-0x3c,
-0x7e,
-0x33,
-0x0e,
-0xc0,
-0xd0,
-0x0f,
-0xe5,
-0xf3,
-0xf7,
-0xcb,
-0x38,
-0x00,
-0x43,
-0x3f,
-0x94,
-0xcf,
-0xec,
-0x93,
-0x0c,
-0x00,
-0xf8,
-0x0f,
-0xfc,
-0x03,
-0x1b,
-0xfe,
-0x01,
-0xfc,
-0xe0,
-0x3f,
-0xf0,
-0x0f,
-0x6f,
-0xf8,
-0x07,
-0xf0,
-0x80,
-0xff,
-0xc0,
-0x3f,
-0xbf,
-0xe1,
-0x1f,
-0xc0,
-0x00,
-0xfe,
-0xbf,
-0x07,
-0x03,
-0xf4,
-0xff,
-0xff,
-0xc8,
-0x0f,
-0xef,
-0x52,
-0x4f,
-0x70,
-0xbf,
-0xe0,
-0xe0,
-0x3a,
-0xfc,
-0x31,
-0x0f,
-0xc0,
-0xd3,
-0xd5,
-0x0c,
-0x70,
-0xe0,
-0xcf,
-0x03,
-0x00,
-0xac,
-0x5c,
-0x7f,
-0x00,
-0xae,
-0x97,
-0x6c,
-0x80,
-0x03,
-0x7f,
-0xfe,
-0x01,
-0x78,
-0x6e,
-0xb1,
-0x01,
-0x0e,
-0xfc,
-0xf9,
-0x07,
-0xe0,
-0xf7,
-0xc7,
-0x06,
-0x38,
-0xf0,
-0x8b,
-0x01,
-0x00,
-0x5e,
-0x81,
-0x7f,
-0x00,
-0xff,
-0x3f,
-0x80,
-0x7f,
-0xc3,
-0x07,
-0xfe,
-0x01,
-0xfc,
-0xff,
-0x00,
-0xfe,
-0x0d,
-0x1f,
-0xf8,
-0x07,
-0xf0,
-0xfc,
-0x03,
-0xf8,
-0x37,
-0xff,
-0xf7,
-0x00,
-0xc0,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x1f,
-0xc0,
-0xbf,
-0xfe,
-0x03,
-0xff,
-0x00,
-0x86,
-0x7f,
-0x00,
-0xff,
-0xf8,
-0x0f,
-0xfc,
-0x03,
-0x1b,
-0xfe,
-0x01,
-0xfc,
-0xe0,
-0xff,
-0x7b,
-0x00,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x01,
-0xfc,
-0x07,
-0xfe,
-0xfe,
-0x0d,
-0xff,
-0x00,
-0x00,
-0xf0,
-0xff,
-0x3d,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0xff,
-0x00,
-0xfe,
-0x03,
-0x00,
-0xff,
-0x86,
-0x7f,
-0x1e,
-0x00,
-0xf8,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0x81,
-0x7f,
-0x00,
-0xff,
-0x3f,
-0x80,
-0x7f,
-0xc3,
-0x7f,
-0x0f,
-0x00,
-0xfc,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x1f,
-0xc0,
-0xbf,
-0xfe,
-0xbf,
-0x07,
-0x00,
-0xfc,
-0x07,
-0xfe,
-0x01,
-0x0d,
-0xff,
-0x00,
-0xfe,
-0xf0,
-0x1f,
-0xf8,
-0x07,
-0x37,
-0xfc,
-0x03,
-0xf8,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0xdf,
-0x03,
-0x00,
-0xfe,
-0x03,
-0xff,
-0xff,
-0x86,
-0x7f,
-0x00,
-0x03,
-0xf8,
-0x0f,
-0xfc,
-0xfc,
-0x1b,
-0xfe,
-0x01,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x01,
-0x80,
-0xff,
-0xef,
-0x7f,
-0x00,
-0xff,
-0x81,
-0x80,
-0x7f,
-0xc3,
-0x3f,
-0xfe,
-0x01,
-0xfc,
-0x07,
-0x00,
-0xfe,
-0x0d,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xd7,
-0x00,
-0x80,
-0xf8,
-0xc0,
-0x3f,
-0x80,
-0xff,
-0x1f,
-0xc0,
-0xbf,
-0xe1,
-0x03,
-0xff,
-0x00,
-0xfe,
-0x7f,
-0x00,
-0xff,
-0x86,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0xfc,
-0x6b,
-0x00,
-0x20,
-0x04,
-0xff,
-0xbf,
-0xe8,
-0xf0,
-0xaf,
-0xf5,
-0xf3,
-0xff,
-0xd9,
-0x7a,
-0x00,
-0x83,
-0x3f,
-0x31,
-0xc0,
-0x0c,
-0x7d,
-0xe3,
-0x00,
-0x0f,
-0xfe,
-0x80,
-0x5e,
-0xf0,
-0xff,
-0x3d,
-0x00,
-0x65,
-0xfe,
-0xff,
-0x9f,
-0x7f,
-0xf8,
-0xc7,
-0xba,
-0x96,
-0xf2,
-0xff,
-0x7f,
-0xfa,
-0xe1,
-0x1f,
-0xeb,
-0x45,
-0x0e,
-0xf8,
-0xff,
-0x9f,
-0x87,
-0x7f,
-0x80,
-0x00,
-0xf8,
-0xff,
-0x1e,
-0x07,
-0xf0,
-0x5f,
-0x8c,
-0x7b,
-0x1d,
-0xf8,
-0x13,
-0xbf,
-0xe8,
-0x1a,
-0xff,
-0xf4,
-0xf3,
-0xf0,
-0x4f,
-0xff,
-0x2f,
-0xe3,
-0xff,
-0xd7,
-0xf5,
-0xc3,
-0xbf,
-0x0f,
-0x00,
-0xfc,
-0x7f,
-0xd6,
-0x03,
-0xf8,
-0xdf,
-0x89,
-0x01,
-0x1e,
-0xfc,
-0xfb,
-0x0f,
-0xe0,
-0x3f,
-0xd6,
-0xa2,
-0x7f,
-0xf8,
-0xff,
-0x7f,
-0x82,
-0xff,
-0x97,
-0xc1,
-0xd6,
-0xe1,
-0x40,
-0x02,
-0x00,
-0x14,
-0x7f,
-0xff,
-0x01,
-0xfc,
-0xdf,
-0x5a,
-0xf4,
-0x0f,
-0xfe,
-0xff,
-0xef,
-0x32,
-0xfc,
-0x03,
-0x9c,
-0x35,
-0x7f,
-0xf7,
-0x5f,
-0xcb,
-0xf0,
-0xaf,
-0xf5,
-0xff,
-0xff,
-0xdf,
-0x03,
-0x00,
-0xfe,
-0x03,
-0xff,
-0x5a,
-0x87,
-0x5f,
-0xad,
-0x2b,
-0xf8,
-0xdf,
-0xd6,
-0x03,
-0x1e,
-0xfa,
-0x89,
-0x7c,
-0x20,
-0x7d,
-0xc0,
-0x9f,
-0x75,
-0xf8,
-0x65,
-0xb0,
-0x80,
-0xff,
-0xef,
-0x01,
-0x00,
-0xff,
-0xdb,
-0x7a,
-0xc0,
-0x83,
-0x3f,
-0x31,
-0x01,
-0xfc,
-0x07,
-0xfe,
-0xf4,
-0x0f,
-0xdf,
-0x5a,
-0x4f,
-0xa0,
-0x3e,
-0xe0,
-0xd8,
-0x3a,
-0xfc,
-0x32,
-0x00,
-0xc0,
-0x01,
-0x48,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0xff,
-0x00,
-0xfe,
-0x03,
-0x00,
-0xff,
-0x86,
-0x7f,
-0xfc,
-0x03,
-0xf8,
-0x0f,
-0x01,
-0xfc,
-0x1b,
-0xfe,
-0x7b,
-0x00,
-0xe0,
-0xff,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0x81,
-0x7f,
-0x00,
-0xff,
-0x3f,
-0x80,
-0x7f,
-0xc3,
-0x07,
-0xfe,
-0x01,
-0xfc,
-0xff,
-0x00,
-0xfe,
-0x0d,
-0xff,
-0x3d,
-0x00,
-0xf0,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x1f,
-0xc0,
-0xbf,
-0xfe,
-0x03,
-0xff,
-0x00,
-0x86,
-0x7f,
-0x00,
-0xff,
-0xf8,
-0xff,
-0x1e,
-0x00,
-0xf0,
-0x1f,
-0xf8,
-0x07,
-0x37,
-0xfc,
-0x03,
-0xf8,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x00,
-0xfc,
-0x7f,
-0x0f,
-0x03,
-0xf8,
-0x0f,
-0xfc,
-0xfc,
-0x1b,
-0xfe,
-0x01,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0x07,
-0x00,
-0xfe,
-0xbf,
-0xfe,
-0x01,
-0xfc,
-0x07,
-0x00,
-0xfe,
-0x0d,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0xdf,
-0x03,
-0x00,
-0xff,
-0x03,
-0xff,
-0x00,
-0xfe,
-0x7f,
-0x00,
-0xff,
-0x86,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xef,
-0x01,
-0x80
-};
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10RevCHtPhyTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10RevCHtPhyTables.c
deleted file mode 100644
index 3e1afa4..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10RevCHtPhyTables.c
+++ /dev/null
@@ -1,440 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Rev C HT PCI tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCHTPHYTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-// HT Phy T a b l e s
-// -------------------------
-STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RevCHtPhyRegisters[] =
-{
-// 0x60:0x68
- {
- HtPhyRangeRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_GT_C0 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- HTPHY_LINKTYPE_SL0_ALL, //
- 0x60, 0x68, // Address range
- 0x00000040, // regData
- 0x00000040, // regMask
- }
- },
-// 0x70:0x78
- {
- HtPhyRangeRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_GT_C0 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- HTPHY_LINKTYPE_SL1_ALL, //
- 0x70, 0x78, // Address range
- 0x00000040, // regData
- 0x00000040, // regMask
- }
- },
-// Erratum 354
-// 0x40:48
- {
- HtPhyRangeRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- (AMD_F10_C2 | AMD_F10_C3) // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- HTPHY_LINKTYPE_SL0_HT3, //
- 0x40, 0x48, // Address
- 0x00000040, // regData
- 0x00000040, // regMask
- }
- },
-// 0x50:0x58
- {
- HtPhyRangeRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- (AMD_F10_C2 | AMD_F10_C3) // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- HTPHY_LINKTYPE_SL1_HT3, //
- 0x50, 0x58, // Address
- 0x00000040, // regData
- 0x00000040, // regMask
- }
- },
-// 0xC0
- {
- HtPhyRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Cx // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- HTPHY_LINKTYPE_SL0_ALL, //
- 0xC0, // Address
- 0x40040000, // regData
- 0xe01F0000, // regMask
- }
- },
-// 0xD0
- {
- HtPhyRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Cx // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- HTPHY_LINKTYPE_SL1_ALL, //
- 0xD0, // Address
- 0x40040000, // regData
- 0xe01F0000, // regMask
- }
- },
-// 0xCF
-// FIFO_PTR_OPT_VALUE
- {
- HtPhyProfileRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C3 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- PERFORMANCE_NB_PSTATES_ENABLE,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xCF, // Address
- 0x0000004A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xDF
-// FIFO_PTR_OPT_VALUE
- {
- HtPhyProfileRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C3 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- PERFORMANCE_NB_PSTATES_ENABLE,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xDF, // Address
- 0x0000004A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0x520A
- {
- HtPhyRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Cx // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- HTPHY_LINKTYPE_SL0_ALL, //
- 0x520A, // Address
- 0x00004000, // regData
- 0x00006000, // regMask
- }
- },
-// 0x530A
- {
- HtPhyRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Cx // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- HTPHY_LINKTYPE_SL1_ALL, //
- 0x530A, // Address
- 0x00004000, // regData
- 0x00006000, // regMask
- }
- },
-
-
-
-
-//
-// Deemphasis Settings
-//
-
-// For C3, also set [7]TxLs23ClkGateEn.
-//deemphasis level DL1[20:16], DL2[12:8], DP1[4:0] PostCur1En[31] PostCur2En[30] PreCur1En[29] MapPostCur2En[6]
-// No deemphasis 00h 00h 00h 0 0 0 0
-// -3dB postcursor 12h 00h 00h 1 0 0 0
-// -6dB postcursor 1Fh 00h 00h 1 0 0 0
-// -8dB postcursor 1Fh 06h 00h 1 1 0 1
-// -11dB postcursor 1Fh 0Dh 00h 1 1 0 1
-// -11dB postcursor with
-// -8dB precursor 1Fh 06h 07h 1 1 1 1
-
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C3 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL_NONE,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0x00000080, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C3 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL_NONE,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0x00000080, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C3 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__3,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0x80120080, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C3 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__3,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0x80120080, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C3 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__6,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0x801F0080, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C3 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__6,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0x801F0080, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C3 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__8,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0xC01F06C0, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C3 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__8,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0xC01F06C0, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C3 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__11,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0xC01F0DC0, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C3 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__11,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0xC01F0DC0, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C3 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__11_8,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0xE01F06C7, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C3 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__11_8,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0xE01F06C7, // regData
- 0xE01F1FDF, // regMask
- }
- },
-};
-
-CONST REGISTER_TABLE ROMDATA F10RevCHtPhyRegisterTable = {
- PrimaryCores,
- (sizeof (F10RevCHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
- F10RevCHtPhyRegisters
-};
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c
deleted file mode 100644
index d92bf99..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c
+++ /dev/null
@@ -1,189 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 HW C1e feature support functions.
- *
- * Provides the functions necessary to initialize the hardware C1e feature.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F10
- * @e \$Revision: 37157 $ @e \$Date: 2010-09-01 03:24:07 +0800 (Wed, 01 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "cpuRegisters.h"
-#include "cpuHwC1e.h"
-#include "cpuApicUtilities.h"
-#include "cpuF10PowerMgmt.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCHWC1E_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-VOID
-STATIC
-F10InitializeHwC1eOnCore (
- IN VOID *IntPendMsr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Should hardware C1e be enabled
- *
- * @param[in] HwC1eServices Pointer to this CPU's HW C1e family services.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval TRUE HW C1e is supported.
- *
- */
-BOOLEAN
-STATIC
-F10IsHwC1eSupported (
- IN HW_C1E_FAMILY_SERVICES *HwC1eServices,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- CPU_LOGICAL_ID LogicalId;
-
- GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
-
- if (((LogicalId.Revision & AMD_F10_RB_ALL) & ~(AMD_F10_RB_C3)) != 0) {
- return FALSE;
- }
- return TRUE;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Enable Hardware C1e on a family 10h CPU.
- *
- * @param[in] HwC1eServices Pointer to this CPU's HW C1e family services.
- * @param[in] EntryPoint Timepoint designator.
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @return AGESA_SUCCESS Always succeeds.
- *
- */
-AGESA_STATUS
-STATIC
-F10InitializeHwC1e (
- IN HW_C1E_FAMILY_SERVICES *HwC1eServices,
- IN UINT64 EntryPoint,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 MsrRegister;
- AP_TASK TaskPtr;
-
- MsrRegister = 0;
- ((INTPEND_MSR *) &MsrRegister)->IoMsgAddr = PlatformConfig->C1ePlatformData;
- ((INTPEND_MSR *) &MsrRegister)->IoRd = 1;
- ((INTPEND_MSR *) &MsrRegister)->C1eOnCmpHalt = 1;
- ((INTPEND_MSR *) &MsrRegister)->SmiOnCmpHalt = 0;
-
- TaskPtr.FuncAddress.PfApTaskI = F10InitializeHwC1eOnCore;
- TaskPtr.DataTransfer.DataSizeInDwords = 2;
- TaskPtr.DataTransfer.DataPtr = &MsrRegister;
- TaskPtr.DataTransfer.DataTransferFlags = 0;
- TaskPtr.ExeFlags = WAIT_FOR_CORE;
- ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
-
- return AGESA_SUCCESS;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Enable Hardware C1e on a family 10h core.
- *
- * @param[in] IntPendMsr MSR value to write to C001_0055 as determined by core 0.
- * @param[in] StdHeader Config Handle for library, services.
- *
- */
-VOID
-STATIC
-F10InitializeHwC1eOnCore (
- IN VOID *IntPendMsr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 MsrRegister;
-
- // Enable C1e
- LibAmdMsrWrite (MSR_INTPEND, (UINT64 *) IntPendMsr, StdHeader);
-
- // Set OS Visible Workaround Status BIT1 to indicate that C1e
- // is enabled.
- LibAmdMsrRead (MSR_OSVW_Status, &MsrRegister, StdHeader);
- MsrRegister |= BIT1;
- LibAmdMsrWrite (MSR_OSVW_Status, &MsrRegister, StdHeader);
-}
-
-
-CONST HW_C1E_FAMILY_SERVICES ROMDATA F10HwC1e =
-{
- 0,
- F10IsHwC1eSupported,
- F10InitializeHwC1e
-};
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10RevCMsrTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10RevCMsrTables.c
deleted file mode 100644
index c786585..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10RevCMsrTables.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Rev C, MSR tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCMSRTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10RevCMsrRegisters[] =
-{
-// M S R T a b l e s
-// ----------------------
-// MSR_LS_CFG (0xC0011020)
-// bit[1] = 0
- {
- MsrRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_GT_B0 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MSR_LS_CFG, // MSR Address
- 0x0000000000000000, // OR Mask
- (1 << 1), // NAND Mask
- }
- },
-
-// MSR_BU_CFG (0xC0011023)
-// bit[21] = 1
- {
- MsrRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_GT_B0 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MSR_BU_CFG, // MSR Address
- (1 << 21), // OR Mask
- (1 << 21), // NAND Mask
- }
- },
-
-// MSR_BU_CFG2 (0xC001102A)
-// bit[50] = 1
-// For GH rev C1 and later [RdMmExtCfgQwEn]=1
- {
- MsrRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_GT_C0 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MSR_BU_CFG2, // MSR Address
- 0x0004000000000000, // OR Mask
- 0x0004000000000000, // NAND Mask
- }
- },
-};
-
-CONST REGISTER_TABLE ROMDATA F10RevCMsrRegisterTable = {
- AllCores,
- (sizeof (F10RevCMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
- (TABLE_ENTRY_FIELDS *) &F10RevCMsrRegisters,
-};
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10RevCPciTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10RevCPciTables.c
deleted file mode 100644
index 3fd5b31..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10RevCPciTables.c
+++ /dev/null
@@ -1,266 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Rev C PCI tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x10/RevC
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "F10PackageType.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCPCITABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-// P C I T a b l e s
-// ----------------------
-
-STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RevCPciRegisters[] =
-{
-// Function 2 - DRAM Controller
-
-// F2x1B0 - Extended Memory Controller Configuration Low Register
-//
-// bit[5:4], AdapPrefNegativeStep = 0
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Cx // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_2, 0x1B0), // Address
- 0x00000000, // regData
- 0x00000030, // regMask
- }
- },
-// Function 3 - Misc. Control
-
-// F3x158 - Link to XCS Token Count
-// bits[3:0] LnkToXcsDRToken = 3
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_GT_A2 // CpuRevision
- },
- AMD_PF_UMA, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x158), // Address
- 0x00000003, // regData
- 0x0000000F, // regMask
- }
- },
-// F3x80 - ACPI Power State Control
-// ACPI State C2
-// bits[0] CpuPrbEn = 1
-// bits[1] NbLowPwrEn = 0
-// bits[2] NbGateEn = 0
-// bits[3] NbCofChg = 0
-// bits[4] AltVidEn = 0
-// bits[7:5] ClkDivisor = 1
-// ACPI State C3, C1E or Link init
-// bits[0] CpuPrbEn = 0
-// bits[1] NbLowPwrEn = 1
-// bits[2] NbGateEn = 1
-// bits[3] NbCofChg = 0
-// bits[4] AltVidEn = 0
-// bits[7:5] ClkDivisor = 7
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Cx // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address
- 0x0000E681, // regData
- 0x0000FFFF, // regMask
- }
- },
-// F3x80 - ACPI Power State Control
-// ACPI State C3, C1E or Link init
-// bits[0] CpuPrbEn = 1
-// bits[1] NbLowPwrEn = 1
-// bits[2] NbGateEn = 1
-// bits[3] NbCofChg = 0
-// bits[4] AltVidEn = 0
-// bits[7:5] ClkDivisor = 4
- {
- HtFeatPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Cx // CpuRevision
- },
- AMD_PF_SINGLE_LINK, // platformFeatures
- {
- HT_HOST_FEAT_HT1, // link feats
- PACKAGE_TYPE_ASB2, // package type
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address
- 0x00008700, // regData
- 0x0000FF00, // regMask
- }
- },
-// F3x80 - ACPI Power State Control
-// ACPI State C3, C1E or Link init
-// bits[0] CpuPrbEn = 0
-// bits[1] NbLowPwrEn = 1
-// bits[2] NbGateEn = 1
-// bits[3] NbCofChg = 0
-// bits[4] AltVidEn = 1
-// bits[7:5] ClkDivisor = 7
- {
- ProfileFixup,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C3 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- PERFORMANCE_VRM_HIGH_SPEED_ENABLE, // PerformanceFeatures
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address
- 0x0000F600, // regData
- 0x0000FF00, // regMask
- }
- },
-// F3x80 - ACPI Power State Control
-// ACPI State C3, C1E or Link init
-// bits[0] CpuPrbEn = 1
-// bits[1] NbLowPwrEn = 1
-// bits[2] NbGateEn = 1
-// bits[3] NbCofChg = 0
-// bits[4] AltVidEn = 0
-// bits[7:5] ClkDivisor = 4
- {
- HtFeatPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Cx // CpuRevision
- },
- AMD_PF_SINGLE_LINK, // platformFeatures
- {
- HT_HOST_FEAT_HT1, // link feats
- PACKAGE_TYPE_ALL & (~ PACKAGE_TYPE_ASB2), // package type
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address
- 0x00008700, // regData
- 0x0000FF00, // regMask
- }
- },
-// F3xDC - Clock Power Timing Control 2
-// bits[14:12] NbsynPtrAdj = 5
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Cx // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC), // Address
- 0x00005000, // regData
- 0x00007000, // regMask
- }
- },
-// F3x180 - NB Extended Configuration
-// bits[23] SyncFloodOnDramTempErr = 1
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Cx // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x180), // Address
- 0x00800000, // regData
- 0x00800000, // regMask
- }
- },
-// F3x188 - NB Extended Configuration Low Register
-// bit[22] = DisHldReg2
-// Errata #346
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Cx // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address
- 0x00400000, // regData
- 0x00400000, // regMask
- }
- }
-};
-
-CONST REGISTER_TABLE ROMDATA F10RevCPciRegisterTable = {
- PrimaryCores,
- (sizeof (F10RevCPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
- F10RevCPciRegisters,
-};
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c
deleted file mode 100644
index 45a1aac..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c
+++ /dev/null
@@ -1,182 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 SW C1e feature support functions.
- *
- * Provides the functions necessary to initialize the software C1e feature.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F10
- * @e \$Revision: 37157 $ @e \$Date: 2010-09-01 03:24:07 +0800 (Wed, 01 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "cpuRegisters.h"
-#include "cpuSwC1e.h"
-#include "cpuApicUtilities.h"
-#include "cpuF10PowerMgmt.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCSWC1E_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-VOID
-STATIC
-F10InitializeSwC1eOnCore (
- IN VOID *IntPendMsr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Should software C1e be enabled
- *
- * @param[in] SwC1eServices Pointer to this CPU's SW C1e family services.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval TRUE SW C1e is supported.
- *
- */
-BOOLEAN
-STATIC
-F10IsSwC1eSupported (
- IN SW_C1E_FAMILY_SERVICES *SwC1eServices,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- return TRUE;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Enable Software C1e on a family 10h CPU.
- *
- * @param[in] SwC1eServices Pointer to this CPU's SW C1e family services.
- * @param[in] EntryPoint Timepoint designator.
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @return AGESA_SUCCESS Always succeeds.
- *
- */
-AGESA_STATUS
-STATIC
-F10InitializeSwC1e (
- IN SW_C1E_FAMILY_SERVICES *SwC1eServices,
- IN UINT64 EntryPoint,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 MsrRegister;
- AP_TASK TaskPtr;
-
- MsrRegister = 0;
- ((INTPEND_MSR *) &MsrRegister)->IoMsgAddr = PlatformConfig->C1ePlatformData1;
- ((INTPEND_MSR *) &MsrRegister)->IoMsgData = PlatformConfig->C1ePlatformData2;
- ((INTPEND_MSR *) &MsrRegister)->IoRd = 0;
- ((INTPEND_MSR *) &MsrRegister)->C1eOnCmpHalt = 0;
- ((INTPEND_MSR *) &MsrRegister)->SmiOnCmpHalt = 1;
-
- TaskPtr.FuncAddress.PfApTaskI = F10InitializeSwC1eOnCore;
- TaskPtr.DataTransfer.DataSizeInDwords = 2;
- TaskPtr.DataTransfer.DataPtr = &MsrRegister;
- TaskPtr.DataTransfer.DataTransferFlags = 0;
- TaskPtr.ExeFlags = WAIT_FOR_CORE;
- ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
-
- return AGESA_SUCCESS;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Enable Software C1e on a family 10h core.
- *
- * @param[in] IntPendMsr MSR value to write to C001_0055 as determined by core 0.
- * @param[in] StdHeader Config Handle for library, services.
- *
- */
-VOID
-STATIC
-F10InitializeSwC1eOnCore (
- IN VOID *IntPendMsr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 MsrRegister;
-
- // Enable C1e
- LibAmdMsrWrite (MSR_INTPEND, (UINT64 *) IntPendMsr, StdHeader);
-
- // Set OS Visible Workaround Status BIT1 to indicate that C1e
- // is enabled.
- LibAmdMsrRead (MSR_OSVW_Status, &MsrRegister, StdHeader);
- MsrRegister |= BIT1;
- LibAmdMsrWrite (MSR_OSVW_Status, &MsrRegister, StdHeader);
-}
-
-
-CONST SW_C1E_FAMILY_SERVICES ROMDATA F10SwC1e =
-{
- 0,
- F10IsSwC1eSupported,
- F10InitializeSwC1e
-};
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
deleted file mode 100644
index c422955..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
+++ /dev/null
@@ -1,436 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 revision Cx specific utility functions.
- *
- * Provides numerous utility functions specific to family 10h rev C.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuF10PowerMgmt.h"
-#include "GeneralServices.h"
-#include "cpuEarlyInit.h"
-#include "cpuPostInit.h"
-#include "cpuFeatures.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCUTILITIES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Set down core register on a revision C processor.
- *
- * This function set F3x190 Downcore Control Register[5:0]
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] Socket Socket ID.
- * @param[in] Module Module ID in socket.
- * @param[in] LeveledCores Number of core.
- * @param[in] CoreLevelMode Core level mode.
- * @param[in] StdHeader Header for library and services.
- *
- * @retval TRUE Down Core register is updated.
- * @retval FALSE Down Core register is not updated.
- */
-BOOLEAN
-F10CommonRevCSetDownCoreRegister (
- IN CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices,
- IN UINT32 *Socket,
- IN UINT32 *Module,
- IN UINT32 *LeveledCores,
- IN CORE_LEVELING_TYPE CoreLevelMode,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 TempVar32_a;
- UINT32 CoreDisableBits;
- PCI_ADDR PciAddress;
- BOOLEAN IsUpdated;
- AGESA_STATUS AgesaStatus;
-
- IsUpdated = FALSE;
-
- switch (*LeveledCores) {
- case 1:
- CoreDisableBits = DOWNCORE_MASK_SINGLE;
- break;
- case 2:
- CoreDisableBits = DOWNCORE_MASK_DUAL;
- break;
- case 3:
- CoreDisableBits = DOWNCORE_MASK_TRI;
- break;
- default:
- CoreDisableBits = 0;
- break;
- }
-
- if (CoreDisableBits != 0) {
- if (GetPciAddress (StdHeader, (UINT8) *Socket, (UINT8) *Module, &PciAddress, &AgesaStatus)) {
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = NORTH_BRIDGE_CAPABILITIES_REG;
-
- LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
- TempVar32_a = (TempVar32_a >> 12) & 0x3;
- if (TempVar32_a == 0) {
- CoreDisableBits &= 0x1;
- } else if (TempVar32_a == 1) {
- CoreDisableBits &= 0x3;
- } else if (TempVar32_a == 2) {
- CoreDisableBits &= 0x7;
- } else if (TempVar32_a == 3) {
- CoreDisableBits &= 0x0F;
- }
- PciAddress.Address.Register = DOWNCORE_CTRL;
- LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
- if ((TempVar32_a | CoreDisableBits) != TempVar32_a) {
- TempVar32_a |= CoreDisableBits;
- LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
- IsUpdated = TRUE;
- }
- }
- }
-
- return IsUpdated;
-}
-
-
-CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevCCoreLeveling =
-{
- 0,
- F10CommonRevCSetDownCoreRegister
-};
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Get CPU pstate current on a revision C processor.
- *
- * @CpuServiceMethod{::F_CPU_GET_IDD_MAX}.
- *
- * This function returns the ProcIddMax.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] Pstate The P-state to check.
- * @param[out] ProcIddMax P-state current in mA.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @retval TRUE P-state is enabled
- * @retval FALSE P-state is disabled
- */
-BOOLEAN
-F10CommonRevCGetProcIddMax (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN UINT8 Pstate,
- OUT UINT32 *ProcIddMax,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 IddDiv;
- UINT32 CmpCap;
- UINT32 PciRegister;
- UINT32 Socket;
- UINT32 Module;
- UINT32 Ignored;
- UINT32 MsrAddress;
- UINT32 SinglePlaneNbIdd;
- UINT64 PstateMsr;
- BOOLEAN IsPstateEnabled;
- PCI_ADDR PciAddress;
- AGESA_STATUS IgnoredSts;
-
- IsPstateEnabled = FALSE;
-
- MsrAddress = (UINT32) (Pstate + PS_REG_BASE);
-
- ASSERT (MsrAddress <= PS_MAX_REG);
-
- LibAmdMsrRead (MsrAddress, &PstateMsr, StdHeader);
- if (((PSTATE_MSR *) &PstateMsr)->PsEnable == 1) {
- IdentifyCore (StdHeader, &Socket, &Module, &Ignored, &IgnoredSts);
- GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
-
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = NB_CAPS_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // F3xE8
- CmpCap = (UINT32) (((NB_CAPS_REGISTER *) &PciRegister)->CmpCapLo);
- CmpCap++;
-
- switch (((PSTATE_MSR *) &PstateMsr)->IddDiv) {
- case 0:
- IddDiv = 1000;
- break;
- case 1:
- IddDiv = 100;
- break;
- case 2:
- IddDiv = 10;
- break;
- default: // IddDiv = 3 is reserved. Use 10
- ASSERT (FALSE);
- IddDiv = 10;
- break;
- }
-
- PciAddress.Address.Register = PW_CTL_MISC_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // F3xE8
- if (((POWER_CTRL_MISC_REGISTER *) &PciRegister)->PviMode == 1) {
- *ProcIddMax = (UINT32) ((PSTATE_MSR *) &PstateMsr)->IddValue * IddDiv * CmpCap;
- } else {
- PciAddress.Address.Register = PRCT_INFO_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // F3xE8
- SinglePlaneNbIdd = ((PRODUCT_INFO_REGISTER *) &PciRegister)->SinglePlaneNbIdd;
- SinglePlaneNbIdd <<= 1;
- *ProcIddMax = ((UINT32) ((PSTATE_MSR *) &PstateMsr)->IddValue * IddDiv * CmpCap) - SinglePlaneNbIdd;
- }
- IsPstateEnabled = TRUE;
- }
- return IsPstateEnabled;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns whether or not BIOS is responsible for configuring the NB COFVID.
- *
- * @CpuServiceMethod{::F_CPU_IS_NBCOF_INIT_NEEDED}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] PciAddress The northbridge to query by pci base address.
- * @param[out] NbVidUpdateAll Do all NbVids need to be updated
- * @param[in] StdHeader Header for library and services
- *
- * @retval TRUE Perform northbridge frequency and voltage config.
- * @retval FALSE Do not configure them.
- */
-BOOLEAN
-F10CommonRevCGetNbCofVidUpdate (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN PCI_ADDR *PciAddress,
- OUT BOOLEAN *NbVidUpdateAll,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 ProductInfoRegister;
-
- PciAddress->Address.Register = PRCT_INFO_REG;
- PciAddress->Address.Function = FUNC_3;
- LibAmdPciRead (AccessWidth32, *PciAddress, &ProductInfoRegister, StdHeader);
- *NbVidUpdateAll = (BOOLEAN) (((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbVidUpdateAll == 1);
- return (BOOLEAN) (((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbCofVidUpdate == 1);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Determines the NB clock on the desired node.
- *
- * @CpuServiceMethod{::F_CPU_GET_NB_PSTATE_INFO}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] PlatformConfig Platform profile/build option config structure.
- * @param[in] PciAddress The segment, bus, and device numbers of the CPU in question.
- * @param[in] NbPstate The NB P-state number to check.
- * @param[out] FreqNumeratorInMHz The desired node's frequency numerator in megahertz.
- * @param[out] FreqDivisor The desired node's frequency divisor.
- * @param[out] VoltageInuV The desired node's voltage in microvolts.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @retval TRUE NbPstate is valid
- * @retval FALSE NbPstate is disabled or invalid
- */
-BOOLEAN
-F10CommonRevCGetNbPstateInfo (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN PCI_ADDR *PciAddress,
- IN UINT32 NbPstate,
- OUT UINT32 *FreqNumeratorInMHz,
- OUT UINT32 *FreqDivisor,
- OUT UINT32 *VoltageInuV,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 NbFid;
- UINT32 NbVid;
- UINT32 PciRegister;
- UINT32 ProductInfoRegister;
- UINT64 MsrRegister;
- BOOLEAN PstateIsValid;
-
- PstateIsValid = TRUE;
- if (NbPstate == 0) {
- *FreqDivisor = 1;
- } else if ((NbPstate == 1) && FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, PlatformConfig, StdHeader)) {
- *FreqDivisor = 2;
- } else {
- PstateIsValid = FALSE;
- }
- if (PstateIsValid) {
- PciAddress->Address.Function = FUNC_3;
- PciAddress->Address.Register = PRCT_INFO_REG;
- LibAmdPciRead (AccessWidth32, *PciAddress, &ProductInfoRegister, StdHeader);
- if ((((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbCofVidUpdate) == 0) {
- PciAddress->Address.Register = CPTC0_REG;
- LibAmdPciRead (AccessWidth32, *PciAddress, &PciRegister, StdHeader);
- NbFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->NbFid;
- LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
- NbVid = (UINT32) ((COFVID_STS_MSR *) &MsrRegister)->CurNbVid;
- } else {
- NbFid = ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->SinglePlaneNbFid;
- NbVid = ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->SinglePlaneNbVid;
- PciAddress->Address.Register = PW_CTL_MISC_REG;
- LibAmdPciRead (AccessWidth32, *PciAddress, &PciRegister, StdHeader);
- if (((POWER_CTRL_MISC_REGISTER *) &PciRegister)->PviMode == 0) {
- NbFid += ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->DualPlaneNbFidOff;
- NbVid -= ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->DualPlaneNbVidOff;
- }
- }
- *FreqNumeratorInMHz = ((NbFid + 4) * 200);
- *VoltageInuV = (1550000 - (12500 * NbVid));
- }
- return PstateIsValid;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Is the Northbridge PState feature enabled?
- *
- * @CpuServiceMethod{::F_IS_NB_PSTATE_ENABLED}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] PlatformConfig Platform profile/build option config structure.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @retval TRUE The NB PState feature is enabled.
- * @retval FALSE The NB PState feature is not enabled.
- */
-BOOLEAN
-F10CommonRevCIsNbPstateEnabled (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Core;
- UINT32 Module;
- UINT32 NbPstate;
- UINT32 Socket;
- PCI_ADDR PciAddress;
- AGESA_STATUS IgnoredSts;
- CPU_LOGICAL_ID LogicalId;
- BOOLEAN Result;
-
- Result = FALSE;
-
- GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
- if (((LogicalId.Revision & AMD_F10_C3) != 0) && (!IsNonCoherentHt1 (StdHeader))) {
- IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
- GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = 0x1F0;
- LibAmdPciReadBits (PciAddress, 18, 16, &NbPstate, StdHeader);
- if (NbPstate != 0) {
- Result = TRUE;
- }
- }
- return Result;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Get number of processor cores to be used in determining the brand string.
- *
- * @CpuServiceMethod{::F_CPU_NUMBER_OF_BRANDSTRING_CORES}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @return The number of cores to be used in brand string calculation.
- */
-UINT8
-F10CommonRevCGetNumberOfCoresForBrandstring (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Socket;
- UINT32 Module;
- UINT32 Core;
- UINT32 PciRegister;
- PCI_ADDR PciAddress;
- AGESA_STATUS IgnoredSts;
-
- IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
- GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = NB_CAPS_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- return (UINT8) (((NB_CAPS_REGISTER *) &PciRegister)->CmpCapLo + 1);
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c
deleted file mode 100644
index 1db923a..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 RB Equivalence Table related data
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/Family/0x10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBEQUIVALENCETABLE_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-STATIC CONST UINT16 ROMDATA CpuF10RbMicrocodeEquivalenceTable[] =
-{
- 0x1040, 0x1040,
- 0x1041, 0x1041,
- 0x1042, 0x1041,
- 0x1043, 0x1043
-};
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns the appropriate microcode patch equivalent ID table.
- *
- * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[out] RbEquivalenceTablePtr Points to the first entry in the table.
- * @param[out] NumberOfElements Number of valid entries in the table.
- * @param[in] StdHeader Header for library and services.
- *
- */
-VOID
-GetF10RbMicrocodeEquivalenceTable (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- OUT CONST VOID **RbEquivalenceTablePtr,
- OUT UINT8 *NumberOfElements,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- *NumberOfElements = ((sizeof (CpuF10RbMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
- *RbEquivalenceTablePtr = CpuF10RbMicrocodeEquivalenceTable;
-}
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c
deleted file mode 100644
index 0a0852d..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 RB PCI tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBHTPHYTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-// HT Phy T a b l e s
-// -------------------------
-STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RbHtPhyRegisters[] =
-{
-// Erratum 354
-// 0x40:0x48
- {
- HtPhyRangeRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- (AMD_F10_RB_C1) // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- HTPHY_LINKTYPE_SL0_HT3, //
- 0x40, 0x48, // Address
- 0x00000040, // regData
- 0x00000040, // regMask
- }
- },
-// 0x50:0x58
- {
- HtPhyRangeRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- (AMD_F10_RB_C1) // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- HTPHY_LINKTYPE_SL1_HT3, //
- 0x50, 0x58, // Address
- 0x00000040, // regData
- 0x00000040, // regMask
- }
- },
-};
-
-CONST REGISTER_TABLE ROMDATA F10RbHtPhyRegisterTable = {
- PrimaryCores,
- (sizeof (F10RbHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
- F10RbHtPhyRegisters
-};
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/RB/F10RbLogicalIdTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/RB/F10RbLogicalIdTables.c
deleted file mode 100644
index 1d6bc5d..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/RB/F10RbLogicalIdTables.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 RB Logical ID Table
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBLOGICALIDTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF10RbLogicalIdAndRevArray[] =
-{
- {
- 0x1040,
- AMD_F10_RB_C0
- },
- {
- 0x1041,
- AMD_F10_RB_C1
- },
- {
- 0x1042,
- AMD_F10_RB_C2
- },
- {
- 0x1043,
- AMD_F10_RB_C3
- }
-};
-
-VOID
-GetF10RbLogicalIdAndRev (
- OUT CONST CPU_LOGICAL_ID_XLAT **RbIdPtr,
- OUT UINT8 *NumberOfElements,
- OUT UINT64 *LogicalFamily,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- *NumberOfElements = (sizeof (CpuF10RbLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT));
- *RbIdPtr = CpuF10RbLogicalIdAndRevArray;
- *LogicalFamily = AMD_FAMILY_10_RB;
-}
-
-//CONST LOGICAL_ID_TABLE ROMDATA CpuF10RbLogicalIdAndRev =
-//{
-// (sizeof (CpuF10RbLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT)),
-// (CPU_LOGICAL_ID_XLAT *) &CpuF10RbLogicalIdAndRevArray
-//};
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c
deleted file mode 100644
index 32a378d..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 RB microcode patches
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/Family/0x10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMICROCODEPATCHTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-extern CONST MICROCODE_PATCHES ROMDATA *CpuF10RbMicroCodePatchArray[];
-extern CONST UINT8 ROMDATA CpuF10RbNumberOfMicrocodePatches;
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns a table containing the appropriate microcode patches.
- *
- * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[out] RbUcodePtr Points to the first entry in the table.
- * @param[out] NumberOfElements Number of valid entries in the table.
- * @param[in] StdHeader Header for library and services.
- *
- */
-VOID
-GetF10RbMicroCodePatchesStruct (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- OUT CONST VOID **RbUcodePtr,
- OUT UINT8 *NumberOfElements,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- *NumberOfElements = CpuF10RbNumberOfMicrocodePatches;
- *RbUcodePtr = &CpuF10RbMicroCodePatchArray[0];
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/RB/F10RbMsrTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/RB/F10RbMsrTables.c
deleted file mode 100644
index 9fbfff7..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/RB/F10RbMsrTables.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 RB, MSR tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMSRTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10RbMsrRegisters[] =
-{
-// M S R T a b l e s
-// ----------------------
-
-// MSR_DC_CFG (0xC0011022)
-// bits[43:42] = 0
-// Errata #326
- {
- MsrRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_RB_C0 // CpuRevision
- },
- AMD_PF_MULTI_LINK, // platformFeatures
- {
- MSR_DC_CFG, // MSR Address
- 0x0000000000000000, // OR Mask
- 0x00000C0000000000, // NAND Mask
- }
- },
-
-// MSR_BU_CFG (0xC0011023)
-// Erratum #309 BU_CFG[23]=1
- {
- MsrRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_RB_C0 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MSR_BU_CFG, // MSR Address
- (1 << 23), // OR Mask
- (1 << 23), // NAND Mask
- }
- }
-};
-
-CONST REGISTER_TABLE ROMDATA F10RbMsrRegisterTable = {
- AllCores,
- (sizeof (F10RbMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
- (TABLE_ENTRY_FIELDS *) &F10RbMsrRegisters,
-};
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c
deleted file mode 100644
index 05f16ad..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c
+++ /dev/null
@@ -1,235 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 RB PCI tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBPCITABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-// P C I T a b l e s
-// ----------------------
-
-STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RbPciRegisters[] =
-{
- // Function 0
-
-// F0x16C - Link Global Extended Control Register, Errata 351
-// bit[15:13] ForceFullT0 = 0
-// bit[5:0] T0Time = 0x14
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- (AMD_F10_RB_C0 | AMD_F10_RB_C1 | AMD_F10_RB_C2) // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
- 0x00000014, // regData
- 0x0000E03F, // regMask
- }
- },
-// F0x16C - Link Global Extended Control Register
-// bit[7:6] InLnSt = 0x01
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_RB_C3 // CpuRevision
- },
- AMD_PF_SINGLE_LINK, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
- 0x00000040, // regData
- 0x000000C0, // regMask
- }
- },
-// F0x16C - Link Global Extended Control Register
-// bit[15:13] ForceFullT0 = 6
-// bit[9] RXCalEn = 1
-// bit[5:0] T0Time = 0x26
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_RB_C3 // CpuRevision
- },
- AMD_PF_SINGLE_LINK, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
- 0x0000C226, // regData
- 0x0000E23F, // regMask
- }
- },
-// F0x170 - Link Extended Control Register - Link 0, sublink 0
-// Errata 351 (only need to override single link case.)
-// bit[8] LS2En = 0,
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- (AMD_F10_RB_C0 | AMD_F10_RB_C1 | AMD_F10_RB_C2) // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_0, 0x170), // Address
- 0x00000000, // regData
- 0x00000100, // regMask
- }
- },
-
-
-// F3xA0 - Power Control Miscellaneous
-// bits[13:11] PllLockTime = 5
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_RB_C0 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0), // Address
- 0x00002800, // regData
- 0x00003800, // regMask
- }
- },
-// F3xA0 - Power Control Miscellaneous
-// bits[28] NbPstateForce = 1
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_RB_C3 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0), // Address
- 0x10000000, // regData
- 0x10000000, // regMask
- }
- },
-// F3xDC - Clock Power Timing Control 2
-// bits[14:12] NbsynPtrAdj = 6
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_RB_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC), // Address
- 0x00006000, // regData
- 0x00007000, // regMask
- }
- },
-// F3xDC - Clock Power Timing Control 2
-// bits[14:12] NbsynPtrAdj = 5
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C0 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC), // Address
- 0x00005000, // regData
- 0x00007000, // regMask
- }
- },
-// F3xDC - Clock Power Timing Control 2
-// bits[14:12] NbsynPtrAdj = 5
- {
- ProfileFixup,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C3 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- PERFORMANCE_NB_PSTATES_ENABLE, // PerformanceFeatures
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC), // Address
- 0x00005000, // regData
- 0x00007000, // regMask
- }
- }
-};
-
-CONST REGISTER_TABLE ROMDATA F10RbPciRegisterTable = {
- PrimaryCores,
- (sizeof (F10RbPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
- F10RbPciRegisters,
-};
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c4.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c4.c
deleted file mode 100644
index 0e07a9b..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c4.c
+++ /dev/null
@@ -1,1040 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Microcode patch.
- *
- * Fam10 Microcode Patch rev 010000c4 for 1081 or equivalent.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x10/REVD
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-// Patch code 010000c4 for 1081 and equivalent
-CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c4 =
-{
-0x10,
-0x20,
-0x03,
-0x03,
-0xc4,
-0x00,
-0x00,
-0x01,
-0x00,
-0x80,
-0x20,
-0x01,
-0x4a,
-0xe0,
-0x9c,
-0x93,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x81,
-0x10,
-0x00,
-0x00,
-0x00,
-0xaa,
-0xaa,
-0xaa,
-0xa7,
-0x0b,
-0x00,
-0x00,
-0x14,
-0x0c,
-0x00,
-0x00,
-0x55,
-0x03,
-0x00,
-0x00,
-0xff,
-0xff,
-0xff,
-0xff,
-0x51,
-0x03,
-0x00,
-0x00,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0x4f,
-0xdf,
-0x38,
-0x00,
-0x81,
-0x3f,
-0x20,
-0xc0,
-0x4e,
-0xf0,
-0xff,
-0xbf,
-0x0f,
-0xff,
-0x5e,
-0x3f,
-0xf0,
-0xdf,
-0xad,
-0x07,
-0x3d,
-0xf8,
-0x7b,
-0x7b,
-0xc0,
-0x00,
-0xd4,
-0x00,
-0x13,
-0xf1,
-0xff,
-0xff,
-0xac,
-0xe1,
-0x1f,
-0xe0,
-0x4e,
-0xfe,
-0xbb,
-0xff,
-0xfe,
-0x87,
-0x7f,
-0xa7,
-0x03,
-0xf8,
-0x7f,
-0xd6,
-0x7c,
-0x1e,
-0xfa,
-0xbd,
-0x00,
-0xe0,
-0xff,
-0x7b,
-0x0e,
-0x00,
-0x3d,
-0x57,
-0xe0,
-0x73,
-0xd0,
-0x0f,
-0xff,
-0x2e,
-0xfe,
-0xff,
-0xc0,
-0xcf,
-0xc3,
-0x3f,
-0xeb,
-0x01,
-0xfc,
-0x77,
-0x5a,
-0x3e,
-0x0f,
-0xfd,
-0x35,
-0x00,
-0x90,
-0x3e,
-0xff,
-0x9f,
-0xe0,
-0xfd,
-0x65,
-0x60,
-0x75,
-0xf8,
-0x9f,
-0xff,
-0x97,
-0xff,
-0x1f,
-0xe0,
-0xe7,
-0xe1,
-0x03,
-0xf5,
-0xde,
-0xff,
-0x7e,
-0x2c,
-0x9f,
-0x87,
-0xff,
-0x1e,
-0x00,
-0xf8,
-0x6f,
-0x95,
-0x03,
-0x50,
-0xf4,
-0x03,
-0xf8,
-0x1c,
-0xf8,
-0xff,
-0x3f,
-0x00,
-0xf0,
-0xee,
-0x84,
-0xfc,
-0xfe,
-0xff,
-0xff,
-0x22,
-0xc3,
-0x1f,
-0x51,
-0x96,
-0x38,
-0x16,
-0x0d,
-0x00,
-0xf8,
-0xfe,
-0xfe,
-0x01,
-0x0e,
-0xfc,
-0xb1,
-0x01,
-0xe5,
-0xa6,
-0xff,
-0x1f,
-0x79,
-0xf8,
-0x07,
-0xf8,
-0x80,
-0xff,
-0xc0,
-0x3f,
-0xbf,
-0xe1,
-0x1f,
-0xc0,
-0x00,
-0xfa,
-0xbf,
-0x07,
-0x01,
-0xfc,
-0x3f,
-0xe3,
-0x3e,
-0x0f,
-0xfd,
-0x50,
-0x03,
-0xb0,
-0xdf,
-0x8c,
-0xf9,
-0x3c,
-0xf4,
-0x43,
-0x0e,
-0xc0,
-0xfd,
-0x32,
-0xe5,
-0xf3,
-0xd0,
-0x0f,
-0x03,
-0x00,
-0x03,
-0x25,
-0xff,
-0x00,
-0xfe,
-0x03,
-0x00,
-0xff,
-0x86,
-0x7f,
-0xfc,
-0x03,
-0xf8,
-0x0f,
-0x01,
-0xfc,
-0x1b,
-0xfe,
-0xf0,
-0x0f,
-0xe0,
-0x3f,
-0x07,
-0xf0,
-0x6f,
-0xf8,
-0xef,
-0x01,
-0x80,
-0xff,
-0xff,
-0xff,
-0x00,
-0xfd,
-0xbb,
-0x14,
-0xf2,
-0xc3,
-0x2f,
-0xf8,
-0x13,
-0xcc,
-0x7f,
-0x0c,
-0xb8,
-0x0e,
-0x74,
-0xf5,
-0x03,
-0xf0,
-0xf8,
-0x33,
-0x03,
-0x1c,
-0x2b,
-0xd7,
-0x00,
-0x00,
-0xeb,
-0xe5,
-0x1f,
-0x80,
-0xc0,
-0x1f,
-0x1b,
-0xe0,
-0x9e,
-0x9b,
-0x7f,
-0x00,
-0x03,
-0x7f,
-0x6c,
-0x80,
-0xf8,
-0x7d,
-0xfe,
-0x01,
-0x0e,
-0xfc,
-0xb1,
-0x01,
-0x80,
-0xd7,
-0x62,
-0x00,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x01,
-0xfc,
-0x07,
-0xfe,
-0xfe,
-0x0d,
-0xff,
-0x00,
-0x00,
-0xf0,
-0xff,
-0x3d,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0xff,
-0x00,
-0xfe,
-0x03,
-0x00,
-0xff,
-0x86,
-0x7f,
-0x1e,
-0x00,
-0xf8,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0x81,
-0x7f,
-0x00,
-0xff,
-0x3f,
-0x80,
-0x7f,
-0xc3,
-0x7f,
-0x0f,
-0x00,
-0xfc,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x1f,
-0xc0,
-0xbf,
-0xfe,
-0xbf,
-0x07,
-0x00,
-0xfc,
-0x07,
-0xfe,
-0x01,
-0x0d,
-0xff,
-0x00,
-0xfe,
-0xf0,
-0x1f,
-0xf8,
-0x07,
-0x37,
-0xfc,
-0x03,
-0xf8,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0xdf,
-0x03,
-0x00,
-0xfe,
-0x03,
-0xff,
-0xff,
-0x86,
-0x7f,
-0x00,
-0x03,
-0xf8,
-0x0f,
-0xfc,
-0xfc,
-0x1b,
-0xfe,
-0x01,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x01,
-0x80,
-0xff,
-0xef,
-0x38,
-0x00,
-0x43,
-0xdf,
-0xa0,
-0xd7,
-0x83,
-0x3f,
-0xe3,
-0x00,
-0x3c,
-0x75,
-0x80,
-0x5e,
-0x07,
-0xfe,
-0xff,
-0xef,
-0x7a,
-0xc1,
-0x73,
-0xfd,
-0x3c,
-0xfc,
-0xf7,
-0x00,
-0xc0,
-0xff,
-0xff,
-0xff,
-0x17,
-0xff,
-0xdf,
-0xeb,
-0xff,
-0xe1,
-0xb7,
-0xf5,
-0x00,
-0xfe,
-0x7f,
-0x6e,
-0x80,
-0x07,
-0xff,
-0xff,
-0x6f,
-0x11,
-0xfe,
-0xb5,
-0xaa,
-0x1f,
-0xff,
-0x7b,
-0x00,
-0xe0,
-0xff,
-0xff,
-0x7f,
-0x8b,
-0xf0,
-0xaf,
-0x75,
-0xff,
-0xff,
-0xdb,
-0x7f,
-0x2f,
-0xc3,
-0xbf,
-0x57,
-0xf5,
-0x0c,
-0xf1,
-0xff,
-0xb7,
-0x0f,
-0xff,
-0x00,
-0x3f,
-0x70,
-0xa2,
-0x35,
-0x00,
-0xe0,
-0xff,
-0x1b,
-0x0f,
-0x79,
-0xe8,
-0xd7,
-0xf2,
-0x80,
-0xff,
-0xc0,
-0x3f,
-0xbf,
-0xe1,
-0x1f,
-0xc0,
-0x00,
-0xfe,
-0x03,
-0xff,
-0xff,
-0x86,
-0x7f,
-0x00,
-0x00,
-0xf8,
-0xff,
-0x1e,
-0x2f,
-0x3a,
-0xc1,
-0xff,
-0xfd,
-0x3c,
-0xfc,
-0x6b,
-0x1e,
-0xc0,
-0x7f,
-0xb6,
-0x0c,
-0xf0,
-0xe0,
-0x4f,
-0xff,
-0x2f,
-0x43,
-0xfc,
-0xc0,
-0xcf,
-0xc3,
-0x3f,
-0x0f,
-0x00,
-0xfc,
-0x7f,
-0xff,
-0x67,
-0x81,
-0xff,
-0xb1,
-0xee,
-0x1f,
-0xfe,
-0x1b,
-0x0f,
-0xe0,
-0xff,
-0xf7,
-0xf6,
-0x7a,
-0xf0,
-0xef,
-0xbf,
-0x96,
-0xff,
-0x1d,
-0xab,
-0xfe,
-0xe1,
-0xbf,
-0x07,
-0x00,
-0xfe,
-0x6f,
-0xff,
-0xb1,
-0xfc,
-0x7f,
-0x58,
-0x59,
-0x0e,
-0xc0,
-0xff,
-0x2f,
-0x72,
-0xfc,
-0x03,
-0xfc,
-0x3c,
-0x7f,
-0x31,
-0x1e,
-0xc0,
-0xe0,
-0x4f,
-0xec,
-0x75,
-0xff,
-0xdf,
-0x03,
-0x00,
-0xd7,
-0xf8,
-0xff,
-0x45,
-0x87,
-0x7f,
-0xa2,
-0x9f,
-0x19,
-0xff,
-0xff,
-0x67,
-0x1f,
-0xfe,
-0xb1,
-0xae,
-0x65,
-0xfc,
-0xff,
-0xff,
-0x7e,
-0xf8,
-0xf7,
-0xba,
-0x80,
-0xff,
-0xef,
-0x01,
-0x00,
-0xff,
-0xdb,
-0x7a,
-0xc0,
-0x83,
-0x3f,
-0x31,
-0x01,
-0xfc,
-0x67,
-0xff,
-0xf4,
-0x0f,
-0xdf,
-0x5a,
-0x4f,
-0xf0,
-0xff,
-0xff,
-0xd8,
-0x3a,
-0xfc,
-0x32,
-0x00,
-0xc0,
-0x01,
-0x48,
-0x7f,
-0x97,
-0xf1,
-0xff,
-0xe0,
-0xac,
-0xe1,
-0x1f,
-0xff,
-0x5a,
-0xfe,
-0xbb,
-0xad,
-0xff,
-0x87,
-0x7f,
-0xfe,
-0x03,
-0xf8,
-0xff,
-0xb5,
-0xe8,
-0x1f,
-0xbe,
-0x7b,
-0x00,
-0xe0,
-0xff,
-0xe0,
-0x5f,
-0xcb,
-0x7f,
-0xab,
-0x75,
-0xe5,
-0xf0,
-0xdb,
-0x7a,
-0x00,
-0xff,
-0x3f,
-0x91,
-0xcf,
-0x43,
-0x0f,
-0xf8,
-0x13,
-0x90,
-0xbf,
-0x0c,
-0xb6,
-0x0e,
-0xff,
-0x3d,
-0x00,
-0xf0,
-0x7f,
-0x5b,
-0x0f,
-0xe0,
-0xf0,
-0x27,
-0x06,
-0x78,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x5b,
-0x8b,
-0xfe,
-0xca,
-0x07,
-0xfc,
-0x09,
-0x87,
-0x5f,
-0x06,
-0x5b,
-0x20,
-0x00,
-0x09,
-0x00,
-0xb0,
-0xc0,
-0x8d,
-0x03,
-0x3c,
-0xf8,
-0x03,
-0x02,
-0x80,
-0xf8,
-0xff,
-0x3f,
-0xfc,
-0xf0,
-0xce,
-0x85,
-0x04,
-0x3a,
-0x0e,
-0xfe,
-0xae,
-0xc3,
-0x1f,
-0x03,
-0x00,
-0xfc,
-0x7f,
-0x0f,
-0x77,
-0x01,
-0x00,
-0xf8,
-0xee,
-0x1f,
-0xfe,
-0xb9,
-0x3f,
-0x65,
-0x40,
-0xe0,
-0xf8,
-0x79,
-0xf8,
-0x07,
-0xff,
-0x94,
-0xf3,
-0xff,
-0xea,
-0xfa,
-0xe0,
-0x5f,
-0x06,
-0x00,
-0x7a,
-0xbc,
-0xff,
-0xa5,
-0xfe,
-0x77,
-0x52,
-0x3f,
-0x0f,
-0xff,
-0xff,
-0xef,
-0xf2,
-0xfe,
-0x03,
-0xfc,
-0x3c,
-0xfc,
-0x77,
-0x1f,
-0xe0,
-0x7f,
-0x2f,
-0xe5,
-0xf3,
-0xd0,
-0xdf,
-0x03,
-0x00,
-0xff,
-0x03,
-0xff,
-0x00,
-0xfe,
-0x7f,
-0x00,
-0xff,
-0x86,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xef,
-0x01,
-0x80
-};
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c
deleted file mode 100644
index 888fe91..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c
+++ /dev/null
@@ -1,1040 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Microcode patch.
- *
- * Fam10 Microcode Patch rev 010000c5 for 1080 or equivalent.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x10/REVD
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-// Patch code 010000c5 for 1080 and equivalent
-CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c5 =
-{
-0x10,
-0x20,
-0x05,
-0x03,
-0xc5,
-0x00,
-0x00,
-0x01,
-0x00,
-0x80,
-0x20,
-0x00,
-0x83,
-0xc5,
-0x93,
-0xcd,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x80,
-0x10,
-0x00,
-0x00,
-0x00,
-0xaa,
-0xaa,
-0xaa,
-0x89,
-0x0b,
-0x00,
-0x00,
-0x55,
-0x03,
-0x00,
-0x00,
-0xff,
-0xff,
-0xff,
-0xff,
-0x51,
-0x03,
-0x00,
-0x00,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xf8,
-0xff,
-0x2e,
-0xc3,
-0x3f,
-0xd7,
-0xfd,
-0xac,
-0xff,
-0xff,
-0xbb,
-0x0f,
-0xff,
-0x5c,
-0xd7,
-0xf3,
-0xdf,
-0xfd,
-0xc7,
-0x3f,
-0xfc,
-0xe3,
-0xf5,
-0x00,
-0x1d,
-0xd5,
-0x00,
-0x00,
-0xfd,
-0xff,
-0x7f,
-0xfa,
-0xe1,
-0xd9,
-0xca,
-0x00,
-0x66,
-0xfa,
-0x71,
-0x80,
-0x07,
-0x7f,
-0x40,
-0x67,
-0xd9,
-0xff,
-0xff,
-0xde,
-0x1d,
-0x7e,
-0xb1,
-0x00,
-0xe0,
-0xff,
-0x7b,
-0x0e,
-0x40,
-0xbd,
-0x55,
-0xe0,
-0x73,
-0xd0,
-0x0f,
-0xff,
-0x00,
-0xe0,
-0xff,
-0x13,
-0xf2,
-0xc3,
-0xbb,
-0xff,
-0x8b,
-0xf8,
-0xff,
-0x44,
-0x59,
-0x0e,
-0x7f,
-0x34,
-0x00,
-0x10,
-0x59,
-0xfb,
-0x07,
-0xe0,
-0xfb,
-0xc7,
-0x06,
-0x38,
-0xf0,
-0xfe,
-0x7f,
-0x94,
-0x9b,
-0x1f,
-0xe0,
-0xe7,
-0xe1,
-0x03,
-0xff,
-0x00,
-0xfe,
-0x7f,
-0x00,
-0xff,
-0x86,
-0xff,
-0x1e,
-0x00,
-0xe8,
-0xff,
-0x8c,
-0x07,
-0xf0,
-0xf4,
-0x43,
-0xf9,
-0x3c,
-0x7e,
-0x33,
-0x0e,
-0xc0,
-0xd0,
-0x0f,
-0xe5,
-0xf3,
-0xf7,
-0xcb,
-0x38,
-0x00,
-0x43,
-0x3f,
-0x94,
-0xcf,
-0x0c,
-0x94,
-0x0c,
-0x00,
-0xf8,
-0x0f,
-0xfc,
-0x03,
-0x1b,
-0xfe,
-0x01,
-0xfc,
-0xe0,
-0x3f,
-0xf0,
-0x0f,
-0x6f,
-0xf8,
-0x07,
-0xf0,
-0x80,
-0xff,
-0xc0,
-0x3f,
-0xbf,
-0xe1,
-0x1f,
-0xc0,
-0x00,
-0xfe,
-0xbf,
-0x07,
-0x03,
-0xf4,
-0xff,
-0xff,
-0xc8,
-0x0f,
-0xef,
-0x52,
-0x4f,
-0x30,
-0xbf,
-0xe0,
-0xe0,
-0x3a,
-0xfc,
-0x31,
-0x0f,
-0xc0,
-0xd3,
-0xd5,
-0x0c,
-0x70,
-0xe0,
-0xcf,
-0x03,
-0x00,
-0xac,
-0x5c,
-0x7f,
-0x00,
-0xae,
-0x97,
-0x6c,
-0x80,
-0x03,
-0x7f,
-0xfe,
-0x01,
-0x78,
-0x6e,
-0xb1,
-0x01,
-0x0e,
-0xfc,
-0xf9,
-0x07,
-0xe0,
-0xf7,
-0xc7,
-0x06,
-0x38,
-0xf0,
-0x8b,
-0x01,
-0x80,
-0x5f,
-0x81,
-0x7f,
-0x00,
-0xff,
-0x3f,
-0x80,
-0x7f,
-0xc3,
-0x07,
-0xfe,
-0x01,
-0xfc,
-0xff,
-0x00,
-0xfe,
-0x0d,
-0x1f,
-0xf8,
-0x07,
-0xf0,
-0xfc,
-0x03,
-0xf8,
-0x37,
-0xff,
-0xf7,
-0x00,
-0xc0,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x1f,
-0xc0,
-0xbf,
-0xfe,
-0x03,
-0xff,
-0x00,
-0x86,
-0x7f,
-0x00,
-0xff,
-0xf8,
-0x0f,
-0xfc,
-0x03,
-0x1b,
-0xfe,
-0x01,
-0xfc,
-0xe0,
-0xff,
-0x7b,
-0x00,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x01,
-0xfc,
-0x07,
-0xfe,
-0xfe,
-0x0d,
-0xff,
-0x00,
-0x00,
-0xf0,
-0xff,
-0x3d,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0xff,
-0x00,
-0xfe,
-0x03,
-0x00,
-0xff,
-0x86,
-0x7f,
-0x1e,
-0x00,
-0xf8,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0x81,
-0x7f,
-0x00,
-0xff,
-0x3f,
-0x80,
-0x7f,
-0xc3,
-0x7f,
-0x0f,
-0x00,
-0xfc,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x1f,
-0xc0,
-0xbf,
-0xfe,
-0xbf,
-0x07,
-0x00,
-0xfc,
-0x07,
-0xfe,
-0x01,
-0x0d,
-0xff,
-0x00,
-0xfe,
-0xf0,
-0x1f,
-0xf8,
-0x07,
-0x37,
-0xfc,
-0x03,
-0xf8,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0xdf,
-0x03,
-0x00,
-0xfe,
-0x03,
-0xff,
-0xff,
-0x86,
-0x7f,
-0x00,
-0x03,
-0xf8,
-0x0f,
-0xfc,
-0xfc,
-0x1b,
-0xfe,
-0x01,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x01,
-0x80,
-0xff,
-0xef,
-0x7f,
-0x00,
-0xff,
-0x81,
-0x80,
-0x7f,
-0xc3,
-0x3f,
-0xfe,
-0x01,
-0xfc,
-0x07,
-0x00,
-0xfe,
-0x0d,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xd7,
-0x00,
-0x40,
-0xf9,
-0xc0,
-0x3f,
-0x80,
-0xff,
-0x1f,
-0xc0,
-0xbf,
-0xe1,
-0x03,
-0xff,
-0x00,
-0xfe,
-0x7f,
-0x00,
-0xff,
-0x86,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0xfc,
-0x6b,
-0x00,
-0x80,
-0x7f,
-0xe0,
-0x1f,
-0xc0,
-0xf0,
-0x0f,
-0xe0,
-0xdf,
-0xff,
-0x81,
-0x7f,
-0x00,
-0xc3,
-0x3f,
-0x80,
-0x7f,
-0xfc,
-0x07,
-0xfe,
-0x01,
-0x0d,
-0xff,
-0x00,
-0xfe,
-0xf0,
-0xff,
-0x3d,
-0x00,
-0xe0,
-0x3f,
-0xf0,
-0x0f,
-0x6f,
-0xf8,
-0x07,
-0xf0,
-0x80,
-0xff,
-0xc0,
-0x3f,
-0xbf,
-0xe1,
-0x1f,
-0xc0,
-0x00,
-0xfe,
-0x03,
-0xff,
-0xff,
-0x86,
-0x7f,
-0x00,
-0x00,
-0xf8,
-0xff,
-0x1e,
-0x07,
-0xf0,
-0x1f,
-0xf8,
-0xf8,
-0x37,
-0xfc,
-0x03,
-0x1f,
-0xc0,
-0x7f,
-0xe0,
-0xe0,
-0xdf,
-0xf0,
-0x0f,
-0x7f,
-0x00,
-0xff,
-0x81,
-0x80,
-0x7f,
-0xc3,
-0x3f,
-0x0f,
-0x00,
-0xfc,
-0x7f,
-0xfc,
-0x03,
-0xf8,
-0x0f,
-0x01,
-0xfc,
-0x1b,
-0xfe,
-0xf0,
-0x0f,
-0xe0,
-0x3f,
-0x07,
-0xf0,
-0x6f,
-0xf8,
-0xc0,
-0x3f,
-0x80,
-0xff,
-0x1f,
-0xc0,
-0xbf,
-0xe1,
-0xbf,
-0x07,
-0x00,
-0xfe,
-0x07,
-0xfe,
-0x01,
-0xfc,
-0xff,
-0x00,
-0xfe,
-0x0d,
-0x1f,
-0xf8,
-0x07,
-0xf0,
-0xfc,
-0x03,
-0xf8,
-0x37,
-0x7f,
-0xe0,
-0x1f,
-0xc0,
-0xf0,
-0x0f,
-0xe0,
-0xdf,
-0xff,
-0xdf,
-0x03,
-0x00,
-0xfe,
-0x03,
-0xff,
-0x00,
-0x86,
-0x7f,
-0x00,
-0xff,
-0xf8,
-0x0f,
-0xfc,
-0x03,
-0x1b,
-0xfe,
-0x01,
-0xfc,
-0xe0,
-0x3f,
-0xf0,
-0x0f,
-0x6f,
-0xf8,
-0x07,
-0xf0,
-0x80,
-0xff,
-0xef,
-0x01,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x01,
-0xfc,
-0x07,
-0xfe,
-0xfe,
-0x0d,
-0xff,
-0x00,
-0x07,
-0xf0,
-0x1f,
-0xf8,
-0xf8,
-0x37,
-0xfc,
-0x03,
-0x00,
-0xc0,
-0xff,
-0xf7,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0xff,
-0x00,
-0xfe,
-0x03,
-0x00,
-0xff,
-0x86,
-0x7f,
-0xfc,
-0x03,
-0xf8,
-0x0f,
-0x01,
-0xfc,
-0x1b,
-0xfe,
-0x7b,
-0x00,
-0xe0,
-0xff,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0x81,
-0x7f,
-0x00,
-0xff,
-0x3f,
-0x80,
-0x7f,
-0xc3,
-0x07,
-0xfe,
-0x01,
-0xfc,
-0xff,
-0x00,
-0xfe,
-0x0d,
-0xff,
-0x3d,
-0x00,
-0xf0,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x1f,
-0xc0,
-0xbf,
-0xfe,
-0x03,
-0xff,
-0x00,
-0x86,
-0x7f,
-0x00,
-0xff,
-0xf8,
-0xff,
-0x1e,
-0x00,
-0xf0,
-0x1f,
-0xf8,
-0x07,
-0x37,
-0xfc,
-0x03,
-0xf8,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x00,
-0xfc,
-0x7f,
-0x0f,
-0x03,
-0xf8,
-0x0f,
-0xfc,
-0xfc,
-0x1b,
-0xfe,
-0x01,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0x07,
-0x00,
-0xfe,
-0xbf,
-0xfe,
-0x01,
-0xfc,
-0x07,
-0x00,
-0xfe,
-0x0d,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0xdf,
-0x03,
-0x00,
-0xff,
-0x03,
-0xff,
-0x00,
-0xfe,
-0x7f,
-0x00,
-0xff,
-0x86,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xef,
-0x01,
-0x80
-};
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/F10RevD32.asm b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/F10RevD32.asm
deleted file mode 100644
index 4112659..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/F10RevD32.asm
+++ /dev/null
@@ -1,113 +0,0 @@
-;/**
-; * @file
-; *
-; * AGESA Family 10h Revision D support routines.
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: CPU/F10
-; * @e \$Revision: 23714 $ @e \$Date: 2009-12-10 07:28:37 +0800 (Thu, 10 Dec 2009) $
-; */
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
- .XLIST
- .LIST
-
- .586P
-
-;===============================================
-;===============================================
-;==
-;== M E M O R Y P R E S E N T S E G M E N T
-;==
-;===============================================
-;===============================================
- .MODEL flat
- .CODE
-
-;======================================================================
-; F10RevDProbeFilterCritical: Performs critical sequence for probe
-; filter initialization.
-;
-; In:
-; PciAddress Full PCI address of the node to init
-; PciRegister Current value of F3x1D4
-;
-;
-; Out:
-; None
-;
-; Destroyed:
-; None
-;
-;======================================================================
-F10RevDProbeFilterCritical PROC NEAR C PUBLIC USES EAX ECX EDX, PciAddress:DWORD, PciRegister:DWORD
-
- mov ecx, 0C001001Fh
- rdmsr
- push eax
- push ecx
- push edx
- or dh, 40h
- wrmsr
-
- mov eax, 810003D4h
-
- mov ecx, PciRegister
- mov edx, PciAddress
- shr edx, 4
- and dh, 0F8h
- or ah, dh
-
- or cl, 2
- db 0Fh, 0AEh, 0F0h ; MFENCE
-
- mov dx, 0CF8h ; Set Reg Config Space
- db 0Fh, 0AEh, 0F0h ; MFENCE
-
- out dx, eax
- db 0Fh, 0AEh, 0F0h ; MFENCE
-
- mov dl, 0FCh ; Set DX to Pci Config Data
- mov eax, ecx ;Set config Reg data
- db 0Fh, 0AEh, 0F0h ; MFENCE
-
- out dx, eax ; move data to return position
- db 0Fh, 0AEh, 0F0h ; MFENCE
-
- pop edx
- pop ecx
- pop eax
- wrmsr
- ret
-
-F10RevDProbeFilterCritical ENDP
-
-END
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/F10RevD64.asm b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/F10RevD64.asm
deleted file mode 100644
index 4353190..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/F10RevD64.asm
+++ /dev/null
@@ -1,127 +0,0 @@
-;/**
-; * @file
-; *
-; * AGESA Family 10h Revision D support routines.
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: CPU/F10
-; * @e \$Revision: 23714 $ @e \$Date: 2009-12-10 07:28:37 +0800 (Thu, 10 Dec 2009) $
-; */
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
- .XLIST
- .LIST
-
-;===============================================
-;===============================================
-;==
-;== M E M O R Y P R E S E N T S E G M E N T
-;==
-;===============================================
-;===============================================
- .CODE
-
-;======================================================================
-; F10RevDProbeFilterCritical: Performs critical sequence for probe
-; filter initialization.
-;
-; In:
-; PciAddress Full PCI address of the node to init
-; PciRegister Current value of F3x1D4
-;
-;
-; Out:
-; None
-;
-; Destroyed:
-; None
-;
-;======================================================================
-PUBLIC F10RevDProbeFilterCritical
-F10RevDProbeFilterCritical PROC
-
- push rax
- push rcx
- push rdx
- push rsi
- push rdi
-
- mov esi, ecx
- mov edi, edx
-
- mov ecx, 0C001001Fh
- rdmsr
- push rax
- push rcx
- push rdx
- or dh, 40h
- wrmsr
-
- mov eax, 810003D4h
-
- mov ecx, edi
- mov edx, esi
-
- shr edx, 4
- and dh, 0F8h
- or ah, dh
-
- or cl, 2
- mfence
-
- mov dx, 0CF8h ; Set Reg Config Space
- mfence
-
- out dx, eax
- mfence
-
- mov dl, 0FCh ; Set DX to Pci Config Data
- mov eax, ecx ;Set config Reg data
- mfence
-
- out dx, eax ; move data to return position
- mfence
-
- pop rdx
- pop rcx
- pop rax
- wrmsr
-
- pop rdi
- pop rsi
- pop rdx
- pop rcx
- pop rax
- ret
-
-F10RevDProbeFilterCritical ENDP
-
-END
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/F10RevDHtAssist.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/F10RevDHtAssist.c
deleted file mode 100644
index 33f7e04..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/F10RevDHtAssist.c
+++ /dev/null
@@ -1,466 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 RevD HT Assist feature support functions.
- *
- * Provides the functions necessary to initialize the HT Assist feature.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "CommonReturns.h"
-#include "cpuRegisters.h"
-#include "cpuF10PowerMgmt.h"
-#include "cpuLateInit.h"
-#include "cpuServices.h"
-#include "GeneralServices.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuHtAssist.h"
-#include "F10PackageType.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVD_F10REVDHTASSIST_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/**
- * The family 10h background scrubber context structure.
- *
- * These fields need to be saved, modified, then restored
- * per die as part of HT Assist initialization.
- */
-typedef struct {
- UINT32 DramScrub:5; ///< DRAM scrub rate
- UINT32 :3; ///< Reserved
- UINT32 L3Scrub:5; ///< L3 scrub rate
- UINT32 :3; ///< Reserved
- UINT32 Redirect:1; ///< DRAM scrubber redirect enable
- UINT32 :15; ///< Reserved
-} F10_SCRUB_CONTEXT;
-
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-extern
-VOID
-F10RevDProbeFilterCritical (
- IN PCI_ADDR PciAddress,
- IN UINT32 PciRegister
- );
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Check to see if the input CPU supports HT Assist.
- *
- * @param[in] HtAssistServices HT Assist family services.
- * @param[in] Socket Processor socket to check.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval TRUE HT Assist is supported.
- * @retval FALSE HT Assist cannot be enabled.
- *
- */
-BOOLEAN
-STATIC
-F10IsHtAssistSupported (
- IN HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
- IN UINT32 Socket,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Module;
- UINT32 PciRegister;
- BOOLEAN IsSupported;
- PCI_ADDR PciAddress;
- AGESA_STATUS IgnoredStatus;
-
- IsSupported = FALSE;
- for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
- if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = NB_CAPS_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- if (((NB_CAPS_REGISTER *) &PciRegister)->L3Capable == 1) {
- IsSupported = TRUE;
- }
- break;
- }
- }
- return IsSupported;
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Enable the Probe filter feature.
- *
- * @param[in] HtAssistServices HT Assist family services.
- * @param[in] Socket Processor socket to check.
- * @param[in] StdHeader Config Handle for library, services.
- *
- */
-VOID
-STATIC
-F10HtAssistInit (
- IN HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
- IN UINT32 Socket,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Module;
- UINT32 PciRegister;
- PCI_ADDR PciAddress;
- AGESA_STATUS IgnoredStatus;
-
- for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
- if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = L3_CACHE_PARAM_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- ((L3_CACHE_PARAM_REGISTER *) &PciRegister)->L3TagInit = 1;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- do {
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- } while (((L3_CACHE_PARAM_REGISTER *) &PciRegister)->L3TagInit != 0);
-
- PciAddress.Address.Register = PROBE_FILTER_CTRL_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- ((PROBE_FILTER_CTRL_REGISTER *) &PciRegister)->PFMode = 0;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
-
- F10RevDProbeFilterCritical (PciAddress, PciRegister);
-
- do {
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- } while (((PROBE_FILTER_CTRL_REGISTER *) &PciRegister)->PFInitDone != 1);
- IDS_OPTION_HOOK (IDS_HT_ASSIST, &PciAddress, StdHeader);
- }
- }
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Save the current settings of the scrubbers, and disabled them.
- *
- * @param[in] HtAssistServices HT Assist family services.
- * @param[in] Socket Processor socket to check.
- * @param[in] ScrubSettings Location to store current L3 scrubber settings.
- * @param[in] StdHeader Config Handle for library, services.
- *
- */
-VOID
-STATIC
-F10GetL3ScrubCtrl (
- IN HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
- IN UINT32 Socket,
- IN UINT32 ScrubSettings[L3_SCRUBBER_CONTEXT_ARRAY_SIZE],
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Module;
- UINT32 ScrubCtrl;
- UINT32 ScrubAddr;
- PCI_ADDR PciAddress;
- AGESA_STATUS IgnoredStatus;
-
- for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
- if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
-
- ASSERT (Module < L3_SCRUBBER_CONTEXT_ARRAY_SIZE);
-
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = DRAM_SCRUB_ADDR_LOW_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &ScrubAddr, StdHeader);
-
- PciAddress.Address.Register = SCRUB_RATE_CTRL_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &ScrubCtrl, StdHeader);
-
- ((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->DramScrub =
- ((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->DramScrub;
- ((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->L3Scrub =
- ((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->L3Scrub;
- ((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->Redirect =
- ((DRAM_SCRUB_ADDR_LOW_REGISTER *) &ScrubAddr)->ScrubReDirEn;
-
- ((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->DramScrub = 0;
- ((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->L3Scrub = 0;
- ((DRAM_SCRUB_ADDR_LOW_REGISTER *) &ScrubAddr)->ScrubReDirEn = 0;
- LibAmdPciWrite (AccessWidth32, PciAddress, &ScrubCtrl, StdHeader);
- PciAddress.Address.Register = DRAM_SCRUB_ADDR_LOW_REG;
- LibAmdPciWrite (AccessWidth32, PciAddress, &ScrubAddr, StdHeader);
- }
- }
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Restore the initial settings for the scrubbers.
- *
- * @param[in] HtAssistServices HT Assist family services.
- * @param[in] Socket Processor socket to check.
- * @param[in] ScrubSettings Location to store current L3 scrubber settings.
- * @param[in] StdHeader Config Handle for library, services.
- *
- */
-VOID
-STATIC
-F10SetL3ScrubCtrl (
- IN HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
- IN UINT32 Socket,
- IN UINT32 ScrubSettings[L3_SCRUBBER_CONTEXT_ARRAY_SIZE],
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Module;
- UINT32 PciRegister;
- PCI_ADDR PciAddress;
- AGESA_STATUS IgnoredStatus;
-
- for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
- if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
-
- ASSERT (Module < L3_SCRUBBER_CONTEXT_ARRAY_SIZE);
-
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = SCRUB_RATE_CTRL_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- ((SCRUB_RATE_CTRL_REGISTER *) &PciRegister)->DramScrub =
- ((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->DramScrub;
- ((SCRUB_RATE_CTRL_REGISTER *) &PciRegister)->L3Scrub =
- ((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->L3Scrub;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
-
- PciAddress.Address.Register = DRAM_SCRUB_ADDR_LOW_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- ((DRAM_SCRUB_ADDR_LOW_REGISTER *) &PciRegister)->ScrubReDirEn =
- ((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->Redirect;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- }
- }
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Set MSR bits required for HT Assist on each core.
- *
- * @param[in] HtAssistServices HT Assist family services.
- * @param[in] StdHeader Config Handle for library, services.
- *
- */
-VOID
-STATIC
-F10HookDisableCache (
- IN HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 MsrRegister;
-
- LibAmdMsrRead (MSR_BU_CFG2, &MsrRegister, StdHeader);
- MsrRegister |= BIT42;
- LibAmdMsrWrite (MSR_BU_CFG2, &MsrRegister, StdHeader);
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Hook before the probe filter initialization sequence.
- *
- * @param[in] HtAssistServices HT Assist family services.
- * @param[in] Socket Processor socket to check.
- * @param[in] StdHeader Config Handle for library, services.
- *
- */
-VOID
-STATIC
-F10HookBeforeInit (
- IN HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
- IN UINT32 Socket,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Module;
- UINT32 PciRegister;
- UINT32 PfCtrlRegister;
- PCI_ADDR PciAddress;
- CPU_LOGICAL_ID LogicalId;
- AGESA_STATUS IgnoredStatus;
- UINT32 PackageType;
-
- GetLogicalIdOfSocket (Socket, &LogicalId, StdHeader);
- PackageType = LibAmdGetPackageType (StdHeader);
-
- PciRegister = 0;
- ((PROBE_FILTER_CTRL_REGISTER *) &PciRegister)->PFWayNum = 2;
- ((PROBE_FILTER_CTRL_REGISTER *) &PciRegister)->PFSubCacheEn = 15;
- ((PROBE_FILTER_CTRL_REGISTER *) &PciRegister)->PFLoIndexHashEn = 1;
- for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
- if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = PROBE_FILTER_CTRL_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &PfCtrlRegister, StdHeader);
- ((PROBE_FILTER_CTRL_REGISTER *) &PciRegister)->PFPreferredSORepl =
- ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFPreferredSORepl;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
-
- // Assumption: all socket use the same CPU package.
- if (((LogicalId.Revision & AMD_F10_D0) != 0) && (PackageType == PACKAGE_TYPE_C32)) {
- // Apply erratum #384
- // Set F2x11C[13:12] = 11b
- PciAddress.Address.Function = FUNC_2;
- PciAddress.Address.Register = 0x11C;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- PciRegister |= 0x3000;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- }
- }
- }
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Check to see if the input CPU is running in the optimal configuration.
- *
- * @param[in] HtAssistServices HT Assist family services.
- * @param[in] Socket Processor socket to check.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval TRUE HT Assist is running sub-optimally.
- * @retval FALSE HT Assist is running optimally.
- *
- */
-BOOLEAN
-F10IsNonOptimalConfig (
- IN HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
- IN UINT32 Socket,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- BOOLEAN IsNonOptimal;
- BOOLEAN IsMemoryPresent;
- UINT32 Module;
- UINT32 PciRegister;
- PCI_ADDR PciAddress;
- AGESA_STATUS IgnoredStatus;
-
- IsNonOptimal = FALSE;
- for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
- if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
- IsMemoryPresent = FALSE;
- PciAddress.Address.Function = FUNC_2;
- PciAddress.Address.Register = DRAM_CFG_HI_REG0;
-
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- if (((DRAM_CFG_HI_REGISTER *) &PciRegister)->MemClkFreqVal == 1) {
- IsMemoryPresent = TRUE;
- if (((DRAM_CFG_HI_REGISTER *) &PciRegister)->MemClkFreq < 4) {
- IsNonOptimal = TRUE;
- break;
- }
- }
-
- PciAddress.Address.Register = DRAM_CFG_HI_REG1;
-
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- if (((DRAM_CFG_HI_REGISTER *) &PciRegister)->MemClkFreqVal == 1) {
- IsMemoryPresent = TRUE;
- if (((DRAM_CFG_HI_REGISTER *) &PciRegister)->MemClkFreq < 4) {
- IsNonOptimal = TRUE;
- break;
- }
- }
- if (!IsMemoryPresent) {
- IsNonOptimal = TRUE;
- break;
- }
- }
- }
- return IsNonOptimal;
-}
-
-
-CONST HT_ASSIST_FAMILY_SERVICES ROMDATA F10HtAssist =
-{
- 0,
- F10IsHtAssistSupported,
- F10HtAssistInit,
- (PF_ATM_MODE_INIT) CommonVoid,
- F10GetL3ScrubCtrl,
- F10SetL3ScrubCtrl,
- F10HookBeforeInit,
- (PF_HT_ASSIST_AFTER_INIT) CommonVoid,
- F10HookDisableCache,
- (PF_HT_ASSIST_ENABLE_CACHE) CommonVoid,
- F10IsNonOptimalConfig
-};
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c
deleted file mode 100644
index 54e0d5f..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c
+++ /dev/null
@@ -1,277 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 RevD Message-Based C1e feature support functions.
- *
- * Provides the functions necessary to initialize the message-based C1e feature.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "cpuRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuFeatures.h"
-#include "cpuServices.h"
-#include "GeneralServices.h"
-#include "cpuMsgBasedC1e.h"
-#include "cpuApicUtilities.h"
-#include "cpuF10PowerMgmt.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVD_F10REVDMSGBASEDC1E_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-VOID
-STATIC
-F10InitializeMsgBasedC1eOnCore (
- IN VOID *BmStsAddress,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-BOOLEAN
-STATIC
-IsDramScrubberEnabled (
- IN PCI_ADDR PciAddress,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Should message-based C1e be enabled
- *
- * @param[in] MsgBasedC1eServices Pointer to this CPU's HW C1e family services.
- * @param[in] Socket Processor socket to check.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval TRUE HW C1e is supported.
- *
- */
-BOOLEAN
-STATIC
-F10IsMsgBasedC1eSupported (
- IN MSG_BASED_C1E_FAMILY_SERVICES *MsgBasedC1eServices,
- IN UINT32 Socket,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- CPU_LOGICAL_ID LogicalId;
-
- GetLogicalIdOfSocket (Socket, &LogicalId, StdHeader);
- return ((BOOLEAN) ((LogicalId.Revision & AMD_F10_GT_D0) != 0));
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Core 0 task to enable message-based C1e on a family 10h CPU.
- *
- * @param[in] MsgBasedC1eServices Pointer to this CPU's HW C1e family services.
- * @param[in] EntryPoint Timepoint designator.
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @return AGESA_SUCCESS Always succeeds.
- *
- */
-AGESA_STATUS
-STATIC
-F10InitializeMsgBasedC1e (
- IN MSG_BASED_C1E_FAMILY_SERVICES *MsgBasedC1eServices,
- IN UINT64 EntryPoint,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 AndMask;
- UINT32 Core;
- UINT32 Module;
- UINT32 OrMask;
- UINT32 PciRegister;
- UINT32 Socket;
- AP_TASK TaskPtr;
- PCI_ADDR PciAddress;
- AGESA_STATUS IgnoredSts;
-
- if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
- // Note that this core 0 does NOT have the ability to launch
- // any of its cores. Attempting to do so could lead to a system
- // hang.
-
- // Set F3xA0[IdleExitEn] = 1
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = PW_CTL_MISC_REG;
- AndMask = 0xFFFFFFFF;
- OrMask = 0;
- ((POWER_CTRL_MISC_REGISTER *) &OrMask)->IdleExitEn = 1;
- ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xA0
-
- // Set F3x188[EnStpGntOnFlushMaskWakeup] = 1
- PciAddress.Address.Register = NB_EXT_CFG_LO_REG;
- OrMask = 0;
- ((NB_EXT_CFG_LO_REGISTER *) &OrMask)->EnStpGntOnFlushMaskWakeup = 1;
- ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x188
-
- // Set F3xD4[MTC1eEn] = 1, F3xD4[CacheFlushImmOnAllHalt] = 1
- // Set F3xD4[StutterScrubEn] = 1 if scrubbing is enabled
- ((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->StutterScrubEn = 0;
- OrMask = 0;
- ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->MTC1eEn = 1;
- ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->CacheFlushImmOnAllHalt = 1;
-
- IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
-
- for (Module = 0; Module < (UINT8)GetPlatformNumberOfModules (); Module++) {
- if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts)) {
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = CPTC0_REG;
- if (IsDramScrubberEnabled (PciAddress, StdHeader)) {
- ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->StutterScrubEn = 1;
- } else {
- ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->StutterScrubEn = 0;
- }
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- PciRegister &= AndMask;
- PciRegister |= OrMask;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- }
- }
-
- } else if (EntryPoint == CPU_FEAT_AFTER_PM_INIT) {
- // At early, this core 0 can launch its subordinate cores.
- TaskPtr.FuncAddress.PfApTaskI = F10InitializeMsgBasedC1eOnCore;
- TaskPtr.DataTransfer.DataSizeInDwords = 1;
- TaskPtr.DataTransfer.DataPtr = &PlatformConfig->C1ePlatformData;
- TaskPtr.DataTransfer.DataTransferFlags = 0;
- TaskPtr.ExeFlags = WAIT_FOR_CORE;
- ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
- }
-
- return AGESA_SUCCESS;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Enable message-based C1e on a family 10h core.
- *
- * @param[in] BmStsAddress System I/O address of the bus master status bit.
- * @param[in] StdHeader Config Handle for library, services.
- *
- */
-VOID
-STATIC
-F10InitializeMsgBasedC1eOnCore (
- IN VOID *BmStsAddress,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 MsrRegister;
-
- // Set MSRC001_0055[SmiOnCmpHalt] = 0, MSRC001_0055[C1eOnCmpHalt] = 0
- LibAmdMsrRead (MSR_INTPEND, &MsrRegister, StdHeader);
- ((INTPEND_MSR *) &MsrRegister)->SmiOnCmpHalt = 0;
- ((INTPEND_MSR *) &MsrRegister)->C1eOnCmpHalt = 0;
- ((INTPEND_MSR *) &MsrRegister)->BmStsClrOnHltEn = 1;
- ((INTPEND_MSR *) &MsrRegister)->IntrPndMsgDis = 0;
- ((INTPEND_MSR *) &MsrRegister)->IntrPndMsg = 0;
- ((INTPEND_MSR *) &MsrRegister)->IoMsgAddr = (UINT64) *((UINT32 *) BmStsAddress);
- LibAmdMsrWrite (MSR_INTPEND, &MsrRegister, StdHeader);
-
- // Set MSRC001_0015[HltXSpCycEn] = 1
- LibAmdMsrRead (MSR_HWCR, &MsrRegister, StdHeader);
- MsrRegister |= BIT12;
- LibAmdMsrWrite (MSR_HWCR, &MsrRegister, StdHeader);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Check to see if the DRAM background scrubbers are enabled or not.
- *
- * @param[in] PciAddress Address of F10 socket/module to check.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval TRUE Memory scrubbers are enabled on the current node.
- * @retval FALSE Memory scrubbers are disabled on the current node.
- */
-BOOLEAN
-STATIC
-IsDramScrubberEnabled (
- IN PCI_ADDR PciAddress,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 PciRegister;
-
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = 0x58;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- return ((BOOLEAN) ((PciRegister & 0x1F) != 0));
-}
-
-
-CONST MSG_BASED_C1E_FAMILY_SERVICES ROMDATA F10MsgBasedC1e =
-{
- 0,
- F10IsMsgBasedC1eSupported,
- F10InitializeMsgBasedC1e
-};
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c
deleted file mode 100644
index 1d46de6..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c
+++ /dev/null
@@ -1,370 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 revision Dx specific utility functions.
- *
- * Provides numerous utility functions specific to family 10h rev D.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuF10PowerMgmt.h"
-#include "GeneralServices.h"
-#include "cpuEarlyInit.h"
-#include "cpuRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVD_F10REVDUTILITIES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Set down core register on a revision D processor.
- *
- * This function set F3x190 Downcore Control Register[5:0]
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] Socket Socket ID.
- * @param[in] Module Module ID in socket.
- * @param[in] LeveledCores Number of core.
- * @param[in] CoreLevelMode Core level mode.
- * @param[in] StdHeader Header for library and services.
- *
- * @retval TRUE Down Core register is updated.
- * @retval FALSE Down Core register is not updated.
- */
-BOOLEAN
-F10CommonRevDSetDownCoreRegister (
- IN CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices,
- IN UINT32 *Socket,
- IN UINT32 *Module,
- IN UINT32 *LeveledCores,
- IN CORE_LEVELING_TYPE CoreLevelMode,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 TempVar32_a;
- UINT32 CoreDisableBits;
- PCI_ADDR PciAddress;
- BOOLEAN IsUpdated;
- AGESA_STATUS AgesaStatus;
-
- IsUpdated = FALSE;
-
- switch (*LeveledCores) {
- case 1:
- CoreDisableBits = DOWNCORE_MASK_SINGLE;
- break;
- case 2:
- CoreDisableBits = DOWNCORE_MASK_DUAL;
- break;
- case 3:
- CoreDisableBits = DOWNCORE_MASK_TRI;
- break;
- case 4:
- CoreDisableBits = DOWNCORE_MASK_FOUR;
- break;
- case 5:
- CoreDisableBits = DOWNCORE_MASK_FIVE;
- break;
- default:
- CoreDisableBits = 0;
- break;
- }
-
- if (CoreDisableBits != 0) {
- if (GetPciAddress (StdHeader, (UINT8) *Socket, (UINT8) *Module, &PciAddress, &AgesaStatus)) {
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = NORTH_BRIDGE_CAPABILITIES_REG;
-
- LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
- TempVar32_a = ((TempVar32_a >> 12) & 0x3) | ((TempVar32_a >> 13) & 0x4);
- if (TempVar32_a == 0) {
- CoreDisableBits &= 0x1;
- } else if (TempVar32_a == 1) {
- CoreDisableBits &= 0x3;
- } else if (TempVar32_a == 2) {
- CoreDisableBits &= 0x7;
- } else if (TempVar32_a == 3) {
- CoreDisableBits &= 0x0F;
- } else if (TempVar32_a == 4) {
- CoreDisableBits &= 0x1F;
- } else if (TempVar32_a == 5) {
- CoreDisableBits &= 0x3F;
- }
- PciAddress.Address.Register = DOWNCORE_CTRL;
- LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
- if ((TempVar32_a | CoreDisableBits) != TempVar32_a) {
- TempVar32_a |= CoreDisableBits;
- LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
- IsUpdated = TRUE;
- }
- }
- }
-
- return IsUpdated;
-}
-
-
-CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevDCoreLeveling =
-{
- 0,
- F10CommonRevDSetDownCoreRegister
-};
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Get CPU pstate current on a revision D processor.
- *
- * @CpuServiceMethod{::F_CPU_GET_IDD_MAX}.
- *
- * This function returns the ProcIddMax.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] Pstate The P-state to check.
- * @param[out] ProcIddMax P-state current in mA.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @retval TRUE P-state is enabled
- * @retval FALSE P-state is disabled
- */
-BOOLEAN
-F10CommonRevDGetProcIddMax (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN UINT8 Pstate,
- OUT UINT32 *ProcIddMax,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 IddDiv;
- UINT32 CmpCap;
- UINT32 MultiNodeCpu;
- UINT32 NbCaps;
- UINT32 Socket;
- UINT32 Module;
- UINT32 Ignored;
- UINT32 MsrAddress;
- UINT64 PstateMsr;
- BOOLEAN IsPstateEnabled;
- PCI_ADDR PciAddress;
- AGESA_STATUS IgnoredSts;
-
- IsPstateEnabled = FALSE;
-
- MsrAddress = (UINT32) (Pstate + PS_REG_BASE);
- ASSERT (MsrAddress <= PS_MAX_REG);
-
- LibAmdMsrRead (MsrAddress, &PstateMsr, StdHeader);
- if (((PSTATE_MSR *) &PstateMsr)->PsEnable == 1) {
- IdentifyCore (StdHeader, &Socket, &Module, &Ignored, &IgnoredSts);
- GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = NB_CAPS_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &NbCaps, StdHeader); // F3xE8
-
- switch (((PSTATE_MSR *) &PstateMsr)->IddDiv) {
- case 0:
- IddDiv = 1000;
- break;
- case 1:
- IddDiv = 100;
- break;
- case 2:
- IddDiv = 10;
- break;
- default: // IddDiv = 3 is reserved. Use 10
- IddDiv = 10;
- break;
- }
- MultiNodeCpu = (UINT32) (((NB_CAPS_REGISTER *) &NbCaps)->MultiNodeCpu + 1);
- CmpCap = (UINT32) (((NB_CAPS_REGISTER *) &NbCaps)->CmpCapHi << 2);
- CmpCap |= (UINT32) (((NB_CAPS_REGISTER *) &NbCaps)->CmpCapLo);
- CmpCap++;
- *ProcIddMax = (UINT32) ((PSTATE_MSR *) &PstateMsr)->IddValue * IddDiv * CmpCap * MultiNodeCpu;
- IsPstateEnabled = TRUE;
- }
- return IsPstateEnabled;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns whether or not BIOS is responsible for configuring the NB COFVID.
- *
- * @CpuServiceMethod{::F_CPU_IS_NBCOF_INIT_NEEDED}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] PciAddress The northbridge to query by pci base address.
- * @param[out] NbVidUpdateAll Do all NbVids need to be updated
- * @param[in] StdHeader Header for library and services
- *
- * @retval TRUE Perform northbridge frequency and voltage config.
- * @retval FALSE Do not configure them.
- */
-BOOLEAN
-F10CommonRevDGetNbCofVidUpdate (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN PCI_ADDR *PciAddress,
- OUT BOOLEAN *NbVidUpdateAll,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- *NbVidUpdateAll = FALSE;
- return FALSE;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Determines the NB clock on the desired node.
- *
- * @CpuServiceMethod{::F_CPU_GET_NB_PSTATE_INFO}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] PlatformConfig Platform profile/build option config structure.
- * @param[in] PciAddress The segment, bus, and device numbers of the CPU in question.
- * @param[in] NbPstate The NB P-state number to check.
- * @param[out] FreqNumeratorInMHz The desired node's frequency numerator in megahertz.
- * @param[out] FreqDivisor The desired node's frequency divisor.
- * @param[out] VoltageInuV The desired node's voltage in microvolts.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @retval TRUE NbPstate is valid
- * @retval FALSE NbPstate is disabled or invalid
- */
-BOOLEAN
-F10CommonRevDGetNbPstateInfo (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN PCI_ADDR *PciAddress,
- IN UINT32 NbPstate,
- OUT UINT32 *FreqNumeratorInMHz,
- OUT UINT32 *FreqDivisor,
- OUT UINT32 *VoltageInuV,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 PciRegister;
- UINT64 MsrRegister;
- BOOLEAN PstateIsValid;
-
- PstateIsValid = FALSE;
- if (NbPstate == 0) {
- PciAddress->Address.Function = FUNC_3;
- PciAddress->Address.Register = CPTC0_REG;
- LibAmdPciRead (AccessWidth32, *PciAddress, &PciRegister, StdHeader);
- *FreqNumeratorInMHz = ((((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->NbFid + 4) * 200);
- *FreqDivisor = 1;
- LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
- *VoltageInuV = (1550000 - (12500 * ((UINT32) ((COFVID_STS_MSR *) &MsrRegister)->CurNbVid)));
- PstateIsValid = TRUE;
- }
- return PstateIsValid;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Get number of processor cores to be used in determining the brand string.
- *
- * @CpuServiceMethod{::F_CPU_NUMBER_OF_BRANDSTRING_CORES}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @return The number of cores to be used in brand string calculation.
- */
-UINT8
-F10CommonRevDGetNumberOfCoresForBrandstring (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 CmpCap;
- UINT32 CmpCapOnNode;
- UINT32 Socket;
- UINT32 Module;
- UINT32 Core;
- UINT32 PciRegister;
- PCI_ADDR PciAddress;
- AGESA_STATUS IgnoredSts;
-
- CmpCap = 0;
- IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
- for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
- if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts)) {
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = NB_CAPS_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- CmpCapOnNode = (UINT8) (((NB_CAPS_REGISTER *) &PciRegister)->CmpCapHi << 2);
- CmpCapOnNode |= (UINT8) (((NB_CAPS_REGISTER *) &PciRegister)->CmpCapLo);
- CmpCapOnNode++;
- CmpCap += CmpCapOnNode;
- }
- }
- return ((UINT8) CmpCap);
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c
deleted file mode 100644
index 6b43faa..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Hydra Equivalence Table related data
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/Family/0x10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYEQUIVALENCETABLE_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-STATIC CONST UINT16 ROMDATA CpuF10HyMicrocodeEquivalenceTable[] =
-{
- 0x1080, 0x1080,
- 0x1081, 0x1081,
- 0x1091, 0x1081
-};
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns the appropriate microcode patch equivalent ID table.
- *
- * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[out] HyEquivalenceTablePtr Points to the first entry in the table.
- * @param[out] NumberOfElements Number of valid entries in the table.
- * @param[in] StdHeader Header for library and services.
- *
- */
-VOID
-GetF10HyMicrocodeEquivalenceTable (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- OUT CONST VOID **HyEquivalenceTablePtr,
- OUT UINT8 *NumberOfElements,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- *NumberOfElements = ((sizeof (CpuF10HyMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
- *HyEquivalenceTablePtr = CpuF10HyMicrocodeEquivalenceTable;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyHtPhyTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyHtPhyTables.c
deleted file mode 100644
index fd8d90b..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyHtPhyTables.c
+++ /dev/null
@@ -1,1295 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Hydra Ht Phy tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYHTPHYTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-// HT Phy T a b l e s
-// -------------------------
-STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10HyHtPhyRegisters[] =
-{
-// 0x60:0x68
- {
- HtPhyRangeRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_GT_C0 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- HTPHY_LINKTYPE_SL0_ALL, //
- 0x60, 0x68, // Address
- 0x00000040, // regData
- 0x00000040, // regMask
- }
- },
-// 0x70:0x78
- {
- HtPhyRangeRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_GT_C0 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- HTPHY_LINKTYPE_SL1_ALL, //
- 0x70, 0x78, // Address
- 0x00000040, // regData
- 0x00000040, // regMask
- }
- },
-// 0xC0
- {
- HtPhyRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_HY_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- HTPHY_LINKTYPE_SL0_ALL, //
- 0xC0, // Address
- 0x40040000, // regData
- 0xe01F0000, // regMask
- }
- },
-// 0xD0
- {
- HtPhyRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_HY_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- HTPHY_LINKTYPE_SL1_ALL, //
- 0xD0, // Address
- 0x40040000, // regData
- 0xe01F0000, // regMask
- }
- },
-// 0xCF
-// Default for HT3, unless overridden below.
- {
- HtPhyRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_HY_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xCF, // Address
- 0x0000002A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xDF
-// Default for HT3, unless overridden below.
- {
- HtPhyRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_HY_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xDF, // Address
- 0x0000002A, // regData
- 0x000000FF, // regMask
- }
- },
-
-//
-// All the entries for XmtRdPtr 6
-//
-
-// 0xCF
-// For HT frequencies 1200-1600 and NB Freq 1600, 1800
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_HY_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_1200M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
- (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
- 0xCF, // Address
- 0x0000006A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xDF
-// For HT frequencies 1200-1600 and NB Freq 1600, 1800
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_HY_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_1200M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
- (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
- 0xDF, // Address
- 0x0000006A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xCF
-// For HT frequencies 1800 and NB Freq 1800
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_HY_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
- (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
- 0xCF, // Address
- 0x0000006A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xDF
-// For HT frequencies 1800 and NB Freq 1800
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_HY_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
- (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
- 0xDF, // Address
- 0x0000006A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xCF
-// For HT frequencies 3200 and NB Freq 1600
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_HY_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_3200M, HT_FREQUENCY_3200M) | COUNT_RANGE_NONE),
- (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
- 0xCF, // Address
- 0x0000006A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xDF
-// For HT frequencies 3200 and NB Freq 1600
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_HY_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_3200M, HT_FREQUENCY_3200M) | COUNT_RANGE_NONE),
- (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
- 0xDF, // Address
- 0x0000006A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xCF
-// For HT frequencies 1200 and 1600 and NB Freq 1600 only for link 1
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_HY_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_1200M, HT_FREQUENCY_1200M) | FREQ_RANGE_1 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M)),
- (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL0_LINK1),
- 0xCF, // Address
- 0x0000006A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xDF
-// For HT frequencies 1200 and 1600 and NB Freq 1600 only for link 1
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_HY_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_1200M, HT_FREQUENCY_1200M) | FREQ_RANGE_1 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M)),
- (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL1_LINK5),
- 0xDF, // Address
- 0x0000006A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xCF
-// For HT frequencies 1200 and 1800 and NB Freq 1800 only for link 1
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_HY_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_1200M, HT_FREQUENCY_1200M) | FREQ_RANGE_1 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M)),
- (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL0_LINK1),
- 0xCF, // Address
- 0x0000006A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xDF
-// For HT frequencies 1200 and 1800 and NB Freq 1800 only for link 1
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_HY_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_1200M, HT_FREQUENCY_1200M) | FREQ_RANGE_1 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M)),
- (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL1_LINK5),
- 0xDF, // Address
- 0x0000006A, // regData
- 0x000000FF, // regMask
- }
- },
-
-//
-// Entries for XmtRdPtr 5
-//
-
-// 0xCF
-// For HT frequencies 1800-2600 and NB Freq 1600
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_HY_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_2600M) | COUNT_RANGE_NONE),
- (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
- 0xCF, // Address
- 0x0000005A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xDF
-// For HT frequencies 1800-2600 and NB Freq 1600
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_HY_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_2600M) | COUNT_RANGE_NONE),
- (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
- 0xDF, // Address
- 0x0000005A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xCF
-// For HT frequencies 2000 - 2800 and NB Freq 1800
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_HY_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_2000M, HT_FREQUENCY_2800M) | COUNT_RANGE_NONE),
- (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
- 0xCF, // Address
- 0x0000005A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xDF
-// For HT frequencies 2000 - 2800 and NB Freq 1800
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_HY_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_2000M, HT_FREQUENCY_2800M) | COUNT_RANGE_NONE),
- (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
- 0xDF, // Address
- 0x0000005A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xCF
-// For HT frequencies 1400 and 1800 and NB Freq 1600 only for link 1
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_HY_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_1400M, HT_FREQUENCY_1400M) | FREQ_RANGE_1 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M)),
- (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL0_LINK1),
- 0xCF, // Address
- 0x0000005A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xDF
-// For HT frequencies 1400 and 1800 and NB Freq 1600 only for link 1
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_HY_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_1400M, HT_FREQUENCY_1400M) | FREQ_RANGE_1 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M)),
- (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL1_LINK5),
- 0xDF, // Address
- 0x0000005A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xCF
-// For HT frequencies 1400 and 1600 and NB Freq 1800 only for link 1
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_HY_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_1400M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
- (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL0_LINK1),
- 0xCF, // Address
- 0x0000005A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xDF
-// For HT frequencies 1400 and 1600 and NB Freq 1800 only for link 1
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_HY_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_1400M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
- (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL1_LINK5),
- 0xDF, // Address
- 0x0000005A, // regData
- 0x000000FF, // regMask
- }
- },
-
-//
-// Entries for XmtRdPtr 4
-//
-
-// 0xCF
-// For HT frequencies 2800-3000 and NB Freq 1600
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_HY_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_2800M, HT_FREQUENCY_3000M) | COUNT_RANGE_NONE),
- (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
- 0xCF, // Address
- 0x0000004A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xDF
-// For HT frequencies 2800-3000 and NB Freq 1600
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_HY_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_2800M, HT_FREQUENCY_3000M) | COUNT_RANGE_NONE),
- (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
- 0xDF, // Address
- 0x0000004A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xCF
-// For HT frequencies 3000 - 3200 and NB Freq 1800
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_HY_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_3000M, HT_FREQUENCY_3200M) | COUNT_RANGE_NONE),
- (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
- 0xCF, // Address
- 0x0000004A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xDF
-// For HT frequencies 3000 - 3200 and NB Freq 1800
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_HY_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_3000M, HT_FREQUENCY_3200M) | COUNT_RANGE_NONE),
- (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
- 0xDF, // Address
- 0x0000004A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xCF
-// For HT frequencies 2000 - 2400 and 3200 and NB Freq 1600 only for link 1
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_HY_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_2000M, HT_FREQUENCY_2400M) | FREQ_RANGE_1 (HT_FREQUENCY_3200M, HT_FREQUENCY_3200M)),
- (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL0_LINK1),
- 0xCF, // Address
- 0x0000004A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xDF
-// For HT frequencies 2000 - 2400 and 3200 and NB Freq 1600 only for link 1
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_HY_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_2000M, HT_FREQUENCY_2400M) | FREQ_RANGE_1 (HT_FREQUENCY_3200M, HT_FREQUENCY_3200M)),
- (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL1_LINK5),
- 0xDF, // Address
- 0x0000004A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xCF
-// For HT frequencies 2000 - 2400 and NB Freq 1800 only for link 1
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_HY_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_2000M, HT_FREQUENCY_2400M) | COUNT_RANGE_NONE),
- (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL0_LINK1),
- 0xCF, // Address
- 0x0000004A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xDF
-// For HT frequencies 2000 - 2400 and NB Freq 1800 only for link 1
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_HY_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_2000M, HT_FREQUENCY_2400M) | COUNT_RANGE_NONE),
- (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL1_LINK5),
- 0xDF, // Address
- 0x0000004A, // regData
- 0x000000FF, // regMask
- }
- },
-
-//
-// Entries for XmtRdPtr 3
-//
-
-// 0xCF
-// For HT frequencies 2600-3000 and NB Freq 1600 only for link 1
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_HY_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_2600M, HT_FREQUENCY_3000M) | COUNT_RANGE_NONE),
- (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL0_LINK1),
- 0xCF, // Address
- 0x0000003A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xDF
-// For HT frequencies 2600-3000 and NB Freq 1600 only for link 1
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_HY_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_2600M, HT_FREQUENCY_3000M) | COUNT_RANGE_NONE),
- (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL1_LINK5),
- 0xDF, // Address
- 0x0000003A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xCF
-// For HT frequencies 2600 - 3200 and NB Freq 1800 only for link 1
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_HY_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_2600M, HT_FREQUENCY_3200M) | COUNT_RANGE_NONE),
- (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL0_LINK1),
- 0xCF, // Address
- 0x0000003A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xDF
-// For HT frequencies 2600 - 3200 and NB Freq 1800 only for link 1
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_HY_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_2600M, HT_FREQUENCY_3200M) | COUNT_RANGE_NONE),
- (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL1_LINK5),
- 0xDF, // Address
- 0x0000003A, // regData
- 0x000000FF, // regMask
- }
- },
-
-//
-// Rev D0 fixups for Erratum 398.
-//
-
-// 0xCF
-// For HT frequencies 1800, 2200 and NB Freq 1400
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_D0 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | FREQ_RANGE_1 (HT_FREQUENCY_2200M, HT_FREQUENCY_2200M)),
- (FREQ_RANGE_0 (HT_FREQUENCY_1400M, HT_FREQUENCY_1400M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK1 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
- 0xCF, // Address
- 0x0000000A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xDF
-// For HT frequencies 1800, 2200 and NB Freq 1400
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_D0 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | FREQ_RANGE_1 (HT_FREQUENCY_2200M, HT_FREQUENCY_2200M)),
- (FREQ_RANGE_0 (HT_FREQUENCY_1400M, HT_FREQUENCY_1400M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK5 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
- 0xDF, // Address
- 0x0000000A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xCF
-// For HT frequencies 2600, 3000 and NB Freq 1400
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_D0 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_2600M, HT_FREQUENCY_2600M) | FREQ_RANGE_1 (HT_FREQUENCY_3000M, HT_FREQUENCY_3000M)),
- (FREQ_RANGE_0 (HT_FREQUENCY_1400M, HT_FREQUENCY_1400M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK1 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
- 0xCF, // Address
- 0x0000000A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xDF
-// For HT frequencies 2600, 3000 and NB Freq 1400
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_D0 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_2600M, HT_FREQUENCY_2600M) | FREQ_RANGE_1 (HT_FREQUENCY_3000M, HT_FREQUENCY_3000M)),
- (FREQ_RANGE_0 (HT_FREQUENCY_1400M, HT_FREQUENCY_1400M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK5 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
- 0xDF, // Address
- 0x0000000A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xCF
-// For HT frequencies 2200, 2600 and NB Freq 1600
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_D0 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_2200M, HT_FREQUENCY_2200M) | FREQ_RANGE_1 (HT_FREQUENCY_2600M, HT_FREQUENCY_2600M)),
- (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
- 0xCF, // Address
- 0x0000003A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xDF
-// For HT frequencies 2200, 2600 and NB Freq 1600
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_D0 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_2200M, HT_FREQUENCY_2200M) | FREQ_RANGE_1 (HT_FREQUENCY_2600M, HT_FREQUENCY_2600M)),
- (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
- 0xDF, // Address
- 0x0000003A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xCF
-// For HT frequencies 3000 and NB Freq 1600
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_D0 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_3000M, HT_FREQUENCY_3000M) | COUNT_RANGE_NONE),
- (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
- 0xCF, // Address
- 0x0000002A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xDF
-// For HT frequencies 3000 and NB Freq 1600
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_D0 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_3000M, HT_FREQUENCY_3000M) | COUNT_RANGE_NONE),
- (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
- 0xDF, // Address
- 0x0000002A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xCF
-// For HT frequencies 2200, 2600 and NB Freq 1800
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_D0 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_2200M, HT_FREQUENCY_2200M) | FREQ_RANGE_1 (HT_FREQUENCY_2600M, HT_FREQUENCY_2600M)),
- (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
- 0xCF, // Address
- 0x0000003A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xDF
-// For HT frequencies 2200, 2600 and NB Freq 1800
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_D0 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_2200M, HT_FREQUENCY_2200M) | FREQ_RANGE_1 (HT_FREQUENCY_2600M, HT_FREQUENCY_2600M)),
- (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
- 0xDF, // Address
- 0x0000003A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xCF
-// For HT frequencies 3000 and NB Freq 1800
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_D0 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_3000M, HT_FREQUENCY_3000M) | COUNT_RANGE_NONE),
- (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
- 0xCF, // Address
- 0x0000002A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xDF
-// For HT frequencies 3000 and NB Freq 1800
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_D0 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_3000M, HT_FREQUENCY_3000M) | COUNT_RANGE_NONE),
- (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
- 0xDF, // Address
- 0x0000002A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xCF
-// For HT frequencies 1800 and NB Freq 1600 for all links
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_D0 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
- (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK1 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
- 0xCF, // Address
- 0x0000003A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xDF
-// For HT frequencies 1800 and NB Freq 1600 for all links
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_D0 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_1800M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
- (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL1_LINK4 | HTPHY_LINKTYPE_SL1_LINK5 | HTPHY_LINKTYPE_SL1_LINK6 | HTPHY_LINKTYPE_SL1_LINK7),
- 0xDF, // Address
- 0x0000003A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xCF
-// For HT frequencies 2200 and NB Freq 1600, 1800 only for link 1
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_D0 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_2200M, HT_FREQUENCY_2200M) | COUNT_RANGE_NONE),
- (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL0_LINK1),
- 0xCF, // Address
- 0x0000002A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xDF
-// For HT frequencies 2200 and NB Freq 1600, 1800 only for link 1
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_D0 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_2200M, HT_FREQUENCY_2200M) | COUNT_RANGE_NONE),
- (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL1_LINK5),
- 0xDF, // Address
- 0x0000002A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xCF
-// For HT frequencies 2600, 3000 and NB Freq 1600, 1800 only for link 1
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_D0 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_2600M, HT_FREQUENCY_2600M) | FREQ_RANGE_1 (HT_FREQUENCY_3000M, HT_FREQUENCY_3000M)),
- (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL0_LINK1),
- 0xCF, // Address
- 0x0000001A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xDF
-// For HT frequencies 2600, 3000 and NB Freq 1600, 1800 only for link 1
- {
- HtPhyFreqRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_D0 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- (FREQ_RANGE_0 (HT_FREQUENCY_2600M, HT_FREQUENCY_2600M) | FREQ_RANGE_1 (HT_FREQUENCY_3000M, HT_FREQUENCY_3000M)),
- (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
- (HTPHY_LINKTYPE_SL1_LINK5),
- 0xDF, // Address
- 0x0000001A, // regData
- 0x000000FF, // regMask
- }
- },
-
-//
-// Deemphasis Settings for D1 processors.
-//
-
-// For D1, also set [7]TxLs23ClkGateEn.
-//deemphasis level DL1[20:16], DL2[12:8], DP1[4:0] PostCur1En[31] PostCur2En[30] PreCur1En[29] MapPostCur2En[6]
-// No deemphasis 00h 00h 00h 0 0 0 0
-// -3dB postcursor 12h 00h 00h 1 0 0 0
-// -6dB postcursor 1Fh 00h 00h 1 0 0 0
-// -8dB postcursor 1Fh 06h 00h 1 1 0 1
-// -11dB postcursor 1Fh 0Dh 00h 1 1 0 1
-// -11dB postcursor with
-// -8dB precursor 1Fh 06h 07h 1 1 1 1
-
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10_HY, // CpuFamily
- AMD_F10_D1 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL_NONE,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0x00000080, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10_HY, // CpuFamily
- AMD_F10_D1 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL_NONE,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0x00000080, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10_HY, // CpuFamily
- AMD_F10_D1 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__3,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0x80120080, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10_HY, // CpuFamily
- AMD_F10_D1 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__3,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0x80120080, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10_HY, // CpuFamily
- AMD_F10_D1 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__6,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0x801F0080, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10_HY, // CpuFamily
- AMD_F10_D1 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__6,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0x801F0080, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10_HY, // CpuFamily
- AMD_F10_D1 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__8,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0xC01F06C0, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10_HY, // CpuFamily
- AMD_F10_D1 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__8,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0xC01F06C0, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10_HY, // CpuFamily
- AMD_F10_D1 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__11,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0xC01F0DC0, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10_HY, // CpuFamily
- AMD_F10_D1 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__11,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0xC01F0DC0, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10_HY, // CpuFamily
- AMD_F10_D1 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__11_8,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0xE01F06C7, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10_HY, // CpuFamily
- AMD_F10_D1 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__11_8,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0xE01F06C7, // regData
- 0xE01F1FDF, // regMask
- }
- },
-
-// 0x520A
- {
- HtPhyRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_HY_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- HTPHY_LINKTYPE_SL0_ALL, //
- 0x520A, // Address
- 0x00004000, // regData
- 0x00006000, // regMask
- }
- },
-// 0x530A
- {
- HtPhyRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_HY_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- HTPHY_LINKTYPE_SL1_ALL, //
- 0x530A, // Address
- 0x00004000, // regData
- 0x00006000, // regMask
- }
- },
-};
-
-CONST REGISTER_TABLE ROMDATA F10HyHtPhyRegisterTable = {
- PrimaryCores,
- (sizeof (F10HyHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
- F10HyHtPhyRegisters,
-};
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c
deleted file mode 100644
index ecb0b0d..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Implements the workaround for erratum 419.
- *
- * Returns the table of initialization steps to perform at
- * AmdInitEarly.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x10/RevD/HY
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "cpuRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "F10PackageType.h"
-#include "cpuEarlyInit.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYINITEARLYTABLE_FILECODE
-
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-extern F_PERFORM_EARLY_INIT_ON_CORE McaInitializationAtEarly;
-extern F_PERFORM_EARLY_INIT_ON_CORE SetRegistersFromTablesAtEarly;
-extern F_PERFORM_EARLY_INIT_ON_CORE SetBrandIdRegistersAtEarly;
-extern F_PERFORM_EARLY_INIT_ON_CORE LocalApicInitializationAtEarly;
-extern F_PERFORM_EARLY_INIT_ON_CORE LoadMicrocodePatchAtEarly;
-extern F_GET_EARLY_INIT_TABLE GetF10EarlyInitOnCoreTable;
-
-CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F10HyC32D0EarlyInitOnCoreTable[] =
-{
- {McaInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION},
- {SetRegistersFromTablesAtEarly, PERFORM_EARLY_ANY_CONDITION},
- {LocalApicInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION},
- {LoadMicrocodePatchAtEarly, PERFORM_EARLY_WARM_RESET},
- {SetBrandIdRegistersAtEarly, PERFORM_EARLY_ANY_CONDITION},
- {NULL, 0}
-};
-
-/*------------------------------------------------------------------------------------*/
-/**
- * Initializer routine that may be invoked at AmdCpuEarly to return the steps
- * appropriate for the executing Rev D core.
- *
- * @CpuServiceMethod{::F_GET_EARLY_INIT_TABLE}.
- *
- * @param[in] FamilyServices The current Family Specific Services.
- * @param[out] Table Table of appropriate init steps for the executing core.
- * @param[in] EarlyParams Service Interface structure to initialize.
- * @param[in] StdHeader Opaque handle to standard config header.
- *
- */
-VOID
-GetF10HyEarlyInitOnCoreTable (
- IN CPU_SPECIFIC_SERVICES *FamilyServices,
- OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table,
- IN AMD_CPU_EARLY_PARAMS *EarlyParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 ProcessorPackageType;
- CPU_LOGICAL_ID LogicalId;
-
- GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
- ProcessorPackageType = LibAmdGetPackageType (StdHeader);
-
- // Check if this CPU is affected by erratum 419.
- if (((LogicalId.Revision & AMD_F10_HY_SCM_D0) != 0) && ((ProcessorPackageType & (PACKAGE_TYPE_G34 | PACKAGE_TYPE_FR2_FR5_FR6)) == 0)) {
- // Return initialization steps such that the microcode patch is applied before
- // brand string determination is performed.
- *Table = F10HyC32D0EarlyInitOnCoreTable;
- } else {
- // No workaround is necessary. Return the standard table.
- GetF10EarlyInitOnCoreTable (FamilyServices, Table, EarlyParams, StdHeader);
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c
deleted file mode 100644
index f0362f0..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Hydra Logical ID Table
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYLOGICALIDTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF10HyLogicalIdAndRevArray[] =
-{
- {
- 0x1080,
- AMD_F10_HY_SCM_D0
- },
- {
- 0x1090,
- AMD_F10_HY_MCM_D0
- },
- {
- 0x1081,
- AMD_F10_HY_SCM_D1
- },
- {
- 0x1091,
- AMD_F10_HY_MCM_D1
- }
-};
-
-VOID
-GetF10HyLogicalIdAndRev (
- OUT CONST CPU_LOGICAL_ID_XLAT **HyIdPtr,
- OUT UINT8 *NumberOfElements,
- OUT UINT64 *LogicalFamily,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- *NumberOfElements = (sizeof (CpuF10HyLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT));
- *HyIdPtr = CpuF10HyLogicalIdAndRevArray;
- *LogicalFamily = AMD_FAMILY_10_HY;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c
deleted file mode 100644
index 5d9555c..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Hydra PCI tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/Family/0x10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMICROCODEPATCHTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-extern CONST MICROCODE_PATCHES ROMDATA *CpuF10HyMicroCodePatchArray[];
-extern CONST UINT8 ROMDATA CpuF10HyNumberOfMicrocodePatches;
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns a table containing the appropriate microcode patches.
- *
- * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[out] HyUcodePtr Points to the first entry in the table.
- * @param[out] NumberOfElements Number of valid entries in the table.
- * @param[in] StdHeader Header for library and services.
- *
- */
-VOID
-GetF10HyMicroCodePatchesStruct (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- OUT CONST VOID **HyUcodePtr,
- OUT UINT8 *NumberOfElements,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- *NumberOfElements = CpuF10HyNumberOfMicrocodePatches;
- *HyUcodePtr = &CpuF10HyMicroCodePatchArray[0];
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c
deleted file mode 100644
index 82a52e3..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 HY MSR tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMSRTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10HyMsrRegisters[] =
-{
-// M S R T a b l e s
-// ----------------------
-
-// MSR_LS_CFG (0xC0011020)
-// bit[1] = 0
- {
- MsrRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_GT_B0 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MSR_LS_CFG, // MSR Address
- 0x0000000000000000, // OR Mask
- (1 << 1) // NAND Mask
- }
- },
-
-// MSR_BU_CFG (0xC0011023)
-// bit[21] = 1
- {
- MsrRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_GT_B0 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MSR_BU_CFG, // MSR Address
- (1 << 21), // OR Mask
- (1 << 21), // NAND Mask
- }
- },
-
-// MSR_BU_CFG2 (0xC001102A)
-// bit[50] = 1
-// For GH rev C1 and later [RdMmExtCfgQwEn]=1
- {
- MsrRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_GT_C0 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MSR_BU_CFG2, // MSR Address
- 0x0004000000000000, // OR Mask
- 0x0004000000000000, // NAND Mask
- }
- }
-};
-
-CONST REGISTER_TABLE ROMDATA F10HyMsrRegisterTable = {
- AllCores,
- (sizeof (F10HyMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
- (TABLE_ENTRY_FIELDS *) &F10HyMsrRegisters,
-};
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c
deleted file mode 100644
index 18026de..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c
+++ /dev/null
@@ -1,350 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Hydra PCI tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYPCITABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-// P C I T a b l e s
-// ----------------------
-
-STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10HyPciRegisters[] =
-{
-// F0x68 -
- // BufRelPri for rev D
- // bits[14:13] BufRelPri = 1
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Dx // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO(0, 0, 24, FUNC_0, 0x68), // Address
- 0x00002000, // regData
- 0x00006000, // regMask
- }
- },
-// F0x150 - Link Global Retry Control Register
-// bit[18:16] TotalRetryAttempts = 7
-// bit[13] HtRetryCrcDatInsDynEn = 1
-// bit[12]HtRetryCrcCmdPackDynEn = 1
-// bit[11:9] HtRetryCrcDatIns = 0
-// bit[8] HtRetryCrcCmdPack = 1
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_D0 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_0, 0x150), // Address
- 0x00073100, // regData
- 0x00073F00, // regMask
- }
- },
-// F0x16C - Link Global Extended Control Register
-// bit[15:13] ForceFullT0 = 6
-// bit[5:0] T0Time = 0x26
- {
- PciRegister,
- {
- AMD_FAMILY_10_HY, // CpuFamily
- AMD_F10_D1 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
- 0x0000C026, // regData
- 0x0000E03F, // regMask
- }
- },
-// F0x16C - Link Global Extended Control Register
-// bit[9] RXCalEn = 1
- {
- PciRegister,
- {
- AMD_FAMILY_10_HY, // CpuFamily
- AMD_F10_Dx // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
- 0x00000200, // regData
- 0x00000200, // regMask
- }
- },
-// F0x16C - Link Global Extended Control Register
-// bit[7:6] InLnSt = 01b (PHY_OFF)
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Dx // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
- 0x00000040, // regData
- 0x000000C0, // regMask
- }
- },
-// F0x[18C:170] - Link Extended Control Register - All connected links.
-// bit[8] LS2En = 1
- {
- HtLinkPciRegister,
- {
- AMD_FAMILY_10_HY, // CpuFamily
- AMD_F10_D1 // CpuRevision
- },
- AMD_PF_ALL, // platform Features
- {
- HT_HOST_FEATURES_ALL,
- MAKE_SBDFO (0, 0, 24, FUNC_0, 0x170), // Address
- 0x00000100, // regData
- 0x00000100, // regMask
- }
- },
-// F2x1B0 - Extended Memory Controller Configuration Low
-// bits[10:8], CohPrefPrbLmt = 0
- {
- ProfileFixup,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Dx // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- PERFORMANCE_PROBEFILTER, // Features
- MAKE_SBDFO (0, 0, 24, FUNC_2, 0x1B0), // Address
- 0x00000000, // regData
- 0x00000700, // regMask
- }
- },
-// Function 3 - Misc. Control
-// F3x158 - Link to XCS Token Count
-// bits[3:0] LnkToXcsDRToken = 3
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_GT_A2 // CpuRevision
- },
- AMD_PF_UMA, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x158), // Address
- 0x00000003, // regData
- 0x0000000F, // regMask
- }
- },
-
-// F3x80 - ACPI Power State Control
-// ACPI State C2
-// bits[0] CpuPrbEn = 1
-// bits[1] NbLowPwrEn = 0
-// bits[2] NbGateEn = 0
-// bits[3] NbCofChg = 0
-// bits[4] AltVidEn = 0
-// bits[7:5] ClkDivisor = 1
-// ACPI State C3, C1E or Link init
-// bits[0] CpuPrbEn = 0
-// bits[1] NbLowPwrEn = 1
-// bits[2] NbGateEn = 1
-// bits[3] NbCofChg = 0
-// bits[4] AltVidEn = 0
-// bits[7:5] ClkDivisor = 5
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_GT_Ax // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address
- 0x0000A681, // regData
- 0x0000FFFF, // regMask
- }
- },
-
-// F3x80 - ACPI Power State Control
-// ACPI State C3, C1E or Link init
-// bits[0] CpuPrbEn = 0
-// bits[1] NbLowPwrEn = 1
-// bits[2] NbGateEn = 1
-// bits[3] NbCofChg = 0
-// bits[4] AltVidEn = 0
-// bits[7:5] ClkDivisor = 7
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_GT_D0 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address
- 0x0000E600, // regData
- 0x0000FF00, // regMask
- }
- },
-
-// F3xA0 - Power Control Miscellaneous
-// bit[14] BpPinsTriEn = 1
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_GT_D0 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0), // Address
- 0x00004000, // regData
- 0x00004000, // regMask
- }
- },
-
-// F3x188 - NB Extended Configuration Low Register
-// bit[27] = DisCpuWrSzDw64ReOrd
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_D0 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address
- 0x08000000, // regData
- 0x08000000, // regMask
- }
- },
-
-// F3x1B8 - L3 Control
-// bit[18] L3RdBufBypDis = 1, Erratum 374
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_D0 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1B8), // Address
- 0x00040000, // regData
- 0x00040000, // regMask
- }
- },
-
-// F3x1B8 - L3 Control
-// bit[23] L3BankSwapDis = 1, Erratum 385
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Dx // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1B8), // Address
- 0x00800000, // regData
- 0x00800000, // regMask
- }
- },
-
-// F3x1D4 - Probe Filter Control Register
-// bits[21:20] PFPreferedSORepl = 2
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Dx // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1D4), // Address
- 0x00200000, // regData
- 0x00300000, // regMask
- }
- }
-};
-
-CONST REGISTER_TABLE ROMDATA F10HyPciRegisterTable = {
- PrimaryCores,
- (sizeof (F10HyPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
- F10HyPciRegisters,
-};
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevE/F10MicrocodePatch010000bf.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevE/F10MicrocodePatch010000bf.c
deleted file mode 100644
index 857e9d5..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevE/F10MicrocodePatch010000bf.c
+++ /dev/null
@@ -1,1040 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Microcode patch.
- *
- * Fam10 Microcode Patch rev 010000bf for 10a0 or equivalent.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x10/REVC
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-// Patch code 010000bf for 10a0 and equivalent
-CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000bf =
-{
-0x10,
-0x20,
-0x17,
-0x02,
-0xbf,
-0x00,
-0x00,
-0x01,
-0x00,
-0x80,
-0x20,
-0x00,
-0x42,
-0x82,
-0x02,
-0x39,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0xa0,
-0x10,
-0x00,
-0x00,
-0x00,
-0xaa,
-0xaa,
-0xaa,
-0x74,
-0x0f,
-0x00,
-0x00,
-0xbe,
-0x01,
-0x00,
-0x00,
-0x33,
-0x0e,
-0x00,
-0x00,
-0xa9,
-0x01,
-0x00,
-0x00,
-0x75,
-0x00,
-0x00,
-0x00,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xa0,
-0xfd,
-0xff,
-0x28,
-0xc3,
-0x3f,
-0xc0,
-0xcf,
-0xff,
-0x07,
-0xe2,
-0x01,
-0x0f,
-0xde,
-0x50,
-0xfe,
-0xf2,
-0xdf,
-0xff,
-0x0f,
-0x3b,
-0xfc,
-0x01,
-0xc5,
-0x40,
-0x03,
-0xd4,
-0x00,
-0x80,
-0xff,
-0xfe,
-0x7f,
-0xfe,
-0xe1,
-0x1b,
-0xc8,
-0x5b,
-0xf6,
-0xff,
-0xff,
-0x7b,
-0x87,
-0x5f,
-0xad,
-0x6b,
-0xf9,
-0x6f,
-0xfe,
-0xfa,
-0x1f,
-0xfe,
-0xb5,
-0x00,
-0x40,
-0x11,
-0x6a,
-0x0e,
-0xc0,
-0x9b,
-0x56,
-0xe8,
-0x75,
-0xe0,
-0x0f,
-0x38,
-0x00,
-0xcf,
-0xcc,
-0xa0,
-0xd7,
-0x83,
-0x3f,
-0xff,
-0x7b,
-0xfc,
-0xbf,
-0x00,
-0x3f,
-0x0f,
-0xff,
-0x35,
-0x00,
-0x80,
-0xd0,
-0x18,
-0x07,
-0x60,
-0x19,
-0x07,
-0xf4,
-0x7a,
-0xf0,
-0xa6,
-0x1c,
-0x00,
-0x38,
-0x1f,
-0xc0,
-0xe7,
-0xa0,
-0xff,
-0xff,
-0x51,
-0x9e,
-0x7f,
-0x80,
-0x9f,
-0x87,
-0x80,
-0x0a,
-0x00,
-0x60,
-0xd3,
-0xe0,
-0x4f,
-0x10,
-0xfc,
-0x32,
-0xd8,
-0x3a,
-0x49,
-0xff,
-0x7f,
-0xcb,
-0xf0,
-0x0f,
-0xf0,
-0xf3,
-0x8c,
-0xff,
-0xff,
-0x00,
-0xc3,
-0x31,
-0x17,
-0xfd,
-0x2c,
-0x47,
-0x0d,
-0x00,
-0xd0,
-0x32,
-0xf0,
-0x27,
-0x1d,
-0x7e,
-0x19,
-0x6c,
-0x60,
-0xf1,
-0xff,
-0x1f,
-0x7f,
-0x38,
-0xe6,
-0xa2,
-0x16,
-0x35,
-0xff,
-0xff,
-0xe7,
-0xe1,
-0x1f,
-0xe0,
-0x00,
-0xfe,
-0xbf,
-0x07,
-0xbb,
-0x9c,
-0xf4,
-0xff,
-0x3f,
-0x0f,
-0xff,
-0x00,
-0x07,
-0xf8,
-0xdf,
-0x8d,
-0x0b,
-0x3e,
-0x78,
-0x73,
-0x3f,
-0x8b,
-0xff,
-0xff,
-0x70,
-0xe5,
-0xf0,
-0x0b,
-0x03,
-0x00,
-0x0f,
-0x50,
-0xff,
-0x52,
-0xfe,
-0xbb,
-0xaf,
-0xfa,
-0x87,
-0x7f,
-0xff,
-0x07,
-0xc0,
-0xff,
-0xa5,
-0x14,
-0x1f,
-0xbe,
-0xff,
-0x9f,
-0xc5,
-0xff,
-0xc4,
-0xaa,
-0x72,
-0xf8,
-0xef,
-0x01,
-0x80,
-0xff,
-0xeb,
-0xff,
-0x00,
-0x43,
-0x37,
-0x96,
-0xfd,
-0xc3,
-0xf6,
-0xff,
-0xab,
-0x80,
-0xff,
-0x00,
-0x3f,
-0x0f,
-0xff,
-0xff,
-0x8f,
-0xe2,
-0xfc,
-0x02,
-0x54,
-0x39,
-0xda,
-0xd5,
-0x00,
-0x80,
-0xff,
-0x68,
-0x3c,
-0xe0,
-0xc1,
-0x9b,
-0xca,
-0xfe,
-0xe4,
-0xff,
-0xff,
-0x09,
-0x87,
-0x5f,
-0x06,
-0x5b,
-0xfe,
-0x0f,
-0xc4,
-0x03,
-0x1e,
-0xfa,
-0xa9,
-0x7c,
-0xe0,
-0xff,
-0x7b,
-0x00,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x01,
-0xfc,
-0x07,
-0xfe,
-0xfe,
-0x0d,
-0xff,
-0x00,
-0x00,
-0xf0,
-0xff,
-0x3d,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0xff,
-0x00,
-0xfe,
-0x03,
-0x00,
-0xff,
-0x86,
-0x7f,
-0x1e,
-0x00,
-0xf8,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0x81,
-0x7f,
-0x00,
-0xff,
-0x3f,
-0x80,
-0x7f,
-0xc3,
-0x7f,
-0x0f,
-0x00,
-0xfc,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x1f,
-0xc0,
-0xbf,
-0xfe,
-0xbf,
-0x07,
-0x00,
-0xfc,
-0x07,
-0xfe,
-0x01,
-0x0d,
-0xff,
-0x00,
-0xfe,
-0xf0,
-0x1f,
-0xf8,
-0x07,
-0x37,
-0xfc,
-0x03,
-0xf8,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0xdf,
-0x03,
-0x00,
-0xfe,
-0x03,
-0xff,
-0xff,
-0x86,
-0x7f,
-0x00,
-0x03,
-0xf8,
-0x0f,
-0xfc,
-0xfc,
-0x1b,
-0xfe,
-0x01,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x01,
-0x80,
-0xff,
-0xef,
-0x7f,
-0xbf,
-0xff,
-0x81,
-0xdf,
-0x95,
-0xc1,
-0xaf,
-0xff,
-0x91,
-0xfc,
-0x2f,
-0x48,
-0x57,
-0x06,
-0xbf,
-0xff,
-0x4f,
-0xb0,
-0xff,
-0x32,
-0xd8,
-0x3a,
-0xfc,
-0xd7,
-0x00,
-0x40,
-0x95,
-0x81,
-0xff,
-0x94,
-0x01,
-0x1f,
-0xe0,
-0xe7,
-0xe1,
-0xff,
-0xff,
-0x53,
-0xce,
-0x7f,
-0xa9,
-0xeb,
-0x83,
-0xff,
-0xef,
-0x4b,
-0xfd,
-0xfc,
-0xbd,
-0xbd,
-0x0e,
-0xff,
-0x7b,
-0x00,
-0xe0,
-0x9c,
-0x56,
-0x0e,
-0x00,
-0xd0,
-0x0f,
-0xe0,
-0x73,
-0xff,
-0x81,
-0x7f,
-0x00,
-0xc3,
-0x3f,
-0x80,
-0x7f,
-0xfc,
-0x07,
-0xfe,
-0x01,
-0x0d,
-0xff,
-0x00,
-0xfe,
-0xe0,
-0xfd,
-0x35,
-0x00,
-0xe0,
-0x0d,
-0x2b,
-0x07,
-0x3a,
-0xf0,
-0x07,
-0xf4,
-0x96,
-0xff,
-0xed,
-0x3f,
-0xff,
-0xe1,
-0x1f,
-0xab,
-0x5b,
-0x02,
-0x00,
-0xfe,
-0xfb,
-0x87,
-0x7f,
-0xac,
-0x00,
-0xa8,
-0xcd,
-0x1a,
-0x6f,
-0x72,
-0xc0,
-0xff,
-0xfc,
-0x3c,
-0xfc,
-0x03,
-0x1f,
-0xc0,
-0x7f,
-0xe0,
-0xe0,
-0xdf,
-0xf0,
-0x0f,
-0x7f,
-0x00,
-0xff,
-0x81,
-0x80,
-0x7f,
-0xc3,
-0x3f,
-0x0f,
-0x00,
-0xfc,
-0x7f,
-0xff,
-0x7f,
-0x79,
-0xfc,
-0x01,
-0x7e,
-0x1e,
-0xfe,
-0x2b,
-0x07,
-0xe0,
-0xfe,
-0x07,
-0xf0,
-0x39,
-0xe8,
-0xc0,
-0x3f,
-0x80,
-0xff,
-0x1f,
-0xc0,
-0xbf,
-0xe1,
-0xb9,
-0x06,
-0x00,
-0x78,
-0xf6,
-0xff,
-0xbf,
-0x80,
-0xff,
-0x00,
-0x3f,
-0x0f,
-0xff,
-0xff,
-0x8f,
-0xe2,
-0xfc,
-0x03,
-0xfc,
-0x3c,
-0x7f,
-0x34,
-0x1e,
-0xf0,
-0xd0,
-0xef,
-0xe5,
-0xf3,
-0xff,
-0xdf,
-0x03,
-0x00,
-0xee,
-0xa3,
-0x72,
-0x00,
-0x83,
-0x7e,
-0x00,
-0x9f,
-0xf8,
-0xfd,
-0xff,
-0x07,
-0x1f,
-0xbe,
-0xb1,
-0xec,
-0x65,
-0x97,
-0xff,
-0x1f,
-0x79,
-0xf8,
-0x07,
-0xf8,
-0x80,
-0xc4,
-0x97,
-0x01,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x01,
-0xfc,
-0x07,
-0xfe,
-0xfe,
-0x0d,
-0xff,
-0x00,
-0x07,
-0xf0,
-0x1f,
-0xf8,
-0xf8,
-0x37,
-0xfc,
-0x03,
-0x00,
-0xc0,
-0xff,
-0xf7,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0xff,
-0x00,
-0xfe,
-0x03,
-0x00,
-0xff,
-0x86,
-0x7f,
-0xfc,
-0x03,
-0xf8,
-0x0f,
-0x01,
-0xfc,
-0x1b,
-0xfe,
-0x7b,
-0x00,
-0xe0,
-0xff,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0x81,
-0x7f,
-0x00,
-0xff,
-0x3f,
-0x80,
-0x7f,
-0xc3,
-0x07,
-0xfe,
-0x01,
-0xfc,
-0xff,
-0x00,
-0xfe,
-0x0d,
-0xff,
-0x3d,
-0x00,
-0xf0,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x1f,
-0xc0,
-0xbf,
-0xfe,
-0x03,
-0xff,
-0x00,
-0x86,
-0x7f,
-0x00,
-0xff,
-0xf8,
-0xff,
-0x1e,
-0x00,
-0xf0,
-0x1f,
-0xf8,
-0x07,
-0x37,
-0xfc,
-0x03,
-0xf8,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x00,
-0xfc,
-0x7f,
-0x0f,
-0x03,
-0xf8,
-0x0f,
-0xfc,
-0xfc,
-0x1b,
-0xfe,
-0x01,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0x07,
-0x00,
-0xfe,
-0xbf,
-0xfe,
-0x01,
-0xfc,
-0x07,
-0x00,
-0xfe,
-0x0d,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0xdf,
-0x03,
-0x00,
-0xff,
-0x03,
-0xff,
-0x00,
-0xfe,
-0x7f,
-0x00,
-0xff,
-0x86,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xef,
-0x01,
-0x80
-};
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevE/F10RevEHtPhyTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevE/F10RevEHtPhyTables.c
deleted file mode 100644
index 3ec04e0..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevE/F10RevEHtPhyTables.c
+++ /dev/null
@@ -1,374 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Rev E HT PCI tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVE_F10REVEHTPHYTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-// HT Phy T a b l e s
-// -------------------------
-STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RevEHtPhyRegisters[] =
-{
-// 0x60:0x68
- {
- HtPhyRangeRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- HTPHY_LINKTYPE_SL0_ALL, //
- 0x60, 0x68, // Address range
- 0x00000040, // regData
- 0x00000040, // regMask
- }
- },
-// 0x70:0x78
- {
- HtPhyRangeRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- HTPHY_LINKTYPE_SL1_ALL, //
- 0x70, 0x78, // Address range
- 0x00000040, // regData
- 0x00000040, // regMask
- }
- },
-// 0xC0
- {
- HtPhyRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- HTPHY_LINKTYPE_SL0_ALL, //
- 0xC0, // Address
- 0x40040000, // regData
- 0xe01F0000, // regMask
- }
- },
-// 0xD0
- {
- HtPhyRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- HTPHY_LINKTYPE_SL1_ALL, //
- 0xD0, // Address
- 0x40040000, // regData
- 0xe01F0000, // regMask
- }
- },
-// 0x520A
- {
- HtPhyRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- HTPHY_LINKTYPE_SL0_ALL, //
- 0x520A, // Address
- 0x00004000, // regData
- 0x00006000, // regMask
- }
- },
-// 0x530A
- {
- HtPhyRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- HTPHY_LINKTYPE_SL1_ALL, //
- 0x530A, // Address
- 0x00004000, // regData
- 0x00006000, // regMask
- }
- },
-
-
-//
-// Deemphasis Settings
-//
-
-// For C3, also set [7]TxLs23ClkGateEn.
-//deemphasis level DL1[20:16], DL2[12:8], DP1[4:0] PostCur1En[31] PostCur2En[30] PreCur1En[29] MapPostCur2En[6]
-// No deemphasis 00h 00h 00h 0 0 0 0
-// -3dB postcursor 12h 00h 00h 1 0 0 0
-// -6dB postcursor 1Fh 00h 00h 1 0 0 0
-// -8dB postcursor 1Fh 06h 00h 1 1 0 1
-// -11dB postcursor 1Fh 0Dh 00h 1 1 0 1
-// -11dB postcursor with
-// -8dB precursor 1Fh 06h 07h 1 1 1 1
-
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL_NONE,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0x00000080, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL_NONE,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0x00000080, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__3,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0x80120080, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__3,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0x80120080, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__6,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0x801F0080, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__6,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0x801F0080, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__8,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0xC01F06C0, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__8,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0xC01F06C0, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__11,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0xC01F0DC0, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__11,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0xC01F0DC0, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__11_8,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0xE01F06C7, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__11_8,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0xE01F06C7, // regData
- 0xE01F1FDF, // regMask
- }
- },
-};
-
-CONST REGISTER_TABLE ROMDATA F10RevEHtPhyRegisterTable = {
- PrimaryCores,
- (sizeof (F10RevEHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
- F10RevEHtPhyRegisters
-};
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevE/F10RevEMsrTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevE/F10RevEMsrTables.c
deleted file mode 100644
index cdfe9ad..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevE/F10RevEMsrTables.c
+++ /dev/null
@@ -1,135 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Rev E, MSR tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVE_F10REVEMSRTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10RevEMsrRegisters[] =
-{
-// M S R T a b l e s
-// ----------------------
-// MSR_LS_CFG (0xC0011020)
-// bit[1] = 0
- {
- MsrRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MSR_LS_CFG, // MSR Address
- 0x0000000000000000, // OR Mask
- (1 << 1), // NAND Mask
- }
- },
-
-// MSR_BU_CFG (0xC0011023)
-// bit[21] = 1
- {
- MsrRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MSR_BU_CFG, // MSR Address
- (1 << 21), // OR Mask
- (1 << 21), // NAND Mask
- }
- },
-
-// MSR_BU_CFG2 (0xC001102A)
-// bit[50] = 1
-// For GH rev C1 and later [RdMmExtCfgQwEn]=1
- {
- MsrRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MSR_BU_CFG2, // MSR Address
- 0x0004000000000000, // OR Mask
- 0x0004000000000000, // NAND Mask
- }
- },
-};
-
-CONST REGISTER_TABLE ROMDATA F10RevEMsrRegisterTable = {
- AllCores,
- (sizeof (F10RevEMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
- (TABLE_ENTRY_FIELDS *) &F10RevEMsrRegisters,
-};
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevE/F10RevEPciTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevE/F10RevEPciTables.c
deleted file mode 100644
index 333c830..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevE/F10RevEPciTables.c
+++ /dev/null
@@ -1,227 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Rev E PCI tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x10/RevE
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "F10PackageType.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVE_F10REVEPCITABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-// P C I T a b l e s
-// ----------------------
-
-STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RevEPciRegisters[] =
-{
-// F0x68 -
-// BufRelPri for rev E
-// bits[14:13] BufRelPri = 1
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO(0, 0, 24, FUNC_0, 0x68), // Address
- 0x00002000, // regData
- 0x00006000, // regMask
- }
- },
-
-// F0x16C - Link Global Extended Control Register
-// bit[7:6] InLnSt = 0x01
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- AMD_PF_SINGLE_LINK, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
- 0x0000C026, // regData
- 0x0000E03F, // regMask
- }
- },
-// F0x16C - Link Global Extended Control Register
-// bit[15:13] ForceFullT0 = 6
-// bit[9] RXCalEn = 1
-// bit[5:0] T0Time = 0x26
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- AMD_PF_SINGLE_LINK, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
- 0x0000C226, // regData
- 0x0000E23F, // regMask
- }
- },
-// F3x80 - ACPI Power State Control
-// ACPI State C2
-// bits[0] CpuPrbEn = 1
-// bits[1] NbLowPwrEn = 0
-// bits[2] NbGateEn = 0
-// bits[3] NbCofChg = 0
-// bits[4] AltVidEn = 0
-// bits[7:5] ClkDivisor = 1
-// ACPI State C3, C1E or Link init
-// bits[0] CpuPrbEn = 0
-// bits[1] NbLowPwrEn = 1
-// bits[2] NbGateEn = 1
-// bits[3] NbCofChg = 0
-// bits[4] AltVidEn = 0
-// bits[7:5] ClkDivisor = 7
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address
- 0x0000E681, // regData
- 0x0000FFFF, // regMask
- }
- },
-// F3xDC - Clock Power Timing Control 2
-// bits[14:12] NbsynPtrAdj = 6
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC), // Address
- 0x00006000, // regData
- 0x00007000, // regMask
- }
- },
-// F3x1C4 - L3 Power Control Register
-// bits[8] L3PwrSavEn = 1
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1C4), // Address
- 0x00000100, // regData
- 0x00000100, // regMask
- }
- },
-// F3x188 - NB Extended Configuration Low Register
-// bit[4] = EnStpGntOnFlushMaskWakeup
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address
- 0x00000010, // regData
- 0x00000010, // regMask
- }
- },
-// F4x15C - Core Performance Boost Control
-// bits[1:0] BoostSrc = 0
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_4, 0x15C), // Address
- 0x00000000, // regData
- 0x00000003, // regMask
- }
- },
-};
-
-CONST REGISTER_TABLE ROMDATA F10RevEPciRegisterTable = {
- PrimaryCores,
- (sizeof (F10RevEPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
- F10RevEPciRegisters,
-};
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c
deleted file mode 100644
index 635c424..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c
+++ /dev/null
@@ -1,370 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 revision Ex specific utility functions.
- *
- * Provides numerous utility functions specific to family 10h rev E.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuF10PowerMgmt.h"
-#include "GeneralServices.h"
-#include "cpuEarlyInit.h"
-#include "cpuRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVE_F10REVEUTILITIES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Set down core register on a revision E processor.
- *
- * This function set F3x190 Downcore Control Register[5:0]
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] Socket Socket ID.
- * @param[in] Module Module ID in socket.
- * @param[in] LeveledCores Number of core.
- * @param[in] CoreLevelMode Core level mode.
- * @param[in] StdHeader Header for library and services.
- *
- * @retval TRUE Down Core register is updated.
- * @retval FALSE Down Core register is not updated.
- */
-BOOLEAN
-F10CommonRevESetDownCoreRegister (
- IN CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices,
- IN UINT32 *Socket,
- IN UINT32 *Module,
- IN UINT32 *LeveledCores,
- IN CORE_LEVELING_TYPE CoreLevelMode,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 TempVar32_a;
- UINT32 CoreDisableBits;
- PCI_ADDR PciAddress;
- BOOLEAN IsUpdated;
- AGESA_STATUS AgesaStatus;
-
- IsUpdated = FALSE;
-
- switch (*LeveledCores) {
- case 1:
- CoreDisableBits = DOWNCORE_MASK_SINGLE;
- break;
- case 2:
- CoreDisableBits = DOWNCORE_MASK_DUAL;
- break;
- case 3:
- CoreDisableBits = DOWNCORE_MASK_TRI;
- break;
- case 4:
- CoreDisableBits = DOWNCORE_MASK_FOUR;
- break;
- case 5:
- CoreDisableBits = DOWNCORE_MASK_FIVE;
- break;
- default:
- CoreDisableBits = 0;
- break;
- }
-
- if (CoreDisableBits != 0) {
- if (GetPciAddress (StdHeader, (UINT8) *Socket, (UINT8) *Module, &PciAddress, &AgesaStatus)) {
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = NORTH_BRIDGE_CAPABILITIES_REG;
-
- LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
- TempVar32_a = ((TempVar32_a >> 12) & 0x3) | ((TempVar32_a >> 13) & 0x4);
- if (TempVar32_a == 0) {
- CoreDisableBits &= 0x1;
- } else if (TempVar32_a == 1) {
- CoreDisableBits &= 0x3;
- } else if (TempVar32_a == 2) {
- CoreDisableBits &= 0x7;
- } else if (TempVar32_a == 3) {
- CoreDisableBits &= 0x0F;
- } else if (TempVar32_a == 4) {
- CoreDisableBits &= 0x1F;
- } else if (TempVar32_a == 5) {
- CoreDisableBits &= 0x3F;
- }
- PciAddress.Address.Register = DOWNCORE_CTRL;
- LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
- if ((TempVar32_a | CoreDisableBits) != TempVar32_a) {
- TempVar32_a |= CoreDisableBits;
- LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
- IsUpdated = TRUE;
- }
- }
- }
-
- return IsUpdated;
-}
-
-
-CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevECoreLeveling =
-{
- 0,
- F10CommonRevESetDownCoreRegister
-};
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Get CPU pstate current on a revision E processor.
- *
- * @CpuServiceMethod{::F_CPU_GET_IDD_MAX}.
- *
- * This function returns the ProcIddMax.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] Pstate The P-state to check.
- * @param[out] ProcIddMax P-state current in mA.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @retval TRUE P-state is enabled
- * @retval FALSE P-state is disabled
- */
-BOOLEAN
-F10CommonRevEGetProcIddMax (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN UINT8 Pstate,
- OUT UINT32 *ProcIddMax,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 IddDiv;
- UINT32 CmpCap;
- UINT32 PciRegister;
- UINT32 Socket;
- UINT32 Module;
- UINT32 Ignored;
- UINT32 MsrAddress;
- UINT32 MultiNodeCpu;
- UINT64 PstateMsr;
- BOOLEAN IsPstateEnabled;
- PCI_ADDR PciAddress;
- AGESA_STATUS IgnoredSts;
-
- IsPstateEnabled = FALSE;
-
- MsrAddress = (UINT32) (Pstate + PS_REG_BASE);
- ASSERT (MsrAddress <= PS_MAX_REG);
-
- LibAmdMsrRead (MsrAddress, &PstateMsr, StdHeader);
- if (((PSTATE_MSR *) &PstateMsr)->PsEnable == 1) {
- IdentifyCore (StdHeader, &Socket, &Module, &Ignored, &IgnoredSts);
- GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
-
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = NB_CAPS_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // F3xE8
-
- switch (((PSTATE_MSR *) &PstateMsr)->IddDiv) {
- case 0:
- IddDiv = 1000;
- break;
- case 1:
- IddDiv = 100;
- break;
- case 2:
- IddDiv = 10;
- break;
- default: // IddDiv = 3 is reserved. Use 10
- ASSERT (FALSE);
- IddDiv = 10;
- break;
- }
- MultiNodeCpu = (UINT32) (((NB_CAPS_REGISTER *) &PciRegister)->MultiNodeCpu + 1);
- CmpCap = (UINT32) (((NB_CAPS_REGISTER *) &PciRegister)->CmpCapHi << 2);
- CmpCap |= (UINT32) (((NB_CAPS_REGISTER *) &PciRegister)->CmpCapLo);
- CmpCap++;
- *ProcIddMax = (UINT32) ((PSTATE_MSR *) &PstateMsr)->IddValue * IddDiv * CmpCap * MultiNodeCpu;
- IsPstateEnabled = TRUE;
- }
- return IsPstateEnabled;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Determines the NB clock on the desired node.
- *
- * @CpuServiceMethod{::F_CPU_GET_NB_PSTATE_INFO}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] PlatformConfig Platform profile/build option config structure.
- * @param[in] PciAddress The segment, bus, and device numbers of the CPU in question.
- * @param[in] NbPstate The NB P-state number to check.
- * @param[out] FreqNumeratorInMHz The desired node's frequency numerator in megahertz.
- * @param[out] FreqDivisor The desired node's frequency divisor.
- * @param[out] VoltageInuV The desired node's voltage in microvolts.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @retval TRUE NbPstate is valid
- * @retval FALSE NbPstate is disabled or invalid
- */
-BOOLEAN
-F10CommonRevEGetNbPstateInfo (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN PCI_ADDR *PciAddress,
- IN UINT32 NbPstate,
- OUT UINT32 *FreqNumeratorInMHz,
- OUT UINT32 *FreqDivisor,
- OUT UINT32 *VoltageInuV,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 PciRegister;
- UINT64 MsrRegister;
- BOOLEAN PstateIsValid;
-
- PstateIsValid = FALSE;
- if (NbPstate == 0) {
- PciAddress->Address.Function = FUNC_3;
- PciAddress->Address.Register = CPTC0_REG;
- LibAmdPciRead (AccessWidth32, *PciAddress, &PciRegister, StdHeader);
- *FreqNumeratorInMHz = ((((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->NbFid + 4) * 200);
- *FreqDivisor = 1;
- LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
- *VoltageInuV = (1550000 - (12500 * ((UINT32) ((COFVID_STS_MSR *) &MsrRegister)->CurNbVid)));
- PstateIsValid = TRUE;
- }
- return PstateIsValid;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns whether or not BIOS is responsible for configuring the NB COFVID.
- *
- * @CpuServiceMethod{::F_CPU_IS_NBCOF_INIT_NEEDED}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] PciAddress The northbridge to query by pci base address.
- * @param[out] NbVidUpdateAll Do all NbVids need to be updated
- * @param[in] StdHeader Header for library and services
- *
- * @retval TRUE Perform northbridge frequency and voltage config.
- * @retval FALSE Do not configure them.
- */
-BOOLEAN
-F10CommonRevEGetNbCofVidUpdate (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN PCI_ADDR *PciAddress,
- OUT BOOLEAN *NbVidUpdateAll,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 ProductInfoRegister;
-
- PciAddress->Address.Register = PRCT_INFO_REG;
- PciAddress->Address.Function = FUNC_3;
- LibAmdPciRead (AccessWidth32, *PciAddress, &ProductInfoRegister, StdHeader);
- *NbVidUpdateAll = (BOOLEAN) (((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbVidUpdateAll == 1);
- return (BOOLEAN) (((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbCofVidUpdate == 1);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Get number of processor cores to be used in determining the brand string.
- *
- * @CpuServiceMethod{::F_CPU_NUMBER_OF_BRANDSTRING_CORES}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @return The number of cores to be used in brand string calculation.
- */
-UINT8
-F10CommonRevEGetNumberOfCoresForBrandstring (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 CmpCap;
- UINT32 Socket;
- UINT32 Module;
- UINT32 Core;
- UINT32 PciRegister;
- PCI_ADDR PciAddress;
- AGESA_STATUS IgnoredSts;
-
- IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
- GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = NB_CAPS_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- CmpCap = (UINT8) (((NB_CAPS_REGISTER *) &PciRegister)->CmpCapHi << 2);
- CmpCap |= (UINT8) (((NB_CAPS_REGISTER *) &PciRegister)->CmpCapLo);
-
- return (UINT8) (CmpCap + 1);
-}
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevE/PH/F10PhEquivalenceTable.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevE/PH/F10PhEquivalenceTable.c
deleted file mode 100644
index 5e2724c..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevE/PH/F10PhEquivalenceTable.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Pharaoh Hound Equivalence Table related data
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/Family/0x10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVE_PH_F10PHEQUIVALENCETABLE_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-STATIC CONST UINT16 ROMDATA CpuF10PhMicrocodeEquivalenceTable[] =
-{
- 0x10a0, 0x10a0
-};
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns the appropriate microcode patch equivalent ID table.
- *
- * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[out] PhEquivalenceTablePtr Points to the first entry in the table.
- * @param[out] NumberOfElements Number of valid entries in the table.
- * @param[in] StdHeader Header for library and services.
- *
- */
-VOID
-GetF10PhMicrocodeEquivalenceTable (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- OUT CONST VOID **PhEquivalenceTablePtr,
- OUT UINT8 *NumberOfElements,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- *NumberOfElements = ((sizeof (CpuF10PhMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
- *PhEquivalenceTablePtr = CpuF10PhMicrocodeEquivalenceTable;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevE/PH/F10PhHtPhyTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevE/PH/F10PhHtPhyTables.c
deleted file mode 100644
index 131a10b..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevE/PH/F10PhHtPhyTables.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Pharaoh Hound Ht Phy tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVE_PH_F10PHHTPHYTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-// HT Phy T a b l e s
-// -------------------------
-STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10PhHtPhyRegisters[] =
-{
-// 0x520A
- {
- HtPhyRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_PH_E0 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- HTPHY_LINKTYPE_SL0_ALL, //
- 0x520A, // Address
- 0x00004000, // regData
- 0x00006000, // regMask
- }
- },
-// 0x530A
- {
- HtPhyRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_PH_E0 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- HTPHY_LINKTYPE_SL1_ALL, //
- 0x530A, // Address
- 0x00004000, // regData
- 0x00006000, // regMask
- }
- },
-};
-
-CONST REGISTER_TABLE ROMDATA F10PhHtPhyRegisterTable = {
- PrimaryCores,
- (sizeof (F10PhHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
- F10PhHtPhyRegisters,
-};
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevE/PH/F10PhLogicalIdTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevE/PH/F10PhLogicalIdTables.c
deleted file mode 100644
index fdc83ac..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevE/PH/F10PhLogicalIdTables.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Pharaoh Hound Logical ID Table
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVE_PH_F10PHLOGICALIDTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF10PhLogicalIdAndRevArray[] =
-{
- {
- 0x10a0,
- AMD_F10_PH_E0
- },
-};
-
-VOID
-GetF10PhLogicalIdAndRev (
- OUT CONST CPU_LOGICAL_ID_XLAT **PhIdPtr,
- OUT UINT8 *NumberOfElements,
- OUT UINT64 *LogicalFamily,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- *NumberOfElements = (sizeof (CpuF10PhLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT));
- *PhIdPtr = CpuF10PhLogicalIdAndRevArray;
- *LogicalFamily = AMD_FAMILY_10_PH;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevE/PH/F10PhMicrocodePatchTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevE/PH/F10PhMicrocodePatchTables.c
deleted file mode 100644
index 2748cb8..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/RevE/PH/F10PhMicrocodePatchTables.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Pharaoh Hound PCI tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/Family/0x10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVE_PH_F10PHMICROCODEPATCHTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-extern CONST MICROCODE_PATCHES ROMDATA *CpuF10PhMicroCodePatchArray[];
-extern CONST UINT8 ROMDATA CpuF10PhNumberOfMicrocodePatches;
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns a table containing the appropriate microcode patches.
- *
- * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[out] PhUcodePtr Points to the first entry in the table.
- * @param[out] NumberOfElements Number of valid entries in the table.
- * @param[in] StdHeader Header for library and services.
- *
- */
-VOID
-GetF10PhMicroCodePatchesStruct (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- OUT CONST VOID **PhUcodePtr,
- OUT UINT8 *NumberOfElements,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- *NumberOfElements = CpuF10PhNumberOfMicrocodePatches;
- *PhUcodePtr = &CpuF10PhMicroCodePatchArray[0];
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuCommonF10Utilities.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuCommonF10Utilities.c
deleted file mode 100644
index 90a91a6..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuCommonF10Utilities.c
+++ /dev/null
@@ -1,330 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 specific utility functions.
- *
- * Provides numerous utility functions specific to family 10h.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuServices.h"
-#include "GeneralServices.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuCommonF10Utilities.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_CPUCOMMONF10UTILITIES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-/**
- * Node ID MSR register fields.
- * Provide the layout of fields in the Node ID MSR.
- */
-typedef struct {
- UINT64 NodeId:3; ///< The core is on the node with this node id.
- UINT64 NodesPerProcessor:3; ///< The number of Nodes in this processor.
- UINT64 HeapIndex:6; ///< The AP core heap index.
- UINT64 :(63 - 11); ///< Reserved.
-} NODE_ID_MSR_FIELDS;
-
-/// Node ID MSR.
-typedef union {
- NODE_ID_MSR_FIELDS Fields; ///< Access the register as individual fields
- UINT64 Value; ///< Access the register value.
-} NODE_ID_MSR;
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Set warm reset status and count
- *
- * @CpuServiceMethod{::F_CPU_SET_WARM_RESET_FLAG}.
- *
- * This function will use bit9, and bit 10 of register F0x6C as a warm reset status and count.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- * @param[in] Request Indicate warm reset status
- *
- */
-VOID
-F10SetAgesaWarmResetFlag (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN WARM_RESET_REQUEST *Request
- )
-{
- PCI_ADDR PciAddress;
- UINT32 PciData;
-
- PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_0, HT_INIT_CTRL);
- LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
-
- // bit[5] - indicate a warm reset is or is not required
- PciData &= ~(HT_INIT_BIOS_RST_DET_0);
- PciData = PciData | (Request->RequestBit << 5);
-
- // bit[10,9] - indicate warm reset status and count
- PciData &= ~(HT_INIT_BIOS_RST_DET_1 | HT_INIT_BIOS_RST_DET_2);
- PciData |= Request->StateBits << 9;
-
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Get warm reset status and count
- *
- * @CpuServiceMethod{::F_CPU_GET_WARM_RESET_FLAG}.
- *
- * This function will bit9, and bit 10 of register F0x6C as a warm reset status and count.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] StdHeader Config handle for library and services
- * @param[out] Request Indicate warm reset status
- *
- */
-VOID
-F10GetAgesaWarmResetFlag (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CONFIG_PARAMS *StdHeader,
- OUT WARM_RESET_REQUEST *Request
- )
-{
- PCI_ADDR PciAddress;
- UINT32 PciData;
-
- PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_0, HT_INIT_CTRL);
- LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
-
- // bit[5] - indicate a warm reset is or is not required
- Request->RequestBit = (UINT8) ((PciData & HT_INIT_BIOS_RST_DET_0) >> 5);
- // bit[10,9] - indicate warm reset status and count
- Request->StateBits = (UINT8) ((PciData & (HT_INIT_BIOS_RST_DET_1 | HT_INIT_BIOS_RST_DET_2)) >> 9);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Use the Mailbox Register to get the Ap Mailbox info for the current core.
- *
- * @CpuServiceMethod{::F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE}.
- *
- * Access the mailbox register used with this NB family. This is valid until the
- * point that some init code initializes the mailbox register for its normal use.
- * The Machine Check Misc (Thresholding) register is available as both a PCI config
- * register and a MSR, so it can be used as a mailbox from HT to other functions.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[out] ApMailboxInfo The AP Mailbox info
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- */
-VOID
-F10GetApMailboxFromHardware (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- OUT AP_MAILBOXES *ApMailboxInfo,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 MailboxInfo;
-
- LibAmdMsrRead (MSR_MC_MISC_LINK_THRESHOLD, &MailboxInfo, StdHeader);
- // Mailbox info is in bits 32 thru 43, 12 bits.
- ApMailboxInfo->ApMailInfo.Info = (((UINT32) (MailboxInfo >> 32)) & (UINT32)0x00000FFF);
- LibAmdMsrRead (MSR_MC_MISC_L3_THRESHOLD, &MailboxInfo, StdHeader);
- // Mailbox info is in bits 32 thru 43, 12 bits.
- ApMailboxInfo->ApMailExtInfo.Info = (((UINT32) (MailboxInfo >> 32)) & (UINT32)0x00000FFF);
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Set the system AP core number in the AP's Mailbox.
- *
- * @CpuServiceMethod{::F_CPU_SET_AP_CORE_NUMBER}.
- *
- * Access the mailbox register used with this NB family. This is only intended to
- * run on the BSC at the time of initial AP launch.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] Socket The AP's socket
- * @param[in] Module The AP's module
- * @param[in] ApCoreNumber The AP's unique core number
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- */
-VOID
-F10SetApCoreNumber (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN UINT32 Socket,
- IN UINT32 Module,
- IN UINT32 ApCoreNumber,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 PciRegister;
- PCI_ADDR PciAddress;
- AGESA_STATUS IgnoredStatus;
-
- GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus);
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = 0x170;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- ((AP_MAIL_EXT_INFO *) &PciRegister)->Fields.HeapIndex = ApCoreNumber;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Get this AP's system core number from hardware.
- *
- * @CpuServiceMethod{::F_CPU_GET_AP_CORE_NUMBER}.
- *
- * Returns the system core number from the scratch MSR, where
- * it was saved at heap initialization.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @return The AP's unique core number
- */
-UINT32
-F10GetApCoreNumber (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- NODE_ID_MSR NodeIdMsr;
-
- LibAmdMsrRead (0xC001100C, &NodeIdMsr.Value, StdHeader);
- return (UINT32) NodeIdMsr.Fields.HeapIndex;
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Move the AP's core number from the mailbox to hardware.
- *
- * @CpuServiceMethod{::F_CPU_TRANSFER_AP_CORE_NUMBER}.
- *
- * Transfers this AP's system core number from the mailbox to
- * the NodeId MSR and initializes the other NodeId fields.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- */
-VOID
-F10TransferApCoreNumber (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AP_MAILBOXES Mailboxes;
- NODE_ID_MSR NodeIdMsr;
- UINT64 ExtFeatures;
-
- NodeIdMsr.Value = 0;
- FamilySpecificServices->GetApMailboxFromHardware (FamilySpecificServices, &Mailboxes, StdHeader);
- NodeIdMsr.Fields.HeapIndex = Mailboxes.ApMailExtInfo.Fields.HeapIndex;
- NodeIdMsr.Fields.NodeId = Mailboxes.ApMailInfo.Fields.Node;
- NodeIdMsr.Fields.NodesPerProcessor = Mailboxes.ApMailInfo.Fields.ModuleType;
- LibAmdMsrWrite (0xC001100C, &NodeIdMsr.Value, StdHeader);
-
- // Indicate that the NodeId MSR is supported.
- LibAmdMsrRead (MSR_CPUID_EXT_FEATS, &ExtFeatures, StdHeader);
- ExtFeatures = (ExtFeatures | BIT51);
- LibAmdMsrWrite (MSR_CPUID_EXT_FEATS, &ExtFeatures, StdHeader);
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Return a number zero or one, based on the Core ID position in the initial APIC Id.
- *
- * @CpuServiceMethod{::F_CORE_ID_POSITION_IN_INITIAL_APIC_ID}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @retval CoreIdPositionZero Core Id is not low
- * @retval CoreIdPositionOne Core Id is low
- */
-CORE_ID_POSITION
-F10CpuAmdCoreIdPositionInInitialApicId (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 InitApicIdCpuIdLo;
-
- // Check bit_54 [InitApicIdCpuIdLo] to find core id position.
- LibAmdMsrRead (MSR_NB_CFG, &InitApicIdCpuIdLo, StdHeader);
- InitApicIdCpuIdLo = ((InitApicIdCpuIdLo & BIT54) >> 54);
- return ((InitApicIdCpuIdLo == 0) ? CoreIdPositionZero : CoreIdPositionOne);
-}
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuCommonF10Utilities.h b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuCommonF10Utilities.h
deleted file mode 100644
index b5ee53f..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuCommonF10Utilities.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 specific utility functions.
- *
- * Provides numerous utility functions specific to family 10h.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: IDS
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPU_COMMON_F10_UTILITES_H_
-#define _CPU_COMMON_F10_UTILITES_H_
-
-
-/*---------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *---------------------------------------------------------------------------------------
- */
-VOID
-F10GetApMailboxFromHardware (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- OUT AP_MAILBOXES *ApMailboxInfo,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-CORE_ID_POSITION
-F10CpuAmdCoreIdPositionInInitialApicId (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-F10SetAgesaWarmResetFlag (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN WARM_RESET_REQUEST *Request
- );
-
-VOID
-F10GetAgesaWarmResetFlag (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CONFIG_PARAMS *StdHeader,
- OUT WARM_RESET_REQUEST *Request
- );
-
-#endif // _CPU_COMMON_F10_UTILITES_H_
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10BrandId.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10BrandId.c
deleted file mode 100644
index 49ecc9b..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10BrandId.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU BrandId related functions and structures.
- *
- * Contains code that provides CPU BrandId information
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10BRANDID_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-extern CPU_BRAND_TABLE *F10BrandIdString1Tables[];
-extern CPU_BRAND_TABLE *F10BrandIdString2Tables[];
-extern CONST UINT8 F10BrandIdString1TableCount;
-extern CONST UINT8 F10BrandIdString2TableCount;
-
-/*---------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns a table containing the appropriate beginnings of the CPU brandstring.
- *
- * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[out] BrandString1Ptr Points to the first entry in the table.
- * @param[out] NumberOfElements Number of valid entries in the table.
- * @param[in] StdHeader Header for library and services.
- *
- */
-VOID
-GetF10BrandIdString1 (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- OUT CONST VOID **BrandString1Ptr,
- OUT UINT8 *NumberOfElements,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- CPU_BRAND_TABLE **TableEntryPtr;
-
- TableEntryPtr = &F10BrandIdString1Tables[0];
- *BrandString1Ptr = TableEntryPtr;
- *NumberOfElements = F10BrandIdString1TableCount;
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns a table containing the appropriate endings of the CPU brandstring.
- *
- * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[out] BrandString2Ptr Points to the first entry in the table.
- * @param[out] NumberOfElements Number of valid entries in the table.
- * @param[in] StdHeader Header for library and services.
- *
- */
-VOID
-GetF10BrandIdString2 (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- OUT CONST VOID **BrandString2Ptr,
- OUT UINT8 *NumberOfElements,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- CPU_BRAND_TABLE **TableEntryPtr;
-
- TableEntryPtr = &F10BrandIdString2Tables[0];
- *BrandString2Ptr = TableEntryPtr;
- *NumberOfElements = F10BrandIdString2TableCount;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c
deleted file mode 100644
index 25d96f5..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c
+++ /dev/null
@@ -1,333 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU BrandId related functions and structures for socket Am3.
- *
- * Contains code that provides CPU BrandId information
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-// PRIVATE FORMAT FOR BRAND TABLE ... FOR AMD USE ONLY
-
-// String1
-/*CHAR8 strEngSample[] = "AMD Engineering Sample";
-CHAR8 strTtkSample[] = "AMD Thermal Test Kit";
-CHAR8 strUnknown[] = "AMD Processor model unknown";
-*/
-//AM3 NC 0
-CONST CHAR8 ROMDATA str_SC_AthlonLE[] = "AMD Athlon(tm) Processor LE-";
-CONST CHAR8 ROMDATA str_SC_SempronLE[] = "AMD Sempron(tm) Processor LE-";
-CONST CHAR8 ROMDATA str_SC_Sempron_1[] = "AMD Sempron(tm) 1";
-CONST CHAR8 ROMDATA str_SC_Athlon_1[] = "AMD Athlon(tm) II 1";
-
-//AM3 NC 1
-CONST CHAR8 ROMDATA str_Athlon[] = "AMD Athlon(tm) ";
-CONST CHAR8 ROMDATA str_Athlon_II_XL_V[] = "AMD Athlon(tm) II XL V";
-CONST CHAR8 ROMDATA str_Athlon_II_XLT_V[] = "AMD Athlon(tm) II XLT V";
-CONST CHAR8 ROMDATA str_Athlon_II_X2_4[] = "AMD Athlon(tm) II X2 4";
-CONST CHAR8 ROMDATA str_Athlon_II_X2_2[] = "AMD Athlon(tm) II X2 2";
-CONST CHAR8 ROMDATA str_Athlon_II_X2_B[] = "AMD Athlon(tm) II X2 B";
-CONST CHAR8 ROMDATA str_Athlon_II_X2[] = "AMD Athlon(tm) II X2 ";
-CONST CHAR8 ROMDATA str_Athlon_II_Neo_X2[] = "AMD Athlon(tm) II Neo X2 ";
-CONST CHAR8 ROMDATA str_Phenom_II_X2_5[] = "AMD Phenom(tm) II X2 5";
-CONST CHAR8 ROMDATA str_Athlon_II_X2_5[] = "AMD Athlon(tm) II X2 5";
-CONST CHAR8 ROMDATA str_Athlon_II_X2_3[] = "AMD Athlon(tm) II X2 3";
-CONST CHAR8 ROMDATA str_Phenom_II_X2[] = "AMD Phenom(tm) II X2 ";
-CONST CHAR8 ROMDATA str_Phenom_II_X2_B[] = "AMD Phenom(tm) II X2 B";
-CONST CHAR8 ROMDATA str_DC_Opteron13[] = "Dual-Core AMD Opteron(tm) Processor 13";
-
-//AM3 NC2
-CONST CHAR8 ROMDATA str_Phenom[] = "AMD Phenom(tm) ";
-CONST CHAR8 ROMDATA str_Phenom_II_X3_5[] = "AMD Phenom(tm) II X3 5";
-CONST CHAR8 ROMDATA str_Phenom_II_X3_4[] = "AMD Phenom(tm) II X3 4";
-CONST CHAR8 ROMDATA str_Phenom_II_X3_B[] = "AMD Phenom(tm) II X3 B";
-CONST CHAR8 ROMDATA str_Phenom_II_X3[] = "AMD Phenom(tm) II X3 ";
-CONST CHAR8 ROMDATA str_Athlon_II_X3_3[] = "AMD Athlon(tm) II X3 3";
-CONST CHAR8 ROMDATA str_Athlon_II_Neo_X3[] = "AMD Athlon(tm) II Neo X3 ";
-CONST CHAR8 ROMDATA str_Athlon_II_X3_4[] = "AMD Athlon(tm) II X3 4";
-CONST CHAR8 ROMDATA str_Phenom_II_X3_7[] = "AMD Phenom(tm) II X3 7";
-CONST CHAR8 ROMDATA str_Athlon_II_X3_B[] = "AMD Athlon(tm) II X3 B";
-CONST CHAR8 ROMDATA str_Athlon_II_X3[] = "AMD Athlon(tm) II X3 ";
-
-//AM3 NC 3
-CONST CHAR8 ROMDATA str_Phenom_FX[] = "AMD Phenom(tm) FX-";
-CONST CHAR8 ROMDATA str_Phenom_II_X4_9[] = "AMD Phenom(tm) II X4 9";
-CONST CHAR8 ROMDATA str_Phenom_II_X4_8[] = "AMD Phenom(tm) II X4 8";
-CONST CHAR8 ROMDATA str_Phenom_II_X4_7[] = "AMD Phenom(tm) II X4 7";
-CONST CHAR8 ROMDATA str_Phenom_II_X4_6[] = "AMD Phenom(tm) II X4 6";
-CONST CHAR8 ROMDATA str_Phenom_II_X4_B[] = "AMD Phenom(tm) II X4 B";
-CONST CHAR8 ROMDATA str_Phenom_II_X4[] = "AMD Phenom(tm) II X4 ";
-CONST CHAR8 ROMDATA str_Phenom_II_Neo_X4[] = "AMD Phenom(tm) II Neo X4 ";
-CONST CHAR8 ROMDATA str_Athlon_II_X4_6[] = "AMD Athlon(tm) II X4 6";
-CONST CHAR8 ROMDATA str_Athlon_II_X4_5[] = "AMD Athlon(tm) II X4 5";
-CONST CHAR8 ROMDATA str_Athlon_II_Neo_X4[] = "AMD Athlon(tm) II Neo X4 ";
-CONST CHAR8 ROMDATA str_Athlon_II_X4_B[] = "AMD Athlon(tm) II X4 B";
-CONST CHAR8 ROMDATA str_Phenom_II__FX[] = "AMD Phenom(tm) II FX-";
-CONST CHAR8 ROMDATA str_Athlon_II_X4[] = "AMD Athlon(tm) II X4 ";
-CONST CHAR8 ROMDATA str_Phenom_II[] = "AMD Phenom(tm) II ";
-CONST CHAR8 ROMDATA str_Phenom_II_XLT_Q[] = "AMD Phenom(tm) II XLT Q";
-CONST CHAR8 ROMDATA str_QC_Opteron13[] = "Quad-Core AMD Opteron(tm) Processor 13";
-
-//AM3 NC 5
-CONST CHAR8 ROMDATA str_Phenom_II_X6_1[] = "AMD Phenom(tm) II X6 1";
-
-// String2
-CONST CHAR8 ROMDATA str2_SE_AM3[] = " SE";
-CONST CHAR8 ROMDATA str2_HE_AM3[] = " HE";
-CONST CHAR8 ROMDATA str2_EE_AM3[] = " EE";
-
-CONST CHAR8 ROMDATA str2_QCP_AM3[] = " Quad-Core Processor";
-CONST CHAR8 ROMDATA str2_00[] = "00";
-CONST CHAR8 ROMDATA str2_10[] = "10";
-CONST CHAR8 ROMDATA str2_20[] = "20";
-CONST CHAR8 ROMDATA str2_30[] = "30";
-CONST CHAR8 ROMDATA str2_40[] = "40";
-CONST CHAR8 ROMDATA str2_50[] = "50";
-CONST CHAR8 ROMDATA str2_60[] = "60";
-CONST CHAR8 ROMDATA str2_70[] = "70";
-CONST CHAR8 ROMDATA str2_80[] = "80";
-CONST CHAR8 ROMDATA str2_90[] = "90";
-CONST CHAR8 ROMDATA str2_DC_00[] = "00 Dual-Core Processor";
-CONST CHAR8 ROMDATA str2_DC_00e[] = "00e Dual-Core Processor";
-CONST CHAR8 ROMDATA str2_DC_00B[] = "00B Dual-Core Processor";
-CONST CHAR8 ROMDATA str2_DC_50[] = "50 Dual-Core Processor";
-CONST CHAR8 ROMDATA str2_DC_50e[] = "50e Dual-Core Processor";
-CONST CHAR8 ROMDATA str2_DC_50B[] = "50B Dual-Core Processor";
-CONST CHAR8 ROMDATA str2_Processor[] = " Processor";
-CONST CHAR8 ROMDATA str2_e_Processor[] = "e Processor";
-CONST CHAR8 ROMDATA str2_B_Processor[] = "B Processor";
-CONST CHAR8 ROMDATA str2_0e_Processor[] = "0e Processor";
-CONST CHAR8 ROMDATA str2_u_Processor[] = "u Processor";
-CONST CHAR8 ROMDATA str2_0_Processor[] = "0 Processor";
-CONST CHAR8 ROMDATA str2_L_Processor[] = "L Processor";
-CONST CHAR8 ROMDATA str2_C_Processor[] = "C Processor";
-CONST CHAR8 ROMDATA str2_TWKR_Black_Edition[] = " TWKR Black Edition";
-
-CONST CHAR8 ROMDATA str2_TC_00[] = "00 Triple-Core Processor";
-CONST CHAR8 ROMDATA str2_TC_00e[] = "00e Triple-Core Processor";
-CONST CHAR8 ROMDATA str2_TC_00B[] = "00B Triple-Core Processor";
-CONST CHAR8 ROMDATA str2_TC_50[] = "50 Triple-Core Processor";
-CONST CHAR8 ROMDATA str2_TC_50e[] = "50e Triple-Core Processor";
-CONST CHAR8 ROMDATA str2_TC_50B[] = "50B Triple-Core Processor";
-CONST CHAR8 ROMDATA str2_QC_00[] = "00 Quad-Core Processor";
-CONST CHAR8 ROMDATA str2_QC_00e[] = "00e Quad-Core Processor";
-CONST CHAR8 ROMDATA str2_QC_00B[] = "00B Quad-Core Processor";
-CONST CHAR8 ROMDATA str2_QC_50[] = "50 Quad-Core Processor";
-CONST CHAR8 ROMDATA str2_QC_50e[] = "50e Quad-Core Processor";
-CONST CHAR8 ROMDATA str2_QC_50B[] = "50B Quad-Core Processor";
-CONST CHAR8 ROMDATA str2_QC_T[] = "T Processor";
-CONST CHAR8 ROMDATA str2_SC_0T[] = "0T Processor";
-CONST CHAR8 ROMDATA str2_SC_5T[] = "5T Processor";
-
-/*---------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *---------------------------------------------------------------------------------------
- */
-
-CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString1ArrayAm3[] =
-{
- // AM3
- {1, 0, 0, DR_SOCKET_AM3, str_SC_AthlonLE, sizeof (str_SC_AthlonLE)},
- {1, 0, 1, DR_SOCKET_AM3, str_SC_SempronLE, sizeof (str_SC_SempronLE)},
- {1, 0, 2, DR_SOCKET_AM3, str_SC_Sempron_1, sizeof (str_SC_Sempron_1)},
- {1, 0, 3, DR_SOCKET_AM3, str_SC_Athlon_1, sizeof (str_SC_Athlon_1)},
-
- {2, 0, 0, DR_SOCKET_AM3, str_DC_Opteron13, sizeof (str_DC_Opteron13)},
- {2, 0, 1, DR_SOCKET_AM3, str_Athlon, sizeof (str_Athlon)},
- {2, 0, 2, DR_SOCKET_AM3, str_Athlon_II_X2_4, sizeof (str_Athlon_II_X2_4)},
- {2, 0, 3, DR_SOCKET_AM3, str_Athlon_II_X2_2, sizeof (str_Athlon_II_X2_2)},
- {2, 0, 4, DR_SOCKET_AM3, str_Athlon_II_X2_B, sizeof (str_Athlon_II_X2_B)},
- {2, 0, 5, DR_SOCKET_AM3, str_Athlon_II_X2, sizeof (str_Athlon_II_X2)},
- {2, 0, 6, DR_SOCKET_AM3, str_Athlon_II_Neo_X2, sizeof (str_Athlon_II_Neo_X2)},
- {2, 0, 7, DR_SOCKET_AM3, str_Phenom_II_X2_5, sizeof (str_Phenom_II_X2_5)},
- {2, 0, 8, DR_SOCKET_AM3, str_Athlon_II_X2_5, sizeof (str_Athlon_II_X2_5)},
- {2, 0, 9, DR_SOCKET_AM3, str_Athlon_II_X2_3, sizeof (str_Athlon_II_X2_3)},
- {2, 0, 10, DR_SOCKET_AM3, str_Phenom_II_X2, sizeof (str_Phenom_II_X2)},
- {2, 0, 11, DR_SOCKET_AM3, str_Phenom_II_X2_B, sizeof (str_Phenom_II_X2_B)},
- {2, 1, 1, DR_SOCKET_AM3, str_Athlon_II_XLT_V, sizeof (str_Athlon_II_XLT_V)},
- {2, 1, 2, DR_SOCKET_AM3, str_Athlon_II_XL_V, sizeof (str_Athlon_II_XL_V)},
-
- {3, 0, 0, DR_SOCKET_AM3, str_Phenom, sizeof (str_Phenom)},
- {3, 0, 1, DR_SOCKET_AM3, str_Phenom_II_X3_5, sizeof (str_Phenom_II_X3_5)},
- {3, 0, 2, DR_SOCKET_AM3, str_Phenom_II_X3_4, sizeof (str_Phenom_II_X3_4)},
- {3, 0, 3, DR_SOCKET_AM3, str_Phenom_II_X3_B, sizeof (str_Phenom_II_X3_B)},
- {3, 0, 4, DR_SOCKET_AM3, str_Phenom_II_X3, sizeof (str_Phenom_II_X3)},
- {3, 0, 5, DR_SOCKET_AM3, str_Athlon_II_X3_3, sizeof (str_Athlon_II_X3_3)},
- {3, 0, 6, DR_SOCKET_AM3, str_Athlon_II_Neo_X3, sizeof (str_Athlon_II_Neo_X3)},
- {3, 0, 7, DR_SOCKET_AM3, str_Athlon_II_X3_4, sizeof (str_Athlon_II_X3_4)},
- {3, 0, 8, DR_SOCKET_AM3, str_Phenom_II_X3_7, sizeof (str_Phenom_II_X3_7)},
- {3, 0, 9, DR_SOCKET_AM3, str_Athlon_II_X3_B, sizeof (str_Athlon_II_X3_B)},
- {3, 0, 10, DR_SOCKET_AM3, str_Athlon_II_X3, sizeof (str_Athlon_II_X3)},
-
- {4, 0, 0, DR_SOCKET_AM3, str_QC_Opteron13, sizeof (str_QC_Opteron13)},
- {4, 0, 1, DR_SOCKET_AM3, str_Phenom_FX, sizeof (str_Phenom_FX)},
- {4, 0, 2, DR_SOCKET_AM3, str_Phenom, sizeof (str_Phenom)},
- {4, 0, 3, DR_SOCKET_AM3, str_Phenom_II_X4_9, sizeof (str_Phenom_II_X4_9)},
- {4, 0, 4, DR_SOCKET_AM3, str_Phenom_II_X4_8, sizeof (str_Phenom_II_X4_8)},
- {4, 0, 5, DR_SOCKET_AM3, str_Phenom_II_X4_7, sizeof (str_Phenom_II_X4_7)},
- {4, 0, 6, DR_SOCKET_AM3, str_Phenom_II_X4_6, sizeof (str_Phenom_II_X4_6)},
- {4, 0, 7, DR_SOCKET_AM3, str_Phenom_II_X4_B, sizeof (str_Phenom_II_X4_B)},
- {4, 0, 8, DR_SOCKET_AM3, str_Phenom_II_X4, sizeof (str_Phenom_II_X4)},
- {4, 0, 9, DR_SOCKET_AM3, str_Phenom_II_Neo_X4, sizeof (str_Phenom_II_Neo_X4)},
- {4, 0, 10, DR_SOCKET_AM3, str_Athlon_II_X4_6, sizeof (str_Athlon_II_X4_6)},
- {4, 0, 11, DR_SOCKET_AM3, str_Athlon_II_X4_5, sizeof (str_Athlon_II_X4_5)},
- {4, 0, 12, DR_SOCKET_AM3, str_Athlon_II_Neo_X4, sizeof (str_Athlon_II_Neo_X4)},
- {4, 0, 13, DR_SOCKET_AM3, str_Athlon_II_X4_B, sizeof (str_Athlon_II_X4_B)},
- {4, 0, 14, DR_SOCKET_AM3, str_Phenom_II__FX, sizeof (str_Phenom_II__FX)},
- {4, 0, 15, DR_SOCKET_AM3, str_Athlon_II_X4, sizeof (str_Athlon_II_X4)},
- {4, 1, 0, DR_SOCKET_AM3, str_Phenom_II, sizeof (str_Phenom_II)},
- {4, 1, 1, DR_SOCKET_AM3, str_Phenom_II_XLT_Q, sizeof (str_Phenom_II_XLT_Q)},
- {4, 1, 2, DR_SOCKET_AM3, str_Phenom_II_X4_9, sizeof (str_Phenom_II_X4_9)},
- {4, 1, 3, DR_SOCKET_AM3, str_Phenom_II_X4_8, sizeof (str_Phenom_II_X4_8)},
-
- {6, 0, 0, DR_SOCKET_AM3, str_Phenom_II_X6_1, sizeof (str_Phenom_II_X6_1)}
-}; //Cores, page, index, socket, stringstart, stringlength
-
-
-CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString2ArrayAm3[] =
-{
- // AM3
- {1, 0, 0x00, DR_SOCKET_AM3, str2_00, sizeof (str2_00)},
- {1, 0, 0x01, DR_SOCKET_AM3, str2_10, sizeof (str2_10)},
- {1, 0, 0x02, DR_SOCKET_AM3, str2_20, sizeof (str2_20)},
- {1, 0, 0x03, DR_SOCKET_AM3, str2_30, sizeof (str2_30)},
- {1, 0, 0x04, DR_SOCKET_AM3, str2_40, sizeof (str2_40)},
- {1, 0, 0x05, DR_SOCKET_AM3, str2_50, sizeof (str2_50)},
- {1, 0, 0x06, DR_SOCKET_AM3, str2_60, sizeof (str2_60)},
- {1, 0, 0x07, DR_SOCKET_AM3, str2_70, sizeof (str2_70)},
- {1, 0, 0x08, DR_SOCKET_AM3, str2_80, sizeof (str2_80)},
- {1, 0, 0x09, DR_SOCKET_AM3, str2_90, sizeof (str2_90)},
- {1, 0, 0x0A, DR_SOCKET_AM3, str2_Processor, sizeof (str2_Processor)},
- {1, 0, 0x0B, DR_SOCKET_AM3, str2_u_Processor, sizeof (str2_u_Processor)},
- {1, 0, 0x0F, DR_SOCKET_AM3, 0, 0}, //Size 0 for no suffix
- {2, 0, 0x00, DR_SOCKET_AM3, str2_DC_00, sizeof (str2_DC_00)},
- {2, 0, 0x01, DR_SOCKET_AM3, str2_DC_00e,sizeof (str2_DC_00e)},
- {2, 0, 0x02, DR_SOCKET_AM3, str2_DC_00B,sizeof (str2_DC_00B)},
- {2, 0, 0x03, DR_SOCKET_AM3, str2_DC_50, sizeof (str2_DC_50)},
- {2, 0, 0x04, DR_SOCKET_AM3, str2_DC_50e,sizeof (str2_DC_50e)},
- {2, 0, 0x05, DR_SOCKET_AM3, str2_DC_50B,sizeof (str2_DC_50B)},
- {2, 0, 0x06, DR_SOCKET_AM3, str2_Processor,sizeof (str2_Processor)},
- {2, 0, 0x07, DR_SOCKET_AM3, str2_e_Processor,sizeof (str2_e_Processor)},
- {2, 0, 0x08, DR_SOCKET_AM3, str2_B_Processor,sizeof (str2_B_Processor)},
- {2, 0, 0x09, DR_SOCKET_AM3, str2_0_Processor,sizeof (str2_0_Processor)},
- {2, 0, 0x0A, DR_SOCKET_AM3, str2_0e_Processor,sizeof (str2_0e_Processor)},
- {2, 0, 0x0B, DR_SOCKET_AM3, str2_u_Processor,sizeof (str2_u_Processor)},
- {2, 0, 0x0F, DR_SOCKET_AM3, 0, 0}, // Size 0 for no suffix
- {2, 1, 0x01, DR_SOCKET_AM3, str2_L_Processor, sizeof (str2_L_Processor)},
- {2, 1, 0x02, DR_SOCKET_AM3, str2_C_Processor, sizeof (str2_C_Processor)},
- {3, 0, 0x00, DR_SOCKET_AM3, str2_TC_00, sizeof (str2_TC_00)},
- {3, 0, 0x01, DR_SOCKET_AM3, str2_TC_00e,sizeof (str2_TC_00e)},
- {3, 0, 0x02, DR_SOCKET_AM3, str2_TC_00B,sizeof (str2_TC_00B)},
- {3, 0, 0x03, DR_SOCKET_AM3, str2_TC_50, sizeof (str2_TC_50)},
- {3, 0, 0x04, DR_SOCKET_AM3, str2_TC_50e,sizeof (str2_TC_50e)},
- {3, 0, 0x05, DR_SOCKET_AM3, str2_TC_50B,sizeof (str2_TC_50B)},
- {3, 0, 0x06, DR_SOCKET_AM3, str2_Processor,sizeof (str2_Processor)},
- {3, 0, 0x07, DR_SOCKET_AM3, str2_e_Processor,sizeof (str2_e_Processor)},
- {3, 0, 0x08, DR_SOCKET_AM3, str2_B_Processor,sizeof (str2_B_Processor)},
- {3, 0, 0x09, DR_SOCKET_AM3, str2_0e_Processor,sizeof (str2_0e_Processor)},
- {3, 0, 0x0A, DR_SOCKET_AM3, str2_0_Processor,sizeof (str2_0_Processor)},
- {3, 0, 0x0F, DR_SOCKET_AM3, 0, 0}, //Size 0 for no suffix
- {4, 0, 0x00, DR_SOCKET_AM3, str2_QC_00, sizeof (str2_QC_00)},
- {4, 0, 0x01, DR_SOCKET_AM3, str2_QC_00e,sizeof (str2_QC_00e)},
- {4, 0, 0x02, DR_SOCKET_AM3, str2_QC_00B,sizeof (str2_QC_00B)},
- {4, 0, 0x03, DR_SOCKET_AM3, str2_QC_50, sizeof (str2_QC_50)},
- {4, 0, 0x04, DR_SOCKET_AM3, str2_QC_50e,sizeof (str2_QC_50e)},
- {4, 0, 0x05, DR_SOCKET_AM3, str2_QC_50B,sizeof (str2_QC_50B)},
- {4, 0, 0x06, DR_SOCKET_AM3, str2_Processor, sizeof (str2_Processor)},
- {4, 0, 0x07, DR_SOCKET_AM3, str2_e_Processor, sizeof (str2_e_Processor)},
- {4, 0, 0x08, DR_SOCKET_AM3, str2_B_Processor, sizeof (str2_B_Processor)},
- {4, 0, 0x09, DR_SOCKET_AM3, str2_0e_Processor, sizeof (str2_0e_Processor)},
- {4, 0, 0x0A, DR_SOCKET_AM3, str2_SE_AM3, sizeof (str2_SE_AM3)},
- {4, 0, 0x0B, DR_SOCKET_AM3, str2_HE_AM3, sizeof (str2_HE_AM3)},
- {4, 0, 0x0C, DR_SOCKET_AM3, str2_EE_AM3, sizeof (str2_EE_AM3)},
- {4, 0, 0x0D, DR_SOCKET_AM3, str2_QCP_AM3, sizeof (str2_QCP_AM3)},
- {4, 0, 0x0E, DR_SOCKET_AM3, str2_0_Processor, sizeof (str2_0_Processor)},
- {4, 0, 0x0F, DR_SOCKET_AM3, 0, 0}, //Size 0 for no suffix
- {4, 1, 0x00, DR_SOCKET_AM3, str2_TWKR_Black_Edition, sizeof (str2_TWKR_Black_Edition)},
- {4, 1, 0x01, DR_SOCKET_AM3, str2_L_Processor, sizeof (str2_L_Processor)},
- {4, 1, 0x04, DR_SOCKET_AM3, str2_QC_T, sizeof (str2_QC_T)},
- {6, 0, 0x00, DR_SOCKET_AM3, str2_SC_5T, sizeof (str2_SC_5T)},
- {6, 0, 0x00, DR_SOCKET_AM3, str2_SC_0T, sizeof (str2_SC_0T)},
- {6, 0, 0x0F, DR_SOCKET_AM3, 0, 0} //Size 0 for no suffix
-};
-
-
-CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayAm3 = {
- (sizeof (CpuF10BrandIdString1ArrayAm3) / sizeof (AMD_CPU_BRAND)),
- CpuF10BrandIdString1ArrayAm3
-};
-
-
-CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayAm3 = {
- (sizeof (CpuF10BrandIdString2ArrayAm3) / sizeof (AMD_CPU_BRAND)),
- CpuF10BrandIdString2ArrayAm3
-};
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c
deleted file mode 100644
index 16664ea..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU BrandId related functions and structures for package ASB2.
- *
- * Contains code that provides CPU BrandId information
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 35874 $ @e \$Date: 2010-08-03 11:32:19 +0800 (Tue, 03 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-#include "F10PackageType.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-// String1
-CONST CHAR8 ROMDATA str_AMD_V[] = "AMD V";
-CONST CHAR8 ROMDATA str_Athlon_II_Neo_K[] = "AMD Athlon(tm) II Neo K";
-CONST CHAR8 ROMDATA str_Athlon_II_Neo_N[] = "AMD Athlon(tm) II Neo N";
-CONST CHAR8 ROMDATA str_Athlon_II_Neo_R[] = "AMD Athlon(tm) II Neo R";
-CONST CHAR8 ROMDATA str_Turion_II_Neo_K[] = "AMD Turion(tm) II Neo K";
-CONST CHAR8 ROMDATA str_Turion_II_Neo_N[] = "AMD Turion(tm) II Neo N";
-
-// String2
-CONST CHAR8 ROMDATA str_Asb2_5_Processor[] = "5 Processor";
-CONST CHAR8 ROMDATA str_Asb2_5_Dual_Core_Processor[] = "5 Dual-Core Processor";
-CONST CHAR8 ROMDATA str_L_Processor[] = "L Processor";
-CONST CHAR8 ROMDATA str_L_Dual_Core_Processor[] = "L Dual-Core Processor";
-CONST CHAR8 ROMDATA str_H_Dual_Core_Processor[] = "H Dual-Core Processor";
-
-/*---------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *---------------------------------------------------------------------------------------
- */
-
-CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString1ArrayAsb2[] =
-{
- // ASB2
- {1, 0, 1, DR_SOCKET_ASB2, str_Athlon_II_Neo_K, sizeof (str_Athlon_II_Neo_K)},
- {1, 0, 2, DR_SOCKET_ASB2, str_AMD_V, sizeof (str_AMD_V)},
- {1, 0, 3, DR_SOCKET_ASB2, str_Athlon_II_Neo_R, sizeof (str_Athlon_II_Neo_R)},
- {2, 0, 1, DR_SOCKET_ASB2, str_Turion_II_Neo_K, sizeof (str_Turion_II_Neo_K)},
- {2, 0, 2, DR_SOCKET_ASB2, str_Athlon_II_Neo_K, sizeof (str_Athlon_II_Neo_K)},
- {2, 0, 3, DR_SOCKET_ASB2, str_AMD_V, sizeof (str_AMD_V)},
- {2, 0, 4, DR_SOCKET_ASB2, str_Turion_II_Neo_N, sizeof (str_Turion_II_Neo_N)},
- {2, 0, 5, DR_SOCKET_ASB2, str_Athlon_II_Neo_N, sizeof (str_Athlon_II_Neo_N)}
-}; //Cores, page, index, socket, stringstart, stringlength
-
-
-CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString2ArrayAsb2[] =
-{
- // ASB2
- {1, 0, 0x01, DR_SOCKET_ASB2, str_Asb2_5_Processor, sizeof (str_Asb2_5_Processor)},
- {1, 0, 0x02, DR_SOCKET_ASB2, str_L_Processor, sizeof (str_L_Processor)},
- {2, 0, 0x01, DR_SOCKET_ASB2, str_Asb2_5_Dual_Core_Processor, sizeof (str_Asb2_5_Dual_Core_Processor)},
- {2, 0, 0x02, DR_SOCKET_ASB2, str_L_Dual_Core_Processor, sizeof (str_L_Dual_Core_Processor)},
- {2, 0, 0x04, DR_SOCKET_ASB2, str_H_Dual_Core_Processor, sizeof (str_H_Dual_Core_Processor)},
- {1, 0, 0x0F, DR_SOCKET_ASB2, 0, 0}, //Size 0 for no suffix
- {2, 0, 0x0F, DR_SOCKET_ASB2, 0, 0}, //Size 0 for no suffix
-};
-
-
-CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayAsb2 = {
- (sizeof (CpuF10BrandIdString1ArrayAsb2) / sizeof (AMD_CPU_BRAND)),
- CpuF10BrandIdString1ArrayAsb2
-};
-
-
-CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayAsb2 = {
- (sizeof (CpuF10BrandIdString2ArrayAsb2) / sizeof (AMD_CPU_BRAND)),
- CpuF10BrandIdString2ArrayAsb2
-};
-
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10BrandIdC32.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10BrandIdC32.c
deleted file mode 100644
index b3f8539..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10BrandIdC32.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU BrandId related functions and structures for socket C32.
- *
- * Contains code that provides CPU BrandId information
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-// PRIVATE FORMAT FOR BRAND TABLE ... FOR AMD USE ONLY
-
-// String1
-CONST CHAR8 ROMDATA str_Opteron_41[] = "AMD Opteron(tm) Processor 41";
-CONST CHAR8 ROMDATA str_Embedded_Opteron_C32[] = "Embedded AMD Opteron(tm) Processor ";
-
-// String2
-CONST CHAR8 ROMDATA str2_HE_C32[] = " HE";
-CONST CHAR8 ROMDATA str2_EE_C32[] = " EE";
-CONST CHAR8 ROMDATA str2_QS_HE_C32[] = "QS HE";
-CONST CHAR8 ROMDATA str2_LE_HE_C32[] = "LE HE";
-CONST CHAR8 ROMDATA str2_KX_HE_C32[] = "KX HE";
-CONST CHAR8 ROMDATA str2_GL_EE_C32[] = "GL EE";
-
-/*---------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *---------------------------------------------------------------------------------------
- */
-
-CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString1ArrayC32[] =
-{
- // C32r1 string1:
- {4, 0, 0x00, DR_SOCKET_C32, str_Opteron_41, sizeof (str_Opteron_41)},
- {4, 1, 0x01, DR_SOCKET_C32, str_Embedded_Opteron_C32, sizeof (str_Embedded_Opteron_C32)},
- {6, 0, 0x00, DR_SOCKET_C32, str_Opteron_41, sizeof (str_Opteron_41)},
- {6, 1, 0x01, DR_SOCKET_C32, str_Embedded_Opteron_C32, sizeof (str_Embedded_Opteron_C32)}
-}; //Cores, page, index, socket, stringstart, stringlength
-
-
-CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString2ArrayC32[] =
-{
- // C32r1 string2:
- {4, 0, 0x00, DR_SOCKET_C32, str2_HE_C32, sizeof (str2_HE_C32)},
- {4, 0, 0x01, DR_SOCKET_C32, str2_EE_C32, sizeof (str2_EE_C32)},
- {4, 0, 0x0F, DR_SOCKET_C32, 0, 0}, //Size 0 for no suffix
- {4, 1, 0x01, DR_SOCKET_C32, str2_QS_HE_C32, sizeof (str2_QS_HE_C32)},
- {4, 1, 0x02, DR_SOCKET_C32, str2_LE_HE_C32, sizeof (str2_LE_HE_C32)},
- {6, 0, 0x00, DR_SOCKET_C32, str2_HE_C32, sizeof (str2_HE_C32)},
- {6, 0, 0x01, DR_SOCKET_C32, str2_EE_C32, sizeof (str2_EE_C32)},
- {6, 0, 0x0F, DR_SOCKET_C32, 0, 0}, //Size 0 for no suffix
- {6, 1, 0x01, DR_SOCKET_C32, str2_KX_HE_C32, sizeof (str2_KX_HE_C32)},
- {6, 1, 0x02, DR_SOCKET_C32, str2_GL_EE_C32, sizeof (str2_GL_EE_C32)}
-};
-
-
-CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayC32 = {
- (sizeof (CpuF10BrandIdString1ArrayC32) / sizeof (AMD_CPU_BRAND)),
- CpuF10BrandIdString1ArrayC32
-};
-
-
-CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayC32 = {
- (sizeof (CpuF10BrandIdString2ArrayC32) / sizeof (AMD_CPU_BRAND)),
- CpuF10BrandIdString2ArrayC32
-};
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c
deleted file mode 100644
index d837f9d..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c
+++ /dev/null
@@ -1,175 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU BrandId related functions and structures for socket Fr1207.
- *
- * Contains code that provides CPU BrandId information
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-// PRIVATE FORMAT FOR BRAND TABLE ... FOR AMD USE ONLY
-
-// String1
-/*CHAR8 strEngSample[] = "AMD Engineering Sample";
-CHAR8 strTtkSample[] = "AMD Thermal Test Kit";
-CHAR8 strUnknown[] = "AMD Processor model unknown";
-*/
-CONST CHAR8 ROMDATA str_DC_Opteron83[] = "Dual-Core AMD Opteron(tm) Processor 83";
-CONST CHAR8 ROMDATA str_DC_Opteron23[] = "Dual-Core AMD Opteron(tm) Processor 23";
-CONST CHAR8 ROMDATA str_QC_Opteron83[] = "Quad-Core AMD Opteron(tm) Processor 83";
-CONST CHAR8 ROMDATA str_QC_Opteron23[] = "Quad-Core AMD Opteron(tm) Processor 23";
-CONST CHAR8 ROMDATA str_eQC_Opteron83[] = "Embedded AMD Opteron(tm) Processor 83";
-CONST CHAR8 ROMDATA str_eQC_Opteron23[] = "Embedded AMD Opteron(tm) Processor 23";
-CONST CHAR8 ROMDATA str_eQC_Opteron13[] = "Embedded AMD Opteron(tm) Processor 13";
-CONST CHAR8 ROMDATA str_Embedded_Opteron[] = "Embedded AMD Opteron(tm) Processor ";
-CONST CHAR8 ROMDATA str_SC_Opteron84[] = "Six-Core AMD Opteron(tm) Processor 84";
-CONST CHAR8 ROMDATA str_SC_Opteron24[] = "Six-Core AMD Opteron(tm) Processor 24";
-
-CONST CHAR8 ROMDATA str_PhenomFX[] = "AMD Phenom(tm) FX-";
-
-
-// String2
-CONST CHAR8 ROMDATA str2_SE[] = " SE";
-CONST CHAR8 ROMDATA str2_HE[] = " HE";
-CONST CHAR8 ROMDATA str2_EE[] = " EE";
-CONST CHAR8 ROMDATA str2_VS[] = "VS";
-
-CONST CHAR8 ROMDATA str2_NP_HE[] = "NP HE";
-CONST CHAR8 ROMDATA str2_GF_HE[] = "GF HE";
-CONST CHAR8 ROMDATA str2_HF_HE[] = "HF HE";
-CONST CHAR8 ROMDATA str2_QS_HE[] = "QS HE";
-CONST CHAR8 ROMDATA str2_KH_HE[] = "KH HE";
-CONST CHAR8 ROMDATA str2_KS_EE[] = "KS HE";
-
-CONST CHAR8 ROMDATA str2_QCP[] = " Quad-Core Processor";
-
-/*---------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *---------------------------------------------------------------------------------------
- */
-
-CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString1ArrayFr1207[] =
-{
- // FR2/FR4 1207
- {2, 0, 0, DR_SOCKET_1207, str_DC_Opteron83, sizeof (str_DC_Opteron83)},
- {2, 0, 1, DR_SOCKET_1207, str_DC_Opteron23, sizeof (str_DC_Opteron23)},
- {3, 0, 0, DR_SOCKET_1207, str_Embedded_Opteron, sizeof (str_Embedded_Opteron)},
- {4, 0, 0, DR_SOCKET_1207, str_QC_Opteron83, sizeof (str_QC_Opteron83)},
- {4, 0, 1, DR_SOCKET_1207, str_QC_Opteron23, sizeof (str_QC_Opteron23)},
- {4, 0, 2, DR_SOCKET_1207, str_eQC_Opteron83, sizeof (str_eQC_Opteron83)},
- {4, 0, 3, DR_SOCKET_1207, str_eQC_Opteron23, sizeof (str_eQC_Opteron23)},
- {4, 0, 4, DR_SOCKET_1207, str_eQC_Opteron13, sizeof (str_eQC_Opteron13)},
- {4, 0, 5, DR_SOCKET_1207, str_PhenomFX, sizeof (str_PhenomFX)},
- {4, 1, 1, DR_SOCKET_1207, str_Embedded_Opteron, sizeof (str_Embedded_Opteron)},
- {6, 0, 0, DR_SOCKET_1207, str_SC_Opteron84, sizeof (str_SC_Opteron84)},
- {6, 0, 1, DR_SOCKET_1207, str_SC_Opteron24, sizeof (str_SC_Opteron24)}
-}; //Cores, page, index, socket, stringstart, stringlength
-
-
-CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString2ArrayFr1207[] =
-{
- // FR2/FR4 1207
- {2, 0, 0x0A, DR_SOCKET_1207, str2_SE, sizeof (str2_SE)},
- {2, 0, 0x0B, DR_SOCKET_1207, str2_HE, sizeof (str2_HE)},
- {2, 0, 0x0C, DR_SOCKET_1207, str2_EE, sizeof (str2_EE)},
- {2, 0, 0x0F, DR_SOCKET_1207, 0, 0}, //Size 0 for no suffix
- {3, 0, 0x00, DR_SOCKET_1207, str2_NP_HE, sizeof (str2_NP_HE)},
- {3, 0, 0x0F, DR_SOCKET_1207, 0, 0}, //Size 0 for no suffix
- {4, 0, 0x0A, DR_SOCKET_1207, str2_SE, sizeof (str2_SE)},
- {4, 0, 0x0B, DR_SOCKET_1207, str2_HE, sizeof (str2_HE)},
- {4, 0, 0x0C, DR_SOCKET_1207, str2_EE, sizeof (str2_EE)},
- {4, 0, 0x0D, DR_SOCKET_1207, str2_QCP, sizeof (str2_QCP)},
- {4, 0, 0x0F, DR_SOCKET_1207, 0, 0}, //Size 0 for no suffix
- {4, 1, 0x01, DR_SOCKET_1207, str2_GF_HE, sizeof (str2_GF_HE)},
- {4, 1, 0x02, DR_SOCKET_1207, str2_HF_HE, sizeof (str2_HF_HE)},
- {4, 1, 0x03, DR_SOCKET_1207, str2_VS, sizeof (str2_VS)},
- {4, 1, 0x04, DR_SOCKET_1207, str2_QS_HE, sizeof (str2_QS_HE)},
- {4, 1, 0x05, DR_SOCKET_1207, str2_NP_HE, sizeof (str2_NP_HE)},
- {4, 1, 0x06, DR_SOCKET_1207, str2_KH_HE, sizeof (str2_KH_HE)},
- {4, 1, 0x07, DR_SOCKET_1207, str2_KS_EE, sizeof (str2_KS_EE)},
- {6, 0, 0x00, DR_SOCKET_1207, str2_SE, sizeof (str2_SE)},
- {6, 0, 0x01, DR_SOCKET_1207, str2_HE, sizeof (str2_HE)},
- {6, 0, 0x02, DR_SOCKET_1207, str2_EE, sizeof (str2_EE)},
- {6, 0, 0x0F, DR_SOCKET_1207, 0, 0} //Size 0 for no suffix
-};
-
-
-CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayFr1207 = {
- (sizeof (CpuF10BrandIdString1ArrayFr1207) / sizeof (AMD_CPU_BRAND)),
- CpuF10BrandIdString1ArrayFr1207
-};
-
-
-CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayFr1207 = {
- (sizeof (CpuF10BrandIdString2ArrayFr1207) / sizeof (AMD_CPU_BRAND)),
- CpuF10BrandIdString2ArrayFr1207
-};
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10BrandIdG34.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10BrandIdG34.c
deleted file mode 100644
index f3f798d..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10BrandIdG34.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU BrandId related functions and structures for socket G34.
- *
- * Contains code that provides CPU BrandId information
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-// PRIVATE FORMAT FOR BRAND TABLE ... FOR AMD USE ONLY
-
-// String1
-CONST CHAR8 ROMDATA str_Opteron_61[] = "AMD Opteron(tm) Processor 61";
-CONST CHAR8 ROMDATA str_Embedded_Opteron_G34[] = "Embedded AMD Opteron(tm) Processor ";
-
-// String2
-CONST CHAR8 ROMDATA str2_SE_G34[] = " SE";
-CONST CHAR8 ROMDATA str2_HE_G34[] = " HE";
-CONST CHAR8 ROMDATA str2_QS_G34[] = "QS";
-CONST CHAR8 ROMDATA str2_KS_G34[] = "KS";
-
-
-/*---------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *---------------------------------------------------------------------------------------
- */
-
-CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString1ArrayG34[] =
-{
- // G34r1 string1:
- {8, 0, 0x00, DR_SOCKET_G34, str_Opteron_61, sizeof (str_Opteron_61)},
- {8, 1, 0x01, DR_SOCKET_G34, str_Embedded_Opteron_G34, sizeof (str_Embedded_Opteron_G34)},
- {12, 0, 0x00, DR_SOCKET_G34, str_Opteron_61, sizeof (str_Opteron_61)}
-}; //Cores, page, index, socket, stringstart, stringlength
-
-CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString2ArrayG34[] =
-{
- // G34r1 string2:
- {8, 0, 0x00, DR_SOCKET_G34, str2_HE_G34, sizeof (str2_HE_G34)},
- {8, 0, 0x01, DR_SOCKET_G34, str2_SE_G34, sizeof (str2_SE_G34)},
- {8, 1, 0x01, DR_SOCKET_G34, str2_QS_G34, sizeof (str2_QS_G34)},
- {8, 1, 0x02, DR_SOCKET_G34, str2_KS_G34, sizeof (str2_KS_G34)},
- {8, 0, 0x0F, DR_SOCKET_G34, 0, 0}, //Size 0 for no suffix
- {12, 0, 0x00, DR_SOCKET_G34, str2_HE_G34, sizeof (str2_HE_G34)},
- {12, 0, 0x01, DR_SOCKET_G34, str2_SE_G34, sizeof (str2_SE_G34)},
- {12, 0, 0x0F, DR_SOCKET_G34, 0, 0} //Size 0 for no suffix
-};
-
-
-CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayG34 = {
- (sizeof (CpuF10BrandIdString1ArrayG34) / sizeof (AMD_CPU_BRAND)),
- CpuF10BrandIdString1ArrayG34
-};
-
-
-CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayG34 = {
- (sizeof (CpuF10BrandIdString2ArrayG34) / sizeof (AMD_CPU_BRAND)),
- CpuF10BrandIdString2ArrayG34
-};
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c
deleted file mode 100644
index e3d09aa..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU BrandId related functions and structures for socket S1g3.
- *
- * Contains code that provides CPU BrandId information
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-// PRIVATE FORMAT FOR BRAND TABLE ... FOR AMD USE ONLY
-
-// String1
-/*CHAR8 strEngSample[] = "AMD Engineering Sample";
-CHAR8 strTtkSample[] = "AMD Thermal Test Kit";
-CHAR8 strUnknown[] = "AMD Processor model unknown";
-*/
-// S1g3 NC 0
-CONST CHAR8 ROMDATA str_Sempron_M1[] = "AMD Sempron(tm) M1";
-
-// S1g3 NC 1
-CONST CHAR8 ROMDATA str_Turion_II_U_DC_M_M6[] = "AMD Turion(tm) II Ultra Dual-Core Mobile M6";
-CONST CHAR8 ROMDATA str_Turion_II_DC_M_M5[] = "AMD Turion(tm) II Dual-Core Mobile M5";
-CONST CHAR8 ROMDATA str_Athlon_II_DC_M3[] = "AMD Athlon(tm) II Dual-Core M3";
-
-// String2
-
-
-/*---------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *---------------------------------------------------------------------------------------
- */
-
-CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString1ArrayS1g3[] =
-{
- // S1g3
- {1, 0, 0, DR_SOCKET_S1G3, str_Sempron_M1, sizeof (str_Sempron_M1)},
- {2, 0, 0, DR_SOCKET_S1G3, str_Turion_II_U_DC_M_M6, sizeof (str_Turion_II_U_DC_M_M6)},
- {2, 0, 1, DR_SOCKET_S1G3, str_Turion_II_DC_M_M5, sizeof (str_Turion_II_DC_M_M5)},
- {2, 0, 2, DR_SOCKET_S1G3, str_Athlon_II_DC_M3, sizeof (str_Athlon_II_DC_M3)}
-}; //Cores, page, index, socket, stringstart, stringlength
-
-
-CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString2ArrayS1g3[] =
-{
- // S1g3
- {1, 0, 0x0F, DR_SOCKET_S1G3, 0, 0}, //Size 0 for no suffix
- {2, 0, 0x0F, DR_SOCKET_S1G3, 0, 0} //Size 0 for no suffix
-};
-
-
-CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayS1g3 = {
- (sizeof (CpuF10BrandIdString1ArrayS1g3) / sizeof (AMD_CPU_BRAND)),
- CpuF10BrandIdString1ArrayS1g3
-};
-
-
-CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayS1g3 = {
- (sizeof (CpuF10BrandIdString2ArrayS1g3) / sizeof (AMD_CPU_BRAND)),
- CpuF10BrandIdString2ArrayS1g3
-};
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c
deleted file mode 100644
index acc908b..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU BrandId related functions and structures for package S1g4.
- *
- * Contains code that provides CPU BrandId information
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 35874 $ @e \$Date: 2010-08-03 11:32:19 +0800 (Tue, 03 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-#include "F10PackageType.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-// String1
-CONST CHAR8 ROMDATA str_AMD_V_S1g4[] = "AMD V";
-CONST CHAR8 ROMDATA str_Turion_II_P[] = "AMD Turion(tm) II P";
-CONST CHAR8 ROMDATA str_Athlon_II_P[] = "AMD Athlon(tm) II P";
-CONST CHAR8 ROMDATA str_Phenom_II_X[] = "AMD Phenom(tm) II X";
-CONST CHAR8 ROMDATA str_Turion_II_N[] = "AMD Turion(tm) II N";
-CONST CHAR8 ROMDATA str_Athlon_II_N[] = "AMD Athlon(tm) II N";
-CONST CHAR8 ROMDATA str_Phenom_II_P[] = "AMD Phenom(tm) II P";
-CONST CHAR8 ROMDATA str_Phenom_II_N[] = "AMD Phenom(tm) II N";
-
-// String2
-CONST CHAR8 ROMDATA str_0_Processor[] = "0 Processor";
-CONST CHAR8 ROMDATA str_0_Dual_Core_Processor[] = "0 Dual-Core Processor";
-CONST CHAR8 ROMDATA str_0_Triple_Core_Processor[] = "0 Triple-Core Processor";
-CONST CHAR8 ROMDATA str_0_Quad_Core_Processor[] = "0 Quad-Core Processor";
-
-/*---------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *---------------------------------------------------------------------------------------
- */
-
-CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString1ArrayS1g4[] =
-{
- // S1g4
- {1, 0, 1, DR_SOCKET_S1G4, str_AMD_V_S1g4, sizeof (str_AMD_V_S1g4)},
- {2, 0, 3, DR_SOCKET_S1G4, str_Turion_II_P, sizeof (str_Turion_II_P)},
- {2, 0, 4, DR_SOCKET_S1G4, str_Athlon_II_P, sizeof (str_Athlon_II_P)},
- {2, 0, 5, DR_SOCKET_S1G4, str_Phenom_II_X, sizeof (str_Phenom_II_X)},
- {2, 0, 6, DR_SOCKET_S1G4, str_Phenom_II_N, sizeof (str_Phenom_II_N)},
- {2, 0, 7, DR_SOCKET_S1G4, str_Turion_II_N, sizeof (str_Turion_II_N)},
- {2, 0, 8, DR_SOCKET_S1G4, str_Athlon_II_N, sizeof (str_Athlon_II_N)},
- {2, 0, 9, DR_SOCKET_S1G4, str_Phenom_II_P, sizeof (str_Phenom_II_P)},
- {3, 0, 2, DR_SOCKET_S1G4, str_Phenom_II_P, sizeof (str_Phenom_II_P)},
- {3, 0, 3, DR_SOCKET_S1G4, str_Phenom_II_N, sizeof (str_Phenom_II_N)},
- {3, 0, 4, DR_SOCKET_S1G4, str_Phenom_II_X, sizeof (str_Phenom_II_X)},
- {4, 0, 1, DR_SOCKET_S1G4, str_Phenom_II_P, sizeof (str_Phenom_II_P)},
- {4, 0, 2, DR_SOCKET_S1G4, str_Phenom_II_X, sizeof (str_Phenom_II_X)},
- {4, 0, 3, DR_SOCKET_S1G4, str_Phenom_II_N, sizeof (str_Phenom_II_N)}
-}; //Cores, page, index, socket, stringstart, stringlength
-
-
-CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString2ArrayS1g4[] =
-{
- // S1g4
- {1, 0, 0x01, DR_SOCKET_S1G4, str_0_Processor, sizeof (str_0_Processor)},
- {2, 0, 0x02, DR_SOCKET_S1G4, str_0_Dual_Core_Processor, sizeof (str_0_Dual_Core_Processor)},
- {3, 0, 0x02, DR_SOCKET_S1G4, str_0_Triple_Core_Processor, sizeof (str_0_Triple_Core_Processor)},
- {4, 0, 0x01, DR_SOCKET_S1G4, str_0_Quad_Core_Processor, sizeof (str_0_Quad_Core_Processor)},
- {1, 0, 0x0F, DR_SOCKET_S1G4, 0, 0}, //Size 0 for no suffix
- {2, 0, 0x0F, DR_SOCKET_S1G4, 0, 0}, //Size 0 for no suffix
- {3, 0, 0x0F, DR_SOCKET_S1G4, 0, 0}, //Size 0 for no suffix
- {4, 0, 0x0F, DR_SOCKET_S1G4, 0, 0} //Size 0 for no suffix
-};
-
-
-CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayS1g4 = {
- (sizeof (CpuF10BrandIdString1ArrayS1g4) / sizeof (AMD_CPU_BRAND)),
- CpuF10BrandIdString1ArrayS1g4
-};
-
-
-CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayS1g4 = {
- (sizeof (CpuF10BrandIdString2ArrayS1g4) / sizeof (AMD_CPU_BRAND)),
- CpuF10BrandIdString2ArrayS1g4
-};
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c
deleted file mode 100644
index e041a02..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 ROM Execution Cache Defaults
- *
- * Contains default values for ROM execution cache setup
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/Family/0x10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuCacheInit.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10CACHEDEFAULTS_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-#define BSP_STACK_SIZE 16384
-#define CORE0_STACK_SIZE 16384
-#define CORE1_STACK_SIZE 4096
-#define MEM_TRAINING_BUFFER_SIZE 16384
-#define VAR_MTRR_MASK 0x0000FFFFFFFFFFFF
-#define VAR_MTRR_MASK_CP VAR_MTRR_MASK
-
-#define HEAP_BASE_MASK 0x0000FFFFFFFFFFFF
-
-#define SHARED_MEM_SIZE 0
-
-CONST CACHE_INFO ROMDATA CpuF10CacheInfo =
-{
- BSP_STACK_SIZE,
- CORE0_STACK_SIZE,
- CORE1_STACK_SIZE,
- MEM_TRAINING_BUFFER_SIZE,
- SHARED_MEM_SIZE,
- VAR_MTRR_MASK,
- VAR_MTRR_MASK,
- HEAP_BASE_MASK,
- LimitedByL2Size
-};
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns the family specific properties of the cache, and its usage.
- *
- * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[out] CacheInfoPtr Points to the cache info properties on exit.
- * @param[out] NumberOfElements Will be one to indicate one entry.
- * @param[in] StdHeader Header for library and services.
- *
- */
-VOID
-GetF10CacheInfo (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- OUT CONST VOID **CacheInfoPtr,
- OUT UINT8 *NumberOfElements,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- *NumberOfElements = 1;
- *CacheInfoPtr = &CpuF10CacheInfo;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c
deleted file mode 100644
index 6a70ced..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU Cache Flush On Halt Function.
- *
- * Contains code to Level the Feature in a multi-socket system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/Family/0x10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuServices.h"
-#include "cpuFamilyTranslation.h"
-#include "GeneralServices.h"
-#include "cpuPostInit.h"
-#include "cpuFeatures.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10CACHEFLUSHONHALT_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P U B L I C F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- * Enable Cpu Cache Flush On Halt Function
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] EntryPoint Timepoint designator.
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Config Handle for library, services.
- */
-VOID
-SetF10CacheFlushOnHaltRegister (
- IN CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices,
- IN UINT64 EntryPoint,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 AndMask;
- UINT32 OrMask;
- UINT32 CoreCount;
- CPU_LOGICAL_ID LogicalId;
- PCI_ADDR PciAddress;
-
- if ((EntryPoint & CPU_FEAT_AFTER_POST_MTRR_SYNC) != 0) {
- // Initialize F3xDC
- // bits[25:19] CacheFlushOnHaltTmr = 28h
- // bits[18:16] CacheFlushOnHaltCtl = 111b
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = CLOCK_POWER_TIMING_CTRL2_REG;
- AndMask = 0xFC00FFFF;
- OrMask = 0x01470000;
-
- GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
- if ((LogicalId.Revision & AMD_F10_C2) != 0) {
- //For F10_C2 single Core, F3xDC[18:16] = 0
- GetActiveCoresInCurrentSocket (&CoreCount, StdHeader);
- if (CoreCount == 1) {
- OrMask = 0x01400000;
- }
- }
-
- IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, &OrMask, StdHeader);
- ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xDC
- }
-}
-
-CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10CacheFlushOnHalt =
-{
- 0,
- SetF10CacheFlushOnHaltRegister
-};
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10Cpb.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10Cpb.c
deleted file mode 100644
index d175ff1..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10Cpb.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 CPB Initialization
- *
- * Enables core performance boost.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F10
- * @e \$Revision: 35636 $ @e \$Date: 2010-07-28 09:24:55 +0800 (Wed, 28 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "GeneralServices.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuF10PowerMgmt.h"
-#include "cpuFeatures.h"
-#include "cpuRegisters.h"
-#include "cpuCpb.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10CPB_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * BSC entry point for checking whether or not CPB is supported.
- *
- * @param[in] CpbServices The current CPU's family services.
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] Socket Zero based socket number to check.
- * @param[in] StdHeader Config handle for library and services.
- *
- * @retval TRUE CPB is supported.
- * @retval FALSE CPB is not supported.
- *
- */
-BOOLEAN
-STATIC
-F10IsCpbSupported (
- IN CPB_FAMILY_SERVICES *CpbServices,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN UINT32 Socket,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 CpbControl;
- PCI_ADDR PciAddress;
- AGESA_STATUS IgnoredSts;
- CPUID_DATA CpuidData;
-
- CpbControl = 0;
- LibAmdCpuidRead (AMD_CPUID_APM, &CpuidData, StdHeader);
- if (((CpuidData.EDX_Reg & 0x00000200) >> 9) == 1) {
- GetPciAddress (StdHeader, Socket, 0, &PciAddress, &IgnoredSts);
- PciAddress.Address.Function = FUNC_4;
- PciAddress.Address.Register = CPB_CTRL_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader);
- }
- return (BOOLEAN) (((CPB_CTRL_REGISTER *) (&CpbControl))->NumBoostStates != 0);
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * BSC entry point for for enabling Core Performance Boost.
- *
- * Set up F4x15C[BoostSrc] and start the PDMs according to the BKDG.
- *
- * @param[in] CpbServices The current CPU's family services.
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] EntryPoint Current CPU feature dispatch point.
- * @param[in] Socket Zero based socket number to check.
- * @param[in] StdHeader Config handle for library and services.
- *
- * @retval AGESA_SUCCESS Always succeeds.
- *
- */
-AGESA_STATUS
-STATIC
-F10InitializeCpb (
- IN CPB_FAMILY_SERVICES *CpbServices,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN UINT64 EntryPoint,
- IN UINT32 Socket,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 CpbControl;
- UINT32 Module;
- PCI_ADDR PciAddress;
- AGESA_STATUS IgnoredSts;
-
- if ((EntryPoint & CPU_FEAT_BEFORE_PM_INIT) != 0) {
- for (Module = 0; Module < (UINT8)GetPlatformNumberOfModules (); Module++) {
- GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
- PciAddress.Address.Function = FUNC_4;
- PciAddress.Address.Register = CPB_CTRL_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader);
- ((CPB_CTRL_REGISTER *) (&CpbControl))->BoostSrc = 3;
- IDS_OPTION_HOOK (IDS_CPB_CTRL, &CpbControl, StdHeader);
- LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl, StdHeader);
-
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = POPUP_PSTATE_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &CpbControl, StdHeader);
- ((POPUP_PSTATE_REGISTER *) (&CpbControl))->CacheFlushPopDownEn = 1;
- LibAmdPciWrite (AccessWidth32, PciAddress, &CpbControl, StdHeader);
- }
- }
- return AGESA_SUCCESS;
-}
-
-CONST CPB_FAMILY_SERVICES ROMDATA F10CpbSupport =
-{
- 0,
- F10IsCpbSupported,
- F10InitializeCpb
-};
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10Dmi.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10Dmi.c
deleted file mode 100644
index b2df819..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10Dmi.c
+++ /dev/null
@@ -1,478 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD DMI Record Creation API, and related functions.
- *
- * Contains code that produce the DMI related information.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 38082 $ @e \$Date: 2010-09-18 01:51:40 +0800 (Sat, 18 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "cpuRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuPstateTables.h"
-#include "cpuLateInit.h"
-#include "cpuF10PowerMgmt.h"
-#include "cpuF10Utilities.h"
-#include "cpuServices.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G3_DXE)
-RDATA_GROUP (G3_DXE)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10DMI_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable;
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-VOID
-STATIC
-F10Translate7BitVidTo6Bit (
- IN OUT UINT8 * MaxVidPtr
- );
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * DmiF10GetInfo
- *
- * Get CPU type information
- *
- * @param[in,out] CpuInfoPtr Pointer to CPU_TYPE_INFO struct.
- * @param[in] StdHeader Standard Head Pointer
- *
- */
-VOID
-DmiF10GetInfo (
- IN OUT CPU_TYPE_INFO *CpuInfoPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- CPUID_DATA CpuId;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
-
- LibAmdCpuidRead (AMD_CPUID_FMF, &CpuId, StdHeader);
- CpuInfoPtr->ExtendedFamily = (UINT8) (CpuId.EAX_Reg >> 20) & 0xFF; // bit 27:20
- CpuInfoPtr->ExtendedModel = (UINT8) (CpuId.EAX_Reg >> 16) & 0xF; // bit 19:16
- CpuInfoPtr->BaseFamily = (UINT8) (CpuId.EAX_Reg >> 8) & 0xF; // bit 11:8
- CpuInfoPtr->BaseModel = (UINT8) (CpuId.EAX_Reg >> 4) & 0xF; // bit 7:4
- CpuInfoPtr->Stepping = (UINT8) (CpuId.EAX_Reg & 0xF); // bit 3:0
-
- CpuInfoPtr->PackageType = (UINT8) (CpuId.EBX_Reg >> 28) & 0xF; // bit 31:28
- CpuInfoPtr->BrandId.Pg = (UINT8) (CpuId.EBX_Reg >> 15) & 0x1; // bit 15
- CpuInfoPtr->BrandId.String1 = (UINT8) (CpuId.EBX_Reg >> 11) & 0xF; // bit 14:11
- CpuInfoPtr->BrandId.Model = (UINT8) (CpuId.EBX_Reg >> 4) & 0x7F; // bit 10:4
- CpuInfoPtr->BrandId.String2 = (UINT8) (CpuId.EBX_Reg & 0xF); // bit 3:0
-
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
- CpuInfoPtr->TotalCoreNumber = FamilySpecificServices->GetNumberOfCoresForBrandstring (FamilySpecificServices, StdHeader);
- CpuInfoPtr->TotalCoreNumber--;
-
- LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuId, StdHeader);
- CpuInfoPtr->EnabledCoreNumber = (UINT8) (CpuId.ECX_Reg & 0xFF); // bit 7:0
-
- switch (CpuInfoPtr->PackageType) {
- case DR_SOCKET_1207:
- CpuInfoPtr->ProcUpgrade = P_UPGRADE_F1207;
- break;
- case DR_SOCKET_AM3:
- CpuInfoPtr->ProcUpgrade = P_UPGRADE_AM3;
- break;
- case DR_SOCKET_S1G3:
- CpuInfoPtr->ProcUpgrade = P_UPGRADE_S1GX;
- break;
- case DR_SOCKET_G34:
- CpuInfoPtr->ProcUpgrade = P_UPGRADE_G34;
- break;
- case DR_SOCKET_ASB2:
- CpuInfoPtr->ProcUpgrade = P_UPGRADE_NONE;
- break;
- case DR_SOCKET_C32:
- CpuInfoPtr->ProcUpgrade = P_UPGRADE_C32;
- break;
- default:
- CpuInfoPtr->ProcUpgrade = P_UPGRADE_UNKNOWN;
- break;
- }
-
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * DmiF10GetVoltage
- *
- * Get the voltage value according to SMBIOS SPEC's requirement.
- *
- * @param[in] StdHeader Standard Head Pointer
- *
- * @retval Voltage - CPU Voltage.
- *
- */
-UINT8
-DmiF10GetVoltage (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 MaxVid;
- UINT8 Voltage;
- UINT32 Pvimode;
- UINT32 CurrentNodeNum;
- UINT64 MsrData;
- PCI_ADDR TempAddr;
-
- // Voltage = 0x80 + (voltage at boot time * 10)
- GetCurrentNodeNum (&CurrentNodeNum, StdHeader);
- TempAddr.AddressValue = MAKE_SBDFO (0, 0, (24 + CurrentNodeNum), FUNC_3, PW_CTL_MISC_REG);
- LibAmdPciReadBits (TempAddr, 8, 8, &Pvimode, (VOID *)StdHeader);
- //Pvimode is a 1-bit register field: 1-PVI 0-SVI
-
- LibAmdMsrRead (MSR_COFVID_STS, &MsrData, StdHeader);
- MaxVid = (UINT8) (((COFVID_STS_MSR *)&MsrData)->MaxVid);
- if (MaxVid == 0) {
- LibAmdMsrRead (MSR_PSTATE_0, &MsrData, StdHeader);
- MaxVid = (UINT8) (((PSTATE_MSR *)&MsrData)->CpuVid);
- }
-
- if (Pvimode) {
- // PVI mode
- F10Translate7BitVidTo6Bit (&MaxVid);
- if (MaxVid >= 0x20) {
- Voltage = (UINT8) ((7625 - (125 * (MaxVid - 0x20)) + 500) / 1000);
- } else {
- Voltage = (UINT8) ((1550 - (25 * MaxVid) + 50) / 100);
- }
- } else {
- // is SVI mode
- if ((MaxVid >= 0x7C) && (MaxVid <= 0x7F)) {
- Voltage = 0;
- } else {
- Voltage = (UINT8) ((15500 - (125 * MaxVid) + 500) / 1000);
- }
- }
-
- Voltage += 0x80;
- return (Voltage);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * DmiF10GetMaxSpeed
- *
- * Get the Max Speed
- *
- * @param[in] StdHeader Standard Head Pointer
- *
- * @retval MaxSpeed - CPU Max Speed.
- *
- */
-UINT16
-DmiF10GetMaxSpeed (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 NumBoostStates;
- UINT32 P0Frequency;
- UINT32 PciData;
- PCI_ADDR PciAddress;
- CPUID_DATA CpuidData;
- AGESA_STATUS IgnoredSts;
- PSTATE_CPU_FAMILY_SERVICES *FamilyServices;
-
- FamilyServices = NULL;
- GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, &FamilyServices, StdHeader);
- ASSERT (FamilyServices != NULL);
- NumBoostStates = 0;
- LibAmdCpuidRead (AMD_CPUID_APM, &CpuidData, StdHeader);
- if (((CpuidData.EDX_Reg & 0x00000200) >> 9) == 1) {
- GetPciAddress (StdHeader, 0, 0, &PciAddress, &IgnoredSts);
- PciAddress.Address.Function = FUNC_4;
- PciAddress.Address.Register = CPB_CTRL_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
- NumBoostStates = (UINT8) ((PciData >> 2) & 1);
- }
-
- FamilyServices->GetPstateFrequency (FamilyServices, NumBoostStates, &P0Frequency, StdHeader);
- return ((UINT16) P0Frequency);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * DmiF10GetExtClock
- *
- * Get the external clock Speed
- *
- * @param[in] StdHeader Standard Head Pointer
- *
- * @retval ExtClock - CPU external clock Speed.
- *
- */
-UINT16
-DmiF10GetExtClock (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- return (EXTERNAL_CLOCK_DFLT);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * DmiF10GetMemInfo
- *
- * Get memory information.
- *
- * @param[in,out] CpuGetMemInfoPtr Pointer to CPU_GET_MEM_INFO struct.
- * @param[in] StdHeader Standard Head Pointer
- *
- */
-VOID
-DmiF10GetMemInfo (
- IN OUT CPU_GET_MEM_INFO *CpuGetMemInfoPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 PciData;
- PCI_ADDR PciAddress;
-
- // DCT 0
- PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_2, 0x90);
- LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
- // Check if F2x90[DimmEccEn] is set
- if ((PciData & 0x00080000) != 0) {
- CpuGetMemInfoPtr->EccCapable = TRUE;
- } else {
- // DCT 1
- PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_2, 0x190);
- LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
- // Check if F2x190[DimmEccEn] is set
- if ((PciData & 0x00080000) != 0) {
- CpuGetMemInfoPtr->EccCapable = TRUE;
- }
- }
-
- // Partition Row Position - 0 is for dual channel memory
- CpuGetMemInfoPtr->PartitionRowPosition = 0;
-}
-
-/*---------------------------------------------------------------------------------------
- * Processor Family Table
- *
- * Note: 'x' means we don't care this field
- * 002h = "Unknown"
- * 038h = "AMD Turion(TM) II Ultra Dual-Core Mobile M Processor Family"
- * 039h = "AMD Turion(TM) II Dual-Core Mobile M Processor Family"
- * 03Ah = "AMD Athlon(TM) II Dual-Core M Processor Family"
- * 083h = "AMD Athlon(tm) 64 Processor Family"
- * 084h = "AMD Opteron(TM) Processor Family"
- * 085h = "AMD Sempron(tm) Processor Family"
- * 087h = "Dual-Core AMD Opteron Processor Family"
- * 08Ah = "Quad-Core AMD Opteron Processor Family"
- * 08Ch = "AMD Phenom FX Quad-Core Processor Family"
- * 08Dh = "AMD Phenom X4 Quad-Core Processor Family"
- * 08Eh = "AMD Phenom X2 Dual-Core Processor Family"
- * 08Fh = "AMD Athlon X2 Dual-Core Processor Family"
- * 0E6h = "Embedded AMD Opteron Processor Family"
- * 0E7h = "AMD Phenom Triple-Core Processor Family"
- * 0ECh = "AMD Phenom(TM) II Processor Family"
- * 0EDh = "AMD Athlon(TM) II Processor Family"
- * 0EEh = "Six-Core AMD Opteron(TM) Processor Family"
- * 0EFh = "AMD Sempron(TM) M Processor Family"
- *-------------------------------------------------------------------------------------*/
-CONST DMI_BRAND_ENTRY ROMDATA Family10BrandList[] =
-{
- // Brand --> DMI ID translation table
- // PackageType, PgOfBrandId, NumberOfCores, String1ofBrandId, ValueSetToDmiTable
- // {'x', 'x', 'x', 'x', 0x02} MUST be the last one.
- {0, 0, 1, 0, 0x87},
- {0, 0, 1, 1, 0x87},
- {0, 0, 2, 0, 0xE6},
- {0, 0, 3, 0, 0x8A},
- {0, 0, 3, 1, 0x8A},
- {0, 0, 3, 2, 0xE6},
- {0, 0, 3, 3, 0xE6},
- {0, 0, 3, 4, 0xE6},
- {0, 0, 3, 5, 0x8C},
- {0, 0, 5, 0, 0xEE},
- {0, 0, 5, 1, 0xEE},
- {0, 1, 3, 1, 0xE6},
- {1, 0, 0, 0, 0x83},
- {1, 0, 0, 1, 0x85},
- {1, 0, 0, 2, 0x85},
- {1, 0, 0, 3, 0xED},
- {1, 0, 1, 0, 0x87},
- {1, 0, 1, 1, 0x8F},
- {1, 0, 1, 2, 0xED},
- {1, 0, 1, 3, 0xED},
- {1, 0, 1, 4, 0xED},
- {1, 0, 1, 5, 0xED},
- {1, 0, 1, 6, 0xED},
- {1, 0, 1, 7, 0xEC},
- {1, 0, 1, 8, 0xED},
- {1, 0, 1, 9, 0xED},
- {1, 0, 1, 0xA, 0xEC},
- {1, 0, 1, 0xB, 0xEC},
- {1, 0, 2, 0, 0xE7},
- {1, 0, 2, 1, 0xEC},
- {1, 0, 2, 2, 0xEC},
- {1, 0, 2, 3, 0xEC},
- {1, 0, 2, 4, 0xEC},
- {1, 0, 2, 5, 0xED},
- {1, 0, 2, 6, 0xED},
- {1, 0, 2, 7, 0xED},
- {1, 0, 2, 8, 0xEC},
- {1, 0, 2, 9, 0xED},
- {1, 0, 2, 0xA, 0xED},
- {1, 0, 3, 0, 0x8A},
- {1, 0, 3, 1, 0x8C},
- {1, 0, 3, 2, 0x8D},
- {1, 0, 3, 3, 0xEC},
- {1, 0, 3, 4, 0xEC},
- {1, 0, 3, 5, 0xEC},
- {1, 0, 3, 6, 0xEC},
- {1, 0, 3, 7, 0xEC},
- {1, 0, 3, 8, 0xEC},
- {1, 0, 3, 9, 0xEC},
- {1, 0, 3, 0xA, 0xED},
- {1, 0, 3, 0xB, 0xED},
- {1, 0, 3, 0xC, 0xED},
- {1, 0, 3, 0xD, 0xED},
- {1, 0, 3, 0xE, 0xEC},
- {1, 0, 3, 0xF, 0xED},
- {1, 1, 1, 1, 0xED},
- {1, 1, 1, 2, 0xED},
- {1, 1, 3, 0, 0xEC},
- {1, 1, 3, 1, 0xEC},
- {2, 0, 0, 0, 0xEF},
- {2, 0, 0, 1, 0xEF},
- {2, 0, 1, 0, 0x38},
- {2, 0, 1, 1, 0x39},
- {2, 0, 1, 2, 0x3A},
- {2, 0, 1, 3, 0x39},
- {2, 0, 1, 4, 0xED},
- {2, 0, 1, 5, 0xEC},
- {2, 0, 1, 6, 0xEC},
- {2, 0, 1, 7, 0x39},
- {2, 0, 1, 8, 0xED},
- {2, 0, 2, 2, 0xEC},
- {2, 0, 2, 3, 0xEC},
- {2, 0, 3, 1, 0xEC},
- {2, 0, 3, 2, 0xEC},
- {2, 0, 3, 3, 0xEC},
- {3, 0, 7, 0, 0x84},
- {3, 0, 0xB, 0, 0x84},
- {4, 0, 0, 1, 0xED},
- {4, 0, 0, 2, 0xEF},
- {4, 0, 0, 3, 0xED},
- {4, 0, 1, 1, 0x39},
- {4, 0, 1, 2, 0x3A},
- {4, 0, 1, 3, 0xEF},
- {4, 0, 1, 4, 0x39},
- {4, 0, 1, 5, 0x3A},
- {5, 'x', 'x', 'x', 0x84},
- {'x', 'x', 'x', 'x', 0x02}
- };
-
-CONST PROC_FAMILY_TABLE ROMDATA ProcFamily10DmiTable =
-{
-// This table is for Processor family 10h
- AMD_FAMILY_10, // ID for Family 10h
- DmiF10GetInfo, // Transfer vectors for family
- DmiF10GetVoltage, // specific routines (above)
- DmiF10GetMaxSpeed,
- DmiF10GetExtClock,
- DmiF10GetMemInfo, // Get memory information
- (sizeof (Family10BrandList) / sizeof (Family10BrandList[0])), // Number of entries in following table
- &Family10BrandList[0]
-};
-
-
-/*---------------------------------------------------------------------------------------
- * L O C A L F U N C T I O N S
- *---------------------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * F10Translate7BitVidTo6Bit
- *
- * translate 7 bit VID to 6 bit VID
- *
- * @param[in, out] MaxVidPtr - Pointer to MaxVid.
- */
-VOID
-STATIC
-F10Translate7BitVidTo6Bit (
- IN OUT UINT8 * MaxVidPtr
- )
-{
- if ((*MaxVidPtr >= 0x5E) && (*MaxVidPtr <= 0x7F)) {
- *MaxVidPtr = 0x3F;
- } else if ((*MaxVidPtr >= 0x3F) && (*MaxVidPtr <= 0x5D)) {
- *MaxVidPtr = *MaxVidPtr - 0x1F;
- } else if (*MaxVidPtr <= 0x3E) {
- *MaxVidPtr = (*MaxVidPtr & 0x7E) >> 1;
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10EarlyInit.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10EarlyInit.c
deleted file mode 100644
index 671af0e..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10EarlyInit.c
+++ /dev/null
@@ -1,424 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 after warm reset sequence
- *
- * Performs the "CPU Core Minimum P-State Transition Sequence After Warm Reset"
- * as described in the BKDG.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/Family/0x10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "cpuF10PowerMgmt.h"
-#include "cpuRegisters.h"
-#include "cpuApicUtilities.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuF10Utilities.h"
-#include "GeneralServices.h"
-#include "cpuServices.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10EARLYINIT_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-/// Enum for handling code branching while transitioning to the
-/// minimum P-state after a warm reset
-typedef enum {
- EXIT_SEQUENCE, ///< Exit the sequence
- STEP7, ///< Go to step 7
- STEP17, ///< Go to step 17
- STEP20 ///< Go to step 20
-} GO_TO_STEP;
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-VOID
-STATIC
-F10PmAfterResetCore (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-STATIC
-WaitForCpuFidAndDidToMatch (
- IN UINT32 PstateNumber,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family 10h core 0 entry point for performing the necessary steps after
- * a warm reset has occurred.
- *
- * The steps are as follows:
- * 1. Modify F3xDC[PstateMaxVal] to reflect the lowest performance P-state
- * supported, as indicated in MSRC001_00[68:64][PstateEn]
- * 2. If MSRC001_0071[CurNbDid] = 0, set MSRC001_001F[GfxNbPstateDis]
- * 3. If MSRC001_0071[CurPstate] != F3xDC[PstateMaxVal], go to step 20
- * 4. If F3xDC[PstateMaxVal] = 0 or F3xDC[PstateMaxVal] != 4, go to step 7
- * 5. If MSRC001_0061[CurPstateLimit] <= F3xDC[PstateMaxVal]-1, go to step 17
- * 6. Exit the sequence
- * 7. Copy the P-state register pointed to by F3xDC[PstateMaxVal] to the P-state
- * register pointed to by F3xDC[PstateMaxVal]+1
- * 8. Write F3xDC[PstateMaxVal]+1 to F3xDC[PstateMaxVal]
- * 9. Write (the new) F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd]
- * 10. Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state
- * register pointed to by (the new) F3xDC[PstateMaxVal]
- * 11. Copy (the new) F3xDC[PstateMaxVal]-1 to MSRC001_0062[PstateCmd]
- * 12. Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state
- * register pointed to by (the new) F3xDC[PstateMaxVal]-1
- * 13. If MSRC001_0071[CurNbDid] = 1, set MSRC001_001F[GfxNbPstateDis]
- * 14. If required, transition the NB COF and VID to the NbDid and NbVid from the
- * P-state register pointed to by MSRC001_0061[CurPstateLimit] using the NB COF
- * and VID transition sequence after a warm reset
- * 15. Write MSRC001_00[68:64][PstateEn]=0 for the P-state pointed to by F3xDC[PstateMaxVal]
- * 16. Write (the new) F3xDC[PstateMaxVal]-1 to F3xDC[PstateMaxVal] and exit the sequence
- * 17. Copy F3xDC[PstateMaxVal]-1 to MSRC001_0062[PstateCmd]
- * 18. Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state
- * register pointed to by F3xDC[PstateMaxVal]-1
- * 19. If MSRC001_0071[CurNbDid] = 0, set MSRC001_001F[GfxNbPstateDis]
- * 20. Copy F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd]
- * 21. Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state
- * register pointed to by F3xDC[PstateMaxVal]
- * 22. If MSRC001_0071[CurNbDid] = 1, set MSRC001_001F[GfxNbPstateDis]
- * 23. Issue an LDTSTOP assertion in the IO hub and exit sequence
- * 24. If required, transition the NB COF and VID to the NbDid and NbVid from the
- * P-state register pointed to by F3xDC[PstateMaxVal] using the NB COF and VID
- * transition sequence after a warm reset
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] CpuEarlyParamsPtr Service parameters
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-F10PmAfterReset (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Socket;
- UINT32 Module;
- UINT32 PsMaxVal;
- UINT32 CoreNum;
- UINT32 MsrAddr;
- UINT32 Core;
- UINT32 AndMask;
- UINT32 OrMask;
- UINT64 MsrRegister;
- PCI_ADDR PciAddress;
- AP_TASK TaskPtr;
- AGESA_STATUS IgnoredSts;
-
- IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
- GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
- GetActiveCoresInCurrentSocket (&CoreNum, StdHeader);
-
- ASSERT (Core == 0);
-
- // Step 1 Modify F3xDC[PstateMaxVal] to reflect the lowest performance
- // P-state supported, as indicated in MSRC001_00[68:64][PstateEn]
- for (MsrAddr = PS_MAX_REG; MsrAddr > PS_REG_BASE; --MsrAddr) {
- LibAmdMsrRead (MsrAddr, &MsrRegister, StdHeader);
- if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
- break;
- }
- }
- PsMaxVal = MsrAddr - PS_REG_BASE;
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = CPTC2_REG;
- AndMask = 0xFFFFFFFF;
- OrMask = 0x00000000;
- ((CLK_PWR_TIMING_CTRL2_REGISTER *) &AndMask)->PstateMaxVal = 0;
- ((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->PstateMaxVal = PsMaxVal;
- ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
-
- // Launch each local core to perform the remaining steps.
- TaskPtr.FuncAddress.PfApTask = F10PmAfterResetCore;
- TaskPtr.DataTransfer.DataSizeInDwords = 0;
- TaskPtr.ExeFlags = WAIT_FOR_CORE;
- ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
-}
-
-
-/*---------------------------------------------------------------------------------------
- * L O C A L F U N C T I O N S
- *---------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Support routine for F10PmAfterReset to perform MSR initialization on all
- * cores of a family 10h socket.
- *
- * This function implements steps 2 - 24 on each core.
- *
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-STATIC
-F10PmAfterResetCore (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Socket;
- UINT32 Module;
- UINT32 Ignored;
- UINT32 PsMaxVal;
- UINT32 PciRegister;
- UINT64 MsrRegister;
- UINT64 SavedMsr;
- UINT64 CurrentLimitMsr;
- PCI_ADDR PciAddress;
- GO_TO_STEP GoToStep;
- AGESA_STATUS IgnoredSts;
- CPU_LOGICAL_ID LogicalId;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
-
- // Step 2 If MSR C001_0071[CurNbDid] = 0, set MSR C001_001F[GfxNbPstateDis]
- GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
- GetCpuServicesFromLogicalId (&LogicalId, &FamilySpecificServices, StdHeader);
- if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) {
- LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
- if (((COFVID_STS_MSR *) &MsrRegister)->CurNbDid == 0) {
- LibAmdMsrRead (NB_CFG, &MsrRegister, StdHeader);
- MsrRegister |= BIT62;
- LibAmdMsrWrite (NB_CFG, &MsrRegister, StdHeader);
- }
- }
-
- GoToStep = EXIT_SEQUENCE;
-
- LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &CurrentLimitMsr, StdHeader);
- PsMaxVal = (UINT32) (((PSTATE_CURLIM_MSR *) &CurrentLimitMsr)->PstateMaxVal);
-
- // Step 3 If MSRC001_0071[CurPstate] != F3xDC[PstateMaxVal], go to step 20
- LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
- if (((COFVID_STS_MSR *) &MsrRegister)->CurPstate !=
- ((PSTATE_CURLIM_MSR *) &CurrentLimitMsr)->PstateMaxVal) {
- GoToStep = STEP20;
- } else {
- // Step 4 If F3xDC[PstateMaxVal] = 0 || F3xDC[PstateMaxVal] != 4, go to step 7
- if ((PsMaxVal == 0) || (PsMaxVal != 4)) {
- GoToStep = STEP7;
- } else {
- // Step 5 If MSRC001_0061[CurPstateLimit] <= F3xDC[PstateMaxVal]-1, go to step 17
- if (((PSTATE_CURLIM_MSR *) &CurrentLimitMsr)->CurPstateLimit <=
- (((PSTATE_CURLIM_MSR *) &CurrentLimitMsr)->PstateMaxVal - 1)) {
- GoToStep = STEP17;
- }
- }
- }
- switch (GoToStep) {
- default:
- case EXIT_SEQUENCE:
- // Step 6 Exit the sequence
- break;
- case STEP7:
- // Workaround for S3 ----Save the value of [The PState[4:0] Registers] MSRC001_00[68:64]
- // pointed to by F3xDC[PstateMaxVal] + 1
- LibAmdMsrRead ((MSR_PSTATE_0 + (PsMaxVal + 1)), &SavedMsr, StdHeader);
-
- // Step 7 Copy the P-state register pointed to by F3xDC[PstateMaxVal] to the P-state
- // register pointed to by F3xDC[PstateMaxVal]+1
- LibAmdMsrRead ((MSR_PSTATE_0 + PsMaxVal), &MsrRegister, StdHeader);
- LibAmdMsrWrite ((MSR_PSTATE_0 + (PsMaxVal + 1)), &MsrRegister, StdHeader);
-
- // Step 8 Write F3xDC[PstateMaxVal]+1 to F3xDC[PstateMaxVal]
- IdentifyCore (StdHeader, &Socket, &Module, &Ignored, &IgnoredSts);
- GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = CPTC2_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal = PsMaxVal + 1;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
-
- // Step 9 Write (the new) F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd]
- FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) (PsMaxVal + 1), (BOOLEAN) FALSE, StdHeader);
-
- // Step 10 Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state
- // register pointed to by (the new) F3xDC[PstateMaxVal]
- WaitForCpuFidAndDidToMatch ((UINT32) (PsMaxVal + 1), StdHeader);
-
- // Step 11 Copy (the new) F3xDC[PstateMaxVal]-1 to MSRC001_0062[PstateCmd]
- FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) PsMaxVal, (BOOLEAN) FALSE, StdHeader);
-
- // Step 12 Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state
- // register pointed to by (the new) F3xDC[PstateMaxVal]-1
- WaitForCpuFidAndDidToMatch (PsMaxVal, StdHeader);
-
- // Step 13 If MSRC001_0071[CurNbDid] = 1, set MSRC001_001F[GfxNbPstateDis]
- if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) {
- LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
- if (((COFVID_STS_MSR *) &MsrRegister)->CurNbDid == 1) {
- LibAmdMsrRead (NB_CFG, &MsrRegister, StdHeader);
- MsrRegister |= BIT62;
- LibAmdMsrWrite (NB_CFG, &MsrRegister, StdHeader);
- }
- }
-
- // Step 14 If required, transition the NB COF and VID to the NbDid and NbVid from the
- // P-state register pointed to by MSRC001_0061[CurPstateLimit] using the NB COF
- // and VID transition sequence after a warm reset
-
- // Step 15 Write 0 to PstateEn of the P-state register pointed to by (the new) F3xDC[PstateMaxVal]
- // Workaround for S3----Restore the value of [The PState[4:0] Registers] MSRC001_00[68:64]
- // pointed to by F3xDC[PstateMaxVal] + 1
- ((PSTATE_MSR *) &SavedMsr)->PsEnable = 0;
- LibAmdMsrWrite ((MSR_PSTATE_0 + (PsMaxVal + 1)), &SavedMsr, StdHeader);
-
- // Step 16 Write (the new) F3xDC[PstateMaxVal]-1 to F3xDC[PstateMaxVal]
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal = PsMaxVal;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- break;
- case STEP17:
- // Step 17 Copy F3xDC[PstateMaxVal]-1 to MSRC001_0062[PstateCmd]
- FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) (PsMaxVal - 1), (BOOLEAN) FALSE, StdHeader);
-
- // Step 18 Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state
- // register pointed to by F3xDC[PstateMaxVal]-1
- WaitForCpuFidAndDidToMatch ((UINT32) (PsMaxVal - 1), StdHeader);
-
- // Step 19 If MSR C001_0071[CurNbDid] = 0, set MSR C001_001F[GfxNbPstateDis]
- if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) {
- LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
- if (((COFVID_STS_MSR *) &MsrRegister)->CurNbDid == 0) {
- LibAmdMsrRead (NB_CFG, &MsrRegister, StdHeader);
- MsrRegister |= BIT62;
- LibAmdMsrWrite (NB_CFG, &MsrRegister, StdHeader);
- }
- }
-
- // Fall through from step 19 to step 20
- case STEP20:
- // Step 20 Copy F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd]
- FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) PsMaxVal, (BOOLEAN) FALSE, StdHeader);
-
- // Step 21 Wait for MSRC001_0071[CurCpuFid/CurCpuDid] = CpuFid/CpuDid from the P-state
- // register pointed to by F3xDC[PstateMaxVal]
- WaitForCpuFidAndDidToMatch (PsMaxVal, StdHeader);
-
- // Step 22 If MSR C001_0071[CurNbDid] = 1, set MSR C001_001F[GfxNbPstateDis] and exit
- // the sequence
- if ((LogicalId.Revision & (AMD_F10_C3 | AMD_F10_DA_C2)) != 0) {
- LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
- if (((COFVID_STS_MSR *) &MsrRegister)->CurNbDid == 1) {
- LibAmdMsrRead (NB_CFG, &MsrRegister, StdHeader);
- MsrRegister |= BIT62;
- LibAmdMsrWrite (NB_CFG, &MsrRegister, StdHeader);
- break;
- }
- }
-
- // Step 23 Issue an LDTSTOP and exit the sequence
-
- // Step 24 If required, transition the NB COF and VID to the NbDid and NbVid from the
- // P-state register pointed to by F3xDC[PstateMaxVal] using the NB COF and VID
- // transition sequence after a warm reset
- break;
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Support routine for F10PmAfterResetCore to wait for Cpu FID and DID to
- * match a specific P-state.
- *
- * This function implements steps 11, 13, 18, and 20 on each core as needed.
- *
- * @param[in] PstateNumber P-state settings to match
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-STATIC
-WaitForCpuFidAndDidToMatch (
- IN UINT32 PstateNumber,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 TargetPsMsr;
- UINT64 CurrentStatus;
- UINT32 PciRegister;
- PCI_ADDR PciAddress;
- CPUID_DATA CpuidData;
-
- // Check if CPB is supported. if yes, skip boosted p-state. The boosted p-state number = F4x15C[NumBoostStates].
- LibAmdCpuidRead (AMD_CPUID_APM, &CpuidData, StdHeader);
- if (((CpuidData.EDX_Reg & 0x00000200) >> 9) == 1) {
- PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // F4x15C
- PstateNumber += (UINT32) (((CPB_CTRL_REGISTER *) &PciRegister)->NumBoostStates);
- }
-
- // Get target P-state settings
- LibAmdMsrRead ((MSR_PSTATE_0 + PstateNumber), &TargetPsMsr, StdHeader);
-
- // Wait for current CPU FID/DID to match target FID/DID
- do {
- LibAmdMsrRead (MSR_COFVID_STS, &CurrentStatus, StdHeader);
- } while ((((COFVID_STS_MSR *) &CurrentStatus)->CurCpuFid != ((PSTATE_MSR *) &TargetPsMsr)->CpuFid) ||
- (((COFVID_STS_MSR *) &CurrentStatus)->CurCpuDid != ((PSTATE_MSR *) &TargetPsMsr)->CpuDid));
-}
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10EarlyInit.h b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10EarlyInit.h
deleted file mode 100644
index bf78e45..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10EarlyInit.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Early Init related functions Prototypes.
- *
- * Contains code that provide power management functionality
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F10
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPU_F10_EARLY_INIT_H_
-#define _CPU_F10_EARLY_INIT_H_
-
-
-/*---------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *---------------------------------------------------------------------------------------
- */
-VOID
-F10PmAfterReset (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif // _CPU_F10_EARLY_INIT_H_
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c
deleted file mode 100644
index a10488c..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c
+++ /dev/null
@@ -1,394 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 specific feature leveling functions.
- *
- * Provides feature leveling functions specific to family 10h.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/Family/0x10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "cpuRegisters.h"
-#include "cpuPostInit.h"
-#include "cpuF10FeatureLeveling.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10FEATURELEVELING_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-cpuFeatureListNeedUpdate (
- IN CPU_FEATURES_LIST *globalCpuFeatureList,
- IN CPU_FEATURES_LIST *thisCoreCpuFeatureList
- );
-
-VOID
-STATIC
-updateCpuFeatureList (
- IN CPU_FEATURES_LIST *globalCpuFeatureList,
- IN CPU_FEATURES_LIST *thisCoreCpuFeatureList
- );
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function get features which CPU supports.
- *
- * @CpuServiceMethod{::F_CPU_SAVE_FEATURES}.
- *
- * Read features from MSR_C0011004 and MSR_C0011005.
- *
- * @param[in] FamilySpecificServices - Pointer to CPU_SPECIFIC_SERVICES struct.
- * @param[in,out] cpuFeatureList - Pointer to CPU_FEATURES_LIST struct.
- * @param[in] StdHeader - Pointer to AMD_CONFIG_PARAMS struct.
- *
- */
-VOID
-F10SaveFeatures (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN OUT CPU_FEATURES_LIST *cpuFeatureList,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 CpuMsrData;
- BOOLEAN *FirstTime;
- BOOLEAN *NeedLeveling;
- CPU_F10_FEATURES *CpuF10Features;
- CPU_F10_EXT_FEATURES *CpuF10ExtFeatures;
- CPU_FEATURES_LIST thisCoreCpuFeatureList;
-
- FirstTime = (BOOLEAN *) ((UINT8 *) cpuFeatureList + sizeof (CPU_FEATURES_LIST));
- NeedLeveling = (BOOLEAN *) ((UINT8 *) cpuFeatureList + sizeof (CPU_FEATURES_LIST) + sizeof (BOOLEAN));
-
- LibAmdMemFill (&thisCoreCpuFeatureList, 0x0, sizeof (CPU_FEATURES_LIST), StdHeader);
- LibAmdMsrRead (MSR_CPUID_FEATS, &CpuMsrData, StdHeader);
- CpuF10Features = (CPU_F10_FEATURES *) &CpuMsrData;
-
- thisCoreCpuFeatureList.APIC = (UINT8) CpuF10Features->CpuF10FeaturesLo.APIC;
- thisCoreCpuFeatureList.CLFSH = (UINT8) CpuF10Features->CpuF10FeaturesLo.CLFSH;
- thisCoreCpuFeatureList.CMOV = (UINT8) CpuF10Features->CpuF10FeaturesLo.CMOV;
- thisCoreCpuFeatureList.CMPXCHG8B = (UINT8) CpuF10Features->CpuF10FeaturesLo.CMPXCHG8B;
- thisCoreCpuFeatureList.DE = (UINT8) CpuF10Features->CpuF10FeaturesLo.DE;
- thisCoreCpuFeatureList.FPU = (UINT8) CpuF10Features->CpuF10FeaturesLo.FPU;
- thisCoreCpuFeatureList.FXSR = (UINT8) CpuF10Features->CpuF10FeaturesLo.FXSR;
- thisCoreCpuFeatureList.HTT = (UINT8) CpuF10Features->CpuF10FeaturesLo.HTT;
- thisCoreCpuFeatureList.MCA = (UINT8) CpuF10Features->CpuF10FeaturesLo.MCA;
- thisCoreCpuFeatureList.MCE = (UINT8) CpuF10Features->CpuF10FeaturesLo.MCE;
- thisCoreCpuFeatureList.MMX = (UINT8) CpuF10Features->CpuF10FeaturesLo.MMX;
- thisCoreCpuFeatureList.MSR = (UINT8) CpuF10Features->CpuF10FeaturesLo.MSR;
- thisCoreCpuFeatureList.MTRR = (UINT8) CpuF10Features->CpuF10FeaturesLo.MTRR;
- thisCoreCpuFeatureList.PAE = (UINT8) CpuF10Features->CpuF10FeaturesLo.PAE;
- thisCoreCpuFeatureList.PAT = (UINT8) CpuF10Features->CpuF10FeaturesLo.PAT;
- thisCoreCpuFeatureList.PGE = (UINT8) CpuF10Features->CpuF10FeaturesLo.PGE;
- thisCoreCpuFeatureList.PSE = (UINT8) CpuF10Features->CpuF10FeaturesLo.PSE;
- thisCoreCpuFeatureList.PSE36 = (UINT8) CpuF10Features->CpuF10FeaturesLo.PSE36;
- thisCoreCpuFeatureList.SSE = (UINT8) CpuF10Features->CpuF10FeaturesLo.SSE;
- thisCoreCpuFeatureList.SSE2 = (UINT8) CpuF10Features->CpuF10FeaturesLo.SSE2;
- thisCoreCpuFeatureList.SysEnterSysExit = (UINT8) CpuF10Features->CpuF10FeaturesLo.SysEnterSysExit;
- thisCoreCpuFeatureList.TimeStampCounter = (UINT8) CpuF10Features->CpuF10FeaturesLo.TimeStampCounter;
- thisCoreCpuFeatureList.VME = (UINT8) CpuF10Features->CpuF10FeaturesLo.VME;
-
- thisCoreCpuFeatureList.CMPXCHG16B = (UINT8) CpuF10Features->CpuF10FeaturesHi.CMPXCHG16B;
- thisCoreCpuFeatureList.Monitor = (UINT8) CpuF10Features->CpuF10FeaturesHi.Monitor;
- thisCoreCpuFeatureList.POPCNT = (UINT8) CpuF10Features->CpuF10FeaturesHi.POPCNT;
- thisCoreCpuFeatureList.SSE3 = (UINT8) CpuF10Features->CpuF10FeaturesHi.SSE3;
-
- LibAmdMsrRead (MSR_CPUID_EXT_FEATS, &CpuMsrData, StdHeader);
- CpuF10ExtFeatures = (CPU_F10_EXT_FEATURES *) &CpuMsrData;
-
- thisCoreCpuFeatureList.ThreeDNow = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.ThreeDNow;
- thisCoreCpuFeatureList.ThreeDNowExt = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.ThreeDNowExt;
- thisCoreCpuFeatureList.APIC = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.APIC;
- thisCoreCpuFeatureList.CMOV = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.CMOV;
- thisCoreCpuFeatureList.CMPXCHG8B = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.CMPXCHG8B;
- thisCoreCpuFeatureList.DE = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.DE;
- thisCoreCpuFeatureList.FFXSR = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.FFXSR;
- thisCoreCpuFeatureList.FPU = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.FPU;
- thisCoreCpuFeatureList.FXSR = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.FXSR;
- thisCoreCpuFeatureList.LM = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.LM;
- thisCoreCpuFeatureList.MCA = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MCA;
- thisCoreCpuFeatureList.MCE = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MCE;
- thisCoreCpuFeatureList.MMX = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MMX;
- thisCoreCpuFeatureList.MmxExt = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MmxExt;
- thisCoreCpuFeatureList.MSR = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MSR;
- thisCoreCpuFeatureList.MTRR = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MTRR;
- thisCoreCpuFeatureList.NX = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.NX;
- thisCoreCpuFeatureList.PAE = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.PAE;
- thisCoreCpuFeatureList.Page1GB = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.Page1GB;
- thisCoreCpuFeatureList.PAT = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.PAT;
- thisCoreCpuFeatureList.PGE = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.PGE;
- thisCoreCpuFeatureList.PSE = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.PSE;
- thisCoreCpuFeatureList.PSE36 = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.PSE36;
- thisCoreCpuFeatureList.RDTSCP = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.RDTSCP;
- thisCoreCpuFeatureList.SysCallSysRet = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.SysCallSysRet;
- thisCoreCpuFeatureList.TimeStampCounter = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.TimeStampCounter;
- thisCoreCpuFeatureList.VME = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesLo.VME;
-
- thisCoreCpuFeatureList.ThreeDNowPrefetch = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.ThreeDNowPrefetch;
- thisCoreCpuFeatureList.ABM = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.ABM;
- thisCoreCpuFeatureList.AltMovCr8 = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.AltMovCr8;
- thisCoreCpuFeatureList.CmpLegacy = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.CmpLegacy;
- thisCoreCpuFeatureList.ExtApicSpace = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.ExtApicSpace;
- thisCoreCpuFeatureList.IBS = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.IBS;
- thisCoreCpuFeatureList.LahfSahf = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.LahfSahf;
- thisCoreCpuFeatureList.MisAlignSse = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.MisAlignSse;
- thisCoreCpuFeatureList.OSVW = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.OSVM;
- thisCoreCpuFeatureList.SKINIT = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.SKINIT;
- thisCoreCpuFeatureList.SSE4A = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.SSE4A;
- thisCoreCpuFeatureList.SVM = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.SVM;
- thisCoreCpuFeatureList.WDT = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.WDT;
- thisCoreCpuFeatureList.NodeId = (UINT8) CpuF10ExtFeatures->CpuF10ExtFeaturesHi.NodeId;
-
- if (*FirstTime) {
- updateCpuFeatureList (cpuFeatureList, &thisCoreCpuFeatureList);
- *FirstTime = FALSE;
- } else if (cpuFeatureListNeedUpdate (cpuFeatureList, &thisCoreCpuFeatureList)) {
- updateCpuFeatureList (cpuFeatureList, &thisCoreCpuFeatureList);
- *NeedLeveling = TRUE;
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function set features which All CPUs support.
- *
- * @CpuServiceMethod{::F_CPU_WRITE_FEATURES}.
- *
- * Write least common features to MSR_C0011004 and MSR_C0011005.
- *
- * @param[in] FamilySpecificServices - Pointer to CPU_SPECIFIC_SERVICES struct.
- * @param[in,out] cpuFeatureList - Pointer to CPU_FEATURES_LIST struct.
- * @param[in] StdHeader - Pointer to AMD_CONFIG_PARAMS struct.
- *
- */
-VOID
-F10WriteFeatures (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN OUT CPU_FEATURES_LIST *cpuFeatureList,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 CpuMsrData;
- CPU_F10_FEATURES *CpuF10Features;
- CPU_F10_EXT_FEATURES *CpuF10ExtFeatures;
-
- CpuMsrData = 0;
- CpuF10Features = (CPU_F10_FEATURES *) &CpuMsrData;
-
- CpuF10Features->CpuF10FeaturesLo.APIC = cpuFeatureList->APIC;
- CpuF10Features->CpuF10FeaturesLo.CLFSH = cpuFeatureList->CLFSH;
- CpuF10Features->CpuF10FeaturesLo.CMOV = cpuFeatureList->CMOV;
- CpuF10Features->CpuF10FeaturesLo.CMPXCHG8B = cpuFeatureList->CMPXCHG8B;
- CpuF10Features->CpuF10FeaturesLo.DE = cpuFeatureList->DE;
- CpuF10Features->CpuF10FeaturesLo.FPU = cpuFeatureList->FPU;
- CpuF10Features->CpuF10FeaturesLo.FXSR = cpuFeatureList->FXSR;
- CpuF10Features->CpuF10FeaturesLo.HTT = cpuFeatureList->HTT;
- CpuF10Features->CpuF10FeaturesLo.MCA = cpuFeatureList->MCA;
- CpuF10Features->CpuF10FeaturesLo.MCE = cpuFeatureList->MCE;
- CpuF10Features->CpuF10FeaturesLo.MMX = cpuFeatureList->MMX;
- CpuF10Features->CpuF10FeaturesLo.MSR = cpuFeatureList->MSR;
- CpuF10Features->CpuF10FeaturesLo.MTRR = cpuFeatureList->MTRR;
- CpuF10Features->CpuF10FeaturesLo.PAE = cpuFeatureList->PAE;
- CpuF10Features->CpuF10FeaturesLo.PAT = cpuFeatureList->PAT;
- CpuF10Features->CpuF10FeaturesLo.PGE = cpuFeatureList->PGE;
- CpuF10Features->CpuF10FeaturesLo.PSE = cpuFeatureList->PSE;
- CpuF10Features->CpuF10FeaturesLo.PSE36 = cpuFeatureList->PSE36;
- CpuF10Features->CpuF10FeaturesLo.SSE = cpuFeatureList->SSE;
- CpuF10Features->CpuF10FeaturesLo.SSE2 = cpuFeatureList->SSE2;
- CpuF10Features->CpuF10FeaturesLo.SysEnterSysExit = cpuFeatureList->SysEnterSysExit;
- CpuF10Features->CpuF10FeaturesLo.TimeStampCounter = cpuFeatureList->TimeStampCounter;
- CpuF10Features->CpuF10FeaturesLo.VME = cpuFeatureList->VME;
-
- CpuF10Features->CpuF10FeaturesHi.CMPXCHG16B = cpuFeatureList->CMPXCHG16B;
- CpuF10Features->CpuF10FeaturesHi.Monitor = cpuFeatureList->Monitor;
- CpuF10Features->CpuF10FeaturesHi.POPCNT = cpuFeatureList->POPCNT;
- CpuF10Features->CpuF10FeaturesHi.SSE3 = cpuFeatureList->SSE3;
-
- LibAmdMsrWrite (MSR_CPUID_FEATS, &CpuMsrData, StdHeader);
-
- CpuMsrData = 0;
- CpuF10ExtFeatures = (CPU_F10_EXT_FEATURES *) &CpuMsrData;
-
- CpuF10ExtFeatures->CpuF10ExtFeaturesLo.ThreeDNow = cpuFeatureList->ThreeDNow;
- CpuF10ExtFeatures->CpuF10ExtFeaturesLo.ThreeDNowExt = cpuFeatureList->ThreeDNowExt;
- CpuF10ExtFeatures->CpuF10ExtFeaturesLo.APIC = cpuFeatureList->APIC;
- CpuF10ExtFeatures->CpuF10ExtFeaturesLo.CMOV = cpuFeatureList->CMOV;
- CpuF10ExtFeatures->CpuF10ExtFeaturesLo.CMPXCHG8B = cpuFeatureList->CMPXCHG8B;
- CpuF10ExtFeatures->CpuF10ExtFeaturesLo.DE = cpuFeatureList->DE;
- CpuF10ExtFeatures->CpuF10ExtFeaturesLo.FFXSR = cpuFeatureList->FFXSR;
- CpuF10ExtFeatures->CpuF10ExtFeaturesLo.FPU = cpuFeatureList->FPU;
- CpuF10ExtFeatures->CpuF10ExtFeaturesLo.FXSR = cpuFeatureList->FXSR;
- CpuF10ExtFeatures->CpuF10ExtFeaturesLo.LM = cpuFeatureList->LM;
- CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MCA = cpuFeatureList->MCA;
- CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MCE = cpuFeatureList->MCE;
- CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MMX = cpuFeatureList->MMX;
- CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MmxExt = cpuFeatureList->MmxExt;
- CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MSR = cpuFeatureList->MSR;
- CpuF10ExtFeatures->CpuF10ExtFeaturesLo.MTRR = cpuFeatureList->MTRR;
- CpuF10ExtFeatures->CpuF10ExtFeaturesLo.NX = cpuFeatureList->NX;
- CpuF10ExtFeatures->CpuF10ExtFeaturesLo.PAE = cpuFeatureList->PAE;
- CpuF10ExtFeatures->CpuF10ExtFeaturesLo.Page1GB = cpuFeatureList->Page1GB;
- CpuF10ExtFeatures->CpuF10ExtFeaturesLo.PAT = cpuFeatureList->PAT;
- CpuF10ExtFeatures->CpuF10ExtFeaturesLo.PGE = cpuFeatureList->PGE;
- CpuF10ExtFeatures->CpuF10ExtFeaturesLo.PSE = cpuFeatureList->PSE;
- CpuF10ExtFeatures->CpuF10ExtFeaturesLo.PSE36 = cpuFeatureList->PSE36;
- CpuF10ExtFeatures->CpuF10ExtFeaturesLo.RDTSCP = cpuFeatureList->RDTSCP;
- CpuF10ExtFeatures->CpuF10ExtFeaturesLo.SysCallSysRet = cpuFeatureList->SysCallSysRet;
- CpuF10ExtFeatures->CpuF10ExtFeaturesLo.TimeStampCounter = cpuFeatureList->TimeStampCounter;
- CpuF10ExtFeatures->CpuF10ExtFeaturesLo.VME = cpuFeatureList->VME;
-
- CpuF10ExtFeatures->CpuF10ExtFeaturesHi.ThreeDNowPrefetch = cpuFeatureList->ThreeDNowPrefetch;
- CpuF10ExtFeatures->CpuF10ExtFeaturesHi.ABM = cpuFeatureList->ABM;
- CpuF10ExtFeatures->CpuF10ExtFeaturesHi.AltMovCr8 = cpuFeatureList->AltMovCr8;
- CpuF10ExtFeatures->CpuF10ExtFeaturesHi.CmpLegacy = cpuFeatureList->CmpLegacy;
- CpuF10ExtFeatures->CpuF10ExtFeaturesHi.ExtApicSpace = cpuFeatureList->ExtApicSpace;
- CpuF10ExtFeatures->CpuF10ExtFeaturesHi.IBS = cpuFeatureList->IBS;
- CpuF10ExtFeatures->CpuF10ExtFeaturesHi.LahfSahf = cpuFeatureList->LahfSahf;
- CpuF10ExtFeatures->CpuF10ExtFeaturesHi.MisAlignSse = cpuFeatureList->MisAlignSse;
- CpuF10ExtFeatures->CpuF10ExtFeaturesHi.OSVM = cpuFeatureList->OSVW;
- CpuF10ExtFeatures->CpuF10ExtFeaturesHi.SKINIT = cpuFeatureList->SKINIT;
- CpuF10ExtFeatures->CpuF10ExtFeaturesHi.SSE4A = cpuFeatureList->SSE4A;
- CpuF10ExtFeatures->CpuF10ExtFeaturesHi.SVM = cpuFeatureList->SVM;
- CpuF10ExtFeatures->CpuF10ExtFeaturesHi.WDT = cpuFeatureList->WDT;
- CpuF10ExtFeatures->CpuF10ExtFeaturesHi.NodeId = cpuFeatureList->NodeId;
- LibAmdMsrWrite (MSR_CPUID_EXT_FEATS, &CpuMsrData, StdHeader);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * cpuFeatureListNeedUpdate
- *
- * Compare global CPU feature list with this core feature list to see if global CPU feature list
- * needs updated.
- *
- * @param[in] globalCpuFeatureList - Pointer to global CPU Feature List.
- * @param[in] thisCoreCpuFeatureList - Pointer to this core CPU Feature List.
- *
- * @retval FALSE globalCpuFeatureList is equal to thisCoreCpuFeatureList
- * @retval True globalCpuFeatureList is NOT equal to thisCoreCpuFeatureList
- */
-BOOLEAN
-STATIC
-cpuFeatureListNeedUpdate (
- IN CPU_FEATURES_LIST *globalCpuFeatureList,
- IN CPU_FEATURES_LIST *thisCoreCpuFeatureList
- )
-{
- BOOLEAN flag;
- UINT8 *global;
- UINT8 *thisCore;
- UINT8 i;
-
- flag = FALSE;
- global = (UINT8 *) globalCpuFeatureList;
- thisCore = (UINT8 *) thisCoreCpuFeatureList;
-
- for (i = 0; i < sizeof (CPU_FEATURES_LIST); i++) {
- if ((*global) != (*thisCore)) {
- flag = TRUE;
- break;
- }
- global++;
- thisCore++;
- }
- return flag;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * updateCpuFeatureList
- *
- * Update global CPU feature list
- *
- * @param[in] globalCpuFeatureList - Pointer to global CPU Feature List.
- * @param[in] thisCoreCpuFeatureList - Pointer to this core CPU Feature List.
- *
- */
-VOID
-STATIC
-updateCpuFeatureList (
- IN CPU_FEATURES_LIST *globalCpuFeatureList,
- IN CPU_FEATURES_LIST *thisCoreCpuFeatureList
- )
-{
- UINT8 *globalFeatureList;
- UINT8 *thisCoreFeatureList;
- UINT32 sizeInByte;
-
- globalFeatureList = (UINT8 *) globalCpuFeatureList;
- thisCoreFeatureList = (UINT8 *) thisCoreCpuFeatureList;
-
- for (sizeInByte = 0; sizeInByte < sizeof (CPU_FEATURES_LIST); sizeInByte++) {
- *globalFeatureList &= *thisCoreFeatureList;
- globalFeatureList++;
- thisCoreFeatureList++;
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.h b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.h
deleted file mode 100644
index b27c3e9..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10FeatureLeveling.h
+++ /dev/null
@@ -1,196 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 specific feature leveling functions.
- *
- * Provides feature leveling functions specific to family 10h.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/Family/0x10
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPU_F10_FEATURE_LEVELING_H_
-#define _CPU_F10_FEATURE_LEVELING_H_
-
-#include "cpuFamilyTranslation.h"
-#include "cpuPostInit.h"
-/*---------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *---------------------------------------------------------------------------------------
- */
-/// F10 CPU Feature Low
-typedef struct {
- UINT32 FPU:1; ///< Bit0
- UINT32 VME:1; ///< Bit1
- UINT32 DE:1; ///< Bit2
- UINT32 PSE:1; ///< Bit3
- UINT32 TimeStampCounter:1; ///< Bit4
- UINT32 MSR:1; ///< Bit5
- UINT32 PAE:1; ///< Bit6
- UINT32 MCE:1; ///< Bit7
- UINT32 CMPXCHG8B:1; ///< Bit8
- UINT32 APIC:1; ///< Bit9
- UINT32 Reserved1:1; ///< Bit10
- UINT32 SysEnterSysExit:1; ///< Bit11
- UINT32 MTRR:1; ///< Bit12
- UINT32 PGE:1; ///< Bit13
- UINT32 MCA:1; ///< Bit14
- UINT32 CMOV:1; ///< Bit15
- UINT32 PAT:1; ///< Bit16
- UINT32 PSE36:1; ///< Bit17
- UINT32 Reserved2:1; ///< Bit18
- UINT32 CLFSH:1; ///< Bit19
- UINT32 Reserved3:3; ///< Bit20~22
- UINT32 MMX:1; ///< Bit23
- UINT32 FXSR:1; ///< Bit24
- UINT32 SSE:1; ///< Bit25
- UINT32 SSE2:1; ///< Bit26
- UINT32 Reserved4:1; ///< Bit27
- UINT32 HTT:1; ///< Bit28
- UINT32 Reserved5:3; ///< Bit29~31
-} CPU_F10_FEATURES_LO;
-
-/// F10 CPU Feature High
-typedef struct {
- UINT32 SSE3:1; ///< Bit0
- UINT32 Reserved1:2; ///< Bit1~2
- UINT32 Monitor:1; ///< Bit3
- UINT32 Reserved2:9; ///< Bit4~12
- UINT32 CMPXCHG16B:1; ///< Bit13
- UINT32 Reserved3:9; ///< Bit14~22
- UINT32 POPCNT:1; ///< Bit23
- UINT32 Reserved4:8; ///< Bit24~31
-} CPU_F10_FEATURES_HI;
-
-/// F10 CPU Feature
-typedef struct {
- CPU_F10_FEATURES_LO CpuF10FeaturesLo; ///< Low
- CPU_F10_FEATURES_HI CpuF10FeaturesHi; ///< High
-} CPU_F10_FEATURES;
-
-/// F10 CPU Extended Feature Low
-typedef struct {
- UINT32 FPU:1; ///< Bit0
- UINT32 VME:1; ///< Bit1
- UINT32 DE:1; ///< Bit2
- UINT32 PSE:1; ///< Bit3
- UINT32 TimeStampCounter:1; ///< Bit4
- UINT32 MSR:1; ///< Bit5
- UINT32 PAE:1; ///< Bit6
- UINT32 MCE:1; ///< Bit7
- UINT32 CMPXCHG8B:1; ///< Bit8
- UINT32 APIC:1; ///< Bit9
- UINT32 Reserved1:1; ///< Bit10
- UINT32 SysCallSysRet:1; ///< Bit11
- UINT32 MTRR:1; ///< Bit12
- UINT32 PGE:1; ///< Bit13
- UINT32 MCA:1; ///< Bit14
- UINT32 CMOV:1; ///< Bit15
- UINT32 PAT:1; ///< Bit16
- UINT32 PSE36:1; ///< Bit17
- UINT32 Reserved2:2; ///< Bit18~19
- UINT32 NX:1; ///< Bit20
- UINT32 Reserved3:1; ///< Bit21
- UINT32 MmxExt:1; ///< Bit22
- UINT32 MMX:1; ///< Bit23
- UINT32 FXSR:1; ///< Bit24
- UINT32 FFXSR:1; ///< Bit25
- UINT32 Page1GB:1; ///< Bit26
- UINT32 RDTSCP:1; ///< Bit27
- UINT32 Reserved4:1; ///< Bit28
- UINT32 LM:1; ///< Bit29
- UINT32 ThreeDNowExt:1; ///< Bit30
- UINT32 ThreeDNow:1; ///< Bit31
-} CPU_F10_EXT_FEATURES_LO;
-
-/// F10 CPU Extended Feature High
-typedef struct {
- UINT32 LahfSahf:1; ///< Bit0
- UINT32 CmpLegacy:1; ///< Bit1
- UINT32 SVM:1; ///< Bit2
- UINT32 ExtApicSpace:1; ///< Bit3
- UINT32 AltMovCr8:1; ///< Bit4
- UINT32 ABM:1; ///< Bit5
- UINT32 SSE4A:1; ///< Bit6
- UINT32 MisAlignSse:1; ///< Bit7
- UINT32 ThreeDNowPrefetch:1; ///< Bit8
- UINT32 OSVM:1; ///< Bit9
- UINT32 IBS:1; ///< Bit10
- UINT32 Reserved1:1; ///< Bit11
- UINT32 SKINIT:1; ///< Bit12
- UINT32 WDT:1; ///< Bit13
- UINT32 Reserved2:5; ///< Bit14~18
- UINT32 NodeId:1; ///< Bit19
- UINT32 Reserved3:12; ///< Bit20~31
-} CPU_F10_EXT_FEATURES_HI;
-
-/// F10 CPU Extended Feature
-typedef struct {
- CPU_F10_EXT_FEATURES_LO CpuF10ExtFeaturesLo; ///< Low
- CPU_F10_EXT_FEATURES_HI CpuF10ExtFeaturesHi; ///< High
-} CPU_F10_EXT_FEATURES;
-/*---------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *---------------------------------------------------------------------------------------
- */
-VOID
-F10SaveFeatures (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN OUT CPU_FEATURES_LIST *cpuFeatureList,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-F10WriteFeatures (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN OUT CPU_FEATURES_LIST *cpuFeatureList,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-#endif // _CPU_F10_FEATURE_LEVELING_H_
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10HtPhyTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10HtPhyTables.c
deleted file mode 100644
index 1ffc91b..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10HtPhyTables.c
+++ /dev/null
@@ -1,752 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 DR PCI tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10HTPHYTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-// HT P C I T a b l e s
-// -------------------------
-STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10HtPhyRegisters[] =
-{
-// 0xCF
-// HT_PHY_HT1_FIFO_PTR_OPT_VALUE
- {
- HtPhyRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- HTPHY_LINKTYPE_SL0_HT1, //
- 0xCF, // Address
- 0x0000006D, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xDF
-// HT_PHY_HT1_FIFO_PTR_OPT_VALUE
- {
- HtPhyRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- HTPHY_LINKTYPE_SL1_HT1, //
- 0xDF, // Address
- 0x0000006D, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xCF
-// Default for HT3, unless overridden below.
- {
- HtPhyRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xCF, // Address
- 0x0000005A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xDF
-// Default for HT3, unless overridden below.
- {
- HtPhyRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xDF, // Address
- 0x0000005A, // regData
- 0x000000FF, // regMask
- }
- },
-// 0xD1
-// [29:22] LfcMax = 20h, [21:14] LfcMin = 10h
- {
- HtPhyRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD1, // Address
- 0x08040000, // regData
- 0x3FFFC000, // regMask
- }
- },
-// 0xC1
-// [29:22] LfcMax = 20h, [21:14] LfcMin = 10h
- {
- HtPhyRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC1, // Address
- 0x08040000, // regData
- 0x3FFFC000, // regMask
- }
- },
-// 0xD1
-// [29:22] LfcMax = 10h, [21:14] LfcMin = 08h
- {
- HtPhyRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- HTPHY_LINKTYPE_SL1_HT1, //
- 0xD1, // Address
- 0x04020000, // regData
- 0x3FFFC000, // regMask
- }
- },
-// 0xC1
-// [29:22] LfcMax = 10h, [21:14] LfcMin = 08h
- {
- HtPhyRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- HTPHY_LINKTYPE_SL0_HT1, //
- 0xC1, // Address
- 0x04020000, // regData
- 0x3FFFC000, // regMask
- }
- },
-//
-// Deemphasis Settings
-//
-
-// HT1: clear any warm reset deemphasis settings.
- {
- HtPhyRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- HTPHY_LINKTYPE_SL0_HT1, //
- 0xC5, // Address
- 0x00000000, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- HtPhyRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- HTPHY_LINKTYPE_SL1_HT1, //
- 0xD5, // Address
- 0x00000000, // regData
- 0xE01F1FDF, // regMask
- }
- },
- {
- HtPhyRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- HTPHY_LINKTYPE_SL0_HT1, //
- 0xC4, // Address
- 0x00000000, // regData
- 0x0000FC00, // regMask
- }
- },
- {
- HtPhyRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- HTPHY_LINKTYPE_SL1_HT1, //
- 0xD4, // Address
- 0x00000000, // regData
- 0x0000FC00, // regMask
- }
- },
-
-//deemphasis level DL1[20:16], DL2[12:8], DP1[4:0] PostCur1En[31] PostCur2En[30] PreCur1En[29] MapPostCur2En[6]
-// No deemphasis 00h 00h 00h 0 0 0 0
-// -3dB postcursor 12h 00h 00h 1 0 0 0
-// -6dB postcursor 1Fh 00h 00h 1 0 0 0
-// -8dB postcursor 1Fh 06h 00h 1 1 0 1
-// -11dB postcursor 1Fh 0Dh 00h 1 1 0 1
-// -11dB postcursor with
-// -8dB precursor 1Fh 06h 07h 1 1 1 1
-
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL_NONE,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0x00000000, // regData
- 0xE01F1F5F, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL_NONE,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0x00000000, // regData
- 0xE01F1F5F, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__3,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0x80120000, // regData
- 0xE01F1F5F, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__3,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0x80120000, // regData
- 0xE01F1F5F, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__6,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0x801F0000, // regData
- 0xE01F1F5F, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__6,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0x801F0000, // regData
- 0xE01F1F5F, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__8,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0xC01F0640, // regData
- 0xE01F1F5F, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__8,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0xC01F0640, // regData
- 0xE01F1F5F, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__11,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0xC01F0D40, // regData
- 0xE01F1F5F, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__11,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0xC01F0D40, // regData
- 0xE01F1F5F, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__11_8,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0xE01F0647, // regData
- 0xE01F1F5F, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DEEMPHASIS_LEVEL__11_8,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0xE01F0647, // regData
- 0xE01F1F5F, // regMask
- }
- },
-
-// Far-device deemphasis setting DCV[15:10]
-// No deemphasis 20h
-// -2dB postcursor 19h
-// -3dB postcursor 17h
-// -5dB postcursor 11h
-// -6dB postcursor 10h
-// -7dB postcursor 0Eh
-// -8dB postcursor 0Dh
-// -9dB postcursor 0Bh
-// -11dB postcursor 09h
-
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DCV_LEVEL_NONE,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC4, // Address
- 0x00008000, // regData
- 0x0000FC00, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DCV_LEVEL_NONE,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD4, // Address
- 0x00008000, // regData
- 0x0000FC00, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DCV_LEVEL__2,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC4, // Address
- 0x00006400, // regData
- 0x0000FC00, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DCV_LEVEL__2,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD4, // Address
- 0x00006400, // regData
- 0x0000FC00, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DCV_LEVEL__3,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC4, // Address
- 0x00005C00, // regData
- 0x0000FC00, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DCV_LEVEL__3,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD4, // Address
- 0x00005C00, // regData
- 0x0000FC00, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DCV_LEVEL__5,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC4, // Address
- 0x00004400, // regData
- 0x0000FC00, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DCV_LEVEL__5,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD4, // Address
- 0x00004400, // regData
- 0x0000FC00, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DCV_LEVEL__6,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC4, // Address
- 0x00004000, // regData
- 0x0000FC00, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DCV_LEVEL__6,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD4, // Address
- 0x00004000, // regData
- 0x0000FC00, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DCV_LEVEL__7,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC4, // Address
- 0x00003800, // regData
- 0x0000FC00, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DCV_LEVEL__7,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD4, // Address
- 0x00003800, // regData
- 0x0000FC00, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DCV_LEVEL__8,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC4, // Address
- 0x00003400, // regData
- 0x0000FC00, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DCV_LEVEL__8,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD4, // Address
- 0x00003400, // regData
- 0x0000FC00, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DCV_LEVEL__9,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC4, // Address
- 0x00002C00, // regData
- 0x0000FC00, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DCV_LEVEL__9,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD4, // Address
- 0x00002C00, // regData
- 0x0000FC00, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DCV_LEVEL__11,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC4, // Address
- 0x00002400, // regData
- 0x0000FC00, // regMask
- }
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- DCV_LEVEL__11,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD4, // Address
- 0x00002400, // regData
- 0x0000FC00, // regMask
- }
- },
-
-};
-
-CONST REGISTER_TABLE ROMDATA F10HtPhyRegisterTable = {
- PrimaryCores,
- (sizeof (F10HtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
- F10HtPhyRegisters,
-};
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10MsrTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10MsrTables.c
deleted file mode 100644
index ce63635..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10MsrTables.c
+++ /dev/null
@@ -1,275 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 DR, MSR tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10MSRTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10MsrRegisters[] =
-{
-// M S R T a b l e s
-// ----------------------
-
-// MSR_TOM2 (0xC001001D)
-// bits[63:0] - TOP_MEM2 = 0
- {
- MsrRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MSR_TOM2, // MSR Address
- 0x0000000000000000, // OR Mask
- 0xFFFFFFFFFFFFFFFF, // NAND Mask
- }
- },
-// MSR_SYS_CFG (0xC0010010)
-// bit[21] = 1
- {
- MsrRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MSR_SYS_CFG, // MSR Address
- (1 << 21), // OR Mask
- (1 << 21), // NAND Mask
- }
- },
-// MSR_HWCR (0xC0010015)
-// Do not set bit[24] = 1, it will be set in AmdInitPost.
-// bit[4] = 1
- {
- MsrRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MSR_HWCR, // MSR Address
- 0x0000000000000010, // OR Mask
- 0x0000000000000010, // NAND Mask
- }
- },
-// MSR_MC4_CTL_MASK (0xC0010048)
-// bit[10] = 1
-// bits[22:19] = 1111b
- {
- MsrRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MSR_MC4_CTL_MASK, // MSR Address
- 0x0000000000780400, // OR Mask
- 0x0000000000780400, // NAND Mask
- }
- },
-// MSR_DC_CFG (0xC0011022)
-// bits[35:34] = 01
- {
- MsrRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_MULTI_LINK, // platformFeatures
- {
- MSR_DC_CFG, // MSR Address
- 0x0000000400000000, // OR Mask
- 0x0000000C00000000, // NAND Mask
- }
- },
-// MSR_NB_CFG (0xC001001F)
-// bit[54] = 1
-// bit[52:51] = 11b for Erratum #372
- {
- MsrRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MSR_NB_CFG, // MSR Address
- 0x0058000000000000, // OR Mask
- 0x0058000000000000, // NAND Mask
- }
- },
-// MSR_DC_CFG (0xC0011022)
-// bit[24] = 1
- {
- MsrRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MSR_DC_CFG, // MSR Address
- (1 << 24), // OR Mask
- (1 << 24), // NAND Mask
- }
- },
-// MSR_CPUID_FEATS (0xC0011004)
-// bit[28] = 1
- {
- MsrRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_MULTI_CORE | AMD_PF_DUAL_CORE), // platformFeatures
- {
- MSR_CPUID_FEATS, // MSR Address
- (1 << 28), // OR Mask
- (1 << 28), // NAND Mask
- }
- },
-// MSR_CPUID_EXT_FEATS (0xC0011005)
-// bit[33] = 1
- {
- MsrRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_DUAL_CORE, // platformFeatures
- {
- MSR_CPUID_EXT_FEATS, // MSR Address
- 0x0000000200000000, // OR Mask
- 0x0000000200000000, // NAND Mask
- }
- },
-// MSR_OSVW_ID_Length (0xC0010140)
-// bit[15:0] = 4
- {
- MsrRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MSR_OSVW_ID_Length, // MSR Address
- 0x0000000000000004, // OR Mask
- 0x000000000000FFFF, // NAND Mask
- }
- },
-// MSR_OSVW_Status (0xC0010141)
-// bit[3] = 1 for Erratum #383
-// bit[2] = 1 for Erratum #415
- {
- MsrRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MSR_OSVW_Status, // MSR Address
- 0x000000000000000C, // OR Mask
- 0x000000000000000C, // NAND Mask
- }
- },
-// This MSR should be set after the code that most errata would be applied in
-// MSR_MC0_CTL (0x00000400)
-// bits[63:0] = 0xFFFFFFFFFFFFFFFF
- {
- MsrRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MSR_MC0_CTL, // MSR Address
- 0xFFFFFFFFFFFFFFFF, // OR Mask
- 0xFFFFFFFFFFFFFFFF, // NAND Mask
- }
- }
-};
-
-CONST REGISTER_TABLE ROMDATA F10MsrRegisterTable = {
- AllCores,
- (sizeof (F10MsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
- (TABLE_ENTRY_FIELDS *)F10MsrRegisters,
-};
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10PciTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10PciTables.c
deleted file mode 100644
index 3f4e237..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10PciTables.c
+++ /dev/null
@@ -1,773 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 DR PCI tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10PCITABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-// P C I T a b l e s
-// ----------------------
-
-STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10PciRegisters[] =
-{
-// Function 0 - HT Config
-
-// F0x68 - Link Transaction Control
-// bit[11] , RespPassPW = 1
-// bit[19:17], for 8bit APIC config
-// bit[22:21], DsNpReqLmt = 10h
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68), // Address
- 0x004E0800, // regData
- 0x006E0800, // regMask
- }
- },
-// F0x68 - Link Transaction Control
-// For uni-processor systems (that is, single link package processors), single core, and no L3:
-// [10, DisFillP] = 1b
-// [3, DisWrDwP] = 1b
-// [2, DisWrBP] = 1b
-// [1, DisRdDwP] = 1b
-// [0, DisRdBP] = 1b
- {
- ProfileFixup,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_AND | AMD_PF_SINGLE_CORE | AMD_PF_SINGLE_LINK), // platformFeatures
- {
- PERFORMANCE_NO_L3_CACHE,
- MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68), // Address
- 0x0000040F, // regData
- 0x0000040F, // regMask
- }
- },
-// F0x[E4,C4,A4,84] - Link 0 Control Register
-// bit[13] LdtStopTriEn = 1
- {
- HtHostPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- HT_HOST_FEATURES_ALL, // link feats
- 0x04, // Address
- 0x00002000, // regData
- 0x00002000, // regMask
- }
- },
-// F0x[E4,C4,A4,84] - Link 0 Control Register
-// bit [12] IsocEn = 0 default
- {
- HtHostPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_NFCM | AMD_PF_UMA),
- {
- HT_HOST_FEATURES_ALL, // link feats
- 0x04, // Address
- 0x00000000, // regData
- 0x00001000, // regMask
- }
- },
-// F0x[E4,C4,A4,84] - Link 0 Control Register
-// bit [12] IsocEn = 1 for Isochronous control flow modes.
- {
- HtHostPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- (AMD_PF_UMA_IFCM | AMD_PF_IFCM | AMD_PF_IOMMU),
- {
- HT_HOST_FEATURES_ALL, // link feats
- 0x04, // Address
- 0x00001000, // regData
- 0x00001000, // regMask
- }
- },
-// F0x[F0,D0,B0,90] - Link Base Channel Buffer Count
-// bit[31] LockBc = 1
- {
- HtHostPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- HT_HOST_FEATURES_ALL, // link feats
- 0x10, // Address
- 0x80000000, // regData
- 0x80000000, // regMask
- }
- },
-// F0x150 - Link Global Retry Control Register
-// bit[18:16] TotalRetryAttempts = 7
-// bit[13] HtRetryCrcDatInsDynEn = 1
-// bit[12]HtRetryCrcCmdPackDynEn = 1
-// bit[11:9] HtRetryCrcDatIns = 4
-// bit[8] HtRetryCrcCmdPack = 1
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_0, 0x150), // Address
- 0x00073900, // regData
- 0x00073F00, // regMask
- }
- },
-// F0x16C - Link Global Extended Control Register
-// bit[15:13] ForceFullT0 = 0
-// bit[5:0] T0Time = 0x14
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
- 0x00000014, // regData
- 0x0000E03F, // regMask
- }
- },
-// F0x16C - Link Global Extended Control Register
-// bit[15:13] ForceFullT0 = 6
-// bit[5:0] T0Time = 0x26
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_SINGLE_LINK, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
- 0x0000C026, // regData
- 0x0000E03F, // regMask
- }
- },
-// F0x16C - Link Global Extended Control Register
-// bit[22:17] FullT0Time = 0x33
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C3 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
- 0x00660000, // regData
- 0x007E0000, // regMask
- }
- },
-
-// Function 1 - Map Init
-
-// Before reading F1x114_x2 or F1x114_x3 software must initialize
-// the registers or NB Array MCA errors may occur. BIOS should
-// initialize index 0h of F1x114_x2 and F1x114_x3 to prevent reads
-// from F1x114 from generating NB Array MCA errors.
-// BKDG Doc #3116 Rev 1.07
-
-// F1x110 - Extended Address Map
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_1, 0x110), // Address
- 0x20000000, // regData
- 0xFFFFFFFF, // regMask
- }
- },
-// F1x114 - Extended Address Map
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_1, 0x114), // Address
- 0x00000000, // regData
- 0xFFFFFFFF, // regMask
- }
- },
-// F1x110 - Extended Address Map
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_1, 0x110), // Address
- 0x30000000, // regData
- 0xFFFFFFFF, // regMask
- }
- },
-// F1x114 - Extended Address Map
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_1, 0x114), // Address
- 0x00000000, // regData
- 0xFFFFFFFF, // regMask
- }
- },
-
-// F2x1B0 - Extended Memory Controller Configuration Low
-// bits[10:8], CohPrefPrbLmt = 1
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_2, 0x1B0), // Address
- 0x00000100, // regData
- 0x00000700, // regMask
- }
- },
-
-// Function 3 - Misc. Control
-// F3x40 - MCA NB Control
-//
-// bit[8], MstrAbrtEn = 1
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x40), // Address
- 0x00000100, // regData
- 0x00000100, // regMask
- }
- },
-// F3x44 - MCA NB Configuration
-// bit[30] SyncOnDramAdrParErrEn = 1
-// bit[27] NB MCA to CPU0 Enable = 1
-// bit[25] DisPciCfgCpuErrRsp = 1
-// bit[21] SyncOnErr = 1
-// bit[20] SyncOnWDTEn = 1
-// bit[6] CpuErrDis = 1
-// bit[4] SyncPktPropDis = 1
-// bit[3] SyncPktGenDis = 1
-// bit[2] SyncOnUcEccEn = 1
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x44), // Address
- 0x4A30005C, // regData
- 0x4A30005C, // regMask
- }
- },
-// F3x80 - ACPI Power State Control
-// ACPI FIDVID Change
-// bits[0] CpuPrbEn = 0
-// bits[1] NbLowPwrEn = 0
-// bits[2] NbGateEn = 0
-// bits[3] NbCofChg = 0
-// bits[4] AltVidEn = 0
-// bits[7:5] ClkDivisor = 0
-// ACPI State S1
-// bits[0] CpuPrbEn = 0
-// bits[1] NbLowPwrEn = 1
-// bits[2] NbGateEn = 1
-// bits[3] NbCofChg = 0
-// bits[4] AltVidEn = 0
-// bits[7:5] ClkDivisor = 7
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address
- 0xE6000000, // regData
- 0xFFFF0000, // regMask
- }
- },
-// F3x80 - ACPI Power State Control
-// ACPI FIDVID Change
-// bits[0] CpuPrbEn = 1
-// bits[1] NbLowPwrEn = 1
-// bits[2] NbGateEn = 0
-// bits[3] NbCofChg = 1
-// bits[4] AltVidEn = 0
-// bits[7:5] ClkDivisor = 0
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C3 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address
- 0x000B0000, // regData
- 0x00FF0000, // regMask
- }
- },
-// F3x84 - ACPI Power State Control
-// ACPI State S3
-// bits[0] CpuPrbEn = 0
-// bits[1] NbLowPwrEn = 1
-// bits[2] NbGateEn = 1
-// bits[3] NbCofChg = 0
-// bits[4] AltVidEn = 0
-// bits[7:5] ClkDivisor = 7
-// ACPI State Throttling
-// bits[0] CpuPrbEn = 1
-// bits[1] NbLowPwrEn = 0
-// bits[2] NbGateEn = 0
-// bits[3] NbCofChg = 0
-// bits[4] AltVidEn = 0
-// bits[7:5] ClkDivisor = 2
-// ACPI State S4/S5
-// bits[0] CpuPrbEn = 0
-// bits[1] NbLowPwrEn = 1
-// bits[2] NbGateEn = 1
-// bits[3] NbCofChg = 0
-// bits[4] AltVidEn = 0
-// bits[7:5] ClkDivisor = 7
-// ACPI State C1
-// bits[0] CpuPrbEn = 0
-// bits[1] NbLowPwrEn = 0
-// bits[2] NbGateEn = 0
-// bits[3] NbCofChg = 0
-// bits[4] AltVidEn = 0
-// bits[7:5] ClkDivisor = 5
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x84), // Address
- 0x01E641E6, // regData
- 0xFFFFFFFF, // regMask
- }
- },
-// F3x84 - ACPI Power State Control
-// ACPI State C1
-// bits[0] CpuPrbEn = 0
-// bits[1] NbLowPwrEn = 0
-// bits[2] NbGateEn = 0
-// bits[3] NbCofChg = 0
-// bits[4] AltVidEn = 0
-// bits[7:5] ClkDivisor = 4
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C2 // CpuRevision
- },
- AMD_PF_SINGLE_CORE, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x84), // Address
- 0x80000000, // regData
- 0xFF000000, // regMask
- }
- },
-// F3x8C - NB Configuration High
-// Errata 373, bits[25] DisFastTprWr = 1
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x8C), // Address
- 0x02000000, // regData
- 0x02000000, // regMask
- }
- },
-// F3x8C - NB Configuration High
-// Clear errata 373, bits[25] DisFastTprWr = 0
- {
- ProfileFixup,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platform Features
- {
- PERFORMANCE_L3_CACHE, // Features
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x8C), // Address
- 0x00000000, // regData
- 0x02000000, // regMask
- }
- },
-// F3xA0 - Power Control Miscellaneous
-// bits[13:11] PllLockTime = 1
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_GT_C0 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0), // Address
- 0x00000800, // regData
- 0x00003800, // regMask
- }
- },
-// F3xA0 - Power Control Miscellaneous
-// bits[9] SviHighFreqSel = 1, if PERFORMANCE_VRM_HIGH_SPEED_ENABLE == TRUE
- {
- ProfileFixup,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C3 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- PERFORMANCE_VRM_HIGH_SPEED_ENABLE, // PerformanceFeatures
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0), // Address
- 0x00000200, // regData
- 0x00000200, // regMask
- }
- },
-// F3xA4 - Reported Temperature Control
-// bits[12:8] PerStepTimeDn = 15
-// bits[7] TmpSlewDnEn = 1
-// bits[6:5] TmpMaxDiffUp = 3
-// bits[4:0] PerStepTimeUp = 15
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA4), // Address
- 0x00000FEF, // regData
- 0x00001FFF, // regMask
- }
- },
-// F3xD4 - Clock Power Timing Control 0
-// bits[11:8] ClkRampHystSel = 1
-// bits[30:28] NbClkDiv = 1
-// bits[31] NbClkDivApplyAll = 1
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD4), // Address
- 0xC0010F00, // regData
- 0xF0030F00, // regMask
- }
- },
-// F3xD8 - Clock Power Timing Control 1
-// bits[2:0] VSSlamTime = 6
-// bits[6:4] VSRampTime = 1
-// bits[26:24] ReConDel = 3
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD8), // Address
- 0x03000016, // regData
- 0x0F000077, // regMask
- }
- },
-// F3xDC - Clock Power Timing Control 2
-// bits[14:12] NbsynPtrAdj = 6
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC), // Address
- 0x00006000, // regData
- 0x00007000, // regMask
- }
- },
-// F3xDC - Clock Power Timing Control 2
-// bits[18:16] CacheFlushOnHaltCtl = 0 to ensure AP cache stability at Early
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_GT_Bx // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC), // Address
- 0x00000000, // regData
- 0x00070000, // regMask
- }
- },
-// F3x180 - NB Extended Configuration
-// bits[1] SyncFloodOnUsPwDataErr = 1
-// bits[5] DisPciCfgCpuMstAbtRsp = 1
-// bits[6] SyncFloodOnDatErr = 1
-// bits[7] SyncFloodOnTgtAbtErr = 1
-// bits[8] SyncOnProtEn = 1
-// bits[9] SyncOnUncNbAryEn = 1
-// bits[20] SyncFloodOnL3LeakErr = 1
-// bits[21] SyncFloodOnCpuLeakErr = 1
-// bits[22] SyncFloodOnTblWalkErr = 1
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x180), // Address
- 0x007003E2, // regData
- 0x007003E2, // regMask
- }
- },
-// F3x188 - NB Extended Configuration Low Register
-// bits[4] EnStpGntOnFlushMaskWakeup = 1
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C3 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address
- 0x00000010, // regData
- 0x00000010, // regMask
- }
- },
-// F3x1A0 - L3 Buffer Count Register
-// bits[14:12] L3ToSriReqCBC = 4, 4 or fewer cores with L3 cache is 4.
- {
- CoreCountsPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- PERFORMANCE_L3_CACHE,
- (CORE_RANGE_0 (COUNT_RANGE_LOW, 4) | COUNT_RANGE_NONE), // 4 or fewer cores.
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1A0), // Address
- 0x00004000, // regData
- 0x00007000, // regMask
- }
- },
-// F3x1A0 - L3 Buffer Count Register
-// bits[14:12] L3ToSriReqCBC = 5, 5-core with L3 cache is 5.
- {
- CoreCountsPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- PERFORMANCE_L3_CACHE,
- (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE), // 5 core.
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1A0), // Address
- 0x00005000, // regData
- 0x00007000, // regMask
- }
- },
-// F3x1A0 - L3 Buffer Count Register
-// bits[14:12] L3ToSriReqCBC = 6, 6-core with L3 cache is 6.
- {
- CoreCountsPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- PERFORMANCE_L3_CACHE,
- (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE), // 6 core.
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1A0), // Address
- 0x00006000, // regData
- 0x00007000, // regMask
- }
- },
-// F3x1B8 - L3 Control
-// bits[12] L3PrivReplEn = 1
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1B8), // Address
- 0x00001000, // regData
- 0x00001000, // regMask
- }
- },
- // F4x1C4 - L3 Power Control Register
- // bits[8] L3PwrSavEn = 1
- {
- ProfileFixup,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- PERFORMANCE_L3_CACHE, // Features
- MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1C4), // Address
- 0x00000100, // regData
- 0x00000100, // regMask
- }
- },
-// F3x1CC - IBS Control
-// bits[8] LvtOffsetVal = 1
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_GT_A2 // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1CC), // Address
- 0x00000100, // regData
- 0x00000100, // regMask
- }
- }
-};
-
-CONST REGISTER_TABLE ROMDATA F10PciRegisterTable = {
- PrimaryCores,
- (sizeof (F10PciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
- F10PciRegisters,
-};
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10PowerCheck.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10PowerCheck.c
deleted file mode 100644
index 031a9a4..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10PowerCheck.c
+++ /dev/null
@@ -1,421 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 P-State power check
- *
- * Performs the "Processor-Systemboard Power Delivery Compatibility Check" as
- * described in the BKDG.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "cpuF10PowerMgmt.h"
-#include "cpuRegisters.h"
-#include "cpuApicUtilities.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuF10PowerCheck.h"
-#include "cpuServices.h"
-#include "GeneralServices.h"
-#include "cpuF10Utilities.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10POWERCHECK_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-VOID
-STATIC
-F10PmPwrCheckCore (
- IN VOID *ErrorData,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-STATIC
-F10PmPwrChkCopyPstate (
- IN UINT8 Dest,
- IN UINT8 Src,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family 10h core 0 entry point for performing the family 10h Processor-
- * Systemboard Power Delivery Check.
- *
- * The steps are as follows:
- * 1. Starting with P0, loop through all P-states until a passing state is
- * found. A passing state is one in which the current required by the
- * CPU is less than the maximum amount of current that the system can
- * provide to the CPU. If P0 is under the limit, no further action is
- * necessary.
- * 2. If at least one P-State is under the limit & at least one P-State is
- * over the limit, the BIOS must:
- * a. If the processor's current P-State is disabled by the power check,
- * then the BIOS must request a transition to an enabled P-state
- * using MSRC001_0062[PstateCmd] and wait for MSRC001_0063[CurPstate]
- * to reflect the new value.
- * b. Copy the contents of the enabled P-state MSRs to the highest
- * performance P-state locations.
- * c. Request a P-state transition to the P-state MSR containing the
- * COF/VID values currently applied.
- * d. On revision E systems with CPUID Fn8000_0007[CPB]=1, if P0 is disabled then
- * program F4x15C[BoostSrc]=0. This step uses hardware P-state numbering.
- * e. Adjust the following P-state parameters affected by the P-state
- * MSR copy by subtracting the number of P-states that are disabled
- * by the power check.
- * 1. F3x64[HtcPstateLimit]
- * 2. F3x68[StcPstateLimit]
- * 3. F3xDC[PstateMaxVal]
- * 3. If all P-States are over the limit, the BIOS must:
- * a. If the processor's current P-State is !=F3xDC[PstateMaxVal], then
- * write F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd] and wait for
- * MSRC001_0063[CurPstate] to reflect the new value.
- * b. If F3xDC[PstateMaxVal]!= 000b, copy the contents of the P-state
- * MSR pointed to by F3xDC[PstateMaxVal] to MSRC001_0064 and set
- * MSRC001_0064[PstateEn]
- * c. Write 000b to MSRC001_0062[PstateCmd] and wait for MSRC001_0063
- * [CurPstate] to reflect the new value.
- * d. Adjust the following P-state parameters to zero on revision D and earlier processors.
- * On revision E processors adjust the following fields to F4x15C[NumBoostStates]:
- * 1. F3x64[HtcPstateLimit]
- * 2. F3x68[StcPstateLimit]
- * 3. F3xDC[PstateMaxVal]
- * e. For revision E systems with CPUID Fn8000_0007[CPB]=1, program F4x15C[BoostSrc]=0.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] CpuEarlyParams Service parameters
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-F10PmPwrCheck (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 DisPsNum;
- UINT8 PsMaxVal;
- UINT8 Pstate;
- UINT32 ProcIddMax;
- UINT32 PciRegister;
- UINT32 Socket;
- UINT32 Module;
- UINT32 Core;
- UINT32 AndMask;
- UINT32 OrMask;
- UINT32 PstateLimit;
- PCI_ADDR PciAddress;
- UINT64 MsrRegister;
- AP_TASK TaskPtr;
- CPUID_DATA CpuidData;
- AGESA_STATUS IgnoredSts;
- PWRCHK_ERROR_DATA ErrorData;
-
- // get the socket number
- IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
- ErrorData.SocketNumber = (UINT8)Socket;
-
- ASSERT (Core == 0);
-
- // get the Max P-state value
- for (PsMaxVal = NM_PS_REG - 1; PsMaxVal != 0; --PsMaxVal) {
- LibAmdMsrRead (PS_REG_BASE + PsMaxVal, &MsrRegister, StdHeader);
- if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
- break;
- }
- }
-
- ErrorData.HwPstateNumber = (UINT8) (PsMaxVal + 1);
-
- DisPsNum = 0;
- for (Pstate = 0; Pstate < ErrorData.HwPstateNumber; Pstate++) {
- if (FamilySpecificServices->GetProcIddMax (FamilySpecificServices, Pstate, &ProcIddMax, StdHeader)) {
- if (ProcIddMax > CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].CurrentLimit) {
- // Add to event log the Pstate that exceeded the current limit
- PutEventLog (AGESA_WARNING,
- CPU_EVENT_PM_PSTATE_OVERCURRENT,
- Socket, Pstate, 0, 0, StdHeader);
- DisPsNum++;
- } else {
- break;
- }
- }
- }
-
- // If all P-state registers are disabled, move P[PsMaxVal] to P0
- // and transition to P0, then wait for CurPstate = 0
-
- ErrorData.AllowablePstateNumber = ((PsMaxVal + 1) - DisPsNum);
-
- // We only need to log this event on the BSC
- if (ErrorData.AllowablePstateNumber == 0) {
- PutEventLog (AGESA_FATAL,
- CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT,
- Socket, 0, 0, 0, StdHeader);
- }
-
- if (DisPsNum != 0) {
- GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
- // Check if CPB is supported. if yes, get the number of boost states.
- ErrorData.NumberofBoostStates = 0;
- LibAmdCpuidRead (AMD_CPUID_APM, &CpuidData, StdHeader);
- if (((CpuidData.EDX_Reg & 0x00000200) >> 9) == 1) {
- PciAddress.Address.Function = FUNC_4;
- PciAddress.Address.Register = CPB_CTRL_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- if (((CPB_CTRL_REGISTER *) &PciRegister)->NumBoostStates == 1) {
- ErrorData.NumberofBoostStates = 1;
- }
- }
-
- TaskPtr.FuncAddress.PfApTaskI = F10PmPwrCheckCore;
- TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (PWRCHK_ERROR_DATA);
- TaskPtr.DataTransfer.DataPtr = &ErrorData;
- TaskPtr.DataTransfer.DataTransferFlags = 0;
- TaskPtr.ExeFlags = WAIT_FOR_CORE;
- ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParams);
-
- // Final Step 1
- // For revision E systems with CPUID Fn8000_0007[CPB]=1, if P0 is disabled then
- // program F4x15C[BoostSrc]=0. This step uses hardware P-state numbering.
- if (ErrorData.NumberofBoostStates == 1) {
- PciAddress.Address.Function = FUNC_4;
- PciAddress.Address.Register = CPB_CTRL_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- ((CPB_CTRL_REGISTER *) &PciRegister)->BoostSrc = 0;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- }
- // Final Step 2
- // F3x64[HtPstatelimit] -= disPsNum
- // F3x68[StcPstateLimit]-= disPsNum
- // F3xDC[PstateMaxVal]-= disPsNum
-
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = HTC_REG;
- AndMask = 0xFFFFFFFF;
- ((HTC_REGISTER *) &AndMask)->HtcPstateLimit = 0;
- OrMask = 0x00000000;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // F3x64
- PstateLimit = ((HTC_REGISTER *) &PciRegister)->HtcPstateLimit;
- if (ErrorData.AllowablePstateNumber != 0) {
- if (PstateLimit > DisPsNum) {
- PstateLimit -= DisPsNum;
- ((HTC_REGISTER *) &OrMask)->HtcPstateLimit = PstateLimit;
- }
- } else {
- ((HTC_REGISTER *) &OrMask)->HtcPstateLimit = ErrorData.NumberofBoostStates;
- }
- ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x64
-
- PciAddress.Address.Register = STC_REG;
- AndMask = 0xFFFFFFFF;
- ((STC_REGISTER *) &AndMask)->StcPstateLimit = 0;
- OrMask = 0x00000000;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // F3x68
- PstateLimit = ((STC_REGISTER *) &PciRegister)->StcPstateLimit;
- if (ErrorData.AllowablePstateNumber != 0) {
- if (PstateLimit > DisPsNum) {
- PstateLimit -= DisPsNum;
- ((STC_REGISTER *) &OrMask)->StcPstateLimit = PstateLimit;
- }
- } else {
- ((STC_REGISTER *) &OrMask)->StcPstateLimit = ErrorData.NumberofBoostStates;
- }
- ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x68
-
- PciAddress.Address.Register = CPTC2_REG;
- AndMask = 0xFFFFFFFF;
- ((CLK_PWR_TIMING_CTRL2_REGISTER *) &AndMask)->PstateMaxVal = 0;
- OrMask = 0x00000000;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // F3xDC
- PstateLimit = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal;
- if (ErrorData.AllowablePstateNumber != 0) {
- if (PstateLimit > DisPsNum) {
- PstateLimit -= DisPsNum;
- ((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->PstateMaxVal = PstateLimit;
- }
- } else {
- ((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->PstateMaxVal = ErrorData.NumberofBoostStates;
- }
- ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xDC
-
- // Now that P0 has changed, recalculate VSSlamTime
- F10ProgramVSSlamTimeOnSocket (&PciAddress, CpuEarlyParams, StdHeader);
- }
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Core-level error handler called if any p-states were determined to be out
- * of range for the mother board.
- *
- * This function implements steps 2a-c and 3a-c on each core.
- *
- * @param[in] ErrorData Details about the error condition.
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-STATIC
-F10PmPwrCheckCore (
- IN VOID *ErrorData,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 i;
- UINT8 PsMaxVal;
- UINT8 DisPsNum;
- UINT8 CurrentPs;
- UINT8 EnBsNum;
- UINT64 MsrRegister;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
-
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
- PsMaxVal = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - 1);
- DisPsNum = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber -
- ((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber);
- EnBsNum = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberofBoostStates;
-
- LibAmdMsrRead (MSR_PSTATE_STS, &MsrRegister, StdHeader);
- CurrentPs = (UINT8) (((PSTATE_STS_MSR *) &MsrRegister)->CurPstate);
-
- if (((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber == 0) {
-
- // Step 1
- // Transition to Pstate Max if not there already
-
- if (CurrentPs != PsMaxVal) {
- FamilySpecificServices->TransitionPstate (FamilySpecificServices, PsMaxVal, (BOOLEAN) TRUE, StdHeader);
- }
-
-
- // Step 2
- // If Pstate Max is not 000b, copy Pstate max contents to P0 and switch
- // to P0. This step uses software P-state numbering
-
- if (PsMaxVal != 0) {
- F10PmPwrChkCopyPstate (EnBsNum, PsMaxVal, StdHeader);
- FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) TRUE, StdHeader);
- }
- } else {
-
- // move remaining P-state register(s) up
- // Step 1
- // Transition to a valid Pstate if current Pstate has been disabled
-
- if (CurrentPs < DisPsNum) {
- FamilySpecificServices->TransitionPstate (FamilySpecificServices, DisPsNum, (BOOLEAN) TRUE, StdHeader);
- CurrentPs = DisPsNum;
- }
-
- // Step 2
- // Move enabled Pstates up and disable the remainder. This step uses software P-state numbering.
- if (DisPsNum > EnBsNum) {
- for (i = 0; (i + DisPsNum) <= PsMaxVal; ++i) {
- F10PmPwrChkCopyPstate ((i + EnBsNum), (i + DisPsNum), StdHeader);
- }
- }
- // Step 3
- // Transition to current COF/VID at shifted location
-
- CurrentPs = (CurrentPs - DisPsNum);
- FamilySpecificServices->TransitionPstate (FamilySpecificServices, CurrentPs, (BOOLEAN) TRUE, StdHeader);
- }
- i = ((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber;
- if (i == 0) {
- ++i;
- }
- while (i <= PsMaxVal) {
- FamilySpecificServices->DisablePstate (FamilySpecificServices, i, StdHeader);
- ++i;
- }
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Copies the contents of one P-State MSR to another.
- *
- * @param[in] Dest Destination p-state number
- * @param[in] Src Source p-state number
- * @param[in] StdHeader Config handle for library and services
- *
- */
-VOID
-STATIC
-F10PmPwrChkCopyPstate (
- IN UINT8 Dest,
- IN UINT8 Src,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 MsrRegister;
-
- LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &MsrRegister, StdHeader);
- LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &MsrRegister, StdHeader);
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10PowerCheck.h b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10PowerCheck.h
deleted file mode 100644
index f9c94b3..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10PowerCheck.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Power related functions and structures
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F10
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPU_F10_POWER_CHECK_H_
-#define _CPU_F10_POWER_CHECK_H_
-
-
-/*---------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *---------------------------------------------------------------------------------------
- */
-/// Power Check Error Data
-typedef struct {
- UINT8 SocketNumber; ///< Socket Number
- UINT8 HwPstateNumber; ///< Hardware P-state Number
- UINT8 AllowablePstateNumber; ///< Allowable P-state Number
- UINT8 NumberofBoostStates; ///< The Number of Boost States
-} PWRCHK_ERROR_DATA;
-
-/*---------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *---------------------------------------------------------------------------------------
- */
-VOID
-F10PmPwrCheck (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif // _CPU_F10_POWER_CHECK_H_
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10PowerMgmt.h b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10PowerMgmt.h
deleted file mode 100644
index 7c6d0e2..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10PowerMgmt.h
+++ /dev/null
@@ -1,548 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Power Management related stuff
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F10
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPUF10POWERMGMT_H_
-#define _CPUF10POWERMGMT_H_
-
-/*
- * Family 10h CPU Power Management MSR definitions
- *
- */
-
-/* Interrupt Pending and CMP-Halt MSR Register 0xC0010055 */
-#define MSR_INTPEND 0xC0010055
-
-/// Interrupt Pending and CMP-Halt MSR Register
-typedef struct {
- UINT64 IoMsgAddr:16; ///< IO message address
- UINT64 IoMsgData:8; ///< IO message data
- UINT64 IntrPndMsgDis:1; ///< Interrupt pending message disable
- UINT64 IntrPndMsg:1; ///< Interrupt pending message
- UINT64 IoRd:1; ///< IO read
- UINT64 SmiOnCmpHalt:1; ///< SMI on chip multi-processing halt
- UINT64 C1eOnCmpHalt:1; ///< C1E on chip multi-processing halt
- UINT64 BmStsClrOnHltEn:1; ///< Clear BM status bit on server C1e entry
- UINT64 :34; ///< Reserved
-} INTPEND_MSR;
-
-
-/* P-state Current Limit Register 0xC0010061 */
-#define MSR_PSTATE_CURRENT_LIMIT 0xC0010061
-
-/// Pstate Current Limit MSR Register
-typedef struct {
- UINT64 CurPstateLimit:3; ///< Current Pstate Limit
- UINT64 :1; ///< Reserved
- UINT64 PstateMaxVal:3; ///< Pstate Max Value
- UINT64 :57; ///< Reserved
-} PSTATE_CURLIM_MSR;
-
-
-/* P-state Control Register 0xC0010062 */
-#define MSR_PSTATE_CTL 0xC0010062
-
-/// Pstate Control MSR Register
-typedef struct {
- UINT64 PstateCmd:3; ///< Pstate change command
- UINT64 :61; ///< Reserved
-} PSTATE_CTRL_MSR;
-
-
-/* P-state Status Register 0xC0010063 */
-#define MSR_PSTATE_STS 0xC0010063
-
-/// Pstate Status MSR Register
-typedef struct {
- UINT64 CurPstate:3; ///< Current Pstate
- UINT64 :61; ///< Reserved
-} PSTATE_STS_MSR;
-
-
-/* P-state Registers 0xC001006[8:4] */
-#define MSR_PSTATE_0 0xC0010064
-#define MSR_PSTATE_1 0xC0010065
-#define MSR_PSTATE_2 0xC0010066
-#define MSR_PSTATE_3 0xC0010067
-#define MSR_PSTATE_4 0xC0010068
-
-#define PS_REG_BASE MSR_PSTATE_0 /* P-state Register base */
-#define PS_MAX_REG MSR_PSTATE_4 /* Maximum P-State Register */
-#define PS_MIN_REG MSR_PSTATE_0 /* Minimum P-State Register */
-#define NM_PS_REG 5 /* number of P-state MSR registers */
-
-/// Pstate MSR
-typedef struct {
- UINT64 CpuFid:6; ///< CpuFid
- UINT64 CpuDid:3; ///< CpuDid
- UINT64 CpuVid:7; ///< CpuVid
- UINT64 :6; ///< Reserved
- UINT64 NbDid:1; ///< NbDid
- UINT64 :2; ///< Reserved
- UINT64 NbVid:7; ///< NbVid
- UINT64 IddValue:8; ///< IddValue
- UINT64 IddDiv:2; ///< IddDiv
- UINT64 :21; ///< Reserved
- UINT64 PsEnable:1; ///< Pstate Enable
-} PSTATE_MSR;
-
-
-/* COFVID Control Register 0xC0010070 */
-#define MSR_COFVID_CTL 0xC0010070
-
-/// COFVID Control MSR Register
-typedef struct {
- UINT64 CpuFid:6; ///< CpuFid
- UINT64 CpuDid:3; ///< CpuDid
- UINT64 CpuVid:7; ///< CpuVid
- UINT64 PstateId:3; ///< Pstate ID
- UINT64 :3; ///< Reserved
- UINT64 NbDid:1; ///< NbDid
- UINT64 :2; ///< Reserved
- UINT64 NbVid:7; ///< NbVid
- UINT64 :32; ///< Reserved
-} COFVID_CTRL_MSR;
-
-
-/* COFVID Status Register 0xC0010071 */
-#define MSR_COFVID_STS 0xC0010071
-
-/// COFVID Status MSR Register
-typedef struct {
- UINT64 CurCpuFid:6; ///< Current CpuFid
- UINT64 CurCpuDid:3; ///< Current CpuDid
- UINT64 CurCpuVid:7; ///< Current CpuVid
- UINT64 CurPstate:3; ///< Current Pstate
- UINT64 :3; ///< Reserved
- UINT64 CurNbDid:1; ///< Current NbDid
- UINT64 :2; ///< Reserved
- UINT64 CurNbVid:7; ///< Current NbVid
- UINT64 StartupPstate:3; ///< Startup Pstate
- UINT64 MaxVid:7; ///< MaxVid
- UINT64 MinVid:7; ///< MinVid
- UINT64 MaxCpuCof:6; ///< MaxCpuCof
- UINT64 :1; ///< Reserved
- UINT64 CurPstateLimit:3; ///< Current Pstate Limit
- UINT64 MaxNbFid:5; ///< MaxNbFid
-} COFVID_STS_MSR;
-
-/* C-state Address Register 0xC0010073 */
-#define MSR_CSTATE_ADDRESS 0xC0010073
-
-/// C-state Address MSR Register
-typedef struct {
- UINT64 CstateAddr:16; ///< C-state address
- UINT64 :48; ///< Reserved
-} CSTATE_ADDRESS_MSR;
-
-/*
- * Family 10h CPU Power Management PCI definitions
- *
- */
-
-/* DRAM Configuration High Register F2x[1,0]94 */
-#define DRAM_CFG_HI_REG0 0x94
-#define DRAM_CFG_HI_REG1 0x194
-
-/// DRAM Configuration High PCI Register
-typedef struct {
- UINT32 MemClkFreq:3; ///< Memory clock frequency
- UINT32 MemClkFreqVal:1; ///< Memory clock frequency valid
- UINT32 :4; ///< Reserved
- UINT32 Ddr3Mode:1; ///< DDR3 mode
- UINT32 LegacyBiosMode:1; ///< Legacy BIOS mode
- UINT32 ZqcsInterval:2; ///< ZQ calibration short interval
- UINT32 RDqsEn:1; ///< Read DQS enable
- UINT32 DisSimulRdWr:1; ///< Disable simultaneous read and write
- UINT32 DisDramInterface:1; ///< Disable the DRAM interface
- UINT32 PowerDownEn:1; ///< Power down mode enable
- UINT32 PowerDownMode:1; ///< Power down mode
- UINT32 :1; ///< Reserved
- UINT32 FourRankRDimm:1; ///< Four rank registered DIMM connected
- UINT32 DcqArbBypassEn:1; ///< DRAM controller arbiter bypass enable
- UINT32 SlowAccessMode:1; ///< Slow access mode
- UINT32 FreqChgInProg:1; ///< Frequency change in progress
- UINT32 BankSwizzleMode:1; ///< Bank swizzle mode
- UINT32 ProcOdtDis:1; ///< Processor on-die termination disable
- UINT32 DcqBypassMax:4; ///< DRAM controller queue bypass maximum
- UINT32 FourActWindow:4; ///< Four bank activate window
-} DRAM_CFG_HI_REGISTER;
-
-
-/* Extended Memory Controller Configuration Low Register F2x1B0 */
-#define EXT_MEMCTRL_CFG_LOW_REG 0x1B0
-
-/// Extended Memory Controller Configuration Low PCI Register
-typedef struct {
- UINT32 AdapPrefMissRatio:2; ///< Adaptive prefetch miss ratio
- UINT32 AdapPrefPositiveStep:2; ///< Adaptive prefetch positive step
- UINT32 AdapPrefNegativeStep:2; ///< Adaptive prefetch negative step
- UINT32 :2; ///< Reserved
- UINT32 CohPrefPrbLmt:3; ///< Coherent prefetch probe limit
- UINT32 DisIoCohPref:1; ///< Disable coherent prefetched for IO
- UINT32 EnSplitDctLimits:1; ///< Split DCT write limits enable
- UINT32 SpecPrefDis:1; ///< Speculative prefetch disable
- UINT32 SpecPrefMis:1; ///< Speculative prefetch predict miss
- UINT32 SpecPrefThreshold:3; ///< Speculative prefetch threshold
- UINT32 :4; ///< Reserved
- UINT32 PrefFourConf:3; ///< Prefetch four-ahead confidence
- UINT32 PrefFiveConf:3; ///< Prefetch five-ahead confidence
- UINT32 DcqBwThrotWm:4; ///< Dcq bandwidth throttle watermark
-} EXT_MEMCTRL_CFG_LOW_REGISTER;
-
-
-/* Scrub Rate Control Register F3x58 */
-#define SCRUB_RATE_CTRL_REG 0x58
-
-/// Scrub Rate Control PCI Register
-typedef struct {
- UINT32 DramScrub:5; ///< DRAM scrub rate
- UINT32 :3; ///< Reserved
- UINT32 L2Scrub:5; ///< L2 cache scrub rate
- UINT32 :3; ///< Reserved
- UINT32 DcacheScrub:5; ///< Data cache scrub rate
- UINT32 :3; ///< Reserved
- UINT32 L3Scrub:5; ///< L3 cache scrub rate
- UINT32 :3; ///< Reserved
-} SCRUB_RATE_CTRL_REGISTER;
-
-/* DRAM Scrub Address Low Register F3x5C */
-#define DRAM_SCRUB_ADDR_LOW_REG 0x5C
-
-/// DRAM Scrub Address Low PCI Register
-typedef struct {
- UINT32 ScrubReDirEn:1; ///< DRAM scrubber redirect enable
- UINT32 :5; ///< Reserved
- UINT32 ScrubAddrLo:26; ///< DRAM scrubber address bits[31:6]
-} DRAM_SCRUB_ADDR_LOW_REGISTER;
-
-
-/* Hardware thermal control register F3x64 */
-#define HTC_REG 0x64
-#define HTC_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, HTC_REG))
-
-/// Hardware Thermal Control PCI Register
-typedef struct {
- UINT32 HtcEn:1; ///< HTC Enable
- UINT32 :3; ///< Reserved
- UINT32 HtcAct:1; ///< HTC Active State
- UINT32 HtcActSts:1; ///< HTC Active Status
- UINT32 PslApicHiEn:1; ///< P-state limit higher APIC int enable
- UINT32 PslApicLoEn:1; ///< P-state limit lower APIC int enable
- UINT32 :8; ///< Reserved
- UINT32 HtcTmpLmt:7; ///< HTC temperature limit
- UINT32 HtcSlewSel:1; ///< HTC slew-controlled temp select
- UINT32 HtcHystLmt:4; ///< HTC hysteresis
- UINT32 HtcPstateLimit:3; ///< HTC P-state limit select
- UINT32 :1; ///< Reserved
-} HTC_REGISTER;
-
-
-/* Software thermal control register F3x68 */
-#define STC_REG 0x68
-
-/// Software Thermal Control PCI Register
-typedef struct {
- UINT32 StcSbcTmpHiEn:1; ///< STC SBC temperature high enable
- UINT32 StcSbcTmpLoEn:1; ///< STC SBC temperature low enable
- UINT32 StcApcTmpHiEn:1; ///< STC APIC temperature high enable
- UINT32 StcApcTmpLoEn:1; ///< STC APIC temperature low enable
- UINT32 :1; ///< Reserved
- UINT32 StcPstateEn:1; ///< STC P-state enable
- UINT32 StcTmpHiSts:1; ///< STC temperature high status
- UINT32 StcTmpLoSts:1; ///< STC temperature low status
- UINT32 :8; ///< Reserved
- UINT32 StcTmpLmt:7; ///< STC temperature limit
- UINT32 StcSlewSel:1; ///< STC slew-controlled temp select
- UINT32 StcHystLmt:4; ///< STC hysteresis
- UINT32 StcPstateLimit:3; ///< STC P-state limit select
- UINT32 :1; ///< Reserved
-} STC_REGISTER;
-
-/* ACPI Power State Control Registers F3x84:80 */
-
-/// System Management Action Field (SMAF) Register
-typedef struct {
- UINT8 CpuPrbEn:1; ///< CPU direct probe enable
- UINT8 NbLowPwrEn:1; ///< Northbridge low-power enable
- UINT8 NbGateEn:1; ///< Northbridge gate enable
- UINT8 NbCofChg:1; ///< NbCofChg
- UINT8 AltVidEn:1; ///< alternate VID enable
- UINT8 ClkDivisor:3; ///< Clock divisor
-} SMAF_REGISTER;
-
-/// union type for ACPI State SMAF setting
-typedef union {
- UINT8 SMAFValue; ///< SMAF raw value
- SMAF_REGISTER SMAF; ///< SMAF structure
-} ACPI_STATE_SMAF;
-
-/// ACPI Power State Control Register F3x80
-typedef struct {
- ACPI_STATE_SMAF C2; ///< [7:0] SMAF Code 000b - C2
- ACPI_STATE_SMAF C3C1eLinkInit; ///< [15:8] SMAF Code 001b - C3, C1e or Link init
- ACPI_STATE_SMAF FidVidChg; ///< [23:16] SMAF Code 010b - FIDVID Change
- ACPI_STATE_SMAF S1; ///< [31:24] SMAF Code 011b - S1
-} ACPI_PSC_0_REGISTER;
-
-/// ACPI Power State Control Register F3x84
-typedef struct {
- ACPI_STATE_SMAF S3; ///< [7:0] SMAF Code 100b - S3
- ACPI_STATE_SMAF Throttling; ///< [15:8] SMAF Code 101b - Throttling
- ACPI_STATE_SMAF S4S5; ///< [23:16] SMAF Code 110b - S4/S5
- ACPI_STATE_SMAF C1; ///< [31:24] SMAF Code 111b - C1
-} ACPI_PSC_4_REGISTER;
-
-
-/* Power Control Miscellaneous Register F3xA0 */
-#define PW_CTL_MISC_REG 0xA0
-#define PW_CTL_MISC_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, PW_CTL_MISC_REG))
-
-/// Power Control Miscellaneous PCI Register
-typedef struct {
- UINT32 PsiVid:7; ///< PSI_L VID threshold
- UINT32 PsiVidEn:1; ///< PSI_L VID enable
- UINT32 PviMode:1; ///< Parallel VID interface mode
- UINT32 SviHighFreqSel:1; ///< SVI high frequency select
- UINT32 IdleExitEn:1; ///< IDLEEXIT_L Enable
- UINT32 PllLockTime:3; ///< PLL synchronization lock time
- UINT32 BpPinsTriEn:1; ///< Breakpoint pins tristate enable
- UINT32 :1; ///< Reserved
- UINT32 PstateId:12; ///< Pstate ID
- UINT32 :1; ///< Reserved
- UINT32 SlamVidMode:1; ///< Slam voltage ID mode
- UINT32 :1; ///< Reserved
- UINT32 CofVidProg:1; ///< COF and VID of Pstate programmed
-} POWER_CTRL_MISC_REGISTER;
-
-/* Popup P-state Register F3xA8 */
-#define POPUP_PSTATE_REG 0xA8
-#define POPUP_PSTATE_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, POPUP_PSTATE_REG))
-
-/// Popup P-state Register
-typedef struct {
- UINT32 PopupEn:1; ///< Popup enable
- UINT32 :1; ///< Reserved
- UINT32 PopupPstate:3; ///< Popup P-state
- UINT32 PopupCpuVid:7; ///< Popup core VID
- UINT32 PopupCpuFid:6; ///< Popup core FID
- UINT32 PopupCpuDid:3; ///< Popup core DID
- UINT32 :6; ///< Reserved
- UINT32 CacheFlushPopDownEn:1; ///< Cache Flush PopDown P-state Enable
- UINT32 :1; ///< Reserved
- UINT32 PopDownPstate:3; ///< Pop-down P-state number
-} POPUP_PSTATE_REGISTER;
-
-/* Clock Power/Timing Control 0 Register F3xD4 */
-#define CPTC0_REG 0xD4
-
-/// Clock Power Timing Control PCI Register
-typedef struct {
- UINT32 NbFid:5; ///< NbFid
- UINT32 NbFidEn:1; ///< NbFidEn
- UINT32 :2; ///< Reserved
- UINT32 ClkRampHystSel:4; ///< Clock Ramp Hysteresis Select
- UINT32 ClkRampHystCtl:1; ///< Clock Ramp Hysteresis Control
- UINT32 MTC1eEn:1; ///< Message Triggered C1e Enable
- UINT32 CacheFlushImmOnAllHalt:1; ///< Cache Flush Immediate on All Halt
- UINT32 StutterScrubEn:1; ///< Stutter Mode Scrub Enable
- UINT32 LnkPllLock:2; ///< Link PLL Lock
- UINT32 :2; ///< Reserved
- UINT32 PowerStepDown:4; ///< Power Step Down
- UINT32 PowerStepUp:4; ///< Power Step Up
- UINT32 NbClkDiv:3; ///< NbClkDiv
- UINT32 NbClkDivApplyAll:1; ///< NbClkDivApplyAll
-} CLK_PWR_TIMING_CTRL_REGISTER;
-
-
-/* Clock Power/Timing Control 1 Register F3xD8 */
-#define CPTC1_REG 0xD8
-
-/// Clock Power Timing Control 1 PCI Register
-typedef struct {
- UINT32 VSSlamTime:3; ///< Voltage stabilization slam time
- UINT32 :1; ///< Reserved
- UINT32 VSRampTime:3; ///< Voltage stabilization ramp time
- UINT32 :1; ///< Reserved
- UINT32 TdpVid:7; ///< Thermal design power VID
- UINT32 :1; ///< Reserved
- UINT32 AltVidStart:7; ///< Alternate VID start limit
- UINT32 :1; ///< Reserved
- UINT32 ReConDel:4; ///< Link reconnect delay
- UINT32 PwrPlanes:1; ///< Power planes
- UINT32 :3; ///< Reserved
-} CLK_PWR_TIMING_CTRL1_REGISTER;
-
-
-/* Clock Power/Timing Control 2 Register F3xDC */
-#define CPTC2_REG 0xDC
-#define CPTC2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC2_REG))
-/// Clock Power Timing Control 2 PCI Register
-typedef struct {
- UINT32 AltVid:7; ///< Alternate VID
- UINT32 :1; ///< Reserved
- UINT32 PstateMaxVal:3; ///< P-state maximum value
- UINT32 :1; ///< Reserved
- UINT32 NbsynPtrAdj:3; ///< NB/Core sync FIFO ptr adjust
- UINT32 :1; ///< Reserved
- UINT32 CacheFlushOnHaltCtl:3; ///< Cache flush on halt control
- UINT32 CacheFlushOnHaltTmr:7; ///< Cache flush on halt timer
- UINT32 :1; ///< Reserved
- UINT32 SlamTimeMode:2; ///< Slam time mode
- UINT32 AltvidVSSlamTime:3; ///< Altvid voltage stabilization slam time
-} CLK_PWR_TIMING_CTRL2_REGISTER;
-
-
-/* Northbridge Capabilities Register F3xE8 */
-#define NB_CAPS_REG 0xE8
-
-/// Northbridge Capabilities PCI Register
-typedef struct {
- UINT32 DctDualCap:1; ///< Two-channel DRAM capable
- UINT32 DualNodeCap:1; ///< Dual-node multi-processor capable
- UINT32 EightNodeCap:1; ///< Eight-node multi-processor capable
- UINT32 EccCapable:1; ///< ECC capable
- UINT32 ChipkillCapable:1; ///< Chipkill ECC capable
- UINT32 DdrMaxRate:3; ///< Maximum DRAM data rate
- UINT32 MctCap:1; ///< Memory controller capable
- UINT32 SvmCapable:1; ///< SVM capable
- UINT32 HtcCapable:1; ///< HTC capable
- UINT32 LnkRtryCap:1; ///< Link error-retry capable
- UINT32 CmpCapLo:2; ///< CMP capable[1:0]
- UINT32 MultiVidPlaneCap:1; ///< Multiple VID plane capable
- UINT32 CmpCapHi:1; ///< CMP capable[2]
- UINT32 MpCap:3; ///< MP capability
- UINT32 :1; ///< Reserved
- UINT32 UnGangEn:4; ///< Link unganging enabled
- UINT32 :1; ///< Reserved
- UINT32 L3Capable:1; ///< L3 capable
- UINT32 HtAcCapable:1; ///< HT AC capable
- UINT32 :2; ///< Reserved
- UINT32 MultiNodeCpu:1; ///< Multinode processor
- UINT32 IntNodeNum:2; ///< Internal node number
-} NB_CAPS_REGISTER;
-
-
-/* NB Extended Configuration Low Register F3x188 */
-#define NB_EXT_CFG_LO_REG 0x188
-
-/// Northbridge Extended Configuration Low PCI Register
-typedef struct {
- UINT32 :4; ///< Reserved
- UINT32 EnStpGntOnFlushMaskWakeup:1; ///< Enable stop grant on flush mask wakeup
- UINT32 :27; ///< Reserved
-} NB_EXT_CFG_LO_REGISTER;
-
-
-/* L3 Cache Parameter Register F3x1C4 */
-#define L3_CACHE_PARAM_REG 0x1C4
-
-/// L3 Cache Parameter PCI Register
-typedef struct {
- UINT32 L3SubcacheSize0:1; ///< L3 subcache size 0
- UINT32 :3; ///< Reserved
- UINT32 L3SubcacheSize1:1; ///< L3 subcache size 1
- UINT32 :3; ///< Reserved
- UINT32 L3SubcacheSize2:2; ///< L3 subcache size 2
- UINT32 :2; ///< Reserved
- UINT32 L3SubcacheSize3:2; ///< L3 subcache size 3
- UINT32 :17; ///< Reserved
- UINT32 L3TagInit:1; ///< L3 tag initialization
-} L3_CACHE_PARAM_REGISTER;
-
-
-/* Probe Filter Control Register F3x1D4 */
-#define PROBE_FILTER_CTRL_REG 0x1D4
-
-/// Probe Filter Control PCI Register
-typedef struct {
- UINT32 PFMode:2; ///< Probe Filter Mode
- UINT32 PFWayNum:2; ///< Probe Filter way number
- UINT32 PFSubCacheSize0:2; ///< Probe filter subcache 0 size
- UINT32 PFSubCacheSize1:2; ///< Probe filter subcache 1 size
- UINT32 PFSubCacheSize2:2; ///< Probe filter subcache 2 size
- UINT32 PFSubCacheSize3:2; ///< Probe filter subcache 3 size
- UINT32 PFSubCacheEn:4; ///< Probe filter subcache enable
- UINT32 :3; ///< Reserved
- UINT32 PFInitDone:1; ///< Probe filter initialization done
- UINT32 PFPreferredSORepl:2; ///< PF preferredSO replacement mode
- UINT32 PFErrInt:2; ///< Probe filter error interrupt type
- UINT32 PFErrIntLvtOff:4; ///< Probe filter error interrupt LVT offset
- UINT32 PFEccError:1; ///< Probe filter ECC error
- UINT32 PFLoIndexHashEn:1; ///< Probe filter low index hash enable
- UINT32 :2; ///< Reserved
-} PROBE_FILTER_CTRL_REGISTER;
-
-
-/* Product Info Register F3x1FC */
-#define PRCT_INFO_REG 0x1FC
-#define PRCT_INFO_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, PRCT_INFO_REG))
-
-/// Product Information PCI Register
-typedef struct {
- UINT32 NbCofVidUpdate:1; ///< NbCofVidUpdate
- UINT32 NbVidUpdateAll:1; ///< NbVidUpdateAll
- UINT32 SinglePlaneNbFid:5; ///< SinglePlaneNbFid
- UINT32 SinglePlaneNbVid:7; ///< SinglePlaneNbVid
- UINT32 DualPlaneNbFidOff:3; ///< DualPlaneNbFidOff
- UINT32 DualPlaneNbVidOff:5; ///< DualPlaneNbVidOff
- UINT32 SinglePlaneNbIdd:4; ///< SinglePlaneNbIdd
-} PRODUCT_INFO_REGISTER;
-
-/* Core Performance Boost Control Register D18F4x15C */
-#define CPB_CTRL_REG 0x15C
-#define CPB_CTRL_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CPB_CTRL_REG))
-
-/// Core Performance Boost Control Register
-typedef struct {
- UINT32 BoostSrc:2; ///< Boost source
- UINT32 NumBoostStates:1; ///< Number of boosted states
- UINT32 :27; ///< Reserved
- UINT32 BoostLock:1; ///< Boost Lock
-} CPB_CTRL_REGISTER;
-#endif /* _CPUF10POWERMGMT_H */
-
-/* Boost Offset Register F3x10C */
-#define F3x10C_REG 0x10C
-#define F3x10C_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, F3x10C_REG))
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c
deleted file mode 100644
index fa8f48d..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Power Management related stuff
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuApicUtilities.h"
-#include "cpuFamilyTranslation.h"
-#include "IdsF10AllService.h"
-#include "cpuPowerMgmtSystemTables.h"
-#include "cpuF10EarlyInit.h"
-#include "cpuF10SoftwareThermal.h"
-#include "cpuF10PowerPlane.h"
-#include "cpuF10PowerCheck.h"
-#include "F10PmNbCofVidInit.h"
-#include "F10PmNbPstateInit.h"
-#include "F10PmAsymBoostInit.h"
-#include "F10PmDualPlaneOnlySupport.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10POWERMGMTSYSTEMTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/* Family 10h Only Table */
-/* ---------------------- */
-CONST SYS_PM_TBL_STEP ROMDATA CpuF10SysPmTableArray[] =
-{
- IDS_INITIAL_F10_PM_STEP
-
- // Step 1 - Configure F3x[84:80]. Handled by PCI register table.
- // Step 2 - Configure Northbridge COF and VID.
- // Execute both cold & warm
- {
- 0,
- F10PmNbCofVidInit
- },
-
- // Step 3 - Dual-plane Only Support.
- {
- PM_EXEFLAGS_WARM_ONLY, // ExeFlags
- F10PmDualPlaneOnlySupport
- },
-
- // Step 4 - Asymmetric Boost.
- // Execute only after warm reset
- {
- PM_EXEFLAGS_WARM_ONLY, // ExeFlags
- F10PmAsymBoostInit
- },
-
- // Step 5 - Configure Nb-Pstates.
- // Execute only after warm reset
- {
- PM_EXEFLAGS_WARM_ONLY, // ExeFlags
- F10PmNbPstateInit
- },
- // Step 6 - Power Plane Initialization
- // Execute both cold & warm
- {
- 0, // ExeFlags
- F10CpuAmdPmPwrPlaneInit // Function Pointer
- },
-
- // Step 7 - Pmin Transition After Reset
- // Execute only after warm reset
- {
- PM_EXEFLAGS_WARM_ONLY, // ExeFlags
- F10PmAfterReset // Function Pointer
- },
-
- // Step 8 - Current Delivery Check
- // Execute only after warm reset
- {
- PM_EXEFLAGS_WARM_ONLY, // ExeFlags
- F10PmPwrCheck // Function Pointer
- },
-
- // Step x - Software Thermal Control Init
- // Execute only after warm reset
- {
- PM_EXEFLAGS_WARM_ONLY, // ExeFlags
- F10PmThermalInit // Function Pointer
- },
-};
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns the appropriate table of steps to perform to initialize the power management
- * subsystem.
- *
- * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[out] SysPmTblPtr Points to the first entry in the table.
- * @param[out] NumberOfElements Number of valid entries in the table.
- * @param[in] StdHeader Header for library and services.
- *
- */
-VOID
-GetF10SysPmTable (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- OUT CONST VOID **SysPmTblPtr,
- OUT UINT8 *NumberOfElements,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- *NumberOfElements = (sizeof (CpuF10SysPmTableArray) / sizeof (SYS_PM_TBL_STEP));
- *SysPmTblPtr = CpuF10SysPmTableArray;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10PowerPlane.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10PowerPlane.c
deleted file mode 100644
index 4011971..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10PowerPlane.c
+++ /dev/null
@@ -1,484 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Power Plane Initialization
- *
- * Performs the "BIOS Requirements for Power Plane Initialization" as described
- * in the BKDG.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F10
- * @e \$Revision: 36224 $ @e \$Date: 2010-08-16 09:46:54 +0800 (Mon, 16 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuF10PowerMgmt.h"
-#include "cpuApicUtilities.h"
-#include "cpuServices.h"
-#include "GeneralServices.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuF10Utilities.h"
-#include "Table.h"
-#include "F10PackageType.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10POWERPLANE_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-// Register encodings for F3xD4[PowerStepUp/PowerStepDown]
-CONST UINT16 ROMDATA PowerStepEncodings[16] =
-{
- 400, // 0000b: 400ns
- 300, // 0001b: 300ns
- 200, // 0010b: 200ns
- 100, // 0011b: 100ns
- 90, // 0100b: 90ns
- 80, // 0101b: 80ns
- 70, // 0110b: 70ns
- 60, // 0111b: 60ns
- 50, // 1000b: 50ns
- 45, // 1001b: 45ns
- 40, // 1010b: 40ns
- 35, // 1011b: 35ns
- 30, // 1100b: 30ns
- 25, // 1101b: 25ns
- 20, // 1110b: 20ns
- 15 // 1111b: 15ns
-};
-
-// Register encodings for F3xDC[AltvidVSSlamTime]
-CONST UINT32 ROMDATA AltvidSlamTime[8] =
-{
- 0, // 000b: <1us
- 10, // 001b: 10us
- 20, // 010b: 20us
- 40, // 011b: 40us
- 50, // 100b: 50us
- 70, // 101b: 70us
- 80, // 110b: 80us
- 90 // 111b: 90us
-};
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-VOID
-STATIC
-F10PmPwrPlaneInitPviCore (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-UINT32
-STATIC
-F10CalculateAltvidVSSlamTimeOnCore (
- IN BOOLEAN PviModeFlag,
- IN PCI_ADDR *PciAddress,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-STATIC
-F10PmVrmLowPowerModeEnable (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
- IN PCI_ADDR PciAddress,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family 10h core 0 entry point for performing power plane initialization.
- *
- * The steps are as follows:
- * 1. If single plane, program lower VID code of CpuVid & NbVid for all
- * enabled P-States.
- * 2. Configure F3xA0[SlamMode] & F3xD8[VsRampTime & VsSlamTime] based on
- * platform requirements.
- * 3. Configure F3xD4[PowerStepUp & PowerStepDown]
- * 4. Optionally configure F3xA0[PsiVidEn & PsiVid]
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] CpuEarlyParams Service parameters
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-F10CpuAmdPmPwrPlaneInit (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- BOOLEAN PviModeFlag;
- PCI_ADDR PciAddress;
- UINT16 PowerStepTime;
- UINT32 PowerStepEncoded;
- UINT32 PciRegister;
- UINT32 VsSlamTime;
- UINT32 Socket;
- UINT32 Module;
- UINT32 Core;
- UINT32 NumOfCores;
- UINT32 LowCore;
- UINT32 AndMask;
- UINT32 OrMask;
- UINT32 ProcessorPackageType;
- UINT64 MsrRegister;
- AP_TASK TaskPtr;
- AGESA_STATUS IgnoredSts;
- PLATFORM_FEATS Features;
- CPU_LOGICAL_ID LogicalId;
-
- // Initialize the union
- Features.PlatformValue = 0;
- GetPlatformFeatures (&Features, &CpuEarlyParams->PlatformConfig, StdHeader);
-
- IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
- GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
-
- ASSERT (Core == 0);
-
- GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
-
- // Set SlamVidMode
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = PW_CTL_MISC_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- AndMask = 0xFFFFFFFF;
- OrMask = 0x00000000;
- if (((POWER_CTRL_MISC_REGISTER *) &PciRegister)->PviMode == 1) {
- PviModeFlag = TRUE;
- ((POWER_CTRL_MISC_REGISTER *) &AndMask)->SlamVidMode = 0;
-
- // Have all single plane cores adjust their NB and CPU VID fields
- TaskPtr.FuncAddress.PfApTask = F10PmPwrPlaneInitPviCore;
- TaskPtr.DataTransfer.DataSizeInDwords = 0;
- TaskPtr.ExeFlags = WAIT_FOR_CORE;
- ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParams);
-
- } else {
- PviModeFlag = FALSE;
- ((POWER_CTRL_MISC_REGISTER *) &OrMask)->SlamVidMode = 1;
- }
- ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
-
- F10ProgramVSSlamTimeOnSocket (&PciAddress, CpuEarlyParams, StdHeader);
-
- // Configure PowerStepUp/PowerStepDown
- PciAddress.Address.Register = CPTC0_REG;
- if ((Features.PlatformFeatures.PlatformSingleLink == 1) ||
- (Features.PlatformFeatures.PlatformUma == 1) ||
- (Features.PlatformFeatures.PlatformUmaIfcm == 1) ||
- (Features.PlatformFeatures.PlatformIfcm == 1) ||
- (Features.PlatformFeatures.PlatformIommu == 1)) {
- PowerStepEncoded = 0x8;
- } else {
- GetGivenModuleCoreRange ((UINT32) Socket,
- (UINT32) Module,
- &LowCore,
- &NumOfCores,
- StdHeader);
- NumOfCores = ((NumOfCores - LowCore) + 1);
- PowerStepTime = (UINT16) (400 / NumOfCores);
- for (PowerStepEncoded = 0xF; PowerStepEncoded > 0; PowerStepEncoded--) {
- if (PowerStepTime <= PowerStepEncodings[PowerStepEncoded]) {
- break;
- }
- }
- }
- AndMask = 0xFFFFFFFF;
- ((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->PowerStepUp = 0;
- ((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->PowerStepDown = 0;
- OrMask = 0x00000000;
- ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->PowerStepUp = PowerStepEncoded;
- ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->PowerStepDown = PowerStepEncoded;
- ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
-
- if ((LogicalId.Revision & AMD_F10_C3) != 0) {
- // Set up Pop up P-state register
- PciAddress.Address.Register = CPTC2_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- AndMask = 0xFFFFFFFF;
- ((POPUP_PSTATE_REGISTER *) &AndMask)->PopupPstate = 0;
- ((POPUP_PSTATE_REGISTER *) &AndMask)->PopupCpuVid = 0;
- ((POPUP_PSTATE_REGISTER *) &AndMask)->PopupCpuFid = 0;
- ((POPUP_PSTATE_REGISTER *) &AndMask)->PopupCpuDid = 0;
- OrMask = 0x00000000;
- ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupEn = 0;
- ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupPstate = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal;
- LibAmdMsrRead ((((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal + PS_REG_BASE), &MsrRegister, StdHeader);
- ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuVid = (UINT32) ((PSTATE_MSR *) &MsrRegister)->CpuVid;
- ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuFid = (UINT32) ((PSTATE_MSR *) &MsrRegister)->CpuFid;
- ((POPUP_PSTATE_REGISTER *) &OrMask)->PopupCpuDid = (UINT32) ((PSTATE_MSR *) &MsrRegister)->CpuDid;
- PciAddress.Address.Register = POPUP_PSTATE_REG;
- ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
-
- // Set AltVidStart
- PciAddress.Address.Register = CPTC1_REG;
- AndMask = 0xFFFFFFFF;
- ((CLK_PWR_TIMING_CTRL1_REGISTER *) &AndMask)->AltVidStart = 0;
- OrMask = 0x00000000;
- ((CLK_PWR_TIMING_CTRL1_REGISTER *) &OrMask)->AltVidStart = (UINT32) ((PSTATE_MSR *) &MsrRegister)->CpuVid;
- ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
-
- // Set up Altvid slam time
- ProcessorPackageType = LibAmdGetPackageType (StdHeader);
- PciAddress.Address.Register = CPTC2_REG;
- VsSlamTime = F10CalculateAltvidVSSlamTimeOnCore (PviModeFlag, &PciAddress, CpuEarlyParams, StdHeader);
- AndMask = 0xFFFFFFFF;
- ((CLK_PWR_TIMING_CTRL2_REGISTER *) &AndMask)->AltvidVSSlamTime = 0;
- ((CLK_PWR_TIMING_CTRL2_REGISTER *) &AndMask)->SlamTimeMode = 0;
- OrMask = 0x00000000;
- ((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->AltvidVSSlamTime = VsSlamTime;
- if (ProcessorPackageType == PACKAGE_TYPE_S1G3_S1G4 || ProcessorPackageType == PACKAGE_TYPE_ASB2) {
- // If CPUID Fn8000_0001_EBX[PkgType]=0010b or 0100b, BIOS should program this to 10b;
- // else BIOS should leave this field at 00b.
- ((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->SlamTimeMode = 2;
- }
- ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
- }
-
- if (IsWarmReset (StdHeader) && !PviModeFlag) {
- // Configure PsiVid
- F10PmVrmLowPowerModeEnable (FamilySpecificServices, CpuEarlyParams, PciAddress, StdHeader);
- }
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Support routine for F10CpuAmdPmPwrPlaneInit.
- *
- * This function implements step 1 on each core.
- *
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-STATIC
-F10PmPwrPlaneInitPviCore (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 MsrAddr;
- UINT32 NbVid;
- UINT32 CpuVid;
- UINT64 MsrRegister;
-
- for (MsrAddr = PS_REG_BASE; MsrAddr <= PS_MAX_REG; MsrAddr++) {
- LibAmdMsrRead (MsrAddr, &MsrRegister, StdHeader);
- if (((PSTATE_MSR *) &MsrRegister)->PsEnable == (UINT64) 1) {
- NbVid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->NbVid);
- CpuVid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuVid);
- if (NbVid != CpuVid) {
- if (NbVid > CpuVid) {
- NbVid = CpuVid;
- }
- ((PSTATE_MSR *) &MsrRegister)->NbVid = NbVid;
- ((PSTATE_MSR *) &MsrRegister)->CpuVid = NbVid;
- LibAmdMsrWrite (MsrAddr, &MsrRegister, StdHeader);
- }
- }
- }
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns the encoded altvid voltage stabilization slam time for the executing
- * family 10h core.
- *
- * This function calculates how much time it will take for the voltage to
- * stabilize when transitioning from altvid to Pmin, and returns the necessary
- * encoded value for the amount of time discovered.
- *
- * @param[in] PviModeFlag Whether or not the platform uses VRMs that
- * employ the parallel VID interface.
- * @param[in] PciAddress Full PCI address of the executing core's config space.
- * @param[in] CpuEarlyParams Service parameters
- * @param[in] StdHeader Config handle for library and services.
- *
- * @retval Encoded register value.
- *
- */
-UINT32
-STATIC
-F10CalculateAltvidVSSlamTimeOnCore (
- IN BOOLEAN PviModeFlag,
- IN PCI_ADDR *PciAddress,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 NbVid;
- UINT8 AltVidCode;
- UINT8 PminVidCode;
- UINT32 MsrAddr;
- UINT32 PciRegister;
- UINT64 MsrRegister;
- PCI_ADDR LocalPciAddress;
-
- // Calculate Slam Time
- // VSSlamTime = 0.4us/mV (or 0.2us/mV) * Vpmin - Altvid
- // In our case, we will scale the values by 100 to avoid
- // decimals.
-
- // Get Pmin's index
- LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrRegister, StdHeader);
- MsrAddr = (UINT32) ((((PSTATE_CURLIM_MSR *) &MsrRegister)->PstateMaxVal) + PS_REG_BASE);
-
- // Get Pmin's VID
- LibAmdMsrRead (MsrAddr, &MsrRegister, StdHeader);
- PminVidCode = (UINT8) (((PSTATE_MSR *) &MsrRegister)->CpuVid);
-
- // If SVI, we only care about CPU VID.
- // If PVI, determine the higher voltage b/t NB and CPU
- if (PviModeFlag) {
- NbVid = (UINT8) (((PSTATE_MSR *) &MsrRegister)->NbVid);
- if (PminVidCode > NbVid) {
- PminVidCode = NbVid;
- }
- }
-
- // Get Alt VID
- LocalPciAddress.AddressValue = PciAddress->AddressValue;
- LocalPciAddress.Address.Function = FUNC_3;
- LocalPciAddress.Address.Register = CPTC2_REG;
- LibAmdPciRead (AccessWidth32, LocalPciAddress, &PciRegister, StdHeader);
- AltVidCode = (UINT8) (((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->AltVid);
-
- return (F10GetSlamTimeEncoding (PminVidCode, AltVidCode, CpuEarlyParams, AltvidSlamTime, StdHeader));
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Sets up PSI_L operation.
- *
- * This function implements the LowPowerThreshold parameter.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] CpuEarlyParams Contains VrmLowPowerThreshold parameter.
- * @param[in] PciAddress PCI address of the executing core's config space.
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-STATIC
-F10PmVrmLowPowerModeEnable (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
- IN PCI_ADDR PciAddress,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Pstate;
- UINT32 PstateCurrent;
- UINT32 NextPstateCurrent;
- UINT32 AndMask;
- UINT32 OrMask;
- UINT32 PreviousVID;
- UINT32 PstateVID;
- UINT32 HwPsMaxVal;
- UINT64 PstateMsr;
- BOOLEAN EnablePsi;
-
- if (CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].LowPowerThreshold != 0) {
- EnablePsi = FALSE;
- PreviousVID = 0x7F; // Initialize to invalid zero volt VID code
- PstateVID = 0x7F;
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = CPTC2_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &HwPsMaxVal, StdHeader);
-
- for (Pstate = 0; Pstate <= (UINT32) ((CLK_PWR_TIMING_CTRL2_REGISTER *) &HwPsMaxVal)->PstateMaxVal; Pstate++) {
- if (FamilySpecificServices->GetProcIddMax (FamilySpecificServices, (UINT8) Pstate, &PstateCurrent, StdHeader)) {
- LibAmdMsrRead ((UINT32) (Pstate + PS_REG_BASE), &PstateMsr, StdHeader);
- PstateVID = (UINT32) (((PSTATE_MSR *) &PstateMsr)->CpuVid);
- if ((Pstate + 1) > (UINT32) ((CLK_PWR_TIMING_CTRL2_REGISTER *) &HwPsMaxVal)->PstateMaxVal) {
- NextPstateCurrent = 0;
- } else if (FamilySpecificServices->GetProcIddMax (FamilySpecificServices, (UINT8) (Pstate + 1), &NextPstateCurrent, StdHeader)) {
- NextPstateCurrent = CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].InrushCurrentLimit + NextPstateCurrent;
- }
- if ((PstateCurrent <= CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].LowPowerThreshold) && (NextPstateCurrent <= CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].LowPowerThreshold) && (PstateVID != PreviousVID)) {
- EnablePsi = TRUE;
- break;
- }
- PreviousVID = PstateVID;
- }
- }
-
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = PW_CTL_MISC_REG;
- AndMask = 0xFFFFFFFF;
- OrMask = 0x00000000;
- ((POWER_CTRL_MISC_REGISTER *) &AndMask)->PsiVid = 0;
- if (EnablePsi) {
- ((POWER_CTRL_MISC_REGISTER *) &OrMask)->PsiVid = PstateVID;
- ((POWER_CTRL_MISC_REGISTER *) &OrMask)->PsiVidEn = 1;
- } else {
- ((POWER_CTRL_MISC_REGISTER *) &AndMask)->PsiVidEn = 0;
- }
- ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10PowerPlane.h b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10PowerPlane.h
deleted file mode 100644
index 8c4860c..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10PowerPlane.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Power Plane related functions and structures
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F10
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPU_F10_POWER_PLANE_H_
-#define _CPU_F10_POWER_PLANE_H_
-
-
-/*---------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *---------------------------------------------------------------------------------------
- */
-VOID
-F10CpuAmdPmPwrPlaneInit (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif // _CPU_F10_POWER_PLANE_H_
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10Pstate.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10Pstate.c
deleted file mode 100644
index ed476a1..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10Pstate.c
+++ /dev/null
@@ -1,863 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Pstate feature support functions.
- *
- * Provides the functions necessary to initialize the Pstate feature.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F10
- * @e \$Revision: 37640 $ @e \$Date: 2010-09-08 23:01:59 +0800 (Wed, 08 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "GeneralServices.h"
-#include "cpuPstateTables.h"
-#include "Table.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuFamRegisters.h"
-#include "cpuF10Utilities.h"
-#include "cpuF10PowerMgmt.h"
-#include "CommonReturns.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10PSTATE_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-VOID
-STATIC
-F10GetPowerStepValueInTime (
- IN OUT UINT32 *PowerStepPtr
- );
-
-VOID
-STATIC
-F10GetPllValueInTime (
- IN OUT UINT32 *PllLockTimePtr
- );
-
-AGESA_STATUS
-STATIC
-F10GetFrequencyXlatRegInfo (
- IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
- IN UINT8 PStateNumber,
- IN UINT32 Frequency,
- OUT UINT32 *CpuFidPtr,
- OUT UINT32 *CpuDidPtr1,
- OUT UINT32 *CpuDidPtr2,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-extern BUILD_OPT_CFG UserOptions;
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family specific call to check if Pstate PSD is dependent.
- *
- * @param[in] PstateCpuServices Pstate CPU services.
- * @param[in,out] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval TRUE PSD is dependent.
- * @retval FALSE PSD is independent.
- *
- */
-BOOLEAN
-STATIC
-F10IsPstatePsdDependent (
- IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
- IN OUT PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- CPU_LOGICAL_ID CpuLogicalId;
- PLATFORM_FEATS Features;
-
- // Initialize the union
- Features.PlatformValue = 0;
- GetLogicalIdOfCurrentCore (&CpuLogicalId, StdHeader);
- GetPlatformFeatures (&Features, PlatformConfig, StdHeader);
-
- //
- // RevC Single link has PSD option, default is dependent.
- // If multi-link, always return independent.
- //
- if ((Features.PlatformFeatures.PlatformSingleLink) && ((CpuLogicalId.Revision & AMD_F10_Cx) != 0)) {
- if (PlatformConfig->ForcePstateIndependent) {
- return FALSE;
- }
- return TRUE;
- }
- return FALSE;
-}
-
-/**
- * Family specific call to set core TscFreqSel.
- *
- * @param[in] PstateCpuServices Pstate CPU services.
- * @param[in] StdHeader Config Handle for library, services.
- *
- */
-VOID
-STATIC
-F10SetTscFreqSel (
- IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 MsrValue;
-
- LibAmdMsrRead (MSR_HWCR, &MsrValue, StdHeader);
- if (UserOptions.OptionMultisocket) {
- //
- // If Agesa need to do p-state leveling on multi-socket, changing the P0
- // frequency after setting this bit has no effect on the TSC rate.
- //
- ASSERT ((MsrValue & BIT24) == 0);
- }
- MsrValue = MsrValue | BIT24;
- LibAmdMsrWrite (MSR_HWCR, &MsrValue, StdHeader);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family specific call to get Pstate Transition Latency.
- *
- * Calculate TransitionLatency by power step value and pll value.
- *
- * @param[in] PstateCpuServices Pstate CPU services.
- * @param[in] PStateLevelingBufferStructPtr Pstate row data buffer pointer
- * @param[in] PciAddress Pci address
- * @param[out] TransitionLatency The transition latency.
- * @param[in] StdHeader Header for library and services
- *
- * @retval AGESA_SUCCESS Always succeeds.
- */
-AGESA_STATUS
-F10GetPstateTransLatency (
- IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
- IN PSTATE_LEVELING *PStateLevelingBufferStructPtr,
- IN PCI_ADDR *PciAddress,
- OUT UINT32 *TransitionLatency,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 TempVar_b;
- UINT32 TempVar_c;
- UINT32 TempVar_d;
- UINT32 TempVar8_a;
- UINT32 TempVar8_b;
- UINT32 Ignored;
- UINT32 k;
- UINT32 CpuFidSameFlag;
- UINT8 PStateMaxValueOnCurrentCore;
- UINT32 TransAndBusMastLatency;
-
- CpuFidSameFlag = 1;
-
- F10GetFrequencyXlatRegInfo (
- PstateCpuServices,
- 0,
- PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateStruct[0].CoreFreq,
- &TempVar_b,
- &TempVar_c,
- &Ignored,
- StdHeader
- );
-
- TempVar_d = TempVar_b;
- PStateMaxValueOnCurrentCore = PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateMaxValue;
-
- //
- //Check if MSRC001_00[68:64][CpuFid] is the same value for all P-states where
- //MSRC001_00[68:64][PstateEn]=1
- //
- for (k = 1; k <= PStateMaxValueOnCurrentCore; k++) {
- if (PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateStruct[k].PStateEnable != 0) {
- F10GetFrequencyXlatRegInfo (
- PstateCpuServices,
- (UINT8) k,
- PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateStruct[k].CoreFreq,
- &TempVar_b,
- &TempVar_c,
- &Ignored,
- StdHeader
- );
- }
-
- if (TempVar_d != TempVar_b) {
- CpuFidSameFlag = 0;
- break;
- }
- }
-
- PciAddress->Address.Register = 0xD4;
- PciAddress->Address.Function = FUNC_3;
- LibAmdPciRead (AccessWidth32, *PciAddress, &TempVar_d, StdHeader);
-
- // PowerStepDown - Bits 20:23
- TempVar8_a = (TempVar_d & 0x00F00000) >> 20;
-
- // PowerStepUp - Bits 24:27
- TempVar8_b = (TempVar_d & 0x0F000000) >> 24;
-
- // Convert the raw numbers in TempVar8_a and TempVar8_b into time
- F10GetPowerStepValueInTime (&TempVar8_a);
- F10GetPowerStepValueInTime (&TempVar8_b);
-
- //
- //(12 * (F3xD4[PowerStepDown] + F3xD4[PowerStepUp]) /1000) us
- //
- TransAndBusMastLatency =
- (12 * (TempVar8_a + TempVar8_b) + 999) / 1000;
-
- if (CpuFidSameFlag == 0) {
- //
- //+ F3xA0[PllLockTime]
- //
- PciAddress->Address.Register = 0xA0;
- LibAmdPciRead (AccessWidth32, *PciAddress, &TempVar_d, StdHeader);
-
- TempVar8_a = (0x00003800 & TempVar_d) >> 11;
- F10GetPllValueInTime (&TempVar8_a);
- TransAndBusMastLatency += TempVar8_a;
- }
-
- *TransitionLatency = TransAndBusMastLatency;
-
- return (AGESA_SUCCESS);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family specific call to calculates the frequency in megahertz of the desired P-state.
- *
- * @param[in] PstateCpuServices Pstate CPU services.
- * @param[in] StateNumber The P-State to analyze.
- * @param[out] FrequencyInMHz The P-State's frequency in MegaHertz
- * @param[in] StdHeader Header for library and services
- *
- * @retval AGESA_SUCCESS Always Succeeds.
- */
-AGESA_STATUS
-F10GetPstateFrequency (
- IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
- IN UINT8 StateNumber,
- OUT UINT32 *FrequencyInMHz,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 TempValue;
- UINT32 CpuDid;
- UINT32 CpuFid;
- UINT64 MsrRegister;
-
- ASSERT (StateNumber < NM_PS_REG);
- LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
- ASSERT (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1);
- CpuDid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuDid);
- CpuFid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuFid);
-
- switch (CpuDid) {
- case 0:
- TempValue = 1;
- break;
- case 1:
- TempValue = 2;
- break;
- case 2:
- TempValue = 4;
- break;
- case 3:
- TempValue = 8;
- break;
- case 4:
- TempValue = 16;
- break;
- default:
- // CpuDid is set to an undefined value. This is due to either a misfused CPU, or
- // an invalid P-state MSR write.
- ASSERT (FALSE);
- TempValue = 1;
- break;
- }
- *FrequencyInMHz = (100 * (CpuFid + 0x10) / TempValue);
- return (AGESA_SUCCESS);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family specific call to sets the Pstate MSR to each APs base on Pstate Buffer.
- *
- * @param[in] PstateCpuServices Pstate CPU services.
- * @param[in] CpuAmdPState Gathered P-state data structure for whole system.
- * @param[in] StdHeader Config for library and services.
- *
- * @retval AGESA_SUCCESS Always succeeds.
- *
- */
-AGESA_STATUS
-F10PstateLevelingCoreMsrModify (
- IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
- IN S_CPU_AMD_PSTATE *CpuAmdPState,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 i;
- UINT32 Ignored;
- UINT32 k;
- UINT32 TempVar_d;
- UINT32 TempVar_e;
- UINT32 TempVar_f;
- UINT32 LogicalSocketCount;
- UINT32 PciRegister;
- UINT32 Socket;
- UINT32 Module;
- UINT32 Core;
- UINT64 MsrValue;
- AGESA_STATUS Status;
- PSTATE_LEVELING *PStateBufferPtr;
- PSTATE_LEVELING *PStateBufferPtrTmp;
- S_CPU_AMD_PSTATE *CpuAmdPstatePtr;
- PCI_ADDR PciAddress;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
-
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
- ASSERT (FamilySpecificServices != NULL);
-
- Ignored = 0;
- CpuAmdPstatePtr = (S_CPU_AMD_PSTATE *) CpuAmdPState;
- PStateBufferPtrTmp = CpuAmdPstatePtr->PStateLevelingStruc;
- PStateBufferPtr = CpuAmdPstatePtr->PStateLevelingStruc;
- LogicalSocketCount = CpuAmdPstatePtr->TotalSocketInSystem;
- PciAddress.AddressValue = 0;
-
- //
- //Try to find the Pstate buffer specific to this core(socket).
- //
- IdentifyCore (StdHeader, &Socket, &Module, &Core, &Status);
- for (i = 0; i < LogicalSocketCount; i++) {
- CpuGetPStateLevelStructure (&PStateBufferPtrTmp, CpuAmdPstatePtr, i, StdHeader);
- if (PStateBufferPtrTmp->SocketNumber == Socket) {
- break;
- }
- }
-
- if (PStateBufferPtr[0].OnlyOneEnabledPState) {
- //
- //If all processors have only 1 enabled P-state, the following sequence should be performed on all cores:
- //
-
- //1. Write the appropriate CpuFid value resulting from the matched CPU COF to MSRC001_0064[CpuFid].
- LibAmdMsrRead (MSR_PSTATE_0, &MsrValue, StdHeader);
- Status = F10GetFrequencyXlatRegInfo (PstateCpuServices, 0, PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].CoreFreq, &TempVar_d, &TempVar_e, &Ignored, StdHeader);
- // Bits 5:0
- ((PSTATE_MSR *) &MsrValue)->CpuFid = TempVar_d;
- // Bits 8:6
- ((PSTATE_MSR *) &MsrValue)->CpuDid = TempVar_e;
- // Bits 39:32
- ((PSTATE_MSR *) &MsrValue)->IddValue = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].IddValue;
- // Bits 41:40
- ((PSTATE_MSR *) &MsrValue)->IddDiv = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].IddDiv;
- // Enable the P-State
- ((PSTATE_MSR *) &MsrValue)->PsEnable = 1;
- LibAmdMsrWrite (MSR_PSTATE_0, &MsrValue, StdHeader);
-
- //2. Copy MSRC001_0064 to MSRC001_0065.
- LibAmdMsrWrite (MSR_PSTATE_1, &MsrValue, StdHeader);
-
- //3. Write 001b to F3xDC[PstatemaxVal].
- GetPciAddress (StdHeader, Socket, Module, &PciAddress, &Status);
- PciAddress.Address.Register = CPTC2_REG;
- PciAddress.Address.Function = FUNC_3;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal = 1;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
-
- //4. Write 001b to MSRC001_0062[PstateCmd].
- FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 1, (BOOLEAN) FALSE, StdHeader);
-
- //5. Wait for MSRC001_0071[CurCpuFid] = MSRC001_0065[CpuFid].
- do {
- LibAmdMsrRead (MSR_COFVID_STS, &MsrValue, StdHeader);
- } while (((COFVID_STS_MSR *) &MsrValue)->CurCpuFid != TempVar_d);
-
- //6. Write 000b to MSRC001_0062[PstateCmd].
- FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) FALSE, StdHeader);
-
- //7. Wait for MSRC001_0071[CurCpuFid] = MSRC001_0064[CpuFid].
- do {
- LibAmdMsrRead (MSR_COFVID_STS, &MsrValue, StdHeader);
- } while (((COFVID_STS_MSR *) &MsrValue)->CurCpuFid != TempVar_d);
-
- //8. Write 0b to MSRC001_0065[PstateEn].
- LibAmdMsrRead (MSR_PSTATE_1, &MsrValue, StdHeader);
- ((PSTATE_MSR *) &MsrValue)->PsEnable = 0;
- LibAmdMsrWrite (MSR_PSTATE_1, &MsrValue, StdHeader);
-
- //9. Write 000b to F3xDC[PstateMaxVal] and exit the sequence (no further steps are required).
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal = 0;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
-
- } else {
- TempVar_f = MSR_PSTATE_0;
-
- for (k = 0; k <= PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue; k++, TempVar_f++) {
- // If pState is not disabled then do update
- LibAmdMsrRead (TempVar_f, &MsrValue, StdHeader);
-
- if (PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].PStateEnable == 1) {
- Status = F10GetFrequencyXlatRegInfo (PstateCpuServices, (UINT8) k, PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].CoreFreq, &TempVar_d, &TempVar_e, &Ignored, StdHeader);
- if (Status != AGESA_ERROR) {
- // Bits 5:0
- ((PSTATE_MSR *) &MsrValue)->CpuFid = TempVar_d;
- // Bits 8:6
- ((PSTATE_MSR *) &MsrValue)->CpuDid = TempVar_e;
- }
-
- // Bits 39:32
- ((PSTATE_MSR *) &MsrValue)->IddValue = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].IddValue;
- // Bits 41:40
- ((PSTATE_MSR *) &MsrValue)->IddDiv = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].IddDiv;
- // Enable the P-State
- ((PSTATE_MSR *) &MsrValue)->PsEnable = 1;
- LibAmdMsrWrite (TempVar_f, &MsrValue, StdHeader);
- } else {
- // Disable the P-State
- ((PSTATE_MSR *) &MsrValue)->PsEnable = 0;
- LibAmdMsrWrite (TempVar_f, &MsrValue, StdHeader);
- }
- }
- }
- return AGESA_SUCCESS;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family specific call to calculates the power in milliWatts of the desired P-state.
- *
- * @param[in] PstateCpuServices Pstate CPU services.
- * @param[in] StateNumber Which P-state to analyze
- * @param[out] PowerInMw The Power in milliWatts of that P-State
- * @param[in] StdHeader Header for library and services
- *
- * @retval AGESA_SUCCESS Always succeeds.
- */
-AGESA_STATUS
-F10GetPstatePower (
- IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
- IN UINT8 StateNumber,
- OUT UINT32 *PowerInMw,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 CpuVid;
- UINT32 IddValue;
- UINT32 IddDiv;
- UINT32 Socket;
- UINT32 Module;
- UINT32 Ignored;
- BOOLEAN PviFlag;
- UINT32 V_x10000;
- UINT32 Power;
- PCI_ADDR PciAddress;
- UINT32 TempVar_a;
- UINT64 MsrRegister;
- AGESA_STATUS IgnoredSts;
-
- ASSERT (StateNumber < NM_PS_REG);
- LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
- ASSERT (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1);
- CpuVid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuVid);
- IddValue = (UINT32) (((PSTATE_MSR *) &MsrRegister)->IddValue);
- IddDiv = (UINT32) (((PSTATE_MSR *) &MsrRegister)->IddDiv);
-
- IdentifyCore (StdHeader, &Socket, &Module, &Ignored, &IgnoredSts);
- GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
-
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = POWER_CTRL_MISCELLANEOUS_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &TempVar_a, StdHeader);
- if ((TempVar_a & 0x00000100) != 0) {
- PviFlag = TRUE;
- } else {
- PviFlag = FALSE;
- }
- if (PviFlag) {
- // Set CpuVid value in case CPU is in PVI mode
- if (CpuVid > 0x5D) {
- CpuVid = 0x3F;
- } else if (CpuVid > 0x3E) {
- CpuVid = CpuVid - 0x1F;
- } else {
- CpuVid = (CpuVid >> 1);
- }
-
- // PVI Encoding
- if (CpuVid >= 0x20) {
- V_x10000 = 7625L - (125L * (CpuVid - 0x20));
- } else {
- V_x10000 = 15500L - (250L * CpuVid);
- }
- } else {
- if (CpuVid >= 0x7C) {
- V_x10000 = 0;
- } else {
- V_x10000 = 15500L - (125L * CpuVid);
- }
- }
-
- Power = V_x10000 * IddValue;
-
- switch (IddDiv) {
- case 0:
- *PowerInMw = Power / 10L;
- break;
- case 1:
- *PowerInMw = Power / 100L;
- break;
- case 2:
- *PowerInMw = Power / 1000L;
- break;
- default:
- // IddDiv is set to an undefined value. This is due to either a misfused CPU, or
- // an invalid P-state MSR write.
- ASSERT (FALSE);
- *PowerInMw = 0;
- break;
- }
- return (AGESA_SUCCESS);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family specific call to get CPU pstate max state.
- *
- * @param[in] PstateCpuServices Pstate CPU services.
- * @param[out] MaxPStateNumber Boolean flag return pstate enable.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @retval AGESA_SUCCESS Always succeeds.
- */
-AGESA_STATUS
-F10GetPstateMaxState (
- IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
- OUT UINT32 *MaxPStateNumber,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 MsrValue;
- UINT32 PciRegister;
- PCI_ADDR PciAddress;
- CPUID_DATA CpuidData;
-
- PciRegister = 0;
-
- // Check if CPB is supported. if yes, skip boosted p-state. The boosted p-state number = F4x15C[NumBoostStates].
- LibAmdCpuidRead (AMD_CPUID_APM, &CpuidData, StdHeader);
- if (((CpuidData.EDX_Reg & 0x00000200) >> 9) == 1) {
- PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // F4x15C
- }
-
- //
- // Read PstateMaxVal [6:4] from MSR C001_0061
- // So, we will know the max pstate state in this socket.
- //
- LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrValue, StdHeader);
- *MaxPStateNumber = (UINT32) (((PSTATE_CURLIM_MSR *) &MsrValue)->PstateMaxVal) + (UINT32) (((CPB_CTRL_REGISTER *) &PciRegister)->NumBoostStates);
-
- return (AGESA_SUCCESS);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family specific call to get CPU pstate register information.
- *
- * @param[in] PstateCpuServices Pstate CPU services.
- * @param[in] PState Input Pstate number for query.
- * @param[out] PStateEnabled Boolean flag return pstate enable.
- * @param[in,out] IddVal Pstate current value.
- * @param[in,out] IddDiv Pstate current divisor.
- * @param[out] SwPstateNumber Software P-state number.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @retval AGESA_SUCCESS Always succeeds.
- */
-AGESA_STATUS
-F10GetPstateRegisterInfo (
- IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
- IN UINT32 PState,
- OUT BOOLEAN *PStateEnabled,
- IN OUT UINT32 *IddVal,
- IN OUT UINT32 *IddDiv,
- OUT UINT32 *SwPstateNumber,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 MsrRegister;
- UINT32 PciRegister;
- PCI_ADDR PciAddress;
- CPUID_DATA CpuidData;
-
- PciRegister = 0;
- ASSERT (PState < NM_PS_REG);
-
- // Check if CPB is supported. if yes, skip boosted p-state. The boosted p-state number = F4x15C[NumBoostStates].
- LibAmdCpuidRead (AMD_CPUID_APM, &CpuidData, StdHeader);
- if (((CpuidData.EDX_Reg & 0x00000200) >> 9) == 1) {
- PciAddress.AddressValue = CPB_CTRL_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // F4x15C
- }
-
- *SwPstateNumber = PState;
-
- // Read PSTATE MSRs
- LibAmdMsrRead (PS_REG_BASE + (UINT32) PState, &MsrRegister, StdHeader);
-
- if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
- // PState enable = bit 63
- *PStateEnabled = TRUE;
- // Check input pstate belongs to Boosted-Pstate, if yes, return *PStateEnabled = FALSE.
- if (PState < ((CPB_CTRL_REGISTER *) &PciRegister)->NumBoostStates) {
- *PStateEnabled = FALSE;
- } else {
- *SwPstateNumber = PState - ((CPB_CTRL_REGISTER *) &PciRegister)->NumBoostStates;
- }
- } else {
- *PStateEnabled = FALSE;
- }
-
- // Bits 39:32 (high 32 bits [7:0])
- *IddVal = (UINT32) ((PSTATE_MSR *) &MsrRegister)->IddValue;
- // Bits 41:40 (high 32 bits [9:8])
- *IddDiv = (UINT32) ((PSTATE_MSR *) &MsrRegister)->IddDiv;
-
- return (AGESA_SUCCESS);
-}
-
-CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F10PstateServices =
-{
- 0,
- (PF_PSTATE_PSD_IS_NEEDED) CommonReturnTrue,
- F10IsPstatePsdDependent,
- F10SetTscFreqSel,
- F10GetPstateTransLatency,
- F10GetPstateFrequency,
- F10PstateLevelingCoreMsrModify,
- F10GetPstatePower,
- F10GetPstateMaxState,
- F10GetPstateRegisterInfo
-};
-
-
-/*---------------------------------------------------------------------------------------
- * L O C A L F U N C T I O N S
- *---------------------------------------------------------------------------------------
- */
-
-
-/**
- *---------------------------------------------------------------------------------------
- *
- * F10GetPowerStepValueInTime
- *
- * Description:
- * Convert power step value in time
- *
- * Parameters:
- * @param[out] *PowerStepPtr
- *
- * @retval VOID
- *
- *---------------------------------------------------------------------------------------
- **/
-VOID
-STATIC
-F10GetPowerStepValueInTime (
- IN OUT UINT32 *PowerStepPtr
- )
-{
- UINT32 TempVar_a;
-
- TempVar_a = *PowerStepPtr;
-
- if (TempVar_a < 0x4) {
- *PowerStepPtr = 400 - (TempVar_a * 100);
- } else if (TempVar_a < 0x9) {
- *PowerStepPtr = 130 - (TempVar_a * 10);
- } else {
- *PowerStepPtr = 90 - (TempVar_a * 5);
- }
-}
-
-
-/**
- *---------------------------------------------------------------------------------------
- *
- * F10GetPllValueInTime
- *
- * Description:
- * Convert PLL Value in time
- *
- * Parameters:
- * @param[out] *PllLockTimePtr
- *
- * @retval VOID
- *
- *---------------------------------------------------------------------------------------
- **/
-VOID
-STATIC
-F10GetPllValueInTime (
- IN OUT UINT32 *PllLockTimePtr
- )
-{
- if (*PllLockTimePtr < 4) {
- *PllLockTimePtr = *PllLockTimePtr + 1;
- } else if (*PllLockTimePtr == 4) {
- *PllLockTimePtr = 8;
- } else if (*PllLockTimePtr == 5) {
- *PllLockTimePtr = 16;
- } else
- *PllLockTimePtr = 0;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * This function will return the CpuFid and CpuDid in MHz, using the formula
- * described in the BKDG MSRC001_00[68:64] P-State [4:0] Registers:bit 8:0
- *
- * @param[in] PstateCpuServices The current Family Specific Services.
- * @param[in] PStateNumber P-state number to check.
- * @param[in] Frequency Leveled target frequency for PStateNumber.
- * @param[out] *CpuFidPtr New leveled FID.
- * @param[out] *CpuDidPtr1 New leveled DID info 1.
- * @param[out] *CpuDidPtr2 New leveled DID info 2.
- * @param[in] *StdHeader Header for library and services.
- *
- * @retval AGESA_WARNING This P-State does not need to be modified.
- * @retval AGESA_SUCCESS This P-State must be modified to be level.
- */
-AGESA_STATUS
-STATIC
-F10GetFrequencyXlatRegInfo (
- IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
- IN UINT8 PStateNumber,
- IN UINT32 Frequency,
- OUT UINT32 *CpuFidPtr,
- OUT UINT32 *CpuDidPtr1,
- OUT UINT32 *CpuDidPtr2,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 i;
- UINT32 j;
- AGESA_STATUS Status;
- UINT32 FrequencyInMHz;
-
- FrequencyInMHz = 0;
- *CpuDidPtr2 = 0xFFFF;
-
- Status = AGESA_SUCCESS;
-
- PstateCpuServices->GetPstateFrequency (PstateCpuServices, PStateNumber, &FrequencyInMHz, StdHeader);
- if (FrequencyInMHz == Frequency) {
- Status |= AGESA_WARNING;
- }
-
- // CPU Frequency = 100 MHz * (CpuFid + 10h) / (2^CpuDid)
- // In this for loop i = 2^CpuDid
-
-
- for (i = 1; i < 17; (i += i)) {
- for (j = 0; j < 64; j++) {
- if (Frequency == ((100 * (j + 0x10)) / i )) {
- *CpuFidPtr = j;
- if (i == 1) {
- *CpuDidPtr1 = 0;
- } else if (i == 2) {
- *CpuDidPtr1 = 1;
- } else if (i == 4) {
- *CpuDidPtr1 = 2;
- } else if (i == 8) {
- *CpuDidPtr1 = 3;
- } else if (i == 16) {
- *CpuDidPtr1 = 4;
- } else {
- *CpuFidPtr = 0xFFFF;
- *CpuDidPtr1 = 0xFFFF;
- }
- // Success
- return Status;
- }
- }
- }
-
- // Error Condition
- *CpuFidPtr = 0x00FF;
- *CpuDidPtr1 = 0x00FF;
- *CpuDidPtr2 = 0x00FF;
-
- return AGESA_ERROR;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c
deleted file mode 100644
index fdde8eb..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 thermal initialization
- *
- * Performs processor thermal initialization.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "cpuRegisters.h"
-#include "GeneralServices.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuF10PowerMgmt.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10SOFTWARETHERMAL_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Main entry point for initializing the Thermal Control
- * safety net feature.
- *
- * This must be run by all Family 10h core 0s in the system.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] CpuEarlyParamsPtr Service parameters.
- * @param[in] StdHeader Config handle for library and services.
- */
-VOID
-F10PmThermalInit (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Core;
- UINT32 Module;
- UINT32 PciRegister;
- UINT32 Socket;
- PCI_ADDR PciAddress;
- AGESA_STATUS IgnoredSts;
-
- IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
- ASSERT (Core == 0);
-
- if (GetPciAddress (StdHeader, Socket, 0, &PciAddress, &IgnoredSts)) {
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = NB_CAPS_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- if (((NB_CAPS_REGISTER *) &PciRegister)->HtcCapable == 1) {
- // Enable HTC
- PciAddress.Address.Register = HTC_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- ((HTC_REGISTER *) &PciRegister)->HtcSlewSel = 0;
- ((HTC_REGISTER *) &PciRegister)->HtcEn = 1;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- }
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.h b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.h
deleted file mode 100644
index ff1c664..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10SoftwareThermal.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 thermal initialization related functions and structures
- *
- * Performs processor thermal initialization.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F10
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPU_F10_SOFTWARE_THERMAL_H_
-#define _CPU_F10_SOFTWARE_THERMAL_H_
-
-
-/*---------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *---------------------------------------------------------------------------------------
- */
-VOID
-F10PmThermalInit (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif // _CPU_F10_SOFTWARE_THERMAL_H_
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10Utilities.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10Utilities.c
deleted file mode 100644
index df6e58b..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10Utilities.c
+++ /dev/null
@@ -1,1119 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 specific utility functions.
- *
- * Provides numerous utility functions specific to family 10h.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F10
- * @e \$Revision: 37150 $ @e \$Date: 2010-08-31 23:53:37 +0800 (Tue, 31 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuPstateTables.h"
-#include "cpuF10PowerMgmt.h"
-#include "cpuApicUtilities.h"
-#include "cpuServices.h"
-#include "GeneralServices.h"
-#include "cpuF10Utilities.h"
-#include "cpuPostInit.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10UTILITIES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-// Register encodings for F3xD8[VSRampTime/VSSlamTime]
-CONST UINT32 ROMDATA VSSlamTime[8] =
-{
- 10, // 000b: 10us
- 20, // 001b: 20us
- 30, // 010b: 30us
- 40, // 011b: 40us
- 60, // 100b: 60us
- 100, // 101b: 100us
- 200, // 110b: 200us
- 500 // 111b: 500us
-};
-
-extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable;
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Performs the necessary steps for the 'Software Initiated CPU
- * Voltage Transitions.'
- *
- * @param[in] VidCode VID code to transition to
- * @param[in] StdHeader Header for library and services
- *
- */
-VOID
-F10PmSwVoltageTransition (
- IN UINT32 VidCode,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 PciRegister;
- UINT32 Socket;
- UINT32 Module;
- UINT32 Ignored;
- UINT64 MsrRegister;
- PCI_ADDR PciAddress;
- AGESA_STATUS IgnoredSts;
-
- IdentifyCore (StdHeader, &Socket, &Module, &Ignored, &IgnoredSts);
- GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
-
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = PW_CTL_MISC_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- if (((POWER_CTRL_MISC_REGISTER *) &PciRegister)->SlamVidMode == 1) {
- LibAmdMsrRead (MSR_COFVID_CTL, &MsrRegister, StdHeader);
- ((COFVID_CTRL_MSR *) &MsrRegister)->CpuVid = VidCode;
- LibAmdMsrWrite (MSR_COFVID_CTL, &MsrRegister, StdHeader);
- F10WaitOutVoltageTransition (TRUE, StdHeader);
- } else
- return;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Performs the necessary steps for the 'Software Initiated NB
- * Voltage Transitions.'
- *
- * This can only be run by a local core 0.
- *
- * @param[in] VidCode VID code to transition to
- * @param[in] SlamMode Whether voltage is to be slammed, or stepped
- * @param[in] StdHeader Header for library and services
- *
- */
-VOID
-F10PmSwVoltageTransitionServerNb (
- IN UINT32 VidCode,
- IN BOOLEAN SlamMode,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Core;
- UINT32 NbVidStatus;
- UINT32 Socket;
- UINT32 IgnoredModule;
- UINT32 IgnoredCore;
- UINT32 CoreNum;
- AP_TASK TaskPtr;
- AGESA_STATUS IgnoredSts;
- SW_VOLT_TRANS_NB RemoteInput;
-
- RemoteInput.VidCode = VidCode;
- RemoteInput.SlamMode = SlamMode;
- TaskPtr.FuncAddress.PfApTaskIO = F10SwVoltageTransitionServerNbCore;
- TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (SW_VOLT_TRANS_NB);
- TaskPtr.DataTransfer.DataPtr = &RemoteInput;
- TaskPtr.DataTransfer.DataTransferFlags = 0;
- TaskPtr.ExeFlags = WAIT_FOR_CORE;
-
- IdentifyCore (StdHeader, &Socket, &IgnoredModule, &IgnoredCore, &IgnoredSts);
- GetActiveCoresInCurrentSocket (&CoreNum, StdHeader);
-
- do {
- NbVidStatus = TaskPtr.FuncAddress.PfApTaskIO (&RemoteInput, StdHeader);
- for (Core = 1; Core < (UINT8) CoreNum; Core++) {
- NbVidStatus |= ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)Core, &TaskPtr, StdHeader);
- }
- F10WaitOutVoltageTransition (SlamMode, StdHeader);
- } while (NbVidStatus != 0);
- return;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns current VsSlamTime in microseconds.
- *
- * @param[out] VsTimeUsecs Provides the wait time needed for a Slam Voltage transition.
- * @param[in] SlamMode Whether voltage is to be slammed, or stepped
- * @param[in] StdHeader Header for library and services
- *
- */
-VOID
-F10GetCurrentVsTimeInUsecs (
- OUT UINT32 *VsTimeUsecs,
- IN BOOLEAN SlamMode,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 RegisterEncoding;
- UINT32 PciRegister;
- UINT32 Socket;
- UINT32 Module;
- UINT32 Ignored;
- CONST UINT16 SlamTimes[8] = {10, 20, 30, 40, 60, 100, 200, 500};
- PCI_ADDR PciAddress;
- AGESA_STATUS IgnoredSts;
-
- IdentifyCore (StdHeader, &Socket, &Module, &Ignored, &IgnoredSts);
- GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
-
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = CPTC1_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
-
- if (SlamMode) {
- RegisterEncoding = (UINT8) ((CLK_PWR_TIMING_CTRL1_REGISTER *) &PciRegister)->VSSlamTime;
- } else {
- RegisterEncoding = (UINT8) ((CLK_PWR_TIMING_CTRL1_REGISTER *) &PciRegister)->VSRampTime;
- }
-
- *VsTimeUsecs = (UINT32) SlamTimes[RegisterEncoding];
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Spins until VsSlamTime microseconds have expired.
- *
- * @param[in] SlamMode Whether voltage is to be slammed, or stepped
- * @param[in] StdHeader Header for library and services
- *
- */
-VOID
-F10WaitOutVoltageTransition (
- IN BOOLEAN SlamMode,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 VsTimeUsecs;
-
- F10GetCurrentVsTimeInUsecs (&VsTimeUsecs, SlamMode, StdHeader);
- WaitMicroseconds (VsTimeUsecs, StdHeader);
- return;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Code required to be run on every local core in order to perform
- * the steps necessary for 'Software Initiated NB Voltage
- * Transitions.'
- *
- * @param[out] InputData Family specific data needed to perform a Voltage transition.
- * @param[in] StdHeader Header for library and services.
- *
- * @retval zero All Voltage Transitions are completed.
- * @retval one There are Voltage transitions remaining to reach target.
- *
- */
-UINT32
-F10SwVoltageTransitionServerNbCore (
- IN VOID *InputData,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 VidCode;
- UINT64 MsrRegister;
-
- if (((SW_VOLT_TRANS_NB *) InputData)->SlamMode) {
- VidCode = ((SW_VOLT_TRANS_NB *) InputData)->VidCode;
- } else {
- LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
- VidCode = (UINT32) (((COFVID_STS_MSR *) &MsrRegister)->CurNbVid);
- if (VidCode > ((SW_VOLT_TRANS_NB *) InputData)->VidCode) {
- --VidCode;
- } else if (VidCode < ((SW_VOLT_TRANS_NB *) InputData)->VidCode) {
- ++VidCode;
- }
- }
- LibAmdMsrRead (MSR_COFVID_CTL, &MsrRegister, StdHeader);
- ((COFVID_CTRL_MSR *) &MsrRegister)->NbVid = VidCode;
- LibAmdMsrWrite (MSR_COFVID_CTL, &MsrRegister, StdHeader);
-
- if (VidCode == ((SW_VOLT_TRANS_NB *) InputData)->VidCode) {
- return 0;
- } else {
- return 1;
- }
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Calculate and reprogram F3xD8[VSSlamTime] based on the algorithm in the BKDG.
- *
- * This function determines the largest voltage step that the core will have
- * to make, calculates how much time it will take for the voltage to stabilize,
- * and programs the necessary encoded value for the amount of time discovered.
- *
- * @param[in] PciAddress Segment/bus/device of a module on the socket
- * to program.
- * @param[in] CpuEarlyParams Service parameters
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-F10ProgramVSSlamTimeOnSocket (
- IN PCI_ADDR *PciAddress,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 NbVid;
- UINT8 P0VidCode;
- UINT8 PminVidCode;
- UINT32 AndMask;
- UINT32 MsrAddr;
- UINT32 OrMask;
- UINT32 PciRegister;
- UINT64 MsrRegister;
- BOOLEAN IsPviMode;
- PCI_ADDR LocalPciAddress;
-
- // Get F3xA0[PviMode]
- LocalPciAddress.AddressValue = PciAddress->AddressValue;
- LocalPciAddress.Address.Function = FUNC_3;
- LocalPciAddress.Address.Register = PW_CTL_MISC_REG;
- LibAmdPciRead (AccessWidth32, LocalPciAddress, &PciRegister, StdHeader);
- if (((POWER_CTRL_MISC_REGISTER *) &PciRegister)->PviMode == 1) {
- IsPviMode = TRUE;
- } else {
- IsPviMode = FALSE;
- }
-
- // Get P0's voltage
- LibAmdMsrRead (PS_REG_BASE, &MsrRegister, StdHeader);
- P0VidCode = (UINT8) (((PSTATE_MSR *) &MsrRegister)->CpuVid);
-
- // If SVI, we only care about CPU VID.
- // If PVI, determine the higher voltage between NB and CPU
- if (IsPviMode) {
- NbVid = (UINT8) (((PSTATE_MSR *) &MsrRegister)->NbVid);
- if (P0VidCode > NbVid) {
- P0VidCode = NbVid;
- }
- }
-
- // Get Pmin's index
- LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrRegister, StdHeader);
- MsrAddr = (UINT32) ((((PSTATE_CURLIM_MSR *) &MsrRegister)->PstateMaxVal) + PS_REG_BASE);
-
- // Get Pmin's VID
- LibAmdMsrRead (MsrAddr, &MsrRegister, StdHeader);
- PminVidCode = (UINT8) (((PSTATE_MSR *) &MsrRegister)->CpuVid);
-
- // If SVI, we only care about CPU VID.
- // If PVI, determine the higher voltage b/t NB and CPU
- if (IsPviMode) {
- NbVid = (UINT8) (((PSTATE_MSR *) &MsrRegister)->NbVid);
- if (PminVidCode > NbVid) {
- PminVidCode = NbVid;
- }
- }
-
- // Program F3xD8[VSSlamTime]
- LocalPciAddress.Address.Register = CPTC1_REG;
- AndMask = 0xFFFFFFFF;
- ((CLK_PWR_TIMING_CTRL1_REGISTER *) &AndMask)->VSSlamTime = 0;
- OrMask = 0x00000000;
- ((CLK_PWR_TIMING_CTRL1_REGISTER *) &OrMask)->VSSlamTime =
- F10GetSlamTimeEncoding (P0VidCode, PminVidCode, CpuEarlyParams, VSSlamTime, StdHeader);
- ModifyCurrentSocketPci (&LocalPciAddress, AndMask, OrMask, StdHeader);
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns the encoded voltage stabilization slam time for the executing
- * family 10h core.
- *
- * This function looks up the appropriate encoded value for the desired
- * VID codes.
- *
- * @param[in] HighVoltageVid VID code of the higher voltage.
- * @param[in] LowVoltageVid VID code of the lower voltage.
- * @param[in] CpuEarlyParams Service parameters
- * @param[in] SlamTimeTable Look-up table of slam times.
- * @param[in] StdHeader Config handle for library and services.
- *
- * @retval Encoded register value.
- *
- */
-UINT32
-F10GetSlamTimeEncoding (
- IN UINT8 HighVoltageVid,
- IN UINT8 LowVoltageVid,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
- IN CONST UINT32 *SlamTimeTable,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 SlamTime;
- UINT32 EncodedSlamTime;
- UINT32 VoltageDifference;
-
- ASSERT (LowVoltageVid >= HighVoltageVid);
- ASSERT (CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].SlewRate != 0);
-
- // Calculate Slam Time
- // VSSlamTime = 0.4us/mV (or 0.2us/mV) * Vhigh - Vlow
- // In our case, we will scale the values by 100 to avoid
- // decimals.
-
- VoltageDifference = (UINT32) ((LowVoltageVid - HighVoltageVid) * 12500);
- SlamTime = (VoltageDifference / CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].SlewRate) + CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].AdditionalDelay;
- if (VoltageDifference % CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].SlewRate) {
- SlamTime++;
- }
-
- // Now round up to nearest register setting
- for (EncodedSlamTime = 0; EncodedSlamTime < 8; EncodedSlamTime++) {
- if (SlamTime <= SlamTimeTable[EncodedSlamTime]) {
- break;
- }
- }
-
- if (EncodedSlamTime > 7) {
- // The VRMs are too slow for this CPU. Set to max, and fire an error trap.
- IDS_ERROR_TRAP;
- EncodedSlamTime = 7;
- }
-
- return (EncodedSlamTime);
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Disables the desired P-state.
- *
- * @CpuServiceMethod{::F_CPU_DISABLE_PSTATE}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] StateNumber The P-State to disable.
- * @param[in] StdHeader Header for library and services
- *
- * @retval AGESA_SUCCESS Always succeeds.
- */
-AGESA_STATUS
-F10DisablePstate (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN UINT8 StateNumber,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 MsrRegister;
-
- ASSERT (StateNumber < NM_PS_REG);
- LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
- ((PSTATE_MSR *) &MsrRegister)->PsEnable = 0;
- LibAmdMsrWrite (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
- return (AGESA_SUCCESS);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Transitions the executing core to the desired P-state.
- *
- * @CpuServiceMethod{::F_CPU_TRANSITION_PSTATE}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] StateNumber The new P-State to make effective.
- * @param[in] WaitForTransition True if the caller wants the transition completed upon return.
- * @param[in] StdHeader Header for library and services
- *
- * @retval AGESA_SUCCESS Always Succeeds
- */
-AGESA_STATUS
-F10TransitionPstate (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN UINT8 StateNumber,
- IN BOOLEAN WaitForTransition,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 MsrRegister;
-
- ASSERT (StateNumber < NM_PS_REG);
- LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
- ASSERT (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1);
- LibAmdMsrRead (MSR_PSTATE_CTL, &MsrRegister, StdHeader);
- ((PSTATE_CTRL_MSR *) &MsrRegister)->PstateCmd = (UINT64) StateNumber;
- LibAmdMsrWrite (MSR_PSTATE_CTL, &MsrRegister, StdHeader);
- if (WaitForTransition) {
- do {
- LibAmdMsrRead (MSR_PSTATE_STS, &MsrRegister, StdHeader);
- } while (((PSTATE_STS_MSR *) &MsrRegister)->CurPstate != (UINT64) StateNumber);
- }
- return (AGESA_SUCCESS);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Determines the rate at which the executing core's time stamp counter is
- * incrementing.
- *
- * @CpuServiceMethod{::F_CPU_GET_TSC_RATE}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[out] FrequencyInMHz TSC actual frequency.
- * @param[in] StdHeader Header for library and services.
- *
- * @return The most severe status of all called services
- */
-AGESA_STATUS
-F10GetTscRate (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- OUT UINT32 *FrequencyInMHz,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 MsrRegister;
- PSTATE_CPU_FAMILY_SERVICES *FamilyServices;
-
- FamilyServices = NULL;
- GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, &FamilyServices, StdHeader);
- ASSERT (FamilyServices != NULL);
-
- LibAmdMsrRead (0xC0010015, &MsrRegister, StdHeader);
- if ((MsrRegister & 0x01000000) != 0) {
- return (FamilyServices->GetPstateFrequency (FamilyServices, 0, FrequencyInMHz, StdHeader));
- } else {
- return (FamilySpecificServices->GetCurrentNbFrequency (FamilySpecificServices, FrequencyInMHz, StdHeader));
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Determines the NB clock on the desired node.
- *
- * @CpuServiceMethod{::F_CPU_GET_NB_FREQ}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[out] FrequencyInMHz Northbridge clock frequency in MHz.
- * @param[in] StdHeader Header for library and services.
- *
- * @return AGESA_SUCCESS FrequencyInMHz is valid.
- */
-AGESA_STATUS
-F10GetCurrentNbFrequency (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- OUT UINT32 *FrequencyInMHz,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Socket;
- UINT32 Module;
- UINT32 Core;
- UINT32 NbFid;
- UINT32 PciRegister;
- UINT64 MsrRegister;
- PCI_ADDR PciAddress;
- AGESA_STATUS ReturnCode;
-
- // get the local node ID
- IdentifyCore (StdHeader, &Socket, &Module, &Core, &ReturnCode);
- if (ReturnCode == AGESA_SUCCESS) {
- GetPciAddress (StdHeader, Socket, Module, &PciAddress, &ReturnCode);
- if (ReturnCode == AGESA_SUCCESS) {
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = CPTC0_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- NbFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->NbFid;
- LibAmdMsrRead (MSR_COFVID_STS, &MsrRegister, StdHeader);
- if (((COFVID_STS_MSR *) &MsrRegister)->CurNbDid == 0) {
- *FrequencyInMHz = ((NbFid + 4) * 200);
- } else {
- *FrequencyInMHz = (((NbFid + 4) * 200) / 2);
- }
- }
- }
- return ReturnCode;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Initially launches the desired core to run from the reset vector.
- *
- * @CpuServiceMethod{::F_CPU_AP_INITIAL_LAUNCH}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] SocketNum The Processor on which the core is to be launched
- * @param[in] ModuleNum The Module in that processor containing that core
- * @param[in] CoreNum The Core to launch
- * @param[in] PrimaryCoreNum The id of the module's primary core.
- * @param[in] StdHeader Header for library and services
- *
- * @retval TRUE The core was launched
- * @retval FALSE The core was previously launched
- */
-BOOLEAN
-F10LaunchApCore (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN UINT32 SocketNum,
- IN UINT32 ModuleNum,
- IN UINT32 CoreNum,
- IN UINT32 PrimaryCoreNum,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 NodeRelativeCoreNum;
- UINT32 PciRegister;
- PCI_ADDR PciAddress;
- BOOLEAN LaunchFlag;
- AGESA_STATUS Ignored;
-
- // Code Start
- LaunchFlag = FALSE;
- NodeRelativeCoreNum = CoreNum - PrimaryCoreNum;
- GetPciAddress (StdHeader, SocketNum, ModuleNum, &PciAddress, &Ignored);
- PciAddress.Address.Function = FUNC_0;
-
- switch (NodeRelativeCoreNum) {
- case 0:
- PciAddress.Address.Register = HT_INIT_CTRL;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- if ((PciRegister & HT_INIT_CTRL_REQ_DIS) != 0) {
- PciRegister &= ~HT_INIT_CTRL_REQ_DIS;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- LaunchFlag = TRUE;
- } else {
- LaunchFlag = FALSE;
- }
- break;
-
- case 1:
- PciAddress.Address.Register = HT_TRANS_CTRL;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- if ((PciRegister & HT_TRANS_CTRL_CPU1_EN) == 0) {
- PciRegister |= HT_TRANS_CTRL_CPU1_EN;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- LaunchFlag = TRUE;
- } else {
- LaunchFlag = FALSE;
- }
- break;
-
- case 2:
- PciAddress.Address.Register = ECS_HT_TRANS_CTRL;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
-
- if ((PciRegister & ECS_HT_TRANS_CTRL_CPU2_EN) == 0) {
- PciRegister |= ECS_HT_TRANS_CTRL_CPU2_EN;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister,
- StdHeader);
- LaunchFlag = TRUE;
- } else {
- LaunchFlag = FALSE;
- }
- break;
-
- case 3:
- PciAddress.Address.Register = ECS_HT_TRANS_CTRL;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- if ((PciRegister & ECS_HT_TRANS_CTRL_CPU3_EN) == 0) {
- PciRegister |= ECS_HT_TRANS_CTRL_CPU3_EN;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- LaunchFlag = TRUE;
- } else {
- LaunchFlag = FALSE;
- }
- break;
-
- case 4:
- PciAddress.Address.Register = ECS_HT_TRANS_CTRL;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- if ((PciRegister & ECS_HT_TRANS_CTRL_CPU4_EN) == 0) {
- PciRegister |= ECS_HT_TRANS_CTRL_CPU4_EN;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- LaunchFlag = TRUE;
- } else {
- LaunchFlag = FALSE;
- }
- break;
-
- case 5:
- PciAddress.Address.Register = ECS_HT_TRANS_CTRL;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- if ((PciRegister & ECS_HT_TRANS_CTRL_CPU5_EN) == 0) {
- PciRegister |= ECS_HT_TRANS_CTRL_CPU5_EN;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- LaunchFlag = TRUE;
- } else {
- LaunchFlag = FALSE;
- }
- break;
-
-
- default:
- break;
- }
-
- return (LaunchFlag);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Get CPU Specific Platform Type Info.
- *
- * @CpuServiceMethod{::F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO}.
- *
- * This function returns Returns the platform features.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in,out] Features The Features supported by this platform.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @retval AGESA_SUCCESS Always succeeds.
- */
-AGESA_STATUS
-F10GetPlatformTypeSpecificInfo (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN OUT PLATFORM_FEATS *Features,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- return (AGESA_SUCCESS);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Provide the features of the next HT link.
- *
- * @CpuServiceMethod{::F_GET_NEXT_HT_LINK_FEATURES}.
- *
- * This method is different than the HT Phy Features method, because for the phy registers
- * sublink 1 matches and should be programmed if the link is ganged but for PCI config
- * registers sublink 1 is reserved if the link is ganged.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in,out] Link Initially zero, each call returns the link number;
- * caller passes it back unmodified each call.
- * @param[in,out] LinkBase Initially the PCI bus, device, function=0, offset=0;
- * Each call returns the HT Host Capability function and offset;
- * Caller may use it to access registers, but must @b not modify it;
- * Each new call passes the previous value as input.
- * @param[out] HtHostFeats The link's features.
- * @param[in] StdHeader Standard Head Pointer
- *
- * @retval TRUE Valid link and features found.
- * @retval FALSE No more links.
- */
-BOOLEAN
-F10GetNextHtLinkFeatures (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN OUT UINTN *Link,
- IN OUT PCI_ADDR *LinkBase,
- OUT HT_HOST_FEATS *HtHostFeats,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- PCI_ADDR PciAddress;
- UINT32 RegValue;
- UINT32 ExtendedFreq;
- UINTN LinkOffset;
- BOOLEAN Result;
-
- ASSERT (FamilySpecificServices != NULL);
-
- // No features present unless link is good and connected.
- HtHostFeats->HtHostValue = 0;
-
- Result = TRUE;
-
- // Find next link.
- if (LinkBase->Address.Register == 0) {
- // Beginning iteration now.
- LinkBase->Address.Register = HT_CAPABILITIES_POINTER;
- LibAmdPciReadBits (*LinkBase, 7, 0, &RegValue, StdHeader);
- } else {
- // Get next link offset.
- LibAmdPciReadBits (*LinkBase, 15, 8, &RegValue, StdHeader);
- }
- if (RegValue == 0) {
- // Are we at the end? Check if we can move to another function.
- if (LinkBase->Address.Function == 0) {
- LinkBase->Address.Function = 4;
- LinkBase->Address.Register = HT_CAPABILITIES_POINTER;
- LibAmdPciReadBits (*LinkBase, 7, 0, &RegValue, StdHeader);
- }
- }
-
- if (RegValue != 0) {
- // Not at end, process the found link.
- LinkBase->Address.Register = RegValue;
- // Compute link number
- *Link = (((LinkBase->Address.Function == 4) ? 4 : 0) + ((LinkBase->Address.Register - 0x80) >> 5));
-
- // Handle pending link power off, check End of Chain, Xmit Off.
- PciAddress = *LinkBase;
- PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_CONTROL_REG_OFFSET;
- LibAmdPciReadBits (PciAddress, 7, 6, &RegValue, StdHeader);
- if (RegValue == 0) {
- // Check coherency (HTHOST_LINK_TYPE_REG = 0x18)
- PciAddress = *LinkBase;
- PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_TYPE_REG_OFFSET;
- LibAmdPciReadBits (PciAddress, 4, 0, &RegValue, StdHeader);
- if (RegValue == 3) {
- HtHostFeats->HtHostFeatures.Coherent = 1;
- } else if (RegValue == 7) {
- HtHostFeats->HtHostFeatures.NonCoherent = 1;
- }
- }
-
- // If link was not connected, don't check other attributes, make sure
- // to return zero, no match.
- if ((HtHostFeats->HtHostFeatures.Coherent == 1) || (HtHostFeats->HtHostFeatures.NonCoherent == 1)) {
- // Check gen3
- PciAddress = *LinkBase;
- PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_EXTENDED_FREQ;
- LibAmdPciRead (AccessWidth32, PciAddress, &ExtendedFreq, StdHeader);
- PciAddress = *LinkBase;
- PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_FREQ_OFFSET;
- LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader);
- RegValue = (((ExtendedFreq & 0x1) << 4) | ((RegValue & 0x00000F00) >> 8));
- if (RegValue > 6) {
- HtHostFeats->HtHostFeatures.Ht3 = 1;
- } else {
- HtHostFeats->HtHostFeatures.Ht1 = 1;
- }
- // Check ganged. Must check the bit for sublink 0.
- LinkOffset = (*Link > 3) ? ((*Link - 4) * 4) : (*Link * 4);
- PciAddress = *LinkBase;
- PciAddress.Address.Function = 0;
- PciAddress.Address.Register = ((UINT32)LinkOffset + 0x170);
- LibAmdPciReadBits (PciAddress, 0, 0, &RegValue, StdHeader);
- if (RegValue == 0) {
- HtHostFeats->HtHostFeatures.UnGanged = 1;
- } else {
- if (*Link < 4) {
- HtHostFeats->HtHostFeatures.Ganged = 1;
- } else {
- // If this is a sublink 1 but it will be ganged, clear all features.
- HtHostFeats->HtHostValue = 0;
- }
- }
- }
- } else {
- // End of links.
- Result = FALSE;
- }
- return Result;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Checks to see if the HT phy register table entry should be applied
- *
- * @CpuServiceMethod{::F_NEXT_LINK_HAS_HTFPY_FEATS}.
- *
- * Find the next link which matches, if any.
- * This method will match for sublink 1 if the link is ganged and sublink 0 matches.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in,out] HtHostCapability Initially the PCI bus, device, function=0, offset=0;
- * Each call returns the HT Host Capability function and offset;
- * Caller may use it to access registers, but must @b not modify it;
- * Each new call passes the previous value as input.
- * @param[in,out] Link Initially zero, each call returns the link number; caller passes it back unmodified each call.
- * @param[in] HtPhyLinkType Link type field from a register table entry to compare against
- * @param[out] MatchedSublink1 TRUE: It is actually just sublink 1 that matches, FALSE: any other condition.
- * @param[out] Frequency0 The frequency of sublink0 (200 MHz if not connected).
- * @param[out] Frequency1 The frequency of sublink1 (200 MHz if not connected).
- * @param[in] StdHeader Standard Head Pointer
- *
- * @retval TRUE Link matches
- * @retval FALSE No more links
- *
- */
-BOOLEAN
-F10NextLinkHasHtPhyFeats (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN OUT PCI_ADDR *HtHostCapability,
- IN OUT UINT32 *Link,
- IN HT_PHY_LINK_FEATS *HtPhyLinkType,
- OUT BOOLEAN *MatchedSublink1,
- OUT HT_FREQUENCIES *Frequency0,
- OUT HT_FREQUENCIES *Frequency1,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 RegValue;
- UINT32 ExtendedFreq;
- PCI_ADDR PciAddress;
- PCI_ADDR SubLink1Address;
- HT_PHY_LINK_FEATS LinkType;
- BOOLEAN IsReallyCheckingBoth;
- BOOLEAN IsFound;
- BOOLEAN Result;
-
- ASSERT (*Link < 4);
- ASSERT (HtPhyLinkType != NULL);
- // error checks: No unknown link type bits set and not a "match none"
- ASSERT ((HtPhyLinkType->HtPhyLinkValue & ~(HTPHY_LINKTYPE_ALL)) == 0);
- ASSERT (HtPhyLinkType->HtPhyLinkValue != 0);
-
- Result = FALSE;
- IsFound = FALSE;
- while (!IsFound) {
- *Frequency0 = 0;
- *Frequency1 = 0;
- IsReallyCheckingBoth = FALSE;
- *MatchedSublink1 = FALSE;
- LinkType.HtPhyLinkValue = 0;
-
- // Find next link.
- PciAddress = *HtHostCapability;
- if (PciAddress.Address.Register == 0) {
- // Beginning iteration now.
- PciAddress.Address.Register = HT_CAPABILITIES_POINTER;
- LibAmdPciReadBits (PciAddress, 7, 0, &RegValue, StdHeader);
- } else {
- // Get next link offset.
- LibAmdPciReadBits (PciAddress, 15, 8, &RegValue, StdHeader);
- }
- if (RegValue != 0) {
- HtHostCapability->Address.Register = RegValue;
- // Compute link number of this sublink pair (so we don't need to account for function).
- *Link = ((HtHostCapability->Address.Register - 0x80) >> 5);
-
- // Set the link indicators. This assumes each sublink set is contiguous, that is, links 3, 2, 1, 0 and 7, 6, 5, 4.
- LinkType.HtPhyLinkValue |= (HTPHY_LINKTYPE_SL0_LINK0 << *Link);
- LinkType.HtPhyLinkValue |= (HTPHY_LINKTYPE_SL1_LINK4 << *Link);
-
- // if ganged, don't read sublink 1, but use sublink 0 to check.
- SubLink1Address = *HtHostCapability;
-
- // Check ganged. Since we got called for sublink 0, sublink 1 is implemented also,
- // but only access it if it is also unganged.
- PciAddress = *HtHostCapability;
- PciAddress.Address.Function = 0;
- PciAddress.Address.Register = ((*Link * 4) + 0x170);
- LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader);
- RegValue = (RegValue & 0x01);
- if (RegValue == 0) {
- // Then really read sublink1, rather than using sublink0
- SubLink1Address.Address.Function = 4;
- IsReallyCheckingBoth = TRUE;
- }
-
- // Checks for Sublink 0
-
- // Handle pending link power off, check End of Chain, Xmit Off.
- PciAddress = *HtHostCapability;
- PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_CONTROL_REG_OFFSET;
- LibAmdPciReadBits (PciAddress, 7, 6, &RegValue, StdHeader);
- if (RegValue == 0) {
- // Check coherency (HTHOST_LINK_TYPE_REG = 0x18)
- PciAddress = *HtHostCapability;
- PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_TYPE_REG_OFFSET;
- LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader);
- if ((RegValue & 0x1F) == 3) {
- LinkType.HtPhyLinkFeatures.HtPhySL0Coh = 1;
- } else if ((RegValue & 0x1F) == 7) {
- LinkType.HtPhyLinkFeatures.HtPhySL0NonCoh = 1;
- }
- }
-
- // If link was not connected, don't check other attributes, make sure
- // to return zero, no match. (Phy may be powered off.)
- if ((LinkType.HtPhyLinkFeatures.HtPhySL0Coh) || (LinkType.HtPhyLinkFeatures.HtPhySL0NonCoh)) {
- // Check gen3
- PciAddress = *HtHostCapability;
- PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_EXTENDED_FREQ;
- LibAmdPciRead (AccessWidth32, PciAddress, &ExtendedFreq, StdHeader);
- PciAddress = *HtHostCapability;
- PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_FREQ_OFFSET;
- LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader);
- RegValue = (((ExtendedFreq & 0x1) << 4) | ((RegValue & 0x00000F00) >> 8));
- *Frequency0 = RegValue;
- if (RegValue > 6) {
- LinkType.HtPhyLinkFeatures.HtPhySL0Ht3 = 1;
- } else {
- LinkType.HtPhyLinkFeatures.HtPhySL0Ht1 = 1;
- }
- } else {
- LinkType.HtPhyLinkValue &= ~(HTPHY_LINKTYPE_SL0_ALL);
- }
-
- // Checks for Sublink 1
- // Handle pending link power off, check End of Chain, Xmit Off.
- PciAddress = SubLink1Address;
- PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_CONTROL_REG_OFFSET;
- LibAmdPciReadBits (PciAddress, 7, 6, &RegValue, StdHeader);
- if (RegValue == 0) {
- // Check coherency (HTHOST_LINK_TYPE_REG = 0x18)
- PciAddress = SubLink1Address;
- PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_TYPE_REG_OFFSET;
- LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader);
- if ((RegValue & 0x1F) == 3) {
- LinkType.HtPhyLinkFeatures.HtPhySL1Coh = 1;
- } else if ((RegValue & 0x1F) == 7) {
- LinkType.HtPhyLinkFeatures.HtPhySL1NonCoh = 1;
- }
- }
-
- if ((LinkType.HtPhyLinkFeatures.HtPhySL1Coh) || (LinkType.HtPhyLinkFeatures.HtPhySL1NonCoh)) {
- // Check gen3
- PciAddress = SubLink1Address;
- PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_EXTENDED_FREQ;
- LibAmdPciRead (AccessWidth32, PciAddress, &ExtendedFreq, StdHeader);
- PciAddress = SubLink1Address;
- PciAddress.Address.Register = PciAddress.Address.Register + HT_LINK_FREQ_OFFSET;
- LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader);
- RegValue = (((ExtendedFreq & 0x1) << 4) | ((RegValue & 0x00000F00) >> 8));
- *Frequency1 = RegValue;
- if (RegValue > 6) {
- LinkType.HtPhyLinkFeatures.HtPhySL1Ht3 = 1;
- } else {
- LinkType.HtPhyLinkFeatures.HtPhySL1Ht1 = 1;
- }
- } else {
- LinkType.HtPhyLinkValue &= ~(HTPHY_LINKTYPE_SL1_ALL);
- }
-
- // For Deemphasis checking, indicate whether it was actually sublink 1 that matched.
- // If the link is ganged or only sublink 0 matched, or the link features didn't match, this is false.
- if ((LinkType.HtPhyLinkValue & HtPhyLinkType->HtPhyLinkValue) != 0) {
- if (IsReallyCheckingBoth &&
- (((LinkType.HtPhyLinkValue & HtPhyLinkType->HtPhyLinkValue) & (HTPHY_LINKTYPE_SL1_ALL)) != 0)) {
- *MatchedSublink1 = TRUE;
- }
- Result = TRUE; // Link matches at least one of the desired characteristics
- IsFound = TRUE;
- } else {
- // Go to next link
- }
- } else {
- // No more links
- IsFound = TRUE;
- }
- }
- return Result;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Applies an HT Phy read-modify-write based on an HT Phy register table entry.
- *
- * @CpuServiceMethod{::F_SET_HT_PHY_REGISTER}.
- *
- * This function performs the necessary sequence of PCI reads, writes, and waits
- * necessary to program an HT Phy register.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] HtPhyEntry HT Phy register table entry to apply
- * @param[in] CapabilitySet The link's HT Host base address.
- * @param[in] Link Zero based, node, link number (not package link).
- * @param[in] StdHeader Config handle for library and services
- *
- */
-VOID
-F10SetHtPhyRegister (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN HT_PHY_TYPE_ENTRY_DATA *HtPhyEntry,
- IN PCI_ADDR CapabilitySet,
- IN UINT32 Link,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Temp;
- UINT32 PhyReg;
- PCI_ADDR PhyBase;
-
- // Determine the PCI config address of the HT Phy portal
- PhyBase = CapabilitySet;
- PhyBase.Address.Function = FUNC_4;
- PhyBase.Address.Register = ((Link << 3) + REG_HT4_PHY_OFFSET_BASE_4X180);
-
- LibAmdPciRead (AccessWidth32, PhyBase, &PhyReg, StdHeader);
-
- // Handle direct map registers if needed
- PhyReg &= ~(HTPHY_DIRECT_OFFSET_MASK);
- if (HtPhyEntry->Address > 0x1FF) {
- PhyReg |= HTPHY_DIRECT_MAP;
- }
-
- PhyReg |= (HtPhyEntry->Address);
- // Ask the portal to read the HT Phy Register contents
- LibAmdPciWrite (AccessWidth32, PhyBase, &PhyReg, StdHeader);
- do
- {
- LibAmdPciRead (AccessWidth32, PhyBase, &Temp, StdHeader);
- } while (!(Temp & HTPHY_IS_COMPLETE_MASK));
-
- // Get the current register contents and do the update requested by the table
- PhyBase.AddressValue += 4;
- LibAmdPciRead (AccessWidth32, PhyBase, &Temp, StdHeader);
- Temp &= ~(HtPhyEntry->Mask);
- Temp |= (HtPhyEntry->Data);
- LibAmdPciWrite (AccessWidth32, PhyBase, &Temp, StdHeader);
-
- PhyBase.AddressValue -= 4;
- // Ask the portal to write our updated value to the HT Phy
- PhyReg |= HTPHY_WRITE_CMD;
- LibAmdPciWrite (AccessWidth32, PhyBase, &PhyReg, StdHeader);
- do
- {
- LibAmdPciRead (AccessWidth32, PhyBase, &Temp, StdHeader);
- } while (!(Temp & HTPHY_IS_COMPLETE_MASK));
-}
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10Utilities.h b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10Utilities.h
deleted file mode 100644
index 3905ed3..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10Utilities.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 specific utility functions.
- *
- * Provides numerous utility functions specific to family 10h.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPU_F10_UTILITES_H_
-#define _CPU_F10_UTILITES_H_
-
-
-/*---------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *---------------------------------------------------------------------------------------
- */
-/// The structure for Software Initiated NB Voltage Transitions
-typedef struct {
- UINT32 VidCode; ///< VID code to transition to
- BOOLEAN SlamMode; ///< Whether voltage is to be slammed, or stepped
-} SW_VOLT_TRANS_NB;
-
-
-/*---------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *---------------------------------------------------------------------------------------
- */
-VOID
-F10PmSwVoltageTransition (
- IN UINT32 VidCode,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-F10PmSwVoltageTransitionServerNb (
- IN UINT32 VidCode,
- IN BOOLEAN SlamMode,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-UINT32
-F10SwVoltageTransitionServerNbCore (
- IN VOID *InputData,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-F10WaitOutVoltageTransition (
- IN BOOLEAN SlamMode,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-F10GetCurrentVsTimeInUsecs (
- OUT UINT32 *VsTimeUsecs,
- IN BOOLEAN SlamMode,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-F10ProgramVSSlamTimeOnSocket (
- IN PCI_ADDR *PciAddress,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-UINT32
-F10GetSlamTimeEncoding (
- IN UINT8 HighVoltageVid,
- IN UINT8 LowVoltageVid,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
- IN CONST UINT32 *SlamTimeTable,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-F10DisablePstate (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN UINT8 StateNumber,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-F10TransitionPstate (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN UINT8 StateNumber,
- IN BOOLEAN WaitForTransition,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-F10GetTscRate (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- OUT UINT32 *FrequencyInMHz,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-BOOLEAN
-F10LaunchApCore (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN UINT32 SocketNum,
- IN UINT32 ModuleNum,
- IN UINT32 CoreNum,
- IN UINT32 PrimaryCoreNum,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-F10GetPlatformTypeSpecificInfo (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN OUT PLATFORM_FEATS *Features,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif // _CPU_F10_UTILITES_H_
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c
deleted file mode 100644
index 62dc72d..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 WHEA initial Data
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuLateInit.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G3_DXE)
-RDATA_GROUP (G3_DXE)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10WHEAINITDATATABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-AMD_HEST_BANK_INIT_DATA F10HestBankInitData[] = {
- {0xFFFFFFFF,0xFFFFFFFF,0x400,0x401,0x402,0x403},
- {0xFFFFFFFF,0xFFFFFFFF,0x404,0x405,0x406,0x407},
- {0xFFFFFFFF,0xFFFFFFFF,0x408,0x409,0x40A,0x40B},
- {0xFFFFFFFF,0xFFFFFFFF,0x40C,0x40D,0x40E,0x40F},
- {0xFFFFFFFF,0xFFFFFFFF,0x410,0x411,0x412,0x413},
- {0xFFFFFFFF,0xFFFFFFFF,0x414,0x415,0x416,0x417},
-};
-
-AMD_WHEA_INIT_DATA F10WheaInitData = {
- 0x000000000, // AmdGlobCapInitDataLsd
- 0x000000000, // AmdGlobCapInitDataMsd
- 0x00000003F, // AmdGlobCtrlInitDataLsd
- 0x000000000, // AmdGlobCtrlInitDataMsd
- 0x00, // AmdMcbClrStatusOnInit
- 0x02, // AmdMcbStatusDataFormat
- 0x00, // AmdMcbConfWriteEn
- (sizeof (F10HestBankInitData) / sizeof (F10HestBankInitData[0])), // HestBankNum
- &F10HestBankInitData[0] // Pointer to Initial data of HEST Bank
-};
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns the family specific WHEA table properties.
- *
- * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[out] F10WheaInitDataPtr Points to the family 10h WHEA properties.
- * @param[out] NumberOfElements Will be one to indicate one structure.
- * @param[in] StdHeader Header for library and services.
- *
- */
-VOID
-GetF10WheaInitData (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- OUT CONST VOID **F10WheaInitDataPtr,
- OUT UINT8 *NumberOfElements,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- *NumberOfElements = 1;
- *F10WheaInitDataPtr = &F10WheaInitData;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10WorkaroundsTable.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10WorkaroundsTable.c
deleted file mode 100644
index e8456c9..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x10/cpuF10WorkaroundsTable.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Family Specific Workaround table
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x10
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "cpuServices.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10WORKAROUNDSTABLE_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-// F a m i l y S p e c i f i c W o r k a r o u n d T a b l e s
-// -----------------------------------------------------------------
-
-STATIC CONST FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER ROMDATA F10Workarounds[] =
-{
-// F0x6C - Link Initialization Control Register
-// Request for warm reset in AmdInitEarly
-// [5, BiosRstDet] = 1b
- {
- FamSpecificWorkaround,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- SetWarmResetAtEarly, // function call
- 0x00000000, // data
- }
- },
-};
-
-CONST REGISTER_TABLE ROMDATA F10WorkaroundsTable = {
- PrimaryCores,
- (sizeof (F10Workarounds) / sizeof (TABLE_ENTRY_FIELDS)),
- (TABLE_ENTRY_FIELDS *)F10Workarounds,
-};
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/F14C6State.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/F14C6State.c
deleted file mode 100644
index 48823ec..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/F14C6State.c
+++ /dev/null
@@ -1,238 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_14 C6 C-state feature support functions.
- *
- * Provides the functions necessary to initialize the C6 feature.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F14
- * @e \$Revision: 37004 $ @e \$Date: 2010-08-28 02:23:00 +0800 (Sat, 28 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-#include "cpuFeatures.h"
-#include "cpuC6State.h"
-#include "cpuF14PowerMgmt.h"
-#include "OptionFamily14hEarlySample.h"
-#include "Filecode.h"
-#define FILECODE PROC_CPU_FAMILY_0X14_F14C6STATE_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-extern F14_ES_C6_SUPPORT F14EarlySampleC6Support;
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Is C6 supported on this CPU
- *
- * @param[in] C6Services Pointer to this CPU's C6 family services.
- * @param[in] Socket This core's zero-based socket number.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval TRUE C6 state is supported.
- * @retval FALSE C6 state is not supported.
- *
- */
-BOOLEAN
-STATIC
-F14IsC6Supported (
- IN C6_FAMILY_SERVICES *C6Services,
- IN UINT32 Socket,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 PciRegister;
- BOOLEAN IsEnabled;
- PCI_ADDR PciAddress;
-
- IsEnabled = TRUE;
-
- PciAddress.AddressValue = CPU_STATE_PM_CTRL1_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- if ((((CPU_STATE_PM_CTRL1_REGISTER *) &PciRegister)->CoreC6Cap == 0) &&
- (((CPU_STATE_PM_CTRL1_REGISTER *) &PciRegister)->PkgC6Cap == 0)) {
- IsEnabled = FALSE;
- }
-
- F14EarlySampleC6Support.F14IsC6SupportedHook (&IsEnabled, StdHeader);
-
- return IsEnabled;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Enable C6 on a family 14h CPU.
- *
- * @param[in] C6Services Pointer to this CPU's C6 family services.
- * @param[in] EntryPoint Timepoint designator.
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @return AGESA_SUCCESS Always succeeds.
- *
- */
-AGESA_STATUS
-STATIC
-F14InitializeC6 (
- IN C6_FAMILY_SERVICES *C6Services,
- IN UINT64 EntryPoint,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 i;
- UINT32 MaxEnabledPstate;
- UINT32 PciRegister;
- UINT64 MsrRegister;
- PCI_ADDR PciAddress;
-
- for (i = MSR_PSTATE_7; i > MSR_PSTATE_0; i--) {
- LibAmdMsrRead (i, &MsrRegister, StdHeader);
- if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
- break;
- }
- }
- MaxEnabledPstate = i - MSR_PSTATE_0;
-
- if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) {
- // Program D18F4x1AC[CoreC6Dis] to 0.
- // Program D18F4x1AC[PkgC6Dis] to 0.
- PciAddress.AddressValue = CPU_STATE_PM_CTRL1_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- ((CPU_STATE_PM_CTRL1_REGISTER *) &PciRegister)->CoreC6Dis = 0;
- ((CPU_STATE_PM_CTRL1_REGISTER *) &PciRegister)->PkgC6Dis = 0;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
-
- F14EarlySampleC6Support.F14InitializeC6 (StdHeader);
-
- } else {
- // Ensure D18F2x118[C6DramLock] and D18F4x12C[C6Base] are programmed.
- PciAddress.AddressValue = MEM_CFG_LOW_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- ASSERT (((MEM_CFG_LOW_REGISTER *) &PciRegister)->C6DramLock == 1);
-
- PciAddress.AddressValue = C6_BASE_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- ASSERT (((C6_BASE_REGISTER *) &PciRegister)->C6Base != 0);
-
- // If PC6 is supported, program D18F4x1AC[PstateIdCoreOffExit] to
- // the index of lowest-performance Pstate with MSRC001_00[6B:64]
- // [PstateEn] == 1 on core 0.
- PciAddress.AddressValue = CPU_STATE_PM_CTRL1_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- if (((CPU_STATE_PM_CTRL1_REGISTER *) &PciRegister)->PkgC6Cap == 1) {
- ((CPU_STATE_PM_CTRL1_REGISTER *) &PciRegister)->PstateIdCoreOffExit = MaxEnabledPstate;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- }
-
- // Program D18F4x118 to 0000_0101h.
- PciAddress.AddressValue = CSTATE_CTRL1_PCI_ADDR;
- PciRegister = 0x00000101;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- }
-
- return AGESA_SUCCESS;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Reload microcode patch for a family 14h CPU after memory is initialized.
- *
- * @param[in] StdHeader Config Handle for library, services.
- *
- */
-VOID
-STATIC
-F14ReloadMicrocodePatchAfterMemInit (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 MsrValue;
-
- // To load a microcode patch while using the cache as general storage,
- // the following steps are followed:
- // 1. Program MSRC001_102B[L2AllocDcFlushVictim]=1.
- // 2. Load the microcode patch.
- // 3. Program MSRC001_102B[L2AllocDcFlushVictim]=0.
- LibAmdMsrRead (MSR_BU_CFG3, &MsrValue, StdHeader);
- MsrValue = MsrValue | BIT7;
- LibAmdMsrWrite (MSR_BU_CFG3, &MsrValue, StdHeader);
-
- // Reload microcode patches.
- LoadMicrocodePatch (StdHeader);
-
- LibAmdMsrRead (MSR_BU_CFG3, &MsrValue, StdHeader);
- MsrValue = MsrValue & ~((UINT64)BIT7);
- LibAmdMsrWrite (MSR_BU_CFG3, &MsrValue, StdHeader);
-}
-
-
-
-CONST C6_FAMILY_SERVICES ROMDATA F14C6Support =
-{
- 0,
- F14IsC6Supported,
- F14InitializeC6,
- F14ReloadMicrocodePatchAfterMemInit
-};
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/F14IoCstate.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/F14IoCstate.c
deleted file mode 100644
index 43f0c68..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/F14IoCstate.c
+++ /dev/null
@@ -1,285 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_14 IO C-state feature support functions.
- *
- * Provides the functions necessary to initialize the IO C-state feature.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F14
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuServices.h"
-#include "cpuFeatures.h"
-#include "cpuIoCstate.h"
-#include "cpuF14PowerMgmt.h"
-#include "cpuLateInit.h"
-#include "cpuApicUtilities.h"
-#include "CommonReturns.h"
-#include "Filecode.h"
-#define FILECODE PROC_CPU_FAMILY_0X14_F14IOCSTATE_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-VOID
-STATIC
-F14InitializeIoCstateOnCore (
- IN VOID *CstateBaseMsr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Enable IO Cstate on a family 14h CPU.
- * Implement steps 1 to 3 of BKDG section 2.5.4.2.9 BIOS Requirements for Initialization
- *
- * @param[in] IoCstateServices Pointer to this CPU's IO Cstate family services.
- * @param[in] EntryPoint Timepoint designator.
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @return AGESA_SUCCESS Always succeeds.
- *
- */
-AGESA_STATUS
-STATIC
-F14InitializeIoCstate (
- IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
- IN UINT64 EntryPoint,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
-
- UINT32 i;
- UINT32 MaxEnabledPstate;
- UINT32 PciRegister;
- UINT64 MsrRegister;
- AP_TASK TaskPtr;
- PCI_ADDR PciAddress;
-
- if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) {
- for (i = MSR_PSTATE_7; i > MSR_PSTATE_0; i--) {
- LibAmdMsrRead (i, &MsrRegister, StdHeader);
- if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
- break;
- }
- }
- MaxEnabledPstate = i - MSR_PSTATE_0;
- // Initialize MSRC001_0073[CstateAddr] on each core to a region of
- // the IO address map with 8 consecutive available addresses.
- MsrRegister = 0;
- ((CSTATE_ADDRESS_MSR *) &MsrRegister)->CstateAddr = PlatformConfig->CStateIoBaseAddress;
- ASSERT ((((CSTATE_ADDRESS_MSR *) &MsrRegister)->CstateAddr != 0) &&
- (((CSTATE_ADDRESS_MSR *) &MsrRegister)->CstateAddr <= 0xFFF8));
-
- TaskPtr.FuncAddress.PfApTaskI = F14InitializeIoCstateOnCore;
- TaskPtr.DataTransfer.DataSizeInDwords = 2;
- TaskPtr.DataTransfer.DataPtr = &MsrRegister;
- TaskPtr.DataTransfer.DataTransferFlags = 0;
- TaskPtr.ExeFlags = WAIT_FOR_CORE;
- ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
-
- // Program D18F4x1A8[PService] to the index of lowest-performance
- // P-state with MSRC001_00[6B:64][PstateEn]==1 on core 0.
- PciAddress.AddressValue = CPU_STATE_PM_CTRL0_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- ((CPU_STATE_PM_CTRL0_REGISTER *) &PciRegister)->PService = MaxEnabledPstate;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
-
- // Program D18F4x1AC[CstPminEn] to 1.
- PciAddress.AddressValue = CPU_STATE_PM_CTRL1_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- ((CPU_STATE_PM_CTRL1_REGISTER *) &PciRegister)->CstPminEn = 1;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- }
- return AGESA_SUCCESS;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Enable C-State on a family 14h core.
- *
- * @param[in] CstateBaseMsr MSR value to write to C001_0073 as determined by core 0.
- * @param[in] StdHeader Config Handle for library, services.
- *
- */
-VOID
-STATIC
-F14InitializeIoCstateOnCore (
- IN VOID *CstateBaseMsr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- // Initialize MSRC001_0073[CstateAddr] on each core
- LibAmdMsrWrite (MSR_CSTATE_ADDRESS, (UINT64 *) CstateBaseMsr, StdHeader);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns the size of CST object
- *
- * @param[in] IoCstateServices IO Cstate services.
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval CstObjSize Size of CST Object
- *
- */
-UINT32
-STATIC
-F14GetAcpiCstObj (
- IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- return (CST_HEADER_SIZE + CST_BODY_SIZE);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Routine to generate the C-State ACPI objects
- *
- * @param[in] IoCstateServices IO Cstate services.
- * @param[in] LocalApicId Local Apic Id for each core.
- * @param[in] **PstateAcpiBufferPtr Pointer to the Acpi Buffer Pointer.
- * @param[in] StdHeader Config Handle for library, services.
- *
- */
-VOID
-STATIC
-F14CreateAcpiCstObj (
- IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
- IN UINT8 LocalApicId,
- IN OUT VOID **PstateAcpiBufferPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 MsrData;
- CST_HEADER_STRUCT *CstHeaderPtr;
- CST_BODY_STRUCT *CstBodyPtr;
-
- // Read from MSR C0010073 to obtain CstateAddr
- LibAmdMsrRead (MSR_CSTATE_ADDRESS, &MsrData, StdHeader);
- ASSERT ((((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr != 0) &&
- (((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr <= 0xFFF8));
-
- // Typecast the pointer
- CstHeaderPtr = (CST_HEADER_STRUCT *) *PstateAcpiBufferPtr;
-
- // Set CST Header
- CstHeaderPtr->NameOpcode = NAME_OPCODE;
- CstHeaderPtr->CstName_a__ = CST_NAME__;
- CstHeaderPtr->CstName_a_C = CST_NAME_C;
- CstHeaderPtr->CstName_a_S = CST_NAME_S;
- CstHeaderPtr->CstName_a_T = CST_NAME_T;
-
- // Typecast the pointer
- CstHeaderPtr++;
- CstBodyPtr = (CST_BODY_STRUCT *) CstHeaderPtr;
-
- // Set CST Body
- CstBodyPtr->PkgOpcode = PACKAGE_OPCODE;
- CstBodyPtr->PkgLength = CST_LENGTH;
- CstBodyPtr->PkgElements = CST_NUM_OF_ELEMENTS;
- CstBodyPtr->BytePrefix = BYTE_PREFIX_OPCODE;
- CstBodyPtr->Count = CST_COUNT;
- CstBodyPtr->PkgOpcode2 = PACKAGE_OPCODE;
- CstBodyPtr->PkgLength2 = CST_PKG_LENGTH;
- CstBodyPtr->PkgElements2 = CST_PKG_ELEMENTS;
- CstBodyPtr->BufferOpcode = BUFFER_OPCODE;
- CstBodyPtr->BufferLength = CST_SUBPKG_LENGTH;
- CstBodyPtr->BufferElements = CST_SUBPKG_ELEMENTS;
- CstBodyPtr->BufferOpcode2 = BUFFER_OPCODE;
- CstBodyPtr->GdrOpcode = GENERIC_REG_DESCRIPTION;
- CstBodyPtr->GdrLength = CST_GDR_LENGTH;
- CstBodyPtr->AddrSpaceId = GDR_ASI_SYSTEM_IO;
- CstBodyPtr->RegBitWidth = 0x08;
- CstBodyPtr->RegBitOffset = 0x00;
- CstBodyPtr->AddressSize = GDR_ASZ_BYTE_ACCESS;
- CstBodyPtr->RegisterAddr = ((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr + 1;
- CstBodyPtr->EndTag = 0x0079;
- CstBodyPtr->BytePrefix2 = BYTE_PREFIX_OPCODE;
- CstBodyPtr->Type = CST_C2_TYPE;
- CstBodyPtr->WordPrefix = WORD_PREFIX_OPCODE;
- CstBodyPtr->Latency = 0x64;
- CstBodyPtr->DWordPrefix = DWORD_PREFIX_OPCODE;
- CstBodyPtr->Power = 0;
-
- CstBodyPtr++;
-
- //Update the pointer
- *PstateAcpiBufferPtr = CstBodyPtr;
-}
-
-CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F14IoCstateSupport =
-{
- 0,
- (PF_IO_CSTATE_IS_SUPPORTED) CommonReturnTrue,
- F14InitializeIoCstate,
- F14GetAcpiCstObj,
- F14CreateAcpiCstObj,
- (PF_IO_CSTATE_IS_CSD_GENERATED) CommonReturnFalse
-};
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c
deleted file mode 100644
index 1b1c6fb..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c
+++ /dev/null
@@ -1,1645 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_14 Microcode patch.
- *
- * Fam14 Microcode Patch rev 0500000B for 5000 or equivalent.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x14
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-// Patch code 0500000B for 5000 and equivalent
-CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch0500000B =
-{
-0x10,
-0x20,
-0x01,
-0x06,
-0x0b,
-0x00,
-0x00,
-0x05,
-0x01,
-0x80,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x50,
-0x00,
-0x00,
-0x00,
-0xaa,
-0xaa,
-0xaa,
-0x67,
-0xe5,
-0x52,
-0x3e,
-0x6b,
-0x1c,
-0x70,
-0x69,
-0xd9,
-0x1c,
-0x8d,
-0xab,
-0xab,
-0xc4,
-0xce,
-0xc5,
-0x4f,
-0xc9,
-0x2d,
-0x81,
-0xeb,
-0x2b,
-0x49,
-0x14,
-0x39,
-0xc9,
-0xea,
-0xd1,
-0x6e,
-0x83,
-0x4c,
-0x14,
-0x6c,
-0x57,
-0x06,
-0xf8,
-0xcf,
-0xa5,
-0xb4,
-0x4a,
-0xab,
-0x40,
-0x63,
-0x38,
-0x0c,
-0x32,
-0x56,
-0x28,
-0x46,
-0xe5,
-0x2c,
-0x62,
-0x26,
-0x54,
-0xf7,
-0xa2,
-0x45,
-0xfe,
-0xcb,
-0x20,
-0x01,
-0xb1,
-0x6d,
-0x5d,
-0xbc,
-0xe8,
-0xf9,
-0xe0,
-0x4e,
-0x11,
-0x94,
-0x1f,
-0x20,
-0x90,
-0x31,
-0x33,
-0x23,
-0x09,
-0xb4,
-0xa4,
-0xc8,
-0x88,
-0xa4,
-0x93,
-0xee,
-0x36,
-0xe4,
-0x18,
-0xb8,
-0xbd,
-0x66,
-0x5a,
-0x69,
-0x03,
-0x9c,
-0xc0,
-0xc9,
-0x44,
-0x38,
-0x29,
-0xbe,
-0xba,
-0x4d,
-0xa7,
-0x42,
-0xac,
-0xe3,
-0x6a,
-0xf9,
-0xfa,
-0xa9,
-0x04,
-0xec,
-0x93,
-0x47,
-0xf0,
-0x1f,
-0x49,
-0xf1,
-0xe7,
-0x69,
-0x24,
-0x4c,
-0x88,
-0x1e,
-0xad,
-0xc3,
-0x57,
-0xec,
-0x45,
-0xd4,
-0xeb,
-0xd1,
-0xdf,
-0xdc,
-0x04,
-0x3b,
-0xc1,
-0xb0,
-0x8d,
-0xa1,
-0x3a,
-0x4d,
-0x79,
-0x4b,
-0xad,
-0x70,
-0x9b,
-0x3d,
-0xcf,
-0x7a,
-0x8d,
-0xe1,
-0xc2,
-0xdb,
-0x53,
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-0x15,
-0x8c,
-0x2f,
-0x44,
-0x4e,
-0x83,
-0xc9,
-0xf3,
-0xa1,
-0xc9,
-0x39,
-0xe8,
-0x3c,
-0xb0,
-0xa7,
-0x51,
-0x69,
-0xce,
-0x4b,
-0xb2,
-0x70,
-0x3e,
-0x8e,
-0xcf,
-0x3e,
-0x3a,
-0x95,
-0x5e,
-0x18,
-0x43,
-0xc9,
-0xde,
-0x4e,
-0x47,
-0xbb,
-0x6e,
-0x0c,
-0x83,
-0x3b,
-0xaf,
-0x58,
-0x67,
-0x06,
-0xd6,
-0x52,
-0xd5,
-0x89,
-0xb7,
-0x1c,
-0xb9,
-0xd9,
-0xa3,
-0x95,
-0x81,
-0x92,
-0x8b,
-0x32,
-0x43,
-0xb9,
-0xf8,
-0x99,
-0x2e,
-0x70,
-0xc9,
-0x1e,
-0x9a,
-0x3a,
-0xaa,
-0x97,
-0xd8,
-0xcc,
-0x2f,
-0xd2,
-0x69,
-0xdc,
-0x69,
-0xab,
-0x63,
-0xc0,
-0x5f,
-0xd5,
-0xb6,
-0xb8,
-0x8b,
-0x8d,
-0x6c,
-0x15,
-0x56,
-0x0a,
-0xe6,
-0x92,
-0xb5,
-0x25,
-0x4b,
-0x24,
-0x1c,
-0x63,
-0x5f,
-0x0c,
-0x1d,
-0x36,
-0x6e,
-0x7a,
-0xc0,
-0x5b,
-0xdb,
-0xa1,
-0xf8,
-0x16,
-0x29,
-0x04,
-0x2f,
-0x2b,
-0xb8,
-0x11,
-0xf9,
-0xef,
-0x1a,
-0x50,
-0x0c,
-0x97,
-0x19,
-0x20,
-0xbc,
-0xe9,
-0x40,
-0xd1,
-0x0b,
-0x74,
-0xec,
-0xa0,
-0xd5,
-0x18,
-0x6b,
-0xc8,
-0x6e,
-0xb1,
-0x65,
-0xd7,
-0x5f,
-0xf3,
-0x7c,
-0x33,
-0x89,
-0xca,
-0x15,
-0xd1,
-0xa8,
-0x7f,
-0x73,
-0xe0,
-0xa2,
-0x72,
-0x27,
-0x6d,
-0x79,
-0xa5,
-0xec,
-0x36,
-0x4e,
-0x47,
-0xd1,
-0x52,
-0xe4,
-0x0f,
-0x3b,
-0x9a,
-0xb5,
-0xef,
-0x97,
-0x0f,
-0xc5,
-0x9c,
-0x7a,
-0x51,
-0xbe,
-0x23,
-0x0f,
-0x15,
-0x87,
-0xd0,
-0xa5,
-0xf6,
-0x12,
-0x81,
-0xdd,
-0x44,
-0xd9,
-0xf4,
-0xcc,
-0xda,
-0x61,
-0x5e,
-0x66,
-0xa4,
-0xf1,
-0x7c,
-0xd7,
-0xd3,
-0xac,
-0xf0,
-0x57,
-0xd0,
-0x53,
-0xeb,
-0x19,
-0xbd,
-0x9d,
-0xb4,
-0xcb,
-0x9e,
-0x61,
-0x1e,
-0xe2,
-0x0e,
-0xdb,
-0x6d,
-0x40,
-0xaa,
-0xe8,
-0xc8,
-0x91,
-0xec,
-0xca,
-0xb0,
-0x0f,
-0xf1,
-0x41,
-0x71,
-0x43,
-0x25,
-0x71,
-0xf5,
-0xab,
-0x93,
-0x03,
-0xa7,
-0x64,
-0xdb,
-0xb4,
-0xde,
-0x11,
-0x4f,
-0x08,
-0xe9,
-0xb2,
-0x6d
-};
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c
deleted file mode 100644
index 5bde1d9..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c
+++ /dev/null
@@ -1,1645 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_14 Microcode patch.
- *
- * Fam14 Microcode Patch rev 0500001A for 5001 or equivalent.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x14
- * @e \$Revision: 37850 $ @e \$Date: 2010-09-13 18:09:57 -0400 (Mon, 13 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-// Patch code 0500001A for 5001 and equivalent
-CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch0500001A =
-{
-0x10,
-0x20,
-0x08,
-0x09,
-0x1a,
-0x00,
-0x00,
-0x05,
-0x01,
-0x80,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x01,
-0x50,
-0x00,
-0x00,
-0x00,
-0xaa,
-0xaa,
-0xaa,
-0x66,
-0xb4,
-0x7f,
-0x31,
-0x85,
-0x36,
-0x47,
-0xfa,
-0xa2,
-0x3e,
-0x1c,
-0xb4,
-0x9d,
-0xaa,
-0x69,
-0x39,
-0xc4,
-0xc0,
-0xc6,
-0xa7,
-0xaf,
-0x4a,
-0x48,
-0xe1,
-0xe4,
-0xbe,
-0x8a,
-0x91,
-0x15,
-0xfd,
-0x1f,
-0x89,
-0xd9,
-0x17,
-0x1e,
-0xe0,
-0xe5,
-0x8d,
-0xd1,
-0x77,
-0xe1,
-0xd6,
-0xbc,
-0x7b,
-0x85,
-0x18,
-0x61,
-0xc0,
-0x94,
-0xb7,
-0x36,
-0x07,
-0x19,
-0x64,
-0x8f,
-0x10,
-0xda,
-0x1e,
-0xf1,
-0xf3,
-0xe4,
-0xe9,
-0xc6,
-0xbd,
-0x05,
-0xe5,
-0xb2,
-0x5c,
-0x8a,
-0xdb,
-0x35,
-0x84,
-0x68,
-0x07,
-0x15,
-0xa1,
-0xca,
-0xcc,
-0x41,
-0x3a,
-0xef,
-0x18,
-0x02,
-0x72,
-0x71,
-0xff,
-0x65,
-0x6e,
-0x3c,
-0x2d,
-0x2a,
-0xe8,
-0x26,
-0x00,
-0xe1,
-0xf8,
-0x8b,
-0x4c,
-0xe2,
-0xbd,
-0x1b,
-0xc0,
-0x83,
-0x11,
-0xc5,
-0x38,
-0x65,
-0x4d,
-0x65,
-0xb7,
-0x9d,
-0x1f,
-0x5b,
-0x46,
-0x96,
-0x6c,
-0x7b,
-0xc1,
-0x03,
-0x59,
-0x1d,
-0x0f,
-0x6b,
-0x0b,
-0x2c,
-0xfc,
-0x96,
-0x3f,
-0xf8,
-0xc5,
-0x76,
-0xaf,
-0x08,
-0xb0,
-0x60,
-0xc8,
-0xaa,
-0x66,
-0x99,
-0x1f,
-0xb1,
-0x67,
-0x85,
-0x2b,
-0x03,
-0x06,
-0x50,
-0x7c,
-0x22,
-0x7c,
-0xa7,
-0xb4,
-0x04,
-0x58,
-0xcc,
-0xdf,
-0xf1,
-0xdc,
-0x94,
-0x84,
-0x84,
-0x06,
-0xf7,
-0x17,
-0xc9,
-0x02,
-0x75,
-0xd6,
-0x03,
-0xd3,
-0x20,
-0x8c,
-0x23,
-0x5e,
-0xfb,
-0x76,
-0xf3,
-0x74,
-0x6b,
-0x4d,
-0x16,
-0x1a,
-0x66,
-0xb6,
-0xfa,
-0x30,
-0x5f,
-0xea,
-0x82,
-0xf1,
-0x5b,
-0x9d,
-0xb0,
-0xd2,
-0xd6,
-0x2c,
-0xa7,
-0x5f,
-0xb0,
-0x4b,
-0xfa,
-0x27,
-0xff,
-0xd5,
-0x7b,
-0xfa,
-0x8d,
-0x18,
-0xab,
-0x96,
-0xfc,
-0x42,
-0xc4,
-0x5b,
-0x85,
-0xbc,
-0x9b,
-0xf5,
-0x4b,
-0x59,
-0x0d,
-0xc7,
-0x88,
-0xfc,
-0xc0,
-0x6e,
-0xac,
-0xe5,
-0xe2,
-0xa3,
-0x14,
-0x44,
-0xf8,
-0xb2,
-0x8a,
-0xe9,
-0x9d,
-0x75,
-0xe2,
-0xdc,
-0xf1,
-0x3b,
-0x18,
-0xe9,
-0x17,
-0x9a,
-0x59,
-0x55,
-0x28,
-0xf3,
-0x84,
-0xcc,
-0xf2,
-0x08,
-0x6e,
-0xe0,
-0x94,
-0xd9,
-0x88,
-0x3d,
-0x3a,
-0xf0,
-0xa2,
-0xdb,
-0xa2,
-0x58,
-0xbe,
-0x7c,
-0x6e,
-0x26,
-0xd6,
-0x2d,
-0xba,
-0x09,
-0xba,
-0xf8,
-0xba,
-0x28,
-0xf9,
-0xff,
-0x71,
-0xd3,
-0xb4,
-0xd7,
-0x31,
-0x31,
-0xd4,
-0x8d,
-0xcc,
-0x44,
-0xcc,
-0xb8,
-0xed,
-0xc7,
-0x83,
-0x97,
-0x04,
-0x88,
-0x05,
-0xb8,
-0x5b,
-0x27,
-0x6b,
-0xef,
-0xe4,
-0x5d,
-0x03,
-0xac,
-0x95,
-0x05,
-0x17,
-0x79,
-0x0b,
-0xe9,
-0xbe,
-0xaf,
-0x25,
-0x4a,
-0x3b,
-0xf2,
-0x09,
-0xd9,
-0x83,
-0x17,
-0x4f,
-0x95,
-0x11,
-0x17,
-0xf5,
-0xa4,
-0xa6,
-0x3e,
-0xb8,
-0x71,
-0x9e,
-0x38,
-0x86,
-0xc8,
-0x97,
-0x7b,
-0x19,
-0xab,
-0xd5,
-0xec,
-0xc3,
-0x99,
-0xe2,
-0x95,
-0x97,
-0xbd,
-0x93,
-0xd0,
-0x1b,
-0x76,
-0xc4,
-0x86,
-0x14,
-0x58,
-0xbf,
-0x0b,
-0x14,
-0x9d,
-0x04,
-0x64,
-0xa8,
-0xa6,
-0xaf,
-0x69,
-0x3b,
-0xe7,
-0x37,
-0xed,
-0x19,
-0xaf,
-0x28,
-0x2b,
-0xff,
-0x36,
-0xbd,
-0x72,
-0xf1,
-0x2b,
-0x06,
-0x7f,
-0xe9,
-0xae,
-0x5e,
-0xa0,
-0xe3,
-0x0d,
-0x1e,
-0x64,
-0x06,
-0xa8,
-0x24,
-0x99,
-0x2e,
-0x7a,
-0x41,
-0x94,
-0x77,
-0x4a,
-0x17,
-0x93,
-0x04,
-0xd6,
-0x2e,
-0x86,
-0x7a,
-0x24,
-0x05,
-0x87,
-0x18,
-0x17,
-0xb6,
-0xe8,
-0x41,
-0xc2,
-0x33,
-0xec,
-0xb6,
-0x42,
-0xb2,
-0x08,
-0xe5,
-0xf2,
-0x12,
-0x15,
-0x6b,
-0xc9,
-0x55,
-0xd4,
-0xce,
-0xa4,
-0x4e,
-0xa5,
-0x2f,
-0xd2,
-0x3b,
-0xd1,
-0x08,
-0x61,
-0x9f,
-0xe4,
-0x92,
-0x1a,
-0x84,
-0x62,
-0x73,
-0x7d,
-0x87,
-0xb2,
-0x4b,
-0x3d,
-0x07,
-0x1c,
-0xad,
-0x13,
-0x9f,
-0xd6,
-0xa5,
-0x80,
-0x90,
-0x95,
-0x09,
-0xf0,
-0x45,
-0x04,
-0x13,
-0xd0,
-0x06,
-0xc2,
-0x24,
-0xd4,
-0x0b,
-0x39,
-0xe7,
-0x7b,
-0xd7,
-0xda,
-0x7b,
-0x88,
-0xe7,
-0xcf,
-0x53,
-0xac,
-0x38,
-0x11,
-0x2e,
-0x01,
-0x94,
-0x69,
-0x5a,
-0x04,
-0xb4,
-0xf5,
-0x1f,
-0x7c,
-0x44,
-0x7a,
-0x3e,
-0x73,
-0x8c,
-0x38,
-0xcf,
-0xf2,
-0xd3,
-0xf6,
-0x3f,
-0x5a,
-0x76,
-0xd3,
-0x5b,
-0x2e,
-0x9f,
-0xb3,
-0xe7,
-0x93,
-0x11,
-0x05,
-0x55,
-0x14,
-0x8d,
-0xc1,
-0x6e,
-0x36,
-0x6e,
-0xa3,
-0xa0,
-0x0b,
-0xe1,
-0x48,
-0x7f,
-0x48,
-0x80,
-0x21,
-0x59,
-0x00,
-0x86,
-0xd9,
-0x1a,
-0x99,
-0x9e,
-0xf6,
-0x4d,
-0xa0,
-0xd7,
-0xbe,
-0xb0,
-0x2b,
-0x13,
-0x5d,
-0x5b,
-0xf3,
-0x01,
-0x7d,
-0xbc,
-0x46,
-0x99,
-0xd9,
-0xb4,
-0xdb,
-0xc8,
-0xd1,
-0x21,
-0x94,
-0x91,
-0xdc,
-0x7a,
-0x85,
-0xaf,
-0x74,
-0x9e,
-0x0b,
-0x18,
-0x05,
-0xfd,
-0xba,
-0xac,
-0x7a,
-0xea,
-0xa9,
-0x6e,
-0x07,
-0x32,
-0xf8,
-0x1d,
-0x0d,
-0x7b,
-0x18,
-0x6f,
-0x13,
-0x89,
-0x4c,
-0xb3,
-0x50,
-0x5d,
-0x8c,
-0x81,
-0xd5,
-0x2a,
-0x6f,
-0xf3,
-0xa4,
-0x93,
-0x7c,
-0x16,
-0xfd,
-0x25,
-0xf8,
-0x83,
-0xc7,
-0xd0,
-0x21,
-0xf9,
-0x51,
-0xc5,
-0xbb,
-0x6a,
-0x42,
-0xe6,
-0xfd,
-0x05,
-0x7e,
-0xa0,
-0x37,
-0x93,
-0x55,
-0x98,
-0x8b,
-0x30,
-0xbd,
-0x62,
-0x33,
-0x91,
-0xe3,
-0x44,
-0xd6,
-0xc5,
-0xa4,
-0x17,
-0x2d,
-0x70,
-0x97,
-0xaa,
-0x02,
-0xc3,
-0xa4,
-0x09,
-0x6f,
-0x7f,
-0x00,
-0xcf,
-0xae,
-0x5f,
-0x25,
-0xf5,
-0x5e,
-0xca,
-0x7b,
-0x7c,
-0x61,
-0x07,
-0x1c,
-0xd9,
-0x49,
-0xa5,
-0x9d,
-0x42,
-0xe4,
-0x74,
-0x93,
-0xe1,
-0x3f,
-0x8f,
-0xc0,
-0xa1,
-0x32,
-0x1a,
-0x83,
-0x06,
-0x3a,
-0x1b,
-0xb2,
-0x25,
-0x69,
-0xec,
-0x20,
-0xd5,
-0x9b,
-0x7a,
-0x9f,
-0x34,
-0xb0,
-0x27,
-0x23,
-0x20,
-0xa0,
-0x31,
-0xc1,
-0x24,
-0xd2,
-0x8e,
-0x34,
-0x1f,
-0x7c,
-0xd8,
-0xc7,
-0x75,
-0xb1,
-0x4c,
-0xe8,
-0x87,
-0x98,
-0xe1,
-0xbb,
-0x94,
-0x55,
-0xc3,
-0x63,
-0x25,
-0x1a,
-0xc8,
-0xae,
-0x0b,
-0xf4,
-0xd9,
-0xb9,
-0xe3,
-0xdc,
-0x5e,
-0x9a,
-0xb1,
-0x98,
-0x89,
-0x4c,
-0x2a,
-0x09,
-0x0e,
-0xfa,
-0x98,
-0x21,
-0x87,
-0xf3,
-0x58,
-0xe0,
-0xa9,
-0x8a,
-0xda,
-0xf5,
-0xc7,
-0x0b,
-0x70,
-0xa5,
-0x69,
-0x0c,
-0xe5,
-0x38,
-0x98,
-0x22,
-0xac,
-0x05,
-0xe4,
-0x45,
-0x56,
-0x77,
-0xa5,
-0xfe,
-0x34,
-0x5b,
-0xb9,
-0x45,
-0x58,
-0x1d,
-0x95,
-0xd2,
-0x62,
-0x60,
-0x86,
-0x88,
-0x19,
-0x03,
-0x2c,
-0xee,
-0xd6,
-0xc4,
-0x32,
-0x41,
-0x5d,
-0xa5,
-0x0b,
-0x71,
-0xfb,
-0x8c,
-0x6c,
-0xb0,
-0xdc,
-0x61,
-0x67,
-0x3d,
-0xfb,
-0xb1,
-0xec,
-0xf1,
-0x95,
-0xfc,
-0x5d,
-0x18,
-0x93,
-0x76,
-0xca,
-0x55,
-0x2c,
-0xdc,
-0x8c,
-0x87,
-0xf1,
-0x00,
-0x84,
-0xa6,
-0x55,
-0x91,
-0xab,
-0xf9,
-0x24,
-0xa5,
-0x27,
-0x55,
-0xfb,
-0xd4,
-0xb4,
-0xfd,
-0xac,
-0xc9,
-0xfe,
-0xdb,
-0xeb,
-0xcc,
-0x6f,
-0xd4,
-0x92,
-0x8a,
-0xa9,
-0x26,
-0x07,
-0xfb,
-0x4f,
-0x53,
-0x3d,
-0x89,
-0xa8,
-0x4c,
-0x94,
-0x7a,
-0xce,
-0xec,
-0xd5,
-0x4b,
-0xef,
-0x65,
-0xab,
-0x65,
-0xc0,
-0x3b,
-0x28,
-0xfe,
-0xfb,
-0xc9,
-0x83,
-0x6b,
-0xbc,
-0x72,
-0x42,
-0xf7,
-0x78,
-0x92,
-0x87,
-0x76,
-0xbe,
-0x0c,
-0x42,
-0x42,
-0x96,
-0x18,
-0x03,
-0x69,
-0x16,
-0x67,
-0xc6,
-0xe7,
-0x75,
-0xee,
-0xb6,
-0x1b,
-0x85,
-0x46,
-0xb4,
-0x65,
-0x0a,
-0x61,
-0xbb,
-0xb9,
-0xb3,
-0x37,
-0xf8,
-0x35,
-0x98,
-0x38,
-0x5d,
-0x93,
-0x3d,
-0x99,
-0x84,
-0x40,
-0x9d,
-0x66,
-0x3e,
-0x3b,
-0xd0,
-0x01,
-0x8a,
-0x67,
-0x83,
-0xce,
-0x26,
-0x48,
-0x76,
-0x93,
-0x70,
-0xa7,
-0xfe,
-0x13,
-0xee,
-0x5a,
-0x30,
-0x2c,
-0xcc,
-0xba,
-0xa9,
-0xe8,
-0x76,
-0x88,
-0xa7,
-0x8e,
-0x78,
-0x22,
-0xdf,
-0xec,
-0xc2,
-0x68,
-0xcf,
-0xf4,
-0x29,
-0x6d,
-0x19,
-0x6e,
-0x4d,
-0xad,
-0x35,
-0xee,
-0x07,
-0xb5,
-0xcf,
-0x20,
-0x80,
-0x77,
-0xf9,
-0xb7,
-0x45,
-0x78,
-0x63,
-0x3a,
-0x39,
-0x7b,
-0x44,
-0xec,
-0x82,
-0x0e,
-0x8f,
-0xf2,
-0x03,
-0xa8,
-0xaf,
-0x83,
-0x3d,
-0x3a,
-0xc5,
-0x54,
-0xfe,
-0xc0,
-0xf5,
-0xf4,
-0x98,
-0xf4,
-0x8d,
-0x96,
-0x2a,
-0x62,
-0xd2,
-0xbc,
-0x56,
-0x3c,
-0xfe,
-0x7d,
-0x46,
-0x7f,
-0x21,
-0x92,
-0x8d,
-0x57,
-0x15,
-0x3f,
-0xff,
-0xc7,
-0xe4,
-0x24,
-0x71,
-0x36,
-0xe3,
-0x25,
-0x7d,
-0xb3,
-0xf7,
-0xd1,
-0x18,
-0xf5,
-0x3e,
-0x0e,
-0xb3,
-0xa3,
-0xd8,
-0x60,
-0xda,
-0xa6,
-0x72,
-0xc6,
-0x84,
-0x09,
-0x2b,
-0xfe,
-0x74,
-0x0d,
-0x7b,
-0x71,
-0x40,
-0x74,
-0x99,
-0x2a,
-0xe9,
-0xc4,
-0x3e,
-0x1f,
-0xab,
-0x22,
-0x21,
-0x97,
-0xab,
-0x93,
-0x4a,
-0x72,
-0x3b,
-0x15,
-0xd8,
-0xc3,
-0x68,
-0x3f,
-0xd0,
-0x7f,
-0x21,
-0x48,
-0x6e,
-0xf2,
-0x68,
-0x41,
-0x16,
-0x49,
-0x6a,
-0x4c,
-0xdd,
-0xe0,
-0x44,
-0xd6,
-0x04,
-0xc1,
-0xc5,
-0x4a,
-0x3e,
-0x06,
-0x2c,
-0x6d,
-0x30,
-0x76,
-0x71,
-0x33,
-0xde,
-0x73,
-0x44,
-0x96,
-0x05,
-0xaa,
-0x3d,
-0x31,
-0x55,
-0xf7,
-0xdb,
-0x17,
-0x5f,
-0xa1,
-0xd0,
-0x36,
-0x9f,
-0xaa,
-0x95,
-0x82,
-0x46,
-0x79,
-0x78,
-0x77,
-0xaf,
-0x04,
-0x78,
-0x7d,
-0xe8,
-0x8a,
-0x5c,
-0x69,
-0xe2,
-0x88,
-0xce,
-0xca,
-0x21,
-0x18,
-0x0d,
-0x1b,
-0xe7,
-0x3c,
-0x14,
-0xec,
-0x8b,
-0xc6,
-0x55,
-0x30,
-0xf1,
-0x40,
-0x7f,
-0x4e,
-0x1d,
-0xda,
-0x86,
-0x81,
-0x05,
-0x72,
-0x3a,
-0x99,
-0xad,
-0x78,
-0xfc,
-0x96,
-0xcc,
-0x0e,
-0x81,
-0x0c,
-0xed,
-0xce,
-0x69,
-0x14,
-0x15,
-0xc9,
-0xdd,
-0xb5,
-0xf7,
-0xde,
-0xf5,
-0x9c,
-0xc7,
-0xc1,
-0xb9,
-0x09,
-0x8e,
-0xf7,
-0xd9,
-0xf2,
-0x05,
-0x02,
-0x36,
-0xe9,
-0x8d,
-0xb4,
-0x51,
-0x23,
-0x78,
-0xc2,
-0x2a,
-0x2f,
-0x27,
-0x2e,
-0x2e,
-0xa1,
-0x9f,
-0xda,
-0xb1,
-0x0d,
-0xc0,
-0x97,
-0x18,
-0x65,
-0x4e,
-0x87,
-0xa6,
-0x95,
-0xa7,
-0xdc,
-0x91,
-0xfd,
-0x10,
-0xee,
-0x32,
-0x36,
-0x23,
-0xad,
-0x79,
-0x66,
-0x68,
-0x16,
-0x6a,
-0x7a,
-0x91,
-0xe9,
-0xb6,
-0xd0,
-0xf7,
-0x38,
-0xc0,
-0xa2,
-0xca,
-0xd4,
-0xc0,
-0xcd,
-0x4a,
-0x68,
-0x01,
-0x07,
-0x8e,
-0x8d,
-0x82,
-0x85,
-0xd1,
-0x88,
-0x8c,
-0x7b,
-0xdf,
-0x90,
-0x9b,
-0x28,
-0x00,
-0xaa,
-0x4d,
-0x14,
-0x2f,
-0x65,
-0xd6,
-0x90,
-0x7a,
-0xe0,
-0x10,
-0xed,
-0xf0,
-0x04,
-0x80,
-0xff,
-0x52,
-0xb5,
-0xb3,
-0x66,
-0xae,
-0xb2,
-0x4c,
-0xe0,
-0x4f,
-0x69,
-0x18,
-0xa6,
-0x4e,
-0x1a,
-0x95,
-0xd2,
-0xf4,
-0x26,
-0xba,
-0x16,
-0xea,
-0xb6,
-0x51,
-0xdc,
-0x3f,
-0xf2,
-0x29,
-0xf8,
-0x5b,
-0x1a,
-0x6e,
-0x0a,
-0x21,
-0xa2,
-0x34,
-0x40,
-0x8a,
-0x58,
-0x10,
-0xb7,
-0xaa,
-0xe5,
-0x4b,
-0xa9,
-0x7a,
-0x7c,
-0x32,
-0x10,
-0xdd,
-0x74,
-0x32,
-0xca,
-0x21,
-0xfb,
-0x92,
-0x88,
-0x22,
-0x29,
-0xdd,
-0x51,
-0xe9,
-0xcc,
-0xcb,
-0x66,
-0x5f,
-0xca,
-0x4a,
-0x9d,
-0xd6,
-0x55,
-0x0a,
-0x5d,
-0xe9,
-0x6c,
-0x37,
-0xba,
-0x75,
-0x18,
-0x7c,
-0x00,
-0x4a,
-0x78,
-0x58,
-0x1f,
-0xec,
-0x47,
-0x75,
-0x74,
-0x21,
-0x13,
-0x69,
-0x66,
-0x44,
-0xe8,
-0x00,
-0x6f,
-0x7d,
-0xb9,
-0x31,
-0xc8,
-0xb1,
-0xdc,
-0xc2,
-0x62,
-0x52,
-0xf1,
-0x20,
-0x1d,
-0xeb,
-0x88,
-0x18,
-0x65,
-0x13,
-0x8f,
-0x78,
-0xba,
-0x5a,
-0xb9,
-0x2b,
-0x6c,
-0x80,
-0xe0,
-0xa7,
-0x5f,
-0xb9,
-0xec,
-0x1b,
-0x86,
-0x06,
-0x8a,
-0xbf,
-0x71,
-0x44,
-0x4f,
-0x41,
-0x73,
-0x32,
-0x59,
-0x01,
-0x33,
-0x54,
-0xac,
-0x5e,
-0xac,
-0xc2,
-0x0a,
-0xa4,
-0xd5,
-0xc3,
-0x54,
-0x05,
-0xbf,
-0x44,
-0xdc,
-0x72,
-0x3d,
-0xc8,
-0x44,
-0x6c,
-0x80,
-0x1f,
-0x69,
-0x16,
-0x85,
-0x65,
-0xbc,
-0xa1,
-0x99,
-0x50,
-0xd9,
-0x39,
-0xa7,
-0x7c,
-0xac,
-0xf1,
-0x0c,
-0xd7,
-0xdc,
-0xe7,
-0x2a,
-0xe4,
-0xf2,
-0xa4,
-0x6f,
-0xf4,
-0xe2,
-0xd5,
-0x12,
-0x36,
-0x93,
-0xa6,
-0xfd,
-0xdd,
-0xde,
-0x4c,
-0x07,
-0x11,
-0x43,
-0x25,
-0x31,
-0xa7,
-0x54,
-0x81,
-0x28,
-0x27,
-0x41,
-0x70,
-0xd9,
-0xb9,
-0x4e,
-0xce,
-0x45,
-0x40,
-0xe2,
-0xb8,
-0xa5,
-0x79,
-0xf6,
-0x39,
-0x8e,
-0xf8,
-0xae,
-0xfe,
-0x25,
-0x47,
-0x8c,
-0xc2,
-0x1a,
-0xc0,
-0x58,
-0x45,
-0x38,
-0x13,
-0x3b,
-0xbb,
-0x1e,
-0x2c,
-0xdf,
-0xf6,
-0x62,
-0xb0,
-0xe0,
-0x88,
-0x26,
-0xf1,
-0xab,
-0xd9,
-0xa0,
-0x5d,
-0x69,
-0x93,
-0x72,
-0x6c,
-0x4a,
-0xe0,
-0xef,
-0x9f,
-0x21,
-0xaf,
-0x2b,
-0x35,
-0x2a,
-0x27,
-0x73,
-0x52,
-0x3b
-};
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/F14MicrocodePatch05000025.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/F14MicrocodePatch05000025.c
deleted file mode 100644
index 8b969cd..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/F14MicrocodePatch05000025.c
+++ /dev/null
@@ -1,1645 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_14 Microcode patch.
- *
- * Fam14 Microcode Patch rev 05000025 for 5010 or equivalent.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x14
- * @e \$Revision: 37850 $ @e \$Date: 2010-09-13 18:09:57 -0400 (Mon, 13 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-// Patch code 05000025 for 5010 and equivalent
-CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch05000025 =
-{
-0x10,
-0x20,
-0x10,
-0x09,
-0x25,
-0x00,
-0x00,
-0x05,
-0x01,
-0x80,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x10,
-0x50,
-0x00,
-0x00,
-0x00,
-0xaa,
-0xaa,
-0xaa,
-0x17,
-0xbc,
-0xec,
-0xce,
-0xc4,
-0x2e,
-0xfb,
-0x70,
-0xa4,
-0x29,
-0x87,
-0x9b,
-0x3f,
-0xa9,
-0x10,
-0xbd,
-0xa1,
-0x80,
-0xc0,
-0x68,
-0x27,
-0x48,
-0x71,
-0xb4,
-0xea,
-0xce,
-0x31,
-0xd5,
-0xe4,
-0xa1,
-0xde,
-0xd2,
-0x94,
-0x1d,
-0x8f,
-0x0a,
-0x68,
-0xb7,
-0x2a,
-0x3c,
-0xa3,
-0x89,
-0x34,
-0x1c,
-0xc3,
-0x3c,
-0x6f,
-0x16,
-0x3e,
-0xba,
-0xfc,
-0x86,
-0xde,
-0x06,
-0xa7,
-0x6b,
-0xff,
-0x30,
-0xfd,
-0x1f,
-0x58,
-0x73,
-0x4f,
-0xf1,
-0x1a,
-0xf9,
-0x1e,
-0xca,
-0x26,
-0xb0,
-0x0f,
-0x44,
-0xb8,
-0xdc,
-0x94,
-0xb8,
-0xeb,
-0x74,
-0xbf,
-0x05,
-0x67,
-0x2e,
-0x97,
-0x5c,
-0x2d,
-0xfe,
-0x30,
-0xde,
-0xf9,
-0x2e,
-0xc0,
-0x82,
-0x72,
-0x8d,
-0xbf,
-0x1d,
-0x7c,
-0x24,
-0x74,
-0x81,
-0x41,
-0x63,
-0x3b,
-0x6c,
-0xe0,
-0x32,
-0x3e,
-0x64,
-0xb9,
-0xce,
-0x1a,
-0x66,
-0x6d,
-0x6a,
-0x99,
-0xcf,
-0x0d,
-0x98,
-0x7d,
-0x32,
-0x80,
-0xc6,
-0xf9,
-0x79,
-0x5f,
-0xe4,
-0x79,
-0x6e,
-0x2a,
-0xd4,
-0x19,
-0x8c,
-0xa1,
-0x39,
-0x94,
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-0xe0,
-0x76,
-0x08,
-0x08,
-0xd4,
-0xfb,
-0xb0,
-0xdc,
-0x2f,
-0xde,
-0xd9,
-0x33,
-0xb8,
-0x35,
-0x71,
-0x8f,
-0x1d,
-0x65,
-0xc5,
-0xec,
-0x78,
-0x74,
-0xa8,
-0x1a,
-0xa7,
-0x06,
-0xb3,
-0x99,
-0xf9,
-0x1a,
-0x61,
-0xf9,
-0xe6,
-0x1b,
-0xcd,
-0xa6,
-0xb7,
-0xcd,
-0x2d,
-0xa2,
-0xc1,
-0xd6,
-0xe2,
-0x75,
-0x1e,
-0x38,
-0x06,
-0xc2,
-0x9c,
-0x22,
-0xf9,
-0x5b,
-0x55,
-0xa8,
-0x09,
-0x8d,
-0x27,
-0x7c,
-0xb0,
-0x3a,
-0x69,
-0xd8,
-0xc9,
-0xd6,
-0x2c,
-0xb0,
-0x04,
-0xd3,
-0xb9,
-0xe2,
-0x16,
-0xdd,
-0x42,
-0x54,
-0x04,
-0x0a,
-0x97,
-0x6f,
-0x25,
-0xf7,
-0xfe,
-0x55,
-0xe0,
-0x56,
-0x52,
-0xc7,
-0x9b,
-0x0d,
-0x6d,
-0x43,
-0xd0,
-0x26,
-0xbf,
-0x5d,
-0x33,
-0x63,
-0xae,
-0x90,
-0x0f,
-0x57,
-0x66,
-0xe4,
-0x9d,
-0xb6,
-0x55,
-0xef,
-0x4c,
-0x12,
-0x35,
-0xb3,
-0x93,
-0x70,
-0x0b,
-0x8c,
-0x2b,
-0xe5,
-0x72,
-0x19,
-0x73,
-0x85,
-0x28,
-0x41,
-0x9d,
-0xbd,
-0xf3,
-0xc0,
-0xc9,
-0xd0,
-0x2b,
-0x1d,
-0xf2,
-0x0e,
-0xb8,
-0xea,
-0x32,
-0x8c,
-0x49,
-0x40,
-0x8c,
-0xcd,
-0xc4,
-0x4c,
-0x5d,
-0x43,
-0x9d,
-0x69,
-0x24,
-0x0f,
-0x77,
-0x0e,
-0xe2,
-0xb7,
-0x86,
-0x1d,
-0x55,
-0xd3,
-0x5f,
-0x72,
-0xa5,
-0x20,
-0x89,
-0x76,
-0xe7,
-0x07,
-0x45,
-0xc0,
-0x4d,
-0x1e,
-0x27,
-0xc0,
-0xed,
-0x3b,
-0x64,
-0xbb,
-0xc8,
-0x4f,
-0x99,
-0xad,
-0xb2,
-0xd3,
-0xc6,
-0xad,
-0x3e,
-0xc7,
-0x2f,
-0x73,
-0xee,
-0x63,
-0x69,
-0x90,
-0x8c,
-0x0a,
-0x3f,
-0x40,
-0xff,
-0xa9,
-0x16,
-0x72,
-0x95,
-0x87,
-0x02,
-0xca,
-0xa6,
-0x7c,
-0xd5,
-0x88,
-0x6f,
-0x20,
-0x0a,
-0xba,
-0xe3,
-0xdb,
-0x8a,
-0x5a,
-0x4c,
-0x60,
-0x53,
-0xc9,
-0x35,
-0x59,
-0x98,
-0xf1,
-0x08,
-0xc6,
-0xb8,
-0x9d,
-0x72,
-0xe1,
-0xee,
-0xc6,
-0x70,
-0x0e,
-0x11,
-0xbe,
-0xf6,
-0xbd,
-0x01,
-0x37,
-0xbf,
-0x54,
-0x5f,
-0xf1,
-0xf0,
-0x0a,
-0x31,
-0x36,
-0x9f,
-0xb9,
-0x9b,
-0xf8,
-0xbc,
-0x3a,
-0x97,
-0x68,
-0xb4,
-0xd1,
-0xfd,
-0x8b,
-0x45,
-0x56,
-0x5b,
-0x7f,
-0x46,
-0x76,
-0x00,
-0x67,
-0xbc
-};
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/F14PackageType.h b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/F14PackageType.h
deleted file mode 100644
index ca9188c..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/F14PackageType.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_14 Package Type Definitions
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F14
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _F14_PACKAGE_TYPE_H_
-#define _F14_PACKAGE_TYPE_H_
-
-
-/*---------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *---------------------------------------------------------------------------------------
- */
-// Below equates are defined to cooperate with LibAmdGetPackageType.
-#define PACKAGE_TYPE_FT1_BIT (1 << 0)
-
-// Raw data definitions
-#define PACKAGE_TYPE_FT1 0
-
-
-/*---------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *---------------------------------------------------------------------------------------
- */
-
-#endif // _F14_PACKAGE_TYPE_H_
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/ON/F14OnEquivalenceTable.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/ON/F14OnEquivalenceTable.c
deleted file mode 100644
index 3cadf73..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/ON/F14OnEquivalenceTable.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_14 Ontario Equivalence Table related data
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/Family/0x14
- * @e \$Revision: 36418 $ @e \$Date: 2010-08-18 17:00:58 +0800 (Wed, 18 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-#include "amdlib.h"
-#include "cpuRegisters.h"
-#define FILECODE PROC_CPU_FAMILY_0X14_ON_F14ONEQUIVALENCETABLE_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-STATIC CONST UINT16 ROMDATA CpuF14MicrocodeEquivalenceTable[] =
-{
- 0x5000, 0x5000,
- 0x5001, 0x5001,
- 0x5010, 0x5010
-};
-
-// Unencrypted equivalent
-STATIC CONST UINT16 ROMDATA CpuF14UnEncryptedMicrocodeEquivalenceTable[] =
-{
- 0x5000, 0x5800,
- 0x5001, 0x5801,
- 0x5010, 0x5810
-};
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns the appropriate microcode patch equivalent ID table.
- *
- * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[out] OnEquivalenceTablePtr Points to the first entry in the table.
- * @param[out] NumberOfElements Number of valid entries in the table.
- * @param[in] StdHeader Header for library and services.
- *
- */
-VOID
-GetF14OnMicrocodeEquivalenceTable (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- OUT CONST VOID **OnEquivalenceTablePtr,
- OUT UINT8 *NumberOfElements,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 MsrMeCfg;
-
- LibAmdMsrRead (MSR_ME_CFG, &MsrMeCfg, StdHeader);
- if ((MsrMeCfg & 0x1000) == 0) {
- *NumberOfElements = ((sizeof (CpuF14UnEncryptedMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
- *OnEquivalenceTablePtr = CpuF14UnEncryptedMicrocodeEquivalenceTable;
- } else {
- *NumberOfElements = ((sizeof (CpuF14MicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
- *OnEquivalenceTablePtr = CpuF14MicrocodeEquivalenceTable;
- }
-}
-
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.c
deleted file mode 100644
index f5f70bd..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.c
+++ /dev/null
@@ -1,309 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Implements the workaround for encrypted microcode patch loading.
- *
- * Returns the table of initialization steps to perform at
- * AmdInitEarly.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x14/ON
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "cpuRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuEarlyInit.h"
-#include "GnbRegistersON.h"
-#include "F14OnInitEarlyTable.h"
-#include "OptionFamily14hEarlySample.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-#define FILECODE PROC_CPU_FAMILY_0X14_ON_F14ONINITEARLYTABLE_FILECODE
-
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-// Field Data
-#define D18F4x164_FixedErrata_0_OFFSET 0
-#define D18F4x164_FixedErrata_0_WIDTH 1
-#define D18F4x164_FixedErrata_0_MASK 0x00000001
-#define D18F4x164_Reserved_31_1_OFFSET 1
-#define D18F4x164_Reserved_31_1_WIDTH 31
-#define D18F4x164_Reserved_31_1_MASK 0xFFFFFFFE
-
-extern F14_ES_CORE_SUPPORT F14EarlySampleCoreSupport;
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-VOID
-F14OnLoadMicrocodePatchAtEarly (
- IN CPU_SPECIFIC_SERVICES *FamilyServices,
- IN AMD_CPU_EARLY_PARAMS *EarlyParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-F14OnProductionErrataAtEarly (
- IN CPU_SPECIFIC_SERVICES *FamilyServices,
- IN AMD_CPU_EARLY_PARAMS *EarlyParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-extern F_PERFORM_EARLY_INIT_ON_CORE McaInitializationAtEarly;
-extern F_PERFORM_EARLY_INIT_ON_CORE SetRegistersFromTablesAtEarly;
-extern F_PERFORM_EARLY_INIT_ON_CORE SetBrandIdRegistersAtEarly;
-extern F_PERFORM_EARLY_INIT_ON_CORE LocalApicInitializationAtEarly;
-
-CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F14OnEarlyInitOnCoreTable[] =
-{
- {McaInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION},
- {SetRegistersFromTablesAtEarly, PERFORM_EARLY_ANY_CONDITION},
- {SetBrandIdRegistersAtEarly, PERFORM_EARLY_ANY_CONDITION},
- {LocalApicInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION},
- {F14OnLoadMicrocodePatchAtEarly, PERFORM_EARLY_ANY_CONDITION},
- {F14NbBufferAllocationAtEarly, PERFORM_EARLY_ANY_CONDITION},
- {F14OnProductionErrataAtEarly, PERFORM_EARLY_ANY_CONDITION},
- {NULL, 0}
-};
-
-/*------------------------------------------------------------------------------------*/
-/**
- * Initializer routine that may be invoked at AmdCpuEarly to return the steps that a
- * processor that uses the standard initialization steps should take.
- *
- * @CpuServiceMethod{::F_GET_EARLY_INIT_TABLE}.
- *
- * @param[in] FamilyServices The current Family Specific Services.
- * @param[out] Table Table of appropriate init steps for the executing core.
- * @param[in] EarlyParams Service Interface structure to initialize.
- * @param[in] StdHeader Opaque handle to standard config header.
- *
- */
-VOID
-GetF14OnEarlyInitOnCoreTable (
- IN CPU_SPECIFIC_SERVICES *FamilyServices,
- OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table,
- IN AMD_CPU_EARLY_PARAMS *EarlyParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- *Table = F14OnEarlyInitOnCoreTable;
-
- F14EarlySampleCoreSupport.F14GetEarlyInitTableHook (Table, StdHeader);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Update microcode patch in current processor for Family14h ON.
- *
- * This function acts as a wrapper for calling the LoadMicrocodePatch
- * routine at AmdInitEarly.
- *
- * @param[in] FamilyServices The current Family Specific Services.
- * @param[in] EarlyParams Service parameters.
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-F14OnLoadMicrocodePatchAtEarly (
- IN CPU_SPECIFIC_SERVICES *FamilyServices,
- IN AMD_CPU_EARLY_PARAMS *EarlyParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 MsrValue;
-
- AGESA_TESTPOINT (TpProcCpuLoadUcode, StdHeader);
- // To load a microcode patch while using the cache as general storage,
- // the following steps are followed:
- // 1. Program MSRC001_102B[L2AllocDcFlushVictim]=1.
- // 2. Load the microcode patch.
- // 3. Program MSRC001_102B[L2AllocDcFlushVictim]=0.
- LibAmdMsrRead (MSR_BU_CFG3, &MsrValue, StdHeader);
- MsrValue = MsrValue | BIT7;
- LibAmdMsrWrite (MSR_BU_CFG3, &MsrValue, StdHeader);
-
- LoadMicrocodePatch (StdHeader);
-
- LibAmdMsrRead (MSR_BU_CFG3, &MsrValue, StdHeader);
- MsrValue = MsrValue & ~((UINT64)BIT7);
- LibAmdMsrWrite (MSR_BU_CFG3, &MsrValue, StdHeader);
-}
-
-/**
- * North bridge bufer allocation for Family14h ON.
- *
- * This function programs North bridge buffer allocation registers and provides
- * hook routine for override at AmdInitEarly.
- *
- * @param[in] FamilyServices The current Family Specific Services.
- * @param[in] EarlyParams Service parameters.
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-F14NbBufferAllocationAtEarly (
- IN CPU_SPECIFIC_SERVICES *FamilyServices,
- IN AMD_CPU_EARLY_PARAMS *EarlyParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- //Buffer allocations cannot be decreased through software, so move these register setting from register table
- //to here to make IDS easy override
- NB_BUFFER_ALLOCATION NbBufAllocation;
- PCI_ADDR PciAddr;
- AGESA_STATUS Ignored;
-
- if (IsBsp (StdHeader, &Ignored)) {
- PciAddr.AddressValue = MAKE_SBDFO (0, 0, 24, FUNC_3, D18F3x6C_ADDRESS);
- LibAmdPciRead (AccessWidth32, PciAddr, &NbBufAllocation.D18F3x6C.Value, StdHeader);
- PciAddr.Address.Register = D18F3x74_ADDRESS;
- LibAmdPciRead (AccessWidth32, PciAddr, &NbBufAllocation.D18F3x74.Value, StdHeader);
- PciAddr.Address.Register = D18F3x7C_ADDRESS;
- LibAmdPciRead (AccessWidth32, PciAddr, &NbBufAllocation.D18F3x7C.Value, StdHeader);
- PciAddr.Address.Register = D18F3x17C_ADDRESS;
- LibAmdPciRead (AccessWidth32, PciAddr, &NbBufAllocation.D18F3x17C.Value, StdHeader);
- //Recommend value for NB buffer allocation
- // D18F3x6C - Upstream Data Buffer Count
- // bits[3:0] UpLoPreqDBC = 0x0E
- // bits[7:4] UpLoNpReqDBC = 1
- // bits[11:8] UpLoRespDBC = 1
- // bits[19:16] UpHiPreqDBC = 0
- // bits[23:20] UpHiNpReqDBC = 0
- NbBufAllocation.D18F3x6C.Field.UpLoPreqDBC = 0x0E;
- NbBufAllocation.D18F3x6C.Field.UpLoNpreqDBC = 1;
- NbBufAllocation.D18F3x6C.Field.UpLoRespDBC = 1;
- NbBufAllocation.D18F3x6C.Field.UpHiPreqDBC = 0;
- NbBufAllocation.D18F3x6C.Field.UpHiNpreqDBC = 0;
-
- // D18F3x74 - Upstream Command Buffer Count
- // bits[3:0] UpLoPreqCBC = 7
- // bits[7:4] UpLoNpreqCBC = 9
- // bits[11:8] UpLoRespCBC = 8
- // bits[19:16] UpHiPreqCBC = 0
- // bits[23:20] UpHiNpreqCBC = 0
- NbBufAllocation.D18F3x74.Field.UpLoPreqCBC = 7;
- NbBufAllocation.D18F3x74.Field.UpLoNpreqCBC = 9;
- NbBufAllocation.D18F3x74.Field.UpLoRespCBC = 8;
- NbBufAllocation.D18F3x74.Field.UpHiPreqCBC = 0;
- NbBufAllocation.D18F3x74.Field.UpHiNpreqCBC = 0;
-
- // D18F3x7C - In-Flight Queue Buffer Allocation
- // bits[5:0] CpuBC = 1
- // bits[13:8] LoPriPBC = 1
- // bits[21:16] LoPriNPBC = 1
- // bits[29:24] FreePoolBC = 0x19
- NbBufAllocation.D18F3x7C.Field.CpuBC = 1;
- NbBufAllocation.D18F3x7C.Field.LoPriPBC = 1;
- NbBufAllocation.D18F3x7C.Field.LoPriNPBC = 1;
- NbBufAllocation.D18F3x7C.Field.FreePoolBC = 0x19;
-
- // D18F3x17C - In-Flight Queue Extended Buffer Allocation
- // bits[5:0] HiPriPBC = 0
- // bits[13:8] HiPriNPBC = 0
- NbBufAllocation.D18F3x17C.Field.HiPriPBC = 0;
- NbBufAllocation.D18F3x17C.Field.HiPriNPBC = 0;
-
- IDS_OPTION_HOOK (IDS_NBBUFFERALLOCATIONATEARLY, &NbBufAllocation, StdHeader);
-
- PciAddr.AddressValue = MAKE_SBDFO (0, 0, 24, FUNC_3, D18F3x6C_ADDRESS);
- LibAmdPciWrite (AccessWidth32, PciAddr, &NbBufAllocation.D18F3x6C.Value, StdHeader);
- PciAddr.Address.Register = D18F3x74_ADDRESS;
- LibAmdPciWrite (AccessWidth32, PciAddr, &NbBufAllocation.D18F3x74.Value, StdHeader);
- PciAddr.Address.Register = D18F3x7C_ADDRESS;
- LibAmdPciWrite (AccessWidth32, PciAddr, &NbBufAllocation.D18F3x7C.Value, StdHeader);
- PciAddr.Address.Register = D18F3x17C_ADDRESS;
- LibAmdPciWrite (AccessWidth32, PciAddr, &NbBufAllocation.D18F3x17C.Value, StdHeader);
- }
-}
-
-/**
- * Production Erratum for Family14h ON.
- *
- * This function implements production errata for Family14h ON.
- * routine at AmdInitEarly.
- *
- * @param[in] FamilyServices The current Family Specific Services.
- * @param[in] EarlyParams Service parameters.
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-F14OnProductionErrataAtEarly (
- IN CPU_SPECIFIC_SERVICES *FamilyServices,
- IN AMD_CPU_EARLY_PARAMS *EarlyParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- CPU_LOGICAL_ID LogicalId;
- PCI_ADDR PciAddr;
- UINT32 PciData;
- UINT64 MsrValue;
-
- GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
- PciAddr.AddressValue = MAKE_SBDFO (0, 0, 24, FUNC_4, D18F4x164_ADDRESS);
- LibAmdPciRead (AccessWidth32, PciAddr, &PciData, StdHeader);
- if (((PciData & D18F4x164_FixedErrata_0_MASK) == 1) &&
- ((LogicalId.Revision & ~(AMD_F14_ON_Ax | AMD_F14_UNKNOWN)) != 0)) {
- // Program MSRC001_1020[18] = 1 only when D18F4x164[0] == 1 on ON B0 and later parts.
- LibAmdMsrRead (MSR_LS_CFG, &MsrValue, StdHeader);
- MsrValue = MsrValue | BIT18;
- LibAmdMsrWrite (MSR_LS_CFG, &MsrValue, StdHeader);
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.h b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.h
deleted file mode 100644
index 5d6074c..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Implements the workaround for encrypted microcode patch loading.
- *
- * Returns the table of initialization steps to perform at
- * AmdInitEarly.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x14/ON
- * @e \$Revision: 37004 $ @e \$Date: 2010-08-28 02:23:00 +0800 (Sat, 28 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-VOID
-F14NbBufferAllocationAtEarly (
- IN CPU_SPECIFIC_SERVICES *FamilyServices,
- IN AMD_CPU_EARLY_PARAMS *EarlyParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-
-/// define NB buffer allocation setting
-typedef struct _NB_BUFFER_ALLOCATION {
- D18F3x6C_STRUCT D18F3x6C; ///< reg for D18F3x6C
- D18F3x74_STRUCT D18F3x74; ///< reg for D18F3x74
- D18F3x7C_STRUCT D18F3x7C; ///< reg for D18F3x7C
- D18F3x17C_STRUCT D18F3x17C; ///< reg for D18F3x17C
-} NB_BUFFER_ALLOCATION;
-
-/// enum for ON Erratum 463 wrokaround
-typedef enum {
- ON_ERRATUM463_WORKAROUND_DISABLE = 0, ///< work around disable
- ON_ERRATUM463_WORKAROUND_ENABLE = 1, ///< work around enable
-} ON_ERRATUM463_WORKAROUND;
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/ON/F14OnLogicalIdTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/ON/F14OnLogicalIdTables.c
deleted file mode 100644
index 82498c7..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/ON/F14OnLogicalIdTables.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_14 Ontario Logical ID Table
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x14
- * @e \$Revision: 36248 $ @e \$Date: 2010-08-16 16:15:26 +0800 (Mon, 16 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Filecode.h"
-#define FILECODE PROC_CPU_FAMILY_0X14_ON_F14ONLOGICALIDTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF14OnLogicalIdAndRevArray[] =
-{
- {
- 0x5000,
- AMD_F14_ON_A0
- },
- {
- 0x5001,
- AMD_F14_ON_A1
- },
- {
- 0x5010,
- AMD_F14_ON_B0
- }
-};
-
-VOID
-GetF14OnLogicalIdAndRev (
- OUT CONST CPU_LOGICAL_ID_XLAT **OnIdPtr,
- OUT UINT8 *NumberOfElements,
- OUT UINT64 *LogicalFamily,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- *NumberOfElements = (sizeof (CpuF14OnLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT));
- *OnIdPtr = CpuF14OnLogicalIdAndRevArray;
- *LogicalFamily = AMD_FAMILY_14_ON;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c
deleted file mode 100644
index ba4b013..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_14 Ontario PCI tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/Family/0x10
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-#define FILECODE PROC_CPU_FAMILY_0X14_ON_F14ONMICROCODEPATCHTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-extern CONST MICROCODE_PATCHES ROMDATA *CpuF14OnMicroCodePatchArray[];
-extern CONST UINT8 ROMDATA CpuF14OnNumberOfMicrocodePatches;
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns a table containing the appropriate microcode patches.
- *
- * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[out] OnUcodePtr Points to the first entry in the table.
- * @param[out] NumberOfElements Number of valid entries in the table.
- * @param[in] StdHeader Header for library and services.
- *
- */
-VOID
-GetF14OnMicroCodePatchesStruct (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- OUT CONST VOID **OnUcodePtr,
- OUT UINT8 *NumberOfElements,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- *NumberOfElements = CpuF14OnNumberOfMicrocodePatches;
- *OnUcodePtr = &CpuF14OnMicroCodePatchArray[0];
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuCommonF14Utilities.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuCommonF14Utilities.c
deleted file mode 100644
index 226e951..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuCommonF14Utilities.c
+++ /dev/null
@@ -1,518 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_14 specific utility functions.
- *
- * Provides numerous utility functions specific to family 10h.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F14
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuCommonF14Utilities.h"
-#include "cpuF14PowerMgmt.h"
-#include "OptionFamily14hEarlySample.h"
-#include "NbSmuLib.h"
-#include "GnbRegistersON.h"
-#include "Filecode.h"
-#define FILECODE PROC_CPU_FAMILY_0X14_CPUCOMMONF14UTILITIES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-extern F14_ES_CORE_SUPPORT F14EarlySampleCoreSupport;
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-CONST UINT16 ROMDATA F14MaxNbFreqAtMinVidFreqTable[] =
-{
- 25, // 00000b
- 50, // 00001b
- 100, // 00010b
- 150, // 00011b
- 167, // 00100b
- 183, // 00101b
- 200, // 00110b
- 217, // 00111b
- 233, // 01000b
- 250, // 01001b
- 267, // 01010b
- 283, // 01011b
- 300, // 01100b
- 317, // 01101b
- 333, // 01110b
- 350, // 01111b
- 366, // 10000b
- 383, // 10001b
- 400, // 10010b
- 417, // 10011b
- 433, // 10100b
- 450, // 10101b
- 467, // 10110b
- 483, // 10111b
- 500, // 11000b
- 517, // 11001b
- 533, // 11010b
- 550, // 11011b
- 563, // 11100b
- 575, // 11101b
- 588, // 11110b
- 600 // 11111b
-};
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-UINT32
-STATIC
-RoundedDivision (
- IN UINT32 Dividend,
- IN UINT32 Divisor
- );
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Set warm reset status and count
- *
- * @CpuServiceMethod{::F_CPU_SET_WARM_RESET_FLAG}.
- *
- * This function will use bit9, and bit 10 of register F0x6C as a warm reset status and count.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- * @param[in] Request Indicate warm reset status
- *
- */
-VOID
-F14SetAgesaWarmResetFlag (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN WARM_RESET_REQUEST *Request
- )
-{
- PCI_ADDR PciAddress;
- UINT32 PciData;
-
- PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_0, HT_INIT_CTRL);
- LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
-
- // bit[5] - indicate a warm reset is or is not required
- PciData &= ~(HT_INIT_BIOS_RST_DET_0);
- PciData = PciData | (Request->RequestBit << 5);
-
- // bit[10,9] - indicate warm reset status and count
- PciData &= ~(HT_INIT_BIOS_RST_DET_1 | HT_INIT_BIOS_RST_DET_2);
- PciData |= Request->StateBits << 9;
-
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Get warm reset status and count
- *
- * @CpuServiceMethod{::F_CPU_GET_WARM_RESET_FLAG}.
- *
- * This function will bit9, and bit 10 of register F0x6C as a warm reset status and count.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] StdHeader Config handle for library and services
- * @param[out] Request Indicate warm reset status
- *
- */
-VOID
-F14GetAgesaWarmResetFlag (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CONFIG_PARAMS *StdHeader,
- OUT WARM_RESET_REQUEST *Request
- )
-{
- PCI_ADDR PciAddress;
- UINT32 PciData;
-
- PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_0, HT_INIT_CTRL);
- LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
-
- // bit[5] - indicate a warm reset is or is not required
- Request->RequestBit = (UINT8) ((PciData & HT_INIT_BIOS_RST_DET_0) >> 5);
- // bit[10,9] - indicate warm reset status and count
- Request->StateBits = (UINT8) ((PciData & (HT_INIT_BIOS_RST_DET_1 | HT_INIT_BIOS_RST_DET_2)) >> 9);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Use the Mailbox Register to get the Ap Mailbox info for the current core.
- *
- * @CpuServiceMethod{::F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE}.
- *
- * Access the mailbox register used with this NB family. This is valid until the
- * point that some init code initializes the mailbox register for its normal use.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[out] ApMailboxInfo The AP Mailbox info
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- */
-VOID
-F14GetApMailboxFromHardware (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- OUT AP_MAILBOXES *ApMailboxInfo,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- // For Family 14h, we will return socket 0, node 0, module 0, module type 0, and 0 for
- // the system degree
- ApMailboxInfo->ApMailInfo.Info = (UINT32) 0x00000000;
- ApMailboxInfo->ApMailExtInfo.Info = (UINT32) 0x00000000;
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Get this AP's system core number from hardware.
- *
- * @CpuServiceMethod{::F_CPU_GET_AP_CORE_NUMBER}.
- *
- * Returns the system core number. For family 14h, this is simply the
- * initial APIC ID.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @return The AP's unique core number
- */
-UINT32
-F14GetApCoreNumber (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- CPUID_DATA Cpuid;
-
- LibAmdCpuidRead (0x1, &Cpuid, StdHeader);
- return ((Cpuid.EBX_Reg >> 24) & 0xFF);
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Return a number zero or one, based on the Core ID position in the initial APIC Id.
- *
- * @CpuServiceMethod{::F_CORE_ID_POSITION_IN_INITIAL_APIC_ID}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @retval CoreIdPositionZero Core Id is not low
- * @retval CoreIdPositionOne Core Id is low
- */
-CORE_ID_POSITION
-F14CpuAmdCoreIdPositionInInitialApicId (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- return (CoreIdPositionOne);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Sets up a valid set of NB P-states based on the value of MEMCLK, transitions
- * to the desired NB P-state, and returns the current NB frequency in megahertz.
- *
- * @param[in] TargetMemclk The target MEMCLK in megahertz, or zero to
- * indicate NB P-state change only.
- * @param[in] TargetMemclkEncoded The target MEMCLK's register encoding.
- * @param[in] TargetNbPstate The NB P-state to exit in.
- * @param[in] CurrentNbFreq Current NB operating frequency in megahertz.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @retval TRUE Transition to TargetNbPstate was successful.
- * @retval FALSE Transition to TargetNbPstate was unsuccessful.
- */
-BOOLEAN
-F14NbPstateInit (
- IN UINT32 TargetMemclk,
- IN UINT32 TargetMemclkEncoded,
- IN UINT32 TargetNbPstate,
- OUT UINT32 *CurrentNbFreq,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 EncodedNbPs1Vid;
- UINT32 EncodedNbPs0NclkDiv;
- UINT32 EncodedNbPs1NclkDiv;
- UINT32 NbP0Cof;
- UINT32 NbP1Cof;
- UINT32 NbPstateNumerator;
- UINT32 TargetNumerator;
- UINT32 TargetDenominator;
- BOOLEAN ReturnStatus;
- PCI_ADDR PciAddress;
- D18F3xD4_STRUCT Cptc0;
- D18F3xDC_STRUCT Cptc2;
- D18F6x90_STRUCT NbPsCfgLow;
- D18F6x98_STRUCT NbPsCtrlSts;
- FCRxFE00_6000_STRUCT FCRxFE00_6000;
- FCRxFE00_6002_STRUCT FCRxFE00_6002;
- FCRxFE00_7006_STRUCT FCRxFE00_7006;
- FCRxFE00_7009_STRUCT FCRxFE00_7009;
-
- // F14 only supports NB P0 and NB P1
- ASSERT (TargetNbPstate < 2);
-
- ReturnStatus = TRUE;
-
- // Get D18F3xD4[MainPllOpFreqId] frequency
- PciAddress.AddressValue = CPTC0_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &Cptc0.Value, StdHeader);
-
- // Calculate the numerator to be used for NB P-state calculations
- NbPstateNumerator = (UINT32) (4 * ((Cptc0.Field.MainPllOpFreqId + 0x10) * 100));
-
- if (TargetMemclk != 0) {
- // Determine the appropriate numerator / denominator of the target memclk
- switch (TargetMemclk) {
- case DDR800_FREQUENCY:
- TargetNumerator = 400;
- TargetDenominator = 1;
- break;
- case DDR1066_FREQUENCY:
- TargetNumerator = 1600;
- TargetDenominator = 3;
- break;
- case DDR1333_FREQUENCY:
- TargetNumerator = 2000;
- TargetDenominator = 3;
- break;
- default:
- // An invalid memclk has been passed in.
- ASSERT (FALSE);
- TargetNumerator = TargetMemclk;
- TargetDenominator = 1;
- break;
- }
-
- FCRxFE00_6000.Value = NbSmuReadEfuse (FCRxFE00_6000_ADDRESS, StdHeader);
- FCRxFE00_6002.Value = NbSmuReadEfuse (FCRxFE00_6002_ADDRESS, StdHeader);
- FCRxFE00_7006.Value = NbSmuReadEfuse (FCRxFE00_7006_ADDRESS, StdHeader);
- FCRxFE00_7009.Value = NbSmuReadEfuse (FCRxFE00_7009_ADDRESS, StdHeader);
-
- F14EarlySampleCoreSupport.F14NbPstateInitHook (&FCRxFE00_6000,
- &FCRxFE00_6002,
- &FCRxFE00_7006,
- &FCRxFE00_7009,
- NbPstateNumerator,
- StdHeader);
-
- // Determine NB P0 settings
- if ((TargetNumerator * FCRxFE00_7009.Field.NbPs0NclkDiv) < (NbPstateNumerator * TargetDenominator)) {
- // Program D18F3xDC[NbPs0NclkDiv] to the minimum divisor where
- // (target memclk frequency >= (D18F3xD4[MainPllOpFreqId] freq) / divisor)
- EncodedNbPs0NclkDiv = ((NbPstateNumerator * TargetDenominator) / TargetNumerator);
- if (((NbPstateNumerator * TargetDenominator) % TargetNumerator) != 0) {
- EncodedNbPs0NclkDiv++;
- }
- // Ensure that the encoded divisor is even to give 50% duty cycle
- EncodedNbPs0NclkDiv = ((EncodedNbPs0NclkDiv + 1) & 0xFFFFFFFE);
-
- ASSERT (EncodedNbPs0NclkDiv >= 8);
- ASSERT (EncodedNbPs0NclkDiv <= 0x3F);
- } else {
- EncodedNbPs0NclkDiv = FCRxFE00_7009.Field.NbPs0NclkDiv;
- }
-
- // Check to see if the DIMMs are too fast for the CPU (NB P0 COF < (Memclk / 2))
- if ((TargetNumerator * EncodedNbPs0NclkDiv) > (NbPstateNumerator * TargetDenominator * 2)) {
- // Indicate the error to the memory code so the DIMMs can be derated.
- ReturnStatus = FALSE;
- }
-
- // Apply the appropriate P0 frequency
- PciAddress.AddressValue = CPTC2_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &Cptc2.Value, StdHeader);
- Cptc2.Field.NbPs0NclkDiv = EncodedNbPs0NclkDiv;
- LibAmdPciWrite (AccessWidth32, PciAddress, &Cptc2.Value, StdHeader);
- NbP0Cof = RoundedDivision (NbPstateNumerator, EncodedNbPs0NclkDiv);
-
- // Determine NB P1 settings if necessary
- PciAddress.AddressValue = NB_PSTATE_CFG_LOW_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCfgLow.Value, StdHeader);
- if (NbPsCfgLow.Field.NbPsCap == 1) {
- if ((TargetNumerator * FCRxFE00_7006.Field.NbPs1NclkDiv) > (NbPstateNumerator * TargetDenominator * 2)) {
- // Program D18F6x90[NbPs1NclkDiv] to the maximum divisor where
- // (target memclk frequency / 2 <= (D18F3xD4[MainPllOpFreqId] freq) / divisor)
- EncodedNbPs1NclkDiv = ((NbPstateNumerator * TargetDenominator * 2) / TargetNumerator);
-
- // Ensure that the encoded divisor is even to give 50% duty cycle
- EncodedNbPs1NclkDiv &= 0xFFFFFFFE;
- ASSERT (EncodedNbPs1NclkDiv >= 8);
- ASSERT (EncodedNbPs1NclkDiv <= 0x3F);
-
- // Calculate the new effective P1 frequency to determine the voltage
- NbP1Cof = RoundedDivision (NbPstateNumerator, EncodedNbPs1NclkDiv);
-
- if (NbP1Cof <= F14MaxNbFreqAtMinVidFreqTable[FCRxFE00_7006.Field.MaxNbFreqAtMinVid]) {
- // Program D18F6x90[NbPs1Vid] = FCRxFE00_6002[NbPs1VidAddl]
- EncodedNbPs1Vid = FCRxFE00_6002.Field.NbPs1VidAddl;
- } else {
- // Program D18F6x90[NbPs1Vid] = FCRxFE00_6002[NbPs1VidHigh]
- EncodedNbPs1Vid = FCRxFE00_6002.Field.NbPs1VidHigh;
- }
- } else {
- // Fused frequency and voltage are legal
- EncodedNbPs1Vid = FCRxFE00_6000.Field.NbPs1Vid;
- EncodedNbPs1NclkDiv = FCRxFE00_7006.Field.NbPs1NclkDiv;
- NbP1Cof = RoundedDivision (NbPstateNumerator, EncodedNbPs1NclkDiv);
- }
-
- if (NbP0Cof < NbP1Cof) {
- // NB P1 frequency is faster than NB P0. Fix it up by slowing
- // P1 to match P0.
- EncodedNbPs1NclkDiv = EncodedNbPs0NclkDiv;
- NbP1Cof = NbP0Cof;
- }
-
- // Program the new NB P1 settings
- NbPsCfgLow.Field.NbPs1NclkDiv = EncodedNbPs1NclkDiv;
- NbPsCfgLow.Field.NbPs1Vid = EncodedNbPs1Vid;
- LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCfgLow.Value, StdHeader);
- } else {
- // NB P-states are not enabled
- NbP1Cof = 0;
- }
- *CurrentNbFreq = NbP0Cof;
- } else {
- // Get NB P0 COF
- PciAddress.AddressValue = CPTC2_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &Cptc2.Value, StdHeader);
- NbP0Cof = RoundedDivision (NbPstateNumerator, Cptc2.Field.NbPs0NclkDiv);
-
- // Read NB P-state status
- PciAddress.AddressValue = NB_PSTATE_CTRL_STS_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlSts.Value, StdHeader);
-
- // Read low config register
- PciAddress.AddressValue = NB_PSTATE_CFG_LOW_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCfgLow.Value, StdHeader);
- if (TargetNbPstate == 1) {
- // If target is P1, the CPU MUST be in P0, otherwise the P1 settings
- // cannot be realized. This is a programming error.
- ASSERT (NbPsCtrlSts.Field.NbPs1Act == 0);
-
- if (NbPsCfgLow.Field.NbPsCap == 1) {
- // The part is capable of NB P-states. Transition to P1.
- NbPsCfgLow.Field.NbPsForceSel = 1;
- LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCfgLow.Value, StdHeader);
-
- // Wait for the transition to complete.
- PciAddress.AddressValue = NB_PSTATE_CTRL_STS_PCI_ADDR;
- do {
- LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlSts.Value, StdHeader);
- } while (NbPsCtrlSts.Field.NbPs1Act != 1);
-
- *CurrentNbFreq = RoundedDivision (NbPstateNumerator, NbPsCfgLow.Field.NbPs1NclkDiv);
- } else {
- // No NB P-states. Return FALSE, and set current frequency to P0.
- *CurrentNbFreq = NbP0Cof;
- ReturnStatus = FALSE;
- }
- } else {
- // Target P0
- *CurrentNbFreq = NbP0Cof;
- if (NbPsCtrlSts.Field.NbPs1Act != 0) {
- // Request transition to P0
- NbPsCfgLow.Field.NbPsForceSel = 0;
- LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCfgLow.Value, StdHeader);
- }
- }
- }
-
- // Ensure that the frequency has settled before returning to memory code.
- PciAddress.AddressValue = CPTC2_PCI_ADDR;
- do {
- LibAmdPciRead (AccessWidth32, PciAddress, &Cptc2.Value, StdHeader);
- } while (Cptc2.Field.NclkFreqDone != 1);
-
- return ReturnStatus;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Performs integer division, and rounds the quotient up if the remainder is greater
- * than or equal to 50% of the divisor.
- *
- * @param[in] Dividend The target MEMCLK in megahertz.
- * @param[in] Divisor The target MEMCLK's register encoding.
- *
- * @return The rounded quotient
- */
-UINT32
-STATIC
-RoundedDivision (
- IN UINT32 Dividend,
- IN UINT32 Divisor
- )
-{
- UINT32 Quotient;
-
- ASSERT (Divisor != 0);
-
- Quotient = Dividend / Divisor;
- if (((Dividend % Divisor) * 2) >= Divisor) {
- Quotient++;
- }
- return Quotient;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuCommonF14Utilities.h b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuCommonF14Utilities.h
deleted file mode 100644
index e40dccb..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuCommonF14Utilities.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family 14h specific utility functions
- *
- * Provides numerous utility functions specific to Family 14h
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/Family/0x14
- * @e \$Revision: 37640 $ @e \$Date: 2010-09-08 23:01:59 +0800 (Wed, 08 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPU_COMMON_F14_UTILITES_H_
-#define _CPU_COMMON_F14_UTILITES_H_
-
-
-/*---------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *---------------------------------------------------------------------------------------
- */
-
-VOID
-F14SetAgesaWarmResetFlag (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN WARM_RESET_REQUEST *Request
- );
-
-VOID
-F14GetAgesaWarmResetFlag (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CONFIG_PARAMS *StdHeader,
- OUT WARM_RESET_REQUEST *Request
- );
-
-VOID
-F14GetApMailboxFromHardware (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- OUT AP_MAILBOXES *ApMailboxInfo,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-BOOLEAN
-F14NbPstateInit (
- IN UINT32 TargetMemclk,
- IN UINT32 TargetMemclkEncoded,
- IN UINT32 TargetNbPstate,
- OUT UINT32 *CurrentNbFreq,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif // _CPU_COMMON_F14_UTILITES_H_
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14BrandId.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14BrandId.c
deleted file mode 100644
index db19787..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14BrandId.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU BrandId related functions and structures.
- *
- * Contains code that provides CPU BrandId information
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 36556 $ @e \$Date: 2010-08-21 01:25:52 +0800 (Sat, 21 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-#define FILECODE PROC_CPU_FAMILY_0X14_CPUF14BRANDID_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-extern CPU_BRAND_TABLE *F14BrandIdString1Tables[];
-extern CPU_BRAND_TABLE *F14BrandIdString2Tables[];
-extern CONST UINT8 F14BrandIdString1TableCount;
-extern CONST UINT8 F14BrandIdString2TableCount;
-
-/*---------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *---------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns a table containing the appropriate beginnings of the CPU brandstring.
- *
- * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[out] BrandString1Ptr Points to the first entry in the table.
- * @param[out] NumberOfElements Number of valid entries in the table.
- * @param[in] StdHeader Header for library and services.
- *
- */
-VOID
-GetF14BrandIdString1 (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- OUT CONST VOID **BrandString1Ptr,
- OUT UINT8 *NumberOfElements,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- CPU_BRAND_TABLE **TableEntryPtr;
-
- TableEntryPtr = &F14BrandIdString1Tables[0];
- *BrandString1Ptr = TableEntryPtr;
- *NumberOfElements = F14BrandIdString1TableCount;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns a table containing the appropriate endings of the CPU brandstring.
- *
- * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[out] BrandString2Ptr Points to the first entry in the table.
- * @param[out] NumberOfElements Number of valid entries in the table.
- * @param[in] StdHeader Header for library and services.
- *
- */
-VOID
-GetF14BrandIdString2 (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- OUT CONST VOID **BrandString2Ptr,
- OUT UINT8 *NumberOfElements,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- CPU_BRAND_TABLE **TableEntryPtr;
-
- TableEntryPtr = &F14BrandIdString2Tables[0];
- *BrandString2Ptr = TableEntryPtr;
- *NumberOfElements = F14BrandIdString2TableCount;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14BrandIdFt1.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14BrandIdFt1.c
deleted file mode 100644
index 2d4e34d..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14BrandIdFt1.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU BrandId related functions and structures.
- *
- * Contains code that provides CPU BrandId information
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 40034 $ @e \$Date: 2010-10-19 04:03:22 +0800 (Tue, 19 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-#include "F14PackageType.h"
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-// String1
-CONST CHAR8 ROMDATA str_AMD_C[] = "AMD C-";
-CONST CHAR8 ROMDATA str_AMD_E[] = "AMD E-";
-CONST CHAR8 ROMDATA str_AMD_G_T[] = "AMD G-T";
-
-// String2
-CONST CHAR8 ROMDATA str___Processor[] = " Processor";
-CONST CHAR8 ROMDATA str___0_Processor[] = "0 Processor";
-CONST CHAR8 ROMDATA str_5_Processor[] = "5 Processor";
-CONST CHAR8 ROMDATA str_0x_Processor[] = "0x Processor";
-CONST CHAR8 ROMDATA str_5x_Processor[] = "5x Processor";
-CONST CHAR8 ROMDATA str_x_Processor[] = "x Processor";
-CONST CHAR8 ROMDATA str_L_Processor[] = "L Processor";
-CONST CHAR8 ROMDATA str_N_Processor[] = "N Processor";
-CONST CHAR8 ROMDATA str_R_Processor[] = "R Processor";
-
-/*---------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *---------------------------------------------------------------------------------------
- */
-
-CONST AMD_CPU_BRAND ROMDATA CpuF14OnBrandIdString1ArrayFt1[] =
-{
- // FT1
- {1, 0, 1, ON_SOCKET_FT1, str_AMD_C, sizeof (str_AMD_C)},
- {2, 0, 1, ON_SOCKET_FT1, str_AMD_C, sizeof (str_AMD_C)},
- {1, 0, 2, ON_SOCKET_FT1, str_AMD_E, sizeof (str_AMD_E)},
- {2, 0, 2, ON_SOCKET_FT1, str_AMD_E, sizeof (str_AMD_E)},
- {1, 0, 4, ON_SOCKET_FT1, str_AMD_G_T, sizeof (str_AMD_G_T)},
- {2, 0, 4, ON_SOCKET_FT1, str_AMD_G_T, sizeof (str_AMD_G_T)}
-}; //Cores, page, index, socket, stringstart, stringlength
-
-
-CONST AMD_CPU_BRAND ROMDATA CpuF14OnBrandIdString2ArrayFt1[] =
-{
- // FT1
- {1, 0, 0x01, ON_SOCKET_FT1, str___Processor, sizeof (str___Processor)},
- {2, 0, 0x01, ON_SOCKET_FT1, str___Processor, sizeof (str___Processor)},
- {1, 0, 0x02, ON_SOCKET_FT1, str___0_Processor, sizeof (str___0_Processor)},
- {2, 0, 0x02, ON_SOCKET_FT1, str___0_Processor, sizeof (str___0_Processor)},
- {1, 0, 0x03, ON_SOCKET_FT1, str_5_Processor, sizeof (str_5_Processor)},
- {2, 0, 0x03, ON_SOCKET_FT1, str_5_Processor, sizeof (str_5_Processor)},
- {1, 0, 0x04, ON_SOCKET_FT1, str_0x_Processor, sizeof (str_0x_Processor)},
- {2, 0, 0x04, ON_SOCKET_FT1, str_0x_Processor, sizeof (str_0x_Processor)},
- {1, 0, 0x05, ON_SOCKET_FT1, str_5x_Processor, sizeof (str_5x_Processor)},
- {2, 0, 0x05, ON_SOCKET_FT1, str_5x_Processor, sizeof (str_5x_Processor)},
- {1, 0, 0x06, ON_SOCKET_FT1, str_x_Processor, sizeof (str_x_Processor)},
- {2, 0, 0x06, ON_SOCKET_FT1, str_x_Processor, sizeof (str_x_Processor)},
- {1, 0, 0x07, ON_SOCKET_FT1, str_L_Processor, sizeof (str_L_Processor)},
- {2, 0, 0x07, ON_SOCKET_FT1, str_L_Processor, sizeof (str_L_Processor)},
- {1, 0, 0x08, ON_SOCKET_FT1, str_N_Processor, sizeof (str_N_Processor)},
- {2, 0, 0x08, ON_SOCKET_FT1, str_N_Processor, sizeof (str_N_Processor)},
- {1, 0, 0x09, ON_SOCKET_FT1, str_R_Processor, sizeof (str_R_Processor)},
- {1, 0, 0x0F, ON_SOCKET_FT1, 0, 0}, //Size 0 for no suffix
- {2, 0, 0x0F, ON_SOCKET_FT1, 0, 0}, //Size 0 for no suffix
- }; //Cores, page, index, socket, stringstart, stringlength
-
-
-CONST CPU_BRAND_TABLE ROMDATA F14OnBrandIdString1ArrayFt1 = {
- (sizeof (CpuF14OnBrandIdString1ArrayFt1) / sizeof (AMD_CPU_BRAND)),
- CpuF14OnBrandIdString1ArrayFt1
-};
-
-
-CONST CPU_BRAND_TABLE ROMDATA F14OnBrandIdString2ArrayFt1 = {
- (sizeof (CpuF14OnBrandIdString2ArrayFt1) / sizeof (AMD_CPU_BRAND)),
- CpuF14OnBrandIdString2ArrayFt1
-};
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c
deleted file mode 100644
index dbead6d..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_14 ROM Execution Cache Defaults
- *
- * Contains default values for ROM execution cache setup
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/Family/0x14
- * @e \$Revision: 36376 $ @e \$Date: 2010-08-18 00:17:10 +0800 (Wed, 18 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuCacheInit.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-#define FILECODE PROC_CPU_FAMILY_0X14_CPUF14CACHEDEFAULTS_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-#define BSP_STACK_SIZE 16384
-#define CORE0_STACK_SIZE 16384
-#define CORE1_STACK_SIZE 4096
-#define MEM_TRAINING_BUFFER_SIZE 16384
-#define VAR_MTRR_MASK 0x0000000FFFFFFFFF
-
-#define HEAP_BASE_MASK 0x0000000FFFFFFFFF
-
-#define SHARED_MEM_SIZE 0
-
-CONST CACHE_INFO ROMDATA CpuF14CacheInfo =
-{
- BSP_STACK_SIZE,
- CORE0_STACK_SIZE,
- CORE1_STACK_SIZE,
- MEM_TRAINING_BUFFER_SIZE,
- SHARED_MEM_SIZE,
- VAR_MTRR_MASK,
- VAR_MTRR_MASK,
- HEAP_BASE_MASK,
- InfiniteExe
-};
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns the family specific properties of the cache, and its usage.
- *
- * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[out] CacheInfoPtr Points to the cache info properties on exit.
- * @param[out] NumberOfElements Will be one to indicate one entry.
- * @param[in] StdHeader Header for library and services.
- *
- */
-VOID
-GetF14CacheInfo (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- OUT CONST VOID **CacheInfoPtr,
- OUT UINT8 *NumberOfElements,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- *NumberOfElements = 1;
- *CacheInfoPtr = &CpuF14CacheInfo;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14Dmi.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14Dmi.c
deleted file mode 100644
index 50ce4d1..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14Dmi.c
+++ /dev/null
@@ -1,272 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD DMI Record Creation API, and related functions.
- *
- * Contains code that produce the DMI related information.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 38893 $ @e \$Date: 2010-10-01 23:54:37 +0800 (Fri, 01 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "cpuRegisters.h"
-#include "OptionDmi.h"
-#include "cpuLateInit.h"
-#include "cpuF14PowerMgmt.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuPstateTables.h"
-#include "cpuF14Utilities.h"
-#include "Filecode.h"
-#define FILECODE PROC_CPU_FAMILY_0X14_CPUF14DMI_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable;
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * DmiF14GetInfo
- *
- * Get CPU type information
- *
- * @param[in,out] CpuInfoPtr Pointer to CPU_TYPE_INFO struct.
- * @param[in] StdHeader Standard Head Pointer
- *
- */
-VOID
-DmiF14GetInfo (
- IN OUT CPU_TYPE_INFO *CpuInfoPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- CPUID_DATA CpuId;
-
- LibAmdCpuidRead (AMD_CPUID_FMF, &CpuId, StdHeader);
- CpuInfoPtr->ExtendedFamily = (UINT8) (CpuId.EAX_Reg >> 20) & 0xFF; // bit 27:20
- CpuInfoPtr->ExtendedModel = (UINT8) (CpuId.EAX_Reg >> 16) & 0xF; // bit 19:16
- CpuInfoPtr->BaseFamily = (UINT8) (CpuId.EAX_Reg >> 8) & 0xF; // bit 11:8
- CpuInfoPtr->BaseModel = (UINT8) (CpuId.EAX_Reg >> 4) & 0xF; // bit 7:4
- CpuInfoPtr->Stepping = (UINT8) (CpuId.EAX_Reg & 0xF); // bit 3:0
-
- CpuInfoPtr->PackageType = (UINT8) (CpuId.EBX_Reg >> 28) & 0xF; // bit 31:28
- CpuInfoPtr->BrandId.Pg = (UINT8) (CpuId.EBX_Reg >> 15) & 0x1; // bit 15
- CpuInfoPtr->BrandId.String1 = (UINT8) (CpuId.EBX_Reg >> 11) & 0xF; // bit 14:11
- CpuInfoPtr->BrandId.Model = (UINT8) (CpuId.EBX_Reg >> 4) & 0x7F; // bit 10:4
- CpuInfoPtr->BrandId.String2 = (UINT8) (CpuId.EBX_Reg & 0xF); // bit 3:0
-
- LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuId, StdHeader);
- CpuInfoPtr->TotalCoreNumber = (UINT8) (CpuId.ECX_Reg & 0xFF); // bit 7:0
- CpuInfoPtr->EnabledCoreNumber = (UINT8) (CpuId.ECX_Reg & 0xFF); // bit 7:0
-
- switch (CpuInfoPtr->PackageType) {
- case ON_SOCKET_FT1:
- CpuInfoPtr->ProcUpgrade = P_UPGRADE_NONE;
- break;
- default:
- CpuInfoPtr->ProcUpgrade = P_UPGRADE_UNKNOWN;
- break;
- }
-
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * DmiF14GetVoltage
- *
- * Get the voltage value according to SMBIOS SPEC's requirement.
- *
- * @param[in] StdHeader Standard Head Pointer
- *
- * @retval Voltage - CPU Voltage.
- *
- */
-UINT8
-DmiF14GetVoltage (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 MaxVid;
- UINT8 Voltage;
- UINT64 MsrData;
-
- // Voltage = 0x80 + (voltage at boot time * 10)
- LibAmdMsrRead (MSR_COFVID_STS, &MsrData, StdHeader);
- MaxVid = (UINT8) (((COFVID_STS_MSR *)&MsrData)->MaxVid);
- if (MaxVid == 0) {
- LibAmdMsrRead (MSR_PSTATE_0, &MsrData, StdHeader);
- MaxVid = (UINT8) (((PSTATE_MSR *)&MsrData)->CpuVid);
- }
-
- if ((MaxVid >= 0x7C) && (MaxVid <= 0x7F)) {
- Voltage = 0;
- } else {
- Voltage = (UINT8) ((15500 - (125 * MaxVid) + 500) / 1000);
- }
-
- Voltage += 0x80;
- return (Voltage);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * DmiF14GetMaxSpeed
- *
- * Get the Max Speed
- *
- * @param[in] StdHeader Standard Head Pointer
- *
- * @retval MaxSpeed - CPU Max Speed.
- *
- */
-UINT16
-DmiF14GetMaxSpeed (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 P0Frequency;
- PSTATE_CPU_FAMILY_SERVICES *FamilyServices;
-
- FamilyServices = NULL;
- GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, &FamilyServices, StdHeader);
- ASSERT (FamilyServices != NULL);
-
- FamilyServices->GetPstateFrequency (FamilyServices, (UINT8) 0x00, &P0Frequency, StdHeader);
- return ((UINT16) P0Frequency);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * DmiF14GetExtClock
- *
- * Get the external clock Speed
- *
- * @param[in, out] StdHeader Standard Head Pointer
- *
- * @retval ExtClock - CPU external clock Speed.
- *
- */
-UINT16
-DmiF14GetExtClock (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- return (EXTERNAL_CLOCK_100MHZ);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * DmiF14GetMemInfo
- *
- * Get memory information.
- *
- * @param[in,out] CpuGetMemInfoPtr Pointer to CPU_GET_MEM_INFO struct.
- * @param[in] StdHeader Standard Head Pointer
- *
- */
-VOID
-DmiF14GetMemInfo (
- IN OUT CPU_GET_MEM_INFO *CpuGetMemInfoPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- // Ontario only has one DCT and does NOT support ECC DIMM
- CpuGetMemInfoPtr->EccCapable = FALSE;
- // Partition Row Position - 2 is for single channel memory
- CpuGetMemInfoPtr->PartitionRowPosition = 2;
-}
-
-/*---------------------------------------------------------------------------------------
- * Processor Family Table
- *
- * Note: 'x' means we don't care this field
- * 002h = "Unknown"
- *-------------------------------------------------------------------------------------*/
-CONST DMI_BRAND_ENTRY ROMDATA Family14BrandList[] =
-{
- // Brand --> DMI ID translation table
- // PackageType, PgOfBrandId, NumberOfCores, String1ofBrandId, ValueSetToDmiTable
- {0, 0, 'x', 1, 0x46},
- {0, 0, 'x', 2, 0x47},
- {'x', 'x', 'x', 'x', 0x02}
-};
-
-CONST PROC_FAMILY_TABLE ROMDATA ProcFamily14DmiTable =
-{
- AMD_FAMILY_14, // ID for Family 14h
- &DmiF14GetInfo, // Transfer vectors for family
- &DmiF14GetVoltage, // specific routines (above)
- &DmiF14GetMaxSpeed,
- &DmiF14GetExtClock,
- &DmiF14GetMemInfo, // Get memory information
- (sizeof (Family14BrandList) / sizeof (Family14BrandList[0])), // Number of entries in following table
- &Family14BrandList[0]
-};
-
-
-/*---------------------------------------------------------------------------------------
- * L O C A L F U N C T I O N S
- *---------------------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14MsrTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14MsrTables.c
deleted file mode 100644
index eeb4173..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14MsrTables.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_14 MSR tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 37263 $ @e \$Date: 2010-09-01 21:58:26 +0800 (Wed, 01 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "Filecode.h"
-#define FILECODE PROC_CPU_FAMILY_0X14_CPUF14MSRTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F14MsrRegisters[] =
-{
-
-// M S R T a b l e s
-// ----------------------
-
-// MSR_TOM2 (0xC001001D)
-// bits[63:0] - TOP_MEM2 = 0
- {
- MsrRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MSR_TOM2, // MSR Address
- 0x0000000000000000, // OR Mask
- 0xFFFFFFFFFFFFFFFF, // NAND Mask
- }
- },
-// MSR_SYS_CFG (0xC0010010)
-// bit[21] - MtrrTom2En = 1
- {
- MsrRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MSR_SYS_CFG, // MSR Address
- (1 << 21), // OR Mask
- (1 << 21), // NAND Mask
- }
- },
-// MSR_CPUID_EXT_FEATS (0xC0011005)
-// bit[41] - OSVW = 0
- {
- MsrRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MSR_CPUID_EXT_FEATS, // MSR Address
- 0x0000000000000000, // OR Mask
- 0x0000020000000000, // NAND Mask
- }
- },
-// MSR_OSVW_ID_Length (0xC0010140)
-// bit[15:0] = 4
- {
- MsrRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MSR_OSVW_ID_Length, // MSR Address
- 0x0000000000000004, // OR Mask
- 0x000000000000FFFF, // NAND Mask
- }
- },
-// MSR_HWCR (0xC0010015)
-// Do not set bit[24] = 1, it will be set in AmdInitPost.
-
-// This MSR should be set after the code that most errata would be applied in
-// MSR_MC0_CTL (0x00000400)
-// bits[63:0] = 0xFFFFFFFFFFFFFFFF
- {
- MsrRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MSR_MC0_CTL, // MSR Address
- 0xFFFFFFFFFFFFFFFF, // OR Mask
- 0xFFFFFFFFFFFFFFFF, // NAND Mask
- }
- },
-// MSR_LS_CFG (0xC0011020)
-// bit[36] Reserved = 1, workaround for erratum #530
-// bit[25] Reserved = 1, workaround for erratum #551
- {
- MsrRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MSR_LS_CFG, // MSR Address
- 0x0000001002000000, // OR Mask
- 0x0000001002000000, // NAND Mask
- }
- },
-// MSR_DC_CFG (0xC0011022)
-// bit[57:56] Reserved = 2
- {
- MsrRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MSR_DC_CFG, // MSR Address
- 0x0200000000000000, // OR Mask
- 0x0300000000000000, // NAND Mask
- }
- }
-};
-
-CONST REGISTER_TABLE ROMDATA F14MsrRegisterTable = {
- AllCores,
- (sizeof (F14MsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
- (TABLE_ENTRY_FIELDS *) &F14MsrRegisters,
-};
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14PciTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14PciTables.c
deleted file mode 100644
index aab474a..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14PciTables.c
+++ /dev/null
@@ -1,716 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_14 PCI tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x14
- * @e \$Revision: 38376 $ @e \$Date: 2010-09-23 11:39:55 +0800 (Thu, 23 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "Filecode.h"
-#define FILECODE PROC_CPU_FAMILY_0X14_CPUF14PCITABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-// P C I T a b l e s
-// ----------------------
-
-STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PciRegisters[] =
-{
-// Function 0 - Link Config
-
-// D18F0x68 - Link Transaction Control
-// bit[11] RespPassPW = 1
-// bits[19:17] for 8bit APIC config
-// bits[22:21] DsNpReqLmt = 1
- {
- PciRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68), // Address
- 0x002E0800, // regData
- 0x006E0800, // regMask
- }
- },
-
-// Function 2 - DRAM Controller
-
-// D18F2xB8
- {
- PciRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_2, 0xB8), // Address
- 0x00000000, // regData
- 0xF000F000, // regMask
- }
- },
-// D18F2xBC
- {
- PciRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_2, 0xBC), // Address
- 0x00000000, // regData
- 0xC0000000, // regMask
- }
- },
-// D18F2x118 - Memory Controller Configuration Low
-// bits[7:6], MctPriHiWr = 10b
- {
- PciRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_2, 0x118), // Address
- 0x00000080, // regData
- 0x000000C0, // regMask
- }
- },
-// D18F2x11C - Memory Controller Configuration High
-// bits[24:22], PrefConf = 1
- {
- PciRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_2, 0x11C), // Address
- 0x00400000, // regData
- 0x01C00000, // regMask
- }
- },
-
-// Function 3 - Misc. Control
-
-// D18F3x40 - MCA NB Control
-// bit[8] MstrAbortEn = 1
- {
- PciRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x40), // Address
- 0x00000100, // regData
- 0x00000100, // regMask
- }
- },
-// D18F3x44 - MCA NB Configuration
-// bit[27] NbMcaToMstCpuEn = 1
-// bit[25] DisPciCfgCpuErrRsp = 1
-// bit[21] SyncOnAnyErrEn = 1
-// bit[20] SyncOnWDTEn = 1
-// bits[13:12] WDTBaseSel = 0
-// bits[11:9] WDTCntSel[2:0] = 0
-// bit[6] CpuErrDis = 1
- {
- PciRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x44), // Address
- 0x0A300040, // regData
- 0x0A303E40, // regMask
- }
- },
-// D18F3x84 - ACPI Power State Control High
-// bit[18] Smaf6DramMemClkTri = 1
-// bit[17] Smaf6DramSr = 1
-// bit[2] Smaf4DramMemClkTri = 1
-// bit[1] Smaf4DramSr = 1
- {
- PciRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x84), // Address
- 0x00060006, // regData
- 0x00060006, // regMask
- }
- },
-// D18F3x8C - NB Configuration High
-// bit[26] EnConvertToNonIsoc = 1
- {
- PciRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x8C), // Address
- 0x04000000, // regData
- 0x04000000, // regMask
- }
- },
-// D18F3xA0 - Power Control Miscellaneous
-// bit[9] SviHighFreqSel = 1
- {
- PciRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0), // Address
- 0x00000200, // regData
- 0x00000200, // regMask
- }
- },
-// D18F3xA4 - Reported Temperature Control
-// bits[12:8] PerStepTimeDn = 0xF
-// bit[7] TmpSlewDnEn = 1
-// bits[6:5] TmpMaxDiffUp = 0x3
-// bits[4:0] PerStepTimeUp = 0xF
-
- {
- PciRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA4), // Address
- 0x00000FEF, // regData
- 0x00001FFF, // regMask
- }
- },
-// D18F3xD4 - Clock Power Timing Control 0
-// bits[11:8] ClkRampHystSel = 0xF
-// bits[15:12] OnionOutHyst = 0x4
-// bit[17] ClockGatingEnDram = 1
- {
- PciRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD4), // Address
- 0x00024F00, // regData
- 0x0002FF00, // regMask
- }
- },
-// D18F3xDC - Clock Power Timing Control 2
-// bits[29:27] NbClockGateHyst = 3
-// bit[30] NbClockGateEn = 1
-// bit[31] CnbCifClockGateEn = 1
- {
- PciRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC), // Address
- 0xD8000000, // regData
- 0xF8000000, // regMask
- }
- },
-// D18F3x180 - Extended NB MCA Configuration
-// bit[2] WDTCntSel[3] = 0
-// bit[5] DisPciCfgCpuMstAbtRsp = 1
-// bit[21] SyncFloodOnCpuLeakErr = 1
- {
- PciRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x180), // Address
- 0x00200020, // regData
- 0x00200024, // regMask
- }
- },
-// D18F3x188 - NB Extended Configuration
-// bit[21] EnCpuSerWrBehindIoRd = 0
-// bit[23] EnCpuSerRdBehindIoRd = 0
-// bits[27:24] FeArbCpuWeightOverLoPrio = 0x0B
-// bits[31:28] FeArbCpuWeightOverHiPrio = 1
- {
- PciRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address
- 0x1B000000, // regData
- 0xFFA00000, // regMask
- }
- },
-
-// Function 4 - Extended Misc. Control
-
-// D18F4x118 - C-state Control 1
-// bits[2:0] CstAct0 = 0
-// bits[10:8] CstAct1 = 0
- {
- PciRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_4, 0x118), // Address
- 0x00000000, // regData
- 0x00000707, // regMask
- }
- },
-// D18F4x124 - C-state Monitor Control 1
-// bit[15] TimerTickIntvlScale = 1
-// bit[16] TrackTimerTickInterEn = 1
-// bit[17] IntMonCC6En = 1
-// bits[21:18] IntMonCC6Lmt = 4
-// bit[22] IntMonPkgC6En = 0
-// bits[26:23] IntMonPkgC6Lmt = 0x0A
- {
- PciRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_4, 0x124), // Address
- 0x05138000, // regData
- 0x07FF8000, // regMask
- }
- },
-// D18F4x134 - C-state Monitor Control 3
-// bits[3:0] IntRatePkgC6MaxDepth = 0
-// bits[7:4] IntRatePkgC6Threshold = 0
-// bits[10:8] IntRatePkgC6BurstLen = 1
-// bits[15:11] IntRatePkgC6DecrRate = 0x0A
-// bits[19:16] IntRateCC6MaxDepth = 5
-// bits[23:20] IntRateCC6Threshold = 4
-// bits[26:24] IntRateCC6BurstLen = 5
-// bits[31:27] IntRateCC6DecrRate = 0x08
- {
- PciRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_4, 0x134), // Address
- 0x45455100, // regData
- 0xFFFFFFFF, // regMask
- }
- },
-// D18F4x13C - SMAF Code DID 1
-// bits[4:0] Smaf4Did = 0x0F
-// bits[20:16] Smaf6Did = 0x0F
- {
- PciRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_4, 0x13C), // Address
- 0x000F000F, // regData
- 0x001F001F, // regMask
- }
- },
-// D18F4x1A4 - C-state Monitor Mask
-// bits[7:0] IntRateMonMask = 0xFC
-// bits[15:8] TimerTickMonMask = 0xFF
-// bits[23:16] NonC0MonMask = 0xFF
-// bits[31:24] C0MonMask = 0xFF
- {
- PciRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1A4), // Address
- 0xFFFFFFFC, // regData
- 0xFFFFFFFF, // regMask
- }
- },
-// D18F4x1A8 - CPU State Power Management Dynamic Control 0
-// bits[4:0] SingleHaltCpuDid = 0x1E
-// bits[9:5] AllHaltCpuDid = 0x1F
-// bit[15] CpuProbEn = 0
-// bits[22:20] PServiceTmr = 1
-// bit[23] PServiceTmrEn = 1
- {
- PciRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1A8), // Address
- 0x009003FE, // regData
- 0x00F083FF, // regMask
- }
- },
-// D18F4x1AC - CPU State Power Management Dynamic Control 1
-// bits[9:5] C6Did = 0x1F
-// bits[28] CoreC6Dis = 1
-// bits[29] PkgC6Dis = 1
- {
- PciRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1AC), // Address
- 0x300003E0, // regData
- 0x300003E0, // regMask
- }
- },
-// D18F6x50 - Configuration Register Access Control
-// bit[1] CfgAccAddrMode = 0
- {
- PciRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_6, 0x50), // Address
- 0x00000000, // regData
- 0x00000002, // regMask
- }
- },
-// D18F6x54 - DRAM Arbitration Control FEQ Collision
-// bits[7:0] FeqLoPrio = 0x20
-// bits[15:8] FeqMedPrio = 0x10
-// bits[23:16] FeqHiPrio = 8
-// bit[31] PpMode = 0
- {
- PciRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_6, 0x54), // Address
- 0x00081020, // regData
- 0x80FFFFFF, // regMask
- }
- },
-// D18F6x58 - DRAM Arbitration Control Display Collision
-// bits[7:0] DispLoPrio = 0x40
-// bits[15:8] DispMedPrio = 0x20
-// bits[23:16] DispHiPrio = 0x10
-// bits[31:24] DispUrgPrio = 0
- {
- PciRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_6, 0x58), // Address
- 0x00102040, // regData
- 0xFFFFFFFF, // regMask
- }
- },
-// D18F6x5C - DRAM Arbitration Control FEQ Write Protect
-// bits[7:0] FeqLoPrio = 0x20
-// bits[15:8] FeqMedPrio = 0x10
-// bits[23:16] FeqHiPrio = 0x08
-// bit[31] PpMode = 0
- {
- PciRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_6, 0x5C), // Address
- 0x00081020, // regData
- 0x80FFFFFF, // regMask
- }
- },
-// D18F6x60 - DRAM Arbitration Control Display Write Protect
-// bits[7:0] DispLoPri = 0x20
-// bits[15:8] DispMedPrio = 0x10
-// bits[23:16] DispHiPrio = 0x08
-// bits[31:24] DispUrgPrio = 0
- {
- PciRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_6, 0x60), // Address
- 0x00081020, // regData
- 0xFFFFFFFF, // regMask
- }
- },
-// D18F6x64 - DRAM Arbitration Control FEQ Read Protect
-// bits[7:0] FeqLoPrio = 0x10
-// bits[15:8] FeqMedPrio = 8
-// bits[23:16] FeqHiPrio = 4
-// bit[31] PpMode = 0
- {
- PciRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_6, 0x64), // Address
- 0x00040810, // regData
- 0x80FFFFFF, // regMask
- }
- },
-// D18F6x68 - DRAM Arbitration Control Display Read Protect
-// bits[7:0] DispLoPrio = 0x10
-// bits[15:8] DispMedPrio = 8
-// bits[23:16] DispHiPrio = 4
-// bits[31:24] DispUrgPrio = 0
- {
- PciRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_6, 0x68), // Address
- 0x00040810, // regData
- 0xFFFFFFFF, // regMask
- }
- },
-// D18F6x6C - DRAM Arbitration Control FEQ Fairness Timer
-// bits[7:0] FeqLoPrio = 0x80
-// bits[15:8] FeqMedPrio = 0x40
-// bits[23:16] FeqHiPrio = 0x20
- {
- PciRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_6, 0x6C), // Address
- 0x00204080, // regData
- 0x00FFFFFF, // regMask
- }
- },
-// D18F6x70 - DRAM Arbitration Control Display Fairness Timer
-// bits[7:0] DispLoPrio = 0x80
-// bits[15:8] DispMedPrio = 0x40
-// bits[23:16] DispHiPrio = 0x20
-// bits[31:24] DispUrPrio = 0
- {
- PciRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_6, 0x70), // Address
- 0x00204080, // regData
- 0xFFFFFFFF, // regMask
- }
- },
-// D18F6x74 - Dram Idle Page Close Limit
-// bits[40] IdleLimit = 0x1E
- {
- PciRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_6, 0x74), // Address
- 0x0000001E, // regData
- 0x0000001F, // regMask
- }
- },
-// D18F6x78 - Dram Prioritization and Arbitration Control
-// bits[1:0] DispDbePrioEn = 3
-// bit[2] FeqDbePrioEn = 1
-// bit[3] DispArbCtrl = 0
-// bits[5:4] GlcEosDet = 3
-// bit[6] GlcEosDetDis = 0
- {
- PciRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_6, 0x78), // Address
- 0x00000037, // regData
- 0x0000007F, // regMask
- }
- },
-// D18F6x90 - NB P-state Config Low
-// As part of BIOS Requirements for NB P-state Initialization
-// bit[30] NbPsCtrlDis = 1
-// bit[29] NbPsForceSel = 0
-// bit[28] NbPsForceReq = 1
- {
- PciRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_6, 0x90), // Address
- 0x50000000, // regData
- 0x70000000, // regMask
- }
- },
-// D18F6x94 - NB P-state Config High
-// bits[2:0] CpuPstateThr = 1
-// bit[3] CpuPstateThrEn = 1
-// bits[25:23] NbPsC0Timer = 4
- {
- PciRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_6, 0x94), // Address
- 0x02000009, // regData
- 0x0380000F, // regMask
- }
- },
-// D18F6x9C - NCLK Reduction Control
-// bits[6:0] NclkRedDiv = 0x60
-// bit[7] NclkRedSelfRefrAlways = 1
-// bit[8] NclkRampWithDllRelock = 1
- {
- PciRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_6, 0x9C), // Address
- 0x000001E0, // regData
- 0x000001FF, // regMask
- }
- }
-};
-
-CONST REGISTER_TABLE ROMDATA F14PciRegisterTable = {
- PrimaryCores,
- (sizeof (F14PciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
- F14PciRegisters,
-};
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14PerCorePciTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14PerCorePciTables.c
deleted file mode 100644
index b75e69f..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14PerCorePciTables.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_14 Per Core PCI tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x14
- * @e \$Revision: 36592 $ @e \$Date: 2010-08-21 05:31:55 +0800 (Sat, 21 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "Filecode.h"
-#define FILECODE PROC_CPU_FAMILY_0X14_CPUF14PERCOREPCITABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-// Per Core P C I T a b l e s
-// ----------------------
-
-STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F14PerCorePciRegisters[] =
-{
-// D18F3x1CC - IBS Control
-// bits[3:0] LvtOffset = 0
-// bit[8] LvtOffsetVal = 1
- {
- PciRegister,
- {
- AMD_FAMILY_14, // CpuFamily
- AMD_F14_ALL // CpuRevision
- },
- AMD_PF_ALL, // platformFeatures
- {
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1CC), // Address
- 0x00000100, // regData
- 0x0000010F, // regMask
- }
- }
-};
-
-CONST REGISTER_TABLE ROMDATA F14PerCorePciRegisterTable = {
- AllCores,
- (sizeof (F14PerCorePciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
- F14PerCorePciRegisters,
-};
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14PowerCheck.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14PowerCheck.c
deleted file mode 100644
index 53e6df5..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14PowerCheck.c
+++ /dev/null
@@ -1,358 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_14 P-State power check
- *
- * Performs the "Processor-Systemboard Power Delivery Compatibility Check" as
- * described in the BKDG.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F14
- * @e \$Revision: 39744 $ @e \$Date: 2010-10-15 02:18:02 +0800 (Fri, 15 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "cpuCacheInit.h"
-#include "cpuF14PowerMgmt.h"
-#include "cpuRegisters.h"
-#include "cpuApicUtilities.h"
-#include "cpuServices.h"
-#include "GeneralServices.h"
-#include "cpuEarlyInit.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuF14PowerCheck.h"
-#include "cpuF14Utilities.h"
-#include "Filecode.h"
-#define FILECODE PROC_CPU_FAMILY_0X14_CPUF14POWERCHECK_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-VOID
-STATIC
-F14PmPwrCheckCore (
- IN VOID *ErrorData,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-STATIC
-F14PmPwrChkCopyPstate (
- IN UINT8 Dest,
- IN UINT8 Src,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family 14h core 0 entry point for performing the family 14h Processor-
- * Systemboard Power Delivery Check.
- *
- * The steps are as follows:
- * 1. Starting with P0, loop through all P-states until a passing state is
- * found. A passing state is one in which the current required by the
- * CPU is less than the maximum amount of current that the system can
- * provide to the CPU. If P0 is under the limit, no further action is
- * necessary.
- * 2. If at least one P-State is under the limit & at least one P-State is
- * over the limit, the BIOS must:
- * a. Clear both D18F4x15C[BoostSrc] and D18F4x15C[NumBoostStates] to 0.
- * b. If the processor's current P-State is disabled by the power check,
- * then the BIOS must request a transition to an enabled P-state
- * using MSRC001_0062[PstateCmd] and wait for MSRC001_0063[CurPstate]
- * to reflect the new value.
- * c. Copy the contents of the enabled P-state MSRs to the highest
- * performance P-state locations.
- * d. Request a P-state transition to the P-state MSR containing the
- * COF/VID values currently applied.
- * e. Adjust the following P-state parameters affected by the P-state
- * MSR copy by subtracting the number of P-states that are disabled
- * by the power check.
- * 1. D18F3x64[HtcPstateLimit]
- * 2. D18F3xDC[PstateMaxVal]
- * 3. If all P-States are over the limit, the BIOS must:
- * a. Clear both D18F4x15C[BoostSrc] and D18F4x15C[NumBoostStates] to 0.
- * b. If the processor's current P-State is != D18F3xDC[PstateMaxVal], then
- * write D18F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd] and wait for
- * MSRC001_0063[CurPstate] to reflect the new value.
- * c. If D18F3xDC[PstateMaxVal]!= 000b, copy the contents of the P-state
- * MSR pointed to by D18F3xDC[PstateMaxVal] to MSRC001_0064 and set
- * MSRC001_0064[PstateEn]
- * d. Write 000b to MSRC001_0062[PstateCmd] and wait for MSRC001_0063
- * [CurPstate] to reflect the new value.
- * e. Adjust the following P-state parameters to zero:
- * 1. D18F3x64[HtcPstateLimit]
- * 2. D18F3xDC[PstateMaxVal]
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] CpuEarlyParams Service parameters.
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-F14PmPwrCheck (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 DisPsNum;
- UINT8 PsMaxVal;
- UINT8 Pstate;
- UINT32 ProcIddMax;
- UINT32 PciRegister;
- UINT32 Socket;
- UINT32 Module;
- UINT32 Core;
- UINT32 PstateLimit;
- PCI_ADDR PciAddress;
- UINT64 MsrRegister;
- AP_TASK TaskPtr;
- AGESA_STATUS IgnoredSts;
- PWRCHK_ERROR_DATA ErrorData;
-
- // get the socket number
- IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
- ErrorData.SocketNumber = (UINT8) Socket;
-
- ASSERT (Core == 0);
-
- // get the Max P-state value
- for (PsMaxVal = NM_PS_REG - 1; PsMaxVal != 0; --PsMaxVal) {
- LibAmdMsrRead (PS_REG_BASE + PsMaxVal, &MsrRegister, StdHeader);
- if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
- break;
- }
- }
-
- ErrorData.HwPstateNumber = (UINT8) (PsMaxVal + 1);
-
- DisPsNum = 0;
- for (Pstate = 0; Pstate < ErrorData.HwPstateNumber; Pstate++) {
- if (FamilySpecificServices->GetProcIddMax (FamilySpecificServices, Pstate, &ProcIddMax, StdHeader)) {
- if (ProcIddMax > CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].CurrentLimit) {
- // Add to event log the Pstate that exceeded the current limit
- PutEventLog (AGESA_WARNING,
- CPU_EVENT_PM_PSTATE_OVERCURRENT,
- Socket, Pstate, 0, 0, StdHeader);
- DisPsNum++;
- } else {
- break;
- }
- }
- }
-
- // If all P-state registers are disabled, move P[PsMaxVal] to P0
- // and transition to P0, then wait for CurPstate = 0
-
- ErrorData.AllowablePstateNumber = ((PsMaxVal + 1) - DisPsNum);
-
- // We only need to log this event on the BSC
- if (ErrorData.AllowablePstateNumber == 0) {
- PutEventLog (AGESA_FATAL,
- CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT,
- Socket, 0, 0, 0, StdHeader);
- }
-
- if (DisPsNum != 0) {
- TaskPtr.FuncAddress.PfApTaskI = F14PmPwrCheckCore;
- TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (PWRCHK_ERROR_DATA);
- TaskPtr.DataTransfer.DataPtr = &ErrorData;
- TaskPtr.DataTransfer.DataTransferFlags = 0;
- TaskPtr.ExeFlags = WAIT_FOR_CORE;
- ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParams);
-
- // Final Step
- // D18F3x64[HtPstatelimit] -= disPsNum
- // D18F3xDC[PstateMaxVal]-= disPsNum
-
- PciAddress.AddressValue = HTC_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // D18F3x64
- PstateLimit = ((HTC_REGISTER *) &PciRegister)->HtcPstateLimit;
- if (PstateLimit > DisPsNum) {
- PstateLimit -= DisPsNum;
- } else {
- PstateLimit = 0;
- }
- ((HTC_REGISTER *) &PciRegister)->HtcPstateLimit = PstateLimit;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader); // D18F3x64
-
- PciAddress.AddressValue = CPTC2_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // D18F3xDC
- PstateLimit = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal;
- if (PstateLimit > DisPsNum) {
- PstateLimit -= DisPsNum;
- } else {
- PstateLimit = 0;
- }
- ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->PstateMaxVal = PstateLimit;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader); // D18F3xDC
- }
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Core-level error handler called if any p-states were determined to be out
- * of range for the mother board.
- *
- * This function implements steps 2b-d and 3b-d on each core.
- *
- * @param[in] ErrorData Details about the error condition.
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-STATIC
-F14PmPwrCheckCore (
- IN VOID *ErrorData,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 i;
- UINT8 PsMaxVal;
- UINT8 DisPsNum;
- UINT8 CurrentPs;
- UINT64 MsrRegister;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
-
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
-
- PsMaxVal = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - 1);
- DisPsNum = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber -
- ((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber);
-
- LibAmdMsrRead (MSR_PSTATE_STS, &MsrRegister, StdHeader);
- CurrentPs = (UINT8) (((PSTATE_STS_MSR *) &MsrRegister)->CurPstate);
-
- if (((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber == 0) {
-
- // Step 1
- // Transition to Pstate Max if not there already
-
- if (CurrentPs != PsMaxVal) {
- FamilySpecificServices->TransitionPstate (FamilySpecificServices, PsMaxVal, (BOOLEAN) TRUE, StdHeader);
- }
-
-
- // Step 2
- // If Pstate Max is not P0, copy Pstate max contents to P0 and switch
- // to P0.
-
- if (PsMaxVal != 0) {
- F14PmPwrChkCopyPstate (0, PsMaxVal, StdHeader);
- FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) TRUE, StdHeader);
- }
- } else {
-
- // move remaining P-state register(s) up
- // Step 1
- // Transition to a valid Pstate if current Pstate has been disabled
-
- if (CurrentPs < DisPsNum) {
- FamilySpecificServices->TransitionPstate (FamilySpecificServices, DisPsNum, (BOOLEAN) TRUE, StdHeader);
- CurrentPs = DisPsNum;
- }
-
- // Step 2
- // Move enabled Pstates up and disable the remainder
-
- for (i = 0; (i + DisPsNum) <= PsMaxVal; ++i) {
- F14PmPwrChkCopyPstate (i, (i + DisPsNum), StdHeader);
- }
-
- // Step 3
- // Transition to current COF/VID at shifted location
-
- CurrentPs = (CurrentPs - DisPsNum);
- FamilySpecificServices->TransitionPstate (FamilySpecificServices, CurrentPs, (BOOLEAN) TRUE, StdHeader);
- }
- i = ((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber;
- if (i == 0) {
- i++;
- }
- while (i <= PsMaxVal) {
- FamilySpecificServices->DisablePstate (FamilySpecificServices, i, StdHeader);
- i++;
- }
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Copies the contents of one P-State MSR to another.
- *
- * @param[in] Dest Destination p-state number
- * @param[in] Src Source p-state number
- * @param[in] StdHeader Config handle for library and services
- *
- */
-VOID
-STATIC
-F14PmPwrChkCopyPstate (
- IN UINT8 Dest,
- IN UINT8 Src,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 MsrRegister;
-
- LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &MsrRegister, StdHeader);
- LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &MsrRegister, StdHeader);
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14PowerCheck.h b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14PowerCheck.h
deleted file mode 100644
index daac001..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14PowerCheck.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_14 Power related functions and structures
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F14
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPU_F14_POWER_CHECK_H_
-#define _CPU_F14_POWER_CHECK_H_
-
-
-/*---------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *---------------------------------------------------------------------------------------
- */
-/// Power Check Error Data
-typedef struct {
- UINT8 SocketNumber; ///< Socket Number
- UINT8 HwPstateNumber; ///< Hardware P-state Number
- UINT8 AllowablePstateNumber; ///< Allowable P-state Number
-} PWRCHK_ERROR_DATA;
-
-/*---------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *---------------------------------------------------------------------------------------
- */
-VOID
-F14PmPwrCheck (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif // _CPU_F14_POWER_CHECK_H_
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14PowerMgmt.h b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14PowerMgmt.h
deleted file mode 100644
index 72cf02f..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14PowerMgmt.h
+++ /dev/null
@@ -1,477 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_14 Power Management related stuff
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F14
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPUF14POWERMGMT_H_
-#define _CPUF14POWERMGMT_H_
-
-/*
- * Family 14h CPU Power Management MSR definitions
- *
- */
-
-/* P-state Current Limit Register 0xC0010061 */
-#define MSR_PSTATE_CURRENT_LIMIT 0xC0010061
-
-/// Pstate Current Limit MSR Register
-typedef struct {
- UINT64 CurPstateLimit:3; ///< Current Pstate Limit
- UINT64 :1; ///< Reserved
- UINT64 PstateMaxVal:3; ///< Pstate Max Value
- UINT64 :57; ///< Reserved
-} PSTATE_CURLIM_MSR;
-
-
-/* P-state Control Register 0xC0010062 */
-#define MSR_PSTATE_CTL 0xC0010062
-
-/// Pstate Control MSR Register
-typedef struct {
- UINT64 PstateCmd:3; ///< Pstate change command
- UINT64 :61; ///< Reserved
-} PSTATE_CTRL_MSR;
-
-
-/* P-state Status Register 0xC0010063 */
-#define MSR_PSTATE_STS 0xC0010063
-
-/// Pstate Status MSR Register
-typedef struct {
- UINT64 CurPstate:3; ///< Current Pstate
- UINT64 :61; ///< Reserved
-} PSTATE_STS_MSR;
-
-
-/* P-state Registers 0xC001006[B:4] */
-#define MSR_PSTATE_0 0xC0010064
-#define MSR_PSTATE_1 0xC0010065
-#define MSR_PSTATE_2 0xC0010066
-#define MSR_PSTATE_3 0xC0010067
-#define MSR_PSTATE_4 0xC0010068
-#define MSR_PSTATE_5 0xC0010069
-#define MSR_PSTATE_6 0xC001006A
-#define MSR_PSTATE_7 0xC001006B
-
-#define PS_REG_BASE MSR_PSTATE_0 /* P-state Register base */
-#define PS_MAX_REG MSR_PSTATE_7 /* Maximum P-State Register */
-#define PS_MIN_REG MSR_PSTATE_0 /* Minimum P-State Register */
-#define NM_PS_REG 8 /* number of P-state MSR registers */
-
-/// Pstate MSR
-typedef struct {
- UINT64 CpuDidLSD:4; ///< CPU core divisor identifier least significant digit
- UINT64 CpuDidMSD:5; ///< CPU core divisor identifier most significant digit
- UINT64 CpuVid:7; ///< CPU core VID
- UINT64 :16; ///< Reserved
- UINT64 IddValue:8; ///< Current value field
- UINT64 IddDiv:2; ///< Current divisor field
- UINT64 :21; ///< Reserved
- UINT64 PsEnable:1; ///< P-state Enable
-} PSTATE_MSR;
-
-
-/* COFVID Status Register 0xC0010071 */
-#define MSR_COFVID_STS 0xC0010071
-
-/// COFVID Status MSR Register
-typedef struct {
- UINT64 CurCpuDid:4; ///< Current CPU core divisor ID
- UINT64 CurCpuDidMSD:5; ///< Current CPU core frequency ID
- UINT64 CurCpuVid:7; ///< Current CPU core VID
- UINT64 CurPstate:3; ///< Current P-state
- UINT64 :1; ///< Reserved
- UINT64 PstateInProgress:1; ///< P-state change in progress
- UINT64 :4; ///< Reserved
- UINT64 CurNbVid:7; ///< Current northbridge VID
- UINT64 StartupPstate:3; ///< Startup P-state number
- UINT64 MaxVid:7; ///< Maximum voltage
- UINT64 MinVid:7; ///< Minimum voltage
- UINT64 MainPllOpFreqIdMax:6; ///< Main PLL operating frequency ID maximum
- UINT64 :1; ///< Reserved
- UINT64 CurPstateLimit:3; ///< Current P-state Limit
- UINT64 :5; ///< Reserved
-} COFVID_STS_MSR;
-
-
-/* C-state Address Register 0xC0010073 */
-#define MSR_CSTATE_ADDRESS 0xC0010073
-
-/// C-state Address MSR Register
-typedef struct {
- UINT64 CstateAddr:16; ///< C-state address
- UINT64 :48; ///< Reserved
-} CSTATE_ADDRESS_MSR;
-
-
-/* CPU Watchdog Timer Register 0xC0010074 */
-#define MSR_CPU_WDT 0xC0010074
-
-/// CPU Watchdog Timer Register
-typedef struct {
- UINT64 CpuWdtEn:1; ///< CPU watchdog timer enable
- UINT64 CpuWdtTimeBase:2; ///< CPU watchdog timer time base
- UINT64 CpuWdtCountSel:4; ///< CPU watchdog timer count select
- UINT64 :57; ///< Reserved
-} CPU_WDT_MSR;
-
-
-/*
- * Family 14h CPU Power Management PCI definitions
- *
- */
-
-/* Memory controller configuration low register D18F2x118 */
-#define MEM_CFG_LOW_REG 0x118
-#define MEM_CFG_LOW_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_2, MEM_CFG_LOW_REG))
-
-/// Memory Controller Configuration Low
-typedef struct {
- UINT32 MctPriCpuRd:2; ///< CPU read priority
- UINT32 MctPriCpuWr:2; ///< CPU write priority
- UINT32 MctPriHiRd:2; ///< High-priority VC set read priority
- UINT32 MctPriHiWr:2; ///< High-priority VC set write priority
- UINT32 MctPriDefault:2; ///< Default non-write priority
- UINT32 MctPriWr:2; ///< Default write priority
- UINT32 :7; ///< Reserved
- UINT32 C6DramLock:1; ///< C6 DRAM lock
- UINT32 :8; ///< Reserved
- UINT32 MctVarPriCntLmt:4; ///< Variable priority time limit
-} MEM_CFG_LOW_REGISTER;
-
-
-/* Hardware thermal control register D18F3x64 */
-#define HTC_REG 0x64
-#define HTC_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, HTC_REG))
-
-/// Hardware Thermal Control PCI Register
-typedef struct {
- UINT32 HtcEn:1; ///< HTC Enable
- UINT32 :3; ///< Reserved
- UINT32 HtcAct:1; ///< HTC Active State
- UINT32 HtcActSts:1; ///< HTC Active Status
- UINT32 PslApicHiEn:1; ///< P-state limit higher APIC int enable
- UINT32 PslApicLoEn:1; ///< P-state limit lower APIC int enable
- UINT32 :8; ///< Reserved
- UINT32 HtcTmpLmt:7; ///< HTC temperature limit
- UINT32 HtcSlewSel:1; ///< HTC slew-controlled temp select
- UINT32 HtcHystLmt:4; ///< HTC hysteresis
- UINT32 HtcPstateLimit:3; ///< HTC P-state limit select
- UINT32 HtcLock:1; ///< HTC lock
-} HTC_REGISTER;
-
-
-/* Power Control Miscellaneous Register D18F3xA0 */
-#define PW_CTL_MISC_REG 0xA0
-#define PW_CTL_MISC_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, PW_CTL_MISC_REG))
-
-/// Power Control Miscellaneous PCI Register
-typedef struct {
- UINT32 PsiVid:7; ///< PSI_L VID threshold
- UINT32 PsiVidEn:1; ///< PSI_L VID enable
- UINT32 :1; ///< Reserved
- UINT32 SviHighFreqSel:1; ///< SVI high frequency select
- UINT32 :6; ///< Reserved
- UINT32 ConfigId:12; ///< Configuration Identifier
- UINT32 :3; ///< Reserved
- UINT32 CofVidProg:1; ///< COF and VID of P-states programmed
-} POWER_CTRL_MISC_REGISTER;
-
-
-/* Clock Power/Timing Control 0 Register D18F3xD4 */
-#define CPTC0_REG 0xD4
-#define CPTC0_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC0_REG))
-
-/// Clock Power Timing Control PCI Register
-typedef struct {
- UINT32 MainPllOpFreqId:6; ///< Main PLL Fid
- UINT32 MainPllOpFreqIdEn:1; ///< Main PLL Fid Enable
- UINT32 :1; ///< Reserved
- UINT32 ClkRampHystSel:4; ///< Clock Ramp Hysteresis Select
- UINT32 OnionOutHyst:4; ///< ONION outbound hysteresis
- UINT32 DisNclkGatingIdle:1; ///< Disable NCLK gating when idle
- UINT32 ClkGatingEnDram:1; ///< Clock gating enable DRAM
- UINT32 :1; ///< Reserved
- UINT32 PstateSpecFuseSel:8; ///< P-State Specification Fuse Select
- UINT32 :5; ///< Reserved
-} CLK_PWR_TIMING_CTRL_REGISTER;
-
-
-/* Clock Power/Timing Control 1 Register D18F3xD8 */
-#define CPTC1_REG 0xD8
-#define CPTC1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC1_REG))
-
-/// Clock Power Timing Control 1 PCI Register
-typedef struct {
- UINT32 :4; ///< Reserved
- UINT32 VSRampSlamTime:3; ///< Voltage stabilization slam time
- UINT32 :22; ///< Reserved
- UINT32 SlamModeSelect:1; ///< Voltage slam mode select
- UINT32 :2; ///< Reserved
-} CLK_PWR_TIMING_CTRL1_REGISTER;
-
-
-/* Clock Power/Timing Control 2 Register D18F3xDC */
-#define CPTC2_REG 0xDC
-#define CPTC2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC2_REG))
-
-/// Clock Power Timing Control 2 PCI Register
-typedef struct {
- UINT32 :8; ///< Reserved
- UINT32 PstateMaxVal:3; ///< P-state maximum value
- UINT32 :1; ///< Reserved
- UINT32 NbPs0Vid:7; ///< NB VID
- UINT32 NclkFreqDone:1; ///< NCLK frequency change done
- UINT32 NbPs0NclkDiv:7; ///< NCLK divisor
- UINT32 NbClockGateHyst:3; ///< Northbridge clock gating hysteresis
- UINT32 NbClockGateEn:1; ///< Northbridge clock gating enable
- UINT32 CnbCifClockGateEn:1; ///< CNB CIF clock gating enable
-} CLK_PWR_TIMING_CTRL2_REGISTER;
-
-
-/* Northbridge Capabilities Register D18F3xE8 */
-#define NB_CAPS_REG 0xE8
-#define NB_CAPS_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, NB_CAPS_REG))
-
-/// Northbridge Capabilities PCI Register
-typedef struct {
- UINT32 DctDualCap:1; ///< Two-channel DRAM capable
- UINT32 :4; ///< Reserved
- UINT32 DdrMaxRate:3; ///< Maximum DRAM data rate
- UINT32 MctCap:1; ///< Memory controller capable
- UINT32 SvmCapable:1; ///< SVM capable
- UINT32 HtcCapable:1; ///< HTC capable
- UINT32 :1; ///< Reserved
- UINT32 CmpCap:2; ///< CMP capable
- UINT32 :14; ///< Reserved
- UINT32 LHtcCapable:1; ///< LHTC capable
- UINT32 :3; ///< Reserved
-} NB_CAPS_REGISTER;
-
-
-/* Clock Power/Timing Control 3 Register D18F3x128 */
-#define CPTC3_REG 0x128
-#define CPTC3_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC3_REG))
-
-/// Clock Power Timing Control 3 PCI Register
-typedef struct {
- UINT32 C6Vid:7; ///< C6 VID
- UINT32 :1; ///< Reserved
- UINT32 NbPsiVid:7; ///< NB PSI_L VID threshold
- UINT32 NbPsiVidEn:1; ///< NB PSI_L enable
- UINT32 :16; ///< Reserved
-} CLK_PWR_TIMING_CTRL3_REGISTER;
-
-
-/* C-state Control 1 Register D18F4x118 */
-#define CSTATE_CTRL1_REG 0x118
-#define CSTATE_CTRL1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_CTRL1_REG))
-
-/// C-state Control 1 Register
-typedef struct {
- UINT32 CstAct0:3; ///< C-state action field 0
- UINT32 :5; ///< Reserved
- UINT32 CstAct1:3; ///< C-state action field 1
- UINT32 :5; ///< Reserved
- UINT32 CstAct2:3; ///< C-state action field 2
- UINT32 :5; ///< Reserved
- UINT32 CstAct3:3; ///< C-state action field 3
- UINT32 :5; ///< Reserved
-} CSTATE_CTRL1_REGISTER;
-
-
-/* C-state Control 2 Register D18F4x11C */
-#define CSTATE_CTRL2_REG 0x11C
-#define CSTATE_CTRL2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_CTRL2_REG))
-
-/// C-state Control 2 Register
-typedef struct {
- UINT32 CstAct4:3; ///< C-state action field 4
- UINT32 :5; ///< Reserved
- UINT32 CstAct5:3; ///< C-state action field 5
- UINT32 :5; ///< Reserved
- UINT32 CstAct6:3; ///< C-state action field 6
- UINT32 :5; ///< Reserved
- UINT32 CstAct7:3; ///< C-state action field 7
- UINT32 :5; ///< Reserved
-} CSTATE_CTRL2_REGISTER;
-
-
-/* Core Performance Boost Control Register D18F4x15C */
-#define CPB_CTRL_REG 0x15C
-#define CPB_CTRL_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CPB_CTRL_REG))
-
-/// Core Performance Boost Control Register
-typedef struct {
- UINT32 BoostSrc:2; ///< Boost source
- UINT32 NumBoostStates:3; ///< Number of boosted states
- UINT32 :24; ///< Reserved
- UINT32 BoostEnAllCores:1; ///< Boost enable all cores
- UINT32 :2; ///< Reserved
-} CPB_CTRL_REGISTER;
-
-
-/* CPU State Power Management Dynamic Control 0 Register D18F4x1A8 */
-#define CPU_STATE_PM_CTRL0_REG 0x1A8
-#define CPU_STATE_PM_CTRL0_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CPU_STATE_PM_CTRL0_REG))
-
-/// CPU State Power Management Dynamic Control 0 Register
-typedef struct {
- UINT32 SingleHaltCpuDid:5; ///< Single hlt CPU DID
- UINT32 AllHaltCpuDid:5; ///< All hlt CPU DID
- UINT32 :5; ///< Reserved
- UINT32 CpuProbEn:1; ///< CPU probe enable
- UINT32 :1; ///< Reserved
- UINT32 PService:3; ///< Service P-state
- UINT32 PServiceTmr:3; ///< Service P-state timer
- UINT32 PServiceTmrEn:1; ///< Service P-state timer enable
- UINT32 DramSrEn:1; ///< DRAM self-refresh enable
- UINT32 MemTriStateEn:1; ///< Memory clock tri-state enable
- UINT32 DramSrHyst:3; ///< DRAM self-refresh hysteresis time
- UINT32 DramSrHystEnable:1; ///< DRAM self-refresh hysteresis enable
- UINT32 :2; ///< Reserved
-} CPU_STATE_PM_CTRL0_REGISTER;
-
-
-/* CPU State Power Management Dynamic Control 1 Register D18F4x1AC */
-#define CPU_STATE_PM_CTRL1_REG 0x1AC
-#define CPU_STATE_PM_CTRL1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CPU_STATE_PM_CTRL1_REG))
-
-/// CPU State Power Management Dynamic Control 1 Register
-typedef struct {
- UINT32 :5; ///< Reserved
- UINT32 C6Did:5; ///< CC6 divisor
- UINT32 :6; ///< Reserved
- UINT32 PstateIdCoreOffExit:3; ///< P-state ID core-off exit
- UINT32 :7; ///< Reserved
- UINT32 PkgC6Cap:1; ///< Package C6 capable
- UINT32 CoreC6Cap:1; ///< Core C6 capable
- UINT32 PkgC6Dis:1; ///< Package C6 disable
- UINT32 CoreC6Dis:1; ///< Core C6 disable
- UINT32 CstPminEn:1; ///< C-state Pmin enable
- UINT32 :1; ///< Reserved
-} CPU_STATE_PM_CTRL1_REGISTER;
-
-
-/* C6 Base Register D18F4x12C */
-#define C6_BASE_REG 0x12C
-#define C6_BASE_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, C6_BASE_REG))
-
-/// C6 Base Register
-typedef struct {
- UINT32 C6Base:12; ///< C6 base[35:24]
- UINT32 :20; ///< Reserved
-} C6_BASE_REGISTER;
-
-
-/* NB P-state Config Low Register D18F6x90 */
-#define NB_PSTATE_CFG_LOW_REG 0x90
-#define NB_PSTATE_CFG_LOW_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_6, NB_PSTATE_CFG_LOW_REG))
-
-/// NB P-state Config Low Register
-typedef struct {
- UINT32 NbPs1NclkDiv:7; ///< NBP1 NCLK divisor
- UINT32 :1; ///< Reserved
- UINT32 NbPs1Vid:7; ///< NBP1 NCLK VID
- UINT32 :1; ///< Reserved
- UINT32 NbPs1GnbSlowIgn:1; ///< NB P-state ignore GNB slow signal
- UINT32 :3; ///< Reserved
- UINT32 NbPsLock:1; ///< NB P-state lock
- UINT32 :7; ///< Reserved
- UINT32 NbPsForceReq:1; ///< NB P-state force request
- UINT32 NbPsForceSel:1; ///< NB P-state force selection
- UINT32 NbPsCtrlDis:1; ///< NB P-state control disable
- UINT32 NbPsCap:1; ///< NB P-state capable
-} NB_PSTATE_CFG_LOW_REGISTER;
-
-
-/* NB P-state Config High Register D18F6x94 */
-#define NB_PSTATE_CFG_HIGH_REG 0x94
-#define NB_PSTATE_CFG_HIGH_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_6, NB_PSTATE_CFG_HIGH_REG))
-
-/// NB P-state Config High Register
-typedef struct {
- UINT32 CpuPstateThr:3; ///< CPU P-state threshold
- UINT32 CpuPstateThrEn:1; ///< CPU P-state threshold enable
- UINT32 NbPs1NoTransOnDma:1; ///< NB P-state no transitions on DMA
- UINT32 :15; ///< Reserved
- UINT32 NbPsNonC0Timer:3; ///< NB P-state non-C0 timer
- UINT32 NbPsC0Timer:3; ///< NB P-state C0 timer
- UINT32 NbPs1ResTmrMin:3; ///< NBP1 minimum residency timer
- UINT32 NbPs0ResTmrMin:3; ///< NBP0 minimum residency timer
-} NB_PSTATE_CFG_HIGH_REGISTER;
-
-
-/* NB P-state Control and Status Register D18F6x98 */
-#define NB_PSTATE_CTRL_STS_REG 0x98
-#define NB_PSTATE_CTRL_STS_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_6, NB_PSTATE_CTRL_STS_REG))
-
-/// NB P-state Control and Status Register
-typedef struct {
- UINT32 NbPsTransInFlight:1; ///< NB P-state transition in flight
- UINT32 NbPs1ActSts:1; ///< NB P-state 1 active status
- UINT32 NbPs1Act:1; ///< NB P-state 1 active
- UINT32 :27; ///< Reserved
- UINT32 NbPsCsrAccSel:1; ///< NB P-state register accessibility select
- UINT32 NbPsDbgEn:1; ///< NB P-state debug enable
-} NB_PSTATE_CTRL_STS_REGISTER;
-
-/* NCLK Reduction Control D18F6x9C */
-#define NCLK_REDUCTION_CTRL_REG 0x9C
-#define NCLK_REDUCTION_CTRL_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_6, NCLK_REDUCTION_CTRL_REG))
-
-/// NCLK Reduction Control
-typedef struct {
- UINT32 NclkRedDiv:7; ///< NCLK reduction divisor
- UINT32 NclkRedSelfRefrAlways:1; ///< NCLK reduction always self refresh
- UINT32 NclkRampWithDllRelock:1; ///< NCLK ramp mode
- UINT32 :23; ///< Reserved
-} NCLK_REDUCTION_CTRL_REGISTER;
-
-/// enum for DSM workaround control
-typedef enum {
- CC6_DSM_WORK_AROUND_DISABLE = 0, ///< work around disable
- CC6_DSM_WORK_AROUND_NORMAL_TRAFFIC, ///< work around With Normal Traffic
- CC6_DSM_WORK_AROUND_HIGH_PRIORITY_CHANNEL, ///< work around With High Priority Channel
-} CC6_DSM_WORK_AROUND;
-
-#endif /* _CPUF14POWERMGMT_H */
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14PowerMgmtSystemTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14PowerMgmtSystemTables.c
deleted file mode 100644
index 44e31d7..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14PowerMgmtSystemTables.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_14 Power Management Initialization Steps
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 37018 $ @e \$Date: 2010-08-28 05:46:16 +0800 (Sat, 28 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuApicUtilities.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuPowerMgmtSystemTables.h"
-#include "cpuF14SoftwareThermal.h"
-#include "cpuF14PowerPlane.h"
-#include "cpuF14PowerCheck.h"
-#include "Filecode.h"
-#define FILECODE PROC_CPU_FAMILY_0X14_CPUF14POWERMGMTSYSTEMTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/* Family 14h Table */
-/* ---------------------- */
-CONST SYS_PM_TBL_STEP ROMDATA CpuF14SysPmTableArray[] =
-{
- IDS_INITIAL_F14_PM_STEP
-
- // Step 1 - Power Plane Initialization
- // Execute both cold & warm
- {
- 0, // ExeFlags
- F14PmPwrPlaneInit // Function Pointer
- },
-
- // Step 2 - Current Delivery Check
- // Execute both cold & warm
- {
- 0, // ExeFlags
- F14PmPwrCheck // Function Pointer
- },
-
- // Step x - Software Thermal Control Init
- // Execute both cold & warm
- {
- 0, // ExeFlags
- F14PmThermalInit // Function Pointer
- },
-};
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns the appropriate table of steps to perform to initialize the power management
- * subsystem.
- *
- * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[out] SysPmTblPtr Points to the first entry in the table.
- * @param[out] NumberOfElements Number of valid entries in the table.
- * @param[in] StdHeader Header for library and services.
- *
- */
-VOID
-GetF14SysPmTable (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- OUT CONST VOID **SysPmTblPtr,
- OUT UINT8 *NumberOfElements,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- *NumberOfElements = (sizeof (CpuF14SysPmTableArray) / sizeof (SYS_PM_TBL_STEP));
- *SysPmTblPtr = CpuF14SysPmTableArray;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14PowerPlane.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14PowerPlane.c
deleted file mode 100644
index 6464954..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14PowerPlane.c
+++ /dev/null
@@ -1,272 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_14 Power Plane Initialization
- *
- * Performs the "BIOS Requirements for Power Plane Initialization" as described
- * in the BKDG.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F14
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuCacheInit.h"
-#include "cpuRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuServices.h"
-#include "cpuF14PowerMgmt.h"
-#include "OptionFamily14hEarlySample.h"
-#include "NbSmuLib.h"
-#include "GnbRegistersON.h"
-#include "Filecode.h"
-#define FILECODE PROC_CPU_FAMILY_0X14_CPUF14POWERPLANE_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-extern F14_ES_CORE_SUPPORT F14EarlySampleCoreSupport;
-
-// Register encodings for D18F3xD8[VSRampSlamTime]
-STATIC CONST UINT32 ROMDATA F14VSRampSlamWaitTimes[8] =
-{
- 625, // 000b: 6.25us
- 500, // 001b: 5.00us
- 417, // 010b: 4.17us
- 313, // 011b: 3.13us
- 250, // 100b: 2.50us
- 167, // 101b: 1.67us
- 125, // 110b: 1.25us
- 100 // 111b: 1.00us
-};
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-VOID
-STATIC
-F14PmVrmLowPowerModeEnable (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family 14h core 0 entry point for performing power plane initialization.
- *
- * The steps are as follows:
- * 1. BIOS must initialize D18F3xD8[VSRampSlamTime].
- * 2. BIOS must configure D18F3xA0[PsiVidEn & PsiVid] and
- * D18F3x128[NbPsiVidEn & NbPsiVid].
- * 3. BIOS must program D18F3xDC[NbPs0Vid] = FCRxFE00_6000[NbPs0Vid] - 1.
- * BIOS must program D18F3xDC[NbPs0Vid] = FCRxFE00_6000[NbPs0Vid].
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] CpuEarlyParams Service parameters
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-F14PmPwrPlaneInit (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 SystemSlewRate;
- UINT32 PciRegister;
- UINT32 WaitTime;
- UINT32 VSRampSlamTime;
- PCI_ADDR PciAddress;
- FCRxFE00_6000_STRUCT FCRxFE00_6000;
-
- // Step 1 - Configure D18F3xD8[VSRampSlamTime] based on platform requirements.
- // Voltage Ramp Time = maximum time to change voltage by 12.5mV rounded to the next higher encoding.
- SystemSlewRate = (CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].SlewRate <=
- CpuEarlyParams->PlatformConfig.VrmProperties[NbVrm].SlewRate) ?
- CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].SlewRate :
- CpuEarlyParams->PlatformConfig.VrmProperties[NbVrm].SlewRate;
-
- ASSERT (SystemSlewRate != 0);
-
- // First, calculate the time it takes to change 12.5mV using the VRM slew rate.
- WaitTime = (12500 * 100) / SystemSlewRate;
- if (((12500 * 100) % SystemSlewRate) != 0) {
- WaitTime++;
- }
-
- // Next, round it to the appropriate encoded value. We will start from encoding 111b which corresponds
- // to the fastest slew rate, and work our way down to 000b, which represents the slowest an acceptable
- // VRM can be.
- for (VSRampSlamTime = ((sizeof (F14VSRampSlamWaitTimes) / sizeof (F14VSRampSlamWaitTimes[0])) - 1); VSRampSlamTime > 0; VSRampSlamTime--) {
- if (WaitTime <= F14VSRampSlamWaitTimes[VSRampSlamTime]) {
- break;
- }
- }
-
- if (WaitTime > F14VSRampSlamWaitTimes[0]) {
- // The VRMs on this motherboard are too slow for this CPU.
- IDS_ERROR_TRAP;
- }
-
- // Lastly, program D18F3xD8[VSRampSlamTime] with the appropriate encoded value.
- PciAddress.AddressValue = CPTC1_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- ((CLK_PWR_TIMING_CTRL1_REGISTER *) &PciRegister)->VSRampSlamTime = VSRampSlamTime;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
-
- // Step 2 - Configure D18F3xA0[PsiVidEn & PsiVid] and D18F3x128[NbPsiVidEn & NbPsiVid].
- F14PmVrmLowPowerModeEnable (FamilySpecificServices, CpuEarlyParams, StdHeader);
-
- // Step 3 - Program D18F3xDC[NbPs0Vid] = FCRxFE00_6000[NbPs0Vid] - 1.
- // Program D18F3xDC[NbPs0Vid] = FCRxFE00_6000[NbPs0Vid].
- FCRxFE00_6000.Value = NbSmuReadEfuse (FCRxFE00_6000_ADDRESS, StdHeader);
-
- F14EarlySampleCoreSupport.F14PowerPlaneInitHook (&FCRxFE00_6000, StdHeader);
-
- PciAddress.AddressValue = CPTC2_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->NbPs0Vid = FCRxFE00_6000.Field.NbPs0Vid - 1;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->NbPs0Vid = FCRxFE00_6000.Field.NbPs0Vid;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Sets up PSI_L operation.
- *
- * This function implements the AMD_CPU_EARLY_PARAMS.VrmLowPowerThreshold parameter.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] CpuEarlyParams Contains VrmLowPowerThreshold parameter.
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-STATIC
-F14PmVrmLowPowerModeEnable (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Pstate;
- UINT32 PstateMaxVal;
- UINT32 PstateCurrent;
- UINT32 NextPstateCurrent;
- UINT32 NextPstateCurrentRaw;
- UINT32 PciRegister;
- UINT32 PreviousVid;
- UINT32 CurrentVid;
- UINT64 PstateMsr;
- UINT64 PstateLimitMsr;
- BOOLEAN IsPsiEnabled;
- PCI_ADDR PciAddress;
-
- // Set up PSI_L for VDD
- IsPsiEnabled = FALSE;
- PreviousVid = 0x7F;
- CurrentVid = 0x7F;
- if (CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].LowPowerThreshold != 0) {
- LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &PstateLimitMsr, StdHeader);
- PstateMaxVal = (UINT32) ((PSTATE_CURLIM_MSR *) &PstateLimitMsr)->PstateMaxVal;
- FamilySpecificServices->GetProcIddMax (FamilySpecificServices, (UINT8) 0, &PstateCurrent, StdHeader);
- for (Pstate = 0; Pstate <= PstateMaxVal; Pstate++) {
- LibAmdMsrRead ((UINT32) (Pstate + PS_REG_BASE), &PstateMsr, StdHeader);
- CurrentVid = (UINT32) ((PSTATE_MSR *) &PstateMsr)->CpuVid;
- if (Pstate == PstateMaxVal) {
- NextPstateCurrentRaw = 0;
- NextPstateCurrent = 0;
- } else {
- FamilySpecificServices->GetProcIddMax (FamilySpecificServices, (UINT8) (Pstate + 1), &NextPstateCurrentRaw, StdHeader);
- NextPstateCurrent = NextPstateCurrentRaw + CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].InrushCurrentLimit;
- }
- if ((PstateCurrent <= CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].LowPowerThreshold) &&
- (NextPstateCurrent <= CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].LowPowerThreshold) &&
- (CurrentVid != PreviousVid)) {
- IsPsiEnabled = TRUE;
- break;
- } else {
- PstateCurrent = NextPstateCurrentRaw;
- PreviousVid = CurrentVid;
- }
- }
- }
- PciAddress.AddressValue = PW_CTL_MISC_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- if (IsPsiEnabled) {
- ((POWER_CTRL_MISC_REGISTER *) &PciRegister)->PsiVid = CurrentVid;
- ((POWER_CTRL_MISC_REGISTER *) &PciRegister)->PsiVidEn = 1;
- } else {
- ((POWER_CTRL_MISC_REGISTER *) &PciRegister)->PsiVidEn = 0;
- }
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
-
-
- // Set up NBPSI_L for VDDNB
- PciAddress.AddressValue = CPTC3_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- if (CpuEarlyParams->PlatformConfig.VrmProperties[NbVrm].LowPowerThreshold != 0) {
- ((CLK_PWR_TIMING_CTRL3_REGISTER *) &PciRegister)->NbPsiVid = 0;
- ((CLK_PWR_TIMING_CTRL3_REGISTER *) &PciRegister)->NbPsiVidEn = 1;
- } else {
- ((CLK_PWR_TIMING_CTRL3_REGISTER *) &PciRegister)->NbPsiVidEn = 0;
- }
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
-}
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14PowerPlane.h b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14PowerPlane.h
deleted file mode 100644
index c2dad37..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14PowerPlane.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_14 Power Plane related functions and structures
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F14
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPU_F14_POWER_PLANE_H_
-#define _CPU_F14_POWER_PLANE_H_
-
-
-/*---------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *---------------------------------------------------------------------------------------
- */
-VOID
-F14PmPwrPlaneInit (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif // _CPU_F14_POWER_PLANE_H_
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14Pstate.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14Pstate.c
deleted file mode 100644
index d37f3fd..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14Pstate.c
+++ /dev/null
@@ -1,364 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_14 Pstate feature support functions.
- *
- * Provides the functions necessary to initialize the Pstate feature.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F14
- * @e \$Revision: 37010 $ @e \$Date: 2010-08-28 03:10:12 +0800 (Sat, 28 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuPstateTables.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuRegisters.h"
-#include "cpuF14Utilities.h"
-#include "cpuF14PowerMgmt.h"
-#include "CommonReturns.h"
-#include "Filecode.h"
-#define FILECODE PROC_CPU_FAMILY_0X14_CPUF14PSTATE_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/**
- * Family specific call to set core TscFreqSel.
- *
- * @param[in] PstateCpuServices Pstate CPU services.
- * @param[in] StdHeader Config Handle for library, services.
- *
- */
-VOID
-STATIC
-F14SetTscFreqSel (
- IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 MsrValue;
-
- LibAmdMsrRead (MSR_HWCR, &MsrValue, StdHeader);
- MsrValue = MsrValue | BIT24;
- LibAmdMsrWrite (MSR_HWCR, &MsrValue, StdHeader);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family specific call to get Pstate Transition Latency.
- *
- * Follow BKDG, return zero currently.
- *
- * @param[in] PstateCpuServices Pstate CPU services.
- * @param[in] PStateLevelingBufferStructPtr Pstate row data buffer pointer
- * @param[in] PciAddress Pci address
- * @param[out] TransitionLatency The transition latency.
- * @param[in] StdHeader Header for library and services
- *
- * @retval AGESA_SUCCESS Always succeeds.
- */
-AGESA_STATUS
-F14GetPstateTransLatency (
- IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
- IN PSTATE_LEVELING *PStateLevelingBufferStructPtr,
- IN PCI_ADDR *PciAddress,
- OUT UINT32 *TransitionLatency,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- //
- // TransitionLatency (us) = BusMasterLatency (us) = 0 us, calculation may
- // change due to a potential new encoding.
- //
- *TransitionLatency = 0;
- return (AGESA_SUCCESS);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family specific call to calculates the frequency in megahertz of the desired P-state.
- *
- * @param[in] PstateCpuServices Pstate CPU services.
- * @param[in] StateNumber The P-State to analyze.
- * @param[out] FrequencyInMHz The P-State's frequency in MegaHertz
- * @param[in] StdHeader Header for library and services
- *
- * @retval AGESA_SUCCESS Always Succeeds.
- */
-AGESA_STATUS
-F14GetPstateFrequency (
- IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
- IN UINT8 StateNumber,
- OUT UINT32 *FrequencyInMHz,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 CpuDidLSD;
- UINT32 CpuDidMSD;
- UINT32 CoreClkDivisor;
- UINT32 PciRegister;
- UINT64 MsrRegister;
- BOOLEAN FrequencyCalculated;
- BOOLEAN ClockDivisorCalculated;
- PCI_ADDR PciAddress;
- UINT32 MainPllOpFreq;
- UINT32 MainPllFid;
-
- ASSERT (StateNumber < NM_PS_REG);
-
- LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
- ASSERT (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1);
-
- CpuDidLSD = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuDidLSD);
- CpuDidMSD = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuDidMSD);
-
- FrequencyCalculated = FALSE;
- ClockDivisorCalculated = FALSE;
- CoreClkDivisor = 1;
-
- if ((CpuDidLSD > 3) || (CpuDidMSD > 0x19)) {
- // Either CpuDidLSD or CpuDidMSD is set to an undefined value.
- // This is due to either a misfused CPU, or an invalid P-state MSR write.
- ASSERT (FALSE);
- ClockDivisorCalculated = TRUE;
- FrequencyCalculated = TRUE;
- CoreClkDivisor = 4;
- *FrequencyInMHz = 100;
- }
-
- if (!ClockDivisorCalculated) {
- CoreClkDivisor = (CpuDidMSD * 4) + CpuDidLSD + 4;
- }
- // Checking for supported divisor value
- ASSERT (((CoreClkDivisor >= 4) && (CoreClkDivisor <= 63)) ||
- ((CoreClkDivisor >= 64) && (CoreClkDivisor <= 106) && ((CoreClkDivisor % 2) == 0)));
-
- if (!FrequencyCalculated) {
- // Get D18F3xD4[MainPllOpFreqId] frequency
- PciAddress.AddressValue = CPTC0_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
-
- if (((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->MainPllOpFreqIdEn == 1) {
- MainPllFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->MainPllOpFreqId;
- } else {
- MainPllFid = 0;
- }
- MainPllOpFreq = ((MainPllFid + 0x10) * 100);
-
- *FrequencyInMHz = MainPllOpFreq * 4 / CoreClkDivisor;
- }
-
- return (AGESA_SUCCESS);
-}
-
-/*--------------------------------------------------------------------------------------*/
-/**
- *
- * Family specific call to calculates the power in milliWatts of the desired P-state.
- *
- * @param[in] PstateCpuServices Pstate CPU services.
- * @param[in] StateNumber Which P-state to analyze
- * @param[out] PowerInMw The Power in milliWatts of that P-State
- * @param[in] StdHeader Header for library and services
- *
- * @retval AGESA_SUCCESS Always succeeds.
- */
-AGESA_STATUS
-F14GetPstatePower (
- IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
- IN UINT8 StateNumber,
- OUT UINT32 *PowerInMw,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 CpuVid;
- UINT32 IddValue;
- UINT32 IddDiv;
- UINT32 V_x10000;
- UINT32 Power;
- UINT64 MsrRegister;
-
- ASSERT (StateNumber < NM_PS_REG);
- LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
- ASSERT (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1);
- CpuVid = (UINT32) (((PSTATE_MSR *) &MsrRegister)->CpuVid);
- IddValue = (UINT32) (((PSTATE_MSR *) &MsrRegister)->IddValue);
- IddDiv = (UINT32) (((PSTATE_MSR *) &MsrRegister)->IddDiv);
-
- if (CpuVid >= 0x7C) {
- V_x10000 = 0;
- } else {
- V_x10000 = 15500L - (125L * CpuVid);
- }
-
- Power = V_x10000 * IddValue;
-
- switch (IddDiv) {
- case 0:
- *PowerInMw = Power / 10L;
- break;
- case 1:
- *PowerInMw = Power / 100L;
- break;
- case 2:
- *PowerInMw = Power / 1000L;
- break;
- default:
- // IddDiv is set to an undefined value. This is due to either a misfused CPU, or
- // an invalid P-state MSR write.
- ASSERT (FALSE);
- *PowerInMw = 0;
- break;
- }
- return (AGESA_SUCCESS);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family specific call to get CPU pstate max state.
- *
- * @param[in] PstateCpuServices Pstate CPU services.
- * @param[out] MaxPStateNumber Boolean flag return pstate enable.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @retval AGESA_SUCCESS Always succeeds.
- */
-AGESA_STATUS
-F14GetPstateMaxState (
- IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
- OUT UINT32 *MaxPStateNumber,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 MsrValue;
-
- //
- // Read PstateMaxVal [6:4] from MSR C001_0061
- // So, we will know the max pstate state in this socket.
- //
- LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &MsrValue, StdHeader);
- *MaxPStateNumber = (UINT32) (((PSTATE_CURLIM_MSR *) &MsrValue)->PstateMaxVal);
-
- return (AGESA_SUCCESS);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family specific call to get CPU pstate register information.
- *
- * @param[in] PstateCpuServices Pstate CPU services.
- * @param[in] PState Input Pstate number for query.
- * @param[out] PStateEnabled Boolean flag return pstate enable.
- * @param[in,out] IddVal Pstate current value.
- * @param[in,out] IddDiv Pstate current divisor.
- * @param[out] SwPstateNumber Software P-state number.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @retval AGESA_SUCCESS Always succeeds.
- */
-AGESA_STATUS
-F14GetPstateRegisterInfo (
- IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
- IN UINT32 PState,
- OUT BOOLEAN *PStateEnabled,
- IN OUT UINT32 *IddVal,
- IN OUT UINT32 *IddDiv,
- OUT UINT32 *SwPstateNumber,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 MsrRegister;
-
- ASSERT (PState < NM_PS_REG);
-
- // Read PSTATE MSRs
- LibAmdMsrRead (PS_REG_BASE + (UINT32) PState, &MsrRegister, StdHeader);
-
- if (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1) {
- // PState enable = bit 63
- *PStateEnabled = TRUE;
- } else {
- *PStateEnabled = FALSE;
- }
-
- *SwPstateNumber = PState;
- // Bits 39:32 (high 32 bits [7:0])
- *IddVal = (UINT32) ((PSTATE_MSR *) &MsrRegister)->IddValue;
- // Bits 41:40 (high 32 bits [9:8])
- *IddDiv = (UINT32) ((PSTATE_MSR *) &MsrRegister)->IddDiv;
-
- return (AGESA_SUCCESS);
-}
-
-
-CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F14PstateServices =
-{
- 0,
- (PF_PSTATE_PSD_IS_NEEDED) CommonReturnTrue,
- (PF_PSTATE_PSD_IS_DEPENDENT) CommonReturnTrue,
- F14SetTscFreqSel,
- F14GetPstateTransLatency,
- F14GetPstateFrequency,
- (PF_CPU_SET_PSTATE_LEVELING_REG) CommonReturnAgesaSuccess,
- F14GetPstatePower,
- F14GetPstateMaxState,
- F14GetPstateRegisterInfo
-};
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14SoftwareThermal.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14SoftwareThermal.c
deleted file mode 100644
index 249a3bc..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14SoftwareThermal.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_14 thermal initialization
- *
- * Performs processor thermal initialization.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F14
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "cpuCacheInit.h"
-#include "cpuRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuF14PowerMgmt.h"
-#include "Filecode.h"
-#define FILECODE PROC_CPU_FAMILY_0X14_CPUF14SOFTWARETHERMAL_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Main entry point for initializing the SW Thermal Control
- * safety net feature.
- *
- * This must be run by all Family 14h core 0s in the system.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] CpuEarlyParamsPtr Service parameters.
- * @param[in] StdHeader Config handle for library and services.
- */
-VOID
-F14PmThermalInit (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 PciRegister;
- PCI_ADDR PciAddress;
-
- PciAddress.AddressValue = NB_CAPS_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- if (((NB_CAPS_REGISTER *) &PciRegister)->HtcCapable == 1) {
- PciAddress.AddressValue = HTC_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- if (((HTC_REGISTER *) &PciRegister)->HtcTmpLmt != 0) {
- // Enable HTC
- ((HTC_REGISTER *) &PciRegister)->HtcEn = 1;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- }
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14SoftwareThermal.h b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14SoftwareThermal.h
deleted file mode 100644
index 7a61f23..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14SoftwareThermal.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_14 thermal initialization related functions and structures
- *
- * Performs processor thermal initialization.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F14
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPU_F14_SOFTWARE_THERMAL_H_
-#define _CPU_F14_SOFTWARE_THERMAL_H_
-
-
-/*---------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *---------------------------------------------------------------------------------------
- */
-VOID
-F14PmThermalInit (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif // _CPU_F14_SOFTWARE_THERMAL_H_
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14Utilities.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14Utilities.c
deleted file mode 100644
index f6a13e5..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14Utilities.c
+++ /dev/null
@@ -1,539 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_14 specific utility functions.
- *
- * Provides numerous utility functions specific to family 14h.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F14
- * @e \$Revision: 37640 $ @e \$Date: 2010-09-08 23:01:59 +0800 (Wed, 08 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuPstateTables.h"
-#include "cpuF14PowerMgmt.h"
-#include "cpuServices.h"
-#include "GeneralServices.h"
-#include "cpuF14Utilities.h"
-#include "cpuPostInit.h"
-#include "Filecode.h"
-#define FILECODE PROC_CPU_FAMILY_0X14_CPUF14UTILITIES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable;
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-VOID
-F14ConvertEnabledBitsIntoCount (
- OUT UINT8 *EnabledCoreCountPtr,
- IN UINT8 FusedCoreCount,
- IN UINT8 EnabledCores
- );
-
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-VOID
-F14ConvertEnabledBitsIntoCount (
- OUT UINT8 *EnabledCoreCountPtr,
- IN UINT8 FusedCoreCount,
- IN UINT8 EnabledCores
- )
-{
- UINT8 i;
- UINT8 j;
- UINT8 EnabledCoreCount;
-
- EnabledCoreCount = 0;
-
- for (i = 0; i < FusedCoreCount+1; i++) {
- j = 1;
- if (!((BOOLEAN) (EnabledCores) & (j << i))) {
- EnabledCoreCount++;
- }
- }
-
- *EnabledCoreCountPtr = EnabledCoreCount;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Disables the desired P-state.
- *
- * @CpuServiceMethod{::F_CPU_DISABLE_PSTATE}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] StateNumber The P-State to disable.
- * @param[in] StdHeader Header for library and services
- *
- * @retval AGESA_SUCCESS Always succeeds.
- */
-AGESA_STATUS
-F14DisablePstate (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN UINT8 StateNumber,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 MsrRegister;
-
- ASSERT (StateNumber < NM_PS_REG);
- LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
- ((PSTATE_MSR *) &MsrRegister)->PsEnable = 0;
- LibAmdMsrWrite (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
- return (AGESA_SUCCESS);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Transitions the executing core to the desired P-state.
- *
- * @CpuServiceMethod{::F_CPU_TRANSITION_PSTATE}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] StateNumber The new P-State to make effective.
- * @param[in] WaitForTransition True if the caller wants the transition completed upon return.
- * @param[in] StdHeader Header for library and services
- *
- * @retval AGESA_SUCCESS Always Succeeds
- */
-AGESA_STATUS
-F14TransitionPstate (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN UINT8 StateNumber,
- IN BOOLEAN WaitForTransition,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 MsrRegister;
-
- ASSERT (StateNumber < NM_PS_REG);
- LibAmdMsrRead (PS_REG_BASE + (UINT32) StateNumber, &MsrRegister, StdHeader);
- ASSERT (((PSTATE_MSR *) &MsrRegister)->PsEnable == 1);
- LibAmdMsrRead (MSR_PSTATE_CTL, &MsrRegister, StdHeader);
- ((PSTATE_CTRL_MSR *) &MsrRegister)->PstateCmd = (UINT64) StateNumber;
- LibAmdMsrWrite (MSR_PSTATE_CTL, &MsrRegister, StdHeader);
- if (WaitForTransition) {
- do {
- LibAmdMsrRead (MSR_PSTATE_STS, &MsrRegister, StdHeader);
- } while (((PSTATE_STS_MSR *) &MsrRegister)->CurPstate != (UINT64) StateNumber);
- }
- return (AGESA_SUCCESS);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Determines the rate at which the executing core's time stamp counter is
- * incrementing.
- *
- * @CpuServiceMethod{::F_CPU_GET_TSC_RATE}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[out] FrequencyInMHz TSC actual frequency.
- * @param[in] StdHeader Header for library and services.
- *
- * @return The most severe status of all called services
- */
-AGESA_STATUS
-F14GetTscRate (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- OUT UINT32 *FrequencyInMHz,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 MsrRegister;
- PSTATE_CPU_FAMILY_SERVICES *FamilyServices;
-
- FamilyServices = NULL;
- GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, &FamilyServices, StdHeader);
- ASSERT (FamilyServices != NULL);
-
- LibAmdMsrRead (0xC0010015, &MsrRegister, StdHeader);
- if ((MsrRegister & 0x01000000) != 0) {
- return (FamilyServices->GetPstateFrequency (FamilyServices, 0, FrequencyInMHz, StdHeader));
- } else {
- return (FamilySpecificServices->GetCurrentNbFrequency (FamilySpecificServices, FrequencyInMHz, StdHeader));
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Determines the NB clock on the desired node.
- *
- * @CpuServiceMethod{::F_CPU_GET_NB_FREQ}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[out] FrequencyInMHz Northbridge clock frequency in MHz.
- * @param[in] StdHeader Header for library and services
- *
- * @retval AGESA_SUCCESS Always succeeds.
- */
-AGESA_STATUS
-F14GetCurrentNbFrequency (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- OUT UINT32 *FrequencyInMHz,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 PciRegister;
- UINT32 MainPllFid;
- PCI_ADDR PciAddress;
-
- PciAddress.AddressValue = CPTC0_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
-
- if (((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->MainPllOpFreqIdEn == 1) {
- MainPllFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &PciRegister)->MainPllOpFreqId;
- } else {
- MainPllFid = 0;
- }
-
- *FrequencyInMHz = ((MainPllFid + 0x10) * 100);
-
- ASSERT (*FrequencyInMHz <= 4000);
-
- return (AGESA_SUCCESS);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Determines the NB clock on the desired node.
- *
- * @CpuServiceMethod{::F_CPU_GET_NB_PSTATE_INFO}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] PlatformConfig Platform profile/build option config structure.
- * @param[in] PciAddress The segment, bus, and device numbers of the CPU in question.
- * @param[in] NbPstate The NB P-state number to check.
- * @param[out] FreqNumeratorInMHz The desired node's frequency numerator in megahertz.
- * @param[out] FreqDivisor The desired node's frequency divisor.
- * @param[out] VoltageInuV The desired node's voltage in microvolts.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @retval TRUE NbPstate is valid
- * @retval FALSE NbPstate is disabled or invalid
- */
-BOOLEAN
-F14GetNbPstateInfo (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN PCI_ADDR *PciAddress,
- IN UINT32 NbPstate,
- OUT UINT32 *FreqNumeratorInMHz,
- OUT UINT32 *FreqDivisor,
- OUT UINT32 *VoltageInuV,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 NbVid;
- UINT32 PciRegister;
- UINT32 MainPllFreq;
- BOOLEAN PstateIsValid;
-
- PstateIsValid = FALSE;
- if ((NbPstate == 0) || ((NbPstate == 1) && FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, PlatformConfig, StdHeader))) {
- FamilySpecificServices->GetCurrentNbFrequency (FamilySpecificServices, &MainPllFreq, StdHeader);
- *FreqNumeratorInMHz = (MainPllFreq * 4);
- if (NbPstate == 0) {
- PciAddress->Address.Function = FUNC_3;
- PciAddress->Address.Register = CPTC2_REG;
- LibAmdPciRead (AccessWidth32, *PciAddress, &PciRegister, StdHeader);
- *FreqDivisor = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->NbPs0NclkDiv;
- NbVid = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &PciRegister)->NbPs0Vid;
- } else {
- PciAddress->Address.Function = FUNC_6;
- PciAddress->Address.Register = NB_PSTATE_CFG_LOW_REG;
- LibAmdPciRead (AccessWidth32, *PciAddress, &PciRegister, StdHeader);
- *FreqDivisor = ((NB_PSTATE_CFG_LOW_REGISTER *) &PciRegister)->NbPs1NclkDiv;
- NbVid = ((NB_PSTATE_CFG_LOW_REGISTER *) &PciRegister)->NbPs1Vid;
- }
- *VoltageInuV = (1550000 - (12500 * NbVid));
- PstateIsValid = TRUE;
- }
- return PstateIsValid;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Is the Northbridge PState feature enabled?
- *
- * @CpuServiceMethod{::F_IS_NB_PSTATE_ENABLED}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] PlatformConfig Platform profile/build option config structure.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @retval TRUE The NB PState feature is enabled.
- * @retval FALSE The NB PState feature is not enabled.
- */
-BOOLEAN
-F14IsNbPstateEnabled (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 PciRegister;
- PCI_ADDR PciAddress;
-
- PciAddress.AddressValue = NB_PSTATE_CFG_LOW_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- return ((BOOLEAN) (((NB_PSTATE_CFG_LOW_REGISTER *) &PciRegister)->NbPsCap == 1));
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns whether or not BIOS is responsible for configuring the NB COFVID.
- *
- * @CpuServiceMethod{::F_CPU_IS_NBCOF_INIT_NEEDED}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] PciAddress The northbridge to query by pci base address.
- * @param[out] NbCofVidUpdateRequired TRUE, perform northbridge frequency and voltage config,
- * FALSE, do not configure them.
- * @param[in] StdHeader Header for library and services
- *
- * @retval AGESA_SUCCESS Always succeeds.
- */
-AGESA_STATUS
-F14GetNbCofVidUpdate (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN PCI_ADDR *PciAddress,
- OUT BOOLEAN *NbCofVidUpdateRequired,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- *NbCofVidUpdateRequired = FALSE;
- return (AGESA_SUCCESS);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Initially launches the desired core to run from the reset vector.
- *
- * @CpuServiceMethod{::F_CPU_AP_INITIAL_LAUNCH}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] SocketNum The Processor on which the core is to be launched
- * @param[in] ModuleNum The Module in that processor containing that core
- * @param[in] CoreNum The Core to launch
- * @param[in] PrimaryCoreNum The id of the module's primary core.
- * @param[in] StdHeader Header for library and services
- *
- * @retval TRUE The core was launched
- * @retval FALSE The core was previously launched
- */
-BOOLEAN
-F14LaunchApCore (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN UINT32 SocketNum,
- IN UINT32 ModuleNum,
- IN UINT32 CoreNum,
- IN UINT32 PrimaryCoreNum,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 NodeRelativeCoreNum;
- UINT32 PciRegister;
- PCI_ADDR PciAddress;
- BOOLEAN LaunchFlag;
-
- // Code Start
- LaunchFlag = FALSE;
- NodeRelativeCoreNum = CoreNum - PrimaryCoreNum;
- PciAddress.AddressValue = MAKE_SBDFO (0, 0, PCI_DEV_BASE, FUNC_0, 0);
-
- switch (NodeRelativeCoreNum) {
- case 1:
- PciAddress.Address.Register = HT_TRANS_CTRL;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- if ((PciRegister & HT_TRANS_CTRL_CPU1_EN) == 0) {
- PciRegister |= HT_TRANS_CTRL_CPU1_EN;
- LibAmdPciWrite (AccessWidth32, PciAddress, &PciRegister, StdHeader);
- LaunchFlag = TRUE;
- } else {
- LaunchFlag = FALSE;
- }
- break;
- default:
- break;
- }
-
- return (LaunchFlag);
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Get CPU Specific Platform Type Info.
- *
- * @CpuServiceMethod{::F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO}.
- *
- * This function returns Returns the platform features.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in,out] Features The Features supported by this platform.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @retval AGESA_SUCCESS Always succeeds.
- */
-AGESA_STATUS
-F14GetPlatformTypeSpecificInfo (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN OUT PLATFORM_FEATS *Features,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- return (AGESA_SUCCESS);
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Get CPU pstate current.
- *
- * @CpuServiceMethod{::F_CPU_GET_IDD_MAX}.
- *
- * This function returns the ProcIddMax.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] Pstate The P-state to check.
- * @param[out] ProcIddMax P-state current in mA.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @retval TRUE P-state is enabled
- * @retval FALSE P-state is disabled
- */
-BOOLEAN
-F14GetProcIddMax (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN UINT8 Pstate,
- OUT UINT32 *ProcIddMax,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 IddDiv;
- UINT32 CmpCap;
- UINT32 PciRegister;
- UINT32 MsrAddress;
- UINT64 PstateMsr;
- BOOLEAN IsPstateEnabled;
- PCI_ADDR PciAddress;
-
- IsPstateEnabled = FALSE;
-
- MsrAddress = (UINT32) (Pstate + PS_REG_BASE);
-
- ASSERT (MsrAddress <= PS_MAX_REG);
-
- LibAmdMsrRead (MsrAddress, &PstateMsr, StdHeader);
- if (((PSTATE_MSR *) &PstateMsr)->PsEnable == 1) {
- PciAddress.AddressValue = NB_CAPS_PCI_ADDR;
- LibAmdPciRead (AccessWidth32, PciAddress, &PciRegister, StdHeader); // F3xE8
- CmpCap = (UINT32) (((NB_CAPS_REGISTER *) &PciRegister)->CmpCap);
- CmpCap++;
-
- switch (((PSTATE_MSR *) &PstateMsr)->IddDiv) {
- case 0:
- IddDiv = 1000;
- break;
- case 1:
- IddDiv = 100;
- break;
- case 2:
- IddDiv = 10;
- break;
- default: // IddDiv = 3 is reserved. Use 10
- ASSERT (FALSE);
- IddDiv = 10;
- break;
- }
-
- *ProcIddMax = (UINT32) ((PSTATE_MSR *) &PstateMsr)->IddValue * IddDiv * CmpCap;
- IsPstateEnabled = TRUE;
- }
- return IsPstateEnabled;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Get number of processor cores to be used in determining the brand string.
- *
- * @CpuServiceMethod{::F_CPU_NUMBER_OF_BRANDSTRING_CORES}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @return The number of cores to be used in brand string calculation.
- */
-UINT8
-F14GetNumberOfCoresForBrandstring (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- CPUID_DATA CpuId;
-
- //
- //CPUID.80000008h.ECX.NC + 1, 000b = 1, 001b = 2, etc.
- //
- LibAmdCpuidRead (CPUID_LONG_MODE_ADDR, &CpuId, StdHeader);
- return ((UINT8) ((CpuId.ECX_Reg & 0xff) + 1));
-}
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14Utilities.h b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14Utilities.h
deleted file mode 100644
index d1b220f..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14Utilities.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_14 specific utility functions.
- *
- * Provides numerous utility functions specific to family 14h.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPU_F14_UTILITES_H_
-#define _CPU_F14_UTILITES_H_
-
-
-/*---------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *---------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *---------------------------------------------------------------------------------------
- */
-
-AGESA_STATUS
-F14DisablePstate (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN UINT8 StateNumber,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-F14TransitionPstate (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN UINT8 StateNumber,
- IN BOOLEAN WaitForTransition,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-F14GetTscRate (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- OUT UINT32 *FrequencyInMHz,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-F14GetCurrentNbFrequency (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- OUT UINT32 *FrequencyInMHz,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-F14GetNbCofVidUpdate (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN PCI_ADDR *PciAddress,
- OUT BOOLEAN *NbCofVidUpdateRequired,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-BOOLEAN
-F14LaunchApCore (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN UINT32 SocketNum,
- IN UINT32 ModuleNum,
- IN UINT32 CoreNum,
- IN UINT32 PrimaryCoreNum,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-CORE_ID_POSITION
-F14CpuAmdCoreIdPositionInInitialApicId (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-F14GetPlatformTypeSpecificInfo (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN OUT PLATFORM_FEATS *Features,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-#endif // _CPU_F14_UTILITES_H_
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14WheaInitDataTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14WheaInitDataTables.c
deleted file mode 100644
index 50c7735..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/0x14/cpuF14WheaInitDataTables.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_14 WHEA initial Data
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuLateInit.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-#define FILECODE PROC_CPU_FAMILY_0X14_CPUF14WHEAINITDATATABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-AMD_HEST_BANK_INIT_DATA F14HestBankInitData[] = {
- {0xFFFFFFFF,0xFFFFFFFF,0x400,0x401,0x402,0x403},
- {0xFFFFFFFF,0xFFFFFFFF,0x404,0x405,0x406,0x407},
- {0xFFFFFFFF,0xFFFFFFFF,0x408,0x409,0x40A,0x40B},
- {0xFFFFFFFF,0xFFFFFFFF,0x410,0x411,0x412,0x413},
- {0xFFFFFFFF,0xFFFFFFFF,0x414,0x415,0x416,0x417},
-};
-
-AMD_WHEA_INIT_DATA F14WheaInitData = {
- 0x000000000, // AmdGlobCapInitDataLsd
- 0x000000000, // AmdGlobCapInitDataMsd
- 0x00000003F, // AmdGlobCtrlInitDataLsd
- 0x000000000, // AmdGlobCtrlInitDataMsd
- 0x00, // AmdMcbClrStatusOnInit
- 0x02, // AmdMcbStatusDataFormat
- 0x00, // AmdMcbConfWriteEn
- (sizeof (F14HestBankInitData) / sizeof (F14HestBankInitData[0])), // HestBankNum
- &F14HestBankInitData[0] // Pointer to Initial data of HEST Bank
-};
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns the family specific WHEA table properties.
- *
- * @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[out] F14WheaInitDataPtr Points to the family 12h WHEA properties.
- * @param[out] NumberOfElements Will be one to indicate one structure.
- * @param[in] StdHeader Header for library and services.
- *
- */
-VOID
-GetF14WheaInitData (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- OUT CONST VOID **F14WheaInitDataPtr,
- OUT UINT8 *NumberOfElements,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- *NumberOfElements = 1;
- *F14WheaInitDataPtr = &F14WheaInitData;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Family/cpuFamRegisters.h b/src/vendorcode/amd/agesa/Proc/CPU/Family/cpuFamRegisters.h
deleted file mode 100644
index bfbbf9b..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Family/cpuFamRegisters.h
+++ /dev/null
@@ -1,213 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU Register Table Related Functions
- *
- * Contains the definition of the CPU CPUID MSRs and PCI registers with BKDG recommended values
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 36421 $ @e \$Date: 2010-08-18 22:46:48 +0800 (Wed, 18 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPU_FAM_REGISTERS_H_
-#define _CPU_FAM_REGISTERS_H_
-
-/*
- *--------------------------------------------------------------
- *
- * M O D U L E S U S E D
- *
- *---------------------------------------------------------------
- */
-
-/*
- *--------------------------------------------------------------
- *
- * D E F I N I T I O N S / M A C R O S
- *
- *---------------------------------------------------------------
- */
-
-// This define should be equal to the total number of families
-// in the cpuFamily enum.
-#define MAX_CPU_FAMILIES 64
-#define MAX_CPU_REVISIONS 63 // Max Cpu Revisions Per Family
-
-// CPU_LOGICAL_ID.Family equates
-// Family 10h equates
-#define AMD_FAMILY_10_RB 0x0000000000000001
-#define AMD_FAMILY_10_BL 0x0000000000000002
-#define AMD_FAMILY_10_DA 0x0000000000000004
-#define AMD_FAMILY_10_HY 0x0000000000000008
-#define AMD_FAMILY_10_PH 0x0000000000000010
-#define AMD_FAMILY_10_C32 AMD_FAMILY_10_HY
-
-#define AMD_FAMILY_10 (AMD_FAMILY_10_RB | AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_HY | AMD_FAMILY_10_PH)
-#define AMD_FAMILY_GH (AMD_FAMILY_10)
-
-// Family 12h equates
-#define AMD_FAMILY_12_LN 0x0000000000000020
-#define AMD_FAMILY_12 (AMD_FAMILY_12_LN)
-#define AMD_FAMILY_LN (AMD_FAMILY_12_LN)
-
-// Family 14h equates
-#define AMD_FAMILY_14_ON 0x0000000000000040
-#define AMD_FAMILY_14 (AMD_FAMILY_14_ON)
-#define AMD_FAMILY_ON (AMD_FAMILY_14_ON)
-
-// Family 15h equates
-#define AMD_FAMILY_15_OR 0x0000000000000080
-#define AMD_FAMILY_15 (AMD_FAMILY_15_OR)
-#define AMD_FAMILY_OR (AMD_FAMILY_15_OR)
-
-// Family 16h equates
-#define AMD_FAMILY_16 0x0000000000000100
-#define AMD_FAMILY_WF (AMD_FAMILY_16)
-
-// Family Unknown
-#define AMD_FAMILY_UNKNOWN 0x8000000000000000
-
-// Family Group equates
-#define AMD_FAMILY_GE_12 (AMD_FAMILY_12 | AMD_FAMILY_14 | AMD_FAMILY_15 | AMD_FAMILY_16)
-
-// Family 10h CPU_LOGICAL_ID.Revision equates
-// -------------------------------------
- // Family 10h RB steppings
-#define AMD_F10_RB_C0 0x0000000000000001
-#define AMD_F10_RB_C1 0x0000000000000002
-#define AMD_F10_RB_C2 0x0000000000000004
-#define AMD_F10_RB_C3 0x0000000000000008
- // Family 10h BL steppings
-#define AMD_F10_BL_C2 0x0000000000000010
-#define AMD_F10_BL_C3 0x0000000000000020
- // Family 10h DA steppings
-#define AMD_F10_DA_C2 0x0000000000000040
-#define AMD_F10_DA_C3 0x0000000000000080
- // Family 10h HY SCM steppings
-#define AMD_F10_HY_SCM_D0 0x0000000000000100
-#define AMD_F10_HY_SCM_D1 0x0000000000000400
- // Family 10h HY MCM steppings
-#define AMD_F10_HY_MCM_D0 0x0000000000000200
-#define AMD_F10_HY_MCM_D1 0x0000000000000800
- // Family 10h PH steppings
-#define AMD_F10_PH_E0 0x0000000000001000
-
- // Family 10h Unknown stepping
-#define AMD_F10_UNKNOWN 0x8000000000000000
-
- // Family 10h Miscellaneous equates
-#define AMD_F10_C0 (AMD_F10_RB_C0)
-#define AMD_F10_C1 (AMD_F10_RB_C1)
-#define AMD_F10_C2 (AMD_F10_RB_C2 | AMD_F10_DA_C2 | AMD_F10_BL_C2)
-#define AMD_F10_C3 (AMD_F10_RB_C3 | AMD_F10_DA_C3 | AMD_F10_BL_C3)
-#define AMD_F10_Cx (AMD_F10_C0 | AMD_F10_C1 | AMD_F10_C2 | AMD_F10_C3)
-
-#define AMD_F10_RB_ALL (AMD_F10_RB_C0 | AMD_F10_RB_C1 | AMD_F10_RB_C2 | AMD_F10_RB_C3)
-
-#define AMD_F10_BL_ALL (AMD_F10_BL_C2 | AMD_F10_BL_C3)
-#define AMD_F10_BL_Cx (AMD_F10_BL_C2 | AMD_F10_BL_C3)
-
-#define AMD_F10_DA_ALL (AMD_F10_DA_C2 | AMD_F10_DA_C3)
-#define AMD_F10_DA_Cx (AMD_F10_DA_C2 | AMD_F10_DA_C3)
-
-#define AMD_F10_D0 (AMD_F10_HY_SCM_D0 | AMD_F10_HY_MCM_D0)
-#define AMD_F10_D1 (AMD_F10_HY_SCM_D1 | AMD_F10_HY_MCM_D1)
-#define AMD_F10_Dx (AMD_F10_D0 | AMD_F10_D1)
-
-#define AMD_F10_PH_ALL (AMD_F10_PH_E0)
-#define AMD_F10_Ex (AMD_F10_PH_E0)
-
-#define AMD_F10_HY_ALL (AMD_F10_Dx)
-#define AMD_F10_C32_ALL (AMD_F10_HY_SCM_D0 | AMD_F10_HY_SCM_D1)
-
-#define AMD_F10_GT_B0 (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex)
-#define AMD_F10_GT_Bx (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex)
-#define AMD_F10_GT_A2 (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex)
-#define AMD_F10_GT_Ax (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex)
-#define AMD_F10_GT_C0 ((AMD_F10_Cx & ~AMD_F10_C0) | AMD_F10_Dx | AMD_F10_Ex)
-#define AMD_F10_GT_D0 (AMD_F10_Dx & ~AMD_F10_D0 | AMD_F10_Ex)
-
-#define AMD_F10_ALL (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex | AMD_F10_UNKNOWN)
-
-// Family 12h CPU_LOGICAL_ID.Revision equates
-// -------------------------------------
-
- // Family 12h LN steppings
-#define AMD_F12_LN_A0 0x0000000000000001
-#define AMD_F12_LN_A1 0x0000000000000002
-#define AMD_F12_LN_B0 0x0000000000000004
- // Family 12h Unknown stepping
-#define AMD_F12_UNKNOWN 0x8000000000000000
-
-#define AMD_F12_LN_Ax (AMD_F12_LN_A0 | AMD_F12_LN_A1)
-#define AMD_F12_LN_Bx (AMD_F12_LN_B0)
-
-#define AMD_F12_ALL (AMD_F12_LN_Ax | AMD_F12_LN_Bx | AMD_F12_UNKNOWN)
-
-// Family 14h CPU_LOGICAL_ID.Revision equates
-// -------------------------------------
-
- // Family 14h ON steppings
-#define AMD_F14_ON_A0 0x0000000000000001
-#define AMD_F14_ON_A1 0x0000000000000002
-#define AMD_F14_ON_B0 0x0000000000000004
- // Family 14h Unknown stepping
-#define AMD_F14_UNKNOWN 0x8000000000000000
-
-#define AMD_F14_ON_Ax (AMD_F14_ON_A0 | AMD_F14_ON_A1)
-#define AMD_F14_ON_Bx (AMD_F14_ON_B0)
-
-#define AMD_F14_ALL (AMD_F14_ON_Ax | AMD_F14_ON_Bx | AMD_F14_UNKNOWN)
-
-// Family 15h CPU_LOGICAL_ID.Revision equates
-// -------------------------------------
-
- // Family 15h OROCHI steppings
-#define AMD_F15_OR_A0 0x0000000000000001
- // Family 15h Unknown stepping
-#define AMD_F15_UNKNOWN 0x8000000000000000
-
-#define AMD_F15_OR_Ax (AMD_F15_OR_A0)
-
-#define AMD_F15_ALL (AMD_F15_OR_Ax | AMD_F15_UNKNOWN)
-
-// Family 16h CPU_LOGICAL_ID.Revision equates
-// TBD
-
-#endif // _CPU_FAM_REGISTERS_H_
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Feature/PreserveMailbox.c b/src/vendorcode/amd/agesa/Proc/CPU/Feature/PreserveMailbox.c
deleted file mode 100644
index a685357..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Feature/PreserveMailbox.c
+++ /dev/null
@@ -1,218 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD AGESA CPU Preserve Registers used for AP Mailbox.
- *
- * Save and Restore the normal feature content of the registers being used for
- * the AP Mailbox.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/Feature
- * @e \$Revision: 37564 $ @e \$Date: 2010-09-08 05:03:38 +0800 (Wed, 08 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "GeneralServices.h"
-#include "OptionMultiSocket.h"
-#include "cpuRegisters.h"
-#include "cpuApicUtilities.h"
-#include "cpuServices.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuFeatures.h"
-#include "PreserveMailbox.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FEATURE_PRESERVEMAILBOX_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-extern CPU_FAMILY_SUPPORT_TABLE PreserveMailboxFamilyServiceTable;
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * The contents of the mailbox registers should always be preserved.
- *
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval TRUE Always TRUE
- *
- */
-BOOLEAN
-STATIC
-IsPreserveAroundMailboxEnabled (
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- return TRUE;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Save and Restore or Initialize the content of the mailbox registers.
- *
- * The registers used for AP mailbox should have the content related to their function
- * preserved.
- *
- * @param[in] EntryPoint Timepoint designator.
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @return AGESA_SUCCESS Always succeeds.
- *
- */
-AGESA_STATUS
-STATIC
-PreserveMailboxes (
- IN UINT64 EntryPoint,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- PRESERVE_MAILBOX_FAMILY_SERVICES *FamilySpecificServices;
- UINT32 Socket;
- UINT32 Module;
- PCI_ADDR BaseAddress;
- PCI_ADDR MailboxRegister;
- PCI_ADDR *NextRegister;
- AGESA_STATUS IgnoredStatus;
- AGESA_STATUS HeapStatus;
- UINT32 Value;
- ALLOCATE_HEAP_PARAMS AllocateParams;
- LOCATE_HEAP_PTR LocateParams;
- UINT32 RegisterEntryIndex;
-
- BaseAddress.AddressValue = ILLEGAL_SBDFO;
-
- if (EntryPoint == CPU_FEAT_AFTER_COHERENT_DISCOVERY) {
- // The save step. Save either the register content or zero (for cold boot, if family specifies that).
- AllocateParams.BufferHandle = PRESERVE_MAIL_BOX_HANDLE;
- AllocateParams.RequestedBufferSize = (sizeof (UINT32) * (MAX_PRESERVE_REGISTER_ENTRIES * (MAX_SOCKETS * MAX_DIES)));
- AllocateParams.Persist = HEAP_SYSTEM_MEM;
- HeapStatus = HeapAllocateBuffer (&AllocateParams, StdHeader);
- ASSERT ((HeapStatus == AGESA_SUCCESS) && (AllocateParams.BufferPtr != NULL));
- LibAmdMemFill (AllocateParams.BufferPtr, 0xFF, AllocateParams.RequestedBufferSize, StdHeader);
- RegisterEntryIndex = 0;
- for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
- for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
- if (GetPciAddress (StdHeader, Socket, Module, &BaseAddress, &IgnoredStatus)) {
- GetFeatureServicesOfSocket (&PreserveMailboxFamilyServiceTable, Socket, &FamilySpecificServices, StdHeader);
- ASSERT (FamilySpecificServices != NULL);
- NextRegister = FamilySpecificServices->RegisterList;
- while (NextRegister->AddressValue != ILLEGAL_SBDFO) {
- ASSERT (RegisterEntryIndex <
- (MAX_PRESERVE_REGISTER_ENTRIES * GetPlatformNumberOfSockets () * GetPlatformNumberOfModules ()));
- if (FamilySpecificServices->IsZeroOnCold && (!IsWarmReset (StdHeader))) {
- Value = 0;
- } else {
- MailboxRegister = BaseAddress;
- MailboxRegister.Address.Function = NextRegister->Address.Function;
- MailboxRegister.Address.Register = NextRegister->Address.Register;
- LibAmdPciRead (AccessWidth32, MailboxRegister, &Value, StdHeader);
- }
- (* (MAILBOX_REGISTER_SAVE_ENTRY) AllocateParams.BufferPtr) [RegisterEntryIndex] = Value;
- RegisterEntryIndex++;
- NextRegister++;
- }
- }
- }
- }
- } else if ((EntryPoint == CPU_FEAT_INIT_LATE_END) || (EntryPoint == CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) {
- // The restore step. Just write out the saved content in the buffer.
- LocateParams.BufferHandle = PRESERVE_MAIL_BOX_HANDLE;
- HeapStatus = HeapLocateBuffer (&LocateParams, StdHeader);
- ASSERT ((HeapStatus == AGESA_SUCCESS) && (LocateParams.BufferPtr != NULL));
- RegisterEntryIndex = 0;
- for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
- for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
- if (GetPciAddress (StdHeader, Socket, Module, &BaseAddress, &IgnoredStatus)) {
- GetFeatureServicesOfSocket (&PreserveMailboxFamilyServiceTable, Socket, &FamilySpecificServices, StdHeader);
- NextRegister = FamilySpecificServices->RegisterList;
- while (NextRegister->AddressValue != ILLEGAL_SBDFO) {
- ASSERT (RegisterEntryIndex <
- (MAX_PRESERVE_REGISTER_ENTRIES * GetPlatformNumberOfSockets () * GetPlatformNumberOfModules ()));
- MailboxRegister = BaseAddress;
- MailboxRegister.Address.Function = NextRegister->Address.Function;
- MailboxRegister.Address.Register = NextRegister->Address.Register;
- Value = (* (MAILBOX_REGISTER_SAVE_ENTRY) LocateParams.BufferPtr) [RegisterEntryIndex];
- LibAmdPciWrite (AccessWidth32, MailboxRegister, &Value, StdHeader);
- RegisterEntryIndex++;
- NextRegister++;
- }
- }
- }
- }
- HeapStatus = HeapDeallocateBuffer (PRESERVE_MAIL_BOX_HANDLE, StdHeader);
- }
- return AGESA_SUCCESS;
-}
-
-
-CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePreserveAroundMailbox =
-{
- PreserveAroundMailbox,
- (CPU_FEAT_AFTER_COHERENT_DISCOVERY | CPU_FEAT_INIT_LATE_END | CPU_FEAT_AFTER_RESUME_MTRR_SYNC),
- IsPreserveAroundMailboxEnabled,
- PreserveMailboxes
-};
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Feature/PreserveMailbox.h b/src/vendorcode/amd/agesa/Proc/CPU/Feature/PreserveMailbox.h
deleted file mode 100644
index e229eeb..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Feature/PreserveMailbox.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD AGESA CPU Preserve Registers used for AP Mailbox.
- *
- * Save and Restore the normal feature content of the registers being used for
- * the AP Mailbox.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/Feature
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _PRESERVE_MAILBOX_H_
-#define _PRESERVE_MAILBOX_H_
-
-/*----------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *----------------------------------------------------------------------------------------
- */
-#define MAX_PRESERVE_REGISTER_ENTRIES 2 ///< There is room on the heap for up to this per node.
-
-/// Reference to a save buffer.
-typedef UINT32 (*MAILBOX_REGISTER_SAVE_ENTRY) [MAX_PRESERVE_REGISTER_ENTRIES];
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/**
- * Descriptor for family specific save-restore.
- *
- * Provide a list of the register offsets to save-restore on each node. Optionally, zero the
- * register instead of restoring it.
- */
-typedef struct {
- UINT16 Revision; ///< Interface version
- // Public Data.
- BOOLEAN IsZeroOnCold; ///< On a cold boot, zero the register instead of restore.
- PCI_ADDR *RegisterList; ///< The list of registers, terminated by ILLEGAL_SBDFO.
-} PRESERVE_MAILBOX_FAMILY_SERVICES;
-
-
-/*----------------------------------------------------------------------------------------
- * F U N C T I O N S P R O T O T Y P E
- *----------------------------------------------------------------------------------------
- */
-
-#endif // _PRESERVE_MAILBOX_H_
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuC6State.c b/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuC6State.c
deleted file mode 100644
index bcc3bd8..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuC6State.c
+++ /dev/null
@@ -1,262 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD AGESA CPU C6 feature support code.
- *
- * Contains code that declares the AGESA CPU C6 related APIs
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/Feature
- * @e \$Revision: 36186 $ @e \$Date: 2010-08-13 01:10:33 +0800 (Fri, 13 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-#include "GeneralServices.h"
-#include "cpuFamilyTranslation.h"
-#include "OptionMultiSocket.h"
-#include "cpuApicUtilities.h"
-#include "cpuServices.h"
-#include "cpuFeatures.h"
-#include "cpuC6State.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FEATURE_CPUC6STATE_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-VOID
-STATIC
-EnableC6OnSocket (
- IN VOID *EntryPoint,
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams
- );
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-extern CPU_FAMILY_SUPPORT_TABLE C6FamilyServiceTable;
-extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Should C6 be enabled
- *
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval TRUE C6 is supported.
- * @retval FALSE C6 cannot be enabled.
- *
- */
-BOOLEAN
-STATIC
-IsC6FeatureEnabled (
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Socket;
- BOOLEAN IsEnabled;
- C6_FAMILY_SERVICES *FamilyServices;
-
- IsEnabled = FALSE;
- if (PlatformConfig->CStateMode == CStateModeC6) {
- IsEnabled = TRUE;
- for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
- if (IsProcessorPresent (Socket, StdHeader)) {
- GetFeatureServicesOfSocket (&C6FamilyServiceTable, Socket, &FamilyServices, StdHeader);
- if ((FamilyServices == NULL) || !FamilyServices->IsC6Supported (FamilyServices, Socket, StdHeader)) {
- IsEnabled = FALSE;
- break;
- }
- }
- }
- }
- return IsEnabled;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Enable the C6 C-state
- *
- * @param[in] EntryPoint Timepoint designator.
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval AGESA_SUCCESS Always succeeds.
- *
- */
-AGESA_STATUS
-STATIC
-InitializeC6Feature (
- IN UINT64 EntryPoint,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 BscSocket;
- UINT32 Ignored;
- UINT32 BscCore;
- UINT32 Core;
- UINT32 Socket;
- UINT32 NumberOfSockets;
- UINT32 NumberOfCores;
- AP_TASK TaskPtr;
- AMD_CPU_EARLY_PARAMS CpuEarlyParams;
- C6_FAMILY_SERVICES *C6FamilyServices;
- AGESA_STATUS IgnoredSts;
-
- CpuEarlyParams.PlatformConfig = *PlatformConfig;
-
- TaskPtr.FuncAddress.PfApTaskIC = EnableC6OnSocket;
- TaskPtr.DataTransfer.DataSizeInDwords = 2;
- TaskPtr.DataTransfer.DataPtr = &EntryPoint;
- TaskPtr.DataTransfer.DataTransferFlags = 0;
- TaskPtr.ExeFlags = PASS_EARLY_PARAMS;
- OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, &CpuEarlyParams);
-
- if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
- // Load any required microcode patches on both normal boot and resume from S3.
- IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredSts);
- GetFeatureServicesOfSocket (&C6FamilyServiceTable, BscSocket, &C6FamilyServices, StdHeader);
- if (C6FamilyServices != NULL) {
- C6FamilyServices->ReloadMicrocodePatchAfterMemInit (StdHeader);
- }
-
- // run code on all APs
- TaskPtr.DataTransfer.DataSizeInDwords = 0;
- TaskPtr.ExeFlags = 0;
-
- NumberOfSockets = GetPlatformNumberOfSockets ();
-
- for (Socket = 0; Socket < NumberOfSockets; Socket++) {
- if (IsProcessorPresent (Socket, StdHeader)) {
- GetFeatureServicesOfSocket (&C6FamilyServiceTable, Socket, &C6FamilyServices, StdHeader);
- if (C6FamilyServices != NULL) {
- // run code on all APs
- TaskPtr.FuncAddress.PfApTask = C6FamilyServices->ReloadMicrocodePatchAfterMemInit;
- if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
- for (Core = 0; Core < NumberOfCores; Core++) {
- if ((Socket != BscSocket) || (Core != BscCore)) {
- ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);
- }
- }
- }
- }
- }
- }
- }
- return AGESA_SUCCESS;
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * 'Local' core 0 task to enable C6 on it's socket.
- *
- * @param[in] EntryPoint Timepoint designator.
- * @param[in] StdHeader Config Handle for library, services.
- * @param[in] CpuEarlyParams Service parameters.
- *
- */
-VOID
-STATIC
-EnableC6OnSocket (
- IN VOID *EntryPoint,
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams
- )
-{
-
- C6_FAMILY_SERVICES *FamilyServices;
-
- IDS_HDT_CONSOLE (CPU_TRACE, " C6 is enabled\n");
-
- GetFeatureServicesOfCurrentCore (&C6FamilyServiceTable, &FamilyServices, StdHeader);
- FamilyServices->InitializeC6 (FamilyServices,
- *((UINT64 *) EntryPoint),
- &CpuEarlyParams->PlatformConfig,
- StdHeader);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Reload microcode patch after memory is initialized.
- *
- * @param[in] StdHeader Config Handle for library, services.
- *
- */
-VOID
-ReloadMicrocodePatchAfterMemInit (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- LoadMicrocodePatch (StdHeader);
-}
-
-
-CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State =
-{
- C6Cstate,
- (CPU_FEAT_AFTER_PM_INIT | CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC),
- IsC6FeatureEnabled,
- InitializeC6Feature
-};
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuC6State.h b/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuC6State.h
deleted file mode 100644
index 546f04c..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuC6State.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD AGESA CPU C6 Functions declarations.
- *
- * Contains code that declares the AGESA CPU C6 related APIs
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/Feature
- * @e \$Revision: 36567 $ @e \$Date: 2010-08-21 02:35:15 +0800 (Sat, 21 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPU_C6_STATE_H_
-#define _CPU_C6_STATE_H_
-
-/*----------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *----------------------------------------------------------------------------------------
- */
-// Forward declaration needed for multi-structure mutual references
-AGESA_FORWARD_DECLARATION (C6_FAMILY_SERVICES);
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family specific call to check if C6 is supported.
- *
- * @param[in] C6Services C6 C-state services.
- * @param[in] Socket Zero-based socket number.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval TRUE C6 is supported.
- * @retval FALSE C6 is not supported.
- *
- */
-typedef BOOLEAN F_C6_IS_SUPPORTED (
- IN C6_FAMILY_SERVICES *C6Services,
- IN UINT32 Socket,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_C6_IS_SUPPORTED *PF_C6_IS_SUPPORTED;
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family specific call to enable C6.
- *
- * @param[in] C6Services C6 services.
- * @param[in] EntryPoint Timepoint designator.
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @return Family specific error value.
- *
- */
-typedef AGESA_STATUS F_C6_INIT (
- IN C6_FAMILY_SERVICES *C6Services,
- IN UINT64 EntryPoint,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_C6_INIT *PF_C6_INIT;
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family specific call to reload microcode patch after memory is initialized.
- *
- * @param[in] StdHeader Config Handle for library, services.
- *
- */
-typedef VOID F_C6_RELOAD_MICORCODE_PATCH_AFTER_MEM_INIT (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_C6_RELOAD_MICORCODE_PATCH_AFTER_MEM_INIT *PF_C6_RELOAD_MICORCODE_PATCH_AFTER_MEM_INIT;
-
-/**
- * Provide the interface to the C6 Family Specific Services.
- *
- * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
- * Each supported Family must provide an implementation for all methods in this interface, even if the
- * implementation is a CommonReturn().
- */
-struct _C6_FAMILY_SERVICES {
- UINT16 Revision; ///< Interface version
- // Public Methods.
- PF_C6_IS_SUPPORTED IsC6Supported; ///< Method: Family specific call to check if C6 is supported.
- PF_C6_INIT InitializeC6; ///< Method: Family specific call to enable C6.
- PF_C6_RELOAD_MICORCODE_PATCH_AFTER_MEM_INIT ReloadMicrocodePatchAfterMemInit; ///< Method: Family specific call to reload microcode patch after memory is initialized.
-};
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Reload microcode patch after memory is initialized.
- *
- * @param[in] StdHeader Config Handle for library, services.
- *
- */
-VOID
-ReloadMicrocodePatchAfterMemInit (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*----------------------------------------------------------------------------------------
- * F U N C T I O N S P R O T O T Y P E
- *----------------------------------------------------------------------------------------
- */
-
-#endif // _CPU_C6_STATE_H_
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuCacheFlushOnHalt.c
deleted file mode 100644
index 3187212..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuCacheFlushOnHalt.c
+++ /dev/null
@@ -1,193 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU Cache Flush On Halt Function.
- *
- * Contains code to Level the Feature in a multi-socket system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "amdlib.h"
-#include "cpuRegisters.h"
-#include "GeneralServices.h"
-#include "cpuServices.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuFeatures.h"
-#include "cpuApicUtilities.h"
-#include "OptionMultiSocket.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-#define FILECODE PROC_CPU_FEATURE_CPUCACHEFLUSHONHALT_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-extern CPU_FAMILY_SUPPORT_TABLE CacheFlushOnHaltFamilyServiceTable;
-extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-VOID
-STATIC
-EnableCacheFlushOnHaltOnSocket (
- IN VOID *EntryPoint,
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams
- );
-/*----------------------------------------------------------------------------------------
- * P U B L I C F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Should cache flush on halt be enabled
- *
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval TRUE core leveling is supported.
- * @retval FALSE core leveling cannot be enabled.
- *
- */
-BOOLEAN
-STATIC
-IsCFOHEnabled (
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- return (TRUE);
-}
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * InitializeCacheFlushOnHaltFeature
- *
- * CPU feature leveling. Enable Cpu Cache Flush On Halt Function
- *
- * @param[in] EntryPoint Timepoint designator.
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in,out] StdHeader Pointer to AMD_CONFIG_PARAMS struct.
- *
- * @return The most severe status of any family specific service.
- */
-AGESA_STATUS
-InitializeCacheFlushOnHaltFeature (
- IN UINT64 EntryPoint,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
-
- AP_TASK TaskPtr;
- AMD_CPU_EARLY_PARAMS CpuEarlyParams;
-
- CpuEarlyParams.PlatformConfig = *PlatformConfig;
-
- IDS_HDT_CONSOLE (CPU_TRACE, " Cache flush on hlt feature is enabled\n");
- TaskPtr.FuncAddress.PfApTaskIC = EnableCacheFlushOnHaltOnSocket;
- TaskPtr.DataTransfer.DataSizeInDwords = 2;
- TaskPtr.DataTransfer.DataPtr = &EntryPoint;
- TaskPtr.DataTransfer.DataTransferFlags = 0;
- TaskPtr.ExeFlags = PASS_EARLY_PARAMS;
- OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, &CpuEarlyParams);
-
- return AGESA_SUCCESS;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * 'Local' core 0 task to enable Cache Flush On Halt on it's socket.
- *
- * @param[in] EntryPoint Timepoint designator.
- * @param[in] StdHeader Config Handle for library, services.
- * @param[in] CpuEarlyParams Service parameters.
- *
- */
-VOID
-STATIC
-EnableCacheFlushOnHaltOnSocket (
- IN VOID *EntryPoint,
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams
- )
-{
- CPU_CFOH_FAMILY_SERVICES *FamilyServices;
-
- GetFeatureServicesOfCurrentCore (&CacheFlushOnHaltFamilyServiceTable, &FamilyServices, StdHeader);
- if (FamilyServices != NULL) {
- FamilyServices->SetCacheFlushOnHaltRegister (FamilyServices, *((UINT64 *) EntryPoint), &CpuEarlyParams->PlatformConfig, StdHeader);
- }
-}
-
-CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt =
-{
- CacheFlushOnHalt,
- (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC),
- IsCFOHEnabled,
- InitializeCacheFlushOnHaltFeature
-};
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuCacheInit.c
deleted file mode 100644
index a38434a..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuCacheInit.c
+++ /dev/null
@@ -1,744 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU Execution Cache Allocation functions.
- *
- * Contains code for doing Execution Cache Allocation for ROM space
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "Topology.h"
-#include "cpuServices.h"
-#include "GeneralServices.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuCacheInit.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FEATURE_CPUCACHEINIT_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-// 8Meg, ~max ROM space
-#define SIZE_INFINITE_EXE_CACHE ((1024 * 1024) * 8)
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * L2 cache Association to Way translation table
- *----------------------------------------------------------------------------
- */
-CONST UINT8 ROMDATA L2AssocToL2WayTranslationTable[] =
-{
- 0,
- 1,
- 2,
- 0xFF,
- 4,
- 0xFF,
- 8,
- 0xFF,
- 16,
- 0xFF,
- 32,
- 48,
- 64,
- 96,
- 128,
- 0xFF,
-};
-
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-UINT8
-STATIC
-Ceiling (
- IN UINT32 Divisor,
- IN UINT32 Dividend
- );
-
-UINT32
-STATIC
-CalculateOccupiedExeCache (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-STATIC
-CompareRegions (
- IN EXECUTION_CACHE_REGION ARegion,
- IN EXECUTION_CACHE_REGION BRegion,
- IN OUT MERGED_CACHE_REGION *CRegion,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-BOOLEAN
-STATIC
-IsPowerOfTwo (
- IN UINT32 TestNumber
- );
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * This function will setup ROM execution cache.
- *
- * The execution cache regions are passed in, the max number of execution cache regions
- * is three. Several rules are checked for compliance. If a rule test fails then one of
- * these error suffixes will be added to the general CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR
- * in the SubReason field
- * -1 available cache size is less than requested, the ROM execution cache
- * region has been reduced or eliminated.
- * -2 at least one execution cache region crosses the 1MB line, the ROM execution
- * cache size has been reduced.
- * -3 at least one execution cache region crosses the 4GB line, the ROM execution
- * cache size has been reduced.
- * -4 the start address of a region is not at the boundary of cache size,
- * the starting address has been adjusted downward
- * -5 execution cache start address less than D0000, request is ignored
- * -6 more than 2 execution cache regions are above 1MB, request is ignored
- * If the start address of all three regions are zero, then no execution cache is allocated.
- *
- * @param[in] StdHeader Handle to config for library and services
- * @param[in] AmdExeAddrMapPtr Pointer to the start of EXECUTION_CACHE_REGION array
- *
- * @retval AGESA_SUCCESS No error
- * @retval AGESA_WARNING AGESA_CACHE_SIZE_REDUCED; AGESA_CACHE_REGIONS_ACROSS_1MB;
- * AGESA_CACHE_REGIONS_ACROSS_4GB;
- * @retval AGESA_ERROR AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY;
- * AGESA_CACHE_START_ADDRESS_LESS_D0000;
- * AGESA_THREE_CACHE_REGIONS_ABOVE_1MB;
- *
- */
-AGESA_STATUS
-AllocateExecutionCache (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr
- )
-{
- AGESA_STATUS AgesaStatus;
- AMD_GET_EXE_SIZE_PARAMS AmdGetExeSize;
- UINT32 CurrentAllocatedExeCacheSize;
- UINT32 RemainingExecutionCacheSize;
- UINT64 MsrData;
- UINT64 SecondMsrData;
- UINT32 RequestStartAddr;
- UINT32 RequestSize;
- UINT32 StartFixMtrr;
- UINT32 CurrentMtrr;
- UINT32 EndFixMtrr;
- UINT8 i;
- UINT8 Ignored;
- CACHE_INFO *CacheInfoPtr;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
- EXECUTION_CACHE_REGION MtrrV6;
- EXECUTION_CACHE_REGION MtrrV7;
- MERGED_CACHE_REGION Result;
-
- //
- // If start addresses of all three regions are zero, then return early
- //
- if (AmdExeAddrMapPtr[0].ExeCacheStartAddr == 0) {
- if (AmdExeAddrMapPtr[1].ExeCacheStartAddr == 0) {
- if (AmdExeAddrMapPtr[2].ExeCacheStartAddr == 0) {
- // No regions defined by the caller
- return AGESA_SUCCESS;
- }
- }
- }
-
- // Get available cache size for ROM execution
- AmdGetExeSize.StdHeader = *StdHeader;
- AgesaStatus = AmdGetAvailableExeCacheSize (&AmdGetExeSize);
- CurrentAllocatedExeCacheSize = CalculateOccupiedExeCache (StdHeader);
- ASSERT (CurrentAllocatedExeCacheSize <= AmdGetExeSize.AvailableExeCacheSize);
- IDS_HDT_CONSOLE (CPU_TRACE, " Cache size available for execution cache: 0x%x\n", AmdGetExeSize.AvailableExeCacheSize);
- RemainingExecutionCacheSize = AmdGetExeSize.AvailableExeCacheSize - CurrentAllocatedExeCacheSize;
-
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
- FamilySpecificServices->GetCacheInfo (FamilySpecificServices, &CacheInfoPtr, &Ignored, StdHeader);
-
- // Process each request entry 0 to 2
- for (i = 0; i < 3; i++) {
- // Exit if no more cache available
- if (RemainingExecutionCacheSize == 0) {
- break;
- }
-
- // Skip the region if ExeCacheSize = 0
- if (AmdExeAddrMapPtr[i].ExeCacheSize == 0) {
- continue;
- }
-
- // Align starting addresses on 32K boundary
- AmdExeAddrMapPtr[i].ExeCacheStartAddr =
- AmdExeAddrMapPtr[i].ExeCacheStartAddr & 0xFFFF8000;
-
- // Adjust size to multiple of 32K (rounding up)
- if ((AmdExeAddrMapPtr[i].ExeCacheSize % 0x8000) != 0) {
- AmdExeAddrMapPtr[i].ExeCacheSize = ((AmdExeAddrMapPtr[i].ExeCacheSize + 0x8000) & 0xFFFF8000);
- }
-
- // Boundary alignment check and confirm size is an even power of two
- if ( !IsPowerOfTwo (AmdExeAddrMapPtr[i].ExeCacheSize) ||
- ((AmdExeAddrMapPtr[i].ExeCacheStartAddr % AmdExeAddrMapPtr[i].ExeCacheSize) != 0) ) {
- AgesaStatus = AGESA_ERROR;
- PutEventLog (AgesaStatus,
- (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR + AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY),
- i, AmdExeAddrMapPtr[i].ExeCacheStartAddr, AmdExeAddrMapPtr[i].ExeCacheSize, 0, StdHeader);
- break;
- }
-
- // Check start address boundary
- if (AmdExeAddrMapPtr[i].ExeCacheStartAddr < 0xD0000) {
- AgesaStatus = AGESA_ERROR;
- PutEventLog (AgesaStatus,
- (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR + AGESA_CACHE_START_ADDRESS_LESS_D0000),
- i, AmdExeAddrMapPtr[i].ExeCacheStartAddr, AmdExeAddrMapPtr[i].ExeCacheSize, 0, StdHeader);
- break;
- }
- // Verify available execution cache size for region 0 to 2 request
- if (RemainingExecutionCacheSize < AmdExeAddrMapPtr[i].ExeCacheSize) {
- // Request is larger than available, reduce the allocation & report the change
- AmdExeAddrMapPtr[i].ExeCacheSize = RemainingExecutionCacheSize;
- RemainingExecutionCacheSize = 0;
- AgesaStatus = AGESA_WARNING;
- PutEventLog (AgesaStatus,
- (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR + AGESA_CACHE_SIZE_REDUCED),
- i, AmdExeAddrMapPtr[i].ExeCacheStartAddr, AmdExeAddrMapPtr[i].ExeCacheSize, 0, StdHeader);
- } else {
- IDS_HDT_CONSOLE (CPU_TRACE, " Exe cache allocated: Base 0x%x, Size 0x%x\n", AmdExeAddrMapPtr[i].ExeCacheStartAddr, AmdExeAddrMapPtr[i].ExeCacheSize);
- RemainingExecutionCacheSize = RemainingExecutionCacheSize - AmdExeAddrMapPtr[i].ExeCacheSize;
- }
-
- RequestStartAddr = AmdExeAddrMapPtr[i].ExeCacheStartAddr;
- RequestSize = AmdExeAddrMapPtr[i].ExeCacheSize;
-
- if (RequestStartAddr < 0x100000) {
- // Region starts below 1MB - Fixed MTTR region,
- // turn on modification bit: MtrrFixDramModEn
- LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
- MsrData |= 0x80000;
- LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
-
-
- // Check for 1M boundary crossing
- if ((RequestStartAddr + RequestSize) > 0x100000) {
- // Request spans the 1M boundary, reduce the size & report the change
- RequestSize = 0x100000 - RequestStartAddr;
- AmdExeAddrMapPtr[i].ExeCacheSize = RequestSize;
- AgesaStatus = AGESA_WARNING;
- PutEventLog (AgesaStatus,
- (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR + AGESA_CACHE_REGIONS_ACROSS_1MB),
- i, RequestStartAddr, RequestSize, 0, StdHeader);
- }
-
- // Find start MTTR and end MTTR for the requested region
- StartFixMtrr = AMD_MTRR_FIX4K_BASE + ((RequestStartAddr >> 15) & 0x7);
- EndFixMtrr = AMD_MTRR_FIX4K_BASE + ((((RequestStartAddr + RequestSize) - 1) >> 15) & 0x7);
-
- //
- //Check Mtrr before we use it,
- // if Mtrr has been used, we need to recover the previously allocated size.
- // (only work in blocks of 32K size - no splitting of ways)
- for (CurrentMtrr = StartFixMtrr; CurrentMtrr <= EndFixMtrr; CurrentMtrr++) {
- LibAmdMsrRead (CurrentMtrr, &MsrData, StdHeader);
- if (MsrData != 0) {
- // MTRR previously allocated, recover size
- RemainingExecutionCacheSize = RemainingExecutionCacheSize + 0x8000;
- } else {
- // Allocate this MTRR
- MsrData = WP_IO;
- LibAmdMsrWrite (CurrentMtrr, &MsrData, StdHeader);
- }
- }
- // Turn off modification bit: MtrrFixDramModEn
- LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
- MsrData &= 0xFFFFFFFFFFF7FFFFULL;
- LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
-
-
- } else {
- // Region above 1MB - Variable MTTR region
- // Need to check both VarMTRRs for each requested region for match or overlap
- //
-
- // Check for 4G boundary crossing (using size-1 to keep in 32bit math range)
- if ((0xFFFFFFFFUL - RequestStartAddr) < (RequestSize - 1)) {
- RequestSize = (0xFFFFFFFFUL - RequestStartAddr) + 1;
- AgesaStatus = AGESA_WARNING;
- AmdExeAddrMapPtr[i].ExeCacheSize = RequestSize;
- PutEventLog (AgesaStatus,
- (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR + AGESA_CACHE_REGIONS_ACROSS_4GB),
- i, RequestStartAddr, RequestSize, 0, StdHeader);
- }
- LibAmdMsrRead (AMD_MTRR_VARIABLE_BASE6, &MsrData, StdHeader);
- MtrrV6.ExeCacheStartAddr = ((UINT32) MsrData) & 0xFFFFF000UL;
- LibAmdMsrRead (AMD_MTRR_VARIABLE_BASE6 + 1, &MsrData, StdHeader);
- MtrrV6.ExeCacheSize = (0xFFFFFFFFUL - (((UINT32) MsrData) & 0xFFFFF000UL)) + 1;
-
- LibAmdMsrRead (AMD_MTRR_VARIABLE_BASE7, &MsrData, StdHeader);
- MtrrV7.ExeCacheStartAddr = ((UINT32) MsrData) & 0xFFFFF000UL;
- LibAmdMsrRead (AMD_MTRR_VARIABLE_BASE7 + 1, &MsrData, StdHeader);
- MtrrV7.ExeCacheSize = (0xFFFFFFFFUL - (((UINT32) MsrData) & 0xFFFFF000UL)) + 1;
-
- CompareRegions (AmdExeAddrMapPtr[i], MtrrV6, &Result, StdHeader);
- if (Result.OverlapType == EmptySet) {
- // MTRR6 is empty. Allocate request into MTRR6.
- // Note: since all merges are moved down to MTRR6, if MTRR6 is empty so should MTRR7 also be empty
- MtrrV6.ExeCacheStartAddr = AmdExeAddrMapPtr[i].ExeCacheStartAddr;
- MtrrV6.ExeCacheSize = AmdExeAddrMapPtr[i].ExeCacheSize;
- } else if ((Result.OverlapType == Disjoint) ||
- (Result.OverlapType == NotCombinable)) {
- // MTRR6 is in use, and request does not overlap with MTRR6, check MTRR7
- CompareRegions (AmdExeAddrMapPtr[i], MtrrV7, &Result, StdHeader);
- if (Result.OverlapType == EmptySet) {
- // MTRR7 is empty. Allocate request into MTRR7.
- MtrrV7.ExeCacheStartAddr = AmdExeAddrMapPtr[i].ExeCacheStartAddr;
- MtrrV7.ExeCacheSize = AmdExeAddrMapPtr[i].ExeCacheSize;
- } else if ((Result.OverlapType == Disjoint) ||
- (Result.OverlapType == NotCombinable)) {
- // MTRR7 is also in use and request does not overlap - error: 3rd region above 1M
- AgesaStatus = AGESA_ERROR;
- PutEventLog (AgesaStatus,
- (CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR + AGESA_THREE_CACHE_REGIONS_ABOVE_1MB),
- i, AmdExeAddrMapPtr[i].ExeCacheStartAddr, AmdExeAddrMapPtr[i].ExeCacheSize, 0, StdHeader);
- break;
- } else {
- // Merge request with MTRR7
- MtrrV7.ExeCacheStartAddr = Result.MergedStartAddr;
- MtrrV7.ExeCacheSize = Result.MergedSize;
- RemainingExecutionCacheSize += Result.OverlapAmount;
- }
- } else {
- // Request overlaps with MTRR6, Merge request with MTRR6
- MtrrV6.ExeCacheStartAddr = Result.MergedStartAddr;
- MtrrV6.ExeCacheSize = Result.MergedSize;
- RemainingExecutionCacheSize += Result.OverlapAmount;
- CompareRegions (MtrrV6, MtrrV7, &Result, StdHeader);
- if ((Result.OverlapType != Disjoint) &&
- (Result.OverlapType != EmptySet) &&
- (Result.OverlapType != NotCombinable)) {
- // MTRR6 and MTRR7 now overlap, merge them into MTRR6
- MtrrV6.ExeCacheStartAddr = Result.MergedStartAddr;
- MtrrV6.ExeCacheSize = Result.MergedSize;
- MtrrV7.ExeCacheStartAddr = 0;
- MtrrV7.ExeCacheSize = 0;
- RemainingExecutionCacheSize += Result.OverlapAmount;
- }
- }
-
- // Set the VarMTRRs. Size first, then base; this allows for expanding the region safely.
- if (MtrrV6.ExeCacheSize != 0) {
- MsrData = (UINT64) ( 0xFFFFFFFF00000000ULL | ((0xFFFFFFFFUL - (MtrrV6.ExeCacheSize - 1)) | 0x0800UL));
- MsrData &= CacheInfoPtr->VariableMtrrMask;
- SecondMsrData = (UINT64) ( MtrrV6.ExeCacheStartAddr | (WP_IO & 0xFULL));
- } else {
- MsrData = 0;
- SecondMsrData = 0;
- }
- LibAmdMsrWrite ((AMD_MTRR_VARIABLE_BASE6 + 1), &MsrData, StdHeader);
- LibAmdMsrWrite (AMD_MTRR_VARIABLE_BASE6, &SecondMsrData, StdHeader);
-
- if (MtrrV7.ExeCacheSize != 0) {
- MsrData = (UINT64) ( 0xFFFFFFFF00000000ULL | ((0xFFFFFFFFUL - (MtrrV7.ExeCacheSize - 1)) | 0x0800UL));
- MsrData &= CacheInfoPtr->VariableMtrrMask;
- SecondMsrData = (UINT64) ( MtrrV7.ExeCacheStartAddr | (WP_IO & 0xFULL));
- } else {
- MsrData = 0;
- SecondMsrData = 0;
- }
- LibAmdMsrWrite ((AMD_MTRR_VARIABLE_BASE7 + 1), &MsrData, StdHeader);
- LibAmdMsrWrite (AMD_MTRR_VARIABLE_BASE7, &SecondMsrData, StdHeader);
- } // endif of MTRR region check
- } // end of requests For loop
-
- return AgesaStatus;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * This function calculates available L2 cache space for ROM execution.
- *
- * @param[in] AmdGetExeSizeParams Pointer to the start of AmdGetExeSizeParamsPtr structure
- *
- * @retval AGESA_SUCCESS No error
- * @retval AGESA_ALERT No cache available for execution cache.
- *
- */
-AGESA_STATUS
-AmdGetAvailableExeCacheSize (
- IN OUT AMD_GET_EXE_SIZE_PARAMS *AmdGetExeSizeParams
- )
-{
- UINT8 WayUsedForCar;
- UINT8 L2Assoc;
- UINT32 L2Size;
- UINT32 L2WaySize;
- UINT32 CurrentCoreNum;
- UINT8 L2Ways;
- UINT8 Ignored;
- UINT32 DieNumber;
- UINT32 TotalCores;
- CPUID_DATA CpuIdDataStruct;
- CACHE_INFO *CacheInfoPtr;
- AP_MAIL_INFO ApMailboxInfo;
- AGESA_STATUS IgnoredStatus;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
-
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, &AmdGetExeSizeParams->StdHeader);
- FamilySpecificServices->GetCacheInfo (FamilySpecificServices, &CacheInfoPtr, &Ignored, &AmdGetExeSizeParams->StdHeader);
- // CAR_EXE mode is either "Limited by L2 size" or "Infinite Execution space"
- ASSERT (CacheInfoPtr->CarExeType < MaxCarExeMode);
- if (CacheInfoPtr->CarExeType == InfiniteExe) {
- AmdGetExeSizeParams->AvailableExeCacheSize = SIZE_INFINITE_EXE_CACHE;
- return AGESA_SUCCESS;
- }
-
- // EXE cache size is limited by size of the L2, minus previous allocations for stack, heap, etc.
- // Check for L2 cache size and way size
- LibAmdCpuidRead (AMD_CPUID_L2L3Cache_L2TLB, &CpuIdDataStruct, &AmdGetExeSizeParams->StdHeader);
- L2Assoc = (UINT8) ((CpuIdDataStruct.ECX_Reg >> 12) & 0x0F);
-
- // get L2Ways from L2 Association to Way translation table
- L2Ways = L2AssocToL2WayTranslationTable[L2Assoc];
- ASSERT (L2Ways != 0xFF);
-
- // get L2Size
- L2Size = 1024 * ((CpuIdDataStruct.ECX_Reg >> 16) & 0xFFFF);
-
- // get each L2WaySize
- L2WaySize = L2Size / L2Ways;
-
- // Determine the size for execution cache
- if (IsBsp (&AmdGetExeSizeParams->StdHeader, &IgnoredStatus)) {
- // BSC (Boot Strap Core)
- WayUsedForCar = Ceiling (CacheInfoPtr->BspStackSize, L2WaySize) +
- Ceiling (CacheInfoPtr->MemTrainingBufferSize, L2WaySize) +
- Ceiling (AMD_HEAP_SIZE_PER_CORE , L2WaySize) +
- Ceiling (CacheInfoPtr->SharedMemSize, L2WaySize);
- } else {
- // AP (Application Processor)
- GetCurrentCore (&CurrentCoreNum, &AmdGetExeSizeParams->StdHeader);
-
- GetApMailbox (&ApMailboxInfo.Info, &AmdGetExeSizeParams->StdHeader);
- DieNumber = (1 << ApMailboxInfo.Fields.ModuleType);
- GetActiveCoresInCurrentSocket (&TotalCores, &AmdGetExeSizeParams->StdHeader);
- ASSERT ((TotalCores % DieNumber) == 0);
- if ((CurrentCoreNum % (TotalCores / DieNumber)) == 0) {
- WayUsedForCar = Ceiling (CacheInfoPtr->Core0StackSize , L2WaySize) +
- Ceiling (CacheInfoPtr->MemTrainingBufferSize, L2WaySize) +
- Ceiling (AMD_HEAP_SIZE_PER_CORE , L2WaySize) +
- Ceiling (CacheInfoPtr->SharedMemSize, L2WaySize);
- } else {
- WayUsedForCar = Ceiling (CacheInfoPtr->Core1StackSize , L2WaySize) +
- Ceiling (AMD_HEAP_SIZE_PER_CORE , L2WaySize) +
- Ceiling (CacheInfoPtr->SharedMemSize, L2WaySize);
- }
- }
-
- ASSERT (WayUsedForCar < L2Ways);
-
- if (WayUsedForCar < L2Ways) {
- AmdGetExeSizeParams->AvailableExeCacheSize = L2WaySize * (L2Ways - WayUsedForCar);
- return AGESA_SUCCESS;
- } else {
- AmdGetExeSizeParams->AvailableExeCacheSize = 0;
- return AGESA_ALERT;
- }
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * This function rounds a quotient up if the remainder is not zero.
- *
- * @param[in] Divisor The divisor
- * @param[in] Dividend The dividend
- *
- * @retval Value Rounded quotient
- *
- */
-UINT8
-STATIC
-Ceiling (
- IN UINT32 Divisor,
- IN UINT32 Dividend
- )
-{
- if ((Divisor % Dividend) == 0) {
- return (UINT8) (Divisor / Dividend);
- } else {
- return (UINT8) ((Divisor / Dividend) + 1);
- }
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * This function calculates the amount of cache that has already been allocated on the
- * executing core.
- *
- * @param[in] StdHeader Handle to config for library and services
- *
- * @returns Allocated size in bytes
- *
- */
-UINT32
-STATIC
-CalculateOccupiedExeCache (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 OccupExeCacheSize;
- UINT64 MsrData;
- UINT8 i;
-
- MsrData = 0;
- OccupExeCacheSize = 0;
-
- //
- //Calculate Variable MTRR base 6~7
- //
- for (i = 0; i < 2; i++) {
- LibAmdMsrRead ((AMD_MTRR_VARIABLE_BASE6 + (2*i)), &MsrData, StdHeader);
- if (MsrData != 0) {
- LibAmdMsrRead ((AMD_MTRR_VARIABLE_BASE6 + (2*i + 1)), &MsrData, StdHeader);
- OccupExeCacheSize = OccupExeCacheSize + ((~((MsrData & (0xFFFF8000)) - 1))&0xFFFF8000);
- }
- }
-
- //
- //Calculate Fixed MTRR base D0000~F8000
- //
- for (i = 0; i < 6; i++) {
- LibAmdMsrRead ((AMD_MTRR_FIX4K_BASE + 2 + i), &MsrData, StdHeader);
- if (MsrData!= 0) {
- OccupExeCacheSize = OccupExeCacheSize + 0x8000;
- }
- }
-
- return (UINT32)OccupExeCacheSize;
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * This function compares two memory regions for overlap and returns the combined
- * Base,Size to describe the new combined region.
- *
- * There are 13 cases for how two regions may overlap: key: [] region A, ** region B
- * 1- [ ] *** 9- *** [ ] disjoint regions
- * 2- [ ]*** 10- ***[ ] adjacent regions
- * 3- [ ***] 11- **[**] common ending
- * 4- [ *]** 12- *[** ] extending
- * 5- [ ** ] 13- *[*]* contained
- * 6- [*** ] common start, contained
- * 7- [***] identity
- * 8- [**]** common start, extending
- * 0- one of the regions is empty (has base=0)
- *
- * @param[in] ARegion pointer to the base,size pair that describes region A
- * @param[in] BRegion pointer to the base,size pair that describes region B
- * @param[in,out] CRegion pointer to the base,size pair that describes region C This struct also has the
- * overlap type and the amount of overlap between the regions.
- * @param[in] StdHeader Handle to config for library and services
- *
- * @returns void, nothing
- */
-
-VOID
-STATIC
-CompareRegions (
- IN EXECUTION_CACHE_REGION ARegion,
- IN EXECUTION_CACHE_REGION BRegion,
- IN OUT MERGED_CACHE_REGION *CRegion,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- // Use Int64 to handle regions ending at or above the 4G boundary.
- UINT64 EndOfA;
- UINT64 EndOfB;
-
-
- if ((BRegion.ExeCacheStartAddr == 0) ||
- (ARegion.ExeCacheStartAddr == 0)) {
- CRegion->MergedStartAddr =
- CRegion->MergedSize =
- CRegion->OverlapAmount = 0;
- CRegion->OverlapType = EmptySet;
- return;
- }
- if (BRegion.ExeCacheStartAddr < ARegion.ExeCacheStartAddr) {
- //swap regions A & B. this collapses types 9-13 onto 1-5 and reduces the number of tests
- CRegion->MergedStartAddr = ARegion.ExeCacheStartAddr;
- CRegion->MergedSize = ARegion.ExeCacheSize;
- ARegion = BRegion;
- BRegion.ExeCacheStartAddr = CRegion->MergedStartAddr;
- BRegion.ExeCacheSize = CRegion->MergedSize;
- }
- CRegion->MergedStartAddr =
- CRegion->MergedSize =
- CRegion->OverlapType =
- CRegion->OverlapAmount = 0;
-
- if (ARegion.ExeCacheStartAddr == BRegion.ExeCacheStartAddr) {
- // Common start, cases 6,7, or 8
- if (ARegion.ExeCacheSize == BRegion.ExeCacheSize) {
- // case 7, identity. Need to recover the overlap size
- CRegion->MergedStartAddr = ARegion.ExeCacheStartAddr;
- CRegion->MergedSize = ARegion.ExeCacheSize;
- CRegion->OverlapAmount = ARegion.ExeCacheSize;
- CRegion->OverlapType = Identity;
- } else if (ARegion.ExeCacheSize < BRegion.ExeCacheSize) {
- // case 8, common start extending
- CRegion->MergedStartAddr = ARegion.ExeCacheStartAddr;
- CRegion->MergedSize = BRegion.ExeCacheSize;
- CRegion->OverlapType = CommonStartExtending;
- CRegion->OverlapAmount = ARegion.ExeCacheSize;
- } else {
- // case 6, common start contained
- CRegion->MergedStartAddr = ARegion.ExeCacheStartAddr;
- CRegion->MergedSize = ARegion.ExeCacheSize;
- CRegion->OverlapType = CommonStartContained;
- CRegion->OverlapAmount = BRegion.ExeCacheSize;
- }
- } else {
- // A_Base is less than B_Base. check for cases 1-5
- EndOfA = ((UINT64) ARegion.ExeCacheStartAddr) + ((UINT64) ARegion.ExeCacheSize);
-
- if (EndOfA < ((UINT64) BRegion.ExeCacheStartAddr)) {
- // case 1, disjoint
- CRegion->MergedStartAddr =
- CRegion->MergedSize =
- CRegion->OverlapAmount = 0;
- CRegion->OverlapType = Disjoint;
-
- } else if (EndOfA == ((UINT64) BRegion.ExeCacheStartAddr)) {
- // case 2, adjacent
- CRegion->OverlapType = Adjacent;
- CRegion->MergedStartAddr = ARegion.ExeCacheStartAddr;
- CRegion->MergedSize = ARegion.ExeCacheSize + BRegion.ExeCacheSize;
- CRegion->OverlapAmount = 0;
- } else {
- // EndOfA is > B_Base. check for cases 3,4,5
- EndOfB = ((UINT64) BRegion.ExeCacheStartAddr) + ((UINT64) BRegion.ExeCacheSize);
-
- if ( EndOfA < EndOfB) {
- // case 4, extending
- CRegion->OverlapType = Extending;
- CRegion->MergedStartAddr = ARegion.ExeCacheStartAddr;
- CRegion->MergedSize = (UINT32) (EndOfB - ((UINT64) ARegion.ExeCacheStartAddr));
- CRegion->OverlapAmount = (UINT32) (EndOfA - ((UINT64) BRegion.ExeCacheStartAddr));
- } else {
- // case 3, same end; or case 5, contained
- CRegion->OverlapType = Contained;
- CRegion->MergedStartAddr = ARegion.ExeCacheStartAddr;
- CRegion->MergedSize = ARegion.ExeCacheSize;
- CRegion->OverlapAmount = BRegion.ExeCacheSize;
- }
- }
- } // endif
- // Once we have combined the regions, they must still obey the MTRR size and boundary rules
- if ( CRegion->OverlapType != Disjoint ) {
- if ((!(IsPowerOfTwo (CRegion->MergedSize))) ||
- ((CRegion->MergedStartAddr % CRegion->MergedSize) != 0) ) {
- CRegion->OverlapType = NotCombinable;
- }
- }
-
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * This local function tests the parameter for being an even power of two
- *
- * @param[in] TestNumber Number to check
- *
- * @retval TRUE - TestNumber is a power of two,
- * @retval FALSE - TestNumber is not a power of two
- *
- */
-BOOLEAN
-STATIC
-IsPowerOfTwo (
- IN UINT32 TestNumber
- )
-{
- UINT32 PowerTwo;
-
- ASSERT (TestNumber >= 0x8000UL);
- PowerTwo = 0x8000UL; // Start at 32K
- while ( TestNumber > PowerTwo ) {
- PowerTwo = PowerTwo * 2;
- }
- return (((TestNumber % PowerTwo) == 0) ? TRUE: FALSE);
-}
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuCacheInit.h b/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuCacheInit.h
deleted file mode 100644
index ef8c812..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuCacheInit.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU Execution Cache Allocation functions.
- *
- * Contains code for doing Execution Cache Allocation for ROM space
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPU_CACHE_INIT_H_
-#define _CPU_CACHE_INIT_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-#define AMD_MTRR_FIX4K_BASE 0x268
-#define AMD_MTRR_VARIABLE_BASE6 0x20C
-#define AMD_MTRR_VARIABLE_BASE7 0x20E
-
-#define WP_IO 0x0505050505050505
-
-#define AGESA_CACHE_SIZE_REDUCED 1
-#define AGESA_CACHE_REGIONS_ACROSS_1MB 2
-#define AGESA_CACHE_REGIONS_ACROSS_4GB 3
-#define AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY 4
-#define AGESA_CACHE_START_ADDRESS_LESS_D0000 5
-#define AGESA_THREE_CACHE_REGIONS_ABOVE_1MB 6
-#define AGESA_DEALLOCATE_CACHE_REGIONS 7
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-/// Cache-As-Ram Executable region allocation modes
-typedef enum {
- LimitedByL2Size, ///< Execution space must be allocated from L2
- InfiniteExe, ///< Family can support unlimited Execution space
- MaxCarExeMode ///< Used as limit or bounds check
-} CAR_EXE_MODE;
-
-/// Cache Information
-typedef struct {
- IN UINT32 BspStackSize; ///< Stack size of BSP
- IN UINT32 Core0StackSize; ///< Stack size of primary cores
- IN UINT32 Core1StackSize; ///< Stack size of all non primary cores
- IN UINT32 MemTrainingBufferSize; ///< Memory training buffer size
- IN UINT32 SharedMemSize; ///< Shared memory size
- IN UINT64 VariableMtrrMask; ///< Mask to apply before variable MTRR writes
- IN UINT64 VariableMtrrHeapMask; ///< Mask to apply before variable MTRR writes for use in heap init.
- IN UINT64 HeapBaseMask; ///< Mask used for the heap MTRR settings
- IN CAR_EXE_MODE CarExeType; ///< Indicates which algorithm to use when allocating EXE space
-} CACHE_INFO;
-
-/// Merged memory region overlap type
-typedef enum {
- EmptySet, ///< One of the regions is zero length
- Disjoint, ///< The two regions do not touch
- Adjacent, ///< one region is next to the other, no gap
- CommonEnd, ///< regions overlap with a common end point
- Extending, ///< the 2nd region is extending the size of the 1st
- Contained, ///< the 2nd region is wholely contained inside the 1st
- CommonStartContained, ///< the 2nd region is contained in the 1st with a common start
- Identity, ///< the two regions are the same
- CommonStartExtending, ///< the 2nd region has same start as 1st, but is larger size
- NotCombinable ///< the combined regions do not follow the cache block rules
-} OVERLAP_TYPE;
-
-/// Result of merging two memory regions for cache coverage
-typedef struct {
- IN OUT UINT32 MergedStartAddr; ///< Start address of the merged regions
- IN OUT UINT32 MergedSize; ///< Size of the merged regions
- OUT UINT32 OverlapAmount; ///< the size of the overlapping section
- OUT OVERLAP_TYPE OverlapType; ///< indicates how the two regions overlap
-} MERGED_CACHE_REGION;
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-AGESA_STATUS
-AllocateExecutionCache (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr
- );
-
-#endif // _CPU_CACHE_INIT_H_
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuCoreLeveling.c b/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuCoreLeveling.c
deleted file mode 100644
index c6d902c..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuCoreLeveling.c
+++ /dev/null
@@ -1,353 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU Core Leveling Function.
- *
- * Contains code to Level the number of core in a multi-socket system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "AMD.h"
-#include "amdlib.h"
-#include "Topology.h"
-#include "cpuRegisters.h"
-#include "GeneralServices.h"
-#include "cpuServices.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuFeatures.h"
-#include "cpuEarlyInit.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-#define FILECODE PROC_CPU_FEATURE_CPUCORELEVELING_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-extern CPU_FAMILY_SUPPORT_TABLE CoreLevelingFamilyServiceTable;
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P U B L I C F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Should core leveling be enabled
- *
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval TRUE core leveling is supported.
- * @retval FALSE core leveling cannot be enabled.
- *
- */
-BOOLEAN
-STATIC
-IsCoreLevelingEnabled (
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- CORE_LEVELING_TYPE CoreLevelMode;
-
- CoreLevelMode = (CORE_LEVELING_TYPE) PlatformConfig->CoreLevelingMode;
- if (CoreLevelMode != CORE_LEVEL_NONE) {
- return (TRUE);
- } else {
- return (FALSE);
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Performs core leveling for the system.
- *
- * This function implements the AMD_CPU_EARLY_PARAMS.CoreLevelingMode parameter.
- * The possible modes are:
- * -0 CORE_LEVEL_LOWEST Level to lowest common denominator
- * -1 CORE_LEVEL_TWO Level to 2 cores
- * -2 CORE_LEVEL_POWER_OF_TWO Level to 1,2,4 or 8
- * -3 CORE_LEVEL_NONE Do no leveling
- * -4 CORE_LEVEL_COMPUTE_UNIT Level cores to one core per compute unit
- *
- * @param[in] EntryPoint Timepoint designator.
- * @param[in] PlatformConfig Contains the leveling mode parameter
- * @param[in] StdHeader Config handle for library and services
- *
- * @return The most severe status of any family specific service.
- *
- */
-AGESA_STATUS
-CoreLevelingAtEarly (
- IN UINT64 EntryPoint,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 CoreNumPerComputeUnit;
- UINT32 MinNumOfComputeUnit;
- UINT32 EnabledComputeUnit;
- UINT32 Socket;
- UINT32 Module;
- UINT32 NumberOfSockets;
- UINT32 NumberOfModules;
- UINT32 MinCoreCountOnNode;
- UINT32 MaxCoreCountOnNode;
- UINT32 LowCore;
- UINT32 HighCore;
- UINT32 LeveledCores;
- UINT32 RequestedCores;
- UINT32 TotalEnabledCoresOnNode;
- BOOLEAN RegUpdated;
- AP_MAIL_INFO ApMailboxInfo;
- CORE_LEVELING_TYPE CoreLevelMode;
- CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices;
- WARM_RESET_REQUEST Request;
-
- MaxCoreCountOnNode = 0;
- MinCoreCountOnNode = 0xFFFFFFFF;
- LeveledCores = 0;
- CoreNumPerComputeUnit = 1;
- MinNumOfComputeUnit = 0xFF;
-
- ASSERT (PlatformConfig->CoreLevelingMode < CoreLevelModeMax);
-
- // Get OEM IO core level mode
- CoreLevelMode = (CORE_LEVELING_TYPE) PlatformConfig->CoreLevelingMode;
-
- // Get socket count
- NumberOfSockets = GetPlatformNumberOfSockets ();
- GetApMailbox (&ApMailboxInfo.Info, StdHeader);
- NumberOfModules = ApMailboxInfo.Fields.ModuleType + 1;
-
- // Collect cpu core info
- for (Socket = 0; Socket < NumberOfSockets; Socket++) {
- if (IsProcessorPresent (Socket, StdHeader)) {
- for (Module = 0; Module < NumberOfModules; Module++) {
- if (GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader)) {
- // Get the highest and lowest core count in all nodes
- TotalEnabledCoresOnNode = HighCore - LowCore + 1;
- if (TotalEnabledCoresOnNode < MinCoreCountOnNode) {
- MinCoreCountOnNode = TotalEnabledCoresOnNode;
- }
- if (TotalEnabledCoresOnNode > MaxCoreCountOnNode) {
- MaxCoreCountOnNode = TotalEnabledCoresOnNode;
- }
- EnabledComputeUnit = TotalEnabledCoresOnNode;
- switch (GetComputeUnitMapping (StdHeader)) {
- case AllCoresMapping:
- // All cores are in their own compute unit.
- break;
- case EvenCoresMapping:
- // Cores are paired in compute units.
- CoreNumPerComputeUnit = 2;
- EnabledComputeUnit = (TotalEnabledCoresOnNode / 2);
- break;
- default:
- ASSERT (FALSE);
- }
- // Get minimum of compute unit. This will either be the minimum number of cores (AllCoresMapping),
- // or less (EvenCoresMapping).
- if (EnabledComputeUnit < MinNumOfComputeUnit) {
- MinNumOfComputeUnit = EnabledComputeUnit;
- }
- }
- }
- }
- }
-
- // Get LeveledCores
- switch (CoreLevelMode) {
- case CORE_LEVEL_LOWEST:
- if (MinCoreCountOnNode == MaxCoreCountOnNode) {
- return (AGESA_SUCCESS);
- }
- LeveledCores = (MinCoreCountOnNode / CoreNumPerComputeUnit) * CoreNumPerComputeUnit;
- break;
- case CORE_LEVEL_TWO:
- LeveledCores = 2 / NumberOfModules;
- if (LeveledCores != 0) {
- LeveledCores = (LeveledCores <= MinCoreCountOnNode) ? LeveledCores : MinCoreCountOnNode;
- } else {
- return (AGESA_WARNING);
- }
- if ((LeveledCores * NumberOfModules) != 2) {
- PutEventLog (
- AGESA_WARNING,
- CPU_WARNING_ADJUSTED_LEVELING_MODE,
- 2, (LeveledCores * NumberOfModules), 0, 0, StdHeader
- );
- }
- break;
- case CORE_LEVEL_POWER_OF_TWO:
- // Level to power of 2 (1, 2, 4, 8...)
- LeveledCores = 1;
- while (MinCoreCountOnNode >= (LeveledCores * 2)) {
- LeveledCores = LeveledCores * 2;
- }
- break;
- case CORE_LEVEL_COMPUTE_UNIT:
- // Level cores to one core per compute unit, with additional reduction to level
- // all processors to match the processor with the minimum number of cores.
- if (CoreNumPerComputeUnit == 1) {
- // If there is one core per compute unit, this is the same as CORE_LEVEL_LOWEST.
- if (MinCoreCountOnNode == MaxCoreCountOnNode) {
- return (AGESA_SUCCESS);
- }
- LeveledCores = MinCoreCountOnNode;
- } else {
- // If there are more than one core per compute unit, level to the number of compute units.
- LeveledCores = MinNumOfComputeUnit;
- }
- break;
- case CORE_LEVEL_ONE:
- LeveledCores = 1;
- if (NumberOfModules > 1) {
- PutEventLog (
- AGESA_WARNING,
- CPU_WARNING_ADJUSTED_LEVELING_MODE,
- 1, NumberOfModules, 0, 0, StdHeader
- );
- }
- break;
- case CORE_LEVEL_THREE:
- case CORE_LEVEL_FOUR:
- case CORE_LEVEL_FIVE:
- case CORE_LEVEL_SIX:
- case CORE_LEVEL_SEVEN:
- case CORE_LEVEL_EIGHT:
- case CORE_LEVEL_NINE:
- case CORE_LEVEL_TEN:
- case CORE_LEVEL_ELEVEN:
- case CORE_LEVEL_TWELVE:
- case CORE_LEVEL_THIRTEEN:
- case CORE_LEVEL_FOURTEEN:
- case CORE_LEVEL_FIFTEEN:
- // MCM processors can not have an odd number of cores. For an odd CORE_LEVEL_N, MCM processors will be
- // leveled as though CORE_LEVEL_N+1 was chosen.
- // Processors with compute units disable all cores in an entire compute unit at a time, or on an MCM processor,
- // two compute units at a time. For example, on an SCM processor with two cores per compute unit, the effective
- // explicit levels are CORE_LEVEL_ONE, CORE_LEVEL_TWO, CORE_LEVEL_FOUR, CORE_LEVEL_SIX, and
- // CORE_LEVEL_EIGHT. The same example for an MCM processor with two cores per compute unit has effective
- // explicit levels of CORE_LEVEL_TWO, CORE_LEVEL_FOUR, CORE_LEVEL_EIGHT, and CORE_LEVEL_TWELVE.
- RequestedCores = CoreLevelMode - CORE_LEVEL_THREE + 3;
- LeveledCores = (RequestedCores + NumberOfModules - 1) / NumberOfModules;
- LeveledCores = (LeveledCores / CoreNumPerComputeUnit) * CoreNumPerComputeUnit;
- LeveledCores = (LeveledCores <= MinCoreCountOnNode) ? LeveledCores : MinCoreCountOnNode;
- if (LeveledCores != 1) {
- LeveledCores = (LeveledCores / CoreNumPerComputeUnit) * CoreNumPerComputeUnit;
- }
- if ((LeveledCores * NumberOfModules * CoreNumPerComputeUnit) != RequestedCores) {
- PutEventLog (
- AGESA_WARNING,
- CPU_WARNING_ADJUSTED_LEVELING_MODE,
- RequestedCores, (LeveledCores * NumberOfModules * CoreNumPerComputeUnit), 0, 0, StdHeader
- );
- }
- break;
- default:
- ASSERT (FALSE);
- }
-
- // Set down core register
- for (Socket = 0; Socket < NumberOfSockets; Socket++) {
- if (IsProcessorPresent (Socket, StdHeader)) {
- GetFeatureServicesOfSocket (&CoreLevelingFamilyServiceTable, Socket, &FamilySpecificServices, StdHeader);
- if (FamilySpecificServices != NULL) {
- for (Module = 0; Module < NumberOfModules; Module++) {
- RegUpdated = FamilySpecificServices->SetDownCoreRegister (FamilySpecificServices, &Socket, &Module, &LeveledCores, CoreLevelMode, StdHeader);
- // If the down core register is updated, trigger a warm reset.
- if (RegUpdated) {
- GetWarmResetFlag (StdHeader, &Request);
- Request.RequestBit = TRUE;
- Request.StateBits = Request.PostStage - 1;
- SetWarmResetFlag (StdHeader, &Request);
- }
- }
- }
- }
- }
-
- return (AGESA_SUCCESS);
-}
-
-
-CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling =
-{
- CoreLeveling,
- (CPU_FEAT_AFTER_PM_INIT),
- IsCoreLevelingEnabled,
- CoreLevelingAtEarly
-};
-
-/*----------------------------------------------------------------------------------------
- * L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuCpb.c b/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuCpb.c
deleted file mode 100644
index 50264f0..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuCpb.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD AGESA CPU Core performance boost feature support code.
- *
- * Contains code that declares the AGESA CPU CPB related APIs
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/Feature
- * @e \$Revision: 35636 $ @e \$Date: 2010-07-28 09:24:55 +0800 (Wed, 28 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuFeatures.h"
-#include "cpuCpb.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FEATURE_CPUCPB_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-extern CPU_FAMILY_SUPPORT_TABLE CpbFamilyServiceTable;
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Should CPB be enabled
- *
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval TRUE CPB is supported.
- * @retval FALSE CPB cannot be enabled.
- *
- */
-BOOLEAN
-STATIC
-IsCpbFeatureEnabled (
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Socket;
- BOOLEAN IsEnabled;
- CPB_FAMILY_SERVICES *FamilyServices;
-
- IsEnabled = FALSE;
-
- ASSERT (PlatformConfig->CpbMode < MaxCpbMode);
-
- if (PlatformConfig->CpbMode == CpbModeAuto) {
- for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
- if (IsProcessorPresent (Socket, StdHeader)) {
- GetFeatureServicesOfSocket (&CpbFamilyServiceTable, Socket, &FamilyServices, StdHeader);
- if (FamilyServices != NULL) {
- if (FamilyServices->IsCpbSupported (FamilyServices, PlatformConfig, Socket, StdHeader)) {
- IsEnabled = TRUE;
- break;
- }
- }
- }
- }
- }
- return IsEnabled;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Enable core performance boost
- *
- * @param[in] EntryPoint Timepoint designator.
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval AGESA_SUCCESS Always succeeds.
- *
- */
-AGESA_STATUS
-STATIC
-InitializeCpbFeature (
- IN UINT64 EntryPoint,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Socket;
- AGESA_STATUS AgesaStatus;
- AGESA_STATUS CalledStatus;
- CPB_FAMILY_SERVICES *FamilyServices;
-
- AgesaStatus = AGESA_SUCCESS;
- CalledStatus = AGESA_SUCCESS;
-
- IDS_HDT_CONSOLE (CPU_TRACE, " Boost is enabled\n");
-
- for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
- if (IsProcessorPresent (Socket, StdHeader)) {
- GetFeatureServicesOfSocket (&CpbFamilyServiceTable, Socket, &FamilyServices, StdHeader);
- if (FamilyServices != NULL) {
- if (FamilyServices->IsCpbSupported (FamilyServices, PlatformConfig, Socket, StdHeader)) {
- CalledStatus = FamilyServices->EnableCpbOnSocket (FamilyServices, PlatformConfig, EntryPoint, Socket, StdHeader);
- if (CalledStatus > AgesaStatus) {
- AgesaStatus = CalledStatus;
- }
- }
- }
- }
- }
-
- return AgesaStatus;
-}
-
-
-CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb =
-{
- CoreBoost,
- (CPU_FEAT_BEFORE_PM_INIT | CPU_FEAT_INIT_LATE_END),
- IsCpbFeatureEnabled,
- InitializeCpbFeature
-};
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuCpb.h b/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuCpb.h
deleted file mode 100644
index 9292e00..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuCpb.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD AGESA CPU Core Performance Boost Functions declarations.
- *
- * Contains code that declares the AGESA CPU CPB related APIs
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/Feature
- * @e \$Revision: 36567 $ @e \$Date: 2010-08-21 02:35:15 +0800 (Sat, 21 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPU_CPB_H_
-#define _CPU_CPB_H_
-
-/*----------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *----------------------------------------------------------------------------------------
- */
-// Forward declaration needed for multi-structure mutual references
-AGESA_FORWARD_DECLARATION (CPB_FAMILY_SERVICES);
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family specific call to check if CPB is supported.
- *
- * @param[in] CpbServices Core Performance Boost services.
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] Socket Zero-based socket number.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval TRUE CPB is supported.
- * @retval FALSE CPB is not supported.
- *
- */
-typedef BOOLEAN F_CPB_IS_SUPPORTED (
- IN CPB_FAMILY_SERVICES *CpbServices,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN UINT32 Socket,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_CPB_IS_SUPPORTED *PF_CPB_IS_SUPPORTED;
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family specific call to enable CPB.
- *
- * @param[in] CpbServices Core Performance Boost services.
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] EntryPoint Timepoint designator.
- * @param[in] Socket Zero-based socket number.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @return Family specific error value.
- *
- */
-typedef AGESA_STATUS F_CPB_INIT (
- IN CPB_FAMILY_SERVICES *CpbServices,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN UINT64 EntryPoint,
- IN UINT32 Socket,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_CPB_INIT *PF_CPB_INIT;
-
-/**
- * Provide the interface to the CPB Family Specific Services.
- *
- * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
- * Each supported Family must provide an implementation for all methods in this interface, even if the
- * implementation is a CommonReturn().
- */
-struct _CPB_FAMILY_SERVICES {
- UINT16 Revision; ///< Interface version
- // Public Methods.
- PF_CPB_IS_SUPPORTED IsCpbSupported; ///< Method: Family specific call to check if CPB is supported.
- PF_CPB_INIT EnableCpbOnSocket; ///< Method: Family specific call to enable CPB.
-};
-
-
-/*----------------------------------------------------------------------------------------
- * F U N C T I O N S P R O T O T Y P E
- *----------------------------------------------------------------------------------------
- */
-
-#endif // _CPU_CPB_H_
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuDmi.c b/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuDmi.c
deleted file mode 100644
index eb2d509..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuDmi.c
+++ /dev/null
@@ -1,681 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD DMI Record Creation API, and related functions.
- *
- * Contains code that produce the DMI related information.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 39742 $ @e \$Date: 2010-10-15 02:11:58 +0800 (Fri, 15 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "OptionDmi.h"
-#include "cpuLateInit.h"
-#include "cpuServices.h"
-#include "cpuRegisters.h"
-#include "GeneralServices.h"
-#include "heapManager.h"
-#include "Ids.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G3_DXE)
-RDATA_GROUP (G3_DXE)
-
-#define FILECODE PROC_CPU_FEATURE_CPUDMI_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-extern OPTION_DMI_CONFIGURATION OptionDmiConfiguration; // global user config record
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-UINT16
-STATIC
-AdjustGranularity (
- IN UINT32 *CacheSizePtr
- );
-
-VOID
-STATIC
-IntToString (
- IN OUT CHAR8 *String,
- IN UINT8 *Integer,
- IN UINT8 SizeInByte
-);
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------
- * L O C A L F U N C T I O N S
- *---------------------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * CreateDmiRecords
- *
- * Description:
- * This function creates DMI/SMBios records pertinent to the processor
- * SMBIOS type 4, type 7, and type 40.
- *
- * Parameters:
- * @param[in, out] *StdHeader
- * @param[in, out] **DmiTable
- *
- * @retval AGESA_STATUS
- *
- */
-
-AGESA_STATUS
-CreateDmiRecords (
- IN OUT AMD_CONFIG_PARAMS *StdHeader,
- IN OUT DMI_INFO **DmiTable
- )
-{
- AGESA_TESTPOINT (TpProcCpuEntryDmi, StdHeader);
- return ((*(OptionDmiConfiguration.DmiFeature)) (StdHeader, DmiTable));
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- * GetDmiInfoStub
- *
- * Description:
- * This is the default routine for use when the DMI option is NOT requested.
- * The option install process will create and fill the transfer vector with
- * the address of the proper routine (Main or Stub). The link optimizer will
- * strip out of the .DLL the routine that is not used.
- *
- * Parameters:
- * @param[in, out] *StdHeader
- * @param[in, out] **DmiTable
- *
- * @retval AGESA_STATUS
- *
- */
-AGESA_STATUS
-GetDmiInfoStub (
- IN OUT AMD_CONFIG_PARAMS *StdHeader,
- IN OUT DMI_INFO **DmiTable
- )
-{
- return AGESA_UNSUPPORTED;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- * GetDmiInfoMain
- *
- * Description:
- * This is the common routine for getting Dmi type4 and type7 CPU related information.
- *
- * Parameters:
- * @param[in, out] *StdHeader
- * @param[in, out] **DmiTable
- *
- * @retval AGESA_STATUS
- *
- */
-AGESA_STATUS
-GetDmiInfoMain (
- IN OUT AMD_CONFIG_PARAMS *StdHeader,
- IN OUT DMI_INFO **DmiTable
- )
-{
- UINT8 Socket;
- UINT8 Channel;
- UINT8 Dimm;
- UINT16 Index;
- UINT16 DimmIndex;
- UINT16 NumberOfDimm;
- UINT32 SocketNum;
- UINT64 MsrData;
- UINT64 MsrRegister;
- BOOLEAN FamilyNotFound;
- AGESA_STATUS Flag;
- AGESA_STATUS CalledStatus;
- AP_EXE_PARAMS ApParams;
- MEM_DMI_INFO *MemInfo;
- DMI_T17_MEMORY_TYPE MemType;
- DMI_INFO *DmiBufferPtr;
- ALLOCATE_HEAP_PARAMS AllocateHeapParams;
- LOCATE_HEAP_PTR LocateHeapParams;
- CPU_LOGICAL_ID LogicalId;
- PROC_FAMILY_TABLE *ProcData;
- CPU_GET_MEM_INFO CpuGetMemInfo;
-
- MsrData = 0;
- Flag = TRUE;
- ProcData = NULL;
- MemInfo = NULL;
- DmiBufferPtr = *DmiTable;
- FamilyNotFound = TRUE;
-
- GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
- for (Index = 0; Index < OptionDmiConfiguration.NumEntries; Index++) {
- ProcData = (PROC_FAMILY_TABLE *) ((*OptionDmiConfiguration.FamilyList)[Index]);
- if ((ProcData->ProcessorFamily & LogicalId.Family) != 0) {
- FamilyNotFound = FALSE;
- break;
- }
- }
-
- if (FamilyNotFound) {
- return AGESA_ERROR;
- }
-
- if (DmiBufferPtr == NULL) {
- //
- // Allocate a buffer by heap function
- //
- AllocateHeapParams.BufferHandle = AMD_DMI_INFO_BUFFER_HANDLE;
- AllocateHeapParams.RequestedBufferSize = sizeof (DMI_INFO);
- AllocateHeapParams.Persist = HEAP_SYSTEM_MEM;
-
- if (HeapAllocateBuffer (&AllocateHeapParams, StdHeader) != AGESA_SUCCESS) {
- return AGESA_ERROR;
- }
-
- DmiBufferPtr = (DMI_INFO *) AllocateHeapParams.BufferPtr;
- *DmiTable = DmiBufferPtr;
- }
-
- IDS_HDT_CONSOLE (CPU_TRACE, " DMI is enabled\n");
-
- // Fill with 0x00
- LibAmdMemFill (DmiBufferPtr, 0x00, sizeof (DMI_INFO), StdHeader);
- // Set type 4 offset 18h Status to
- // bit[6] to 1 - CPU Socket Populated
- // bit[2:0] to 0 - Unknown
- for (SocketNum = 0; SocketNum < MAX_SOCKETS_SUPPORTED; SocketNum++) {
- DmiBufferPtr->T4[SocketNum].T4Status = SOCKET_POPULATED | CPU_STATUS_UNKNOWN;
- }
- //
- // Get CPU information
- //
-
- // Run GetType4Type7Info on all core0s.
- ApParams.StdHeader = *StdHeader;
- ApParams.FunctionNumber = AP_LATE_TASK_GET_TYPE4_TYPE7;
- ApParams.RelatedDataBlock = (VOID *) DmiBufferPtr;
- ApParams.RelatedBlockLength = sizeof (DMI_INFO);
- CalledStatus = RunLateApTaskOnAllCore0s (&ApParams, StdHeader);
- if (CalledStatus > Flag) {
- Flag = CalledStatus;
- }
- CalledStatus = GetType4Type7Info (&ApParams);
- if (CalledStatus > Flag) {
- Flag = CalledStatus;
- }
-
- //------------------------------
- // T Y P E 16 17 19 20
- //------------------------------
-
- LocateHeapParams.BufferHandle = AMD_DMI_MEM_DEV_INFO_HANDLE;
- if (HeapLocateBuffer (&LocateHeapParams, StdHeader) != AGESA_SUCCESS) {
- if (Flag < AGESA_ERROR) {
- Flag = AGESA_ERROR;
- }
- } else {
- NumberOfDimm = *((UINT16 *) (LocateHeapParams.BufferPtr));
- MemType = *((DMI_T17_MEMORY_TYPE *) ((UINT8 *) (LocateHeapParams.BufferPtr) + 2));
- MemInfo = (MEM_DMI_INFO *) ((UINT8 *) (LocateHeapParams.BufferPtr) + 2 + sizeof (DMI_T17_MEMORY_TYPE));
- // TYPE 16
- DmiBufferPtr->T16.Location = 0x03;
- DmiBufferPtr->T16.Use = 0x03;
-
- // Gather memory information
- ProcData->DmiGetMemInfo (&CpuGetMemInfo, StdHeader);
-
- if (CpuGetMemInfo.EccCapable) {
- DmiBufferPtr->T16.MemoryErrorCorrection = 0x04;
- } else {
- DmiBufferPtr->T16.MemoryErrorCorrection = 0x03;
- }
-
- LibAmdMsrRead (TOP_MEM2, &MsrData, StdHeader);
- if (MsrData == 0) {
- LibAmdMsrRead (TOP_MEM, &MsrData, StdHeader);
- DmiBufferPtr->T16.MaximumCapacity = (UINT32) (MsrData >> 10);
- } else {
- DmiBufferPtr->T16.MaximumCapacity = (UINT32) (MsrData >> 10);
- }
-
- DmiBufferPtr->T16.NumberOfMemoryDevices = NumberOfDimm;
-
- // TYPE 17
- for (DimmIndex = 0; DimmIndex < NumberOfDimm; DimmIndex++) {
- Socket = (MemInfo + DimmIndex)->Socket;
- Channel = (MemInfo + DimmIndex)->Channel;
- Dimm = (MemInfo + DimmIndex)->Dimm;
-
- DmiBufferPtr->T17[Socket][Channel][Dimm].TotalWidth = (MemInfo + DimmIndex)->TotalWidth;
- DmiBufferPtr->T17[Socket][Channel][Dimm].DataWidth = (MemInfo + DimmIndex)->DataWidth;
- DmiBufferPtr->T17[Socket][Channel][Dimm].MemorySize = (MemInfo + DimmIndex)->MemorySize;
- DmiBufferPtr->T17[Socket][Channel][Dimm].FormFactor = (MemInfo + DimmIndex)->FormFactor;
- DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceSet = 0;
-
- DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[0] = 'D';
- DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[1] = 'I';
- DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[2] = 'M';
- DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[3] = 'M';
- DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[4] = ' ';
- DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[5] = Dimm + 0x30;
- DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[6] = '\0';
- DmiBufferPtr->T17[Socket][Channel][Dimm].DeviceLocator[7] = '\0';
-
- DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[0] = 'C';
- DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[1] = 'H';
- DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[2] = 'A';
- DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[3] = 'N';
- DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[4] = 'N';
- DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[5] = 'E';
- DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[6] = 'L';
- DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[7] = ' ';
- DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[8] = Channel + 0x41;
- DmiBufferPtr->T17[Socket][Channel][Dimm].BankLocator[9] = '\0';
-
- DmiBufferPtr->T17[Socket][Channel][Dimm].MemoryType = MemType;
- DmiBufferPtr->T17[Socket][Channel][Dimm].TypeDetail.Synchronous = 1;
- DmiBufferPtr->T17[Socket][Channel][Dimm].Speed = (MemInfo + DimmIndex)->Speed;
-
- DmiBufferPtr->T17[Socket][Channel][Dimm].ManufacturerIdCode = (MemInfo + DimmIndex)->ManufacturerIdCode;
-
- IntToString (DmiBufferPtr->T17[Socket][Channel][Dimm].SerialNumber, (MemInfo + DimmIndex)->SerialNumber, (sizeof DmiBufferPtr->T17[Socket][Channel][Dimm].SerialNumber - 1) / 2);
-
- LibAmdMemCopy (&DmiBufferPtr->T17[Socket][Channel][Dimm].PartNumber, &(MemInfo + DimmIndex)->PartNumber, sizeof (DmiBufferPtr->T17[Socket][Channel][Dimm].PartNumber), StdHeader);
- DmiBufferPtr->T17[Socket][Channel][Dimm].PartNumber[18] = 0;
-
- DmiBufferPtr->T17[Socket][Channel][Dimm].Attributes = (MemInfo + DimmIndex)->Attributes;
- DmiBufferPtr->T17[Socket][Channel][Dimm].ExtSize = (MemInfo + DimmIndex)->ExtSize;
- DmiBufferPtr->T17[Socket][Channel][Dimm].ConfigSpeed = (MemInfo + DimmIndex)->ConfigSpeed;
-
- //TYPE 20
- DmiBufferPtr->T20[Socket][Channel][Dimm].StartingAddr = (MemInfo + DimmIndex)->StartingAddr;
- DmiBufferPtr->T20[Socket][Channel][Dimm].EndingAddr = (MemInfo + DimmIndex)->EndingAddr;
- // Partition Row Position - 2 for single channel memory
- // 0 for dual channel memory
- DmiBufferPtr->T20[Socket][Channel][Dimm].PartitionRowPosition = CpuGetMemInfo.PartitionRowPosition;
- DmiBufferPtr->T20[Socket][Channel][Dimm].InterleavePosition = 0xFF;
- DmiBufferPtr->T20[Socket][Channel][Dimm].InterleavedDataDepth = 0xFF;
- }
-
- // TYPE 19
- DmiBufferPtr->T19.StartingAddr = 0;
-
- LibAmdMsrRead (TOP_MEM2, &MsrRegister, StdHeader);
- if (MsrRegister == 0) {
- LibAmdMsrRead (TOP_MEM, &MsrRegister, StdHeader);
- DmiBufferPtr->T19.EndingAddr = (UINT32) (MsrRegister >> 10);
- } else if (MsrRegister != 0) {
- DmiBufferPtr->T19.EndingAddr = (UINT32) (MsrRegister >> 10);
- }
-
- DmiBufferPtr->T19.PartitionWidth = 0xFF;
- }
- return (Flag);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * GetType4Type7Info
- *
- * Description:
- * This routine should be run on core 0 of every socket. It creates DMI type 4 and type 7 tables.
- *
- * Parameters:
- * @param[in] ApExeParams Handle to config for library and services.
- *
- * @retval AGESA_STATUS
- *
- * Processing:
- *
- */
-AGESA_STATUS
-GetType4Type7Info (
- IN AP_EXE_PARAMS *ApExeParams
- )
-{
- UINT8 ByteIndexInUint64;
- UINT16 Index;
- UINT32 SocketNum;
- UINT32 CacheSize;
- UINT32 IgnoredModule;
- UINT32 IgnoredCore;
- UINT64 MsrData;
- DMI_INFO *DmiBufferPtr;
- AGESA_STATUS IgnoredSts;
- AGESA_STATUS Flag;
- BOOLEAN FamilyNotFound;
- CPUID_DATA CpuId;
- CPU_TYPE_INFO CpuInfo;
- PROC_FAMILY_TABLE *ProcData;
- CPU_LOGICAL_ID LogicalID;
-
- Flag = TRUE;
- DmiBufferPtr = (DMI_INFO *) ApExeParams->RelatedDataBlock;
- GetLogicalIdOfCurrentCore (&LogicalID, &ApExeParams->StdHeader);
-
- ProcData = NULL;
- FamilyNotFound = TRUE;
- for (Index = 0; Index < OptionDmiConfiguration.NumEntries; Index++) {
- ProcData = (PROC_FAMILY_TABLE *) ((*OptionDmiConfiguration.FamilyList)[Index]);
- if ((ProcData->ProcessorFamily & LogicalID.Family) != 0) {
- FamilyNotFound = FALSE;
- break;
- }
- }
-
- if (FamilyNotFound) {
- return AGESA_ERROR;
- }
-
- ProcData->DmiGetCpuInfo (&CpuInfo, &ApExeParams->StdHeader);
-
- // ------------------------------
- // T Y P E 4
- // ------------------------------
-
- IdentifyCore (&ApExeParams->StdHeader, &SocketNum, &IgnoredModule, &IgnoredCore, &IgnoredSts);
-
- // Type 4 Offset 0x05, Processor Type
- DmiBufferPtr->T4[SocketNum].T4ProcType = CENTRAL_PROCESSOR;
-
- // Type 4 Offset 0x06, Processor Family
- for (Index = 0; Index < ProcData->LenBrandList; Index++) {
- if ((ProcData->DmiBrandList[Index].PackageType == 'x' || ProcData->DmiBrandList[Index].PackageType == CpuInfo.PackageType) &&
- (ProcData->DmiBrandList[Index].PgOfBrandId == 'x' || ProcData->DmiBrandList[Index].PgOfBrandId == CpuInfo.BrandId.Pg) &&
- (ProcData->DmiBrandList[Index].NumberOfCores == 'x' || ProcData->DmiBrandList[Index].NumberOfCores == CpuInfo.TotalCoreNumber) &&
- (ProcData->DmiBrandList[Index].String1ofBrandId == 'x' || ProcData->DmiBrandList[Index].String1ofBrandId == CpuInfo.BrandId.String1)) {
- DmiBufferPtr->T4[SocketNum].T4ProcFamily = ProcData->DmiBrandList[Index].ValueSetToDmiTable;
- break;
- }
- }
-
- if (DmiBufferPtr->T4[SocketNum].T4ProcFamily == P_UPGRADE_UNKNOWN) {
- Flag = AGESA_ERROR;
- }
-
- // Type4 Offset 0x08, Processor ID
- LibAmdCpuidRead (AMD_CPUID_APICID_LPC_BID, &CpuId, &ApExeParams->StdHeader);
- DmiBufferPtr->T4[SocketNum].T4ProcId.ProcIdLsd = CpuId.EAX_Reg;
- DmiBufferPtr->T4[SocketNum].T4ProcId.ProcIdMsd = CpuId.EDX_Reg;
-
- // Type4 Offset 0x11, Voltage
- DmiBufferPtr->T4[SocketNum].T4Voltage = ProcData->DmiGetVoltage (&ApExeParams->StdHeader);
-
- // Type4 Offset 0x12, External Clock
- DmiBufferPtr->T4[SocketNum].T4ExternalClock = ProcData->DmiGetExtClock (&ApExeParams->StdHeader);
-
- // Type4 Offset 0x14, Max Speed
- DmiBufferPtr->T4[SocketNum].T4MaxSpeed = ProcData->DmiGetMaxSpeed (&ApExeParams->StdHeader);
-
- // Type4 Offset 0x16, Current Speed
- DmiBufferPtr->T4[SocketNum].T4CurrentSpeed = DmiBufferPtr->T4[SocketNum].T4MaxSpeed;
-
- // Type4 Offset 0x18, Status
- DmiBufferPtr->T4[SocketNum].T4Status = SOCKET_POPULATED | CPU_STATUS_ENABLED;
-
- // Type4 Offset 0x19, Processor Upgrade
- DmiBufferPtr->T4[SocketNum].T4ProcUpgrade = CpuInfo.ProcUpgrade;
-
- // Type4 Offset 0x23, 0x24 and 0x25, Core Count, Core Enabled and Thread Count
- DmiBufferPtr->T4[SocketNum].T4CoreCount = CpuInfo.TotalCoreNumber + 1;
- DmiBufferPtr->T4[SocketNum].T4CoreEnabled = CpuInfo.EnabledCoreNumber + 1;
- DmiBufferPtr->T4[SocketNum].T4ThreadCount = CpuInfo.EnabledCoreNumber + 1;
-
- // Type4 Offset 0x26, Processor Characteristics
- DmiBufferPtr->T4[SocketNum].T4ProcCharacteristics = P_CHARACTERISTICS;
-
- // Type4 Offset 0x28, Processor Family 2
- DmiBufferPtr->T4[SocketNum].T4ProcFamily2 = DmiBufferPtr->T4[SocketNum].T4ProcFamily;
-
- // Type4 ProcVersion
- for (Index = 0; Index <= 5; Index++) {
- LibAmdMsrRead ((MSR_CPUID_NAME_STRING0 + Index), &MsrData, &ApExeParams->StdHeader);
- for (ByteIndexInUint64 = 0; ByteIndexInUint64 <= 7; ByteIndexInUint64++) {
- DmiBufferPtr->T4[SocketNum].T4ProcVersion[Index * 8 + ByteIndexInUint64] = (UINT8) (MsrData >> (8 * ByteIndexInUint64));
- }
- }
-
- //------------------------------
- // T Y P E 7
- //------------------------------
-
- // Type7 Offset 0x05, Cache Configuration
- DmiBufferPtr->T7L1[SocketNum].T7CacheCfg = CACHE_CFG_L1;
- DmiBufferPtr->T7L2[SocketNum].T7CacheCfg = CACHE_CFG_L2;
- DmiBufferPtr->T7L3[SocketNum].T7CacheCfg = CACHE_CFG_L3;
-
- // Type7 Offset 0x07 and 09, Maximum Cache Size and Installed Size
- LibAmdCpuidRead (AMD_CPUID_TLB_L1Cache, &CpuId, &ApExeParams->StdHeader);
-
- // Maximum L1 cache size
- CacheSize = (UINT32) (((UINT8) (CpuId.ECX_Reg >> 24) + (UINT8) (CpuId.EDX_Reg >> 24)) * (CpuInfo.EnabledCoreNumber + 1));
- DmiBufferPtr->T7L1[SocketNum].T7MaxCacheSize = AdjustGranularity (&CacheSize);
-
- // Installed L1 cache size
- DmiBufferPtr->T7L1[SocketNum].T7InstallSize = DmiBufferPtr->T7L1[SocketNum].T7MaxCacheSize;
-
- // Maximum L2 cache size
- LibAmdCpuidRead (AMD_CPUID_L2L3Cache_L2TLB, &CpuId, &ApExeParams->StdHeader);
- CacheSize = (UINT32) ((UINT16) (CpuId.ECX_Reg >> 16) * (CpuInfo.EnabledCoreNumber + 1));
- DmiBufferPtr->T7L2[SocketNum].T7MaxCacheSize = AdjustGranularity (&CacheSize);
-
- // Installed L2 cache size
- DmiBufferPtr->T7L2[SocketNum].T7InstallSize = DmiBufferPtr->T7L2[SocketNum].T7MaxCacheSize;
-
- // Maximum L3 cache size
- CacheSize = ((CpuId.EDX_Reg >> 18) & 0x3FFF) * 512;
- DmiBufferPtr->T7L3[SocketNum].T7MaxCacheSize = AdjustGranularity (&CacheSize);
-
- // Installed L3 cache size
- DmiBufferPtr->T7L3[SocketNum].T7InstallSize = DmiBufferPtr->T7L3[SocketNum].T7MaxCacheSize;
-
- // Type7 Offset 0x0B and 0D, Supported SRAM Type and Current SRAM Type
- DmiBufferPtr->T7L1[SocketNum].T7SupportedSramType = SRAM_TYPE;
- DmiBufferPtr->T7L1[SocketNum].T7CurrentSramType = SRAM_TYPE;
- DmiBufferPtr->T7L2[SocketNum].T7SupportedSramType = SRAM_TYPE;
- DmiBufferPtr->T7L2[SocketNum].T7CurrentSramType = SRAM_TYPE;
- DmiBufferPtr->T7L3[SocketNum].T7SupportedSramType = SRAM_TYPE;
- DmiBufferPtr->T7L3[SocketNum].T7CurrentSramType = SRAM_TYPE;
-
- // Type7 Offset 0x0F, Cache Speed
- DmiBufferPtr->T7L1[SocketNum].T7CacheSpeed = 1;
- DmiBufferPtr->T7L2[SocketNum].T7CacheSpeed = 1;
- DmiBufferPtr->T7L3[SocketNum].T7CacheSpeed = 1;
-
- // Type7 Offset 0x10, Error Correction Type
- DmiBufferPtr->T7L1[SocketNum].T7ErrorCorrectionType = ERR_CORRECT_TYPE;
- DmiBufferPtr->T7L2[SocketNum].T7ErrorCorrectionType = ERR_CORRECT_TYPE;
- DmiBufferPtr->T7L3[SocketNum].T7ErrorCorrectionType = ERR_CORRECT_TYPE;
-
- // Type7 Offset 0x11, System Cache Type
- DmiBufferPtr->T7L1[SocketNum].T7SystemCacheType = CACHE_TYPE;
- DmiBufferPtr->T7L2[SocketNum].T7SystemCacheType = CACHE_TYPE;
- DmiBufferPtr->T7L3[SocketNum].T7SystemCacheType = CACHE_TYPE;
-
- // Type7 Offset 0x12, Associativity
- DmiBufferPtr->T7L1[SocketNum].T7Associativity = ASSOCIATIVE_2_WAY;
- DmiBufferPtr->T7L2[SocketNum].T7Associativity = ASSOCIATIVE_16_WAY;
- if (((CpuId.EDX_Reg >> 12) & 0x0F) == ASSOCIATIVE_16_WAY) {
- DmiBufferPtr->T7L3[SocketNum].T7Associativity = ASSOCIATIVE_16_WAY;
- } else {
- DmiBufferPtr->T7L3[SocketNum].T7Associativity = ASSOCIATIVE_OTHER;
- }
- return (Flag);
-}
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * AdjustGranularity
- *
- * Description:
- * If cache size is greater than or equal to 32M, then set granularity
- * to 64K. otherwise, set granularity to 1K
- *
- * Parameters:
- * @param[in] *CacheSizePtr
- *
- * @retval CacheSize
- *
- * Processing:
- *
- */
-UINT16
-STATIC
-AdjustGranularity (
- IN UINT32 *CacheSizePtr
- )
-{
- UINT16 CacheSize;
-
- if (*CacheSizePtr >= 0x8000) {
- CacheSize = (UINT16) (*CacheSizePtr / 64);
- CacheSize |= 0x8000;
- } else {
- CacheSize = (UINT16) *CacheSizePtr;
- }
-
- return (CacheSize);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- * ReleaseDmiBufferStub
- *
- * Description:
- * This is the default routine for use when the DMI option is NOT requested.
- *
- * Parameters:
- * @param[in, out] *StdHeader
- *
- * @retval AGESA_STATUS
- *
- */
-AGESA_STATUS
-ReleaseDmiBufferStub (
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- return AGESA_UNSUPPORTED;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- * ReleaseDmiBuffer
- *
- * Description:
- * Deallocate DMI buffer
- *
- * Parameters:
- * @param[in, out] *StdHeader
- *
- * @retval AGESA_STATUS
- *
- */
-AGESA_STATUS
-ReleaseDmiBuffer (
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- HeapDeallocateBuffer ((UINT32) AMD_DMI_MEM_DEV_INFO_HANDLE, StdHeader);
-
- return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * IntToString
- *
- * Description:
- * Translate UINT array to CHAR array.
- *
- * Parameters:
- * @param[in, out] *String Pointer to CHAR array
- * @param[in] *Integer Pointer to UINT array
- * @param[in] SizeInByte The size of UINT array
- *
- * Processing:
- *
- */
-VOID
-STATIC
-IntToString (
- IN OUT CHAR8 *String,
- IN UINT8 *Integer,
- IN UINT8 SizeInByte
- )
-{
- UINT8 Index;
-
- for (Index = 0; Index < SizeInByte; Index++) {
- *(String + Index * 2) = (*(Integer + Index) >> 4) & 0x0F;
- *(String + Index * 2 + 1) = *(Integer + Index) & 0x0F;
- }
- for (Index = 0; Index < (SizeInByte * 2); Index++) {
- if (*(String + Index) >= 0x0A) {
- *(String + Index) += 0x37;
- } else {
- *(String + Index) += 0x30;
- }
- }
- *(String + SizeInByte * 2) = 0x0;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuFeatureLeveling.c b/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuFeatureLeveling.c
deleted file mode 100644
index afa2226..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuFeatureLeveling.c
+++ /dev/null
@@ -1,266 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU Feature Leveling Function.
- *
- * Contains code to Level the Feature in a multi-socket system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "cpuRegisters.h"
-#include "GeneralServices.h"
-#include "cpuServices.h"
-#include "cpuPostInit.h"
-#include "cpuApicUtilities.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FEATURE_CPUFEATURELEVELING_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-VOID
-STATIC
-SaveFeatures (
- IN OUT VOID *cpuFeatureListPtr,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-STATIC
-WriteFeatures (
- IN OUT VOID *cpuFeatureListPtr,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-STATIC
-GetGlobalCpuFeatureListAddress (
- OUT UINT64 **Address,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*----------------------------------------------------------------------------------------
- * P U B L I C F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * FeatureLeveling
- *
- * CPU feature leveling. Set least common features set of all CPUs
- *
- * @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct.
- *
- */
-VOID
-FeatureLeveling (
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 BscSocket;
- UINT32 Ignored;
- UINT32 BscCore;
- UINT32 Socket;
- UINT32 Core;
- UINT32 NumberOfSockets;
- UINT32 NumberOfCores;
- BOOLEAN *FirstTime;
- BOOLEAN *NeedLeveling;
- AGESA_STATUS IgnoredSts;
- CPU_FEATURES_LIST *globalCpuFeatureList;
- AP_TASK TaskPtr;
-
- ASSERT (IsBsp (StdHeader, &IgnoredSts));
-
- GetGlobalCpuFeatureListAddress ((UINT64 **) &globalCpuFeatureList, StdHeader);
- FirstTime = (BOOLEAN *) ((UINT8 *) globalCpuFeatureList + sizeof (CPU_FEATURES_LIST));
- NeedLeveling = (BOOLEAN *) ((UINT8 *) globalCpuFeatureList + sizeof (CPU_FEATURES_LIST) + sizeof (BOOLEAN));
-
- *FirstTime = TRUE;
- *NeedLeveling = FALSE;
-
- LibAmdMemFill (globalCpuFeatureList, 0xFF, sizeof (CPU_FEATURES_LIST), StdHeader);
- IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredSts);
- NumberOfSockets = GetPlatformNumberOfSockets ();
-
- TaskPtr.FuncAddress.PfApTaskI = SaveFeatures;
- TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (CPU_FEATURES_LIST);
- TaskPtr.ExeFlags = WAIT_FOR_CORE;
- TaskPtr.DataTransfer.DataPtr = globalCpuFeatureList;
- TaskPtr.DataTransfer.DataTransferFlags = DATA_IN_MEMORY;
-
- for (Socket = 0; Socket < NumberOfSockets; Socket++) {
- if (IsProcessorPresent (Socket, StdHeader)) {
- if (Socket != BscSocket) {
- ApUtilRunCodeOnSocketCore ((UINT8)Socket, 0, &TaskPtr, StdHeader);
- }
- }
- }
- ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, NULL);
-
- if (*NeedLeveling) {
- TaskPtr.FuncAddress.PfApTaskI = WriteFeatures;
- for (Socket = 0; Socket < NumberOfSockets; Socket++) {
- if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
- for (Core = 0; Core < NumberOfCores; Core++) {
- if ((Socket != BscSocket) || (Core != BscCore)) {
- ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)Core, &TaskPtr, StdHeader);
- }
- }
- }
- }
- ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, NULL);
- }
-}
-
-/*----------------------------------------------------------------------------------------
- * L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * SaveFeatures
- *
- * save least common features set of all CPUs
- *
- * @param[in,out] cpuFeatureListPtr - Pointer to CPU Feature List.
- * @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct.
- *
- */
-VOID
-STATIC
-SaveFeatures (
- IN OUT VOID *cpuFeatureListPtr,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
- FamilySpecificServices = NULL;
-
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
- FamilySpecificServices->SaveFeatures (FamilySpecificServices, cpuFeatureListPtr, StdHeader);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * WriteFeatures
- *
- * Write out least common features set of all CPUs
- *
- * @param[in,out] cpuFeatureListPtr - Pointer to CPU Feature List.
- * @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct.
- *
- */
-VOID
-STATIC
-WriteFeatures (
- IN OUT VOID *cpuFeatureListPtr,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
- FamilySpecificServices = NULL;
-
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
- FamilySpecificServices->WriteFeatures (FamilySpecificServices, cpuFeatureListPtr, StdHeader);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * GetGlobalCpuFeatureListAddress
- *
- * Determines the address in system DRAM that should be used for CPU feature leveling.
- *
- * @param[out] Address Address to utilize
- * @param[in] StdHeader Config handle for library and services
- *
- *
- */
-VOID
-STATIC
-GetGlobalCpuFeatureListAddress (
- OUT UINT64 **Address,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 AddressValue;
-
- AddressValue = GLOBAL_CPU_FEATURE_LIST_TEMP_ADDR;
-
- *Address = (UINT64 *)(AddressValue);
-}
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuFeatures.c b/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuFeatures.c
deleted file mode 100644
index fa18acf..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuFeatures.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Implement general feature dispatcher.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 37150 $ @e \$Date: 2010-08-31 23:53:37 +0800 (Tue, 31 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "GeneralServices.h"
-#include "cpuFeatures.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-#define FILECODE PROC_CPU_FEATURE_CPUFEATURES_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S - External General Services API
- *----------------------------------------------------------------------------------------
- */
-extern CONST CPU_FEATURE_DESCRIPTOR* ROMDATA SupportedCpuFeatureList[];
-
-/**
- * Determines if a specific feature is or will be enabled.
- *
- * This code traverses the feature list until a match is
- * found, then invokes the 'IsEnabled' function of the
- * feature.
- *
- * @param[in] Feature Indicates the desired feature.
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Standard AMD configuration parameters.
- *
- * @retval TRUE Feature is or will be enabled
- * @retval FALSE Feature is not enabled
- */
-BOOLEAN
-IsFeatureEnabled (
- IN DISPATCHABLE_CPU_FEATURES Feature,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINTN i;
-
- ASSERT (Feature < MaxCpuFeature);
-
- for (i = 0; SupportedCpuFeatureList[i] != NULL; i++) {
- if (SupportedCpuFeatureList[i]->Feature == Feature) {
- return (SupportedCpuFeatureList[i]->IsEnabled (PlatformConfig, StdHeader));
- }
- }
- return FALSE;
-}
-
-/**
- * Dispatches all features needing to perform some initialization at
- * this time point.
- *
- * This routine searches the feature table for features needing to
- * run at this time point, and invokes them.
- *
- * @param[in] EntryPoint Timepoint designator
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Standard AMD configuration parameters.
- *
- * @return The most severe status of any called service.
- */
-AGESA_STATUS
-DispatchCpuFeatures (
- IN UINT64 EntryPoint,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINTN i;
- AGESA_STATUS AgesaStatus;
- AGESA_STATUS CalledStatus;
- AGESA_STATUS IgnoredStatus;
-
- AgesaStatus = AGESA_SUCCESS;
-
- if (IsBsp (StdHeader, &IgnoredStatus)) {
- for (i = 0; SupportedCpuFeatureList[i] != NULL; i++) {
- if ((SupportedCpuFeatureList[i]->EntryPoint & EntryPoint) != 0) {
- if (SupportedCpuFeatureList[i]->IsEnabled (PlatformConfig, StdHeader)) {
- CalledStatus = SupportedCpuFeatureList[i]->InitializeFeature (EntryPoint, PlatformConfig, StdHeader);
- if (CalledStatus > AgesaStatus) {
- AgesaStatus = CalledStatus;
- }
- }
- }
- }
- }
- return AgesaStatus;
-}
-
-/**
- * This routine checks whether any non-coherent links in the system
- * runs in HT1 mode; used to determine whether certain features
- * should be disabled when this routine returns TRUE.
- *
- * @param[in] StdHeader Standard AMD configuration parameters.
- *
- * @retval TRUE One of the non-coherent links in the
- * system runs in HT1 mode
- * @retval FALSE None of the non-coherent links in the
- * system is running in HT1 mode
- */
-BOOLEAN
-IsNonCoherentHt1 (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINTN Link;
- UINT32 Socket;
- UINT32 Module;
- PCI_ADDR PciAddress;
- AGESA_STATUS AgesaStatus;
- HT_HOST_FEATS HtHostFeats;
- CPU_SPECIFIC_SERVICES *CpuServices;
-
- for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
- if (IsProcessorPresent (Socket, StdHeader)) {
- GetCpuServicesOfSocket (Socket, &CpuServices, StdHeader);
- for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
- if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &AgesaStatus)) {
- HtHostFeats.HtHostValue = 0;
- Link = 0;
- while (CpuServices->GetNextHtLinkFeatures (CpuServices, &Link, &PciAddress, &HtHostFeats, StdHeader)) {
- // Return TRUE and exit routine once we find a non-coherent link in HT1
- if ((HtHostFeats.HtHostFeatures.NonCoherent == 1) && (HtHostFeats.HtHostFeatures.Ht1 == 1)) {
- return TRUE;
- }
- }
- }
- }
- }
- }
-
- return FALSE;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuFeatures.h b/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuFeatures.h
deleted file mode 100644
index acd08b9..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuFeatures.h
+++ /dev/null
@@ -1,267 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Generic CPU feature dispatcher and related services.
- *
- * Provides a feature processing engine to handle feature in a
- * more generic way.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Common
- * @e \$Revision: 37157 $ @e \$Date: 2010-09-01 03:24:07 +0800 (Wed, 01 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPU_FEATURES_H_
-#define _CPU_FEATURES_H_
-
-/**
- * @page cpufeatimpl CPU Generic Feature Implementation Guide
- *
- * The CPU generic feature dispatcher provides services which can be used to implement a
- * wide range of features in a manner that isolates calling code from knowledge about which
- * families or features are supported in the current build.
- *
- * @par Determine if a New Feature is a Suitable Candidate
- *
- * A feature must meet the following requirements:
- * <ul>
- * <li> Any core in the system must be able to determine if the feature should be enabled or not.
- *
- * <ul>
- * <li> MSRs cannot be read in multisocket systems in the 'IsEnabled' function.
- *
- * <li> Cores cannot be launched in the 'IsEnabled' function.
- * </ul>
- * </ul>
- *
- * @par Determine the Time Point at which the Feature Should be Enabled
- *
- * Factors to consider in making this determination:
- *
- * <ul>
- * <li> Determine if there are any dependencies on other settings that require strict ordering.
- *
- * <li> Consider the state of the APs that you will need.
- *
- * <li> Remember that features enabled during AmdInitEarly will automatically be restored on S3 resume.
- * </ul>
- *
- * @par Implementing a new feature
- *
- * Perform the following steps to implement a new feature:
- *
- * <ul>
- * <li> Create a unique equate for your time point, @b if you cannot use an existing time point.
- *
- * <li> Create a new value in the DISPATCHABLE_CPU_FEATURES enum for your feature.
- *
- * <li> Add a new 'C' file to the Features folder for your feature.
- *
- * <ul>
- * <li> The 'C' file must implement 2 functions -- 'IsEnabled' and 'Initialize'
- *
- * <li> The 'C' file must instantiate a CPU_FEATURE_DESCRIPTOR structure.
- * </ul>
- *
- * <li> Add a new 'H' file to the Features folder for your feature.
- *
- * <ul>
- * <li> The 'H' file declares whatever family specific functions required by the feature.
- *
- * <li> The 'H' file declares a structure containing all family specific functions. For a reference
- * example, your feature API should have a set of conventions similar to cpu specific services,
- * @ref cpuimplfss.
- * </ul>
- *
- * <li> Create 'C' files in all applicable family folders.
- *
- * <ul>
- * <li> Implement the required family specific functions.
- *
- * <li> Instantiate a family specific services structure.
- * </ul>
- *
- * <li> Create \<feature name\>Install.h in the include folder.
- *
- * <ul>
- * <li> Add logic to determine when your feature should be included in the build.
- *
- * <li> If the feature should be included, define OPTION_\<feature name\> to the address of your
- * CPU_FEATURE_DESCRIPTOR instantiation. If not, define OPTION_\<feature name\> to be blank.
- *
- * <li> Create a family translation table pointing to all applicable instantiations of
- * family specific function structures.
- * </ul>
- *
- * <li> Modify OptionCpuFeaturesInstall.h in the include folder.
- *
- * <ul>
- * <li> Include \<feature name\>Install.h.
- *
- * <li> Add OPTION_\<feature name\> to the SupportedCpuFeatureList array.
- * </ul>
- *
- * <li> If a new time point was created, add a call to DispatchCpuFeatures at the desired location,
- * passing your new time point equate.
- * </ul>
- *
- */
-
-
-/*----------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *----------------------------------------------------------------------------------------
- */
-#define CPU_FEAT_BEFORE_PM_INIT (0x0000000000000001ull)
-#define CPU_FEAT_AFTER_PM_INIT (0x0000000000000002ull)
-#define CPU_FEAT_AFTER_POST_MTRR_SYNC (0x0000000000000004ull)
-#define CPU_FEAT_INIT_MID_END (0x0000000000000008ull)
-#define CPU_FEAT_INIT_LATE_END (0x0000000000000010ull)
-#define CPU_FEAT_S3_LATE_RESTORE_END (0x0000000000000020ull)
-#define CPU_FEAT_AFTER_RESUME_MTRR_SYNC (0x0000000000000040ull)
-#define CPU_FEAT_AFTER_COHERENT_DISCOVERY (0x0000000000000080ull)
-/**
- * Enumerated list of supported features.
- */
-typedef enum {
- HardwareC1e, ///< Hardware C1e
- HtAssist, ///< Probe filter
- MsgBasedC1e, ///< Message-based C1e
- SoftwareC1e, ///< Software C1e
- CoreLeveling, ///< Core Leveling
- C6Cstate, ///< C6 C-state
- IoCstate, ///< IO C-state
- CacheFlushOnHalt, ///< Cache Flush On Halt
- PreserveAroundMailbox, ///< Save-Restore the registers used for AP mailbox, to preserve their normal function.
- CoreBoost, ///< Core Performance Boost (CPB)
- LowPwrPstate, ///< 500 MHz Low Power P-state
- MaxCpuFeature ///< Not a valid value, used for verifying input
-} DISPATCHABLE_CPU_FEATURES;
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Feature specific call to check if it is supported by the system.
- *
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval TRUE Feature is supported.
- * @retval FALSE Feature is not supported.
- *
- */
-typedef BOOLEAN F_CPU_FEATURE_IS_ENABLED (
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_CPU_FEATURE_IS_ENABLED *PF_CPU_FEATURE_IS_ENABLED;
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * The feature's main entry point for enablement.
- *
- * @param[in] EntryPoint Timepoint designator.
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @return Family specific error value.
- *
- */
-typedef AGESA_STATUS F_CPU_FEATURE_INITIALIZE (
- IN UINT64 EntryPoint,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_CPU_FEATURE_INITIALIZE *PF_CPU_FEATURE_INITIALIZE;
-
-
-/**
- * Generic feature descriptor
- */
-typedef struct {
- DISPATCHABLE_CPU_FEATURES Feature; ///< Enumerated feature ID
- UINT64 EntryPoint; ///< Timepoint designator
- PF_CPU_FEATURE_IS_ENABLED IsEnabled; ///< Pointer to the function that checks if the feature is supported
- PF_CPU_FEATURE_INITIALIZE InitializeFeature; ///< Pointer to the function that enables the feature
-} CPU_FEATURE_DESCRIPTOR;
-
-/**
- * Table descriptor for the installed features.
- */
-typedef struct {
- UINT8 NumberOfFeats; ///< Number of valid entries in the table.
- CPU_FEATURE_DESCRIPTOR *FeatureList; ///< Pointer to the first element in the array.
-} CPU_FEATURE_TABLE;
-
-/*----------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *----------------------------------------------------------------------------------------
- */
-
-BOOLEAN
-IsFeatureEnabled (
- IN DISPATCHABLE_CPU_FEATURES Feature,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-DispatchCpuFeatures (
- IN UINT64 EntryPoint,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-BOOLEAN
-IsNonCoherentHt1 (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif // _CPU_FEATURES_H_
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuHtAssist.c b/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuHtAssist.c
deleted file mode 100644
index c0c3e0a..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuHtAssist.c
+++ /dev/null
@@ -1,357 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU HT Assist Initialization functions.
- *
- * Contains code for doing probe filter initialization.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Topology.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuLateInit.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuServices.h"
-#include "GeneralServices.h"
-#include "cpuFeatures.h"
-#include "cpuHtAssist.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_CPU_FEATURE_CPUHTASSIST_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-extern CPU_FAMILY_SUPPORT_TABLE HtAssistFamilyServiceTable;
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Should HT Assist be enabled
- *
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval TRUE HT Assist is supported.
- * @retval FALSE HT Assist cannot be enabled.
- *
- */
-BOOLEAN
-STATIC
-IsHtAssistEnabled (
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- BOOLEAN IsEnabled;
- UINT32 CpuCount;
- UINT32 Socket;
- AP_MAILBOXES ApMailboxes;
- HT_ASSIST_FAMILY_SERVICES *FamilyServices;
-
- IsEnabled = FALSE;
- if (PlatformConfig->PlatformProfile.UseHtAssist ||
- PlatformConfig->PlatformProfile.UseAtmMode) {
- CpuCount = GetNumberOfProcessors (StdHeader);
- ASSERT (CpuCount != 0);
-
- if (CpuCount == 1) {
- GetApMailbox (&ApMailboxes.ApMailInfo.Info, StdHeader);
- if (ApMailboxes.ApMailInfo.Fields.ModuleType != 0) {
- IsEnabled = TRUE;
- }
- } else if (CpuCount > 1) {
- IsEnabled = TRUE;
- }
- if (IsEnabled) {
- for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
- if (IsProcessorPresent (Socket, StdHeader)) {
- GetFeatureServicesOfSocket (&HtAssistFamilyServiceTable, Socket, &FamilyServices, StdHeader);
- if ((FamilyServices == NULL) || !FamilyServices->IsHtAssistSupported (FamilyServices, Socket, StdHeader)) {
- IsEnabled = FALSE;
- break;
- }
- }
- }
- }
- }
- return IsEnabled;
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Enable the HT Assist feature.
- *
- * HT Assist initialization requires the following series of steps.
- * -# Disable Cache on @b all cores.
- * -# Initialize Probe Filter PCI regs
- * -# Save L3 Scrub Rate
- * -# On each node:
- * -# Turn off L3Scrubber and Disable L3 cache
- * -# On each node:
- * -# Enable probe filter
- * -# On each node:
- * -# Enable L3 cache and turn on Scrubber.
- * -# Restore L3 Scrub Rate
- * -# Enable Cache on @b all cores.
- *
- * @param[in] EntryPoint Timepoint designator.
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval AGESA_SUCCESS HT Assist feature is running optimally.
- * @retval AGESA_WARNING HT Assist feature is not running optimally.
- *
- */
-AGESA_STATUS
-STATIC
-InitializeHtAssistFeature (
- IN UINT64 EntryPoint,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 CpuCount;
- UINT32 Socket;
- AGESA_STATUS AgesaStatus;
- AP_MAILBOXES ApMailboxes;
- AP_EXE_PARAMS ApParams;
- UINT32 Scrubbers[MAX_SOCKETS_SUPPORTED][L3_SCRUBBER_CONTEXT_ARRAY_SIZE];
- HT_ASSIST_FAMILY_SERVICES *FamilyServices[MAX_SOCKETS_SUPPORTED];
-
- AgesaStatus = AGESA_SUCCESS;
-
- IDS_HDT_CONSOLE (CPU_TRACE, " HT assist is enabled\n");
-
- // There are many family service call outs. Initialize the family service array while
- // cache is still enabled.
- for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) {
- if (IsProcessorPresent (Socket, StdHeader)) {
- GetFeatureServicesOfSocket (&HtAssistFamilyServiceTable, Socket, &FamilyServices[Socket], StdHeader);
- } else {
- FamilyServices[Socket] = NULL;
- }
- }
-
- if (EntryPoint == CPU_FEAT_AFTER_POST_MTRR_SYNC) {
- // Check for optimal settings
- GetApMailbox (&ApMailboxes.ApMailInfo.Info, StdHeader);
- CpuCount = GetNumberOfProcessors (StdHeader);
- if (((CpuCount == 1) && (ApMailboxes.ApMailInfo.Fields.ModuleType == 1)) ||
- ((CpuCount == 2) && (ApMailboxes.ApMailInfo.Fields.ModuleType == 0))) {
- for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
- if (FamilyServices[Socket] != NULL) {
- if (FamilyServices[Socket]->IsNonOptimalConfig (FamilyServices[Socket], Socket, StdHeader)) {
- // Non-optimal settings. Log an event.
- AgesaStatus = AGESA_WARNING;
- PutEventLog (AgesaStatus, CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG, 0, 0, 0, 0, StdHeader);
- break;
- }
- }
- }
- }
- } else {
- // Disable the scrubbers.
- for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
- if (FamilyServices[Socket] != NULL) {
- FamilyServices[Socket]->GetL3ScrubCtrl (FamilyServices[Socket], Socket, &Scrubbers[Socket][0], StdHeader);
- }
- }
-
- // Wait for 40us
- WaitMicroseconds ((UINT32) 40, StdHeader);
-
- // Run DisableAllCaches on AP cores.
- ApParams.StdHeader = *StdHeader;
- ApParams.FunctionNumber = AP_LATE_TASK_DISABLE_CACHE;
- ApParams.RelatedDataBlock = NULL;
- ApParams.RelatedBlockLength = 0;
- RunLateApTaskOnAllAPs (&ApParams, StdHeader);
-
- // Run DisableAllCaches on core 0.
- DisableAllCaches (&ApParams);
-
- // Family hook before initialization.
- for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
- if (FamilyServices[Socket] != NULL) {
- FamilyServices[Socket]->HookBeforeInit (FamilyServices[Socket], Socket, StdHeader);
- }
- }
-
- // Activate Probe Filter & ATM mode.
- for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
- if (FamilyServices[Socket] != NULL) {
- if (PlatformConfig->PlatformProfile.UseHtAssist) {
- FamilyServices[Socket]->HtAssistInit (FamilyServices[Socket], Socket, StdHeader);
- }
- if (PlatformConfig->PlatformProfile.UseAtmMode) {
- FamilyServices[Socket]->AtmModeInit (FamilyServices[Socket], Socket, StdHeader);
- }
- }
- }
-
- // Family hook after initialization.
- for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
- if (FamilyServices[Socket] != NULL) {
- FamilyServices[Socket]->HookAfterInit (FamilyServices[Socket], Socket, StdHeader);
- }
- }
-
- // Run EnableAllCaches on core 0.
- EnableAllCaches (&ApParams);
-
- // Run EnableAllCaches on every core.
- ApParams.FunctionNumber = AP_LATE_TASK_ENABLE_CACHE;
- RunLateApTaskOnAllAPs (&ApParams, StdHeader);
-
- // Restore the scrubbers.
- for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
- if (FamilyServices[Socket] != NULL) {
- FamilyServices[Socket]->SetL3ScrubCtrl (FamilyServices[Socket], Socket, &Scrubbers[Socket][0], StdHeader);
- }
- }
- }
-
- return AgesaStatus;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * Disable all the caches on current core.
- *
- * @param[in] ApExeParams Handle to config for library and services.
- *
- * @retval AGESA_SUCCESS Always succeeds.
- *
- */
-AGESA_STATUS
-DisableAllCaches (
- IN AP_EXE_PARAMS *ApExeParams
- )
-{
- UINT32 CR0Data;
- HT_ASSIST_FAMILY_SERVICES *FamilyServices;
-
- GetFeatureServicesOfCurrentCore (&HtAssistFamilyServiceTable, &FamilyServices, &ApExeParams->StdHeader);
-
- FamilyServices->HookDisableCache (FamilyServices, &ApExeParams->StdHeader);
-
- // Disable cache through CR0.
- LibAmdReadCpuReg (0, &CR0Data);
- CR0Data |= (0x60000000);
- LibAmdWriteCpuReg (0, CR0Data);
-
- // Execute wbinvd
- LibAmdWriteBackInvalidateCache ();
-
- return AGESA_SUCCESS;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * Enable all the caches on current core.
- *
- * @param[in] ApExeParams Handle to config for library and services.
- *
- * @retval AGESA_SUCCESS Always succeeds.
- *
- */
-AGESA_STATUS
-EnableAllCaches (
- IN AP_EXE_PARAMS *ApExeParams
- )
-{
- UINT32 CR0Data;
- HT_ASSIST_FAMILY_SERVICES *FamilyServices;
-
- // Enable cache through CR0.
- LibAmdReadCpuReg (0, &CR0Data);
- CR0Data &= ~(0x60000000);
- LibAmdWriteCpuReg (0, CR0Data);
-
- GetFeatureServicesOfCurrentCore (&HtAssistFamilyServiceTable, &FamilyServices, &ApExeParams->StdHeader);
-
- FamilyServices->HookEnableCache (FamilyServices, &ApExeParams->StdHeader);
-
- return AGESA_SUCCESS;
-}
-
-CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHtAssist =
-{
- HtAssist,
- (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_INIT_MID_END | CPU_FEAT_S3_LATE_RESTORE_END),
- IsHtAssistEnabled,
- InitializeHtAssistFeature
-};
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuHtAssist.h b/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuHtAssist.h
deleted file mode 100644
index 74e05f1..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuHtAssist.h
+++ /dev/null
@@ -1,301 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD AGESA CPU HT Assist Function declarations.
- *
- * Contains code that declares the AGESA CPU Probe filter related APIs
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/Feature
- * @e \$Revision: 36567 $ @e \$Date: 2010-08-21 02:35:15 +0800 (Sat, 21 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPU_HT_ASSIST_H_
-#define _CPU_HT_ASSIST_H_
-
-#include "Filecode.h"
-/*----------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *----------------------------------------------------------------------------------------
- */
-// Forward declaration needed for multi-structure mutual references
-AGESA_FORWARD_DECLARATION (HT_ASSIST_FAMILY_SERVICES);
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-#define AP_LATE_TASK_DISABLE_CACHE (0x00000000 | PROC_CPU_FEATURE_CPUHTASSIST_FILECODE)
-#define AP_LATE_TASK_ENABLE_CACHE (0x00010000 | PROC_CPU_FEATURE_CPUHTASSIST_FILECODE)
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-#define L3_SCRUBBER_CONTEXT_ARRAY_SIZE 4
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family specific call to check if HT Assist is supported.
- *
- * @param[in] HtAssistServices HT Assist family services.
- * @param[in] Socket Processor socket to check.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval TRUE HT Assist is supported.
- * @retval FALSE HT Assist is not supported.
- *
- */
-typedef BOOLEAN F_HT_ASSIST_IS_SUPPORTED (
- IN HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
- IN UINT32 Socket,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_HT_ASSIST_IS_SUPPORTED *PF_HT_ASSIST_IS_SUPPORTED;
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family specific hook before HT Assist is initialized.
- *
- * @param[in] HtAssistServices HT Assist family services.
- * @param[in] Socket Processor socket to check.
- * @param[in] StdHeader Config Handle for library, services.
- *
- */
-typedef VOID F_HT_ASSIST_BEFORE_INIT (
- IN HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
- IN UINT32 Socket,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_HT_ASSIST_BEFORE_INIT *PF_HT_ASSIST_BEFORE_INIT;
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family specific call to disable cache.
- *
- * @param[in] HtAssistServices HT Assist family services.
- * @param[in] StdHeader Config Handle for library, services.
- *
- */
-typedef VOID F_HT_ASSIST_DISABLE_CACHE (
- IN HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_HT_ASSIST_DISABLE_CACHE *PF_HT_ASSIST_DISABLE_CACHE;
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family specific call to disable cache.
- *
- * @param[in] HtAssistServices HT Assist family services.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @return Family specific error value.
- *
- */
-typedef VOID F_HT_ASSIST_ENABLE_CACHE (
- IN HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_HT_ASSIST_ENABLE_CACHE *PF_HT_ASSIST_ENABLE_CACHE;
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family specific call to Initialize HT Assist
- *
- * @param[in] HtAssistServices HT Assist family services.
- * @param[in] Socket Processor socket to enable.
- * @param[in] StdHeader Config Handle for library, services.
- *
- */
-typedef VOID F_HT_ASSIST_INIT (
- IN HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
- IN UINT32 Socket,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_HT_ASSIST_INIT *PF_HT_ASSIST_INIT;
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family specific call to Initialize ATM mode
- *
- * @param[in] HtAssistServices HT Assist family services.
- * @param[in] Socket Processor socket to enable.
- * @param[in] StdHeader Config Handle for library, services.
- *
- */
-typedef VOID F_ATM_MODE_INIT (
- IN HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
- IN UINT32 Socket,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_ATM_MODE_INIT *PF_ATM_MODE_INIT;
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family specific hook after HT Assist is initialized.
- *
- * @param[in] HtAssistServices HT Assist family services.
- * @param[in] Socket Processor socket to check.
- * @param[in] StdHeader Config Handle for library, services.
- *
- */
-typedef VOID F_HT_ASSIST_AFTER_INIT (
- IN HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
- IN UINT32 Socket,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_HT_ASSIST_AFTER_INIT *PF_HT_ASSIST_AFTER_INIT;
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family specific call to save the L3 scrubber.
- *
- * @param[in] HtAssistServices HT Assist family services.
- * @param[in] Socket Processor socket to check.
- * @param[in] ScrubSettings Location to store current L3 scrubber settings.
- * @param[in] StdHeader Config Handle for library, services.
- *
- */
-typedef VOID F_HT_ASSIST_GET_L3_SCRUB_CTRL (
- IN HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
- IN UINT32 Socket,
- IN UINT32 ScrubSettings[L3_SCRUBBER_CONTEXT_ARRAY_SIZE],
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_HT_ASSIST_GET_L3_SCRUB_CTRL *PF_HT_ASSIST_GET_L3_SCRUB_CTRL;
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family specific call to restore the L3 scrubber.
- *
- * @param[in] HtAssistServices HT Assist family services.
- * @param[in] Socket Processor socket to check.
- * @param[in] ScrubSettings Contains L3 scrubber settings to restore.
- * @param[in] StdHeader Config Handle for library, services.
- *
- */
-typedef VOID F_HT_ASSIST_SET_L3_SCRUB_CTRL (
- IN HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
- IN UINT32 Socket,
- IN UINT32 ScrubSettings[L3_SCRUBBER_CONTEXT_ARRAY_SIZE],
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_HT_ASSIST_SET_L3_SCRUB_CTRL *PF_HT_ASSIST_SET_L3_SCRUB_CTRL;
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family specific call to provide non_optimal HT Assist support
- *
- * @param[in] HtAssistServices HT Assist family services.
- * @param[in] Socket Processor socket to check.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @return TRUE The system may be running with non-optimal settings.
- * @return FALSE The system may is running optimally.
- *
- */
-typedef BOOLEAN F_HT_ASSIST_IS_NONOPTIMAL (
- IN HT_ASSIST_FAMILY_SERVICES *HtAssistServices,
- IN UINT32 Socket,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_HT_ASSIST_IS_NONOPTIMAL *PF_HT_ASSIST_IS_NONOPTIMAL;
-
-
-/**
- * Provide the interface to the HT Assist Family Specific Services.
- *
- * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
- * Each supported Family must provide an implementation for all methods in this interface, even if the
- * implementation is a CommonReturn().
- */
-struct _HT_ASSIST_FAMILY_SERVICES {
- UINT16 Revision; ///< Interface version
- // Public Methods.
- PF_HT_ASSIST_IS_SUPPORTED IsHtAssistSupported; ///< Method: Check if HT Assist is supported.
- PF_HT_ASSIST_INIT HtAssistInit; ///< Method: Enable HT Assist.
- PF_ATM_MODE_INIT AtmModeInit; ///< Method: Enable ATM Mode
- PF_HT_ASSIST_GET_L3_SCRUB_CTRL GetL3ScrubCtrl; ///< Method: Save/disable the L3 scrubber.
- PF_HT_ASSIST_SET_L3_SCRUB_CTRL SetL3ScrubCtrl; ///< Method: Restore the L3 scrubber.
- PF_HT_ASSIST_BEFORE_INIT HookBeforeInit; ///< Method: Hook before enabling HT Assist.
- PF_HT_ASSIST_AFTER_INIT HookAfterInit; ///< Method: Hook after enabling HT Assist.
- PF_HT_ASSIST_DISABLE_CACHE HookDisableCache; ///< Method: Core hook just before disabling cache.
- PF_HT_ASSIST_ENABLE_CACHE HookEnableCache; ///< Method: Core hook just after enabling cache.
- PF_HT_ASSIST_IS_NONOPTIMAL IsNonOptimalConfig; ///< Method: Check if HT Assist is running optimally.
-};
-
-
-/*----------------------------------------------------------------------------------------
- * F U N C T I O N S P R O T O T Y P E
- *----------------------------------------------------------------------------------------
- */
-AGESA_STATUS
-DisableAllCaches (
- IN AP_EXE_PARAMS *ApExeParams
- );
-
-AGESA_STATUS
-EnableAllCaches (
- IN AP_EXE_PARAMS *ApExeParams
- );
-
-#endif // _CPU_HT_ASSIST_H_
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuHwC1e.c b/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuHwC1e.c
deleted file mode 100644
index b5b62c7..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuHwC1e.c
+++ /dev/null
@@ -1,175 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD AGESA CPU HW C1e feature support code.
- *
- * Contains code that declares the AGESA CPU C1e related APIs
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/Feature
- * @e \$Revision: 37157 $ @e \$Date: 2010-09-01 03:24:07 +0800 (Wed, 01 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuApicUtilities.h"
-#include "cpuServices.h"
-#include "GeneralServices.h"
-#include "cpuFamilyTranslation.h"
-#include "Topology.h"
-#include "cpuFeatures.h"
-#include "cpuHwC1e.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FEATURE_CPUHWC1E_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-extern CPU_FAMILY_SUPPORT_TABLE HwC1eFamilyServiceTable;
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Should hardware C1e be enabled
- *
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval TRUE HW C1e is supported.
- * @retval FALSE HW C1e cannot be enabled.
- *
- */
-BOOLEAN
-STATIC
-IsHwC1eFeatureEnabled (
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- BOOLEAN IsEnabled;
- AP_MAILBOXES ApMailboxes;
- HW_C1E_FAMILY_SERVICES *FamilyServices;
-
- ASSERT (PlatformConfig->C1eMode < MaxC1eMode);
- IsEnabled = FALSE;
- if ((PlatformConfig->C1eMode == C1eModeHardware) || (PlatformConfig->C1eMode == C1eModeHardwareSoftwareDeprecated)) {
- ASSERT (PlatformConfig->C1ePlatformData < 0x10000);
- ASSERT (PlatformConfig->C1ePlatformData != 0);
- if ((PlatformConfig->C1ePlatformData != 0) && (PlatformConfig->C1ePlatformData < 0xFFFE)) {
- if (!IsNonCoherentHt1 (StdHeader)) {
- if (GetNumberOfProcessors (StdHeader) == 1) {
- GetApMailbox (&ApMailboxes.ApMailInfo.Info, StdHeader);
- if (ApMailboxes.ApMailInfo.Fields.ModuleType == 0) {
- GetFeatureServicesOfCurrentCore (&HwC1eFamilyServiceTable, &FamilyServices, StdHeader);
- if (FamilyServices != NULL) {
- IsEnabled = FamilyServices->IsHwC1eSupported (FamilyServices, StdHeader);
- }
- }
- }
- }
- }
- }
- return IsEnabled;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Enable Hardware C1e
- *
- * @param[in] EntryPoint Timepoint designator.
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @return The most severe status of any family specific service.
- *
- */
-AGESA_STATUS
-STATIC
-InitializeHwC1eFeature (
- IN UINT64 EntryPoint,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_STATUS CalledStatus;
- AGESA_STATUS AgesaStatus;
- HW_C1E_FAMILY_SERVICES *FamilyServices;
-
- AgesaStatus = AGESA_SUCCESS;
-
- IDS_HDT_CONSOLE (CPU_TRACE, " HW C1e is enabled\n");
-
- if (IsWarmReset (StdHeader)) {
- GetFeatureServicesOfCurrentCore (&HwC1eFamilyServiceTable, &FamilyServices, StdHeader);
- CalledStatus = FamilyServices->InitializeHwC1e (FamilyServices, EntryPoint, PlatformConfig, StdHeader);
- if (CalledStatus > AgesaStatus) {
- AgesaStatus = CalledStatus;
- }
- }
- return AgesaStatus;
-}
-
-CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHwC1e =
-{
- HardwareC1e,
- CPU_FEAT_AFTER_PM_INIT,
- IsHwC1eFeatureEnabled,
- InitializeHwC1eFeature
-};
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuHwC1e.h b/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuHwC1e.h
deleted file mode 100644
index bad0956..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuHwC1e.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD AGESA CPU HW C1e Functions declarations.
- *
- * Contains code that declares the AGESA CPU C1e related APIs
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/Feature
- * @e \$Revision: 36567 $ @e \$Date: 2010-08-21 02:35:15 +0800 (Sat, 21 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPU_HW_C1E_H_
-#define _CPU_HW_C1E_H_
-
-/*----------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *----------------------------------------------------------------------------------------
- */
-// Forward declaration needed for multi-structure mutual references
-AGESA_FORWARD_DECLARATION (HW_C1E_FAMILY_SERVICES);
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family specific call to check if hardware C1e is supported.
- *
- * @param[in] HwC1eServices Hardware C1e services.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval TRUE HW C1e is supported.
- * @retval FALSE HW C1e is not supported.
- *
- */
-typedef BOOLEAN F_HW_C1E_IS_SUPPORTED (
- IN HW_C1E_FAMILY_SERVICES *HwC1eServices,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_HW_C1E_IS_SUPPORTED *PF_HW_C1E_IS_SUPPORTED;
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family specific call to enable hardware C1e.
- *
- * @param[in] HwC1eServices Hardware C1e services.
- * @param[in] EntryPoint Timepoint designator.
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @return Family specific error value.
- *
- */
-typedef AGESA_STATUS F_HW_C1E_INIT (
- IN HW_C1E_FAMILY_SERVICES *HwC1eServices,
- IN UINT64 EntryPoint,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_HW_C1E_INIT *PF_HW_C1E_INIT;
-
-/**
- * Provide the interface to the hardware C1e Family Specific Services.
- *
- * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
- * Each supported Family must provide an implementation for all methods in this interface, even if the
- * implementation is a CommonReturn().
- */
-struct _HW_C1E_FAMILY_SERVICES {
- UINT16 Revision; ///< Interface version
- // Public Methods.
- PF_HW_C1E_IS_SUPPORTED IsHwC1eSupported; ///< Method: Family specific call to check if hardware C1e is supported.
- PF_HW_C1E_INIT InitializeHwC1e; ///< Method: Family specific call to enable hardware C1e.
-};
-
-
-/*----------------------------------------------------------------------------------------
- * F U N C T I O N S P R O T O T Y P E
- *----------------------------------------------------------------------------------------
- */
-
-#endif // _CPU_HW_C1E_H_
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuIoCstate.c b/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuIoCstate.c
deleted file mode 100644
index 8893415..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuIoCstate.c
+++ /dev/null
@@ -1,209 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD AGESA CPU IO Cstate function declarations.
- *
- * Contains code that declares the AGESA CPU IO Cstate related APIs
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/Feature
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "cpuFeatures.h"
-#include "cpuIoCstate.h"
-#include "cpuServices.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuApicUtilities.h"
-#include "OptionMultiSocket.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FEATURE_CPUIOCSTATE_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-VOID
-STATIC
-EnableIoCstateOnSocket (
- IN VOID *EntryPoint,
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams
- );
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-extern CPU_FAMILY_SUPPORT_TABLE IoCstateFamilyServiceTable;
-extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Should IO Cstate be enabled
- * If all processors support IO Cstate, return TRUE. Otherwise, return FALSE
- *
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval TRUE IO Cstate is supported.
- * @retval FALSE IO Cstate cannot be enabled.
- *
- */
-BOOLEAN
-STATIC
-IsIoCstateFeatureSupported (
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Socket;
- BOOLEAN IsSupported;
- IO_CSTATE_FAMILY_SERVICES *IoCstateServices;
-
- IsSupported = FALSE;
- if ((PlatformConfig->CStateIoBaseAddress != 0) && (PlatformConfig->CStateIoBaseAddress <= 0xFFF8)) {
- for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
- if (IsProcessorPresent (Socket, StdHeader)) {
- GetFeatureServicesOfSocket (&IoCstateFamilyServiceTable, Socket, &IoCstateServices, StdHeader);
- if (IoCstateServices != NULL) {
- if (IoCstateServices->IsIoCstateSupported (IoCstateServices, Socket, StdHeader)) {
- IsSupported = TRUE;
- } else {
- // Stop checking remaining socket(s) once we find one that does not support IO Cstates
- IsSupported = FALSE;
- break;
- }
- } else {
- // Exit the for loop if we found a socket that does not have the IO Cstates feature installed
- IsSupported = FALSE;
- break;
- }
- }
- }
- }
- return IsSupported;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Enable IO Cstate feature
- *
- * @param[in] EntryPoint Timepoint designator.
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval AGESA_SUCCESS Always succeeds.
- *
- */
-AGESA_STATUS
-STATIC
-InitializeIoCstateFeature (
- IN UINT64 EntryPoint,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AP_TASK TaskPtr;
- AMD_CPU_EARLY_PARAMS CpuEarlyParams;
-
- IDS_HDT_CONSOLE (CPU_TRACE, " IO C-state is enabled\n");
-
- CpuEarlyParams.PlatformConfig = *PlatformConfig;
-
- TaskPtr.FuncAddress.PfApTaskIC = EnableIoCstateOnSocket;
- TaskPtr.DataTransfer.DataSizeInDwords = 2;
- TaskPtr.DataTransfer.DataPtr = &EntryPoint;
- TaskPtr.DataTransfer.DataTransferFlags = 0;
- TaskPtr.ExeFlags = PASS_EARLY_PARAMS;
- OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, &CpuEarlyParams);
-
- return AGESA_SUCCESS;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * 'Local' core 0 task to enable IO Cstate on it's socket.
- *
- * @param[in] EntryPoint Timepoint designator.
- * @param[in] StdHeader Config Handle for library, services.
- * @param[in] CpuEarlyParams Service parameters.
- *
- */
-VOID
-STATIC
-EnableIoCstateOnSocket (
- IN VOID *EntryPoint,
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams
- )
-{
- IO_CSTATE_FAMILY_SERVICES *FamilyServices;
-
- GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, &FamilyServices, StdHeader);
- FamilyServices->InitializeIoCstate (FamilyServices,
- *((UINT64 *) EntryPoint),
- &CpuEarlyParams->PlatformConfig,
- StdHeader);
-}
-
-CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate =
-{
- IoCstate,
- (CPU_FEAT_AFTER_PM_INIT),
- IsIoCstateFeatureSupported,
- InitializeIoCstateFeature
-};
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuIoCstate.h b/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuIoCstate.h
deleted file mode 100644
index 42d7f7c..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuIoCstate.h
+++ /dev/null
@@ -1,285 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD AGESA CPU IO Cstate feature support code.
- *
- * Contains code that declares the AGESA CPU IO Cstate related APIs
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/Feature
- * @e \$Revision: 36567 $ @e \$Date: 2010-08-21 02:35:15 +0800 (Sat, 21 Aug 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPU_IO_CSTATE_H_
-#define _CPU_IO_CSTATE_H_
-
-/*----------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *----------------------------------------------------------------------------------------
- */
-// Forward declaration needed for multi-structure mutual references
-AGESA_FORWARD_DECLARATION (IO_CSTATE_FAMILY_SERVICES);
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-// Defines for ACPI C-State Objects
-#define CST_NAME__ '_'
-#define CST_NAME_C 'C'
-#define CST_NAME_S 'S'
-#define CST_NAME_T 'T'
-#define CST_LENGTH (CST_BODY_SIZE - 1)
-#define CST_NUM_OF_ELEMENTS 0x02
-#define CST_COUNT 0x01
-#define CST_PKG_LENGTH (CST_BODY_SIZE - 6) // CST_BODY_SIZE - PkgHeader - Count Buffer
-#define CST_PKG_ELEMENTS 0x04
-#define CST_SUBPKG_LENGTH 0x14
-#define CST_SUBPKG_ELEMENTS 0x0A
-#define CST_GDR_LENGTH 0x000C
-#define CST_C1_TYPE 0x01
-#define CST_C2_TYPE 0x02
-
-#define CSD_NAME_D 'D'
-#define CSD_COORD_TYPE_HW_ALL 0xFE
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-/* AML code definition */
-
-/// CST Header
-typedef struct _CST_HEADER_STRUCT {
- UINT8 NameOpcode; ///< Name Opcode
- UINT8 CstName_a__; ///< String "_"
- UINT8 CstName_a_C; ///< String "C"
- UINT8 CstName_a_S; ///< String "S"
- UINT8 CstName_a_T; ///< String "T"
-} CST_HEADER_STRUCT;
-#define CST_HEADER_SIZE 5
-
-/// CST Body
-typedef struct _CST_BODY_STRUCT {
- UINT8 PkgOpcode; ///< Package Opcode
- UINT8 PkgLength; ///< Package Length
- UINT8 PkgElements; ///< Number of Elements
- UINT8 BytePrefix; ///< Byte Prefix Opcode
- UINT8 Count; ///< Number of Cstate info packages
- UINT8 PkgOpcode2; ///< Package Opcode
- UINT8 PkgLength2; ///< Package Length
- UINT8 PkgElements2; ///< Number of Elements
- UINT8 BufferOpcode; ///< Buffer Opcode
- UINT8 BufferLength; ///< Buffer Length
- UINT8 BufferElements; ///< Number of Elements
- UINT8 BufferOpcode2; ///< Buffer Opcode
- UINT8 GdrOpcode; ///< Generic Register Descriptor Opcode
- UINT16 GdrLength; ///< Descriptor Length
- UINT8 AddrSpaceId; ///< Address Space ID
- UINT8 RegBitWidth; ///< Register Bit Width
- UINT8 RegBitOffset; ///< Register Bit Offset
- UINT8 AddressSize; ///< Address Size
- UINT64 RegisterAddr; ///< Register Address
- UINT16 EndTag; ///< End Tag Descriptor
- UINT8 BytePrefix2; ///< Byte Prefix Opcode
- UINT8 Type; ///< Type
- UINT8 WordPrefix; ///< Word Prefix Opcode
- UINT16 Latency; ///< Latency
- UINT8 DWordPrefix; ///< Dword Prefix Opcode
- UINT32 Power; ///< Power
-} CST_BODY_STRUCT;
-#define CST_BODY_SIZE 39
-
-/// CSD Header
-typedef struct _CSD_HEADER_STRUCT {
- UINT8 NameOpcode; ///< Name Opcode
- UINT8 CsdName_a__; ///< String "_"
- UINT8 CsdName_a_C; ///< String "C"
- UINT8 CsdName_a_S; ///< String "S"
- UINT8 CsdName_a_D; ///< String "D"
-} CSD_HEADER_STRUCT;
-#define CSD_HEADER_SIZE 5
-
-/// CSD Body
-typedef struct _CSD_BODY_STRUCT {
- UINT8 PkgOpcode; ///< Package Opcode
- UINT8 PkgLength; ///< Package Length
- UINT8 PkgElements; ///< Number of Elements
- UINT8 PkgOpcode2; ///< Package Opcode
- UINT8 PkgLength2; ///< Package Length
- UINT8 PkgElements2; ///< Number of Elements
- UINT8 BytePrefix; ///< Byte Prefix Opcode
- UINT8 NumEntries; ///< Number of Entries
- UINT8 BytePrefix2; ///< Byte Prefix Opcode
- UINT8 Revision; ///< Revision
- UINT8 DWordPrefix; ///< DWord Prefix Opcode
- UINT32 Domain; ///< Dependency Domain Number
- UINT8 DWordPrefix2; ///< DWord Prefix Opcode
- UINT32 CoordType; ///< Coordination Type
- UINT8 DWordPrefix3; ///< Dword Prefix Opcode
- UINT32 NumProcessors; ///< Number of Processors in the Domain
- UINT8 DWordPrefix4; ///< Dword Prefix Opcode
- UINT32 Index; ///< Index of C-State entry for which dependency applies
-} CSD_BODY_STRUCT;
-#define CSD_BODY_SIZE 30
-
-/// input for create _CST
-typedef struct _ACPI_CST_CREATE_INPUT {
- IO_CSTATE_FAMILY_SERVICES *IoCstateServices; ///< Family service of IoCstate
- UINT8 LocalApicId; ///< Local Apic for create _CST
- VOID **PstateAcpiBufferPtr; ///< buffer for fill _CST
-} ACPI_CST_CREATE_INPUT ;
-
-/// input for get _CST
-typedef struct _ACPI_CST_GET_INPUT {
- IO_CSTATE_FAMILY_SERVICES *IoCstateServices; ///< Family service of IoCstate
- PLATFORM_CONFIGURATION *PlatformConfig; ///< platform config
- UINT32 *CStateAcpiObjSizePtr; ///< Point to size of _CST
-} ACPI_CST_GET_INPUT ;
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family specific call to check if IO Cstate is supported.
- *
- * @param[in] IoCstateServices IO Cstate services.
- * @param[in] Socket Zero-based socket number.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval TRUE IO Cstate is supported.
- * @retval FALSE IO Cstate is not supported.
- *
- */
-typedef BOOLEAN F_IO_CSTATE_IS_SUPPORTED (
- IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
- IN UINT32 Socket,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family specific call to enable IO Cstate.
- *
- * @param[in] IoCstateServices IO Cstate services.
- * @param[in] EntryPoint Timepoint designator.
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @return Family specific error value.
- *
- */
-typedef AGESA_STATUS F_IO_CSTATE_INIT (
- IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
- IN UINT64 EntryPoint,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family specific call to return the size of ACPI C-State Objects
- *
- * @param[in] IoCstateServices IO Cstate services.
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval Size of ACPI C-State Objects
- *
- */
-typedef UINT32 F_IO_CSTATE_GET_CST_SIZE (
- IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family specific call to create ACPI C-State Objects
- *
- * @param[in] IoCstateServices IO Cstate services.
- * @param[in] LocalApicId Local Apic Id
- * @param[in, out] PstateAcpiBufferPtr Pointer to Pstate data buffer
- * @param[in] StdHeader Config Handle for library, services.
- *
- */
-typedef VOID F_IO_CSTATE_CREATE_CST (
- IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
- IN UINT8 LocalApicId,
- IN OUT VOID **PstateAcpiBufferPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family specific call to check whether CSD object should be created.
- *
- * @param[in] IoCstateServices IO Cstate services.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval TRUE CSD Object should be created.
- * @retval FALSE CSD Object should not be created.
- *
- */
-typedef BOOLEAN F_IO_CSTATE_IS_CSD_GENERATED (
- IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method
-typedef F_IO_CSTATE_IS_SUPPORTED *PF_IO_CSTATE_IS_SUPPORTED;
-typedef F_IO_CSTATE_INIT *PF_IO_CSTATE_INIT;
-typedef F_IO_CSTATE_GET_CST_SIZE *PF_IO_CSTATE_GET_CST_SIZE;
-typedef F_IO_CSTATE_CREATE_CST *PF_IO_CSTATE_CREATE_CST;
-typedef F_IO_CSTATE_IS_CSD_GENERATED *PF_IO_CSTATE_IS_CSD_GENERATED;
-
-/**
- * Provide the interface to the IO Cstate Family Specific Services.
- *
- * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
- * Each supported Family must provide an implementation for all methods in this interface, even if the
- * implementation is a CommonReturn().
- */
-struct _IO_CSTATE_FAMILY_SERVICES {
- UINT16 Revision; ///< Interface version
- // Public Methods.
- PF_IO_CSTATE_IS_SUPPORTED IsIoCstateSupported; ///< Method: Family specific call to check if IO Cstate is supported.
- PF_IO_CSTATE_INIT InitializeIoCstate; ///< Method: Family specific call to enable IO Cstate
- PF_IO_CSTATE_GET_CST_SIZE GetAcpiCstObj; ///< Method: Family specific call to return the size of ACPI CST objects.
- PF_IO_CSTATE_CREATE_CST CreateAcpiCstObj; ///< Method: Family specific call to create ACPI CST object
- PF_IO_CSTATE_IS_CSD_GENERATED IsCsdObjGenerated; ///< Method: Family specific call to check whether CSD Object should be created.
-};
-
-#endif // _CPU_IO_CSTATE_H_
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuLowPwrPstate.c b/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuLowPwrPstate.c
deleted file mode 100644
index 0b29512..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuLowPwrPstate.c
+++ /dev/null
@@ -1,206 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD AGESA CPU create low power P-state for PROCHOT_L throttling support code.
- *
- * Contains code that declares the AGESA CPU low power P-state related APIs
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/Feature
- * @e \$Revision: 35155 $ @e \$Date: 2010-07-16 17:11:52 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuFamilyTranslation.h"
-#include "OptionMultiSocket.h"
-#include "cpuRegisters.h"
-#include "cpuApicUtilities.h"
-#include "cpuFeatures.h"
-#include "cpuLowPwrPstate.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FEATURE_CPULOWPWRPSTATE_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-VOID
-STATIC
-EnableLowPwrPstateOnSocket (
- IN VOID *EntryPoint,
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams
- );
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-extern CPU_FAMILY_SUPPORT_TABLE LowPwrPstateFamilyServiceTable;
-extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Should Low Power P-state be enabled
- * If all processors support Low Power P-state, reture TRUE, otherwise reture FALSE
- *
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval TRUE Low Power P-state is supported.
- * @retval FALSE Low Power P-state cannot be enabled.
- *
- */
-BOOLEAN
-STATIC
-IsLowPwrPstateFeatureSupported (
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Socket;
- BOOLEAN IsSupported;
- LOW_PWR_PSTATE_FAMILY_SERVICES *FamilyServices;
-
- IsSupported = FALSE;
- for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
- if (IsProcessorPresent (Socket, StdHeader)) {
- GetFeatureServicesOfSocket (&LowPwrPstateFamilyServiceTable, Socket, &FamilyServices, StdHeader);
- if (FamilyServices != NULL) {
- if (FamilyServices->IsLowPwrPstateSupported (FamilyServices, PlatformConfig, Socket, StdHeader)) {
- IsSupported = TRUE;
- } else {
- IsSupported = FALSE;
- break;
- }
- } else {
- IsSupported = FALSE;
- break;
- }
- }
- }
- IDS_OPTION_HOOK (IDS_LOW_POWER_PSTATE, &IsSupported, StdHeader);
- return IsSupported;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Enable low power P-state
- *
- * @param[in] EntryPoint Timepoint designator.
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval AGESA_SUCCESS Always succeeds.
- *
- */
-AGESA_STATUS
-STATIC
-InitializeLowPwrPstateFeature (
- IN UINT64 EntryPoint,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AP_TASK TaskPtr;
- AMD_CPU_EARLY_PARAMS CpuEarlyParams;
-
- IDS_HDT_CONSOLE (CPU_TRACE, " Low pwr P-state is enabled\n");
-
- CpuEarlyParams.PlatformConfig = *PlatformConfig;
-
- TaskPtr.FuncAddress.PfApTaskIC = EnableLowPwrPstateOnSocket;
- TaskPtr.DataTransfer.DataSizeInDwords = 2;
- TaskPtr.DataTransfer.DataPtr = &EntryPoint;
- TaskPtr.DataTransfer.DataTransferFlags = 0;
- TaskPtr.ExeFlags = PASS_EARLY_PARAMS;
- OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, &CpuEarlyParams);
-
- return AGESA_SUCCESS;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * 'Local' core 0 task to enable low power P-state
- *
- * @param[in] EntryPoint Timepoint designator.
- * @param[in] StdHeader Config Handle for library, services.
- * @param[in] CpuEarlyParams Service parameters.
- *
- */
-VOID
-STATIC
-EnableLowPwrPstateOnSocket (
- IN VOID *EntryPoint,
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams
- )
-{
- LOW_PWR_PSTATE_FAMILY_SERVICES *FamilyServices;
-
- GetFeatureServicesOfCurrentCore (&LowPwrPstateFamilyServiceTable, &FamilyServices, StdHeader);
- FamilyServices->EnableLowPwrPstate (FamilyServices,
- &CpuEarlyParams->PlatformConfig,
- *((UINT64 *) EntryPoint),
- StdHeader);
-}
-
-
-CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureLowPwrPstate =
-{
- LowPwrPstate,
- CPU_FEAT_AFTER_PM_INIT,
- IsLowPwrPstateFeatureSupported,
- InitializeLowPwrPstateFeature
-};
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuLowPwrPstate.h b/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuLowPwrPstate.h
deleted file mode 100644
index 9897bfc..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuLowPwrPstate.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD AGESA CPU create low power P-state for PROCHOT_L throttling Functions declarations.
- *
- * Contains code that declares the AGESA CPU low power P-state related APIs
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/Feature
- * @e \$Revision: 36567 $ @e \$Date: 2010-08-21 02:35:15 +0800 (Sat, 21 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPU_LOW_PWR_PSTATE_H_
-#define _CPU_LOW_PWR_PSTATE_H_
-
-/*----------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *----------------------------------------------------------------------------------------
- */
-// Forward declaration needed for multi-structure mutual references
-AGESA_FORWARD_DECLARATION (LOW_PWR_PSTATE_FAMILY_SERVICES);
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family specific call to check if Low Power P-state is supported.
- *
- * @param[in] LowPwrPstateService Low Power P-state services.
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] Socket Zero-based socket number.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval TRUE Low Power P-state is supported.
- * @retval FALSE Low Power P-state is not supported.
- *
- */
-typedef BOOLEAN F_LOW_PWR_PSTATE_IS_SUPPORTED (
- IN LOW_PWR_PSTATE_FAMILY_SERVICES *LowPwrPstateService,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN UINT32 Socket,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_LOW_PWR_PSTATE_IS_SUPPORTED *PF_LOW_PWR_PSTATE_IS_SUPPORTED;
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family specific call to enable Low Power P-state
- *
- * @param[in] LowPwrPstateService Low Power P-state services.
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] EntryPoint Timepoint designator.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @return Family specific error value.
- *
- */
-typedef AGESA_STATUS F_LOW_PWR_PSTATE_INIT (
- IN LOW_PWR_PSTATE_FAMILY_SERVICES *LowPwrPstateService,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN UINT64 EntryPoint,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_LOW_PWR_PSTATE_INIT *PF_LOW_PWR_PSTATE_INIT;
-
-/**
- * Provide the interface to the Low Power P-state Family Specific Services.
- *
- * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
- * Each supported Family must provide an implementation for all methods in this interface, even if the
- * implementation is a CommonReturn().
- */
-struct _LOW_PWR_PSTATE_FAMILY_SERVICES {
- UINT16 Revision; ///< Interface version
- // Public Methods.
- PF_LOW_PWR_PSTATE_IS_SUPPORTED IsLowPwrPstateSupported; ///< Method: Family specific call to check if Low Power P-state is supported.
- PF_LOW_PWR_PSTATE_INIT EnableLowPwrPstate; ///< Method: Family specific call to enable Low Power P-state.
-};
-
-
-/*----------------------------------------------------------------------------------------
- * F U N C T I O N S P R O T O T Y P E
- *----------------------------------------------------------------------------------------
- */
-
-#endif // _CPU_LOW_PWR_PSTATE_H_
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuMsgBasedC1e.c b/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuMsgBasedC1e.c
deleted file mode 100644
index f09b2b5..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuMsgBasedC1e.c
+++ /dev/null
@@ -1,213 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD AGESA CPU Message-based C1e feature support code.
- *
- * Contains code that declares the AGESA CPU C1e related APIs
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/Feature
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMultiSocket.h"
-#include "cpuRegisters.h"
-#include "cpuApicUtilities.h"
-#include "cpuServices.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuFeatures.h"
-#include "cpuMsgBasedC1e.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FEATURE_CPUMSGBASEDC1E_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-VOID
-STATIC
-EnableMsgC1eOnSocket (
- IN VOID *EntryPoint,
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams
- );
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-extern CPU_FAMILY_SUPPORT_TABLE MsgBasedC1eFamilyServiceTable;
-extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Should message-based C1e be enabled
- *
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval TRUE Message-based C1e is supported.
- * @retval FALSE Message-based C1e cannot be enabled.
- *
- */
-BOOLEAN
-STATIC
-IsMsgBasedC1eFeatureEnabled (
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- BOOLEAN IsEnabled;
- UINT32 Socket;
- MSG_BASED_C1E_FAMILY_SERVICES *FamilyServices;
-
- ASSERT (PlatformConfig->C1eMode < MaxC1eMode);
-
- IsEnabled = FALSE;
- if (PlatformConfig->C1eMode == C1eModeMsgBased) {
- ASSERT (PlatformConfig->C1ePlatformData < 0x10000);
- ASSERT (PlatformConfig->C1ePlatformData != 0);
- if ((PlatformConfig->C1ePlatformData != 0) && (PlatformConfig->C1ePlatformData < 0xFFFE)) {
- IsEnabled = TRUE;
- if (IsNonCoherentHt1 (StdHeader)) {
- IsEnabled = FALSE;
- } else {
- for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
- if (IsProcessorPresent (Socket, StdHeader)) {
- GetFeatureServicesOfSocket (&MsgBasedC1eFamilyServiceTable, Socket, &FamilyServices, StdHeader);
- if ((FamilyServices == NULL) || !FamilyServices->IsMsgBasedC1eSupported (FamilyServices, Socket, StdHeader)) {
- IsEnabled = FALSE;
- break;
- }
- }
- }
- }
- }
- }
- return IsEnabled;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Enable Message-based C1e
- *
- * @param[in] EntryPoint Timepoint designator.
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @return AGESA_SUCCESS Always succeeds.
- *
- */
-AGESA_STATUS
-STATIC
-InitializeMsgBasedC1eFeature (
- IN UINT64 EntryPoint,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AP_TASK TaskPtr;
- AMD_CPU_EARLY_PARAMS CpuEarlyParams;
-
- IDS_HDT_CONSOLE (CPU_TRACE, " MT C1e is enabled\n");
-
- if ((EntryPoint != CPU_FEAT_AFTER_PM_INIT) || (IsWarmReset (StdHeader))) {
- CpuEarlyParams.PlatformConfig = *PlatformConfig;
-
- TaskPtr.FuncAddress.PfApTaskIC = EnableMsgC1eOnSocket;
- TaskPtr.DataTransfer.DataSizeInDwords = 2;
- TaskPtr.DataTransfer.DataPtr = &EntryPoint;
- TaskPtr.DataTransfer.DataTransferFlags = 0;
- TaskPtr.ExeFlags = PASS_EARLY_PARAMS;
- OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, &CpuEarlyParams);
- }
- return AGESA_SUCCESS;
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * 'Local' core 0 task to enable message-based C1e on it's socket.
- *
- * @param[in] EntryPoint Timepoint designator.
- * @param[in] StdHeader Config Handle for library, services.
- * @param[in] CpuEarlyParams Service parameters.
- *
- */
-VOID
-STATIC
-EnableMsgC1eOnSocket (
- IN VOID *EntryPoint,
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams
- )
-{
- MSG_BASED_C1E_FAMILY_SERVICES *FamilyServices;
-
- GetFeatureServicesOfCurrentCore (&MsgBasedC1eFamilyServiceTable, &FamilyServices, StdHeader);
- FamilyServices->InitializeMsgBasedC1e (FamilyServices,
- *((UINT64 *) EntryPoint),
- &CpuEarlyParams->PlatformConfig,
- StdHeader);
-}
-
-CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureMsgBasedC1e =
-{
- MsgBasedC1e,
- (CPU_FEAT_AFTER_PM_INIT | CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC),
- IsMsgBasedC1eFeatureEnabled,
- InitializeMsgBasedC1eFeature
-};
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuMsgBasedC1e.h b/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuMsgBasedC1e.h
deleted file mode 100644
index 9c675b7..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuMsgBasedC1e.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD AGESA CPU Message-based C1e Functions declarations.
- *
- * Contains code that declares the AGESA CPU C1e related APIs
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/Feature
- * @e \$Revision: 36567 $ @e \$Date: 2010-08-21 02:35:15 +0800 (Sat, 21 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPU_MSG_BASED_C1E_H_
-#define _CPU_MSG_BASED_C1E_H_
-
-/*----------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *----------------------------------------------------------------------------------------
- */
-// Forward declaration needed for multi-structure mutual references
-AGESA_FORWARD_DECLARATION (MSG_BASED_C1E_FAMILY_SERVICES);
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family specific call to check if message-based C1e is supported.
- *
- * @param[in] MsgBasedC1eServices Contains the runtime modifiable feature input data.
- * @param[in] Socket Processor socket to check.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval TRUE Message-based C1e is supported.
- * @retval FALSE Message-based C1e is not supported.
- *
- */
-typedef BOOLEAN F_MSG_BASED_C1E_IS_SUPPORTED (
- IN MSG_BASED_C1E_FAMILY_SERVICES *MsgBasedC1eServices,
- IN UINT32 Socket,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_MSG_BASED_C1E_IS_SUPPORTED *PF_MSG_BASED_C1E_IS_SUPPORTED;
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family specific call to enable hardware C1e.
- *
- * @param[in] MsgBasedC1eServices Hardware C1e services.
- * @param[in] EntryPoint Timepoint designator.
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @return Family specific error value.
- *
- */
-typedef AGESA_STATUS F_MSG_BASED_C1E_INIT (
- IN MSG_BASED_C1E_FAMILY_SERVICES *MsgBasedC1eServices,
- IN UINT64 EntryPoint,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_MSG_BASED_C1E_INIT *PF_MSG_BASED_C1E_INIT;
-
-/**
- * Provide the interface to the hardware C1e Family Specific Services.
- *
- * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
- * Each supported Family must provide an implementation for all methods in this interface, even if the
- * implementation is a CommonReturn().
- */
-struct _MSG_BASED_C1E_FAMILY_SERVICES {
- UINT16 Revision; ///< Interface version
- // Public Methods.
- PF_MSG_BASED_C1E_IS_SUPPORTED IsMsgBasedC1eSupported; ///< Method: Family specific call to check if hardware C1e is supported.
- PF_MSG_BASED_C1E_INIT InitializeMsgBasedC1e; ///< Method: Family specific call to enable hardware C1e.
-};
-
-
-/*----------------------------------------------------------------------------------------
- * F U N C T I O N S P R O T O T Y P E
- *----------------------------------------------------------------------------------------
- */
-
-#endif // _CPU_MSG_BASED_C1E_H_
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuPstateGather.c b/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuPstateGather.c
deleted file mode 100644
index 96ac698..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuPstateGather.c
+++ /dev/null
@@ -1,397 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU Pstate Data Gather Function.
- *
- * Contains code to collect all the Pstate related information from MSRs, and PCI registers.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 37640 $ @e \$Date: 2010-09-08 23:01:59 +0800 (Wed, 08 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "OptionPstate.h"
-#include "cpuRegisters.h"
-#include "cpuServices.h"
-#include "GeneralServices.h"
-#include "cpuPostInit.h"
-#include "Ids.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuPstateTables.h"
-#include "cpuApicUtilities.h"
-#include "cpuFeatures.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FEATURE_CPUPSTATEGATHER_FILECODE
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-extern OPTION_PSTATE_POST_CONFIGURATION OptionPstatePostConfiguration; // global user config record
-extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable;
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-VOID
-PStateGather (
- IN OUT VOID *PStateBuffer,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- *---------------------------------------------------------------------------------------
- *
- * PStateGatherData
- *
- * Description:
- * This function will gather PState information from the MSRs and fill up the
- * pStateBuf. This buffer will be used by the PState Leveling, and PState Table
- * generation code later.
- *
- * Parameters:
- * @param[in] *PlatformConfig
- * @param[in, out] *PStateStrucPtr
- * @param[in] *StdHeader
- *
- * @retval AGESA_STATUS
- *
- *---------------------------------------------------------------------------------------
- **/
-AGESA_STATUS
-PStateGatherData (
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
-
-
- AGESA_STATUS AgesaStatus;
-
- AGESA_TESTPOINT (TpProcCpuEntryPstateGather, StdHeader);
- AgesaStatus = AGESA_SUCCESS;
-
- // Gather data for ACPI Tables if ACPI P-States/C-States object generation is enabled.
- if ((PlatformConfig->UserOptionPState) || (IsFeatureEnabled (IoCstate, PlatformConfig, StdHeader))) {
- AgesaStatus = (*(OptionPstatePostConfiguration.PstateGather)) (StdHeader, PStateStrucPtr);
- // Note: Split config struct into PEI/DXE halves. This one is PEI.
- }
-
- return AgesaStatus;
-}
-
-/**--------------------------------------------------------------------------------------
- *
- * PStateGatherStub
- *
- * Description:
- * This is the default routine for use when the PState option is NOT requested.
- * The option install process will create and fill the transfer vector with
- * the address of the proper routine (Main or Stub). The link optimizer will
- * strip out of the .DLL the routine that is not used.
- *
- * Parameters:
- * @param[in] *StdHeader
- * @param[in, out] *PStateStrucPtr
- *
- * @retval AGESA_STATUS
- *
- *---------------------------------------------------------------------------------------
- **/
-AGESA_STATUS
-PStateGatherStub (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr
- )
-{
- return AGESA_UNSUPPORTED;
-}
-
-/**--------------------------------------------------------------------------------------
- *
- * PStateGatherMain
- *
- * Description:
- * This is the common routine for BSP gathering the Pstate data.
- *
- * Parameters:
- * @param[in] *StdHeader
- * @param[in, out] *PStateStrucPtr
- *
- * @retval AGESA_STATUS
- *
- *---------------------------------------------------------------------------------------
- **/
-AGESA_STATUS
-PStateGatherMain (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr
- )
-{
- AP_TASK TaskPtr;
- UINT32 BscSocket;
- UINT32 Ignored;
- UINT32 PopulatedSockets;
- UINT32 NumberOfSockets;
- UINT32 Socket;
- AGESA_STATUS IgnoredSts;
- PSTATE_LEVELING *PStateBufferPtr;
- PSTATE_CPU_FAMILY_SERVICES *FamilyServices;
- UINT32 MaxState;
-
- ASSERT (IsBsp (StdHeader, &IgnoredSts));
-
- FamilyServices = NULL;
- GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, &FamilyServices, StdHeader);
- ASSERT (FamilyServices != NULL);
-
- PopulatedSockets = 1;
- PStateBufferPtr = PStateStrucPtr->PStateLevelingStruc;
-
- NumberOfSockets = GetPlatformNumberOfSockets ();
- IdentifyCore (StdHeader, &BscSocket, &Ignored, &Ignored, &IgnoredSts);
-
- PStateStrucPtr->SizeOfBytes = sizeof (S_CPU_AMD_PSTATE);
-
- MaxState = 0;
- FamilyServices->GetPstateMaxState (FamilyServices, &MaxState, StdHeader);
-
- TaskPtr.FuncAddress.PfApTaskI = PStateGather;
- //
- // Calculate max buffer size in dwords that need to pass to ap task.
- //
- TaskPtr.DataTransfer.DataSizeInDwords = (UINT16) ((MaxState + 1) * (SIZE_IN_DWORDS (S_PSTATE_VALUES)));
- TaskPtr.ExeFlags = WAIT_FOR_CORE;
- TaskPtr.DataTransfer.DataPtr = PStateBufferPtr;
- TaskPtr.DataTransfer.DataTransferFlags = DATA_IN_MEMORY;
-
- //
- //Get P-States and fill the PStateBufferPtr for BSP
- //
- ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, NULL);
-
- //
- //Calculate next node buffer address
- //
- PStateBufferPtr->SocketNumber = (UINT8) BscSocket;
- PStateBufferPtr->PStateLevelingSizeOfBytes = (UINT16) (sizeof (PSTATE_LEVELING) + (UINT32) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES)));
- PStateStrucPtr->SizeOfBytes += (UINT32) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES));
- PStateBufferPtr = (PSTATE_LEVELING *) ((UINT8 *) PStateBufferPtr + (UINTN) sizeof (PSTATE_LEVELING) + (UINTN) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES)));
- CpuGetPStateLevelStructure (&PStateBufferPtr, PStateStrucPtr, 1, StdHeader);
- //
- //Get CPU P-States and fill the PStateBufferPtr for each node(BSC)
- //
- for (Socket = 0; Socket < NumberOfSockets; Socket++) {
- if (Socket != BscSocket) {
- if (IsProcessorPresent (Socket, StdHeader)) {
- PopulatedSockets++;
- LibAmdMemFill (PStateBufferPtr, 0, sizeof (PSTATE_LEVELING), StdHeader);
- TaskPtr.DataTransfer.DataPtr = PStateBufferPtr;
- ApUtilRunCodeOnSocketCore ((UINT8)Socket, 0, &TaskPtr, StdHeader);
- PStateBufferPtr->SocketNumber = (UINT8) Socket;
- //
- //Calculate next node buffer address
- //
- PStateBufferPtr->PStateLevelingSizeOfBytes = (UINT16) (sizeof (PSTATE_LEVELING) + (UINT32) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES)));
- PStateStrucPtr->SizeOfBytes += PStateBufferPtr->PStateLevelingSizeOfBytes;
- PStateBufferPtr = (PSTATE_LEVELING *) ((UINT8 *) PStateBufferPtr + (UINTN) sizeof (PSTATE_LEVELING) + (UINTN) (PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES)));
- }
- }
- }
- PStateStrucPtr->TotalSocketInSystem = PopulatedSockets;
-
- return AGESA_SUCCESS;
-}
-/**--------------------------------------------------------------------------------------
- *
- * PStateGather
- *
- * Description:
- * This is the common routine run on each BSC for gathering Pstate data.
- *
- * Parameters:
- * @param[in,out] *PStateBuffer
- * @param[in] *StdHeader
- *
- * @retval VOID
- *
- *---------------------------------------------------------------------------------------
- **/
-VOID
-PStateGather (
- IN OUT VOID *PStateBuffer,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 k;
- UINT32 IddVal;
- UINT32 IddDiv;
- UINT32 NodeNum;
- UINT32 CoreNum;
- UINT32 TempVar_c;
- UINT32 TotalEnabledPStates;
- UINT32 SwPstate;
- PCI_ADDR PciAddress;
- PSTATE_LEVELING *PStateBufferPtr;
- BOOLEAN PStateEnabled;
- PSTATE_CPU_FAMILY_SERVICES *FamilyServices;
- UINT32 Socket;
- AGESA_STATUS IgnoredSts;
- CPUID_DATA CpuId;
-
- PStateBufferPtr = (PSTATE_LEVELING *) PStateBuffer;
- TotalEnabledPStates = 0;
- FamilyServices = NULL;
- PStateEnabled = FALSE;
-
- GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, &FamilyServices, StdHeader);
- ASSERT (FamilyServices != NULL);
-
- //
- /// Sockets number: code looking at PStateBufferPtr->TotalCoresInNode
- /// needs to know it is Processor (or socket) core count and NOT a Node Core count.
- GetActiveCoresInCurrentSocket (&CoreNum, StdHeader);
- PStateBufferPtr->TotalCoresInNode = (UINT8) CoreNum;
-
- //
- // Assume current CoreNum always zero.(BSC)
- //
- GetCurrentNodeAndCore (&NodeNum, &CoreNum, StdHeader);
-
- PStateBufferPtr->CreateAcpiTables = 1;
-
- //
- // We need to know the max pstate state in this socket.
- //
- FamilyServices->GetPstateMaxState (FamilyServices, &TempVar_c, StdHeader);
- PStateBufferPtr->PStateCoreStruct[0].PStateMaxValue = (UINT8) TempVar_c;
-
- for (k = 0; k <= TempVar_c; k++) {
- // Check if PState is enabled
- FamilyServices->GetPstateRegisterInfo ( FamilyServices,
- k,
- &PStateEnabled,
- &IddVal,
- &IddDiv,
- &SwPstate,
- StdHeader);
-
- LibAmdMemFill (&(PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k]), 0, sizeof (S_PSTATE_VALUES), StdHeader);
-
- if (PStateEnabled) {
- FamilyServices->GetPstateFrequency (
- FamilyServices,
- (UINT8) k,
- &(PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k].CoreFreq),
- StdHeader);
-
- FamilyServices->GetPstatePower (
- FamilyServices,
- (UINT8) k,
- &(PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k].Power),
- StdHeader);
-
- PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k].IddValue = IddVal;
- PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k].IddDiv = IddDiv;
- PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k].SwPstateNumber = SwPstate;
-
- PStateBufferPtr->PStateCoreStruct[0].PStateStruct[k].PStateEnable = 1;
- TotalEnabledPStates++;
- }
- } // for (k = 0; k < MPPSTATE_MAXIMUM_STATES; k++)
-
- // Don't create ACPI Tables if there is one or less than one PState is enabled
- if (TotalEnabledPStates <= 1) {
- PStateBufferPtr[0].CreateAcpiTables = 0;
- }
-
- //--------------------Check Again--------------------------------
-
- IdentifyCore (StdHeader, &Socket, &NodeNum, &CoreNum, &IgnoredSts);
- GetPciAddress (StdHeader, Socket, NodeNum, &PciAddress, &IgnoredSts);
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = NORTH_BRIDGE_CAPABILITIES_REG;
- TempVar_c = 0;
- LibAmdPciRead (AccessWidth32, PciAddress, &TempVar_c, StdHeader);
- PStateBufferPtr->PStateCoreStruct[0].HtcCapable =
- (UINT8) ((TempVar_c & 0x00000400) >> 10); // Bit 10
-
- TempVar_c = 0;
- PciAddress.Address.Register = HARDWARE_THERMAL_CTRL_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &TempVar_c, StdHeader);
- PStateBufferPtr->PStateCoreStruct[0].HtcPstateLimit =
- (UINT8) ((TempVar_c & 0x70000000) >> 28); // Bits 30:28
-
- // Get LocalApicId from CPUID Fn0000_0001_EBX
- LibAmdCpuidRead (AMD_CPUID_APICID_LPC_BID, &CpuId, StdHeader);
- PStateBufferPtr->PStateCoreStruct[0].LocalApicId = (UINT8) ((CpuId.EBX_Reg & 0xFF000000) >> 24);
-}
-
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuPstateLeveling.c b/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuPstateLeveling.c
deleted file mode 100644
index a59b791..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuPstateLeveling.c
+++ /dev/null
@@ -1,1073 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU Pstate Leveling Function.
- *
- * Contains code to level the Pstates in a multi-socket system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 35664 $ @e \$Date: 2010-07-28 20:02:15 +0800 (Wed, 28 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "OptionPstate.h"
-#include "cpuLateInit.h"
-#include "cpuRegisters.h"
-#include "cpuPostInit.h"
-#include "Ids.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuPstateTables.h"
-#include "cpuApicUtilities.h"
-#include "cpuServices.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FEATURE_CPUPSTATELEVELING_FILECODE
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-extern OPTION_PSTATE_POST_CONFIGURATION OptionPstatePostConfiguration; // global user config record
-extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable;
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-AGESA_STATUS
-PutAllCoreInPState0 (
- IN OUT PSTATE_LEVELING *PStateBufferPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-StartPstateMsrModify (
- IN S_CPU_AMD_PSTATE *CpuAmdPState,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-STATIC
-PutCoreInPState0 (
- IN VOID *PStateBuffer,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-
-/**
- *---------------------------------------------------------------------------------------
- *
- * PStateLeveling
- *
- * Description:
- * This function will populate the PStateBuffer, after doing the PState Leveling
- * Note: This function should be called for every core in the system.
- *
- * Parameters:
- * @param[in,out] *PStateStrucPtr
- * @param[in] *StdHeader
- *
- * @retval AGESA_STATUS
- *
- *---------------------------------------------------------------------------------------
- **/
-AGESA_STATUS
-PStateLeveling (
- IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_TESTPOINT (TpProcCpuEntryPstateLeveling, StdHeader);
- return ((*(OptionPstatePostConfiguration.PstateLeveling)) (PStateStrucPtr, StdHeader));
- // Note: Split config struct into PEI/DXE halves. This one is PEI.
-}
-
-/**--------------------------------------------------------------------------------------
- *
- * PStateLevelingStub
- *
- * Description:
- * This is the default routine for use when the PState option is NOT requested.
- * The option install process will create and fill the transfer vector with
- * the address of the proper routine (Main or Stub). The link optimizer will
- * strip out of the .DLL the routine that is not used.
- *
- * Parameters:
- * @param[in,out] *PStateStrucPtr
- * @param[in] *StdHeader
- *
- * @retval AGESA_STATUS
- *
- *---------------------------------------------------------------------------------------
- **/
-AGESA_STATUS
-PStateLevelingStub (
- IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- return AGESA_UNSUPPORTED;
-}
-
-/**--------------------------------------------------------------------------------------
- *
- * PStateLevelingMain
- *
- * Description:
- * This is the common routine for creating the ACPI information tables.
- *
- * Parameters:
- * @param[in,out] *PStateStrucPtr
- * @param[in] *StdHeader
- *
- * @retval AGESA_STATUS
- *
- *---------------------------------------------------------------------------------------
- **/
-AGESA_STATUS
-PStateLevelingMain (
- IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 i;
- UINT32 k;
- UINT32 m;
- UINT32 TotalIterations;
- UINT32 LogicalSocketCount;
- UINT32 TempVar_a;
- UINT32 TempVar_b;
- UINT32 TempVar_c;
- UINT32 TempVar_d;
- UINT32 TempVar_e;
- UINT32 TempVar_f;
- PCI_ADDR PciAddress;
-
- UINT32 TempFreqArray[20];
- UINT32 TempPowerArray[20];
- UINT32 TempIddValueArray[20];
- UINT32 TempIddDivArray[20];
- UINT32 TempSocketPiArray[20];
-
- BOOLEAN TempFlag1;
- BOOLEAN TempFlag2;
- BOOLEAN TempFlag3;
- BOOLEAN TempFlag4;
- BOOLEAN AllCoresHaveHtcCapEquToZeroFlag;
- BOOLEAN AllCoreHaveMaxOnePStateFlag;
- BOOLEAN PstateMaxValEquToPstateHtcLimitFlag;
- BOOLEAN AtLeastOneCoreHasPstateHtcLimitEquToOneFlag;
- BOOLEAN PstateMaxValMinusHtcPstateLimitLessThan2Flag;
- PSTATE_LEVELING *PStateBufferPtr;
- PSTATE_LEVELING *PStateBufferPtrTmp;
- UINT32 MaxPstateInNode;
- AGESA_STATUS Status;
-
- TempFlag1 = FALSE;
- TempFlag2 = FALSE;
- TempFlag3 = FALSE;
- TempFlag4 = FALSE;
- AllCoresHaveHtcCapEquToZeroFlag = FALSE;
- AllCoreHaveMaxOnePStateFlag = FALSE;
- PstateMaxValEquToPstateHtcLimitFlag = FALSE;
- AtLeastOneCoreHasPstateHtcLimitEquToOneFlag = FALSE;
- PstateMaxValMinusHtcPstateLimitLessThan2Flag = FALSE;
- PStateBufferPtr = PStateStrucPtr->PStateLevelingStruc;
- Status = AGESA_SUCCESS;
-
- if (PStateBufferPtr[0].SetPState0 == PSTATE_FLAG_1) {
- PStateBufferPtr[0].AllCpusHaveIdenticalPStates = TRUE;
- PStateBufferPtr[0].InitStruct = 1;
- return AGESA_UNSUPPORTED;
- }
-
- LogicalSocketCount = PStateStrucPtr->TotalSocketInSystem;
-
- // This section of code will execute only for "core 0" i.e. BSP
- // Read P-States of all the cores.
- if (PStateBufferPtr[0].InitStruct == 0) {
- // Check if core frequency and power are same across all sockets.
- TempFlag1 = FALSE;
- for (i = 1; i < LogicalSocketCount; i++) {
- CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
- if ((PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue != PStateBufferPtr[0].PStateCoreStruct[0].PStateMaxValue)) {
- TempFlag1 = TRUE;
- break;
- }
- MaxPstateInNode = PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue;
- for (k = 0; k <= MaxPstateInNode; k++) {
- if ((PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[k].CoreFreq !=
- PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].CoreFreq) ||
- (PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[k].Power !=
- PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].Power)) {
- TempFlag1 = TRUE;
- break; // Come out of the inner FOR loop
- }
- }
- if (TempFlag1) {
- break; // Come out of the outer FOR loop
- }
- }
-
- if (!TempFlag1) {
- // No need to do pStateLeveling, or writing to pState MSR registers
- // if all CPUs have Identical PStates
- PStateBufferPtr[0].AllCpusHaveIdenticalPStates = TRUE;
- PStateBufferPtr[0].InitStruct = 1;
- PutAllCoreInPState0 (PStateBufferPtr, StdHeader);
- return AGESA_UNSUPPORTED;
- } else {
- PStateBufferPtr[0].AllCpusHaveIdenticalPStates = FALSE;
- }
-
- // 1_b) & 1_c)
- TempFlag1 = FALSE;
- TempFlag2 = FALSE;
- for (i = 0; i < LogicalSocketCount; i++) {
- CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
- if (PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue == 0) {
- TempFlag1 = TRUE;
- } else {
- TempFlag2 = TRUE;
- }
- if (PStateBufferPtrTmp->PStateCoreStruct[0].HtcCapable == 0) {
- TempFlag3 = TRUE;
- } else {
- TempFlag4 = TRUE;
- }
-
- if ((PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue -
- PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit) < 2) {
- PstateMaxValMinusHtcPstateLimitLessThan2Flag = TRUE;
- }
-
- if (PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue ==
- PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit) {
- PstateMaxValEquToPstateHtcLimitFlag = TRUE;
- }
-
- if (PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit == 1) {
- AtLeastOneCoreHasPstateHtcLimitEquToOneFlag = TRUE;
- }
- }
-
- // Do general setup of flags, that we may use later
- // Implementation of (1_b)
- if (TempFlag1 && TempFlag2) {
- //
- //Processors with only one enabled P-state (F3xDC[PstateMaxVal]=000b) cannot be mixed in a system with
- //processors with more than one enabled P-state (F3xDC[PstateMaxVal]!=000b).
- //
- PStateBufferPtr[0].InitStruct = 1;
- PStateBufferPtr[0].CreateAcpiTables = 0;
- PutAllCoreInPState0 (PStateBufferPtr, StdHeader);
- return AGESA_UNSUPPORTED;
- } else if (TempFlag1 && !TempFlag2) {
- //
- //all processors have only 1 enabled P-state
- //
- AllCoreHaveMaxOnePStateFlag = TRUE;
- PStateBufferPtr[0].OnlyOneEnabledPState = TRUE;
- }
-
- // Processors with F3xE8[HTC_CAPABLE] = 1 can not be
- // mixed in system with processors with F3xE8[HTC_CAPABLE] = 0.
- if (TempFlag3 && TempFlag4) {
- PStateBufferPtr[0].InitStruct = 1;
- PStateBufferPtr[0].CreateAcpiTables = 0;
- PutAllCoreInPState0 (PStateBufferPtr, StdHeader);
- return AGESA_UNSUPPORTED;
- }
-
- if (TempFlag3) {
- //
- //If code run to here means that all processors do not have HTC_CAPABLE.
- //
- AllCoresHaveHtcCapEquToZeroFlag = TRUE;
- }
-
- //--------------------------------------------------------------------------------
- // S T E P - 2
- //--------------------------------------------------------------------------------
- // Now run the PState Leveling Algorithm which will create mixed CPU P-State
- // Tables.
- // Follow the algorithm in the latest BKDG
- // -------------------------------------------------------------------------------
- // Match P0 CPU COF for all CPU cores to the lowest P0 CPU COF value in the
- // coherent fabric, and match P0 power for all CPU cores to the highest P0 power
- // value in the coherent fabric.
- // 2_a) If all processors have only 1 enabled P-State BIOS must write the
- // appropriate CpuFid value resulting from the matched CPU COF to all
- // copies of MSRC001_0070[CpuFid], and exit the sequence (No further
- // steps are executed)
- //--------------------------------------------------------------------------------
- // Identify the lowest P0 Frequency and maximum P0 Power
- TempVar_d = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[0].CoreFreq;
- TempVar_e = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[0].Power;
- TempVar_a = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[0].IddValue;
- TempVar_b = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[0].IddDiv;
-
- for (i = 0; i < LogicalSocketCount; i++) {
- CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
- if (TempVar_d > PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].CoreFreq) {
- TempVar_d = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].CoreFreq;
- }
-
- if (TempVar_e < PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].Power) {
- TempVar_e = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].Power;
- TempVar_a = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].IddValue;
- TempVar_b = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].IddDiv;
- }
- }
-
- // Set P0 Frequency and Power for all CPUs
- for (i = 0; i < LogicalSocketCount; i++) {
- CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
- PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].CoreFreq = TempVar_d;
- PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].Power = TempVar_e;
- PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].IddValue = TempVar_a;
- PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[0].IddDiv = TempVar_b;
- }
-
- // 2_a)
- if (!AllCoreHaveMaxOnePStateFlag) {
- //--------------------------------------------------------------------------
- // STEP - 3
- //--------------------------------------------------------------------------
- // Match the CPU COF and power for P-states used by HTC. Skip to step 4
- // is any processor reports F3xE8[HTC_Capable] = 0;
- // 3_a) Set F3x64[HtcPstateLimit] = 001b and F3x68[StcPstateLimit] = 001b for
- // processors with F3x64[HtcPstateLimit] = 000b.
- // 3_b) Identify the lowest CPU COF for all processors in the P-state
- // pointed to by [The Hardware Thermal Control (HTC) Register]
- // F3x64[HtcPstateLimit]
- // 3_c) Modify the CPU COF pointed to by [The Hardware Thermal Control
- // (HTC) Register] F3x64[HtcPstateLimit] for all processors to the
- // previously identified lowest CPU COF value.
- // 3_d) Identify the highest power for all processors in the P-state
- // pointed to by [The Hardware Thermal Control (HTC) Register]
- // F3x64[HtcPstateLimit].
- // 3_e) Modify the power pointed to by [The Hardware Thermal Control (HTC)
- // Register] F3x64[HtcPstateLimit] to the previously identified
- // highest power value.
- if (!AllCoresHaveHtcCapEquToZeroFlag) {
- // 3_a)
- for (i = 0; i < LogicalSocketCount; i++) {
- CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
- if (PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit == 0) {
- // To Be Done (Set Htc and Stc PstateLimit values)
- // for this CPU (using PCI address space)
- for (k = 0; k < (UINT8)GetPlatformNumberOfModules (); k++) {
- if (GetPciAddress (StdHeader, PStateBufferPtrTmp->SocketNumber, k, &PciAddress, &Status)) {
- // Set F3x64[HtcPstateLimit] = 001b
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = HARDWARE_THERMAL_CTRL_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &TempVar_d, StdHeader);
- // Bits 30:28
- TempVar_d = (TempVar_d & 0x8FFFFFFF) | 0x10000000;
- LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar_d, StdHeader);
-
- // Set F3x68[StcPstateLimit] = 001b
- PciAddress.Address.Register = SOFTWARE_THERMAL_CTRL_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &TempVar_d, StdHeader);
- // Bits 28:30
- TempVar_d = (TempVar_d & 0x8FFFFFFF) | 0x10000000;
- LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar_d, StdHeader);
- }
- }
- // Set LocalBuffer
- PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit = 1;
- if ((PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue - 1) < 2) {
- PstateMaxValMinusHtcPstateLimitLessThan2Flag = TRUE;
- }
-
- if (PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue == 1) {
- PstateMaxValEquToPstateHtcLimitFlag = TRUE;
- }
- }
-
- if (PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit == 1) {
- AtLeastOneCoreHasPstateHtcLimitEquToOneFlag = TRUE;
- }
- }
-
- // 3_b) and 3_d)
- TempVar_a = PStateBufferPtr[0].PStateCoreStruct[0].HtcPstateLimit;
- TempVar_d = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].CoreFreq;
- TempVar_e = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].Power;
- TempVar_f = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].IddValue;
- TempVar_c = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].IddDiv;
- for (i = 0; i < LogicalSocketCount; i++) {
- CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
- for (k = 0; k < 1; k++) {
- TempVar_b = PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit;
- if (TempVar_d > PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].CoreFreq) {
- TempVar_d = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].CoreFreq;
- }
-
- if (TempVar_e < PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].Power) {
- TempVar_e = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].Power;
- TempVar_f = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].IddValue;
- TempVar_c = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].IddDiv;
- }
- }
- }
-
- // 3_c) and 3_e)
- for (i = 0; i < LogicalSocketCount; i++) {
- CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
- TempVar_a = PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit;
- PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].CoreFreq = TempVar_d;
- PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].Power = TempVar_e;
- PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].IddValue = TempVar_f;
- PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].IddDiv = TempVar_c;
- }
- } // if(AllCoresHaveHtcCapEquToZeroFlag)
-
-
- //--------------------------------------------------------------------------
- // STEP - 4
- //--------------------------------------------------------------------------
- // Match the CPU COF and power for the lowest performance P-state:
- // 4_a) If F3xDC[PstateMaxVal] = F3x64[HtcPstateLimit] for any processor,
- // set PstateEn = 0 for all the P-states greater than
- // F3x64[HtcPstateLimit] for all processors.
- // 4_b) Identify the lowest CPU COF for all processors in the P-state
- // pointed to by F3xDC[PstateMaxVal].
- // 4_c) Modify the CPU COF for all processors in the P-state pointed to by
- // F3xDC[PstateMaxVal] to the previously identified lowest CPU COF
- // value.
- // 4_d) Identify the highest power for all processors in the P-state
- // pointed to by F3xDC[PstateMaxVal].
- // 4_e) Modify the power for all processors in the P-state pointed to by
- // F3xDC[PstateMaxVal] to the previously identified highest power
- // value.
-
- // 4_a)
- if (PstateMaxValEquToPstateHtcLimitFlag) {
- for (i = 0; i < LogicalSocketCount; i++) {
- CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
- TempVar_b = PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit + 1;
- for (k = TempVar_b; k <= PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue; k++) {
- PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].PStateEnable = 0;
- }
- //--------------------------------------------------------------------------
- // STEP - 5
- //--------------------------------------------------------------------------
- // 5_a) Modify F3xDC[PstateMaxVal] to indicate the lowest performance
- // P-state with PstateEn set for each processor (Step 4 can disable
- // P-states pointed to by F3xDC[PstateMaxVal])
-
- // Use this value of HtcPstateLimit to program the
- // F3xDC[pStateMaxValue]
- TempVar_e = PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit;
- TempVar_e <<= 8;
- // Bits 10:8
-
- for (m = 0; m < (UINT8)GetPlatformNumberOfModules (); m++) {
- if (GetPciAddress (StdHeader, PStateBufferPtrTmp->SocketNumber, m, &PciAddress, &Status)) {
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = CLOCK_POWER_TIMING_CTRL2_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &TempVar_d, StdHeader);
- TempVar_d = (TempVar_d & 0xFFFFF8FF) | TempVar_e;
- LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar_d, StdHeader);
- }
- }//End of step 5
- }
- }// End of 4_a)
-
- // 4_b) and 4_d)
- TempVar_a = PStateBufferPtr[0].PStateCoreStruct[0].PStateMaxValue;
- TempVar_d = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].CoreFreq;
- TempVar_e = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].Power;
- TempVar_f = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].IddValue;
- TempVar_c = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempVar_a].IddDiv;
-
- for (i = 0; i < LogicalSocketCount; i++) {
- CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
- TempVar_b = PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue;
- if (TempVar_d >
- PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].CoreFreq) {
- TempVar_d =
- PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].CoreFreq;
- }
-
- if (TempVar_e < PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].Power) {
- TempVar_e = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].Power;
- TempVar_f = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].IddValue;
- TempVar_c = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_b].IddDiv;
- }
- }
-
- // 4_c) and 4_e)
- for (i = 0; i < LogicalSocketCount; i++) {
- CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
- TempVar_a = PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue;
- PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].CoreFreq = TempVar_d;
- PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].Power = TempVar_e;
- PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].IddValue = TempVar_f;
- PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempVar_a].IddDiv = TempVar_c;
- }
-
-
- //--------------------------------------------------------------------------
- // STEP - 6
- //--------------------------------------------------------------------------
- // Match the CPU COF and power for upper intermediate performance
- // P-state(s):
- // Upper intermediate PStates = PStates between (Not including) P0 and
- // F3x64[HtcPstateLimit]
- // 6_a) If F3x64[HtcPstateLimit] = 001b for any processor, set PstateEn = 0
- // for enabled upper intermediate P-states for all processors with
- // F3x64[HtcPstateLimit] > 001b and skip the remaining actions for
- // this numbered step.
- // 6_b) Define each of the available upper intermediate P-states; for each
- // processor concurrently evaluate the following loop; when any
- // processor falls out of the loop (runs out of available upper
- // intermediate Pstates) all other processors have their remaining
- // upper intermediate P-states invalidated (PstateEn = 0);
- // for (i = F3x64[HtcPstateLimit] - 1; i > 0; i--)
- // - Identify the lowest CPU COF for P(i).
- // - Identify the highest power for P(i).
- // - Modify P(i) CPU COF for all processors to the previously
- // identified lowest CPU COF value.
- // - Modify P(i) power for all processors to the previously
- // identified highest power value.
-
- // 6_a)
- if (AtLeastOneCoreHasPstateHtcLimitEquToOneFlag) {
- for (i = 0; i < LogicalSocketCount; i++) {
- CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
- for (k = 1; k < (PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit); k++) {
- if (PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit > 1) {
- // Make a function call to clear the
- // structure values
- PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].PStateEnable = 0;
- }
- }
- }
- }
- // 6_b)
- else {
- // Identify Lowest Frequency and Highest Power
- TotalIterations = 0;
- TempFlag1 = TRUE;
-
- for (i = 0; i < LogicalSocketCount; i++) {
- CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
- TempSocketPiArray[i] = PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit - 1;
- }
-
- do {
- //For first socket, try to find a candidate
- if (TempSocketPiArray[0] != 0) {
- while (PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].PStateEnable == 0) {
- TempSocketPiArray[0] = TempSocketPiArray[0] - 1;
- if (TempSocketPiArray[0] == 0) {
- TempFlag1 = FALSE;
- break;
- }
- }
- } else {
- TempFlag1 = FALSE;
- }
- if (TempFlag1) {
- TempFreqArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].CoreFreq;
- TempPowerArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].Power;
- TempIddValueArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].IddValue;
- TempIddDivArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].IddDiv;
-
- //Try to find next candidate
- for (i = 1; i < LogicalSocketCount; i++) {
- CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
- if (TempSocketPiArray[i] != 0) {
- while (PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].PStateEnable == 0) {
- TempSocketPiArray[i]--;
- if (TempSocketPiArray[i] == 0) {
- TempFlag1 = FALSE;
- break;
- }
- }//end while
- } else {
- TempFlag1 = FALSE;
- }
-
- } //end for LogicalSocketCount
- }
-
- if (TempFlag1) {
- for (i = 0; i < LogicalSocketCount; i++) {
- //
- //Compare
- //
- CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
- if (TempFreqArray[TotalIterations] > PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq) {
- TempFreqArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq;
- }
-
- if (TempPowerArray[TotalIterations] < PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power) {
- TempPowerArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power;
- TempIddValueArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddValue;
- TempIddDivArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddDiv;
- }
- }
- // Modify (Pi) CPU COF and Power for all the CPUs
- for (i = 0; i < LogicalSocketCount; i++) {
- CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
- PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq = TempFreqArray[TotalIterations];
- PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power = TempPowerArray[TotalIterations];
- PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddValue = TempIddValueArray[TotalIterations];
- PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddDiv = TempIddDivArray[TotalIterations];
- TempSocketPiArray[i] = TempSocketPiArray[i] - 1;
- }
- } else {
- for (i = 0; i < LogicalSocketCount; i++) {
- CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
- for (m = TempSocketPiArray[i]; m > 0; m--) {
- PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[m].PStateEnable = 0;
- }
- }
- }
-
- TotalIterations++;
- } while (TempFlag1);
-
- } // else
-
- //--------------------------------------------------------------------------
- // STEP - 7
- //--------------------------------------------------------------------------
- // Match the CPU COF and power for lower intermediate performance P - state(s)
- // Lower Intermediate Pstates = Pstates between (not including)
- // F3x64[HtcPstateLimit] and F3xDC[PstateMaxVal]
- // 7_a) If F3xDC[PstateMaxVal] - F3x64[HtcPstateLimit] < 2 for any
- // processor, set PstateEn = 0 for enabled lower intermediate P - states
- // for all processors with (F3xDC[PstateMaxVal] -
- // F3x64[HtcPstateLimit] > 1) and skip the remaining actions for this
- // numbered step.
- // 7_b) Define each of the available lower intermediate P-states; for each
- // processor concurrently evaluate the following loop; when any
- // processor falls out of the loop (runs out of available lower
- // intermediate Pstates) all other processors have their remaining
- // lower intermediate P-states invalidated (PstateEn = 0);
- // for (i = F3xDC[PstateMaxVal]-1; i > F3x64[HtcPstateLimit]; i--)
- // - Identify the lowest CPU COF for P-states between
- // (not including) F3x64[HtcPstateLimit] and P(i).
- // - Identify the highest power for P-states between
- // (not including) F3x64[HtcPstateLimit] and P(i).
- // - Modify P(i) CPU COF for all processors to the previously
- // identified lowest CPU COF value.
- // - Modify P(i) power for all processors to the previously
- // identified highest power value.
-
-
- // 7_a)
- if (PstateMaxValMinusHtcPstateLimitLessThan2Flag) {
- for (i = 0; i < LogicalSocketCount; i++) {
- CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
-
- for (k = PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue - 1;
- k > PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit;
- k--) {
- if ((PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue -
- PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit) > 1) {
- PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].PStateEnable = 0;
- }
- }
- }
- }
-
- // 7_b)
- else {
- // Identify Lowest Frequency and Highest Power
-
- TotalIterations = 0;
- TempFlag1 = TRUE;
-
- for (i = 0; i < LogicalSocketCount; i++) {
- CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
- TempSocketPiArray[i] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateMaxValue - 1;
- }
-
- do {
- //For first socket, try to find a candidate
- if (TempSocketPiArray[0] != PStateBufferPtr[0].PStateCoreStruct[0].HtcPstateLimit) {
- while (PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].PStateEnable == 0) {
- TempSocketPiArray[0] = TempSocketPiArray[0] - 1;
- if (TempSocketPiArray[0] == PStateBufferPtr[0].PStateCoreStruct[0].HtcPstateLimit) {
- TempFlag1 = FALSE;
- break;
- }
- }
- } else {
- TempFlag1 = FALSE;
- }
- if (TempFlag1) {
- TempFreqArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].CoreFreq;
- TempPowerArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].Power;
- TempIddValueArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].IddValue;
- TempIddDivArray[TotalIterations] = PStateBufferPtr[0].PStateCoreStruct[0].PStateStruct[TempSocketPiArray[0]].IddDiv;
-
- //Try to find next candidate
- for (i = 1; i < LogicalSocketCount; i++) {
- CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
- if (TempSocketPiArray[i] != PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit) {
- while (PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].PStateEnable == 0) {
- TempSocketPiArray[i]--;
- if (TempSocketPiArray[i] == PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit) {
- TempFlag1 = FALSE;
- break;
- }
- }//end while
- } else {
- TempFlag1 = FALSE;
- }
- } //end for LogicalSocketCount
- }
-
- if (TempFlag1) {
- for (i = 0; i < LogicalSocketCount; i++) {
- //
- //Compare
- //
- CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
- if (TempFreqArray[TotalIterations] > PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq) {
- TempFreqArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq;
- }
- if (TempPowerArray[TotalIterations] < PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power) {
- TempPowerArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power;
- TempIddValueArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddValue;
- TempIddDivArray[TotalIterations] = PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddDiv;
- }
- }
- // Modify (Pi) CPU COF and Power for all the CPUs
- for (i = 0; i < LogicalSocketCount; i++) {
- CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
- PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].CoreFreq = TempFreqArray[TotalIterations];
- PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].Power = TempPowerArray[TotalIterations];
- PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddValue = TempIddValueArray[TotalIterations];
- PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[TempSocketPiArray[i]].IddDiv = TempIddDivArray[TotalIterations];
- TempSocketPiArray[i] = TempSocketPiArray[i] - 1;
- }
- } else {
- for (i = 0; i < LogicalSocketCount; i++) {
- CpuGetPStateLevelStructure (&PStateBufferPtrTmp, PStateStrucPtr, i, StdHeader);
- for (m = TempSocketPiArray[i]; m > PStateBufferPtrTmp->PStateCoreStruct[0].HtcPstateLimit; m--) {
- PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[m].PStateEnable = 0;
- }
- }
- }
- TotalIterations++;
- } while (TempFlag1);
- } // else
- } // if(!AllCoreHaveMaxOnePStateFlag)
-
- PStateBufferPtr[0].InitStruct = 1;
- } // CurrentCore
-
-
- // Update the pState MSRs
- // This can be done only by individual core
- StartPstateMsrModify (PStateStrucPtr, StdHeader);
-
- //----------------------------------------------------------------------------------
- // STEP - 8
- //----------------------------------------------------------------------------------
- // Place all cores into a valid COF and VID configuration corresponding to an
- // enabled P-state:
- // 8_a) Select an enabled P-state != to the P-state pointed to by
- // MSRC001_0063[CurPstate] for each core.
- // 8_b) Transition all cores to the selected P-states by writing the Control value
- // from the_PSS object corresponding to the selected P-state to
- // MSRC001_0062[PstateCmd].
- // 8_c) Wait for all cores to report the Status value from the _PSS object
- // corresponding to the selected P-state in MSRC001_0063[CurPstate].
- //
- PutAllCoreInPState0 (PStateBufferPtr, StdHeader);
-
- return AGESA_SUCCESS;
-}
-
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/**
- *---------------------------------------------------------------------------------------
- *
- * PutAllCoreInPState0
- *
- * Description:
- * This function will put core pstate to p0.
- *
- * Parameters:
- * @param[in,out] *PStateBufferPtr
- * @param[in] *StdHeader
- *
- * @retval AGESA_STATUS
- *
- *---------------------------------------------------------------------------------------
- **/
-AGESA_STATUS
-PutAllCoreInPState0 (
- IN OUT PSTATE_LEVELING *PStateBufferPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AP_TASK TaskPtr;
- UINT32 BscSocket;
- UINT32 Ignored;
- UINT32 BscCore;
- UINT32 Core;
- UINT32 Socket;
- UINT32 NumberOfSockets;
- UINT32 NumberOfCores;
- AGESA_STATUS IgnoredSts;
-
- TaskPtr.FuncAddress.PfApTaskI = PutCoreInPState0;
- TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (PSTATE_LEVELING);
- TaskPtr.ExeFlags = WAIT_FOR_CORE;
- TaskPtr.DataTransfer.DataPtr = PStateBufferPtr;
- TaskPtr.DataTransfer.DataTransferFlags = DATA_IN_MEMORY;
-
- IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredSts);
- NumberOfSockets = GetPlatformNumberOfSockets ();
-
- PutCoreInPState0 (PStateBufferPtr, StdHeader);
-
- for (Socket = 0; Socket < NumberOfSockets; Socket++) {
- if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
- for (Core = 0; Core < NumberOfCores; Core++) {
- if ((Socket != (UINT32) BscSocket) || (Core != (UINT32) BscCore)) {
- ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);
- }
- }
- }
- }
-
- return AGESA_SUCCESS;
-}
-
-/**
- *---------------------------------------------------------------------------------------
- *
- * CorePstateRegModify
- *
- * Description:
- * This function will setting the Pstate MSR to each APs base on Pstate Buffer.
- * Note: This function should be called for every core in the system.
- *
- * Parameters:
- * @param[in,out] *CpuAmdPState
- * @param[in] *StdHeader
- *
- * @retval VOID
- *
- *---------------------------------------------------------------------------------------
- **/
-VOID
-CorePstateRegModify (
- IN VOID *CpuAmdPState,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- PSTATE_CPU_FAMILY_SERVICES *FamilySpecificServices;
- FamilySpecificServices = NULL;
-
- GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, &FamilySpecificServices, StdHeader);
- ASSERT (FamilySpecificServices != NULL)
- FamilySpecificServices->SetPStateLevelReg (FamilySpecificServices, (S_CPU_AMD_PSTATE *) CpuAmdPState, StdHeader);
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * This function will set msr on all cores of all nodes.
- *
- * @param[in] CpuAmdPState Pointer to S_CPU_AMD_PSTATE.
- * @param[in] StdHeader Header for library and services.
- *
- * @retval AGESA_SUCCESS Always succeeds
- *
- */
-AGESA_STATUS
-StartPstateMsrModify (
- IN S_CPU_AMD_PSTATE *CpuAmdPState,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AP_TASK TaskPtr;
- UINT32 BscSocket;
- UINT32 Ignored;
- UINT32 BscCore;
- UINT32 Core;
- UINT32 Socket;
- UINT32 NumberOfSockets;
- UINT32 NumberOfCores;
- AGESA_STATUS IgnoredSts;
-
- TaskPtr.FuncAddress.PfApTaskI = CorePstateRegModify;
- TaskPtr.DataTransfer.DataSizeInDwords = (UINT16) (CpuAmdPState->SizeOfBytes / 4 + 1);
- TaskPtr.ExeFlags = WAIT_FOR_CORE;
- TaskPtr.DataTransfer.DataPtr = CpuAmdPState;
- TaskPtr.DataTransfer.DataTransferFlags = DATA_IN_MEMORY;
-
- IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredSts);
- NumberOfSockets = GetPlatformNumberOfSockets ();
-
- CorePstateRegModify (CpuAmdPState, StdHeader);
-
- for (Socket = 0; Socket < NumberOfSockets; Socket++) {
- if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
- for (Core = 0; Core < NumberOfCores; Core++) {
- if ((Socket != (UINT32) BscSocket) || (Core != (UINT32) BscCore)) {
- ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);
- }
- }
- }
- }
-
- return AGESA_SUCCESS;
-}
-
-
-/**
- *---------------------------------------------------------------------------------------
- *
- * CpuGetPStateLevelStructure
- *
- * Description:
- * Based on the LogicalSocketNumber, this function will return a pointer
- * point to the accurate offset of the PSTATE_LEVELING structure.
- *
- * Parameters:
- * @param[in,out] *PStateBufferPtr
- * @param[in] *CpuAmdPState
- * @param[in] LogicalSocketNumber
- * @param[in] *StdHeader
- *
- * @retval VOID
- *
- *---------------------------------------------------------------------------------------
- **/
-AGESA_STATUS
-CpuGetPStateLevelStructure (
- OUT PSTATE_LEVELING **PStateBufferPtr,
- IN S_CPU_AMD_PSTATE *CpuAmdPState,
- IN UINT32 LogicalSocketNumber,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- PSTATE_LEVELING *PStateBufferPtrTmp;
- UINT32 i;
-
- if (LogicalSocketNumber > CpuAmdPState->TotalSocketInSystem) {
- return AGESA_UNSUPPORTED;
- }
-
- PStateBufferPtrTmp = CpuAmdPState->PStateLevelingStruc;
-
- for (i = 1; i <= LogicalSocketNumber; i++) {
- PStateBufferPtrTmp = (PSTATE_LEVELING *) ((UINT8 *) PStateBufferPtrTmp + ((UINTN) PStateBufferPtrTmp->PStateLevelingSizeOfBytes));
- }
-
- *PStateBufferPtr = PStateBufferPtrTmp;
-
- return AGESA_SUCCESS;
-}
-
-
-/**
- *---------------------------------------------------------------------------------------
- *
- * PutCoreInPState0
- *
- * Description:
- * This function will take the CPU core into P0
- *
- * Parameters:
- * @param[in] *PStateBuffer
- * @param[in] *StdHeader
- *
- * @retval VOID
- *
- *---------------------------------------------------------------------------------------
- **/
-VOID
-STATIC
-PutCoreInPState0 (
- IN VOID *PStateBuffer,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
- PSTATE_LEVELING *PStateBufferPtr;
-
- PStateBufferPtr = (PSTATE_LEVELING *) PStateBuffer;
-
- if ((PStateBufferPtr[0].SetPState0 == PSTATE_FLAG_1 ) ||
- (PStateBufferPtr[0].SetPState0 == PSTATE_FLAG_2)) {
- return;
- }
-
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
-
- FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) FALSE, StdHeader);
-}
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuPstateTables.c b/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuPstateTables.c
deleted file mode 100644
index 428b345..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuPstateTables.c
+++ /dev/null
@@ -1,830 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD PSTATE, ACPI table related API functions.
- *
- * Contains code that generates the _PSS, _PCT, and other ACPI tables.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "OptionPstate.h"
-#include "cpuLateInit.h"
-#include "cpuRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "GeneralServices.h"
-#include "cpuServices.h"
-#include "heapManager.h"
-#include "Ids.h"
-#include "Filecode.h"
-#include "GeneralServices.h"
-#include "cpuPstateTables.h"
-#include "cpuFeatures.h"
-#include "cpuIoCstate.h"
-CODE_GROUP (G3_DXE)
-RDATA_GROUP (G3_DXE)
-
-#define FILECODE PROC_CPU_FEATURE_CPUPSTATETABLES_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-extern OPTION_PSTATE_LATE_CONFIGURATION OptionPstateLateConfiguration; // global user config record
-extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable;
-extern CPU_FAMILY_SUPPORT_TABLE IoCstateFamilyServiceTable;
-
-STATIC ACPI_TABLE_HEADER ROMDATA CpuSsdtHdrStruct =
-{
- 'S','S','D','T',
- 0,
- 1,
- 0,
- 'A','M','D',' ',' ',' ',
- 'P','O','W','E','R','N','O','W',
- 1,
- 'A','M','D',' ',
- 1
-};
-
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/**
- *---------------------------------------------------------------------------------------
- *
- * CalAcpiTablesSize
- *
- * Description:
- * This function will calculate the size of ACPI PState tables
- *
- * Parameters:
- * @param[in] *AmdPstatePtr
- * @param[in] *PlatformConfig
- * @param[in] *StdHeader
- *
- * @retval UINT32
- *
- *---------------------------------------------------------------------------------------
- */
-UINT32
-CalAcpiTablesSize (
- IN S_CPU_AMD_PSTATE *AmdPstatePtr,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 ScopeSize;
- UINT32 CoreCount;
- UINT32 SocketCount;
- UINT32 MaxCoreNumberInCurrentSocket;
- UINT32 MaxSocketNumberInSystem;
- UINT32 MaxPstateNumberInCurrentCore;
- UINT32 CstateAcpiObjSize;
- PSTATE_LEVELING *PStateLevelingBufferStructPtr;
- IO_CSTATE_FAMILY_SERVICES *IoCstateFamilyServices;
-
- ScopeSize = sizeof (ACPI_TABLE_HEADER);
- CstateAcpiObjSize = 0;
- IoCstateFamilyServices = NULL;
-
- PStateLevelingBufferStructPtr = AmdPstatePtr->PStateLevelingStruc;
- MaxSocketNumberInSystem = AmdPstatePtr->TotalSocketInSystem;
-
- if (IsFeatureEnabled (IoCstate, PlatformConfig, StdHeader)) {
- GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, &IoCstateFamilyServices, StdHeader);
- // If we're supporting multiple families, only proceed when IO Cstate family services are available
- if (IoCstateFamilyServices != NULL) {
- CstateAcpiObjSize = IoCstateFamilyServices->GetAcpiCstObj (IoCstateFamilyServices, PlatformConfig, StdHeader);
- }
- }
-
- for (SocketCount = 0; SocketCount < MaxSocketNumberInSystem; SocketCount++) {
- MaxCoreNumberInCurrentSocket = PStateLevelingBufferStructPtr->TotalCoresInNode;
- for (CoreCount = 0; CoreCount < MaxCoreNumberInCurrentSocket; CoreCount++) {
- MaxPstateNumberInCurrentCore = PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateMaxValue + 1;
-
- ScopeSize += (SCOPE_STRUCT_SIZE - 1); // Scope size per core
- ScopeSize += CstateAcpiObjSize; // C-State ACPI objects size per core
-
- // Add P-State ACPI Objects size per core
- if ((PStateLevelingBufferStructPtr[0].CreateAcpiTables != 0) && (PlatformConfig->UserOptionPState)) {
- ScopeSize += (PCT_STRUCT_SIZE +
- PSS_HEADER_STRUCT_SIZE +
- (MaxPstateNumberInCurrentCore * PSS_BODY_STRUCT_SIZE) +
- XPSS_HEADER_STRUCT_SIZE +
- (MaxPstateNumberInCurrentCore * XPSS_BODY_STRUCT_SIZE) +
- PSD_HEADER_STRUCT_SIZE +
- PSD_BODY_STRUCT_SIZE +
- PPC_HEADER_BODY_STRUCT_SIZE);
- }
- }
- ScopeSize += MaxCoreNumberInCurrentSocket;
- PStateLevelingBufferStructPtr = (PSTATE_LEVELING *) ((UINT8 *) PStateLevelingBufferStructPtr + (UINTN) sizeof (PSTATE_LEVELING) + (UINTN) (PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES)));
- }
- AmdPstatePtr->SizeOfBytes = ScopeSize;
-
- return ScopeSize;
-}
-
-/**--------------------------------------------------------------------------------------
- *
- * GenerateSsdtStub
- *
- * Description:
- * This is the default routine for use when both PState and CState option is NOT
- * requested. The option install process will create and fill the transfer vector
- * with the address of the proper routine (Main or Stub). The link optimizer will
- * strip out of the .DLL the routine that is not used.
- *
- * Parameters:
- * @param[in] StdHeader Handle to config for library and services
- * @param[in] PlatformConfig Contains the power cap parameter
- * @param[in,out] SsdtPtr ACPI SSDT table pointer
- *
- * @retval AGESA_STATUS
- *
- *---------------------------------------------------------------------------------------
- **/
-AGESA_STATUS
-GenerateSsdtStub (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN OUT VOID **SsdtPtr
- )
-{
- return AGESA_UNSUPPORTED;
-}
-
-/**
- *---------------------------------------------------------------------------------------
- *
- * GenerateSsdt
- *
- * Description:
- * This function will populate the SSDT with ACPI P-States and C-States Objects, whenever
- * necessary
- * This function should be called only from BSP
- *
- * Parameters:
- * @param[in] StdHeader Handle to config for library and services
- * @param[in] PlatformConfig Contains the power cap parameter
- * @param[in,out] SsdtPtr ACPI SSDT pointer
- *
- * @retval AGESA_STATUS
- *
- *---------------------------------------------------------------------------------------
- */
-AGESA_STATUS
-GenerateSsdt (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN OUT VOID **SsdtPtr
- )
-{
- UINT32 i;
- UINT32 j;
- UINT32 TempVar8_a;
- UINT32 CurrSize;
- UINT32 TempVar_a;
- UINT32 TempVar_b;
- UINT32 ScopeSize;
- UINT32 CoreCount;
- UINT32 SocketCount;
- UINT32 MaxCorePerNode;
- UINT8 LocalApicId;
- UINT8 *IntermediatePtr;
- AGESA_STATUS AgesaStatus;
- LOCATE_HEAP_PTR LocateHeapParams;
- ALLOCATE_HEAP_PARAMS AllocateHeapParams;
- S_CPU_AMD_PSTATE *AmdPstatePtr;
- PSTATE_LEVELING *PStateLevelingBufferStructPtr;
- SCOPE *ScopeAcpiTablesStructPtr;
- SCOPE *ScopeAcpiTablesStructPtrTemp;
-
- AGESA_TESTPOINT (TpProcCpuEntryPstate, StdHeader);
-
- ASSERT (IsBsp (StdHeader, &AgesaStatus));
-
- // If P-State and C-State ACPI tables do not need to be generated, exit this routine
- if ((!PlatformConfig->UserOptionPState) && (!IsFeatureEnabled (IoCstate, PlatformConfig, StdHeader))) {
- AgesaStatus = AGESA_UNSUPPORTED;
- return AgesaStatus;
- }
-
- // Initialize data variables
- ScopeSize = 0;
- CoreCount = 0;
- LocalApicId = 0;
- CurrSize = 0;
-
- // Locate P-State data buffer
- LocateHeapParams.BufferHandle = AMD_PSTATE_DATA_BUFFER_HANDLE;
- AGESA_TESTPOINT (TpProcCpuBeforeLocateSsdtBuffer, StdHeader);
- if (HeapLocateBuffer (&LocateHeapParams, StdHeader) != AGESA_SUCCESS) {
- return AGESA_ERROR;
- }
- AGESA_TESTPOINT (TpProcCpuAfterLocateSsdtBuffer, StdHeader);
-
- AmdPstatePtr = (S_CPU_AMD_PSTATE *) LocateHeapParams.BufferPtr;
- PStateLevelingBufferStructPtr = AmdPstatePtr->PStateLevelingStruc;
-
- // Allocate rough buffer for AcpiTable, if SsdtPtr is NULL
- if (*SsdtPtr == NULL) {
- //Do not know the actual size.. pre-calculate it.
- AllocateHeapParams.RequestedBufferSize = CalAcpiTablesSize (AmdPstatePtr, PlatformConfig, StdHeader);
- AllocateHeapParams.BufferHandle = AMD_PSTATE_ACPI_BUFFER_HANDLE;
- AllocateHeapParams.Persist = HEAP_SYSTEM_MEM;
-
- AGESA_TESTPOINT (TpProcCpuBeforeAllocateSsdtBuffer, StdHeader);
- if (HeapAllocateBuffer (&AllocateHeapParams, StdHeader) != AGESA_SUCCESS) {
- return AGESA_ERROR;
- }
- AGESA_TESTPOINT (TpProcCpuAfterAllocateSsdtBuffer, StdHeader);
- *SsdtPtr = AllocateHeapParams.BufferPtr;
- }
-
- IDS_HDT_CONSOLE (CPU_TRACE, " SSDT is created\n");
-
- // Copy SSDT header into allocated buffer
- LibAmdMemCopy (*SsdtPtr, (VOID *) &CpuSsdtHdrStruct, (UINTN) (sizeof (ACPI_TABLE_HEADER)), StdHeader);
- IntermediatePtr = (UINT8 *) *SsdtPtr;
- ScopeAcpiTablesStructPtr = (SCOPE *) &IntermediatePtr[sizeof (ACPI_TABLE_HEADER)];
-
- SocketCount = AmdPstatePtr->TotalSocketInSystem;
-
- // Generate name scope and ACPI objects for every core in the system
- for (i = 0; i < SocketCount; i++) {
- MaxCorePerNode = PStateLevelingBufferStructPtr->TotalCoresInNode;
- for (j = 0; j < MaxCorePerNode; j++) {
- CoreCount++;
- // Set Name Scope for CPU0, 1, 2, ..... n
- // CPU0 to CPUn will name as C000 to Cnnn
- // -----------------------------------------
- ScopeAcpiTablesStructPtr->ScopeOpcode = SCOPE_OPCODE;
- // This value will be filled at the end of this function
- // Since at this time, we don't know how many Pstates we
- // would have
- ScopeAcpiTablesStructPtr->ScopeLength = 0;
- ScopeAcpiTablesStructPtr->ScopeValue1 = SCOPE_VALUE1;
- ScopeAcpiTablesStructPtr->ScopeValue2 = SCOPE_VALUE2;
- ScopeAcpiTablesStructPtr->ScopeNamePt1a__ = SCOPE_NAME__;
- if (PlatformConfig->ProcessorScopeInSb) {
- ScopeAcpiTablesStructPtr->ScopeNamePt1a_P = SCOPE_NAME_S;
- ScopeAcpiTablesStructPtr->ScopeNamePt1a_R = SCOPE_NAME_B;
- } else {
- ScopeAcpiTablesStructPtr->ScopeNamePt1a_P = SCOPE_NAME_P;
- ScopeAcpiTablesStructPtr->ScopeNamePt1a_R = SCOPE_NAME_R;
- }
- ScopeAcpiTablesStructPtr->ScopeNamePt1b__ = SCOPE_NAME__;
- ASSERT ((PlatformConfig->ProcessorScopeName0 >= 'A') && (PlatformConfig->ProcessorScopeName0 <= 'Z'))
- ASSERT ((PlatformConfig->ProcessorScopeName1 >= 'A') && (PlatformConfig->ProcessorScopeName1 <= 'Z') || \
- (PlatformConfig->ProcessorScopeName1 >= '0') && (PlatformConfig->ProcessorScopeName1 <= '9') || \
- (PlatformConfig->ProcessorScopeName1 == '_'))
-
- ScopeAcpiTablesStructPtr->ScopeNamePt2a_C = PlatformConfig->ProcessorScopeName0;
- ScopeAcpiTablesStructPtr->ScopeNamePt2a_P = PlatformConfig->ProcessorScopeName1;
-
- TempVar8_a = ((CoreCount - 1) >> 4) & 0x0F;
- ScopeAcpiTablesStructPtr->ScopeNamePt2a_U = (UINT8) (SCOPE_NAME_0 + TempVar8_a);
-
- TempVar8_a = (CoreCount - 1) & 0x0F;
- if (TempVar8_a < 0xA) {
- ScopeAcpiTablesStructPtr->ScopeNamePt2a_0 = (UINT8) (SCOPE_NAME_0 + TempVar8_a);
- } else {
- ScopeAcpiTablesStructPtr->ScopeNamePt2a_0 = (UINT8) (SCOPE_NAME_A + TempVar8_a - 0xA);
- }
- // Increment and typecast the pointer
- ScopeAcpiTablesStructPtrTemp = ScopeAcpiTablesStructPtr;
- ScopeAcpiTablesStructPtrTemp++;
-
- // Get the Local Apic Id for each core
- LocalApicId = PStateLevelingBufferStructPtr->PStateCoreStruct[0].LocalApicId + (UINT8) j;
-
- // Create P-State ACPI Objects
- CurrSize += ((*(OptionPstateLateConfiguration.PstateFeature)) (PlatformConfig, PStateLevelingBufferStructPtr, (VOID *) &ScopeAcpiTablesStructPtrTemp, LocalApicId, StdHeader));
-
- // Create C-State ACPI Objects
- CurrSize += ((*(OptionPstateLateConfiguration.CstateFeature)) (PlatformConfig, PStateLevelingBufferStructPtr, (VOID *) &ScopeAcpiTablesStructPtrTemp, LocalApicId, StdHeader));
-
- // Now update the SCOPE Length field
- {
- CurrSize += (SCOPE_STRUCT_SIZE - 1);
- ScopeSize += CurrSize;
-
- TempVar_b = ((CurrSize << 4) & 0x0000FF00);
- TempVar_b |= ((CurrSize & 0x0000000F) | 0x00000040);
- TempVar_a = TempVar_b;
- ScopeAcpiTablesStructPtr->ScopeLength = (UINT16) TempVar_a;
- CurrSize = 0;
- }
-
- ScopeAcpiTablesStructPtr = ScopeAcpiTablesStructPtrTemp;
- }
- //Calculate next node buffer address
- PStateLevelingBufferStructPtr = (PSTATE_LEVELING *) ((UINT8 *) PStateLevelingBufferStructPtr + (UINTN) sizeof (PSTATE_LEVELING) + (UINTN) (PStateLevelingBufferStructPtr->PStateCoreStruct[0].PStateMaxValue * sizeof (S_PSTATE_VALUES)));
- }
- //Update SSDT header Checksum
- ((ACPI_TABLE_HEADER *) *SsdtPtr)->TableLength = (ScopeSize + CoreCount + sizeof (ACPI_TABLE_HEADER));
- ChecksumAcpiTable ((ACPI_TABLE_HEADER *) *SsdtPtr, StdHeader);
-
- return AGESA_SUCCESS;
-}
-
-/**--------------------------------------------------------------------------------------
- *
- * CreateAcpiTablesStub
- *
- * Description:
- * This is the default routine for use when the P-State or C-State option is NOT
- * requested. The option install process will create and fill the transfer vector
- * with the address of the proper routine (Main or Stub). The link optimizer will
- * strip out of the .DLL the routine that is not used.
- *
- * Parameters:
- * @param[in] PlatformConfig Platform operational characteristics; power cap
- * @param[in] PStateLevelingBuffer Buffer that contains P-State Leveling information
- * @param[in,out] SsdtPtr ACPI SSDT table pointer
- * @param[in] LocalApicId Local Apic Id
- * @param[in] StdHeader Handle to config for library and services
- *
- * @retval Size of generated ACPI objects
- *
- *---------------------------------------------------------------------------------------
- **/
-UINT32
-CreateAcpiTablesStub (
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN PSTATE_LEVELING *PStateLevelingBuffer,
- IN OUT VOID **SsdtPtr,
- IN UINT8 LocalApicId,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- return 0;
-}
-
-
-/**--------------------------------------------------------------------------------------
- *
- * CreatePStateAcpiTables
- *
- * Description:
- * This is the common routine for creating ACPI P-State objects
- *
- * Parameters:
- * @param[in] PlatformConfig Platform operational characteristics; power cap
- * @param[in] PStateLevelingBuffer Buffer that contains P-State Leveling information
- * @param[in,out] SsdtPtr ACPI SSDT table pointer
- * @param[in] LocalApicId Local Apic Id
- * @param[in] StdHeader Handle to config for library and services
- *
- * @retval Size of generated ACPI P-States objects
- *
- *---------------------------------------------------------------------------------------
- **/
-UINT32
-CreatePStateAcpiTables (
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN PSTATE_LEVELING *PStateLevelingBuffer,
- IN OUT VOID **SsdtPtr,
- IN UINT8 LocalApicId,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 PstateCapLevelSupport;
- UINT8 PStateMaxValueOnCurrentCore;
- BOOLEAN PstateCapEnable;
- BOOLEAN PstateCapLevelSupportDetermined;
- BOOLEAN IsPsdDependent;
- UINT32 k;
- UINT32 TempVar_a;
- UINT32 TempVar_b;
- UINT32 TempVar_c;
- UINT32 PstateCapInputMilliWatts;
- UINT32 CurrSize;
- UINT32 PstateCount;
- UINT32 CoreCount1;
- UINT32 TransAndBusMastLatency;
- AGESA_STATUS IgnoredStatus;
- PCI_ADDR PciAddress;
- PCT_HEADER_BODY *pPctAcpiTables;
- PSS_HEADER *pPssHeaderAcpiTables;
- PSS_BODY *pPssBodyAcpiTables;
- XPSS_HEADER *pXpssHeaderAcpiTables;
- XPSS_BODY *pXpssBodyAcpiTables;
- PSD_HEADER *pPsdHeaderAcpiTables;
- PSD_BODY *pPsdBodyAcpiTables;
- PPC_HEADER_BODY *pPpcAcpiTables;
- PSTATE_CPU_FAMILY_SERVICES *FamilyServices;
-
- CurrSize = 0;
- PstateCount = 0;
- PstateCapEnable = FALSE;
- PstateCapLevelSupport = DEFAULT_PERF_PRESENT_CAP;
- PstateCapLevelSupportDetermined = TRUE;
- PstateCapInputMilliWatts = PlatformConfig->PowerCeiling;
- IsPsdDependent = !(PlatformConfig->ForcePstateIndependent);
- TransAndBusMastLatency = 0;
-
- if ((PStateLevelingBuffer[0].CreateAcpiTables != 0) && (PlatformConfig->UserOptionPState)) {
- pPctAcpiTables = (PCT_HEADER_BODY *) *SsdtPtr;
-
- //Check Pstate Capability
- if (PstateCapInputMilliWatts != 0) {
- PstateCapEnable = TRUE;
- PstateCapLevelSupportDetermined = FALSE;
- }
-
- PStateMaxValueOnCurrentCore = PStateLevelingBuffer->PStateCoreStruct[0].PStateMaxValue;
- if (OptionPstateLateConfiguration.CfgPstatePct) {
- // Set _PCT Table
- // --------------
- pPctAcpiTables->NameOpcode = NAME_OPCODE;
- pPctAcpiTables->PctName_a__ = PCT_NAME__;
- pPctAcpiTables->PctName_a_P = PCT_NAME_P;
- pPctAcpiTables->PctName_a_C = PCT_NAME_C;
- pPctAcpiTables->PctName_a_T = PCT_NAME_T;
- pPctAcpiTables->Value1 = PCT_VALUE1;
- pPctAcpiTables->Value2 = PCT_VALUE2;
- pPctAcpiTables->Value3 = PCT_VALUE3;
- pPctAcpiTables->GenericRegDescription1 = GENERIC_REG_DESCRIPTION;
- pPctAcpiTables->Length1 = PCT_LENGTH;
- pPctAcpiTables->AddressSpaceId1 = PCT_ADDRESS_SPACE_ID;
- pPctAcpiTables->RegisterBitWidth1 = PCT_REGISTER_BIT_WIDTH;
- pPctAcpiTables->RegisterBitOffset1 = PCT_REGISTER_BIT_OFFSET;
- pPctAcpiTables->Reserved1 = PCT_RESERVED;
- pPctAcpiTables->ControlRegAddressLo = PCT_CONTROL_REG_LO;
- pPctAcpiTables->ControlRegAddressHi = PCT_CONTROL_REG_HI;
- pPctAcpiTables->Value4 = PCT_VALUE4;
- pPctAcpiTables->Value5 = PCT_VALUE5;
- pPctAcpiTables->GenericRegDescription2 = GENERIC_REG_DESCRIPTION;
- pPctAcpiTables->Length2 = PCT_LENGTH;
- pPctAcpiTables->AddressSpaceId2 = PCT_ADDRESS_SPACE_ID;
- pPctAcpiTables->RegisterBitWidth2 = PCT_REGISTER_BIT_WIDTH;
- pPctAcpiTables->RegisterBitOffset2 = PCT_REGISTER_BIT_OFFSET;
- pPctAcpiTables->Reserved2 = PCT_RESERVED;
- pPctAcpiTables->StatusRegAddressLo = PCT_STATUS_REG_LO;
- pPctAcpiTables->StatusRegAddressHi = PCT_STATUS_REG_HI;
- pPctAcpiTables->Value6 = PCT_VALUE6;
-
- // Increment and then typecast the pointer
- pPctAcpiTables++;
- CurrSize += PCT_STRUCT_SIZE;
-
- *SsdtPtr = pPctAcpiTables;
- } // end of OptionPstateLateConfiguration.CfgPstatePct
-
- pPssHeaderAcpiTables = (PSS_HEADER *) pPctAcpiTables;
- pPssBodyAcpiTables = (PSS_BODY *) pPctAcpiTables;
- if (OptionPstateLateConfiguration.CfgPstatePss) {
- // Set _PSS Header
- // Note: Set pssLength and numOfItemsInPss later
- //---------------------------------------------------
- pPssHeaderAcpiTables->NameOpcode = NAME_OPCODE;
- pPssHeaderAcpiTables->PssName_a__ = PSS_NAME__;
- pPssHeaderAcpiTables->PssName_a_P = PSS_NAME_P;
- pPssHeaderAcpiTables->PssName_a_S = PSS_NAME_S;
- pPssHeaderAcpiTables->PssName_b_S = PSS_NAME_S;
- pPssHeaderAcpiTables->PkgOpcode = PACKAGE_OPCODE;
-
- pPssHeaderAcpiTables++;
- pPssBodyAcpiTables = (PSS_BODY *) pPssHeaderAcpiTables;
- // Restore the pPssHeaderAcpiTables
- pPssHeaderAcpiTables--;
-
- // Set _PSS Body
- //---------------
- PstateCount = 0;
-
- // Calculate PCI address for socket only
- GetPciAddress (StdHeader, (UINT32) PStateLevelingBuffer->SocketNumber, 0, &PciAddress, &IgnoredStatus);
- TransAndBusMastLatency = 0;
- GetFeatureServicesOfSocket (&PstateFamilyServiceTable, (UINT32) PStateLevelingBuffer->SocketNumber, &FamilyServices, StdHeader);
- ASSERT (FamilyServices != NULL)
- FamilyServices->GetPstateLatency ( FamilyServices,
- PStateLevelingBuffer,
- &PciAddress,
- &TransAndBusMastLatency,
- StdHeader);
-
- for (k = 0; k <= PStateMaxValueOnCurrentCore; k++) {
- if (PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].PStateEnable != 0) {
- pPssBodyAcpiTables->PkgOpcode = PACKAGE_OPCODE;
- pPssBodyAcpiTables->PkgLength = PSS_PKG_LENGTH;
- pPssBodyAcpiTables->NumOfElements = PSS_NUM_OF_ELEMENTS;
- pPssBodyAcpiTables->DwordPrefixOpcode1 = DWORD_PREFIX_OPCODE;
- pPssBodyAcpiTables->Frequency =
- PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].CoreFreq;
- pPssBodyAcpiTables->DwordPrefixOpcode2 = DWORD_PREFIX_OPCODE;
- pPssBodyAcpiTables->Power =
- PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].Power;
-
- if (PstateCapEnable && (!PstateCapLevelSupportDetermined) && (PstateCapInputMilliWatts >= pPssBodyAcpiTables->Power)) {
- PstateCapLevelSupport = (UINT8) PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].SwPstateNumber;
- PstateCapLevelSupportDetermined = TRUE;
- }
-
- pPssBodyAcpiTables->DwordPrefixOpcode3 = DWORD_PREFIX_OPCODE;
- pPssBodyAcpiTables->TransitionLatency = TransAndBusMastLatency;
- pPssBodyAcpiTables->DwordPrefixOpcode4 = DWORD_PREFIX_OPCODE;
- pPssBodyAcpiTables->BusMasterLatency = TransAndBusMastLatency;
- pPssBodyAcpiTables->DwordPrefixOpcode5 = DWORD_PREFIX_OPCODE;
- pPssBodyAcpiTables->Control =
- PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].SwPstateNumber;
- pPssBodyAcpiTables->DwordPrefixOpcode6 = DWORD_PREFIX_OPCODE;
- pPssBodyAcpiTables->Status =
- PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].SwPstateNumber;
-
- pPssBodyAcpiTables++;
- PstateCount++;
- }
- } // for (k = 0; k < MPPSTATE_MAXIMUM_STATES; k++)
-
- if (PstateCapEnable && (!PstateCapLevelSupportDetermined)) {
- PstateCapLevelSupport = PStateMaxValueOnCurrentCore;
- }
-
- // Set _PSS Header again
- // Now Set pssLength and numOfItemsInPss
- //---------------------------------------
- TempVar_a = (PstateCount * PSS_BODY_STRUCT_SIZE) + 3;
- TempVar_b = TempVar_a;
- TempVar_c = ((TempVar_b << 4) & 0x0000FF00);
- TempVar_c = TempVar_c | ((TempVar_b & 0x0000000F) | 0x00000040);
- TempVar_a = (UINT16) TempVar_c;
-
- pPssHeaderAcpiTables->PssLength = (UINT16) TempVar_a;
- pPssHeaderAcpiTables->NumOfItemsInPss = (UINT8) PstateCount;
- CurrSize += (PSS_HEADER_STRUCT_SIZE + (PstateCount * PSS_BODY_STRUCT_SIZE));
-
- *SsdtPtr = pPssBodyAcpiTables;
- } // end of PSS Body if OptionPstateLateConfiguration.CfgPstatePss
-
- // Set XPSS Table
- //---------------
- // Typecast the pointer
- pXpssHeaderAcpiTables = (XPSS_HEADER *) pPssBodyAcpiTables;
- pXpssBodyAcpiTables = (XPSS_BODY *) pPssBodyAcpiTables;
- if (OptionPstateLateConfiguration.CfgPstateXpss) {
- // Set XPSS Header
- // Note: Set the pssLength and numOfItemsInPss later
- //---------------------------------------------------
- pXpssHeaderAcpiTables->NameOpcode = NAME_OPCODE;
- pXpssHeaderAcpiTables->XpssName_a_X = PSS_NAME_X;
- pXpssHeaderAcpiTables->XpssName_a_P = PSS_NAME_P;
- pXpssHeaderAcpiTables->XpssName_a_S = PSS_NAME_S;
- pXpssHeaderAcpiTables->XpssName_b_S = PSS_NAME_S;
- pXpssHeaderAcpiTables->PkgOpcode = PACKAGE_OPCODE;
-
- // Increment and then typecast the pointer
- pXpssHeaderAcpiTables++;
- pXpssBodyAcpiTables = (XPSS_BODY *) pXpssHeaderAcpiTables;
- // Restore the pXpssHeaderAcpiTables
- pXpssHeaderAcpiTables--;
-
- // Set XPSS Body
- //---------------
- for (k = 0; k <= PStateMaxValueOnCurrentCore; k++) {
- if (PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].PStateEnable != 0) {
- pXpssBodyAcpiTables->PkgOpcode = PACKAGE_OPCODE;
- pXpssBodyAcpiTables->PkgLength = XPSS_PKG_LENGTH;
- pXpssBodyAcpiTables->NumOfElements = XPSS_NUM_OF_ELEMENTS;
- pXpssBodyAcpiTables->XpssValueTbd = 04;
- pXpssBodyAcpiTables->DwordPrefixOpcode1 = DWORD_PREFIX_OPCODE;
- pXpssBodyAcpiTables->Frequency =
- PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].CoreFreq;
- pXpssBodyAcpiTables->DwordPrefixOpcode2 = DWORD_PREFIX_OPCODE;
- pXpssBodyAcpiTables->Power =
- PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].Power;
- pXpssBodyAcpiTables->DwordPrefixOpcode3 = DWORD_PREFIX_OPCODE;
- pXpssBodyAcpiTables->TransitionLatency = TransAndBusMastLatency;
- pXpssBodyAcpiTables->DwordPrefixOpcode4 = DWORD_PREFIX_OPCODE;
- pXpssBodyAcpiTables->BusMasterLatency = TransAndBusMastLatency;
- pXpssBodyAcpiTables->ControlBuffer = XPSS_ACPI_BUFFER;
- pXpssBodyAcpiTables->ControlLo =
- PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].SwPstateNumber;
- pXpssBodyAcpiTables->ControlHi = 0;
- pXpssBodyAcpiTables->StatusBuffer = XPSS_ACPI_BUFFER;
- pXpssBodyAcpiTables->StatusLo =
- PStateLevelingBuffer->PStateCoreStruct[0].PStateStruct[k].SwPstateNumber;
- pXpssBodyAcpiTables->StatusHi = 0;
- pXpssBodyAcpiTables->ControlMaskBuffer = XPSS_ACPI_BUFFER;
- pXpssBodyAcpiTables->ControlMaskLo = 0;
- pXpssBodyAcpiTables->ControlMaskHi = 0;
- pXpssBodyAcpiTables->StatusMaskBuffer = XPSS_ACPI_BUFFER;
- pXpssBodyAcpiTables->StatusMaskLo = 0;
- pXpssBodyAcpiTables->StatusMaskHi = 0;
-
- pXpssBodyAcpiTables++;
- }
- } // for (k = 0; k < MPPSTATE_MAXIMUM_STATES; k++)
-
- // Set XPSS Header again
- // Now set pssLength and numOfItemsInPss
- //---------------------------------------
- TempVar_a = (PstateCount * XPSS_BODY_STRUCT_SIZE) + 3;
- TempVar_b = TempVar_a;
- TempVar_c = ((TempVar_b << 4) & 0x0000FF00);
- TempVar_c = TempVar_c | ((TempVar_b & 0x0000000F) | 0x00000040);
- TempVar_a = (UINT16) TempVar_c;
-
- pXpssHeaderAcpiTables->XpssLength = (UINT16) TempVar_a;
- pXpssHeaderAcpiTables->NumOfItemsInXpss = (UINT8) PstateCount;
- CurrSize += (XPSS_HEADER_STRUCT_SIZE + (PstateCount * XPSS_BODY_STRUCT_SIZE));
-
- *SsdtPtr = pXpssBodyAcpiTables;
- } //end of XPSS Body OptionPstateLateConfiguration.CfgPstateXpss
-
- // Set _PSD Table
- //---------------
- // Typecast the pointer
- pPsdHeaderAcpiTables = (PSD_HEADER *) pXpssBodyAcpiTables;
- pPsdBodyAcpiTables = (PSD_BODY *) pXpssBodyAcpiTables;
- // Get Total Cores Per Node
- if (GetActiveCoresInGivenSocket ((UINT32) PStateLevelingBuffer->SocketNumber, &CoreCount1, StdHeader)) {
- GetFeatureServicesOfSocket (&PstateFamilyServiceTable, (UINT32) PStateLevelingBuffer->SocketNumber, &FamilyServices, StdHeader);
- ASSERT (FamilyServices != NULL)
- if ((CoreCount1 != 1) && (OptionPstateLateConfiguration.CfgPstatePsd) &&
- FamilyServices->IsPstatePsdNeeded (FamilyServices, PlatformConfig, StdHeader)) {
- // Set _PSD Header
- //----------------
- pPsdHeaderAcpiTables->NameOpcode = NAME_OPCODE;
- pPsdHeaderAcpiTables->PkgOpcode = PACKAGE_OPCODE;
- pPsdHeaderAcpiTables->PsdLength = PSD_HEADER_LENGTH;
- pPsdHeaderAcpiTables->Value1 = PSD_VALUE1;
- pPsdHeaderAcpiTables->PsdName_a__ = PSD_NAME__;
- pPsdHeaderAcpiTables->PsdName_a_P = PSD_NAME_P;
- pPsdHeaderAcpiTables->PsdName_a_S = PSD_NAME_S;
- pPsdHeaderAcpiTables->PsdName_a_D = PSD_NAME_D;
-
- // Typecast the pointer
- pPsdHeaderAcpiTables++;
- CurrSize += PSD_HEADER_STRUCT_SIZE;
- pPsdBodyAcpiTables = (PSD_BODY *) pPsdHeaderAcpiTables;
-
- pPsdHeaderAcpiTables--;
- // Set _PSD Body
- //--------------
- pPsdBodyAcpiTables->PkgOpcode = PACKAGE_OPCODE;
- pPsdBodyAcpiTables->PkgLength = PSD_PKG_LENGTH;
- pPsdBodyAcpiTables->NumOfEntries = NUM_OF_ENTRIES;
- pPsdBodyAcpiTables->BytePrefixOpcode1 = BYTE_PREFIX_OPCODE;
- pPsdBodyAcpiTables->PsdNumOfEntries = PSD_NUM_OF_ENTRIES;
- pPsdBodyAcpiTables->BytePrefixOpcode2 = BYTE_PREFIX_OPCODE;
- pPsdBodyAcpiTables->PsdRevision = PSD_REVISION;
- pPsdBodyAcpiTables->DwordPrefixOpcode1 = DWORD_PREFIX_OPCODE;
-
- IsPsdDependent = FamilyServices->IsPstatePsdDependent (FamilyServices, PlatformConfig, StdHeader);
-
- if (IsPsdDependent) {
- pPsdBodyAcpiTables->DependencyDomain = PSD_DEPENDENCY_DOMAIN;
- pPsdBodyAcpiTables->CoordinationType = PSD_COORDINATION_TYPE_SW_ALL;
- pPsdBodyAcpiTables->NumOfProcessors = CoreCount1;
- } else {
- switch (GetComputeUnitMapping (StdHeader)) {
- case AllCoresMapping:
- // All cores are in their own compute unit.
- pPsdBodyAcpiTables->DependencyDomain = LocalApicId;
- pPsdBodyAcpiTables->CoordinationType = PSD_COORDINATION_TYPE_SW_ANY;
- pPsdBodyAcpiTables->NumOfProcessors = PSD_NUM_OF_PROCESSORS;
- break;
- case EvenCoresMapping:
- // Cores are paired in compute units.
- pPsdBodyAcpiTables->DependencyDomain = (LocalApicId >> 1) & PSD_DOMAIN_COMPUTE_UNIT_MASK;
- pPsdBodyAcpiTables->CoordinationType = PSD_COORDINATION_TYPE_HW_ALL;
- pPsdBodyAcpiTables->NumOfProcessors = PSD_CORE_NUM_PER_COMPUTE_UNIT;
- break;
- default:
- ASSERT (FALSE);
- }
- }
- pPsdBodyAcpiTables->DwordPrefixOpcode2 = DWORD_PREFIX_OPCODE;
- pPsdBodyAcpiTables->DwordPrefixOpcode3 = DWORD_PREFIX_OPCODE;
-
- pPsdBodyAcpiTables++;
- *SsdtPtr = pPsdBodyAcpiTables;
- CurrSize += PSD_BODY_STRUCT_SIZE;
- }
- }// end of PSD Body if (CoreCount1 != 1) || (OptionPstateLateConfiguration.CfgPstatePsd)
- // Typecast the pointer
-
- pPpcAcpiTables = (PPC_HEADER_BODY *) pPsdBodyAcpiTables;
-
- // Set _PPC Table
- //---------------
- if (OptionPstateLateConfiguration.CfgPstatePpc) {
- pPpcAcpiTables->NameOpcode = NAME_OPCODE;
- pPpcAcpiTables->PpcName_a__ = PPC_NAME__;
- pPpcAcpiTables->PpcName_a_P = PPC_NAME_P;
- pPpcAcpiTables->PpcName_b_P = PPC_NAME_P;
- pPpcAcpiTables->PpcName_a_C = PPC_NAME_C;
- pPpcAcpiTables->Value1 = PPC_VALUE1;
-
- pPpcAcpiTables->DefaultPerfPresentCap = PstateCapLevelSupport;
- CurrSize += PPC_HEADER_BODY_STRUCT_SIZE;
- // Increment and typecast the pointer
- pPpcAcpiTables++;
- *SsdtPtr = pPpcAcpiTables;
- }// end of OptionPstateLateConfiguration.CfgPstatePpc
- }
- return CurrSize;
-}
-
-/**--------------------------------------------------------------------------------------
- *
- * CreateCStateAcpiTables
- *
- * Description:
- * This is the common routine for creating ACPI C-State objects
- *
- * Parameters:
- * @param[in] PlatformConfig Platform operational characteristics; power cap
- * @param[in] PStateLevelingBuffer Buffer that contains P-State Leveling information
- * @param[in,out] SsdtPtr ACPI SSDT table pointer
- * @param[in] LocalApicId Local Apic Id
- * @param[in] StdHeader Handle to config for library and services
- *
- * @retval Size of ACPI C-States objects generated
- *
- *---------------------------------------------------------------------------------------
- **/
-UINT32
-CreateCStateAcpiTables (
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN PSTATE_LEVELING *PStateLevelingBuffer,
- IN OUT VOID **SsdtPtr,
- IN UINT8 LocalApicId,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 ObjSize;
- IO_CSTATE_FAMILY_SERVICES *IoCstateFamilyServices;
-
- ObjSize = 0;
-
- if (IsFeatureEnabled (IoCstate, PlatformConfig, StdHeader)) {
- GetFeatureServicesOfCurrentCore (&IoCstateFamilyServiceTable, &IoCstateFamilyServices, StdHeader);
- // If we're supporting multiple families, only proceed when IO Cstate family services are available
- if (IoCstateFamilyServices != NULL) {
- IoCstateFamilyServices->CreateAcpiCstObj (IoCstateFamilyServices, LocalApicId, SsdtPtr, StdHeader);
- ObjSize = IoCstateFamilyServices->GetAcpiCstObj (IoCstateFamilyServices, PlatformConfig, StdHeader);
- }
- }
- return ObjSize;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuPstateTables.h b/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuPstateTables.h
deleted file mode 100644
index 3e8ada7..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuPstateTables.h
+++ /dev/null
@@ -1,329 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD AGESA CPU Pstate Table Functions declarations.
- *
- * Contains code that declares the AGESA CPU _PSS related APIs
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/Feature
- * @e \$Revision: 36567 $ @e \$Date: 2010-08-21 02:35:15 +0800 (Sat, 21 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPU_PSTATE_TABLES_H_
-#define _CPU_PSTATE_TABLES_H_
-
-/*----------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *----------------------------------------------------------------------------------------
- */
-// Forward declaration needed for multi-structure mutual references
-AGESA_FORWARD_DECLARATION (PSTATE_CPU_FAMILY_SERVICES);
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-/// P-state structure for each state
-typedef struct {
- IN OUT UINT32 PStateEnable; ///< Pstate enable
- IN OUT UINT32 CoreFreq; ///< MHz
- IN OUT UINT32 Power; ///< milliWatts
- IN OUT UINT32 IddValue; ///< Current value field
- IN OUT UINT32 IddDiv; ///< Current divisor field
- IN OUT UINT32 SwPstateNumber; ///< Software P-state number
-} S_PSTATE_VALUES;
-
-/// P-state structure for each core
-typedef struct {
- IN OUT UINT8 PStateMaxValue; ///< Max p-state number in this core
- IN OUT UINT8 HtcPstateLimit; ///< Htc limit
- IN OUT UINT8 HtcCapable; ///< Htc capable
- IN OUT UINT8 LocalApicId; ///< Local Apic Id
- IN OUT S_PSTATE_VALUES PStateStruct[1]; ///< P state struc
-} S_PSTATE;
-
-/// P-state structure for each node
-typedef struct {
- IN UINT8 SetPState0; ///< If value = 0x55 (Don't set PState0)
- IN UINT8 TotalCoresInNode; ///< core number per node
- IN UINT16 PStateLevelingSizeOfBytes; ///< Size
- IN BOOLEAN OnlyOneEnabledPState; ///< Only P0
- IN UINT8 InitStruct; ///< Init struc
- IN BOOLEAN AllCpusHaveIdenticalPStates; ///< Have Identical p state
- IN UINT8 CreateAcpiTables; ///< Create table flag
- IN UINT8 SocketNumber; ///< Physical socket number of this socket
- IN UINT8 Reserved[3]; ///< Reserved.
- IN OUT S_PSTATE PStateCoreStruct[1]; ///< P state core struc
-} PSTATE_LEVELING;
-
-/// P-state structure for whole system
-typedef struct {
- IN OUT UINT32 TotalSocketInSystem; ///< Total node number in system
- IN OUT UINT32 SizeOfBytes; ///< Structure size
- IN OUT PSTATE_LEVELING PStateLevelingStruc[1]; ///< P state level structure
-} S_CPU_AMD_PSTATE;
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family specific call to check if PSD need to be generated.
- *
- * @param[in] PstateCpuFamilyServices Pstate CPU services.
- * @param[in,out] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval TRUE PSD need to be generated
- * @retval FALSE PSD does NOT need to be generated
- *
- */
-typedef BOOLEAN F_PSTATE_PSD_IS_NEEDED (
- IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
- IN OUT PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_PSTATE_PSD_IS_NEEDED *PF_PSTATE_PSD_IS_NEEDED;
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family specific call to check if Pstate PSD is dependent.
- *
- * @param[in] PstateCpuFamilyServices Pstate CPU services.
- * @param[in,out] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval TRUE PSD is dependent.
- * @retval FALSE PSD is independent.
- *
- */
-typedef BOOLEAN F_PSTATE_PSD_IS_DEPENDENT (
- IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
- IN OUT PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_PSTATE_PSD_IS_DEPENDENT *PF_PSTATE_PSD_IS_DEPENDENT;
-
-/**
- * Family specific call to set core TscFreqSel.
- *
- * @param[in] PstateCpuFamilyServices Pstate CPU services.
- * @param[in] StdHeader Config Handle for library, services.
- *
- */
-typedef VOID F_PSTATE_SET_TSC_FREQ_SEL (
- IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_PSTATE_SET_TSC_FREQ_SEL *PF_PSTATE_SET_TSC_FREQ_SEL;
-
-/**
- * Family specific call to get CPU pstate transition latency for current socket.
- *
- * @param[in] PstateCpuFamilyServices Pstate CPU services.
- * @param[in] PStateLevelingBufferStructPtr Pstate row data buffer pointer.
- * @param[in] PciAddress Pci address struct.
- * @param[out] TransitionLatency Pstate Transition latency result.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- */
-typedef AGESA_STATUS F_CPU_PSTATE_TRANSITION_LATENCY (
- IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
- IN PSTATE_LEVELING *PStateLevelingBufferStructPtr,
- IN PCI_ADDR *PciAddress,
- OUT UINT32 *TransitionLatency,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_CPU_PSTATE_TRANSITION_LATENCY *PF_CPU_PSTATE_TRANSITION_LATENCY;
-
-/**
- * Family specific call to get the desired P-state's frequency in megahertz.
- *
- * @param[in] PstateCpuFamilyServices Pstate CPU services.
- * @param[in] StateNumber P-state number.
- * @param[out] PowerInMw P-state frequency in megahertz.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- */
-typedef AGESA_STATUS F_CPU_GET_PSTATE_FREQ (
- IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
- IN UINT8 StateNumber,
- OUT UINT32 *FreqInMHz,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_CPU_GET_PSTATE_FREQ *PF_CPU_GET_PSTATE_FREQ;
-
-/**
- * Family specific call to set the system wide P-state settings on the current core.
- *
- * @param[in] PstateCpuFamilyServices Pstate CPU services.
- * @param[in] CpuAmdPState The current core's P-state data.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- */
-typedef AGESA_STATUS F_CPU_SET_PSTATE_LEVELING_REG (
- IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
- IN S_CPU_AMD_PSTATE *CpuAmdPState,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_CPU_SET_PSTATE_LEVELING_REG *PF_CPU_SET_PSTATE_LEVELING_REG;
-
-/**
- * Family specific call to get the desired P-state's rated power in milliwatts.
- *
- * @param[in] PstateCpuFamilyServices Pstate CPU services.
- * @param[in] StateNumber P-state number.
- * @param[out] PowerInMw P-state power in milliwatts.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- */
-typedef AGESA_STATUS F_CPU_GET_PSTATE_POWER (
- IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
- IN UINT8 StateNumber,
- OUT UINT32 *PowerInMw,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_CPU_GET_PSTATE_POWER *PF_CPU_GET_PSTATE_POWER;
-
-/**
- * Family specific call to get CPU Pstate Max State.
- *
- * @param[in] PstateCpuFamilyServices Pstate CPU services.
- * @param[out] MaxPStateNumber The value return max pstate value current socket.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- */
-typedef AGESA_STATUS F_CPU_GET_PSTATE_MAX_STATE (
- IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
- OUT UINT32 *MaxPStateNumber,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_CPU_GET_PSTATE_MAX_STATE *PF_CPU_GET_PSTATE_MAX_STATE;
-
-/**
- * Family specific call to get CPU pstate register information.
- *
- * @param[in] PstateCpuFamilyServices Pstate CPU services.
- * @param[in] PState Input Pstate number for query.
- * @param[out] PStateEnabled Boolean flag return pstate enable.
- * @param[in,out] IddVal Pstate current value.
- * @param[in,out] IddDiv Pstate current divisor.
- * @param[out] SwPstateNumber Software P-state number.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- */
-typedef AGESA_STATUS F_CPU_GET_PSTATE_REGISTER_INFO (
- IN PSTATE_CPU_FAMILY_SERVICES *PstateCpuServices,
- IN UINT32 PState,
- OUT BOOLEAN *PStateEnabled,
- IN OUT UINT32 *IddVal,
- IN OUT UINT32 *IddDiv,
- OUT UINT32 *SwPstateNumber,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_CPU_GET_PSTATE_REGISTER_INFO *PF_CPU_GET_PSTATE_REGISTER_INFO;
-
-/**
- * Provide the interface to the Pstate dependent Family Specific Services.
- *
- * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
- * Each supported Family must provide an implementation for all methods in this interface, even if the
- * implementation is a CommonReturn().
- */
-struct _PSTATE_CPU_FAMILY_SERVICES {
- UINT16 Revision; ///< Interface version
- // Public Methods.
- PF_PSTATE_PSD_IS_NEEDED IsPstatePsdNeeded; ///< Method: Family specific call to check if PSD need to be generated.
- PF_PSTATE_PSD_IS_DEPENDENT IsPstatePsdDependent; ///< Method: Family specific call to check if PSD is dependent.
- PF_PSTATE_SET_TSC_FREQ_SEL CpuSetTscFreqSel; ///< Method: Family specific call to set core TscFreqSel.
- PF_CPU_PSTATE_TRANSITION_LATENCY GetPstateLatency; ///< Method: Family specific call to get pstate transition latency.
- PF_CPU_GET_PSTATE_FREQ GetPstateFrequency; ///< Method: Family specific call to get the desired P-state's frequency in megahertz.
- PF_CPU_SET_PSTATE_LEVELING_REG SetPStateLevelReg; ///< Method: Family specific call to set the system wide P-state settings on the current core.
- PF_CPU_GET_PSTATE_POWER GetPstatePower; ///< Method: Family specific call to get the desired P-state's rated power in milliwatts.
- PF_CPU_GET_PSTATE_MAX_STATE GetPstateMaxState; ///< Method: Family specific call to get pstate max state number.
- PF_CPU_GET_PSTATE_REGISTER_INFO GetPstateRegisterInfo; ///< Method: Family specific call to get pstate register information.
-};
-
-
-/*----------------------------------------------------------------------------------------
- * F U N C T I O N S P R O T O T Y P E
- *----------------------------------------------------------------------------------------
- */
-AGESA_STATUS
-PStateGatherData (
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-PStateLeveling (
- IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-CpuGetPStateLevelStructure (
- OUT PSTATE_LEVELING **PStateBufferPtr,
- IN S_CPU_AMD_PSTATE *CpuAmdPState,
- IN UINT32 LogicalSocketNumber,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif // _CPU_PSTATE_TABLES_H_
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuSlit.c b/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuSlit.c
deleted file mode 100644
index 7056722..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuSlit.c
+++ /dev/null
@@ -1,357 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD SLIT, ACPI table related API functions.
- *
- * Contains code that generates the SLIT table
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------
- * This file provides functions, that will generate SLIT tables
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "OptionSlit.h"
-#include "heapManager.h"
-#include "cpuLateInit.h"
-#include "cpuRegisters.h"
-#include "Topology.h"
-#include "Ids.h"
-#include "cpuFeatures.h"
-#include "Filecode.h"
-CODE_GROUP (G3_DXE)
-RDATA_GROUP (G3_DXE)
-
-#define FILECODE PROC_CPU_FEATURE_CPUSLIT_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-extern OPTION_SLIT_CONFIGURATION OptionSlitConfiguration; // global user config record
-
-STATIC ACPI_TABLE_HEADER ROMDATA CpuSlitHdrStruct =
-{
- 'S','L','I','T',
- 0,
- 1,
- 0,
- 'A','M','D',' ',' ',' ',
- 'A','G','E','S','A',' ',' ',' ',
- 1,
- 'A','M','D',' ',
- 1
-};
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-VOID
-STATIC
-AcpiSlitHBufferFind (
- IN OUT AMD_CONFIG_PARAMS *StdHeader,
- IN UINT8 **SocketTopologyPtr
- );
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * This function generates a complete SLIT table into a memory buffer.
- * After completion, this table must be set by the system BIOS into its
- * internal ACPI namespace, and linked into the RSDT/XSDT
- *
- * @param[in, out] StdHeader Standard Head Pointer
- * @param[in] PlatformConfig Config handle for platform specific information
- * @param[in, out] SlitPtr Point to Slit Struct including buffer address and length
- *
- * @retval UINT32 AGESA_STATUS
- */
-AGESA_STATUS
-CreateAcpiSlit (
- IN OUT AMD_CONFIG_PARAMS *StdHeader,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN OUT VOID **SlitPtr
- )
-{
- AGESA_TESTPOINT (TpProcCpuEntrySlit, StdHeader);
- return ((*(OptionSlitConfiguration.SlitFeature)) (StdHeader, PlatformConfig, SlitPtr));
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * This is the default routine for use when the SLIT option is NOT requested.
- *
- * The option install process will create and fill the transfer vector with
- * the address of the proper routine (Main or Stub). The link optimizer will
- * strip out of the .DLL the routine that is not used.
- *
- * @param[in, out] StdHeader Standard Head Pointer
- * @param[in] PlatformConfig Config handle for platform specific information
- * @param[in, out] SlitPtr Point to Slit Struct including buffer address and length
- *
- * @retval AGESA_STATUS
- */
-
-AGESA_STATUS
-GetAcpiSlitStub (
- IN OUT AMD_CONFIG_PARAMS *StdHeader,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN OUT VOID **SlitPtr
- )
-{
- return AGESA_UNSUPPORTED;
-}
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * This function generates a complete SLIT table into a memory buffer.
- * After completion, this table must be set by the system BIOS into its
- * internal ACPI namespace, and linked into the RSDT/XSDT
- *
- * @param[in, out] StdHeader Standard Head Pointer
- * @param[in] PlatformConfig Config handle for platform specific information
- * @param[in, out] SlitPtr Point to Slit Struct including buffer address and length
- *
- * @retval UINT32 AGESA_STATUS
- */
-AGESA_STATUS
-GetAcpiSlitMain (
- IN OUT AMD_CONFIG_PARAMS *StdHeader,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN OUT VOID **SlitPtr
- )
-{
- UINT8 MaxHops;
- UINT8 SocketNum;
- UINT8 i;
- UINT8 j;
- UINT8 *BufferPtr;
- UINT8 *SocketTopologyDataPtr;
- UINT8 *SocketTopologyPtr;
- ACPI_TABLE_HEADER *CpuSlitHeaderStructPtr;
- AGESA_STATUS Flag;
- ALLOCATE_HEAP_PARAMS AllocStruct;
-
- MaxHops = 0;
- SocketTopologyPtr = NULL;
- Flag = AGESA_ERROR;
-
- // find out the pointer to the BufferHandle which contains
- // Node Topology information
- AcpiSlitHBufferFind (StdHeader, &SocketTopologyPtr);
- if (SocketTopologyPtr == 0) {
- return (Flag);
- }
-
- SocketNum = *SocketTopologyPtr;
-
- IDS_HDT_CONSOLE (CPU_TRACE, " SLIT is created\n");
-
- // create a buffer by calling IBV callout routine
- AllocStruct.RequestedBufferSize = (SocketNum * SocketNum) + AMD_ACPI_SLIT_SOCKET_NUM_LENGTH + sizeof (ACPI_TABLE_HEADER);
- AllocStruct.BufferHandle = AMD_ACPI_SLIT_BUFFER_HANDLE;
- AllocStruct.Persist = HEAP_SYSTEM_MEM;
- if (HeapAllocateBuffer (&AllocStruct, StdHeader) != AGESA_SUCCESS) {
- return (Flag);
- }
- *SlitPtr = AllocStruct.BufferPtr;
-
- //SLIT header
- LibAmdMemCopy (*SlitPtr, (VOID *) &CpuSlitHdrStruct, (UINTN) (sizeof (ACPI_TABLE_HEADER)), StdHeader);
- CpuSlitHeaderStructPtr = (ACPI_TABLE_HEADER *) *SlitPtr;
- CpuSlitHeaderStructPtr->TableLength = (UINT32) AllocStruct.RequestedBufferSize;
- BufferPtr = *SlitPtr;
-
- Flag = AGESA_SUCCESS;
- // SLIT body
- // check if is PfMode (Prober Filer Mode)
- if (!IsFeatureEnabled (HtAssist, PlatformConfig, StdHeader)) {
- // probe filter is disabled
-
- // get MaxHops
- SocketTopologyDataPtr = SocketTopologyPtr + sizeof (SocketNum);
- for (i = 0; i < SocketNum; i++) {
- for (j = 0; j < SocketNum; j++) {
- if (*SocketTopologyDataPtr > MaxHops) {
- MaxHops = *SocketTopologyDataPtr;
- }
- SocketTopologyDataPtr++;
- }
- }
-
- // the Max hop entries have a value of 13
- // and all other entries have 10.
- SocketTopologyDataPtr = SocketTopologyPtr + sizeof (SocketNum);
- for (i = 0; i < SocketNum; i++) {
- for (j = 0; j < SocketNum; j++) {
- if (*SocketTopologyDataPtr++ == MaxHops) {
- *(BufferPtr + sizeof (ACPI_TABLE_HEADER) +
- AMD_ACPI_SLIT_SOCKET_NUM_LENGTH + (i * SocketNum) + j) = 13;
- } else {
- *(BufferPtr + sizeof (ACPI_TABLE_HEADER) +
- AMD_ACPI_SLIT_SOCKET_NUM_LENGTH + (i * SocketNum) + j) = 10;
- }
- }
- }
- } else {
- // probe filter is enabled
-
- // formula : num_hops * 6 + 10
- SocketTopologyDataPtr = SocketTopologyPtr + sizeof (SocketNum);
- for (i = 0; i < SocketNum; i++) {
- for (j = 0; j < SocketNum; j++) {
- *(BufferPtr + sizeof (ACPI_TABLE_HEADER) +
- AMD_ACPI_SLIT_SOCKET_NUM_LENGTH + (i * SocketNum) + j) =
- ((*SocketTopologyDataPtr++) * 6) + 10;
- }
- }
- }
-
- BufferPtr += sizeof (ACPI_TABLE_HEADER);
- *((UINT64 *) BufferPtr) = (UINT64) SocketNum;
-
- //Update SLIT header Checksum
- ChecksumAcpiTable ((ACPI_TABLE_HEADER *) *SlitPtr, StdHeader);
-
- return (Flag);
-}
-
-/*---------------------------------------------------------------------------------------
- * L O C A L F U N C T I O N S
- *---------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * Find out the pointer to the BufferHandle which contains
- * Node Topology information
- *
- * @param[in, out] StdHeader Standard Head Pointer
- * @param[in] SocketTopologyPtr Point to the address of Socket Topology
- *
- */
-VOID
-STATIC
-AcpiSlitHBufferFind (
- IN OUT AMD_CONFIG_PARAMS *StdHeader,
- IN UINT8 **SocketTopologyPtr
- )
-{
- LOCATE_HEAP_PTR LocateBuffer;
-
- LocateBuffer.BufferHandle = HOP_COUNT_TABLE_HANDLE;
- if (HeapLocateBuffer (&LocateBuffer, StdHeader) == AGESA_SUCCESS) {
- *SocketTopologyPtr = (UINT8 *) LocateBuffer.BufferPtr;
- }
-
- return;
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- * ReleaseSlitBufferStub
- *
- * Description:
- * This is the default routine for use when the SLIT option is NOT requested.
- *
- * Parameters:
- * @param[in, out] *StdHeader
- *
- * @retval AGESA_STATUS
- *
- */
-AGESA_STATUS
-ReleaseSlitBufferStub (
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- return AGESA_UNSUPPORTED;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- * ReleaseSlitBuffer
- *
- * Description:
- * Deallocate SLIT buffer
- *
- * Parameters:
- * @param[in, out] *StdHeader
- *
- * @retval AGESA_STATUS
- *
- */
-AGESA_STATUS
-ReleaseSlitBuffer (
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- HeapDeallocateBuffer ((UINT32) HOP_COUNT_TABLE_HANDLE, StdHeader);
-
- return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuSrat.c b/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuSrat.c
deleted file mode 100644
index e3ba902..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuSrat.c
+++ /dev/null
@@ -1,565 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD SRAT, ACPI table related API functions.
- *
- * Contains code that Create the APCI SRAT Table after early reset.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 35658 $ @e \$Date: 2010-07-28 18:11:31 +0800 (Wed, 28 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "cpuServices.h"
-#include "OptionSrat.h"
-#include "heapManager.h"
-#include "cpuRegisters.h"
-#include "cpuLateInit.h"
-#include "Ids.h"
-#include "Filecode.h"
-CODE_GROUP (G3_DXE)
-RDATA_GROUP (G3_DXE)
-
-#define FILECODE PROC_CPU_FEATURE_CPUSRAT_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-extern OPTION_SRAT_CONFIGURATION OptionSratConfiguration; // global user config record
-
-#define NodeID 0x60
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * All of the DATA should be defined in _CODE segment.
- * Use ROMDATA to specify that it belongs to _CODE.
- *----------------------------------------------------------------------------
- */
-STATIC CPU_SRAT_HEADER ROMDATA CpuSratHdrStruct =
-{
- 'S','R','A','T',
- 0,
- 2,
- 0,
- 'A','M','D',' ',' ',' ',
- 'A','G','E','S','A',' ',' ',' ',
- 1,
- 'A','M','D',' ',
- 1,
- 1,
- {0, 0, 0, 0, 0, 0, 0, 0}
-};
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-UINT8
-STATIC
-*MakeApicEntry (
- IN UINT8 ApicId,
- IN UINT8 Domain,
- IN UINT8 *BufferLocPtr
- );
-
-UINT8
-STATIC
-*FillMemoryForCurrentNode (
- IN UINT8 *PDomain,
- IN OUT UINT8 *PDomainForBase640K,
- IN UINT8 Node,
- IN OUT UINT8 *BufferLocPtr,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-UINT8
-STATIC
-*MakeMemEntry (
- IN UINT8 PDomain,
- IN UINT8 Node,
- IN UINT32 Base,
- IN UINT32 Size,
- IN UINT8 *BufferLocPtr
- );
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * This function will generate a complete Static Resource Affinity Table
- * i.e. SRAT into a memory buffer. After completion, this table must be set
- * by the system BIOS into its internal ACPI name space.
- *
- * @param[in, out] StdHeader Standard Head Pointer
- * @param[in, out] SratPtr Point to Srat Struct including buffer address and length
- *
- * @retval AGESA_STATUS
- */
-
-AGESA_STATUS
-CreateAcpiSrat (
- IN OUT AMD_CONFIG_PARAMS *StdHeader,
- IN OUT VOID **SratPtr
- )
-{
- AGESA_TESTPOINT (TpProcCpuEntrySrat, StdHeader);
- return ((*(OptionSratConfiguration.SratFeature)) (StdHeader, SratPtr));
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * This is the default routine for use when the SRAT option is NOT requested.
- *
- * The option install process will create and fill the transfer vector with
- * the address of the proper routine (Main or Stub). The link optimizer will
- * strip out of the .DLL the routine that is not used.
- *
- * @param[in, out] StdHeader Standard Head Pointer
- * @param[in, out] SratPtr Point to Srat Struct including buffer address and length
- *
- * @retval AGESA_STATUS
- */
-
-AGESA_STATUS
-GetAcpiSratStub (
- IN OUT AMD_CONFIG_PARAMS *StdHeader,
- IN OUT VOID **SratPtr
- )
-{
- return AGESA_UNSUPPORTED;
-}
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * This function will generate a complete Static Resource Affinity Table
- * i.e. SRAT into a memory buffer. After completion, this table must be set
- * by the system BIOS into its internal ACPI name space.
- *
- * @param[in, out] StdHeader Standard Head Pointer
- * @param[in, out] SratPtr Point to Srat Struct including buffer address and length
- *
- * @retval AGESA_STATUS
- */
-AGESA_STATUS
-GetAcpiSratMain (
- IN OUT AMD_CONFIG_PARAMS *StdHeader,
- IN OUT VOID **SratPtr
- )
-{
- UINT8 *BufferPtr;
- UINT8 NodeNum;
- UINT8 NodeCount;
- UINT8 PDomain;
- UINT8 PDomainForBase640K;
- UINT32 Socket;
- UINT32 Module;
- UINT32 LowCore;
- UINT32 HighCore;
- UINT32 CoreNum;
- UINT32 RegVal;
- UINT32 tempVar_32;
- AMD_APIC_PARAMS ApicParams;
- PCI_ADDR PciAddress;
- CPU_SRAT_HEADER *CpuSratHeaderStructPtr;
- ALLOCATE_HEAP_PARAMS AllocParams;
-
- // Get Node count
- PciAddress.AddressValue = MAKE_SBDFO (0, 0, LOW_NODE_DEVICEID, FUNC_0, NodeID);
- LibAmdPciRead (AccessWidth32 , PciAddress, &RegVal, StdHeader);
- NodeCount = (UINT8) (((RegVal >> 4) & 0x7) + 1);
-
- // The worst-case buffer size to request is for the SRAT table header, one
- // entree for special region (base 640k block), two memory
- // regions per node, and APIC entries for each core in the system.
- tempVar_32 = (sizeof (CPU_SRAT_HEADER)) + (sizeof (CPU_SRAT_MEMORY_ENTRY))
- + ((UINT32) NodeCount * (2 * (sizeof (CPU_SRAT_MEMORY_ENTRY))
- + ((UINT32) GetActiveCoresInCurrentModule (StdHeader) * sizeof (CPU_SRAT_APIC_ENTRY))));
-
- if (*SratPtr == NULL) {
- //
- // Allocate a buffer
- //
- AllocParams.RequestedBufferSize = tempVar_32;
- AllocParams.BufferHandle = AMD_SRAT_INFO_BUFFER_HANDLE;
- AllocParams.Persist = HEAP_SYSTEM_MEM;
-
- AGESA_TESTPOINT (TpProcCpuBeforeAllocateSratBuffer, StdHeader);
- if (HeapAllocateBuffer (&AllocParams, StdHeader) != AGESA_SUCCESS) {
- return AGESA_ERROR;
- }
- AGESA_TESTPOINT (TpProcCpuAfterAllocateSratBuffer, StdHeader);
-
- *SratPtr = AllocParams.BufferPtr;
- }
-
- IDS_HDT_CONSOLE (CPU_TRACE, " SRAT is created\n");
-
- CpuSratHeaderStructPtr = (CPU_SRAT_HEADER *) *SratPtr;
- BufferPtr = (UINT8 *) *SratPtr;
-
- // Copy acpiSRATHeader -> data buffer
- LibAmdMemCopy (*SratPtr, (VOID *) &CpuSratHdrStruct, (UINTN) (sizeof (CPU_SRAT_HEADER)), StdHeader);
-
- BufferPtr += sizeof (CPU_SRAT_HEADER);
-
- // Place all memory and IO affinity entries
- NodeNum = 0;
- PDomain = 0;
- PDomainForBase640K = 0xFF;
- ApicParams.StdHeader = *StdHeader;
- while (NodeNum < NodeCount) {
- GetSocketModuleOfNode ((UINT32) NodeNum, &Socket, &Module, StdHeader);
- GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader);
- BufferPtr = FillMemoryForCurrentNode (&PDomain, &PDomainForBase640K, NodeNum, BufferPtr, StdHeader);
- for (CoreNum = LowCore; CoreNum <= HighCore; CoreNum++) {
- ApicParams.Socket = (UINT8) Socket;
- ApicParams.Core = (UINT8) CoreNum;
- AmdGetApicId (&ApicParams);
- if (ApicParams.IsPresent) {
- BufferPtr = MakeApicEntry (ApicParams.ApicAddress, PDomain, BufferPtr);
- }
- }
-
- NodeNum++;
- PDomain = NodeNum;
- }
-
- // Store size in table (current buffer offset - buffer start offset)
- CpuSratHeaderStructPtr->TableLength = (UINT32) (BufferPtr - (UINT8 *) CpuSratHeaderStructPtr);
-
- //Update SSDT header Checksum
- ChecksumAcpiTable ((ACPI_TABLE_HEADER *) CpuSratHeaderStructPtr, StdHeader);
-
- return AGESA_SUCCESS;
-}
-
-
-/*----------------------------------------------------------------------------------------
- * L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * This function will build Memory entry for current node.
- * Note that we only create a memory affinity entry if we find one
- * that matches the current node. This makes an easier to read table
- * though it is not necessary.
- *
- * @param[in] PDomain Proximity Domain
- * @param[in, out] PDomainForBase640K The PDomain for Base 640K
- * @param[in] Node The number of Node
- * @param[in, out] BufferLocPtr Point to the address of buffer
- * @param[in, out] StdHeader Standard Head Pointer
- *
- * @retval UINT8 *(New buffer location ptr)
- */
-UINT8
-STATIC
-*FillMemoryForCurrentNode (
- IN UINT8 *PDomain,
- IN OUT UINT8 *PDomainForBase640K,
- IN UINT8 Node,
- IN OUT UINT8 *BufferLocPtr,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 ValueLimit;
- UINT32 ValueTOM;
- BOOLEAN isModified;
- UINT8 Domain;
- UINT32 RegVal;
- UINT32 DramLeng;
- UINT32 DramBase;
- UINT32 DramLimit;
- UINT32 OffsetRegs;
- PCI_ADDR PciAddress;
- UINT64 MsrValue;
-
- Domain = *PDomain;
-
- PciAddress.Address.Segment = 0;
- PciAddress.Address.Bus = 0;
- PciAddress.Address.Device = LOW_NODE_DEVICEID;
- PciAddress.Address.Function = FUNC_1;
-
- for (OffsetRegs = DRAMBase0; OffsetRegs < MMIOBase0; OffsetRegs += 8) {
- isModified = FALSE; // FALSE means normal update procedure
- // Get DRAM Base Address
- PciAddress.Address.Register = OffsetRegs;
- LibAmdPciRead (AccessWidth32, PciAddress, &RegVal, StdHeader);
- if ((RegVal & 3) != 3) {
- // 0:1 set if memory range enabled
- // Not set, so we don't have an enabled range
- continue; // Proceed to next Base register
- }
-
- // Get DRAM Limit
- PciAddress.Address.Register = OffsetRegs + 4;
- LibAmdPciRead (AccessWidth32, PciAddress, &DramLimit, StdHeader);
- if (DramLimit == 0xFFFFFFFF) {
- // Node not installed(all FF's)?
- continue; // Proceed to next Base register
- }
-
- if ((DramLimit & 0xFF) != Node) {
- // Check if Destination Node ID is current node
- continue; // Proceed to next Base register
- }
-
- // We only add an entry now if detected range belongs to current node/PDomain
- DramLimit >>= 16; // Get DRAM Limit addr [39:24]
- DramLimit++; // Add 1 for potential length
- DramLimit <<= 16; // Restore it to original location
-
- // Get DRAM Base Address
- PciAddress.Address.Register = OffsetRegs;
- LibAmdPciRead (AccessWidth32, PciAddress, &DramBase, StdHeader);
- DramBase &= 0xFFFF0000; // Keep only Base value [31:16]
- DramLeng = DramLimit - DramBase; // Subtract base from limit to get length
-
- // Leave hole for conventional memory (Less than 640K). It must be on CPU 0.
- if (DramBase == 0) {
- if (*PDomainForBase640K == 0xFF) {
- // It is the first time that the range start at 0.
- // If Yes, then Place 1MB memory gap and save Domain to PDomainForBase640K
- BufferLocPtr = MakeMemEntry (
- Domain,
- Node,
- 0, // Base = 0
- 0xA0000 >> 8, // Put it into format used in DRAM regs..
- BufferLocPtr
- );
- DramBase += 0x1000; // Add 1MB, so range = 1MB to Top of Region
- DramLeng -= 0x1000; // Also subtract 1MB from the length
- *PDomainForBase640K = Domain; // Save Domain number for memory Less than 640K
- } else {
- // If No, there are more than one memory range less than 640K, it should that
- // node interleaving is enabled. All nodes have the same memory ranges
- // and all cores in these nodes belong to the same domain.
- *PDomain = *PDomainForBase640K;
- return (BufferLocPtr);
- }
- }
- LibAmdMsrRead (TOP_MEM, &MsrValue, StdHeader);
- ValueTOM = (UINT32) MsrValue >> 8; // Save it in 39:24 format
- ValueLimit = DramBase + DramLeng; // We need to know how large region is
-
- // SPECIAL CASES:
- //
- // Several conditions require that we process the values of the memory range differently.
- // Here are descriptions of the corner cases.
- //
- // 1. TRUNCATE LOW - Memory range starts below TOM, ends in TOM (memory hole). For this case,
- // the range must be truncated to end at TOM.
- // ******************************* *******************************
- // * * * -> * *
- // ******************************* *******************************
- // 2 TOM 4 2 TOM
- //
- // 2. TRUNCATE HIGH - Memory range starts below 4GB, ends above 4GB. This is handled by changing the
- // start base to 4GB.
- // **************** **********
- // * * * -> * *
- // **************** **********
- // TOM 3.8 4 6 TOM 3.8 4 6
- //
- // 3. Memory range starts below TOM, ends above 4GB. For this case, the range must be truncated
- // to end at TOM. Note that this scenario creates two ranges, as the second comparison below
- // will find that it ends above 4GB since base and limit have been restored after first truncation,
- // and a second range will be written based at 4GB ending at original end address.
- // ******************************* **************** **********
- // * * * * -> * * * *
- // ******************************* **************** **********
- // 2 TOM 4 6 2 TOM 4 6
- //
- // 4. Memory range starts above TOM, ends below or equal to 4GB. This invalid range should simply
- // be ignored.
- // *******
- // * * -> < NULL >
- // *******
- // TOM 3.8 4
-
- if (((DramBase < ValueTOM) && (ValueLimit <= FOURGB) && (ValueLimit > ValueTOM))
- || ((DramBase < ValueTOM) && (ValueLimit > FOURGB))) {
- // TRUNCATE LOW!!! Shrink entry below TOM...
- // Base = DramBase, Size = TOM - DramBase
- BufferLocPtr = MakeMemEntry (Domain, Node, DramBase, (ValueTOM - DramBase), BufferLocPtr);
- isModified = TRUE;
- }
-
- if ((ValueLimit > FOURGB) && (DramBase < FOURGB)) {
- // TRUNCATE HIGH!!! Shrink entry above 4GB...
- // Size = Base + Size - 4GB, Base = 4GB
- BufferLocPtr = MakeMemEntry (Domain, Node, FOURGB, (DramLeng + DramBase - FOURGB), BufferLocPtr);
- isModified = TRUE;
- }
-
- if ((DramBase >= ValueTOM) && (ValueLimit <= FOURGB)) {
- // IGNORE!!! Entry located entirely within memory hole
- isModified = TRUE;
- }
-
- // If special range(isModified), we are done.
- // If not, finally write the memory entry.
- if (isModified == FALSE) {
- // Finally write the memory entry.
- BufferLocPtr = MakeMemEntry (Domain, Node, DramBase, DramLeng, BufferLocPtr);
- }
-
- } // for ( OffsetRegs = DRAMBase0; ... )
-
- return (BufferLocPtr);
-} // FillMemoryForCurrentNode()
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * This function will add APIC entry.
- *
- * @param[in] ApicId APIC ID number
- * @param[in] Domain Domain number
- * @param[in] BufferLocPtr Point to the address of buffer
- *
- * @retval UINT8 *(New buffer location ptr)
- */
-UINT8
-STATIC
-*MakeApicEntry (
- IN UINT8 ApicId,
- IN UINT8 Domain,
- IN UINT8 *BufferLocPtr
- )
-{
- CPU_SRAT_APIC_ENTRY *psSratApicEntry;
- UINT8 ReservedBytes;
-
- psSratApicEntry = (CPU_SRAT_APIC_ENTRY *)BufferLocPtr;
-
- psSratApicEntry->Type = AE_APIC;
- psSratApicEntry->Length = (UINT8)sizeof (CPU_SRAT_APIC_ENTRY);
- psSratApicEntry->Domain = Domain;
- psSratApicEntry->ApicId = ApicId;
- psSratApicEntry->Flags = ENABLED;
- psSratApicEntry->LSApicEid = 0;
- for (ReservedBytes = 0; ReservedBytes < (UINT8)sizeof (psSratApicEntry->Reserved); ReservedBytes++) {
- psSratApicEntry->Reserved[ReservedBytes] = 0;
- }
- return (BufferLocPtr + (UINT8)sizeof (CPU_SRAT_APIC_ENTRY));
-} // MakeApicEntry
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * This function will add Memory entry.
- *
- * Parameters:
- * @param[in] PDomain Proximity Domain
- * @param[in] Node The number of Node
- * @param[in] Base Memory Base
- * @param[in] Size Memory Size
- * @param[in] BufferLocPtr Point to the address of buffer
- *
- * @retval UINT8 * (new buffer location ptr)
- */
-UINT8
-STATIC
-*MakeMemEntry (
- IN UINT8 PDomain,
- IN UINT8 Node,
- IN UINT32 Base,
- IN UINT32 Size,
- IN UINT8 *BufferLocPtr
- )
-{
- CPU_SRAT_MEMORY_ENTRY *psSratMemEntry;
- UINT8 ReservedBytes;
-
- psSratMemEntry = (CPU_SRAT_MEMORY_ENTRY *)BufferLocPtr;
-
- psSratMemEntry->Type = AE_MEMORY; // [0] = Memory Entry
- psSratMemEntry->Length = (UINT8)sizeof (CPU_SRAT_MEMORY_ENTRY); // [1] = 40
- psSratMemEntry->Domain = PDomain; // [2] = Proximity Domain
-
- // [6-7] = Reserved
- for (ReservedBytes = 0; ReservedBytes < (UINT8)sizeof (psSratMemEntry->Reserved1); ReservedBytes++) {
- psSratMemEntry->Reserved1[ReservedBytes] = 0;
- }
-
- // [8-11] = Keep 31:0 of address only -> Base Addr Low
- psSratMemEntry->BaseAddrLow = Base << 8;
-
- // [12-15] = Keep 39:32 of address only -> Base Addr High
- psSratMemEntry->BaseAddrHigh = Base >> 24;
-
- // [16-19] = Keep 31:0 of address only -> Length Low
- psSratMemEntry->LengthAddrLow = Size << 8;
-
- // [20-23] = Keep 39:32 of address only -> Length High
- psSratMemEntry->LengthAddrHigh = Size >> 24;
-
- // [24-27] = Reserved
- for (ReservedBytes = 0; ReservedBytes < (UINT8)sizeof (psSratMemEntry->Reserved2); ReservedBytes++) {
- psSratMemEntry->Reserved2[ReservedBytes] = 0;
- }
-
- // [28-31] = Flags
- psSratMemEntry->Flags = ENABLED;
-
- // [32-40] = Reserved
- for (ReservedBytes = 0; ReservedBytes < (UINT8)sizeof (psSratMemEntry->Reserved3); ReservedBytes++) {
- psSratMemEntry->Reserved3[ReservedBytes] = 0;
- }
- return (BufferLocPtr + (UINT8)sizeof (CPU_SRAT_MEMORY_ENTRY));
-} // MakeMemEntry()
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuSwC1e.c b/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuSwC1e.c
deleted file mode 100644
index 9fe66ce..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuSwC1e.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD AGESA CPU SW C1e feature support code.
- *
- * Contains code that declares the AGESA CPU C1e related APIs
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/Feature
- * @e \$Revision: 37157 $ @e \$Date: 2010-09-01 03:24:07 +0800 (Wed, 01 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuApicUtilities.h"
-#include "cpuServices.h"
-#include "GeneralServices.h"
-#include "cpuFamilyTranslation.h"
-#include "Topology.h"
-#include "cpuFeatures.h"
-#include "cpuSwC1e.h"
-#include "cpuHwC1e.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_FEATURE_CPUSWC1E_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-extern CPU_FAMILY_SUPPORT_TABLE SwC1eFamilyServiceTable;
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Should software C1e be enabled
- *
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval TRUE SW C1e is supported.
- * @retval FALSE SW C1e not supported.
- *
- */
-BOOLEAN
-STATIC
-IsSwC1eFeatureEnabled (
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- BOOLEAN IsEnabled;
- AP_MAILBOXES ApMailboxes;
- SW_C1E_FAMILY_SERVICES *SwFamilyServices;
-
- ASSERT (PlatformConfig->C1eMode < MaxC1eMode);
- IsEnabled = FALSE;
- // Check whether software C1e is enabled only if hardware C1e is not supported or if the platform specifically
- // uses C1eModeSoftwareDeprecated.
- if ((PlatformConfig->C1eMode == C1eModeSoftwareDeprecated) ||
- ((PlatformConfig->C1eMode == C1eModeHardwareSoftwareDeprecated) && (!IsFeatureEnabled (HardwareC1e, PlatformConfig, StdHeader)))) {
- ASSERT ((PlatformConfig->C1ePlatformData1 < 0x10000) && (PlatformConfig->C1ePlatformData1 != 0));
- ASSERT (PlatformConfig->C1ePlatformData2 < 0x100);
- if ((PlatformConfig->C1ePlatformData1 != 0) && (PlatformConfig->C1ePlatformData1 < 0xFFFE) && (PlatformConfig->C1ePlatformData2 < 0xFF)) {
- if (!IsNonCoherentHt1 (StdHeader)) {
- if (GetNumberOfProcessors (StdHeader) == 1) {
- GetApMailbox (&ApMailboxes.ApMailInfo.Info, StdHeader);
- if (ApMailboxes.ApMailInfo.Fields.ModuleType == 0) {
- GetFeatureServicesOfCurrentCore (&SwC1eFamilyServiceTable, &SwFamilyServices, StdHeader);
- if (SwFamilyServices != NULL) {
- IsEnabled = SwFamilyServices->IsSwC1eSupported (SwFamilyServices, StdHeader);
- }
- }
- }
- }
- }
- }
- return IsEnabled;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Enable Software C1e
- *
- * @param[in] EntryPoint Timepoint designator.
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @return The most severe status of any family specific service.
- *
- */
-AGESA_STATUS
-STATIC
-InitializeSwC1eFeature (
- IN UINT64 EntryPoint,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_STATUS AgesaStatus;
- SW_C1E_FAMILY_SERVICES *FamilyServices;
-
- AgesaStatus = AGESA_SUCCESS;
-
- IDS_HDT_CONSOLE (CPU_TRACE, " SW C1e is enabled\n");
-
- if (IsWarmReset (StdHeader)) {
- GetFeatureServicesOfCurrentCore (&SwC1eFamilyServiceTable, &FamilyServices, StdHeader);
- AgesaStatus = FamilyServices->InitializeSwC1e (FamilyServices, EntryPoint, PlatformConfig, StdHeader);
- }
-
- return AgesaStatus;
-}
-
-CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureSwC1e =
-{
- SoftwareC1e,
- CPU_FEAT_AFTER_PM_INIT,
- IsSwC1eFeatureEnabled,
- InitializeSwC1eFeature
-};
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuSwC1e.h b/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuSwC1e.h
deleted file mode 100644
index 8c182e1..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuSwC1e.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD AGESA CPU SW C1e Functions declarations.
- *
- * Contains code that declares the AGESA CPU C1e related APIs
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/Feature
- * @e \$Revision: 37157 $ @e \$Date: 2010-09-01 03:24:07 +0800 (Wed, 01 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPU_SW_C1E_H_
-#define _CPU_SW_C1E_H_
-
-/*----------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *----------------------------------------------------------------------------------------
- */
-// Forward declaration needed for multi-structure mutual references
-AGESA_FORWARD_DECLARATION (SW_C1E_FAMILY_SERVICES);
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family specific call to check if software C1e is supported.
- *
- * @param[in] SwC1eServices Software C1e services.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval TRUE SW C1e is supported.
- * @retval FALSE SW C1e is not supported.
- *
- */
-typedef BOOLEAN F_SW_C1E_IS_SUPPORTED (
- IN SW_C1E_FAMILY_SERVICES *SwC1eServices,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method
-typedef F_SW_C1E_IS_SUPPORTED *PF_SW_C1E_IS_SUPPORTED;
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Family specific call to enable software C1e.
- *
- * @param[in] SwC1eServices Software C1e services.
- * @param[in] EntryPoint Timepoint designator.
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @return Family specific error value.
- *
- */
-typedef AGESA_STATUS F_SW_C1E_INIT (
- IN SW_C1E_FAMILY_SERVICES *SwC1eServices,
- IN UINT64 EntryPoint,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method
-typedef F_SW_C1E_INIT *PF_SW_C1E_INIT;
-
-/**
- * Provide the interface to the software C1e Family Specific Services.
- *
- * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
- * Each supported Family must provide an implementation for all methods in this interface, even if the
- * implementation is a CommonReturn().
- */
-struct _SW_C1E_FAMILY_SERVICES {
- UINT16 Revision; ///< Interface version
- // Public Methods.
- PF_SW_C1E_IS_SUPPORTED IsSwC1eSupported; ///< Method: Family specific call to check if software C1e is supported.
- PF_SW_C1E_INIT InitializeSwC1e; ///< Method: Family specific call to enable software C1e.
-};
-
-#endif // _CPU_SW_C1E_H_
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuWhea.c b/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuWhea.c
deleted file mode 100644
index ca2bd24..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Feature/cpuWhea.c
+++ /dev/null
@@ -1,271 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD WHEA Table Creation API, and related functions.
- *
- * Contains code that produce the ACPI WHEA related information.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "OptionWhea.h"
-#include "cpuLateInit.h"
-#include "heapManager.h"
-#include "cpuRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "Ids.h"
-#include "Filecode.h"
-CODE_GROUP (G3_DXE)
-RDATA_GROUP (G3_DXE)
-
-#define FILECODE PROC_CPU_FEATURE_CPUWHEA_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *---------------------------------------------------------------------------------------
- */
-
-extern OPTION_WHEA_CONFIGURATION OptionWheaConfiguration; // global user config record
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-VOID
-STATIC
-CreateHestBank (
- IN AMD_HEST_BANK *HestBankPtr,
- IN UINT8 BankNum,
- IN AMD_WHEA_INIT_DATA *WheaInitDataPtr
- );
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * It will create the ACPI table of WHEA and return the pointer to the table.
- *
- * @param[in, out] StdHeader Standard Head Pointer
- * @param[in, out] WheaMcePtr Point to Whea Hest Mce table
- * @param[in, out] WheaCmcPtr Point to Whea Hest Cmc table
- *
- * @retval AGESA_STATUS
- */
-AGESA_STATUS
-CreateAcpiWhea (
- IN OUT AMD_CONFIG_PARAMS *StdHeader,
- IN OUT VOID **WheaMcePtr,
- IN OUT VOID **WheaCmcPtr
- )
-{
- AGESA_TESTPOINT (TpProcCpuEntryWhea, StdHeader);
- return ((*(OptionWheaConfiguration.WheaFeature)) (StdHeader, WheaMcePtr, WheaCmcPtr));
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * This is the default routine for use when the WHEA option is NOT requested.
- *
- * The option install process will create and fill the transfer vector with
- * the address of the proper routine (Main or Stub). The link optimizer will
- * strip out of the .DLL the routine that is not used.
- *
- * @param[in, out] StdHeader Standard Head Pointer
- * @param[in, out] WheaMcePtr Point to Whea Hest Mce table
- * @param[in, out] WheaCmcPtr Point to Whea Hest Cmc table
- *
- * @retval AGESA_STATUS
- */
-
-AGESA_STATUS
-GetAcpiWheaStub (
- IN OUT AMD_CONFIG_PARAMS *StdHeader,
- IN OUT VOID **WheaMcePtr,
- IN OUT VOID **WheaCmcPtr
- )
-{
- return AGESA_UNSUPPORTED;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * It will create the ACPI tale of WHEA and return the pointer to the table.
- *
- * @param[in, out] StdHeader Standard Head Pointer
- * @param[in, out] WheaMcePtr Point to Whea Hest Mce table
- * @param[in, out] WheaCmcPtr Point to Whea Hest Cmc table
- *
- * @retval UINT32 AGESA_STATUS
- */
-AGESA_STATUS
-GetAcpiWheaMain (
- IN OUT AMD_CONFIG_PARAMS *StdHeader,
- IN OUT VOID **WheaMcePtr,
- IN OUT VOID **WheaCmcPtr
- )
-{
- UINT8 BankNum;
- UINT8 Entries;
- UINT16 HestMceTableSize;
- UINT16 HestCmcTableSize;
- UINT64 MsrData;
- AMD_HEST_MCE_TABLE *HestMceTablePtr;
- AMD_HEST_CMC_TABLE *HestCmcTablePtr;
- AMD_HEST_BANK *HestBankPtr;
- AMD_WHEA_INIT_DATA *WheaInitDataPtr;
- ALLOCATE_HEAP_PARAMS AllocParams;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
-
- FamilySpecificServices = NULL;
-
- IDS_HDT_CONSOLE (CPU_TRACE, " WHEA is created\n");
-
- // step 1: calculate Hest table size
- LibAmdMsrRead (MSR_MCG_CAP, &MsrData, StdHeader);
- BankNum = (UINT8) (((MSR_MCG_CAP_STRUCT *) (&MsrData))->Count);
- if (BankNum == 0) {
- return AGESA_ERROR;
- }
-
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
- FamilySpecificServices->GetWheaInitData (FamilySpecificServices, &WheaInitDataPtr, &Entries, StdHeader);
-
- ASSERT (WheaInitDataPtr->HestBankNum <= BankNum);
-
- HestMceTableSize = sizeof (AMD_HEST_MCE_TABLE) + WheaInitDataPtr->HestBankNum * sizeof (AMD_HEST_BANK);
- HestCmcTableSize = sizeof (AMD_HEST_CMC_TABLE) + WheaInitDataPtr->HestBankNum * sizeof (AMD_HEST_BANK);
-
- HestMceTablePtr = (AMD_HEST_MCE_TABLE *) *WheaMcePtr;
- HestCmcTablePtr = (AMD_HEST_CMC_TABLE *) *WheaCmcPtr;
-
- // step 2: allocate a buffer by callback function
- if ((HestMceTablePtr == NULL) || (HestCmcTablePtr == NULL)) {
- AllocParams.RequestedBufferSize = (UINT32) (HestMceTableSize + HestCmcTableSize);
- AllocParams.BufferHandle = AMD_WHEA_BUFFER_HANDLE;
- AllocParams.Persist = HEAP_SYSTEM_MEM;
-
- AGESA_TESTPOINT (TpProcCpuBeforeAllocateWheaBuffer, StdHeader);
- if (HeapAllocateBuffer (&AllocParams, StdHeader) != AGESA_SUCCESS) {
- return AGESA_ERROR;
- }
- AGESA_TESTPOINT (TpProcCpuAfterAllocateWheaBuffer, StdHeader);
-
- HestMceTablePtr = (AMD_HEST_MCE_TABLE *) AllocParams.BufferPtr;
- HestCmcTablePtr = (AMD_HEST_CMC_TABLE *) ((UINT8 *) (HestMceTablePtr + 1) + (WheaInitDataPtr->HestBankNum * sizeof (AMD_HEST_BANK)));
- }
-
- // step 3: fill in Hest MCE table
- HestMceTablePtr->TblLength = HestMceTableSize;
- HestMceTablePtr->GlobCapInitDataLSD = WheaInitDataPtr->GlobCapInitDataLSD;
- HestMceTablePtr->GlobCapInitDataMSD = WheaInitDataPtr->GlobCapInitDataMSD;
- HestMceTablePtr->GlobCtrlInitDataLSD = WheaInitDataPtr->GlobCtrlInitDataLSD;
- HestMceTablePtr->GlobCtrlInitDataMSD = WheaInitDataPtr->GlobCtrlInitDataMSD;
- HestMceTablePtr->NumHWBanks = WheaInitDataPtr->HestBankNum;
-
- HestBankPtr = (AMD_HEST_BANK *) (HestMceTablePtr + 1);
- CreateHestBank (HestBankPtr, WheaInitDataPtr->HestBankNum, WheaInitDataPtr);
-
- // step 4: fill in Hest CMC table
- HestCmcTablePtr->NumHWBanks = WheaInitDataPtr->HestBankNum;
- HestCmcTablePtr->TblLength = HestCmcTableSize;
-
- HestBankPtr = (AMD_HEST_BANK *) (HestCmcTablePtr + 1);
- CreateHestBank (HestBankPtr, WheaInitDataPtr->HestBankNum, WheaInitDataPtr);
-
- // step 5: fill in the incoming structure
- *WheaMcePtr = HestMceTablePtr;
- *WheaCmcPtr = HestCmcTablePtr;
-
- return (AGESA_SUCCESS);
-}
-
-/*---------------------------------------------------------------------------------------
- * L O C A L F U N C T I O N S
- *---------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * It will create Bank structure for Hest table
- *
- * @param[in] HestBankPtr Pointer to the Hest Back structure
- * @param[in] BankNum The number of Bank
- * @param[in] WheaInitDataPtr Pointer to the AMD_WHEA_INIT_DATA structure
- *
- */
-VOID
-STATIC
-CreateHestBank (
- IN AMD_HEST_BANK *HestBankPtr,
- IN UINT8 BankNum,
- IN AMD_WHEA_INIT_DATA *WheaInitDataPtr
- )
-{
- UINT8 BankIndex;
- for (BankIndex = 0; BankIndex < BankNum; BankIndex++) {
- HestBankPtr->BankNum = BankIndex;
- HestBankPtr->ClrStatusOnInit = WheaInitDataPtr->ClrStatusOnInit;
- HestBankPtr->StatusDataFormat = WheaInitDataPtr->StatusDataFormat;
- HestBankPtr->ConfWriteEn = WheaInitDataPtr->ConfWriteEn;
- HestBankPtr->CtrlRegMSRAddr = WheaInitDataPtr->HestBankInitData[BankIndex].CtrlRegMSRAddr;
- HestBankPtr->CtrlInitDataLSD = WheaInitDataPtr->HestBankInitData[BankIndex].CtrlInitDataLSD;
- HestBankPtr->CtrlInitDataMSD = WheaInitDataPtr->HestBankInitData[BankIndex].CtrlInitDataMSD;
- HestBankPtr->StatRegMSRAddr = WheaInitDataPtr->HestBankInitData[BankIndex].StatRegMSRAddr;
- HestBankPtr->AddrRegMSRAddr = WheaInitDataPtr->HestBankInitData[BankIndex].AddrRegMSRAddr;
- HestBankPtr->MiscRegMSRAddr = WheaInitDataPtr->HestBankInitData[BankIndex].MiscRegMSRAddr;
- HestBankPtr++;
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/S3.c b/src/vendorcode/amd/agesa/Proc/CPU/S3.c
deleted file mode 100644
index 5f2ef34..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/S3.c
+++ /dev/null
@@ -1,1219 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * ACPI S3 Support routines
- *
- * Contains routines needed for supporting resume from the ACPI S3 sleep state.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Interface
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "S3.h"
-#include "mfs3.h"
-#include "GeneralServices.h"
-#include "cpuServices.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_S3_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-VOID
-SaveDeviceContext (
- IN DEVICE_BLOCK_HEADER *DeviceList,
- IN CALL_POINTS CallPoint,
- OUT UINT32 *ActualBufferSize,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-SavePciDevice (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN PCI_DEVICE_DESCRIPTOR *Device,
- IN CALL_POINTS CallPoint,
- IN OUT VOID **OrMask
- );
-
-VOID
-SaveConditionalPciDevice (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device,
- IN CALL_POINTS CallPoint,
- IN OUT VOID **OrMask
- );
-
-VOID
-SaveMsrDevice (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN MSR_DEVICE_DESCRIPTOR *Device,
- IN CALL_POINTS CallPoint,
- IN OUT UINT64 **OrMask
- );
-
-VOID
-SaveConditionalMsrDevice (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device,
- IN CALL_POINTS CallPoint,
- IN OUT UINT64 **OrMask
- );
-
-VOID
-RestorePciDevice (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN PCI_DEVICE_DESCRIPTOR *Device,
- IN CALL_POINTS CallPoint,
- IN OUT VOID **OrMask
- );
-
-VOID
-RestoreConditionalPciDevice (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device,
- IN CALL_POINTS CallPoint,
- IN OUT VOID **OrMask
- );
-
-VOID
-RestoreMsrDevice (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN MSR_DEVICE_DESCRIPTOR *Device,
- IN CALL_POINTS CallPoint,
- IN OUT UINT64 **OrMask
- );
-
-VOID
-RestoreConditionalMsrDevice (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device,
- IN CALL_POINTS CallPoint,
- IN OUT UINT64 **OrMask
- );
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Saves all devices in the given device list.
- *
- * This traverses the entire device list twice. In the first pass, we save
- * all devices identified as Pre ESR. In the second pass, we save devices
- * marked as post ESR.
- *
- * @param[in] DeviceList Beginning of the device list to save.
- * @param[in] Storage Beginning of the context buffer.
- * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or
- * AMD_S3LATE_RESTORE.
- * @param[out] ActualBufferSize Actual size used in saving the device list.
- * @param[in] StdHeader AMD standard header config param.
- *
- */
-VOID
-SaveDeviceListContext (
- IN DEVICE_BLOCK_HEADER *DeviceList,
- IN VOID *Storage,
- IN CALL_POINTS CallPoint,
- OUT UINT32 *ActualBufferSize,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- // Copy device list over
- LibAmdMemCopy (Storage,
- DeviceList,
- (UINTN) DeviceList->RelativeOrMaskOffset,
- StdHeader);
- SaveDeviceContext (Storage, CallPoint, ActualBufferSize, StdHeader);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Saves all devices in the given device list.
- *
- * This traverses the entire device list twice. In the first pass, we save
- * all devices identified as Pre ESR. In the second pass, we save devices
- * marked as post ESR.
- *
- * @param[in,out] DeviceList Beginning of the device list to save.
- * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or
- * AMD_S3LATE_RESTORE.
- * @param[out] ActualBufferSize Actual size used in saving the device list.
- * @param[in] StdHeader AMD standard header config param.
- *
- */
-VOID
-SaveDeviceContext (
- IN DEVICE_BLOCK_HEADER *DeviceList,
- IN CALL_POINTS CallPoint,
- OUT UINT32 *ActualBufferSize,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- DEVICE_DESCRIPTORS Device;
- UINT16 i;
- UINT64 StartAddress;
- UINT64 EndAddress;
- VOID *OrMask;
-
- StartAddress = (UINT64) DeviceList;
- Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1];
- OrMask = (UINT8 *) DeviceList + DeviceList->RelativeOrMaskOffset;
-
- // Process Pre ESR List
- for (i = 0; i < DeviceList->NumDevices; i++) {
- switch (Device.CommonDeviceHeader->Type) {
- case DEV_TYPE_PCI_PRE_ESR:
- SavePciDevice (StdHeader, Device.PciDevice, CallPoint, &OrMask);
- // Fall through to advance the pointer after saving context
- case DEV_TYPE_PCI:
- Device.PciDevice++;
- break;
- case DEV_TYPE_CPCI_PRE_ESR:
- SaveConditionalPciDevice (StdHeader, Device.CPciDevice, CallPoint, &OrMask);
- // Fall through to advance the pointer after saving context
- case DEV_TYPE_CPCI:
- Device.CPciDevice++;
- break;
- case DEV_TYPE_MSR_PRE_ESR:
- SaveMsrDevice (StdHeader, Device.MsrDevice, CallPoint, (UINT64 **) &OrMask);
- // Fall through to advance the pointer after saving context
- case DEV_TYPE_MSR:
- Device.MsrDevice++;
- break;
- case DEV_TYPE_CMSR_PRE_ESR:
- SaveConditionalMsrDevice (StdHeader, Device.CMsrDevice, CallPoint, (UINT64 **) &OrMask);
- // Fall through to advance the pointer after saving context
- case DEV_TYPE_CMSR:
- Device.CMsrDevice++;
- break;
- }
- }
-
- Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1];
- // Process Post ESR List
- for (i = 0; i < DeviceList->NumDevices; i++) {
- switch (Device.CommonDeviceHeader->Type) {
- case DEV_TYPE_PCI:
- SavePciDevice (StdHeader, Device.PciDevice, CallPoint, &OrMask);
- // Fall through to advance the pointer after saving context
- case DEV_TYPE_PCI_PRE_ESR:
- Device.PciDevice++;
- break;
- case DEV_TYPE_CPCI:
- SaveConditionalPciDevice (StdHeader, Device.CPciDevice, CallPoint, &OrMask);
- // Fall through to advance the pointer after saving context
- case DEV_TYPE_CPCI_PRE_ESR:
- Device.CPciDevice++;
- break;
- case DEV_TYPE_MSR:
- SaveMsrDevice (StdHeader, Device.MsrDevice, CallPoint, (UINT64 **) &OrMask);
- // Fall through to advance the pointer after saving context
- case DEV_TYPE_MSR_PRE_ESR:
- Device.MsrDevice++;
- break;
- case DEV_TYPE_CMSR:
- SaveConditionalMsrDevice (StdHeader, Device.CMsrDevice, CallPoint, (UINT64 **) &OrMask);
- // Fall through to advance the pointer after saving context
- case DEV_TYPE_CMSR_PRE_ESR:
- Device.CMsrDevice++;
- break;
- }
- }
- EndAddress = (UINT64) OrMask;
- *ActualBufferSize = (UINT32) (EndAddress - StartAddress);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Saves the context of a PCI device.
- *
- * This traverses the provided register list saving PCI registers.
- *
- * @param[in] StdHeader AMD standard header config param.
- * @param[in] Device PCI device to restore.
- * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or
- * AMD_S3LATE_RESTORE.
- * @param[in,out] OrMask Current buffer pointer of raw register values.
- *
- */
-VOID
-SavePciDevice (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN PCI_DEVICE_DESCRIPTOR *Device,
- IN CALL_POINTS CallPoint,
- IN OUT VOID **OrMask
- )
-{
- UINT8 RegSizeInBytes;
- UINT8 SpecialCaseIndex;
- UINT8 *IntermediatePtr;
- UINT16 i;
- UINT32 Socket;
- UINT32 Module;
- UINT32 AndMask;
- ACCESS_WIDTH AccessWidth;
- AGESA_STATUS IgnoredSts;
- PCI_ADDR PciAddress;
- PCI_REGISTER_BLOCK_HEADER *RegisterHdr;
-
- GetSocketModuleOfNode ((UINT32) Device->Node,
- &Socket,
- &Module,
- StdHeader);
- GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
-
- if (CallPoint == INIT_RESUME) {
- MemFS3GetPciDeviceRegisterList (Device, &RegisterHdr, StdHeader);
- } else {
- S3GetPciDeviceRegisterList (Device, &RegisterHdr, StdHeader);
- }
-
- for (i = 0; i < RegisterHdr->NumRegisters; i++) {
- PciAddress.Address.Function = RegisterHdr->RegisterList[i].Function;
- PciAddress.Address.Register = RegisterHdr->RegisterList[i].Offset;
- RegSizeInBytes = RegisterHdr->RegisterList[i].Type.RegisterSize;
- switch (RegSizeInBytes) {
- case 1:
- AndMask = 0xFFFFFFFF & ((UINT8) RegisterHdr->RegisterList[i].AndMask);
- AccessWidth = AccessS3SaveWidth8;
- break;
- case 2:
- AndMask = 0xFFFFFFFF & ((UINT16) RegisterHdr->RegisterList[i].AndMask);
- AccessWidth = AccessS3SaveWidth16;
- break;
- case 3:
- // In this case, we don't need to save a register. We just need to call a special
- // function to do certain things in the save and resume sequence.
- // This should not be used in a non-special case.
- AndMask = 0;
- RegSizeInBytes = 0;
- AccessWidth = 0;
- break;
- default:
- AndMask = RegisterHdr->RegisterList[i].AndMask;
- RegSizeInBytes = 4;
- AccessWidth = AccessS3SaveWidth32;
- break;
- }
- if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) {
- ASSERT ((AndMask != 0) && (RegSizeInBytes != 0) && (AccessWidth != 0));
- LibAmdPciRead (AccessWidth, PciAddress, *OrMask, StdHeader);
- } else {
- SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex;
- RegisterHdr->SpecialCases[SpecialCaseIndex].Save (AccessWidth, PciAddress, *OrMask, StdHeader);
- }
- if (AndMask != 0) {
- // If AndMask is 0, then it is a not-care. Don't need to apply it to the OrMask
- **((UINT32 **) OrMask) &= AndMask;
- }
- IntermediatePtr = (UINT8 *) *OrMask;
- *OrMask = &IntermediatePtr[RegSizeInBytes]; // += RegSizeInBytes;
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Saves the context of a 'conditional' PCI device.
- *
- * This traverses the provided register list saving PCI registers when appropriate.
- *
- * @param[in] StdHeader AMD standard header config param.
- * @param[in] Device 'conditional' PCI device to restore.
- * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or
- * AMD_S3LATE_RESTORE.
- * @param[in,out] OrMask Current buffer pointer of raw register values.
- *
- */
-VOID
-SaveConditionalPciDevice (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device,
- IN CALL_POINTS CallPoint,
- IN OUT VOID **OrMask
- )
-{
- UINT8 RegSizeInBytes;
- UINT8 SpecialCaseIndex;
- UINT8 *IntermediatePtr;
- UINT16 i;
- UINT32 Socket;
- UINT32 Module;
- UINT32 AndMask;
- ACCESS_WIDTH AccessWidth;
- AGESA_STATUS IgnoredSts;
- PCI_ADDR PciAddress;
- CPCI_REGISTER_BLOCK_HEADER *RegisterHdr;
-
- GetSocketModuleOfNode ((UINT32) Device->Node,
- &Socket,
- &Module,
- StdHeader);
- GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
-
- if (CallPoint == INIT_RESUME) {
- MemFS3GetCPciDeviceRegisterList (Device, &RegisterHdr, StdHeader);
- } else {
- S3GetCPciDeviceRegisterList (Device, &RegisterHdr, StdHeader);
- }
-
- for (i = 0; i < RegisterHdr->NumRegisters; i++) {
- if (((Device->Mask1 & RegisterHdr->RegisterList[i].Mask1) != 0) &&
- ((Device->Mask2 & RegisterHdr->RegisterList[i].Mask2) != 0)) {
- PciAddress.Address.Function = RegisterHdr->RegisterList[i].Function;
- PciAddress.Address.Register = RegisterHdr->RegisterList[i].Offset;
- RegSizeInBytes = RegisterHdr->RegisterList[i].Type.RegisterSize;
- switch (RegSizeInBytes) {
- case 1:
- AndMask = 0xFFFFFFFF & ((UINT8) RegisterHdr->RegisterList[i].AndMask);
- AccessWidth = AccessS3SaveWidth8;
- break;
- case 2:
- AndMask = 0xFFFFFFFF & ((UINT16) RegisterHdr->RegisterList[i].AndMask);
- AccessWidth = AccessS3SaveWidth16;
- break;
- case 3:
- // In this case, we don't need to save a register. We just need to call a special
- // function to do certain things in the save and resume sequence.
- // This should not be used in a non-special case.
- AndMask = 0;
- RegSizeInBytes = 0;
- AccessWidth = 0;
- break;
- default:
- AndMask = RegisterHdr->RegisterList[i].AndMask;
- RegSizeInBytes = 4;
- AccessWidth = AccessS3SaveWidth32;
- break;
- }
- if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) {
- ASSERT ((AndMask != 0) && (RegSizeInBytes != 0) && (AccessWidth != 0));
- LibAmdPciRead (AccessWidth, PciAddress, *OrMask, StdHeader);
- } else {
- SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex;
- RegisterHdr->SpecialCases[SpecialCaseIndex].Save (AccessWidth, PciAddress, *OrMask, StdHeader);
- }
- if (AndMask != 0) {
- // If AndMask is 0, then it is a not-care. Don't need to apply it to the OrMask
- **((UINT32 **) OrMask) &= AndMask;
- }
- IntermediatePtr = (UINT8 *) *OrMask;
- *OrMask = &IntermediatePtr[RegSizeInBytes]; // += RegSizeInBytes;
- }
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Saves the context of an MSR device.
- *
- * This traverses the provided register list saving MSRs.
- *
- * @param[in] StdHeader AMD standard header config param.
- * @param[in] Device MSR device to restore.
- * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or
- * AMD_S3LATE_RESTORE.
- * @param[in,out] OrMask Current buffer pointer of raw register values.
- *
- */
-VOID
-SaveMsrDevice (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN MSR_DEVICE_DESCRIPTOR *Device,
- IN CALL_POINTS CallPoint,
- IN OUT UINT64 **OrMask
- )
-{
- UINT8 SpecialCaseIndex;
- UINT16 i;
- MSR_REGISTER_BLOCK_HEADER *RegisterHdr;
-
- if (CallPoint == INIT_RESUME) {
- MemFS3GetMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader);
- } else {
- S3GetMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader);
- }
-
- for (i = 0; i < RegisterHdr->NumRegisters; i++) {
- if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) {
- LibAmdMsrRead (RegisterHdr->RegisterList[i].Address, *OrMask, StdHeader);
- } else {
- SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex;
- RegisterHdr->SpecialCases[SpecialCaseIndex].Save (RegisterHdr->RegisterList[i].Address, *OrMask, StdHeader);
- }
- **OrMask &= RegisterHdr->RegisterList[i].AndMask;
- (*OrMask)++;
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Saves the context of a 'conditional' MSR device.
- *
- * This traverses the provided register list saving MSRs when appropriate.
- *
- * @param[in] StdHeader AMD standard header config param.
- * @param[in] Device 'conditional' MSR device to restore.
- * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or
- * AMD_S3LATE_RESTORE.
- * @param[in,out] OrMask Current buffer pointer of raw register values.
- *
- */
-VOID
-SaveConditionalMsrDevice (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device,
- IN CALL_POINTS CallPoint,
- IN OUT UINT64 **OrMask
- )
-{
- UINT8 SpecialCaseIndex;
- UINT16 i;
- CMSR_REGISTER_BLOCK_HEADER *RegisterHdr;
-
- if (CallPoint == INIT_RESUME) {
- MemFS3GetCMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader);
- } else {
- S3GetCMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader);
- }
-
- for (i = 0; i < RegisterHdr->NumRegisters; i++) {
- if (((Device->Mask1 & RegisterHdr->RegisterList[i].Mask1) != 0) &&
- ((Device->Mask2 & RegisterHdr->RegisterList[i].Mask2) != 0)) {
- if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) {
- LibAmdMsrRead (RegisterHdr->RegisterList[i].Address, (UINT64 *) *OrMask, StdHeader);
- } else {
- SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex;
- RegisterHdr->SpecialCases[SpecialCaseIndex].Save (RegisterHdr->RegisterList[i].Address, (UINT64 *) *OrMask, StdHeader);
- }
- **OrMask &= RegisterHdr->RegisterList[i].AndMask;
- (*OrMask)++;
- }
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Determines the maximum amount of space required to store all raw register
- * values for the given device list.
- *
- * This traverses the entire device list, and calculates the worst case size
- * of each device in the device list.
- *
- * @param[in] DeviceList Beginning of the device list.
- * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or
- * AMD_S3LATE_RESTORE.
- * @param[in] StdHeader AMD standard header config param.
- *
- * @retval Size in bytes required for storing all registers.
- */
-UINT32
-GetWorstCaseContextSize (
- IN DEVICE_BLOCK_HEADER *DeviceList,
- IN CALL_POINTS CallPoint,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 WorstCaseSize;
- DEVICE_DESCRIPTORS Device;
- UINT16 i;
- REGISTER_BLOCK_HEADERS RegisterHdr;
-
- WorstCaseSize = DeviceList->RelativeOrMaskOffset;
- Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1];
-
- // Process Device List
- for (i = 0; i < DeviceList->NumDevices; i++) {
- switch (Device.CommonDeviceHeader->Type) {
- case DEV_TYPE_PCI_PRE_ESR:
- // PRE_ESR and post ESR take the same amount of space
- case DEV_TYPE_PCI:
- if (CallPoint == INIT_RESUME) {
- MemFS3GetPciDeviceRegisterList (Device.PciDevice, &RegisterHdr.PciRegisters, StdHeader);
- } else {
- S3GetPciDeviceRegisterList (Device.PciDevice, &RegisterHdr.PciRegisters, StdHeader);
- }
- WorstCaseSize += (RegisterHdr.PciRegisters->NumRegisters * 4);
- Device.PciDevice++;
- break;
- case DEV_TYPE_CPCI_PRE_ESR:
- // PRE_ESR and post ESR take the same amount of space
- case DEV_TYPE_CPCI:
- if (CallPoint == INIT_RESUME) {
- MemFS3GetCPciDeviceRegisterList (Device.CPciDevice, &RegisterHdr.CPciRegisters, StdHeader);
- } else {
- S3GetCPciDeviceRegisterList (Device.CPciDevice, &RegisterHdr.CPciRegisters, StdHeader);
- }
- WorstCaseSize += (RegisterHdr.CPciRegisters->NumRegisters * 4);
- Device.CPciDevice++;
- break;
- case DEV_TYPE_MSR_PRE_ESR:
- // PRE_ESR and post ESR take the same amount of space
- case DEV_TYPE_MSR:
- if (CallPoint == INIT_RESUME) {
- MemFS3GetMsrDeviceRegisterList (Device.MsrDevice, &RegisterHdr.MsrRegisters, StdHeader);
- } else {
- S3GetMsrDeviceRegisterList (Device.MsrDevice, &RegisterHdr.MsrRegisters, StdHeader);
- }
- WorstCaseSize += (RegisterHdr.MsrRegisters->NumRegisters * 8);
- Device.MsrDevice++;
- break;
- case DEV_TYPE_CMSR_PRE_ESR:
- // PRE_ESR and post ESR take the same amount of space
- case DEV_TYPE_CMSR:
- if (CallPoint == INIT_RESUME) {
- MemFS3GetCMsrDeviceRegisterList (Device.CMsrDevice, &RegisterHdr.CMsrRegisters, StdHeader);
- } else {
- S3GetCMsrDeviceRegisterList (Device.CMsrDevice, &RegisterHdr.CMsrRegisters, StdHeader);
- }
- WorstCaseSize += (RegisterHdr.CMsrRegisters->NumRegisters * 8);
- Device.CMsrDevice++;
- break;
- default:
- ASSERT (FALSE);
- }
- }
- return (WorstCaseSize);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Restores all devices marked as 'before exiting self-refresh.'
- *
- * This traverses the entire device list, restoring all devices identified
- * as Pre ESR.
- *
- * @param[in,out] OrMaskPtr Current buffer pointer of raw register values.
- * @param[in] Storage Beginning of the device list.
- * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or
- * AMD_S3LATE_RESTORE.
- * @param[in] StdHeader AMD standard header config param.
- *
- */
-VOID
-RestorePreESRContext (
- OUT VOID **OrMaskPtr,
- IN VOID *Storage,
- IN CALL_POINTS CallPoint,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- DEVICE_DESCRIPTORS Device;
- UINT16 i;
- DEVICE_BLOCK_HEADER *DeviceList;
-
- DeviceList = (DEVICE_BLOCK_HEADER *) Storage;
- Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1];
- *OrMaskPtr = (UINT8 *) DeviceList + DeviceList->RelativeOrMaskOffset;
-
- // Process Pre ESR List
- for (i = 0; i < DeviceList->NumDevices; i++) {
- switch (Device.CommonDeviceHeader->Type) {
- case DEV_TYPE_PCI_PRE_ESR:
- RestorePciDevice (StdHeader, Device.PciDevice, CallPoint, OrMaskPtr);
- // Fall through to advance the pointer after restoring context
- case DEV_TYPE_PCI:
- Device.PciDevice++;
- break;
- case DEV_TYPE_CPCI_PRE_ESR:
- RestoreConditionalPciDevice (StdHeader, Device.CPciDevice, CallPoint, OrMaskPtr);
- // Fall through to advance the pointer after restoring context
- case DEV_TYPE_CPCI:
- Device.CPciDevice++;
- break;
- case DEV_TYPE_MSR_PRE_ESR:
- RestoreMsrDevice (StdHeader, Device.MsrDevice, CallPoint, (UINT64 **) OrMaskPtr);
- // Fall through to advance the pointer after restoring context
- case DEV_TYPE_MSR:
- Device.MsrDevice++;
- break;
- case DEV_TYPE_CMSR_PRE_ESR:
- RestoreConditionalMsrDevice (StdHeader, Device.CMsrDevice, CallPoint, (UINT64 **) OrMaskPtr);
- // Fall through to advance the pointer after restoring context
- case DEV_TYPE_CMSR:
- Device.CMsrDevice++;
- break;
- }
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Restores all devices marked as 'after exiting self-refresh.'
- *
- * This traverses the entire device list, restoring all devices identified
- * as Post ESR.
- *
- * @param[in] OrMaskPtr Current buffer pointer of raw register values.
- * @param[in] Storage Beginning of the device list.
- * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or
- * AMD_S3LATE_RESTORE.
- * @param[in] StdHeader AMD standard header config param.
- *
- */
-VOID
-RestorePostESRContext (
- IN VOID *OrMaskPtr,
- IN VOID *Storage,
- IN CALL_POINTS CallPoint,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- DEVICE_DESCRIPTORS Device;
- UINT16 i;
- DEVICE_BLOCK_HEADER *DeviceList;
-
- DeviceList = (DEVICE_BLOCK_HEADER *) Storage;
- Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1];
-
- // Process Pre ESR List
- for (i = 0; i < DeviceList->NumDevices; i++) {
- switch (Device.CommonDeviceHeader->Type) {
- case DEV_TYPE_PCI:
- RestorePciDevice (StdHeader, Device.PciDevice, CallPoint, &OrMaskPtr);
- // Fall through to advance the pointer after restoring context
- case DEV_TYPE_PCI_PRE_ESR:
- Device.PciDevice++;
- break;
- case DEV_TYPE_CPCI:
- RestoreConditionalPciDevice (StdHeader, Device.CPciDevice, CallPoint, &OrMaskPtr);
- // Fall through to advance the pointer after restoring context
- case DEV_TYPE_CPCI_PRE_ESR:
- Device.CPciDevice++;
- break;
- case DEV_TYPE_MSR:
- RestoreMsrDevice (StdHeader, Device.MsrDevice, CallPoint, (UINT64 **) &OrMaskPtr);
- // Fall through to advance the pointer after restoring context
- case DEV_TYPE_MSR_PRE_ESR:
- Device.MsrDevice++;
- break;
- case DEV_TYPE_CMSR:
- RestoreConditionalMsrDevice (StdHeader, Device.CMsrDevice, CallPoint, (UINT64 **) &OrMaskPtr);
- // Fall through to advance the pointer after restoring context
- case DEV_TYPE_CMSR_PRE_ESR:
- Device.CMsrDevice++;
- break;
- }
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Restores the context of a PCI device.
- *
- * This traverses the provided register list restoring PCI registers.
- *
- * @param[in] StdHeader AMD standard header config param.
- * @param[in] Device 'conditional' PCI device to restore.
- * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or
- * AMD_S3LATE_RESTORE.
- * @param[in,out] OrMask Current buffer pointer of raw register values.
- *
- */
-VOID
-RestorePciDevice (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN PCI_DEVICE_DESCRIPTOR *Device,
- IN CALL_POINTS CallPoint,
- IN OUT VOID **OrMask
- )
-{
- UINT8 RegSizeInBytes;
- UINT8 SpecialCaseIndex;
- UINT8 *IntermediatePtr;
- UINT16 i;
- UINT32 Socket;
- UINT32 Module;
- UINT32 AndMask;
- UINT32 RegValueRead;
- UINT32 RegValueWrite;
- ACCESS_WIDTH AccessWidth;
- AGESA_STATUS IgnoredSts;
- PCI_ADDR PciAddress;
- PCI_REGISTER_BLOCK_HEADER *RegisterHdr;
-
- GetSocketModuleOfNode ((UINT32) Device->Node,
- &Socket,
- &Module,
- StdHeader);
- GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
-
- if (CallPoint == INIT_RESUME) {
- MemFS3GetPciDeviceRegisterList (Device, &RegisterHdr, StdHeader);
- } else {
- S3GetPciDeviceRegisterList (Device, &RegisterHdr, StdHeader);
- }
-
- for (i = 0; i < RegisterHdr->NumRegisters; i++) {
- PciAddress.Address.Function = RegisterHdr->RegisterList[i].Function;
- PciAddress.Address.Register = RegisterHdr->RegisterList[i].Offset;
- RegSizeInBytes = RegisterHdr->RegisterList[i].Type.RegisterSize;
- switch (RegSizeInBytes) {
- case 1:
- AndMask = 0xFFFFFFFF & ((UINT8) RegisterHdr->RegisterList[i].AndMask);
- RegValueWrite = **(UINT8 **)OrMask;
- AccessWidth = AccessS3SaveWidth8;
- break;
- case 2:
- AndMask = 0xFFFFFFFF & ((UINT16) RegisterHdr->RegisterList[i].AndMask);
- RegValueWrite = **(UINT16 **)OrMask;
- AccessWidth = AccessS3SaveWidth16;
- break;
- case 3:
- // In this case, we don't need to restore a register. We just need to call a special
- // function to do certain things in the save and resume sequence.
- // This should not be used in a non-special case.
- AndMask = 0;
- RegValueWrite = 0;
- RegSizeInBytes = 0;
- AccessWidth = 0;
- break;
- default:
- AndMask = RegisterHdr->RegisterList[i].AndMask;
- RegSizeInBytes = 4;
- RegValueWrite = **(UINT32 **)OrMask;
- AccessWidth = AccessS3SaveWidth32;
- break;
- }
- if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) {
- ASSERT ((AndMask != 0) && (RegSizeInBytes != 0) && (AccessWidth != 0));
- LibAmdPciRead (AccessWidth, PciAddress, &RegValueRead, StdHeader);
- RegValueWrite |= RegValueRead & (~AndMask);
- LibAmdPciWrite (AccessWidth, PciAddress, &RegValueWrite, StdHeader);
- } else {
- SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex;
- if (AndMask != 0) {
- RegisterHdr->SpecialCases[SpecialCaseIndex].Save (AccessWidth,
- PciAddress,
- &RegValueRead,
- StdHeader);
- RegValueWrite |= RegValueRead & (~AndMask);
- }
- RegisterHdr->SpecialCases[SpecialCaseIndex].Restore (AccessWidth,
- PciAddress,
- &RegValueWrite,
- StdHeader);
- }
- IntermediatePtr = (UINT8 *) *OrMask;
- *OrMask = &IntermediatePtr[RegSizeInBytes]; // += RegSizeInBytes;
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Restores the context of a 'conditional' PCI device.
- *
- * This traverses the provided register list restoring PCI registers when appropriate.
- *
- * @param[in] StdHeader AMD standard header config param.
- * @param[in] Device 'conditional' PCI device to restore.
- * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or
- * AMD_S3LATE_RESTORE.
- * @param[in,out] OrMask Current buffer pointer of raw register values.
- *
- */
-VOID
-RestoreConditionalPciDevice (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device,
- IN CALL_POINTS CallPoint,
- IN OUT VOID **OrMask
- )
-{
- UINT8 RegSizeInBytes;
- UINT8 SpecialCaseIndex;
- UINT8 *IntermediatePtr;
- UINT16 i;
- UINT32 Socket;
- UINT32 Module;
- UINT32 RegValueRead;
- UINT32 RegValueWrite;
- UINT32 AndMask;
- ACCESS_WIDTH AccessWidth;
- AGESA_STATUS IgnoredSts;
- PCI_ADDR PciAddress;
- CPCI_REGISTER_BLOCK_HEADER *RegisterHdr;
-
- GetSocketModuleOfNode ((UINT32) Device->Node,
- &Socket,
- &Module,
- StdHeader);
- GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
-
- if (CallPoint == INIT_RESUME) {
- MemFS3GetCPciDeviceRegisterList (Device, &RegisterHdr, StdHeader);
- } else {
- S3GetCPciDeviceRegisterList (Device, &RegisterHdr, StdHeader);
- }
-
- for (i = 0; i < RegisterHdr->NumRegisters; i++) {
- if (((Device->Mask1 & RegisterHdr->RegisterList[i].Mask1) != 0) &&
- ((Device->Mask2 & RegisterHdr->RegisterList[i].Mask2) != 0)) {
- PciAddress.Address.Function = RegisterHdr->RegisterList[i].Function;
- PciAddress.Address.Register = RegisterHdr->RegisterList[i].Offset;
- RegSizeInBytes = RegisterHdr->RegisterList[i].Type.RegisterSize;
- switch (RegSizeInBytes) {
- case 1:
- AndMask = 0xFFFFFFFF & ((UINT8) RegisterHdr->RegisterList[i].AndMask);
- RegValueWrite = **(UINT8 **)OrMask;
- AccessWidth = AccessS3SaveWidth8;
- break;
- case 2:
- AndMask = 0xFFFFFFFF & ((UINT16) RegisterHdr->RegisterList[i].AndMask);
- RegValueWrite = **(UINT16 **)OrMask;
- AccessWidth = AccessS3SaveWidth16;
- break;
- case 3:
- // In this case, we don't need to restore a register. We just need to call a special
- // function to do certain things in the save and resume sequence.
- // This should not be used in a non-special case.
- AndMask = 0;
- RegValueWrite = 0;
- RegSizeInBytes = 0;
- AccessWidth = 0;
- break;
- default:
- AndMask = RegisterHdr->RegisterList[i].AndMask;
- RegSizeInBytes = 4;
- RegValueWrite = **(UINT32 **)OrMask;
- AccessWidth = AccessS3SaveWidth32;
- break;
- }
- if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) {
- LibAmdPciRead (AccessWidth, PciAddress, &RegValueRead, StdHeader);
- RegValueWrite |= RegValueRead & (~AndMask);
- LibAmdPciWrite (AccessWidth, PciAddress, &RegValueWrite, StdHeader);
- } else {
- SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex;
- if (AndMask != 0) {
- RegisterHdr->SpecialCases[SpecialCaseIndex].Save (AccessWidth,
- PciAddress,
- &RegValueRead,
- StdHeader);
- RegValueWrite |= RegValueRead & (~AndMask);
- }
- RegisterHdr->SpecialCases[SpecialCaseIndex].Restore (AccessWidth,
- PciAddress,
- &RegValueWrite,
- StdHeader);
- }
- IntermediatePtr = (UINT8 *) *OrMask;
- *OrMask = &IntermediatePtr[RegSizeInBytes];
- }
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Restores the context of an MSR device.
- *
- * This traverses the provided register list restoring MSRs.
- *
- * @param[in] StdHeader AMD standard header config param.
- * @param[in] Device MSR device to restore.
- * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or
- * AMD_S3LATE_RESTORE.
- * @param[in,out] OrMask Current buffer pointer of raw register values.
- *
- */
-VOID
-RestoreMsrDevice (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN MSR_DEVICE_DESCRIPTOR *Device,
- IN CALL_POINTS CallPoint,
- IN OUT UINT64 **OrMask
- )
-{
- UINT8 SpecialCaseIndex;
- UINT16 i;
- UINT64 RegValueRead;
- UINT64 RegValueWrite;
- MSR_REGISTER_BLOCK_HEADER *RegisterHdr;
-
- if (CallPoint == INIT_RESUME) {
- MemFS3GetMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader);
- } else {
- S3GetMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader);
- }
-
- for (i = 0; i < RegisterHdr->NumRegisters; i++) {
- RegValueWrite = **OrMask;
- if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) {
- LibAmdMsrRead (RegisterHdr->RegisterList[i].Address, &RegValueRead, StdHeader);
- RegValueWrite |= RegValueRead & (~RegisterHdr->RegisterList[i].AndMask);
- LibAmdMsrWrite (RegisterHdr->RegisterList[i].Address, &RegValueWrite, StdHeader);
- } else {
- SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex;
- RegisterHdr->SpecialCases[SpecialCaseIndex].Save (RegisterHdr->RegisterList[i].Address,
- &RegValueRead,
- StdHeader);
- RegValueWrite |= RegValueRead & (~RegisterHdr->RegisterList[i].AndMask);
- RegisterHdr->SpecialCases[SpecialCaseIndex].Restore (RegisterHdr->RegisterList[i].Address,
- &RegValueWrite,
- StdHeader);
- }
- (*OrMask)++;
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Restores the context of a 'conditional' MSR device.
- *
- * This traverses the provided register list restoring MSRs when appropriate.
- *
- * @param[in] StdHeader AMD standard header config param.
- * @param[in] Device 'conditional' MSR device to restore.
- * @param[in] CallPoint Indicates whether this is AMD_INIT_RESUME or
- * AMD_S3LATE_RESTORE.
- * @param[in,out] OrMask Current buffer pointer of raw register values.
- *
- */
-VOID
-RestoreConditionalMsrDevice (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device,
- IN CALL_POINTS CallPoint,
- IN OUT UINT64 **OrMask
- )
-{
- UINT8 SpecialCaseIndex;
- UINT16 i;
- UINT64 RegValueRead;
- UINT64 RegValueWrite;
- CMSR_REGISTER_BLOCK_HEADER *RegisterHdr;
-
- if (CallPoint == INIT_RESUME) {
- MemFS3GetCMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader);
- } else {
- S3GetCMsrDeviceRegisterList (Device, &RegisterHdr, StdHeader);
- }
-
- for (i = 0; i < RegisterHdr->NumRegisters; i++) {
- if (((Device->Mask1 & RegisterHdr->RegisterList[i].Mask1) != 0) &&
- ((Device->Mask2 & RegisterHdr->RegisterList[i].Mask2) != 0)) {
- RegValueWrite = **OrMask;
- if (RegisterHdr->RegisterList[i].Type.SpecialCaseFlag == 0) {
- LibAmdMsrRead (RegisterHdr->RegisterList[i].Address, &RegValueRead, StdHeader);
- RegValueWrite |= RegValueRead & (~RegisterHdr->RegisterList[i].AndMask);
- LibAmdMsrWrite (RegisterHdr->RegisterList[i].Address, &RegValueWrite, StdHeader);
- } else {
- SpecialCaseIndex = RegisterHdr->RegisterList[i].Type.SpecialCaseIndex;
- RegisterHdr->SpecialCases[SpecialCaseIndex].Save (RegisterHdr->RegisterList[i].Address,
- &RegValueRead,
- StdHeader);
- RegValueWrite |= RegValueRead & (~RegisterHdr->RegisterList[i].AndMask);
- RegisterHdr->SpecialCases[SpecialCaseIndex].Restore (RegisterHdr->RegisterList[i].Address,
- &RegValueWrite,
- StdHeader);
- }
- (*OrMask)++;
- }
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Unique device ID to PCI register list translator.
- *
- * This translates the given device header in storage to the appropriate list
- * of registers in the AGESA image.
- *
- * @param[out] NonMemoryRelatedDeviceList List of devices to save and restore
- * during S3LateRestore.
- * @param[in] StdHeader AMD standard header config param.
- *
- */
-VOID
-GetNonMemoryRelatedDeviceList (
- OUT DEVICE_BLOCK_HEADER **NonMemoryRelatedDeviceList,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- *NonMemoryRelatedDeviceList = NULL;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Unique device ID to PCI register list translator.
- *
- * This translates the given device header in storage to the appropriate list
- * of registers in the AGESA image.
- *
- * @param[in] Device Device header containing the unique ID.
- * @param[out] RegisterHdr Output PCI register list pointer.
- * @param[in] StdHeader AMD standard header config param.
- *
- * @retval AGESA_SUCCESS Always succeeds.
- */
-AGESA_STATUS
-S3GetPciDeviceRegisterList (
- IN PCI_DEVICE_DESCRIPTOR *Device,
- OUT PCI_REGISTER_BLOCK_HEADER **RegisterHdr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- *RegisterHdr = NULL;
- return AGESA_SUCCESS;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Unique device ID to 'conditional' PCI register list translator.
- *
- * This translates the given device header in storage to the appropriate list
- * of registers in the AGESA image.
- *
- * @param[in] Device Device header containing the unique ID.
- * @param[out] RegisterHdr Output 'conditional' PCI register list pointer.
- * @param[in] StdHeader AMD standard header config param.
- *
- * @retval AGESA_SUCCESS Always succeeds.
- */
-AGESA_STATUS
-S3GetCPciDeviceRegisterList (
- IN CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device,
- OUT CPCI_REGISTER_BLOCK_HEADER **RegisterHdr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- *RegisterHdr = NULL;
- return AGESA_SUCCESS;
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Unique device ID to MSR register list translator.
- *
- * This translates the given device header in storage to the appropriate list
- * of registers in the AGESA image.
- *
- * @param[in] Device Device header containing the unique ID.
- * @param[out] RegisterHdr Output MSR register list pointer.
- * @param[in] StdHeader AMD standard header config param.
- *
- * @retval AGESA_SUCCESS Always succeeds.
- */
-AGESA_STATUS
-S3GetMsrDeviceRegisterList (
- IN MSR_DEVICE_DESCRIPTOR *Device,
- OUT MSR_REGISTER_BLOCK_HEADER **RegisterHdr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- *RegisterHdr = NULL;
- return AGESA_SUCCESS;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Unique device ID to 'conditional' MSR register list translator.
- *
- * This translates the given device header in storage to the appropriate list
- * of registers in the AGESA image.
- *
- * @param[in] Device Device header containing the unique ID.
- * @param[out] RegisterHdr Output 'conditional' MSR register list pointer.
- * @param[in] StdHeader AMD standard header config param.
- *
- * @retval AGESA_SUCCESS Always succeeds.
- */
-AGESA_STATUS
-S3GetCMsrDeviceRegisterList (
- IN CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device,
- OUT CMSR_REGISTER_BLOCK_HEADER **RegisterHdr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- *RegisterHdr = NULL;
- return AGESA_SUCCESS;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Constructor for the AMD_S3_PARAMS structure.
- *
- * This routine initializes failsafe values for the AMD_S3_PARAMS structure
- * to be used by the AMD_INIT_RESUME, AMD_S3_SAVE, and AMD_S3LATE_RESTORE
- * entry points.
- *
- * @param[in,out] S3Params Required input parameter for the AMD_S3_SAVE,
- * AMD_INIT_RESUME, and AMD_S3_SAVE entry points.
- *
- */
-VOID
-AmdS3ParamsInitializer (
- OUT AMD_S3_PARAMS *S3Params
- )
-{
- S3Params->Signature = 0x52545341;
- S3Params->Version = 0x0000;
- S3Params->VolatileStorage = NULL;
- S3Params->VolatileStorageSize = 0x00000000;
- S3Params->Flags = 0x00000000;
- S3Params->NvStorage = NULL;
- S3Params->NvStorageSize = 0x00000000;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/S3.h b/src/vendorcode/amd/agesa/Proc/CPU/S3.h
deleted file mode 100644
index 418c74c..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/S3.h
+++ /dev/null
@@ -1,395 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * ACPI S3 support definitions.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _S3_H_
-#define _S3_H_
-
-
-/*---------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *---------------------------------------------------------------------------------------
- */
-
-/* Device related definitions */
-
-/// Header at the beginning of a context save buffer.
-typedef struct {
- UINT16 Version; ///< Version of header
- UINT16 NumDevices; ///< Number of devices in the list
- UINT16 RelativeOrMaskOffset; ///< Size of device list + header
-} DEVICE_BLOCK_HEADER;
-
-/// S3 device types
-typedef enum {
- DEV_TYPE_PCI_PRE_ESR, ///< PCI device before exiting self-refresh
- DEV_TYPE_PCI, ///< PCI device after exiting self-refresh
- DEV_TYPE_CPCI_PRE_ESR, ///< 'conditional' PCI device before exiting self-refresh
- DEV_TYPE_CPCI, ///< 'conditional' PCI device after exiting self-refresh
- DEV_TYPE_MSR_PRE_ESR, ///< MSR device before exiting self-refresh
- DEV_TYPE_MSR, ///< MSR device after exiting self-refresh
- DEV_TYPE_CMSR_PRE_ESR, ///< 'conditional' MSR device before exiting self-refresh
- DEV_TYPE_CMSR ///< 'conditional' MSR device after exiting self-refresh
-} S3_DEVICE_TYPES;
-
-/// S3 restoration call points
-typedef enum {
- INIT_RESUME, ///< AMD_INIT_RESUME
- S3_LATE_RESTORE ///< AMD_S3LATE_RESTORE
-} CALL_POINTS;
-
-/// S3 device common header
-typedef struct {
- UINT32 RegisterListID; ///< Unique ID of this device
- UINT8 Type; ///< Appropriate S3_DEVICE_TYPES type
-} DEVICE_DESCRIPTOR;
-
-/// S3 PCI device header
-typedef struct {
- UINT32 RegisterListID; ///< Unique ID of this device
- UINT8 Type; ///< DEV_TYPE_PCI / DEV_TYPE_PCI_PRE_ESR
- UINT8 Node; ///< Zero-based node number
-} PCI_DEVICE_DESCRIPTOR;
-
-/// S3 'conditional' PCI device header
-typedef struct {
- UINT32 RegisterListID; ///< Unique ID of this device
- UINT8 Type; ///< DEV_TYPE_CPCI / DEV_TYPE_CPCI_PRE_ESR
- UINT8 Node; ///< Zero-based node number
- UINT8 Mask1; ///< Conditional mask 1
- UINT8 Mask2; ///< Conditional mask 2
-} CONDITIONAL_PCI_DEVICE_DESCRIPTOR;
-
-/// S3 MSR device header
-typedef struct {
- UINT32 RegisterListID; ///< Unique ID of this device
- UINT8 Type; ///< DEV_TYPE_MSR / DEV_TYPE_MSR_PRE_ESR
-} MSR_DEVICE_DESCRIPTOR;
-
-/// S3 'conditional' MSR device header
-typedef struct {
- UINT32 RegisterListID; ///< Unique ID of this device
- UINT8 Type; ///< DEV_TYPE_CMSR / DEV_TYPE_CMSR_PRE_ESR
- UINT8 Mask1; ///< Conditional mask 1
- UINT8 Mask2; ///< Conditional mask 2
-} CONDITIONAL_MSR_DEVICE_DESCRIPTOR;
-
-/* Special case related definitions */
-
-/**
- * PCI special case save handler
- *
- * @param[in] AccessWidth 8, 16, or 32 bit wide access
- * @param[in] Address full PCI address of the register to save
- * @param[out] Value Value read from the register
- * @param[in] ConfigPtr AMD standard header config parameter
- *
- */
-typedef VOID (*PF_S3_SPECIAL_PCI_SAVE) (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR Address,
- OUT VOID *Value,
- IN VOID *ConfigPtr
- );
-
-/**
- * PCI special case restore handler
- *
- * @param[in] AccessWidth 8, 16, or 32 bit wide access
- * @param[in] Address full PCI address of the register to save
- * @param[in] Value Value to write to the register
- * @param[in] ConfigPtr AMD standard header config parameter
- *
- */
-typedef VOID (*PF_S3_SPECIAL_PCI_RESTORE) (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR PciAddress,
- IN VOID *Value,
- IN VOID *StdHeader
- );
-
-/**
- * MSR special case save handler
- *
- * @param[in] MsrAddress Address of model specific register to save
- * @param[out] Value Value read from the register
- * @param[in] ConfigPtr AMD standard header config parameter
- *
- */
-typedef VOID (*PF_S3_SPECIAL_MSR_SAVE) (
- IN UINT32 MsrAddress,
- OUT UINT64 *Value,
- IN VOID *StdHeader
- );
-
-/**
- * MSR special case restore handler
- *
- * @param[in] MsrAddress Address of model specific register to restore
- * @param[in] Value Value to write to the register
- * @param[in] ConfigPtr AMD standard header config parameter
- *
- */
-typedef VOID (*PF_S3_SPECIAL_MSR_RESTORE) (
- IN UINT32 MsrAddress,
- IN UINT64 *Value,
- IN VOID *StdHeader
- );
-
-/// PCI special case save/restore structure.
-typedef struct {
- PF_S3_SPECIAL_PCI_SAVE Save; ///< Save routine
- PF_S3_SPECIAL_PCI_RESTORE Restore; ///< Restore routine
-} PCI_SPECIAL_CASE;
-
-/// MSR special case save/restore structure.
-typedef struct {
- PF_S3_SPECIAL_MSR_SAVE Save; ///< Save routine
- PF_S3_SPECIAL_MSR_RESTORE Restore; ///< Restore routine
-} MSR_SPECIAL_CASE;
-
-/* Register related definitions */
-/// S3 register type bit fields
-typedef struct {
- UINT8 SpecialCaseIndex:4; ///< Special Case array index
- UINT8 RegisterSize:3; ///< For PCI, 1 = byte, 2 = word, else = dword.
- ///< For MSR, don't care
- UINT8 SpecialCaseFlag:1; ///< Indicates special case
-} S3_REGISTER_TYPE;
-
-/// S3 PCI register descriptor.
-typedef struct {
- S3_REGISTER_TYPE Type; ///< Type[7] = special case flag,
- ///< Type[6:3] = register size in bytes,
- ///< Type[2:0] = special case index
- UINT8 Function; ///< PCI function of the register
- UINT16 Offset; ///< PCI offset of the register
- UINT32 AndMask; ///< AND mask to be applied to the value before saving
-} PCI_REG_DESCRIPTOR;
-
-/// S3 'conditional' PCI register descriptor.
-typedef struct {
- S3_REGISTER_TYPE Type; ///< Type[7] = special case flag,
- ///< Type[6:3] = register size in bytes,
- ///< Type[2:0] = special case index
- UINT8 Function; ///< PCI function of the register
- UINT16 Offset; ///< PCI offset of the register
- UINT32 AndMask; ///< AND mask to be applied to the value before saving
- UINT8 Mask1; ///< conditional mask 1
- UINT8 Mask2; ///< conditional mask 2
-} CONDITIONAL_PCI_REG_DESCRIPTOR;
-
-/// S3 MSR register descriptor.
-typedef struct {
- S3_REGISTER_TYPE Type; ///< Type[7] = special case flag,
- ///< Type[6:3] = reserved,
- ///< Type[2:0] = special case index
- UINT32 Address; ///< MSR address
- UINT64 AndMask; ///< AND mask to be applied to the value before saving
-} MSR_REG_DESCRIPTOR;
-
-/// S3 'conditional' MSR register descriptor.
-typedef struct {
- S3_REGISTER_TYPE Type; ///< Type[7] = special case flag,
- ///< Type[6:3] = reserved,
- ///< Type[2:0] = special case index
- UINT32 Address; ///< MSR address
- UINT64 AndMask; ///< AND mask to be applied to the value before saving
- UINT8 Mask1; ///< conditional mask 1
- UINT8 Mask2; ///< conditional mask 2
-} CONDITIONAL_MSR_REG_DESCRIPTOR;
-
-/// Common header at the beginning of an S3 register list.
-typedef struct {
- UINT16 Version; ///< Version of header
- UINT16 NumRegisters; ///< Number of registers in the list
-} REGISTER_BLOCK_HEADER;
-
-/// S3 PCI register list header.
-typedef struct {
- UINT16 Version; ///< Version of header
- UINT16 NumRegisters; ///< Number of registers in the list
- PCI_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor
- PCI_SPECIAL_CASE *SpecialCases; ///< Pointer to array of special case handlers
-} PCI_REGISTER_BLOCK_HEADER;
-
-/// S3 'conditional' PCI register list header.
-typedef struct {
- UINT16 Version; ///< Version of header
- UINT16 NumRegisters; ///< Number of registers in the list
- CONDITIONAL_PCI_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor
- PCI_SPECIAL_CASE *SpecialCases; ///< Pointer to array of special case handlers
-} CPCI_REGISTER_BLOCK_HEADER;
-
-/// S3 MSR register list header.
-typedef struct {
- UINT16 Version; ///< Version of header
- UINT16 NumRegisters; ///< Number of registers in the list
- MSR_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor
- MSR_SPECIAL_CASE *SpecialCases; ///< Pointer to array of special case handlers
-} MSR_REGISTER_BLOCK_HEADER;
-
-/// S3 'conditional' MSR register list header.
-typedef struct {
- UINT16 Version; ///< Version of header
- UINT16 NumRegisters; ///< Number of registers in the list
- CONDITIONAL_MSR_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor
- MSR_SPECIAL_CASE *SpecialCases; ///< Pointer to array of special case handlers
-} CMSR_REGISTER_BLOCK_HEADER;
-
-/// S3 device descriptor pointers for ease of proper pointer advancement.
-typedef union {
- DEVICE_DESCRIPTOR *CommonDeviceHeader; ///< Common header
- PCI_DEVICE_DESCRIPTOR *PciDevice; ///< PCI header
- CONDITIONAL_PCI_DEVICE_DESCRIPTOR *CPciDevice; ///< 'conditional' PCI header
- MSR_DEVICE_DESCRIPTOR *MsrDevice; ///< MSR header
- CONDITIONAL_MSR_DEVICE_DESCRIPTOR *CMsrDevice; ///< 'conditional' MSR header
-} DEVICE_DESCRIPTORS;
-
-/// S3 register list header pointers for ease of proper pointer advancement.
-typedef union {
- DEVICE_DESCRIPTOR *CommonDeviceHeader; ///< Common header
- PCI_REGISTER_BLOCK_HEADER *PciRegisters; ///< PCI header
- CPCI_REGISTER_BLOCK_HEADER *CPciRegisters; ///< 'conditional' PCI header
- MSR_REGISTER_BLOCK_HEADER *MsrRegisters; ///< MSR header
- CMSR_REGISTER_BLOCK_HEADER *CMsrRegisters; ///< 'conditional' MSR header
-} REGISTER_BLOCK_HEADERS;
-
-/// S3 Volatile Storage Header
-typedef struct {
- UINT32 HeapOffset; ///< Offset to beginning of heap data
- UINT32 HeapSize; ///< Size of the heap data
- UINT32 RegisterDataOffset; ///< Offset to beginning of raw save data
- UINT32 RegisterDataSize; ///< Size of raw save data
-} S3_VOLATILE_STORAGE_HEADER;
-
-
-/*---------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *---------------------------------------------------------------------------------------
- */
-UINT32
-GetWorstCaseContextSize (
- IN DEVICE_BLOCK_HEADER *DeviceList,
- IN CALL_POINTS CallPoint,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-SaveDeviceListContext (
- IN DEVICE_BLOCK_HEADER *DeviceList,
- IN VOID *Storage,
- IN CALL_POINTS CallPoint,
- OUT UINT32 *ActualBufferSize,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-RestorePreESRContext (
- OUT VOID **OrMaskPtr,
- IN VOID *Storage,
- IN CALL_POINTS CallPoint,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-RestorePostESRContext (
- IN VOID *OrMaskPtr,
- IN VOID *Storage,
- IN CALL_POINTS CallPoint,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-AmdS3ParamsInitializer (
- OUT AMD_S3_PARAMS *S3Params
- );
-
-VOID
-GetNonMemoryRelatedDeviceList (
- OUT DEVICE_BLOCK_HEADER **NonMemoryRelatedDeviceList,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-S3GetPciDeviceRegisterList (
- IN PCI_DEVICE_DESCRIPTOR *Device,
- OUT PCI_REGISTER_BLOCK_HEADER **RegisterHdr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-S3GetCPciDeviceRegisterList (
- IN CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device,
- OUT CPCI_REGISTER_BLOCK_HEADER **RegisterHdr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-S3GetMsrDeviceRegisterList (
- IN MSR_DEVICE_DESCRIPTOR *Device,
- OUT MSR_REGISTER_BLOCK_HEADER **RegisterHdr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-S3GetCMsrDeviceRegisterList (
- IN CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device,
- OUT CMSR_REGISTER_BLOCK_HEADER **RegisterHdr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-
-#endif // _S3_H_
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Table.c b/src/vendorcode/amd/agesa/Proc/CPU/Table.c
deleted file mode 100644
index 1ceaed0..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Table.c
+++ /dev/null
@@ -1,1664 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU Register Table Related Functions
- *
- * Set registers according to a set of register tables
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 38402 $ @e \$Date: 2010-09-24 02:11:44 +0800 (Fri, 24 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "OptionMultiSocket.h"
-#include "cpuRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "Table.h"
-#include "GeneralServices.h"
-#include "cpuServices.h"
-#include "cpuFeatures.h"
-#include "CommonReturns.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_TABLE_FILECODE
-
-extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-extern BUILD_OPT_CFG UserOptions;
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * An iterator for all the Family and Model Register Tables.
- *
- * RegisterTableHandle should be set to NULL to begin iteration, the first time the method is
- * invoked. Register tables can be processed, until this method returns NULL. RegisterTableHandle
- * should simply be passed back to the method without modification or use by the caller.
- * The table selector allows the relevant tables for different cores to be iterated, if the family separates
- * tables. For example, MSRs can be in a table processed by all cores and PCI registers in a table processed by
- * primary cores.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] Selector Select whether to iterate over tables for either all cores, primary cores, bsp, ....
- * @param[in,out] RegisterTableHandle IN: The handle of the current register table, or NULL if Begin.
- * OUT: The handle of the next register table, if not End.
- * @param[out] NumberOfEntries The number of entries in the table returned, if not End.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @return The pointer to the next Register Table, or NULL if End.
- */
-TABLE_ENTRY_FIELDS
-STATIC
-*GetNextRegisterTable (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN TABLE_CORE_SELECTOR Selector,
- IN OUT REGISTER_TABLE ***RegisterTableHandle,
- OUT UINTN *NumberOfEntries,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- REGISTER_TABLE **NextTable;
- TABLE_ENTRY_FIELDS *Entries;
-
- ASSERT ((FamilySpecificServices != NULL) && (StdHeader != NULL));
- ASSERT (Selector < TableEntryTypeMax);
-
- NextTable = *RegisterTableHandle;
- if (NextTable == NULL) {
- // Begin
- NextTable = FamilySpecificServices->RegisterTableList;
- IDS_OPTION_HOOK (IDS_REG_TABLE, &NextTable, StdHeader);
- } else {
- NextTable++;
- }
- // skip if not selected
- while ((*NextTable != NULL) && (*NextTable)->Selector != Selector) {
- NextTable++;
- }
- if (*NextTable == NULL) {
- // End
- *RegisterTableHandle = NULL;
- Entries = NULL;
- } else {
- // Iterate next table
- *RegisterTableHandle = NextTable;
- *NumberOfEntries = (*NextTable)->NumberOfEntries;
- Entries = (TABLE_ENTRY_FIELDS *) (*NextTable)->Table;
- }
- return Entries;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Compare counts to a pair of ranges.
- *
- * @param[in] FirstCount The actual count to be compared to the first range.
- * @param[in] SecondCount The actual count to be compared to the second range.
- * @param[in] Ranges The ranges which the counts are compared to.
- *
- * @retval TRUE Either one, or both, of the counts is in the range given.
- * @retval FALSE Neither count is in the range given.
- */
-BOOLEAN
-IsEitherCountInRange (
- IN UINTN FirstCount,
- IN UINTN SecondCount,
- IN COUNT_RANGE_FEATURE Ranges
- )
-{
- // Errors: Entire Range value is zero, Min and Max reversed or not <=, ranges overlap (OK if first range is all),
- // the real counts are too big.
- ASSERT ((Ranges.Range0Min <= Ranges.Range0Max) &&
- (Ranges.Range1Min <= Ranges.Range1Max) &&
- (Ranges.Range0Max != 0) &&
- (Ranges.Range1Max != 0) &&
- ((Ranges.Range0Max == COUNT_RANGE_HIGH) || (Ranges.Range0Max < Ranges.Range1Min)) &&
- ((FirstCount < COUNT_RANGE_HIGH) && (SecondCount < COUNT_RANGE_HIGH)));
-
- return (BOOLEAN) (((FirstCount <= Ranges.Range0Max) && (FirstCount >= Ranges.Range0Min)) ||
- ((SecondCount <= Ranges.Range1Max) && (SecondCount >= Ranges.Range1Min)));
-}
-
-/*-------------------------------------------------------------------------------------*/
-/**
- * Returns the performance profile features list of the currently running processor core.
- *
- * @param[out] Features The performance profile features supported by this platform
- * @param[in] PlatformConfig Config handle for platform specific information
- * @param[in] StdHeader Header for library and services
- *
- */
-VOID
-GetPerformanceFeatures (
- OUT PERFORMANCE_PROFILE_FEATS *Features,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- CPUID_DATA CpuidDataStruct;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
-
- Features->PerformanceProfileValue = 0;
- // Reflect Probe Filter Configuration.
- Features->PerformanceProfileFeatures.ProbeFilter = 0;
- if (IsFeatureEnabled (HtAssist, PlatformConfig, StdHeader)) {
- Features->PerformanceProfileFeatures.ProbeFilter = 1;
- }
-
- // Reflect Display Refresh Requests use 32 bytes Configuration.
- Features->PerformanceProfileFeatures.RefreshRequest32Byte = 0;
- if (PlatformConfig->PlatformProfile.Use32ByteRefresh) {
- Features->PerformanceProfileFeatures.RefreshRequest32Byte = 1;
- }
- // Reflect Mct Isoc Read Priority set to variable Configuration.
- Features->PerformanceProfileFeatures.MctIsocVariable = 0;
- if (PlatformConfig->PlatformProfile.UseVariableMctIsocPriority) {
- Features->PerformanceProfileFeatures.MctIsocVariable = 1;
- }
- // Indicate if this boot is a warm reset.
- Features->PerformanceProfileFeatures.IsWarmReset = 0;
- if (IsWarmReset (StdHeader)) {
- Features->PerformanceProfileFeatures.IsWarmReset = 1;
- }
-
- // Get L3 Cache present as indicated by CPUID
- Features->PerformanceProfileFeatures.L3Cache = 0;
- Features->PerformanceProfileFeatures.NoL3Cache = 1;
- LibAmdCpuidRead (AMD_CPUID_L2L3Cache_L2TLB, &CpuidDataStruct, StdHeader);
- if (((CpuidDataStruct.EDX_Reg & 0xFFFC0000) >> 18) != 0) {
- Features->PerformanceProfileFeatures.L3Cache = 1;
- Features->PerformanceProfileFeatures.NoL3Cache = 0;
- }
-
- // Get VRM select high speed from build option.
- Features->PerformanceProfileFeatures.VrmHighSpeed = 0;
- if (PlatformConfig->VrmProperties[CoreVrm].HiSpeedEnable) {
- Features->PerformanceProfileFeatures.VrmHighSpeed = 1;
- }
-
- // Get some family, model specific performance type info.
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
- ASSERT (FamilySpecificServices != NULL);
-
- // Is the Northbridge P-State feature enabled
- Features->PerformanceProfileFeatures.NbPstates = 0;
- if (FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, PlatformConfig, StdHeader)) {
- Features->PerformanceProfileFeatures.NbPstates = 1;
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Perform the MSR Register Entry.
- *
- * @TableEntryTypeMethod{::MsrRegister}.
- *
- * Read - Modify - Write the MSR, clearing masked bits, and setting the data bits.
- *
- * @param[in] Entry The MSR register entry to perform
- * @param[in] PlatformConfig Config handle for platform specific information
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-SetRegisterForMsrEntry (
- IN TABLE_ENTRY_DATA *Entry,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 MsrData;
-
- // Even for only single bit fields, use those in the mask. "Mask nothing" is a bug, even if just by policy.
- ASSERT (Entry->MsrEntry.Mask != 0);
-
- LibAmdMsrRead (Entry->MsrEntry.Address, &MsrData, StdHeader);
- MsrData = MsrData & (~(Entry->MsrEntry.Mask));
- MsrData = MsrData | Entry->MsrEntry.Data;
- LibAmdMsrWrite (Entry->MsrEntry.Address, &MsrData, StdHeader);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Perform the PCI Register Entry.
- *
- * @TableEntryTypeMethod{::PciRegister}.
- *
- * Make the current core's PCI address with the function and register for the entry.
- * Read - Modify - Write the PCI register, clearing masked bits, and setting the data bits.
- *
- * @param[in] Entry The PCI register entry to perform
- * @param[in] PlatformConfig Config handle for platform specific information
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-SetRegisterForPciEntry (
- IN TABLE_ENTRY_DATA *Entry,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 TempVar32_a;
- UINT32 MySocket;
- UINT32 MyModule;
- UINT32 Ignored;
- PCI_ADDR MyPciAddress;
- AGESA_STATUS IgnoredSts;
- TABLE_ENTRY_DATA PciEntry;
-
- // Errors: Possible values in unused entry space, extra type features, value range checks.
- // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
- // Even for only single bit fields, use those in the mask. "Mask nothing" is a bug, even if just by policy.
- ASSERT ((Entry->InitialValues[4] == 0) &&
- (Entry->InitialValues[3] == 0) &&
- (Entry->PciEntry.Mask != 0));
-
- LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader);
- PciEntry.PciEntry = Entry->PciEntry;
-
- IDS_OPTION_HOOK (IDS_SET_PCI_REGISTER_ENTRY, &PciEntry, StdHeader);
-
- IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredSts);
- GetPciAddress (StdHeader, MySocket, MyModule, &MyPciAddress, &IgnoredSts);
- MyPciAddress.Address.Function = PciEntry.PciEntry.Address.Address.Function;
- MyPciAddress.Address.Register = PciEntry.PciEntry.Address.Address.Register;
- LibAmdPciRead (AccessWidth32, MyPciAddress, &TempVar32_a, StdHeader);
- TempVar32_a = TempVar32_a & (~(PciEntry.PciEntry.Mask));
- TempVar32_a = TempVar32_a | PciEntry.PciEntry.Data;
- LibAmdPciWrite (AccessWidth32, MyPciAddress, &TempVar32_a, StdHeader);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Perform the Family Specific Workaround Register Entry.
- *
- * @TableEntryTypeMethod{::FamSpecificWorkaround}.
- *
- * Call the function, passing the data.
- *
- * See if you can use the other entries or make an entry that covers the fix.
- * After all, the purpose of having a table entry is to @b NOT have code which
- * isn't generic feature code, but is family/model code specific to one case.
- *
- * @param[in] Entry The Family Specific Workaround register entry to perform
- * @param[in] PlatformConfig Config handle for platform specific information
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-SetRegisterForFamSpecificWorkaroundEntry (
- IN TABLE_ENTRY_DATA *Entry,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- ASSERT (Entry->FamSpecificEntry.DoAction != NULL);
-
- Entry->FamSpecificEntry.DoAction (Entry->FamSpecificEntry.Data, StdHeader);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Program HT Phy PCI registers using BKDG values.
- *
- * @TableEntryTypeMethod{::HtPhyRegister}.
- *
- *
- * @param[in] Entry The type specific entry data to be implemented (that is written).
- * @param[in] PlatformConfig Config handle for platform specific information
- * @param[in] StdHeader Config params for library, services.
- *
- */
-VOID
-SetRegisterForHtPhyEntry (
- IN TABLE_ENTRY_DATA *Entry,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Link;
- UINT32 MySocket;
- UINT32 MyModule;
- AGESA_STATUS IgnoredStatus;
- UINT32 Ignored;
- CPU_LOGICAL_ID CpuFamilyRevision;
- PCI_ADDR CapabilitySet;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
- BOOLEAN MatchedSublink1;
- HT_FREQUENCIES Freq0;
- HT_FREQUENCIES Freq1;
-
- // Errors: Possible values in unused entry space, extra type features, value range checks.
- // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
- ASSERT ((Entry->InitialValues[4] == 0) &&
- ((Entry->HtPhyEntry.TypeFeats.HtPhyLinkValue & ~(HTPHY_LINKTYPE_ALL)) == 0) &&
- (Entry->HtPhyEntry.Address < HTPHY_REGISTER_MAX));
-
- IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus);
- GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus);
- GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
- GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader);
- Link = 0;
- while (FamilySpecificServices->NextLinkHasHtPhyFeats (
- FamilySpecificServices,
- &CapabilitySet,
- &Link,
- &Entry->HtPhyEntry.TypeFeats,
- &MatchedSublink1,
- &Freq0,
- &Freq1,
- StdHeader)) {
- FamilySpecificServices->SetHtPhyRegister (FamilySpecificServices, &Entry->HtPhyEntry, CapabilitySet, Link, StdHeader);
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Program a range of HT Phy PCI registers using BKDG values.
- *
- * @TableEntryTypeMethod{::HtPhyRangeRegister}.
- *
- *
- * @param[in] Entry The type specific entry data to be implemented (that is written).
- * @param[in] PlatformConfig Config handle for platform specific information
- * @param[in] StdHeader Config params for library, services.
- *
- */
-VOID
-SetRegisterForHtPhyRangeEntry (
- IN TABLE_ENTRY_DATA *Entry,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Link;
- UINT32 MySocket;
- UINT32 MyModule;
- AGESA_STATUS IgnoredStatus;
- UINT32 Ignored;
- CPU_LOGICAL_ID CpuFamilyRevision;
- PCI_ADDR CapabilitySet;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
- HT_PHY_TYPE_ENTRY_DATA CurrentHtPhyRegister;
- BOOLEAN MatchedSublink1;
- HT_FREQUENCIES Freq0;
- HT_FREQUENCIES Freq1;
-
- // Errors: Possible values in unused entry space, extra type features, value range checks.
- // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
- ASSERT (((Entry->HtPhyRangeEntry.TypeFeats.HtPhyLinkValue & ~(HTPHY_LINKTYPE_ALL)) == 0) &&
- (Entry->HtPhyRangeEntry.LowAddress <= Entry->HtPhyRangeEntry.HighAddress) &&
- (Entry->HtPhyRangeEntry.HighAddress < HTPHY_REGISTER_MAX) &&
- (Entry->HtPhyRangeEntry.HighAddress != 0));
-
- CurrentHtPhyRegister.Mask = Entry->HtPhyRangeEntry.Mask;
- CurrentHtPhyRegister.Data = Entry->HtPhyRangeEntry.Data;
- CurrentHtPhyRegister.TypeFeats = Entry->HtPhyRangeEntry.TypeFeats;
-
- IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus);
- GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus);
- GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
- GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader);
- Link = 0;
- while (FamilySpecificServices->NextLinkHasHtPhyFeats (
- FamilySpecificServices,
- &CapabilitySet,
- &Link,
- &Entry->HtPhyRangeEntry.TypeFeats,
- &MatchedSublink1,
- &Freq0,
- &Freq1,
- StdHeader)) {
- for (CurrentHtPhyRegister.Address = Entry->HtPhyRangeEntry.LowAddress;
- CurrentHtPhyRegister.Address <= Entry->HtPhyRangeEntry.HighAddress;
- CurrentHtPhyRegister.Address++) {
- FamilySpecificServices->SetHtPhyRegister (FamilySpecificServices, &CurrentHtPhyRegister, CapabilitySet, Link, StdHeader);
- }
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Is PackageLink an Internal Link?
- *
- * This is a test for the logical link match codes in the user interface, not a test for
- * the actual northbridge links.
- *
- * @param[in] PackageLink The link
- *
- * @retval TRUE This is an internal link
- * @retval FALSE This is not an internal link
- */
-BOOLEAN
-STATIC
-IsDeemphasisLinkInternal (
- IN UINT32 PackageLink
- )
-{
- return (BOOLEAN) ((PackageLink <= HT_LIST_MATCH_INTERNAL_LINK_2) && (PackageLink >= HT_LIST_MATCH_INTERNAL_LINK_0));
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get the Package Link number, for the current node and real link number.
- *
- * Based on the link to package link mapping from BKDG, look up package link for
- * the input link on the internal node number corresponding to the current core's node.
- * For single module processors, the northbridge link and package link are the same.
- *
- * @param[in] Link the link on the current node.
- * @param[in] FamilySpecificServices CPU specific support interface.
- * @param[in] StdHeader Config params for library, services.
- *
- * @return the Package Link, HT_LIST_TERMINAL Not connected in package, HT_LIST_MATCH_INTERNAL_LINK package internal link.
- *
- */
-UINT32
-STATIC
-LookupPackageLink (
- IN UINT32 Link,
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 PackageLinkMapItem;
- UINT32 PackageLink;
- AP_MAIL_INFO ApMailbox;
-
- PackageLink = HT_LIST_TERMINAL;
-
- GetApMailbox (&ApMailbox.Info, StdHeader);
-
- if (ApMailbox.Fields.ModuleType != 0) {
- ASSERT (FamilySpecificServices->PackageLinkMap != NULL);
- // Use table to find this module's package link
- PackageLinkMapItem = 0;
- while ((*FamilySpecificServices->PackageLinkMap)[PackageLinkMapItem].Link != HT_LIST_TERMINAL) {
- if (((*FamilySpecificServices->PackageLinkMap)[PackageLinkMapItem].Module == ApMailbox.Fields.Module) &&
- ((*FamilySpecificServices->PackageLinkMap)[PackageLinkMapItem].Link == Link)) {
- PackageLink = (*FamilySpecificServices->PackageLinkMap)[PackageLinkMapItem].PackageLink;
- break;
- }
- PackageLinkMapItem++;
- }
- } else {
- PackageLink = Link;
- }
- return PackageLink;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Get the platform's specified deemphasis levels for the current link.
- *
- * Search the platform's list for a match to the current link and also matching frequency.
- * If a match is found, use the specified deemphasis levels.
- *
- * @param[in] Socket The current Socket.
- * @param[in] Link The link on that socket.
- * @param[in] Frequency The frequency the link is set to.
- * @param[in] PlatformConfig Config handle for platform specific information
- * @param[in] FamilySpecificServices CPU specific support interface.
- * @param[in] StdHeader Config params for library, services.
- *
- * @return The Deemphasis values for the link.
- */
-UINT32
-STATIC
-GetLinkDeemphasis (
- IN UINT32 Socket,
- IN UINT32 Link,
- IN HT_FREQUENCIES Frequency,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Result;
- CPU_HT_DEEMPHASIS_LEVEL *Match;
- UINT32 PackageLink;
-
- PackageLink = LookupPackageLink (Link, FamilySpecificServices, StdHeader);
- // All External and Internal links have deemphasis level none as the default.
- // However, it is expected that the platform BIOS will provide deemphasis levels for the external links.
- Result = ((DCV_LEVEL_NONE) | (DEEMPHASIS_LEVEL_NONE));
-
- if (PlatformConfig->PlatformDeemphasisList != NULL) {
- Match = PlatformConfig->PlatformDeemphasisList;
- while (Match->Socket != HT_LIST_TERMINAL) {
- if (((Match->Socket == Socket) || (Match->Socket == HT_LIST_MATCH_ANY)) &&
- ((Match->Link == PackageLink) ||
- ((Match->Link == HT_LIST_MATCH_ANY) && (!IsDeemphasisLinkInternal (PackageLink))) ||
- ((Match->Link == HT_LIST_MATCH_INTERNAL_LINK) && (IsDeemphasisLinkInternal (PackageLink)))) &&
- ((Match->LoFreq <= Frequency) && (Match->HighFreq >= Frequency))) {
- // Found a match, get the deemphasis value.
- ASSERT ((MaxPlatformDeemphasisLevel > Match->DcvDeemphasis) | (MaxPlatformDeemphasisLevel > Match->ReceiverDeemphasis));
- Result = ((1 << Match->DcvDeemphasis) | (1 << Match->ReceiverDeemphasis));
- break;
- } else {
- Match++;
- }
- }
- }
- return Result;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Program Deemphasis registers using BKDG values, for the platform specified levels.
- *
- * @TableEntryTypeMethod{::DeemphasisRegister}.
- *
- *
- * @param[in] Entry The type specific entry data to be implemented (that is written).
- * @param[in] PlatformConfig Config handle for platform specific information
- * @param[in] StdHeader Config params for library, services.
- *
- */
-VOID
-SetRegisterForDeemphasisEntry (
- IN TABLE_ENTRY_DATA *Entry,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Link;
- UINT32 MySocket;
- UINT32 MyModule;
- AGESA_STATUS IgnoredStatus;
- UINT32 Ignored;
- CPU_LOGICAL_ID CpuFamilyRevision;
- PCI_ADDR CapabilitySet;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
- BOOLEAN MatchedSublink1;
- HT_FREQUENCIES Freq0;
- HT_FREQUENCIES Freq1;
-
- // Errors: Possible values in unused entry space, extra type features, value range checks.
- // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
- ASSERT (((Entry->DeemphasisEntry.Levels.DeemphasisValues & ~(VALID_DEEMPHASIS_LEVELS)) == 0) &&
- ((Entry->DeemphasisEntry.HtPhyEntry.TypeFeats.HtPhyLinkValue & ~(HTPHY_LINKTYPE_ALL)) == 0) &&
- (Entry->DeemphasisEntry.HtPhyEntry.Address < HTPHY_REGISTER_MAX));
-
- IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus);
- GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus);
- GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
- GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader);
- Link = 0;
- while (FamilySpecificServices->NextLinkHasHtPhyFeats (
- FamilySpecificServices,
- &CapabilitySet,
- &Link,
- &Entry->DeemphasisEntry.HtPhyEntry.TypeFeats,
- &MatchedSublink1,
- &Freq0,
- &Freq1,
- StdHeader)) {
- if (DoesEntryTypeSpecificInfoMatch (
- GetLinkDeemphasis (
- MySocket,
- (MatchedSublink1 ? (Link + 4) : Link),
- (MatchedSublink1 ? Freq1 : Freq0),
- PlatformConfig,
- FamilySpecificServices,
- StdHeader),
- Entry->DeemphasisEntry.Levels.DeemphasisValues)) {
- FamilySpecificServices->SetHtPhyRegister (
- FamilySpecificServices,
- &Entry->DeemphasisEntry.HtPhyEntry,
- CapabilitySet,
- Link,
- StdHeader
- );
- }
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Program HT Phy PCI registers which have complex frequency dependencies.
- *
- * @TableEntryTypeMethod{::HtPhyFreqRegister}.
- *
- * After matching a link for HT Features, check if the HT frequency matches the given range.
- * If it does, get the northbridge frequency limits for implemented NB P-states and check if
- * each matches the given range - range 0 and range 1 for each NB frequency, respectively.
- * If all matches, apply the entry.
- *
- * @param[in] Entry The type specific entry data to be implemented (that is written).
- * @param[in] PlatformConfig Config handle for platform specific information
- * @param[in] StdHeader Config params for library, services.
- *
- */
-VOID
-SetRegisterForHtPhyFreqEntry (
- IN TABLE_ENTRY_DATA *Entry,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Link;
- UINT32 MySocket;
- UINT32 MyModule;
- AGESA_STATUS IgnoredStatus;
- UINT32 Ignored;
- CPU_LOGICAL_ID CpuFamilyRevision;
- PCI_ADDR CapabilitySet;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
- BOOLEAN MatchedSublink1;
- HT_FREQUENCIES Freq0;
- HT_FREQUENCIES Freq1;
- BOOLEAN Temp1;
- BOOLEAN Temp2;
- UINT32 NbFreq0;
- UINT32 NbFreq1;
- UINT32 NbDivisor0;
- UINT32 NbDivisor1;
-
- // Errors: extra type features, value range checks.
- // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
- ASSERT (((Entry->HtPhyFreqEntry.HtPhyEntry.TypeFeats.HtPhyLinkValue & ~(HTPHY_LINKTYPE_ALL)) == 0) &&
- (Entry->HtPhyFreqEntry.HtPhyEntry.Address < HTPHY_REGISTER_MAX));
-
- IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus);
- GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus);
- GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
- GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader);
- Link = 0;
- while (FamilySpecificServices->NextLinkHasHtPhyFeats (
- FamilySpecificServices,
- &CapabilitySet,
- &Link,
- &Entry->HtPhyFreqEntry.HtPhyEntry.TypeFeats,
- &MatchedSublink1,
- &Freq0,
- &Freq1,
- StdHeader)) {
- // Check the HT Frequency for match to the range.
- if (IsEitherCountInRange (
- (MatchedSublink1 ? Freq1 : Freq0),
- (MatchedSublink1 ? Freq1 : Freq0),
- Entry->HtPhyFreqEntry.HtFreqCounts.HtFreqCountRanges)) {
- // Get the NB Frequency, convert to 100's of MHz, then convert to equivalent HT encoding. This supports
- // NB frequencies from 800 MHz to 2600 MHz, which is currently greater than any processor supports.
- OptionMultiSocketConfiguration.GetSystemNbPstateSettings (
- (UINT32) 0,
- PlatformConfig,
- &NbFreq0,
- &NbDivisor0,
- &Temp1,
- &Temp2,
- StdHeader);
-
- if (OptionMultiSocketConfiguration.GetSystemNbPstateSettings (
- (UINT32) 1,
- PlatformConfig,
- &NbFreq1,
- &NbDivisor1,
- &Temp1,
- &Temp2,
- StdHeader)) {
- ASSERT (NbDivisor1 != 0);
- NbFreq1 = (NbFreq1 / NbDivisor1);
- NbFreq1 = (NbFreq1 / 100);
- NbFreq1 = (NbFreq1 / 2) + 1;
- } else {
- NbFreq1 = 0;
- }
-
- ASSERT (NbDivisor0 != 0);
- NbFreq0 = (NbFreq0 / NbDivisor0);
- NbFreq0 = (NbFreq0 / 100);
- NbFreq0 = (NbFreq0 / 2) + 1;
- if (IsEitherCountInRange (NbFreq0, NbFreq1, Entry->HtPhyFreqEntry.NbFreqCounts.HtFreqCountRanges)) {
- FamilySpecificServices->SetHtPhyRegister (
- FamilySpecificServices,
- &Entry->HtPhyFreqEntry.HtPhyEntry,
- CapabilitySet,
- Link,
- StdHeader);
- }
- }
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Perform the Performance Profile PCI Register Entry.
- *
- * @TableEntryTypeMethod{::ProfileFixup}.
- *
- * Check the entry's performance profile features to the platform's and do the
- * PCI register entry if they match.
- *
- * @param[in] Entry The Performance Profile register entry to perform
- * @param[in] PlatformConfig Config handle for platform specific information
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-SetRegisterForPerformanceProfileEntry (
- IN TABLE_ENTRY_DATA *Entry,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- PERFORMANCE_PROFILE_FEATS PlatformProfile;
- TABLE_ENTRY_DATA PciEntry;
-
- // Errors: Possible values in unused entry space, extra type features, value range checks.
- // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
- ASSERT (((Entry->TokenPciEntry.TypeFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0) &&
- (Entry->InitialValues[4] == 0));
-
- GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader);
- if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue,
- Entry->FixupEntry.TypeFeats.PerformanceProfileValue)) {
- LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader);
- PciEntry.PciEntry = Entry->FixupEntry.PciEntry;
- SetRegisterForPciEntry (&PciEntry, PlatformConfig, StdHeader);
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Perform the HT Phy Performance Profile Register Entry.
- *
- * @TableEntryTypeMethod{::HtPhyProfileRegister}.
- *
- * @param[in] Entry The HT Phy register entry to perform
- * @param[in] PlatformConfig Config handle for platform specific information
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-SetRegisterForHtPhyProfileEntry (
- IN TABLE_ENTRY_DATA *Entry,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- PERFORMANCE_PROFILE_FEATS PlatformProfile;
- TABLE_ENTRY_DATA HtPhyEntry;
-
- // Errors: Possible values in unused entry space, extra type features, value range checks.
- // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
- ASSERT (((Entry->HtPhyProfileEntry.TypeFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0) &&
- (Entry->InitialValues[5] == 0));
-
- GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader);
- if (DoesEntryTypeSpecificInfoMatch (
- PlatformProfile.PerformanceProfileValue,
- Entry->HtPhyProfileEntry.TypeFeats.PerformanceProfileValue)) {
- LibAmdMemFill (&HtPhyEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader);
- HtPhyEntry.HtPhyEntry = Entry->HtPhyProfileEntry.HtPhyEntry;
- SetRegisterForHtPhyEntry (&HtPhyEntry, PlatformConfig, StdHeader);
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Perform the HT Host PCI Register Entry.
- *
- * @TableEntryTypeMethod{::HtHostPciRegister}.
- *
- * Make the current core's PCI address with the function and register for the entry.
- * For all HT links, check the link's feature set for a match to the entry.
- * Read - Modify - Write the PCI register, clearing masked bits, and setting the data bits.
- *
- * @param[in] Entry The PCI register entry to perform
- * @param[in] PlatformConfig Config handle for platform specific information
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-SetRegisterForHtHostEntry (
- IN TABLE_ENTRY_DATA *Entry,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINTN Link;
- UINT32 MySocket;
- UINT32 MyModule;
- AGESA_STATUS IgnoredStatus;
- UINT32 Ignored;
- CPU_LOGICAL_ID CpuFamilyRevision;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
- PCI_ADDR CapabilitySet;
- PCI_ADDR PciAddress;
- HT_HOST_FEATS HtHostFeats;
- UINT32 RegisterData;
-
- // Errors: Possible values in unused entry space, extra type features, value range checks.
- // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
- ASSERT ((Entry->InitialValues[4] == 0) &&
- ((Entry->HtHostEntry.TypeFeats.HtHostValue & ~((HT_HOST_FEATURES_ALL) | (HT_HOST_AND))) == 0) &&
- (Entry->HtHostEntry.Address.Address.Register < HT_LINK_HOST_CAP_MAX));
-
- HtHostFeats.HtHostValue = 0;
- IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus);
- GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus);
- GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
- GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader);
- Link = 0;
- while (FamilySpecificServices->GetNextHtLinkFeatures (FamilySpecificServices, &Link, &CapabilitySet, &HtHostFeats, StdHeader)) {
- if (DoesEntryTypeSpecificInfoMatch (HtHostFeats.HtHostValue, Entry->HtHostEntry.TypeFeats.HtHostValue)) {
- // Do the HT Host PCI register update.
- PciAddress = CapabilitySet;
- PciAddress.Address.Register += Entry->HtHostEntry.Address.Address.Register;
- LibAmdPciRead (AccessWidth32, PciAddress, &RegisterData, StdHeader);
- RegisterData = RegisterData & (~(Entry->HtHostEntry.Mask));
- RegisterData = RegisterData | Entry->HtHostEntry.Data;
- LibAmdPciWrite (AccessWidth32, PciAddress, &RegisterData, StdHeader);
- }
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Perform the HT Host Performance PCI Register Entry.
- *
- * @TableEntryTypeMethod{::HtHostPerfPciRegister}.
- *
- * Make the current core's PCI address with the function and register for the entry.
- * For all HT links, check the link's feature set for a match to the entry.
- * Read - Modify - Write the PCI register, clearing masked bits, and setting the data bits.
- *
- * @param[in] Entry The PCI register entry to perform
- * @param[in] PlatformConfig Config handle for platform specific information
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-SetRegisterForHtHostPerfEntry (
- IN TABLE_ENTRY_DATA *Entry,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- PERFORMANCE_PROFILE_FEATS PlatformProfile;
- TABLE_ENTRY_DATA HtHostPciTypeEntryData;
-
- // Errors: Possible values in unused entry space, extra type features, value range checks.
- // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
- ASSERT ((Entry->InitialValues[5] == 0) &&
- ((Entry->HtHostEntry.TypeFeats.HtHostValue & ~((HT_HOST_FEATURES_ALL) | (HT_HOST_AND))) == 0) &&
- (Entry->HtHostEntry.Address.Address.Register < HT_LINK_HOST_CAP_MAX));
-
- // Check for any performance profile features.
- GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader);
- if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue,
- Entry->HtHostPerfEntry.PerformanceFeats.PerformanceProfileValue)) {
- // Perform HT Host entry process.
- LibAmdMemFill (&HtHostPciTypeEntryData, 0, sizeof (TABLE_ENTRY_DATA), StdHeader);
- HtHostPciTypeEntryData.HtHostEntry = Entry->HtHostPerfEntry.HtHostEntry;
- SetRegisterForHtHostEntry (&HtHostPciTypeEntryData, PlatformConfig, StdHeader);
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Set the HT Link Token Count registers.
- *
- * @TableEntryTypeMethod{::HtTokenPciRegister}.
- *
- * Make the current core's PCI address with the function and register for the entry.
- * Check the performance profile features.
- * For all HT links, check the link's feature set for a match to the entry.
- * Read - Modify - Write the PCI register, clearing masked bits, and setting the data bits.
- *
- * @param[in] Entry The Link Token register entry to perform
- * @param[in] PlatformConfig Config handle for platform specific information
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-SetRegisterForHtLinkTokenEntry (
- IN TABLE_ENTRY_DATA *Entry,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINTN Link;
- UINT32 MySocket;
- UINT32 MyModule;
- AGESA_STATUS IgnoredStatus;
- UINT32 Ignored;
- CPU_LOGICAL_ID CpuFamilyRevision;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
- PCI_ADDR CapabilitySet;
- HT_HOST_FEATS HtHostFeats;
- PERFORMANCE_PROFILE_FEATS PlatformProfile;
- UINTN ProcessorCount;
- UINTN SystemDegree;
- UINT32 RegisterData;
- PCI_ADDR PciAddress;
-
- // Errors: Possible values in unused entry space, extra type features, value range checks.
- // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
- ASSERT (((Entry->HtTokenEntry.LinkFeats.HtHostValue & ~((HT_HOST_FEATURES_ALL) | (HT_HOST_AND))) == 0) &&
- ((Entry->HtTokenEntry.PerformanceFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0) &&
- (Entry->HtTokenEntry.Mask != 0));
-
- HtHostFeats.HtHostValue = 0;
- IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus);
- GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus);
- GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
- GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader);
-
- // Check if the actual processor count and SystemDegree are in either range.
- ProcessorCount = GetNumberOfProcessors (StdHeader);
- SystemDegree = GetSystemDegree (StdHeader);
- if (IsEitherCountInRange (ProcessorCount, SystemDegree, Entry->HtTokenEntry.ConnectivityCount.ConnectivityCountRanges)) {
- // Check for any performance profile features.
- GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader);
- if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue,
- Entry->HtTokenEntry.PerformanceFeats.PerformanceProfileValue)) {
- // Check the link features.
- Link = 0;
- while (FamilySpecificServices->GetNextHtLinkFeatures (FamilySpecificServices, &Link, &CapabilitySet, &HtHostFeats, StdHeader)) {
- if (DoesEntryTypeSpecificInfoMatch (HtHostFeats.HtHostValue, Entry->HtTokenEntry.LinkFeats.HtHostValue)) {
- // Do the HT Host PCI register update. Token register are four registers, sublink 0 and 1 share fields.
- // If sublink 0 is unconnected, we should let sublink 1 match. If the links are ganged, of course only sublink 0 matches.
- // If the links are unganged and both connected, the BKDG settings are for both coherent.
- PciAddress = CapabilitySet;
- PciAddress.Address.Register = Entry->HtTokenEntry.Address.Address.Register +
- ((Link > 3) ? (((UINT32)Link - 4) * 4) : ((UINT32)Link * 4));
- PciAddress.Address.Function = Entry->HtTokenEntry.Address.Address.Function;
- LibAmdPciRead (AccessWidth32, PciAddress, &RegisterData, StdHeader);
- RegisterData = RegisterData & (~(Entry->HtTokenEntry.Mask));
- RegisterData = RegisterData | Entry->HtTokenEntry.Data;
- LibAmdPciWrite (AccessWidth32, PciAddress, &RegisterData, StdHeader);
- }
- }
- }
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Perform the Core Counts Performance PCI Register Entry.
- *
- * @TableEntryTypeMethod{::CoreCountsPciRegister}.
- *
- * Check the performance profile.
- * Check the actual core count to the range pair given, and apply if matched.
- *
- * @param[in] Entry The PCI register entry to perform
- * @param[in] PlatformConfig Config handle for platform specific information
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-SetRegisterForCoreCountsPerformanceEntry (
- IN TABLE_ENTRY_DATA *Entry,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- PERFORMANCE_PROFILE_FEATS PlatformProfile;
- UINTN ActualCoreCount;
- TABLE_ENTRY_DATA PciEntry;
-
- // Errors: Possible values in unused entry space, extra type features, value range checks.
- // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
- ASSERT (((Entry->CoreCountEntry.TypeFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0));
-
- GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader);
- if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue, Entry->CoreCountEntry.TypeFeats.PerformanceProfileValue)) {
- ActualCoreCount = GetActiveCoresInCurrentModule (StdHeader);
- // Check if the actual core count is in either range.
- if (IsEitherCountInRange (ActualCoreCount, ActualCoreCount, Entry->CoreCountEntry.CoreCounts.CoreRanges)) {
- LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader);
- PciEntry.PciEntry = Entry->CoreCountEntry.PciEntry;
- SetRegisterForPciEntry (&PciEntry, PlatformConfig, StdHeader);
- }
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Perform the Processor Counts PCI Register Entry.
- *
- * @TableEntryTypeMethod{::ProcCountsPciRegister}.
- *
- * Check the performance profile.
- * Check the actual processor count (not node count!) to the range pair given, and apply if matched.
- *
- * @param[in] Entry The PCI register entry to perform
- * @param[in] PlatformConfig Config handle for platform specific information
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-SetRegisterForProcessorCountsEntry (
- IN TABLE_ENTRY_DATA *Entry,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- PERFORMANCE_PROFILE_FEATS PlatformProfile;
- UINTN ProcessorCount;
- TABLE_ENTRY_DATA PciEntry;
-
- // Errors: Possible values in unused entry space, extra type features, value range checks.
- // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
- ASSERT (((Entry->ProcCountEntry.TypeFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0));
-
- GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader);
- if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue, Entry->ProcCountEntry.TypeFeats.PerformanceProfileValue)) {
- ProcessorCount = GetNumberOfProcessors (StdHeader);
- // Check if the actual processor count is in either range.
- if (IsEitherCountInRange (ProcessorCount, ProcessorCount, Entry->ProcCountEntry.ProcessorCounts.ProcessorCountRanges)) {
- LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader);
- PciEntry.PciEntry = Entry->ProcCountEntry.PciEntry;
- SetRegisterForPciEntry (&PciEntry, PlatformConfig, StdHeader);
- }
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Perform the Compute Unit Counts PCI Register Entry.
- *
- * @TableEntryTypeMethod{::CompUnitCountsPciRegister}.
- *
- * Check the entry's performance profile features and the compute unit count
- * to the platform's and do the PCI register entry if they match.
- *
- * @param[in] Entry The PCI register entry to perform
- * @param[in] PlatformConfig Config handle for platform specific information
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-SetRegisterForComputeUnitCountsEntry (
- IN TABLE_ENTRY_DATA *Entry,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- PERFORMANCE_PROFILE_FEATS PlatformProfile;
- UINTN ComputeUnitCount;
- TABLE_ENTRY_DATA PciEntry;
-
- // Errors: Possible values in unused entry space, extra type features, value range checks.
- // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
- ASSERT (((Entry->CompUnitCountEntry.TypeFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0));
-
- GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader);
- if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue, Entry->CompUnitCountEntry.TypeFeats.PerformanceProfileValue)) {
- ComputeUnitCount = GetNumberOfCompUnitsInCurrentModule (StdHeader);
- // Check if the actual compute unit count is in either range.
- if (IsEitherCountInRange (ComputeUnitCount, ComputeUnitCount, Entry->CompUnitCountEntry.ComputeUnitCounts.ComputeUnitRanges)) {
- LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader);
- PciEntry.PciEntry = Entry->ProcCountEntry.PciEntry;
- SetRegisterForPciEntry (&PciEntry, PlatformConfig, StdHeader);
- }
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Perform the Processor Token Counts PCI Register Entry.
- *
- * @TableEntryTypeMethod{::TokenPciRegister}.
- *
- * The table criteria then translate as:
- * - 2 Socket, half populated == Degree 1
- * - 4 Socket, half populated == Degree 2
- * - 2 Socket, fully populated == Degree 3
- * - 4 Socket, fully populated == Degree > 3. (4 or 5 if 3P, 6 if 4P)
- *
- * @param[in] Entry The PCI register entry to perform
- * @param[in] PlatformConfig Config handle for platform specific information
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-SetRegisterForTokenPciEntry (
- IN TABLE_ENTRY_DATA *Entry,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- PERFORMANCE_PROFILE_FEATS PlatformProfile;
- UINTN SystemDegree;
- TABLE_ENTRY_DATA PciEntry;
-
- // Errors: Possible values in unused entry space, extra type features, value range checks.
- // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
- ASSERT (((Entry->TokenPciEntry.TypeFeats.PerformanceProfileValue & ~((PERFORMANCE_PROFILE_ALL) | (PERFORMANCE_AND))) == 0));
-
- GetPerformanceFeatures (&PlatformProfile, PlatformConfig, StdHeader);
- if (DoesEntryTypeSpecificInfoMatch (PlatformProfile.PerformanceProfileValue, Entry->TokenPciEntry.TypeFeats.PerformanceProfileValue)) {
- SystemDegree = GetSystemDegree (StdHeader);
- // Check if the system degree is in the range.
- if (IsEitherCountInRange (SystemDegree, SystemDegree, Entry->TokenPciEntry.ConnectivityCount.ConnectivityCountRanges)) {
- LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader);
- PciEntry.PciEntry = Entry->TokenPciEntry.PciEntry;
- SetRegisterForPciEntry (&PciEntry, PlatformConfig, StdHeader);
- }
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Perform the HT Link Feature PCI Register Entry.
- *
- * @TableEntryTypeMethod{::HtFeatPciRegister}.
- *
- * Set a single field (that is, the register field is not in HT Host capability or a
- * set of per link registers) in PCI config, based on HT link features and package type.
- * This code is used for two cases: single link processors and multilink processors.
- * For single link cases, the link will be tested for a match to the HT Features for the link.
- * For multilink processors, the entry will match if @b any link is found which matches.
- * For example, a setting can be applied based on coherent HT3 by matching coherent AND HT3.
- *
- * Make the core's PCI address. Check the package type (currently more important to the single link case),
- * and if matching, iterate through all links checking for an HT feature match until found or exhausted.
- * If a match was found, pass the PCI entry data to the implementer for writing for the current core.
- *
- * @param[in] Entry The PCI register entry to perform
- * @param[in] PlatformConfig Config handle for platform specific information
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-SetRegisterForHtFeaturePciEntry (
- IN TABLE_ENTRY_DATA *Entry,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINTN Link;
- UINT32 MySocket;
- UINT32 MyModule;
- AGESA_STATUS IgnoredStatus;
- UINT32 Ignored;
- CPU_LOGICAL_ID CpuFamilyRevision;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
- PCI_ADDR CapabilitySet;
- HT_HOST_FEATS HtHostFeats;
- UINT32 ProcessorPackageType;
- BOOLEAN IsMatch;
- TABLE_ENTRY_DATA PciEntry;
-
- // Errors: Possible values in unused entry space, extra type features, value range checks.
- // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
- ASSERT ((Entry->HtFeatPciEntry.PciEntry.Mask != 0) &&
- ((Entry->HtFeatPciEntry.LinkFeats.HtHostValue & ~((HT_HOST_FEATURES_ALL) | (HT_HOST_AND))) == 0));
-
- HtHostFeats.HtHostValue = 0;
- LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader);
- PciEntry.PciEntry = Entry->HtFeatPciEntry.PciEntry;
- IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus);
- GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus);
- GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
- GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader);
-
- ASSERT ((Entry->HtFeatPciEntry.PackageType.PackageTypeValue & ~(PACKAGE_TYPE_ALL)) == 0);
-
- ProcessorPackageType = LibAmdGetPackageType (StdHeader);
- if (DoesEntryTypeSpecificInfoMatch (ProcessorPackageType, Entry->HtFeatPciEntry.PackageType.PackageTypeValue)) {
- IsMatch = FALSE;
- while (FamilySpecificServices->GetNextHtLinkFeatures (FamilySpecificServices, &Link, &CapabilitySet, &HtHostFeats, StdHeader)) {
- if (DoesEntryTypeSpecificInfoMatch (HtHostFeats.HtHostValue, Entry->HtFeatPciEntry.LinkFeats.HtHostValue)) {
- IsMatch = TRUE;
- break;
- }
- }
- if (IsMatch) {
- // Do the PCI register update.
- SetRegisterForPciEntry (&PciEntry, PlatformConfig, StdHeader);
- }
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Perform the HT Link PCI Register Entry.
- *
- * @TableEntryTypeMethod{::HtLinkPciRegister}.
- *
- * Make the current core's PCI address with the function and register for the entry.
- * Registers are processed for match per link, assuming sequential PCI address per link.
- * Read - Modify - Write each matching link's PCI register, clearing masked bits, and setting the data bits.
- *
- * @param[in] Entry The PCI register entry to perform
- * @param[in] PlatformConfig Config handle for platform specific information
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-SetRegisterForHtLinkPciEntry (
- IN TABLE_ENTRY_DATA *Entry,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINTN Link;
- UINT32 MySocket;
- UINT32 MyModule;
- AGESA_STATUS IgnoredStatus;
- UINT32 Ignored;
- CPU_LOGICAL_ID CpuFamilyRevision;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
- PCI_ADDR CapabilitySet;
- HT_HOST_FEATS HtHostFeats;
- TABLE_ENTRY_DATA PciEntry;
-
- // Errors: Possible values in unused entry space, extra type features, value range checks.
- // Check that the entry type is correct and the actual supplied entry data is appropriate for that entry.
- ASSERT ((Entry->HtLinkPciEntry.PciEntry.Mask != 0) &&
- ((Entry->HtLinkPciEntry.LinkFeats.HtHostValue & ~((HT_HOST_FEATURES_ALL) | (HT_HOST_AND))) == 0));
-
- HtHostFeats.HtHostValue = 0;
- LibAmdMemFill (&PciEntry, 0, sizeof (TABLE_ENTRY_DATA), StdHeader);
- PciEntry.PciEntry = Entry->HtLinkPciEntry.PciEntry;
- IdentifyCore (StdHeader, &MySocket, &MyModule, &Ignored, &IgnoredStatus);
- GetPciAddress (StdHeader, MySocket, MyModule, &CapabilitySet, &IgnoredStatus);
- GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
- GetCpuServicesFromLogicalId (&CpuFamilyRevision, &FamilySpecificServices, StdHeader);
-
- Link = 0;
- while (FamilySpecificServices->GetNextHtLinkFeatures (FamilySpecificServices, &Link, &CapabilitySet, &HtHostFeats, StdHeader)) {
- if (DoesEntryTypeSpecificInfoMatch (HtHostFeats.HtHostValue, Entry->HtLinkPciEntry.LinkFeats.HtHostValue)) {
- // Do the update to the link's non-Host PCI register, based on the entry address.
- PciEntry.PciEntry.Address = Entry->HtLinkPciEntry.PciEntry.Address;
- PciEntry.PciEntry.Address.Address.Register = PciEntry.PciEntry.Address.Address.Register + ((UINT32)Link * 4);
- SetRegisterForPciEntry (&PciEntry, PlatformConfig, StdHeader);
- }
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- * Returns the platform features list of the currently running processor core.
- *
- * @param[out] Features The Features supported by this platform
- * @param[in] PlatformConfig Config handle for platform specific information
- * @param[in] StdHeader Header for library and services
- *
- */
-VOID
-GetPlatformFeatures (
- OUT PLATFORM_FEATS *Features,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- PCI_ADDR PciAddress;
- UINT32 CapabilityReg;
- UINT32 Link;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
- UINT32 CoreCount;
-
- // Start with none.
- Features->PlatformValue = 0;
-
- switch (PlatformConfig->PlatformProfile.PlatformControlFlowMode) {
- case Nfcm:
- Features->PlatformFeatures.PlatformNfcm = 1;
- break;
- case UmaDr:
- Features->PlatformFeatures.PlatformUma = 1;
- break;
- case UmaIfcm:
- Features->PlatformFeatures.PlatformUmaIfcm = 1;
- break;
- case Ifcm:
- Features->PlatformFeatures.PlatformIfcm = 1;
- break;
- case Iommu:
- Features->PlatformFeatures.PlatformIommu = 1;
- break;
- default:
- ASSERT (FALSE);
- }
- // Check - Single Link?
- // This is based on the implemented links on the package regardless of their
- // connection status. All processors must match the BSP, so we only check it and
- // not the current node. We don't care exactly how many links there are, as soon
- // as we find more than one we are done.
- Link = 0;
- PciAddress.AddressValue = MAKE_SBDFO (0, 0, PCI_DEV_BASE, FUNC_0, 0);
- // Until either all capabilities are done or until the desired link is found,
- // keep looking for HT Host Capabilities.
- while (Link < 2) {
- LibAmdPciFindNextCap (&PciAddress, StdHeader);
- if (PciAddress.AddressValue != ILLEGAL_SBDFO) {
- LibAmdPciRead (AccessWidth32, PciAddress, &CapabilityReg, StdHeader);
- if ((CapabilityReg & 0xE00000FF) == 0x20000008) {
- Link++;
- }
- // A capability other than an HT capability, keep looking.
- } else {
- // end of capabilities
- break;
- }
- }
- if (Link < 2) {
- Features->PlatformFeatures.PlatformSingleLink = 1;
- } else {
- Features->PlatformFeatures.PlatformMultiLink = 1;
- }
-
- // Set the legacy core count bits.
- GetActiveCoresInCurrentSocket (&CoreCount, StdHeader);
- switch (CoreCount) {
- case 1:
- Features->PlatformFeatures.PlatformSingleCore = 1;
- break;
- case 2:
- Features->PlatformFeatures.PlatformDualCore = 1;
- break;
- default:
- Features->PlatformFeatures.PlatformMultiCore = 1;
- }
-
- //
- // Get some specific platform type info, VC...etc.
- //
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
- ASSERT (FamilySpecificServices != NULL);
- FamilySpecificServices->GetPlatformTypeSpecificInfo (FamilySpecificServices, Features, StdHeader);
-
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Checks if a register table entry applies to the executing core.
- *
- * This function uses a combination of logical ID and platform features to
- * determine whether or not a register table entry applies to the executing core.
- *
- * @param[in] CoreCpuRevision The current core's logical ID
- * @param[in] EntryCpuRevision The entry's desired logical IDs
- * @param[in] PlatformFeatures The platform features
- * @param[in] EntryFeatures The entry's desired platform features
- *
- * @retval TRUE This entry should be applied
- * @retval FALSE This entry does not apply
- *
- */
-BOOLEAN
-STATIC
-DoesEntryMatchPlatform (
- IN CPU_LOGICAL_ID CoreCpuRevision,
- IN CPU_LOGICAL_ID EntryCpuRevision,
- IN PLATFORM_FEATS PlatformFeatures,
- IN PLATFORM_FEATS EntryFeatures
- )
-{
- BOOLEAN Result;
-
- Result = FALSE;
-
- if (((CoreCpuRevision.Family & EntryCpuRevision.Family) != 0) &&
- ((CoreCpuRevision.Revision & EntryCpuRevision.Revision) != 0)) {
- if (EntryFeatures.PlatformFeatures.AndPlatformFeats == 0) {
- // Match if ANY entry feats match a platform feat (an OR test)
- if ((EntryFeatures.PlatformValue & PlatformFeatures.PlatformValue) != 0) {
- Result = TRUE;
- }
- } else {
- // Match if ALL entry feats match a platform feat (an AND test)
- if ((EntryFeatures.PlatformValue & ~(AMD_PF_AND)) ==
- (EntryFeatures.PlatformValue & PlatformFeatures.PlatformValue)) {
- Result = TRUE;
- }
- }
- }
-
- return Result;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Checks register table entry type specific criteria to the platform.
- *
- * Entry Data Type implementer methods can use this generically to check their own
- * specific criteria. The method collects the actual platform characteristics and
- * provides them along with the table entry's criteria to this service.
- *
- * There are a couple considerations for any implementer method using this service.
- * The criteria value has to be representable as a UINT32. The MSB, Bit 31, has to
- * be used as a AND test request if set in the entry. (The platform value should never
- * have that bit set.)
- *
- * @param[in] PlatformTypeSpecificFeatures The platform features
- * @param[in] EntryTypeFeatures The entry's desired platform features
- *
- * @retval TRUE This entry should be applied
- * @retval FALSE This entry does not apply
- *
- */
-BOOLEAN
-DoesEntryTypeSpecificInfoMatch (
- IN UINT32 PlatformTypeSpecificFeatures,
- IN UINT32 EntryTypeFeatures
- )
-{
- BOOLEAN Result;
-
- Result = FALSE;
-
- if ((EntryTypeFeatures & BIT31) == 0) {
- // Match if ANY entry feats match a platform feat (an OR test)
- if ((EntryTypeFeatures & PlatformTypeSpecificFeatures) != 0) {
- Result = TRUE;
- }
- } else {
- // Match if ALL entry feats match a platform feat (an AND test)
- if ((EntryTypeFeatures & ~(BIT31)) == (EntryTypeFeatures & PlatformTypeSpecificFeatures)) {
- Result = TRUE;
- }
- }
- return Result;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Determine this core's Selector matches.
- *
- * @param[in] Selector Is the current core this selector type?
- * @param[in] StdHeader Config handle for library and services.
- *
- * @retval TRUE Yes, it is.
- * @retval FALSE No, it is not.
- */
-BOOLEAN
-STATIC
-IsCoreSelector (
- IN TABLE_CORE_SELECTOR Selector,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- BOOLEAN Result;
- AGESA_STATUS CalledStatus;
-
- Result = TRUE;
- ASSERT (Selector < TableCoreSelectorMax);
-
- if ((Selector == PrimaryCores) && !IsCurrentCorePrimary (StdHeader)) {
- Result = FALSE;
- }
- if ((Selector == CorePairPrimary) && !IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) {
- Result = FALSE;
- }
- if ((Selector == BscCore) && (!IsBsp (StdHeader, &CalledStatus))) {
- Result = FALSE;
- }
- return Result;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Set the registers for this core based on entries in a list of Register Tables.
- *
- * Determine the platform features and this core's logical id. Get the specific table
- * entry type implementations for the logical model, which may be either generic (the ones
- * in this file) or specific.
- *
- * Scan the tables starting the with ones for all cores and progressively narrowing the selection
- * based on this core's role (ex. primary core). For a selected table, check for each entry
- * matching the current core and platform, and call the implementer method to perform the
- * register set operation if it matches.
- *
- * @param[in] PlatformConfig Config handle for platform specific information
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-SetRegistersFromTables (
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- CPU_LOGICAL_ID CpuLogicalId;
- PLATFORM_FEATS PlatformFeatures;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
- TABLE_ENTRY_FIELDS *Entries;
- TABLE_CORE_SELECTOR Selector;
- TABLE_ENTRY_TYPE EntryType;
- REGISTER_TABLE **TableHandle;
- UINTN NumberOfEntries;
- UINTN CurrentEntryCount;
- TABLE_ENTRY_TYPE_DESCRIPTOR *TypeImplementer;
- PF_DO_TABLE_ENTRY DoTableEntry[TableEntryTypeMax];
-
- // Did you really mean to increase the size of ALL table entries??!!
- // While it is not necessarily a bug to increase the size of table entries:
- // - Is this warning a surprise? Please fix it.
- // - If expected, is this really a feature which is worth the increase? Then let other entries also use the space.
- ASSERT (sizeof (TABLE_ENTRY_DATA) == (MAX_ENTRY_TYPE_ITEMS32 * sizeof (UINT32)));
-
- PlatformFeatures.PlatformValue = 0;
- GetLogicalIdOfCurrentCore (&CpuLogicalId, StdHeader);
- GetPlatformFeatures (&PlatformFeatures, PlatformConfig, StdHeader);
- GetCpuServicesFromLogicalId (&CpuLogicalId, &FamilySpecificServices, StdHeader);
-
- // Build a non-sparse table of implementer methods, so we don't have to keep searching.
- // It is a bug to not include a descriptor for a type that is in the table (but the
- // descriptor can point to a non-assert stub).
- // Also, it is not a bug to have no register table implementations, but it is a bug to have none and call this routine.
- for (EntryType = MsrRegister; EntryType < TableEntryTypeMax; EntryType++) {
- DoTableEntry[EntryType] = (PF_DO_TABLE_ENTRY)CommonAssert;
- }
- TypeImplementer = FamilySpecificServices->TableEntryTypeDescriptors;
- ASSERT (TypeImplementer != NULL);
- while (TypeImplementer->EntryType < TableEntryTypeMax) {
- DoTableEntry[TypeImplementer->EntryType] = TypeImplementer->DoTableEntry;
- TypeImplementer++;
- }
-
- for (Selector = AllCores; Selector < TableCoreSelectorMax; Selector++) {
- if (IsCoreSelector (Selector, StdHeader)) {
- // If the current core is the selected type of core, work the table list for tables for that type of core.
- TableHandle = NULL;
- Entries = GetNextRegisterTable (FamilySpecificServices, Selector, &TableHandle, &NumberOfEntries, StdHeader);
- while (Entries != NULL) {
- for (CurrentEntryCount = 0; CurrentEntryCount < NumberOfEntries; CurrentEntryCount++, Entries++) {
- if (DoesEntryMatchPlatform (CpuLogicalId, Entries->CpuRevision, PlatformFeatures, Entries->Features)) {
- // The entry matches this config, Do It!
- // Find the implementer for this entry type and pass the entry data to it.
- ASSERT (Entries->EntryType < TableEntryTypeMax);
- DoTableEntry[Entries->EntryType] (&Entries->Entry, PlatformConfig, StdHeader);
- }
- }
- Entries = GetNextRegisterTable (FamilySpecificServices, Selector, &TableHandle, &NumberOfEntries, StdHeader);
- }
- } else {
- // Once a selector does not match the current core, quit looking.
- break;
- }
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Set the registers for this core based on entries in a list of Register Tables.
- *
- * This function acts as a wrapper for calling the SetRegistersFromTables
- * routine at AmdInitEarly.
- *
- * @param[in] FamilyServices The current Family Specific Services.
- * @param[in] EarlyParams Service parameters.
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-SetRegistersFromTablesAtEarly (
- IN CPU_SPECIFIC_SERVICES *FamilyServices,
- IN AMD_CPU_EARLY_PARAMS *EarlyParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_TESTPOINT (TpProcCpuProcessRegisterTables, StdHeader);
- SetRegistersFromTables (&EarlyParams->PlatformConfig, StdHeader);
-}
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/Table.h b/src/vendorcode/amd/agesa/Proc/CPU/Table.h
deleted file mode 100644
index 76ec4b0..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/Table.h
+++ /dev/null
@@ -1,1238 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU Register Table Related Functions
- *
- * Contains code to initialize the CPU MSRs and PCI registers with BKDG recommended values
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 38402 $ @e \$Date: 2010-09-24 02:11:44 +0800 (Fri, 24 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPU_TABLE_H_
-#define _CPU_TABLE_H_
-
-#define MAX_ENTRY_TYPE_ITEMS32 6 // The maximum number of initializer items for UINT32 entry data types.
-
-/**
- * @page regtableimpl Register Table Implementation Guide
- *
- * This register table implementation is modular and extensible, so that support code as
- * well as table data can be family specific or built out if not needed, and new types
- * of table entries can be added with low overhead. Because many aspects are now generic,
- * there can be common implementations for CPU revision and platform feature matching and for
- * finding and iterating tables.
- *
- * @par Adding a new table entry type.
- *
- * To add a new table entry type follow these steps.
- * <ul>
- * <li> Add a member to the enum TABLE_ENTRY_TYPE which is a descriptive name of the entry's purpose
- * or distinct characteristics.
- *
- * <li> Create an entry data struct with the customized data needed. For example, custom register designations,
- * data and mask sizes, or feature comparisons. Name your struct by adding "_" and upper-casing the enum name
- * and adding "_TYPE_ENTRY_DATA" at the end.
- *
- * <li> Add the entry data type as a member of the TABLE_ENTRY_DATA union. Be aware of the size of your
- * entry data struct; all table entries in all tables will share any size increase you introduce!
- *
- * <li> If your data entry contains any member types except for UINT32, you can't use the generic first union member
- * for the initializers that make up the actual tables (it's just UINT32's). The generic MSR entry is
- * an example. Follow the steps below:
- *
- * <ul>
- * <li> Make a union which has your entry data type as the first member. Use TABLE_ENTRY_DATA as the
- * second member. Name this with your register followed by "_DATA_INITIALIZER".
- *
- * <li> Make a copy of TABLE_ENTRY_FIELDS, and rename it your register "_TYPE_ENTRY_INITIALIZER". Rename
- * the TABLE_ENTRY_DATA member of that struct to have the type you created in the previous step.
- * This type can be used to declare an array of entries and make a register table in some family specific
- * file.
- * </ul>
- *
- * <li> Add the descriptor that will link table entries of your data type to an implementation for it.
- * <ul>
- * <li> Find the options file which instantiates the CPU_SPECIFIC_SERVICES for each logical model that will
- * support the new entry type.
- *
- * <li> From there find the instantiation of its TABLE_ENTRY_TYPE_DESCRIPTOR. Add a descriptor to the
- * to the list for your new type. Provide the name of a function which will implement the
- * entry data. The function name should reflect that it implements the action for the entry type.
- * The function must be an instance of F_DO_TABLE_ENTRY.
- * </ul>
- *
- * <li> Implement the function for your entry type data. (If parts of it are family specific add methods to
- * CPU_SPECIFIC_SERVICES for that and implement them for each family or model required.) @n
- * The definition of the function must conform to F_DO_TABLE_ENTRY.
- * In the function preamble, include a cross reference to the entry enum:
- * @code
- * *
- * * @TableEntryTypeMethod{::MyRegister}
- * *
- * @endcode
- *
- * </ul>
- *
- * @par Adding a new Register Table
- *
- * To add a new register table for a logical CPU model follow the steps below.
- *
- * <ul>
- * <li> Find the options file which instantiates the CPU_SPECIFIC_SERVICES for the logical model that
- * should include the table.
- *
- * <li> From there find the instantiation of its REGISTER_TABLE list. Add the name of the new register table.
- * </ul>
- *
- */
-
-/*------------------------------------------------------------------------------------------*/
-/*
- * Define the supported table entries.
- */
-/*------------------------------------------------------------------------------------------*/
-
-/**
- * These are the available types of table entries.
- *
- * Each type corresponds to:
- * - a semantics for the type specific data, for example semantics for a Register value,
- * Data value, and Mask value.
- * - optionally, including a method for type specific matching criteria
- * - a method for writing the desired update to the hardware.
- *
- * All types share in common a method to match CPU Family and Model and a method to match
- * platform feature set.
- *
- */
-typedef enum {
- MsrRegister, ///< Processor MSR registers.
- PciRegister, ///< Processor Config Space registers.
- FamSpecificWorkaround, ///< Processor Family Specific Workarounds which are @b not practical using the other types.
- HtPhyRegister, ///< Processor HT Phy registers.
- HtPhyRangeRegister, ///< Processor HT Phy range of contiguous registers (ex. 40h:48h).
- DeemphasisRegister, ///< Processor Deemphasis register (HT Phy special case).
- HtPhyFreqRegister, ///< Processor Frequency dependent HT Phy settings.
- ProfileFixup, ///< Processor Performance Profile fixups to PCI Config Registers.
- HtHostPciRegister, ///< Processor Ht Host capability registers (PCI Config).
- HtHostPerfPciRegister, ///< Processor Ht Host capability registers which depend on performance features.
- HtTokenPciRegister, ///< Processor Ht Link Token count registers.
- CoreCountsPciRegister, ///< Processor PCI Config Registers which depend on core counts.
- ProcCountsPciRegister, ///< Processor PCI Config Registers which depend on processor counts.
- CompUnitCountsPciRegister, ///< Processor PCI Config Registers which depend on compute unit counts.
- TokenPciRegister, ///< Processor northbridge Token Count register which may be dependent on connectivity.
- HtFeatPciRegister, ///< Processor HT Link feature dependant PCI Config Registers.
- HtPhyProfileRegister, ///< Processor HT Phy registers which depend on performance features.
- HtLinkPciRegister, ///< Processor HT Link registers (one per link) not part of HT Host capability.
- TableEntryTypeMax ///< Not a valid entry type, use for limit checking.
-} TABLE_ENTRY_TYPE;
-
-/*------------------------------------------------------------------------------------------*/
-/*
- * Useful types and defines: Selectors, Platform Features, and type specific features.
- */
-/*------------------------------------------------------------------------------------------*/
-
-/**
- * Select tables for the current core.
- *
- * This allows more efficient register table processing, by allowing cores to skip
- * redundantly setting PCI registers, for example. This feature is not intended to
- * be relied on for function: it is valid to have a single register table with all settings
- * processed by every core; it's just slower.
- *
- */
-typedef enum {
- AllCores, ///< Select only tables which apply to all cores.
- CorePairPrimary, ///< Select tables which apply to the primary core of a compute unit (SharedC, SharedNc).
- PrimaryCores, ///< Select tables which apply to primary cores.
- BscCore, ///< Select tables which apply to the boot core.
- TableCoreSelectorMax ///< Not a valid selector, use for limit checking.
-} TABLE_CORE_SELECTOR;
-
-// Initializer bit pattern values for platform features.
-// Keep in synch with the PLATFORM_FEATURES struct!
-
-// The 5 control flow modes.
-#define AMD_PF_NFCM BIT0
-#define AMD_PF_UMA BIT1 // UMA_DR
-#define AMD_PF_UMA_IFCM BIT2
-#define AMD_PF_IFCM BIT3
-#define AMD_PF_IOMMU BIT4
-// Degree of HT connectivity possible.
-#define AMD_PF_SINGLE_LINK BIT5
-#define AMD_PF_MULTI_LINK BIT6
-// For some legacy MSRs, define a couple core count bits. Do not continue adding
-// core counts to the platform feats, if you need more than this design a table entry type.
-// Here, provide exactly 1, exactly 2, or anything else.
-#define AMD_PF_SINGLE_CORE BIT7
-#define AMD_PF_DUAL_CORE BIT8
-#define AMD_PF_MULTI_CORE BIT9
-
-// Not a platform type, but treat all others as AND
-#define AMD_PF_AND BIT31
-
-#define AMD_PF_ALL (AMD_PF_NFCM | \
- AMD_PF_UMA | \
- AMD_PF_UMA_IFCM | \
- AMD_PF_IFCM | \
- AMD_PF_IOMMU | \
- AMD_PF_SINGLE_LINK | \
- AMD_PF_MULTI_LINK | \
- AMD_PF_SINGLE_CORE | \
- AMD_PF_DUAL_CORE | \
- AMD_PF_MULTI_CORE)
-// Do not include AMD_PF_AND in AMD_PF_ALL !
-
-/**
- * The current platform features.
- *
- * Keep this in sync with defines above that are used in the initializers!
- *
- * The comments with the bit number are useful for the computing the reserved member size, but
- * do not write code that assumes you know what bit number one of these members is.
- *
- * These platform features are standard for all logical families and models.
- */
-typedef struct {
- UINT32 PlatformNfcm:1; ///< BIT_0 Normal Flow Control Mode.
- UINT32 PlatformUma:1; ///< BIT_1 UMA (Display Refresh) Flow Control.
- UINT32 PlatformUmaIfcm:1; ///< BIT_2 UMA using Isochronous Flow Control.
- UINT32 PlatformIfcm:1; ///< BIT_3 Isochronous Flow Control Mode (not UMA).
- UINT32 PlatformIommu:1; ///< BIT_4 IOMMU (a special case Isochronous mode).
- UINT32 PlatformSingleLink:1; ///< BIT_5 The processor is in a package which implements only a single HT Link.
- UINT32 PlatformMultiLink:1; ///< BIT_6 The processor is in a package which implements more than one HT Link.
- UINT32 PlatformSingleCore:1; ///< BIT_7 Single Core processor, for legacy entries.
- UINT32 PlatformDualCore:1; ///< BIT_8 Dual Core processor, for legacy entries.
- UINT32 PlatformMultiCore:1; ///< BIT_9 More than dual Core processor, for legacy entries.
- UINT32 :(30 - 9); ///< The possibilities are (not quite) endless.
- UINT32 AndPlatformFeats:1; ///< BIT_31
-} PLATFORM_FEATURES;
-
-/**
- * Platform Features
- */
-typedef union {
- UINT32 PlatformValue; ///< Describe Platform Features in UINT32.
- ///< This one goes first, because then initializers use it automatically for the union.
- PLATFORM_FEATURES PlatformFeatures; ///< Describe Platform Features in structure
-} PLATFORM_FEATS;
-
-// Sublink Types are defined so they can match each attribute against either
-// sublink zero or one. The table entry must contain the correct matching
-// values based on the register. This is available in the BKDG, for each register
-// which sublink it controls. If the register is independent of sublink, OR values
-// together or use HT_LINKTYPE_ALL to match if either sublink matches (ex. E0 - E5).
-// Sublink 0 types, bits 0 thru 14
-#define HTPHY_LINKTYPE_SL0_HT3 BIT0
-#define HTPHY_LINKTYPE_SL0_HT1 BIT1
-#define HTPHY_LINKTYPE_SL0_COHERENT BIT2
-#define HTPHY_LINKTYPE_SL0_NONCOHERENT BIT3
-#define HTPHY_LINKTYPE_SL0_LINK0 BIT4
-#define HTPHY_LINKTYPE_SL0_LINK1 BIT5
-#define HTPHY_LINKTYPE_SL0_LINK2 BIT6
-#define HTPHY_LINKTYPE_SL0_LINK3 BIT7
-// bit 15 is reserved
-
-// SubLink 1 types, bits 16 thru 30
-#define HTPHY_LINKTYPE_SL1_HT3 BIT16
-#define HTPHY_LINKTYPE_SL1_HT1 BIT17
-#define HTPHY_LINKTYPE_SL1_COHERENT BIT18
-#define HTPHY_LINKTYPE_SL1_NONCOHERENT BIT19
-#define HTPHY_LINKTYPE_SL1_LINK4 BIT20
-#define HTPHY_LINKTYPE_SL1_LINK5 BIT21
-#define HTPHY_LINKTYPE_SL1_LINK6 BIT22
-#define HTPHY_LINKTYPE_SL1_LINK7 BIT23
-// bit 31 is reserved
-
-#define HTPHY_LINKTYPE_SL0_ALL (HTPHY_LINKTYPE_SL0_HT3 | \
- HTPHY_LINKTYPE_SL0_HT1 | \
- HTPHY_LINKTYPE_SL0_COHERENT | \
- HTPHY_LINKTYPE_SL0_NONCOHERENT | \
- HTPHY_LINKTYPE_SL0_LINK0 | \
- HTPHY_LINKTYPE_SL0_LINK1 | \
- HTPHY_LINKTYPE_SL0_LINK2 | \
- HTPHY_LINKTYPE_SL0_LINK3)
-#define HTPHY_LINKTYPE_SL1_ALL (HTPHY_LINKTYPE_SL1_HT3 | \
- HTPHY_LINKTYPE_SL1_HT1 | \
- HTPHY_LINKTYPE_SL1_COHERENT | \
- HTPHY_LINKTYPE_SL1_NONCOHERENT | \
- HTPHY_LINKTYPE_SL1_LINK4 | \
- HTPHY_LINKTYPE_SL1_LINK5 | \
- HTPHY_LINKTYPE_SL1_LINK6 | \
- HTPHY_LINKTYPE_SL1_LINK7)
-#define HTPHY_LINKTYPE_ALL (HTPHY_LINKTYPE_SL0_ALL | HTPHY_LINKTYPE_SL1_ALL)
-
-#define HTPHY_REGISTER_MAX 0x0000FFFFul
-/**
- * HT PHY Link Features
- */
-typedef struct {
- UINT32 HtPhySL0Ht3:1; ///< Ht Phy Sub-link 0 Ht3
- UINT32 HtPhySL0Ht1:1; ///< Ht Phy Sub-link 0 Ht1
- UINT32 HtPhySL0Coh:1; ///< Ht Phy Sub-link 0 Coherent
- UINT32 HtPhySL0NonCoh:1; ///< Ht Phy Sub-link 0 NonCoherent
- UINT32 HtPhySL0Link0:1; ///< Ht Phy Sub-link 0 specifically for node link 0.
- UINT32 HtPhySL0Link1:1; ///< Ht Phy Sub-link 0 specifically for node link 1.
- UINT32 HtPhySL0Link2:1; ///< Ht Phy Sub-link 0 specifically for node link 2.
- UINT32 HtPhySL0Link3:1; ///< Ht Phy Sub-link 0 specifically for node link 3.
- UINT32 :(15 - 7); ///< Ht Phy Sub-link 0 Pad
- UINT32 HtPhySL1Ht3:1; ///< Ht Phy Sub-link 1 Ht3
- UINT32 HtPhySL1Ht1:1; ///< Ht Phy Sub-link 1 Ht1
- UINT32 HtPhySL1Coh:1; ///< Ht Phy Sub-link 1 Coherent
- UINT32 HtPhySL1NonCoh:1; ///< Ht Phy Sub-link 1 NonCoherent
- UINT32 HtPhySL1Link4:1; ///< Ht Phy Sub-link 1 specifically for node link 4.
- UINT32 HtPhySL1Link5:1; ///< Ht Phy Sub-link 1 specifically for node link 5.
- UINT32 HtPhySL1Link6:1; ///< Ht Phy Sub-link 1 specifically for node link 6.
- UINT32 HtPhySL1Link7:1; ///< Ht Phy Sub-link 1 specifically for node link 7.
- UINT32 :(31 - 23); ///< Ht Phy Sub-link 1 Pad
-} HT_PHY_LINK_FEATURES;
-
-/**
- * Ht Phy Link Features
- */
-typedef union {
- UINT32 HtPhyLinkValue; ///< Describe HY Phy Features in UINT32.
- ///< This one goes first, because then initializers use it automatically for the union.
- HT_PHY_LINK_FEATURES HtPhyLinkFeatures; ///< Describe HT Phy Features in structure.
-} HT_PHY_LINK_FEATS;
-
-// DB Level for initializing Deemphasis
-// This must be in sync with DEEMPHASIS_FEATURES and PLATFORM_DEEMPHASIS_LEVEL (agesa.h)
-#define DEEMPHASIS_LEVEL_NONE BIT0
-#define DEEMPHASIS_LEVEL__3 BIT1
-#define DEEMPHASIS_LEVEL__6 BIT2
-#define DEEMPHASIS_LEVEL__8 BIT3
-#define DEEMPHASIS_LEVEL__11 BIT4
-#define DEEMPHASIS_LEVEL__11_8 BIT5
-#define DCV_LEVEL_NONE BIT16
-#define DCV_LEVEL__2 BIT17
-#define DCV_LEVEL__3 BIT18
-#define DCV_LEVEL__5 BIT19
-#define DCV_LEVEL__6 BIT20
-#define DCV_LEVEL__7 BIT21
-#define DCV_LEVEL__8 BIT22
-#define DCV_LEVEL__9 BIT23
-#define DCV_LEVEL__11 BIT24
-// Note that an "AND" feature doesn't make any sense, levels are mutually exclusive.
-
-// An error check value.
-#define VALID_DEEMPHASIS_LEVELS (DEEMPHASIS_LEVEL_NONE | \
- DEEMPHASIS_LEVEL__3 | \
- DEEMPHASIS_LEVEL__6 | \
- DEEMPHASIS_LEVEL__8 | \
- DEEMPHASIS_LEVEL__11 | \
- DEEMPHASIS_LEVEL__11_8 | \
- DCV_LEVEL_NONE | \
- DCV_LEVEL__2 | \
- DCV_LEVEL__3 | \
- DCV_LEVEL__5 | \
- DCV_LEVEL__6 | \
- DCV_LEVEL__7 | \
- DCV_LEVEL__8 | \
- DCV_LEVEL__9 | \
- DCV_LEVEL__11)
-
-/**
- * Deemphasis Ht Phy Link Deemphasis.
- *
- * This must be in sync with defines above and ::PLATFORM_DEEMPHASIS_LEVEL (agesa.h)
- */
-typedef struct {
- UINT32 DeemphasisLevelNone:1; ///< The deemphasis level None.
- UINT32 DeemphasisLevelMinus3:1; ///< The deemphasis level minus 3 db.
- UINT32 DeemphasisLevelMinus6:1; ///< The deemphasis level minus 6 db.
- UINT32 DeemphasisLevelMinus8:1; ///< The deemphasis level minus 8 db.
- UINT32 DeemphasisLevelMinus11:1; ///< The deemphasis level minus 11 db.
- UINT32 DeemphasisLevelMinus11w8:1; ///< The deemphasis level minus 11 db, minus 8 precursor.
- UINT32 :(15 - 5); ///< reserved.
- UINT32 DcvLevelNone:1; ///< The level for DCV None.
- UINT32 DcvLevelMinus2:1; ///< The level for DCV minus 2 db.
- UINT32 DcvLevelMinus3:1; ///< The level for DCV minus 3 db.
- UINT32 DcvLevelMinus5:1; ///< The level for DCV minus 5 db.
- UINT32 DcvLevelMinus6:1; ///< The level for DCV minus 6 db.
- UINT32 DcvLevelMinus7:1; ///< The level for DCV minus 7 db.
- UINT32 DcvLevelMinus8:1; ///< The level for DCV minus 8 db.
- UINT32 DcvLevelMinus9:1; ///< The level for DCV minus 9 db.
- UINT32 DcvLevelMinus11:1; ///< The level for DCV minus 11 db.
- UINT32 :(15 - 8); ///< reserved.
-} DEEMPHASIS_FEATURES;
-
-/**
- * Deemphasis Ht Phy Link Features.
- */
-typedef union {
- UINT32 DeemphasisValues; ///< Initialize HT Deemphasis in UINT32.
- DEEMPHASIS_FEATURES DeemphasisLevels; ///< HT Deemphasis levels.
-} DEEMPHASIS_FEATS;
-
-// Initializer bit patterns for PERFORMANCE_PROFILE_FEATS.
-#define PERFORMANCE_REFRESH_REQUEST_32B BIT0
-#define PERFORMANCE_PROBEFILTER BIT1
-#define PERFORMANCE_L3_CACHE BIT2
-#define PERFORMANCE_NO_L3_CACHE BIT3
-#define PERFORMANCE_MCT_ISOC_VARIABLE BIT4
-#define PERFORMANCE_IS_WARM_RESET BIT5
-#define PERFORMANCE_VRM_HIGH_SPEED_ENABLE BIT6
-#define PERFORMANCE_NB_PSTATES_ENABLE BIT7
-#define PERFORMANCE_AND BIT31
-
-#define PERFORMANCE_PROFILE_ALL (PERFORMANCE_REFRESH_REQUEST_32B | \
- PERFORMANCE_PROBEFILTER | \
- PERFORMANCE_L3_CACHE | \
- PERFORMANCE_NO_L3_CACHE | \
- PERFORMANCE_MCT_ISOC_VARIABLE | \
- PERFORMANCE_IS_WARM_RESET | \
- PERFORMANCE_VRM_HIGH_SPEED_ENABLE | \
- PERFORMANCE_NB_PSTATES_ENABLE)
-
-/**
- * Performance Profile specific Type Features.
- *
- * Register settings for the different control flow modes can have additional dependencies
- */
-typedef struct {
- UINT32 RefreshRequest32Byte:1; ///< BIT_0. Display Refresh Requests use 32 bytes (32BE).
- UINT32 ProbeFilter:1; ///< BIT_1 Probe Filter will be enabled.
- UINT32 L3Cache:1; ///< BIT_2 L3 Cache is present.
- UINT32 NoL3Cache:1; ///< BIT_3 L3 Cache is NOT present.
- UINT32 MctIsocVariable:1; ///< BIT_4 Mct Isoc Read Priority set to variable.
- UINT32 IsWarmReset:1; ///< BIT_5 This boot is on a warm reset, cold reset pass is already completed.
- UINT32 VrmHighSpeed:1; ///< BIT_6 Select high speed VRM.
- UINT32 NbPstates:1; ///< BIT_7 Northbridge PStates are enabled
- UINT32 :(30 - 7); ///< available for future expansion.
- UINT32 AndPerformanceFeats:1; ///< BIT_31. AND other selected features.
-} PERFORMANCE_PROFILE_FEATURES;
-
-/**
- * Performance Profile features.
- */
-typedef union {
- UINT32 PerformanceProfileValue; ///< Initializer value.
- PERFORMANCE_PROFILE_FEATURES PerformanceProfileFeatures; ///< The performance profile features.
-} PERFORMANCE_PROFILE_FEATS;
-
-/**
- * Package Type Features
- *
- */
-typedef struct {
- UINT32 PkgType0:1; ///< Package Type 0
- UINT32 PkgType1:1; ///< Package Type 1
- UINT32 PkgType2:1; ///< Package Type 2
- UINT32 PkgType3:1; ///< Package Type 3
- UINT32 PkgType4:1; ///< Package Type 4
- UINT32 PkgType5:1; ///< Package Type 5
- UINT32 PkgType6:1; ///< Package Type 6
- UINT32 PkgType7:1; ///< Package Type 7
- UINT32 PkgType8:1; ///< Package Type 8
- UINT32 PkgType9:1; ///< Package Type 9
- UINT32 PkgType10:1; ///< Package Type 10
- UINT32 PkgType11:1; ///< Package Type 11
- UINT32 PkgType12:1; ///< Package Type 12
- UINT32 PkgType13:1; ///< Package Type 13
- UINT32 PkgType14:1; ///< Package Type 14
- UINT32 PkgType15:1; ///< Package Type 15
- UINT32 Reserved:15; ///< Package Type Reserved
- UINT32 ReservedAndFeats:1; ///< BIT_31. AND other selected features. Always zero here.
-} PACKAGE_TYPE_FEATURES;
-
-// Initializer Values for Package Type
-#define PACKAGE_TYPE_ALL 0XFFFF ///< Package Type apply all packages
-
-// Initializer Values for Ht Host Pci Config Registers
-#define HT_HOST_FEAT_COHERENT BIT0
-#define HT_HOST_FEAT_NONCOHERENT BIT1
-#define HT_HOST_FEAT_GANGED BIT2
-#define HT_HOST_FEAT_UNGANGED BIT3
-#define HT_HOST_FEAT_HT3 BIT4
-#define HT_HOST_FEAT_HT1 BIT5
-#define HT_HOST_AND BIT31
-
-#define HT_HOST_FEATURES_ALL (HT_HOST_FEAT_COHERENT | \
- HT_HOST_FEAT_NONCOHERENT | \
- HT_HOST_FEAT_GANGED | \
- HT_HOST_FEAT_UNGANGED | \
- HT_HOST_FEAT_HT3 | \
- HT_HOST_FEAT_HT1)
-
-/**
- * HT Host PCI register features.
- *
- * Links which are not connected do not match any of these features.
- */
-typedef struct {
- UINT32 Coherent:1; ///< BIT_0 Apply to links with a coherent connection.
- UINT32 NonCoherent:1; ///< BIT_1 Apply to links with a non-coherent connection.
- UINT32 Ganged:1; ///< BIT_2 Apply to links with a ganged connection.
- UINT32 UnGanged:1; ///< BIT_3 Apply to links with a unganged connection.
- UINT32 Ht3:1; ///< BIT_4 Apply to links with HT3 frequency (> 1000 MHz)
- UINT32 Ht1:1; ///< BIT_5 Apply to links with HT1 frequency (< 1200 MHz)
- UINT32 :(30 - 5); ///< Future expansion.
- UINT32 AndHtHostFeats:1; ///< BIT_31. AND other selected features.
-} HT_HOST_FEATURES;
-
-/**
- * HT Host features for table data.
- */
-typedef union {
- UINT32 HtHostValue; ///< Initializer value.
- HT_HOST_FEATURES HtHostFeatures; ///< The HT Host Features.
-} HT_HOST_FEATS;
-
-// Core Range Initializer values.
-#define COUNT_RANGE_LOW 0ul
-#define COUNT_RANGE_HIGH 0xFFul
-
-// A count range matching none is often useful as the second range, matching will then be
-// based on the first range. A count range all is provided as a first range for default settings.
-#define COUNT_RANGE_NONE ((((COUNT_RANGE_HIGH) << 8) | (COUNT_RANGE_HIGH)) << 16)
-#define COUNT_RANGE_ALL (((COUNT_RANGE_HIGH) << 8) | (COUNT_RANGE_LOW))
-#define IGNORE_FREQ_0 (((COUNT_RANGE_HIGH) << 8) | (COUNT_RANGE_HIGH))
-#define IGNORE_PROCESSOR_0 (((COUNT_RANGE_HIGH) << 8) | (COUNT_RANGE_HIGH))
-
-#define CORE_RANGE_0(min, max) ((((UINT32)(max)) << 8) | (UINT32)(min))
-#define CORE_RANGE_1(min, max) (((((UINT32)(max)) << 8) | (UINT32)(min)) << 16)
-#define PROCESSOR_RANGE_0(min, max) ((((UINT32)(max)) << 8) | (UINT32)(min))
-#define PROCESSOR_RANGE_1(min, max) (((((UINT32)(max)) << 8) | (UINT32)(min)) << 16)
-#define DEGREE_RANGE_0(min, max) ((((UINT32)(max)) << 8) | (UINT32)(min))
-#define DEGREE_RANGE_1(min, max) (((((UINT32)(max)) << 8) | (UINT32)(min)) << 16)
-#define FREQ_RANGE_0(min, max) ((((UINT32)(max)) << 8) | (UINT32)(min))
-#define FREQ_RANGE_1(min, max) (((((UINT32)(max)) << 8) | (UINT32)(min)) << 16)
-#define COMPUTE_UNIT_RANGE_0(min, max) ((((UINT32)(max)) << 8) | (UINT32)(min))
-#define COMPUTE_UNIT_RANGE_1(min, max) (((((UINT32)(max)) << 8) | (UINT32)(min)) << 16)
-
-/**
- * Count Range Feature, two count ranges for core counts, processor counts, or node counts.
- */
-typedef struct {
- UINT32 Range0Min:8; ///< The minimum of the first count range.
- UINT32 Range0Max:8; ///< The maximum of the first count range.
- UINT32 Range1Min:8; ///< The minimum of the second count range.
- UINT32 Range1Max:8; ///< The maximum of the second count range.
-} COUNT_RANGE_FEATURE;
-
-/**
- * Core Count Ranges for table data.
- *
- * Provide a pair of core count ranges. If the actual core count is included in either range (OR),
- * the feature should be considered a match.
- */
-typedef union {
- UINT32 CoreRangeValue; ///< Initializer value.
- COUNT_RANGE_FEATURE CoreRanges; ///< The Core Counts.
-} CORE_COUNT_RANGES;
-
-/**
- * Processor count ranges for table data.
- *
- * Provide a pair of processor count ranges. If the actual counts are included in either range (OR),
- * the feature should be considered a match.
- */
-typedef union {
- UINT32 ProcessorCountRangeValue; ///< Initializer value.
- COUNT_RANGE_FEATURE ProcessorCountRanges; ///< The Processor and Node Counts.
-} PROCESSOR_COUNTS;
-
-/**
- * Compute unit count ranges for table data.
- *
- * Provide a pair of compute unit count ranges. If the actual counts are included in either ranges (OR),
- * the feature should be considered a match.
- */
-typedef union {
- UINT32 ComputeUnitRangeValue; ///< Initializer value.
- COUNT_RANGE_FEATURE ComputeUnitRanges; ///< The Processor and Node Counts.
-} COMPUTE_UNIT_COUNTS;
-
-/**
- * Connectivity count ranges for table data.
- *
- * Provide a processor count range and a system degree range. The degree of a system is
- * the maximum degree of any node. The degree of a node is the number of nodes to which
- * it is directly connected (not considering width or redundant links). If both the actual
- * counts are included in each range (AND), the feature should be considered a match.
- */
-typedef union {
- UINT32 ConnectivityCountRangeValue; ///< Initializer value.
- COUNT_RANGE_FEATURE ConnectivityCountRanges; ///< The Processor and Degree Counts.
-} CONNECTIVITY_COUNT;
-
-/**
- * HT Frequency Count Range.
- *
- * Provide a pair of Frequency count ranges, with the frequency encoded as an HT Frequency value
- * (such as would be programmed into the HT Host Link Frequency register). By converting a NB freq,
- * the same count can be applied for it. If the actual value is included in either range
- */
-typedef union {
- UINT32 HtFreqCountRangeValue; ///< Initializer value.
- COUNT_RANGE_FEATURE HtFreqCountRanges; ///< The HT Freq counts.
-} HT_FREQ_COUNTS;
-
-/*------------------------------------------------------------------------------------------*/
-/*
- * The specific data for each table entry.
- */
-/*------------------------------------------------------------------------------------------*/
-
-/**
- * Make an extra type so we can use compilers that don't support designated initializers.
- *
- * All the entry type unions are no more than 5 UINT32's in size. For entry types which are a struct of UINT32's,
- * this type can be used so that initializers can be declared TABLE_ENTRY_FIELDS, instead of a special non-union type.
- * A non-union type then has to be cast back to TABLE_ENTRY_FIELDS in order to process the table, and you can't mix
- * entry types with non-union initializers in the same table with any other type.
- *
- * If the entry type contains anything but UINT32's, then it must have a non-union initializer type for creating the
- * actual tables. For example, MSR entry has UINT64 and workaround entry has a function pointer.
- */
-typedef UINT32 GENERIC_TYPE_ENTRY_INITIALIZER[MAX_ENTRY_TYPE_ITEMS32];
-
-/**
- * Table Entry Data for MSR Registers.
- *
- * Apply data to register after mask, for MSRs.
- */
-typedef struct {
- UINT32 Address; ///< MSR address
- UINT64 Data; ///< Data to set in the MSR
- UINT64 Mask; ///< Mask to be applied to the MSR. Set every bit of all updated fields.
-} MSR_TYPE_ENTRY_DATA;
-
-/**
- * Table Entry Data for PCI Registers.
- *
- * Apply data to register after mask, for PCI Config registers.
- */
-typedef struct {
- PCI_ADDR Address; ///< Address should contain Function, Offset only. It will apply to all CPUs
- UINT32 Data; ///< Data to be written into PCI device
- UINT32 Mask; ///< Mask to be used before data write. Set every bit of all updated fields.
-} PCI_TYPE_ENTRY_DATA;
-
-/**
- * Table Entry Data for HT Phy Registers.
- *
- * Apply data to register after mask, for HT Phy registers, repeated for all active links.
- */
-typedef struct {
- HT_PHY_LINK_FEATS TypeFeats; ///< HT Phy Link Features
- UINT32 Address; ///< Address of Ht Phy Register
- UINT32 Data; ///< Data to be written into PCI device
- UINT32 Mask; ///< Mask to be used before data write. Set every bit of all updated fields.
-} HT_PHY_TYPE_ENTRY_DATA;
-
-/**
- * Table Entry Data for HT Phy Register Ranges.
- *
- * Apply data to register after mask, for a range of HT Phy registers, repeated for all active links.
- */
-typedef struct {
- HT_PHY_LINK_FEATS TypeFeats; ///< HT Phy Link Features
- UINT32 LowAddress; ///< Low address of Ht Phy Register range.
- UINT32 HighAddress; ///< High address of register range.
- UINT32 Data; ///< Data to be written into PCI device.
- UINT32 Mask; ///< Mask to be used before data write. Set every bit of all updated fields.
-} HT_PHY_RANGE_TYPE_ENTRY_DATA;
-
-/**
- * Table Entry Data for HT Phy Deemphasis Registers.
- *
- * Apply data to register after mask, for HT Phy registers, repeated for all active links.
- */
-typedef struct {
- DEEMPHASIS_FEATS Levels; ///< The DCV and Deemphasis levels to match
- HT_PHY_TYPE_ENTRY_DATA HtPhyEntry; ///< The HT Phy Entry to set the deemphasis values
-} DEEMPHASIS_HT_PHY_TYPE_ENTRY_DATA;
-
-/**
- * Table Entry Date for HT Phy Frequency Count Register updates.
- *
- * Compare the NB freq to a range, the HT freq to a range, the link features.
- * Apply data to register after mask, if all three matched.
- */
-typedef struct {
- HT_FREQ_COUNTS HtFreqCounts; ///< Specify the HT Frequency range.
- HT_FREQ_COUNTS NbFreqCounts; ///< Specify the NB Frequency range.
- HT_PHY_TYPE_ENTRY_DATA HtPhyEntry; ///< The HT Phy register update to perform.
-} HT_PHY_FREQ_TYPE_ENTRY_DATA;
-
-/**
- * Table Entry Data for Profile Fixup Registers.
- *
- * If TypeFeats matches current config, apply data to register after mask for PCI Config registers.
- */
-typedef struct {
- PERFORMANCE_PROFILE_FEATS TypeFeats; ///< Profile Fixup Features.
- PCI_TYPE_ENTRY_DATA PciEntry; ///< The PCI Register entry data.
-} PROFILE_FIXUP_TYPE_ENTRY_DATA;
-
-/**
- * A variation of PCI register for the HT Host registers.
- *
- * A setting to the HT Host buffer counts needs to be made to all the registers for
- * all the links. There are also link specific criteria to check.
- */
-typedef struct {
- HT_HOST_FEATS TypeFeats; ///< Link Features.
- PCI_ADDR Address; ///< Address of PCI Register to Fixed Up.
- UINT32 Data; ///< Data to be written into PCI device
- UINT32 Mask; ///< Mask to be used before data write. Set every bit of all updated fields.
-} HT_HOST_PCI_TYPE_ENTRY_DATA;
-
-/**
- * A variation of PCI register for the HT Host performance registers.
- *
- * A setting to the HT Host buffer counts needs to be made to all the registers for
- * all the links. There are also link specific criteria to check.
- */
-typedef struct {
- PERFORMANCE_PROFILE_FEATS PerformanceFeats; ///< Performance Profile features.
- HT_HOST_PCI_TYPE_ENTRY_DATA HtHostEntry; ///< Link Features.
-} HT_HOST_PERFORMANCE_PCI_TYPE_ENTRY_DATA;
-
-/**
- * A variation of HT Host PCI register for the Link Token registers.
- *
- * Use Link Features, Performance Fixup features, and processor counts to match entries.
- * Link Features are iterated through the connected links. All the matching Link Token count
- * registers are updated.
- */
-typedef struct {
- CONNECTIVITY_COUNT ConnectivityCount; ///< Specify Processor count and Degree count range.
- PERFORMANCE_PROFILE_FEATS PerformanceFeats; ///< Performance Profile features.
- HT_HOST_FEATS LinkFeats; ///< Link Features.
- PCI_ADDR Address; ///< Address of PCI Register to Fixed Up.
- UINT32 Data; ///< Data to be written into PCI device
- UINT32 Mask; ///< Mask to be used before data write. Set every bit of all updated fields.
-} HT_TOKEN_PCI_REGISTER;
-
-/**
- * Core Count dependent PCI registers.
- *
- */
-typedef struct {
- PERFORMANCE_PROFILE_FEATS TypeFeats; ///< Profile Fixup Features.
- CORE_COUNT_RANGES CoreCounts; ///< Specify up to two core count ranges to match.
- PCI_TYPE_ENTRY_DATA PciEntry; ///< The PCI Register entry data.
-} CORE_COUNTS_PCI_TYPE_ENTRY_DATA;
-
-/**
- * Processor Count dependent PCI registers.
- *
- */
-typedef struct {
- PERFORMANCE_PROFILE_FEATS TypeFeats; ///< Profile Fixup Features.
- PROCESSOR_COUNTS ProcessorCounts; ///< Specify a processor count range.
- PCI_TYPE_ENTRY_DATA PciEntry; ///< The PCI Register entry data.
-} PROCESSOR_COUNTS_PCI_TYPE_ENTRY_DATA;
-
-/**
- * Compute Unit Count dependent PCI registers.
- *
- */
-typedef struct {
- PERFORMANCE_PROFILE_FEATS TypeFeats; ///< Profile Fixup Features.
- COMPUTE_UNIT_COUNTS ComputeUnitCounts; ///< Specify a compute unit count range.
- PCI_TYPE_ENTRY_DATA PciEntry; ///< The PCI Register entry data.
-} COMPUTE_UNIT_COUNTS_PCI_TYPE_ENTRY_DATA;
-
-/**
- * System connectivity dependent PCI registers.
- *
- * The topology specific recommended settings are based on the different connectivity of nodes
- * in each configuration: the more connections, the fewer resources each connection gets.
- * The connectivity criteria translate as:
- * - 2 Socket, half populated == Degree 1
- * - 4 Socket, half populated == Degree 2
- * - 2 Socket, fully populated == Degree 3
- * - 4 Socket, fully populated == Degree > 3. (4 or 5 if 3P, 6 if 4P)
- *
- */
-typedef struct {
- PERFORMANCE_PROFILE_FEATS TypeFeats; ///< Profile Fixup Features.
- CONNECTIVITY_COUNT ConnectivityCount; ///< Specify a system degree range.
- PCI_TYPE_ENTRY_DATA PciEntry; ///< The PCI Register entry data.
-} CONNECTIVITY_COUNTS_PCI_TYPE_ENTRY_DATA;
-
-/**
- * A Family Specific Workaround method.
- *
- * \@TableTypeFamSpecificInstances.
- *
- * When called, the entry's CPU Logical ID and Platform Features matched the current config.
- * The method must implement any specific criteria checking for the workaround.
- *
- * See if you can use the other entries or make an entry specifically for the fix.
- * After all, the purpose of having a table entry is to @b NOT have code which
- * isn't generic feature code, but is family/model specific.
- *
- * @param[in] Data The table data value, for example to indicate which CPU and Platform types matched.
- * @param[in] StdHeader Config params for library, services.
- */
-typedef VOID F_FAM_SPECIFIC_WORKAROUND (
- IN UINT32 Data,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-/// Reference to a method.
-typedef F_FAM_SPECIFIC_WORKAROUND *PF_FAM_SPECIFIC_WORKAROUND;
-
-/**
- * Table Entry Data for Family Specific Workarounds.
- *
- * See if you can use the other entries or make an entry specifically for the fix.
- * After all, the purpose of having a table entry is to @b NOT have code which
- * isn't generic feature code, but is family/model specific.
- *
- * Call DoAction passing Data.
- */
-typedef struct {
- PF_FAM_SPECIFIC_WORKAROUND DoAction; ///< A function implementing the workaround.
- UINT32 Data; ///< This data is passed to DoAction().
-} FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_DATA;
-
-/**
- * Package Type Features
- *
- * FamilyPackageType are various among CPU families.
- *
- */
-typedef union {
- UINT32 PackageTypeValue; ///< Package Type
- PACKAGE_TYPE_FEATURES FamilyPackageType; ///< Package Type of CPU family
-} PACKAGE_TYPE_FEATS;
-
-/**
- * HT Features dependent Global PCI registers.
- *
- */
-typedef struct {
- HT_HOST_FEATS LinkFeats; ///< Link Features.
- PACKAGE_TYPE_FEATS PackageType; ///< Package Type
- PCI_TYPE_ENTRY_DATA PciEntry; ///< The PCI Register entry data.
-} HT_FEATURES_PCI_TYPE_ENTRY_DATA;
-
-/**
- * Table Entry Data for HT Phy Registers which depend on performance profile features.
- *
- * Match performance profile features and link features.
- * Apply data to register after mask, for HT Phy registers, repeated for all active links.
- */
-typedef struct {
- PERFORMANCE_PROFILE_FEATS TypeFeats; ///< Profile Fixup Features.
- HT_PHY_TYPE_ENTRY_DATA HtPhyEntry; ///< The HT Phy Entry to set the deemphasis values
-} PROFILE_HT_PHY_TYPE_ENTRY_DATA;
-
-/**
- * HT Link PCI registers that are not in the HT Host capability.
- *
- * Some HT Link registers have an instance per link, but are just sequential. Specify the base register
- * in the table register address (link 0 sublink 0).
- */
-typedef struct {
- HT_HOST_FEATS LinkFeats; ///< Link Features.
- PCI_TYPE_ENTRY_DATA PciEntry; ///< The PCI Register entry data.
-} HT_LINK_PCI_TYPE_ENTRY_DATA;
-
-/*------------------------------------------------------------------------------------------*/
-/*
- * A complete register table and table entries.
- */
-/*------------------------------------------------------------------------------------------*/
-
-/**
- * All the available entry data types.
- */
-typedef union {
- GENERIC_TYPE_ENTRY_INITIALIZER InitialValues; ///< Not a valid entry type; as the first union item,
- ///< it can be used with initializers.
- MSR_TYPE_ENTRY_DATA MsrEntry; ///< Msr entry.
- PCI_TYPE_ENTRY_DATA PciEntry; ///< PCI entry.
- FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_DATA FamSpecificEntry; ///< Family Specific Workaround entry.
- HT_PHY_TYPE_ENTRY_DATA HtPhyEntry; ///< HT Phy entry.
- HT_PHY_RANGE_TYPE_ENTRY_DATA HtPhyRangeEntry; ///< A range of Ht Phy Registers
- DEEMPHASIS_HT_PHY_TYPE_ENTRY_DATA DeemphasisEntry; ///< A HT Deemphasis level's settings.
- HT_PHY_FREQ_TYPE_ENTRY_DATA HtPhyFreqEntry; ///< A frequency dependent Ht Phy Register setting.
- PROFILE_FIXUP_TYPE_ENTRY_DATA FixupEntry; ///< Profile Fixup entry.
- HT_HOST_PCI_TYPE_ENTRY_DATA HtHostEntry; ///< HT Host PCI entry.
- HT_HOST_PERFORMANCE_PCI_TYPE_ENTRY_DATA HtHostPerfEntry; ///< HT Host Performance PCI entry
- HT_TOKEN_PCI_REGISTER HtTokenEntry; ///< HT Link Token Count entry.
- CORE_COUNTS_PCI_TYPE_ENTRY_DATA CoreCountEntry; ///< Core count dependent settings.
- PROCESSOR_COUNTS_PCI_TYPE_ENTRY_DATA ProcCountEntry; ///< Processor count entry.
- COMPUTE_UNIT_COUNTS_PCI_TYPE_ENTRY_DATA CompUnitCountEntry; ///< Compute unit count dependent entry.
- CONNECTIVITY_COUNTS_PCI_TYPE_ENTRY_DATA TokenPciEntry; ///< System connectivity dependent Token register.
- HT_FEATURES_PCI_TYPE_ENTRY_DATA HtFeatPciEntry; ///< HT Features PCI entry.
- PROFILE_HT_PHY_TYPE_ENTRY_DATA HtPhyProfileEntry; ///< Performance dependent HT Phy register.
- HT_LINK_PCI_TYPE_ENTRY_DATA HtLinkPciEntry; ///< Per Link, non HT Host, PCI registers.
-} TABLE_ENTRY_DATA;
-
-/**
- * Register Table Entry common fields.
- *
- * All the various types of register table entries are subclasses of this object.
- */
-typedef struct {
- TABLE_ENTRY_TYPE EntryType; ///< The type of table entry this is.
- CPU_LOGICAL_ID CpuRevision; ///< Common CPU Logical ID match criteria.
- PLATFORM_FEATS Features; ///< Common Platform Features match criteria.
- TABLE_ENTRY_DATA Entry; ///< The type dependent entry data (ex. register, data, mask).
-} TABLE_ENTRY_FIELDS;
-
-/**
- * An entire register table.
- */
-typedef struct {
- TABLE_CORE_SELECTOR Selector; ///< For efficiency, these cores should process this table
- UINTN NumberOfEntries; ///< The number of entries in the table.
- CONST TABLE_ENTRY_FIELDS *Table; ///< The table entries.
-} REGISTER_TABLE;
-
-/*------------------------------------------------------------------------------------------*/
-/*
- * Describe implementers for table entries.
- */
-/*------------------------------------------------------------------------------------------*/
-
-/**
- * Implement the semantics of a Table Entry Type.
- *
- * @TableEntryTypeInstances.
- *
- * @param[in] CurrentEntry The type specific entry data to be implemented (that is written).
- * @param[in] PlatformConfig Config handle for platform specific information
- * @param[in] StdHeader Config params for library, services.
- */
-typedef VOID F_DO_TABLE_ENTRY (
- IN TABLE_ENTRY_DATA *CurrentEntry,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-/// Reference to a method
-typedef F_DO_TABLE_ENTRY *PF_DO_TABLE_ENTRY;
-
-/**
- * Describe the attributes of a Table Entry Type.
- */
-typedef struct {
- TABLE_ENTRY_TYPE EntryType; ///< The type of table entry this describes.
- PF_DO_TABLE_ENTRY DoTableEntry; ///< Provide all semantics associated with TABLE_ENTRY_DATA
-} TABLE_ENTRY_TYPE_DESCRIPTOR;
-
-/*------------------------------------------------------------------------------------------*/
-/*
- * Non-union initializers for entry data which is not just UINT32.
- */
-/*------------------------------------------------------------------------------------------*/
-
-/**
- * A union of data types, that can be initialized with MSR data.
- *
- * This ensures the entry data is the same size as TABLE_ENTRY_DATA.
- */
-typedef union {
- MSR_TYPE_ENTRY_DATA MsrInitializer; ///< The data in the table initializer is assigned to this member.
- TABLE_ENTRY_DATA Reserved; ///< Make sure the size is the same as the real union.
-} MSR_DATA_INITIALIZER;
-
-/**
- * A type suitable for an initializer for MSR Table entries.
- */
-typedef struct {
- TABLE_ENTRY_TYPE Type; ///< The type of table entry this is.
- CPU_LOGICAL_ID CpuRevision; ///< Common CPU Logical ID match criteria.
- PLATFORM_FEATS Features; ///< Common Platform Features match criteria.
- MSR_DATA_INITIALIZER EntryData; ///< The special union which accepts msr data initializer.
-} MSR_TYPE_ENTRY_INITIALIZER;
-
-/**
- * A union of data types, that can be initialized with Family Specific Workaround data.
- *
- * This ensures the entry data is the same size as TABLE_ENTRY_DATA.
- */
-typedef union {
- FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_DATA FamSpecificInitializer; ///< The data in the table initializer is assigned to this member.
- TABLE_ENTRY_DATA Reserved; ///< Make sure the size is the same as the real union.
-} FAM_SPECIFIC_WORKAROUND_DATA_INITIALIZER;
-
-/**
- * A type suitable for an initializer for Family Specific Workaround Table entries.
- */
-typedef struct {
- TABLE_ENTRY_TYPE Type; ///< The type of table entry this is.
- CPU_LOGICAL_ID CpuRevision; ///< Common CPU Logical ID match criteria.
- PLATFORM_FEATS Features; ///< Common Platform Features match criteria.
- FAM_SPECIFIC_WORKAROUND_DATA_INITIALIZER EntryData; ///< Special union accepts family specific workaround data initializer.
-} FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER;
-
-/*------------------------------------------------------------------------------------------*/
-/*
- * Table related function prototypes (many are instance of F_DO_TABLE_ENTRY method).
- */
-/*------------------------------------------------------------------------------------------*/
-
-/**
- * Set the registers for this core based on entries in a list of Register Tables.
- */
-VOID SetRegistersFromTables (
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * Find the features of the running platform.
- */
-VOID
-GetPlatformFeatures (
- OUT PLATFORM_FEATS *Features,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * Checks register table entry type specific criteria to the platform.
- */
-BOOLEAN
-DoesEntryTypeSpecificInfoMatch (
- IN UINT32 PlatformTypeSpecificFeatures,
- IN UINT32 EntryTypeFeatures
- );
-
-/**
- * Perform the MSR Register Entry.
- */
-VOID
-SetRegisterForMsrEntry (
- IN TABLE_ENTRY_DATA *Entry,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * Perform the PCI Register Entry.
- */
-VOID
-SetRegisterForPciEntry (
- IN TABLE_ENTRY_DATA *Entry,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * Perform the Performance Profile PCI Register Entry.
- */
-VOID
-SetRegisterForPerformanceProfileEntry (
- IN TABLE_ENTRY_DATA *Entry,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * Perform the HT Host PCI Register Entry.
- */
-VOID
-SetRegisterForHtHostEntry (
- IN TABLE_ENTRY_DATA *Entry,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * Perform the HT Host Performance PCI Register Entry.
- */
-VOID
-SetRegisterForHtHostPerfEntry (
- IN TABLE_ENTRY_DATA *Entry,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * Set the HT Link Token Count registers.
- */
-VOID
-SetRegisterForHtLinkTokenEntry (
- IN TABLE_ENTRY_DATA *Entry,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * Perform the Core Counts Performance PCI Register Entry.
- */
-VOID
-SetRegisterForCoreCountsPerformanceEntry (
- IN TABLE_ENTRY_DATA *Entry,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * Perform the Processor Counts PCI Register Entry.
- */
-VOID
-SetRegisterForProcessorCountsEntry (
- IN TABLE_ENTRY_DATA *Entry,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * Perform the Compute Unit Counts PCI Register Entry.
- */
-VOID
-SetRegisterForComputeUnitCountsEntry (
- IN TABLE_ENTRY_DATA *Entry,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * Perform the Family Specific Workaround Register Entry.
- */
-VOID
-SetRegisterForFamSpecificWorkaroundEntry (
- IN TABLE_ENTRY_DATA *Entry,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * Program HT Phy PCI registers.
- */
-VOID
-SetRegisterForHtPhyEntry (
- IN TABLE_ENTRY_DATA *Entry,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * Program a range of HT Phy PCI registers.
- */
-VOID
-SetRegisterForHtPhyRangeEntry (
- IN TABLE_ENTRY_DATA *Entry,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * Program Deemphasis registers, for the platform specified levels.
- */
-VOID
-SetRegisterForDeemphasisEntry (
- IN TABLE_ENTRY_DATA *Entry,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * Program HT Phy PCI registers which have complex frequency dependencies.
- */
-VOID
-SetRegisterForHtPhyFreqEntry (
- IN TABLE_ENTRY_DATA *Entry,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * Perform the Processor Token Counts PCI Register Entry.
- */
-VOID
-SetRegisterForTokenPciEntry (
- IN TABLE_ENTRY_DATA *Entry,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * Perform the HT Link Feature PCI Register Entry.
- */
-VOID
-SetRegisterForHtFeaturePciEntry (
- IN TABLE_ENTRY_DATA *Entry,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * Perform the HT Phy Performance Profile Register Entry.
- */
-VOID
-SetRegisterForHtPhyProfileEntry (
- IN TABLE_ENTRY_DATA *Entry,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * Perform the HT Link PCI Register Entry.
- */
-VOID
-SetRegisterForHtLinkPciEntry (
- IN TABLE_ENTRY_DATA *Entry,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * Compare counts to a pair of ranges.
- */
-BOOLEAN
-IsEitherCountInRange (
- IN UINTN FirstCount,
- IN UINTN SecondCount,
- IN COUNT_RANGE_FEATURE Ranges
- );
-
-/**
- * Returns the performance profile features list of the currently running processor core.
- */
-VOID
-GetPerformanceFeatures (
- OUT PERFORMANCE_PROFILE_FEATS *Features,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif // _CPU_TABLE_H_
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/cahalt.asm b/src/vendorcode/amd/agesa/Proc/CPU/cahalt.asm
deleted file mode 100644
index 3ffe146..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/cahalt.asm
+++ /dev/null
@@ -1,345 +0,0 @@
-;/**
-; * @file
-; *
-; * Agesa pre-memory miscellaneous support, including ap halt loop.
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: CPU
-; * @e \$Revision: 35270 $ @e \$Date: 2010-07-20 00:02:41 +0800 (Tue, 20 Jul 2010) $
-; */
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
- .XLIST
- INCLUDE agesa.inc
- INCLUDE cpcarmac.inc
- .LIST
-
- .586P
-
-;===============================================
-;===============================================
-;==
-;== M E M O R Y A B S E N T S E G M E N T
-;==
-;===============================================
-;===============================================
- .MODEL flat
- .CODE
-;======================================================================
-; ExecuteFinalHltInstruction: Disables the stack and performs
-; a hlt instruction on an AP.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; eax, ebx, ecx, edx, esp
-;
-;======================================================================
-PUBLIC ExecuteFinalHltInstruction
-ExecuteFinalHltInstruction PROC NEAR C USES ESI EDI HaltFlags:DWORD, ApMtrrSettingList:PTR, StandardHeader:PTR
-
- mov esi, StandardHeader ; The code must reference all parameters to avoid a build warning
- mov esi, HaltFlags
- mov edi, ApMtrrSettingList
- ; Do these special steps in case if the core is part of a compute unit
- ; Note: The following bits are family specific flags, that gets set during build time,
- ; and indicates things like "family cache control methodology", etc.
- ; esi bit0 = 0 -> not a Primary core
- ; esi bit0 = 1 -> Primary core
- ; esi bit1 = 0 -> Cache disable
- ; esi bit1 = 1 -> Cache enable
- .if (esi & 2h)
- ; Set CombineCr0Cd bit
- mov ecx, CU_CFG3
- _RDMSR
- bts edx, (COMBINE_CR0_CD - 32)
- _WRMSR
- ; Clear the CR0.CD bit
- mov eax, CR0 ; Make sure cache is enabled for all APs
- btr eax, CR0_CD
- btr eax, CR0_NW
- mov CR0, eax ; Write back to CR0
- .else
- mov eax, CR0 ; Make sure cache is disabled for all APs
- bts eax, CR0_CD ; Disable cache
- bts eax, CR0_NW
- mov CR0, eax ; Write back to CR0
- .endif
-
- .if (esi & 1h)
- ; This core is a primary core and needs to do all the MTRRs, including shared MTRRs.
- mov esi, edi ; Get ApMtrrSettingList
-
- ; Configure the MTRRs on the AP so
- ; when it runs remote code it will execute
- ; out of RAM instead of ROM.
-
- ; Disable MTRRs and turn on modification enable bit
- mov ecx, MTRR_SYS_CFG
- _RDMSR
- btr eax, MTRR_VAR_DRAM_EN ; Disable
- bts eax, MTRR_FIX_DRAM_MOD_EN ; Enable
- btr eax, MTRR_FIX_DRAM_EN ; Disable
- bts eax, SYS_UC_LOCK_EN
- _WRMSR
-
- ; Setup default values for Fixed-Sized MTRRs
- ; Set 7FFFh-00000h as WB
- mov ecx, AMD_AP_MTRR_FIX64k_00000
- mov eax, 1E1E1E1Eh
- mov edx, eax
- _WRMSR
-
- ; Set 9FFFFh-80000h also as WB
- mov ecx, AMD_AP_MTRR_FIX16k_80000
- _WRMSR
-
- ; Set BFFFFh-A0000h as Uncacheable Memory-mapped IO
- mov ecx, AMD_AP_MTRR_FIX16k_A0000
- xor eax, eax
- xor edx, edx
- _WRMSR
-
- ; Set DFFFFh-C0000h as Uncacheable Memory-mapped IO
- xor eax, eax
- xor edx, edx
- mov ecx, AMD_AP_MTRR_FIX4k_C0000
-
-CDLoop:
- _WRMSR
- inc ecx
- cmp ecx, AMD_AP_MTRR_FIX4k_D8000
- jbe CDLoop
-
- ; Set FFFFFh-E0000h as Uncacheable Memory
- mov eax, 18181818h
- mov edx, eax
-
- mov ecx, AMD_AP_MTRR_FIX4k_E0000
-
-EFLoop:
- _WRMSR
- inc ecx
- cmp ecx, AMD_AP_MTRR_FIX4k_F8000
- jbe EFLoop
-
- ; If IBV provided settings for Fixed-Sized MTRRs,
- ; overwrite the default settings.
- .if ((esi != 0) && (esi != 0FFFFFFFFh))
- mov ecx, (AP_MTRR_SETTINGS ptr [esi]).MsrAddr
- ; While we are not at the end of the list
- .while (ecx != CPU_LIST_TERMINAL)
- ; Ensure that the MSR address is valid for Fixed-Sized MTRRs
- .if ( ((ecx >= AMD_AP_MTRR_FIX4k_C0000) && (ecx <= AMD_AP_MTRR_FIX4k_F8000)) || \
- (ecx == AMD_AP_MTRR_FIX64k_00000) || (ecx == AMD_AP_MTRR_FIX16k_80000 ) || (ecx == AMD_AP_MTRR_FIX16k_A0000))
- mov eax, dword ptr (AP_MTRR_SETTINGS ptr [esi]).MsrData
- mov edx, dword ptr (AP_MTRR_SETTINGS ptr [esi+4]).MsrData
- _WRMSR
- .endif
- add esi, sizeof (AP_MTRR_SETTINGS)
- mov ecx, (AP_MTRR_SETTINGS ptr [esi]).MsrAddr
- .endw
- .endif
-
- ; restore variable MTTR6 and MTTR7 to default states
- mov ecx, AMD_MTRR_VARIABLE_BASE6 ; clear MTRRPhysBase6 MTRRPhysMask6
- xor eax, eax ; and MTRRPhysBase7 MTRRPhysMask7
- xor edx, edx
- .while (cl < 010h)
- _WRMSR
- inc cl
- .endw
-
- ; Enable fixed-range and variable-range MTRRs
- mov ecx, AMD_MTRR_DEFTYPE
- _RDMSR
- bts eax, MTRR_DEF_TYPE_EN ; MtrrDefTypeEn
- bts eax, MTRR_DEF_TYPE_FIX_EN ; MtrrDefTypeFixEn
- _WRMSR
-
- ; Enable Top-of-Memory setting
- ; Enable use of RdMem/WrMem bits attributes
- mov ecx, MTRR_SYS_CFG
- _RDMSR
- bts eax, MTRR_VAR_DRAM_EN ; Enable
- btr eax, MTRR_FIX_DRAM_MOD_EN ; Disable
- bts eax, MTRR_FIX_DRAM_EN ; Enable
- _WRMSR
-
- mov esi, (1 SHL FLAG_IS_PRIMARY)
- .else ; end if primary core
- xor esi, esi
- .endif
- ; Make sure not to touch any Shared MSR from this point on
-
- AMD_DISABLE_STACK_FAMILY_HOOK
-
- xor eax, eax
-
-@@:
- cli
- hlt
- jmp @B ;ExecuteHltInstruction
- ret
-ExecuteFinalHltInstruction ENDP
-
-;======================================================================
-; ExecuteHltInstruction: Performs a hlt instruction.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; eax, ebx, ecx, edx, esp
-;
-;======================================================================
-PUBLIC ExecuteHltInstruction
-ExecuteHltInstruction PROC NEAR C
- cli
- hlt
- ret
-ExecuteHltInstruction ENDP
-
-;======================================================================
-; NmiHandler: Simply performs an IRET.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; None
-;
-;======================================================================
-PUBLIC NmiHandler
-NmiHandler PROC NEAR C
- iretd
-NmiHandler ENDP
-
-;======================================================================
-; GetCsSelector: Returns the current protected mode CS selector.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; None
-;
-;======================================================================
-PUBLIC GetCsSelector
-GetCsSelector PROC NEAR C, CsSelector:PTR
- push ax
- push ebx
-
- call FarCallGetCs
- mov ebx, CsSelector
- mov [ebx], ax
- pop ebx
- pop ax
- ret
-GetCsSelector ENDP
-
-;======================================================================
-; FarCallGetCs:
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; none
-;
-; WARNING: This routine has a mirror routine in the PREMEM segment.
-; These two routines MUST be sync'd for content.
-;======================================================================
-FarCallGetCs PROC FAR PRIVATE
-
- mov ax, ss:[esp + 4]
- retf
-
-FarCallGetCs ENDP
-
-;======================================================================
-; SetIdtr:
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; none
-;
-; WARNING: This routine has a mirror routine in the PREMEM segment.
-; These two routines MUST be sync'd for content.
-;======================================================================
-PUBLIC SetIdtr
-SetIdtr PROC NEAR C USES EBX, IdtPtr:PTR
- mov ebx, IdtPtr
- lidt fword ptr ss:[ebx]
- ret
-SetIdtr ENDP
-
-;======================================================================
-; ExecuteWbinvdInstruction: Performs a wbinvd instruction.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; None
-;
-;======================================================================
-PUBLIC ExecuteWbinvdInstruction
-ExecuteWbinvdInstruction PROC NEAR C
- wbinvd ; Write back the cache tag RAMs
- ret
-ExecuteWbinvdInstruction ENDP
-
-END
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/cahalt.c b/src/vendorcode/amd/agesa/Proc/CPU/cahalt.c
deleted file mode 100644
index c4c3892..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/cahalt.c
+++ /dev/null
@@ -1,317 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * HyperTransport features and sequence implementation.
- *
- * Implements the external AmdHtInitialize entry point.
- * Contains routines for directing the sequence of available features.
- * Mostly, but not exclusively, AGESA_TESTPOINT invocations should be
- * contained in this file, and not in the feature code.
- *
- * From a build option perspective, it may be that a few lines could be removed
- * from compilation in this file for certain options. It is considered that
- * the code savings from this are too small to be of concern and this file
- * should not have any explicit build option implementation.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35978 $ @e \$Date: 2010-08-07 02:18:50 +0800 (Sat, 07 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Filecode.h"
-
- /*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-// typedef unsigned int uintptr_t;
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-VOID
-ExecuteFinalHltInstruction (
- IN UINT32 SharedCore,
- IN AP_MTRR_SETTINGS *ApMtrrSettingsList,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-SetIdtr (
- IN IDT_BASE_LIMIT *IdtInfo,
- IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr
- );
-
-VOID
-GetCsSelector (
- IN UINT16 *Selector,
- IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr
- );
-
-VOID
-NmiHandler (
- IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr
- );
-
-VOID
-ExecuteHltInstruction (
- IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr
- );
-
-VOID
-ExecuteWbinvdInstruction (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
- /*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-//----------------------------------------------------------------------------
-
-STATIC
-VOID
-PrimaryCoreFunctions (AP_MTRR_SETTINGS *ApMtrrSettingsList)
- {
- UINT64 data;
- UINT32 msrno;
- // Configure the MTRRs on the AP so
- // when it runs remote code it will execute
- // out of RAM instead of ROM.
- // Disable MTRRs and turn on modification enable bit
-
- data = __readmsr (0xC0010010); // MTRR_SYS_CFG
- data &= ~(1 << 18); // MtrrFixDramEn
- data &= ~(1 << 20); // MtrrVarDramEn
- data |= (1 << 19); // MtrrFixDramModEn
- data |= (1 << 17); // SysUcLockEn
-
-
- __writemsr (0xC0010010, data);
-
- // Set 7FFFh-00000h and 9FFFFh-80000h as WB DRAM
- __writemsr (0x250, 0x1E1E1E1E1E1E1E1E); // AMD_MTRR_FIX64k_00000
- __writemsr (0x258, 0x1E1E1E1E1E1E1E1E); // AMD_MTRR_FIX16k_80000
-
- // Set BFFFFh-A0000h, DFFFFh-C0000h as Uncacheable Memory-mapped IO
- __writemsr (0x259, 0); // AMD_AP_MTRR_FIX16k_A0000
- __writemsr (0x268, 0); // AMD_MTRR_FIX4k_C0000
- __writemsr (0x269, 0); // AMD_MTRR_FIX4k_C8000
- __writemsr (0x26A, 0); // AMD_MTRR_FIX4k_D0000
- __writemsr (0x26B, 0); // AMD_MTRR_FIX4k_D8000
-
- // Set FFFFFh-E0000h as Uncacheable Memory
- for (msrno = 0x26C; msrno <= 0x26F; msrno++)
- __writemsr (msrno, 0x1818181818181818);
-
- // If IBV provided settings for Fixed-Sized MTRRs,
- // overwrite the default settings.
- if ((uintptr_t) ApMtrrSettingsList != 0 && (uintptr_t) ApMtrrSettingsList != 0xFFFFFFFF)
- {
- int index;
- for (index = 0; ApMtrrSettingsList [index].MsrAddr != CPU_LIST_TERMINAL; index++)
- __writemsr (ApMtrrSettingsList [index].MsrAddr, ApMtrrSettingsList [index].MsrData);
- }
-
- // restore variable MTTR6 and MTTR7 to default states
- for (msrno = 0x20F; msrno <= 0x20C; msrno--) // decrement so that the pair is disable before the base is cleared
- __writemsr (msrno, 0);
-
- // Enable fixed-range and variable-range MTRRs
- // Set Fixed-Range Enable (FE) and MTRR Enable (E) bits
- __writemsr (0x2FF, __readmsr (0x2FF) | 0xC00);
-
- // Enable Top-of-Memory setting
- // Enable use of RdMem/WrMem bits attributes
- data = __readmsr (0xC0010010); // MTRR_SYS_CFG
- data |= (1 << 18); // MtrrFixDramEn
- data |= (1 << 20); // MtrrVarDramEn
- data &= ~(1 << 19); // MtrrFixDramModEn
- __writemsr (0xC0010010, data);
- }
-
-//----------------------------------------------------------------------------
-
-VOID
-ExecuteFinalHltInstruction (
- IN UINT32 SharedCore,
- IN AP_MTRR_SETTINGS *ApMtrrSettingsList,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- int abcdRegs [4];
- UINT32 cr0val;
- UINT64 data;
-
- cr0val = __readcr0 ();
- if (SharedCore & 2)
- {
- // set CombineCr0Cd and enable cache in CR0
- __writemsr (MSR_CU_CFG3, __readmsr (MSR_CU_CFG3) | 1ULL << 49);
- __writecr0 (cr0val & ~0x60000000);
- }
- else
- __writecr0 (cr0val | 0x60000000);
-
- if (SharedCore & 1) PrimaryCoreFunctions (ApMtrrSettingsList);
-
- // Make sure not to touch any Shared MSR from this point on
-
- // Restore settings that were temporarily overridden for the cache as ram phase
- data = __readmsr (0xC0011022); // MSR_DC_CFG
- data &= ~(1 << 4); // DC_DIS_SPEC_TLB_RLD
- data &= ~(1 << 8); // DIS_CLR_WBTOL2_SMC_HIT
- data &= ~(1 << 13); // DIS_HW_PF
- __writemsr (0xC0011022, data);
-
- data = __readmsr (0xC0011021); // MSR_IC_CFG - C001_1021
- data &= ~(1 << 9); // IC_DIS_SPEC_TLB_RLD
- __writemsr (0xC0011021, data);
-
- // AMD_DISABLE_STACK_FAMILY_HOOK
- __cpuid (abcdRegs, 1);
- if ((abcdRegs [0] >> 20) == 1) //-----family 10h (Hydra) only-----
- {
- data = __readmsr (0xC0011022);
- data &= ~(1 << 4);
- data &= ~(1 << 8);
- data &= ~(1 << 13);
- __writemsr (0xC0011022, data);
-
- data = __readmsr (0xC0011021);
- data &= ~(1 << 14);
- data &= ~(1 << 9);
- __writemsr (0xC0011021, data);
-
- data = __readmsr (0xC001102A);
- data &= ~(1 << 15);
- data &= ~(1ull << 35);
- __writemsr (0xC001102A, data);
- }
- else if ((abcdRegs [0] >> 20) == 6) //-----family 15h (Orochi) only-----
- {
- data = __readmsr (0xC0011020);
- data &= ~(1 << 28);
- __writemsr (0xC0011020, data);
-
- data = __readmsr (0xC0011021);
- data &= ~(1 << 9);
- __writemsr (0xC0011021, data);
-
- data = __readmsr (0xC0011022);
- data &= ~(1 << 4);
- data &= ~(1l << 13);
- __writemsr (0xC0011022, data);
- }
-
- for (;;)
- {
- _disable ();
- __halt ();
- }
- }
-
-//----------------------------------------------------------------------------
-
-/// Structure needed to load the IDTR using the lidt instruction
-
-VOID
-SetIdtr (
- IN IDT_BASE_LIMIT *IdtInfo,
- IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr
- )
-{
- __lidt (IdtInfo);
-}
-
-//----------------------------------------------------------------------------
-
-VOID
-GetCsSelector (
- IN UINT16 *Selector,
- IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr
- )
-{
- static const UINT8 opcode [] = {0x8C, 0xC8, 0xC3}; // mov eax, cs; ret
- *Selector = ((UINT16 (*)(void)) (size_t) opcode) ();
-}
-
-//----------------------------------------------------------------------------
-
-VOID
-NmiHandler (
- IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr
- )
-{
- static const UINT8 opcode [] = {0xCF}; // iret
- ((void (*)(void)) (size_t) opcode) ();
-}
-
-//----------------------------------------------------------------------------
-
-VOID
-ExecuteHltInstruction (
- IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr
- )
-{
- _disable ();
- __halt ();
-}
-
-//---------------------------------------------------------------------------
-
-VOID
-ExecuteWbinvdInstruction (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- __wbinvd ();
-}
-
-//----------------------------------------------------------------------------
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/cahalt64.asm b/src/vendorcode/amd/agesa/Proc/CPU/cahalt64.asm
deleted file mode 100644
index f1411fa..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/cahalt64.asm
+++ /dev/null
@@ -1,157 +0,0 @@
-;/**
-; * @file
-; *
-; * Agesa pre-memory miscellaneous support, including ap halt loop.
-; *
-; * @xrefitem bom "File Content Label" "Release Content"
-; * @e project: AGESA
-; * @e sub-project: CPU
-; * @e \$Revision: 10071 $ @e \$Date: 2008-12-16 18:03:04 -0600 (Tue, 16 Dec 2008) $
-; */
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
- text SEGMENT
-
-
-;======================================================================
-; ExecuteFinalHltInstruction: Performs a hlt instruction.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; eax, ebx, ecx, edx, esp
-;
-;======================================================================
-ExecuteFinalHltInstruction PROC PUBLIC
-@@:
- cli
- hlt
- jmp @B ;ExecuteHltInstruction
-ExecuteFinalHltInstruction ENDP
-
-;======================================================================
-; ExecuteHltInstruction: Performs a hlt instruction.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; eax, ebx, ecx, edx, esp
-;
-;======================================================================
-ExecuteHltInstruction PROC PUBLIC
- cli
- hlt
- ret
-ExecuteHltInstruction ENDP
-
-;======================================================================
-; NmiHandler: Simply performs an IRET.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; None
-;
-;======================================================================
-NmiHandler PROC PUBLIC
- iretq
-NmiHandler ENDP
-
-;======================================================================
-; GetCsSelector: Returns the current protected mode CS selector.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; None
-;
-;======================================================================
-GetCsSelector PROC PUBLIC
- ; This stub function is here to avoid compilation errors.
- ; At this time, there is no need to provide a 64 bit function.
- ret
-GetCsSelector ENDP
-
-;======================================================================
-; SetIdtr:
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; none
-;
-; WARNING: This routine has a mirror routine in the PREMEM segment.
-; These two routines MUST be sync'd for content.
-;======================================================================
-SetIdtr PROC PUBLIC
- ; This stub function is here to avoid compilation errors.
- ; At this time, there is no need to provide a 64 bit function.
- ret
-SetIdtr ENDP
-
-;======================================================================
-; ExecuteWbinvdInstruction: Performs a wbinvd instruction.
-;
-; In:
-; None
-;
-; Out:
-; None
-;
-; Destroyed:
-; None
-;
-;======================================================================
-ExecuteWbinvdInstruction PROC PUBLIC
- wbinvd ; Write back the cache tag RAMs
- ret
-ExecuteWbinvdInstruction ENDP
-
-END
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/cpuApicUtilities.c b/src/vendorcode/amd/agesa/Proc/CPU/cpuApicUtilities.c
deleted file mode 100644
index 9476969..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/cpuApicUtilities.c
+++ /dev/null
@@ -1,1466 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU APIC related utility functions.
- *
- * Contains code that provides mechanism to invoke and control APIC communication.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuCacheInit.h"
-#include "cpuRegisters.h"
-#include "cpuApicUtilities.h"
-#include "cpuFamilyTranslation.h"
-#include "GeneralServices.h"
-#include "cpuServices.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_CPUAPICUTILITIES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-/* ApFlags bits */
-#define AP_TASK_HAS_INPUT 0x00000001
-#define AP_TASK_HAS_OUTPUT 0x00000002
-#define AP_RETURN_PARAMS 0x00000004
-#define AP_END_AT_HLT 0x00000008
-#define AP_PASS_EARLY_PARAMS 0x00000010
-
-#define SEG_DESC_PRESENT 0x80
-
-#define SEG_DESC_TYPE_LDT 0x02
-#define SEG_DESC_TYPE_CALL16 0x04
-#define SEG_DESC_TYPE_TASK 0x05
-#define SEG_DESC_TYPE_INT16 0x06
-#define SEG_DESC_TYPE_TRAP16 0x07
-#define SEG_DESC_TYPE_CALL32 0x0C
-#define SEG_DESC_TYPE_INT32 0x0E
-#define SEG_DESC_TYPE_TRAP32 0x0F
-
-#define XFER_ELEMENT_SIZE sizeof (UINT32)
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-typedef VOID F_CPU_AMD_NMI_HANDLER (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-typedef F_CPU_AMD_NMI_HANDLER *PF_CPU_AMD_NMI_HANDLER;
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-VOID
-STATIC
-ApUtilSetupIdtForHlt (
- IN IDT_DESCRIPTOR *NmiIdtDescPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-UINT32
-STATIC
-ApUtilRemoteRead (
- IN UINT8 Socket,
- IN UINT8 Core,
- IN UINT8 RegAddr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-STATIC
-ApUtilLocalWrite (
- IN UINT32 RegAddr,
- IN UINT32 Value,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-UINT32
-STATIC
-ApUtilLocalRead (
- IN UINT32 RegAddr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-STATIC
-ApUtilGetLocalApicBase (
- OUT UINT64 *ApicBase,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-UINT8
-STATIC
-ApUtilCalculateUniqueId (
- IN UINT8 Socket,
- IN UINT8 Core,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-STATIC
-ApUtilFireDirectedNmi (
- IN UINT8 Socket,
- IN UINT8 Core,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-STATIC
-ApUtilReceivePointer (
- IN UINT8 Socket,
- IN UINT8 Core,
- OUT VOID **ReturnPointer,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-STATIC
-ApUtilTransmitPointer (
- IN UINT8 Socket,
- IN UINT8 Core,
- IN VOID **Pointer,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-STATIC
-PerformFinalHalt (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-extern
-VOID
-ExecuteHltInstruction (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-extern
-VOID
-GetCsSelector (
- IN UINT16 *Selector,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-extern
-VOID
-NmiHandler (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-extern
-VOID
-SetIdtr (
- IN IDT_BASE_LIMIT *IdtInfo,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-extern
-VOID
-ExecuteFinalHltInstruction (
- IN UINT32 SharedCore,
- IN AP_MTRR_SETTINGS *ApMtrrSettingsList,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-extern BUILD_OPT_CFG UserOptions;
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Initialize the Local APIC.
- *
- * This function determines and programs the appropriate APIC ID value
- * for the executing core. This code must be run after HT initialization
- * is complete.
- *
- * @param[in] CpuEarlyParamsPtr Service parameters.
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-LocalApicInitialization (
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 CurrentCore;
- UINT32 CurrentNodeNum;
- UINT32 CoreIdBits;
- UINT32 Mnc;
- UINT32 ProcessorCount;
- UINT32 ProcessorApicIndex;
- UINT32 IoApicNum;
- UINT32 StartLocalApicId;
- UINT64 LocalApicBase;
- UINT32 TempVar_a;
- UINT64 MsrData;
- UINT64 Address;
- CPUID_DATA CpuidData;
-
- // Local variables default values
- IoApicNum = CpuEarlyParamsPtr->PlatformConfig.NumberOfIoApics;
-
- GetCurrentCore (&CurrentCore, StdHeader);
- GetCurrentNodeNum (&CurrentNodeNum, StdHeader);
-
- // Get Mnc
- LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuidData, StdHeader);
- CoreIdBits = (CpuidData.ECX_Reg & 0x0000F000) >> 12;
- Mnc = 1 << (CoreIdBits & 0x000F);
-
- // Get ProcessorCount in the system
- ProcessorCount = GetNumberOfProcessors (StdHeader);
-
- // Get the APIC Index of this processor.
- ProcessorApicIndex = GetProcessorApicIndex (CurrentNodeNum, StdHeader);
-
- TempVar_a = (Mnc * ProcessorCount) + IoApicNum;
- ASSERT (TempVar_a < 255);
-
- // Apply apic enumeration rules
- // For systems with >= 16 APICs, put the IO-APICs at 0..n and
- // put the local-APICs at m..z
- // For systems with < 16 APICs, put the Local-APICs at 0..n and
- // put the IO-APICs at (n + 1)..z
- // This is needed because many IO-APIC devices only have 4 bits
- // for their APIC id and therefore must reside at 0..15
- StartLocalApicId = 0;
- if (TempVar_a >= 16) {
- if (IoApicNum >= 1) {
- StartLocalApicId = (IoApicNum - 1) / Mnc;
- StartLocalApicId = (StartLocalApicId + 1) * Mnc;
- }
- }
-
- // Set local apic id
- TempVar_a = (ProcessorApicIndex * Mnc) + CurrentCore + StartLocalApicId;
- IDS_HDT_CONSOLE (CPU_TRACE, " Node %d core %d APIC ID = 0x%x\n", CurrentNodeNum, CurrentCore, TempVar_a);
- TempVar_a = TempVar_a << APIC20_ApicId;
-
- // Enable local apic id
- LibAmdMsrRead (MSR_APIC_BAR, &MsrData, StdHeader);
- MsrData |= APIC_ENABLE_BIT;
- LibAmdMsrWrite (MSR_APIC_BAR, &MsrData, StdHeader);
-
- // Get local apic base Address
- ApUtilGetLocalApicBase (&LocalApicBase, StdHeader);
-
- Address = LocalApicBase + APIC_ID_REG;
- LibAmdMemWrite (AccessWidth32, Address, &TempVar_a, StdHeader);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Initialize the Local APIC at the AmdInitEarly entry point.
- *
- * This function acts as a wrapper for calling the LocalApicInitialization
- * routine at AmdInitEarly.
- *
- * @param[in] FamilyServices The current Family Specific Services.
- * @param[in] EarlyParams Service parameters.
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-LocalApicInitializationAtEarly (
- IN CPU_SPECIFIC_SERVICES *FamilyServices,
- IN AMD_CPU_EARLY_PARAMS *EarlyParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_TESTPOINT (TpProcCpuLocalApicInit, StdHeader);
- LocalApicInitialization (EarlyParams, StdHeader);
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Main entry point for all APs in the system.
- *
- * This routine puts the AP cores in an infinite loop in which the cores
- * will poll their masters, waiting to be told to perform a task. At early,
- * all socket-relative core zeros will receive their tasks from the BSC.
- * All others will receive their tasks from the core zero of their local
- * processor. At the end of AmdInitEarly, all cores will switch to receiving
- * their tasks from the BSC.
- *
- * @param[in] StdHeader Handle to config for library and services.
- * @param[in] CpuEarlyParams AMD_CPU_EARLY_PARAMS pointer.
- *
- */
-VOID
-ApEntry (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams
- )
-{
- UINT8 RemoteCmd;
- UINT8 SourceSocket;
- UINT8 CommandStart;
- UINT32 ApFlags;
- UINT32 FuncType;
- UINT32 ReturnCode;
- UINT32 CurrentSocket;
- UINT32 CurrentCore;
- UINT32 *InputDataPtr;
- UINT32 BscSocket;
- UINT32 Ignored;
- AP_FUNCTION_PTR FuncAddress;
- IDT_DESCRIPTOR IdtDesc;
- AP_DATA_TRANSFER DataTransferInfo;
- AGESA_STATUS IgnoredSts;
-
- ASSERT (!IsBsp (StdHeader, &IgnoredSts));
-
- // Initialize local variables
- ReturnCode = 0;
- DataTransferInfo.DataTransferFlags = 0;
- InputDataPtr = NULL;
-
- // Determine the executing core's socket and core numbers
- IdentifyCore (StdHeader, &CurrentSocket, &Ignored, &CurrentCore, &IgnoredSts);
-
- IDS_HDT_CONSOLE (CPU_TRACE, " Socket %d core %d begin AP tasking engine\n", CurrentSocket, CurrentCore);
-
- // Determine the BSC's socket number
- GetSocketModuleOfNode ((UINT32) 0x00000000, &BscSocket, &Ignored, StdHeader);
-
- // Setup Interrupt Descriptor Table for sleep mode
- ApUtilSetupIdtForHlt (&IdtDesc, StdHeader);
-
- // Indicate to the BSC that we have reached the tasking engine
- ApUtilWriteControlByte (CORE_IDLE, StdHeader);
-
- if (CurrentCore == 0) {
- // Core 0s receive their tasks from the BSC
- SourceSocket = (UINT8) BscSocket;
- } else {
- // All non-zero cores receive their tasks from the core 0 of their socket
- SourceSocket = (UINT8) CurrentSocket;
- }
-
- // Determine the unique value that the master will write when it has a task
- // for this core to perform.
- CommandStart = ApUtilCalculateUniqueId (
- (UINT8)CurrentSocket,
- (UINT8)CurrentCore,
- StdHeader
- );
- for (;;) {
- RemoteCmd = ApUtilReadRemoteControlByte (SourceSocket, 0, StdHeader);
- if (RemoteCmd == CommandStart) {
- ApFlags = ApUtilReadRemoteDataDword (SourceSocket, 0, StdHeader);
-
- ApUtilReceivePointer (SourceSocket, 0, (VOID **) &FuncAddress, StdHeader);
-
- FuncType = ApFlags & (UINT32) (AP_TASK_HAS_INPUT | AP_TASK_HAS_OUTPUT | AP_PASS_EARLY_PARAMS);
- if ((ApFlags & AP_TASK_HAS_INPUT) != 0) {
- DataTransferInfo.DataSizeInDwords = 0;
- DataTransferInfo.DataPtr = NULL;
- DataTransferInfo.DataTransferFlags = 0;
- if (ApUtilReceiveBuffer (SourceSocket, 0, &DataTransferInfo, StdHeader) == AGESA_ERROR) {
- // There is not enough space to put the input data on the heap. Undefined behavior is about
- // to result.
- IDS_ERROR_TRAP;
- }
- InputDataPtr = (UINT32 *) DataTransferInfo.DataPtr;
- }
- ApUtilWriteControlByte (CORE_ACTIVE, StdHeader);
- switch (FuncType) {
- case 0:
- FuncAddress.PfApTask (StdHeader);
- break;
- case AP_TASK_HAS_INPUT:
- FuncAddress.PfApTaskI (InputDataPtr, StdHeader);
- break;
- case AP_PASS_EARLY_PARAMS:
- FuncAddress.PfApTaskC (StdHeader, CpuEarlyParams);
- break;
- case (AP_TASK_HAS_INPUT | AP_PASS_EARLY_PARAMS):
- FuncAddress.PfApTaskIC (InputDataPtr, StdHeader, CpuEarlyParams);
- break;
- case AP_TASK_HAS_OUTPUT:
- ReturnCode = FuncAddress.PfApTaskO (StdHeader);
- break;
- case (AP_TASK_HAS_INPUT | AP_TASK_HAS_OUTPUT):
- ReturnCode = FuncAddress.PfApTaskIO (InputDataPtr, StdHeader);
- break;
- case (AP_TASK_HAS_OUTPUT | AP_PASS_EARLY_PARAMS):
- ReturnCode = FuncAddress.PfApTaskOC (StdHeader, CpuEarlyParams);
- break;
- case (AP_TASK_HAS_INPUT | AP_TASK_HAS_OUTPUT | AP_PASS_EARLY_PARAMS):
- ReturnCode = FuncAddress.PfApTaskIOC (InputDataPtr, StdHeader, CpuEarlyParams);
- break;
- default:
- ReturnCode = 0;
- break;
- }
- if (((ApFlags & AP_RETURN_PARAMS) != 0)) {
- ApUtilTransmitBuffer (SourceSocket, 0, &DataTransferInfo, StdHeader);
- }
- if ((ApFlags & AP_TASK_HAS_OUTPUT) != 0) {
- ApUtilWriteDataDword (ReturnCode, StdHeader);
- }
- if ((ApFlags & AP_END_AT_HLT) != 0) {
- RemoteCmd = CORE_IDLE_HLT;
- } else {
- ApUtilWriteControlByte (CORE_IDLE, StdHeader);
- }
- }
- if (RemoteCmd == CORE_IDLE_HLT) {
- SourceSocket = (UINT8) BscSocket;
- ApUtilWriteControlByte (CORE_IDLE_HLT, StdHeader);
- ExecuteHltInstruction (StdHeader);
- ApUtilWriteControlByte (CORE_IDLE, StdHeader);
- }
- }
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Reads the 'control byte' on the designated remote core.
- *
- * This function will read the current contents of the control byte
- * on the designated core using the APIC remote read inter-
- * processor interrupt sequence.
- *
- * @param[in] Socket Socket number of the desired core
- * @param[in] Core Core number of the desired core
- * @param[in] StdHeader Configuration parameters pointer
- *
- * @return The current value of the remote cores control byte
- *
- */
-UINT8
-ApUtilReadRemoteControlByte (
- IN UINT8 Socket,
- IN UINT8 Core,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 ControlByte;
- UINT32 ApicRegister;
-
- ApicRegister = ApUtilRemoteRead (Socket, Core, APIC_CTRL_DWORD, StdHeader);
- ControlByte = (UINT8) ((ApicRegister & APIC_CTRL_MASK) >> APIC_CTRL_SHIFT);
- return (ControlByte);
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Writes the 'control byte' on the executing core.
- *
- * This function writes data to a local APIC offset used in inter-
- * processor communication.
- *
- * @param[in] Value
- * @param[in] StdHeader
- *
- */
-VOID
-ApUtilWriteControlByte (
- IN UINT8 Value,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 ApicRegister;
-
- ApicRegister = ApUtilLocalRead (APIC_CTRL_REG, StdHeader);
- ApicRegister = ((ApicRegister & ~APIC_CTRL_MASK) | (UINT32) (Value << APIC_CTRL_SHIFT));
- ApUtilLocalWrite (APIC_CTRL_REG, ApicRegister, StdHeader);
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Reads the 'data dword' on the designated remote core.
- *
- * This function will read the current contents of the data dword
- * on the designated core using the APIC remote read inter-
- * processor interrupt sequence.
-
- * @param[in] Socket Socket number of the desired core
- * @param[in] Core Core number of the desired core
- * @param[in] StdHeader Configuration parameters pointer
- *
- * @return The current value of the remote core's data dword
- *
- */
-UINT32
-ApUtilReadRemoteDataDword (
- IN UINT8 Socket,
- IN UINT8 Core,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- return (ApUtilRemoteRead (Socket, Core, APIC_DATA_DWORD, StdHeader));
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Writes the 'data dword' on the executing core.
- *
- * This function writes data to a local APIC offset used in inter-
- * processor communication.
- *
- * @param[in] Value Value to write
- * @param[in] StdHeader Configuration parameters pointer
- *
- */
-VOID
-ApUtilWriteDataDword (
- IN UINT32 Value,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- ApUtilLocalWrite (APIC_DATA_REG, Value, StdHeader);
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Runs the given task on the specified local core.
- *
- * This function is used to invoke an AP to run a specified AGESA
- * procedure. It can only be called by cores that have subordinate
- * APs -- the BSC at POST, or any socket-relative core 0s at Early.
- *
- * @param[in] Socket Socket number of the target core
- * @param[in] Core Core number of the target core
- * @param[in] TaskPtr Function descriptor
- * @param[in] StdHeader Configuration parameters pointer
- *
- * @return Return value of the task that the AP core ran,
- * or zero if the task was VOID.
- *
- */
-UINT32
-ApUtilRunCodeOnSocketCore (
- IN UINT8 Socket,
- IN UINT8 Core,
- IN AP_TASK *TaskPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 CoreId;
- UINT8 CurrentStatus;
- UINT8 WaitStatus[3];
- UINT32 ApFlags;
- UINT32 ReturnCode;
- AP_WAIT_FOR_STATUS WaitForStatus;
-
- ApFlags = 0;
- ReturnCode = 0;
-
- CoreId = ApUtilCalculateUniqueId (Socket, Core, StdHeader);
-
- if (TaskPtr->DataTransfer.DataSizeInDwords != 0) {
- ApFlags |= AP_TASK_HAS_INPUT;
- if (((TaskPtr->ExeFlags & RETURN_PARAMS) != 0) &&
- ((TaskPtr->DataTransfer.DataTransferFlags & DATA_IN_MEMORY) == 0)) {
- ApFlags |= AP_RETURN_PARAMS;
- }
- }
-
- if ((TaskPtr->ExeFlags & TASK_HAS_OUTPUT) != 0) {
- ApFlags |= AP_TASK_HAS_OUTPUT;
- }
-
- if ((TaskPtr->ExeFlags & END_AT_HLT) != 0) {
- ApFlags |= AP_END_AT_HLT;
- }
-
- if ((TaskPtr->ExeFlags & PASS_EARLY_PARAMS) != 0) {
- ApFlags |= AP_PASS_EARLY_PARAMS;
- }
-
- WaitStatus[0] = CORE_IDLE;
- WaitStatus[1] = CORE_IDLE_HLT;
- WaitStatus[2] = CORE_UNAVAILABLE;
- WaitForStatus.Status = WaitStatus;
- WaitForStatus.NumberOfElements = 3;
- WaitForStatus.RetryCount = WAIT_INFINITELY;
- WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY;
- CurrentStatus = ApUtilWaitForCoreStatus (Socket, Core, &WaitForStatus, StdHeader);
-
- if (CurrentStatus != CORE_UNAVAILABLE) {
- ApUtilWriteDataDword (ApFlags, StdHeader);
- ApUtilWriteControlByte (CoreId, StdHeader);
-
- if (CurrentStatus == CORE_IDLE_HLT) {
- ApUtilFireDirectedNmi (Socket, Core, StdHeader);
- }
-
- ApUtilTransmitPointer (Socket, Core, (VOID **) &TaskPtr->FuncAddress, StdHeader);
-
- if ((ApFlags & AP_TASK_HAS_INPUT) != 0) {
- ApUtilTransmitBuffer (Socket, Core, &TaskPtr->DataTransfer, StdHeader);
- }
-
- if ((TaskPtr->ExeFlags & WAIT_FOR_CORE) != 0) {
- if (((ApFlags & AP_TASK_HAS_INPUT) != 0) &&
- ((ApFlags & AP_RETURN_PARAMS) != 0) &&
- ((TaskPtr->DataTransfer.DataTransferFlags & DATA_IN_MEMORY) == 0)) {
- if (ApUtilReceiveBuffer (Socket, Core, &TaskPtr->DataTransfer, StdHeader) == AGESA_ERROR) {
- // There is not enough space to put the return data. This should never occur. If it
- // does, this would point to strange heap corruption.
- IDS_ERROR_TRAP;
- }
- }
-
- ApUtilWaitForCoreStatus (Socket, Core, &WaitForStatus, StdHeader);
- if ((ApFlags & AP_TASK_HAS_OUTPUT) != 0) {
- ReturnCode = ApUtilReadRemoteDataDword (Socket, Core, StdHeader);
- }
- }
- } else {
- ReturnCode = 0;
- }
- return (ReturnCode);
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Waits for a remote core's control byte value to either be equal or
- * not equal to any number of specified values.
- *
- * This function will loop doing remote read IPIs until the remote core's
- * control byte becomes one of the values in the input array if the input
- * flags are set for equality. Otherwise, the loop will continue until
- * the control byte value is not equal to one of the elements in the
- * array. The caller can also specify an iteration count for timeout
- * purposes.
- *
- * @param[in] Socket
- * @param[in] Core
- * @param[in] WaitParamsPtr
- * @param[in] StdHeader
- *
- * @return The current value of the remote core's control byte
- *
- */
-UINT8
-ApUtilWaitForCoreStatus (
- IN UINT8 Socket,
- IN UINT8 Core,
- IN AP_WAIT_FOR_STATUS *WaitParamsPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- BOOLEAN IsEqual;
- UINT8 CoreStatus;
- UINT8 i;
- UINT8 j;
-
- CoreStatus = 0;
- for (i = 0; (WaitParamsPtr->RetryCount == WAIT_INFINITELY) ||
- (i < WaitParamsPtr->RetryCount); ++i) {
- CoreStatus = ApUtilReadRemoteControlByte (Socket, Core, StdHeader);
- // Determine whether or not the current remote status is equal
- // to an element in the array.
- IsEqual = FALSE;
- for (j = 0; !IsEqual && j < WaitParamsPtr->NumberOfElements; ++j) {
- if (CoreStatus == WaitParamsPtr->Status[j]) {
- IsEqual = TRUE;
- }
- }
- if ((((WaitParamsPtr->WaitForStatusFlags & WAIT_STATUS_EQUALITY) != 0) && IsEqual) ||
- (((WaitParamsPtr->WaitForStatusFlags & WAIT_STATUS_EQUALITY) == 0) && !IsEqual)) {
- break;
- }
- }
- return (CoreStatus);
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Runs the AP task on the executing core.
- *
- * @param[in] TaskPtr Function descriptor
- * @param[in] StdHeader Configuration parameters pointer
- * @param[in] ConfigParams Entry point CPU parameters pointer
- *
- * @return Return value of the task, or zero if the task
- * was VOID.
- *
- */
-UINT32
-ApUtilTaskOnExecutingCore (
- IN AP_TASK *TaskPtr,
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN VOID *ConfigParams
- )
-{
- UINT32 InvocationOptions;
- UINT32 ReturnCode;
-
- ReturnCode = 0;
- InvocationOptions = 0;
-
- if (TaskPtr->DataTransfer.DataSizeInDwords != 0) {
- InvocationOptions |= AP_TASK_HAS_INPUT;
- }
- if ((TaskPtr->ExeFlags & TASK_HAS_OUTPUT) != 0) {
- InvocationOptions |= AP_TASK_HAS_OUTPUT;
- }
- if ((TaskPtr->ExeFlags & PASS_EARLY_PARAMS) != 0) {
- InvocationOptions |= AP_PASS_EARLY_PARAMS;
- }
-
- switch (InvocationOptions) {
- case 0:
- TaskPtr->FuncAddress.PfApTask (StdHeader);
- break;
- case AP_TASK_HAS_INPUT:
- TaskPtr->FuncAddress.PfApTaskI (TaskPtr->DataTransfer.DataPtr, StdHeader);
- break;
- case AP_PASS_EARLY_PARAMS:
- TaskPtr->FuncAddress.PfApTaskC (StdHeader, ConfigParams);
- break;
- case (AP_TASK_HAS_INPUT | AP_PASS_EARLY_PARAMS):
- TaskPtr->FuncAddress.PfApTaskIC (TaskPtr->DataTransfer.DataPtr, StdHeader, ConfigParams);
- break;
- case AP_TASK_HAS_OUTPUT:
- ReturnCode = TaskPtr->FuncAddress.PfApTaskO (StdHeader);
- break;
- case (AP_TASK_HAS_INPUT | AP_TASK_HAS_OUTPUT):
- ReturnCode = TaskPtr->FuncAddress.PfApTaskIO (TaskPtr->DataTransfer.DataPtr, StdHeader);
- break;
- case (AP_TASK_HAS_OUTPUT | AP_PASS_EARLY_PARAMS):
- ReturnCode = TaskPtr->FuncAddress.PfApTaskOC (StdHeader, ConfigParams);
- break;
- case (AP_TASK_HAS_INPUT | AP_TASK_HAS_OUTPUT | AP_PASS_EARLY_PARAMS):
- ReturnCode = TaskPtr->FuncAddress.PfApTaskIOC (TaskPtr->DataTransfer.DataPtr, StdHeader, ConfigParams);
- break;
- default:
- ReturnCode = 0;
- break;
- }
- return (ReturnCode);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Sets up the AP's IDT with NMI (INT2) being the only valid descriptor
- *
- * This function prepares the executing AP core for recovering from a hlt
- * instruction by initializing its IDTR.
- *
- * @param[in] NmiIdtDescPtr Pointer to a writable IDT entry to
- * be used for NMIs
- * @param[in] StdHeader Configuration parameters pointer
- *
- */
-VOID
-STATIC
-ApUtilSetupIdtForHlt (
- IN IDT_DESCRIPTOR *NmiIdtDescPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 DescSize;
- UINT64 HandlerOffset;
- UINT64 EferRegister;
- IDT_BASE_LIMIT IdtInfo;
-
- LibAmdMsrRead (MSR_EXTENDED_FEATURE_EN, &EferRegister, StdHeader);
- if ((EferRegister & 0x100) != 0) {
- DescSize = 16;
- } else {
- DescSize = 8;
- }
-
- HandlerOffset = (UINT64) NmiHandler;
- NmiIdtDescPtr->OffsetLo = (UINT16) HandlerOffset & 0xFFFF;
- NmiIdtDescPtr->OffsetHi = (UINT16) (HandlerOffset >> 16);
- GetCsSelector (&NmiIdtDescPtr->Selector, StdHeader);
- NmiIdtDescPtr->Flags = SEG_DESC_PRESENT | SEG_DESC_TYPE_INT32;
- NmiIdtDescPtr->Rsvd = 0;
- NmiIdtDescPtr->Offset64 = (UINT32) (HandlerOffset >> 32);
- NmiIdtDescPtr->Rsvd64 = 0;
- IdtInfo.Limit = (UINT16) ((DescSize * 3) - 1);
- IdtInfo.Base = (UINT64) NmiIdtDescPtr - (DescSize * 2);
- SetIdtr (&IdtInfo , StdHeader);
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Calculate the APIC ID for a given core.
- *
- * Get the current node's apic id and deconstruct it to the base id of local apic id space.
- * Then construct the target's apic id using that base.
- * @b Assumes: The target Socket and Core exist!
- * Other Notes:
- * - Must run after HT initialization is complete.
- * - Code sync: This calculation MUST match the assignment
- * calculation done above in LocalApicInitializationAtEarly function.
- * - Assumes family homogeneous population of all sockets.
- *
- * @param[in] TargetSocket The socket in which the Core's Processor is installed.
- * @param[in] TargetCore The Core on that Processor
- * @param[out] LocalApicId Its APIC Id
- * @param[in] StdHeader Handle to header for library and services.
- *
- */
-VOID
-GetLocalApicIdForCore (
- IN UINT32 TargetSocket,
- IN UINT32 TargetCore,
- OUT UINT32 *LocalApicId,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 CoreIdBits;
- UINT32 CurrentNode;
- UINT32 CurrentCore;
- UINT32 TargetNode;
- UINT32 MaxCoresInProcessor;
- UINT32 TotalCores;
- UINT32 CurrentLocalApicId;
- UINT64 LocalApicBase;
- UINT32 TempVar_a;
- UINT64 Address;
- UINT32 ProcessorApicIndex;
- BOOLEAN ReturnResult;
- CPUID_DATA CpuidData;
-
- TargetNode = 0;
-
- // Get local apic base Address
- ApUtilGetLocalApicBase (&LocalApicBase, StdHeader);
- Address = LocalApicBase + APIC_ID_REG;
-
- LibAmdMemRead (AccessWidth32, Address, &TempVar_a, StdHeader);
-
- // ApicId [7:0]
- CurrentLocalApicId = (TempVar_a >> APIC20_ApicId) & 0x000000FF;
-
- GetCurrentNodeAndCore (&CurrentNode, &CurrentCore, StdHeader);
- LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuidData, StdHeader);
- CoreIdBits = (CpuidData.ECX_Reg & 0x0000F000) >> 12;
- MaxCoresInProcessor = (1 << CoreIdBits);
-
- // Get the APIC Index of this processor.
- ProcessorApicIndex = GetProcessorApicIndex (CurrentNode, StdHeader);
-
- TotalCores = (MaxCoresInProcessor * ProcessorApicIndex) + CurrentCore;
- CurrentLocalApicId -= TotalCores;
-
- // Use the Node Id of TargetSocket, Module 0. No socket transitions are missed or added,
- // even if the TargetCore is not on Module 0 in that processor and that's all that matters now.
- ReturnResult = GetNodeId (TargetSocket, 0, (UINT8 *)&TargetNode, StdHeader);
- ASSERT (ReturnResult);
-
- // Get the APIC Index of this processor.
- ProcessorApicIndex = GetProcessorApicIndex (TargetNode, StdHeader);
-
- CurrentLocalApicId += ((MaxCoresInProcessor * ProcessorApicIndex) + TargetCore);
- *LocalApicId = CurrentLocalApicId;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Securely passes a buffer to the designated remote core.
- *
- * This function uses a sequence of remote reads to transmit a data
- * buffer, one UINT32 at a time.
- *
- * @param[in] Socket Socket number of the remote core
- * @param[in] Core Core number of the remote core
- * @param[in] BufferInfo Information about the buffer to pass, and
- * how to pass it
- * @param[in] StdHeader Configuration parameters pointer
- *
- */
-VOID
-ApUtilTransmitBuffer (
- IN UINT8 Socket,
- IN UINT8 Core,
- IN AP_DATA_TRANSFER *BufferInfo,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 TargetCore;
- UINT8 MyUniqueId;
- UINT8 CurrentStatus;
- UINT32 *CurrentPtr;
- UINT32 i;
- UINT32 MyCore;
- UINT32 MySocket;
- UINT32 Ignored;
- AP_WAIT_FOR_STATUS WaitForStatus;
- AGESA_STATUS IgnoredSts;
-
- if ((BufferInfo->DataTransferFlags & DATA_IN_MEMORY) != 0) {
- ApUtilWriteDataDword ((UINT32) 0x00000000, StdHeader);
- } else {
- ApUtilWriteDataDword ((UINT32) BufferInfo->DataSizeInDwords, StdHeader);
- }
- TargetCore = ApUtilCalculateUniqueId (Socket, Core, StdHeader);
-
- ApUtilWriteControlByte (TargetCore, StdHeader);
-
- IdentifyCore (StdHeader, &MySocket, &Ignored, &MyCore, &IgnoredSts);
-
- MyUniqueId = ApUtilCalculateUniqueId ((UINT8)MySocket, (UINT8)MyCore, StdHeader);
-
- WaitForStatus.Status = &MyUniqueId;
- WaitForStatus.NumberOfElements = 1;
- WaitForStatus.RetryCount = WAIT_INFINITELY;
- WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY;
-
- ApUtilWaitForCoreStatus (Socket, Core, &WaitForStatus, StdHeader);
- ApUtilWriteDataDword (BufferInfo->DataTransferFlags, StdHeader);
-
- ApUtilWriteControlByte (CORE_DATA_FLAGS_READY, StdHeader);
- WaitForStatus.WaitForStatusFlags = 0;
- ApUtilWaitForCoreStatus (Socket, Core, &WaitForStatus, StdHeader);
- if ((BufferInfo->DataTransferFlags & DATA_IN_MEMORY) != 0) {
- ApUtilTransmitPointer (Socket, Core, (VOID **) &BufferInfo->DataPtr, StdHeader);
- } else {
- ApUtilWriteControlByte (CORE_STS_DATA_READY_1, StdHeader);
- CurrentStatus = CORE_STS_DATA_READY_0;
- WaitForStatus.Status = &CurrentStatus;
- WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY;
- ApUtilWaitForCoreStatus (Socket, Core, &WaitForStatus, StdHeader);
- WaitForStatus.WaitForStatusFlags = 0;
- CurrentPtr = (UINT32 *) BufferInfo->DataPtr;
- for (i = 0; i < BufferInfo->DataSizeInDwords; ++i) {
- ApUtilWriteDataDword (*CurrentPtr++, StdHeader);
- ApUtilWriteControlByte (CurrentStatus, StdHeader);
- ApUtilWaitForCoreStatus (Socket, Core, &WaitForStatus, StdHeader);
- CurrentStatus ^= 0x01;
- }
- }
- ApUtilWriteControlByte (CORE_ACTIVE, StdHeader);
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Securely receives a buffer from the designated remote core.
- *
- * This function uses a sequence of remote reads to receive a data
- * buffer, one UINT32 at a time.
- *
- * @param[in] Socket Socket number of the remote core
- * @param[in] Core Core number of the remote core
- * @param[in] BufferInfo Information about where to place the buffer
- * @param[in] StdHeader Configuration parameters pointer
- *
- * @retval AGESA_SUCCESS Transaction was successful
- * @retval AGESA_ALERT The non-NULL desired location to place
- * the buffer was not used as the buffer
- * resides in a shared memory space. The
- * input data pointer has changed.
- * @retval AGESA_ERROR There is not enough room to receive the
- * buffer.
- *
- */
-AGESA_STATUS
-ApUtilReceiveBuffer (
- IN UINT8 Socket,
- IN UINT8 Core,
- IN OUT AP_DATA_TRANSFER *BufferInfo,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 MyUniqueId;
- UINT8 SourceUniqueId;
- UINT8 CurrentStatus;
- UINT32 i;
- UINT32 MySocket;
- UINT32 MyCore;
- UINT32 Ignored;
- UINT32 *CurrentPtr;
- UINT32 TransactionSize;
- AGESA_STATUS ReturnStatus;
- ALLOCATE_HEAP_PARAMS HeapMalloc;
- AP_WAIT_FOR_STATUS WaitForStatus;
-
- ReturnStatus = AGESA_SUCCESS;
- IdentifyCore (StdHeader, &MySocket, &Ignored, &MyCore, &ReturnStatus);
-
- MyUniqueId = ApUtilCalculateUniqueId ((UINT8)MySocket, (UINT8)MyCore, StdHeader);
-
- WaitForStatus.Status = &MyUniqueId;
- WaitForStatus.NumberOfElements = 1;
- WaitForStatus.RetryCount = WAIT_INFINITELY;
- WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY;
-
- ApUtilWaitForCoreStatus (Socket, Core, &WaitForStatus, StdHeader);
- TransactionSize = ApUtilReadRemoteDataDword (Socket, Core, StdHeader);
-
- if (BufferInfo->DataPtr == NULL && TransactionSize != 0) {
- HeapMalloc.BufferHandle = AMD_CPU_AP_TASKING_HANDLE;
- HeapMalloc.Persist = HEAP_LOCAL_CACHE;
- // Deallocate the general purpose heap structure, if it exists. Ignore
- // the status in case it does not exist.
- HeapDeallocateBuffer (HeapMalloc.BufferHandle, StdHeader);
- HeapMalloc.RequestedBufferSize = (TransactionSize * XFER_ELEMENT_SIZE);
- if (HeapAllocateBuffer (&HeapMalloc, StdHeader) == AGESA_SUCCESS) {
- BufferInfo->DataPtr = (UINT32 *) HeapMalloc.BufferPtr;
- BufferInfo->DataSizeInDwords = (UINT16) (HeapMalloc.RequestedBufferSize / XFER_ELEMENT_SIZE);
- } else {
- BufferInfo->DataSizeInDwords = 0;
- }
- }
-
- if (TransactionSize <= BufferInfo->DataSizeInDwords) {
- SourceUniqueId = ApUtilCalculateUniqueId (Socket, Core, StdHeader);
- ApUtilWriteControlByte (SourceUniqueId, StdHeader);
- CurrentStatus = CORE_DATA_FLAGS_READY;
- WaitForStatus.Status = &CurrentStatus;
- ApUtilWaitForCoreStatus (Socket, Core, &WaitForStatus, StdHeader);
- BufferInfo->DataTransferFlags = ApUtilReadRemoteDataDword (Socket, Core, StdHeader);
- ApUtilWriteControlByte (CORE_DATA_FLAGS_ACKNOWLEDGE, StdHeader);
- if ((BufferInfo->DataTransferFlags & DATA_IN_MEMORY) != 0) {
- if (BufferInfo->DataPtr != NULL) {
- ReturnStatus = AGESA_ALERT;
- }
- ApUtilReceivePointer (Socket, Core, (VOID **) &BufferInfo->DataPtr, StdHeader);
- } else {
- CurrentStatus = CORE_STS_DATA_READY_1;
- ApUtilWaitForCoreStatus (Socket, Core, &WaitForStatus, StdHeader);
- CurrentStatus = CORE_STS_DATA_READY_0;
- ApUtilWriteControlByte (CurrentStatus, StdHeader);
- CurrentPtr = BufferInfo->DataPtr;
- for (i = 0; i < TransactionSize; ++i) {
- ApUtilWaitForCoreStatus (Socket, Core, &WaitForStatus, StdHeader);
- *CurrentPtr++ = ApUtilReadRemoteDataDword (Socket, Core, StdHeader);
- CurrentStatus ^= 0x01;
- ApUtilWriteControlByte (CurrentStatus, StdHeader);
- }
- }
- ApUtilWriteControlByte (CORE_ACTIVE, StdHeader);
- } else {
- BufferInfo->DataSizeInDwords = (UINT16) TransactionSize;
- ReturnStatus = AGESA_ERROR;
- }
- return (ReturnStatus);
-}
-
-
-VOID
-RelinquishControlOfAllAPs (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 BscSocket;
- UINT32 Ignored;
- UINT32 BscCore;
- UINT32 Core;
- UINT32 Socket;
- UINT32 NumberOfSockets;
- AP_TASK TaskPtr;
- AGESA_STATUS IgnoredSts;
-
- ASSERT (IsBsp (StdHeader, &IgnoredSts));
-
- TaskPtr.FuncAddress.PfApTask = PerformFinalHalt;
- TaskPtr.DataTransfer.DataSizeInDwords = 0;
- TaskPtr.ExeFlags = WAIT_FOR_CORE;
-
- IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredSts);
- NumberOfSockets = GetPlatformNumberOfSockets ();
-
- for (Socket = 0; Socket < NumberOfSockets; Socket++) {
- if (GetActiveCoresInGivenSocket (Socket, &Core, StdHeader)) {
- while (Core-- > 0) {
- if ((Socket != BscSocket) || (Core != BscCore)) {
- ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);
- }
- }
- }
- }
-}
-
-/*---------------------------------------------------------------------------------------
- * L O C A L F U N C T I O N S
- *---------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * The last AGESA code that an AP performs
- *
- * This function, run only by APs, breaks down their cache subsystem, sets up
- * for memory to be present upon wake (from IBV Init/Startup IPIs), and halts.
- *
- * @param[in] StdHeader Config handle for library and services
- *
- */
-VOID
-STATIC
-PerformFinalHalt (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 PrimaryCore;
- UINT32 HaltFlags;
- UINT32 CacheEnDis;
- CPU_SPECIFIC_SERVICES *FamilyServices;
-
- GetCpuServicesOfCurrentCore (&FamilyServices, StdHeader);
- ASSERT (FamilyServices != NULL);
- // CacheEnDis is a family specific flag, that lets the code to decide whether to
- // keep the cache control bits set or cleared.
- CacheEnDis = FamilyServices->InitCacheDisabled;
-
- // Determine if the current core has the primary core role. The first core to execute
- // in each compute unit has the primary role.
- PrimaryCore = (UINT32) IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader);
-
- // Aggregate the flags for the halt service.
- HaltFlags = PrimaryCore | (CacheEnDis << 1);
-
- ApUtilWriteControlByte (CORE_UNAVAILABLE, StdHeader);
- ExecuteFinalHltInstruction (HaltFlags, UserOptions.CfgApMtrrSettingsList, StdHeader);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Reads the APIC register on the designated remote core.
- *
- * This function uses the remote read inter-processor interrupt protocol
- * to read an APIC register from the remote core
- *
- * @param[in] Socket Socket number of remote core
- * @param[in] Core Core number of remote core
- * @param[in] RegAddr APIC register to read
- * @param[in] StdHeader Configuration parameters pointer
- *
- * @return The current value of the remote core's desired APIC register
- *
- */
-UINT32
-STATIC
-ApUtilRemoteRead (
- IN UINT8 Socket,
- IN UINT8 Core,
- IN UINT8 RegAddr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 ApicRegister;
- UINT32 TargetApicId;
- UINT64 ApicBase;
- UINT64 ApicAddr;
-
- ApUtilGetLocalApicBase (&ApicBase, StdHeader);
- GetLocalApicIdForCore ((UINT32) Socket, (UINT32) Core, &TargetApicId, StdHeader);
- TargetApicId <<= LOCAL_APIC_ID;
-
- do {
- ApicAddr = ApicBase + APIC_CMD_HI_REG;
- LibAmdMemWrite (AccessWidth32, ApicAddr, &TargetApicId, StdHeader);
- ApicAddr = ApicBase + APIC_CMD_LO_REG;
- ApicRegister = CMD_REG_TO_READ | (UINT32) RegAddr;
- LibAmdMemWrite (AccessWidth32, ApicAddr, &ApicRegister, StdHeader);
- do {
- LibAmdMemRead (AccessWidth32, ApicAddr, &ApicRegister, StdHeader);
- } while ((ApicRegister & CMD_REG_DELIVERY_STATUS) != 0);
- while ((ApicRegister & CMD_REG_REMOTE_RD_STS_MSK) == CMD_REG_REMOTE_DELIVERY_PENDING) {
- LibAmdMemRead (AccessWidth32, ApicAddr, &ApicRegister, StdHeader);
- }
- } while ((ApicRegister & CMD_REG_REMOTE_RD_STS_MSK) != CMD_REG_REMOTE_DELIVERY_DONE);
- ApicAddr = ApicBase + APIC_REMOTE_READ_REG;
- LibAmdMemRead (AccessWidth32, ApicAddr, &ApicRegister, StdHeader);
- return (ApicRegister);
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Writes an APIC register on the executing core.
- *
- * This function gets the base address of the executing core's local APIC,
- * and writes a UINT32 value to a specified offset.
- *
- * @param[in] RegAddr APIC register to write to
- * @param[in] Value Data to be written to the desired APIC register
- * @param[in] StdHeader Configuration parameters pointer
- *
- */
-VOID
-STATIC
-ApUtilLocalWrite (
- IN UINT32 RegAddr,
- IN UINT32 Value,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 ApicAddr;
-
- ApUtilGetLocalApicBase (&ApicAddr, StdHeader);
- ApicAddr += RegAddr;
-
- LibAmdMemWrite (AccessWidth32, ApicAddr, &Value, StdHeader);
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Reads an APIC register on the executing core.
- *
- * This function gets the base address of the executing core's local APIC,
- * and reads a UINT32 value from a specified offset.
- *
- * @param[in] RegAddr APIC register to read from
- * @param[in] StdHeader Configuration parameters pointer
- *
- * @return The current value of the local APIC register
- *
- */
-UINT32
-STATIC
-ApUtilLocalRead (
- IN UINT32 RegAddr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 ApicRegister;
- UINT64 ApicAddr;
-
- ApUtilGetLocalApicBase (&ApicAddr, StdHeader);
- ApicAddr += RegAddr;
- LibAmdMemRead (AccessWidth32, ApicAddr, &ApicRegister, StdHeader);
-
- return (ApicRegister);
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns the 64-bit base address of the executing core's local APIC.
- *
- * This function reads the APICBASE MSR and isolates the programmed address.
- *
- * @param[out] ApicBase Base address
- * @param[in] StdHeader Configuration parameters pointer
- *
- */
-VOID
-STATIC
-ApUtilGetLocalApicBase (
- OUT UINT64 *ApicBase,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- LibAmdMsrRead (MSR_APIC_BAR, ApicBase, StdHeader);
- *ApicBase &= LAPIC_BASE_ADDR_MASK;
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Determines the unique ID of the input Socket/Core.
- *
- * This routine converts a socket-core combination to to a number
- * that will be used to directly address a particular core. This
- * unique value must be less than 128 because we only have a byte
- * to use for status. APIC IDs are not guaranteed to be below
- * 128.
- *
- * @param[in] Socket Socket number of the remote core
- * @param[in] Core Core number of the remote core
- * @param[in] StdHeader Configuration parameters pointer
- *
- * @return The unique ID of the desired core
- *
- */
-UINT8
-STATIC
-ApUtilCalculateUniqueId (
- IN UINT8 Socket,
- IN UINT8 Core,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 UniqueId;
-
- UniqueId = ((Core << 3) | Socket);
- ASSERT ((UniqueId & 0x80) == 0);
- return (UniqueId);
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Wakes up a core from the halted state.
- *
- * This function sends a directed NMI inter-processor interrupt to
- * the input Socket/Core.
- *
- * @param[in] Socket Socket number of remote core to wake up
- * @param[in] Core Socket-relative core number of the remote core to wake up
- * @param[in] StdHeader Configuration parameters pointer
- *
- */
-VOID
-STATIC
-ApUtilFireDirectedNmi (
- IN UINT8 Socket,
- IN UINT8 Core,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 TargetApicId;
-
- GetLocalApicIdForCore ((UINT32) Socket, (UINT32) Core, &TargetApicId, StdHeader);
- TargetApicId <<= LOCAL_APIC_ID;
-
- ApUtilLocalWrite ((UINT32) APIC_CMD_HI_REG, TargetApicId, StdHeader);
- ApUtilLocalWrite ((UINT32) APIC_CMD_LO_REG, (UINT32) CMD_REG_TO_NMI, StdHeader);
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Securely receives a pointer from the designated remote core.
- *
- * This function uses a sequence of remote reads to receive a pointer,
- * one UINT32 at a time.
- *
- * @param[in] Socket Socket number of the remote core
- * @param[in] Core Core number of the remote core
- * @param[out] ReturnPointer Pointer passed from remote core
- * @param[in] StdHeader Configuration parameters pointer
- *
- */
-VOID
-STATIC
-ApUtilReceivePointer (
- IN UINT8 Socket,
- IN UINT8 Core,
- OUT VOID **ReturnPointer,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 i;
- UINT8 WaitStatus;
- UINT32 *AddressScratchPtr;
- AP_WAIT_FOR_STATUS WaitForStatus;
-
- WaitStatus = CORE_STS_DATA_READY_0;
- WaitForStatus.Status = &WaitStatus;
- WaitForStatus.NumberOfElements = 1;
- WaitForStatus.RetryCount = WAIT_INFINITELY;
- AddressScratchPtr = (UINT32 *) ReturnPointer;
- for (i = 0; i < SIZE_IN_DWORDS (AddressScratchPtr); ++i) {
- ApUtilWriteControlByte (CORE_NEEDS_PTR, StdHeader);
- WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY;
- ApUtilWaitForCoreStatus (Socket, Core, &WaitForStatus, StdHeader);
- *AddressScratchPtr++ = ApUtilReadRemoteDataDword (Socket, Core, StdHeader);
- ApUtilWriteControlByte (CORE_ACTIVE, StdHeader);
- WaitForStatus.WaitForStatusFlags = 0;
- ApUtilWaitForCoreStatus (Socket, Core, &WaitForStatus, StdHeader);
- }
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Securely transmits a pointer to the designated remote core.
- *
- * This function uses a sequence of remote reads to transmit a pointer,
- * one UINT32 at a time.
- *
- * @param[in] Socket Socket number of the remote core
- * @param[in] Core Core number of the remote core
- * @param[out] Pointer Pointer passed from remote core
- * @param[in] StdHeader Configuration parameters pointer
- *
- */
-VOID
-STATIC
-ApUtilTransmitPointer (
- IN UINT8 Socket,
- IN UINT8 Core,
- IN VOID **Pointer,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 i;
- UINT8 WaitStatus;
- UINT32 *AddressScratchPtr;
- AP_WAIT_FOR_STATUS WaitForStatus;
-
- WaitStatus = CORE_NEEDS_PTR;
- WaitForStatus.Status = &WaitStatus;
- WaitForStatus.NumberOfElements = 1;
- WaitForStatus.RetryCount = WAIT_INFINITELY;
-
- AddressScratchPtr = (UINT32 *) Pointer;
-
- for (i = 0; i < SIZE_IN_DWORDS (AddressScratchPtr); i++) {
- WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY;
- ApUtilWaitForCoreStatus (Socket, Core, &WaitForStatus, StdHeader);
- ApUtilWriteDataDword (*AddressScratchPtr++, StdHeader);
- ApUtilWriteControlByte (CORE_STS_DATA_READY_0, StdHeader);
- WaitForStatus.WaitForStatusFlags = 0;
- ApUtilWaitForCoreStatus (Socket, Core, &WaitForStatus, StdHeader);
- ApUtilWriteControlByte (CORE_ACTIVE, StdHeader);
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/cpuApicUtilities.h b/src/vendorcode/amd/agesa/Proc/CPU/cpuApicUtilities.h
deleted file mode 100644
index 96549a7..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/cpuApicUtilities.h
+++ /dev/null
@@ -1,262 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU APIC related utility functions and structures
- *
- * Contains code that provides mechanism to invoke and control APIC communication.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPU_APIC_UTILITIES_H_
-#define _CPU_APIC_UTILITIES_H_
-
-
-/*---------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *---------------------------------------------------------------------------------------
- */
-#define APIC_CTRL_DWORD 0xF
-#define APIC_CTRL_REG (APIC_CTRL_DWORD << 4)
-#define APIC_CTRL_MASK 0xFF
-#define APIC_CTRL_SHIFT 0
-
-#define APIC_DATA_DWORD 0x38
-#define APIC_DATA_REG (APIC_DATA_DWORD << 4)
-
-#define APIC_REMOTE_READ_REG 0xC0
-#define APIC_CMD_LO_REG 0x300
-#define APIC_CMD_HI_REG 0x310
-
-// APIC_CMD_LO_REG bits
-#define CMD_REG_DELIVERY_STATUS 0x1000
-#define CMD_REG_TO_READ 0x300
-#define CMD_REG_REMOTE_RD_STS_MSK 0x30000
-#define CMD_REG_REMOTE_DELIVERY_PENDING 0x10000
-#define CMD_REG_REMOTE_DELIVERY_DONE 0x20000
-#define CMD_REG_TO_NMI 0x400
-
-// ExeFlags bits
-#define WAIT_FOR_CORE 0x00000001
-#define TASK_HAS_OUTPUT 0x00000002
-#define RETURN_PARAMS 0x00000004
-#define END_AT_HLT 0x00000008
-#define PASS_EARLY_PARAMS 0x00000010
-
-// Control Byte Values
-// bit 7 indicates the type of message
-// 1 - control message
-// 0 - launch + APIC ID = message to go
-//
-#define CORE_UNAVAILABLE 0xFF
-#define CORE_IDLE 0xFE
-#define CORE_IDLE_HLT 0xFD
-#define CORE_ACTIVE 0xFC
-#define CORE_NEEDS_PTR 0xFB
-#define CORE_NEEDS_DATA_SIZE 0xFA
-#define CORE_STS_DATA_READY_1 0xF9
-#define CORE_STS_DATA_READY_0 0xF8
-#define CORE_DATA_FLAGS_READY 0xF7
-#define CORE_DATA_FLAGS_ACKNOWLEDGE 0xF6
-#define CORE_DATA_PTR_READY 0xF5
-
-// Macro used to determine the number of dwords to transmit to the AP as input
-#define SIZE_IN_DWORDS(sInput) ((UINT32) (((sizeof (sInput)) + 3) >> 2))
-
-/*---------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *---------------------------------------------------------------------------------------
- */
-typedef VOID (*PF_AP_TASK) (AMD_CONFIG_PARAMS *StdHeader);
-typedef VOID (*PF_AP_TASK_I) (VOID *, AMD_CONFIG_PARAMS *StdHeader);
-typedef VOID (*PF_AP_TASK_C) (AMD_CONFIG_PARAMS *StdHeader, AMD_CPU_EARLY_PARAMS *);
-typedef VOID (*PF_AP_TASK_IC) (VOID *, AMD_CONFIG_PARAMS *StdHeader, AMD_CPU_EARLY_PARAMS *);
-typedef UINT32 (*PF_AP_TASK_O) (AMD_CONFIG_PARAMS *StdHeader);
-typedef UINT32 (*PF_AP_TASK_IO) (VOID *, AMD_CONFIG_PARAMS *StdHeader);
-typedef UINT32 (*PF_AP_TASK_OC) (AMD_CONFIG_PARAMS *StdHeader, AMD_CPU_EARLY_PARAMS *);
-typedef UINT32 (*PF_AP_TASK_IOC) (VOID *, AMD_CONFIG_PARAMS *StdHeader, AMD_CPU_EARLY_PARAMS *);
-
-/// Function pointer union representing the eight different
-/// types of functions that an AP can be asked to perform.
-typedef union {
- PF_AP_TASK PfApTask; ///< AMD_CONFIG_PARAMS * input with no output
- PF_AP_TASK_I PfApTaskI; ///< VOID * + AMD_CONFIG_PARAMS * input with no output
- PF_AP_TASK_C PfApTaskC; ///< AMD_CONFIG_PARAMS * + AMD_CPU_EARLY_PARAMS * input with no output
- PF_AP_TASK_IC PfApTaskIC; ///< VOID * + AMD_CONFIG_PARAMS * + AMD_CPU_EARLY_PARAMS * input with no output
- PF_AP_TASK_O PfApTaskO; ///< AMD_CONFIG_PARAMS * input with UINT32 output
- PF_AP_TASK_IO PfApTaskIO; ///< VOID * + AMD_CONFIG_PARAMS * input with UINT32 output
- PF_AP_TASK_OC PfApTaskOC; ///< AMD_CONFIG_PARAMS * + AMD_CPU_EARLY_PARAMS * input with UINT32 output
- PF_AP_TASK_IOC PfApTaskIOC; ///< VOID * + AMD_CONFIG_PARAMS * + AMD_CPU_EARLY_PARAMS * input with UINT32 output
-} AP_FUNCTION_PTR;
-
-/// Input structure for ApUtilTransmitBuffer and ApUtilReceiveBuffer
-/// containing information about the data transfer from one core
-/// to another.
-typedef struct {
- IN OUT UINT16 DataSizeInDwords; ///< Size of the data to be transferred rounded up to the nearest dword
- IN OUT VOID *DataPtr; ///< Pointer to the data
- IN UINT32 DataTransferFlags; ///< Flags dictating certain aspects of the data transfer
-} AP_DATA_TRANSFER;
-
-/// Input structure for ApUtilRunCodeOnSocketCore.
-typedef struct _AP_TASK {
- AP_FUNCTION_PTR FuncAddress; ///< Pointer to the function that the AP will run
- AP_DATA_TRANSFER DataTransfer; ///< Data transfer struct for optionally passing data that the AP should use as input to the function
- UINT32 ExeFlags; ///< Flags dictating certain aspects of the AP tasking sequence
-} AP_TASK;
-
-/// Input structure for ApUtilWaitForCoreStatus.
-typedef struct {
- IN UINT8 *Status; ///< Pointer to the 1st element of an array of values to wait for
- IN UINT8 NumberOfElements; ///< Number of elements in the array
- IN UINT32 RetryCount; ///< Number of remote read cycles to complete before quitting
- IN UINT32 WaitForStatusFlags; ///< Flags dictating certain aspects of ApUtilWaitForCoreStatus
-} AP_WAIT_FOR_STATUS;
-
-#define WAIT_STATUS_EQUALITY 0x00000001
-#define WAIT_INFINITELY 0
-
-// Data Transfer Flags
-#define DATA_IN_MEMORY 0x00000001
-
-
-/*---------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *---------------------------------------------------------------------------------------
- */
-// These are P U B L I C functions, used by AGESA
-UINT8
-ApUtilReadRemoteControlByte (
- IN UINT8 Socket,
- IN UINT8 Core,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-ApUtilWriteControlByte (
- IN UINT8 Value,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-UINT32
-ApUtilReadRemoteDataDword (
- IN UINT8 Socket,
- IN UINT8 Core,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-ApUtilWriteDataDword (
- IN UINT32 Value,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-UINT32
-ApUtilRunCodeOnSocketCore (
- IN UINT8 Socket,
- IN UINT8 Core,
- IN AP_TASK *TaskPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-UINT8
-ApUtilWaitForCoreStatus (
- IN UINT8 Socket,
- IN UINT8 Core,
- IN AP_WAIT_FOR_STATUS *WaitParamsPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-ApEntry (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams
- );
-
-UINT32
-ApUtilTaskOnExecutingCore (
- IN AP_TASK *TaskPtr,
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN VOID *ConfigParams
- );
-
-VOID
-ApUtilTransmitBuffer (
- IN UINT8 Socket,
- IN UINT8 Core,
- IN AP_DATA_TRANSFER *BufferInfo,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-ApUtilReceiveBuffer (
- IN UINT8 Socket,
- IN UINT8 Core,
- IN OUT AP_DATA_TRANSFER *BufferInfo,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-GetLocalApicIdForCore (
- IN UINT32 TargetSocket,
- IN UINT32 TargetCore,
- OUT UINT32 *LocalApicId,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-ApUtilRunCodeOnAllLocalCoresAtEarly (
- IN AP_TASK *TaskPtr,
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr
- );
-
-VOID
-RelinquishControlOfAllAPs (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif /* _CPU_APIC_UTILITIES_H_ */
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/cpuBist.c b/src/vendorcode/amd/agesa/Proc/CPU/cpuBist.c
deleted file mode 100644
index dbdd4b9..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/cpuBist.c
+++ /dev/null
@@ -1,173 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU BIST Status Check Implementation.
- *
- * Implement CPU BIST Status checking
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "GeneralServices.h"
-#include "cpuServices.h"
-#include "cpuApicUtilities.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-#define FILECODE PROC_CPU_CPUBIST_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-UINT32
-STATIC
-GetBistResults (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
- /*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
- /*---------------------------------------------------------------------------------------*/
- /**
- *
- * This function checks the status of BIST and places the error status in the event log
- * if there are any errors
- *
- * @param[in] StdHeader Header for library and services
- *
- * @retval AGESA_SUCCESS No BIST errors have been logged.
- * @retval AGESA_ALERT BIST errors have been detected and added to the
- * event log.
- */
-AGESA_STATUS
-CheckBistStatus (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Socket;
- UINT32 Core;
- UINT32 BscSocket;
- UINT32 BscCore;
- UINT32 NumberOfSockets;
- UINT32 NumberOfCores;
- UINT32 Ignored;
- UINT32 ReturnCode;
- AGESA_STATUS IgnoredSts;
- AGESA_STATUS AgesaStatus;
- AP_TASK TaskPtr;
-
- // Make sure that Standard Header is valid
- ASSERT (StdHeader != NULL);
- ASSERT (IsBsp (StdHeader, &IgnoredSts));
-
- AgesaStatus = AGESA_SUCCESS;
-
- // Get the BscSocket, BscCore and NumberOfSockets in the system
- IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredSts);
- NumberOfSockets = GetPlatformNumberOfSockets ();
-
- // Setup TaskPtr struct to execute routine on APs
- TaskPtr.FuncAddress.PfApTaskO = GetBistResults;
- TaskPtr.DataTransfer.DataSizeInDwords = 0;
- TaskPtr.ExeFlags = TASK_HAS_OUTPUT | WAIT_FOR_CORE;
-
- for (Socket = 0; Socket < NumberOfSockets; Socket++) {
- if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
- for (Core = 0; Core < NumberOfCores; Core++) {
- if ((Socket != BscSocket) || (Core != BscCore)) {
- ReturnCode = ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)Core, &TaskPtr, StdHeader);
- } else {
- ReturnCode = TaskPtr.FuncAddress.PfApTaskO (StdHeader);
- }
-
- // If BIST value is non-zero, add to BSP's event log
- if (ReturnCode != 0) {
- IDS_HDT_CONSOLE (CPU_TRACE, " BIST failure: socket %d core %d, status = 0x%x\n", Socket, Core, ReturnCode);
- AgesaStatus = AGESA_ALERT;
- PutEventLog (AGESA_ALERT,
- CPU_EVENT_BIST_ERROR,
- ReturnCode, Socket, Core, 0, StdHeader);
- }
- }
- }
- }
-
- return AgesaStatus;
-}
-
-/*----------------------------------------------------------------------------------------
- * L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
-*/
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * Reads the lower 32 bits of the BIST register
- *
- * @param[in] StdHeader Header for library and services
- *
- * @retval Value of the BIST register
-*/
-UINT32
-STATIC
-GetBistResults (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 BistResults;
-
- // Read MSRC001_0060 BIST Results Register
- LibAmdMsrRead (MSR_BIST, &BistResults, StdHeader);
-
- return (UINT32) (BistResults & 0xFFFFFFFF);
-}
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/cpuBrandId.c b/src/vendorcode/amd/agesa/Proc/CPU/cpuBrandId.c
deleted file mode 100644
index 0db12af..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/cpuBrandId.c
+++ /dev/null
@@ -1,309 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU BrandId related functions.
- *
- * Contains code that provides CPU BrandId information
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 37640 $ @e \$Date: 2010-09-08 23:01:59 +0800 (Wed, 08 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "OptionPstate.h"
-#include "cpuRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuEarlyInit.h"
-#include "cpuRegisters.h"
-#include "heapManager.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-#define FILECODE PROC_CPU_CPUBRANDID_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-CONST CHAR8 ROMDATA strEngSample[] = "AMD Engineering Sample";
-CONST CHAR8 ROMDATA strTtkSample[] = "AMD Thermal Test Kit";
-CONST CHAR8 ROMDATA strUnknown[] = "AMD Processor Model Unknown";
-
-CONST AMD_CPU_BRAND ROMDATA EngSample_Str = {0, 0, 0, SOCKET_IGNORE, strEngSample, sizeof (strEngSample)};
-CONST AMD_CPU_BRAND ROMDATA TtkSample_Str = {0, 1, 0, SOCKET_IGNORE, strTtkSample, sizeof (strTtkSample)};
-CONST AMD_CPU_BRAND ROMDATA Dflt_Str1 = {0, 0, 0, SOCKET_IGNORE, strUnknown, sizeof (strUnknown)};
-CONST AMD_CPU_BRAND ROMDATA Dflt_Str2 = {0, 0, 0, SOCKET_IGNORE, DR_NO_STRING, DR_NO_STRING};
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Program BrandID registers (CPUIDNameStringPtr[0-5])
- *
- * This function determines the appropriate brand string for the executing
- * core, and programs the namestring MSRs.
- *
- * @param[in,out] StdHeader Config handle for library and services.
- *
- */
-VOID
-SetBrandIdRegisters (
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 SocketIndex;
- UINT8 SuffixStatus;
- UINT8 TableElements;
- UINT8 TableEntryCount;
- UINT8 TableEntryIndex;
- CHAR8 TempChar;
- CHAR8 *NameStringPtr;
- CHAR8 *SuffixStringPtr;
- CHAR8 *BrandStringPtr;
- CHAR8 *TempNameCharPtr;
- UINT32 MsrIndex;
- UINT32 Quotient;
- UINT32 Remainder;
- UINT64 *MsrNameStringPtrPtr;
- CPUID_DATA CpuId;
- CPU_LOGICAL_ID CpuLogicalId;
- CPU_BRAND_TABLE *SocketTableEntry;
- CPU_BRAND_TABLE **SocketTableEntry1;
- AMD_CPU_BRAND *SocketTablePtr;
- AMD_CPU_BRAND_DATA Data;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
-
- SuffixStatus = 0;
- FamilySpecificServices = NULL;
- SocketTablePtr = NULL;
- SocketTableEntry = NULL;
-
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
- // Step1: Allocate 48 bytes from Heap space
- AllocHeapParams.RequestedBufferSize = CPU_BRAND_ID_LENGTH;
- AllocHeapParams.BufferHandle = AMD_BRAND_ID_BUFFER_HANDLE;
- AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
- if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
- // Clear NameBuffer
- BrandStringPtr = (CHAR8 *) AllocHeapParams.BufferPtr;
- LibAmdMemFill (BrandStringPtr, 0, CPU_BRAND_ID_LENGTH, StdHeader);
- } else {
- PutEventLog (
- AGESA_ERROR,
- CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE,
- 0, 0, 0, 0, StdHeader
- );
- return;
- }
-
- // Step2: Get brandid from model number and model string
- LibAmdCpuidRead (AMD_CPUID_FMF, &CpuId, StdHeader);
-
- // Step3: Figure out Socket/Page/Model/String1/String2/Core Number
- Data.String2 = (UINT8) (CpuId.EBX_Reg & 0x0f);
- Data.Model = (UINT8) ((CpuId.EBX_Reg >> 4) & 0x7f);
- Data.String1 = (UINT8) ((CpuId.EBX_Reg >> 11) & 0x0f);
- Data.Page = (UINT8) ((CpuId.EBX_Reg >> 15) & 0x01);
- Data.Socket = (UINT8) ((CpuId.EBX_Reg >> 28) & 0x0f);
- Data.Cores = FamilySpecificServices->GetNumberOfCoresForBrandstring (FamilySpecificServices, StdHeader);
-
- // Step4: If NN = 0, we have an engineering sample, no suffix; then jump to Step6
- if (Data.Model == 0) {
- if (Data.Page == 0) {
- SocketTablePtr = (AMD_CPU_BRAND *)&EngSample_Str;
- } else {
- SocketTablePtr = (AMD_CPU_BRAND *)&TtkSample_Str;
- }
- } else {
-
- // Model is not equal to zero, so decrement it
- // For family 10 if PkgType[3:0] is greater than or equal to 2h and families >= 12h
- GetLogicalIdOfCurrentCore (&CpuLogicalId, StdHeader);
- if ((((CpuLogicalId.Family & AMD_FAMILY_10) != 0) && (Data.Socket >= DR_SOCKET_S1G3)) ||
- ((CpuLogicalId.Family & AMD_FAMILY_GE_12) != 0)) {
- Data.Model--;
- }
-
- // Step5: Search for String1 (there can be only 1)
- FamilySpecificServices->GetBrandString1 (FamilySpecificServices, (VOID **) &SocketTableEntry, &TableEntryCount, StdHeader);
- SocketTableEntry1 = (CPU_BRAND_TABLE **) SocketTableEntry;
- for (TableEntryIndex = 0; ((TableEntryIndex < TableEntryCount)
- && (SuffixStatus == 0)); TableEntryIndex++, SocketTableEntry1++) {
- if (*SocketTableEntry1 == NULL) {
- break;
- }
- SocketTablePtr = (AMD_CPU_BRAND *) (*SocketTableEntry1)->Table;
- TableElements = (*SocketTableEntry1)->NumberOfEntries;
- for (SocketIndex = 0; (SocketIndex < TableElements)
- && SuffixStatus == 0; SocketIndex++) {
- if ((SocketTablePtr->Page == Data.Page) &&
- (SocketTablePtr->Index == Data.String1) &&
- (SocketTablePtr->Socket == Data.Socket) &&
- (SocketTablePtr->Cores == Data.Cores)) {
- SuffixStatus = 1;
- } else {
- SocketTablePtr++;
- }
- }
- }
- if (SuffixStatus == 0) {
- SocketTablePtr = (AMD_CPU_BRAND *)&Dflt_Str1; // We did not find one, make 'Unknown'
- }
- }
-
- // Step6: Copy String into NameBuffer
- // We now have data structure pointing to correct type in (*SocketTablePtr)
- LibAmdMemCopy (BrandStringPtr,
- (CHAR8 *)SocketTablePtr->Stringstart,
- SocketTablePtr->Stringlength,
- StdHeader);
-
- // Step7: Get suffix, determine addition to BRANDSPEED
- if (SuffixStatus != 0) {
- // Turn our value into a decimal string
- // We have a value like 37d which we need to turn into '3' '7'
- // Divide by 10, store remainder as an ASCII char on stack, repeat until Quotient is 0
- NameStringPtr = BrandStringPtr + SocketTablePtr->Stringlength - 1;
- TempNameCharPtr = NameStringPtr;
- Quotient = Data.Model;
- do {
- Remainder = Quotient % 10;
- Quotient = Quotient / 10;
- *TempNameCharPtr++ = (CHAR8) (Remainder + '0'); // Put suffix into our NameBuffer
- } while (Quotient != 0);
- if (Data.Model < 10) {
- *TempNameCharPtr++ = '0';
- }
-
- // Step8: Reverse the string sequence and copy into NameBuffer
- SuffixStringPtr = TempNameCharPtr--;
- while (NameStringPtr < TempNameCharPtr) {
- TempChar = *NameStringPtr;
- *NameStringPtr = *TempNameCharPtr;
- *TempNameCharPtr = TempChar;
- NameStringPtr++;
- TempNameCharPtr--;
- }
-
- // Step9: Search for String2
- SuffixStatus = 0;
- FamilySpecificServices->GetBrandString2 (FamilySpecificServices, (VOID **) &SocketTableEntry, &TableEntryCount, StdHeader);
- SocketTableEntry1 = (CPU_BRAND_TABLE **) SocketTableEntry;
- for (TableEntryIndex = 0; ((TableEntryIndex < TableEntryCount)
- && (SuffixStatus == 0)); TableEntryIndex++, SocketTableEntry1++) {
- if (*SocketTableEntry1 == NULL) {
- break;
- }
- SocketTablePtr = (AMD_CPU_BRAND *) (*SocketTableEntry1)->Table;
- TableElements = (*SocketTableEntry1)->NumberOfEntries;
- for (SocketIndex = 0; (SocketIndex < TableElements)
- && SuffixStatus == 0; SocketIndex++) {
- if ((SocketTablePtr->Page == Data.Page) &&
- (SocketTablePtr->Index == Data.String2) &&
- (SocketTablePtr->Socket == Data.Socket) &&
- (SocketTablePtr->Cores == Data.Cores)) {
- SuffixStatus = 1;
- } else {
- SocketTablePtr++;
- }
- }
- }
- if (SuffixStatus == 0) {
- SocketTablePtr = (AMD_CPU_BRAND *)&Dflt_Str2;
- }
-
- // Step10: Copy String2 into our NameBuffer
- if (SocketTablePtr->Stringlength != 0) {
- LibAmdMemCopy (SuffixStringPtr,
- (CHAR8 *)SocketTablePtr->Stringstart,
- SocketTablePtr->Stringlength,
- StdHeader);
- }
- }
-
- // Step11: Put values into name MSRs, Always write the full 48 bytes
- MsrNameStringPtrPtr = (UINT64 *) BrandStringPtr;
- for (MsrIndex = MSR_CPUID_NAME_STRING0; MsrIndex <= MSR_CPUID_NAME_STRING5; MsrIndex++) {
- LibAmdMsrWrite (MsrIndex, MsrNameStringPtrPtr, StdHeader);
- MsrNameStringPtrPtr++;
- }
- HeapDeallocateBuffer (AMD_BRAND_ID_BUFFER_HANDLE, StdHeader);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Program BrandID registers (CPUIDNameStringPtr[0-5])
- *
- * This function acts as a wrapper for calling the SetBrandIdRegisters
- * routine at AmdInitEarly.
- *
- * @param[in] FamilyServices The current Family Specific Services.
- * @param[in] EarlyParams Service parameters.
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-SetBrandIdRegistersAtEarly (
- IN CPU_SPECIFIC_SERVICES *FamilyServices,
- IN AMD_CPU_EARLY_PARAMS *EarlyParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_TESTPOINT (TpProcCpuSetBrandID, StdHeader);
- SetBrandIdRegisters (StdHeader);
-}
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/cpuEarlyInit.c b/src/vendorcode/amd/agesa/Proc/CPU/cpuEarlyInit.c
deleted file mode 100644
index d5e27f5..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/cpuEarlyInit.c
+++ /dev/null
@@ -1,404 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU Reset API, and related functions.
- *
- * Contains code that initialized the CPU after early reset.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 35636 $ @e \$Date: 2010-07-28 09:24:55 +0800 (Wed, 28 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuServices.h"
-#include "GeneralServices.h"
-#include "Table.h"
-#include "cpuApicUtilities.h"
-#include "cpuEarlyInit.h"
-#include "Topology.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuFeatures.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_CPUEARLYINIT_FILECODE
-
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-extern BUILD_OPT_CFG UserOptions;
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-VOID
-STATIC
-GetPerformEarlyFlag (
- IN OUT UINT32 *PerformEarlyFlag,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-/*------------------------------------------------------------------------------------*/
-/**
- * Initializer routine that will be invoked by AmdCpuEarly to initialize the input
- * structure for the Cpu Init @ Early routine.
- *
- * @param[in] StdHeader Opaque handle to standard config header
- * @param[in] PlatformConfig Config handle for platform specific information
- * @param[in,out] CpuEarlyParamsPtr Service Interface structure to initialize.
- *
- * @retval AGESA_SUCCESS Always Succeeds
- */
-VOID
-AmdCpuEarlyInitializer (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN OUT AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr
- )
-{
- ASSERT (CpuEarlyParamsPtr != NULL);
-
- CpuEarlyParamsPtr->MemInitPState = (UINT8) UserOptions.CfgMemInitPstate;
- CpuEarlyParamsPtr->PlatformConfig = *PlatformConfig;
-}
-/*---------------------------------------------------------------------------------------*/
-/**
- * Performs CPU related initialization at the early entry point
- *
- * This function performs a large list of initialization items. These items
- * include:
- *
- * -1 local APIC initialization
- * -2 MSR table initialization
- * -3 PCI table initialization
- * -4 HT Phy PCI table initialization
- * -5 microcode patch loading
- * -6 namestring determination/programming
- * -7 AP initialization
- * -8 power management initialization
- * -9 core leveling
- *
- * This routine must be run by all cores in the system. Please note that
- * all APs that enter will never exit.
- *
- * @param[in] StdHeader Config handle for library and services
- * @param[in] PlatformConfig Config handle for platform specific information
- *
- * @retval AGESA_SUCCESS
- *
- */
-AGESA_STATUS
-AmdCpuEarly (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN PLATFORM_CONFIGURATION *PlatformConfig
- )
-{
- UINT8 WaitStatus;
- UINT8 i;
- UINT8 StartCore;
- UINT8 EndCore;
- UINT32 NodeNum;
- UINT32 PrimaryCore;
- UINT32 SocketNum;
- UINT32 ModuleNum;
- UINT32 HighCore;
- UINT32 ApHeapIndex;
- UINT32 CurrentPerformEarlyFlag;
- AP_WAIT_FOR_STATUS WaitForStatus;
- AGESA_STATUS Status;
- AGESA_STATUS CalledStatus;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
- AMD_CPU_EARLY_PARAMS CpuEarlyParams;
- S_PERFORM_EARLY_INIT_ON_CORE *EarlyTableOnCore;
-
- Status = AGESA_SUCCESS;
- CalledStatus = AGESA_SUCCESS;
-
- AmdCpuEarlyInitializer (StdHeader, PlatformConfig, &CpuEarlyParams);
-
- IDS_OPTION_HOOK (IDS_CPU_Early_Override, &CpuEarlyParams, StdHeader);
-
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
- EarlyTableOnCore = NULL;
- FamilySpecificServices->GetEarlyInitOnCoreTable (FamilySpecificServices, &EarlyTableOnCore, &CpuEarlyParams, StdHeader);
- if (EarlyTableOnCore != NULL) {
- GetPerformEarlyFlag (&CurrentPerformEarlyFlag, StdHeader);
- for (i = 0; EarlyTableOnCore[i].PerformEarlyInitOnCore != NULL; i++) {
- if ((EarlyTableOnCore[i].PerformEarlyInitFlag & CurrentPerformEarlyFlag) != 0) {
- IDS_HDT_CONSOLE (CPU_TRACE, " Perform core init step %d\n", i);
- EarlyTableOnCore[i].PerformEarlyInitOnCore (FamilySpecificServices, &CpuEarlyParams, StdHeader);
- }
- }
- }
-
- // B S P C O D E T O I N I T I A L I Z E A Ps
- // -------------------------------------------------------
- // -------------------------------------------------------
- // IMPORTANT: Here we determine if we are BSP or AP
- if (IsBsp (StdHeader, &CalledStatus)) {
-
- // Even though the bsc does not need to send itself a heap index, this sequence performs other important initialization.
- // Use '0' as a dummy heap index value.
- GetSocketModuleOfNode (0, &SocketNum, &ModuleNum, StdHeader);
- GetCpuServicesOfSocket (SocketNum, &FamilySpecificServices, StdHeader);
- FamilySpecificServices->SetApCoreNumber (FamilySpecificServices, SocketNum, ModuleNum, 0, StdHeader);
- FamilySpecificServices->TransferApCoreNumber (FamilySpecificServices, StdHeader);
-
- // Clear BSP's Status Byte
- ApUtilWriteControlByte (CORE_ACTIVE, StdHeader);
-
- NodeNum = 0;
- ApHeapIndex = 1;
- while (NodeNum < MAX_NODES &&
- GetSocketModuleOfNode (NodeNum, &SocketNum, &ModuleNum, StdHeader)) {
- GetCpuServicesOfSocket (SocketNum, &FamilySpecificServices, StdHeader);
- GetGivenModuleCoreRange (SocketNum, ModuleNum, &PrimaryCore, &HighCore, StdHeader);
- if (NodeNum == 0) {
- StartCore = (UINT8) PrimaryCore + 1;
- } else {
- StartCore = (UINT8) PrimaryCore;
- }
-
- EndCore = (UINT8) HighCore;
- for (i = StartCore; i <= EndCore; i++) {
- FamilySpecificServices->SetApCoreNumber (FamilySpecificServices, SocketNum, ModuleNum, ApHeapIndex, StdHeader);
- IDS_HDT_CONSOLE (CPU_TRACE, " Launch socket %d core %d\n", SocketNum, i);
- if (FamilySpecificServices->LaunchApCore (FamilySpecificServices, SocketNum, ModuleNum, i, PrimaryCore, StdHeader)) {
- IDS_HDT_CONSOLE (CPU_TRACE, " Waiting for socket %d core %d\n", SocketNum, i);
- WaitStatus = CORE_IDLE;
- WaitForStatus.Status = &WaitStatus;
- WaitForStatus.NumberOfElements = 1;
- WaitForStatus.RetryCount = WAIT_INFINITELY;
- WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY;
- ApUtilWaitForCoreStatus ((UINT8) SocketNum,
- i,
- &WaitForStatus,
- StdHeader
- );
- ApHeapIndex++;
- }
- }
- NodeNum++;
- }
-
- // B S P P h a s e - 1 E N D
- AGESA_TESTPOINT (TpProcCpuBeforePMFeatureInit, StdHeader);
- IDS_HDT_CONSOLE (CPU_TRACE, " Dispatch CPU features before early power mgmt init\n");
- CalledStatus = DispatchCpuFeatures (CPU_FEAT_BEFORE_PM_INIT, PlatformConfig, StdHeader);
- if (CalledStatus > Status) {
- Status = CalledStatus;
- }
-
- AGESA_TESTPOINT (TpProcCpuPowerMgmtInit, StdHeader);
- CalledStatus = PmInitializationAtEarly (&CpuEarlyParams, StdHeader);
- if (CalledStatus > Status) {
- Status = CalledStatus;
- }
-
- AGESA_TESTPOINT (TpProcCpuEarlyFeatureInit, StdHeader);
- IDS_HDT_CONSOLE (CPU_TRACE, " Dispatch CPU features after early power mgmt init\n");
- CalledStatus = DispatchCpuFeatures (CPU_FEAT_AFTER_PM_INIT, PlatformConfig, StdHeader);
-
- IDS_OPTION_HOOK (IDS_BEFORE_AP_EARLY_HALT, &CpuEarlyParams, StdHeader);
-
- // Sleep all APs
- IDS_HDT_CONSOLE (CPU_TRACE, " Halting all APs\n");
- ApUtilWriteControlByte (CORE_IDLE_HLT, StdHeader);
- } // if (amdIsBsp()) - END
- else {
- ApEntry (StdHeader, &CpuEarlyParams);
- }
-
- if (CalledStatus > Status) {
- Status = CalledStatus;
- }
-
- return (Status);
-}
-
-/*---------------------------------------------------------------------------------------
- * L O C A L F U N C T I O N S
- *---------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Initialize Machine Check Architecture registers
- *
- * This function initializes the MCA MSRs. On cold reset, these registers
- * have an invalid data that must be cleared on all cores.
- *
- * @param[in] StdHeader Config handle for library and services
- *
- *---------------------------------------------------------------------------------------
- */
-VOID
-McaInitialization (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT16 TempVar16_a;
- UINT32 MsrAddress;
- UINT64 MsrData;
- CPUID_DATA CpuIdDataStruct;
-
- if (!(IsWarmReset (StdHeader))) {
- // Run CPUID to verify that the processor supports MCE and MCA
- // i.e. edx[7], and edx[14]
- // CPUID_MODEL = 1
- LibAmdCpuidRead (1, &CpuIdDataStruct, StdHeader);
- if ((CpuIdDataStruct.EDX_Reg & 0x4080) != 0) {
- // Check to see if the MCG_CTL_P bit is set
- // MCG = Global Machine Check Exception Reporting Control Register
- LibAmdMsrRead (MSR_MCG_CAP, &MsrData, StdHeader);
- if ((MsrData & MCG_CTL_P) != 0) {
- TempVar16_a = (UINT16) ((MsrData & 0x000000FF) << 2);
- TempVar16_a += MSR_MC0_CTL;
-
- // Initialize the data
- MsrData = 0;
- for (MsrAddress = MSR_MC0_CTL; MsrAddress < TempVar16_a; MsrAddress++) {
- LibAmdMsrWrite (MsrAddress, &MsrData, StdHeader);
- }
- }
- }
- }
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Initialize Machine Check Architecture registers
- *
- * This function acts as a wrapper for calling the McaInitialization
- * routine at AmdInitEarly.
- *
- * @param[in] FamilyServices The current Family Specific Services.
- * @param[in] EarlyParams Service parameters.
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-McaInitializationAtEarly (
- IN CPU_SPECIFIC_SERVICES *FamilyServices,
- IN AMD_CPU_EARLY_PARAMS *EarlyParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- McaInitialization (StdHeader);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Runs the given task on all cores (including self) on the socket of the executing
- * core 0.
- *
- * This function is used to invoke all APs on the socket of the executing core 0 to
- * run a specified AGESA procedure.
- *
- * @param[in] TaskPtr Function descriptor
- * @param[in] StdHeader Config handle for library and services
- * @param[in] CpuEarlyParamsPtr Required input parameters for early CPU initialization
- *
- */
-VOID
-ApUtilRunCodeOnAllLocalCoresAtEarly (
- IN AP_TASK *TaskPtr,
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr
- )
-{
- UINT32 Core;
- UINT32 Socket;
- UINT32 IgnoredModule;
- UINT32 IgnoredCore;
- UINT32 ActiveCores;
- AGESA_STATUS IgnoredSts;
-
- IdentifyCore (StdHeader, &Socket, &IgnoredModule, &IgnoredCore, &IgnoredSts);
- GetActiveCoresInCurrentSocket (&ActiveCores, StdHeader);
-
- for (Core = 1; Core < (UINT8) ActiveCores; ++Core) {
- ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)Core, TaskPtr, StdHeader);
- }
- ApUtilTaskOnExecutingCore (TaskPtr, StdHeader, (VOID *) CpuEarlyParamsPtr);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Get current condition, such as warm/cold reset, to determine if related function
- * need to be performed at early stage
- *
- * @param[in, out] PerformEarlyFlag Perform early flag.
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-STATIC
-GetPerformEarlyFlag (
- IN OUT UINT32 *PerformEarlyFlag,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- *PerformEarlyFlag = 0;
- if (IsWarmReset (StdHeader)) {
- *PerformEarlyFlag |= PERFORM_EARLY_WARM_RESET;
- } else {
- *PerformEarlyFlag |= PERFORM_EARLY_COLD_BOOT;
- }
- return;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/cpuEarlyInit.h b/src/vendorcode/amd/agesa/Proc/CPU/cpuEarlyInit.h
deleted file mode 100644
index 95c26d0..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/cpuEarlyInit.h
+++ /dev/null
@@ -1,250 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU Reset API, and related functions and structures.
- *
- * Contains code that initialized the CPU after early reset.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 36567 $ @e \$Date: 2010-08-21 02:35:15 +0800 (Sat, 21 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPU_EARLY_INIT_H_
-#define _CPU_EARLY_INIT_H_
-
-
-/*---------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *---------------------------------------------------------------------------------------
- */
-AGESA_FORWARD_DECLARATION (CPU_CORE_LEVELING_FAMILY_SERVICES);
-
-/*---------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *---------------------------------------------------------------------------------------
- */
-//----------------------------------------------------------------------------
-// CPU BRAND ID TYPEDEFS, STRUCTURES, ENUMS
-//
-//----------------------------------------------------------------------------
-#define CPU_BRAND_ID_LENGTH 48 // Total number of characters supported
-#define LOW_NODE_DEVICEID 24
-#define NB_CAPABILITIES 0xE8 //Function 3 Registers
-//----------------------------------------------------------------------------
-// CPU MICROCODE PATCH TYPEDEFS, STRUCTURES, ENUMS
-//
-//----------------------------------------------------------------------------
-/* All lengths are in bytes */
-#define MICROCODE_TRIADE_SIZE 28
-#define MICROCODE_HEADER_LENGTH 64
-
-/* Offsets in UCODE PATCH Header */
-/* Note: Header is 64 bytes */
-#define DATE_CODE_OFFSET 0 // 4 bytes
-#define PATCH_ID 4 // 4 bytes
-#define MICROCODE_PATH_DATA_ID 8 // 2 bytes
-#define MICROCODE_PATCH_DATA_LENGTH 10 // 1 byte
-#define MICROCODE_PATCH_DATA_CHECKSUM 12 // 4 bytes
-#define CHIPSET_1_DEVICE_ID 16 // 4 bytes
-#define CHIPSET_2_DEVICE_ID 20 // 4 bytes
-#define PROCESSOR_REV_ID 24 // 2 bytes
-#define CHIPSET_1_REV_ID 26 // 1 byte
-#define CHIPSET_2_REV_ID 27 // 1 byte
-
-#define MICROCODE_PATCH_2K_SIZE 2048
-#define MICROCODE_PATCH_4K_SIZE 4096
-/*---------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *---------------------------------------------------------------------------------------
- */
-//----------------------------------------------------------------------------
-// CPU BRAND ID TYPEDEFS, STRUCTURES, ENUMS
-//
-//----------------------------------------------------------------------------
-/// A structure representing BrandId[15:0] from
-/// CPUID Fn8000_0001_EBX
-typedef struct {
- UINT8 String1:4; ///< An index to a string value used to create the name string
- UINT8 String2:4; ///< An index to a string value used to create the name string
- UINT8 Page:1; ///< An index to the appropriate page for the String1, String2, and Model values
- UINT8 Model:7; ///< A field used to create the model number in the name string
- UINT8 Socket:4; ///< Specifies the package type
- UINT8 Cores:4; ///< Identifies how many physical cores are present
-} AMD_CPU_BRAND_DATA;
-
-/// A structure containing string1 and string2 values
-/// as well as information pertaining to their usage
-typedef struct {
- IN UINT8 Cores; ///< Appropriate number of physical cores
- IN UINT8 Page; ///< This string's page number
- IN UINT8 Index; ///< String index
- IN UINT8 Socket; ///< Package type information
- IN CONST CHAR8 *Stringstart; ///< The literal string
- IN UINT8 Stringlength; ///< Number of characters in the string
-} AMD_CPU_BRAND;
-
-/// An entire CPU brand table.
-typedef struct {
- UINT8 NumberOfEntries; ///< The number of entries in the table.
- CONST AMD_CPU_BRAND *Table; ///< The table entries.
-} CPU_BRAND_TABLE;
-
-//----------------------------------------------------------------------------
-// CPU MICROCODE PATCH TYPEDEFS, STRUCTURES, ENUMS
-//
-//----------------------------------------------------------------------------
-/// Microcode patch field definitions
-typedef struct {
- UINT32 DateCode; ///< Date of patch creation
- UINT32 PatchID; ///< Patch level
- UINT16 MicrocodePatchDataID; ///< Internal use only
- UINT8 MicrocodePatchDataLength; ///< Internal use only
- UINT8 InitializationFlag; ///< Internal use only
- UINT32 MicrocodePatchDataChecksum; ///< Doubleword sum of data block
- UINT32 Chipset1DeviceID; ///< Device ID of 1st HT device to match
- UINT32 Chipset2DeviceID; ///< Device ID of 2nd HT device to match
- UINT16 ProcessorRevisionID; ///< Equivalent ID
- UINT8 Chipset1RevisionID; ///< Revision level of 1st HT device to match
- UINT8 Chipset2RevisionID; ///< Revision level of 2nd HT device to match
- UINT8 BiosApiRevision; ///< BIOS INT 15 API revision required
- UINT8 Reserved1[3]; ///< Reserved
- UINT32 MatchRegister0; ///< Internal use only
- UINT32 MatchRegister1; ///< Internal use only
- UINT32 MatchRegister2; ///< Internal use only
- UINT32 MatchRegister3; ///< Internal use only
- UINT32 MatchRegister4; ///< Internal use only
- UINT32 MatchRegister5; ///< Internal use only
- UINT32 MatchRegister6; ///< Internal use only
- UINT32 MatchRegister7; ///< Internal use only
- UINT8 PatchDataBlock[896]; ///< Raw patch data
- UINT8 Reserved2[896]; ///< Reserved
- UINT8 X86CodePresent; ///< Boolean to determine if executable code exists
- UINT8 X86CodeEntry[191]; ///< Code to execute if X86CodePresent != 0
-} MICROCODE_PATCH;
-
-/// Two kilobyte array containing the raw
-/// microcode patch binary data
-typedef struct {
- IN UINT8 MicrocodePatches[MICROCODE_PATCH_2K_SIZE]; ///< 2k UINT8 elements
-} MICROCODE_PATCHES;
-
-/// Four kilobyte array containing the raw
-/// microcode patch binary data
-typedef struct {
- IN UINT8 MicrocodePatches[MICROCODE_PATCH_4K_SIZE]; ///< 4k UINT8 elements
-} MICROCODE_PATCHES_4K;
-
-/**
- * Set down core register
- *
- * @CpuServiceInstances
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] Socket Socket ID.
- * @param[in] Module Module ID in socket.
- * @param[in] LeveledCores Number of core.
- * @param[in] CoreLevelMode Core level mode.
- * @param[in] StdHeader Header for library and services.
- *
- * @retval TRUE Down Core register is updated.
- * @retval FALSE Down Core register is not updated.
- */
-typedef BOOLEAN (F_CPU_SET_DOWN_CORE_REGISTER) (
- IN CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices,
- IN UINT32 *Socket,
- IN UINT32 *Module,
- IN UINT32 *LeveledCores,
- IN CORE_LEVELING_TYPE CoreLevelMode,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a method
-typedef F_CPU_SET_DOWN_CORE_REGISTER *PF_CPU_SET_DOWN_CORE_REGISTER;
-
-/**
- * Provide the interface to the Core Leveling Family Specific Services.
- *
- * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
- * Each supported Family must provide an implementation for all methods in this interface, even if the
- * implementation is a CommonReturn().
- */
-struct _CPU_CORE_LEVELING_FAMILY_SERVICES { // See Forward Declaration above
- UINT16 Revision; ///< Interface version
- // Public Methods.
- PF_CPU_SET_DOWN_CORE_REGISTER SetDownCoreRegister; ///< Method: Set down core register.
-};
-
-//----------------------------------------------------------------------------
-// CPU PERFORM EARLY INIT ON CORE
-//
-//----------------------------------------------------------------------------
-/// Flag definition.
-#define PERFORM_EARLY_WARM_RESET 0x1 // bit 0 --- the related function needs to be run if it's warm reset
-#define PERFORM_EARLY_COLD_BOOT 0x2 // bit 1 --- the related function needs to be run if it's cold boot
-
-#define PERFORM_EARLY_ANY_CONDITION 0xFFFFFFFF // the related function always needs to be run
-/*---------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *---------------------------------------------------------------------------------------
- */
-
-// These are P U B L I C functions, used by IBVs
-AGESA_STATUS
-AmdCpuEarly (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN PLATFORM_CONFIGURATION *PlatformConfig
- );
-
-// These are P U B L I C functions, used by AGESA
-VOID
-SetBrandIdRegisters (
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-PmInitializationAtEarly (
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-BOOLEAN
-LoadMicrocodePatch (
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-#endif // _CPU_EARLY_INIT_H_
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/cpuEnvInit.h b/src/vendorcode/amd/agesa/Proc/CPU/cpuEnvInit.h
deleted file mode 100644
index 4da3bb7..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/cpuEnvInit.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU Env Init API functions Prototypes.
- *
- * Contains code for doing any Env CPU initialization
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPU_ENV_INIT_H_
-#define _CPU_ENV_INIT_H_
-
-/*----------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *----------------------------------------------------------------------------------------
- */
-// HobTransfer
-AGESA_STATUS
-CopyHeapToMainRamAtPost (
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif // _CPU_ENV_INIT_H_
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/cpuEventLog.c b/src/vendorcode/amd/agesa/Proc/CPU/cpuEventLog.c
deleted file mode 100644
index 97fd052..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/cpuEventLog.c
+++ /dev/null
@@ -1,399 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Event (Error) Log APIs, and related functions.
- *
- * Contains code that records and returns the events and errors.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "heapManager.h"
-#include "GeneralServices.h"
-#include "Ids.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_CPUEVENTLOG_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-#define TOTAL_EVENT_LOG_BUFFERS 16
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/**
- * A wrapper for each Event Log entry.
- */
-typedef struct {
- UINT16 Count; ///< Entry number
- AGESA_EVENT AgesaEvent; ///< The entry itself.
-} AGESA_EVENT_STRUCT;
-
-/**
- * The Event Log.
- */
-typedef struct {
- UINT16 ReadWriteFlag; ///< Read Write flag.
- UINT16 Count; ///< The total number of active entries.
- UINT16 ReadRecordPtr; ///< The next entry to read.
- UINT16 WriteRecordPtr; ///< The next entry to write.
- AGESA_EVENT_STRUCT AgesaEventStruct[TOTAL_EVENT_LOG_BUFFERS]; ///< The entries.
-} AGESA_STRUCT_BUFFER;
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-VOID
-STATIC
-GetEventLogHeapPointer (
- OUT AGESA_STRUCT_BUFFER **EventLog,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * External AGESA interface to read an Event from the Event Log.
- *
- * This is the implementation of the external AGESA interface entry, as a thin wrapper
- * around the internal log services.
- *
- * @param[in] Event The event class, id, and any associated data.
- *
- * @retval AGESA_SUCCESS Always Succeeds.
- */
-AGESA_STATUS
-AmdReadEventLog (
- IN EVENT_PARAMS *Event
- )
-{
- AGESA_EVENT LogEvent;
- AGESA_STATUS Status;
-
- AGESA_TESTPOINT (TpIfAmdReadEventLogEntry, &Event->StdHeader);
-
- ASSERT (Event != NULL);
- Event->StdHeader.HeapBasePtr = HeapGetBaseAddress (&Event->StdHeader);
- Status = GetEventLog (&LogEvent, &Event->StdHeader);
-
- Event->EventClass = LogEvent.EventClass;
- Event->EventInfo = LogEvent.EventInfo;
- Event->DataParam1 = LogEvent.DataParam1;
- Event->DataParam2 = LogEvent.DataParam2;
- Event->DataParam3 = LogEvent.DataParam3;
- Event->DataParam4 = LogEvent.DataParam4;
-
- AGESA_TESTPOINT (TpIfAmdReadEventLogExit, &Event->StdHeader);
- return Status;
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * This function prepares the Event Log for use.
- *
- * Allocate the memory for an event log on the heap. Set the read pointer, write pointer,
- * and count to reflect the log is empty.
- *
- * @param[in] StdHeader Our configuration, for passing to services.
- *
- * @retval AGESA_SUCCESS The event log is initialized.
- * @retval AGESA_ERROR Allocate Heap Buffer returned an error.
- *
- */
-AGESA_STATUS
-EventLogInitialization (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- ALLOCATE_HEAP_PARAMS AllocateHeapParams;
- AGESA_STRUCT_BUFFER *AgesaEventAlloc;
- AGESA_STATUS Status;
-
- AllocateHeapParams.BufferHandle = EVENT_LOG_BUFFER_HANDLE;
- AllocateHeapParams.RequestedBufferSize = sizeof (AGESA_STRUCT_BUFFER);
- AllocateHeapParams.Persist = HEAP_SYSTEM_MEM;
- Status = HeapAllocateBuffer (&AllocateHeapParams, StdHeader);
- AgesaEventAlloc = (AGESA_STRUCT_BUFFER *) AllocateHeapParams.BufferPtr;
- AgesaEventAlloc->Count = 0;
- AgesaEventAlloc->ReadRecordPtr = 0;
- AgesaEventAlloc->WriteRecordPtr = 0;
- AgesaEventAlloc->ReadWriteFlag = 1;
-
- return Status;
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * This function logs AGESA events into the event log.
- *
- * It will put the information in a circular buffer consisting of 16 such log
- * entries. If the buffer gets full, then the next event log entry will be written
- * over the oldest event log entry.
- *
- * @param[in] EventClass The severity of the event, its associated AGESA_STATUS.
- * @param[in] EventInfo Uniquely identifies the event.
- * @param[in] DataParam1 Event specific additional data
- * @param[in] DataParam2 Event specific additional data
- * @param[in] DataParam3 Event specific additional data
- * @param[in] DataParam4 Event specific additional data
- * @param[in] StdHeader Header for library and services
- *
- */
-VOID
-PutEventLog (
- IN AGESA_STATUS EventClass,
- IN UINT32 EventInfo,
- IN UINT32 DataParam1,
- IN UINT32 DataParam2,
- IN UINT32 DataParam3,
- IN UINT32 DataParam4,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT16 Index;
- AGESA_STRUCT_BUFFER *AgesaEventAlloc;
-
- IDS_HDT_CONSOLE (MAIN_FLOW, "\n * %s Event: %08x Data: %x, %x, %x, %x\n\n",
- (EventClass == AGESA_FATAL) ? "FATAL" :
- (EventClass == AGESA_CRITICAL) ? "CRITICAL" :
- (EventClass == AGESA_ERROR) ? "ERROR" :
- (EventClass == AGESA_WARNING) ? "WARNING" :
- (EventClass == AGESA_ALERT) ? "ALERT" :
- (EventClass == AGESA_BOUNDS_CHK) ? "BOUNDS_CHK" :
- (EventClass == AGESA_UNSUPPORTED) ? "UNSUPPORTED" :
- "SUCCESS", EventInfo, DataParam1, DataParam2, DataParam3, DataParam4);
-
- AgesaEventAlloc = NULL;
- GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader);
- ASSERT (AgesaEventAlloc != NULL);
- Index = AgesaEventAlloc->WriteRecordPtr;
-
- // Add the new event log data into a circular buffer
- AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.EventClass = EventClass;
- AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.EventInfo = EventInfo;
- AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam1 = DataParam1;
- AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam2 = DataParam2;
- AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam3 = DataParam3;
- AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam4 = DataParam4;
-
- if ((AgesaEventAlloc->WriteRecordPtr == AgesaEventAlloc->ReadRecordPtr) &&
- (AgesaEventAlloc->ReadWriteFlag == 0)) {
- AgesaEventAlloc->WriteRecordPtr += 1;
- AgesaEventAlloc->ReadRecordPtr += 1;
- if (AgesaEventAlloc->WriteRecordPtr == TOTAL_EVENT_LOG_BUFFERS) {
- AgesaEventAlloc->WriteRecordPtr = 0;
- AgesaEventAlloc->ReadRecordPtr = 0;
- }
- } else {
- AgesaEventAlloc->WriteRecordPtr += 1;
- if (AgesaEventAlloc->WriteRecordPtr == TOTAL_EVENT_LOG_BUFFERS) {
- AgesaEventAlloc->WriteRecordPtr = 0;
- }
- AgesaEventAlloc->ReadWriteFlag = 0;
- }
- AgesaEventAlloc->Count = AgesaEventAlloc->Count + 1;
-
- if (AgesaEventAlloc->Count <= TOTAL_EVENT_LOG_BUFFERS) {
- AgesaEventAlloc->AgesaEventStruct[Index].Count = Index;
- }
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * This function gets event logs from the circular buffer.
- *
- * It will read the oldest entry from the circular buffer and place that information to the structure
- * pointed to by the parameter. The read pointers will be incremented to remove the entry from buffer
- * so that a subsequent call will return the next entry from the buffer. If the buffer is empty the
- * returned log event will have EventInfo zero, which is not a valid event id.
- *
- * @param[out] EventRecord The next log event.
- * @param[in] StdHeader Header for library and services
- *
- * @retval AGESA_SUCCESS Always succeeds.
- *
- */
-AGESA_STATUS
-GetEventLog (
- OUT AGESA_EVENT *EventRecord,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT16 Index;
- AGESA_STRUCT_BUFFER *AgesaEventAlloc;
-
- AgesaEventAlloc = NULL;
-
- GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader);
- ASSERT (AgesaEventAlloc != NULL);
-
- if ((AgesaEventAlloc->ReadRecordPtr == AgesaEventAlloc->WriteRecordPtr) &&
- (AgesaEventAlloc->ReadWriteFlag == 1)) {
- // EventInfo == zero, means no more data.
- LibAmdMemFill (EventRecord, 0, sizeof (AGESA_EVENT), StdHeader);
- } else {
- Index = AgesaEventAlloc->ReadRecordPtr;
- EventRecord->EventClass = AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.EventClass;
- EventRecord->EventInfo = AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.EventInfo;
- EventRecord->DataParam1 = AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam1;
- EventRecord->DataParam2 = AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam2;
- EventRecord->DataParam3 = AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam3;
- EventRecord->DataParam4 = AgesaEventAlloc->AgesaEventStruct[Index].AgesaEvent.DataParam4;
- if (AgesaEventAlloc->ReadRecordPtr == (TOTAL_EVENT_LOG_BUFFERS - 1)) {
- AgesaEventAlloc->ReadRecordPtr = 0;
- } else {
- AgesaEventAlloc->ReadRecordPtr = AgesaEventAlloc->ReadRecordPtr + 1;
- }
- if (AgesaEventAlloc->ReadRecordPtr == AgesaEventAlloc->WriteRecordPtr) {
- AgesaEventAlloc->ReadWriteFlag = 1;
- }
- }
- return (AGESA_SUCCESS);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * This function gets event logs from the circular buffer without flushing the entry.
- *
- * It will read the desired entry from the circular buffer and place that information to the structure
- * pointed to by the parameter. The read pointers will not be incremented to remove the entry from the
- * buffer. If the buffer is empty, or the desired entry does not exist, FALSE will be returned.
- *
- * @param[out] EventRecord The next log event.
- * @param[in] Index Zero-based unread entry index
- * @param[in] StdHeader Header for library and services
- *
- * @retval TRUE Entry exists
- * @retval FALSE Entry does not exist
- *
- */
-BOOLEAN
-PeekEventLog (
- OUT AGESA_EVENT *EventRecord,
- IN UINT16 Index,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT16 ActualIndex;
- UINT16 UnreadEntries;
- AGESA_STRUCT_BUFFER *AgesaEventAlloc;
-
- AgesaEventAlloc = NULL;
-
- GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader);
- ASSERT (AgesaEventAlloc != NULL);
-
- if ((AgesaEventAlloc->ReadRecordPtr == AgesaEventAlloc->WriteRecordPtr) &&
- (AgesaEventAlloc->ReadWriteFlag == 1)) {
- // EventInfo == zero, means no more data.
- return FALSE;
- }
- if (AgesaEventAlloc->ReadRecordPtr < AgesaEventAlloc->WriteRecordPtr) {
- UnreadEntries = AgesaEventAlloc->WriteRecordPtr - AgesaEventAlloc->ReadRecordPtr;
- } else {
- UnreadEntries = TOTAL_EVENT_LOG_BUFFERS - (AgesaEventAlloc->ReadRecordPtr - AgesaEventAlloc->WriteRecordPtr);
- }
- if (Index >= UnreadEntries) {
- return FALSE;
- }
- ActualIndex = Index + AgesaEventAlloc->ReadRecordPtr;
- if (ActualIndex >= TOTAL_EVENT_LOG_BUFFERS) {
- ActualIndex -= TOTAL_EVENT_LOG_BUFFERS;
- }
-
- EventRecord->EventClass = AgesaEventAlloc->AgesaEventStruct[ActualIndex].AgesaEvent.EventClass;
- EventRecord->EventInfo = AgesaEventAlloc->AgesaEventStruct[ActualIndex].AgesaEvent.EventInfo;
- EventRecord->DataParam1 = AgesaEventAlloc->AgesaEventStruct[ActualIndex].AgesaEvent.DataParam1;
- EventRecord->DataParam2 = AgesaEventAlloc->AgesaEventStruct[ActualIndex].AgesaEvent.DataParam2;
- EventRecord->DataParam3 = AgesaEventAlloc->AgesaEventStruct[ActualIndex].AgesaEvent.DataParam3;
- EventRecord->DataParam4 = AgesaEventAlloc->AgesaEventStruct[ActualIndex].AgesaEvent.DataParam4;
-
- return TRUE;
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * This function gets the Event Log pointer.
- *
- * It will locate the Event Log on the heap using the heap locate service. If the Event
- * Log is not located, NULL is returned.
- *
- * @param[out] EventLog Pointer to the Event Log, or NULL.
- * @param[in] StdHeader Our Configuration, for passing to services.
- *
- */
-VOID
-STATIC
-GetEventLogHeapPointer (
- OUT AGESA_STRUCT_BUFFER **EventLog,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- LOCATE_HEAP_PTR LocateHeapStruct;
-
- LocateHeapStruct.BufferHandle = EVENT_LOG_BUFFER_HANDLE;
- LocateHeapStruct.BufferPtr = NULL;
- if ((HeapLocateBuffer (&LocateHeapStruct, StdHeader)) == AGESA_SUCCESS) {
- *EventLog = (AGESA_STRUCT_BUFFER *)LocateHeapStruct.BufferPtr;
- } else {
- *EventLog = NULL;
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/cpuFamilyTranslation.c b/src/vendorcode/amd/agesa/Proc/CPU/cpuFamilyTranslation.c
deleted file mode 100644
index 7882c58..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/cpuFamilyTranslation.c
+++ /dev/null
@@ -1,483 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU Family Translation functions.
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/Interface
- * @e \$Revision: 37150 $ @e \$Date: 2010-08-31 23:53:37 +0800 (Tue, 31 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "CommonReturns.h"
-#include "GeneralServices.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_CPUFAMILYTRANSLATION_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-CONST CPU_SPECIFIC_SERVICES ROMDATA cpuNullServices =
-{
- 0,
- (PF_CPU_DISABLE_PSTATE) CommonReturnAgesaSuccess,
- (PF_CPU_TRANSITION_PSTATE) CommonReturnAgesaSuccess,
- (PF_CPU_GET_IDD_MAX) CommonReturnFalse,
- (PF_CPU_GET_TSC_RATE) CommonReturnAgesaSuccess,
- (PF_CPU_GET_NB_FREQ) CommonReturnAgesaSuccess,
- (PF_CPU_GET_NB_PSTATE_INFO) CommonReturnFalse,
- (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonReturnAgesaSuccess,
- (PF_CPU_AP_INITIAL_LAUNCH) CommonReturnFalse,
- (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonReturnZero8,
- (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonReturnAgesaSuccess,
- (PF_CPU_SET_AP_CORE_NUMBER) CommonVoid,
- (PF_CPU_GET_AP_CORE_NUMBER) CommonReturnZero32,
- (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid,
- (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonReturnAgesaSuccess,
- (PF_CPU_SAVE_FEATURES) CommonReturnAgesaSuccess,
- (PF_CPU_WRITE_FEATURES) CommonReturnAgesaSuccess,
- (PF_CPU_SET_WARM_RESET_FLAG) CommonReturnAgesaSuccess,
- (PF_CPU_GET_WARM_RESET_FLAG) CommonReturnAgesaSuccess,
- GetEmptyArray,
- GetEmptyArray,
- GetEmptyArray,
- GetEmptyArray,
- GetEmptyArray,
- GetEmptyArray,
- GetEmptyArray,
- (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonReturnAgesaSuccess,
- (PF_IS_NB_PSTATE_ENABLED) CommonReturnFalse,
- (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
- (PF_SET_HT_PHY_REGISTER) CommonVoid,
- (PF_GET_NEXT_HT_LINK_FEATURES) CommonVoid,
- NULL,
- NULL,
- NULL,
- NULL,
- InitCacheDisabled,
- (PF_GET_EARLY_INIT_TABLE) CommonVoid
-};
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-VOID
-STATIC
-GetCpuServices (
- IN CPU_FAMILY_SUPPORT_TABLE *FamilyTable,
- IN UINT64 *MatchData,
- OUT CONST VOID **CpuServices,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-extern CPU_FAMILY_SUPPORT_TABLE CpuSupportedFamiliesTable;
-extern CPU_FAMILY_ID_XLAT_TABLE CpuSupportedFamilyIdTable;
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * Returns the logical ID of the desired processor. This will be obtained by
- * reading the CPUID and converting it into a "logical ID" which is not package
- * dependent.
- *
- * @param[in] Socket Socket
- * @param[out] LogicalId The Processor's Logical ID
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- */
-VOID
-GetLogicalIdOfSocket (
- IN UINT32 Socket,
- OUT CPU_LOGICAL_ID *LogicalId,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 RawCpuid;
- PCI_ADDR PciAddress;
- AGESA_STATUS AssumedSuccess;
-
- RawCpuid = 0;
-
- if (GetPciAddress (StdHeader, (UINT8)Socket, 0, &PciAddress, &AssumedSuccess)) {
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = CPUID_FMR;
- LibAmdPciRead (AccessWidth32, PciAddress, &RawCpuid, StdHeader);
- GetLogicalIdFromCpuid (RawCpuid, LogicalId, StdHeader);
- } else {
- LogicalId->Family = 0;
- LogicalId->Revision = 0;
- // Logical ID was not found.
- IDS_ERROR_TRAP;
- }
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * Returns the logical ID of the executing core. This will be obtained by reading
- * the CPUID and converting it into a "logical ID" which is not package dependent.
- *
- * @param[out] LogicalId The Processor's Logical ID
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- */
-VOID
-GetLogicalIdOfCurrentCore (
- OUT CPU_LOGICAL_ID *LogicalId,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- CPUID_DATA CpuidDataStruct;
-
- LibAmdCpuidRead (AMD_CPUID_APICID_LPC_BID, &CpuidDataStruct, StdHeader);
- GetLogicalIdFromCpuid (CpuidDataStruct.EAX_Reg, LogicalId, StdHeader);
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * Returns the logical ID of a processor with the given CPUID value. This
- * will be obtained by converting it into a "logical ID" which is not package
- * dependent.
- *
- * @param[in] RawCpuid The unprocessed CPUID value to be translated
- * @param[out] LogicalId The Processor's Logical ID
- * @param[in] StdHeader Handle of Header for calling lib functions and services
- *
- */
-VOID
-GetLogicalIdFromCpuid (
- IN UINT32 RawCpuid,
- OUT CPU_LOGICAL_ID *LogicalId,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 i;
- UINT8 k;
- UINT8 NumberOfFamiliesSupported;
- UINT8 NumberOfLogicalSubFamilies;
- UINT8 LogicalIdEntries;
- UINT32 j;
- UINT32 RawFamily;
- UINT32 CpuModelAndExtendedModel;
- UINT64 LogicalFamily;
- BOOLEAN IdNotFound;
- BOOLEAN FamilyNotFound;
- CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY *SubFamilyIdPtr;
- CPU_LOGICAL_ID_XLAT *CpuLogicalIdAndRevPtr;
- CONST CPU_LOGICAL_ID_FAMILY_XLAT *ImageSupportedId;
-
- IdNotFound = TRUE;
- FamilyNotFound = TRUE;
- CpuLogicalIdAndRevPtr = NULL;
- ImageSupportedId = CpuSupportedFamilyIdTable.FamilyIdTable;
- NumberOfFamiliesSupported = CpuSupportedFamilyIdTable.Elements;
-
- RawFamily = ((RawCpuid & 0xF00) >> 8) + ((RawCpuid & 0xFF00000) >> 20);
- RawCpuid &= (UINT32) CPU_FMS_MASK;
- CpuModelAndExtendedModel = (UINT16) ((RawCpuid >> 8) | RawCpuid);
-
- LogicalId->Family = 0;
- LogicalId->Revision = 0;
-
- for (i = 0; i < NumberOfFamiliesSupported && FamilyNotFound; i++) {
- if (ImageSupportedId[i].Family == RawFamily) {
- FamilyNotFound = FALSE;
- LogicalId->Family = ImageSupportedId[i].UnknownRevision.Family;
- LogicalId->Revision = ImageSupportedId[i].UnknownRevision.Revision;
-
- NumberOfLogicalSubFamilies = ImageSupportedId[i].Elements;
- SubFamilyIdPtr = ImageSupportedId[i].SubFamilyIdTable;
- for (j = 0; j < NumberOfLogicalSubFamilies && IdNotFound; j++) {
- SubFamilyIdPtr[j] (&CpuLogicalIdAndRevPtr, &LogicalIdEntries, &LogicalFamily, StdHeader);
- ASSERT (CpuLogicalIdAndRevPtr != NULL);
- for (k = 0; k < LogicalIdEntries; k++) {
- if (CpuLogicalIdAndRevPtr[k].RawId == CpuModelAndExtendedModel) {
- IdNotFound = FALSE;
- LogicalId->Family = LogicalFamily;
- LogicalId->Revision = CpuLogicalIdAndRevPtr[k].LogicalId;
- break;
- }
- }
- }
- }
- }
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * Retrieves a pointer to the desired processor's family specific services structure.
- *
- * @param[in] Socket The Processor in this Socket.
- * @param[out] FunctionTable The Processor's Family Specific services.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- */
-VOID
-GetCpuServicesOfSocket (
- IN UINT32 Socket,
- OUT CONST CPU_SPECIFIC_SERVICES **FunctionTable,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- GetFeatureServicesOfSocket (&CpuSupportedFamiliesTable,
- Socket,
- FunctionTable,
- StdHeader);
- if (*FunctionTable == NULL) {
- *FunctionTable = &cpuNullServices;
- }
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * Retrieves a pointer to the desired processor's family specific services structure.
- *
- * @param[in] FamilyTable The table to search in.
- * @param[in] Socket The Processor in this Socket.
- * @param[out] CpuServices The Processor's Family Specific services.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- */
-VOID
-GetFeatureServicesOfSocket (
- IN CPU_FAMILY_SUPPORT_TABLE *FamilyTable,
- IN UINT32 Socket,
- OUT CONST VOID **CpuServices,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- CPU_LOGICAL_ID CpuFamilyRevision;
-
- GetLogicalIdOfSocket (Socket, &CpuFamilyRevision, StdHeader);
- GetFeatureServicesFromLogicalId (FamilyTable, &CpuFamilyRevision, CpuServices, StdHeader);
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * Retrieves a pointer to the executing core's family specific services structure.
- *
- * @param[out] FunctionTable The Processor's Family Specific services.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- */
-VOID
-GetCpuServicesOfCurrentCore (
- OUT CONST CPU_SPECIFIC_SERVICES **FunctionTable,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- GetFeatureServicesOfCurrentCore (&CpuSupportedFamiliesTable,
- FunctionTable,
- StdHeader);
- if (*FunctionTable == NULL) {
- *FunctionTable = &cpuNullServices;
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * Retrieves a pointer to the family specific services structure for a processor
- * with the given logical ID.
- *
- * @param[in] FamilyTable The table to search in.
- * @param[out] CpuServices The Processor's Family Specific services.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- */
-VOID
-GetFeatureServicesOfCurrentCore (
- IN CPU_FAMILY_SUPPORT_TABLE *FamilyTable,
- OUT CONST VOID **CpuServices,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- CPU_LOGICAL_ID CpuFamilyRevision;
-
- GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
- GetFeatureServicesFromLogicalId (FamilyTable, &CpuFamilyRevision, CpuServices, StdHeader);
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * Retrieves a pointer to the family specific services structure for a processor
- * with the given logical ID.
- *
- * @param[in] LogicalId The Processor's logical ID.
- * @param[out] FunctionTable The Processor's Family Specific services.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- */
-VOID
-GetCpuServicesFromLogicalId (
- IN CPU_LOGICAL_ID *LogicalId,
- OUT CONST CPU_SPECIFIC_SERVICES **FunctionTable,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- GetFeatureServicesFromLogicalId (&CpuSupportedFamiliesTable,
- LogicalId,
- FunctionTable,
- StdHeader);
- if (*FunctionTable == NULL) {
- *FunctionTable = &cpuNullServices;
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * Retrieves a pointer to the family specific services structure for a processor
- * with the given logical ID.
- *
- * @param[in] FamilyTable The table to search in.
- * @param[in] LogicalId The Processor's logical ID.
- * @param[out] CpuServices The Processor's Family Specific services.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- */
-VOID
-GetFeatureServicesFromLogicalId (
- IN CPU_FAMILY_SUPPORT_TABLE *FamilyTable,
- IN CPU_LOGICAL_ID *LogicalId,
- OUT CONST VOID **CpuServices,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- GetCpuServices (FamilyTable, &LogicalId->Family, CpuServices, StdHeader);
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * Finds a family match in the given table, and returns the pointer to the
- * appropriate table. If no match is found in the table, NULL will be returned.
- *
- * @param[in] FamilyTable The table to search in.
- * @param[in] MatchData Family data that must match.
- * @param[out] CpuServices The Processor's Family Specific services.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- */
-VOID
-STATIC
-GetCpuServices (
- IN CPU_FAMILY_SUPPORT_TABLE *FamilyTable,
- IN UINT64 *MatchData,
- OUT CONST VOID **CpuServices,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- BOOLEAN IsFamily;
- UINT8 i;
- UINT8 NumberOfFamiliesSupported;
- CONST CPU_SPECIFIC_SERVICES_XLAT *ImageSupportedFamiliesPtr;
-
- ImageSupportedFamiliesPtr = FamilyTable->FamilyTable;
- NumberOfFamiliesSupported = FamilyTable->Elements;
- IsFamily = FALSE;
- for (i = 0; i < NumberOfFamiliesSupported; i++) {
- if ((ImageSupportedFamiliesPtr[i].Family & *MatchData) != 0) {
- IsFamily = TRUE;
- break;
- }
- }
- if (IsFamily) {
- *CpuServices = ImageSupportedFamiliesPtr[i].TablePtr;
- } else {
- *CpuServices = NULL;
- }
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Used to stub out various family specific tables of information.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] Empty NULL, to indicate no data.
- * @param[out] NumberOfElements Zero, to indicate no data.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- */
-VOID
-GetEmptyArray (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- OUT CONST VOID **Empty,
- OUT UINT8 *NumberOfElements,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- *NumberOfElements = 0;
- *Empty = NULL;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/cpuFamilyTranslation.h b/src/vendorcode/amd/agesa/Proc/CPU/cpuFamilyTranslation.h
deleted file mode 100644
index deae446..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/cpuFamilyTranslation.h
+++ /dev/null
@@ -1,957 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU Family Translation functions.
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 39160 $ @e \$Date: 2010-10-07 22:32:44 +0800 (Thu, 07 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPU_FAMILY_TRANSLATION_H_
-#define _CPU_FAMILY_TRANSLATION_H_
-
-/**
- * @page cpuimplfss CPU Family Specific Services Implementation Guide
- *
- * CPU Family Specific Services provides access to supported family service functions and data,
- * in a manner that isolates calling code from knowledge about particular families or which
- * families are supported in the current build.
- *
- * @par Adding a Method to Family Specific Services
- *
- * To add a new method to Family Specific Services, follow these steps.
- * <ul>
- * <li> Create a typedef for the Method with the correct parameters and return type.
- *
- * <ul>
- * <li> Name the method typedef (*PF_METHOD_NAME)(), where METHOD_NAME is the same name as the method table item,
- * but with "_"'s and UPPERCASE, rather than mixed case.
- * @n <tt> typedef VOID (*PF_METHOD_NAME)(); </tt> @n
- *
- * <li> [Optionally make the type F_<name> and provide a separate:
- * @n <tt> typedef F_METHOD_NAME *PF_METHOD_NAME> </tt> @n
- * and provide a single line "///" doxygen comment brief description on the PF_ type.]
- * </ul>
- *
- * <li> The first parameter to @b all Family Specific Service Methods is @b required to be a reference to
- * their Family Service struct.
- * @n <tt> IN CPU_SPECIFIC_SERVICES *FamilySpecificServices </tt> @n
- *
- * <li> Provide a standard doxygen function preamble for the Method typedef. Begin the
- * detailed description by provide a reference to the method instances page by including
- * the lines below:
- * @code
- * *
- * * @CpuServiceInstances
- * *
- * @endcode
- * @note It is important to provide documentation for the method type, because the method may not
- * have an implementation in any families supported by the current package. @n
- *
- * <li> Add to the CPU_SPECIFIC_SERVICES struct an item for the Method:
- * @n <tt> PF_METHOD_NAME MethodName; ///< Method: description. </tt> @n
- * </ul>
- *
- * @par Implementing a Family Specific Instance of the method.
- *
- * To implement an instance of a method for a specific family follow these steps.
- *
- * - In appropriate files in the family specific directory, implement the method with the return type
- * and parameters matching the method typedef.
- *
- * - Name the function FnnMethodName(), where nn is the family number.
- *
- * - Create a doxygen function preamble for the method instance. Begin the detailed description with
- * an Implements command to reference the method type and add this instance to the Method Instances page.
- * @code
- * *
- * * @CpuServiceMethod{::F_METHOD_NAME}.
- * *
- * @endcode
- *
- * - To access other family specific services as part of the method implementation, the function
- * @b must use FamilySpecificServices->OtherMethod(). Do not directly call other family specific
- * routines, because in the table there may be overrides or this routine may be shared by multiple families.
- *
- * - Do @b not call Family translation services from a family specific instance. Use the parameter.
- *
- * - Add the instance to the family specific CPU_SPECIFIC_SERVICES instance.
- *
- * - If a family does not need an instance of the method use one of the CommonReturns from
- * CommonReturns.h with the same return type.
- *
- * @par Invoking Family Specific Services.
- *
- * The following example shows how to invoke a family specific method.
- * @n @code
- * CPU_SPECIFIC_SERVICES *FamilyServices;
- *
- * GetCpuServicesOfCurrentCore (&FamilyServices, StdHeader);
- * ASSERT (FamilyServices != NULL);
- * FamilyServices->MethodName (FamilyServices, StdHeader);
- * @endcode
- *
- */
-
-
-/*---------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *---------------------------------------------------------------------------------------
- */
-#include "cpuPostInit.h"
-#include "cpuRegisters.h"
-#include "cpuServices.h"
-#include "Table.h"
-#include "Ids.h"
-#include "Topology.h"
-
-// Forward declaration needed for multi-structure mutual references.
-AGESA_FORWARD_DECLARATION (CPU_SPECIFIC_SERVICES);
-
-/*---------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *---------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *---------------------------------------------------------------------------------------
- */
-
-/**
- * Disable the desired P-state.
- *
- * @CpuServiceInstances
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] StateNumber P-state number.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- */
-typedef AGESA_STATUS F_CPU_DISABLE_PSTATE (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN UINT8 StateNumber,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_CPU_DISABLE_PSTATE *PF_CPU_DISABLE_PSTATE;
-
-/**
- * Transition the current core to the desired P-state.
- *
- * @CpuServiceInstances
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] StateNumber P-state number.
- * @param[in] WaitForChange Wait/don't wait for P-state change to complete.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- */
-typedef AGESA_STATUS F_CPU_TRANSITION_PSTATE (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN UINT8 StateNumber,
- IN BOOLEAN WaitForChange,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_CPU_TRANSITION_PSTATE *PF_CPU_TRANSITION_PSTATE;
-
-/**
- * Get the desired P-state's maximum current required in milliamps.
- *
- * @CpuServiceInstances
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] StateNumber The desired P-state number.
- * @param[out] ProcIddMax The P-state's maximum current.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @retval TRUE The P-state is enabled, and ProcIddMax is valid.
- * @retval FALSE The P-state is disabled.
- *
- */
-typedef BOOLEAN F_CPU_GET_IDD_MAX (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN UINT8 StateNumber,
- OUT UINT32 *ProcIddMax,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_CPU_GET_IDD_MAX *PF_CPU_GET_IDD_MAX;
-
-
-/**
- * Returns the rate at which the current core's timestamp counter increments in megahertz.
- *
- * @CpuServiceInstances
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[out] FreqInMHz The rate at which the TSC increments in megahertz.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- */
-typedef AGESA_STATUS F_CPU_GET_TSC_RATE (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- OUT UINT32 *FreqInMHz,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_CPU_GET_TSC_RATE *PF_CPU_GET_TSC_RATE;
-
-/**
- * Returns the processor north bridge's clock rate in megahertz.
- *
- * @CpuServiceInstances
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[out] FreqInMHz The desired node's frequency in megahertz.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @retval AGESA_SUCCESS FreqInMHz is valid.
- */
-typedef AGESA_STATUS F_CPU_GET_NB_FREQ (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- OUT UINT32 *FreqInMHz,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_CPU_GET_NB_FREQ *PF_CPU_GET_NB_FREQ;
-
-/**
- * Returns the processor north bridge's P-state settings.
- *
- * @CpuServiceInstances
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] PlatformConfig Platform profile/build option config structure.
- * @param[in] PciAddress The segment, bus, and device numbers of the CPU in question.
- * @param[in] NbPstate The NB P-state number to check.
- * @param[out] FreqNumeratorInMHz The desired node's frequency numerator in megahertz.
- * @param[out] FreqDivisor The desired node's frequency divisor.
- * @param[out] VoltageInuV The desired node's voltage in microvolts.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @retval TRUE NbPstate is valid
- * @retval FALSE NbPstate is disabled or invalid
- */
-typedef BOOLEAN F_CPU_GET_NB_PSTATE_INFO (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN PCI_ADDR *PciAddress,
- IN UINT32 NbPstate,
- OUT UINT32 *FreqNumeratorInMHz,
- OUT UINT32 *FreqDivisor,
- OUT UINT32 *VoltageInuV,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_CPU_GET_NB_PSTATE_INFO *PF_CPU_GET_NB_PSTATE_INFO;
-
-/**
- * Launches the desired core from the reset vector.
- *
- * @CpuServiceInstances
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] SocketNumber The desired core's socket number.
- * @param[in] ModuleNumber The desired core's die number.
- * @param[in] CoreNumber The desired core's die relative core number.
- * @param[in] PrimaryCoreNumber SocketNumber / ModuleNumber's primary core number.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @retval TRUE The core was launched successfully.
- * @retval FALSE The core was previously launched, or has a problem.
- */
-typedef BOOLEAN F_CPU_AP_INITIAL_LAUNCH (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN UINT32 SocketNumber,
- IN UINT32 ModuleNumber,
- IN UINT32 CoreNumber,
- IN UINT32 PrimaryCoreNumber,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_CPU_AP_INITIAL_LAUNCH *PF_CPU_AP_INITIAL_LAUNCH;
-
-/**
- * Returns the appropriate number of processor cores for brandstring detection
- *
- * @CpuServiceInstances
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @return One-based number of cores on current processor
- */
-typedef UINT8 F_CPU_NUMBER_OF_BRANDSTRING_CORES (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_CPU_NUMBER_OF_BRANDSTRING_CORES *PF_CPU_NUMBER_OF_BRANDSTRING_CORES;
-
-/**
- * Returns whether or not the NB frequency initialization sequence is required
- * to be performed by the BIOS.
- *
- * @CpuServiceInstances
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] PciAddress The northbridge to query by pci base address.
- * @param[out] NbVidUpdateAll Do all NbVids need to be updated as well.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- */
-typedef BOOLEAN F_CPU_IS_NBCOF_INIT_NEEDED (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN PCI_ADDR *PciAddress,
- OUT BOOLEAN *NbVidUpdateAll,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_CPU_IS_NBCOF_INIT_NEEDED *PF_CPU_IS_NBCOF_INIT_NEEDED;
-
-/**
- * Returns a family specific table of information pointer and size.
- *
- * @CpuServiceInstances
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[out] FamilySpecificArray Pointer to the appropriate list for the core.
- * @param[out] NumberOfElements Number of valid entries FamilySpecificArray.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- */
-typedef VOID F_CPU_GET_FAMILY_SPECIFIC_ARRAY (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- OUT CONST VOID **FamilySpecificArray,
- OUT UINT8 *NumberOfElements,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_CPU_GET_FAMILY_SPECIFIC_ARRAY *PF_CPU_GET_FAMILY_SPECIFIC_ARRAY;
-
-/**
- * Returns a model specific list of logical IDs.
- *
- * @param[out] LogicalIdXlat Installed logical ID table.
- * @param[out] NumberOfElements Number of entries in the Logical ID translate table.
- * @param[out] LogicalFamily Base logical family bit mask.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- */
-typedef VOID F_CPU_GET_SUBFAMILY_ID_ARRAY (
- OUT CONST CPU_LOGICAL_ID_XLAT **LogicalIdXlat,
- OUT UINT8 *NumberOfElements,
- OUT UINT64 *LogicalFamily,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a method.
-typedef F_CPU_GET_SUBFAMILY_ID_ARRAY *PF_CPU_GET_SUBFAMILY_ID_ARRAY;
-
-/**
- * Use the Mailbox Register to get the Ap Mailbox info for the current core.
- *
- * @CpuServiceInstances
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[out] ApMailboxInfo The AP Mailbox info
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- */
-typedef VOID (F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- OUT AP_MAILBOXES *ApMailboxInfo,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a method
-typedef F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE *PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE;
-
-/**
- * Set the AP core number in the AP's Mailbox.
- *
- * @CpuServiceInstances
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] Socket The AP's socket
- * @param[in] Module The AP's module
- * @param[in] ApCoreNumber The AP's unique core number
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- */
-typedef VOID (F_CPU_SET_AP_CORE_NUMBER) (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN UINT32 Socket,
- IN UINT32 Module,
- IN UINT32 ApCoreNumber,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a method
-typedef F_CPU_SET_AP_CORE_NUMBER *PF_CPU_SET_AP_CORE_NUMBER;
-
-/**
- * Get the AP core number from hardware.
- *
- * @CpuServiceInstances
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @return The AP's unique core number
- */
-typedef UINT32 (F_CPU_GET_AP_CORE_NUMBER) (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a method
-typedef F_CPU_GET_AP_CORE_NUMBER *PF_CPU_GET_AP_CORE_NUMBER;
-
-/**
- * Move the AP's core number from the mailbox to hardware.
- *
- * @CpuServiceInstances
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @return The AP's unique core number
- */
-typedef VOID (F_CPU_TRANSFER_AP_CORE_NUMBER) (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a method
-typedef F_CPU_TRANSFER_AP_CORE_NUMBER *PF_CPU_TRANSFER_AP_CORE_NUMBER;
-
-/**
- * Core ID position in the initial APIC ID, reflected as a number zero or one.
- */
-typedef enum {
- CoreIdPositionZero, ///< Zero, the Core Id bits are the Most Significant bits.
- CoreIdPositionOne, ///< One, the Core Id bits are the Least Significant bits.
- CoreIdPositionMax ///< Limit check.
-} CORE_ID_POSITION;
-
-/**
- * Return a number zero or one, based on the Core ID position in the initial APIC Id.
- *
- * @CpuServiceInstances
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @retval CoreIdPositionZero Core Id is not low
- * @retval CoreIdPositionOne Core Id is low
- */
-typedef CORE_ID_POSITION F_CORE_ID_POSITION_IN_INITIAL_APIC_ID (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a method
-typedef F_CORE_ID_POSITION_IN_INITIAL_APIC_ID *PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID;
-
-/**
- * Get least common features set of all CPUs and save them to CPU_FEATURES_LIST
- *
- * @CpuServiceInstances
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in,out] cpuFeatureListPtr The CPU Features List
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- */
-typedef VOID (F_CPU_SAVE_FEATURES) (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN OUT CPU_FEATURES_LIST *cpuFeatureListPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a method
-typedef F_CPU_SAVE_FEATURES *PF_CPU_SAVE_FEATURES;
-
-/**
- * Get least common features from CPU_FEATURES_LIST and write them to CPU
- *
- * @CpuServiceInstances
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in,out] cpuFeatureListPtr The CPU Features List
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- */
-typedef VOID (F_CPU_WRITE_FEATURES) (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN OUT CPU_FEATURES_LIST *cpuFeatureListPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a method
-typedef F_CPU_WRITE_FEATURES *PF_CPU_WRITE_FEATURES;
-
-/**
- * Set Warm Reset Flag
- *
- * @CpuServiceInstances
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] StdHeader Header for library and services.
- * @param[in] Request Value to set the flags to.
- *
- */
-typedef VOID (F_CPU_SET_WARM_RESET_FLAG) (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN WARM_RESET_REQUEST *Request
- );
-
-/// Reference to a method
-typedef F_CPU_SET_WARM_RESET_FLAG *PF_CPU_SET_WARM_RESET_FLAG;
-
-/**
- * Get Warm Reset Flag
- *
- * @CpuServiceInstances
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] StdHeader Header for library and services.
- * @param[out] BiosRstDet Indicate warm reset status.
- *
- */
-typedef VOID (F_CPU_GET_WARM_RESET_FLAG) (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CONFIG_PARAMS *StdHeader,
- OUT WARM_RESET_REQUEST *Request
- );
-
-/// Reference to a method
-typedef F_CPU_GET_WARM_RESET_FLAG *PF_CPU_GET_WARM_RESET_FLAG;
-
-
-/**
- * Get CPU Specific Platform Type Info.
- *
- * @CpuServiceInstances
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in,out] FeaturesUnion The Features supported by this platform.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- */
-typedef AGESA_STATUS F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN OUT PLATFORM_FEATS *FeaturesUnion,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO *PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO;
-
-/**
- * Is the Northbridge PState feature enabled?
- *
- * @CpuServiceInstances
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] PlatformConfig Platform profile/build option config structure.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @retval TRUE The NB PState feature is enabled.
- * @retval FALSE The NB PState feature is not enabled.
- */
-typedef BOOLEAN F_IS_NB_PSTATE_ENABLED (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a method
-typedef F_IS_NB_PSTATE_ENABLED *PF_IS_NB_PSTATE_ENABLED;
-
-/**
- * Gets the next link with features matching the HT phy register table entry type features.
- *
- * @CpuServiceInstances
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in,out] HtHostCapability Initially the PCI bus, device, function=0, offset=0;
- * Each call returns the HT Host Capability function and offset;
- * Caller may use it to access registers, but must @b not modify it;
- * Each new call passes the previous value as input.
- * @param[in,out] Link Initially zero, each call returns the link number; caller passes it back unmodified each call.
- * @param[in] HtPhyLinkType Link type field from a register table entry to compare against
- * @param[out] MatchedSublink1 TRUE: It is actually just sublink 1 that matches, FALSE: any other condition.
- * @param[out] Frequency0 The frequency of sublink0 (200 MHz if not connected).
- * @param[out] Frequency1 The frequency of sublink1 (200 MHz if not connected).
- * @param[in] StdHeader Standard Head Pointer
- *
- * @retval TRUE Link matches
- * @retval FALSE No more links
- *
- */
-typedef BOOLEAN F_NEXT_LINK_HAS_HTFPY_FEATS (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN OUT PCI_ADDR *HtHostCapability,
- IN OUT UINT32 *Link,
- IN HT_PHY_LINK_FEATS *HtPhyLinkType,
- OUT BOOLEAN *MatchedSublink1,
- OUT HT_FREQUENCIES *Frequency0,
- OUT HT_FREQUENCIES *Frequency1,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-/// Reference to a Method.
-typedef F_NEXT_LINK_HAS_HTFPY_FEATS *PF_NEXT_LINK_HAS_HTFPY_FEATS;
-
-/**
- * Applies an HT Phy read-modify-write based on an HT Phy register table entry.
- *
- * @CpuServiceInstances
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] HtPhyEntry HT Phy register table entry to apply
- * @param[in] CapabilitySet The link's HT Host base address.
- * @param[in] Link Zero based, node, link number (not package link), always a sublink0 link.
- * @param[in] StdHeader Config handle for library and services
- *
- */
-typedef VOID F_SET_HT_PHY_REGISTER (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN HT_PHY_TYPE_ENTRY_DATA *HtPhyEntry,
- IN PCI_ADDR CapabilitySet,
- IN UINT32 Link,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-/// Reference to a Method.
-typedef F_SET_HT_PHY_REGISTER *PF_SET_HT_PHY_REGISTER;
-
-/**
- * Performs an early initialization function on the executing core.
- *
- * @param[in] FamilyServices The current Family Specific Services.
- * @param[in] EarlyParams CPU module early paramters.
- * @param[in] StdHeader Config handle for library and services
- *
- */
-typedef VOID F_PERFORM_EARLY_INIT_ON_CORE (
- IN CPU_SPECIFIC_SERVICES *FamilyServices,
- IN AMD_CPU_EARLY_PARAMS *EarlyParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-/// Reference to a Method.
-typedef F_PERFORM_EARLY_INIT_ON_CORE *PF_PERFORM_EARLY_INIT_ON_CORE;
-
-/**
- * A struct that contains function pointer and function flag
- *
- * the flag indicates if the function need to be run.
- */
-typedef struct _S_PERFORM_EARLY_INIT_ON_CORE {
- PF_PERFORM_EARLY_INIT_ON_CORE PerformEarlyInitOnCore; ///< Function Pointer, which points to the function need to be run at early stage
- UINT32 PerformEarlyInitFlag; ///< Function Flag, which indicates if the function need to be run.
-} S_PERFORM_EARLY_INIT_ON_CORE;
-
-/**
- * Returns the initialization steps that the executing core should
- * perform at AmdInitEarly.
- *
- * @CpuServiceInstances
- *
- * @param[in] FamilyServices The current Family Specific Services.
- * @param[out] Table Table of appropriate init steps for the executing core.
- * @param[in] EarlyParams CPU module early paramters.
- * @param[in] StdHeader Config handle for library and services
- *
- */
-typedef VOID F_GET_EARLY_INIT_TABLE (
- IN CPU_SPECIFIC_SERVICES *FamilyServices,
- OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table,
- IN AMD_CPU_EARLY_PARAMS *EarlyParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-/// Reference to a Method.
-typedef F_GET_EARLY_INIT_TABLE *PF_GET_EARLY_INIT_TABLE;
-
-/**
- * Provide the features of the next HT link.
- *
- * @CpuServiceInstances
- *
- * This method is different than the HT Phy Features method, because for the phy registers
- * sublink 1 matches and should be programmed if the link is ganged but for PCI config
- * registers sublink 1 is reserved if the link is ganged.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in,out] Link The link number, for accessing non-capability set registers.
- * Zero on initial call, and passed back unmodified on each subsequent call.
- * @param[in,out] LinkBase IN: initially the node's PCI config base address, passed back on each call.
- * OUT: the base HT Host capability PCI address for the link.
- * @param[out] HtHostFeats The link's features.
- * @param[in] StdHeader Standard Head Pointer
- *
- * @retval TRUE Valid link and features found.
- * @retval FALSE No more links.
- */
-typedef BOOLEAN F_GET_NEXT_HT_LINK_FEATURES (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN OUT UINTN *Link,
- IN OUT PCI_ADDR *LinkBase,
- OUT HT_HOST_FEATS *HtHostFeats,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-/// Reference to a Method.
-typedef F_GET_NEXT_HT_LINK_FEATURES *PF_GET_NEXT_HT_LINK_FEATURES;
-
-/// Cache Enable / Disable policy before giving control back to OS.
-typedef enum {
- InitCacheDisabled, ///<Disable cache CR0.CD bit
- InitCacheEnabled ///<Enable cache CR0.CD bit
-} FAMILY_CACHE_INIT_POLICY;
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Provide the interface to all cpu Family Specific Services.
- *
- * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
- * Each supported Family must provide an implementation for all methods in this interface, even if the
- * implementation is a CommonReturn().
- * See CPU Family Specific Services Implementation Guide for adding new services.
- */
-struct _CPU_SPECIFIC_SERVICES { // See the Forwaqrd Declaration above
- UINT16 Revision; ///< Interface version
- // Public Methods.
- PF_CPU_DISABLE_PSTATE DisablePstate; ///< Method: Disable the desired P-state.
- PF_CPU_TRANSITION_PSTATE TransitionPstate; ///< Method: Transition the current core to the desired P-state.
- PF_CPU_GET_IDD_MAX GetProcIddMax; ///< Method: Gets P-state maximum current required
- PF_CPU_GET_TSC_RATE GetTscRate; ///< Method: Returns the rate at which the current core's timestamp counter increments in megahertz.
- PF_CPU_GET_NB_FREQ GetCurrentNbFrequency; ///< Method: Returns the processor north bridge's clock rate in megahertz.
- PF_CPU_GET_NB_PSTATE_INFO GetNbPstateInfo; ///< Method: Returns information about the processor north bridge's P-states.
- PF_CPU_IS_NBCOF_INIT_NEEDED IsNbCofInitNeeded; ///< Method: Returns whether or not the NB frequency initialization sequence is required to be performed by the BIOS.
- PF_CPU_AP_INITIAL_LAUNCH LaunchApCore; ///< Method: Launches the desired core from the reset vector.
- PF_CPU_NUMBER_OF_BRANDSTRING_CORES GetNumberOfCoresForBrandstring; ///< Method: Get the current core's number of cores used in the brandstring calculation.
- PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE GetApMailboxFromHardware; ///< Method: Get the AP's topology info from the hardware mailbox.
- PF_CPU_SET_AP_CORE_NUMBER SetApCoreNumber; ///< Method: Set the AP's core number to the hardware mailbox.
- PF_CPU_GET_AP_CORE_NUMBER GetApCoreNumber; ///< Method: Get the AP's core number from hardware.
- PF_CPU_TRANSFER_AP_CORE_NUMBER TransferApCoreNumber; ///< Method: Move the AP's core number from the mailbox to hardware.
- PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID CoreIdPositionInInitialApicId; ///< Method: Which bits in initial APIC Id are the Core Id.
- PF_CPU_SAVE_FEATURES SaveFeatures; ///< Method: Get least common features set of all CPUs and save them to CPU_FEATURES_LIST
- PF_CPU_WRITE_FEATURES WriteFeatures; ///< Method: Get least common features from CPU_FEATURES_LIST and write them to CPU
- PF_CPU_SET_WARM_RESET_FLAG SetWarmResetFlag; ///< Method: Set Warm Reset Flag
- PF_CPU_GET_WARM_RESET_FLAG GetWarmResetFlag; ///< Method: Get Warm Reset Flag
- PF_CPU_GET_FAMILY_SPECIFIC_ARRAY GetBrandString1; ///< Method: Get a Brand String table
- PF_CPU_GET_FAMILY_SPECIFIC_ARRAY GetBrandString2; ///< Method: Get a Brand String table
- PF_CPU_GET_FAMILY_SPECIFIC_ARRAY GetMicroCodePatchesStruct; ///< Method: Get microcode patches
- PF_CPU_GET_FAMILY_SPECIFIC_ARRAY GetMicrocodeEquivalenceTable; ///< Method: Get CPU equivalence for loading microcode patches.
- PF_CPU_GET_FAMILY_SPECIFIC_ARRAY GetCacheInfo; ///< Method: Get setup for cache use and initialization.
- PF_CPU_GET_FAMILY_SPECIFIC_ARRAY GetSysPmTableStruct; ///< Method: Get Power Management settings.
- PF_CPU_GET_FAMILY_SPECIFIC_ARRAY GetWheaInitData; ///< Method: Get Whea Initial Data.
- PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO GetPlatformTypeSpecificInfo; ///< Method: Get Specific platform Type features.
- PF_IS_NB_PSTATE_ENABLED IsNbPstateEnabled; ///< Method: Get whether Northbridge PStates feature is enabled.
- PF_NEXT_LINK_HAS_HTFPY_FEATS NextLinkHasHtPhyFeats; ///< Method: Iterate over HT Links matching features, for HT PHY entries.
- PF_SET_HT_PHY_REGISTER SetHtPhyRegister; ///< Method: Set an Ht Phy register based on table entry.
- PF_GET_NEXT_HT_LINK_FEATURES GetNextHtLinkFeatures; ///< Method: Iterate over HT links, returning link features.
- REGISTER_TABLE **RegisterTableList; ///< Public Data: The available register tables.
- TABLE_ENTRY_TYPE_DESCRIPTOR *TableEntryTypeDescriptors; ///< Public Data: implemented register table entry types.
- PACKAGE_HTLINK_MAP PackageLinkMap; ///< Public Data: translate northbridge HT links to package level links, or NULL.
- CORE_PAIR_MAP *CorePairMap; ///< Public Data: translate compute unit core pairing, or NULL.
- FAMILY_CACHE_INIT_POLICY InitCacheDisabled; ///< public Data: Family related information.
- PF_GET_EARLY_INIT_TABLE GetEarlyInitOnCoreTable; ///< Method: Get the initialization steps needed at AmdInitEarly.
-};
-
-/**
- * A Family Id and an interface to it's implementations of Family Specific Services.
- *
- * Note that this is a logical family id, which may specify family, model (or even stepping).
- */
-typedef struct {
- UINT64 Family; ///< The Family to which this interface belongs.
- CONST VOID *TablePtr; ///< The interface to its Family Specific Services.
-} CPU_SPECIFIC_SERVICES_XLAT;
-
-/**
- * A collection of Family specific interfaces to Family Specific services.
- */
-typedef struct {
- UINT8 Elements; ///< The number of tables to search.
- CONST CPU_SPECIFIC_SERVICES_XLAT *FamilyTable; ///< The family interfaces.
-} CPU_FAMILY_SUPPORT_TABLE;
-
-/**
- * Implement the translation of a logical CPU id to an id that can be used to get Family specific services.
- */
-typedef struct {
- UINT32 Family; ///< Provide translation for this family
- CPU_LOGICAL_ID UnknownRevision; ///< In this family, unrecognized models (or steppings) are treated as though they were this model and stepping.
- CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY *SubFamilyIdTable; ///< Method: Get family specific model (and stepping) resolution.
- UINT8 Elements; ///< The number of family specific model tables pointed to by SubFamilyIdTable
-} CPU_LOGICAL_ID_FAMILY_XLAT;
-
-/**
- * A collection of all available family id translations.
- */
-typedef struct {
- UINT8 Elements; ///< The number of family translation items to search.
- CONST CPU_LOGICAL_ID_FAMILY_XLAT *FamilyIdTable; ///< The family translation items.
-} CPU_FAMILY_ID_XLAT_TABLE;
-
-/*---------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *---------------------------------------------------------------------------------------
- */
-
-/**
- * Get a logical identifier for the specified processor, based on CPUID, but independent of CPUID formatting.
- */
-VOID
-GetLogicalIdOfSocket (
- IN UINT32 Socket,
- OUT CPU_LOGICAL_ID *LogicalId,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * Get a logical identifier for the executing core, based on CPUID, but independent of CPUID formatting.
- */
-VOID
-GetLogicalIdOfCurrentCore (
- OUT CPU_LOGICAL_ID *LogicalId,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * Get a logical identifier for the specified CPUID value.
- */
-VOID
-GetLogicalIdFromCpuid (
- IN UINT32 RawCpuid,
- OUT CPU_LOGICAL_ID *LogicalId,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * Retrieves a pointer to the desired processor's family specific services structure.
- */
-VOID
-GetCpuServicesOfSocket (
- IN UINT32 Socket,
- OUT CONST CPU_SPECIFIC_SERVICES **FunctionTable,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * Retrieves a pointer to the desired processor's family specific services structure.
- */
-VOID
-GetFeatureServicesOfSocket (
- IN CPU_FAMILY_SUPPORT_TABLE *FamilyTable,
- IN UINT32 Socket,
- OUT CONST VOID **CpuServices,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * Retrieves a pointer to the executing core's family specific services structure.
- */
-VOID
-GetCpuServicesOfCurrentCore (
- OUT CONST CPU_SPECIFIC_SERVICES **FunctionTable,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * Retrieves a pointer to the executing core's family specific services structure.
- */
-VOID
-GetFeatureServicesOfCurrentCore (
- IN CPU_FAMILY_SUPPORT_TABLE *FamilyTable,
- OUT CONST VOID **CpuServices,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * Retrieves a pointer to the family specific services structure for a processor
- * with the given logical ID.
- */
-VOID
-GetCpuServicesFromLogicalId (
- IN CPU_LOGICAL_ID *LogicalId,
- OUT CONST CPU_SPECIFIC_SERVICES **FunctionTable,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * Retrieves a pointer to the family specific services structure for a processor
- * with the given logical ID.
- */
-VOID
-GetFeatureServicesFromLogicalId (
- IN CPU_FAMILY_SUPPORT_TABLE *FamilyTable,
- IN CPU_LOGICAL_ID *LogicalId,
- OUT CONST VOID **CpuServices,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * Used by logical families which don't need a certain register setting table or other data array.
- */
-VOID
-GetEmptyArray (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- OUT CONST VOID **Empty,
- OUT UINT8 *NumberOfElements,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif // _CPU_FAMILY_TRANSLATION_H_
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/cpuGeneralServices.c b/src/vendorcode/amd/agesa/Proc/CPU/cpuGeneralServices.c
deleted file mode 100644
index 29309ce..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/cpuGeneralServices.c
+++ /dev/null
@@ -1,1277 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Implement External, AGESA Common, and CPU component General Services.
- *
- * Contains implementation of the interfaces: General Services API in AGESA.h,
- * GeneralServices.h, and cpuServices.h.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 36208 $ @e \$Date: 2010-08-13 22:55:05 +0800 (Fri, 13 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Options.h"
-#include "Topology.h"
-#include "cpuRegisters.h"
-#include "GeneralServices.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuServices.h"
-#include "heapManager.h"
-#include "cpuApicUtilities.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_CPUGENERALSERVICES_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-extern OPTIONS_CONFIG_TOPOLOGY TopologyConfiguration;
-extern BUILD_OPT_CFG UserOptions;
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S - External General Services API
- *----------------------------------------------------------------------------------------
- */
-
-/**
- * Get a specified Core's APIC ID.
- *
- * Invoke corresponding Cpu Service for external user.
- *
- * @param[in,out] AmdParamApic Our interface struct
- *
- * @return The most severe status of any called service.
- */
-AGESA_STATUS
-AmdGetApicId (
- IN OUT AMD_APIC_PARAMS *AmdParamApic
- )
-{
- AGESA_STATUS AgesaStatus;
-
- AGESA_TESTPOINT (TpIfAmdGetApicIdEntry, &AmdParamApic->StdHeader);
- AmdParamApic->StdHeader.HeapBasePtr = HeapGetBaseAddress (&AmdParamApic->StdHeader);
-
- AmdParamApic->IsPresent = GetApicId (
- &AmdParamApic->StdHeader,
- AmdParamApic->Socket,
- AmdParamApic->Core,
- &AmdParamApic->ApicAddress,
- &AgesaStatus
- );
-
- AGESA_TESTPOINT (TpIfAmdGetApicIdExit, &AmdParamApic->StdHeader);
- return AgesaStatus;
-}
-
-/**
- * Get Processor Module's PCI Config Space address.
- *
- * Invoke corresponding Cpu Service for external user.
- *
- * @param[in,out] AmdParamGetPci Our interface struct
- *
- * @return The most severe status of any called service.
- */
-AGESA_STATUS
-AmdGetPciAddress (
- IN OUT AMD_GET_PCI_PARAMS *AmdParamGetPci
- )
-{
- AGESA_STATUS AgesaStatus;
-
- AGESA_TESTPOINT (TpIfAmdGetPciAddressEntry, &AmdParamGetPci->StdHeader);
- AmdParamGetPci->StdHeader.HeapBasePtr = HeapGetBaseAddress (&AmdParamGetPci->StdHeader);
-
- AmdParamGetPci->IsPresent = GetPciAddress (
- &AmdParamGetPci->StdHeader,
- AmdParamGetPci->Socket,
- AmdParamGetPci->Module,
- &AmdParamGetPci->PciAddress,
- &AgesaStatus
- );
-
- AGESA_TESTPOINT (TpIfAmdGetPciAddressExit, &AmdParamGetPci->StdHeader);
- return AgesaStatus;
-}
-
-/**
- * "Who am I" for the current running core.
- *
- * Invoke corresponding Cpu Service for external user.
- *
- * @param[in,out] AmdParamIdentify Our interface struct
- *
- * @return The most severe status of any called service.
- */
-AGESA_STATUS
-AmdIdentifyCore (
- IN OUT AMD_IDENTIFY_PARAMS *AmdParamIdentify
- )
-{
- AGESA_STATUS AgesaStatus;
- UINT32 Socket;
- UINT32 Module;
- UINT32 Core;
-
- AGESA_TESTPOINT (TpIfAmdIdentifyCoreEntry, &AmdParamIdentify->StdHeader);
- AmdParamIdentify->StdHeader.HeapBasePtr = HeapGetBaseAddress (&AmdParamIdentify->StdHeader);
-
- IdentifyCore (
- &AmdParamIdentify->StdHeader,
- &Socket,
- &Module,
- &Core,
- &AgesaStatus
- );
- AmdParamIdentify->Socket = (UINT8)Socket;
- AmdParamIdentify->Module = (UINT8)Module;
- AmdParamIdentify->Core = (UINT8)Core;
-
- AGESA_TESTPOINT (TpIfAmdIdentifyCoreExit, &AmdParamIdentify->StdHeader);
- return AgesaStatus;
-}
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S - AGESA common General Services
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Get a specified Core's APIC ID.
- *
- * Code sync: This calculation MUST match the assignment
- * calculation done in LocalApicInitializationAtEarly function.
- *
- * @param[in] StdHeader Header for library and services.
- * @param[in] Socket The socket in which the Core's Processor is installed.
- * @param[in] Core The Core id.
- * @param[out] ApicAddress The Core's APIC ID.
- * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
- *
- * @retval TRUE The core is present, APIC Id valid
- * @retval FALSE The core is not present, APIC Id not valid.
-*/
-BOOLEAN
-GetApicId (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN UINT32 Socket,
- IN UINT32 Core,
- OUT UINT8 *ApicAddress,
- OUT AGESA_STATUS *AgesaStatus
- )
-{
- BOOLEAN ReturnValue;
- UINT32 CoreCount;
- UINT32 ApicID;
-
- ReturnValue = FALSE;
- if (GetActiveCoresInGivenSocket (Socket, &CoreCount, StdHeader)) {
- if (Core < CoreCount) {
- ReturnValue = TRUE;
- GetLocalApicIdForCore (Socket, Core, &ApicID, StdHeader);
- *ApicAddress = (UINT8) ApicID;
- }
- }
-
- // Always Succeeds.
- *AgesaStatus = AGESA_SUCCESS;
-
- return ReturnValue;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Get Processor Module's PCI Config Space address.
- *
- * @param[in] StdHeader Header for library and services.
- * @param[in] Socket The Core's Socket.
- * @param[in] Module The Module in that Processor
- * @param[out] PciAddress The Processor's PCI Config Space address (Function 0, Register 0)
- * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
- *
- * @retval TRUE The core is present, PCI Address valid
- * @retval FALSE The core is not present, PCI Address not valid.
- */
-BOOLEAN
-GetPciAddress (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN UINT32 Socket,
- IN UINT32 Module,
- OUT PCI_ADDR *PciAddress,
- OUT AGESA_STATUS *AgesaStatus
- )
-{
- UINT8 Node;
- BOOLEAN Result;
-
- ASSERT (Socket < MAX_SOCKETS);
- ASSERT (Module < MAX_DIES);
-
- Result = TRUE;
- // Always Succeeds.
- *AgesaStatus = AGESA_SUCCESS;
-
- if (GetNodeId (Socket, Module, &Node, StdHeader)) {
- // socket is populated
- PciAddress->AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0);
- PciAddress->Address.Device = PciAddress->Address.Device + Node;
- } else {
- // socket is not populated
- PciAddress->AddressValue = ILLEGAL_SBDFO;
- Result = FALSE;
- }
- return Result;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * "Who am I" for the current running core.
- *
- * @param[in] StdHeader Header for library and services.
- * @param[out] Socket The current Core's Socket
- * @param[out] Module The current Core's Processor Module
- * @param[out] Core The current Core's core id.
- * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
- *
- */
-VOID
-IdentifyCore (
- IN AMD_CONFIG_PARAMS *StdHeader,
- OUT UINT32 *Socket,
- OUT UINT32 *Module,
- OUT UINT32 *Core,
- OUT AGESA_STATUS *AgesaStatus
- )
-{
- AP_MAIL_INFO ApMailboxInfo;
- UINT32 CurrentCore;
-
- // Always Succeeds.
- *AgesaStatus = AGESA_SUCCESS;
-
- GetApMailbox (&ApMailboxInfo.Info, StdHeader);
- ASSERT (ApMailboxInfo.Fields.Socket < MAX_SOCKETS);
- ASSERT (ApMailboxInfo.Fields.Module < MAX_DIES);
- *Socket = (UINT8)ApMailboxInfo.Fields.Socket;
- *Module = (UINT8)ApMailboxInfo.Fields.Module;
-
- // Get Core Id
- GetCurrentCore (&CurrentCore, StdHeader);
- *Core = (UINT8)CurrentCore;
-}
-
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S - cpu component General Services
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Get the current Platform's number of Sockets, regardless of how many are populated.
- *
- * The Options component can provide how many sockets are available in system.
- * This can be used to avoid testing presence of Processors in Sockets which don't exist.
- * The result can be one socket to the maximum possible sockets of any supported processor family.
- * You cannot assume that all sockets contain a processor or that the sockets have processors
- * installed in any particular order. Do not convert this number to a number of nodes.
- *
- * @return The number of available sockets for the platform.
- *
- */
-UINT32
-GetPlatformNumberOfSockets ()
-{
- return TopologyConfiguration.PlatformNumberOfSockets;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Get the number of Modules to check presence in each Processor.
- *
- * The Options component can provide how many modules need to be check for presence in each
- * processor, regardless whether all, or any, processor have that many modules present on this boot.
- * The result can be one module to the maximum possible modules of any supported processor family.
- * You cannot assume that Modules are in any particular order, especially with respect to node id.
- *
- * @return The maximum number of modules in each processor.
- *
- */
-UINT32
-GetPlatformNumberOfModules ()
-{
- return TopologyConfiguration.PlatformNumberOfModules;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Is a processor present in Socket?
- *
- * Check to see if any possible module of the processor is present. This provides
- * support for a few cases where a PCI address isn't needed, but code still needs to
- * iterate by Socket.
- *
- * @param[in] Socket The socket which is being tested
- * @param[in] StdHeader Header for library and services.
- *
- * @retval TRUE The socket has a processor installed
- * @retval FALSE The socket is empty (or the processor is dead).
- *
- */
-BOOLEAN
-IsProcessorPresent (
- IN UINT32 Socket,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- SOCKET_DIE_TO_NODE_MAP pSocketDieMap;
- LOCATE_HEAP_PTR SocketDieHeapDataBlock;
- BOOLEAN Result;
- UINT32 Module;
- AGESA_STATUS Status;
-
- ASSERT (Socket < MAX_SOCKETS);
- Result = FALSE;
- SocketDieHeapDataBlock.BufferHandle = SOCKET_DIE_MAP_HANDLE;
-
- // Get data block from heap
- Status = HeapLocateBuffer (&SocketDieHeapDataBlock, StdHeader);
- pSocketDieMap = (SOCKET_DIE_TO_NODE_MAP)SocketDieHeapDataBlock.BufferPtr;
- ASSERT ((pSocketDieMap != NULL) && (Status == AGESA_SUCCESS));
- for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
- if ((*pSocketDieMap)[Socket][Module].Node != 0xFF) {
- Result = TRUE;
- break;
- }
- }
- return Result;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Provide the number of installed processors (not Nodes! and not Sockets!)
- *
- * Iterate over the Socket, Module to Node Map, counting the number of present nodes.
- * Do not use this as a Node Count! Do not use this as the number of Sockets! (This
- * is for APIC ID utilities.)
- *
- * @param[in] StdHeader Header for library and services.
- *
- * @return the number of processors installed
- *
- */
-UINT32
-GetNumberOfProcessors (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- SOCKET_DIE_TO_NODE_MAP pSocketDieMap;
- LOCATE_HEAP_PTR SocketDieHeapDataBlock;
- UINT32 Result;
- UINT32 Socket;
- UINT32 Module;
- AGESA_STATUS Status;
-
- Result = 0;
- SocketDieHeapDataBlock.BufferHandle = SOCKET_DIE_MAP_HANDLE;
-
- // Get data block from heap
- Status = HeapLocateBuffer (&SocketDieHeapDataBlock, StdHeader);
- pSocketDieMap = (SOCKET_DIE_TO_NODE_MAP)SocketDieHeapDataBlock.BufferPtr;
- ASSERT ((pSocketDieMap != NULL) && (Status == AGESA_SUCCESS));
- for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
- for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
- if ((*pSocketDieMap)[Socket][Module].Node != 0xFF) {
- Result++;
- break;
- }
- }
- }
- return Result;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * For a specific Node, get its Socket and Module ids.
- *
- * If asking for the current running Node, read the mailbox socket, module. Specific Node,
- * locate the Node to Socket/Module Map in heap, and return the ids, if present.
- *
- * @param[in] Node What Socket and Module is this Node?
- * @param[out] Socket The Socket containing that Node.
- * @param[out] Module The Processor Module of that Node.
- * @param[in] StdHeader Header for library and services.
- *
- * @retval TRUE Node is present, Socket, Module are valid.
- * @retval FALSE Node is not present, why do you ask?
- */
-BOOLEAN
-GetSocketModuleOfNode (
- IN UINT32 Node,
- OUT UINT32 *Socket,
- OUT UINT32 *Module,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- NODE_TO_SOCKET_DIE_MAP pNodeMap;
- LOCATE_HEAP_PTR SocketDieHeapDataBlock;
- BOOLEAN Result;
- AGESA_STATUS Status;
-
- Result = FALSE;
-
- ASSERT (Node < MAX_NODES);
-
- // Get Map from heap
- SocketDieHeapDataBlock.BufferHandle = NODE_ID_MAP_HANDLE;
- Status = HeapLocateBuffer (&SocketDieHeapDataBlock, StdHeader);
- pNodeMap = (NODE_TO_SOCKET_DIE_MAP)SocketDieHeapDataBlock.BufferPtr;
- ASSERT ((pNodeMap != NULL) && (Status == AGESA_SUCCESS));
- *Socket = (*pNodeMap)[Node].Socket;
- *Module = (*pNodeMap)[Node].Die;
- if ((*pNodeMap)[Node].Socket != 0xFF) {
- Result = TRUE;
- }
- return Result;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Get the current core's Processor APIC Index.
- *
- * The Processor APIC Index is the position of the current processor in the APIC id
- * assignment. Processors are ordered in node id order. This is not the same, however,
- * as the node id of the current socket and module or the current socket id.
- *
- * @param[in] Node The current desired core's node id (usually the current core).
- * @param[in] StdHeader Header for library and services.
- *
- * @return Processor APIC Index
- *
- */
-UINT32
-GetProcessorApicIndex (
- IN UINT32 Node,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 ProcessorApicIndex;
- UINT32 PreviousSocket;
- UINT32 CurrentSocket;
- UINT32 Ignored;
- UINT32 i;
-
- ASSERT (Node < MAX_NODES);
-
- // Calculate total APIC devices up to Current Node, Core.
- ProcessorApicIndex = 0;
- PreviousSocket = 0xFF;
- for (i = 0; i < (Node + 1); i++) {
- GetSocketModuleOfNode (i, &CurrentSocket, &Ignored, StdHeader);
- if (CurrentSocket != PreviousSocket) {
- ProcessorApicIndex++;
- PreviousSocket = CurrentSocket;
- }
- }
- // Convert to Index (zero based) from count (one based).
- ProcessorApicIndex--;
- return ProcessorApicIndex;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns current node number
- *
- * @param[out] Node This Core's Node id
- * @param[in] StdHeader Header for library and services.
- *
- */
-VOID
-GetCurrentNodeNum (
- OUT UINT32 *Node,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AP_MAIL_INFO ApMailboxInfo;
-
- // Get the Node Id from the Mailbox.
- GetApMailbox (&ApMailboxInfo.Info, StdHeader);
- ASSERT (ApMailboxInfo.Fields.Node < MAX_NODES);
- *Node = ApMailboxInfo.Fields.Node;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Writes to all nodes on the executing core's socket.
- *
- * @param[in] PciAddress The Function and Register to update
- * @param[in] Mask The bitwise AND mask to apply to the current register value
- * @param[in] Data The bitwise OR mask to apply to the current register value
- * @param[in] StdHeader Header for library and services.
- *
- */
-VOID
-ModifyCurrentSocketPci (
- IN PCI_ADDR *PciAddress,
- IN UINT32 Mask,
- IN UINT32 Data,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Socket;
- UINT32 Module;
- UINT32 Core;
- UINT32 PciRegister;
- AGESA_STATUS AgesaStatus;
- PCI_ADDR Reg;
-
- IdentifyCore (StdHeader, &Socket, &Module, &Core, &AgesaStatus);
-
- for (Module = 0; Module < (UINT8)GetPlatformNumberOfModules (); Module++) {
- if (GetPciAddress (StdHeader, Socket, Module, &Reg, &AgesaStatus)) {
- Reg.Address.Function = PciAddress->Address.Function;
- Reg.Address.Register = PciAddress->Address.Register;
- LibAmdPciRead (AccessWidth32, Reg, &PciRegister, StdHeader);
- PciRegister &= Mask;
- PciRegister |= Data;
- LibAmdPciWrite (AccessWidth32, Reg, &PciRegister, StdHeader);
- }
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns Total number of active cores in the current socket
- *
- * @param[out] CoreCount The cores in this processor.
- * @param[in] StdHeader Header for library and services.
- *
- */
-VOID
-GetActiveCoresInCurrentSocket (
- OUT UINT32 *CoreCount,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- CPUID_DATA CpuidDataStruct;
- UINT32 TotalCoresCount;
-
- LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuidDataStruct, StdHeader);
- TotalCoresCount = (CpuidDataStruct.ECX_Reg & 0x000000FF) + 1;
- *CoreCount = TotalCoresCount;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Provides the Total number of active cores in the current core's node.
- *
- * @param[in] StdHeader Header for library and services.
- *
- * @return The current node core count
- */
-UINTN
-GetActiveCoresInCurrentModule (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Socket;
- UINT32 Module;
- UINT32 Core;
- UINT32 LowCore;
- UINT32 HighCore;
- UINT32 ProcessorCoreCount;
- AGESA_STATUS AgesaStatus;
-
- ProcessorCoreCount = 0;
-
- IdentifyCore (StdHeader, &Socket, &Module, &Core, &AgesaStatus);
- if (GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader)) {
- ProcessorCoreCount = ((HighCore - LowCore) + 1);
- }
- return ProcessorCoreCount;
-}
-
-/**
- * Provide the number of compute units on current module.
- *
- *
- * @param[in] StdHeader Header for library and services.
- *
- * @return The current compute unit counts.
- *
- */
-UINTN
-GetNumberOfCompUnitsInCurrentModule (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Socket;
- UINT32 Module;
- UINT32 CurrentCore;
- UINT32 ComputeUnitCount;
- UINT32 Enabled;
- AGESA_STATUS IgnoredSts;
- LOCATE_HEAP_PTR SocketDieHeapDataBlock;
- SOCKET_DIE_TO_NODE_MAP pSocketDieMap;
-
- ComputeUnitCount = 0;
-
- ASSERT ((GetComputeUnitMapping (StdHeader) == AllCoresMapping) ||
- (GetComputeUnitMapping (StdHeader) == EvenCoresMapping));
-
- IdentifyCore (StdHeader, &Socket, &Module, &CurrentCore, &IgnoredSts);
- // Get data block from heap
- SocketDieHeapDataBlock.BufferHandle = SOCKET_DIE_MAP_HANDLE;
- IgnoredSts = HeapLocateBuffer (&SocketDieHeapDataBlock, StdHeader);
- pSocketDieMap = (SOCKET_DIE_TO_NODE_MAP)SocketDieHeapDataBlock.BufferPtr;
- ASSERT ((pSocketDieMap != NULL) && (IgnoredSts == AGESA_SUCCESS));
- // Current Core's socket, module must be present.
- ASSERT ((*pSocketDieMap)[Socket][Module].Node != 0xFF);
- // Process compute unit info
- Enabled = (*pSocketDieMap)[Socket][Module].EnabledComputeUnits;
-
- while (Enabled > 0) {
- if ((Enabled & 0x1) != 0) {
- ComputeUnitCount++;
- }
- Enabled >>= 1;
- }
-
- return ComputeUnitCount;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Provides the Total number of active cores in the given socket.
- *
- * @param[in] Socket Get a core count for the processor in this socket.
- * @param[out] CoreCount Its core count
- * @param[in] StdHeader Header for library and services.
- *
- * @retval TRUE A processor is present in the Socket and the CoreCount is valid.
- * @retval FALSE The Socket does not have a Processor
- */
-BOOLEAN
-GetActiveCoresInGivenSocket (
- IN UINT32 Socket,
- OUT UINT32 *CoreCount,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Module;
- UINT32 LowCore;
- UINT32 HighCore;
- UINT32 ProcessorCoreCount;
- BOOLEAN Result;
-
- Result = FALSE;
- ProcessorCoreCount = 0;
-
- for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
- if (GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader)) {
- ProcessorCoreCount = ProcessorCoreCount + ((HighCore - LowCore) + 1);
- Result = TRUE;
- } else {
- break;
- }
- }
- *CoreCount = ProcessorCoreCount;
- return Result;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Provides the range of Cores in a Processor which are in a Module.
- *
- * Cores are named uniquely in a processor, 0 to TotalCores. Any module in the processor has
- * a set of those cores, named from LowCore to HighCore.
- *
- * @param[in] Socket Get a core range for the processor in this socket.
- * @param[in] Module Get a core range for this Module in the processor.
- * @param[out] LowCore The lowest Processor Core in the Module.
- * @param[out] HighCore The highest Processor Core in the Module.
- * @param[in] StdHeader Header for library and services.
- *
- * @retval TRUE A processor is present in the Socket and the Core Range is valid.
- * @retval FALSE The Socket does not have a Processor
- */
-BOOLEAN
-GetGivenModuleCoreRange (
- IN UINT32 Socket,
- IN UINT32 Module,
- OUT UINT32 *LowCore,
- OUT UINT32 *HighCore,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- SOCKET_DIE_TO_NODE_MAP pSocketDieMap;
- LOCATE_HEAP_PTR SocketDieHeapDataBlock;
- BOOLEAN Result;
- AGESA_STATUS Status;
-
- ASSERT (Socket < MAX_SOCKETS);
- ASSERT (Module < MAX_DIES);
- Result = FALSE;
- SocketDieHeapDataBlock.BufferHandle = SOCKET_DIE_MAP_HANDLE;
-
- // Get data block from heap
- Status = HeapLocateBuffer (&SocketDieHeapDataBlock, StdHeader);
- pSocketDieMap = (SOCKET_DIE_TO_NODE_MAP)SocketDieHeapDataBlock.BufferPtr;
- ASSERT ((pSocketDieMap != NULL) && (Status == AGESA_SUCCESS));
- *LowCore = (*pSocketDieMap)[Socket][Module].LowCore;
- *HighCore = (*pSocketDieMap)[Socket][Module].HighCore;
- if ((*pSocketDieMap)[Socket][Module].Node != 0xFF) {
- Result = TRUE;
- }
- return Result;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns the current running core number.
- *
- * @param[out] Core The core id.
- * @param[in] StdHeader Header for library and services.
- *
- */
-VOID
-GetCurrentCore (
- OUT UINT32 *Core,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- CPUID_DATA CpuidDataStruct;
- UINT32 LocalApicId;
- UINT32 ApicIdCoreIdSize;
- CORE_ID_POSITION InitApicIdCpuIdLo;
- CPU_SPECIFIC_SERVICES *FamilyServices;
-
- GetCpuServicesOfCurrentCore (&FamilyServices, StdHeader);
- ASSERT (FamilyServices != NULL);
-
- // Read CPUID ebx[31:24] to get initial APICID
- LibAmdCpuidRead (AMD_CPUID_APICID_LPC_BID, &CpuidDataStruct, StdHeader);
- LocalApicId = (CpuidDataStruct.EBX_Reg & 0xFF000000) >> 24;
-
- // Find the core ID size.
- LibAmdCpuidRead (AMD_CPUID_ASIZE_PCCOUNT, &CpuidDataStruct, StdHeader);
- ApicIdCoreIdSize = (CpuidDataStruct.ECX_Reg & 0x0000F000) >> 12;
-
- InitApicIdCpuIdLo = FamilyServices->CoreIdPositionInInitialApicId (FamilyServices, StdHeader);
- ASSERT (InitApicIdCpuIdLo < CoreIdPositionMax);
-
- // Now extract the core ID from the Apic ID by right justifying the id and masking off non-core Id bits.
- *Core = ((LocalApicId >> ((1 - (UINT32)InitApicIdCpuIdLo) * (MAX_CORE_ID_SIZE - ApicIdCoreIdSize))) &
- (MAX_CORE_ID_MASK >> (MAX_CORE_ID_SIZE - ApicIdCoreIdSize)));
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns current node, and core number.
- *
- * @param[out] Node The node id of the current core's node.
- * @param[out] Core The core id if the current core.
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-GetCurrentNodeAndCore (
- OUT UINT32 *Node,
- OUT UINT32 *Core,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- // Get Node Id
- GetCurrentNodeNum (Node, StdHeader);
-
- // Get Core Id
- GetCurrentCore (Core, StdHeader);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Is the current core a primary core of it's node?
- *
- * @param[in] StdHeader Config handle for library and services.
- *
- * @retval TRUE Is Primary Core
- * @retval FALSE Is not Primary Core
- *
- */
-BOOLEAN
-IsCurrentCorePrimary (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- BOOLEAN Result;
- UINT32 Core;
- UINT32 Socket;
- UINT32 Module;
- UINT32 PrimaryCore;
- UINT32 IgnoredCore;
- AGESA_STATUS IgnoredSts;
-
- Result = FALSE;
-
- IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
- GetGivenModuleCoreRange (Socket, Module, &PrimaryCore, &IgnoredCore, StdHeader);
- if (Core == PrimaryCore) {
- Result = TRUE;
- }
- return Result;
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns node id based on SocketId and ModuleId.
- *
- * @param[in] SocketId The socket to look up
- * @param[in] ModuleId The module in that socket
- * @param[out] NodeId Provide the corresponding Node Id.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @retval TRUE The socket is populated
- * @retval FALSE The socket is not populated
- *
- */
-BOOLEAN
-GetNodeId (
- IN UINT32 SocketId,
- IN UINT32 ModuleId,
- OUT UINT8 *NodeId,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- SOCKET_DIE_TO_NODE_MAP pSocketDieMap;
- LOCATE_HEAP_PTR SocketDieHeapDataBlock;
- BOOLEAN Result;
- AGESA_STATUS Status;
-
- Result = FALSE;
- SocketDieHeapDataBlock.BufferHandle = SOCKET_DIE_MAP_HANDLE;
-
- // Get data block from heap
- Status = HeapLocateBuffer (&SocketDieHeapDataBlock, StdHeader);
- pSocketDieMap = (SOCKET_DIE_TO_NODE_MAP)SocketDieHeapDataBlock.BufferPtr;
- ASSERT ((pSocketDieMap != NULL) && (Status == AGESA_SUCCESS));
- *NodeId = (*pSocketDieMap)[SocketId][ModuleId].Node;
- if ((*pSocketDieMap)[SocketId][ModuleId].Node != 0xFF) {
- Result = TRUE;
- }
- return Result;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Get the cached AP Mailbox Info if available, or read the info from the hardware.
- *
- * Locate the known AP Mailbox Info Cache buffer in this core's local heap. If it
- * doesn't exist, read the hardware to get the info.
- * This routine gets the main AP mailbox, not the system degree.
- *
- * @param[out] ApMailboxInfo Provide the info in this AP core's mailbox
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-GetApMailbox (
- OUT UINT32 *ApMailboxInfo,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_STATUS Ignored;
- LOCATE_HEAP_PTR LocalApMailboxCache;
- CPU_SPECIFIC_SERVICES *FamilyServices;
- AP_MAILBOXES ApMailboxes;
- BOOLEAN IamBsp;
-
- IamBsp = IsBsp (StdHeader, &Ignored);
- LocalApMailboxCache.BufferHandle = LOCAL_AP_MAIL_BOX_CACHE_HANDLE;
- if (((StdHeader->HeapStatus == HEAP_LOCAL_CACHE) || IamBsp) &&
- (HeapLocateBuffer (&LocalApMailboxCache, StdHeader) == AGESA_SUCCESS)) {
- // If during HEAP_LOCAL_CACHE stage, we always try to get ApMailbox from heap
- // If we're not in HEAP_LOCAL_CACHE stage, only BSP can get ApMailbox from heap
- *ApMailboxInfo = ((AP_MAILBOXES *) LocalApMailboxCache.BufferPtr)->ApMailInfo.Info;
- } else if (!IamBsp) {
- // If this is an AP, the hardware register should be good.
- GetCpuServicesOfCurrentCore (&FamilyServices, StdHeader);
- ASSERT (FamilyServices != NULL);
- FamilyServices->GetApMailboxFromHardware (FamilyServices, &ApMailboxes, StdHeader);
- *ApMailboxInfo = ApMailboxes.ApMailInfo.Info;
- } else {
- // This is the BSC. The hardware mailbox has not been set up yet.
- ASSERT (FALSE);
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Cache the Ap Mailbox info in our local heap for later use.
- *
- * This enables us to use the info even after the mailbox register is initialized
- * with operational values. Get all the AP mailboxes and keep them in one buffer.
- *
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-CacheApMailbox (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
- AP_MAILBOXES ApMailboxes;
- CPU_SPECIFIC_SERVICES *FamilyServices;
-
- GetCpuServicesOfCurrentCore (&FamilyServices, StdHeader);
- ASSERT (FamilyServices != NULL);
-
- // Get mailbox from hardware.
- FamilyServices->GetApMailboxFromHardware (FamilyServices, &ApMailboxes, StdHeader);
-
- // Allocate heap for the info
- AllocHeapParams.RequestedBufferSize = sizeof (AP_MAILBOXES);
- AllocHeapParams.BufferHandle = LOCAL_AP_MAIL_BOX_CACHE_HANDLE;
- AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
- if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
- *(AP_MAILBOXES *)AllocHeapParams.BufferPtr = ApMailboxes;
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Compute the degree of the system.
- *
- * The degree of a system is the maximum degree of any node. The degree of a node is the
- * number of nodes to which it is directly connected (not considering width or redundant
- * links).
- *
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-UINTN
-GetSystemDegree (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AP_MAILBOXES *ApMailboxes;
- LOCATE_HEAP_PTR LocalApMailboxCache;
- AGESA_STATUS Status;
-
- // Get data block from heap
- LocalApMailboxCache.BufferHandle = LOCAL_AP_MAIL_BOX_CACHE_HANDLE;
- Status = HeapLocateBuffer (&LocalApMailboxCache, StdHeader);
- // non-Success handled by ASSERT not NULL below.
- ApMailboxes = (AP_MAILBOXES *)LocalApMailboxCache.BufferPtr;
- ASSERT ((ApMailboxes != NULL) && (Status == AGESA_SUCCESS));
- return ApMailboxes->ApMailExtInfo.Fields.SystemDegree;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Spins until the number of microseconds specified have
- * expired regardless of CPU operational frequency.
- *
- * @param[in] Microseconds Wait time in microseconds
- * @param[in] StdHeader Header for library and services
- *
- */
-VOID
-WaitMicroseconds (
- IN UINT32 Microseconds,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 TscRateInMhz;
- UINT64 NumberOfTicks;
- UINT64 InitialTsc;
- UINT64 CurrentTsc;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
-
- LibAmdMsrRead (TSC, &InitialTsc, StdHeader);
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
- FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRateInMhz, StdHeader);
- NumberOfTicks = Microseconds * TscRateInMhz;
- do {
- LibAmdMsrRead (TSC, &CurrentTsc, StdHeader);
- } while ((CurrentTsc - InitialTsc) < NumberOfTicks);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * A boolean function determine executed CPU is BSP core.
- *
- * @param[in,out] StdHeader Header for library and services
- * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
- *
- */
-BOOLEAN
-IsBsp (
- IN OUT AMD_CONFIG_PARAMS *StdHeader,
- OUT AGESA_STATUS *AgesaStatus
- )
-{
- UINT64 MsrData;
-
- // Always Succeeds.
- *AgesaStatus = AGESA_SUCCESS;
-
- // Read APIC_BASE register (0x1B), bit[8] returns 1 for BSP
- LibAmdMsrRead (MSR_APIC_BAR, &MsrData, StdHeader);
- if ((MsrData & BIT8) != 0 ) {
- return TRUE;
- } else {
- return FALSE;
- }
-
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Get the compute unit mapping algorithm.
- *
- * Look up the compute unit values for the current core's socket/module and find the matching
- * core pair map item. This will tell us how to determine the core's status.
- *
- * @param[in] StdHeader Header for library and services
- *
- * @retval AllCoresMapping Each core is in a compute unit of its own.
- * @retval EvenCoresMapping Even/Odd pairs of cores are in each compute unit.
- */
-COMPUTE_UNIT_MAPPING
-GetComputeUnitMapping (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 CurrentCore;
- UINT32 Module;
- UINT32 Socket;
- UINT8 Enabled;
- UINT8 DualCore;
- AGESA_STATUS IgnoredSts;
- SOCKET_DIE_TO_NODE_MAP pSocketDieMap;
- LOCATE_HEAP_PTR SocketDieHeapDataBlock;
- CPU_SPECIFIC_SERVICES *FamilyServices;
- CORE_PAIR_MAP *CorePairMap;
- COMPUTE_UNIT_MAPPING Result;
-
- // Invalid mapping, unless we find one.
- Result = MaxComputeUnitMapping;
-
- IdentifyCore (StdHeader, &Socket, &Module, &CurrentCore, &IgnoredSts);
- GetCpuServicesOfCurrentCore (&FamilyServices, StdHeader);
- ASSERT (FamilyServices != NULL);
-
- // Get data block from heap
- SocketDieHeapDataBlock.BufferHandle = SOCKET_DIE_MAP_HANDLE;
- IgnoredSts = HeapLocateBuffer (&SocketDieHeapDataBlock, StdHeader);
- pSocketDieMap = (SOCKET_DIE_TO_NODE_MAP)SocketDieHeapDataBlock.BufferPtr;
- ASSERT ((pSocketDieMap != NULL) && (IgnoredSts == AGESA_SUCCESS));
- // Current Core's socket, module must be present.
- ASSERT ((*pSocketDieMap)[Socket][Module].Node != 0xFF);
-
- // Process compute unit info
- Enabled = (*pSocketDieMap)[Socket][Module].EnabledComputeUnits;
- DualCore = (*pSocketDieMap)[Socket][Module].DualCoreComputeUnits;
- CorePairMap = FamilyServices->CorePairMap;
- if ((Enabled != 0) && (CorePairMap != NULL)) {
- while (CorePairMap->Enabled != 0xFF) {
- if ((Enabled == CorePairMap->Enabled) && (DualCore == CorePairMap->DualCore)) {
- break;
- }
- CorePairMap++;
- }
- // The assert is for finding a processor configured in a way the core pair map doesn't support.
- ASSERT (CorePairMap->Enabled != 0xFF);
- Result = CorePairMap->Mapping;
- } else {
- // Families that don't have compute units act as though each core is in its own compute unit
- // and all cores are primary
- Result = AllCoresMapping;
- }
- return Result;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Is current core the primary core of its compute unit?
- *
- * Get the mapping algorithm and the current core number. Selecting First/Last ordering for
- * primary @b ASSUMES cores are launched in ascending core number order.
- *
- * @param[in] Selector Select whether first or last core has the primary core role.
- * @param[in] StdHeader Header for library and services
- *
- * @retval TRUE This is the primary core of a compute unit.
- * @retval FALSE This is the second shared core of a compute unit.
- *
- */
-BOOLEAN
-IsCorePairPrimary (
- IN COMPUTE_UNIT_PRIMARY_SELECTOR Selector,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- BOOLEAN Result;
- UINT32 CurrentCore;
- UINT32 Module;
- UINT32 Socket;
- AGESA_STATUS IgnoredSts;
-
- IdentifyCore (StdHeader, &Socket, &Module, &CurrentCore, &IgnoredSts);
-
- Result = FALSE;
- switch (GetComputeUnitMapping (StdHeader)) {
- case AllCoresMapping:
- // All cores are primaries
- Result = TRUE;
- break;
- case EvenCoresMapping:
- // Even core numbers are first to execute, odd cores are last to execute
- if (Selector == FirstCoreIsComputeUnitPrimary) {
- Result = (BOOLEAN) ((CurrentCore & 1) == 0);
- } else {
- Result = (BOOLEAN) ((CurrentCore & 1) != 0);
- }
- break;
- default:
- ASSERT (FALSE);
- }
- return Result;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Are the two specified cores shared in a compute unit?
- *
- * Look up the compute unit values for the current core's socket/module and find the matching
- * core pair map item. This will tell us how to determine the core's status.
- *
- * @param[in] Socket The processor in this socket is to be checked
- * @param[in] Module The processor in this module is to be checked
- * @param[in] CoreA One of the two cores to check
- * @param[in] CoreB The other core to be checked
- * @param[in] StdHeader Header for library and services
- *
- * @retval TRUE The cores are in the same compute unit.
- * @retval FALSE The cores are not in the same compute unit, or the processor does
- * not have compute units.
- *
- */
-BOOLEAN
-AreCoresPaired (
- IN UINT32 Socket,
- IN UINT32 Module,
- IN UINT32 CoreA,
- IN UINT32 CoreB,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- BOOLEAN Result;
-
- Result = FALSE;
- switch (GetComputeUnitMapping (StdHeader)) {
- case AllCoresMapping:
- // No cores are sharing a compute unit
- Result = FALSE;
- break;
- case EvenCoresMapping:
- // Even core numbers are paired with odd core numbers, n with n + 1
- if ((CoreA & 1) == 0) {
- Result = (BOOLEAN) (CoreA == (CoreB - 1));
- } else {
- Result = (BOOLEAN) (CoreA == (CoreB + 1));
- }
- break;
- default:
- ASSERT (FALSE);
- }
- return Result;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * This routine programs the registers necessary to get the PCI MMIO mechanism
- * up and functioning.
- *
- * @param[in] StdHeader Pointer to structure containing the function call
- * whose parameter structure is to be created, the
- * allocation method, and a pointer to the newly
- * created structure.
- *
- */
-VOID
-InitializePciMmio (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 EncodedSize;
- UINT64 MsrRegister;
-
- // Make sure that Standard header is valid
- ASSERT (StdHeader != NULL);
-
- if ((UserOptions.CfgPciMmioAddress != 0) && (UserOptions.CfgPciMmioSize != 0)) {
- EncodedSize = LibAmdBitScanForward (UserOptions.CfgPciMmioSize);
- MsrRegister = ((UserOptions.CfgPciMmioAddress | BIT0) | (EncodedSize << 2));
- LibAmdMsrWrite (MSR_MMIO_Cfg_Base, &MsrRegister, StdHeader);
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/cpuInitEarlyTable.c b/src/vendorcode/amd/agesa/Proc/CPU/cpuInitEarlyTable.c
deleted file mode 100644
index a7844aa..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/cpuInitEarlyTable.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Initialize the 'common' way of running early initialization.
- *
- * Returns the table of initialization steps to perform at
- * AmdInitEarly.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-#include "cpuEarlyInit.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_CPUINITEARLYTABLE_FILECODE
-
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-extern F_PERFORM_EARLY_INIT_ON_CORE McaInitializationAtEarly;
-extern F_PERFORM_EARLY_INIT_ON_CORE SetRegistersFromTablesAtEarly;
-extern F_PERFORM_EARLY_INIT_ON_CORE SetBrandIdRegistersAtEarly;
-extern F_PERFORM_EARLY_INIT_ON_CORE LocalApicInitializationAtEarly;
-extern F_PERFORM_EARLY_INIT_ON_CORE LoadMicrocodePatchAtEarly;
-
-CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA CommonEarlyInitOnCoreTable[] =
-{
- {McaInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION},
- {SetRegistersFromTablesAtEarly, PERFORM_EARLY_ANY_CONDITION},
- {SetBrandIdRegistersAtEarly, PERFORM_EARLY_ANY_CONDITION},
- {LocalApicInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION},
- {LoadMicrocodePatchAtEarly, PERFORM_EARLY_ANY_CONDITION},
- {NULL, 0}
-};
-
-/*------------------------------------------------------------------------------------*/
-/**
- * Initializer routine that may be invoked at AmdCpuEarly to return the steps that a
- * processor that uses the standard initialization steps should take.
- *
- * @CpuServiceMethod{::F_GET_EARLY_INIT_TABLE}.
- *
- * @param[in] FamilyServices The current Family Specific Services.
- * @param[out] Table Table of appropriate init steps for the executing core.
- * @param[in] EarlyParams Service Interface structure to initialize.
- * @param[in] StdHeader Opaque handle to standard config header.
- *
- */
-VOID
-GetCommonEarlyInitOnCoreTable (
- IN CPU_SPECIFIC_SERVICES *FamilyServices,
- OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table,
- IN AMD_CPU_EARLY_PARAMS *EarlyParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- *Table = CommonEarlyInitOnCoreTable;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/cpuLateInit.c b/src/vendorcode/amd/agesa/Proc/CPU/cpuLateInit.c
deleted file mode 100644
index 3915e49..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/cpuLateInit.c
+++ /dev/null
@@ -1,286 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU Late Init API
- *
- * Contains code for doing any late CPU initialization.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuLateInit.h"
-#include "cpuRegisters.h"
-#include "GeneralServices.h"
-#include "cpuServices.h"
-#include "Filecode.h"
-CODE_GROUP (G3_DXE)
-RDATA_GROUP (G3_DXE)
-
-#define FILECODE PROC_CPU_CPULATEINIT_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-VOID
-DisableCf8ExtCfg (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Performs CPU related initialization at the late entry point
- *
- * This function should be the last function run by the AGESA
- * CPU module and prepares the processor for the operating system
- * bootstrap load process.
- *
- * @param[in] StdHeader Config handle for library and services
- *
- * @retval AGESA_SUCCESS
- *
- */
-AGESA_STATUS
-AmdCpuLate (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- DisableCf8ExtCfg (StdHeader);
- return (AGESA_SUCCESS);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Clear EnableCf8ExtCfg on all socket
- *
- * Clear F3x8C bit 14 EnableCf8ExtCfg
- *
- * @param[in] StdHeader Config handle for library and services
- *
- *
- */
-VOID
-DisableCf8ExtCfg (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_STATUS AgesaStatus;
- PCI_ADDR PciAddress;
- UINT32 Socket;
- UINT32 Module;
- UINT32 PciData;
- UINT32 LegacyPciAccess;
-
- ASSERT (IsBsp (StdHeader, &AgesaStatus));
-
- for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
- for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
- if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &AgesaStatus)) {
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = NB_CFG_HIGH_REG;
- LegacyPciAccess = ((1 << 31) + (PciAddress.Address.Register & 0xFC) + (PciAddress.Address.Function << 8) + (PciAddress.Address.Device << 11) + (PciAddress.Address.Bus << 16) + ((PciAddress.Address.Register & 0xF00) << (24 - 8)));
- // read from PCI register
- LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader);
- LibAmdIoRead (AccessWidth32, IOCFC, &PciData, StdHeader);
- // Disable Cf8ExtCfg
- PciData &= 0xFFFFBFFF;
- // write to PCI register
- LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader);
- LibAmdIoWrite (AccessWidth32, IOCFC, &PciData, StdHeader);
- }
- }
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Calculate an ACPI style checksum
- *
- * Computes the checksum and stores the value to the checksum
- * field of the passed in ACPI table's header.
- *
- * @param[in] Table ACPI table to checksum
- * @param[in] StdHeader Config handle for library and services
- *
- */
-VOID
-ChecksumAcpiTable (
- IN OUT ACPI_TABLE_HEADER *Table,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 *BuffTempPtr;
- UINT8 Checksum;
- UINT32 BufferOffset;
-
- Table->Checksum = 0;
- Checksum = 0;
- BuffTempPtr = (UINT8 *) Table;
- for (BufferOffset = 0; BufferOffset < Table->TableLength; BufferOffset++) {
- Checksum = Checksum - *(BuffTempPtr + BufferOffset);
- }
-
- Table->Checksum = Checksum;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * Run code on every AP in the system.
- *
- * @param[in] ApParams AP task pointer.
- * @param[in] StdHeader Handle to config for library and services
- *
- * @return The most severe AGESA_STATUS returned by an AP.
- *
- */
-AGESA_STATUS
-RunLateApTaskOnAllAPs (
- IN AP_EXE_PARAMS *ApParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 NumberOfSockets;
- UINT32 NumberOfCores;
- UINT8 Socket;
- UINT8 Core;
- UINT8 ApicId;
- UINT32 BscSocket;
- UINT32 Ignored;
- UINT32 BscCore;
- AGESA_STATUS CalledStatus;
- AGESA_STATUS IgnoredStatus;
- AGESA_STATUS AgesaStatus;
-
- ASSERT (IsBsp (StdHeader, &IgnoredStatus));
-
- AgesaStatus = AGESA_SUCCESS;
-
- IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredStatus);
- NumberOfSockets = GetPlatformNumberOfSockets ();
-
- for (Socket = 0; Socket < NumberOfSockets; Socket++) {
- if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
- for (Core = 0; Core < NumberOfCores; Core++) {
- if ((Socket != BscSocket) || (Core != BscCore)) {
- GetApicId (StdHeader, Socket, Core, &ApicId, &IgnoredStatus);
- AGESA_TESTPOINT (TpIfBeforeRunApFromAllAps, StdHeader);
- CalledStatus = AgesaRunFcnOnAp ((UINTN) ApicId, ApParams);
- AGESA_TESTPOINT (TpIfAfterRunApFromAllAps, StdHeader);
- if (CalledStatus > AgesaStatus) {
- AgesaStatus = CalledStatus;
- }
- }
- }
- }
- }
- return AgesaStatus;
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * Run code on core 0 of every socket in the system.
- *
- * @param[in] ApParams AP task pointer.
- * @param[in] StdHeader Handle to config for library and services
- *
- * @return The most severe AGESA_STATUS returned by an AP.
- *
- */
-AGESA_STATUS
-RunLateApTaskOnAllCore0s (
- IN AP_EXE_PARAMS *ApParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 NumberOfSockets;
- UINT8 Socket;
- UINT8 ApicId;
- UINT32 BscSocket;
- UINT32 IgnoredModule;
- UINT32 IgnoredCore;
- AGESA_STATUS CalledStatus;
- AGESA_STATUS IgnoredStatus;
- AGESA_STATUS AgesaStatus;
-
- ASSERT (IsBsp (StdHeader, &IgnoredStatus));
-
- AgesaStatus = AGESA_SUCCESS;
-
- IdentifyCore (StdHeader, &BscSocket, &IgnoredModule, &IgnoredCore, &IgnoredStatus);
- NumberOfSockets = GetPlatformNumberOfSockets ();
-
- for (Socket = 0; Socket < NumberOfSockets; Socket++) {
- if (IsProcessorPresent (Socket, StdHeader)) {
- if (Socket != BscSocket) {
- GetApicId (StdHeader, Socket, 0, &ApicId, &IgnoredStatus);
- AGESA_TESTPOINT (TpIfBeforeRunApFromAllCore0s, StdHeader);
- CalledStatus = AgesaRunFcnOnAp ((UINTN) ApicId, ApParams);
- AGESA_TESTPOINT (TpIfAfterRunApFromAllCore0s, StdHeader);
- if (CalledStatus > AgesaStatus) {
- AgesaStatus = CalledStatus;
- }
- }
- }
- }
- return AgesaStatus;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/cpuLateInit.h b/src/vendorcode/amd/agesa/Proc/CPU/cpuLateInit.h
deleted file mode 100644
index aea840d..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/cpuLateInit.h
+++ /dev/null
@@ -1,821 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU Late Init API functions Prototypes.
- *
- * Contains code for doing any late CPU initialization
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 38082 $ @e \$Date: 2010-09-18 01:51:40 +0800 (Sat, 18 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPU_LATE_INIT_H_
-#define _CPU_LATE_INIT_H_
-
-#include "Filecode.h"
-/*----------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-//----------------------------------------------------------------------------
-// DMI DEFINITIONS AND MACROS
-//
-//----------------------------------------------------------------------------
-#define AP_LATE_TASK_GET_TYPE4_TYPE7 (PROC_CPU_FEATURE_CPUDMI_FILECODE)
-// SMBIOS constant definition
-#define CENTRAL_PROCESSOR 0x03
-#define EXTERNAL_CLOCK_DFLT 200
-#define EXTERNAL_CLOCK_100MHZ 100
-#define UNKNOWN 0x02
-#define P_CHARACTERISTICS 0x4
-#define CACHE_CFG_L1 0x180
-#define CACHE_CFG_L2 0x181
-#define CACHE_CFG_L3 0x182
-#define SRAM_TYPE 0x10
-#define ERR_CORRECT_TYPE 0x06
-#define CACHE_TYPE 0x05
-#define ASSOCIATIVE_2_WAY 0x04
-#define ASSOCIATIVE_16_WAY 0x08
-#define ASSOCIATIVE_OTHER 0x01
-#define SOCKET_POPULATED 0x40
-#define CPU_STATUS_UNKNOWN 0x00
-#define CPU_STATUS_ENABLED 0x01
-
-// Processor Upgrade Definition
-#define P_UPGRADE_UNKNOWN 0x02
-#define P_UPGRADE_NONE 0x06
-#define P_UPGRADE_S1GX 0x16
-#define P_UPGRADE_AM2 0x17
-#define P_UPGRADE_F1207 0x18
-#define P_UPGRADE_G34 0x1A
-#define P_UPGRADE_AM3 0x1B
-#define P_UPGRADE_C32 0x1C
-
-//----------------------------------------------------------------------------
-// SRAT DEFINITIONS AND MACROS
-//
-//----------------------------------------------------------------------------
-#define NorthbridgeCapabilities 0xE8
-#define DRAMBase0 0x40
-#define MMIOBase0 0x80
-#define TOP_MEM 0xC001001A
-#define LOW_NODE_DEVICEID 24
-#define LOW_APICID 0
-
-
-// Miscellaneous AMD related values
-#define MAX_NUMBER_NODES 8
-#define FOURGB 0x01000000 // Use format as in MCT DRAM range registers [39:24]
-
-// Flags
-#define ENABLED 1 // Bit 0
-#define DISABLED 0 // Bit 0
-#define HOTPLUGGABLE 2 // Bit 1
-
-// Affinity Entry Structures
-#define AE_APIC 0
-#define AE_MEMORY 1
-
-
-// Memory Types
-#define TYPE_MEMORY 1
-#define TYPE_RESERVED 2
-#define TYPE_ACPI 3
-#define TYPE_NVS 4
-
-//----------------------------------------------------------------------------
-// SLIT DEFINITIONS AND MACROS
-//
-//----------------------------------------------------------------------------
-#define PROBE_FILTER_CTRL_REG 0x1D4
-#define AMD_ACPI_SLIT_SOCKET_NUM_LENGTH 8
-
-//----------------------------------------------------------------------------
-// P-STATE DEFINITIONS AND MACROS
-//
-//----------------------------------------------------------------------------
-//-------------------------------------
-// ERROR Codes
-//-------------------------------------
-#define NO_ERROR 0x0
-#define USER_DISABLE_ERROR 0x01 // User disabled SSDT generation
-#define CORES_MISSMATCH_PSS_ERROR 0x02 // No PSS match
-#define PNOW_SUPPORT_ERROR 0x04 // One of the Cores do not support PNOW!
-#define PWR_FREQ_MATCH_ERROR 0x08 // FREQ and PWR mismatch
-#define NO_PSS_SIZE_ERROR 0x10 // Error in PSS Size
-#define INVALID_PSTATE_ERROR 0x20 // Invalid Max or only 1 P-State available
-#define NO_PSS_ENTRY 0x0FFFF
-#define INVALID_FREQ 0x0FFFFFFFF
-
-//-------------------------
-// Default definitions
-// AMD BKDG default values
-//-------------------------
-#define DEFAULT_ISOCH_RELIEF_TIME IRT_80uS
-#define DEFAULT_RAMP_VOLTAGE_OFFSET RVO_50mV
-#define DEFAULT_MAX_VOLTAGE_STEP MVS_25mV
-#define DEFAULT_PERF_PRESENT_CAP 0 // default for Desktop
-#define DEFAULT_VOLTAGE_STABLE_TIME (100 / 20) // 100uS
-#define DEFAULT_PLL_LOCK_TIME 2 // 2uS
-#define DEFAULT_TRANSITION_LATENCY 100 // 100uS
-#define DEFAULT_BUS_MASTER_LATENCY 9 // 9uS
-#define DEFAULT_CPU_SCOPE_NUMBER "0UPC"
-
-// Defines for Common ACPI
-// -----------------------------
-#define SCOPE_OPCODE 0x10
-#define NAME_OPCODE 0x08
-#define PACKAGE_OPCODE 0x12
-#define BUFFER_OPCODE 0x11
-#define BYTE_PREFIX_OPCODE 0x0A
-#define WORD_PREFIX_OPCODE 0x0B
-#define DWORD_PREFIX_OPCODE 0x0C
-#define ACPI_BUFFER 0x080A0B11
-
-// Generic Register Descriptor (GDR) Fields
-#define GDR_ASI_SYSTEM_IO 0x01 // Address Space ID
-#define GDR_ASZ_BYTE_ACCESS 0x01 // Address Size
-
-// Defines for ACPI Scope Table
-// ----------------------------
-#define SCOPE_LENGTH (SCOPE_STRUCT_SIZE + \
- PCT_STRUCT_SIZE + \
- PSS_HEADER_STRUCT_SIZE + \
- PSS_BODY_STRUCT_SIZE + \
- PPC_HEADER_BODY_STRUCT_SIZE)
-#define SCOPE_VALUE1 0x5C
-#define SCOPE_VALUE2 0x2E
-#define SCOPE_NAME__ '_'
-#define SCOPE_NAME_P 'P'
-#define SCOPE_NAME_R 'R'
-#define SCOPE_NAME_S 'S'
-#define SCOPE_NAME_B 'B'
-#define SCOPE_NAME_C 'C'
-#define SCOPE_NAME_U 'U'
-#define SCOPE_NAME_0 '0'
-#define SCOPE_NAME_1 '1'
-#define SCOPE_NAME_2 '2'
-#define SCOPE_NAME_3 '3'
-#define SCOPE_NAME_A 'A'
-
-#ifdef OEM_SCOPE_NAME
- #if (OEM_SCOPE_NAME > 'Z') || (OEM_SCOPE_NAME < 'A')
- #error "OEM_SCOPE_NAME: it should be only one char long AND a valid letter (A~Z)"
- #endif
- #define SCOPE_NAME_VALUE OEM_SCOPE_NAME
-#else
- #define SCOPE_NAME_VALUE SCOPE_NAME_C
-#endif // OEM_SCOPE_NAME
-
-#ifdef OEM_SCOPE_NAME1
- #if (!(((OEM_SCOPE_NAME1 >= 'A') && (OEM_SCOPE_NAME1 <= 'Z')) || \
- ((OEM_SCOPE_NAME1 >= '0') && (OEM_SCOPE_NAME1 <= '9')) || \
- (OEM_SCOPE_NAME1 == '_')))
- #error "OEM_SCOPE_NAME1: it should be only one char long AND a valid letter (0~9, A~F)"
- #endif
- #define SCOPE_NAME_VALUE1 OEM_SCOPE_NAME1
-#else
- #define SCOPE_NAME_VALUE1 SCOPE_NAME_0
-#endif // OEM_SCOPE_NAME
-
-// Defines for PCT Control and Status Table
-// ----------------------------------------
-#define PCT_NAME__ '_'
-#define PCT_NAME_P 'P'
-#define PCT_NAME_C 'C'
-#define PCT_NAME_T 'T'
-#define PCT_VALUE1 0x11022C12
-#define PCT_VALUE2 0x0A14
-#define PCT_VALUE3 0x11
-#define GENERIC_REG_DESCRIPTION 0x82
-#define PCT_LENGTH 0x0C
-#define PCT_ADDRESS_SPACE_ID 0x7F
-#define PCT_REGISTER_BIT_WIDTH 0x40
-#define PCT_REGISTER_BIT_OFFSET 0x00
-#define PCT_RESERVED 0x00
-#define PCT_CONTROL_REG_LO 0xC0010062
-#define PCT_CONTROL_REG_HI 0x00
-#define PCT_VALUE4 0x14110079
-#define PCT_VALUE5 0x110A
-#define PCT_STATUS_REG_LO 0x00
-#define PCT_STATUS_REG_HI 0x00
-#define PCT_VALUE6 0x0079
-
-
-// Defines for PSS Header Table
-// ----------------------------
-#define PSS_NAME__ '_'
-#define PSS_NAME_X 'X'
-#define PSS_NAME_P 'P'
-#define PSS_NAME_S 'S'
-#define PSS_LENGTH (sizeof pssBodyStruct + 3)
-#define NUM_OF_ITEMS_IN_PSS 0x00
-
-
-// Defines for PSS Header Table
-// ----------------------------
-#define PSS_PKG_LENGTH 0x20 // PSS_BODY_STRUCT_SIZE - 1
-#define PSS_NUM_OF_ELEMENTS 0x06
-#define PSS_FREQUENCY 0x00
-#define PSS_POWER 0x00
-#define PSS_TRANSITION_LATENCY DEFAULT_TRANSITION_LATENCY
-#define PSS_BUS_MASTER_LATENCY DEFAULT_BUS_MASTER_LATENCY
-#define PSS_CONTROL ((DEFAULT_ISOCH_RELIEF_TIME << 30) + \
- (DEFAULT_RAMP_VOLTAGE_OFFSET << 28) + \
- (DEFAULT_EXT_TYPE << 27) + \
- (DEFAULT_PLL_LOCK_TIME << 20) + \
- (DEFAULT_MAX_VOLTAGE_STEP << 18) + \
- (DEFAULT_VOLTAGE_STABLE_TIME << 11) + \
- (PSS_VID << 6) + PSS_FID)
-#define PSS_STATUS (DEFAULT_EXTENDED_TYPE << 11) + (PSS_VID << 6) + (PSS_FID)
-
-// Defines for XPSS Header Table
-// ----------------------------
-#define XPSS_PKG_LENGTH 0x47 // XPSS_BODY_STRUCT_SIZE - 1
-#define XPSS_NUM_OF_ELEMENTS 0x08
-#define XPSS_ACPI_BUFFER 0x080A0B11
-
-
-// Defines for PPC Header Table
-// ----------------------------
-#define PPC_NAME__ '_'
-#define PPC_NAME_P 'P'
-#define PPC_NAME_C 'C'
-#define PPC_VALUE1 0x0A;
-
-// Defines for PSD Header Table
-// ----------------------------
-#define PSD_NAME__ '_'
-#define PSD_NAME_P 'P'
-#define PSD_NAME_S 'S'
-#define PSD_NAME_D 'D'
-#define PSD_HEADER_LENGTH (PSD_BODY_STRUCT_SIZE + 2)
-#define PSD_VALUE1 0x01
-
-
-// Defines for PSD Header Table
-// ----------------------------
-#define PSD_PKG_LENGTH (PSD_BODY_STRUCT_SIZE - 1)
-#define NUM_OF_ENTRIES 0x05
-#define PSD_NUM_OF_ENTRIES 0x05
-#define PSD_REVISION 0x00
-#define PSD_DEPENDENCY_DOMAIN 0x00
-#define PSD_COORDINATION_TYPE_HW_ALL 0xFE
-#define PSD_COORDINATION_TYPE_SW_ANY 0xFD
-#define PSD_COORDINATION_TYPE_SW_ALL 0xFC
-#define PSD_NUM_OF_PROCESSORS 0x01
-#define PSD_CORE_NUM_PER_COMPUTE_UNIT 0x02
-#define PSD_DOMAIN_COMPUTE_UNIT_MASK 0x7F
-
-
-#define CUSTOM_PSTATE_FLAG 0x55
-#define PSTATE_FLAG_1 0x55
-#define TARGET_PSTATE_FLAG 0xAA
-#define PSTATE_FLAG_2 0xAA
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *----------------------------------------------------------------------------------------
- */
-//----------------------------------------------------------------------------
-// ACPI P-States AML TYPEDEFS, STRUCTURES, ENUMS
-//
-//----------------------------------------------------------------------------
-
-//--------------------------------------------
-// AML code definition
-// (Scope)
-//---------------------------------------------
-/// SCOPE
-typedef struct _SCOPE {
- UINT8 ScopeOpcode; ///< Opcode
- UINT16 ScopeLength; ///< Scope Length
- UINT8 ScopeValue1; ///< Value1
- UINT8 ScopeValue2; ///< Value2
- UINT8 ScopeNamePt1a__; ///< Name Pointer
- UINT8 ScopeNamePt1a_P; ///< Name Pointer
- UINT8 ScopeNamePt1a_R; ///< Name Pointer
- UINT8 ScopeNamePt1b__; ///< Name Pointer
- UINT8 ScopeNamePt2a_C; ///< Name Pointer
- UINT8 ScopeNamePt2a_P; ///< Name Pointer
- UINT8 ScopeNamePt2a_U; ///< Name Pointer
- UINT8 ScopeNamePt2a_0; ///< Name Pointer
-} SCOPE;
-#define SCOPE_STRUCT_SIZE 13 // 13 Bytes
-
-//--------------------------------------------
-// AML code definition
-// (PCT Header and Body)
-//---------------------------------------------
-
-///Performance Control Header
-typedef struct _PCT_HEADER_BODY {
- UINT8 NameOpcode; ///< Opcode
- UINT8 PctName_a__; ///< String "_"
- UINT8 PctName_a_P; ///< String "P"
- UINT8 PctName_a_C; ///< String "C"
- UINT8 PctName_a_T; ///< String "T"
- UINT32 Value1; ///< Value1
- UINT16 Value2; ///< Value2
- UINT8 Value3; ///< Value3
- UINT8 GenericRegDescription1; ///< Generic Reg Description
- UINT16 Length1; ///< Length1
- UINT8 AddressSpaceId1; ///< PCT Address Space ID
- UINT8 RegisterBitWidth1; ///< PCT Register Bit Width
- UINT8 RegisterBitOffset1; ///< PCT Register Bit Offset
- UINT8 Reserved1; ///< Reserved
- UINT32 ControlRegAddressLo; ///< Control Register Address Low
- UINT32 ControlRegAddressHi; ///< Control Register Address High
- UINT32 Value4; ///< Value4
- UINT16 Value5; ///< Value 5
- UINT8 GenericRegDescription2; ///< Generic Reg Description
- UINT16 Length2; ///< Length2
- UINT8 AddressSpaceId2; ///< PCT Address Space ID
- UINT8 RegisterBitWidth2; ///< PCT Register Bit Width
- UINT8 RegisterBitOffset2; ///< PCT Register Bit Offset
- UINT8 Reserved2; ///< Reserved
- UINT32 StatusRegAddressLo; ///< Control Register Address Low
- UINT32 StatusRegAddressHi; ///< Control Register Address High
- UINT16 Value6; ///< Values
-} PCT_HEADER_BODY;
-#define PCT_STRUCT_SIZE 50 // 50 Bytes
-
-
-//--------------------------------------------
-// AML code definition
-// (PSS Header)
-//--------------------------------------------
-///Performance Supported States Header
-typedef struct _PSS_HEADER {
- UINT8 NameOpcode; ///< Opcode
- UINT8 PssName_a__; ///< String "_"
- UINT8 PssName_a_P; ///< String "P"
- UINT8 PssName_a_S; ///< String "S"
- UINT8 PssName_b_S; ///< String "S"
- UINT8 PkgOpcode; ///< Package Opcode
- UINT16 PssLength; ///< PSS Length
- UINT8 NumOfItemsInPss; ///< Number of Items in PSS
-} PSS_HEADER;
-#define PSS_HEADER_STRUCT_SIZE 9 // 9 Bytes
-
-
-//--------------------------------------------
-// AML code definition
-// (PSS Body)
-//--------------------------------------------
-///Performance Supported States Body
-typedef struct _PSS_BODY {
- UINT8 PkgOpcode; ///< Package Opcode
- UINT8 PkgLength; ///< Package Length
- UINT8 NumOfElements; ///< Number of Elements
- UINT8 DwordPrefixOpcode1; ///< Prefix Opcode1
- UINT32 Frequency; ///< Frequency
- UINT8 DwordPrefixOpcode2; ///< Prefix Opcode2
- UINT32 Power; ///< Power
- UINT8 DwordPrefixOpcode3; ///< Prefix Opcode3
- UINT32 TransitionLatency; ///< Transition Latency
- UINT8 DwordPrefixOpcode4; ///< Prefix Opcode4
- UINT32 BusMasterLatency; ///< Bus Master Latency
- UINT8 DwordPrefixOpcode5; ///< Prefix Opcode5
- UINT32 Control; ///< Control
- UINT8 DwordPrefixOpcode6; ///< Prefix Opcode6
- UINT32 Status; ///< Status
-} PSS_BODY;
-#define PSS_BODY_STRUCT_SIZE 33 // 33 Bytes
-
-
-/*--------------------------------------------
- * AML code definition
- * (XPSS Header)
- *--------------------------------------------
- */
-/// Extended PSS Header
-typedef struct _XPSS_HEADER {
- UINT8 NameOpcode; ///< 08h
- UINT8 XpssName_a_X; ///< String "X"
- UINT8 XpssName_a_P; ///< String "P"
- UINT8 XpssName_a_S; ///< String "S"
- UINT8 XpssName_b_S; ///< String "S"
- UINT8 PkgOpcode; ///< 12h
- UINT16 XpssLength; ///< XPSS Length
- UINT8 NumOfItemsInXpss; ///< Number of Items in XPSS
-} XPSS_HEADER;
-#define XPSS_HEADER_STRUCT_SIZE 9 // 9 Bytes
-
-/*--------------------------------------------
- * AML code definition
- * (XPSS Body)
- *--------------------------------------------
- */
-/// Extended PSS Body
-typedef struct _XPSS_BODY {
- UINT8 PkgOpcode; ///< 12h
- UINT8 PkgLength; ///< Package Length
- UINT8 XpssValueTbd; ///< XPSS Value
- UINT8 NumOfElements; ///< Number of Elements
- UINT8 DwordPrefixOpcode1; ///< Prefix Opcode1
- UINT32 Frequency; ///< Frequency
- UINT8 DwordPrefixOpcode2; ///< Prefix Opcode2
- UINT32 Power; ///< Power
- UINT8 DwordPrefixOpcode3; ///< Prefix Opcode3
- UINT32 TransitionLatency; ///< Transition Latency
- UINT8 DwordPrefixOpcode4; ///< Prefix Opcode4
- UINT32 BusMasterLatency; ///< Bus Master Latency
- UINT32 ControlBuffer; ///< Control Buffer
- UINT32 ControlLo; ///< Control Low
- UINT32 ControlHi; ///< Control High
- UINT32 StatusBuffer; ///< Status Buffer
- UINT32 StatusLo; ///< Status Low
- UINT32 StatusHi; ///< Status High
- UINT32 ControlMaskBuffer; ///< Control Mask Buffer
- UINT32 ControlMaskLo; ///< Control Mask Low
- UINT32 ControlMaskHi; ///< Control Mask High
- UINT32 StatusMaskBuffer; ///< Status Mask Buffer
- UINT32 StatusMaskLo; ///< Status Mask Low
- UINT32 StatusMaskHi; ///< Status Mask High
-} XPSS_BODY;
-#define XPSS_BODY_STRUCT_SIZE 72 // 72 Bytes
-
-/*--------------------------------------------
- * AML code definition
- * (PPC Header and Body)
- *--------------------------------------------
- */
-/// Performance Present Capabilities Header
-typedef struct _PPC_HEADER_BODY {
- UINT8 NameOpcode; ///< Name Opcode
- UINT8 PpcName_a__; ///< String "_"
- UINT8 PpcName_a_P; ///< String "P"
- UINT8 PpcName_b_P; ///< String "P"
- UINT8 PpcName_a_C; ///< String "C"
- UINT8 Value1; ///< Value
- UINT8 DefaultPerfPresentCap; ///< Default Perf Present Cap
-} PPC_HEADER_BODY;
-#define PPC_HEADER_BODY_STRUCT_SIZE 7 // 7 Bytes
-
-
-/*--------------------------------------------
- * AML code definition
- * (PSD Header)
- *--------------------------------------------
- */
-/// P-State Dependency Header
-typedef struct _PSD_HEADER {
- UINT8 NameOpcode; ///< Name Opcode
- UINT8 PsdName_a__; ///< String "_"
- UINT8 PsdName_a_P; ///< String "P"
- UINT8 PsdName_a_S; ///< String "S"
- UINT8 PsdName_a_D; ///< String "D"
- UINT8 PkgOpcode; ///< Package Opcode
- UINT8 PsdLength; ///< PSD Length
- UINT8 Value1; ///< Value
-} PSD_HEADER;
-#define PSD_HEADER_STRUCT_SIZE 8 // 8 Bytes
-
-/*--------------------------------------------
- * AML code definition
- * (PSD Body)
- *--------------------------------------------
- */
-/// P-State Dependency Body
-typedef struct _PSD_BODY {
- UINT8 PkgOpcode; ///< Package Opcode
- UINT8 PkgLength; ///< Package Length
- UINT8 NumOfEntries; ///< Number of Entries
- UINT8 BytePrefixOpcode1; ///< Prefix Opcode1 in Byte
- UINT8 PsdNumOfEntries; ///< PSD Number of Entries
- UINT8 BytePrefixOpcode2; ///< Prefix Opcode2 in Byte
- UINT8 PsdRevision; ///< PSD Revision
- UINT8 DwordPrefixOpcode1; ///< Prefix Opcode1 in DWord
- UINT32 DependencyDomain; ///< Dependency Domain
- UINT8 DwordPrefixOpcode2; ///< Prefix Opcode2 in DWord
- UINT32 CoordinationType; ///< (0xFC = SW_ALL, 0xFD = SW_ANY, 0xFE = HW_ALL)
- UINT8 DwordPrefixOpcode3; ///< Prefix Opcode3 in DWord
- UINT32 NumOfProcessors; ///< Number of Processors
-} PSD_BODY;
-#define PSD_BODY_STRUCT_SIZE 22 // 22 Bytes
-
-//----------------------------------------------------------------------------
-// WHEA TYPEDEFS, STRUCTURES, ENUMS
-//
-//----------------------------------------------------------------------------
-
-/// HEST MCE TABLE
-typedef struct _AMD_HEST_MCE_TABLE {
- UINT16 TblLength; ///< Length, in bytes, of entire AMD_HEST_MCE structure.
- UINT32 GlobCapInitDataLSD; ///< Holds the value that the OS will program into
- UINT32 GlobCapInitDataMSD; ///< the machine check global capability register(MCG_CAP).
- UINT32 GlobCtrlInitDataLSD; ///< Holds the value that the OS will program into
- UINT32 GlobCtrlInitDataMSD; ///< the machine check global control register(MCG_CTL).
- UINT8 NumHWBanks; ///< The number of hardware error reporting banks.
- UINT8 Rsvd[7]; ///< reserve 7 bytes as spec's required
-} AMD_HEST_MCE_TABLE;
-
-/// HEST CMC TABLE
-typedef struct _AMD_HEST_CMC_TABLE {
- UINT16 TblLength; ///< Length, in bytes, of entire AMD_HEST_CMC structure.
- UINT8 NumHWBanks; ///< The number of hardware error reporting banks.
- UINT8 Rsvd[3]; ///< reserve 3 bytes as spec's required
-} AMD_HEST_CMC_TABLE;
-
-/// HEST BANK
-typedef struct _AMD_HEST_BANK {
- UINT8 BankNum; ///< Zero-based index identifies the machine check error bank.
- UINT8 ClrStatusOnInit; ///< Indicates if the status information in this machine check bank
- ///< is to be cleared during system initialization.
- UINT8 StatusDataFormat; ///< Indicates the format of the data in the status register
- UINT8 ConfWriteEn; ///< This field indicates whether configuration parameters may be
- ///< modified by the OS. If the bit for the associated parameter is
- ///< set, the parameter is writable by the OS.
- UINT32 CtrlRegMSRAddr; ///< Address of the hardware bank's control MSR. Ignored if zero.
-
- UINT32 CtrlInitDataLSD; ///< This is the value the OS will program into the machine check
- UINT32 CtrlInitDataMSD; ///< bank's control register
- UINT32 StatRegMSRAddr; ///< Address of the hardware bank's MCi_STAT MSR. Ignored if zero.
- UINT32 AddrRegMSRAddr; ///< Address of the hardware bank's MCi_ADDR MSR. Ignored if zero.
- UINT32 MiscRegMSRAddr; ///< Address of the hardware bank's MCi_MISC MSR. Ignored if zero.
-} AMD_HEST_BANK;
-
-/// Initial data of AMD_HEST_BANK
-typedef struct _AMD_HEST_BANK_INIT_DATA {
- UINT32 CtrlInitDataLSD; ///< Initial data of CtrlInitDataLSD
- UINT32 CtrlInitDataMSD; ///< Initial data of CtrlInitDataMSD
- UINT32 CtrlRegMSRAddr; ///< Initial data of CtrlRegMSRAddr
- UINT32 StatRegMSRAddr; ///< Initial data of StatRegMSRAddr
- UINT32 AddrRegMSRAddr; ///< Initial data of AddrRegMSRAddr
- UINT32 MiscRegMSRAddr; ///< Initial data of MiscRegMSRAddr
-} AMD_HEST_BANK_INIT_DATA;
-
-/// MSR179 Global Machine Check Capabilities data struct
-typedef struct _MSR_MCG_CAP_STRUCT {
- UINT64 Count:8; ///< Indicates the number of
- ///< error-reporting banks visible to each core
- UINT64 McgCtlP:1; ///< 1=The machine check control registers
- UINT64 Rsvd:55; ///< reserved
-} MSR_MCG_CAP_STRUCT;
-
-/// Initial data of WHEA
-typedef struct _AMD_WHEA_INIT_DATA {
- UINT32 GlobCapInitDataLSD; ///< Holds the value that the OS will program into the machine
- UINT32 GlobCapInitDataMSD; ///< Check global capability register
- UINT32 GlobCtrlInitDataLSD; ///< Holds the value that the OS will grogram into the machine
- UINT32 GlobCtrlInitDataMSD; ///< Check global control register
- UINT8 ClrStatusOnInit; ///< Indicates if the status information in this machine check
- ///< bank is to be cleared during system initialization
- UINT8 StatusDataFormat; ///< Indicates the format of the data in the status register
- UINT8 ConfWriteEn; ///< This field indicates whether configuration parameters may be
- ///< modified by the OS. If the bit for the associated parameter is
- ///< set, the parameter is writable by the OS.
- UINT8 HestBankNum; ///< Number of HEST Bank
- AMD_HEST_BANK_INIT_DATA *HestBankInitData; ///< Pointer to Initial data of HEST Bank
-} AMD_WHEA_INIT_DATA;
-
-//----------------------------------------------------------------------------
-// DMI TYPEDEFS, STRUCTURES, ENUMS
-//
-//----------------------------------------------------------------------------
-/// DMI brand information
-typedef struct {
- UINT16 String1:4; ///< String1
- UINT16 String2:4; ///< String2
- UINT16 Model:7; ///< Model
- UINT16 Pg:1; ///< Page
-} BRAND_ID;
-
-/// DMI processor information
-typedef struct {
- UINT8 ExtendedFamily; ///< Extended Family
- UINT8 ExtendedModel; ///< Extended Model
- UINT8 BaseFamily; ///< Base Family
- UINT8 BaseModel; ///< Base Model
- UINT8 Stepping; ///< Stepping
- UINT8 PackageType; ///< PackageType
- BRAND_ID BrandId; ///< BrandId which contains information about String1, String2, Model and Page
- UINT8 TotalCoreNumber; ///< Number of total cores
- UINT8 EnabledCoreNumber; ///< Number of enabled cores
- UINT8 ProcUpgrade; ///< ProcUpdrade
-} CPU_TYPE_INFO;
-
-/// DMI ECC information
-typedef struct {
- BOOLEAN EccCapable; ///< ECC Capable
- UINT8 PartitionRowPosition; ///< DMI Type 20 offset 10h: Partition Row Position
- ///< 2 - single channel memory
- ///< 0 - dual channel memory
-} CPU_GET_MEM_INFO;
-
-/* Transfer vectors for DMI family specific routines */
-typedef VOID OPTION_DMI_GET_CPU_INFO (
- IN OUT CPU_TYPE_INFO *CpuInfoPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-typedef UINT8 OPTION_DMI_GET_VOLTAGE (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-typedef UINT16 OPTION_DMI_GET_MAX_SPEED (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-typedef UINT16 OPTION_DMI_GET_EXT_CLOCK (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-typedef VOID OPTION_DMI_GET_MEM_INFO (
- IN OUT CPU_GET_MEM_INFO *CpuGetMemInfoPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Brand table entry format
-typedef struct {
- UINT8 PackageType; ///< Package type
- UINT8 PgOfBrandId; ///< Page
- UINT8 NumberOfCores; ///< Number of cores
- UINT8 String1ofBrandId; ///< String1
- UINT8 ValueSetToDmiTable; ///< The value which will should be set to DMI table
-} DMI_BRAND_ENTRY;
-
-/// Family specific data table structure
-typedef struct {
- UINT64 ProcessorFamily; ///< processor
- OPTION_DMI_GET_CPU_INFO *DmiGetCpuInfo; ///< transfer vectors
- OPTION_DMI_GET_VOLTAGE *DmiGetVoltage; ///< vector for reading voltage
- OPTION_DMI_GET_MAX_SPEED *DmiGetMaxSpeed; ///< vector for reading speed
- OPTION_DMI_GET_EXT_CLOCK *DmiGetExtClock; ///< vector for reading external clock speed
- OPTION_DMI_GET_MEM_INFO *DmiGetMemInfo; ///< Get memory information
- UINT8 LenBrandList; ///< size of brand table
- CONST DMI_BRAND_ENTRY *DmiBrandList; ///< translate brand info to DMI identifier
-} PROC_FAMILY_TABLE;
-
-//----------------------------------------------------------------------------
-// SLIT TYPEDEFS, STRUCTURES, ENUMS
-//
-//----------------------------------------------------------------------------
-/// Format for SRAT Header
-typedef struct {
- UINT8 Sign[4]; ///< Signature
- UINT32 TableLength; ///< Table Length
- UINT8 Revision; ///< Revision
- UINT8 Checksum; ///< Checksum
- UINT8 OemId[6]; ///< OEM ID
- UINT8 OemTableId[8]; ///< OEM Tabled ID
- UINT32 OemRev; ///< OEM Revision
- UINT8 CreatorId[4]; ///< Creator ID
- UINT32 CreatorRev; ///< Creator Revision
-} ACPI_TABLE_HEADER;
-
-//----------------------------------------------------------------------------
-// SRAT TYPEDEFS, STRUCTURES, ENUMS
-//
-//----------------------------------------------------------------------------
-/// Format for SRAT Header
-typedef struct _CPU_SRAT_HEADER {
- UINT8 Sign[4]; ///< Signature
- UINT32 TableLength; ///< Table Length
- UINT8 Revision; ///< Revision
- UINT8 Checksum; ///< Checksum
- UINT8 OemId[6]; ///< OEM ID
- UINT8 OemTableId[8]; ///< OEM Tabled ID
- UINT32 OemRev; ///< OEM Revision
- UINT8 CreatorId[4]; ///< Creator ID
- UINT32 CreatorRev; ///< Creator Revision
- UINT32 TableRev; ///< Table Revision
- UINT8 Reserved[8]; ///< Reserved
-} CPU_SRAT_HEADER;
-
-
-/// Format for SRAT APIC Affinity Entry
-typedef struct _CPU_SRAT_APIC_ENTRY {
- UINT8 Type; ///< Type
- UINT8 Length; ///< Length
- UINT8 Domain; ///< Domain
- UINT8 ApicId; ///< Apic ID
- UINT32 Flags; ///< Flags
- UINT8 LSApicEid; ///< Local SAPIC EID
- UINT8 Reserved[7]; ///< Reserved
-} CPU_SRAT_APIC_ENTRY;
-
-
-/// Format for SRAT Memory Affinity Entry
-typedef struct _CPU_SRAT_MEMORY_ENTRY {
- UINT8 Type; ///< 0: Memory affinity = 1
- UINT8 Length; ///< 1: Length = 40 bytes
- UINT32 Domain; ///< 2: Proximity domain
- UINT8 Reserved1[2]; ///< 6: Reserved
- UINT32 BaseAddrLow; ///< 8: Low 32bits address base
- UINT32 BaseAddrHigh; ///< 12: High 32bits address base
- UINT32 LengthAddrLow; ///< 16: Low 32bits address limit
- UINT32 LengthAddrHigh; ///< 20: High 32bits address limit
- UINT8 Reserved2[4]; ///< 24: Memory Type
- UINT32 Flags; ///< 28: Flags
- UINT8 Reserved3[8]; ///< 32: Reserved
-} CPU_SRAT_MEMORY_ENTRY;
-
-/*----------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *----------------------------------------------------------------------------------------
- */
-
-AGESA_STATUS
-AmdCpuLate (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-CreateAcpiWhea (
- IN OUT AMD_CONFIG_PARAMS *StdHeader,
- IN OUT VOID **WheaMcePtr,
- IN OUT VOID **WheaCmcPtr
- );
-
-AGESA_STATUS
-CreateDmiRecords (
- IN OUT AMD_CONFIG_PARAMS *StdHeader,
- IN OUT DMI_INFO **DmiTable
- );
-
-AGESA_STATUS
-GetType4Type7Info (
- IN AP_EXE_PARAMS *ApExeParams
- );
-
-AGESA_STATUS
-CreateAcpiSrat (
- IN OUT AMD_CONFIG_PARAMS *StdHeader,
- IN OUT VOID **SratPtr
- );
-
-AGESA_STATUS
-CreateAcpiSlit (
- IN OUT AMD_CONFIG_PARAMS *StdHeader,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN OUT VOID **SlitPtr
- );
-
-VOID
-ChecksumAcpiTable (
- IN OUT ACPI_TABLE_HEADER *Table,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-RunLateApTaskOnAllAPs (
- IN AP_EXE_PARAMS *ApParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-RunLateApTaskOnAllCore0s (
- IN AP_EXE_PARAMS *ApParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-GenerateSsdt (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN OUT VOID **SsdtPtr
- );
-
-#endif // _CPU_LATE_INIT_H_
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/cpuMicrocodePatch.c b/src/vendorcode/amd/agesa/Proc/CPU/cpuMicrocodePatch.c
deleted file mode 100644
index c19b105..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/cpuMicrocodePatch.c
+++ /dev/null
@@ -1,441 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU Microcode Patch Related Functions
- *
- * Contains code to program a microcode into the CPU
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 35924 $ @e \$Date: 2010-08-04 23:23:29 +0800 (Wed, 04 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*---------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *---------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuEarlyInit.h"
-#include "GeneralServices.h"
-#include "cpuServices.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_CPUMICROCODEPATCH_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-typedef union {
- UINT64 RawData;
- PATCH_LOADER_MSR BitFields;
-} PATCH_LOADER;
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-LoadMicrocode (
- IN MICROCODE_PATCH *MicrocodePatchPtr,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-BOOLEAN
-STATIC
-GetPatchEquivalentId (
- IN OUT UINT16 *ProcessorEquivalentId,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-BOOLEAN
-STATIC
-ValidateMicrocode (
- IN MICROCODE_PATCH *MicrocodePatchPtr,
- IN UINT16 ProcessorEquivalentId,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-STATIC
-GetMicrocodeVersion (
- OUT UINT32 *pMicrocodeVersion,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- * Update microcode patch in current processor.
- *
- * Then reads the patch id, and compare it to the expected, in the Microprocessor
- * patch block.
- *
- * @param[in] StdHeader - Config handle for library and services.
- *
- * @retval TRUE - Patch Loaded Successfully.
- * @retval FALSE - Patch Did Not Get Loaded.
- *
- */
-BOOLEAN
-LoadMicrocodePatch (
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 PatchNumber;
- UINT8 TotalPatches;
- UINT16 ProcessorEquivalentId;
- BOOLEAN Status;
- MICROCODE_PATCH **MicrocodePatchPtr;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
-
- Status = FALSE;
-
- if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) {
- // Get the patch pointer
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
- FamilySpecificServices->GetMicroCodePatchesStruct (FamilySpecificServices, (VOID **) &MicrocodePatchPtr, &TotalPatches, StdHeader);
-
- IDS_OPTION_HOOK (IDS_UCODE, &TotalPatches, StdHeader);
-
- // Get the processor microcode path equivalent ID
- if (GetPatchEquivalentId (&ProcessorEquivalentId, StdHeader)) {
- // parse the patch table to see if we have one for the current cpu
- for (PatchNumber = 0; PatchNumber < TotalPatches; PatchNumber++) {
- if (ValidateMicrocode (MicrocodePatchPtr[PatchNumber], ProcessorEquivalentId, StdHeader)) {
- if (LoadMicrocode (MicrocodePatchPtr[PatchNumber], StdHeader)) {
- Status = TRUE;
- } else {
- PutEventLog (AGESA_ERROR,
- CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED,
- 0, 0, 0, 0, StdHeader);
- }
- break; // Once we find a microcode patch that matches the processor, exit the for loop
- }
- }
- }
- }
- return Status;
-}
-
-/*---------------------------------------------------------------------------------------
- * L O C A L F U N C T I O N S
- *---------------------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * LoadMicrocode
- *
- * Update microcode patch in current processor, then reads the
- * patch id, and compare it to the expected, in the Microprocessor
- * patch block.
- *
- * @param[in] MicrocodePatchPtr - Pointer to Microcode Patch.
- * @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct.
- *
- * @retval TRUE - Patch Loaded Successfully.
- * @retval FALSE - Patch Did Not Get Loaded.
- *
- */
-BOOLEAN
-STATIC
-LoadMicrocode (
- IN MICROCODE_PATCH *MicrocodePatchPtr,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 MicrocodeVersion;
- PATCH_LOADER PatchLoaderMsr;
-
- // Load microcode patch into CPU
- PatchLoaderMsr.RawData = (UINT64) MicrocodePatchPtr;
- PatchLoaderMsr.BitFields.SBZ = 0;
- LibAmdMsrWrite (MSR_PATCH_LOADER, &PatchLoaderMsr.RawData, StdHeader);
-
- // Do ucode patch Authentication
- // Read microcode version back from CPU, determine if
- // it is the same patch level as contained in the source
- // microprocessor patch block passed in
- GetMicrocodeVersion (&MicrocodeVersion, StdHeader);
- if (MicrocodeVersion == MicrocodePatchPtr->PatchID) {
- return (TRUE);
- } else {
- return (FALSE);
- }
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * GetPatchEquivalentId
- *
- * Return the equivalent ID for microcode patching
- *
- * @param[in,out] ProcessorEquivalentId - Pointer to Processor Equivalent ID table.
- * @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct.
- *
- * @retval TRUE - ID Found.
- * @retval FALSE - ID Not Found.
- *
- */
-BOOLEAN
-STATIC
-GetPatchEquivalentId (
- IN OUT UINT16 *ProcessorEquivalentId,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 i;
- UINT8 EquivalencyEntries;
- UINT16 ProcessorRevisionId;
- UINT16 *MicrocodeEquivalenceTable;
- CPUID_DATA CpuIdData;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
-
- //
- // compute the processor revision ID
- //
- LibAmdCpuidRead (AMD_CPUID_FMF, &CpuIdData, StdHeader);
- // high byte contains extended model and extended family
- ProcessorRevisionId = (UINT16) ((CpuIdData.EAX_Reg & (CPU_EMODEL | CPU_EFAMILY)) >> 8);
- // low byte contains model and family
- ProcessorRevisionId |= (CpuIdData.EAX_Reg & (CPU_STEPPING | CPU_MODEL));
-
- //
- // find the equivalent ID for microcode purpose using the equivalence table
- //
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
-
- FamilySpecificServices->GetMicrocodeEquivalenceTable (FamilySpecificServices,
- &MicrocodeEquivalenceTable,
- &EquivalencyEntries,
- StdHeader);
-
- // parse the equivalence table
- for (i = 0; i < (EquivalencyEntries * 2); i += 2) {
- // check for equivalence
- if (ProcessorRevisionId == MicrocodeEquivalenceTable[i]) {
- *ProcessorEquivalentId = MicrocodeEquivalenceTable[i + 1];
- return (TRUE);
- }
- }
- // end of table reach, this processor is not supported
- *ProcessorEquivalentId = 0x0000;
- return (FALSE);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * ValidateMicrocode
- *
- * Determine if the microcode patch block, currently pointed to
- * is valid, and is appropriate for the current processor
-
- * @param[in] MicrocodePatchPtr - Pointer to Microcode Patch.
- * @param[in] ProcessorEquivalentId - Pointer to Processor Equivalent ID table.
- * @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct.
- *
- * @retval TRUE - Patch Found.
- * @retval FALSE - Patch Not Found.
- *
- */
-BOOLEAN
-STATIC
-ValidateMicrocode (
- IN MICROCODE_PATCH *MicrocodePatchPtr,
- IN UINT16 ProcessorEquivalentId,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- BOOLEAN Chipset1Matched;
- BOOLEAN Chipset2Matched;
- PCI_ADDR PciAddress;
- UINT32 PciDeviceVidDid;
- UINT8 PciDeviceRevision;
- UINT8 DevCount;
- UINT8 FunCount;
- UINT32 Chipset1DeviceID;
- UINT32 Chipset2DeviceID;
- UINT8 MulitFunction;
-
- Chipset1Matched = FALSE;
- Chipset2Matched = FALSE;
- PciDeviceVidDid = 0;
- PciDeviceRevision = 0;
- Chipset1DeviceID = MicrocodePatchPtr->Chipset1DeviceID;
- Chipset2DeviceID = MicrocodePatchPtr->Chipset2DeviceID;
- MulitFunction = 0;
-
- //
- // parse the supplied microcode to see if it is compatible with the processor
- //
- if (MicrocodePatchPtr->ProcessorRevisionID != ProcessorEquivalentId) {
- return (FALSE);
- }
-
- if (Chipset1DeviceID == 0) {
- Chipset1Matched = TRUE;
- }
- if (Chipset2DeviceID == 0) {
- Chipset2Matched = TRUE;
- }
-
- if ((!Chipset1Matched) || (!Chipset2Matched)) {
- //
- // Scan all PCI devices in Bus 0, try to find out matched case.
- //
- for (DevCount = 0; DevCount < 32; DevCount++) {
- for (FunCount = 0; FunCount < 8; FunCount++) {
- PciAddress.AddressValue = MAKE_SBDFO (0, 0, DevCount, FunCount, 0);
- LibAmdPciRead (AccessWidth32, PciAddress, &PciDeviceVidDid, StdHeader);
- if (PciDeviceVidDid == 0xFFFFFFFF) {
- if (FunCount == 0) {
- break;
- } else {
- continue;
- }
- }
- PciAddress.Address.Register = 0x8;
- LibAmdPciRead (AccessWidth8, PciAddress, &PciDeviceRevision, StdHeader);
- if ((!Chipset1Matched) && (PciDeviceVidDid == Chipset1DeviceID)) {
- if (PciDeviceRevision == MicrocodePatchPtr->Chipset1RevisionID) {
- Chipset1Matched = TRUE;
- }
- }
- if ((!Chipset2Matched) && (PciDeviceVidDid == Chipset2DeviceID)) {
- if (PciDeviceRevision == MicrocodePatchPtr->Chipset2RevisionID) {
- Chipset2Matched = TRUE;
- }
- }
- if (Chipset1Matched && Chipset2Matched) {
- break;
- }
- //
- // Check multi-function. If it doesen't exist, we don't have to loop functions to 7.
- //
- if (FunCount == 0) {
- MulitFunction = 0;
- PciAddress.Address.Register = 0xE;
- LibAmdPciRead (AccessWidth8, PciAddress, &MulitFunction, StdHeader);
- if ((MulitFunction & 0x80) == 0) {
- break;
- }
- }
- } // end FunCount for loop.
-
- if (Chipset1Matched && Chipset2Matched) {
- break;
- }
- } // end DevCount for loop.
- }
-
- return (Chipset1Matched && Chipset2Matched);
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * GetMicrocodeVersion
- *
- * Return the version of the currently loaded microcode patch, if any.
- * Read from the patch level MSR, return the value in eax. If no patch
- * has been loaded, 0 will be returned.
- *
- * @param[out] pMicrocodeVersion - Pointer to Microcode Version.
- * @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct.
- *
- */
-VOID
-STATIC
-GetMicrocodeVersion (
- OUT UINT32 *pMicrocodeVersion,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 MsrData;
-
- MsrData = 0;
- LibAmdMsrRead (MSR_PATCH_LEVEL, &MsrData, StdHeader);
-
- *pMicrocodeVersion = (UINT32) MsrData;
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Update microcode patch in current processor.
- *
- * This function acts as a wrapper for calling the LoadMicrocodePatch
- * routine at AmdInitEarly.
- *
- * @param[in] FamilyServices The current Family Specific Services.
- * @param[in] EarlyParams Service parameters.
- * @param[in] StdHeader Config handle for library and services.
- *
- */
-VOID
-LoadMicrocodePatchAtEarly (
- IN CPU_SPECIFIC_SERVICES *FamilyServices,
- IN AMD_CPU_EARLY_PARAMS *EarlyParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_TESTPOINT (TpProcCpuLoadUcode, StdHeader);
- LoadMicrocodePatch (StdHeader);
-}
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/cpuPage.h b/src/vendorcode/amd/agesa/Proc/CPU/cpuPage.h
deleted file mode 100644
index 5fe0f0d..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/cpuPage.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Create outline and references for CPU Component mainpage documentation.
- *
- * Design guides, maintenance guides, and general documentation, are
- * collected using this file onto the documentation mainpage.
- * This file contains doxygen comment blocks, only.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Documentation
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/**
- * @page cpumain CPU Component Documentation
- *
- * Additional documentation for the CPU component consists of
- *
- * - Maintenance Guides:
- * - @subpage cpuimplfss "CPU Family Specific Services Implementation Guide"
- * - @subpage regtableimpl "Register Table Implementation Guide"
- * - @subpage cpufeatimpl "CPU Generic Feature Implementation Guide"
- * - add here >>>
- * - Design Guides:
- * - add here >>>
- *
- */
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/cpuPostInit.c b/src/vendorcode/amd/agesa/Proc/CPU/cpuPostInit.c
deleted file mode 100644
index 0bdd006..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/cpuPostInit.c
+++ /dev/null
@@ -1,481 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU POST API, and related functions.
- *
- * Contains code that initialized the CPU after memory init.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 35756 $ @e \$Date: 2010-07-30 08:37:21 +0800 (Fri, 30 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Options.h"
-#include "cpuRegisters.h"
-#include "cpuApicUtilities.h"
-#include "heapManager.h"
-#include "cpuServices.h"
-#include "cpuFeatures.h"
-#include "GeneralServices.h"
-#include "cpuPostInit.h"
-#include "cpuPstateTables.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-#define FILECODE PROC_CPU_CPUPOSTINIT_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-VOID
-STATIC
-SyncVariableMTRR (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-extern BUILD_OPT_CFG UserOptions;
-extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable;
-
-extern
-VOID
-ExecuteWbinvdInstruction (
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-PstateCreateHeapInfo (
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Performs CPU related initialization at the POST entry point
- *
- * This function performs a large list of initialization items. These items
- * include:
- *
- * -1 AP MTRR sync
- * -2 feature leveling
- * -3 P-state data gather
- * -4 P-state leveling
- * -5 AP cache breakdown & release
- *
- * @param[in] StdHeader Config handle for library and services
- * @param[in] PlatformConfig Config handle for platform specific information
- *
- * @retval AGESA_SUCCESS
- *
- */
-AGESA_STATUS
-AmdCpuPost (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN PLATFORM_CONFIGURATION *PlatformConfig
- )
-{
- AGESA_STATUS AgesaStatus;
- AGESA_STATUS CalledStatus;
-
- AgesaStatus = AGESA_SUCCESS;
- //
- // Sync variable MTRR
- //
- AGESA_TESTPOINT (TpProcCpuApMtrrSync, StdHeader);
- SyncVariableMTRR (StdHeader);
-
- AGESA_TESTPOINT (TpProcCpuPostFeatureInit, StdHeader);
- IDS_HDT_CONSOLE (CPU_TRACE, " Dispatch CPU features after AP MTRR sync\n");
- CalledStatus = DispatchCpuFeatures (CPU_FEAT_AFTER_POST_MTRR_SYNC, PlatformConfig, StdHeader);
- if (CalledStatus > AgesaStatus) {
- AgesaStatus = CalledStatus;
- }
- //
- // Feature Leveling
- //
- AGESA_TESTPOINT (TpProcCpuFeatureLeveling, StdHeader);
- IDS_HDT_CONSOLE (CPU_TRACE, " Perform feature leveling\n");
- FeatureLeveling (StdHeader);
- //
- // P-state Gathered and set heap info
- //
- IDS_HDT_CONSOLE (CPU_TRACE, " Create P-state info in the heap\n");
- PstateCreateHeapInfo (PlatformConfig, StdHeader);
-
- // Set TscFreqSel at the rate specified by the core P0 after core frequency leveling.
- SetCoresTscFreqSel (StdHeader);
-
- // Relinquish control of all APs to IBV.
- IDS_HDT_CONSOLE (CPU_TRACE, " Relinquish control of APs\n");
- RelinquishControlOfAllAPs (StdHeader);
-
- return (AgesaStatus);
-}
-
-/*---------------------------------------------------------------------------------------
- * L O C A L F U N C T I O N S
- *---------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Determines the address in system DRAM that should be used for p-state data
- * gather and leveling.
- *
- * @param[out] Ptr Address to utilize
- * @param[in] StdHeader Config handle for library and services
- *
- * @retval AGESA_SUCCESS
- *
- */
-AGESA_STATUS
-GetPstateGatherDataAddressAtPost (
- OUT UINT64 **Ptr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 AddressValue;
-
- AddressValue = P_STATE_DATA_GATHER_TEMP_ADDR;
-
- *Ptr = (UINT64 *)(AddressValue);
-
- return AGESA_SUCCESS;
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * AP task to sync memory subsystem MSRs with the BSC
- *
- * This function processes a list of MSRs and the BSC's current values for those
- * MSRs. This will allow the APs to see system RAM.
- *
- * @param[in] MtrrTable Memory related MSR table
- * @param[in] StdHeader Config handle for library and services
- *
- */
-VOID
-SyncAllApMtrrToBsc (
- IN VOID *MtrrTable,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 i;
-
- for (i = 0; ((BSC_AP_MSR_SYNC *) MtrrTable)[i].RegisterAddress != 0; i++) {
- LibAmdMsrWrite (((BSC_AP_MSR_SYNC *) MtrrTable)[i].RegisterAddress,
- &((BSC_AP_MSR_SYNC *) MtrrTable)[i].RegisterValue,
- StdHeader);
- }
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Creates p-state information on the heap
- *
- * This function gathers p-state information from all processors in the system,
- * determines a level set of p-states, and places that information into the
- * heap. This heap data will be used by GenerateSsdt to generate the
- * final _PSS and XPSS objects.
- *
- * @param[in] PlatformConfig Pointer to runtime configuration options
- * @param[in] StdHeader Config handle for library and services
- *
- * @retval AGESA_SUCCESS No error
- * @retval AGESA_ERROR CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE
- */
-AGESA_STATUS
-PstateCreateHeapInfo (
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_STATUS AgesaStatus;
- S_CPU_AMD_PSTATE *PStateBufferPtr;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
- UINT8 *PStateBufferPtrInHeap;
-
- ASSERT (IsBsp (StdHeader, &AgesaStatus));
-
- //
- //Get proper address for gather data pool address
- //Zero P-state gather data pool
- //
- GetPstateGatherDataAddressAtPost ((UINT64 **)&PStateBufferPtr, StdHeader);
- LibAmdMemFill (PStateBufferPtr, 0, sizeof (S_CPU_AMD_PSTATE), StdHeader);
-
- //
- //Get all the CPUs P-States and fill the PStateBufferPtr for each core
- //
- AgesaStatus = PStateGatherData (PlatformConfig, PStateBufferPtr, StdHeader);
- if (AgesaStatus != AGESA_SUCCESS) {
- return AgesaStatus;
- }
-
- //
- //Do Pstate Leveling for each core if needed.
- //
- AgesaStatus = PStateLeveling (PStateBufferPtr, StdHeader);
-
- //
- //Create Heap and store p-state data for ACPI table in CpuLate
- //
- AllocHeapParams.RequestedBufferSize = PStateBufferPtr->SizeOfBytes;
- AllocHeapParams.BufferHandle = AMD_PSTATE_DATA_BUFFER_HANDLE;
- AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
- AgesaStatus = HeapAllocateBuffer (&AllocHeapParams, StdHeader);
- if (AgesaStatus == AGESA_SUCCESS) {
- //
- // Zero Buffer
- //
- PStateBufferPtrInHeap = (UINT8 *) AllocHeapParams.BufferPtr;
- LibAmdMemFill (PStateBufferPtrInHeap, 0, PStateBufferPtr->SizeOfBytes, StdHeader);
- LibAmdMemCopy (PStateBufferPtrInHeap, PStateBufferPtr, PStateBufferPtr->SizeOfBytes, StdHeader);
-
- } else {
- PutEventLog (AGESA_ERROR,
- CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE,
- 0, 0, 0, 0, StdHeader);
- }
-
- return AgesaStatus;
-}
-
-VOID
-SyncApMsrsToBsc (
- IN OUT BSC_AP_MSR_SYNC *ApMsrSync,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AP_TASK TaskPtr;
- UINT16 i;
- UINT32 BscSocket;
- UINT32 Ignored;
- UINT32 BscCore;
- UINT32 Core;
- UINT32 Socket;
- UINT32 NumberOfSockets;
- UINT32 NumberOfCores;
- AGESA_STATUS IgnoredSts;
-
- ASSERT (IsBsp (StdHeader, &IgnoredSts));
-
- IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredSts);
- NumberOfSockets = GetPlatformNumberOfSockets ();
-
- //
- //Sync all MTRR settings with BSP
- //
- for (i = 0; ApMsrSync[i].RegisterAddress != 0; i++) {
- LibAmdMsrRead (ApMsrSync[i].RegisterAddress, &ApMsrSync[i].RegisterValue, StdHeader);
- }
-
- TaskPtr.FuncAddress.PfApTaskI = SyncAllApMtrrToBsc;
- TaskPtr.DataTransfer.DataSizeInDwords = (UINT16) ((((sizeof (BSC_AP_MSR_SYNC)) * i) + 4) >> 2);
- TaskPtr.ExeFlags = WAIT_FOR_CORE;
- TaskPtr.DataTransfer.DataPtr = ApMsrSync;
- TaskPtr.DataTransfer.DataTransferFlags = 0;
-
- for (Socket = 0; Socket < NumberOfSockets; Socket++) {
- if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
- for (Core = 0; Core < NumberOfCores; Core++) {
- if ((Socket != BscSocket) || (Core != BscCore)) {
- ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);
- }
- }
- }
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * SyncVariableMTRR
- *
- * Sync variable MTRR
- *
- * @param[in] StdHeader Config handle for library and services
- *
- */
-VOID
-STATIC
-SyncVariableMTRR (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- BSC_AP_MSR_SYNC ApMsrSync[20];
-
- ApMsrSync[0].RegisterAddress = SYS_CFG;
- ApMsrSync[1].RegisterAddress = TOP_MEM;
- ApMsrSync[2].RegisterAddress = TOP_MEM2;
- ApMsrSync[3].RegisterAddress = 0x200;
- ApMsrSync[4].RegisterAddress = 0x201;
- ApMsrSync[5].RegisterAddress = 0x202;
- ApMsrSync[6].RegisterAddress = 0x203;
- ApMsrSync[7].RegisterAddress = 0x204;
- ApMsrSync[8].RegisterAddress = 0x205;
- ApMsrSync[9].RegisterAddress = 0x206;
- ApMsrSync[10].RegisterAddress = 0x207;
- ApMsrSync[11].RegisterAddress = 0x208;
- ApMsrSync[12].RegisterAddress = 0x209;
- ApMsrSync[13].RegisterAddress = 0x20A;
- ApMsrSync[14].RegisterAddress = 0x20B;
- ApMsrSync[15].RegisterAddress = 0xC0010016;
- ApMsrSync[16].RegisterAddress = 0xC0010017;
- ApMsrSync[17].RegisterAddress = 0xC0010018;
- ApMsrSync[18].RegisterAddress = 0xC0010019;
- ApMsrSync[19].RegisterAddress = 0;
- SyncApMsrsToBsc (ApMsrSync, StdHeader);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * The function suppose to do any thing need to be done at the end of AmdInitPost.
- *
- * @param[in] StdHeader Config handle for library and services
- *
- * @retval AGESA_SUCCESS
- *
- */
-AGESA_STATUS
-FinalizeAtPost (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- //
- // Execute wbinvd to ensure heap data in cache write back to memory.
- //
- ExecuteWbinvdInstruction (StdHeader);
-
- return AGESA_SUCCESS;
-}
-/*---------------------------------------------------------------------------------------*/
-/**
- * Set TSC Frequency Selection.
- *
- * This function set TSC Frequency Selection.
- *
- * @param[in] StdHeader Config handle for library and services
- *
- */
-VOID
-STATIC
-SetTscFreqSel (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- PSTATE_CPU_FAMILY_SERVICES *FamilyServices;
-
- FamilyServices = NULL;
-
- GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, &FamilyServices, StdHeader);
- if (FamilyServices != NULL) {
- FamilyServices->CpuSetTscFreqSel (FamilyServices, StdHeader);
- }
-
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Set TSC Frequency Selection to all cores.
- *
- * This function set TscFreqSel to all cores in the system.
- *
- * @param[in] StdHeader Config handle for library and services
- *
- */
-VOID
-SetCoresTscFreqSel (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AP_TASK TaskPtr;
- UINT32 BscSocket;
- UINT32 Ignored;
- UINT32 BscCore;
- UINT32 Core;
- UINT32 Socket;
- UINT32 NumberOfSockets;
- UINT32 NumberOfCores;
- AGESA_STATUS IgnoredSts;
-
- ASSERT (IsBsp (StdHeader, &IgnoredSts));
-
- IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCore, &IgnoredSts);
- NumberOfSockets = GetPlatformNumberOfSockets ();
-
- SetTscFreqSel (StdHeader);
-
- TaskPtr.FuncAddress.PfApTask = SetTscFreqSel;
- TaskPtr.ExeFlags = WAIT_FOR_CORE;
- TaskPtr.DataTransfer.DataTransferFlags = 0;
- TaskPtr.DataTransfer.DataSizeInDwords = 0;
- TaskPtr.DataTransfer.DataPtr = NULL;
-
- for (Socket = 0; Socket < NumberOfSockets; Socket++) {
- if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) {
- for (Core = 0; Core < NumberOfCores; Core++) {
- if ((Socket != BscSocket) || (Core != BscCore)) {
- ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, &TaskPtr, StdHeader);
- }
- }
- }
- }
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/cpuPostInit.h b/src/vendorcode/amd/agesa/Proc/CPU/cpuPostInit.h
deleted file mode 100644
index 6d2870a..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/cpuPostInit.h
+++ /dev/null
@@ -1,228 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU Reset API, and related functions and structures.
- *
- * Contains code that initialized the CPU after early reset.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 36462 $ @e \$Date: 2010-08-20 00:49:49 +0800 (Fri, 20 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPU_POST_INIT_H_
-#define _CPU_POST_INIT_H_
-
-
-/*---------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *---------------------------------------------------------------------------------------
- */
-// Forward declaration needed for multi-structure mutual references
-AGESA_FORWARD_DECLARATION (CPU_CFOH_FAMILY_SERVICES);
-
-/*---------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *---------------------------------------------------------------------------------------
- */
-#define P_STATE_DATA_GATHER_TEMP_ADDR 0x200000 ///< Fixed the row data at 2M memory address.
-#define GLOBAL_CPU_FEATURE_LIST_TEMP_ADDR 0x200000 ///< Fixed the row data at 2M memory address.
-/*---------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *---------------------------------------------------------------------------------------
- */
-//----------------------------------------------------------------------------
-// CPU FEATURE LEVELING TYPEDEFS, STRUCTURES, ENUMS
-//
-//----------------------------------------------------------------------------
-/// CPU FEATURE LIST
-typedef struct {
- UINT8 ABM:1; ///< byte 0 bit 0
- UINT8 AES:1; ///< byte 0 bit 1
- UINT8 AltMovCr8:1; ///< byte 0 bit 2
- UINT8 APIC:1; ///< byte 0 bit 3
- UINT8 AVX:1; ///< byte 0 bit 4
- UINT8 CLFSH:1; ///< byte 0 bit 5
- UINT8 CMOV:1; ///< byte 0 bit 6
- UINT8 CmpLegacy:1; ///< byte 0 bit 7
- UINT8 CMPXCHG8B:1; ///< byte 1 bit 0
- UINT8 CMPXCHG16B:1; ///< byte 1 bit 1
- UINT8 CVT16:1; ///< byte 1 bit 2
- UINT8 DE:1; ///< byte 1 bit 3
- UINT8 ExtApicSpace:1; ///< byte 1 bit 4
- UINT8 FFXSR:1; ///< byte 1 bit 5
- UINT8 FMA:1; ///< byte 1 bit 6
- UINT8 FMA4:1; ///< byte 1 bit 7
- UINT8 FPU:1; ///< byte 2 bit 0
- UINT8 FXSR:1; ///< byte 2 bit 1
- UINT8 HTT:1; ///< byte 2 bit 2
- UINT8 IBS:1; ///< byte 2 bit 3
- UINT8 LahfSahf:1; ///< byte 2 bit 4
- UINT8 LM:1; ///< byte 2 bit 5
- UINT8 LWP:1; ///< byte 2 bit 6
- UINT8 MCA:1; ///< byte 2 bit 7
- UINT8 MCE:1; ///< byte 3 bit 0
- UINT8 MisAlignSse:1; ///< byte 3 bit 1
- UINT8 MMX:1; ///< byte 3 bit 2
- UINT8 MmxExt:1; ///< byte 3 bit 3
- UINT8 Monitor:1; ///< byte 3 bit 4
- UINT8 MSR:1; ///< byte 3 bit 5
- UINT8 MTRR:1; ///< byte 3 bit 6
- UINT8 NodeId:1; ///< byte 3 bit 7
- UINT8 NX:1; ///< byte 4 bit 0
- UINT8 OSVW:1; ///< byte 4 bit 1
- UINT8 OSXSAVE:1; ///< byte 4 bit 2
- UINT8 PAE:1; ///< byte 4 bit 3
- UINT8 Page1GB:1; ///< byte 4 bit 4
- UINT8 PAT:1; ///< byte 4 bit 5
- UINT8 PCLMULQDQ:1; ///< byte 4 bit 6
- UINT8 PGE:1; ///< byte 4 bit 7
- UINT8 POPCNT:1; ///< byte 5 bit 0
- UINT8 PSE:1; ///< byte 5 bit 1
- UINT8 PSE36:1; ///< byte 5 bit 2
- UINT8 RDTSCP:1; ///< byte 5 bit 3
- UINT8 SKINIT:1; ///< byte 5 bit 4
- UINT8 SSE:1; ///< byte 5 bit 5
- UINT8 SSE2:1; ///< byte 5 bit 6
- UINT8 SSE3:1; ///< byte 5 bit 7
- UINT8 SSE4A:1; ///< byte 6 bit 0
- UINT8 SSE41:1; ///< byte 6 bit 1
- UINT8 SSE42:1; ///< byte 6 bit 2
- UINT8 SSE5:1; ///< byte 6 bit 3
- UINT8 SSSE3:1; ///< byte 6 bit 4
- UINT8 SVM:1; ///< byte 6 bit 5
- UINT8 SysCallSysRet:1; ///< byte 6 bit 6
- UINT8 SysEnterSysExit:1; ///< byte 6 bit 7
- UINT8 TBM0:1; ///< byte 7 bit 0
- UINT8 TCE:1; ///< byte 7 bit 1
- UINT8 ThreeDNow:1; ///< byte 7 bit 2
- UINT8 ThreeDNowExt:1; ///< byte 7 bit 3
- UINT8 ThreeDNowPrefetch:1; ///< byte 7 bit 4
- UINT8 TimeStampCounter:1; ///< byte 7 bit 5
- UINT8 VME:1; ///< byte 7 bit 6
- UINT8 WDT:1; ///< byte 7 bit 7
- UINT8 X2APIC:1; ///< byte 8 bit 0
- UINT8 XOP:1; ///< byte 8 bit 1
- UINT8 XSAVE:1; ///< byte 8 bit 2
- UINT8 Reserve:5; ///< Reserved
-} CPU_FEATURES_LIST;
-
-//----------------------------------------------------------------------------
-// POST INIT TYPEDEFS, STRUCTURES, ENUMS
-//
-//----------------------------------------------------------------------------
-/// BSC to AP MSR sync up
-typedef struct {
- UINT32 RegisterAddress; ///< MSR Address
- UINT64 RegisterValue; ///< BSC's MSR Value
-} BSC_AP_MSR_SYNC;
-
-/**
- * Set Cache Flush On Halt Register.
- *
- * @CpuServiceInstances
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] EntryPoint Timepoint designator.
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- */
-typedef VOID (F_CPU_SET_CFOH_REG) (
- IN CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices,
- IN UINT64 EntryPoint,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
- /// Reference to a Method.
-typedef F_CPU_SET_CFOH_REG *PF_CPU_SET_CFOH_REG;
-
-/**
- * Provide the interface to the Cache Flush On Halt Family Specific Services.
- *
- * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
- * Each supported Family must provide an implementation for all methods in this interface, even if the
- * implementation is a CommonReturn().
- */
-struct _CPU_CFOH_FAMILY_SERVICES { // See forward reference above
- UINT16 Revision; ///< Interface version
- // Public Methods.
- PF_CPU_SET_CFOH_REG SetCacheFlushOnHaltRegister; ///< Method: Set Cache Flush On Halt register.
-};
-
-/*---------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *---------------------------------------------------------------------------------------
- */
-
-// These are P U B L I C functions, used by IBVs
-AGESA_STATUS
-AmdCpuPost (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN PLATFORM_CONFIGURATION *PlatformConfig
- );
-
-// These are P U B L I C functions, used by AGESA
-
-VOID
-FeatureLeveling (
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-CopyHeapToTempRamAtPost (
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-SyncApMsrsToBsc (
- IN OUT BSC_AP_MSR_SYNC *ApMsrSync,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-FinalizeAtPost (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-SetCoresTscFreqSel (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-#endif // _CPU_POST_INIT_H_
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/cpuPowerMgmt.c b/src/vendorcode/amd/agesa/Proc/CPU/cpuPowerMgmt.c
deleted file mode 100644
index c5be715..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/cpuPowerMgmt.c
+++ /dev/null
@@ -1,253 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU Power Management functions.
- *
- * Contains code for doing early power management
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 36369 $ @e \$Date: 2010-08-17 22:54:34 +0800 (Tue, 17 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "cpuRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "OptionMultiSocket.h"
-#include "cpuApicUtilities.h"
-#include "cpuEarlyInit.h"
-#include "cpuPowerMgmtSystemTables.h"
-#include "cpuServices.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_CPUPOWERMGMT_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-VOID
-STATIC
-PerformThisPmStep (
- IN VOID *Step,
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr
- );
-
-VOID
-STATIC
-GoToMemInitPstateCore0 (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr
- );
-
-VOID
-STATIC
-GoToMemInitPstateCore (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr
- );
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Perform the "BIOS Requirements for P-State Initialization and Transitions."
- *
- * This is the generic arbiter code to be executed by the BSC. The system power
- * management init tables will be traversed. This must be run by the system BSC
- * only.
- *
- * @param[in] CpuEarlyParams Required input parameters for early CPU initialization
- * @param[in] StdHeader Config handle for library and services
- *
- * @return Most severe AGESA_STATUS level that any system processor encountered
- *
- */
-AGESA_STATUS
-PmInitializationAtEarly (
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 i;
- UINT8 NumberOfSystemWideSteps;
- AP_TASK TaskPtr;
- AGESA_STATUS ReturnCode;
- WARM_RESET_REQUEST Request;
-
- // Determine the number of steps to perform
- OptionMultiSocketConfiguration.GetNumberOfSystemPmSteps (&NumberOfSystemWideSteps, StdHeader);
-
- // Traverse the PM init table
- TaskPtr.FuncAddress.PfApTaskIC = PerformThisPmStep;
- TaskPtr.DataTransfer.DataSizeInDwords = 1;
- TaskPtr.DataTransfer.DataPtr = &i;
- TaskPtr.DataTransfer.DataTransferFlags = 0;
- TaskPtr.ExeFlags = PASS_EARLY_PARAMS;
- for (i = 0; i < NumberOfSystemWideSteps; ++i) {
- IDS_HDT_CONSOLE (CPU_TRACE, " Perform PM init step %d\n", i);
- OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, CpuEarlyParams);
- }
-
- // GoToMemInitPstateCore0 only if there is no pending warm reset.
- GetWarmResetFlag (StdHeader, &Request);
- if (Request.RequestBit == FALSE) {
- TaskPtr.FuncAddress.PfApTaskC = GoToMemInitPstateCore0;
- TaskPtr.DataTransfer.DataSizeInDwords = 0;
- TaskPtr.ExeFlags = PASS_EARLY_PARAMS;
- IDS_HDT_CONSOLE (CPU_TRACE, " Transition all cores to POST P-state\n");
- OptionMultiSocketConfiguration.BscRunCodeOnAllSystemCore0s (&TaskPtr, StdHeader, CpuEarlyParams);
- }
-
- // Retrieve/Process any errors
- ReturnCode = OptionMultiSocketConfiguration.BscRetrievePmEarlyInitErrors (StdHeader);
-
- return (ReturnCode);
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Performs the next step in the executing core 0's family specific power
- * management table.
- *
- * This function determines if the input step is valid, and invokes the power
- * management step if appropriate. This must be run by processor core 0s only.
- *
- * @param[in] Step Zero based step number
- * @param[in] StdHeader Config handle for library and services
- * @param[in] CpuEarlyParamsPtr Required input parameters for early CPU initialization
- *
- */
-VOID
-STATIC
-PerformThisPmStep (
- IN VOID *Step,
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr
- )
-{
- UINT8 MyNumberOfSteps;
- SYS_PM_TBL_STEP *FamilyTablePtr;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
-
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
- FamilySpecificServices->GetSysPmTableStruct (FamilySpecificServices, &FamilyTablePtr, &MyNumberOfSteps, StdHeader);
-
- if (*(UINT8 *)Step < MyNumberOfSteps) {
- if (FamilyTablePtr[*(UINT8 *)Step].FuncPtr != NULL) {
- if (!(BOOLEAN) (FamilyTablePtr[*(UINT8 *)Step].ExeFlags & PM_EXEFLAGS_WARM_ONLY) ||
- IsWarmReset (StdHeader)) {
- FamilyTablePtr[*(UINT8 *)Step].FuncPtr (FamilySpecificServices, CpuEarlyParamsPtr, StdHeader);
- }
- }
- }
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Transitions the executing processor to the desired P-state.
- *
- * This function implements the AMD_CPU_EARLY_PARAMS.MemInitPState parameter, and is
- * run by all processor core 0s.
- *
- * @param[in] StdHeader Config handle for library and services
- * @param[in] CpuEarlyParamsPtr Required input parameters for early CPU initialization
- *
- */
-VOID
-STATIC
-GoToMemInitPstateCore0 (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr
- )
-{
- AP_TASK TaskPtr;
-
- TaskPtr.FuncAddress.PfApTaskC = GoToMemInitPstateCore;
- TaskPtr.DataTransfer.DataSizeInDwords = 0;
- TaskPtr.ExeFlags = WAIT_FOR_CORE | PASS_EARLY_PARAMS;
- ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Transitions the executing core to the desired P-state.
- *
- * This function implements the AMD_CPU_EARLY_PARAMS.MemInitPState parameter, and is
- * run by all system cores.
- *
- * @param[in] StdHeader Config handle for library and services
- * @param[in] CpuEarlyParamsPtr Required input parameters for early CPU initialization
- *
- */
-VOID
-STATIC
-GoToMemInitPstateCore (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr
- )
-{
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
-
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
- FamilySpecificServices->TransitionPstate (FamilySpecificServices, CpuEarlyParamsPtr->MemInitPState, (BOOLEAN) FALSE, StdHeader);
-}
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/cpuPowerMgmtMultiSocket.c b/src/vendorcode/amd/agesa/Proc/CPU/cpuPowerMgmtMultiSocket.c
deleted file mode 100644
index 07cfd9d..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/cpuPowerMgmtMultiSocket.c
+++ /dev/null
@@ -1,432 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU Power Management Multisocket Functions.
- *
- * Contains code for doing power management for multisocket CPUs
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "GeneralServices.h"
-#include "cpuServices.h"
-#include "cpuApicUtilities.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuPowerMgmtSystemTables.h"
-#include "cpuPowerMgmtMultiSocket.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_CPUPOWERMGMTMULTISOCKET_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-VOID
-STATIC
-GetNextEvent (
- IN OUT VOID *EventLogEntryPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Multisocket BSC call to start all system core 0s to perform a standard AP_TASK.
- *
- * This function loops through all possible socket locations, starting core 0 of
- * each populated socket to perform the passed in AP_TASK. After starting all
- * other core 0s, the BSC will perform the AP_TASK as well. This must be run by
- * the system BSC only.
- *
- * @param[in] TaskPtr Function descriptor
- * @param[in] StdHeader Config handle for library and services
- * @param[in] ConfigParams AMD entry point's CPU parameter structure
- *
- */
-VOID
-RunCodeOnAllSystemCore0sMulti (
- IN AP_TASK *TaskPtr,
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN VOID *ConfigParams
- )
-{
- UINT32 BscSocket;
- UINT32 BscModule;
- UINT32 BscCore;
- UINT8 Socket;
- UINT32 NumberOfSockets;
- AGESA_STATUS DummyStatus;
-
- ASSERT (IsBsp (StdHeader, &DummyStatus));
-
- NumberOfSockets = GetPlatformNumberOfSockets ();
-
- IdentifyCore (StdHeader, &BscSocket, &BscModule, &BscCore, &DummyStatus);
-
- for (Socket = 0; Socket < NumberOfSockets; Socket++) {
- if (Socket != BscSocket) {
- if (IsProcessorPresent (Socket, StdHeader)) {
- ApUtilRunCodeOnSocketCore (Socket, 0, TaskPtr, StdHeader);
- }
- }
- }
- ApUtilTaskOnExecutingCore (TaskPtr, StdHeader, ConfigParams);
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Multisocket BSC call to determine the maximum number of steps that any single
- * processor needs to execute.
- *
- * This function loops through all possible socket locations, gathering the number
- * of power management steps each populated socket requires, and returns the
- * highest number.
- *
- * @param[out] NumSystemSteps Maximum number of system steps required
- * @param[in] StdHeader Config handle for library and services
- *
- */
-VOID
-GetNumberOfSystemPmStepsPtrMulti (
- OUT UINT8 *NumSystemSteps,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 NumberOfSteps;
- UINT32 NumberOfSockets;
- UINT32 Socket;
- SYS_PM_TBL_STEP *Ignored;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
-
- NumberOfSockets = GetPlatformNumberOfSockets ();
- *NumSystemSteps = 0;
-
- for (Socket = 0; Socket < NumberOfSockets; Socket++) {
- if (IsProcessorPresent (Socket, StdHeader)) {
- GetCpuServicesOfSocket (Socket, &FamilySpecificServices, StdHeader);
- FamilySpecificServices->GetSysPmTableStruct (FamilySpecificServices, &Ignored, &NumberOfSteps, StdHeader);
- if (NumberOfSteps > *NumSystemSteps) {
- *NumSystemSteps = NumberOfSteps;
- }
- }
- }
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Multisocket call to determine the frequency that the northbridges must run.
- *
- * This function loops through all possible socket locations, comparing the
- * maximum NB frequencies to determine the slowest. This function also
- * determines if all coherent NB frequencies are equivalent.
- *
- * @param[in] NbPstate NB P-state number to check (0 = fastest)
- * @param[in] PlatformConfig Platform profile/build option config structure.
- * @param[out] SystemNbCofNumerator NB frequency numerator for the system in MHz
- * @param[out] SystemNbCofDenominator NB frequency denominator for the system
- * @param[out] SystemNbCofsMatch Whether or not all NB frequencies are equivalent
- * @param[out] NbPstateIsEnabledOnAllCPUs Whether or not NbPstate is valid on all CPUs
- * @param[in] StdHeader Config handle for library and services
- *
- * @retval TRUE At least one processor has NbPstate enabled.
- * @retval FALSE NbPstate is disabled on all CPUs
- *
- */
-BOOLEAN
-GetSystemNbCofMulti (
- IN UINT32 NbPstate,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- OUT UINT32 *SystemNbCofNumerator,
- OUT UINT32 *SystemNbCofDenominator,
- OUT BOOLEAN *SystemNbCofsMatch,
- OUT BOOLEAN *NbPstateIsEnabledOnAllCPUs,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Socket;
- UINT8 Module;
- UINT32 CurrentNbCof;
- UINT32 CurrentDivisor;
- UINT32 CurrentFreq;
- UINT32 LowFrequency;
- UINT32 Ignored32;
- BOOLEAN FirstCofNotFound;
- BOOLEAN NbPstateDisabled;
- BOOLEAN IsNbPstateEnabledOnAny;
- PCI_ADDR PciAddress;
- AGESA_STATUS Ignored;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
-
- // Find the slowest NB COF in the system & whether or not all are equivalent
- LowFrequency = 0xFFFFFFFF;
- *SystemNbCofsMatch = TRUE;
- *NbPstateIsEnabledOnAllCPUs = FALSE;
- IsNbPstateEnabledOnAny = FALSE;
- FirstCofNotFound = TRUE;
- NbPstateDisabled = FALSE;
- for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) {
- if (IsProcessorPresent (Socket, StdHeader)) {
- GetCpuServicesOfSocket (Socket, &FamilySpecificServices, StdHeader);
- for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
- if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &Ignored)) {
- break;
- }
- }
- if (FamilySpecificServices->GetNbPstateInfo (FamilySpecificServices,
- PlatformConfig,
- &PciAddress,
- NbPstate,
- &CurrentNbCof,
- &CurrentDivisor,
- &Ignored32,
- StdHeader)) {
- ASSERT (CurrentDivisor != 0);
- CurrentFreq = (CurrentNbCof / CurrentDivisor);
- if (FirstCofNotFound) {
- *SystemNbCofNumerator = CurrentNbCof;
- *SystemNbCofDenominator = CurrentDivisor;
- LowFrequency = CurrentFreq;
- IsNbPstateEnabledOnAny = TRUE;
- if (!NbPstateDisabled) {
- *NbPstateIsEnabledOnAllCPUs = TRUE;
- }
- FirstCofNotFound = FALSE;
- } else {
- if (CurrentFreq != LowFrequency) {
- *SystemNbCofsMatch = FALSE;
- if (CurrentFreq < LowFrequency) {
- LowFrequency = CurrentFreq;
- *SystemNbCofNumerator = CurrentNbCof;
- *SystemNbCofDenominator = CurrentDivisor;
- }
- }
- }
- } else {
- NbPstateDisabled = TRUE;
- *NbPstateIsEnabledOnAllCPUs = FALSE;
- }
- }
- }
- return IsNbPstateEnabledOnAny;
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Multisocket call to determine if the BIOS is responsible for updating the
- * northbridge operating frequency and voltage.
- *
- * This function loops through all possible socket locations, checking whether
- * any populated sockets require NB COF VID programming.
- *
- * @param[in] StdHeader Config handle for library and services
- *
- * @retval TRUE BIOS needs to set up NB frequency and voltage
- * @retval FALSE BIOS does not need to set up NB frequency and voltage
- *
- */
-BOOLEAN
-GetSystemNbCofVidUpdateMulti (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 Module;
- UINT32 Socket;
- UINT32 NumberOfSockets;
- BOOLEAN IgnoredBool;
- BOOLEAN AtLeast1RequiresUpdate;
- PCI_ADDR PciAddress;
- AGESA_STATUS Ignored;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
-
- NumberOfSockets = GetPlatformNumberOfSockets ();
-
- AtLeast1RequiresUpdate = FALSE;
- for (Socket = 0; Socket < NumberOfSockets; Socket++) {
- if (IsProcessorPresent (Socket, StdHeader)) {
- GetCpuServicesOfSocket (Socket, &FamilySpecificServices, StdHeader);
- for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
- if (GetPciAddress (StdHeader, (UINT8) Socket, Module, &PciAddress, &Ignored)) {
- break;
- }
- }
- if (FamilySpecificServices->IsNbCofInitNeeded (FamilySpecificServices, &PciAddress, &IgnoredBool, StdHeader)) {
- AtLeast1RequiresUpdate = TRUE;
- break;
- }
- }
- }
- return AtLeast1RequiresUpdate;
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Multisocket call to determine the most severe AGESA_STATUS return value after
- * processing the power management initialization tables.
- *
- * This function loops through all possible socket locations, collecting any
- * power management initialization errors that may have occurred. These errors
- * are transferred from the core 0s of the socket in which the errors occurred
- * to the BSC's heap. The BSC's heap is then searched for the most severe error
- * that occurred, and returns it. This function must be called by the BSC only.
- *
- * @param[in] StdHeader Config handle for library and services
- *
- * @return The most severe error code from power management init
- *
- */
-AGESA_STATUS
-GetEarlyPmErrorsMulti (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT16 i;
- UINT32 BscSocket;
- UINT32 BscModule;
- UINT32 BscCore;
- UINT32 Socket;
- UINT32 NumberOfSockets;
- AP_TASK TaskPtr;
- AGESA_EVENT EventLogEntry;
- AGESA_STATUS ReturnCode;
- AGESA_STATUS DummyStatus;
-
- ASSERT (IsBsp (StdHeader, &ReturnCode));
-
- ReturnCode = AGESA_SUCCESS;
- EventLogEntry.EventClass = AGESA_SUCCESS;
- EventLogEntry.EventInfo = 0;
- EventLogEntry.DataParam1 = 0;
- EventLogEntry.DataParam2 = 0;
- EventLogEntry.DataParam3 = 0;
- EventLogEntry.DataParam4 = 0;
-
- NumberOfSockets = GetPlatformNumberOfSockets ();
- IdentifyCore (StdHeader, &BscSocket, &BscModule, &BscCore, &DummyStatus);
-
- TaskPtr.FuncAddress.PfApTaskI = GetNextEvent;
- TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (AGESA_EVENT);
- TaskPtr.DataTransfer.DataPtr = &EventLogEntry;
- TaskPtr.DataTransfer.DataTransferFlags = 0;
- TaskPtr.ExeFlags = WAIT_FOR_CORE | RETURN_PARAMS;
- for (Socket = 0; Socket < NumberOfSockets; Socket++) {
- if (Socket != BscSocket) {
- if (IsProcessorPresent (Socket, StdHeader)) {
- do {
- ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8) 0, &TaskPtr, StdHeader);
- if ((EventLogEntry.EventInfo & CPU_EVENT_PM_EVENT_MASK) == CPU_EVENT_PM_EVENT_CLASS) {
- PutEventLog (
- EventLogEntry.EventClass,
- EventLogEntry.EventInfo,
- EventLogEntry.DataParam1,
- EventLogEntry.DataParam2,
- EventLogEntry.DataParam3,
- EventLogEntry.DataParam4,
- StdHeader
- );
- }
- } while (EventLogEntry.EventInfo != 0);
- }
- }
- }
-
- for (i = 0; PeekEventLog (&EventLogEntry, i, StdHeader); i++) {
- if ((EventLogEntry.EventInfo & CPU_EVENT_PM_EVENT_MASK) == CPU_EVENT_PM_EVENT_CLASS) {
- if (EventLogEntry.EventClass > ReturnCode) {
- ReturnCode = EventLogEntry.EventClass;
- }
- }
- }
- return (ReturnCode);
-}
-
-/*---------------------------------------------------------------------------------------
- * L O C A L F U N C T I O N S
- *---------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * AP task to return the next event log entry to the BSC.
- *
- * This function calls to the event log manager to retrieve the next error out
- * of the heap.
- *
- * @param[out] EventLogEntryPtr The AP's next event log entry
- * @param[in] StdHeader Config handle for library and services
- *
- */
-VOID
-STATIC
-GetNextEvent (
- IN OUT VOID *EventLogEntryPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- GetEventLog ((AGESA_EVENT *) EventLogEntryPtr, StdHeader);
-}
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/cpuPowerMgmtMultiSocket.h b/src/vendorcode/amd/agesa/Proc/CPU/cpuPowerMgmtMultiSocket.h
deleted file mode 100644
index b88d4d1..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/cpuPowerMgmtMultiSocket.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU Power Management Multisocket Functions.
- *
- * Contains code for doing power management for multisocket CPUs
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPU_POWER_MGMT_MULTI_SOCKET_H_
-#define _CPU_POWER_MGMT_MULTI_SOCKET_H_
-
-
-/*---------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *---------------------------------------------------------------------------------------
- */
-VOID
-RunCodeOnAllSystemCore0sMulti (
- IN AP_TASK *TaskPtr,
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN VOID *ConfigParams
- );
-
-VOID
-GetNumberOfSystemPmStepsPtrMulti (
- OUT UINT8 *NumSystemSteps,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-BOOLEAN
-GetSystemNbCofMulti (
- IN UINT32 NbPstate,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- OUT UINT32 *SystemNbCofNumerator,
- OUT UINT32 *SystemNbCofDenominator,
- OUT BOOLEAN *SystemNbCofsMatch,
- OUT BOOLEAN *NbPstateIsEnabledOnAllCPUs,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-BOOLEAN
-GetSystemNbCofVidUpdateMulti (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif // _CPU_POWER_MGMT_MULTI_SOCKET_H_
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/cpuPowerMgmtSingleSocket.c b/src/vendorcode/amd/agesa/Proc/CPU/cpuPowerMgmtSingleSocket.c
deleted file mode 100644
index 4e9a47f..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/cpuPowerMgmtSingleSocket.c
+++ /dev/null
@@ -1,246 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU Power Management Single Socket Functions.
- *
- * Contains code for doing power management for single socket CPU
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "GeneralServices.h"
-#include "cpuRegisters.h"
-#include "cpuApicUtilities.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuPowerMgmtSystemTables.h"
-#include "cpuPowerMgmtSingleSocket.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_CPUPOWERMGMTSINGLESOCKET_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Single socket BSC call to start all system core 0s to perform a standard AP_TASK.
- *
- * This function will simply invoke the task on the executing core. This must be
- * run by the system BSC only.
- *
- * @param[in] TaskPtr Function descriptor
- * @param[in] StdHeader Config handle for library and services
- * @param[in] ConfigParams AMD entry point's CPU parameter structure
- *
- */
-VOID
-RunCodeOnAllSystemCore0sSingle (
- IN AP_TASK *TaskPtr,
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN VOID *ConfigParams
- )
-{
- ApUtilTaskOnExecutingCore (TaskPtr, StdHeader, ConfigParams);
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Single socket BSC call to determine the maximum number of steps that any single
- * processor needs to execute.
- *
- * This function simply returns the number of steps that the BSC needs.
- *
- * @param[out] NumSystemSteps Maximum number of system steps required
- * @param[in] StdHeader Config handle for library and services
- *
- */
-VOID
-GetNumberOfSystemPmStepsPtrSingle (
- OUT UINT8 *NumSystemSteps,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- SYS_PM_TBL_STEP *Ignored;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
-
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
- FamilySpecificServices->GetSysPmTableStruct (FamilySpecificServices, &Ignored, NumSystemSteps, StdHeader);
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Single socket call to determine the frequency that the northbridges must run.
- *
- * This function simply returns the executing core's NB frequency, and that all
- * NB frequencies are equivalent.
- *
- * @param[in] NbPstate NB P-state number to check (0 = fastest)
- * @param[in] PlatformConfig Platform profile/build option config structure.
- * @param[out] SystemNbCofNumerator NB frequency numerator for the system in MHz
- * @param[out] SystemNbCofDenominator NB frequency denominator for the system
- * @param[out] SystemNbCofsMatch Whether or not all NB frequencies are equivalent
- * @param[out] NbPstateIsEnabledOnAllCPUs Whether or not NbPstate is valid on all CPUs
- * @param[in] StdHeader Config handle for library and services
- *
- * @retval TRUE At least one processor has NbPstate enabled.
- * @retval FALSE NbPstate is disabled on all CPUs
- *
- */
-BOOLEAN
-GetSystemNbCofSingle (
- IN UINT32 NbPstate,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- OUT UINT32 *SystemNbCofNumerator,
- OUT UINT32 *SystemNbCofDenominator,
- OUT BOOLEAN *SystemNbCofsMatch,
- OUT BOOLEAN *NbPstateIsEnabledOnAllCPUs,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Ignored;
- PCI_ADDR PciAddress;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
-
- PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0);
- *SystemNbCofsMatch = TRUE;
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
- *NbPstateIsEnabledOnAllCPUs = FamilySpecificServices->GetNbPstateInfo (FamilySpecificServices,
- PlatformConfig,
- &PciAddress,
- NbPstate,
- SystemNbCofNumerator,
- SystemNbCofDenominator,
- &Ignored,
- StdHeader);
- return *NbPstateIsEnabledOnAllCPUs;
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Single socket call to determine if the BIOS is responsible for updating the
- * northbridge operating frequency and voltage.
- *
- * This function simply returns whether or not the executing core needs NB COF
- * VID programming.
- *
- * @param[in] StdHeader Config handle for library and services
- *
- * @retval TRUE BIOS needs to set up NB frequency and voltage
- * @retval FALSE BIOS does not need to set up NB frequency and voltage
- *
- */
-BOOLEAN
-GetSystemNbCofVidUpdateSingle (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- BOOLEAN Ignored;
- PCI_ADDR PciAddress;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
-
- PciAddress.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0);
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
- return (FamilySpecificServices->IsNbCofInitNeeded (FamilySpecificServices, &PciAddress, &Ignored, StdHeader));
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Single socket call to determine the most severe AGESA_STATUS return value after
- * processing the power management initialization tables.
- *
- * This function searches the event log for the most severe error and returns
- * the status code. This function must be called by the BSC only.
- *
- * @param[in] StdHeader Config handle for library and services
- *
- * @return The most severe error code from power management init
- *
- */
-AGESA_STATUS
-GetEarlyPmErrorsSingle (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT16 i;
- AGESA_EVENT EventLogEntry;
- AGESA_STATUS ReturnCode;
-
- ASSERT (IsBsp (StdHeader, &ReturnCode));
-
- ReturnCode = AGESA_SUCCESS;
- for (i = 0; PeekEventLog (&EventLogEntry, i, StdHeader); i++) {
- if ((EventLogEntry.EventInfo & CPU_EVENT_PM_EVENT_MASK) == CPU_EVENT_PM_EVENT_CLASS) {
- if (EventLogEntry.EventClass > ReturnCode) {
- ReturnCode = EventLogEntry.EventClass;
- }
- }
- }
-
- return (ReturnCode);
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/cpuPowerMgmtSingleSocket.h b/src/vendorcode/amd/agesa/Proc/CPU/cpuPowerMgmtSingleSocket.h
deleted file mode 100644
index d132284..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/cpuPowerMgmtSingleSocket.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU Power Management Single Socket Functions.
- *
- * Contains code for doing power management for single socket CPU
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPU_POWER_MGMT_SINGLE_SOCKET_H_
-#define _CPU_POWER_MGMT_SINGLE_SOCKET_H_
-
-
-/*---------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *---------------------------------------------------------------------------------------
- */
-VOID
-RunCodeOnAllSystemCore0sSingle (
- IN AP_TASK *TaskPtr,
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN VOID *ConfigParams
- );
-
-VOID
-GetNumberOfSystemPmStepsPtrSingle (
- OUT UINT8 *NumSystemSteps,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-BOOLEAN
-GetSystemNbCofSingle (
- IN UINT32 NbPstate,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- OUT UINT32 *SystemNbCofNumerator,
- OUT UINT32 *SystemNbCofDenominator,
- OUT BOOLEAN *SystemNbCofsMatch,
- OUT BOOLEAN *NbPstateIsEnabledOnAllCPUs,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-BOOLEAN
-GetSystemNbCofVidUpdateSingle (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif // _CPU_POWER_MGMT_SINGLE_SOCKET_H_
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/cpuPowerMgmtSystemTables.h b/src/vendorcode/amd/agesa/Proc/CPU/cpuPowerMgmtSystemTables.h
deleted file mode 100644
index 46d83c7..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/cpuPowerMgmtSystemTables.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Power Management Table declarations.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPU_POWER_MGMT_SYSTEM_TABLES_H_
-#define _CPU_POWER_MGMT_SYSTEM_TABLES_H_
-
-
-/*---------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *---------------------------------------------------------------------------------------
- */
-#define PM_EXEFLAGS_WARM_ONLY 0x00000001 /* Skip step if set && cold reset */
-#define PM_EXEFLAGS_NOT_ON_S3 0x00000002 /* Skip step if S3 resume */
-#define PM_EXEFLAGS_SYSTEM_TASK 0x00000004 /* Future use */
-#define PM_EXEFLAGS_SERIAL_EXE 0x00000008 /* BSC will wait for remote core 0 to complete the step*/
-
-
-/*---------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *---------------------------------------------------------------------------------------
- */
-typedef VOID F_PM_STEP_FUNCTION (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a Method.
-typedef F_PM_STEP_FUNCTION *PF_PM_STEP_FUNCTION;
-
-
-/// A structure representing a step in a power management
-/// initialization process to be invoked at AmdInitEarly
-typedef struct {
- UINT32 ExeFlags; ///< Execution flags
- PF_PM_STEP_FUNCTION FuncPtr; ///< Function pointer
-} SYS_PM_TBL_STEP;
-
-
-/*---------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *---------------------------------------------------------------------------------------
- */
-
-
-#endif // _CPU_POWER_MGMT_SYSTEM_TABLES_H_/
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/agesa/Proc/CPU/cpuRegisters.h
deleted file mode 100644
index beeb2a4..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/cpuRegisters.h
+++ /dev/null
@@ -1,407 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU Register Table Related Functions
- *
- * Contains the definition of the CPU CPUID MSRs and PCI registers with BKDG recommended values
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 37150 $ @e \$Date: 2010-08-31 23:53:37 +0800 (Tue, 31 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPU_REGISTERS_H_
-#define _CPU_REGISTERS_H_
-
-#include "cpuFamRegisters.h"
-/*
- *--------------------------------------------------------------
- *
- * M O D U L E S U S E D
- *
- *---------------------------------------------------------------
- */
-
-/*
- *--------------------------------------------------------------
- *
- * D E F I N I T I O N S / M A C R O S
- *
- *---------------------------------------------------------------
- */
-
-#define BIT0 0x0000000000000001ull
-#define BIT1 0x0000000000000002ull
-#define BIT2 0x0000000000000004ull
-#define BIT3 0x0000000000000008ull
-#define BIT4 0x0000000000000010ull
-#define BIT5 0x0000000000000020ull
-#define BIT6 0x0000000000000040ull
-#define BIT7 0x0000000000000080ull
-#define BIT8 0x0000000000000100ull
-#define BIT9 0x0000000000000200ull
-#define BIT10 0x0000000000000400ull
-#define BIT11 0x0000000000000800ull
-#define BIT12 0x0000000000001000ull
-#define BIT13 0x0000000000002000ull
-#define BIT14 0x0000000000004000ull
-#define BIT15 0x0000000000008000ull
-#define BIT16 0x0000000000010000ull
-#define BIT17 0x0000000000020000ull
-#define BIT18 0x0000000000040000ull
-#define BIT19 0x0000000000080000ull
-#define BIT20 0x0000000000100000ull
-#define BIT21 0x0000000000200000ull
-#define BIT22 0x0000000000400000ull
-#define BIT23 0x0000000000800000ull
-#define BIT24 0x0000000001000000ull
-#define BIT25 0x0000000002000000ull
-#define BIT26 0x0000000004000000ull
-#define BIT27 0x0000000008000000ull
-#define BIT28 0x0000000010000000ull
-#define BIT29 0x0000000020000000ull
-#define BIT30 0x0000000040000000ull
-#define BIT31 0x0000000080000000ull
-#define BIT32 0x0000000100000000ull
-#define BIT33 0x0000000200000000ull
-#define BIT34 0x0000000400000000ull
-#define BIT35 0x0000000800000000ull
-#define BIT36 0x0000001000000000ull
-#define BIT37 0x0000002000000000ull
-#define BIT38 0x0000004000000000ull
-#define BIT39 0x0000008000000000ull
-#define BIT40 0x0000010000000000ull
-#define BIT41 0x0000020000000000ull
-#define BIT42 0x0000040000000000ull
-#define BIT43 0x0000080000000000ull
-#define BIT44 0x0000100000000000ull
-#define BIT45 0x0000200000000000ull
-#define BIT46 0x0000400000000000ull
-#define BIT47 0x0000800000000000ull
-#define BIT48 0x0001000000000000ull
-#define BIT49 0x0002000000000000ull
-#define BIT50 0x0004000000000000ull
-#define BIT51 0x0008000000000000ull
-#define BIT52 0x0010000000000000ull
-#define BIT53 0x0020000000000000ull
-#define BIT54 0x0040000000000000ull
-#define BIT55 0x0080000000000000ull
-#define BIT56 0x0100000000000000ull
-#define BIT57 0x0200000000000000ull
-#define BIT58 0x0400000000000000ull
-#define BIT59 0x0800000000000000ull
-#define BIT60 0x1000000000000000ull
-#define BIT61 0x2000000000000000ull
-#define BIT62 0x4000000000000000ull
-#define BIT63 0x8000000000000000ull
-
-/// CPUID related registers
-#define AMD_CPUID_FMF 0x80000001 // Family Model Features information
-#define AMD_CPUID_APICID_LPC_BID 0x00000001 // Local APIC ID, Logical Processor Count, Brand ID
-#define AMD_CPUID_L2L3Cache_L2TLB 0x80000006
-#define AMD_CPUID_TLB_L1Cache 0x80000005
-#define AMD_CPUID_APM 0x80000007
-#define LOCAL_APIC_ID 24
-#define LOGICAL_PROCESSOR_COUNT 16
-#define AMD_CPUID_ASIZE_PCCOUNT 0x80000008 // Address Size, Physical Core Count
-
-/// CPU Logical ID Transfer
-typedef struct {
- UINT32 RawId; ///< RawID
- UINT64 LogicalId; ///< LogicalID
-} CPU_LOGICAL_ID_XLAT;
-
-/// Logical CPU ID Table
-typedef struct {
- IN UINT32 Elements; ///< Number of Elements
- IN CPU_LOGICAL_ID_XLAT *LogicalIdTable; ///< CPU Logical ID Transfer table Pointer
-} LOGICAL_ID_TABLE;
-
-// MSRs
-// ------------------------
-#define MCG_CTL_P 0x00000100 // bit 8 for MCG_CTL_P under MSRR
-#define MSR_MCG_CAP 0x00000179
-#define MSR_MC0_CTL 0x00000400
-
-#define MSR_APIC_BAR 0x0000001B
-#define MSR_PATCH_LEVEL 0x0000008B
-
-#define CPUID_LONG_MODE_ADDR 0x80000008
-#define AMD_CPUID_FMF 0x80000001
-
-#define MSR_EXTENDED_FEATURE_EN 0xC0000080
-#define MSR_MC_MISC_LINK_THRESHOLD 0xC0000408
-#define MSR_MC_MISC_L3_THRESHOLD 0xC0000409
-#define MSR_PATCH_LOADER 0xC0010020
-
-/// Patch Loader Register
-typedef struct {
- UINT64 PatchBase:32; ///< Linear address of patch header address block
- UINT64 SBZ:32; ///< Should be zero
-} PATCH_LOADER_MSR;
-
-#define MSR_SYS_CFG 0xC0010010 // SYSCFG - F15 Shared
-#define MSR_TOM2 0xC001001D // TOP_MEM2 - F15 Shared
-#define MSR_MC4_CTL_MASK 0xC0010048 // MC4 Control Mask
-
-#define MSR_CPUID_FEATS 0xC0011004 // CPUID Features
-#define MSR_CPUID_EXT_FEATS 0xC0011005 // CPUID Extended Features
-#define MSR_HWCR 0xC0010015
-#define MSR_NB_CFG 0xC001001F // NB Config
-#define ENABLE_CF8_EXT_CFG 0x00004000 // [46]
-#define INIT_APIC_CPUID_LO 0x00400000 // [54]
-#define MSR_LS_CFG 0xC0011020
-#define MSR_IC_CFG 0xC0011021 // ICache Config - F15 Shared
-#define MSR_DC_CFG 0xC0011022
-#define MSR_ME_CFG 0xC0011029
-#define MSR_BU_CFG 0xC0011023
-#define MSR_CU_CFG 0xC0011023 // F15 Shared
-#define MSR_DE_CFG 0xC0011029 // F15 Shared
-#define MSR_BU_CFG2 0xC001102A
-#define MSR_CU_CFG2 0xC001102A // F15 Shared
-#define MSR_BU_CFG3 0xC001102B
-#define MSR_CU_CFG3 0xC001102B // F15 Shared
-#define MSR_IBS_OP_DATA3 0xC0011037
-
-
-#define MSR_CPUID_NAME_STRING0 0xC0010030 // First CPUID namestring register
-#define MSR_CPUID_NAME_STRING1 0xC0010031
-#define MSR_CPUID_NAME_STRING2 0XC0010032
-#define MSR_CPUID_NAME_STRING3 0xC0010033
-#define MSR_CPUID_NAME_STRING4 0xC0010034
-#define MSR_CPUID_NAME_STRING5 0xC0010035 // Last CPUID namestring register
-#define MSR_MMIO_Cfg_Base 0xC0010058 // MMIO Configuration Base Address Register
-#define MSR_BIST 0xC0010060 // BIST Results register
-#define MSR_OSVW_ID_Length 0xC0010140
-#define MSR_OSVW_Status 0xC0010141
-#define MSR_PERF_CONTROL3 0xC0010003 // Perfromance control register number 3
-#define MSR_PERF_COUNTER3 0xC0010007 // Performance counter register number 3
-#define PERF_RESERVE_BIT_MASK 0x030FFFDFFFFF // Mask of the Performance control Reserve bits
-#define PERF_CAR_CORRUPTION_EVENT 0x040040F0E2 // Configure the controller to capture the
- // CAR Corruption
-// FUNC_0 registers
-// ----------------
-#define HT_LINK_FREQ_OFFSET 8 // Link HT Frequency from capability base
-#define HT_LINK_CONTROL_REG_OFFSET 4
-#define HT_LINK_TYPE_REG_OFFSET 0x18
-#define HT_LINK_EXTENDED_FREQ 0x1C
-#define HT_LINK_HOST_CAP_MAX 0x20 // HT Host Capability offsets are less than its size.
-#define HT_CAPABILITIES_POINTER 0x34
-#define NODE_ID 0x60
-#define HT_INIT_CTRL 0x6C
-#define HT_INIT_CTRL_REQ_DIS 0x02 // [1] = ReqDis
-#define HT_INIT_COLD_RST_DET BIT4
-#define HT_INIT_BIOS_RST_DET_0 BIT5
-#define HT_INIT_BIOS_RST_DET_1 BIT9
-#define HT_INIT_BIOS_RST_DET_2 BIT10
-#define HT_INIT_BIOS_RST_DET BIT9 | BIT10
-#define HT_TRANS_CTRL 0x68
-#define HT_TRANS_CTRL_CPU1_EN 0x00000020 // [5] = CPU1 Enable
-#define HT_LINK_CONTROL_0 0x84
-#define HT_LINK_FREQ_0 0x88 // Link HT Frequency
-#define EXTENDED_NODE_ID 0x160
-#define ECS_HT_TRANS_CTRL 0x168
-#define ECS_HT_TRANS_CTRL_CPU2_EN 0x00000001 // [0] = CPU2 Enable
-#define ECS_HT_TRANS_CTRL_CPU3_EN 0x00000002 // [1] = CPU3 Enable
-#define ECS_HT_TRANS_CTRL_CPU4_EN 0x00000004 // [2] = CPU4 Enable
-#define ECS_HT_TRANS_CTRL_CPU5_EN 0x00000008 // [3] = CPU5 Enable
-
-#define CORE_CTRL 0x1DC
-#define CORE_CTRL_CORE1_EN 0x00000002
-#define CORE_CTRL_CORE2_EN 0x00000004
-#define CORE_CTRL_CORE3_EN 0x00000008
-#define CORE_CTRL_CORE4_EN 0x00000010
-#define CORE_CTRL_CORE5_EN 0x00000020
-#define CORE_CTRL_CORE6_EN 0x00000040
-#define CORE_CTRL_CORE7_EN 0x00000080
-
-// FUNC_3 registers
-// ----------------
-#define HARDWARE_THERMAL_CTRL_REG 0x64
-#define SOFTWARE_THERMAL_CTRL_REG 0x68
-
-#define ACPI_PSC_0_REG 0x80 // ACPI Power State Control Registers
-#define ACPI_PSC_4_REG 0x84
-
-#define NB_CFG_HIGH_REG 0x8C
-#define POWER_CTRL_MISCELLANEOUS_REG 0xA0
-#define CLOCK_POWER_TIMING_CTRL2_REG 0xDC
-#define NORTH_BRIDGE_CAPABILITIES_REG 0xE8
-#define MULTI_NODE_CPU 29
-#define CPUID_FMR 0xFC // Family / Model registers
-#define DOWNCORE_CTRL 0x190 // Downcore Control Register
-
-#define LINK_TO_XCS_TOKEN_COUNT_REG_3X148 0x148
-#define REG_HT4_PHY_OFFSET_BASE_4X180 0x180
-#define REG_HT4_PHY_DATA_PORT_BASE_4X184 0x184
-
-#define HTPHY_OFFSET_MASK 0xE00001FF
-#define HTPHY_WRITE_CMD 0x40000000
-#define HTPHY_IS_COMPLETE_MASK 0x80000000
-#define HTPHY_DIRECT_MAP 0x20000000
-#define HTPHY_DIRECT_OFFSET_MASK 0xE000FFFF
-
-// FUNC_5 registers
-// ----------------
-#define COMPUTE_UNIT_STATUS 0x80
-#define NORTH_BRIDGE_CAPABILITIES_2_REG 0x84
-
-
-// Misc. defines.
-#define PCI_DEV_BASE 24
-
-#define CPU_STEPPING 0x0000000F
-#define CPU_MODEL 0x000000F0
-#define CPU_EMODEL 0x000F0000
-#define CPU_EFAMILY 0x00F00000
-#define CPU_FMS_MASK CPU_EFAMILY | CPU_EMODEL | CPU_MODEL | CPU_STEPPING
-
-#define HTPHY_SELECT 2
-#define PCI_SELECT 1
-#define MSR_SELECT 0
-
-#define LOGICAL_ID 1
-#define F_SCHEME 0
-#define DR_SCHEME 1
-#define GR_SCHEME 2
-
-#define DR_NO_STRING 0
-#define DR_SOCKET_C32 5
-#define DR_SOCKET_ASB2 4
-#define DR_SOCKET_G34 3
-#define DR_SOCKET_S1G3 2
-#define DR_SOCKET_S1G4 2
-#define DR_SOCKET_AM3 1
-#define DR_SOCKET_1207 0
-#define LN_SOCKET_FM1 2
-#define LN_SOCKET_FS1 1
-#define LN_SOCKET_FP1 0
-#define ON_SOCKET_FT1 0
-#define OR_SOCKET_AM3 1
-#define OR_SOCKET_G34 3
-#define OR_SOCKET_C32 5
-#define SOCKET_IGNORE 0xF
-
-#define LAPIC_BASE_ADDR_MASK 0x0000FFFFFFFFF000
-#define APIC_EXT_BRDCST_MASK 0x000E0000
-#define APIC_ENABLE_BIT 0x00000800
-#define LOCAL_APIC_ADDR 0xFEE00000
-#define INT_CMD_REG_LO 0x300
-#define INT_CMD_REG_HI 0x310
-#define REMOTE_MSG_REG 0x380
-#define REMOTE_READ_REG 0xC0
-#define APIC_ID_REG 0x20
-#define APIC20_ApicId 24
-#define CMD_REG_TO_READ_DATA 0x338
-
-#define MAX_CORE_ID_SIZE 8
-#define MAX_CORE_ID_MASK ((1 << MAX_CORE_ID_SIZE) - 1)
-
-/*-------------------------
- * Default definitions
- *-------------------------
- */
-#define DOWNCORE_MASK_SINGLE 0xFFFFFFFE
-#define DOWNCORE_MASK_DUAL 0xFFFFFFFC
-#define DOWNCORE_MASK_TRI 0xFFFFFFF8
-#define DOWNCORE_MASK_FOUR 0xFFFFFFF0
-#define DOWNCORE_MASK_FIVE 0xFFFFFFE0
-#define DOWNCORE_MASK_SIX 0xFFFFFFC0
-#define DOWNCORE_MASK_DUAL_COMPUTE_UNIT 0xFFFFFFFA
-#define DOWNCORE_MASK_TRI_COMPUTE_UNIT 0xFFFFFFEA
-#define DOWNCORE_MASK_FOUR_COMPUTE_UNIT 0xFFFFFFAA
-
-#define DELIVERY_STATUS BIT13
-#define REMOTE_READ_STAT_MASK 0x00030000
-#define REMOTE_DELIVERY_PENDING 0x00010000
-#define REMOTE_DELIVERY_DONE 0x00020000
-
-/*
- * --------------------------------------------------------------------------------------
- *
- * D E F I N E S / T Y P E D E F S / S T R U C T U R E S
- *
- * --------------------------------------------------------------------------------------
- */
-
-/// CpuEarly param type
-typedef struct {
- IN UINT8 MemInitPState; ///< Pstate value during memory initial
- IN PLATFORM_CONFIGURATION PlatformConfig; ///< Runtime configurable user options
-} AMD_CPU_EARLY_PARAMS;
-
-/// Enum - Will be used to access each structure
-/// related to each CPU family
-typedef enum {
- REVF, ///< NPT, RevF
- REVG, ///< NPT, RevG
- DEERHOUND, ///< Family 10h, Deerhound
- GRIFFIN ///< Family 11h, Griffin
-} CPU_FAMILY;
-
-/// CPUID
-typedef enum {
- REG_EAX, ///< EAX
- REG_EBX, ///< EBX
- REG_ECX, ///< ECX
- REG_EDX ///< EDX
-} CPUID_REG;
-
-/// MSR table entry for DSM workaround
-typedef struct {
- UINT32 Address; ///< MSR address to program
- UINT64 Nand; ///< Bitwise NAND mask to apply during read-modify-write
- UINT64 Or; ///< Bitwise OR mask to apply during read-modify-write
-} MSR_DSM_ENTRY;
-
-/// Interrupt Descriptor Table entry
-typedef struct {
- UINT16 OffsetLo; ///< Lower 16 bits of the interrupt handler routine's offset
- UINT16 Selector; ///< Interrupt handler routine's selector
- UINT8 Rsvd; ///< Reserved
- UINT8 Flags; ///< Interrupt flags
- UINT16 OffsetHi; ///< Upper 16 bits of the interrupt handler routine's offset
- UINT32 Offset64; ///< High order 32 bits of the handler's offset needed when in 64 bit mode
- UINT32 Rsvd64; ///< Reserved
-} IDT_DESCRIPTOR;
-
-typedef struct {
- UINT16 Limit; ///< Interrupt Descriptor Table size
- UINT64 Base; ///< Interrupt Descriptor Table base address
-} IDT_BASE_LIMIT;
-#endif // _CPU_REGISTERS_H_
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/cpuServices.h b/src/vendorcode/amd/agesa/Proc/CPU/cpuServices.h
deleted file mode 100644
index eedfc0b..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/cpuServices.h
+++ /dev/null
@@ -1,347 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU Services
- *
- * Related to the General Services API's, but for the CPU component.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 36208 $ @e \$Date: 2010-08-13 22:55:05 +0800 (Fri, 13 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPU_SERVICES_H_
-#define _CPU_SERVICES_H_
-
-/*----------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
- /// WARM RESET STATE_BITS
-#define WR_STATE_COLD 00
-#define WR_STATE_RESET 01
-#define WR_STATE_EARLY 02
-#define WR_STATE_POST 03
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *----------------------------------------------------------------------------------------
- */
-
-/**
- * The role of primary core for each compute unit can be relative to the cores' launch order.
- *
- * One core of a compute unit is always given the role as primary. In different feature algorithms
- * the core performing the primary core role can be designated relative to compute order. In most cases,
- * the primary core is the first core of a compute unit to execute. However, in some cases the primary core
- * role is associated with the last core to execute.
- *
- * If the launch order is strictly ascending, then first core is the lowest number and last core is highest.
- * But if the launch order is not ascending, the first and last core follow the launch order, not the numbering order.
- *
- * Note that for compute units with only one core (AllCoresMapping), that core is primary for both orderings.
- * (This includes processors without hardware compute units.)
- *
- */
-typedef enum {
- FirstCoreIsComputeUnitPrimary, ///< the primary core role associates with the first core.
- LastCoreIsComputeUnitPrimary, ///< the primary core role associates with the last core.
- MaxComputeUnitPrimarySelector, ///< limit check.
-} COMPUTE_UNIT_PRIMARY_SELECTOR;
-
-/**
- * The supported Core to Compute unit mappings.
- */
-typedef enum {
- AllCoresMapping, ///< All Cores are primary cores
- EvenCoresMapping, ///< Compute units are even/odd core pairs.
- BitMapMapping, ///< Currently not supported by any family, arbitrary core
- ///< to compute unit mapping.
- MaxComputeUnitMapping ///< Not a mapping, use for limit check.
-} COMPUTE_UNIT_MAPPING;
-
-/**
- * Core Pair Map entry.
- * Provide for interpreting the core pairing for the processor's compute units.
- *
- * HT_LIST_TERMINAL as an Enabled value means the end of a list of map structs.
- * Zero as an Enabled value implies Compute Units are not supported by the processor
- * and the mapping is assumed to be AllCoresMapping.
- *
- */
-typedef struct {
- UINT8 Enabled; ///< The value of the Enabled Compute Units
- UINT8 DualCore; ///< The value of the Dual Core Compute Units
- COMPUTE_UNIT_MAPPING Mapping; ///< When the processor module matches these values, use this mapping method.
-} CORE_PAIR_MAP;
-
-//----------------------------------------------------------------------------
-// CPU SYSTEM INFO TYPEDEFS, STRUCTURES, ENUMS
-//
-//----------------------------------------------------------------------------
-/// SYSTEM INFO
-typedef struct _SYSTEM_INFO {
- UINT32 TotalNumberOfSockets; ///< Total Number of Sockets
- UINT32 TotalNumberOfCores; ///< Total Number Of Cores
- UINT32 CurrentSocketNum; ///< Current Socket Number
- UINT32 CurrentCoreNum; ///< Current Core Number
- UINT32 CurrentCoreApicId; ///< Current Core Apic ID
- UINT32 CurrentLogicalCpuId; ///< Current Logical CPU ID
-} SYSTEM_INFO;
-
-/// WARM_RESET_REQUEST
-typedef struct _WARM_RESET_REQUEST {
- UINT8 RequestBit:1; ///< Request Bit
- UINT8 StateBits:2; ///< State Bits
- UINT8 PostStage:2; ///< Post Stage
- UINT8 Reserved:(8-5); ///< Reserved
-} WARM_RESET_REQUEST;
-/*----------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *----------------------------------------------------------------------------------------
- */
-
-VOID
-GetCurrentNodeNum (
- OUT UINT32 *Node,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * Get the current Platform's number of Sockets, regardless of how many are populated.
- *
- */
-UINT32
-GetPlatformNumberOfSockets (VOID);
-
-/**
- * Get the number of Modules to check presence in each Processor.
- *
- */
-UINT32
-GetPlatformNumberOfModules (VOID);
-
-BOOLEAN
-IsProcessorPresent (
- IN UINT32 Socket,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * For a specific Node, get its Socket and Module ids.
- *
- */
-BOOLEAN
-GetSocketModuleOfNode (
- IN UINT32 Node,
- OUT UINT32 *Socket,
- OUT UINT32 *Module,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * Get the current core's Processor APIC Index.
- */
-UINT32
-GetProcessorApicIndex (
- IN UINT32 Node,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * Writes to all nodes on the executing core's socket.
- *
- */
-VOID
-ModifyCurrentSocketPci (
- IN PCI_ADDR *PciAddress,
- IN UINT32 Mask,
- IN UINT32 Data,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * Provide the number of installed processors (not Nodes! and not Sockets!)
- */
-UINT32
-GetNumberOfProcessors (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-GetActiveCoresInCurrentSocket (
- OUT UINT32 *CoreCount,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-BOOLEAN
-GetActiveCoresInGivenSocket (
- IN UINT32 Socket,
- OUT UINT32 *CoreCount,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-UINTN
-GetActiveCoresInCurrentModule (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-UINTN
-GetNumberOfCompUnitsInCurrentModule (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-BOOLEAN
-GetGivenModuleCoreRange (
- IN UINT32 Socket,
- IN UINT32 Module,
- OUT UINT32 *LowCore,
- OUT UINT32 *HighCore,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-GetCurrentCore (
- OUT UINT32 *Core,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-GetCurrentNodeAndCore (
- OUT UINT32 *Node,
- OUT UINT32 *Core,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-BOOLEAN
-IsCurrentCorePrimary (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-GetApMailbox (
- OUT UINT32 *ApMailboxInfo,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-CacheApMailbox (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-UINTN
-GetSystemDegree (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-BOOLEAN
-GetNodeId (
- IN UINT32 SocketId,
- IN UINT32 ModuleId,
- OUT UINT8 *NodeId,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-WaitMicroseconds (
- IN UINT32 Microseconds,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * Get the compute unit mapping algorithm.
- */
-COMPUTE_UNIT_MAPPING
-GetComputeUnitMapping (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * Does the current core have the role of primary core for the compute unit?
- */
-BOOLEAN
-IsCorePairPrimary (
- IN COMPUTE_UNIT_PRIMARY_SELECTOR Selector,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * Are the two specified cores shared in a compute unit?
- */
-BOOLEAN
-AreCoresPaired (
- IN UINT32 Socket,
- IN UINT32 Module,
- IN UINT32 CoreA,
- IN UINT32 CoreB,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-SetWarmResetFlag (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN WARM_RESET_REQUEST *Request
- );
-
-VOID
-GetWarmResetFlag (
- IN AMD_CONFIG_PARAMS *StdHeader,
- OUT WARM_RESET_REQUEST *Request
- );
-
-BOOLEAN
-IsWarmReset (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-CheckBistStatus (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-SetWarmResetAtEarly (
- IN UINT32 Data,
- IN AMD_CONFIG_PARAMS *StdHeader
-);
-
-#endif // _CPU_SERVICES_H_
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/cpuWarmReset.c b/src/vendorcode/amd/agesa/Proc/CPU/cpuWarmReset.c
deleted file mode 100644
index bfed40a..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/cpuWarmReset.c
+++ /dev/null
@@ -1,237 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU Warm Reset Implementation.
- *
- * Implement Warm Reset Interface.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuServices.h"
-#include "cpuFamilyTranslation.h"
-#include "amdlib.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_CPUWARMRESET_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * This function will set the CPU register warm reset bits.
- *
- * Note: This function will be called by UEFI BIOS's
- * The UEFI wrapper code should register this function, to be called back later point
- * in time, before the wrapper code does warm reset.
- *
- * @param[in] StdHeader Config handle for library and services
- * @param[in] Request Indicate warm reset status
- *
- *---------------------------------------------------------------------------------------
- **/
-VOID
-SetWarmResetFlag (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN WARM_RESET_REQUEST *Request
- )
-{
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
- FamilySpecificServices = NULL;
-
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
- FamilySpecificServices->SetWarmResetFlag (FamilySpecificServices, StdHeader, Request);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * This function will get the CPU register warm reset bits.
- *
- * Note: This function will be called by UEFI BIOS's
- * The UEFI wrapper code should register this function, to be called back later point
- * in time, before the wrapper code does warm reset.
- *
- * @param[in] StdHeader Config handle for library and services
- * @param[out] Request Indicate warm reset status
- *
- *---------------------------------------------------------------------------------------
- **/
-VOID
-GetWarmResetFlag (
- IN AMD_CONFIG_PARAMS *StdHeader,
- OUT WARM_RESET_REQUEST *Request
- )
-{
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
- FamilySpecificServices = NULL;
-
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
- FamilySpecificServices->GetWarmResetFlag (FamilySpecificServices, StdHeader, Request);
-
- switch (StdHeader->Func) {
- case AMD_INIT_RESET:
- Request->PostStage = (UINT8) WR_STATE_RESET;
- break;
- case AMD_INIT_EARLY:
- Request->PostStage = (UINT8) WR_STATE_EARLY;
- break;
- case AMD_INIT_POST:
- // Fall through to default case
- default:
- Request->PostStage = (UINT8) WR_STATE_POST;
- break;
- }
-}
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S - (AGESA ONLY)
- *----------------------------------------------------------------------------------------
- */
-
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Is this boot a warm reset?
- *
- * This function reads the CPU register warm reset bit that is preserved after a warm reset.
- * Which in fact gets set before issuing warm reset. We just use the BSP's register always.
- *
- * @param[in] StdHeader Config handle for library and services
- *
- * @retval TRUE Warm Reset
- * @retval FALSE Not Warm Reset
- *
- */
-BOOLEAN
-IsWarmReset (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 PostStage;
- WARM_RESET_REQUEST Request;
- BOOLEAN WarmReset;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
-
- FamilySpecificServices = NULL;
-
- switch (StdHeader->Func) {
- case AMD_INIT_RESET:
- PostStage = WR_STATE_RESET;
- break;
- case AMD_INIT_EARLY:
- PostStage = WR_STATE_EARLY;
- break;
- case AMD_INIT_POST:
- default:
- PostStage = WR_STATE_POST;
- break;
- }
-
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
- FamilySpecificServices->GetWarmResetFlag (FamilySpecificServices, StdHeader, &Request);
-
- if (Request.StateBits >= PostStage) {
- WarmReset = TRUE;
- } else {
- WarmReset = FALSE;
- }
-
- return WarmReset;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * This function will set the CPU register warm reset bits at AmdInitEarly if it is
- * currently in cold boot. To request for a warm reset, set the RequestBit to TRUE
- * and the StateBits to (current poststage - 1)
- *
- * @param[in] Data The table data value (unused in this routine)
- * @param[in] StdHeader Config handle for library and services
- *
- *---------------------------------------------------------------------------------------
- **/
-VOID
-SetWarmResetAtEarly (
- IN UINT32 Data,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- WARM_RESET_REQUEST Request;
-
- if (!IsWarmReset (StdHeader)) {
- GetWarmResetFlag (StdHeader, &Request);
-
- Request.RequestBit = TRUE;
- Request.StateBits = (Request.PostStage - 1);
-
- SetWarmResetFlag (StdHeader, &Request);
- }
-}
-
-/*----------------------------------------------------------------------------------------
- * L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/Proc/CPU/heapManager.c
deleted file mode 100644
index 520b961..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/heapManager.c
+++ /dev/null
@@ -1,853 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Heap Manager and Heap Allocation APIs, and related functions.
- *
- * Contains code that initialize, maintain, and allocate the heap space.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 38448 $ @e \$Date: 2010-09-24 07:13:08 +0800 (Fri, 24 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuServices.h"
-#include "GeneralServices.h"
-#include "heapManager.h"
-#include "cpuCacheInit.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_CPU_HEAPMANAGER_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-UINT64
-STATIC
-HeapGetCurrentBase (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-STATIC
-DeleteFreeSpaceNode (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN UINT32 OffsetOfDeletedNode
- );
-
-VOID
-STATIC
-InsertFreeSpaceNode (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN UINT32 OffsetOfInsertNode
- );
-
-/*----------------------------------------------------------------------------------------
- * P U B L I C F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-extern BUILD_OPT_CFG UserOptions;
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * This function initializes the heap for each CPU core.
- *
- * Check for already initialized. If not, determine offset of local heap in CAS and
- * setup initial heap markers and bookkeeping status. Initialize a couple heap items
- * all cores need, for convenience. Currently these are caching the AP mailbox info and
- * an initial event log.
- *
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @retval AGESA_SUCCESS This core's heap is initialized
- * @retval AGESA_FATAL This core's heap cannot be initialized due to any reasons below:
- * - current processor family cannot be identified.
- *
- */
-AGESA_STATUS
-HeapManagerInit (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- // First Time Initialization
- // Note: First 16 bytes of buffer is reserved for Heap Manager use
- UINT16 HeapAlreadyInitSizeDword;
- UINT32 HeapAlreadyRead;
- UINT8 L2LineSize;
- UINT8 *HeapBufferPtr;
- UINT8 *HeapInitPtr;
- UINT32 *HeapDataPtr;
- UINT64 MsrData;
- UINT64 MsrMask;
- UINT8 Ignored;
- CPUID_DATA CpuId;
- BUFFER_NODE *FreeSpaceNode;
- CACHE_INFO *CacheInfoPtr;
- AGESA_STATUS IgnoredSts;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
- CPU_LOGICAL_ID CpuFamilyRevision;
-
- // Check whether this is a known processor family.
- GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
- if ((CpuFamilyRevision.Family == 0) && (CpuFamilyRevision.Revision == 0)) {
- IDS_ERROR_TRAP;
- return AGESA_FATAL;
- }
-
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
- FamilySpecificServices->GetCacheInfo (FamilySpecificServices, &CacheInfoPtr, &Ignored, StdHeader);
- HeapBufferPtr = (UINT8 *) StdHeader->HeapBasePtr;
-
- // Check whether the heap manager is already initialized
- LibAmdMsrRead (AMD_MTRR_VARIABLE_HEAP_MASK, &MsrData, StdHeader);
- if (MsrData == (CacheInfoPtr->VariableMtrrMask & AMD_HEAP_MTRR_MASK)) {
- LibAmdMsrRead (AMD_MTRR_VARIABLE_HEAP_BASE, &MsrData, StdHeader);
- if ((MsrData & CacheInfoPtr->HeapBaseMask) == ((UINT64) HeapBufferPtr & CacheInfoPtr->HeapBaseMask)) {
- if (((HEAP_MANAGER *) HeapBufferPtr)->Signature == HEAP_SIGNATURE_VALID) {
- // This is not a bug, there are multiple premem basic entry points,
- // and each will call heap init to make sure create struct will succeed.
- // If that is later deemed a problem, there needs to be a reasonable test
- // for the calling code to make to determine if it needs to init heap or not.
- // In the mean time, add this to the event log
- PutEventLog (AGESA_SUCCESS,
- CPU_ERROR_HEAP_IS_ALREADY_INITIALIZED,
- 0, 0, 0, 0, StdHeader);
- return AGESA_SUCCESS;
- }
- }
- }
-
- // Set variable MTRR base and mask
- MsrData = ((UINT64) HeapBufferPtr & CacheInfoPtr->HeapBaseMask);
- MsrMask = CacheInfoPtr->VariableMtrrHeapMask & AMD_HEAP_MTRR_MASK;
-
- MsrData |= 0x06;
- LibAmdMsrWrite (AMD_MTRR_VARIABLE_HEAP_BASE, &MsrData, StdHeader);
- LibAmdMsrWrite (AMD_MTRR_VARIABLE_HEAP_MASK, &MsrMask, StdHeader);
-
- // Set top of memory to a temp value
- MsrData = (UINT64) (AMD_TEMP_TOM);
- LibAmdMsrWrite (TOP_MEM, &MsrData, StdHeader);
-
- // Enable variable MTTRs
- LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader);
- MsrData |= AMD_VAR_MTRR_ENABLE_BIT;
- LibAmdMsrWrite (SYS_CFG, &MsrData, StdHeader);
-
- // Initialize Heap Space
- // BIOS may store to a line only after it has been allocated by a load
- LibAmdCpuidRead (AMD_CPUID_L2L3Cache_L2TLB, &CpuId, StdHeader);
- L2LineSize = (UINT8) (CpuId.ECX_Reg);
- HeapInitPtr = HeapBufferPtr ;
- for (HeapAlreadyRead = 0; HeapAlreadyRead < AMD_HEAP_SIZE_PER_CORE;
- (HeapAlreadyRead = HeapAlreadyRead + L2LineSize)) {
- Ignored = *HeapInitPtr;
- HeapInitPtr += L2LineSize;
- }
-
- HeapDataPtr = (UINT32 *) HeapBufferPtr;
- for (HeapAlreadyInitSizeDword = 0; HeapAlreadyInitSizeDword < AMD_HEAP_SIZE_DWORD_PER_CORE; HeapAlreadyInitSizeDword++) {
- *HeapDataPtr = 0;
- HeapDataPtr++;
- }
-
- // Note: We are reserving the first 16 bytes for Heap Manager use
- // UsedSize indicates the size of heap spaced is used for HEAP_MANAGER, BUFFER_NODE,
- // Pad for 16-byte alignment, buffer data, and IDS SENTINEL.
- // FirstActiveBufferOffset is initalized as invalid heap offset, AMD_HEAP_INVALID_HEAP_OFFSET.
- // FirstFreeSpaceOffset is initalized as the byte right after HEAP_MANAGER header.
- // Then we set Signature of HEAP_MANAGER header as valid, HEAP_SIGNATURE_VALID.
- ((HEAP_MANAGER*) HeapBufferPtr)->UsedSize = sizeof (HEAP_MANAGER);
- ((HEAP_MANAGER*) HeapBufferPtr)->FirstActiveBufferOffset = AMD_HEAP_INVALID_HEAP_OFFSET;
- ((HEAP_MANAGER*) HeapBufferPtr)->FirstFreeSpaceOffset = sizeof (HEAP_MANAGER);
- ((HEAP_MANAGER*) HeapBufferPtr)->Signature = HEAP_SIGNATURE_VALID;
- // Create free space link
- FreeSpaceNode = (BUFFER_NODE *) (HeapBufferPtr + sizeof (HEAP_MANAGER));
- FreeSpaceNode->BufferSize = AMD_HEAP_SIZE_PER_CORE - sizeof (HEAP_MANAGER) - sizeof (BUFFER_NODE);
- FreeSpaceNode->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET;
-
- StdHeader->HeapStatus = HEAP_LOCAL_CACHE;
- if (!IsBsp (StdHeader, &IgnoredSts)) {
- // The BSP's hardware mailbox has not been initialized, so only APs
- // can do this at this point.
- CacheApMailbox (StdHeader);
- }
- EventLogInitialization (StdHeader);
- return AGESA_SUCCESS;
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Allocates space for a new buffer in the heap
- *
- * This function will allocate new buffer either by using internal 'AGESA' heapmanager
- * or by using externa (IBV) heapmanager. This function will also determine if whether or not
- * there is enough space for the new structure. If so, it will zero out the buffer,
- * and return a pointer to the region.
- *
- * @param[in,out] AllocateHeapParams structure pointer containing the size of the
- * desired new region, its handle, and the
- * return pointer.
- * @param[in,out] StdHeader Config handle for library and services.
- *
- * @retval AGESA_SUCCESS No error
- * @retval AGESA_BOUNDS_CHK Handle already exists, or not enough
- * free space
- * @retval AGESA_ERROR Heap is invaild
- *
- */
-AGESA_STATUS
-HeapAllocateBuffer (
- IN OUT ALLOCATE_HEAP_PARAMS *AllocateHeapParams,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 *BaseAddress;
- UINT8 AlignTo16Byte;
- UINT32 RemainSize;
- UINT32 OffsetOfSplitNode;
- UINT32 OffsetOfNode;
- HEAP_MANAGER *HeapManager;
- BUFFER_NODE *FreeSpaceNode;
- BUFFER_NODE *SplitFreeSpaceNode;
- BUFFER_NODE *CurrentBufferNode;
- BUFFER_NODE *NewBufferNode;
- AGESA_BUFFER_PARAMS AgesaBuffer;
-
- ASSERT (StdHeader != NULL);
-
- // At this stage we will decide to either use external (IBV) heap manger
- // or internal (AGESA) heap manager.
-
- // If (HeapStatus == HEAP_SYSTEM_MEM), then use the call function to call
- // external heap manager
- if (StdHeader->HeapStatus == HEAP_SYSTEM_MEM) {
- AgesaBuffer.StdHeader = *StdHeader;
- AgesaBuffer.BufferHandle = AllocateHeapParams->BufferHandle;
- AgesaBuffer.BufferLength = AllocateHeapParams->RequestedBufferSize;
-
- AGESA_TESTPOINT (TpIfBeforeAllocateHeapBuffer, StdHeader);
- if (AgesaAllocateBuffer (0, &AgesaBuffer) != AGESA_SUCCESS) {
- AllocateHeapParams->BufferPtr = NULL;
- return AGESA_ERROR;
- }
- AGESA_TESTPOINT (TpIfAfterAllocateHeapBuffer, StdHeader);
-
- AllocateHeapParams->BufferPtr = (UINT8 *) (AgesaBuffer.BufferPointer);
- return AGESA_SUCCESS;
- }
-
- // If (StdHeader->HeapStatus != HEAP_SYSTEM_MEM), then allocated buffer
- // using following AGESA Heap Manager code.
-
- // Buffer pointer is NULL unless we return a buffer.
- AlignTo16Byte = 0;
- AllocateHeapParams->BufferPtr = NULL;
- AllocateHeapParams->RequestedBufferSize += NUM_OF_SENTINEL * SIZE_OF_SENTINEL;
-
- // Get base address
- BaseAddress = (UINT8 *) StdHeader->HeapBasePtr;
- HeapManager = (HEAP_MANAGER *) BaseAddress;
-
- // Check Heap database is valid
- if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) {
- ASSERT (FALSE);
- return AGESA_ERROR;
- }
-
- // Allocate
- CurrentBufferNode = (BUFFER_NODE *) (BaseAddress + sizeof (HEAP_MANAGER));
- // If there already has been a heap with the incoming BufferHandle, we return AGESA_BOUNDS_CHK.
- if (HeapManager->FirstActiveBufferOffset != AMD_HEAP_INVALID_HEAP_OFFSET) {
- CurrentBufferNode = (BUFFER_NODE *) (BaseAddress + HeapManager->FirstActiveBufferOffset);
- while (CurrentBufferNode->OffsetOfNextNode != AMD_HEAP_INVALID_HEAP_OFFSET) {
- if (CurrentBufferNode->BufferHandle == AllocateHeapParams->BufferHandle) {
- PutEventLog (AGESA_BOUNDS_CHK,
- CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED,
- AllocateHeapParams->BufferHandle, 0, 0, 0, StdHeader);
- return AGESA_BOUNDS_CHK;
- } else {
- CurrentBufferNode = (BUFFER_NODE *) (BaseAddress + CurrentBufferNode->OffsetOfNextNode);
- }
- }
- if (CurrentBufferNode->BufferHandle == AllocateHeapParams->BufferHandle) {
- PutEventLog (AGESA_BOUNDS_CHK,
- CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED,
- AllocateHeapParams->BufferHandle, 0, 0, 0, StdHeader);
- return AGESA_BOUNDS_CHK;
- }
- }
-
- // Find the buffer size that first matches the requested buffer size (i.e. the first free buffer of greater size).
- OffsetOfNode = HeapManager->FirstFreeSpaceOffset;
- FreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfNode);
- while (OffsetOfNode != AMD_HEAP_INVALID_HEAP_OFFSET) {
- AlignTo16Byte = (UINT8) ((0x10 - (((UINTN) (VOID *) FreeSpaceNode + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL) & 0xF)) & 0xF);
- AllocateHeapParams->RequestedBufferSize = (UINT32) (AllocateHeapParams->RequestedBufferSize + AlignTo16Byte);
- if (FreeSpaceNode->BufferSize >= AllocateHeapParams->RequestedBufferSize) {
- break;
- }
- AllocateHeapParams->RequestedBufferSize = (UINT32) (AllocateHeapParams->RequestedBufferSize - AlignTo16Byte);
- OffsetOfNode = FreeSpaceNode->OffsetOfNextNode;
- FreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfNode);
- }
- if (OffsetOfNode == AMD_HEAP_INVALID_HEAP_OFFSET) {
- // We don't find any free space buffer that matches the requested buffer size.
- PutEventLog (AGESA_BOUNDS_CHK,
- CPU_ERROR_HEAP_IS_FULL,
- AllocateHeapParams->BufferHandle, 0, 0, 0, StdHeader);
- return AGESA_BOUNDS_CHK;
- } else {
- // We find one matched free space buffer.
- DeleteFreeSpaceNode (StdHeader, OffsetOfNode);
- NewBufferNode = FreeSpaceNode;
- // Add new buffer node to the buffer chain
- if (HeapManager->FirstActiveBufferOffset == AMD_HEAP_INVALID_HEAP_OFFSET) {
- HeapManager->FirstActiveBufferOffset = sizeof (HEAP_MANAGER);
- } else {
- CurrentBufferNode->OffsetOfNextNode = OffsetOfNode;
- }
- // New buffer size
- RemainSize = FreeSpaceNode->BufferSize - AllocateHeapParams->RequestedBufferSize;
- if (RemainSize > sizeof (BUFFER_NODE)) {
- NewBufferNode->BufferSize = AllocateHeapParams->RequestedBufferSize;
- OffsetOfSplitNode = OffsetOfNode + sizeof (BUFFER_NODE) + NewBufferNode->BufferSize;
- SplitFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfSplitNode);
- SplitFreeSpaceNode->BufferSize = RemainSize - sizeof (BUFFER_NODE);
- InsertFreeSpaceNode (StdHeader, OffsetOfSplitNode);
- } else {
- // Remain size is less than BUFFER_NODE, we use whole size instead of requested size.
- NewBufferNode->BufferSize = FreeSpaceNode->BufferSize;
- }
- }
-
- // Initialize BUFFER_NODE structure of NewBufferNode
- NewBufferNode->BufferHandle = AllocateHeapParams->BufferHandle;
- if ((AllocateHeapParams->Persist == HEAP_TEMP_MEM) || (AllocateHeapParams->Persist == HEAP_SYSTEM_MEM)) {
- NewBufferNode->Persist = AllocateHeapParams->Persist;
- } else {
- NewBufferNode->Persist = HEAP_LOCAL_CACHE;
- }
- NewBufferNode->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET;
- NewBufferNode->PadSize = AlignTo16Byte;
-
- // Clear to 0x00
- LibAmdMemFill ((VOID *) ((UINT8 *) NewBufferNode + sizeof (BUFFER_NODE)), 0x00, NewBufferNode->BufferSize, StdHeader);
-
- // Debug feature
- SET_SENTINEL_BEFORE (NewBufferNode, AlignTo16Byte);
- SET_SENTINEL_AFTER (NewBufferNode);
-
- // Update global variables
- HeapManager->UsedSize += NewBufferNode->BufferSize + sizeof (BUFFER_NODE);
-
- // Now fill in the incoming structure
- AllocateHeapParams->BufferPtr = (UINT8 *) ((UINT8 *) NewBufferNode + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL + AlignTo16Byte);
- AllocateHeapParams->RequestedBufferSize -= (NUM_OF_SENTINEL * SIZE_OF_SENTINEL + AlignTo16Byte);
-
- return AGESA_SUCCESS;
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Deallocates a previously allocated buffer in the heap
- *
- * This function will deallocate buffer either by using internal 'AGESA' heapmanager
- * or by using externa (IBV) heapmanager.
- *
- * @param[in] BufferHandle Handle of the buffer to free.
- * @param[in] StdHeader Config handle for library and services.
- *
- * @retval AGESA_SUCCESS No error
- * @retval AGESA_BOUNDS_CHK Handle does not exist on the heap
- *
- */
-AGESA_STATUS
-HeapDeallocateBuffer (
- IN UINT32 BufferHandle,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 *BaseAddress;
- UINT32 NodeSize;
- UINT32 OffsetOfFreeSpaceNode;
- UINT32 OffsetOfPreviousNode;
- UINT32 OffsetOfCurrentNode;
- BOOLEAN HeapLocateFlag;
- HEAP_MANAGER *HeapManager;
- BUFFER_NODE *CurrentNode;
- BUFFER_NODE *PreviousNode;
- BUFFER_NODE *FreeSpaceNode;
- AGESA_BUFFER_PARAMS AgesaBuffer;
-
- ASSERT (StdHeader != NULL);
-
- HeapLocateFlag = TRUE;
- BaseAddress = (UINT8 *) StdHeader->HeapBasePtr;
- HeapManager = (HEAP_MANAGER *) BaseAddress;
-
- // Check Heap database is valid
- if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) {
- ASSERT (FALSE);
- return AGESA_ERROR;
- }
-
- OffsetOfPreviousNode = AMD_HEAP_INVALID_HEAP_OFFSET;
- OffsetOfCurrentNode = HeapManager->FirstActiveBufferOffset;
- CurrentNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode);
-
- // Locate heap
- if ((BaseAddress != NULL) && (HeapManager->Signature == HEAP_SIGNATURE_VALID)) {
- if (OffsetOfCurrentNode == AMD_HEAP_INVALID_HEAP_OFFSET) {
- HeapLocateFlag = FALSE;
- } else {
- while (CurrentNode->BufferHandle != BufferHandle) {
- if (CurrentNode->OffsetOfNextNode == AMD_HEAP_INVALID_HEAP_OFFSET) {
- HeapLocateFlag = FALSE;
- break;
- } else {
- OffsetOfPreviousNode = OffsetOfCurrentNode;
- OffsetOfCurrentNode = CurrentNode->OffsetOfNextNode;
- CurrentNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode);
- }
- }
- }
- } else {
- HeapLocateFlag = FALSE;
- }
-
- if (HeapLocateFlag == TRUE) {
- // CurrentNode points to the buffer which wanted to be deallocated.
- // Remove deallocated heap from active buffer chain.
- if (OffsetOfPreviousNode == AMD_HEAP_INVALID_HEAP_OFFSET) {
- HeapManager->FirstActiveBufferOffset = CurrentNode->OffsetOfNextNode;
- } else {
- PreviousNode = (BUFFER_NODE *) (BaseAddress + OffsetOfPreviousNode);
- PreviousNode->OffsetOfNextNode = CurrentNode->OffsetOfNextNode;
- }
- // Now, CurrentNode become a free space node.
- HeapManager->UsedSize -= CurrentNode->BufferSize + sizeof (BUFFER_NODE);
- // Loop free space chain to see if any free space node is just before/after CurrentNode, then merge them.
- OffsetOfFreeSpaceNode = HeapManager->FirstFreeSpaceOffset;
- FreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfFreeSpaceNode);
- while (OffsetOfFreeSpaceNode != AMD_HEAP_INVALID_HEAP_OFFSET) {
- if ((OffsetOfFreeSpaceNode + sizeof (BUFFER_NODE) + FreeSpaceNode->BufferSize) == OffsetOfCurrentNode) {
- DeleteFreeSpaceNode (StdHeader, OffsetOfFreeSpaceNode);
- NodeSize = FreeSpaceNode->BufferSize + CurrentNode->BufferSize + sizeof (BUFFER_NODE);
- OffsetOfCurrentNode = OffsetOfFreeSpaceNode;
- CurrentNode = FreeSpaceNode;
- CurrentNode->BufferSize = NodeSize;
- } else if (OffsetOfFreeSpaceNode == (OffsetOfCurrentNode + sizeof (BUFFER_NODE) + CurrentNode->BufferSize)) {
- DeleteFreeSpaceNode (StdHeader, OffsetOfFreeSpaceNode);
- NodeSize = FreeSpaceNode->BufferSize + CurrentNode->BufferSize + sizeof (BUFFER_NODE);
- CurrentNode->BufferSize = NodeSize;
- }
- OffsetOfFreeSpaceNode = FreeSpaceNode->OffsetOfNextNode;
- FreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfFreeSpaceNode);
- }
- InsertFreeSpaceNode (StdHeader, OffsetOfCurrentNode);
- return AGESA_SUCCESS;
- } else {
- // If HeapStatus == HEAP_SYSTEM_MEM, try callout function
- if (StdHeader->HeapStatus == HEAP_SYSTEM_MEM) {
- AgesaBuffer.StdHeader = *StdHeader;
- AgesaBuffer.BufferHandle = BufferHandle;
-
- AGESA_TESTPOINT (TpIfBeforeDeallocateHeapBuffer, StdHeader);
- if (AgesaDeallocateBuffer (0, &AgesaBuffer) != AGESA_SUCCESS) {
- return AGESA_ERROR;
- }
- AGESA_TESTPOINT (TpIfAfterDeallocateHeapBuffer, StdHeader);
-
- return AGESA_SUCCESS;
- }
- // If we are still unable to locate the buffer handle, return AGESA_BOUNDS_CHK
- if ((BaseAddress != NULL) && (HeapManager->Signature == HEAP_SIGNATURE_VALID)) {
- PutEventLog (AGESA_BOUNDS_CHK,
- CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT,
- BufferHandle, 0, 0, 0, StdHeader);
- } else {
- ASSERT (FALSE);
- }
- return AGESA_BOUNDS_CHK;
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Locates a previously allocated buffer on the heap.
- *
- * This function searches the heap for a buffer with the desired handle, and
- * returns a pointer to the buffer.
- *
- * @param[in,out] LocateHeap Structure containing the buffer's handle,
- * and the return pointer.
- * @param[in] StdHeader Config handle for library and services.
- *
- * @retval AGESA_SUCCESS No error
- * @retval AGESA_BOUNDS_CHK Handle does not exist on the heap
- *
- */
-AGESA_STATUS
-HeapLocateBuffer (
- IN OUT LOCATE_HEAP_PTR *LocateHeap,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 *BaseAddress;
- UINT8 AlignTo16Byte;
- UINT32 OffsetOfCurrentNode;
- BOOLEAN HeapLocateFlag;
- HEAP_MANAGER *HeapManager;
- BUFFER_NODE *CurrentNode;
- AGESA_BUFFER_PARAMS AgesaBuffer;
-
- ASSERT (StdHeader != NULL);
-
- HeapLocateFlag = TRUE;
- BaseAddress = (UINT8 *) StdHeader->HeapBasePtr;
- HeapManager = (HEAP_MANAGER *) BaseAddress;
-
- // Check Heap database is valid
- if ((BaseAddress == NULL) || (HeapManager->Signature != HEAP_SIGNATURE_VALID)) {
- ASSERT (FALSE);
- return AGESA_ERROR;
- }
- OffsetOfCurrentNode = HeapManager->FirstActiveBufferOffset;
- CurrentNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode);
-
- // Find buffer using internal heap manager
- // Locate the heap using handle = LocateHeap-> BufferHandle
- // If HeapStatus != HEAP_SYSTEM_ MEM
- if ((BaseAddress != NULL) && (HeapManager->Signature == HEAP_SIGNATURE_VALID)) {
- if (OffsetOfCurrentNode == AMD_HEAP_INVALID_HEAP_OFFSET) {
- HeapLocateFlag = FALSE;
- } else {
- while (CurrentNode->BufferHandle != LocateHeap->BufferHandle) {
- if (CurrentNode->OffsetOfNextNode == AMD_HEAP_INVALID_HEAP_OFFSET) {
- HeapLocateFlag = FALSE;
- break;
- } else {
- OffsetOfCurrentNode = CurrentNode->OffsetOfNextNode;
- CurrentNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode);
- }
- }
- }
- } else {
- HeapLocateFlag = FALSE;
- }
-
- if (HeapLocateFlag) {
- AlignTo16Byte = CurrentNode->PadSize;
- LocateHeap->BufferPtr = (UINT8 *) ((UINT8 *) CurrentNode + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL + AlignTo16Byte);
- LocateHeap->BufferSize = CurrentNode->BufferSize - NUM_OF_SENTINEL * SIZE_OF_SENTINEL - AlignTo16Byte;
- return AGESA_SUCCESS;
- } else {
- // If HeapStatus == HEAP_SYSTEM_MEM, try callout function
- if (StdHeader->HeapStatus == HEAP_SYSTEM_MEM) {
- AgesaBuffer.StdHeader = *StdHeader;
- AgesaBuffer.BufferHandle = LocateHeap->BufferHandle;
-
- AGESA_TESTPOINT (TpIfBeforeLocateHeapBuffer, StdHeader);
- if (AgesaLocateBuffer (0, &AgesaBuffer) != AGESA_SUCCESS) {
- LocateHeap->BufferPtr = NULL;
- return AGESA_ERROR;
- }
- LocateHeap->BufferSize = AgesaBuffer.BufferLength;
- AGESA_TESTPOINT (TpIfAfterLocateHeapBuffer, StdHeader);
-
- LocateHeap->BufferPtr = (UINT8 *) (AgesaBuffer.BufferPointer);
- return AGESA_SUCCESS;
- }
-
- // If we are still unable to deallocate the buffer handle, return AGESA_BOUNDS_CHK
- LocateHeap->BufferPtr = NULL;
- LocateHeap->BufferSize = 0;
- if ((BaseAddress != NULL) && (HeapManager->Signature == HEAP_SIGNATURE_VALID)) {
- PutEventLog (AGESA_BOUNDS_CHK,
- CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT,
- LocateHeap->BufferHandle, 0, 0, 0, StdHeader);
- } else {
- ASSERT (FALSE);
- }
- return AGESA_BOUNDS_CHK;
- }
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Get the heap base address
- *
- * This function will try to locate heap from cache, temp memory, main memory.
- * The heap signature will be checked for validity on each possible location.
- * Firstly, try if heap base is in cache by calling the function HeapGetCurrentBase.
- * Secondly, try if heap base is temp memory by UserOptoions.CfgHeapDramAddress.
- * Thirdly, try if heap base is in main memory by doing a buffer locate with buffer handle
- * AMD_HEAP_IN_MAIN_MEMORY_HANDLE.
- * If no valid heap signature is found in each possible location above, a NULL pointer is returned.
- *
- * @param[in] StdHeader Config handle for library and services.
- *
- * @return Heap base address of the executing core's heap.
- *
- */
-UINT64
-HeapGetBaseAddress (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 BaseAddress;
- HEAP_MANAGER *HeapManager;
- AGESA_BUFFER_PARAMS AgesaBuffer;
-
- // Firstly, we try to see if heap is in cache
- BaseAddress = HeapGetCurrentBase (StdHeader);
- HeapManager = (HEAP_MANAGER *) BaseAddress;
-
- if ((HeapManager->Signature != HEAP_SIGNATURE_VALID) &&
- (StdHeader->HeapStatus != HEAP_DO_NOT_EXIST_YET) &&
- (StdHeader->HeapStatus != HEAP_LOCAL_CACHE)) {
- // Secondly, we try to see if heap is in temp memory
- BaseAddress = UserOptions.CfgHeapDramAddress;
- HeapManager = (HEAP_MANAGER *) BaseAddress;
- if (HeapManager->Signature != HEAP_SIGNATURE_VALID) {
- // Thirdly, we try to see if heap in main memory
- // by locating with external buffer manager (IBV)
- AgesaBuffer.StdHeader = *StdHeader;
- AgesaBuffer.BufferHandle = AMD_HEAP_IN_MAIN_MEMORY_HANDLE;
- if (AgesaLocateBuffer (0, &AgesaBuffer) == AGESA_SUCCESS) {
- BaseAddress = (UINT64) AgesaBuffer.BufferPointer;
- HeapManager = (HEAP_MANAGER *) BaseAddress;
- if (HeapManager->Signature != HEAP_SIGNATURE_VALID) {
- // No valid heap signature ever found, return a NULL pointer
- BaseAddress = NULL;
- }
- } else {
- // No heap buffer is allocated by external manager (IBV), return a NULL pointer
- BaseAddress = NULL;
- }
- }
- }
-
- return BaseAddress;
-}
-
-/*---------------------------------------------------------------------------------------
- * L O C A L F U N C T I O N S
- *---------------------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * DeleteFreeSpaceNode
- *
- * Description:
- * Delete a free space node from free space chain
- *
- * Parameters:
- * @param[in] StdHeader Config handle for library and services.
- * @param[in] OffsetOfDeletedNode Offset of deleted node.
- *
- * Processing:
- *
- */
-VOID
-STATIC
-DeleteFreeSpaceNode (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN UINT32 OffsetOfDeletedNode
- )
-{
- UINT8 *BaseAddress;
- UINT32 OffsetOfPreviousNode;
- UINT32 OffsetOfCurrentNode;
- HEAP_MANAGER *HeapManager;
- BUFFER_NODE *CurrentFreeSpaceNode;
- BUFFER_NODE *PreviousFreeSpaceNode;
-
-
- BaseAddress = (UINT8 *) StdHeader->HeapBasePtr;
- HeapManager = (HEAP_MANAGER *) BaseAddress;
-
- OffsetOfPreviousNode = AMD_HEAP_INVALID_HEAP_OFFSET;
- OffsetOfCurrentNode = HeapManager->FirstFreeSpaceOffset;
- //
- // After AmdInitEnv, there is no free space provided for HeapAllocateBuffer.
- // Hence if the FirstFreeSpaceOffset is AMD_HEAP_INVALID_HEAP_OFFSET, then
- // no need to do more on delete node.
- //
- if (OffsetOfCurrentNode != AMD_HEAP_INVALID_HEAP_OFFSET) {
- CurrentFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode);
- while ((OffsetOfCurrentNode != AMD_HEAP_INVALID_HEAP_OFFSET) && (OffsetOfCurrentNode != OffsetOfDeletedNode)) {
- OffsetOfPreviousNode = OffsetOfCurrentNode;
- OffsetOfCurrentNode = CurrentFreeSpaceNode->OffsetOfNextNode;
- CurrentFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode);
- }
- if (OffsetOfCurrentNode != AMD_HEAP_INVALID_HEAP_OFFSET) {
- if (OffsetOfPreviousNode == AMD_HEAP_INVALID_HEAP_OFFSET) {
- HeapManager->FirstFreeSpaceOffset = CurrentFreeSpaceNode->OffsetOfNextNode;
- } else {
- PreviousFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfPreviousNode);
- PreviousFreeSpaceNode->OffsetOfNextNode = CurrentFreeSpaceNode->OffsetOfNextNode;
- }
- }
- }
- return;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * InsertFreeSpaceNode
- *
- * Description:
- * Insert a free space node to free space chain, size order
- *
- * Parameters:
- * @param[in] StdHeader Config handle for library and services.
- * @param[in] OffsetOfInsertNode Offset of inserted node.
- *
- * Processing:
- *
- */
-VOID
-STATIC
-InsertFreeSpaceNode (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN UINT32 OffsetOfInsertNode
- )
-{
- UINT8 *BaseAddress;
- UINT32 OffsetOfPreviousNode;
- UINT32 OffsetOfCurrentNode;
- HEAP_MANAGER *HeapManager;
- BUFFER_NODE *CurrentFreeSpaceNode;
- BUFFER_NODE *PreviousFreeSpaceNode;
- BUFFER_NODE *InsertFreeSpaceNode;
-
- BaseAddress = (UINT8 *) StdHeader->HeapBasePtr;
- HeapManager = (HEAP_MANAGER *) BaseAddress;
-
- OffsetOfPreviousNode = AMD_HEAP_INVALID_HEAP_OFFSET;
- OffsetOfCurrentNode = HeapManager->FirstFreeSpaceOffset;
- CurrentFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode);
- InsertFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfInsertNode);
- while ((OffsetOfCurrentNode != AMD_HEAP_INVALID_HEAP_OFFSET) &&
- (CurrentFreeSpaceNode->BufferSize < InsertFreeSpaceNode->BufferSize)) {
- OffsetOfPreviousNode = OffsetOfCurrentNode;
- OffsetOfCurrentNode = CurrentFreeSpaceNode->OffsetOfNextNode;
- CurrentFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfCurrentNode);
- }
- InsertFreeSpaceNode->OffsetOfNextNode = OffsetOfCurrentNode;
- if (OffsetOfPreviousNode == AMD_HEAP_INVALID_HEAP_OFFSET) {
- HeapManager->FirstFreeSpaceOffset = OffsetOfInsertNode;
- } else {
- PreviousFreeSpaceNode = (BUFFER_NODE *) (BaseAddress + OffsetOfPreviousNode);
- PreviousFreeSpaceNode->OffsetOfNextNode = OffsetOfInsertNode;
- }
- return;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Determines the base address of the executing core's heap.
- *
- * This function uses the executing core's socket/core numbers to determine
- * where it's heap should be located.
- *
- * @param[in] StdHeader Config handle for library and services.
- *
- * @return A pointer to the executing core's heap.
- *
- */
-UINT64
-STATIC
-HeapGetCurrentBase (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 SystemCoreNumber;
- UINT64 ReturnPtr;
- AGESA_STATUS IgnoredStatus;
- CPU_SPECIFIC_SERVICES *FamilyServices;
-
- if (IsBsp (StdHeader, &IgnoredStatus)) {
- ReturnPtr = AMD_HEAP_START_ADDRESS;
- } else {
- GetCpuServicesOfCurrentCore (&FamilyServices, StdHeader);
- ASSERT (FamilyServices != NULL);
-
- SystemCoreNumber = FamilyServices->GetApCoreNumber (FamilyServices, StdHeader);
- ASSERT (SystemCoreNumber != 0);
- ASSERT (SystemCoreNumber < 64);
- ReturnPtr = ((SystemCoreNumber * AMD_HEAP_SIZE_PER_CORE) + AMD_HEAP_START_ADDRESS);
- }
- ASSERT (ReturnPtr <= ((AMD_HEAP_REGION_END_ADDRESS + 1) - AMD_HEAP_SIZE_PER_CORE));
- return ReturnPtr;
-}
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/CPU/heapManager.h b/src/vendorcode/amd/agesa/Proc/CPU/heapManager.h
deleted file mode 100644
index 14e58f0..0000000
--- a/src/vendorcode/amd/agesa/Proc/CPU/heapManager.h
+++ /dev/null
@@ -1,230 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Heap Manager and Heap Allocation APIs, and related functions.
- *
- * Contains code that initialize, maintain, and allocate the heap space.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _HEAP_MANAGER_H_
-#define _HEAP_MANAGER_H_
-
-/*---------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *---------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *---------------------------------------------------------------------------------------
- */
-#define AMD_MTRR_VARIABLE_BASE0 0x200
-#define AMD_MTRR_VARIABLE_HEAP_BASE 0x20A
-#define AMD_MTRR_VARIABLE_HEAP_MASK (AMD_MTRR_VARIABLE_HEAP_BASE + 1)
-
-#define AMD_HEAP_START_ADDRESS 0x400000
-#define AMD_HEAP_REGION_END_ADDRESS 0xBFFFFF
-#define AMD_HEAP_SIZE_PER_CORE 0x010000
-#define AMD_HEAP_INVALID_HEAP_OFFSET 0xFFFFFFFF
-#define AMD_HEAP_MTRR_MASK ((0xFFFFFFFFFFFFF800 & ((AMD_HEAP_SIZE_PER_CORE ^ (-1)) + 1) | 0x800))
-#define AMD_HEAP_SIZE_DWORD_PER_CORE (AMD_HEAP_SIZE_PER_CORE / 4)
-
-#define AMD_TEMP_TOM 0x20000000 // Set TOM to 512 MB (temporary value)
-#define AMD_VAR_MTRR_ENABLE_BIT 0x100000 // bit 20
-
-#define AMD_HEAP_RAM_ADDRESS 0xB0000
-
-#define HEAP_SIGNATURE_VALID 0x50414548 // Signature: 'HEAP'
-#define HEAP_SIGNATURE_INVALID 0x00000000 // Signature cleared
-
-///Heap Manager Life cycle
-#define HEAP_DO_NOT_EXIST_YET 1
-#define HEAP_LOCAL_CACHE 2
-#define HEAP_TEMP_MEM 3
-#define HEAP_SYSTEM_MEM 4
-#define HEAP_DO_NOT_EXIST_ANYMORE 5
-#define HEAP_S3_RESUME 6
-
-
-#define AMD_MTRR_FIX64k_00000 0x250
-#define AMD_MTRR_FIX16k_80000 0x258
-#define AMD_MTRR_FIX16k_A0000 0x259
-#define AMD_MTRR_FIX4k_C0000 0x268
-#define AMD_MTRR_FIX4k_C8000 0x269
-#define AMD_MTRR_FIX4k_D0000 0x26A
-#define AMD_MTRR_FIX4k_D8000 0x26B
-#define AMD_MTRR_FIX4k_E0000 0x26C
-#define AMD_MTRR_FIX4k_E8000 0x26D
-#define AMD_MTRR_FIX4k_F0000 0x26E
-#define AMD_MTRR_FIX4k_F8000 0x26F
-
-#define AMD_MTRR_FIX64K_WB_DRAM 0x1E
-#define AMD_MTRR_FIX64K_WT_DRAM 0x1C
-#define AMD_MTRR_FIX64K_UC_DRAM 0x18
-#define AMD_MTRR_FIX16K_WB_DRAM 0x1E1E1E1E1E1E1E1E
-#define AMD_MTRR_FIX16K_WT_DRAM 0x1C1C1C1C1C1C1C1C
-#define AMD_MTRR_FIX16K_UC_DRAM 0x1818181818181818
-#define AMD_MTRR_FIX4K_WB_DRAM 0x1E1E1E1E1E1E1E1E
-#define AMD_MTRR_FIX4K_WT_DRAM 0x1C1C1C1C1C1C1C1C
-#define AMD_MTRR_FIX4K_UC_DRAM 0x1818181818181818
-
-/*---------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *---------------------------------------------------------------------------------------
- */
-/// Allocate Heap Parameters
-typedef struct _ALLOCATE_HEAP_PARAMS {
- UINT32 RequestedBufferSize; ///< Size of buffer.
- UINT32 BufferHandle; ///< An unique ID of buffer.
- UINT8 Persist; ///< A flag. If marked, to be stored and passed to AmdInitLate.
- UINT8 *BufferPtr; ///< Pointer to buffer.
-} ALLOCATE_HEAP_PARAMS;
-
-/// Locate Heap Parameters
-typedef struct _LOCATE_HEAP_PTR {
- UINT32 BufferHandle; ///< An unique ID of buffer.
- UINT32 BufferSize; ///< Data buffer size.
- UINT8 *BufferPtr; ///< Pointer to buffer.
-} LOCATE_HEAP_PTR;
-
-/// Heap Node Header
-typedef struct _BUFFER_NODE {
- UINT32 BufferHandle; ///< An unique ID of buffer.
- UINT32 BufferSize; ///< Size of buffer.
- UINT8 Persist; ///< A flag. If marked, to be stored and passed to AmdInitLate.
- UINT8 PadSize; ///< Size of pad.
- UINT32 OffsetOfNextNode; ///< Offset of next node (relative to the base).
-} BUFFER_NODE;
-
-/// Heap Manager
-typedef struct _HEAP_MANAGER {
- UINT32 Signature; ///< a signature to indicate if the heap is valid.
- UINT32 UsedSize; ///< Used size of heap.
- UINT32 FirstActiveBufferOffset; ///< Offset of the first active buffer.
- UINT32 FirstFreeSpaceOffset; ///< Offset of the first free space.
-} HEAP_MANAGER;
-
-/// AGESA Buffer Handles (These are reserved)
-typedef enum {
- AMD_INIT_RESET_HANDLE = 0x000A000, ///< Assign 0x000A000 buffer handle to AmdInitReset routine.
- AMD_INIT_EARLY_HANDLE, ///< Assign 0x000A001 buffer handle to AmdInitEarly routine.
- AMD_INIT_POST_HANDLE, ///< Assign 0x000A002 buffer handle to AmdInitPost routine.
- AMD_INIT_ENV_HANDLE, ///< Assign 0x000A003 buffer handle to AmdInitEnv routine.
- AMD_INIT_MID_HANDLE, ///< Assign 0x000A004 buffer handle to AmdInitMid routine.
- AMD_INIT_LATE_HANDLE, ///< Assign 0x000A005 buffer handle to AmdInitLate routine.
- AMD_INIT_RESUME_HANDLE, ///< Assign 0x000A006 buffer handle to AmdInitResume routine.
- AMD_LATE_RUN_AP_TASK_HANDLE, ///< Assign 0x000A007 buffer handle to AmdLateRunApTask routine.
- AMD_S3_SAVE_HANDLE, ///< Assign 0x000A008 buffer handle to AmdS3Save routine.
- AMD_S3_LATE_RESTORE_HANDLE, ///< Assign 0x000A009 buffer handle to AmdS3LateRestore routine.
- AMD_S3_SCRIPT_SAVE_TABLE_HANDLE, ///< Assign 0x000A00A buffer handle to be used for S3 save table
- AMD_S3_SCRIPT_TEMP_BUFFER_HANDLE, ///< Assign 0x000A00B buffer handle to be used for S3 save table
- AMD_CPU_AP_TASKING_HANDLE, ///< Assign 0x000A00C buffer handle to AP tasking input parameters.
- AMD_REC_MEM_SOCKET_HANDLE, ///< Assign 0x000A00D buffer handle to save socket with memory in memory recovery mode.
- AMD_MEM_AUTO_HANDLE, ///< Assign 0x000A00E buffer handle to AmdMemAuto routine.
- AMD_MEM_SPD_HANDLE, ///< Assign 0x000A00F buffer handle to AmdMemSpd routine.
- AMD_MEM_DATA_HANDLE, ///< Assign 0x000A010 buffer handle to MemData
- AMD_MEM_TRAIN_BUFFER_HANDLE, ///< Assign 0x000A011 buffer handle to allocate buffer for training
- AMD_MEM_S3_DATA_HANDLE, ///< Assign 0x000A012 buffer handle to special case register for S3
- AMD_MEM_S3_NB_HANDLE, ///< Assign 0x000A013 buffer handle to NB block for S3
- AMD_UMA_INFO_HANDLE, ///< Assign 0x000A014 buffer handle to be used for Uma information
- AMD_DMI_MEM_DEV_INFO_HANDLE, ///< Assign 0x000A015 buffer handle to DMI Type16 17 19 20 information
- HT_STATE_DATA_HANDLE, ///< Assign 0x000A016 buffer handle to HT State Data
- PRESERVE_MAIL_BOX_HANDLE, ///< Assign 0x000A017 buffer handle for Preserve Mailbox Feature.
- EVENT_LOG_BUFFER_HANDLE, ///< Assign 0x000A018 buffer handle to Event Log
- IDS_CONTROL_HANDLE, ///< Assign 0x000A019 buffer handle to AmdIds routine.
- IDS_HT_DATA_HANDLE, ///< Assign 0x000A01A buffer handle to Ht IDS control
- IDS_HDT_OUT_BUFFER_HANDLE, ///< Assign 0x000A01B buffer handle to be used for HDTOUT support.
- IDS_CHECK_POINT_PERF_HANDLE, ///< Assign 0x000A01C buffer handle to Performance analysis
- IDS_GRA_HANDLE, ///< Assign 0x000A01D buffer handle to be used for GRA support
- AMD_PCIE_COMPLEX_DATA_HANDLE, ///< Assign 0x000A01E buffer handle to be used for PCIe support
- AMD_GNB_SMU_CONFIG_HANDLE, ///< Assign 0x000A01F buffer handle to be used for GNB SMU configuration
- AMD_PP_FUSE_TABLE_HANDLE, ///< Assign 0x000A020 buffer handle to be used for TT fuse table
- AMD_GFX_PLATFORM_CONFIG_HANDLE, ///< Assign 0x000A021 buffer handle to be used for Gfx platform configuration
- AMD_MEM_MISC_HANDLES_START = 0x1000000, ///< Reserve 0x1000000 to 0x1FFFFFF buffer handle
- AMD_MEM_MISC_HANDLES_END = 0x1FFFFFF, ///< miscellaneous memory init tasks' buffers.
- AMD_HEAP_IN_MAIN_MEMORY_HANDLE = 0x8000000, ///< Assign 0x8000000 to AMD_HEAP_IN_MAIN_MEMORY_HANDLE.
- SOCKET_DIE_MAP_HANDLE = 0x534F4B54, ///< 'sokt'
- NODE_ID_MAP_HANDLE = 0x4E4F4445, ///< 'node'
- HOP_COUNT_TABLE_HANDLE = 0x484F5053, ///< 'hops'
- LOCAL_AP_MAIL_BOX_CACHE_HANDLE = 0x414D4258, ///< 'ambx'
- IDS_REG_TABLE_HANDLE = 0x49524547 ///< 'IREG' Handle for IDS register table
-} AGESA_BUFFER_HANDLE;
-
-
-/*---------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *---------------------------------------------------------------------------------------
- */
-
-AGESA_STATUS
-HeapManagerInit (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-HeapAllocateBuffer (
- IN OUT ALLOCATE_HEAP_PARAMS *AllocateHeapParams,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-HeapDeallocateBuffer (
- IN UINT32 BufferHandle,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-HeapLocateBuffer (
- IN OUT LOCATE_HEAP_PTR *LocateHeap,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-UINT64
-HeapGetBaseAddress (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-EventLogInitialization (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-#endif // _HEAP_MANAGER_H_
diff --git a/src/vendorcode/amd/agesa/Proc/Common/AmdInitEarly.c b/src/vendorcode/amd/agesa/Proc/Common/AmdInitEarly.c
deleted file mode 100644
index bf74376..0000000
--- a/src/vendorcode/amd/agesa/Proc/Common/AmdInitEarly.c
+++ /dev/null
@@ -1,281 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD AGESA Basic Level Public APIs
- *
- * Contains basic Level Initialization routines.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Interface
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuCacheInit.h"
-#include "cpuRegisters.h"
-#include "cpuApicUtilities.h"
-#include "cpuEarlyInit.h"
-#include "AdvancedApi.h"
-#include "cpuServices.h"
-#include "CommonInits.h"
-#include "GnbInterface.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_COMMON_AMDINITEARLY_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-EXECUTION_CACHE_REGION InitExeCacheMap[] =
-{
- {0x00000000, 0x00000000},
- {0x00000000, 0x00000000},
- {0x00000000, 0x00000000}
-};
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-extern BUILD_OPT_CFG UserOptions;
-/*------------------------------------------------------------------------------------*/
-/**
- * Initialize AmdInitEarly stage platform profile and user option input.
- *
- * @param[in,out] PlatformConfig Platform profile/build option config structure
- * @param[in,out] StdHeader AMD standard header config param
- *
- * @retval AGESA_SUCCESS Always Succeeds.
- *
- */
-AGESA_STATUS
-AmdEarlyPlatformConfigInit (
- IN OUT PLATFORM_CONFIGURATION *PlatformConfig,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- CommonPlatformConfigInit (PlatformConfig, StdHeader);
-
- return AGESA_SUCCESS;
-}
-/*------------------------------------------------------------------------------------*/
-/**
- * Initializer routine that will be invoked by the wrapper to initialize the input
- * structure for the AllocateExecutionCache.
- *
- * @param[in] StdHeader Opaque handle to standard config header
- * @param[in] AmdExeAddrMapPtr Our Service interface struct
- *
- * @retval AGESA_SUCCESS Always Succeeds.
- *
- */
-AGESA_STATUS
-AllocateExecutionCacheInitializer (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr
- )
-{
- UINT8 i;
- ASSERT (AmdExeAddrMapPtr != NULL);
-
- for (i = 0; i < MAX_CACHE_REGIONS; ++i) {
- AmdExeAddrMapPtr[i].ExeCacheStartAddr = InitExeCacheMap[i].ExeCacheStartAddr;
- AmdExeAddrMapPtr[i].ExeCacheSize = InitExeCacheMap[i].ExeCacheSize;
- }
-
- return AGESA_SUCCESS;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * Initializer routine that will be invoked by the wrapper to initialize the input
- * structure for the AmdInitEarly.
- *
- * @param[in] StdHeader AMD standard header config param.
- * @param[in,out] EarlyParams The service interface struct to initialize.
- *
- * @retval AGESA_SUCCESS Always succeeds.
- */
-AGESA_STATUS
-AmdInitEarlyInitializer (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN OUT AMD_EARLY_PARAMS *EarlyParams
- )
-{
- ASSERT (StdHeader != NULL);
- ASSERT (EarlyParams != NULL);
-
- EarlyParams->StdHeader = *StdHeader;
-
- // We don't check any AGESA_STATUS from the called constructors, since they MUST all SUCCEED.
- //
-
- AllocateExecutionCacheInitializer (&EarlyParams->StdHeader, &EarlyParams->CacheRegion[0]);
-
- AmdHtInterfaceConstructor (&EarlyParams->StdHeader, &EarlyParams->HtConfig);
-
- AmdEarlyPlatformConfigInit (&EarlyParams->PlatformConfig, &EarlyParams->StdHeader);
-
- return AGESA_SUCCESS;
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Perform initialization services required at the Early Init POST time point.
- *
- * Execution Cache, HyperTransport, and AP Init advanced services are performed.
- *
- * @param[in] EarlyParams The interface struct for all early services
- *
- * @return The most severe AGESA_STATUS returned by any called service.
- *
- */
-AGESA_STATUS
-AmdInitEarly (
- IN OUT AMD_EARLY_PARAMS *EarlyParams
- )
-{
- AGESA_STATUS CalledAgesaStatus;
- AGESA_STATUS EarlyInitStatus;
- WARM_RESET_REQUEST Request;
- UINT8 PrevRequestBit;
- UINT8 PrevStateBits;
-
- AGESA_TESTPOINT (TpIfAmdInitEarlyEntry, &EarlyParams->StdHeader);
- IDS_PERF_TIME_MEASURE (&EarlyParams->StdHeader);
- ASSERT (EarlyParams != NULL);
- EarlyInitStatus = AGESA_SUCCESS;
- PrevRequestBit = FALSE;
- PrevStateBits = WR_STATE_COLD;
- IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitEarly: Start %x \n\n", PrevStateBits);
- // If a previously requested warm reset cannot be triggered in the
- // current stage, store the previous state of request and reset the
- // request struct to the current post stage
- GetWarmResetFlag (&EarlyParams->StdHeader, &Request);
- if (Request.RequestBit == TRUE) {
- if (Request.StateBits >= Request.PostStage) {
- PrevRequestBit = Request.RequestBit;
- PrevStateBits = Request.StateBits;
- Request.RequestBit = FALSE;
- Request.StateBits = Request.PostStage - 1;
- SetWarmResetFlag (&EarlyParams->StdHeader, &Request);
- }
- }
-
- IDS_OPTION_HOOK (IDS_INIT_EARLY_BEFORE, EarlyParams, &EarlyParams->StdHeader);
-
- // Setup ROM execution cache
- IDS_HDT_CONSOLE (MAIN_FLOW, "AllocateExecutionCache: Start\n");
- CalledAgesaStatus = AllocateExecutionCache (&EarlyParams->StdHeader, &EarlyParams->CacheRegion[0]);
- IDS_HDT_CONSOLE (MAIN_FLOW, "AllocateExecutionCache: End\n");
- if (CalledAgesaStatus > EarlyInitStatus) {
- EarlyInitStatus = CalledAgesaStatus;
- }
-
- // Full Hypertransport Initialization
- // IMPORTANT: All AP cores call Ht Init. HT Init handles full init for the BSC, and map init for APs.
- IDS_HDT_CONSOLE (MAIN_FLOW, "AmdHtInitialize: Start\n");
- CalledAgesaStatus = AmdHtInitialize (&EarlyParams->StdHeader, &EarlyParams->PlatformConfig, &EarlyParams->HtConfig);
- IDS_HDT_CONSOLE (MAIN_FLOW, "AmdHtInitialize: End\n");
- if (CalledAgesaStatus > EarlyInitStatus) {
- EarlyInitStatus = CalledAgesaStatus;
- }
-
- // AP launch
- IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuEarly: Start\n");
- CalledAgesaStatus = AmdCpuEarly (&EarlyParams->StdHeader, &EarlyParams->PlatformConfig);
- IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuEarly: End\n");
- if (CalledAgesaStatus > EarlyInitStatus) {
- EarlyInitStatus = CalledAgesaStatus;
- }
-
- // Warm Reset, should be at the end of AmdInitEarly
- GetWarmResetFlag (&EarlyParams->StdHeader, &Request);
- // If a warm reset is requested in the current post stage, trigger the
- // warm reset and ignore the previous request
- if (Request.RequestBit == TRUE) {
- if (Request.StateBits < Request.PostStage) {
- AgesaDoReset (WARM_RESET_WHENEVER, &EarlyParams->StdHeader);
- }
- } else {
- // Otherwise, if there's a previous request, restore it
- // so that the subsequent post stage can trigger the warm reset
- if (PrevRequestBit == TRUE) {
- Request.RequestBit = PrevRequestBit;
- Request.StateBits = PrevStateBits;
- SetWarmResetFlag (&EarlyParams->StdHeader, &Request);
- }
- }
-
- CalledAgesaStatus = GnbInitAtEarly (EarlyParams);
-
- if (CalledAgesaStatus > EarlyInitStatus) {
- EarlyInitStatus = CalledAgesaStatus;
- }
- // Check for Cache As Ram Corruption
- IDS_CAR_CORRUPTION_CHECK (&EarlyParams->StdHeader);
-
- IDS_OPTION_HOOK (IDS_BEFORE_WARM_RESET, EarlyParams, &EarlyParams->StdHeader);
- IDS_OPTION_HOOK (IDS_INIT_EARLY_AFTER, EarlyParams, &EarlyParams->StdHeader);
- IDS_PERF_TIME_MEASURE (&EarlyParams->StdHeader);
- AGESA_TESTPOINT (TpIfAmdInitEarlyExit, &EarlyParams->StdHeader);
- IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitEarly: End\n\n");
- return EarlyInitStatus;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Common/AmdInitEnv.c b/src/vendorcode/amd/agesa/Proc/Common/AmdInitEnv.c
deleted file mode 100644
index c986795..0000000
--- a/src/vendorcode/amd/agesa/Proc/Common/AmdInitEnv.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD AGESA Basic Level Public APIs
- *
- * Contains basic Level Initialization routines.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Interface
- * @e \$Revision: 37658 $ @e \$Date: 2010-09-09 15:25:38 +0800 (Thu, 09 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "cpuEnvInit.h"
-#include "heapManager.h"
-#include "GnbInterface.h"
-#include "CommonInits.h"
-#include "S3SaveState.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_COMMON_AMDINITENV_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-/*
- *---------------------------------------------------------------------------------------
- *
- * Initializer routine that will be invoked by the wrapper
- * to initialize the input structure for the AmdInitEnv
- *
- * @param[in,out] EnvParamsPtr Newly created interface parameters for AmdInitEnv
- *
- * @retval AGESA_SUCCESS Always succeeds
- *
- *---------------------------------------------------------------------------------------
- */
-AGESA_STATUS
-AmdInitEnvInitializer (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN OUT AMD_ENV_PARAMS *EnvParamsPtr
- )
-{
- ASSERT (StdHeader != NULL);
- ASSERT (EnvParamsPtr != NULL);
-
- EnvParamsPtr->StdHeader = *StdHeader;
-
- CommonPlatformConfigInit (&EnvParamsPtr->PlatformConfig, &EnvParamsPtr->StdHeader);
- GnbInitDataStructAtEnvDef (&EnvParamsPtr->GnbEnvConfiguration, EnvParamsPtr);
-
- return AGESA_SUCCESS;
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Main entry point for the AMD_INIT_ENV function.
- *
- * This entry point is responsible for copying the heap contents from the
- * temp RAM area to main memory.
- *
- * @param[in,out] EnvParams Required input parameters for the AMD_INIT_ENV
- * entry point.
- *
- * @return Aggregated status across all internal AMD env calls invoked.
- *
- */
-AGESA_STATUS
-AmdInitEnv (
- IN OUT AMD_ENV_PARAMS *EnvParams
- )
-{
- AGESA_STATUS AgesaStatus;
- AGESA_STATUS AmdInitEnvStatus;
-
- AGESA_TESTPOINT (TpIfAmdInitEnvEntry, &EnvParams->StdHeader);
-
- ASSERT (EnvParams != NULL);
- AmdInitEnvStatus = AGESA_SUCCESS;
-
-
- //Copy Temp Ram heap content to Main Ram
- AgesaStatus = CopyHeapToMainRamAtPost (&(EnvParams->StdHeader));
- if (AgesaStatus > AmdInitEnvStatus) {
- AmdInitEnvStatus = AgesaStatus;
- }
- EnvParams->StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
- EnvParams->StdHeader.HeapBasePtr = HeapGetBaseAddress (&EnvParams->StdHeader);
- // Any heap allocate/deallocat/locate buffer should be used after heap is rebuild from here.
- // After persist heaps are tansfer and rebuild, HeapLocateBuffer can start to be used in IDS hook.
-
- //Heap have been relocated, so Debug Print need be init again to get new address
- IDS_HDT_CONSOLE_INIT (&EnvParams->StdHeader);
- IDS_HDT_CONSOLE (MAIN_FLOW, "Heap transfer End\n");
- IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitEnv: Start\n\n");
- IDS_OPTION_HOOK (IDS_PLATFORMCFG_OVERRIDE, &EnvParams->PlatformConfig, &(EnvParams->StdHeader));
- IDS_OPTION_HOOK (IDS_BEFORE_PCI_INIT, EnvParams, &(EnvParams->StdHeader));
-
- AgesaStatus = S3ScriptInit (&EnvParams->StdHeader);
- if (AgesaStatus > AmdInitEnvStatus) {
- AmdInitEnvStatus = AgesaStatus;
- }
-
- AgesaStatus = GnbInitAtEnv (EnvParams);
- if (AgesaStatus > AmdInitEnvStatus) {
- AmdInitEnvStatus = AgesaStatus;
- }
-
- AGESA_TESTPOINT (TpIfAmdInitEnvExit, &EnvParams->StdHeader);
- IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitEnv: End\n");
- IDS_HDT_CONSOLE_FLUSH_BUFFER (&EnvParams->StdHeader);
- return AmdInitEnvStatus;
-}
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Common/AmdInitLate.c b/src/vendorcode/amd/agesa/Proc/Common/AmdInitLate.c
deleted file mode 100644
index 3bc1aa2..0000000
--- a/src/vendorcode/amd/agesa/Proc/Common/AmdInitLate.c
+++ /dev/null
@@ -1,292 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD AGESA Basic Level Public APIs
- *
- * Contains basic Level Initialization routines.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Interface
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionDmi.h"
-#include "OptionSlit.h"
-#include "cpuLateInit.h"
-#include "cpuFeatures.h"
-#include "CommonInits.h"
-#include "GnbInterface.h"
-#include "OptionPstate.h"
-#include "Filecode.h"
-CODE_GROUP (G3_DXE)
-RDATA_GROUP (G3_DXE)
-
-#define FILECODE PROC_COMMON_AMDINITLATE_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-extern OPTION_DMI_CONFIGURATION OptionDmiConfiguration; // global user config record
-extern OPTION_SLIT_CONFIGURATION OptionSlitConfiguration; // global user config record
-extern OPTION_PSTATE_LATE_CONFIGURATION OptionPstateLateConfiguration;
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-extern BUILD_OPT_CFG UserOptions;
-
-/*------------------------------------------------------------------------------------*/
-/**
- * Initialize AmdInitLate stage platform profile and user option input.
- *
- * @param[in,out] PlatformConfig Platform profile/build option config structure
- * @param[in,out] StdHeader AMD standard header config param
- *
- * @retval AGESA_SUCCESS Always Succeeds.
- *
- */
-AGESA_STATUS
-AmdLatePlatformConfigInit (
- IN OUT PLATFORM_CONFIGURATION *PlatformConfig,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- CommonPlatformConfigInit (PlatformConfig, StdHeader);
-
- return AGESA_SUCCESS;
-}
-
-/*
- *---------------------------------------------------------------------------------------
- *
- * AmdInitLateInitializer
- *
- * Initializer routine that will be invoked by the wrapper
- * to initialize the input structure for the AmdInitLate
- *
- * @param[in, out] IN OUT AMD_LATE_PARAMS *LateParamsPtr
- *
- * @retval AGESA_STATUS
- *
- *---------------------------------------------------------------------------------------
- */
-AGESA_STATUS
-AmdInitLateInitializer (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN OUT AMD_LATE_PARAMS *LateParamsPtr
- )
-{
- ASSERT (StdHeader != NULL);
- ASSERT (LateParamsPtr != NULL);
-
- LateParamsPtr->StdHeader = *StdHeader;
-
- AmdLatePlatformConfigInit (&LateParamsPtr->PlatformConfig, &LateParamsPtr->StdHeader);
-
- LateParamsPtr->AcpiSlit = NULL;
-
- LateParamsPtr->AcpiSrat = NULL;
-
- LateParamsPtr->AcpiWheaMce = NULL;
- LateParamsPtr->AcpiWheaCmc = NULL;
-
- LateParamsPtr->AcpiPState = NULL;
-
- LateParamsPtr->DmiTable = NULL;
-
- LateParamsPtr->AcpiAlib = NULL;
-
- return AGESA_SUCCESS;
-}
-
-/*
- *---------------------------------------------------------------------------------------
- *
- * AmdInitLateDestructor
- *
- * Destruct routine that provide a chance if something need to be done
- * before the end of AmdInitLate.
- *
- * @param[in] StdHeader The standard header.
- * @param[in] LateParamsPtr AMD init late param.
- *
- * @retval AGESA_STATUS
- *
- *---------------------------------------------------------------------------------------
- */
-AGESA_STATUS
-AmdInitLateDestructor (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN AMD_LATE_PARAMS *LateParamsPtr
- )
-{
-
- ASSERT (LateParamsPtr != NULL);
-
- (*(OptionDmiConfiguration.DmiReleaseBuffer)) (StdHeader);
- (*(OptionSlitConfiguration.SlitReleaseBuffer)) (StdHeader);
-
- return AGESA_SUCCESS;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Main entry point for the AMD_INIT_LATE function.
- *
- * This entry point is responsible for creating any desired ACPI tables, providing
- * information for DMI, and to prepare the processors for the operating system
- * bootstrap load process.
- *
- * @param[in,out] LateParams Required input parameters for the AMD_INIT_LATE
- * entry point.
- *
- * @return Aggregated status across all internal AMD late calls invoked.
- *
- */
-AGESA_STATUS
-AmdInitLate (
- IN OUT AMD_LATE_PARAMS *LateParams
- )
-{
- AGESA_STATUS AgesaStatus;
- AGESA_STATUS AmdInitLateStatus;
- IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitLate: Start\n\n");
- AGESA_TESTPOINT (TpIfAmdInitLateEntry, &LateParams->StdHeader);
- IDS_PERF_TIME_MEASURE (&LateParams->StdHeader);
-
- ASSERT (LateParams != NULL);
- AmdInitLateStatus = AGESA_SUCCESS;
-
- IDS_OPTION_HOOK (IDS_INIT_LATE_BEFORE, LateParams, &LateParams->StdHeader);
-
- IDS_HDT_CONSOLE (MAIN_FLOW, "CreatSystemTable: Start\n");
- // _PSS, XPSS, _PCT, _PSD, _PPC, _CST, _CSD Tables
- if ((LateParams->PlatformConfig.UserOptionPState) || (IsFeatureEnabled (IoCstate, &LateParams->PlatformConfig, &LateParams->StdHeader))) {
- AgesaStatus = ((*(OptionPstateLateConfiguration.SsdtFeature)) (&LateParams->StdHeader, &LateParams->PlatformConfig, &LateParams->AcpiPState));
- if (AgesaStatus > AmdInitLateStatus) {
- AmdInitLateStatus = AgesaStatus;
- }
- }
-
- // SRAT Table Generation
- if (LateParams->PlatformConfig.UserOptionSrat) {
- AgesaStatus = CreateAcpiSrat (&LateParams->StdHeader, &LateParams->AcpiSrat);
- if (AgesaStatus > AmdInitLateStatus) {
- AmdInitLateStatus = AgesaStatus;
- }
- }
-
- // SLIT Table Generation
- if (LateParams->PlatformConfig.UserOptionSlit) {
- AgesaStatus = CreateAcpiSlit (&LateParams->StdHeader, &LateParams->PlatformConfig, &LateParams->AcpiSlit);
- if (AgesaStatus > AmdInitLateStatus) {
- AmdInitLateStatus = AgesaStatus;
- }
- }
-
- // WHEA Table Generation
- if (LateParams->PlatformConfig.UserOptionWhea) {
- AgesaStatus = CreateAcpiWhea (&LateParams->StdHeader, &LateParams->AcpiWheaMce, &LateParams->AcpiWheaCmc);
- if (AgesaStatus > AmdInitLateStatus) {
- AmdInitLateStatus = AgesaStatus;
- }
- }
-
- // DMI Table Generation
- if (LateParams->PlatformConfig.UserOptionDmi) {
- AgesaStatus = CreateDmiRecords (&LateParams->StdHeader, &LateParams->DmiTable);
- if (AgesaStatus > AmdInitLateStatus) {
- AmdInitLateStatus = AgesaStatus;
- }
- }
- IDS_HDT_CONSOLE (MAIN_FLOW, "CreatSystemTable: End\n");
-
- // Cpu Features
- IDS_HDT_CONSOLE (MAIN_FLOW, "DispatchCpuFeatures: LateStart\n");
- AgesaStatus = DispatchCpuFeatures (CPU_FEAT_INIT_LATE_END, &LateParams->PlatformConfig, &LateParams->StdHeader);
- IDS_HDT_CONSOLE (MAIN_FLOW, "DispatchCpuFeatures: LateEnd\n");
- if (AgesaStatus > AmdInitLateStatus) {
- AmdInitLateStatus = AgesaStatus;
- }
-
- // It is the last function run by the AGESA CPU module and prepares the processor
- // for the operating system bootstrap load process.
- IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuLate: Start\n");
- AgesaStatus = AmdCpuLate (&LateParams->StdHeader);
- IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuLate: End\n");
- if (AgesaStatus > AmdInitLateStatus) {
- AmdInitLateStatus = AgesaStatus;
- }
-
- AgesaStatus = GnbInitAtLate (LateParams);
- if (AgesaStatus > AmdInitLateStatus) {
- AmdInitLateStatus = AgesaStatus;
- }
-
- IDS_OPTION_HOOK (IDS_INIT_LATE_AFTER, LateParams, &LateParams->StdHeader);
-
- IDS_OPTION_HOOK (IDS_BEFORE_OS, LateParams, &LateParams->StdHeader);
- IDS_PERF_TIME_MEASURE (&LateParams->StdHeader);
- AGESA_TESTPOINT (TpIfAmdInitLateExit, &LateParams->StdHeader);
- IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitLate: End\n\n");
- AGESA_TESTPOINT (EndAgesaTps, &LateParams->StdHeader);
-//End Debug Print Service
- IDS_HDT_CONSOLE_EXIT (&LateParams->StdHeader);
- return AmdInitLateStatus;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/Common/AmdInitMid.c b/src/vendorcode/amd/agesa/Proc/Common/AmdInitMid.c
deleted file mode 100644
index efa668c..0000000
--- a/src/vendorcode/amd/agesa/Proc/Common/AmdInitMid.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD AGESA Basic Level Public APIs
- *
- * Contains basic Level Initialization routines.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Interface
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "cpuFeatures.h"
-#include "CommonInits.h"
-#include "GnbInterface.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_COMMON_AMDINITMID_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-/*
- *---------------------------------------------------------------------------------------
- *
- * Initializer routine that will be invoked by the wrapper
- * to initialize the input structure for the AmdInitMid
- *
- * @param[in,out] MidParamsPtr Newly created interface parameters for AmdInitMid
- *
- * @retval AGESA_SUCCESS Always succeeds
- *
- *---------------------------------------------------------------------------------------
- */
-AGESA_STATUS
-AmdInitMidInitializer (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN OUT AMD_MID_PARAMS *MidParamsPtr
- )
-{
- ASSERT (StdHeader != NULL);
- ASSERT (MidParamsPtr != NULL);
-
- MidParamsPtr->StdHeader = *StdHeader;
- CommonPlatformConfigInit (&MidParamsPtr->PlatformConfig, &MidParamsPtr->StdHeader);
-
- return AGESA_SUCCESS;
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Main entry point for the AMD_INIT_MID function.
- *
- * This entry point is responsible for performing any necessary functions needed
- * after PCI bus enumeration and just before control is passed to the video option ROM.
- *
- * @param[in,out] MidParams Required input parameters for the AMD_INIT_MID
- * entry point.
- *
- * @return Aggregated status across all internal AMD mid calls invoked.
- *
- */
-AGESA_STATUS
-AmdInitMid (
- IN OUT AMD_MID_PARAMS *MidParams
- )
-{
- AGESA_STATUS AgesaStatus;
- AGESA_STATUS CalledStatus;
- IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitMid: Start\n\n");
- AGESA_TESTPOINT (TpIfAmdInitMidEntry, &MidParams->StdHeader);
- IDS_PERF_TIME_MEASURE (&MidParams->StdHeader);
-
- AgesaStatus = AGESA_SUCCESS;
-
- ASSERT (MidParams != NULL);
- IDS_OPTION_HOOK (IDS_INIT_MID_BEFORE, MidParams, &MidParams->StdHeader);
-
- IDS_HDT_CONSOLE (MAIN_FLOW, "DispatchCpuFeatures: MidStart\n");
- CalledStatus = DispatchCpuFeatures (CPU_FEAT_INIT_MID_END, &MidParams->PlatformConfig, &MidParams->StdHeader);
- IDS_HDT_CONSOLE (MAIN_FLOW, "DispatchCpuFeatures: MidEnd\n");
- if (CalledStatus > AgesaStatus) {
- AgesaStatus = CalledStatus;
- }
-
- CalledStatus = GnbInitAtMid (MidParams);
- if (CalledStatus > AgesaStatus) {
- AgesaStatus = CalledStatus;
- }
-
- IDS_OPTION_HOOK (IDS_INIT_MID_AFTER, MidParams, &MidParams->StdHeader);
-
- IDS_PERF_TIME_MEASURE (&MidParams->StdHeader);
- AGESA_TESTPOINT (TpIfAmdInitMidExit, &MidParams->StdHeader);
- IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitMid: End\n\n");
- IDS_HDT_CONSOLE_FLUSH_BUFFER (&MidParams->StdHeader);
- return AgesaStatus;
-}
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Common/AmdInitPost.c b/src/vendorcode/amd/agesa/Proc/Common/AmdInitPost.c
deleted file mode 100644
index c7ab7d4..0000000
--- a/src/vendorcode/amd/agesa/Proc/Common/AmdInitPost.c
+++ /dev/null
@@ -1,339 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD AGESA Basic Level Public APIs
- *
- * Contains basic Level Initialization routines.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Interface
- * @e \$Revision: 37437 $ @e \$Date: 2010-09-04 01:15:21 +0800 (Sat, 04 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "mm.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuServices.h"
-#include "cpuPostInit.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "CommonInits.h"
-#include "cpuServices.h"
-#include "GnbInterface.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_COMMON_AMDINITPOST_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-
-/*------------------------------------------------------------------------------------*/
-/**
- * Initialize AmdInitPost stage platform profile and user option input.
- *
- * @param[in,out] PlatformConfig Platform profile/build option config structure
- * @param[in,out] StdHeader AMD standard header config param
- *
- * @retval AGESA_SUCCESS Always Succeeds.
- *
- */
-AGESA_STATUS
-AmdPostPlatformConfigInit (
- IN OUT PLATFORM_CONFIGURATION *PlatformConfig,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- CommonPlatformConfigInit (PlatformConfig, StdHeader);
-
- return AGESA_SUCCESS;
-}
-
-/*
- *---------------------------------------------------------------------------------------
- *
- * AmdInitPostInitializer
- *
- * Initializer routine that will be invoked by the wrapper
- * to initialize the input structure for the AmdInitPost
- *
- * @param[in, out] IN OUT AMD_POST_PARAMS *PostParamsPtr
- *
- * @retval AGESA_STATUS
- *
- *---------------------------------------------------------------------------------------
- */
-AGESA_STATUS
-AmdInitPostInitializer (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN OUT AMD_POST_PARAMS *PostParamsPtr
- )
-{
- AGESA_STATUS AgesaStatus;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
- ASSERT (StdHeader != NULL);
- ASSERT (PostParamsPtr != NULL);
-
- PostParamsPtr->StdHeader = *StdHeader;
-
- AllocHeapParams.RequestedBufferSize = sizeof (MEM_DATA_STRUCT);
- AllocHeapParams.BufferHandle = AMD_MEM_DATA_HANDLE;
- AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
- AgesaStatus = HeapAllocateBuffer (&AllocHeapParams, &PostParamsPtr->StdHeader);
-
- if (AgesaStatus == AGESA_SUCCESS) {
- PostParamsPtr->MemConfig.MemData = (MEM_DATA_STRUCT *) AllocHeapParams.BufferPtr;
- PostParamsPtr->MemConfig.MemData->ParameterListPtr = &(PostParamsPtr->MemConfig);
- PostParamsPtr->MemConfig.MemData->StdHeader = PostParamsPtr->StdHeader;
- AmdPostPlatformConfigInit (&PostParamsPtr->PlatformConfig, &PostParamsPtr->StdHeader);
- AmdMemInitDataStructDef (PostParamsPtr->MemConfig.MemData, &PostParamsPtr->PlatformConfig);
- }
- return AgesaStatus;
-}
-
-/*
- *---------------------------------------------------------------------------------------
- *
- * AmdInitPostDestructor
- *
- * Destruct routine that provide a chance if something need to be done
- * before the end of AmdInitPost.
- *
- * @param[in] StdHeader The standard header.
- * @param[in] PostParamsPtr AMD init post param.
- *
- * @retval AGESA_STATUS
- *
- *---------------------------------------------------------------------------------------
- */
-AGESA_STATUS
-AmdInitPostDestructor (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN AMD_POST_PARAMS *PostParamsPtr
- )
-{
-
- ASSERT (PostParamsPtr != NULL);
-
- PostParamsPtr->StdHeader = *StdHeader;
- PostParamsPtr->MemConfig.MemData->StdHeader = *StdHeader;
-
- //
- // AmdMemAuto completed. Here, release heap space which is used for memory init.
- //
- MemAmdFinalize (PostParamsPtr->MemConfig.MemData);
- HeapDeallocateBuffer (AMD_MEM_DATA_HANDLE, StdHeader);
-
- //
- // AmdCpuPost completed.
- //
- if (PostParamsPtr->MemConfig.SysLimit != 0) {
- // WBINVD can only be executed when memory is available
- FinalizeAtPost (StdHeader);
- }
-
- return AGESA_SUCCESS;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Main entry point for the AMD_INIT_POST function.
- *
- * This entry point is responsible for initializing all system memory,
- * gathering important data out of the pre-memory cache storage into a
- * temporary holding buffer in main memory. After that APs will be
- * shutdown in preparation for the host environment to take control.
- * Note: pre-memory stack will be disabled also.
- *
- * @param[in,out] PostParams Required input parameters for the AMD_INIT_POST
- * entry point.
- *
- * @return Aggregated status across all internal AMD POST calls invoked.
- *
- */
-AGESA_STATUS
-AmdInitPost (
- IN OUT AMD_POST_PARAMS *PostParams
- )
-{
- AGESA_STATUS AgesaStatus;
- AGESA_STATUS AmdInitPostStatus;
- WARM_RESET_REQUEST Request;
- UINT8 PrevRequestBit;
- UINT8 PrevStateBits;
-
- AGESA_TESTPOINT (TpIfAmdInitPostEntry, &PostParams->StdHeader);
- IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitPost: Start\n\n");
- IDS_PERF_TIME_MEASURE (&PostParams->StdHeader);
-
- ASSERT (PostParams != NULL);
- AmdInitPostStatus = AGESA_SUCCESS;
- PrevRequestBit = FALSE;
- PrevStateBits = WR_STATE_COLD;
-
- IDS_OPTION_HOOK (IDS_INIT_POST_BEFORE, PostParams, &PostParams->StdHeader);
-
- IDS_OPTION_HOOK (IDS_BEFORE_MEM_INIT, PostParams, &PostParams->StdHeader);
-
- // If a previously requested warm reset cannot be triggered in the
- // current stage, store the previous state of request and reset the
- // request struct to the current post stage
- GetWarmResetFlag (&PostParams->StdHeader, &Request);
- if (Request.RequestBit == TRUE) {
- if (Request.StateBits >= Request.PostStage) {
- PrevRequestBit = Request.RequestBit;
- PrevStateBits = Request.StateBits;
- Request.RequestBit = FALSE;
- Request.StateBits = Request.PostStage - 1;
- SetWarmResetFlag (&PostParams->StdHeader, &Request);
- }
- }
-
- AgesaStatus = GnbInitAtPost (PostParams);
- if (AgesaStatus > AmdInitPostStatus) {
- AmdInitPostStatus = AgesaStatus;
- }
-
- IDS_HDT_CONSOLE (MAIN_FLOW, "AmdMemAuto: Start\n");
- AgesaStatus = AmdMemAuto (PostParams->MemConfig.MemData);
- IDS_HDT_CONSOLE (MAIN_FLOW, "AmdMemAuto: End\n");
- if (AgesaStatus > AmdInitPostStatus) {
- AmdInitPostStatus = AgesaStatus;
- }
-
- if (AgesaStatus != AGESA_FATAL) {
-
- IDS_OPTION_HOOK (IDS_INIT_POST_MID, PostParams, &PostParams->StdHeader);
-
- // Check BIST status
- AgesaStatus = CheckBistStatus (&PostParams->StdHeader);
- if (AgesaStatus > AmdInitPostStatus) {
- AmdInitPostStatus = AgesaStatus;
- }
-
- //
- // P-State data gathered, then, Relinquish APs
- //
- IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuPost: Start\n");
- AgesaStatus = AmdCpuPost (&PostParams->StdHeader, &PostParams->PlatformConfig);
- IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuPost: End\n");
- if (AgesaStatus > AmdInitPostStatus) {
- AmdInitPostStatus = AgesaStatus;
- }
-
- // Warm Reset
- GetWarmResetFlag (&PostParams->StdHeader, &Request);
- // If a warm reset is requested in the current post stage, trigger the
- // warm reset and ignore the previous request
- if (Request.RequestBit == TRUE) {
- if (Request.StateBits < Request.PostStage) {
- AgesaDoReset (WARM_RESET_WHENEVER, &PostParams->StdHeader);
- }
- } else {
- // Otherwise, if there's a previous request, restore it
- // so that the subsequent post stage can trigger the warm reset
- if (PrevRequestBit == TRUE) {
- Request.RequestBit = PrevRequestBit;
- Request.StateBits = PrevStateBits;
- SetWarmResetFlag (&PostParams->StdHeader, &Request);
- }
- }
-
- AgesaStatus = GnbInitAtPostAfterDram (PostParams);
- if (AgesaStatus > AmdInitPostStatus) {
- AmdInitPostStatus = AgesaStatus;
- }
-
- IDS_OPTION_HOOK (IDS_INIT_POST_AFTER, PostParams, &PostParams->StdHeader);
-
- IDS_PERF_TIME_MEASURE (&PostParams->StdHeader);
- AGESA_TESTPOINT (TpIfAmdInitPostExit, &PostParams->StdHeader);
- IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitPost: End\n\n");
- IDS_HDT_CONSOLE (MAIN_FLOW, "Heap transfer Start ...\n\n");
-
- //For Heap will be relocate to new address in next stage, flush out debug print buffer if needed
- IDS_HDT_CONSOLE_FLUSH_BUFFER (&PostParams->StdHeader);
-
- // Copies BSP heap content to RAM, and it should be at the end of AmdInitPost
- AgesaStatus = CopyHeapToTempRamAtPost (&(PostParams->StdHeader));
- if (AgesaStatus > AmdInitPostStatus) {
- AmdInitPostStatus = AgesaStatus;
- }
- PostParams->StdHeader.HeapStatus = HEAP_TEMP_MEM;
- }
- // Check for Cache As Ram Corruption
- IDS_CAR_CORRUPTION_CHECK (&PostParams->StdHeader);
-
- // At the end of AmdInitPost, set StateBits to POST to allow any warm reset that occurs outside
- // of AGESA to be recognized by IsWarmReset()
- GetWarmResetFlag (&PostParams->StdHeader, &Request);
- Request.StateBits = Request.PostStage;
- SetWarmResetFlag (&PostParams->StdHeader, &Request);
-
- return AmdInitPostStatus;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/Common/AmdInitRecovery.c b/src/vendorcode/amd/agesa/Proc/Common/AmdInitRecovery.c
deleted file mode 100644
index efa2671..0000000
--- a/src/vendorcode/amd/agesa/Proc/Common/AmdInitRecovery.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD AGESA Basic Level Public APIs
- *
- * Contains basic Level Initialization routines.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Common
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "AdvancedApi.h"
-#include "heapManager.h"
-#include "mm.h"
-#include "GnbInterface.h"
-#include "cpuRecovery.h"
-#include "cpuCacheInit.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_COMMON_AMDINITRECOVERY_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Perform initialization services required at the Early Init POST time point.
- *
- * Execution Cache, HyperTransport, C1e, and AP Init advanced services are performed.
- *
- * @param[in, out] RecoveryParams The interface struct for Recovery services
- *
- * @return The most severe AGESA_STATUS returned by any called service.
- *
- */
-AGESA_STATUS
-AmdInitRecovery (
- IN OUT AMD_RECOVERY_PARAMS *RecoveryParams
- )
-{
- AGESA_STATUS AgesaStatus;
- AGESA_STATUS CalledAgesaStatus;
-
- AGESA_TESTPOINT (TpIfAmdInitRecoveryEntry, &RecoveryParams->StdHeader);
-
- ASSERT (RecoveryParams != NULL);
-
- AgesaStatus = AGESA_SUCCESS;
-
- // Setup ROM execution cache
- CalledAgesaStatus = AllocateExecutionCache (&RecoveryParams->StdHeader, &RecoveryParams->CacheRegion[0]);
- if (CalledAgesaStatus > AgesaStatus) {
- AgesaStatus = CalledAgesaStatus;
- }
-
- CalledAgesaStatus = AmdHtInitRecovery (&RecoveryParams->StdHeader);
- if (CalledAgesaStatus > AgesaStatus) {
- AgesaStatus = CalledAgesaStatus;
- }
-
- CalledAgesaStatus = AmdCpuRecovery ((AMD_CPU_RECOVERY_PARAMS *) &RecoveryParams->StdHeader);
- if (CalledAgesaStatus > AgesaStatus) {
- AgesaStatus = CalledAgesaStatus;
- }
-
- CalledAgesaStatus = AmdMemRecovery (RecoveryParams->MemConfig.MemData);
- if (CalledAgesaStatus > AgesaStatus) {
- AgesaStatus = CalledAgesaStatus;
- }
-
- CalledAgesaStatus = AmdGnbRecovery (&RecoveryParams->StdHeader);
- if (CalledAgesaStatus > AgesaStatus) {
- AgesaStatus = CalledAgesaStatus;
- }
-
- AGESA_TESTPOINT (TpIfAmdInitRecoveryExit, &RecoveryParams->StdHeader);
- return AgesaStatus;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * Initialize defaults and options for Amd Init Reset.
- *
- * @param[in] StdHeader AMD standard header config param.
- * @param[in] AmdRecoveryParamsPtr The Reset Init interface to initialize.
- *
- * @retval AGESA_SUCCESS Always Succeeds.
- */
-AGESA_STATUS
-AmdInitRecoveryInitializer (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN OUT AMD_RECOVERY_PARAMS *AmdRecoveryParamsPtr
- )
-{
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
- ASSERT (StdHeader != NULL);
- ASSERT (AmdRecoveryParamsPtr != NULL);
-
- AmdRecoveryParamsPtr->StdHeader = *StdHeader;
-
- AllocHeapParams.RequestedBufferSize = sizeof (MEM_DATA_STRUCT);
- AllocHeapParams.BufferHandle = AMD_MEM_DATA_HANDLE;
- AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
- if (HeapAllocateBuffer (&AllocHeapParams, &AmdRecoveryParamsPtr->StdHeader) == AGESA_SUCCESS) {
- AmdRecoveryParamsPtr->MemConfig.MemData = (MEM_DATA_STRUCT *) AllocHeapParams.BufferPtr;
- AmdRecoveryParamsPtr->MemConfig.MemData->ParameterListPtr = &(AmdRecoveryParamsPtr->MemConfig);
- LibAmdMemCopy ((VOID *) AmdRecoveryParamsPtr->MemConfig.MemData,
- (VOID *) AmdRecoveryParamsPtr,
- (UINTN) sizeof (AmdRecoveryParamsPtr->StdHeader),
- &AmdRecoveryParamsPtr->StdHeader
- );
- AmdMemInitDataStructDefRecovery (AmdRecoveryParamsPtr->MemConfig.MemData);
- return AGESA_SUCCESS;
- } else {
- return AGESA_ERROR;
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Common/AmdInitReset.c b/src/vendorcode/amd/agesa/Proc/Common/AmdInitReset.c
deleted file mode 100644
index 2a7b99e..0000000
--- a/src/vendorcode/amd/agesa/Proc/Common/AmdInitReset.c
+++ /dev/null
@@ -1,245 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD AGESA Basic Level Public APIs
- *
- * Contains basic Level Initialization routines.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Interface
- * @e \$Revision: 36908 $ @e \$Date: 2010-08-27 09:19:54 +0800 (Fri, 27 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuCacheInit.h"
-#include "cpuServices.h"
-#include "AdvancedApi.h"
-#include "GeneralServices.h"
-#include "OptionsHt.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_COMMON_AMDINITRESET_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-extern CONST OPTION_HT_INIT_RESET HtOptionInitReset;
-extern BUILD_OPT_CFG UserOptions;
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*------------------------------------------------------------------------------------*/
-/**
- * Initializer routine that will be invoked by the wrapper to initialize the input
- * structure for the AllocateExecutionCache.
- *
- * Parameters:
- * @param[in] StdHeader Opaque handle to standard config header
- * @param[in] AmdExeAddrMapPtr Our Service interface struct
- *
- * @retval AGESA_SUCCESS Always Succeeds.
- *
- */
-AGESA_STATUS
-AmdInitResetExecutionCacheAllocateInitializer (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr
- )
-{
- ASSERT (AmdExeAddrMapPtr != NULL);
-
- LibAmdMemFill (AmdExeAddrMapPtr, 0, sizeof (EXECUTION_CACHE_REGION) * MAX_CACHE_REGIONS, StdHeader);
-
- return AGESA_SUCCESS;
-}
-/*---------------------------------------------------------------------------------------*/
-/**
- * Main entry point for the AMD_INIT_RESET function.
- *
- * This entry point is responsible for establishing the HT links to the program
- * ROM and for performing basic processor initialization.
- *
- * @param[in,out] ResetParams Required input parameters for the AMD_INIT_RESET
- * entry point.
- *
- * @return Aggregated status across all internal AMD reset calls invoked.
- *
- */
-AGESA_STATUS
-AmdInitReset (
- IN OUT AMD_RESET_PARAMS *ResetParams
- )
-{
- AGESA_STATUS AgesaStatus;
- AGESA_STATUS CalledAgesaStatus;
- WARM_RESET_REQUEST Request;
- UINT8 PrevRequestBit;
- UINT8 PrevStateBits;
-
- // Init Debug Print function
- IDS_HDT_CONSOLE_INIT (&ResetParams->StdHeader);
- IDS_HDT_CONSOLE (MAIN_FLOW, "\n*** %s ***\n\n", &UserOptions.VersionString);
-
- IDS_HDT_CONSOLE_DEBUG_CODE (
- {
- extern CHAR8 *BldOptDebugOutput[];
-
- UINT8 i;
- for (i = 0; BldOptDebugOutput[i] != NULL; i++) {
- IDS_HDT_CONSOLE (MAIN_FLOW, "\t%s\n", BldOptDebugOutput[i]);
- }
- }
- )
-
- IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitReset: Start\n\n");
-
- AGESA_TESTPOINT (TpIfAmdInitResetEntry, &ResetParams->StdHeader);
- ASSERT (ResetParams != NULL);
-
- AgesaStatus = AGESA_SUCCESS;
- PrevRequestBit = FALSE;
- PrevStateBits = WR_STATE_COLD;
-
- // If a previously requested warm reset cannot be triggered in the
- // current stage, store the previous state of request and reset the
- // request struct to the current post stage
- GetWarmResetFlag (&ResetParams->StdHeader, &Request);
- if (Request.RequestBit == TRUE) {
- if (Request.StateBits >= Request.PostStage) {
- PrevRequestBit = Request.RequestBit;
- PrevStateBits = Request.StateBits;
- Request.RequestBit = FALSE;
- Request.StateBits = Request.PostStage - 1;
- SetWarmResetFlag (&ResetParams->StdHeader, &Request);
- }
- }
-
- IDS_HDT_CONSOLE (MAIN_FLOW, "AllocateExecutionCache: Start\n");
- // Setup ROM execution cache
- CalledAgesaStatus = AllocateExecutionCache (&ResetParams->StdHeader, &ResetParams->CacheRegion[0]);
- IDS_HDT_CONSOLE (MAIN_FLOW, "AllocateExecutionCache: End\n");
- if (CalledAgesaStatus > AgesaStatus) {
- AgesaStatus = CalledAgesaStatus;
- }
-
- // Initialize the PCI MMIO access mechanism
- InitializePciMmio (&ResetParams->StdHeader);
-
- // Initialize Hyper Transport Registers
- if (HtOptionInitReset.HtInitReset != NULL) {
- IDS_HDT_CONSOLE (MAIN_FLOW, "HtInitReset: Start\n");
- CalledAgesaStatus = HtOptionInitReset.HtInitReset (&ResetParams->StdHeader, &ResetParams->HtConfig);
- IDS_HDT_CONSOLE (MAIN_FLOW, "HtInitReset: End\n");
- if (CalledAgesaStatus > AgesaStatus) {
- AgesaStatus = CalledAgesaStatus;
- }
- }
-
- // Warm Reset, should be at the end of AmdInitReset
- GetWarmResetFlag (&ResetParams->StdHeader, &Request);
- // If a warm reset is requested in the current post stage, trigger the
- // warm reset and ignore the previous request
- if (Request.RequestBit == TRUE) {
- if (Request.StateBits < Request.PostStage) {
- AgesaDoReset (WARM_RESET_WHENEVER, &ResetParams->StdHeader);
- }
- } else {
- // Otherwise, if there's a previous request, restore it
- // so that the subsequent post stage can trigger the warm reset
- if (PrevRequestBit == TRUE) {
- Request.RequestBit = PrevRequestBit;
- Request.StateBits = PrevStateBits;
- SetWarmResetFlag (&ResetParams->StdHeader, &Request);
- }
- }
- // Check for Cache As Ram Corruption
- IDS_CAR_CORRUPTION_CHECK (&ResetParams->StdHeader);
- IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitReset: End\n\n");
-
- AGESA_TESTPOINT (TpIfAmdInitResetExit, &ResetParams->StdHeader);
- return AgesaStatus;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Initialize defaults and options for Amd Init Reset.
- *
- * @param[in] StdHeader Header
- * @param[in] AmdResetParams The Reset Init interface to initialize.
- *
- * @retval AGESA_SUCCESS Always Succeeds.
- */
-AGESA_STATUS
-AmdInitResetConstructor (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN AMD_RESET_PARAMS *AmdResetParams
- )
-{
- ASSERT (AmdResetParams != NULL);
-
- AmdResetParams->StdHeader = *StdHeader;
-
- AmdInitResetExecutionCacheAllocateInitializer (&AmdResetParams->StdHeader, &AmdResetParams->CacheRegion[0]);
- AmdHtResetConstructor (&AmdResetParams->StdHeader, &AmdResetParams->HtConfig);
-
- return AGESA_SUCCESS;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/Common/AmdInitResume.c b/src/vendorcode/amd/agesa/Proc/Common/AmdInitResume.c
deleted file mode 100644
index b199fba..0000000
--- a/src/vendorcode/amd/agesa/Proc/Common/AmdInitResume.c
+++ /dev/null
@@ -1,233 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD AGESA Basic Level Public APIs
- *
- * Contains basic Level Initialization routines.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Interface
- * @e \$Revision: 38446 $ @e \$Date: 2010-09-24 06:51:03 +0800 (Fri, 24 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "S3.h"
-#include "mfs3.h"
-#include "Filecode.h"
-#include "cpuRegisters.h"
-#include "cpuApicUtilities.h"
-#include "cpuPostInit.h"
-#include "CommonInits.h"
-#include "cpuFeatures.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_COMMON_AMDINITRESUME_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Main entry point for the AMD_INIT_RESUME function.
- *
- * This entry point is responsible for performing silicon device and memory
- * re-initialization for the resume boot path.
- *
- * @param[in] ResumeParams Required input parameters for the AMD_INIT_RESUME
- * entry point.
- *
- * @return Aggregated status across all internal AMD resume calls invoked.
- *
- */
-AGESA_STATUS
-AmdInitResume (
- IN AMD_RESUME_PARAMS *ResumeParams
- )
-{
- VOID *OrMaskPtr;
- AGESA_STATUS ReturnStatus;
- AGESA_STATUS AmdInitResumeStatus;
- BSC_AP_MSR_SYNC ApMsrSync[4];
-
- AGESA_TESTPOINT (TpIfAmdInitResumeEntry, &ResumeParams->StdHeader);
-
- AmdInitResumeStatus = AGESA_SUCCESS;
-
- ASSERT (ResumeParams != NULL);
-
- if (ResumeParams->S3DataBlock.NvStorage != NULL) {
-
- MemS3ResumeInitNB (&ResumeParams->StdHeader);
-
- // Restore registers before exiting self refresh
- RestorePreESRContext (&OrMaskPtr,
- ResumeParams->S3DataBlock.NvStorage,
- INIT_RESUME,
- &ResumeParams->StdHeader);
- // Exit self refresh
- ReturnStatus = AmdMemS3Resume (&ResumeParams->StdHeader);
- if (ReturnStatus > AmdInitResumeStatus) {
- AmdInitResumeStatus = ReturnStatus;
- }
- if (ReturnStatus == AGESA_SUCCESS) {
-
- // Restore registers after exiting self refresh
- RestorePostESRContext (OrMaskPtr,
- ResumeParams->S3DataBlock.NvStorage,
- INIT_RESUME,
- &ResumeParams->StdHeader);
-
- ApMsrSync[0].RegisterAddress = SYS_CFG;
- ApMsrSync[1].RegisterAddress = TOP_MEM;
- ApMsrSync[2].RegisterAddress = TOP_MEM2;
- ApMsrSync[3].RegisterAddress = 0;
- SyncApMsrsToBsc (ApMsrSync, &ResumeParams->StdHeader);
-
- IDS_HDT_CONSOLE (CPU_TRACE, " Dispatch CPU features after S3 AP MTRR sync\n");
- ReturnStatus = DispatchCpuFeatures (CPU_FEAT_AFTER_RESUME_MTRR_SYNC, &ResumeParams->PlatformConfig, &ResumeParams->StdHeader);
- if (ReturnStatus > AmdInitResumeStatus) {
- AmdInitResumeStatus = ReturnStatus;
- }
- }
- }
-
- // Set TscFreqSel at the rate specified by the core P0
- SetCoresTscFreqSel (&ResumeParams->StdHeader);
- // HDT out of All Aps
- IDS_HDT_CONSOLE_S3_AP_EXIT (&ResumeParams->StdHeader);
- // Relinquish control of all APs to IBV
- RelinquishControlOfAllAPs (&ResumeParams->StdHeader);
-
- AGESA_TESTPOINT (TpIfAmdInitResumeExit, &ResumeParams->StdHeader);
- return (AmdInitResumeStatus);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Constructor for the AMD_INIT_RESUME function.
- *
- * This routine is responsible for setting default values for the
- * input parameters needed by the AMD_INIT_RESUME entry point.
- *
- * @param[in] StdHeader The standard header.
- * @param[in,out] ResumeParams Required input parameters for the AMD_INIT_RESUME
- * entry point.
- *
- * @retval AGESA_SUCCESS Always Succeeds.
- *
- */
-AGESA_STATUS
-AmdInitResumeInitializer (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN OUT AMD_RESUME_PARAMS *ResumeParams
- )
-{
- ASSERT (StdHeader != NULL);
- ASSERT (ResumeParams != NULL);
-
- ResumeParams->StdHeader = *StdHeader;
-
- AmdS3ParamsInitializer (&ResumeParams->S3DataBlock);
- CommonPlatformConfigInit (&ResumeParams->PlatformConfig, &ResumeParams->StdHeader);
-
- return AGESA_SUCCESS;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Destructor for the AMD_INIT_RESUME function.
- *
- * This routine is responsible for deallocation of heap space allocated during
- * AMD_INIT_RESUME entry point.
- *
- * @param[in] StdHeader The standard header.
- * @param[in,out] ResumeParams Required input parameters for the AMD_INIT_RESUME
- * entry point.
- *
- * @retval AGESA_STATUS
- *
- */
-AGESA_STATUS
-AmdInitResumeDestructor (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN OUT AMD_RESUME_PARAMS *ResumeParams
- )
-{
- AGESA_STATUS ReturnStatus;
- AGESA_STATUS RetVal;
-
- ASSERT (ResumeParams != NULL);
-
- ReturnStatus = AGESA_SUCCESS;
-
- // Deallocate heap space allocated during memory S3 resume
- RetVal = MemS3Deallocate (&ResumeParams->StdHeader);
- if (RetVal > ReturnStatus) {
- ReturnStatus = RetVal;
- }
-
- return ReturnStatus;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Common/AmdLateRunApTask.c b/src/vendorcode/amd/agesa/Proc/Common/AmdLateRunApTask.c
deleted file mode 100644
index 74aebbc..0000000
--- a/src/vendorcode/amd/agesa/Proc/Common/AmdLateRunApTask.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD AGESA Basic Level Public APIs
- *
- * Contains basic Level Initialization routines.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Interface
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "Options.h"
-#include "Filecode.h"
-CODE_GROUP (G3_DXE)
-RDATA_GROUP (G3_DXE)
-
-#define FILECODE PROC_COMMON_AMDLATERUNAPTASK_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-extern CONST DISPATCH_TABLE ApDispatchTable[];
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Application Processor perform a function as directed by the BSC.
- *
- * This is needed for an AP task that must run after AGESA has relinquished control
- * of the APs to the IBV.
- *
- * @param[in] AmdApExeParams The interface struct for any required routine.
- *
- * @return The most severe AGESA_STATUS returned by any called service. Note
- * that this will be the return value passed back to the BSC as the
- * return value for the call out.
- *
- */
-AGESA_STATUS
-AmdLateRunApTask (
- IN AP_EXE_PARAMS *AmdApExeParams
- )
-{
- AGESA_STATUS CalledAgesaStatus;
- AGESA_STATUS ApLateTaskStatus;
- DISPATCH_TABLE *Entry;
-
- AGESA_TESTPOINT (TpIfAmdLateRunApTaskEntry, &AmdApExeParams->StdHeader);
-
- ASSERT (AmdApExeParams != NULL);
- ApLateTaskStatus = AGESA_SUCCESS;
- CalledAgesaStatus = AGESA_UNSUPPORTED;
-
- // Dispatch, if valid
- Entry = (DISPATCH_TABLE *) ApDispatchTable;
- while (Entry->FunctionId != 0) {
- if (AmdApExeParams->FunctionNumber == Entry->FunctionId) {
- CalledAgesaStatus = Entry->EntryPoint (AmdApExeParams);
- break;
- }
- Entry++;
- }
-
- if (CalledAgesaStatus > ApLateTaskStatus) {
- ApLateTaskStatus = CalledAgesaStatus;
- }
-
- AGESA_TESTPOINT (TpIfAmdLateRunApTaskExit, &AmdApExeParams->StdHeader);
- return ApLateTaskStatus;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Constructor for the AMD_LATE_RUN_AP_TASK function.
- *
- * This routine is responsible for setting default values for the
- * input parameters needed by the AMD_S3_SAVE entry point.
- *
- * @param[in] StdHeader The standard header.
- * @param[in,out] AmdApExeParams Required input parameters for the AMD_LATE_RUN_AP_TASK
- * entry point.
- *
- * @retval AGESA_SUCCESS Always Succeeds.
- *
- */
-AGESA_STATUS
-AmdLateRunApTaskInitializer (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN OUT AP_EXE_PARAMS *AmdApExeParams
- )
-{
- ASSERT (StdHeader != NULL);
- ASSERT (AmdApExeParams != NULL);
-
- AmdApExeParams->StdHeader = *StdHeader;
- AmdApExeParams->FunctionNumber = 0;
- AmdApExeParams->RelatedDataBlock = NULL;
- AmdApExeParams->RelatedBlockLength = 0;
- return AGESA_SUCCESS;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/Common/AmdS3LateRestore.c b/src/vendorcode/amd/agesa/Proc/Common/AmdS3LateRestore.c
deleted file mode 100644
index b38bb67..0000000
--- a/src/vendorcode/amd/agesa/Proc/Common/AmdS3LateRestore.c
+++ /dev/null
@@ -1,215 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD AGESA Basic Level Public APIs
- *
- * Contains basic Level Initialization routines.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Interface
- * @e \$Revision: 38446 $ @e \$Date: 2010-09-24 06:51:03 +0800 (Fri, 24 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "S3.h"
-#include "cpuFeatures.h"
-#include "S3SaveState.h"
-#include "CommonInits.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_COMMON_AMDS3LATERESTORE_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-AGESA_STATUS
-AmdS3LateRestorePlatformConfigInit (
- IN OUT PLATFORM_CONFIGURATION *PlatformConfig,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-extern BUILD_OPT_CFG UserOptions;
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Main entry point for the AMD_S3LATE_RESTORE function.
- *
- * This entry point is responsible for restoring saved registers and preparing the
- * silicon components for OS restart.
- *
- * @param[in,out] S3LateParams Required input parameters for the AMD_S3LATE_RESTORE
- * entry point.
- *
- * @return Aggregated status across all internal AMD S3 late restore calls invoked.
- *
- */
-AGESA_STATUS
-AmdS3LateRestore (
- IN OUT AMD_S3LATE_PARAMS *S3LateParams
- )
-{
- UINT8 *BufferPointer;
- VOID *OrMaskPtr;
- VOID *LateContextPtr;
- AGESA_STATUS ReturnStatus;
- AGESA_STATUS CalledStatus;
-
- AGESA_TESTPOINT (TpIfAmdS3LateRestoreEntry, &S3LateParams->StdHeader);
- IDS_HDT_CONSOLE (MAIN_FLOW, "AmdS3LateRestore: Start\n\n");
- ReturnStatus = AGESA_SUCCESS;
-
- ASSERT (S3LateParams != NULL);
-
- BufferPointer = (UINT8 *) S3LateParams->S3DataBlock.VolatileStorage;
- S3LateParams->StdHeader.HeapBasePtr = (UINT64) &BufferPointer[((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->HeapOffset];
- ASSERT (S3LateParams->StdHeader.HeapBasePtr != NULL);
-
- IDS_OPTION_HOOK (IDS_PLATFORMCFG_OVERRIDE, &S3LateParams->PlatformConfig, &S3LateParams->StdHeader);
- IDS_OPTION_HOOK (IDS_BEFORE_S3_RESTORE, S3LateParams, &(S3LateParams->StdHeader));
-
- if (((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->RegisterDataSize != 0) {
- LateContextPtr = &BufferPointer[((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->RegisterDataOffset];
- // Restore registers before exiting self refresh
- RestorePreESRContext (&OrMaskPtr,
- LateContextPtr,
- S3_LATE_RESTORE,
- &S3LateParams->StdHeader);
- // Restore registers after exiting self refresh
- RestorePostESRContext (OrMaskPtr,
- LateContextPtr,
- S3_LATE_RESTORE,
- &S3LateParams->StdHeader);
- }
-
- // Dispatch any features needing to run at this time point
- IDS_HDT_CONSOLE (CPU_TRACE, " Dispatch CPU features at S3 late restore end\n");
- CalledStatus = DispatchCpuFeatures (CPU_FEAT_S3_LATE_RESTORE_END,
- &S3LateParams->PlatformConfig,
- &S3LateParams->StdHeader);
- if (CalledStatus > ReturnStatus) {
- ReturnStatus = CalledStatus;
- }
-
- CalledStatus = S3ScriptRestore (&S3LateParams->StdHeader);
- if (CalledStatus > ReturnStatus) {
- ReturnStatus = CalledStatus;
- }
-
- IDS_OPTION_HOOK (IDS_AFTER_S3_RESTORE, S3LateParams, &S3LateParams->StdHeader);
- AGESA_TESTPOINT (TpIfAmdS3LateRestoreExit, &S3LateParams->StdHeader);
- IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdS3LateRestore: End\n\n");
- IDS_HDT_CONSOLE_S3_EXIT (&S3LateParams->StdHeader);
- return ReturnStatus;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Constructor for the AMD_S3LATE_RESTORE function.
- *
- * This routine is responsible for setting default values for the
- * input parameters needed by the AMD_S3LATE_RESTORE entry point.
- *
- * @param[in] StdHeader AMD standard header config param.
- * @param[in,out] S3LateParams Required input parameters for the
- * AMD_S3LATE_RESTORE entry point.
- *
- * @retval AGESA_SUCCESS Always Succeeds.
- *
- */
-AGESA_STATUS
-AmdS3LateRestoreInitializer (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN OUT AMD_S3LATE_PARAMS *S3LateParams
- )
-{
- ASSERT (StdHeader != NULL);
- ASSERT (S3LateParams != NULL);
-
- S3LateParams->StdHeader = *StdHeader;
-
- AmdS3ParamsInitializer (&S3LateParams->S3DataBlock);
-
- AmdS3LateRestorePlatformConfigInit (&S3LateParams->PlatformConfig, &S3LateParams->StdHeader);
-
- return AGESA_SUCCESS;
-}
-
-/*------------------------------------------------------------------------------------*/
-/**
- * Initialize AmdS3Save stage platform profile and user option input.
- *
- * @param[in,out] PlatformConfig Platform profile/build option config structure
- * @param[in,out] StdHeader AMD standard header config param
- *
- * @retval AGESA_SUCCESS Always Succeeds.
- *
- */
-AGESA_STATUS
-AmdS3LateRestorePlatformConfigInit (
- IN OUT PLATFORM_CONFIGURATION *PlatformConfig,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- CommonPlatformConfigInit (PlatformConfig, StdHeader);
-
- return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Common/AmdS3Save.c b/src/vendorcode/amd/agesa/Proc/Common/AmdS3Save.c
deleted file mode 100644
index 147487b..0000000
--- a/src/vendorcode/amd/agesa/Proc/Common/AmdS3Save.c
+++ /dev/null
@@ -1,381 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD AGESA Basic Level Public APIs
- *
- * Contains basic Level Initialization routines.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Interface
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "S3.h"
-#include "mfs3.h"
-#include "CommonInits.h"
-#include "Filecode.h"
-#include "heapManager.h"
-#include "Topology.h"
-CODE_GROUP (G3_DXE)
-RDATA_GROUP (G3_DXE)
-
-#define FILECODE PROC_COMMON_AMDS3SAVE_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-CONST UINT32 ROMDATA S3LateHeapTable[] =
-{
- EVENT_LOG_BUFFER_HANDLE,
- SOCKET_DIE_MAP_HANDLE,
- NODE_ID_MAP_HANDLE,
- LOCAL_AP_MAIL_BOX_CACHE_HANDLE,
- IDS_CONTROL_HANDLE,
- AMD_S3_SCRIPT_SAVE_TABLE_HANDLE,
- AMD_PCIE_COMPLEX_DATA_HANDLE
-};
-
-#define S3LATE_TABLE_SIZE (sizeof (S3LateHeapTable) / sizeof (UINT32)) //(sizeof (S3LateHeapTable) / sizeof (S3LATE_HEAP_ELEMENT))
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-AGESA_STATUS
-AmdS3SavePlatformConfigInit (
- IN OUT PLATFORM_CONFIGURATION *PlatformConfig,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-extern BUILD_OPT_CFG UserOptions;
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Main entry point for the AMD_S3_SAVE function.
- *
- * This entry point is responsible for saving silicon component registers to the
- * SMM save area in preparation of entering system suspend-to-RAM mode.
- *
- * @param[in,out] AmdS3SaveParams Required input parameters for the AMD_S3_SAVE
- * entry point.
- *
- * @return Aggregated status across all internal AMD S3 save calls invoked.
- *
- */
-AGESA_STATUS
-AmdS3Save (
- IN OUT AMD_S3SAVE_PARAMS *AmdS3SaveParams
- )
-{
- UINTN i;
- UINT32 EarlyBufferSize;
- UINT32 LateBufferSize;
- UINT32 LateContextSize;
- UINT32 HeapSize;
- UINT8 *BufferPointer;
- UINT8 HeapStatus;
- ALLOCATE_HEAP_PARAMS HeapParams;
- LOCATE_HEAP_PTR LocateHeap;
- BUFFER_NODE *FreeSpaceNode;
- ALLOCATE_HEAP_PARAMS AllocParams;
- DEVICE_BLOCK_HEADER *MemoryRelatedDeviceList;
- DEVICE_BLOCK_HEADER *NonMemoryRelatedDeviceList;
- AGESA_STATUS ReturnStatus;
- VOID *HeapPtrs[S3LATE_TABLE_SIZE];
- UINT32 HeapSizes[S3LATE_TABLE_SIZE];
- UINT32 HeapBuffersPresent;
- HEAP_MANAGER *HeapPtr;
-
- AGESA_TESTPOINT (TpIfAmdS3SaveEntry, &AmdS3SaveParams->StdHeader);
-
- ASSERT (AmdS3SaveParams != NULL);
-
- HeapBuffersPresent = 0;
- EarlyBufferSize = 0;
- LateBufferSize = 0;
- LateContextSize = 0;
- HeapSize = 0;
- NonMemoryRelatedDeviceList = NULL;
- MemoryRelatedDeviceList = NULL;
- ReturnStatus = AGESA_SUCCESS;
-
- IDS_SKIP_HOOK (IDS_BEFORE_S3_SAVE, AmdS3SaveParams, &(AmdS3SaveParams->StdHeader)) {
-
- // Get memory device list
- MemFS3GetDeviceList (&MemoryRelatedDeviceList, &AmdS3SaveParams->StdHeader);
- if (MemoryRelatedDeviceList != NULL) {
- // Determine size needed
- EarlyBufferSize = GetWorstCaseContextSize (MemoryRelatedDeviceList, INIT_RESUME, &AmdS3SaveParams->StdHeader);
- }
-
- if (UserOptions.CfgS3LateRestore) {
- for (i = 0; i < S3LATE_TABLE_SIZE; i++) {
- LocateHeap.BufferHandle = S3LateHeapTable[i];
- if (HeapLocateBuffer (&LocateHeap, &AmdS3SaveParams->StdHeader) == AGESA_SUCCESS) {
- HeapBuffersPresent++;
- HeapSize += LocateHeap.BufferSize;
- HeapPtrs[i] = LocateHeap.BufferPtr;
- HeapSizes[i] = LocateHeap.BufferSize;
- } else {
- HeapPtrs[i] = NULL;
- HeapSizes[i] = 0;
- }
- }
-
- // Determine heap data size requirements
- if (HeapBuffersPresent != 0) {
- HeapSize += ((sizeof (HEAP_MANAGER)) + (HeapBuffersPresent * ((sizeof (BUFFER_NODE)) + (NUM_OF_SENTINEL * SIZE_OF_SENTINEL) + 0xF))); // reserve 0xF per buffer node for 16 byte alignment
- }
-
- // Get non memory device list
- GetNonMemoryRelatedDeviceList (&NonMemoryRelatedDeviceList, &AmdS3SaveParams->StdHeader);
-
- if (NonMemoryRelatedDeviceList != NULL) {
- // Determine size needed
- LateContextSize = GetWorstCaseContextSize (NonMemoryRelatedDeviceList, S3_LATE_RESTORE, &AmdS3SaveParams->StdHeader);
- }
- LateBufferSize = HeapSize + LateContextSize;
- if (LateBufferSize != 0) {
- LateBufferSize += sizeof (S3_VOLATILE_STORAGE_HEADER);
- }
- }
-
- if ((EarlyBufferSize != 0) || (LateBufferSize != 0)) {
- //
- // Allocate a buffer
- //
- AllocParams.RequestedBufferSize = EarlyBufferSize + LateBufferSize;
- AllocParams.BufferHandle = AMD_S3_INFO_BUFFER_HANDLE;
-
- AGESA_TESTPOINT (TpIfBeforeAllocateS3SaveBuffer, &AmdS3SaveParams->StdHeader);
- if (HeapAllocateBuffer (&AllocParams, &AmdS3SaveParams->StdHeader) != AGESA_SUCCESS) {
- if (AGESA_ERROR > ReturnStatus) {
- ReturnStatus = AGESA_ERROR;
- }
- }
- AGESA_TESTPOINT (TpIfAfterAllocateS3SaveBuffer, &AmdS3SaveParams->StdHeader);
-
- if (EarlyBufferSize != 0) {
- AmdS3SaveParams->S3DataBlock.NvStorage = AllocParams.BufferPtr;
- SaveDeviceListContext (MemoryRelatedDeviceList,
- AmdS3SaveParams->S3DataBlock.NvStorage,
- INIT_RESUME,
- &EarlyBufferSize,
- &AmdS3SaveParams->StdHeader);
-
- AmdS3SaveParams->S3DataBlock.NvStorageSize = EarlyBufferSize;
- }
-
- if (LateBufferSize != 0) {
- BufferPointer = AllocParams.BufferPtr;
- AmdS3SaveParams->S3DataBlock.VolatileStorage = &(BufferPointer[EarlyBufferSize]);
-
- ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->HeapOffset = NULL;
- ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->HeapSize = HeapSize;
- ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->RegisterDataOffset = NULL;
- ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->RegisterDataSize = LateContextSize;
-
- if (HeapSize != 0) {
- // Transfer heap contents
- ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->HeapOffset = sizeof (S3_VOLATILE_STORAGE_HEADER);
- HeapPtr = (HEAP_MANAGER *) &BufferPointer[EarlyBufferSize + sizeof (S3_VOLATILE_STORAGE_HEADER)];
- HeapPtr->UsedSize = sizeof (HEAP_MANAGER);
- HeapPtr->Signature = HEAP_SIGNATURE_VALID;
- HeapPtr->FirstActiveBufferOffset = AMD_HEAP_INVALID_HEAP_OFFSET;
- HeapPtr->FirstFreeSpaceOffset = sizeof (HEAP_MANAGER);
- FreeSpaceNode = (BUFFER_NODE *) ((UINT8 *) HeapPtr + sizeof (HEAP_MANAGER));
- FreeSpaceNode->BufferSize = HeapSize - sizeof (HEAP_MANAGER) - sizeof (BUFFER_NODE);
- FreeSpaceNode->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET;
-
- HeapStatus = AmdS3SaveParams->StdHeader.HeapStatus;
- AmdS3SaveParams->StdHeader.HeapStatus = HEAP_S3_RESUME;
- AmdS3SaveParams->StdHeader.HeapBasePtr = (UINT64) HeapPtr;
-
- for (i = 0; i < S3LATE_TABLE_SIZE; i++) {
- if (HeapPtrs[i] != NULL) {
- HeapParams.RequestedBufferSize = HeapSizes[i]; // S3LateHeapTable[i].BufferLength;
- HeapParams.BufferHandle = S3LateHeapTable[i];
- HeapParams.Persist = HEAP_S3_RESUME;
- if (HeapAllocateBuffer (&HeapParams, &AmdS3SaveParams->StdHeader) == AGESA_SUCCESS) {
- LibAmdMemCopy ((VOID *) HeapParams.BufferPtr, HeapPtrs[i], HeapSizes[i], &AmdS3SaveParams->StdHeader);
- }
- }
- }
-
- AmdS3SaveParams->StdHeader.HeapStatus = HeapStatus;
- }
-
-
- if (LateContextSize != 0) {
-
- ((S3_VOLATILE_STORAGE_HEADER *) AmdS3SaveParams->S3DataBlock.VolatileStorage)->RegisterDataOffset = HeapSize + sizeof (S3_VOLATILE_STORAGE_HEADER);
-
- SaveDeviceListContext (NonMemoryRelatedDeviceList,
- &(BufferPointer[EarlyBufferSize + HeapSize + sizeof (S3_VOLATILE_STORAGE_HEADER)]),
- S3_LATE_RESTORE,
- &LateContextSize,
- &AmdS3SaveParams->StdHeader);
- }
-
- AmdS3SaveParams->S3DataBlock.VolatileStorageSize = HeapSize + LateContextSize + sizeof (S3_VOLATILE_STORAGE_HEADER);
- }
- }
- }
- IDS_OPTION_HOOK (IDS_AFTER_S3_SAVE, AmdS3SaveParams, &AmdS3SaveParams->StdHeader);
- AGESA_TESTPOINT (TpIfAmdS3SaveExit, &AmdS3SaveParams->StdHeader);
- return ReturnStatus;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Constructor for the AMD_S3_SAVE function.
- *
- * This routine is responsible for setting default values for the
- * input parameters needed by the AMD_S3_SAVE entry point.
- *
- * @param[in] StdHeader The standard header.
- * @param[in,out] S3SaveParams Required input parameters for the AMD_S3_SAVE
- * entry point.
- *
- * @retval AGESA_SUCCESS Always Succeeds.
- *
- */
-AGESA_STATUS
-AmdS3SaveInitializer (
- IN OUT AMD_CONFIG_PARAMS *StdHeader,
- IN OUT AMD_S3SAVE_PARAMS *S3SaveParams
- )
-{
- ASSERT (StdHeader != NULL);
- ASSERT (S3SaveParams != NULL);
-
- S3SaveParams->StdHeader = *StdHeader;
-
- AmdS3ParamsInitializer (&S3SaveParams->S3DataBlock);
-
- AmdS3SavePlatformConfigInit (&S3SaveParams->PlatformConfig, &S3SaveParams->StdHeader);
-
- return AGESA_SUCCESS;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Destructor for the AMD_S3_SAVE function.
- *
- * This routine is responsible for deallocation of heap space allocated during
- * AMD_S3_SAVE entry point.
- *
- * @param[in] StdHeader The standard header.
- * @param[in,out] S3SaveParams Required input parameters for the AMD_INIT_RESUME
- * entry point.
- *
- * @retval AGESA_STATUS
- *
- */
-AGESA_STATUS
-AmdS3SaveDestructor (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN OUT AMD_S3SAVE_PARAMS *S3SaveParams
- )
-{
- AGESA_STATUS ReturnStatus;
- AGESA_STATUS RetVal;
-
- ASSERT (S3SaveParams != NULL);
-
- ReturnStatus = AGESA_SUCCESS;
-
- // Deallocate heap space allocated during memory S3 save
- RetVal = MemS3Deallocate (&S3SaveParams->StdHeader);
- if (RetVal > ReturnStatus) {
- ReturnStatus = RetVal;
- }
-
- RetVal = HeapDeallocateBuffer (AMD_S3_NB_INFO_BUFFER_HANDLE, StdHeader);
- if (RetVal > ReturnStatus) {
- ReturnStatus = RetVal;
- }
-
- RetVal = HeapDeallocateBuffer (AMD_S3_INFO_BUFFER_HANDLE, StdHeader);
- if (RetVal > ReturnStatus) {
- ReturnStatus = RetVal;
- }
-
- return ReturnStatus;
-}
-
-/*------------------------------------------------------------------------------------*/
-/**
- * Initialize AmdS3Save stage platform profile and user option input.
- *
- * @param[in,out] PlatformConfig Platform profile/build option config structure
- * @param[in,out] StdHeader AMD standard header config param
- *
- * @retval AGESA_SUCCESS Always Succeeds.
- *
- */
-AGESA_STATUS
-AmdS3SavePlatformConfigInit (
- IN OUT PLATFORM_CONFIGURATION *PlatformConfig,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- CommonPlatformConfigInit (PlatformConfig, StdHeader);
-
- return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Common/CommonInits.c b/src/vendorcode/amd/agesa/Proc/Common/CommonInits.c
deleted file mode 100644
index edfdbb1..0000000
--- a/src/vendorcode/amd/agesa/Proc/Common/CommonInits.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Common initialization routines.
- *
- * Contains common initialization routines across AGESA entries of phases.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Common
- * @e \$Revision: 37157 $ @e \$Date: 2010-09-01 03:24:07 +0800 (Wed, 01 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "Filecode.h"
-#include "heapManager.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_COMMON_COMMONINITS_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-extern BUILD_OPT_CFG UserOptions;
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*------------------------------------------------------------------------------------*/
-
-/**
- * Common routine to initialize PLATFORM_CONFIGURATION.
- *
- * @param[in,out] PlatformConfig Platform profile/build option config structure
- * @param[in,out] StdHeader AMD standard header config param
- *
- * @retval AGESA_SUCCESS Always Succeeds.
- *
- */
-AGESA_STATUS
-CommonPlatformConfigInit (
- IN OUT PLATFORM_CONFIGURATION *PlatformConfig,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINTN i;
-
- PlatformConfig->PlatformProfile = UserOptions.CfgPerformanceProfile;
- PlatformConfig->PlatformDeemphasisList = UserOptions.CfgPlatformDeemphasisList;
- PlatformConfig->CoreLevelingMode = (UINT8) UserOptions.CfgCoreLevelingMode;
- PlatformConfig->C1eMode = UserOptions.CfgPlatformC1eMode;
- PlatformConfig->C1ePlatformData = UserOptions.CfgPlatformC1eOpData;
- PlatformConfig->C1ePlatformData1 = UserOptions.CfgPlatformC1eOpData1;
- PlatformConfig->C1ePlatformData2 = UserOptions.CfgPlatformC1eOpData2;
- PlatformConfig->CStateMode = UserOptions.CfgPlatformCStateMode;
- PlatformConfig->CStatePlatformData = UserOptions.CfgPlatformCStateOpData;
- PlatformConfig->CStateIoBaseAddress = UserOptions.CfgPlatformCStateIoBaseAddress;
- PlatformConfig->CpbMode = UserOptions.CfgPlatformCpbMode;
- PlatformConfig->UserOptionDmi = UserOptions.OptionDmi;
- PlatformConfig->UserOptionPState = UserOptions.OptionAcpiPstates;
- PlatformConfig->UserOptionSrat = UserOptions.OptionSrat;
- PlatformConfig->UserOptionSlit = UserOptions.OptionSlit;
- PlatformConfig->UserOptionWhea = UserOptions.OptionWhea;
- PlatformConfig->PowerCeiling = UserOptions.CfgAmdPstateCapValue;
- PlatformConfig->ForcePstateIndependent = UserOptions.CfgAcpiPstateIndependent;
- PlatformConfig->NumberOfIoApics = UserOptions.CfgPlatNumIoApics;
- for (i = 0; i < MaxVrmType; i++) {
- PlatformConfig->VrmProperties[i] = UserOptions.CfgPlatVrmCfg[i];
- }
- PlatformConfig->ProcessorScopeInSb = UserOptions.CfgProcessorScopeInSb;
- PlatformConfig->ProcessorScopeName0 = UserOptions.CfgProcessorScopeName0;
- PlatformConfig->ProcessorScopeName1 = UserOptions.CfgProcessorScopeName1;
- PlatformConfig->GnbHdAudio = UserOptions.CfgGnbHdAudio;
- PlatformConfig->AbmSupport = UserOptions.CfgAbmSupport;
- PlatformConfig->DynamicRefreshRate = UserOptions.CfgDynamicRefreshRate;
- PlatformConfig->LcdBackLightControl = UserOptions.CfgLcdBackLightControl;
- if ((StdHeader->HeapStatus == HEAP_LOCAL_CACHE) ||
- (StdHeader->HeapStatus == HEAP_TEMP_MEM) ||
- (StdHeader->HeapStatus == HEAP_SYSTEM_MEM)) {
- IDS_OPTION_HOOK (IDS_PLATFORMCFG_OVERRIDE, PlatformConfig, StdHeader);
- }
- return AGESA_SUCCESS;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/Common/CommonInits.h b/src/vendorcode/amd/agesa/Proc/Common/CommonInits.h
deleted file mode 100644
index 3bd6109..0000000
--- a/src/vendorcode/amd/agesa/Proc/Common/CommonInits.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Common initialization routines.
- *
- * Contains common initialization routines across AGESA entries of phases.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Common
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _COMMON_INITS_H_
-#define _COMMON_INITS_H_
-
-/**
- * Common routine to initialize PLATFORM_CONFIGURATION.
- *
- * @param[in,out] PlatformConfig Platform profile/build option config structure
- * @param[in,out] StdHeader AMD standard header config param
- *
- * @retval AGESA_SUCCESS Always Succeeds.
- *
- */
-AGESA_STATUS
-CommonPlatformConfigInit (
- IN OUT PLATFORM_CONFIGURATION *PlatformConfig,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif // _COMMON_INITS_H_
-
diff --git a/src/vendorcode/amd/agesa/Proc/Common/CommonPage.h b/src/vendorcode/amd/agesa/Proc/Common/CommonPage.h
deleted file mode 100644
index 9cc7232..0000000
--- a/src/vendorcode/amd/agesa/Proc/Common/CommonPage.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Create outline and references for Processor Common Component mainpage documentation.
- *
- * Design guides, maintenance guides, and general documentation, are
- * collected using this file onto the documentation mainpage.
- * This file contains doxygen comment blocks, only.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Documentation
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/**
- * @page commonmain Processor Common Component Documentation
- *
- * Additional documentation for the Common component consists of
- *
- * - Maintenance Guides:
- * - @subpage amdconfigparamname "Naming Guidelines for type AMD_CONFIG_PARAMS"
- * - Design Guides:
- * - add here >>>
- *
- */
-
-/**
- * @page amdconfigparamname Naming Guidelines for type AMD_CONFIG_PARAMS
- * @par
- * These are the guidelines for naming objects of type AMD_CONFIG_PARAMS and AMD_CONFIG_PARAMS * in AGESA code.
- * <ul>
- *
- * <li>
- * Formal parameter names of type AMD_CONFIG_PARAMS and AMD_CONFIG_PARAMS * will always be named
- * StdHeader. This covers all function prototypes, function definitions, and method typedefs (a
- * typedef of a function prototype) in AGESA code. Examples:
- * @n @code
- * VOID
- * LibAmdPciFindNextCap (
- * IN OUT PCI_ADDR *Address,
- * IN AMD_CONFIG_PARAMS *StdHeader
- * )
- *
- * typedef VOID F_DO_TABLE_ENTRY (
- * IN TABLE_ENTRY_DATA *CurrentEntry,
- * IN PLATFORM_CONFIGURATION *PlatformConfig,
- * IN AMD_CONFIG_PARAMS *StdHeader
- * );
- *
- * @endcode
- *
- * <li>
- * Structure members of type AMD_CONFIG_PARAMS or AMD_CONFIG_PARAMS * will always be named StdHeader. Examples:
- * @n @code
- /// Example of struct member naming.
- * typedef struct {
- * IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard Header
- * IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
- * } AMD_CPU_RECOVERY_PARAMS;
- *
- * @endcode
- *
- * <li>
- * Routines which define local variables of type AMD_CONFIG_PARAMS or AMD_CONFIG_PARAMS * should
- * name the local variable as closely as practical to StdHeader, but otherwise freedom is allowed. Example:
- * @n @code
- * AMD_CONFIG_PARAMS *NewStdHeader;
- * [...]
- * NewStdHeader = (AMD_CONFIG_PARAMS *)AllocHeapParams.BufferPtr;
- * @endcode
- *
- * <li>
- * Arguments to routines with AMD_CONFIG_PARAMS or AMD_CONFIG_PARAMS * formal parameters are not
- * checked. Freedom is allowed in order to conform to these guidelines in a practical, readable
- * way. This includes typecast arguments. Examples:
- * @n @code
- * Status = GetEventLog (&LogEvent, (AMD_CONFIG_PARAMS *)Event);
- *
- * MemS3ExitSelfRefRegDA (NBPtr, &MemPtr->StdHeader);
- * @endcode
- *
- * </ul>
- *
- */
diff --git a/src/vendorcode/amd/agesa/Proc/Common/CommonReturns.c b/src/vendorcode/amd/agesa/Proc/Common/CommonReturns.c
deleted file mode 100644
index 90e2918..0000000
--- a/src/vendorcode/amd/agesa/Proc/Common/CommonReturns.c
+++ /dev/null
@@ -1,174 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Common Return routines.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Common
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_COMMON_COMMONRETURNS_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
-* Return TRUE.
-*
-* @retval TRUE Default case, no special action
-*/
-BOOLEAN
-CommonReturnTrue (VOID)
-{
- return TRUE;
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
-* Return False.
-*
-* @retval FALSE Default case, no special action
-*/
-BOOLEAN
-CommonReturnFalse (VOID)
-{
- return FALSE;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Return (UINT8)zero.
- *
- *
- * @retval zero None, or only case zero.
- */
-UINT8
-CommonReturnZero8 (VOID)
-{
- return 0;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Return (UINT32)zero.
- *
- *
- * @retval zero None, or only case zero.
- */
-UINT32
-CommonReturnZero32 (VOID)
-{
- return 0;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Return (UINT64)zero.
- *
- *
- * @retval zero None, or only case zero.
- */
-UINT64
-CommonReturnZero64 (VOID)
-{
- return 0;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Return NULL
- *
- * @retval NULL pointer to nothing
- */
-VOID *
-CommonReturnNULL (VOID)
-{
- return NULL;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
-* Return AGESA_SUCCESS.
-*
-* @retval AGESA_SUCCESS Success.
-*/
-AGESA_STATUS
-CommonReturnAgesaSuccess (VOID)
-{
- return AGESA_SUCCESS;
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Do Nothing.
- *
- */
-VOID
-CommonVoid (VOID)
-{
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * ASSERT if this routine is called.
- *
- */
-VOID
-CommonAssert (VOID)
-{
- ASSERT (FALSE);
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Common/CreateStruct.c b/src/vendorcode/amd/agesa/Proc/Common/CreateStruct.c
deleted file mode 100644
index 68ecb63..0000000
--- a/src/vendorcode/amd/agesa/Proc/Common/CreateStruct.c
+++ /dev/null
@@ -1,315 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD AGESA Input Structure Creation
- *
- * Contains AGESA input structure creation support.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Common
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "GeneralServices.h"
-#include "heapManager.h"
-#include "CreateStruct.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_COMMON_CREATESTRUCT_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-extern CONST FUNCTION_PARAMS_INFO FuncParamsInfo[];
-extern CONST UINTN InitializerCount;
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-extern BUILD_OPT_CFG UserOptions;
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Allocate and initialize Config headers and Service Interface structures.
- *
- * This function will be called for each AGESA public APIs.
- * This function will do the following:
- * -# Locate the AGESA API structure parameters initializer function information.
- * -# Find the size of the structure that gets passed to each public APIs as
- * the entry parameter. Allocate heap space using the size for PreMemHeap, callout for
- * memory allocation for PostMemDram, and just set the config and service interface
- * pointers for ByHost.
- * -# If the allocation is not ByHost, copy the AmdConfigParams into the newly created AmdConfigParams.
- * For ByHost, we're using the caller's existing config params.
- * -# Call the initializer function, and pass a reference to the Config params and to
- * the Service Interface struct. On return the constructor will have filled the
- * remaining structure with default values.
- * -# Fill the remaining info in the newly created structure on heap in AMD_CONFIG_PARAMS
- * area (i.e. Fill *newStructPtr with the pointer to the newly created structure)
- * -# Set the appropriate AGESA function number in the StdHeader member of the input
- * parameter structure.
- *
- * @param[in,out] InterfaceParams Pointer to structure containing the function call
- * whose parameter structure is to be created, the
- * allocation method, and a pointer to the newly
- * created structure.
- *
- * @retval AGESA_SUCCESS The interface struct is allocated and initialized.
- * @retval AGESA_UNSUPPORTED The Service is not supported.
- *
- */
-AGESA_STATUS
-AmdCreateStruct (
- IN OUT AMD_INTERFACE_PARAMS *InterfaceParams
- )
-{
- UINTN ServiceIndex;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
- AMD_CONFIG_PARAMS *NewlyCreatedConfig;
- VOID *NewlyCreatedServiceInterface;
- AGESA_STATUS AgesaStatus;
- AGESA_STATUS TempStatus;
- AGESA_STATUS IgnoredSts;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
-
- AgesaStatus = AGESA_SUCCESS;
-
- ASSERT (InterfaceParams != NULL);
-
- switch (InterfaceParams->AgesaFunctionName) {
- case AMD_INIT_RESET:
- if (!IsBsp (&InterfaceParams->StdHeader, &IgnoredSts)) {
- // APs must transfer their system core number from the mailbox to
- // a local register while it is still valid.
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, &InterfaceParams->StdHeader);
- FamilySpecificServices->TransferApCoreNumber (FamilySpecificServices, &InterfaceParams->StdHeader);
- }
- InterfaceParams->StdHeader.HeapStatus = HEAP_DO_NOT_EXIST_YET;
- break;
- case AMD_INIT_EARLY:
- case AMD_INIT_RECOVERY:
- case AMD_INIT_RESUME:
- case AMD_INIT_POST:
- InterfaceParams->StdHeader.HeapStatus = HEAP_LOCAL_CACHE;
- break;
- case AMD_INIT_ENV:
- InterfaceParams->StdHeader.HeapStatus = HEAP_TEMP_MEM;
- break;
- case AMD_INIT_LATE:
- case AMD_INIT_MID:
- case AMD_S3_SAVE:
- case AMD_LATE_RUN_AP_TASK:
- InterfaceParams->StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
- break;
- case AMD_S3LATE_RESTORE:
- InterfaceParams->StdHeader.HeapStatus = HEAP_S3_RESUME;
- break;
- default:
- ASSERT (FALSE);
- InterfaceParams->StdHeader.HeapStatus = HEAP_LOCAL_CACHE;
- break;
- }
-
- InterfaceParams->StdHeader.HeapBasePtr = HeapGetBaseAddress (&InterfaceParams->StdHeader);
-
- if (InterfaceParams->AgesaFunctionName == AMD_INIT_RESET) {
- AgesaStatus = HeapManagerInit (&InterfaceParams->StdHeader);
- }
-
- // Step 1
- for (ServiceIndex = 0; ServiceIndex < InitializerCount; ServiceIndex++) {
- if (FuncParamsInfo[ServiceIndex].AgesaFunctionName == InterfaceParams->AgesaFunctionName) {
- break;
- }
- }
- if (ServiceIndex >= InitializerCount) {
- // A call was made to AGESA with an invalid function number. This wrapper error may be due to the build target
- // not containing the desired entry point.
- return AGESA_UNSUPPORTED;
- }
-
- // Step 2
- LibAmdMemFill (&AllocHeapParams, 0, (UINTN) (sizeof (ALLOCATE_HEAP_PARAMS)), &InterfaceParams->StdHeader);
-
- if (InterfaceParams->AllocationMethod < ByHost) {
- // Allocate one buffer to contain the config params and the service struct.
- // The service struct begins immediately after the config params.
- AllocHeapParams.RequestedBufferSize = FuncParamsInfo[ServiceIndex].CreateStructSize + sizeof (AMD_CONFIG_PARAMS);
- AllocHeapParams.BufferHandle = FuncParamsInfo[ServiceIndex].BufferHandle;
- AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
- TempStatus = HeapAllocateBuffer (&AllocHeapParams, &(InterfaceParams->StdHeader));
- AgesaStatus = ((AgesaStatus > TempStatus) ? AgesaStatus : TempStatus);
- NewlyCreatedConfig = (AMD_CONFIG_PARAMS *)AllocHeapParams.BufferPtr;
- NewlyCreatedConfig++;
- NewlyCreatedServiceInterface = NewlyCreatedConfig;
- NewlyCreatedConfig = (AMD_CONFIG_PARAMS *)AllocHeapParams.BufferPtr;
- } else {
- // The caller (example, agesa basic interface implementation) already has a buffer to use.
- NewlyCreatedConfig = (AMD_CONFIG_PARAMS *)InterfaceParams;
- NewlyCreatedServiceInterface = InterfaceParams->NewStructPtr;
- ASSERT (InterfaceParams->NewStructSize >= FuncParamsInfo[ServiceIndex].CreateStructSize);
- }
- ASSERT (NewlyCreatedConfig != NULL);
- ASSERT (NewlyCreatedServiceInterface != NULL);
-
- // Step 3
- if (InterfaceParams->AllocationMethod != ByHost) {
- *NewlyCreatedConfig = InterfaceParams->StdHeader;
- }
-
- // Step 4
- TempStatus = FuncParamsInfo[ServiceIndex].AgesaFunction (NewlyCreatedConfig, NewlyCreatedServiceInterface);
- AgesaStatus = ((AgesaStatus > TempStatus) ? AgesaStatus : TempStatus);
-
- // Step 5
- if (InterfaceParams->AllocationMethod != ByHost) {
- InterfaceParams->NewStructPtr = (VOID *) NewlyCreatedServiceInterface;
- InterfaceParams->NewStructSize = FuncParamsInfo[ServiceIndex].CreateStructSize;
- }
-
- // Step 6
- ((AMD_CONFIG_PARAMS *) InterfaceParams->NewStructPtr)->Func = InterfaceParams->AgesaFunctionName;
- return AgesaStatus;
-}
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Clears storage space from allocation for a parameter block of an
- * AGESA software call entry.
- *
- * @param[in,out] InterfaceParams Pointer to structure containing the function call
- * whose parameter structure is to be deallocated.
- *
- * @retval AGESA_STATUS
- *
- *---------------------------------------------------------------------------------------
- **/
-AGESA_STATUS
-AmdReleaseStruct (
- IN OUT AMD_INTERFACE_PARAMS *InterfaceParams
- )
-{
- UINT8 i;
- UINT8 *BufferPtr;
- VOID *ServicePtr;
- AGESA_STATUS AgesaStatus;
- AGESA_STATUS TempStatus;
- LOCATE_HEAP_PTR LocHeap;
-
- AgesaStatus = AGESA_SUCCESS;
-
- switch (InterfaceParams->AgesaFunctionName) {
- case AMD_INIT_RESET:
- case AMD_INIT_EARLY:
- case AMD_INIT_RECOVERY:
- case AMD_INIT_RESUME:
- InterfaceParams->StdHeader.HeapStatus = HEAP_LOCAL_CACHE;
- break;
- case AMD_INIT_POST:
- InterfaceParams->StdHeader.HeapStatus = HEAP_TEMP_MEM;
- break;
- case AMD_INIT_ENV:
- case AMD_INIT_LATE:
- case AMD_INIT_MID:
- case AMD_S3_SAVE:
- case AMD_LATE_RUN_AP_TASK:
- InterfaceParams->StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
- break;
- case AMD_S3LATE_RESTORE:
- InterfaceParams->StdHeader.HeapStatus = HEAP_S3_RESUME;
- break;
- default:
- ASSERT (FALSE);
- InterfaceParams->StdHeader.HeapStatus = HEAP_LOCAL_CACHE;
- break;
- }
-
- InterfaceParams->StdHeader.HeapBasePtr = HeapGetBaseAddress (&InterfaceParams->StdHeader);
-
-// Step 1
- for (i = 0; i < InitializerCount; i++) {
- if (FuncParamsInfo[i].AgesaFunctionName == InterfaceParams->AgesaFunctionName) {
- break;
- }
- }
- if (i >= InitializerCount) {
- return AGESA_BOUNDS_CHK;
- }
-
- // Step 2
- if (InterfaceParams->AllocationMethod < ByHost) {
- LocHeap.BufferHandle = FuncParamsInfo[i].BufferHandle;
- if (HeapLocateBuffer (&LocHeap, &(InterfaceParams->StdHeader)) == AGESA_SUCCESS) {
- BufferPtr = (UINT8 *) LocHeap.BufferPtr;
- ServicePtr = &BufferPtr[sizeof (AMD_CONFIG_PARAMS)];
- TempStatus = FuncParamsInfo[i].AgesaDestructor (&(InterfaceParams->StdHeader), ServicePtr);
- AgesaStatus = ((AgesaStatus > TempStatus) ? AgesaStatus : TempStatus);
- }
- }
-
- // Step 3
- if (InterfaceParams->AllocationMethod < ByHost) {
- TempStatus = HeapDeallocateBuffer (FuncParamsInfo[i].BufferHandle, &(InterfaceParams->StdHeader));
- AgesaStatus = ((AgesaStatus > TempStatus) ? AgesaStatus : TempStatus);
- } else {
- // Unless we define service specific destructors, nothing to do for ByHost.
- return AGESA_SUCCESS;
- }
- return AgesaStatus;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Common/CreateStruct.h b/src/vendorcode/amd/agesa/Proc/Common/CreateStruct.h
deleted file mode 100644
index df47cbe..0000000
--- a/src/vendorcode/amd/agesa/Proc/Common/CreateStruct.h
+++ /dev/null
@@ -1,197 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD AGESA Input Structure Creation
- *
- * Contains AGESA input creation structures.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Common
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CREATE_STRUCT_H_
-#define _CREATE_STRUCT_H_
-
-/**
- * A constructor method.
- *
- * Sets inputs to valid, basic level, defaults for the specific service instance.
- * Constructors should avoid using the header, since these routines should not
- * do operations which may fail or require status back to the user. The constructor
- * should always SUCCEED.
- *
- * @param[in] StdHeader Opaque handle to standard config header
- * @param[in] ServiceInterface Service Interface structure to initialize.
- *
- * @retval AGESA_SUCCESS Constructors are not allowed to fail
-*/
-typedef AGESA_STATUS
-F_AGESA_FUNCTION (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN VOID *ServiceInterface
- );
-
-/// Reference to a Method.
-typedef F_AGESA_FUNCTION *PF_AGESA_FUNCTION;
-
-/**
- * A Destructor method.
- *
- * Sets inputs to valid, basic level, defaults for the specific service instance.
- * The constructor should always SUCCEED.
- *
- * @param[in] StdHeader Opaque handle to standard config header.
- * @param[in] ServiceInterface Service Interface structure to initialize.
- *
- * @retval AGESA_SUCCESS Constructors are not allowed to fail
-*/
-typedef AGESA_STATUS
-F_AGESA_DESTRUCTOR (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN VOID *ServiceInterface
- );
-
-/// Reference to a Method.
-typedef F_AGESA_DESTRUCTOR *PF_AGESA_DESTRUCTOR;
-
-/**
- * Provide the information needed to invoke each service constructor.
- */
-typedef struct {
- IN AGESA_STRUCT_NAME AgesaFunctionName; ///< Identifies the service
- IN UINT16 CreateStructSize; ///< The service's input struct size.
- /// Do NOT include a config params header!
- OUT PF_AGESA_FUNCTION AgesaFunction; ///< The constructor function
- OUT PF_AGESA_DESTRUCTOR AgesaDestructor; ///< The destructor function.
- IN AGESA_BUFFER_HANDLE BufferHandle; ///< The buffer handle id for the service.
-} FUNCTION_PARAMS_INFO;
-
-/**
- * All available services have their constructor info here.
- */
-AGESA_STATUS
-AmdInitResetConstructor (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN AMD_RESET_PARAMS *AmdResetParams
- );
-
-AGESA_STATUS
-AmdInitRecoveryInitializer (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN OUT AMD_RECOVERY_PARAMS *AmdRecoveryParamsPtr
- );
-
-AGESA_STATUS
-AmdInitEarlyInitializer (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN OUT AMD_EARLY_PARAMS *EarlyParams
- );
-
-AGESA_STATUS
-AmdInitPostInitializer (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN OUT AMD_POST_PARAMS *PostParamsPtr
- );
-
-AGESA_STATUS
-AmdInitPostDestructor (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN AMD_POST_PARAMS *PostParamsPtr
- );
-
-AGESA_STATUS
-AmdInitEnvInitializer (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN OUT AMD_ENV_PARAMS *EnvParamsPtr
- );
-
-AGESA_STATUS
-AmdInitMidInitializer (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN OUT AMD_MID_PARAMS *MidParamsPtr
- );
-
-AGESA_STATUS
-AmdInitLateInitializer (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN OUT AMD_LATE_PARAMS *LateParamsPtr
- );
-
-AGESA_STATUS
-AmdInitLateDestructor (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN AMD_LATE_PARAMS *LateParamsPtr
- );
-
-AGESA_STATUS
-AmdInitResumeInitializer (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN OUT AMD_RESUME_PARAMS *ResumeParams
- );
-
-AGESA_STATUS
-AmdInitResumeDestructor (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN OUT AMD_RESUME_PARAMS *ResumeParams
- );
-
-AGESA_STATUS
-AmdS3SaveInitializer (
- IN OUT AMD_CONFIG_PARAMS *StdHeader,
- IN OUT AMD_S3SAVE_PARAMS *S3SaveParams
- );
-
-AGESA_STATUS
-AmdS3SaveDestructor (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN OUT AMD_S3SAVE_PARAMS *S3SaveParams
- );
-
-AGESA_STATUS
-AmdS3LateRestoreInitializer (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN OUT AMD_S3LATE_PARAMS *S3LateParams
- );
-
-AGESA_STATUS
-AmdLateRunApTaskInitializer (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN OUT AP_EXE_PARAMS *AmdApExeParams
- );
-#endif // _CREATE_STRUCT_H_
-
diff --git a/src/vendorcode/amd/agesa/Proc/Common/S3RestoreState.c b/src/vendorcode/amd/agesa/Proc/Common/S3RestoreState.c
deleted file mode 100644
index 5e32121..0000000
--- a/src/vendorcode/amd/agesa/Proc/Common/S3RestoreState.c
+++ /dev/null
@@ -1,443 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * S3 save/restore script
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "Porting.h"
-#include "AMD.h"
-#include "AGESA.h"
-#include "Ids.h"
-#include "amdlib.h"
-#include "heapManager.h"
-#include "S3SaveState.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_COMMON_S3RESTORESTATE_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-extern S3_SCRIPT_CONFIGURATION OptionS3ScriptConfiguration;
-extern S3_DISPATCH_FUNCTION_ENTRY S3DispatchFunctionTable[];
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-AGESA_STATUS
-STATIC
-S3RestoreStateFromTable (
- IN S3_SAVE_TABLE_HEADER *S3SaveTablePtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Initialize S3 Script framework
- *
- *
- *
- * @param[in] StdHeader Pointer to standard header
- */
-AGESA_STATUS
-S3ScriptRestore (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- return OptionS3ScriptConfiguration.Restore (StdHeader);
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Initialize S3 Script framework
- *
- *
- *
- * @param[in] StdHeader Pointer to standard header
- */
-AGESA_STATUS
-S3ScriptRestoreStateStub (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- return AGESA_SUCCESS;
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Initialize S3 Script framework
- *
- *
- *
- * @param[in] StdHeader Pointer to standard header
- */
-AGESA_STATUS
-S3ScriptRestoreState (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_STATUS Status;
- S3_SAVE_TABLE_HEADER *S3SaveTablePtr;
- Status = S3ScriptGetS3SaveTable (StdHeader, &S3SaveTablePtr);
- if (Status != AGESA_SUCCESS) {
- IDS_ERROR_TRAP;
- return AGESA_FATAL;
- }
- S3SaveTablePtr->Locked = TRUE;
- Status = S3RestoreStateFromTable (S3SaveTablePtr, StdHeader);
- return Status;
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Initialize S3 Script framework
- *
- *
- *
- * @param[in] S3SaveTablePtr Pointer to S3 Save Table
- * @param[in] StdHeader Pointer to standard header
- */
-AGESA_STATUS
-STATIC
-S3RestoreStateFromTable (
- IN S3_SAVE_TABLE_HEADER *S3SaveTablePtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- VOID *S3SaveTableRecordPtr;
- PCI_ADDR PciAddress;
- UINTN Index;
- S3SaveTableRecordPtr = (UINT8 *) S3SaveTablePtr + sizeof (S3_SAVE_TABLE_HEADER);
- IDS_HDT_CONSOLE (S3_TRACE, "Start S3 restore\n", ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address);
- while ((UINT8 *) S3SaveTableRecordPtr < ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset)) {
- switch (*(UINT16 *) S3SaveTableRecordPtr) {
- case SAVE_STATE_IO_WRITE_OPCODE:
- S3_SCRIPT_DEBUG_CODE (
- IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT16) ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address);
- S3SaveDebugPrintHexArray (StdHeader, (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_WRITE_OP_HEADER), 1, ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width);
- IDS_HDT_CONSOLE (S3_TRACE, "\n");
- );
- LibAmdIoWrite (
- ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width,
- (UINT16) ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address,
- (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_WRITE_OP_HEADER),
- StdHeader
- );
- S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
- sizeof (S3_WRITE_OP_HEADER) +
- LibAmdAccessWidth (((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width);
- break;
- case SAVE_STATE_IO_READ_WRITE_OPCODE:
- S3_SCRIPT_DEBUG_CODE (
- IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT16) ((S3_READ_WRITE_OP_HEADER*) S3SaveTableRecordPtr)->Address);
- S3SaveDebugPrintHexArray (
- StdHeader,
- (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER),
- 1,
- ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width
- );
- IDS_HDT_CONSOLE (S3_TRACE, " Mask: ");
- S3SaveDebugPrintHexArray (
- StdHeader,
- (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER) + LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width),
- 1,
- ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width
- );
- IDS_HDT_CONSOLE (S3_TRACE, "\n");
- );
- LibAmdIoRMW (
- ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width,
- (UINT16) ((S3_READ_WRITE_OP_HEADER*) S3SaveTableRecordPtr)->Address,
- (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER),
- (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER) + LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width),
- StdHeader
- );
- S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
- sizeof (S3_READ_WRITE_OP_HEADER) +
- 2 * LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width);
- break;
- case SAVE_STATE_MEM_WRITE_OPCODE:
- S3_SCRIPT_DEBUG_CODE (
- IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT16) ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address);
- S3SaveDebugPrintHexArray (StdHeader, (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_WRITE_OP_HEADER), 1, ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width);
- IDS_HDT_CONSOLE (S3_TRACE, "\n");
- );
- LibAmdMemWrite (
- ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width,
- ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address,
- (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_WRITE_OP_HEADER),
- StdHeader
- );
- S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
- sizeof (S3_WRITE_OP_HEADER) +
- LibAmdAccessWidth (((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width);
- break;
- case SAVE_STATE_MEM_READ_WRITE_OPCODE:
- S3_SCRIPT_DEBUG_CODE (
- IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT16) ((S3_READ_WRITE_OP_HEADER*) S3SaveTableRecordPtr)->Address);
- S3SaveDebugPrintHexArray (
- StdHeader,
- (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER),
- 1,
- ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width
- );
- IDS_HDT_CONSOLE (S3_TRACE, " Mask: ");
- S3SaveDebugPrintHexArray (
- StdHeader,
- (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER) + LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width),
- 1,
- ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width
- );
- IDS_HDT_CONSOLE (S3_TRACE, "\n");
- );
- LibAmdMemRMW (
- ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width,
- ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address,
- (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER),
- (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER) + LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER*) S3SaveTableRecordPtr)->Width),
- StdHeader
- );
- S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
- sizeof (S3_READ_WRITE_OP_HEADER) +
- 2 * LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width);
- break;
- case SAVE_STATE_PCI_CONFIG_WRITE_OPCODE:
- PciAddress.AddressValue = (UINT32) ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address;
- S3_SCRIPT_DEBUG_CODE (
- IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT16) ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address);
- S3SaveDebugPrintHexArray (StdHeader, (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_WRITE_OP_HEADER), 1, ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width);
- IDS_HDT_CONSOLE (S3_TRACE, "\n");
- );
- LibAmdPciWrite (
- ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width,
- PciAddress,
- (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_WRITE_OP_HEADER),
- StdHeader
- );
- S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
- sizeof (S3_WRITE_OP_HEADER) +
- LibAmdAccessWidth (((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width);
- break;
- case SAVE_STATE_PCI_CONFIG_READ_WRITE_OPCODE:
- PciAddress.AddressValue = (UINT32) ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address;
- S3_SCRIPT_DEBUG_CODE (
- IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT16) ((S3_READ_WRITE_OP_HEADER*) S3SaveTableRecordPtr)->Address);
- S3SaveDebugPrintHexArray (
- StdHeader,
- (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER),
- 1,
- ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width
- );
- IDS_HDT_CONSOLE (S3_TRACE, " Mask: ");
- S3SaveDebugPrintHexArray (
- StdHeader,
- (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER) + LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width),
- 1,
- ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width
- );
- IDS_HDT_CONSOLE (S3_TRACE, "\n");
- );
- LibAmdPciRMW (
- ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width,
- PciAddress,
- (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER),
- (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_READ_WRITE_OP_HEADER) + LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width),
- StdHeader
- );
- S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
- sizeof (S3_READ_WRITE_OP_HEADER) +
- 2 * LibAmdAccessWidth (((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width);
- break;
- case SAVE_STATE_STALL_OPCODE:
- break;
- case SAVE_STATE_INFORMATION_OPCODE:
- IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: Info: [%s]\n", (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_INFO_OP_HEADER));
- S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
- sizeof (S3_INFO_OP_HEADER) +
- ((S3_INFO_OP_HEADER*) S3SaveTableRecordPtr)->Length;
- break;
- case SAVE_STATE_DISPATCH_OPCODE:
- S3_SCRIPT_DEBUG_CODE (
- IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: %s Function Id: 0x%02x, Context: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), ((S3_DISPATCH_OP_HEADER*) S3SaveTableRecordPtr)->FunctionId);
- S3SaveDebugPrintHexArray (
- StdHeader,
- (VOID*)((UINT8*) S3SaveTableRecordPtr + sizeof (S3_DISPATCH_OP_HEADER)),
- ((S3_DISPATCH_OP_HEADER*) S3SaveTableRecordPtr)->Length,
- AccessWidth8);
- IDS_HDT_CONSOLE (S3_TRACE, "\n");
- );
- Index = 0;
- while (S3DispatchFunctionTable[Index].FunctionId != 0) {
- if (S3DispatchFunctionTable[Index].FunctionId == ((S3_DISPATCH_OP_HEADER*) S3SaveTableRecordPtr)->FunctionId) {
- (S3DispatchFunctionTable[Index].Function) (
- StdHeader,
- ((S3_DISPATCH_OP_HEADER*) S3SaveTableRecordPtr)->Length,
- (VOID*)((UINT8*) S3SaveTableRecordPtr + sizeof (S3_DISPATCH_OP_HEADER))
- );
- break;
- }
- Index++;
- }
- ASSERT (S3DispatchFunctionTable[Index].FunctionId != 0);
- S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
- sizeof (S3_DISPATCH_OP_HEADER) +
- ((S3_DISPATCH_OP_HEADER*) S3SaveTableRecordPtr)->Length;
- break;
-
- case SAVE_STATE_IO_POLL_OPCODE:
- S3_SCRIPT_DEBUG_CODE (
- IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: %s Address: 0x%04x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT16) ((S3_POLL_OP_HEADER*) S3SaveTableRecordPtr)->Address);
- S3SaveDebugPrintHexArray (
- StdHeader,
- (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER),
- 1,
- ((S3_READ_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Width
- );
- IDS_HDT_CONSOLE (S3_TRACE, " Mask: ");
- S3SaveDebugPrintHexArray (
- StdHeader,
- (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER) + LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width),
- 1,
- ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width
- );
- )
- LibAmdIoPoll (
- ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width,
- (UINT16) ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Address,
- (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER),
- (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER) + LibAmdAccessWidth (((S3_POLL_OP_HEADER*) S3SaveTableRecordPtr)->Width),
- ((S3_POLL_OP_HEADER*) S3SaveTableRecordPtr)->Delay,
- StdHeader
- );
- S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
- sizeof (S3_POLL_OP_HEADER) +
- 2 * LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width);
- break;
- case SAVE_STATE_MEM_POLL_OPCODE:
- S3_SCRIPT_DEBUG_CODE (
- IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT32) ((S3_POLL_OP_HEADER*) S3SaveTableRecordPtr)->Address);
- S3SaveDebugPrintHexArray (
- StdHeader,
- (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER),
- 1,
- ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width
- );
- IDS_HDT_CONSOLE (S3_TRACE, " Mask: ");
- S3SaveDebugPrintHexArray (
- StdHeader,
- (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER) + LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width),
- 1,
- ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width
- );
- )
- LibAmdMemPoll (
- ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width,
- ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Address,
- (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER),
- (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER) + LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width),
- ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Delay,
- StdHeader
- );
- S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
- sizeof (S3_POLL_OP_HEADER) +
- 2 * LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width);
- break;
- case SAVE_STATE_PCI_CONFIG_POLL_OPCODE:
- PciAddress.AddressValue = (UINT32) ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Address;
- S3_SCRIPT_DEBUG_CODE (
- IDS_HDT_CONSOLE (S3_TRACE, " S3 Restore: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, *(UINT16 *) S3SaveTableRecordPtr), (UINT32) ((S3_POLL_OP_HEADER*) S3SaveTableRecordPtr)->Address);
- S3SaveDebugPrintHexArray (
- StdHeader,
- (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER),
- 1,
- ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width
- );
- IDS_HDT_CONSOLE (S3_TRACE, " Mask: ");
- S3SaveDebugPrintHexArray (
- StdHeader,
- (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER) + LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width),
- 1,
- ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width
- );
- )
- LibAmdPciPoll (
- ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width,
- PciAddress,
- (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER),
- (UINT8 *) S3SaveTableRecordPtr + sizeof (S3_POLL_OP_HEADER) + LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width),
- ((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Delay,
- StdHeader
- );
- S3SaveTableRecordPtr = (UINT8 *) S3SaveTableRecordPtr +
- sizeof (S3_POLL_OP_HEADER) +
- 2 * LibAmdAccessWidth (((S3_POLL_OP_HEADER *) S3SaveTableRecordPtr)->Width);
- break;
- default:
- IDS_HDT_CONSOLE (S3_TRACE, " ERROR!!! Invalid S3 restore opcode\n");
- ASSERT (FALSE);
- return AGESA_ERROR;
- }
- }
- IDS_HDT_CONSOLE (S3_TRACE, " End S3 Restore \n");
- return AGESA_SUCCESS;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/Common/S3SaveState.c b/src/vendorcode/amd/agesa/Proc/Common/S3SaveState.c
deleted file mode 100644
index 7fe7476..0000000
--- a/src/vendorcode/amd/agesa/Proc/Common/S3SaveState.c
+++ /dev/null
@@ -1,647 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * S3 save/restore script
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 37640 $ @e \$Date: 2010-09-08 23:01:59 +0800 (Wed, 08 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "Porting.h"
-#include "AMD.h"
-#include "AGESA.h"
-#include "Ids.h"
-#include "amdlib.h"
-#include "heapManager.h"
-#include "S3SaveState.h"
-#include "Filecode.h"
-CODE_GROUP (G3_DXE)
-RDATA_GROUP (G3_DXE)
-
-#define FILECODE PROC_COMMON_S3SAVESTATE_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-extern S3_SCRIPT_CONFIGURATION OptionS3ScriptConfiguration;
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Initialize S3 Script framework
- *
- *
- *
- * @param[in] StdHeader Pointer to standard header
- */
-AGESA_STATUS
-S3ScriptInit (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- return OptionS3ScriptConfiguration.Init (StdHeader);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Initialize S3 Script framework
- *
- *
- *
- * @param[in] StdHeader Pointer to standard header
- */
-AGESA_STATUS
-S3ScriptInitStateStub (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- return AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Initialize S3 Script framework
- *
- *
- *
- * @param[in] StdHeader Pointer to standard header
- */
-AGESA_STATUS
-S3ScriptInitState (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_STATUS Status;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
- AllocHeapParams.RequestedBufferSize = S3_TABLE_LENGTH;
- AllocHeapParams.BufferHandle = AMD_S3_SCRIPT_SAVE_TABLE_HANDLE;
- AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
- Status = HeapAllocateBuffer (&AllocHeapParams, StdHeader);
- if (Status == AGESA_SUCCESS) {
- ((S3_SAVE_TABLE_HEADER *) AllocHeapParams.BufferPtr)->TableLength = S3_TABLE_LENGTH;
- ((S3_SAVE_TABLE_HEADER *) AllocHeapParams.BufferPtr)->SaveOffset = sizeof (S3_SAVE_TABLE_HEADER);
- ((S3_SAVE_TABLE_HEADER *) AllocHeapParams.BufferPtr)->Locked = FALSE;
- }
- return Status;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Initialize S3 Script framework
- *
- *
- *
- * @param[in] StdHeader Pointer to standard header
- * @param[in,out] S3SaveTable S3 save table header
- */
-AGESA_STATUS
-S3SaveStateExtendTableLenth (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN OUT S3_SAVE_TABLE_HEADER **S3SaveTable
- )
-{
- AGESA_STATUS Status;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
- VOID *TempBuffer;
- UINT16 NewTableLength;
- UINT16 CurrentTableLength;
- //Allocate temporary buffer
- NewTableLength = (*S3SaveTable)->TableLength + S3_TABLE_LENGTH_INCREMENT;
- AllocHeapParams.RequestedBufferSize = NewTableLength;
- AllocHeapParams.BufferHandle = AMD_S3_SCRIPT_TEMP_BUFFER_HANDLE;
- AllocHeapParams.Persist = StdHeader->HeapStatus;
- Status = HeapAllocateBuffer (&AllocHeapParams, StdHeader);
- if (Status != AGESA_SUCCESS) {
- return Status;
- }
- //Save current table length
- CurrentTableLength = (*S3SaveTable)->TableLength;
- //Update table length
- (*S3SaveTable)->TableLength = NewTableLength;
- //Copy S3 save toable to temporary location
- LibAmdMemCopy (AllocHeapParams.BufferPtr, *S3SaveTable, CurrentTableLength, StdHeader);
- //Save pointer to temp buffer
- TempBuffer = AllocHeapParams.BufferPtr;
- // Free original S3 save buffer
- HeapDeallocateBuffer (AMD_S3_SCRIPT_SAVE_TABLE_HANDLE, StdHeader);
-
- AllocHeapParams.RequestedBufferSize = NewTableLength;
- AllocHeapParams.BufferHandle = AMD_S3_SCRIPT_SAVE_TABLE_HANDLE;
- AllocHeapParams.Persist = StdHeader->HeapStatus;
- Status = HeapAllocateBuffer (&AllocHeapParams, StdHeader);
- if (Status != AGESA_SUCCESS) {
- return Status;
- }
- LibAmdMemCopy (AllocHeapParams.BufferPtr, TempBuffer, AllocHeapParams.RequestedBufferSize, StdHeader);
- *S3SaveTable = (S3_SAVE_TABLE_HEADER*) AllocHeapParams.BufferPtr;
- HeapDeallocateBuffer (AMD_S3_SCRIPT_TEMP_BUFFER_HANDLE, StdHeader);
- return Status;
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Initialize S3 Script framework
- *
- *
- *
- * @param[in] StdHeader Pointer to standard header
- * @param[out] S3SaveTable S3 save table header
- */
-AGESA_STATUS
-S3ScriptGetS3SaveTable (
- IN AMD_CONFIG_PARAMS *StdHeader,
- OUT S3_SAVE_TABLE_HEADER **S3SaveTable
- )
-{
- AGESA_STATUS Status;
- LOCATE_HEAP_PTR LocHeapParams;
- LocHeapParams.BufferHandle = AMD_S3_SCRIPT_SAVE_TABLE_HANDLE;
- Status = HeapLocateBuffer (&LocHeapParams, StdHeader);
- if (Status != AGESA_SUCCESS) {
- *S3SaveTable = NULL;
- return Status;
- }
- *S3SaveTable = (S3_SAVE_TABLE_HEADER *) LocHeapParams.BufferPtr;
- return AGESA_SUCCESS;
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Save S3 write opcode
- *
- *
- *
- * @param[in] StdHeader Pointer to standard header
- * @param[in] OpCode Operation opcode
- * @param[in] Width Width
- * @param[in] Address Register address
- * @param[in] Count Number of register writes
- * @param[in] Buffer Pointer to write buffer
- */
-AGESA_STATUS
-S3SaveStateSaveWriteOp (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN UINT16 OpCode,
- IN ACCESS_WIDTH Width,
- IN UINT64 Address,
- IN UINT32 Count,
- IN VOID *Buffer
- )
-{
- S3_SAVE_TABLE_HEADER *S3SaveTablePtr;
- S3_WRITE_OP_HEADER *SaveOffsetPtr;
- UINT32 OpCodeLength;
- UINT32 WidthLength;
- AGESA_STATUS Status;
-
- Status = S3ScriptGetS3SaveTable (StdHeader, &S3SaveTablePtr);
- if (Status != AGESA_SUCCESS) {
- return Status;
- }
- if (S3SaveTablePtr->Locked) {
- return AGESA_UNSUPPORTED;
- }
- WidthLength = LibAmdAccessWidth (Width);
- OpCodeLength = sizeof (S3_WRITE_OP_HEADER) + WidthLength * Count;
- if ((S3SaveTablePtr->SaveOffset + OpCodeLength) > S3SaveTablePtr->TableLength) {
- Status = S3SaveStateExtendTableLenth (StdHeader, &S3SaveTablePtr);
- if (Status != AGESA_SUCCESS) {
- return Status;
- }
- }
- S3_SCRIPT_DEBUG_CODE (
- IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address);
- S3SaveDebugPrintHexArray (StdHeader, Buffer, Count, Width);
- IDS_HDT_CONSOLE (S3_TRACE, "\n");
- );
- SaveOffsetPtr = (S3_WRITE_OP_HEADER *) ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset);
- SaveOffsetPtr->OpCode = OpCode;
- SaveOffsetPtr->Width = Width;
- SaveOffsetPtr->Count = Count;
- SaveOffsetPtr->Address = Address;
- LibAmdMemCopy (
- (UINT8 *) SaveOffsetPtr + sizeof (S3_WRITE_OP_HEADER),
- Buffer,
- WidthLength * Count,
- StdHeader
- );
- S3SaveTablePtr->SaveOffset += OpCodeLength;
- return AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Save S3 write opcode
- *
- *
- *
- * @param[in] StdHeader Pointer to standard header
- * @param[in] OpCode Operation opcode
- * @param[in] Width Width
- * @param[in] Address Register address
- * @param[in] Data Pointer to data
- * @param[in] DataMask Pointer data mask
- */
-AGESA_STATUS
-S3SaveStateSaveReadWriteOp (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN UINT16 OpCode,
- IN ACCESS_WIDTH Width,
- IN UINT64 Address,
- IN VOID *Data,
- IN VOID *DataMask
- )
-{
-
- S3_SAVE_TABLE_HEADER *S3SaveTablePtr;
- S3_READ_WRITE_OP_HEADER *SaveOffsetPtr;
- UINT32 OpCodeLength;
- UINT32 WidthLength;
- AGESA_STATUS Status;
-
- Status = S3ScriptGetS3SaveTable (StdHeader, &S3SaveTablePtr);
- if (Status != AGESA_SUCCESS) {
- return Status;
- }
- if (S3SaveTablePtr->Locked) {
- return AGESA_UNSUPPORTED;
- }
- WidthLength = LibAmdAccessWidth (Width);
- OpCodeLength = sizeof (S3_READ_WRITE_OP_HEADER) + WidthLength * 2;
- if ((S3SaveTablePtr->SaveOffset + OpCodeLength) > S3SaveTablePtr->TableLength) {
- Status = S3SaveStateExtendTableLenth (StdHeader, &S3SaveTablePtr);
- if (Status != AGESA_SUCCESS) {
- return Status;
- }
- }
- S3_SCRIPT_DEBUG_CODE (
- IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address);
- S3SaveDebugPrintHexArray (StdHeader, Data, 1, Width);
- IDS_HDT_CONSOLE (S3_TRACE, " Mask: ");
- S3SaveDebugPrintHexArray (StdHeader, DataMask, 1, Width);
- IDS_HDT_CONSOLE (S3_TRACE, "\n");
- );
- SaveOffsetPtr = (S3_READ_WRITE_OP_HEADER *) ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset);
- SaveOffsetPtr->OpCode = OpCode;
- SaveOffsetPtr->Width = Width;
- SaveOffsetPtr->Address = Address;
-
- LibAmdMemCopy (
- (UINT8 *) SaveOffsetPtr + sizeof (S3_READ_WRITE_OP_HEADER),
- Data,
- WidthLength,
- StdHeader
- );
- LibAmdMemCopy (
- (UINT8 *) SaveOffsetPtr + sizeof (S3_READ_WRITE_OP_HEADER) + WidthLength,
- DataMask,
- WidthLength,
- StdHeader
- );
- S3SaveTablePtr->SaveOffset += OpCodeLength;
- return AGESA_SUCCESS;
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Save S3 poll opcode
- *
- *
- *
- * @param[in] StdHeader Pointer to standard header
- * @param[in] OpCode Operation opcode
- * @param[in] Width Width
- * @param[in] Address Register address
- * @param[in] Data Pointer to data
- * @param[in] DataMask Pointer data mask
- * @param[in] Delay Time delay for poll
- */
-AGESA_STATUS
-S3SaveStateSavePollOp (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN UINT16 OpCode,
- IN ACCESS_WIDTH Width,
- IN UINT64 Address,
- IN VOID *Data,
- IN VOID *DataMask,
- IN UINT64 Delay
- )
-{
-
- S3_SAVE_TABLE_HEADER *S3SaveTablePtr;
- S3_POLL_OP_HEADER *SaveOffsetPtr;
- UINT32 OpCodeLength;
- UINT32 WidthLength;
- AGESA_STATUS Status;
-
- Status = S3ScriptGetS3SaveTable (StdHeader, &S3SaveTablePtr);
- if (Status != AGESA_SUCCESS) {
- return Status;
- }
- if (S3SaveTablePtr->Locked) {
- return AGESA_UNSUPPORTED;
- }
- WidthLength = LibAmdAccessWidth (Width);
- OpCodeLength = sizeof (S3_POLL_OP_HEADER) + WidthLength * 2;
- if ((S3SaveTablePtr->SaveOffset + OpCodeLength) > S3SaveTablePtr->TableLength) {
- Status = S3SaveStateExtendTableLenth (StdHeader, &S3SaveTablePtr);
- if (Status != AGESA_SUCCESS) {
- return Status;
- }
- }
- S3_SCRIPT_DEBUG_CODE (
- IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address);
- S3SaveDebugPrintHexArray (StdHeader, Data, 1, Width);
- IDS_HDT_CONSOLE (S3_TRACE, " Mask: ");
- S3SaveDebugPrintHexArray (StdHeader, DataMask, 1, Width);
- IDS_HDT_CONSOLE (S3_TRACE, "\n");
- );
- SaveOffsetPtr = (S3_POLL_OP_HEADER *) ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset);
- SaveOffsetPtr->OpCode = OpCode;
- SaveOffsetPtr->Width = Width;
- SaveOffsetPtr->Delay = Delay;
- SaveOffsetPtr->Address = Address;
-
- LibAmdMemCopy (
- (UINT8 *) SaveOffsetPtr + sizeof (S3_POLL_OP_HEADER),
- Data,
- WidthLength,
- StdHeader
- );
- LibAmdMemCopy (
- (UINT8 *) SaveOffsetPtr + sizeof (S3_POLL_OP_HEADER) + WidthLength,
- DataMask,
- WidthLength,
- StdHeader
- );
- S3SaveTablePtr->SaveOffset += OpCodeLength;
- return AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Save S3 info opcode
- *
- *
- *
- * @param[in] StdHeader Pointer to standard header
- * @param[in] OpCode Operation opcode
- * @param[in] InformationLength Info length
- * @param[in] Information Pointer to information
- */
-AGESA_STATUS
-S3SaveStateSaveInfoOp (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN UINT16 OpCode,
- IN UINT32 InformationLength,
- IN VOID *Information
- )
-{
-
- S3_SAVE_TABLE_HEADER *S3SaveTablePtr;
- S3_INFO_OP_HEADER *SaveOffsetPtr;
- UINT32 OpCodeLength;
-
- AGESA_STATUS Status;
-
- Status = S3ScriptGetS3SaveTable (StdHeader, &S3SaveTablePtr);
- if (Status != AGESA_SUCCESS) {
- return Status;
- }
- if (S3SaveTablePtr->Locked) {
- return AGESA_UNSUPPORTED;
- }
- OpCodeLength = sizeof (S3_INFO_OP_HEADER) + InformationLength;
- if ((S3SaveTablePtr->SaveOffset + OpCodeLength) > S3SaveTablePtr->TableLength) {
- Status = S3SaveStateExtendTableLenth (StdHeader, &S3SaveTablePtr);
- if (Status != AGESA_SUCCESS) {
- return Status;
- }
- }
- SaveOffsetPtr = (S3_INFO_OP_HEADER *) ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset);
- SaveOffsetPtr->OpCode = OpCode;
- SaveOffsetPtr->Length = InformationLength;
- S3_SCRIPT_DEBUG_CODE (
- IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: Info: %s \n", Information);
- );
- LibAmdMemCopy (
- (UINT8 *) SaveOffsetPtr + sizeof (S3_INFO_OP_HEADER),
- Information,
- InformationLength,
- StdHeader
- );
- S3SaveTablePtr->SaveOffset += OpCodeLength;
- return AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Save S3 dispatch opcode
- *
- *
- *
- * @param[in] StdHeader Pointer to standard header
- * @param[in] OpCode Operation opcode
- * @param[in] FunctionId Function ID
- * @param[in] ContextLength Context length
- * @param[in] Context Pointer to Context
- */
-AGESA_STATUS
-S3SaveStateSaveDispatchOp (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN UINT16 OpCode,
- IN UINT16 FunctionId,
- IN UINT16 ContextLength,
- IN VOID *Context
- )
-{
-
- S3_SAVE_TABLE_HEADER *S3SaveTablePtr;
- S3_DISPATCH_OP_HEADER *SaveOffsetPtr;
- UINT32 OpCodeLength;
- AGESA_STATUS Status;
-
- Status = S3ScriptGetS3SaveTable (StdHeader, &S3SaveTablePtr);
- if (Status != AGESA_SUCCESS) {
- return Status;
- }
- if (S3SaveTablePtr->Locked) {
- return AGESA_UNSUPPORTED;
- }
- OpCodeLength = sizeof (S3_DISPATCH_OP_HEADER) + ContextLength;
- if ((S3SaveTablePtr->SaveOffset + OpCodeLength) > S3SaveTablePtr->TableLength) {
- Status = S3SaveStateExtendTableLenth (StdHeader, &S3SaveTablePtr);
- if (Status != AGESA_SUCCESS) {
- return Status;
- }
- }
- S3_SCRIPT_DEBUG_CODE (
- IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Function Id: 0x%02x, Context: ", S3SaveDebugOpcodeString (StdHeader, OpCode), FunctionId);
- S3SaveDebugPrintHexArray (StdHeader, Context, ContextLength, AccessWidth8);
- IDS_HDT_CONSOLE (S3_TRACE, "\n");
- );
- SaveOffsetPtr = (S3_DISPATCH_OP_HEADER *) ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset);
- SaveOffsetPtr->OpCode = OpCode;
- SaveOffsetPtr->Length = ContextLength;
- SaveOffsetPtr->FunctionId = FunctionId;
- LibAmdMemCopy (
- (UINT8 *) SaveOffsetPtr + sizeof (S3_DISPATCH_OP_HEADER),
- Context,
- ContextLength,
- StdHeader
- );
-
- S3SaveTablePtr->SaveOffset += OpCodeLength;
- return AGESA_SUCCESS;
-}
-
-
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Save S3 debug support
- *
- *
- *
- * @param[in] StdHeader Pointer to standard header
- * @param[in] Op Opcode
- */
-CHAR8*
-S3SaveDebugOpcodeString (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN UINT16 Op
- )
-{
- switch (Op) {
- case SAVE_STATE_IO_WRITE_OPCODE:
- return "IO WR";
- case SAVE_STATE_IO_READ_WRITE_OPCODE:
- return "IO RD/WR";
- case SAVE_STATE_IO_POLL_OPCODE:
- return "IO POLL";
- case SAVE_STATE_MEM_WRITE_OPCODE:
- return "MEM WR";
- case SAVE_STATE_MEM_READ_WRITE_OPCODE:
- return "MEM RD/WR";
- case SAVE_STATE_MEM_POLL_OPCODE:
- return "MEM POLL";
- case SAVE_STATE_PCI_CONFIG_WRITE_OPCODE:
- return "PCI WR";
- case SAVE_STATE_PCI_CONFIG_READ_WRITE_OPCODE:
- return "PCI RD/WR";
- case SAVE_STATE_PCI_CONFIG_POLL_OPCODE:
- return "PCI POLL";
- case SAVE_STATE_STALL_OPCODE:
- return "STALL";
- case SAVE_STATE_DISPATCH_OPCODE:
- return "DISPATCH";
- default:
- IDS_ERROR_TRAP;
- }
- return "!!! Unrecognize opcode !!!";
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Save S3 debug support
- *
- *
- *
- * @param[in] StdHeader Pointer to standard header
- * @param[in] Array Array
- * @param[in] Count Count of element in array
- * @param[in] Width Array Element width
- */
-VOID
-S3SaveDebugPrintHexArray (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN VOID *Array,
- IN UINT32 Count,
- IN ACCESS_WIDTH Width
- )
-{
- UINTN Index;
-
- for (Index = 0; Index < Count; Index++) {
- switch (Width) {
- case AccessWidth8:
- case AccessS3SaveWidth8:
- IDS_HDT_CONSOLE (S3_TRACE, "0x%02x", *((UINT8*)Array + Index));
- break;
- case AccessWidth16:
- case AccessS3SaveWidth16:
- IDS_HDT_CONSOLE (S3_TRACE, "0x%04x", *((UINT16*)Array + Index));
- break;
- case AccessWidth32:
- case AccessS3SaveWidth32:
- IDS_HDT_CONSOLE (S3_TRACE, "0x%08x", *((UINT32*)Array + Index));
- break;
- case AccessWidth64:
- case AccessS3SaveWidth64:
- IDS_HDT_CONSOLE (S3_TRACE, "0x%08x%08x", ((UINT32*) ((UINT64*)Array + Index)[1], ((UINT32*) ((UINT64*)Array + Index))[0]));
- break;
- default:
- IDS_ERROR_TRAP;
- }
- if (Index < (Count - 1)) {
- IDS_HDT_CONSOLE (S3_TRACE, ", ");
- }
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Common/S3SaveState.h b/src/vendorcode/amd/agesa/Proc/Common/S3SaveState.h
deleted file mode 100644
index 07637c6..0000000
--- a/src/vendorcode/amd/agesa/Proc/Common/S3SaveState.h
+++ /dev/null
@@ -1,357 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Various PCI service routines.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _S3SAVESTATE_H_
-#define _S3SAVESTATE_H_
-
-#pragma pack (push, 1)
-
-#ifndef S3_SCRIPT_DEBUG_CODE
- #define S3_SCRIPT_DEBUG_CODE(Code) Code
-#endif
-
-/// Dispatch function ID repository
-typedef enum {
- S3DispatchGnbSmuServiceRequest = 1, ///< GNB SMU service request function ID.
- S3DispatchGnbPcieLateRestore, ///< GNB PCIe late restore function ID.
- S3DispatchGnbSmuIndirectWrite ///< GNB SMU indirect write.
-} S3_DISPATCH_FUNCTION_ID;
-
-#define SAVE_STATE_IO_WRITE_OPCODE 0x00
-#define SAVE_STATE_IO_READ_WRITE_OPCODE 0x01
-#define SAVE_STATE_MEM_WRITE_OPCODE 0x02
-#define SAVE_STATE_MEM_READ_WRITE_OPCODE 0x03
-#define SAVE_STATE_PCI_CONFIG_WRITE_OPCODE 0x04
-#define SAVE_STATE_PCI_CONFIG_READ_WRITE_OPCODE 0x05
-#define SAVE_STATE_STALL_OPCODE 0x07
-#define SAVE_STATE_INFORMATION_OPCODE 0x0A
-#define SAVE_STATE_IO_POLL_OPCODE 0x0D
-#define SAVE_STATE_MEM_POLL_OPCODE 0x0E
-#define SAVE_STATE_PCI_CONFIG_POLL_OPCODE 0x0F
-#define SAVE_STATE_DISPATCH_OPCODE 0x20
-#define SAVE_STATE_BREAKPOINT_OPCODE 0x21
-
-
-#define S3_TABLE_LENGTH 8 * 1024
-#define S3_TABLE_LENGTH_INCREMENT 1 * 1024
-
-/// S3 Save Table
-typedef struct {
- UINT16 TableLength; ///< Table Length
- UINT32 SaveOffset; ///< Save Location
- BOOLEAN Locked; ///< Locked
-} S3_SAVE_TABLE_HEADER;
-
-/// S3 write operation header
-typedef struct {
- UINT16 OpCode; ///< Opcode
- ACCESS_WIDTH Width; ///< Data width (byte, word, dword)
- UINT64 Address; ///< Register address
- UINT32 Count; ///< Write count
-} S3_WRITE_OP_HEADER;
-
-/// S3 Read and Write Operation header
-typedef struct {
- UINT16 OpCode; ///< Opcode
- ACCESS_WIDTH Width; ///< Data width (byte, word, dword)
- UINT64 Address; ///< Register Address
-} S3_READ_WRITE_OP_HEADER;
-
-/// S3 Poll operation header
-typedef struct {
- UINT16 OpCode; ///< Opcode
- ACCESS_WIDTH Width; ///< Data width (byte, word, dword)
- UINT64 Address; ///< Register address
- UINT64 Delay; ///< Time delay
-} S3_POLL_OP_HEADER;
-
-/// Information operation header
-typedef struct {
- UINT16 OpCode; ///< Opcode
- UINT32 Length; ///< Length of info
-} S3_INFO_OP_HEADER;
-
-/// Dispatch operation header
-typedef struct {
- UINT16 OpCode; ///< Opcode
- UINT16 FunctionId; ///< Function ID
- UINT16 Length; ///< Length in bytes of the context
-} S3_DISPATCH_OP_HEADER;
-
-
-typedef VOID S3_DISPATCH_FUNCTION (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN UINT16 ContextLength,
- IN VOID *Context
- );
-
-/// Dispatch function table entry
-typedef struct {
- UINT16 FunctionId; ///<Function ID
- S3_DISPATCH_FUNCTION *Function; ///<Function pointer
-} S3_DISPATCH_FUNCTION_ENTRY;
-
-typedef AGESA_STATUS (*S3_SCRIPT_INIT) (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-typedef AGESA_STATUS (*S3_SCRIPT_RESTORE) (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// S3 Script Configuration
-typedef struct {
- S3_SCRIPT_INIT Init; ///< Script initialization
- S3_SCRIPT_RESTORE Restore; ///< Script restore
-} S3_SCRIPT_CONFIGURATION;
-
-AGESA_STATUS
-S3ScriptInit (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-S3ScriptInitState (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-S3ScriptInitStateStub (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-S3ScriptRestore (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-S3ScriptRestoreState (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-S3ScriptRestoreStateStub (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-S3ScriptGetS3SaveTable (
- IN AMD_CONFIG_PARAMS *StdHeader,
- OUT S3_SAVE_TABLE_HEADER **S3SaveTable
- );
-
-VOID
-S3SaveDebugPrintHexArray (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN VOID *Array,
- IN UINT32 Count,
- IN ACCESS_WIDTH Width
- );
-
-CHAR8*
-S3SaveDebugOpcodeString (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN UINT16 Op
- );
-
-AGESA_STATUS
-S3SaveStateSaveWriteOp (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN UINT16 OpCode,
- IN ACCESS_WIDTH Width,
- IN UINT64 Address,
- IN UINT32 Count,
- IN VOID *Buffer
- );
-
-AGESA_STATUS
-S3SaveStateSaveReadWriteOp (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN UINT16 OpCode,
- IN ACCESS_WIDTH Width,
- IN UINT64 Address,
- IN VOID *Data,
- IN VOID *DataMask
- );
-
-AGESA_STATUS
-S3SaveStateSavePollOp (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN UINT16 OpCode,
- IN ACCESS_WIDTH Width,
- IN UINT64 Address,
- IN VOID *Data,
- IN VOID *DataMask,
- IN UINT64 Delay
- );
-
-AGESA_STATUS
-S3SaveStateSaveInfoOp (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN UINT16 OpCode,
- IN UINT32 InformationLength,
- IN VOID *Information
- );
-
-AGESA_STATUS
-S3SaveStateSaveDispatchOp (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN UINT16 OpCode,
- IN UINT16 FunctionId,
- IN UINT16 ContextLength,
- IN VOID *Context
- );
-
-//PCI write
-#define S3_SAVE_PCI_WRITE(StdHeader, Address, Width, DataPtr) \
- S3SaveStateSaveWriteOp ( \
- StdHeader, \
- SAVE_STATE_PCI_CONFIG_WRITE_OPCODE, \
- Width, \
- Address.AddressValue, \
- 1, \
- DataPtr \
- )
-
-//PCI read modify write
-#define S3_SAVE_PCI_RMW (StdHeader, Address, Width, DataPtr, DataMaskPtr) \
- S3SaveStateSaveWriteOp ( \
- StdHeader, \
- SAVE_STATE_PCI_CONFIG_READ_WRITE_OPCODE, \
- Width, \
- Address.AddressValue, \
- DataPtr, \
- DataMask \
- )
-
-//PCI read modify write
-#define S3_SAVE_PCI_POLL(StdHeader, Address, Width, DataPtr, DataMaskPtr, Delay) \
- S3SaveStateSavePollOp ( \
- StdHeader, \
- SAVE_STATE_PCI_CONFIG_POLL_OPCODE, \
- Width, \
- Address.AddressValue, \
- DataPtr, \
- DataMask, \
- Delay \
- )
-
-//Memory/MMIO write
-#define S3_SAVE_MEM_WRITE(StdHeader, Address, Width, DataPtr) \
- S3SaveStateSaveWriteOp ( \
- StdHeader, \
- SAVE_STATE_MEM_WRITE_OPCODE, \
- Width, \
- Address, \
- 1, \
- DataPtr \
- )
-
-//Memory/MMIO read modify write
-#define S3_SAVE_MEM_RMW(StdHeader, Address, Width, DataPtr, DataMaskPtr) \
- S3SaveStateSaveWriteOp ( \
- StdHeader, \
- SAVE_STATE_MEM_READ_WRITE_OPCODE, \
- Width, \
- Address, \
- DataPtr, \
- DataMask \
- )
-
-//Memory/MMIO read modify write
-#define S3_SAVE_MEM_POLL(StdHeader, Address, Width, DataPtr, DataMaskPtr, Delay) \
- S3SaveStateSavePollOp ( \
- StdHeader, \
- SAVE_STATE_MEM_POLL_OPCODE, \
- Width, \
- Address, \
- DataPtr, \
- DataMask, \
- Delay \
- )
-
-// I/O write
-#define S3_SAVE_IO_WRITE(StdHeader, Address, Width, DataPtr) \
- S3SaveStateSaveWriteOp ( \
- StdHeader, \
- SAVE_STATE_IO_WRITE_OPCODE, \
- Width, \
- Address, \
- 1, \
- DataPtr \
- )
-
-// Save information
-#define S3_SAVE_INFORMATION(StdHeader, InformationLength, Information) \
- S3SaveStateSaveInfoOp ( \
- StdHeader, \
- SAVE_STATE_INFORMATION_OPCODE, \
- InformationLength, \
- Information \
- )
-
-// Save information string S3_SAVE_INFORMATION_STRING (StdHeader, "Message")
-#define S3_SAVE_INFORMATION_STRING(StdHeader, Information) \
- S3SaveStateSaveInfoOp ( \
- StdHeader, \
- SAVE_STATE_INFORMATION_OPCODE, \
- sizeof (Information), \
- Information \
- )
-
-// Save dispatch function
-#define S3_SAVE_DISPATCH(StdHeader, FunctionId, ContextLength, Context) \
- S3SaveStateSaveDispatchOp ( \
- StdHeader, \
- SAVE_STATE_DISPATCH_OPCODE, \
- FunctionId, \
- ContextLength, \
- Context \
- )
-
-#pragma pack (pop)
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Common/Gnb.h b/src/vendorcode/amd/agesa/Proc/GNB/Common/Gnb.h
deleted file mode 100644
index 72ccb84..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Common/Gnb.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Misc common definition
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 40151 $ @e \$Date: 2010-10-20 06:38:17 +0800 (Wed, 20 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _GNB_H_
-#define _GNB_H_
-
-
-#define GNB_DEADLOOP() \
-{ \
- VOLATILE BOOLEAN k; \
- k = TRUE; \
- while (k) { \
- } \
-}
-#ifdef IDSOPT_TRACING_ENABLED
- #if (IDSOPT_TRACING_ENABLED == TRUE)
- #define GNB_TRACE_ENABLE
- #endif
-#endif
-
-
-#ifndef GNB_DEBUG_CODE
- #ifdef GNB_TRACE_ENABLE
- #define GNB_DEBUG_CODE(Code) Code
- #else
- #define GNB_DEBUG_CODE(Code)
- #endif
-#endif
-
-#define MIN(x, y) (((x) > (y))? (y):(x))
-#define MAX(x, y) (((x) > (y))? (x):(y))
-
-#define OFF 0
-
-#define PVOID UINT64
-
-#define GnbLibGetHeader(x) ((AMD_CONFIG_PARAMS*) (x)->StdHeader)
-
-#define AGESA_STATUS_UPDATE(Current, Aggregated) \
-if (Current > Aggregated) { \
- Aggregated = Current; \
-}
-
-#ifndef offsetof
- #define offsetof(s, m) (UINTN)&(((s *)0)->m)
-#endif
-
-/// Power gaiter data setting (do not change this structure definition)
-typedef struct {
- UINT16 MothPsoPwrup; ///< Mother Timer Powerup
- UINT16 MothPsoPwrdn; ///< Mother Timer Powerdown
- UINT16 DaugPsoPwrup; ///< Daughter Timer Powerup
- UINT16 DaugPsoPwrdn; ///< Daughter Timer Powerdown
- UINT16 ResetTimer; ///< Reset Timer
- UINT16 IsoTimer; ///< Isolation Timer
-} POWER_GATE_DATA;
-
-#define GNB_STRINGIZE(x) #x
-#define GNB_SERVICE_DEFINITIONS(x) GNB_STRINGIZE (Services/x/x.h)
-#define GNB_MODULE_DEFINITIONS(x) GNB_STRINGIZE (Modules/x/x.h)
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Common/GnbFuseTable.h b/src/vendorcode/amd/agesa/Proc/GNB/Common/GnbFuseTable.h
deleted file mode 100644
index fe41a39..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Common/GnbFuseTable.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Graphics controller BIF straps control services.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 38902 $ @e \$Date: 2010-10-02 02:01:38 +0800 (Sat, 02 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-#ifndef _GNBFUSETABLE_H_
-#define _GNBFUSETABLE_H_
-
-#pragma pack (push, 1)
-
-#define PP_FUSE_MAX_NUM_DPM_STATE 5
-#define PP_FUSE_MAX_NUM_SW_STATE 6
-/// Fuse definition structure
-typedef struct {
- UINT8 PPlayTableRev; ///< PP table revision
- UINT8 SclkDpmValid[6]; ///< Valid DPM states
- UINT8 SclkDpmDid[5]; ///< Sclk DPM DID
- UINT8 SclkDpmVid[5]; ///< Sclk DPM VID
- UINT8 SclkDpmCac[5]; ///< Sclk DPM Cac
- UINT8 PolicyFlags[6]; ///< State policy flags
- UINT8 PolicyLabel[6]; ///< State policy label
- UINT8 VclkDid[4]; ///< VCLK DID
- UINT8 DclkDid[4]; ///< DCLK DID
- UINT8 SclkThermDid; ///< Thermal SCLK
- UINT8 VclkDclkSel[6]; ///< Vclk/Dclk selector
- UINT8 LclkDpmValid[4]; ///< Valid Lclk DPM states
- UINT8 LclkDpmDid[4]; ///< Lclk DPM DID
- UINT8 LclkDpmVid[4]; ///< Lclk DPM VID
- UINT8 DisplclkDid[4]; ///< Displclk DID
- UINT8 PcieGen2Vid; ///< Pcie Gen 2 VID
- UINT8 MainPllId; ///< Main PLL Id from fuses
- UINT8 WrCkDid; ///< WRCK SMU clock Divisor
-} PP_FUSE_ARRAY;
-
-#pragma pack (pop)
-
-#endif
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Common/GnbGfx.h b/src/vendorcode/amd/agesa/Proc/GNB/Common/GnbGfx.h
deleted file mode 100644
index 65212e2..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Common/GnbGfx.h
+++ /dev/null
@@ -1,290 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Initialize GFX configuration data structure.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 38882 $ @e \$Date: 2010-09-30 18:42:57 -0700 (Thu, 30 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _GNBGFX_H_
-#define _GNBGFX_H_
-
-//#ifndef PVOID
-// typedef UINT64 PVOID;
-//#endif
-
-#define DEVICE_DFP 0x1
-#define DEVICE_CRT 0x2
-#define DEVICE_LCD 0x3
-
-
-#define CONNECTOR_DISPLAYPORT_ENUM 0x3013
-#define CONNECTOR_HDMI_TYPE_A_ENUM 0x300c
-#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM 0x3003
-#define CONNECTOR_DUAL_LINK_DVI_D_ENUM 0x3004
-#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM 0x3001
-#define CONNECTOR_DUAL_LINK_DVI_I_ENUM 0x3002
-#define CONNECTOR_VGA_ENUM 0x3005
-#define CONNECTOR_LVDS_ENUM 0x300E
-#define CONNECTOR_eDP_ENUM 0x3014
-#define CONNECTOR_LVDS_eDP_ENUM 0x3016
-//Travis DP to VGA:
-#define ENCODER_TRAVIS_ENUM_ID1 0x2123
-//Travis DP to LVDS:
-#define ENCODER_TRAVIS_ENUM_ID2 0x2223
-//Hudson-2 NutMeg DP to VGA:
-#define ENCODER_ALMOND_ENUM_ID1 0x2122
-#define ENCODER_NOT_PRESENT 0x0000
-
-
-#define ATOM_DEVICE_CRT1_SUPPORT 0x0001
-#define ATOM_DEVICE_DFP1_SUPPORT 0x0008
-#define ATOM_DEVICE_DFP6_SUPPORT 0x0040
-#define ATOM_DEVICE_DFP2_SUPPORT 0x0080
-#define ATOM_DEVICE_DFP3_SUPPORT 0x0200
-#define ATOM_DEVICE_DFP4_SUPPORT 0x0400
-#define ATOM_DEVICE_DFP5_SUPPORT 0x0800
-#define ATOM_DEVICE_LCD1_SUPPORT 0x0002
-
-
-/// UMA Steering to either Garlic bus or Enum bus
-typedef enum {
- Garlic, ///< Garlic
- Onion ///< Onion
-} UMA_STEERING;
-
-/// GFX enable Policy
-typedef enum {
- GfxEnableAuto, ///< Auto
- GfxEnableForcePrimary, ///< GFX Enable Force As Primary
- GfxEnableForceSecondary ///< GFX Enable Force As Secondary
-} GFX_ENABLE_POLICY;
-
-/// User Options
-typedef enum {
- OptionDisabled, ///< Disabled
- OptionEnabled ///< Enabled
-} CONTROL_OPTION;
-
-/// GFX enable Policy
-typedef enum {
- GmcPowerGatingDisabled, ///< Disable Power gating
- GmcPowerGatingStutterOnly, ///< GMC Stutter Only mode
- GmcPowerGatingWidthStutter ///< GMC Power gating with Stutter mode
-} GMC_POWER_GATING;
-
-/// Internal GFX mode
-typedef enum {
- GfxControllerLegacyBridgeMode, ///< APC bridge Legacy mode
- GfxControllerPcieEndpointMode, ///< IGFX PCIE Bus 0, Device 1
-} GFX_CONTROLLER_MODE;
-
-/// Graphics Platform Configuration
-typedef struct {
- PVOID StdHeader; ///< Standard Header
- PCI_ADDR GfxPciAddress; ///< Graphics PCI Address
- UMA_INFO UmaInfo; ///< UMA Information
- UINT32 GmmBase; ///< GMM Base
- UINT8 GnbHdAudio; ///< Control GFX HD Audio controller(Used for HDMI and DP display output),
- ///< essentially it enables function 1 of graphics device.
- ///< @li 0 = HD Audio disable
- ///< @li 1 = HD Audio enable
- UINT8 AbmSupport; ///< Automatic adjust LVDS/eDP Back light level support.It is
- ///< characteristic specific to display panel which used by platform design.
- ///< @li 0 = ABM support disabled
- ///< @li 1 = ABM support enabled
- UINT8 DynamicRefreshRate; ///< Adjust refresh rate on LVDS/eDP.
- UINT16 LcdBackLightControl; ///< The PWM frequency to LCD backlight control.
- ///< If equal to 0 backlight not controlled by iGPU.
- UINT32 AmdPlatformType; ///< Platform type
- UMA_STEERING UmaSteering; ///< UMA Steering
- GFX_ENABLE_POLICY ForceGfxMode; ///< Force GFX Mode
- CONTROL_OPTION GmcClockGating; ///< Clock gating
- BOOLEAN GfxFusedOff; ///< Record if GFX is fused off.
- GMC_POWER_GATING GmcPowerGating; ///< Gmc Power Gating.
- UINT8 Gnb3dStereoPinIndex; ///< 3D Stereo Pin ID
- GFX_CONTROLLER_MODE GfxControllerMode; ///< Gfx controller mode
- UINT16 LvdsSpreadSpectrum; ///< Spread spectrum value in 0.01 %
- UINT16 LvdsSpreadSpectrumRate; ///< Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz
-} GFX_PLATFORM_CONFIG;
-
-
-typedef UINT32 ULONG;
-typedef UINT16 USHORT;
-typedef UINT8 UCHAR;
-
-/// Driver interface header structure
-typedef struct _ATOM_COMMON_TABLE_HEADER {
- USHORT usStructureSize; ///< Structure size
- UCHAR ucTableFormatRevision; ///< Format revision number
- UCHAR ucTableContentRevision; ///< Contents revision number
-} ATOM_COMMON_TABLE_HEADER;
-
-/// Link ping mapping for DP/eDP/LVDS
-typedef struct _ATOM_DP_CONN_CHANNEL_MAPPING {
- UCHAR ucDP_Lane0_Source :2; ///< Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
- UCHAR ucDP_Lane1_Source :2; ///< Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
- UCHAR ucDP_Lane2_Source :2; ///< Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
- UCHAR ucDP_Lane3_Source :2; ///< Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
-} ATOM_DP_CONN_CHANNEL_MAPPING;
-
-/// Link ping mapping for DVI/HDMI
-typedef struct _ATOM_DVI_CONN_CHANNEL_MAPPING {
- UCHAR ucDVI_DATA2_Source :2; ///< Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
- UCHAR ucDVI_DATA1_Source :2; ///< Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
- UCHAR ucDVI_DATA0_Source :2; ///< Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
- UCHAR ucDVI_CLK_Source :2; ///< Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
-} ATOM_DVI_CONN_CHANNEL_MAPPING;
-
-
-/// External Display Path
-typedef struct _EXT_DISPLAY_PATH {
- USHORT usDeviceTag; ///< A bit vector to show what devices are supported
- USHORT usDeviceACPIEnum; ///< 16bit device ACPI id.
- USHORT usDeviceConnector; ///< A physical connector for displays to plug in, using object connector definitions
- UCHAR ucExtAUXDDCLutIndex; ///< An index into external AUX/DDC channel LUT
- UCHAR ucExtHPDPINLutIndex; ///< An index into external HPD pin LUT
- USHORT usExtEncoderObjId; ///< external encoder object id
- union { ///< Lane mapping
- UCHAR ucChannelMapping; ///< lane mapping on connector (ucChannelMapping=0 use default)
- ATOM_DP_CONN_CHANNEL_MAPPING asDPMapping; ///< lane mapping on connector (ucChannelMapping=0 use default)
- ATOM_DVI_CONN_CHANNEL_MAPPING asDVIMapping; ///< lane mapping on connector (ucChannelMapping=0 use default)
- } ChannelMapping;
- UCHAR ucReserved; ///< Reserved
- USHORT usReserved[2]; ///< Reserved
-} EXT_DISPLAY_PATH;
-
-/// External Display Connection Information
-typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO {
- ATOM_COMMON_TABLE_HEADER sHeader; ///< Standard Header
- UCHAR ucGuid [16]; ///< Guid
- EXT_DISPLAY_PATH sPath[7]; ///< External Display Path
- UCHAR ucChecksum; ///< Checksum
- UCHAR uc3DStereoPinId; ///< 3D Stereo Pin ID
- UCHAR Reserved [6]; ///< Reserved
-} ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO;
-
-/// Displclk to VID relation table
-typedef struct _ATOM_CLK_VOLT_CAPABILITY {
- ULONG ulVoltageIndex; ///< The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table
- ULONG ulMaximumSupportedCLK;///< Maximum clock supported with specified voltage index, unit in 10kHz
-} ATOM_CLK_VOLT_CAPABILITY;
-
-/// Available Sclk table
-typedef struct _ATOM_AVAILABLE_SCLK_LIST {
- ULONG ulSupportedSCLK; ///< Maximum clock supported with specified voltage index, unit in 10kHz
- USHORT usVoltageIndex; ///< The Voltage Index indicated by FUSE for specified SCLK
- USHORT usVoltageID; ///< The Voltage ID indicated by FUSE for specified SCLK
-} ATOM_AVAILABLE_SCLK_LIST;
-
-/// Integrate System Info Table is used for Llano/Ontario APU
-typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 {
- ATOM_COMMON_TABLE_HEADER sHeader; ///< Standard Header
- ULONG ulBootUpEngineClock; ///< VBIOS bootup Engine clock frequency, in 10kHz unit.
- ULONG ulDentistVCOFreq; ///< Dentist VCO clock in 10kHz unit.
- ULONG ulBootUpUMAClock; ///< System memory boot up clock frequency in 10Khz unit.
- ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; ///< Report Display clock voltage requirement.
- ULONG ulBootUpReqDisplayVector; /**< VBIOS boot up display IDs, following are supported devices in Llano/Fam 12 and Ontario/Fam 14 projects:
- * ATOM_DEVICE_CRT1_SUPPORT 0x0001
- * ATOM_DEVICE_CRT2_SUPPORT 0x0010
- * ATOM_DEVICE_DFP1_SUPPORT 0x0008
- * ATOM_DEVICE_DFP6_SUPPORT 0x0040
- * ATOM_DEVICE_DFP2_SUPPORT 0x0080
- * ATOM_DEVICE_DFP3_SUPPORT 0x0200
- * ATOM_DEVICE_DFP4_SUPPORT 0x0400
- * ATOM_DEVICE_DFP5_SUPPORT 0x0800
- * ATOM_DEVICE_LCD1_SUPPORT 0x0002
- */
- ULONG ulOtherDisplayMisc; ///< Other display related flags, not defined yet.
- ULONG ulGPUCapInfo; ///< TBD
- ULONG ulSB_MMIO_Base_Addr; ///< Physical Base address to SB MMIO space. Driver need to initialize it for SMU usage.
- USHORT usRequestedPWMFreqInHz; ///< Panel Required PWM frequency. if this parameter is 0 PWM from to control LCD Backlight will be disabled.
- UCHAR ucHtcTmpLmt; ///< HTC temperature limit.The processor enters HTC-active state when Tctl reaches or exceeds HtcHystLmt.
- UCHAR ucHtcHystLmt; ///< HTC hysteresis.The processor exits HTC-active state when Tctl is less than HtcTmpLmt minus HtcHystLmt.
- ULONG ulMinEngineClock; ///< Min SCLK
- ULONG ulSystemConfig; /**< System configuration
- * @li BIT[0] - 0: PCIE Power Gating Disabled, 1: PCIE Power Gating Enabled.
- * @li BIT[1] - 0: DDR-DLL shut-down feature disabled, 1: DDR-DLL shut-down feature enabled.
- * @li BIT[2] - 0: DDR-PLL Power down feature disabled, 1: DDR-PLL Power down feature enabled.
- */
- ULONG ulCPUCapInfo; ///< TBD
- USHORT usNBP0Voltage; ///< VID for voltage on NB P0 State
- USHORT usNBP1Voltage; ///< VID for voltage on NB P1 State
- USHORT usBootUpNBVoltage; ///< Voltage Index of GNB voltage configured by SBIOS, which is sufficient to support VBIOS DISPCLK requirement.
- USHORT usExtDispConnInfoOffset; ///< Offset to sExtDispConnInfo inside the structure
- USHORT usPanelRefreshRateRange; /**< Bit vector for LVDS/eDP supported refresh rate range. If DRR is enabled, 2 of the bits must be set.
- * SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004
- * SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008
- * SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010
- * SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020
- */
- UCHAR ucMemoryType; ///< Memory type (3 for DDR3)
- UCHAR ucUMAChannelNumber; ///< System memory channel numbers.
- ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10]; ///< Arrays with values for CSR M3 arbiter for default.
- ULONG ulCSR_M3_ARB_CNTL_UVD[10]; ///< Arrays with values for CSR M3 arbiter for UVD playback.
- ULONG ulCSR_M3_ARB_CNTL_FS3D[10]; ///< Arrays with values for CSR M3 arbiter for Full Screen 3D applications.
- ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; ///< Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high
- ULONG ulGMCRestoreResetTime; ///< GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns.
- ULONG ulMinimumNClk; ///< Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz.
- ULONG ulIdleNClk; ///< NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
- ULONG ulDDR_DLL_PowerUpTime; ///< DDR PHY DLL power up time. Unit in ns.
- ULONG ulDDR_PLL_PowerUpTime; ///< DDR PHY PLL power up time. Unit in ns
- USHORT usPCIEClkSSPercentage; ///< usPCIEClkSSPercentage
- USHORT usPCIEClkSSType; ///< usPCIEClkSSType
- USHORT usLvdsSSPercentage; ///< usLvdsSSPercentage
- USHORT usLvdsSSpreadRateIn10Hz; ///< usLvdsSSpreadRateIn10Hz
- USHORT usHDMISSPercentage; ///< usHDMISSPercentage
- USHORT usHDMISSpreadRateIn10Hz; ///< usHDMISSpreadRateIn10Hz
- USHORT usDVISSPercentage; ///< usDVISSPercentage
- USHORT usDVISSpreadRateIn10Hz; ///< usDVISSpreadRateIn10Hz
- ULONG ulReserved3[21]; ///< Reserved
- ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; ///< Display connector definition
-} ATOM_INTEGRATED_SYSTEM_INFO_V6;
-
-/// this Table is used for Llano/Ontario APU
-typedef struct _ATOM_FUSION_SYSTEM_INFO_V1 {
- ATOM_INTEGRATED_SYSTEM_INFO_V6 sIntegratedSysInfo; ///< Refer to ATOM_INTEGRATED_SYSTEM_INFO_V6 definition.
- ULONG ulPowerplayTable[128]; ///< This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0]
-} ATOM_FUSION_SYSTEM_INFO_V1;
-
-#define GNB_SBDFO MAKE_SBDFO(0, 0, 0, 0, 0)
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Common/GnbGfxFamServices.h b/src/vendorcode/amd/agesa/Proc/GNB/Common/GnbGfxFamServices.h
deleted file mode 100644
index 42e4ef3..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Common/GnbGfxFamServices.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe family specific services.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _GNBGFXFAMSERVICES_H_
-#define _GNBGFXFAMSERVICES_H_
-
-
-AGESA_STATUS
-GfxFmMapEngineToDisplayPath (
- IN PCIe_ENGINE_CONFIG *Engine,
- OUT EXT_DISPLAY_PATH *DisplayPathList,
- IN GFX_PLATFORM_CONFIG *Gfx
- );
-
-AGESA_STATUS
-GfxFmCalculateClock (
- IN UINT8 Did,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Common/GnbLibFeatures.c b/src/vendorcode/amd/agesa/Proc/GNB/Common/GnbLibFeatures.c
deleted file mode 100644
index afa6522..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Common/GnbLibFeatures.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/* $NoKeywords:$ */
- /**
- * @file
- *
- * GNB register access services.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 40151 $ @e \$Date: 2010-10-20 06:38:17 +0800 (Wed, 20 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "Porting.h"
-#include "AMD.h"
-#include "Gnb.h"
-#include "OptionGnb.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_COMMON_GNBLIBFEATURES_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * DIspathc feature tanle
- *
- *
- */
-
-AGESA_STATUS
-GnbLibDispatchFeatures (
- IN OPTION_GNB_CONFIGURATION *ConfigTable,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_STATUS Status;
- AGESA_STATUS AgesaStatus;
- AgesaStatus = AGESA_SUCCESS;
-
- while (ConfigTable->GnbFeature != NULL) {
- Status = ConfigTable->GnbFeature (StdHeader);
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
- ConfigTable++;
- }
- return AgesaStatus;
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Feature stub function
- *
- *
- */
-
-AGESA_STATUS
-GnbCommonFeatureStub (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- return AGESA_SUCCESS;
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Common/GnbLibFeatures.h b/src/vendorcode/amd/agesa/Proc/GNB/Common/GnbLibFeatures.h
deleted file mode 100644
index 05b765c..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Common/GnbLibFeatures.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * GNB register access services.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 40151 $ @e \$Date: 2010-10-20 06:38:17 +0800 (Wed, 20 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _GNBLIBFEATURES_H_
-#define _GNBLIBFEATURES_H_
-
-
-AGESA_STATUS
-GnbLibDispatchFeatures (
- IN OPTION_GNB_CONFIGURATION *ConfigTable,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Common/GnbPcie.h b/src/vendorcode/amd/agesa/Proc/GNB/Common/GnbPcie.h
deleted file mode 100644
index 2a819b2..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Common/GnbPcie.h
+++ /dev/null
@@ -1,352 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe component definitions.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 38931 $ @e \$Date: 2010-10-01 15:50:05 -0700 (Fri, 01 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _PCIEDEFS_H_
-#define _PCIEDEFS_H_
-
-#pragma pack (push, 1)
-
-#ifndef MAX_NUMBER_OF_COMPLEXES
- #define MAX_NUMBER_OF_COMPLEXES 1
-#endif
-
-#define DESCRIPTOR_ALLOCATED 0x40000000ull
-#define DESCRIPTOR_VIRTUAL 0x20000000ull
-#define DESCRIPTOR_COMPLEX 0x08000000ull
-#define DESCRIPTOR_SILICON 0x04000000ull
-#define DESCRIPTOR_PCIE_WRAPPER 0x00400000ull
-#define DESCRIPTOR_DDI_WRAPPER 0x00200000ull
-#define DESCRIPTOR_PCIE_ENGINE 0x00040000ull
-#define DESCRIPTOR_DDI_ENGINE 0x00020000ull
-#define DESCRIPTOR_ALL_WRAPPERS (DESCRIPTOR_DDI_WRAPPER | DESCRIPTOR_PCIE_WRAPPER)
-#define DESCRIPTOR_ALL_ENGINES (DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_PCIE_ENGINE)
-
-#define UNUSED_LANE_ID 128
-#define PCIE_LINK_RECEIVER_DETECTION_POOLING (60 * 1000)
-#define PCIE_LINK_L0_POOLING (60 * 1000)
-#define PCIE_LINK_GPIO_RESET_ASSERT_TIME (2 * 1000)
-#define PCIE_LINK_RESET_TO_TRAINING_TIME (2 * 1000)
-
-#define IS_LAST_DESCRIPTOR(x) (x->Flags & DESCRIPTOR_TERMINATE_LIST) == 0
-#define IS_VALID_DESCRIPTOR(x) ((x->Flags & DESCRIPTOR_ALLOCATED) != 0)
-
-// Get lowes phy lane on engine
-#define PcieUtilGetLoPhyLane(Engine) ((Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? Engine->EngineData.EndLane : Engine->EngineData.StartLane)
-// Get highest phy lane on engine
-#define PcieUtilGetHiPhyLane(Engine) ((Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? Engine->EngineData.StartLane : Engine->EngineData.EndLane)
-// Get number of lanes on wrapper
-#define PcieLibWrapperNumberOfLanes(Wrapper) ((UINT8)(Wrapper->EndPhyLane - Wrapper->StartPhyLane + 1))
-// Check if virtual descriptor
-#define PcieLibIsVirtualDesciptor(Descriptor) ((Descriptor->Flags & DESCRIPTOR_VIRTUAL) != 0)
-// Check if it is allocated descriptor
-#define PcieLibIsEngineAllocated(Descriptor) ((Descriptor->Flags & DESCRIPTOR_ALLOCATED) != 0)
-// Check if it is last descriptor in list
-#define PcieLibIsLastDescriptor(Descriptor) ((Descriptor->Flags & DESCRIPTOR_TERMINATE_LIST) != 0)
-// Check if descriptor a PCIe engine
-#define PcieLibIsPcieEngine(Descriptor) ((Descriptor->Flags & DESCRIPTOR_PCIE_ENGINE) != 0)
-// Check if descriptor a DDI engine
-#define PcieLibIsDdiEngine(Descriptor) ((Descriptor->Flags & DESCRIPTOR_DDI_ENGINE) != 0)
-// Check if descriptor a DDI wrapper
-#define PcieLibIsDdiWrapper(Descriptor) ((Descriptor->Flags & DESCRIPTOR_DDI_WRAPPER) != 0)
-// Check if descriptor a PCIe wrapper
-#define PcieLibIsPcieWrapper(Descriptor) ((Descriptor->Flags & DESCRIPTOR_PCIE_WRAPPER) != 0)
-// Check if descriptor a PCIe wrapper
-#define PcieLibGetNextDescriptor(Descriptor) ((((Descriptor->Flags & DESCRIPTOR_TERMINATE_LIST) != 0) ? NULL : (++Descriptor)))
-
-
-
-#define LANE_TYPE_PCIE_ALL 0x0001
-#define LANE_TYPE_PCIE_ALLOCATED 0x0002
-#define LANE_TYPE_PCIE_ACTIVE 0x0004
-#define LANE_TYPE_PCIE_SB 0x0008
-#define LANE_TYPE_PCIE_HOTPLUG 0x0010
-
-#define LANE_TYPE_PCIE_LANES 0x000FFF
-
-#define LANE_TYPE_DDI_ALL 0x1000
-#define LANE_TYPE_DDI_ALLOCATED 0x2000
-#define LANE_TYPE_DDI_ACTIVE 0x4000
-
-#define LANE_TYPE_DDI_LANES 0xFFF000
-
-#define LANE_TYPE_ALL (LANE_TYPE_PCIE_ALL | LANE_TYPE_DDI_ALL)
-#define LANE_TYPE_ACTIVE (LANE_TYPE_PCIE_ACTIVE | LANE_TYPE_DDI_ACTIVE)
-#define LANE_TYPE_ALLOCATED (LANE_TYPE_PCIE_ALLOCATED | LANE_TYPE_DDI_ALLOCATED)
-
-typedef UINT64 PPCIe_ENGINE_CONFIG;
-typedef UINT64 PPCIe_WRAPPER_CONFIG;
-typedef UINT64 PPCIe_SILICON_CONFIG;
-
-#define INIT_STATUS_PCIE_PORT_GEN2_RECOVERY 0x00000001ull
-#define INIT_STATUS_PCIE_PORT_BROKEN_LANE_RECOVERY 0x00000002ull
-#define INIT_STATUS_PCIE_PORT_TRAINING_FAIL 0x00000004ull
-#define INIT_STATUS_PCIE_TRAINING_SUCCESS 0x00000008ull
-#define INIT_STATUS_PCIE_EP_NOT_PRESENT 0x00000010ull
-#define INIT_STATUS_PCIE_PORT_IN_COMPLIANCE 0x00000020ull
-#define INIT_STATUS_DDI_ACTIVE 0x00000040ull
-#define INIT_STATUS_ALLOCATED 0x00000080ull
-
-#define PCIE_PORT_GEN_CAP_BOOT 0x00000001
-#define PCIE_PORT_GEN_CAP_MAX 0x00000002
-#define PCIE_GLOBAL_GEN_CAP_ALL_PORTS 0x00000010
-#define PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS 0x00000011
-#define PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS 0x00000012
-
-/// PCIe port configuration info
-typedef struct {
- PCIe_PORT_DATA PortData; ///< Port data
- UINT16 StartCoreLane; ///< Start Core Lane
- UINT16 EndCoreLane; ///< End Core lane
- UINT8 NativeDevNumber; ///< Native PCI device number of the port
- UINT8 NativeFunNumber; ///< Native PCI function number of the port
- UINT8 CoreId; ///< PCIe core ID
- UINT8 PortId; ///< Port id on wrapper
- PCI_ADDR Address; ///< PCI address of the port
- BOOLEAN IsSB; ///< Is it NB to SB link?
- UINT8 State; ///< Training state
- UINT32 TimeStamp; ///< Time stamp used to during training process
- UINT8 GfxWrkRetryCount; ///< Number of retry for GFX workaround
-} PCIe_PORT_CONFIG;
-
-/// DDI (Digital Display Interface) configuration info
-typedef struct {
- PCIe_DDI_DATA DdiData; ///< DDI Data
- UINT8 DisplayPriorityIndex; ///< Display priority index
- UINT8 ConnectorId; ///< Connector id determined by enumeration
- UINT8 DisplayDeviceId; ///< Display device id determined by enumeration
-} PCIe_DDI_CONFIG;
-
-/// Engine configuration data
-typedef struct {
- UINT32 Flags; /**< Descriptor flags
- * @li @b Bit31 - last descriptor on wrapper
- * @li @b Bit30 - Descriptor allocated for PCIe port or DDI
- */
- PPCIe_WRAPPER_CONFIG Wrapper; ///< Pointer to parent wrapper
- PCIe_ENGINE_DATA EngineData; ///< Engine Data
- UINT32 InitStatus; ///< Initialization Status
- UINT8 Scratch; ///< Scratch pad
- union {
- PCIe_PORT_CONFIG Port; ///< PCIe port configuration data
- PCIe_DDI_CONFIG Ddi; ///< DDI configuration data
- } Type;
-} PCIe_ENGINE_CONFIG;
-
-#define PcieEngineGetParentWrapper(mEnginerPtr) ((PCIe_WRAPPER_CONFIG *) (mEnginerPtr->Wrapper))
-
-/// Wrapper configuration data
-typedef struct {
- UINT32 Flags; /**< Descriptor flags
- * @li @b Bit31 - last descriptor on silicon
- */
- UINT8 WrapId; ///< Wrapper ID
- UINT8 NumberOfPIFs; ///< Number of PIFs on wrapper
- UINT8 StartPhyLane; ///< Start PHY Lane
- UINT8 EndPhyLane; ///< End PHY Lane
- UINT8 StartPcieCoreId; ///< Start PCIe Core ID
- UINT8 EndPcieCoreId; ///< End PCIe Core ID
- struct {
- UINT8 PowerOffUnusedLanes:1; ///< Power Off unused lanes
- UINT8 PowerOffUnusedPlls:1; ///< Power Off unused Plls
- UINT8 ClkGating:1; ///< TXCLK gating
- UINT8 LclkGating:1; ///< LCLK gating
- UINT8 TxclkGatingPllPowerDown:1; ///< TXCLK clock gating PLL power down
- UINT8 PllOffInL1:1; ///< PLL off in L1
- } Features;
- PPCIe_ENGINE_CONFIG EngineList; ///< Pointer to Engine list
- PPCIe_SILICON_CONFIG Silicon; ///< Pointer to parent silicon
- PVOID FmWrapper; ///< Pointer to family Specific configuration data
-} PCIe_WRAPPER_CONFIG;
-
-
-#define PcieWrapperGetEngineList(mWrapperPtr) ((PCIe_ENGINE_CONFIG *)(mWrapperPtr->EngineList))
-#define PcieWrapperGetParentSilicon(mWrapperPtr) ((PCIe_SILICON_CONFIG *)(mWrapperPtr->Silicon))
-
-/// Silicon configuration data
-typedef struct {
- UINT32 Flags; /**< Descriptor flags
- * @li @b Bit31 - last descriptor on complex
- */
- PCI_ADDR Address; ///< PCI address of GNB host bridge
- PPCIe_WRAPPER_CONFIG WrapperList; ///< Pointer to wrapper list
- PVOID FmSilicon; ///< Pointer to family Specific configuration data
-} PCIe_SILICON_CONFIG;
-
-#define PcieSiliconGetWrapperList(mSiliconPtr) ((PCIe_WRAPPER_CONFIG *) (mSiliconPtr->WrapperList))
-
-/// Complex configuration data
-typedef struct {
- UINT32 Flags; /**< Descriptor flags
- * @li @b Bit31 - last descriptor on platform
- */
- UINT8 SocketId; ///< Processor socket ID
- PPCIe_SILICON_CONFIG SiliconList; ///< Pointer to silicon list
-} PCIe_COMPLEX_CONFIG;
-
-#define PcieComplexGetSiliconList(mComplexPtr) ((PCIe_SILICON_CONFIG *)(UINTN)((mComplexPtr)->SiliconList))
-
-/// PCIe platform configuration info
-typedef struct {
- PVOID StdHeader; ///< Standard configuration header
- UINT64 This; ///< base structure Base
- UINT32 LinkReceiverDetectionPooling; ///< Receiver pooling detection time in us.
- UINT32 LinkL0Pooling; ///< Pooling for link to get to L0 in us
- UINT32 LinkGpioResetAssertionTime; ///< Gpio reset assertion time in us
- UINT32 LinkResetToTrainingTime; ///< Time duration between deassert GPIO reset and release training in us ///
- UINT8 GfxCardWorkaround; ///< GFX Card Workaround
- UINT8 PsppPolicy; ///< PSPP policy
- PCIe_COMPLEX_CONFIG ComplexList[MAX_NUMBER_OF_COMPLEXES]; ///<
-} PCIe_PLATFORM_CONFIG;
-
-/// PCIe Engine Description
-typedef struct {
- UINT32 Flags; /**< Descriptor flags
- * @li @b Bit31 - last descriptor on wrapper
- * @li @b Bit30 - Descriptor allocated for PCIe port or DDI
- */
- PCIe_ENGINE_DATA EngineData; ///< Engine Data
-} PCIe_ENGINE_DESCRIPTOR;
-
-/// PCIe Link Training State
-typedef enum {
- LinkStateResetAssert, ///< Assert port GPIO reset
- LinkStateResetDuration, ///< Timeout for reset duration
- LinkStateResetExit, ///< Deassert port GPIO reset
- LinkTrainingResetTimeout, ///< Port GPIO reset timeout
- LinkStateReleaseTraining, ///< Release link training
- LinkStateDetectPresence, ///< Detect device presence
- LinkStateDetecting, ///< Detect link training.
- LinkStateBrokenLane, ///< Check and handle broken lane
- LinkStateGen2Fail, ///< Check and handle device that fail training if GEN2 capability advertised
- LinkStateL0, ///< Device trained to L0
- LinkStateVcoNegotiation, ///< Check VCO negotiation complete
- LinkStateRetrain, ///< Force retrain link.
- LinkStateTrainingFail, ///< Link training fail
- LinkStateTrainingSuccess, ///< Link training success
- LinkStateGfxWorkaround, ///< GFX workaround
- LinkStateCompliance, ///< Link in compliance mode
- LinkStateDeviceNotPresent, ///< Link is not connected
- LinkStateTrainingCompleted ///< Link training completed
-} PCIE_LINK_TRAINING_STATE;
-
-/// PCIe Port Visibility
-typedef enum {
- UnhidePorts, ///< Command to unhide port
- HidePorts, ///< Command to hide unused ports
-} PCIE_PORT_VISIBILITY;
-
-
-/// Table Register Entry
-typedef struct {
- UINT16 Reg; ///< Address
- UINT32 Mask; ///< Mask
- UINT32 Data; ///< Data
-} PCIE_PORT_REGISTER_ENTRY;
-
-/// Table Register Entry
-typedef struct {
- UINT32 Reg; ///< Address
- UINT32 Mask; ///< Mask
- UINT32 Data; ///< Data
-} PCIE_HOST_REGISTER_ENTRY;
-
-///Link ASPM info
-typedef struct {
- PCI_ADDR DownstreamPort; ///< PCI address of downstream port
- PCIE_ASPM_TYPE DownstreamAspm ; ///< Downstream Device Aspm
- PCI_ADDR UpstreamPort; ///< PCI address of upstream port
- PCIE_ASPM_TYPE UpstreamAspm; ///< Upstream Device Capability
- PCIE_ASPM_TYPE RequestedAspm; ///< Requested ASPM
-} PCIe_LINK_ASPM;
-
-///PCIe ASPM Latency Information
-typedef struct {
- UINT8 MaxL0sExitLatency; ///< Max L0s exit latency in us
- UINT8 MaxL1ExitLatency; ///< Max L1 exit latency in us
-} PCIe_ASPM_LATENCY_INFO;
-
-/// PCI address association
-typedef struct {
- UINT8 NewDeviceAddress; ///< New PCI address (Device,Fucntion)
- UINT8 NativeDeviceAddress; ///< Native PCI address (Device,Fucntion)
-} PCI_ADDR_LIST;
-
-/// The return status for GFX Card Workaround.
-typedef enum {
- GFX_WORKAROUND_DEVICE_NOT_READY, ///< GFX Workaround device is not ready.
- GFX_WORKAROUND_RESET_DEVICE, ///< GFX Workaround device need reset.
- GFX_WORKAROUND_SUCCESS ///< The service completed normally.
-} GFX_WORKAROUND_STATUS;
-
-/// GFX workaround control
-typedef enum {
- GfxWorkaroundDisable, ///< GFX Workaround disabled
- GfxWorkaroundEnable ///< GFX Workaround enabled
-} GFX_WORKAROUND_CONTROL;
-
-/// PIF lane power state
-typedef enum {
- PifPowerStateL0, ///<
- PifPowerStateLS1, ///<
- PifPowerStateLS2, ///<
- PifPowerStateOff = 0x7, ///<
-} PCIE_PIF_POWER_STATE;
-
-/// PIF lane power control
-typedef enum {
- PowerDownPifs, ///<
- PowerUpPifs ///<
-} PCIE_PIF_POWER_CONTROL;
-
-///PLL rumup time
-typedef enum {
- NormalRampup, ///<
- LongRampup, ///<
-} PCIE_PLL_RAMPUP_TIME;
-
-#pragma pack (pop)
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Common/GnbPcieFamServices.h b/src/vendorcode/amd/agesa/Proc/GNB/Common/GnbPcieFamServices.h
deleted file mode 100644
index 975f30b..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Common/GnbPcieFamServices.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe family specific services.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _GNBPCIEFAMSERVICES_H_
-#define _GNBPCIEFAMSERVICES_H_
-
-
-AGESA_STATUS
-PcieFmGetComplexDataLength (
- IN UINT32 SocketId,
- OUT UINTN *Length
- );
-
-AGESA_STATUS
-PcieFmBuildComplexConfiguration (
- OUT VOID *Buffer,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-PcieFmConfigureEnginesLaneAllocation (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIE_ENGINE_TYPE EngineType,
- IN UINT8 ConfigurationId
- );
-
-AGESA_STATUS
-PcieFmGetCoreConfigurationValue (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN UINT8 CoreId,
- IN UINT64 ConfigurationSignature,
- IN UINT8 *ConfigurationValue
- );
-
-BOOLEAN
-PcieFmCheckPortPciDeviceMapping (
- IN PCIe_PORT_DESCRIPTOR *PortDescriptor,
- IN PCIe_ENGINE_CONFIG *Engine
- );
-
-AGESA_STATUS
-PcieFmMapPortPciAddress (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-BOOLEAN
-PcieFmCheckPortPcieLaneCanBeMuxed (
- IN PCIe_PORT_DESCRIPTOR *PortDescriptor,
- IN PCIe_ENGINE_CONFIG *Engine
- );
-
-CONST CHAR8*
-PcieFmDebugGetCoreConfigurationString (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN UINT8 ConfigurationValue
- );
-
-CONST CHAR8*
-PcieFmDebugGetWrapperNameString (
- IN PCIe_WRAPPER_CONFIG *Wrapper
- );
-
-CONST CHAR8*
-PcieFmDebugGetHostRegAddressSpaceString (
- IN UINT16 AddressFrame
- );
-
-PCIE_LINK_SPEED_CAP
-PcieFmGetLinkSpeedCap (
- IN UINT32 Flags,
- IN PCIe_ENGINE_CONFIG *Engine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Common/GnbRegistersON.h b/src/vendorcode/amd/agesa/Proc/GNB/Common/GnbRegistersON.h
deleted file mode 100644
index 2095f0e..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Common/GnbRegistersON.h
+++ /dev/null
@@ -1,12425 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Register definitions
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision:$ @e \$Date:$
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************
- *
- */
-
-#ifndef _GNBREGISTERSON_H_
-#define _GNBREGISTERSON_H_
-#define TYPE_D0F0 0x1
-#define TYPE_D0F0x64 0x2
-#define TYPE_D0F0x98 0x3
-#define TYPE_D0F0xE4 0x5
-#define TYPE_DxF0 0x6
-#define TYPE_DxF0xE4 0x7
-#define TYPE_D18F1 0xb
-#define TYPE_D18F2 0xc
-#define TYPE_D18F3 0xd
-#define TYPE_MSR 0x10
-#define TYPE_D1F0 0x11
-#define TYPE_GMM 0x12
-#define D18F2x9C 0xe
-#define GMM 0x11
-#ifndef WRAP_SPACE
- #define WRAP_SPACE(w, x) (0x01300000 | (w << 16) | (x))
-#endif
-#ifndef CORE_SPACE
- #define CORE_SPACE(c, x) (0x00010000 | (c << 24) | (x))
-#endif
-#ifndef PHY_SPACE
- #define PHY_SPACE(w, p, x) (0x00200000 | ((p + 1) << 24) | (w << 16) | (x))
-#endif
-#ifndef PIF_SPACE
- #define PIF_SPACE(w, p, x) (0x00100000 | ((p + 1) << 24) | (w << 16) | (x))
-#endif
-// **** D0F0x00 Register Definition ****
-// Address
-#define D0F0x00_ADDRESS 0x0
-
-// Type
-#define D0F0x00_TYPE TYPE_D0F0
-// Field Data
-#define D0F0x00_VendorID_OFFSET 0
-#define D0F0x00_VendorID_WIDTH 16
-#define D0F0x00_VendorID_MASK 0xffff
-#define D0F0x00_DeviceID_OFFSET 16
-#define D0F0x00_DeviceID_WIDTH 16
-#define D0F0x00_DeviceID_MASK 0xffff0000
-
-/// D0F0x00
-typedef union {
- struct { ///<
- UINT32 VendorID:16; ///<
- UINT32 DeviceID:16; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x00_STRUCT;
-
-// **** D0F0x04 Register Definition ****
-// Address
-#define D0F0x04_ADDRESS 0x4
-
-// Type
-#define D0F0x04_TYPE TYPE_D0F0
-// Field Data
-#define D0F0x04_IoAccessEn_OFFSET 0
-#define D0F0x04_IoAccessEn_WIDTH 1
-#define D0F0x04_IoAccessEn_MASK 0x1
-#define D0F0x04_MemAccessEn_OFFSET 1
-#define D0F0x04_MemAccessEn_WIDTH 1
-#define D0F0x04_MemAccessEn_MASK 0x2
-#define D0F0x04_BusMasterEn_OFFSET 2
-#define D0F0x04_BusMasterEn_WIDTH 1
-#define D0F0x04_BusMasterEn_MASK 0x4
-#define D0F0x04_SpecialCycleEn_OFFSET 3
-#define D0F0x04_SpecialCycleEn_WIDTH 1
-#define D0F0x04_SpecialCycleEn_MASK 0x8
-#define D0F0x04_MemWriteInvalidateEn_OFFSET 4
-#define D0F0x04_MemWriteInvalidateEn_WIDTH 1
-#define D0F0x04_MemWriteInvalidateEn_MASK 0x10
-#define D0F0x04_PalSnoopEn_OFFSET 5
-#define D0F0x04_PalSnoopEn_WIDTH 1
-#define D0F0x04_PalSnoopEn_MASK 0x20
-#define D0F0x04_ParityErrorEn_OFFSET 6
-#define D0F0x04_ParityErrorEn_WIDTH 1
-#define D0F0x04_ParityErrorEn_MASK 0x40
-#define D0F0x04_Reserved_7_7_OFFSET 7
-#define D0F0x04_Reserved_7_7_WIDTH 1
-#define D0F0x04_Reserved_7_7_MASK 0x80
-#define D0F0x04_SerrEn_OFFSET 8
-#define D0F0x04_SerrEn_WIDTH 1
-#define D0F0x04_SerrEn_MASK 0x100
-#define D0F0x04_FastB2BEn_OFFSET 9
-#define D0F0x04_FastB2BEn_WIDTH 1
-#define D0F0x04_FastB2BEn_MASK 0x200
-#define D0F0x04_Reserved_19_10_OFFSET 10
-#define D0F0x04_Reserved_19_10_WIDTH 10
-#define D0F0x04_Reserved_19_10_MASK 0xffc00
-#define D0F0x04_CapList_OFFSET 20
-#define D0F0x04_CapList_WIDTH 1
-#define D0F0x04_CapList_MASK 0x100000
-#define D0F0x04_PCI66En_OFFSET 21
-#define D0F0x04_PCI66En_WIDTH 1
-#define D0F0x04_PCI66En_MASK 0x200000
-#define D0F0x04_Reserved_22_22_OFFSET 22
-#define D0F0x04_Reserved_22_22_WIDTH 1
-#define D0F0x04_Reserved_22_22_MASK 0x400000
-#define D0F0x04_FastBackCapable_OFFSET 23
-#define D0F0x04_FastBackCapable_WIDTH 1
-#define D0F0x04_FastBackCapable_MASK 0x800000
-#define D0F0x04_Reserved_24_24_OFFSET 24
-#define D0F0x04_Reserved_24_24_WIDTH 1
-#define D0F0x04_Reserved_24_24_MASK 0x1000000
-#define D0F0x04_DevselTiming_OFFSET 25
-#define D0F0x04_DevselTiming_WIDTH 2
-#define D0F0x04_DevselTiming_MASK 0x6000000
-#define D0F0x04_SignalTargetAbort_OFFSET 27
-#define D0F0x04_SignalTargetAbort_WIDTH 1
-#define D0F0x04_SignalTargetAbort_MASK 0x8000000
-#define D0F0x04_ReceivedTargetAbort_OFFSET 28
-#define D0F0x04_ReceivedTargetAbort_WIDTH 1
-#define D0F0x04_ReceivedTargetAbort_MASK 0x10000000
-#define D0F0x04_ReceivedMasterAbort_OFFSET 29
-#define D0F0x04_ReceivedMasterAbort_WIDTH 1
-#define D0F0x04_ReceivedMasterAbort_MASK 0x20000000
-#define D0F0x04_SignaledSystemError_OFFSET 30
-#define D0F0x04_SignaledSystemError_WIDTH 1
-#define D0F0x04_SignaledSystemError_MASK 0x40000000
-#define D0F0x04_ParityErrorDetected_OFFSET 31
-#define D0F0x04_ParityErrorDetected_WIDTH 1
-#define D0F0x04_ParityErrorDetected_MASK 0x80000000
-
-/// D0F0x04
-typedef union {
- struct { ///<
- UINT32 IoAccessEn:1 ; ///<
- UINT32 MemAccessEn:1 ; ///<
- UINT32 BusMasterEn:1 ; ///<
- UINT32 SpecialCycleEn:1 ; ///<
- UINT32 MemWriteInvalidateEn:1 ; ///<
- UINT32 PalSnoopEn:1 ; ///<
- UINT32 ParityErrorEn:1 ; ///<
- UINT32 Reserved_7_7:1 ; ///<
- UINT32 SerrEn:1 ; ///<
- UINT32 FastB2BEn:1 ; ///<
- UINT32 Reserved_19_10:10; ///<
- UINT32 CapList:1 ; ///<
- UINT32 PCI66En:1 ; ///<
- UINT32 Reserved_22_22:1 ; ///<
- UINT32 FastBackCapable:1 ; ///<
- UINT32 Reserved_24_24:1 ; ///<
- UINT32 DevselTiming:2 ; ///<
- UINT32 SignalTargetAbort:1 ; ///<
- UINT32 ReceivedTargetAbort:1 ; ///<
- UINT32 ReceivedMasterAbort:1 ; ///<
- UINT32 SignaledSystemError:1 ; ///<
- UINT32 ParityErrorDetected:1 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x04_STRUCT;
-
-// **** D0F0x08 Register Definition ****
-// Address
-#define D0F0x08_ADDRESS 0x8
-
-// Type
-#define D0F0x08_TYPE TYPE_D0F0
-// Field Data
-#define D0F0x08_RevID_OFFSET 0
-#define D0F0x08_RevID_WIDTH 8
-#define D0F0x08_RevID_MASK 0xff
-#define D0F0x08_ClassCode_OFFSET 8
-#define D0F0x08_ClassCode_WIDTH 24
-#define D0F0x08_ClassCode_MASK 0xffffff00
-
-/// D0F0x08
-typedef union {
- struct { ///<
- UINT32 RevID:8 ; ///<
- UINT32 ClassCode:24; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x08_STRUCT;
-
-// **** D0F0x0C Register Definition ****
-// Address
-#define D0F0x0C_ADDRESS 0xc
-
-// Type
-#define D0F0x0C_TYPE TYPE_D0F0
-// Field Data
-#define D0F0x0C_CacheLineSize_OFFSET 0
-#define D0F0x0C_CacheLineSize_WIDTH 8
-#define D0F0x0C_CacheLineSize_MASK 0xff
-#define D0F0x0C_LatencyTimer_OFFSET 8
-#define D0F0x0C_LatencyTimer_WIDTH 8
-#define D0F0x0C_LatencyTimer_MASK 0xff00
-#define D0F0x0C_HeaderTypeReg_OFFSET 16
-#define D0F0x0C_HeaderTypeReg_WIDTH 8
-#define D0F0x0C_HeaderTypeReg_MASK 0xff0000
-#define D0F0x0C_BIST_OFFSET 24
-#define D0F0x0C_BIST_WIDTH 8
-#define D0F0x0C_BIST_MASK 0xff000000
-
-/// D0F0x0C
-typedef union {
- struct { ///<
- UINT32 CacheLineSize:8 ; ///<
- UINT32 LatencyTimer:8 ; ///<
- UINT32 HeaderTypeReg:8 ; ///<
- UINT32 BIST:8 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x0C_STRUCT;
-
-// **** D0F0x2C Register Definition ****
-// Address
-#define D0F0x2C_ADDRESS 0x2c
-
-// Type
-#define D0F0x2C_TYPE TYPE_D0F0
-// Field Data
-#define D0F0x2C_SubsystemVendorID_OFFSET 0
-#define D0F0x2C_SubsystemVendorID_WIDTH 16
-#define D0F0x2C_SubsystemVendorID_MASK 0xffff
-#define D0F0x2C_SubsystemID_OFFSET 16
-#define D0F0x2C_SubsystemID_WIDTH 16
-#define D0F0x2C_SubsystemID_MASK 0xffff0000
-
-/// D0F0x2C
-typedef union {
- struct { ///<
- UINT32 SubsystemVendorID:16; ///<
- UINT32 SubsystemID:16; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x2C_STRUCT;
-
-// **** D0F0x34 Register Definition ****
-// Address
-#define D0F0x34_ADDRESS 0x34
-
-// Type
-#define D0F0x34_TYPE TYPE_D0F0
-// Field Data
-#define D0F0x34_CapPtr_OFFSET 0
-#define D0F0x34_CapPtr_WIDTH 8
-#define D0F0x34_CapPtr_MASK 0xff
-#define D0F0x34_Reserved_31_8_OFFSET 8
-#define D0F0x34_Reserved_31_8_WIDTH 24
-#define D0F0x34_Reserved_31_8_MASK 0xffffff00
-
-/// D0F0x34
-typedef union {
- struct { ///<
- UINT32 CapPtr:8 ; ///<
- UINT32 Reserved_31_8:24; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x34_STRUCT;
-
-// **** D0F0x4C Register Definition ****
-// Address
-#define D0F0x4C_ADDRESS 0x4c
-
-// Type
-#define D0F0x4C_TYPE TYPE_D0F0
-// Field Data
-#define D0F0x4C_Function1Enable_OFFSET 0
-#define D0F0x4C_Function1Enable_WIDTH 1
-#define D0F0x4C_Function1Enable_MASK 0x1
-#define D0F0x4C_ApicEnable_OFFSET 1
-#define D0F0x4C_ApicEnable_WIDTH 1
-#define D0F0x4C_ApicEnable_MASK 0x2
-#define D0F0x4C_Reserved_2_2_OFFSET 2
-#define D0F0x4C_Reserved_2_2_WIDTH 1
-#define D0F0x4C_Reserved_2_2_MASK 0x4
-#define D0F0x4C_Cf8Dis_OFFSET 3
-#define D0F0x4C_Cf8Dis_WIDTH 1
-#define D0F0x4C_Cf8Dis_MASK 0x8
-#define D0F0x4C_PMEDis_OFFSET 4
-#define D0F0x4C_PMEDis_WIDTH 1
-#define D0F0x4C_PMEDis_MASK 0x10
-#define D0F0x4C_SerrDis_OFFSET 5
-#define D0F0x4C_SerrDis_WIDTH 1
-#define D0F0x4C_SerrDis_MASK 0x20
-#define D0F0x4C_Reserved_10_6_OFFSET 6
-#define D0F0x4C_Reserved_10_6_WIDTH 5
-#define D0F0x4C_Reserved_10_6_MASK 0x7c0
-#define D0F0x4C_CRS_OFFSET 11
-#define D0F0x4C_CRS_WIDTH 1
-#define D0F0x4C_CRS_MASK 0x800
-#define D0F0x4C_CfgRdTime_OFFSET 12
-#define D0F0x4C_CfgRdTime_WIDTH 3
-#define D0F0x4C_CfgRdTime_MASK 0x7000
-#define D0F0x4C_Reserved_22_15_OFFSET 15
-#define D0F0x4C_Reserved_22_15_WIDTH 8
-#define D0F0x4C_Reserved_22_15_MASK 0x7f8000
-#define D0F0x4C_MMIOEnable_OFFSET 23
-#define D0F0x4C_MMIOEnable_WIDTH 1
-#define D0F0x4C_MMIOEnable_MASK 0x800000
-#define D0F0x4C_Reserved_25_24_OFFSET 24
-#define D0F0x4C_Reserved_25_24_WIDTH 2
-#define D0F0x4C_Reserved_25_24_MASK 0x3000000
-#define D0F0x4C_HPDis_OFFSET 26
-#define D0F0x4C_HPDis_WIDTH 1
-#define D0F0x4C_HPDis_MASK 0x4000000
-#define D0F0x4C_Reserved_31_27_OFFSET 27
-#define D0F0x4C_Reserved_31_27_WIDTH 5
-#define D0F0x4C_Reserved_31_27_MASK 0xf8000000
-
-/// D0F0x4C
-typedef union {
- struct { ///<
- UINT32 Function1Enable:1 ; ///<
- UINT32 ApicEnable:1 ; ///<
- UINT32 Reserved_2_2:1 ; ///<
- UINT32 Cf8Dis:1 ; ///<
- UINT32 PMEDis:1 ; ///<
- UINT32 SerrDis:1 ; ///<
- UINT32 Reserved_10_6:5 ; ///<
- UINT32 CRS:1 ; ///<
- UINT32 CfgRdTime:3 ; ///<
- UINT32 Reserved_22_15:8 ; ///<
- UINT32 MMIOEnable:1 ; ///<
- UINT32 Reserved_25_24:2 ; ///<
- UINT32 HPDis:1 ; ///<
- UINT32 Reserved_31_27:5 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x4C_STRUCT;
-
-// **** D0F0x60 Register Definition ****
-// Address
-#define D0F0x60_ADDRESS 0x60
-
-// Type
-#define D0F0x60_TYPE TYPE_D0F0
-// Field Data
-#define D0F0x60_MiscIndAddr_OFFSET 0
-#define D0F0x60_MiscIndAddr_WIDTH 7
-#define D0F0x60_MiscIndAddr_MASK 0x7f
-#define D0F0x60_MiscIndWrEn_OFFSET 7
-#define D0F0x60_MiscIndWrEn_WIDTH 1
-#define D0F0x60_MiscIndWrEn_MASK 0x80
-#define D0F0x60_Reserved_31_8_OFFSET 8
-#define D0F0x60_Reserved_31_8_WIDTH 24
-#define D0F0x60_Reserved_31_8_MASK 0xffffff00
-
-/// D0F0x60
-typedef union {
- struct { ///<
- UINT32 MiscIndAddr:7 ; ///<
- UINT32 MiscIndWrEn:1 ; ///<
- UINT32 Reserved_31_8:24; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x60_STRUCT;
-
-// **** D0F0x64 Register Definition ****
-// Address
-#define D0F0x64_ADDRESS 0x64
-
-// Type
-#define D0F0x64_TYPE TYPE_D0F0
-// Field Data
-#define D0F0x64_MiscIndData_OFFSET 0
-#define D0F0x64_MiscIndData_WIDTH 32
-#define D0F0x64_MiscIndData_MASK 0xffffffff
-
-/// D0F0x64
-typedef union {
- struct { ///<
- UINT32 MiscIndData:32; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x64_STRUCT;
-
-// **** D0F0x78 Register Definition ****
-// Address
-#define D0F0x78_ADDRESS 0x78
-
-// Type
-#define D0F0x78_TYPE TYPE_D0F0
-// Field Data
-#define D0F0x78_Scratch_OFFSET 0
-#define D0F0x78_Scratch_WIDTH 32
-#define D0F0x78_Scratch_MASK 0xffffffff
-
-/// D0F0x78
-typedef union {
- struct { ///<
- UINT32 Scratch:32; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x78_STRUCT;
-
-// **** D0F0x7C Register Definition ****
-// Address
-#define D0F0x7C_ADDRESS 0x7c
-
-// Type
-#define D0F0x7C_TYPE TYPE_D0F0
-// Field Data
-#define D0F0x7C_ForceIntGFXDisable_OFFSET 0
-#define D0F0x7C_ForceIntGFXDisable_WIDTH 1
-#define D0F0x7C_ForceIntGFXDisable_MASK 0x1
-#define D0F0x7C_Reserved_31_1_OFFSET 1
-#define D0F0x7C_Reserved_31_1_WIDTH 31
-#define D0F0x7C_Reserved_31_1_MASK 0xfffffffe
-
-/// D0F0x7C
-typedef union {
- struct { ///<
- UINT32 ForceIntGFXDisable:1 ; ///<
- UINT32 Reserved_31_1:31; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x7C_STRUCT;
-
-// **** D0F0x84 Register Definition ****
-// Address
-#define D0F0x84_ADDRESS 0x84
-
-// Type
-#define D0F0x84_TYPE TYPE_D0F0
-// Field Data
-#define D0F0x84_Reserved_3_0_OFFSET 0
-#define D0F0x84_Reserved_3_0_WIDTH 4
-#define D0F0x84_Reserved_3_0_MASK 0xf
-#define D0F0x84_Ev6Mode_OFFSET 4
-#define D0F0x84_Ev6Mode_WIDTH 1
-#define D0F0x84_Ev6Mode_MASK 0x10
-#define D0F0x84_Reserved_7_5_OFFSET 5
-#define D0F0x84_Reserved_7_5_WIDTH 3
-#define D0F0x84_Reserved_7_5_MASK 0xe0
-#define D0F0x84_PmeMode_OFFSET 8
-#define D0F0x84_PmeMode_WIDTH 1
-#define D0F0x84_PmeMode_MASK 0x100
-#define D0F0x84_PmeTurnOff_OFFSET 9
-#define D0F0x84_PmeTurnOff_WIDTH 1
-#define D0F0x84_PmeTurnOff_MASK 0x200
-#define D0F0x84_Reserved_31_10_OFFSET 10
-#define D0F0x84_Reserved_31_10_WIDTH 22
-#define D0F0x84_Reserved_31_10_MASK 0xfffffc00
-
-/// D0F0x84
-typedef union {
- struct { ///<
- UINT32 Reserved_3_0:4 ; ///<
- UINT32 Ev6Mode:1 ; ///<
- UINT32 Reserved_7_5:3 ; ///<
- UINT32 PmeMode:1 ; ///<
- UINT32 PmeTurnOff:1 ; ///<
- UINT32 Reserved_31_10:22; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x84_STRUCT;
-
-// **** D0F0x90 Register Definition ****
-// Address
-#define D0F0x90_ADDRESS 0x90
-
-// Type
-#define D0F0x90_TYPE TYPE_D0F0
-// Field Data
-#define D0F0x90_Reserved_22_0_OFFSET 0
-#define D0F0x90_Reserved_22_0_WIDTH 23
-#define D0F0x90_Reserved_22_0_MASK 0x7fffff
-#define D0F0x90_TopOfDram_OFFSET 23
-#define D0F0x90_TopOfDram_WIDTH 9
-#define D0F0x90_TopOfDram_MASK 0xff800000
-
-/// D0F0x90
-typedef union {
- struct { ///<
- UINT32 Reserved_22_0:23; ///<
- UINT32 TopOfDram:9 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x90_STRUCT;
-
-// **** D0F0x94 Register Definition ****
-// Address
-#define D0F0x94_ADDRESS 0x94
-
-// Type
-#define D0F0x94_TYPE TYPE_D0F0
-// Field Data
-#define D0F0x94_OrbIndAddr_OFFSET 0
-#define D0F0x94_OrbIndAddr_WIDTH 7
-#define D0F0x94_OrbIndAddr_MASK 0x7f
-#define D0F0x94_Reserved_7_7_OFFSET 7
-#define D0F0x94_Reserved_7_7_WIDTH 1
-#define D0F0x94_Reserved_7_7_MASK 0x80
-#define D0F0x94_OrbIndWrEn_OFFSET 8
-#define D0F0x94_OrbIndWrEn_WIDTH 1
-#define D0F0x94_OrbIndWrEn_MASK 0x100
-#define D0F0x94_Reserved_31_9_OFFSET 9
-#define D0F0x94_Reserved_31_9_WIDTH 23
-#define D0F0x94_Reserved_31_9_MASK 0xfffffe00
-
-/// D0F0x94
-typedef union {
- struct { ///<
- UINT32 OrbIndAddr:7 ; ///<
- UINT32 Reserved_7_7:1 ; ///<
- UINT32 OrbIndWrEn:1 ; ///<
- UINT32 Reserved_31_9:23; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x94_STRUCT;
-
-// **** D0F0x98 Register Definition ****
-// Address
-#define D0F0x98_ADDRESS 0x98
-
-// Type
-#define D0F0x98_TYPE TYPE_D0F0
-// Field Data
-#define D0F0x98_OrbIndData_OFFSET 0
-#define D0F0x98_OrbIndData_WIDTH 32
-#define D0F0x98_OrbIndData_MASK 0xffffffff
-
-/// D0F0x98
-typedef union {
- struct { ///<
- UINT32 OrbIndData:32; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x98_STRUCT;
-
-// **** D0F0xE0 Register Definition ****
-// Address
-#define D0F0xE0_ADDRESS 0xe0
-
-// Type
-#define D0F0xE0_TYPE TYPE_D0F0
-// Field Data
-#define D0F0xE0_PcieIndxAddr_OFFSET 0
-#define D0F0xE0_PcieIndxAddr_WIDTH 16
-#define D0F0xE0_PcieIndxAddr_MASK 0xffff
-#define D0F0xE0_FrameType_OFFSET 16
-#define D0F0xE0_FrameType_WIDTH 8
-#define D0F0xE0_FrameType_MASK 0xff0000
-#define D0F0xE0_BlockSelect_OFFSET 24
-#define D0F0xE0_BlockSelect_WIDTH 8
-#define D0F0xE0_BlockSelect_MASK 0xff000000
-
-/// D0F0xE0
-typedef union {
- struct { ///<
- UINT32 PcieIndxAddr:16; ///<
- UINT32 FrameType:8 ; ///<
- UINT32 BlockSelect:8 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0xE0_STRUCT;
-
-// **** D0F0xE4 Register Definition ****
-// Address
-#define D0F0xE4_ADDRESS 0xe4
-
-// Type
-#define D0F0xE4_TYPE TYPE_D0F0
-// Field Data
-#define D0F0xE4_PcieIndxData_OFFSET 0
-#define D0F0xE4_PcieIndxData_WIDTH 32
-#define D0F0xE4_PcieIndxData_MASK 0xffffffff
-
-/// D0F0xE4
-typedef union {
- struct { ///<
- UINT32 PcieIndxData:32; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0xE4_STRUCT;
-
-// **** D18F1xF0 Register Definition ****
-// Address
-#define D18F1xF0_ADDRESS 0xf0
-
-// Type
-#define D18F1xF0_TYPE TYPE_D18F1
-// Field Data
-#define D18F1xF0_DramHoleValid_OFFSET 0
-#define D18F1xF0_DramHoleValid_WIDTH 1
-#define D18F1xF0_DramHoleValid_MASK 0x1
-#define D18F1xF0_Reserved_6_1_OFFSET 1
-#define D18F1xF0_Reserved_6_1_WIDTH 6
-#define D18F1xF0_Reserved_6_1_MASK 0x7e
-#define D18F1xF0_DramHoleOffset_31_23__OFFSET 7
-#define D18F1xF0_DramHoleOffset_31_23__WIDTH 9
-#define D18F1xF0_DramHoleOffset_31_23__MASK 0xff80
-#define D18F1xF0_Reserved_23_16_OFFSET 16
-#define D18F1xF0_Reserved_23_16_WIDTH 8
-#define D18F1xF0_Reserved_23_16_MASK 0xff0000
-#define D18F1xF0_DramHoleBase_31_24__OFFSET 24
-#define D18F1xF0_DramHoleBase_31_24__WIDTH 8
-#define D18F1xF0_DramHoleBase_31_24__MASK 0xff000000
-
-/// D18F1xF0
-typedef union {
- struct { ///<
- UINT32 DramHoleValid:1 ; ///<
- UINT32 Reserved_6_1:6 ; ///<
- UINT32 DramHoleOffset_31_23_:9 ; ///<
- UINT32 Reserved_23_16:8 ; ///<
- UINT32 DramHoleBase_31_24_:8 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F1xF0_STRUCT;
-
-// **** D18F2x00 Register Definition ****
-// Address
-#define D18F2x00_ADDRESS 0x0
-
-// Type
-#define D18F2x00_TYPE TYPE_D18F2
-// Field Data
-#define D18F2x00_VendorID_OFFSET 0
-#define D18F2x00_VendorID_WIDTH 16
-#define D18F2x00_VendorID_MASK 0xffff
-#define D18F2x00_DeviceID_OFFSET 16
-#define D18F2x00_DeviceID_WIDTH 16
-#define D18F2x00_DeviceID_MASK 0xffff0000
-
-/// D18F2x00
-typedef union {
- struct { ///<
- UINT32 VendorID:16; ///<
- UINT32 DeviceID:16; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F2x00_STRUCT;
-
-// **** D18F2x04 Register Definition ****
-// Address
-#define D18F2x04_ADDRESS 0x4
-
-// Type
-#define D18F2x04_TYPE TYPE_D18F2
-// Field Data
-#define D18F2x04_Command_OFFSET 0
-#define D18F2x04_Command_WIDTH 16
-#define D18F2x04_Command_MASK 0xffff
-#define D18F2x04_Status_OFFSET 16
-#define D18F2x04_Status_WIDTH 16
-#define D18F2x04_Status_MASK 0xffff0000
-
-/// D18F2x04
-typedef union {
- struct { ///<
- UINT32 Command:16; ///<
- UINT32 Status:16; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F2x04_STRUCT;
-
-// **** D18F2x08 Register Definition ****
-// Address
-#define D18F2x08_ADDRESS 0x8
-
-// Type
-#define D18F2x08_TYPE TYPE_D18F2
-// Field Data
-#define D18F2x08_RevID_OFFSET 0
-#define D18F2x08_RevID_WIDTH 8
-#define D18F2x08_RevID_MASK 0xff
-#define D18F2x08_ClassCode_OFFSET 8
-#define D18F2x08_ClassCode_WIDTH 24
-#define D18F2x08_ClassCode_MASK 0xffffff00
-
-/// D18F2x08
-typedef union {
- struct { ///<
- UINT32 RevID:8 ; ///<
- UINT32 ClassCode:24; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F2x08_STRUCT;
-
-// **** D18F2x0C Register Definition ****
-// Address
-#define D18F2x0C_ADDRESS 0xc
-
-// Type
-#define D18F2x0C_TYPE TYPE_D18F2
-// Field Data
-#define D18F2x0C_HeaderTypeReg_OFFSET 0
-#define D18F2x0C_HeaderTypeReg_WIDTH 32
-#define D18F2x0C_HeaderTypeReg_MASK 0xffffffff
-
-/// D18F2x0C
-typedef union {
- struct { ///<
- UINT32 HeaderTypeReg:32; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F2x0C_STRUCT;
-
-// **** D18F2x34 Register Definition ****
-// Address
-#define D18F2x34_ADDRESS 0x34
-
-// Type
-#define D18F2x34_TYPE TYPE_D18F2
-// Field Data
-#define D18F2x34_CapPtr_OFFSET 0
-#define D18F2x34_CapPtr_WIDTH 8
-#define D18F2x34_CapPtr_MASK 0xff
-#define D18F2x34_Reserved_31_8_OFFSET 8
-#define D18F2x34_Reserved_31_8_WIDTH 24
-#define D18F2x34_Reserved_31_8_MASK 0xffffff00
-
-/// D18F2x34
-typedef union {
- struct { ///<
- UINT32 CapPtr:8 ; ///<
- UINT32 Reserved_31_8:24; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F2x34_STRUCT;
-
-// **** D18F2x40 Register Definition ****
-// Address
-#define D18F2x40_ADDRESS 0x40
-
-// Type
-#define D18F2x40_TYPE TYPE_D18F2
-// Field Data
-#define D18F2x40_CSEnable_OFFSET 0
-#define D18F2x40_CSEnable_WIDTH 1
-#define D18F2x40_CSEnable_MASK 0x1
-#define D18F2x40_Reserved_1_1_OFFSET 1
-#define D18F2x40_Reserved_1_1_WIDTH 1
-#define D18F2x40_Reserved_1_1_MASK 0x2
-#define D18F2x40_TestFail_OFFSET 2
-#define D18F2x40_TestFail_WIDTH 1
-#define D18F2x40_TestFail_MASK 0x4
-#define D18F2x40_OnDimmMirror_OFFSET 3
-#define D18F2x40_OnDimmMirror_WIDTH 1
-#define D18F2x40_OnDimmMirror_MASK 0x8
-#define D18F2x40_Reserved_4_4_OFFSET 4
-#define D18F2x40_Reserved_4_4_WIDTH 1
-#define D18F2x40_Reserved_4_4_MASK 0x10
-#define D18F2x40_BaseAddr_21_13__OFFSET 5
-#define D18F2x40_BaseAddr_21_13__WIDTH 9
-#define D18F2x40_BaseAddr_21_13__MASK 0x3fe0
-#define D18F2x40_Reserved_18_14_OFFSET 14
-#define D18F2x40_Reserved_18_14_WIDTH 5
-#define D18F2x40_Reserved_18_14_MASK 0x7c000
-#define D18F2x40_BaseAddr_35_27__OFFSET 19
-#define D18F2x40_BaseAddr_35_27__WIDTH 9
-#define D18F2x40_BaseAddr_35_27__MASK 0xff80000
-#define D18F2x40_Reserved_28_28_OFFSET 28
-#define D18F2x40_Reserved_28_28_WIDTH 1
-#define D18F2x40_Reserved_28_28_MASK 0x10000000
-#define D18F2x40_Reserved_31_29_OFFSET 29
-#define D18F2x40_Reserved_31_29_WIDTH 3
-#define D18F2x40_Reserved_31_29_MASK 0xe0000000
-
-/// D18F2x40
-typedef union {
- struct { ///<
- UINT32 CSEnable:1 ; ///<
- UINT32 Reserved_1_1:1 ; ///<
- UINT32 TestFail:1 ; ///<
- UINT32 OnDimmMirror:1 ; ///<
- UINT32 Reserved_4_4:1 ; ///<
- UINT32 BaseAddr_21_13_:9 ; ///<
- UINT32 Reserved_18_14:5 ; ///<
- UINT32 BaseAddr_35_27_:9 ; ///<
- UINT32 Reserved_28_28:1 ; ///<
- UINT32 Reserved_31_29:3 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F2x40_STRUCT;
-
-// **** D18F2x44 Register Definition ****
-// Address
-#define D18F2x44_ADDRESS 0x44
-
-// Type
-#define D18F2x44_TYPE TYPE_D18F2
-// Field Data
-#define D18F2x44_CSEnable_OFFSET 0
-#define D18F2x44_CSEnable_WIDTH 1
-#define D18F2x44_CSEnable_MASK 0x1
-#define D18F2x44_Reserved_1_1_OFFSET 1
-#define D18F2x44_Reserved_1_1_WIDTH 1
-#define D18F2x44_Reserved_1_1_MASK 0x2
-#define D18F2x44_TestFail_OFFSET 2
-#define D18F2x44_TestFail_WIDTH 1
-#define D18F2x44_TestFail_MASK 0x4
-#define D18F2x44_OnDimmMirror_OFFSET 3
-#define D18F2x44_OnDimmMirror_WIDTH 1
-#define D18F2x44_OnDimmMirror_MASK 0x8
-#define D18F2x44_Reserved_4_4_OFFSET 4
-#define D18F2x44_Reserved_4_4_WIDTH 1
-#define D18F2x44_Reserved_4_4_MASK 0x10
-#define D18F2x44_BaseAddr_21_13__OFFSET 5
-#define D18F2x44_BaseAddr_21_13__WIDTH 9
-#define D18F2x44_BaseAddr_21_13__MASK 0x3fe0
-#define D18F2x44_Reserved_18_14_OFFSET 14
-#define D18F2x44_Reserved_18_14_WIDTH 5
-#define D18F2x44_Reserved_18_14_MASK 0x7c000
-#define D18F2x44_BaseAddr_35_27__OFFSET 19
-#define D18F2x44_BaseAddr_35_27__WIDTH 9
-#define D18F2x44_BaseAddr_35_27__MASK 0xff80000
-#define D18F2x44_Reserved_28_28_OFFSET 28
-#define D18F2x44_Reserved_28_28_WIDTH 1
-#define D18F2x44_Reserved_28_28_MASK 0x10000000
-#define D18F2x44_Reserved_31_29_OFFSET 29
-#define D18F2x44_Reserved_31_29_WIDTH 3
-#define D18F2x44_Reserved_31_29_MASK 0xe0000000
-
-/// D18F2x44
-typedef union {
- struct { ///<
- UINT32 CSEnable:1 ; ///<
- UINT32 Reserved_1_1:1 ; ///<
- UINT32 TestFail:1 ; ///<
- UINT32 OnDimmMirror:1 ; ///<
- UINT32 Reserved_4_4:1 ; ///<
- UINT32 BaseAddr_21_13_:9 ; ///<
- UINT32 Reserved_18_14:5 ; ///<
- UINT32 BaseAddr_35_27_:9 ; ///<
- UINT32 Reserved_28_28:1 ; ///<
- UINT32 Reserved_31_29:3 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F2x44_STRUCT;
-
-// **** D18F2x48 Register Definition ****
-// Address
-#define D18F2x48_ADDRESS 0x48
-
-// Type
-#define D18F2x48_TYPE TYPE_D18F2
-// Field Data
-#define D18F2x48_CSEnable_OFFSET 0
-#define D18F2x48_CSEnable_WIDTH 1
-#define D18F2x48_CSEnable_MASK 0x1
-#define D18F2x48_Reserved_1_1_OFFSET 1
-#define D18F2x48_Reserved_1_1_WIDTH 1
-#define D18F2x48_Reserved_1_1_MASK 0x2
-#define D18F2x48_TestFail_OFFSET 2
-#define D18F2x48_TestFail_WIDTH 1
-#define D18F2x48_TestFail_MASK 0x4
-#define D18F2x48_OnDimmMirror_OFFSET 3
-#define D18F2x48_OnDimmMirror_WIDTH 1
-#define D18F2x48_OnDimmMirror_MASK 0x8
-#define D18F2x48_Reserved_4_4_OFFSET 4
-#define D18F2x48_Reserved_4_4_WIDTH 1
-#define D18F2x48_Reserved_4_4_MASK 0x10
-#define D18F2x48_BaseAddr_21_13__OFFSET 5
-#define D18F2x48_BaseAddr_21_13__WIDTH 9
-#define D18F2x48_BaseAddr_21_13__MASK 0x3fe0
-#define D18F2x48_Reserved_18_14_OFFSET 14
-#define D18F2x48_Reserved_18_14_WIDTH 5
-#define D18F2x48_Reserved_18_14_MASK 0x7c000
-#define D18F2x48_BaseAddr_35_27__OFFSET 19
-#define D18F2x48_BaseAddr_35_27__WIDTH 9
-#define D18F2x48_BaseAddr_35_27__MASK 0xff80000
-#define D18F2x48_Reserved_28_28_OFFSET 28
-#define D18F2x48_Reserved_28_28_WIDTH 1
-#define D18F2x48_Reserved_28_28_MASK 0x10000000
-#define D18F2x48_Reserved_31_29_OFFSET 29
-#define D18F2x48_Reserved_31_29_WIDTH 3
-#define D18F2x48_Reserved_31_29_MASK 0xe0000000
-
-/// D18F2x48
-typedef union {
- struct { ///<
- UINT32 CSEnable:1 ; ///<
- UINT32 Reserved_1_1:1 ; ///<
- UINT32 TestFail:1 ; ///<
- UINT32 OnDimmMirror:1 ; ///<
- UINT32 Reserved_4_4:1 ; ///<
- UINT32 BaseAddr_21_13_:9 ; ///<
- UINT32 Reserved_18_14:5 ; ///<
- UINT32 BaseAddr_35_27_:9 ; ///<
- UINT32 Reserved_28_28:1 ; ///<
- UINT32 Reserved_31_29:3 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F2x48_STRUCT;
-
-// **** D18F2x4C Register Definition ****
-// Address
-#define D18F2x4C_ADDRESS 0x4c
-
-// Type
-#define D18F2x4C_TYPE TYPE_D18F2
-// Field Data
-#define D18F2x4C_CSEnable_OFFSET 0
-#define D18F2x4C_CSEnable_WIDTH 1
-#define D18F2x4C_CSEnable_MASK 0x1
-#define D18F2x4C_Reserved_1_1_OFFSET 1
-#define D18F2x4C_Reserved_1_1_WIDTH 1
-#define D18F2x4C_Reserved_1_1_MASK 0x2
-#define D18F2x4C_TestFail_OFFSET 2
-#define D18F2x4C_TestFail_WIDTH 1
-#define D18F2x4C_TestFail_MASK 0x4
-#define D18F2x4C_OnDimmMirror_OFFSET 3
-#define D18F2x4C_OnDimmMirror_WIDTH 1
-#define D18F2x4C_OnDimmMirror_MASK 0x8
-#define D18F2x4C_Reserved_4_4_OFFSET 4
-#define D18F2x4C_Reserved_4_4_WIDTH 1
-#define D18F2x4C_Reserved_4_4_MASK 0x10
-#define D18F2x4C_BaseAddr_21_13__OFFSET 5
-#define D18F2x4C_BaseAddr_21_13__WIDTH 9
-#define D18F2x4C_BaseAddr_21_13__MASK 0x3fe0
-#define D18F2x4C_Reserved_18_14_OFFSET 14
-#define D18F2x4C_Reserved_18_14_WIDTH 5
-#define D18F2x4C_Reserved_18_14_MASK 0x7c000
-#define D18F2x4C_BaseAddr_35_27__OFFSET 19
-#define D18F2x4C_BaseAddr_35_27__WIDTH 9
-#define D18F2x4C_BaseAddr_35_27__MASK 0xff80000
-#define D18F2x4C_Reserved_28_28_OFFSET 28
-#define D18F2x4C_Reserved_28_28_WIDTH 1
-#define D18F2x4C_Reserved_28_28_MASK 0x10000000
-#define D18F2x4C_Reserved_31_29_OFFSET 29
-#define D18F2x4C_Reserved_31_29_WIDTH 3
-#define D18F2x4C_Reserved_31_29_MASK 0xe0000000
-
-/// D18F2x4C
-typedef union {
- struct { ///<
- UINT32 CSEnable:1 ; ///<
- UINT32 Reserved_1_1:1 ; ///<
- UINT32 TestFail:1 ; ///<
- UINT32 OnDimmMirror:1 ; ///<
- UINT32 Reserved_4_4:1 ; ///<
- UINT32 BaseAddr_21_13_:9 ; ///<
- UINT32 Reserved_18_14:5 ; ///<
- UINT32 BaseAddr_35_27_:9 ; ///<
- UINT32 Reserved_28_28:1 ; ///<
- UINT32 Reserved_31_29:3 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F2x4C_STRUCT;
-
-// **** D18F2x60 Register Definition ****
-// Address
-#define D18F2x60_ADDRESS 0x60
-
-// Type
-#define D18F2x60_TYPE TYPE_D18F2
-// Field Data
-#define D18F2x60_Reserved_4_0_OFFSET 0
-#define D18F2x60_Reserved_4_0_WIDTH 5
-#define D18F2x60_Reserved_4_0_MASK 0x1f
-#define D18F2x60_AddrMask_21_13__OFFSET 5
-#define D18F2x60_AddrMask_21_13__WIDTH 9
-#define D18F2x60_AddrMask_21_13__MASK 0x3fe0
-#define D18F2x60_Reserved_18_14_OFFSET 14
-#define D18F2x60_Reserved_18_14_WIDTH 5
-#define D18F2x60_Reserved_18_14_MASK 0x7c000
-#define D18F2x60_AddrMask_35_27__OFFSET 19
-#define D18F2x60_AddrMask_35_27__WIDTH 9
-#define D18F2x60_AddrMask_35_27__MASK 0xff80000
-#define D18F2x60_Reserved_28_28_OFFSET 28
-#define D18F2x60_Reserved_28_28_WIDTH 1
-#define D18F2x60_Reserved_28_28_MASK 0x10000000
-#define D18F2x60_Reserved_31_29_OFFSET 29
-#define D18F2x60_Reserved_31_29_WIDTH 3
-#define D18F2x60_Reserved_31_29_MASK 0xe0000000
-
-/// D18F2x60
-typedef union {
- struct { ///<
- UINT32 Reserved_4_0:5 ; ///<
- UINT32 AddrMask_21_13_:9 ; ///<
- UINT32 Reserved_18_14:5 ; ///<
- UINT32 AddrMask_35_27_:9 ; ///<
- UINT32 Reserved_28_28:1 ; ///<
- UINT32 Reserved_31_29:3 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F2x60_STRUCT;
-
-// **** D18F2x64 Register Definition ****
-// Address
-#define D18F2x64_ADDRESS 0x64
-
-// Type
-#define D18F2x64_TYPE TYPE_D18F2
-// Field Data
-#define D18F2x64_Reserved_4_0_OFFSET 0
-#define D18F2x64_Reserved_4_0_WIDTH 5
-#define D18F2x64_Reserved_4_0_MASK 0x1f
-#define D18F2x64_AddrMask_21_13__OFFSET 5
-#define D18F2x64_AddrMask_21_13__WIDTH 9
-#define D18F2x64_AddrMask_21_13__MASK 0x3fe0
-#define D18F2x64_Reserved_18_14_OFFSET 14
-#define D18F2x64_Reserved_18_14_WIDTH 5
-#define D18F2x64_Reserved_18_14_MASK 0x7c000
-#define D18F2x64_AddrMask_35_27__OFFSET 19
-#define D18F2x64_AddrMask_35_27__WIDTH 9
-#define D18F2x64_AddrMask_35_27__MASK 0xff80000
-#define D18F2x64_Reserved_28_28_OFFSET 28
-#define D18F2x64_Reserved_28_28_WIDTH 1
-#define D18F2x64_Reserved_28_28_MASK 0x10000000
-#define D18F2x64_Reserved_31_29_OFFSET 29
-#define D18F2x64_Reserved_31_29_WIDTH 3
-#define D18F2x64_Reserved_31_29_MASK 0xe0000000
-
-/// D18F2x64
-typedef union {
- struct { ///<
- UINT32 Reserved_4_0:5 ; ///<
- UINT32 AddrMask_21_13_:9 ; ///<
- UINT32 Reserved_18_14:5 ; ///<
- UINT32 AddrMask_35_27_:9 ; ///<
- UINT32 Reserved_28_28:1 ; ///<
- UINT32 Reserved_31_29:3 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F2x64_STRUCT;
-
-// **** D18F2x78 Register Definition ****
-// Address
-#define D18F2x78_ADDRESS 0x78
-
-// Type
-#define D18F2x78_TYPE TYPE_D18F2
-// Field Data
-#define D18F2x78_RdPtrInit_OFFSET 0
-#define D18F2x78_RdPtrInit_WIDTH 4
-#define D18F2x78_RdPtrInit_MASK 0xf
-#define D18F2x78_Reserved_5_4_OFFSET 4
-#define D18F2x78_Reserved_5_4_WIDTH 2
-#define D18F2x78_Reserved_5_4_MASK 0x30
-#define D18F2x78_RxPtrInitReq_OFFSET 6
-#define D18F2x78_RxPtrInitReq_WIDTH 1
-#define D18F2x78_RxPtrInitReq_MASK 0x40
-#define D18F2x78_Reserved_7_7_OFFSET 7
-#define D18F2x78_Reserved_7_7_WIDTH 1
-#define D18F2x78_Reserved_7_7_MASK 0x80
-#define D18F2x78_Twrrd_3_2__OFFSET 8
-#define D18F2x78_Twrrd_3_2__WIDTH 2
-#define D18F2x78_Twrrd_3_2__MASK 0x300
-#define D18F2x78_Twrwr_3_2__OFFSET 10
-#define D18F2x78_Twrwr_3_2__WIDTH 2
-#define D18F2x78_Twrwr_3_2__MASK 0xc00
-#define D18F2x78_Trdrd_3_2__OFFSET 12
-#define D18F2x78_Trdrd_3_2__WIDTH 2
-#define D18F2x78_Trdrd_3_2__MASK 0x3000
-#define D18F2x78_Reserved_16_14_OFFSET 14
-#define D18F2x78_Reserved_16_14_WIDTH 3
-#define D18F2x78_Reserved_16_14_MASK 0x1c000
-#define D18F2x78_AddrCmdTriEn_OFFSET 17
-#define D18F2x78_AddrCmdTriEn_WIDTH 1
-#define D18F2x78_AddrCmdTriEn_MASK 0x20000
-#define D18F2x78_Reserved_19_18_OFFSET 18
-#define D18F2x78_Reserved_19_18_WIDTH 2
-#define D18F2x78_Reserved_19_18_MASK 0xc0000
-#define D18F2x78_ForceCasToSlot0_OFFSET 20
-#define D18F2x78_ForceCasToSlot0_WIDTH 1
-#define D18F2x78_ForceCasToSlot0_MASK 0x100000
-#define D18F2x78_DisCutThroughMode_OFFSET 21
-#define D18F2x78_DisCutThroughMode_WIDTH 1
-#define D18F2x78_DisCutThroughMode_MASK 0x200000
-#define D18F2x78_MaxRdLatency_OFFSET 22
-#define D18F2x78_MaxRdLatency_WIDTH 10
-#define D18F2x78_MaxRdLatency_MASK 0xffc00000
-
-/// D18F2x78
-typedef union {
- struct { ///<
- UINT32 RdPtrInit:4 ; ///<
- UINT32 Reserved_5_4:2 ; ///<
- UINT32 RxPtrInitReq:1 ; ///<
- UINT32 Reserved_7_7:1 ; ///<
- UINT32 Twrrd_3_2_:2 ; ///<
- UINT32 Twrwr_3_2_:2 ; ///<
- UINT32 Trdrd_3_2_:2 ; ///<
- UINT32 Reserved_16_14:3 ; ///<
- UINT32 AddrCmdTriEn:1 ; ///<
- UINT32 Reserved_19_18:2 ; ///<
- UINT32 ForceCasToSlot0:1 ; ///<
- UINT32 DisCutThroughMode:1 ; ///<
- UINT32 MaxRdLatency:10; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F2x78_STRUCT;
-
-// **** D18F2x7C Register Definition ****
-// Address
-#define D18F2x7C_ADDRESS 0x7c
-
-// Type
-#define D18F2x7C_TYPE TYPE_D18F2
-// Field Data
-#define D18F2x7C_MrsAddress_OFFSET 0
-#define D18F2x7C_MrsAddress_WIDTH 16
-#define D18F2x7C_MrsAddress_MASK 0xffff
-#define D18F2x7C_MrsBank_OFFSET 16
-#define D18F2x7C_MrsBank_WIDTH 3
-#define D18F2x7C_MrsBank_MASK 0x70000
-#define D18F2x7C_Reserved_19_19_OFFSET 19
-#define D18F2x7C_Reserved_19_19_WIDTH 1
-#define D18F2x7C_Reserved_19_19_MASK 0x80000
-#define D18F2x7C_MrsChipSel_OFFSET 20
-#define D18F2x7C_MrsChipSel_WIDTH 3
-#define D18F2x7C_MrsChipSel_MASK 0x700000
-#define D18F2x7C_Reserved_23_23_OFFSET 23
-#define D18F2x7C_Reserved_23_23_WIDTH 1
-#define D18F2x7C_Reserved_23_23_MASK 0x800000
-#define D18F2x7C_SendPchgAll_OFFSET 24
-#define D18F2x7C_SendPchgAll_WIDTH 1
-#define D18F2x7C_SendPchgAll_MASK 0x1000000
-#define D18F2x7C_SendAutoRefresh_OFFSET 25
-#define D18F2x7C_SendAutoRefresh_WIDTH 1
-#define D18F2x7C_SendAutoRefresh_MASK 0x2000000
-#define D18F2x7C_SendMrsCmd_OFFSET 26
-#define D18F2x7C_SendMrsCmd_WIDTH 1
-#define D18F2x7C_SendMrsCmd_MASK 0x4000000
-#define D18F2x7C_DeassertMemRstX_OFFSET 27
-#define D18F2x7C_DeassertMemRstX_WIDTH 1
-#define D18F2x7C_DeassertMemRstX_MASK 0x8000000
-#define D18F2x7C_AssertCke_OFFSET 28
-#define D18F2x7C_AssertCke_WIDTH 1
-#define D18F2x7C_AssertCke_MASK 0x10000000
-#define D18F2x7C_SendZQCmd_OFFSET 29
-#define D18F2x7C_SendZQCmd_WIDTH 1
-#define D18F2x7C_SendZQCmd_MASK 0x20000000
-#define D18F2x7C_Reserved_30_30_OFFSET 30
-#define D18F2x7C_Reserved_30_30_WIDTH 1
-#define D18F2x7C_Reserved_30_30_MASK 0x40000000
-#define D18F2x7C_EnDramInit_OFFSET 31
-#define D18F2x7C_EnDramInit_WIDTH 1
-#define D18F2x7C_EnDramInit_MASK 0x80000000
-
-/// D18F2x7C
-typedef union {
- struct { ///<
- UINT32 MrsAddress:16; ///<
- UINT32 MrsBank:3 ; ///<
- UINT32 Reserved_19_19:1 ; ///<
- UINT32 MrsChipSel:3 ; ///<
- UINT32 Reserved_23_23:1 ; ///<
- UINT32 SendPchgAll:1 ; ///<
- UINT32 SendAutoRefresh:1 ; ///<
- UINT32 SendMrsCmd:1 ; ///<
- UINT32 DeassertMemRstX:1 ; ///<
- UINT32 AssertCke:1 ; ///<
- UINT32 SendZQCmd:1 ; ///<
- UINT32 Reserved_30_30:1 ; ///<
- UINT32 EnDramInit:1 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F2x7C_STRUCT;
-
-// **** D18F2x80 Register Definition ****
-// Address
-#define D18F2x80_ADDRESS 0x80
-
-// Type
-#define D18F2x80_TYPE TYPE_D18F2
-// Field Data
-#define D18F2x80_Dimm0AddrMap_OFFSET 0
-#define D18F2x80_Dimm0AddrMap_WIDTH 4
-#define D18F2x80_Dimm0AddrMap_MASK 0xf
-#define D18F2x80_Dimm1AddrMap_OFFSET 4
-#define D18F2x80_Dimm1AddrMap_WIDTH 4
-#define D18F2x80_Dimm1AddrMap_MASK 0xf0
-#define D18F2x80_Reserved_31_8_OFFSET 8
-#define D18F2x80_Reserved_31_8_WIDTH 24
-#define D18F2x80_Reserved_31_8_MASK 0xffffff00
-
-/// D18F2x80
-typedef union {
- struct { ///<
- UINT32 Dimm0AddrMap:4 ; ///<
- UINT32 Dimm1AddrMap:4 ; ///<
- UINT32 Reserved_31_8:24; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F2x80_STRUCT;
-
-// **** D18F2x084 Register Definition ****
-// Address
-#define D18F2x084_ADDRESS 0x84
-
-// Type
-#define D18F2x084_TYPE TYPE_D18F2
-// Field Data
-#define D18F2x084_BurstCtrl_OFFSET 0
-#define D18F2x084_BurstCtrl_WIDTH 2
-#define D18F2x084_BurstCtrl_MASK 0x3
-#define D18F2x084_Reserved_3_2_OFFSET 2
-#define D18F2x084_Reserved_3_2_WIDTH 2
-#define D18F2x084_Reserved_3_2_MASK 0xc
-#define D18F2x084_Twr_OFFSET 4
-#define D18F2x084_Twr_WIDTH 3
-#define D18F2x084_Twr_MASK 0x70
-#define D18F2x084_Reserved_19_7_OFFSET 7
-#define D18F2x084_Reserved_19_7_WIDTH 13
-#define D18F2x084_Reserved_19_7_MASK 0xfff80
-#define D18F2x084_Tcwl_OFFSET 20
-#define D18F2x084_Tcwl_WIDTH 3
-#define D18F2x084_Tcwl_MASK 0x700000
-#define D18F2x084_PchgPDModeSel_OFFSET 23
-#define D18F2x084_PchgPDModeSel_WIDTH 1
-#define D18F2x084_PchgPDModeSel_MASK 0x800000
-#define D18F2x084_Reserved_31_24_OFFSET 24
-#define D18F2x084_Reserved_31_24_WIDTH 8
-#define D18F2x084_Reserved_31_24_MASK 0xff000000
-
-/// D18F2x084
-typedef union {
- struct { ///<
- UINT32 BurstCtrl:2 ; ///<
- UINT32 Reserved_3_2:2 ; ///<
- UINT32 Twr:3 ; ///<
- UINT32 Reserved_19_7:13; ///<
- UINT32 Tcwl:3 ; ///<
- UINT32 PchgPDModeSel:1 ; ///<
- UINT32 Reserved_31_24:8 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F2x084_STRUCT;
-
-// **** D18F2x08C Register Definition ****
-// Address
-#define D18F2x08C_ADDRESS 0x8c
-
-// Type
-#define D18F2x08C_TYPE TYPE_D18F2
-// Field Data
-#define D18F2x08C_TrwtWB_OFFSET 0
-#define D18F2x08C_TrwtWB_WIDTH 4
-#define D18F2x08C_TrwtWB_MASK 0xf
-#define D18F2x08C_TrwtTO_OFFSET 4
-#define D18F2x08C_TrwtTO_WIDTH 4
-#define D18F2x08C_TrwtTO_MASK 0xf0
-#define D18F2x08C_Reserved_9_8_OFFSET 8
-#define D18F2x08C_Reserved_9_8_WIDTH 2
-#define D18F2x08C_Reserved_9_8_MASK 0x300
-#define D18F2x08C_Twrrd_1_0__OFFSET 10
-#define D18F2x08C_Twrrd_1_0__WIDTH 2
-#define D18F2x08C_Twrrd_1_0__MASK 0xc00
-#define D18F2x08C_Twrwr_1_0__OFFSET 12
-#define D18F2x08C_Twrwr_1_0__WIDTH 2
-#define D18F2x08C_Twrwr_1_0__MASK 0x3000
-#define D18F2x08C_Trdrd_1_0__OFFSET 14
-#define D18F2x08C_Trdrd_1_0__WIDTH 2
-#define D18F2x08C_Trdrd_1_0__MASK 0xc000
-#define D18F2x08C_Tref_OFFSET 16
-#define D18F2x08C_Tref_WIDTH 2
-#define D18F2x08C_Tref_MASK 0x30000
-#define D18F2x08C_DisAutoRefresh_OFFSET 18
-#define D18F2x08C_DisAutoRefresh_WIDTH 1
-#define D18F2x08C_DisAutoRefresh_MASK 0x40000
-#define D18F2x08C_Reserved_19_19_OFFSET 19
-#define D18F2x08C_Reserved_19_19_WIDTH 1
-#define D18F2x08C_Reserved_19_19_MASK 0x80000
-#define D18F2x08C_Trfc0_OFFSET 20
-#define D18F2x08C_Trfc0_WIDTH 3
-#define D18F2x08C_Trfc0_MASK 0x700000
-#define D18F2x08C_Trfc1_OFFSET 23
-#define D18F2x08C_Trfc1_WIDTH 3
-#define D18F2x08C_Trfc1_MASK 0x3800000
-#define D18F2x08C_Reserved_31_26_OFFSET 26
-#define D18F2x08C_Reserved_31_26_WIDTH 6
-#define D18F2x08C_Reserved_31_26_MASK 0xfc000000
-
-/// D18F2x08C
-typedef union {
- struct { ///<
- UINT32 TrwtWB:4 ; ///<
- UINT32 TrwtTO:4 ; ///<
- UINT32 Reserved_9_8:2 ; ///<
- UINT32 Twrrd_1_0_:2 ; ///<
- UINT32 Twrwr_1_0_:2 ; ///<
- UINT32 Trdrd_1_0_:2 ; ///<
- UINT32 Tref:2 ; ///<
- UINT32 DisAutoRefresh:1 ; ///<
- UINT32 Reserved_19_19:1 ; ///<
- UINT32 Trfc0:3 ; ///<
- UINT32 Trfc1:3 ; ///<
- UINT32 Reserved_31_26:6 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F2x08C_STRUCT;
-
-// **** D18F2x090 Register Definition ****
-// Address
-#define D18F2x090_ADDRESS 0x90
-
-// Type
-#define D18F2x090_TYPE TYPE_D18F2
-// Field Data
-#define D18F2x090_Reserved_0_0_OFFSET 0
-#define D18F2x090_Reserved_0_0_WIDTH 1
-#define D18F2x090_Reserved_0_0_MASK 0x1
-#define D18F2x090_ExitSelfRef_OFFSET 1
-#define D18F2x090_ExitSelfRef_WIDTH 1
-#define D18F2x090_ExitSelfRef_MASK 0x2
-#define D18F2x090_Reserved_16_2_OFFSET 2
-#define D18F2x090_Reserved_16_2_WIDTH 15
-#define D18F2x090_Reserved_16_2_MASK 0x1fffc
-#define D18F2x090_EnterSelfRef_OFFSET 17
-#define D18F2x090_EnterSelfRef_WIDTH 1
-#define D18F2x090_EnterSelfRef_MASK 0x20000
-#define D18F2x090_Reserved_19_18_OFFSET 18
-#define D18F2x090_Reserved_19_18_WIDTH 2
-#define D18F2x090_Reserved_19_18_MASK 0xc0000
-#define D18F2x090_DynPageCloseEn_OFFSET 20
-#define D18F2x090_DynPageCloseEn_WIDTH 1
-#define D18F2x090_DynPageCloseEn_MASK 0x100000
-#define D18F2x090_IdleCycInit_OFFSET 21
-#define D18F2x090_IdleCycInit_WIDTH 2
-#define D18F2x090_IdleCycInit_MASK 0x600000
-#define D18F2x090_ForceAutoPchg_OFFSET 23
-#define D18F2x090_ForceAutoPchg_WIDTH 1
-#define D18F2x090_ForceAutoPchg_MASK 0x800000
-#define D18F2x090_Reserved_24_24_OFFSET 24
-#define D18F2x090_Reserved_24_24_WIDTH 1
-#define D18F2x090_Reserved_24_24_MASK 0x1000000
-#define D18F2x090_EnDispAutoPrecharge_OFFSET 25
-#define D18F2x090_EnDispAutoPrecharge_WIDTH 1
-#define D18F2x090_EnDispAutoPrecharge_MASK 0x2000000
-#define D18F2x090_DbeSkidBufDis_OFFSET 26
-#define D18F2x090_DbeSkidBufDis_WIDTH 1
-#define D18F2x090_DbeSkidBufDis_MASK 0x4000000
-#define D18F2x090_DisDllShutdownSR_OFFSET 27
-#define D18F2x090_DisDllShutdownSR_WIDTH 1
-#define D18F2x090_DisDllShutdownSR_MASK 0x8000000
-#define D18F2x090_Reserved_31_28_OFFSET 28
-#define D18F2x090_Reserved_31_28_WIDTH 4
-#define D18F2x090_Reserved_31_28_MASK 0xf0000000
-
-/// D18F2x090
-typedef union {
- struct { ///<
- UINT32 Reserved_0_0:1 ; ///<
- UINT32 ExitSelfRef:1 ; ///<
- UINT32 Reserved_16_2:15; ///<
- UINT32 EnterSelfRef:1 ; ///<
- UINT32 Reserved_19_18:2 ; ///<
- UINT32 DynPageCloseEn:1 ; ///<
- UINT32 IdleCycInit:2 ; ///<
- UINT32 ForceAutoPchg:1 ; ///<
- UINT32 Reserved_24_24:1 ; ///<
- UINT32 EnDispAutoPrecharge:1 ; ///<
- UINT32 DbeSkidBufDis:1 ; ///<
- UINT32 DisDllShutdownSR:1 ; ///<
- UINT32 Reserved_31_28:4 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F2x090_STRUCT;
-
-// **** D18F2x9C Register Definition ****
-// Address
-#define D18F2x9C_ADDRESS 0x9c
-
-// **** D18F2xA0 Register Definition ****
-// Address
-#define D18F2xA0_ADDRESS 0xa0
-
-// Type
-#define D18F2xA0_TYPE TYPE_D18F2
-// Field Data
-#define D18F2xA0_Reserved_31_0_OFFSET 0
-#define D18F2xA0_Reserved_31_0_WIDTH 32
-#define D18F2xA0_Reserved_31_0_MASK 0xffffffff
-
-/// D18F2xA0
-typedef union {
- struct { ///<
- UINT32 Reserved_31_0:32; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F2xA0_STRUCT;
-
-// **** D18F2xA4 Register Definition ****
-// Address
-#define D18F2xA4_ADDRESS 0xa4
-
-// Type
-#define D18F2xA4_TYPE TYPE_D18F2
-// Field Data
-#define D18F2xA4_DoubleTrefRateEn_OFFSET 0
-#define D18F2xA4_DoubleTrefRateEn_WIDTH 1
-#define D18F2xA4_DoubleTrefRateEn_MASK 0x1
-#define D18F2xA4_ThrottleEn_OFFSET 1
-#define D18F2xA4_ThrottleEn_WIDTH 2
-#define D18F2xA4_ThrottleEn_MASK 0x6
-#define D18F2xA4_Reserved_31_3_OFFSET 3
-#define D18F2xA4_Reserved_31_3_WIDTH 29
-#define D18F2xA4_Reserved_31_3_MASK 0xfffffff8
-
-/// D18F2xA4
-typedef union {
- struct { ///<
- UINT32 DoubleTrefRateEn:1 ; ///<
- UINT32 ThrottleEn:2 ; ///<
- UINT32 Reserved_31_3:29; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F2xA4_STRUCT;
-
-// **** D18F2xA8 Register Definition ****
-// Address
-#define D18F2xA8_ADDRESS 0xa8
-
-// Type
-#define D18F2xA8_TYPE TYPE_D18F2
-// Field Data
-#define D18F2xA8_Reserved_19_0_OFFSET 0
-#define D18F2xA8_Reserved_19_0_WIDTH 20
-#define D18F2xA8_Reserved_19_0_MASK 0xfffff
-#define D18F2xA8_BankSwap_OFFSET 20
-#define D18F2xA8_BankSwap_WIDTH 1
-#define D18F2xA8_BankSwap_MASK 0x100000
-#define D18F2xA8_DbeGskMemClkAlignMode_OFFSET 21
-#define D18F2xA8_DbeGskMemClkAlignMode_WIDTH 2
-#define D18F2xA8_DbeGskMemClkAlignMode_MASK 0x600000
-#define D18F2xA8_Reserved_31_23_OFFSET 23
-#define D18F2xA8_Reserved_31_23_WIDTH 9
-#define D18F2xA8_Reserved_31_23_MASK 0xff800000
-
-/// D18F2xA8
-typedef union {
- struct { ///<
- UINT32 Reserved_19_0:20; ///<
- UINT32 BankSwap:1 ; ///<
- UINT32 DbeGskMemClkAlignMode:2 ; ///<
- UINT32 Reserved_31_23:9 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F2xA8_STRUCT;
-
-// **** D18F2xAC Register Definition ****
-// Address
-#define D18F2xAC_ADDRESS 0xac
-
-// Type
-#define D18F2xAC_TYPE TYPE_D18F2
-// Field Data
-#define D18F2xAC_MemTempHot_OFFSET 0
-#define D18F2xAC_MemTempHot_WIDTH 1
-#define D18F2xAC_MemTempHot_MASK 0x1
-#define D18F2xAC_Reserved_31_1_OFFSET 1
-#define D18F2xAC_Reserved_31_1_WIDTH 31
-#define D18F2xAC_Reserved_31_1_MASK 0xfffffffe
-
-/// D18F2xAC
-typedef union {
- struct { ///<
- UINT32 MemTempHot:1 ; ///<
- UINT32 Reserved_31_1:31; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F2xAC_STRUCT;
-
-// **** D18F2xF0 Register Definition ****
-// Address
-#define D18F2xF0_ADDRESS 0xf0
-
-// Type
-#define D18F2xF0_TYPE TYPE_D18F2
-// Field Data
-#define D18F2xF0_DctOffset_OFFSET 0
-#define D18F2xF0_DctOffset_WIDTH 28
-#define D18F2xF0_DctOffset_MASK 0xfffffff
-#define D18F2xF0_Reserved_29_28_OFFSET 28
-#define D18F2xF0_Reserved_29_28_WIDTH 2
-#define D18F2xF0_Reserved_29_28_MASK 0x30000000
-#define D18F2xF0_DctAccessWrite_OFFSET 30
-#define D18F2xF0_DctAccessWrite_WIDTH 1
-#define D18F2xF0_DctAccessWrite_MASK 0x40000000
-#define D18F2xF0_DctAccessDone_OFFSET 31
-#define D18F2xF0_DctAccessDone_WIDTH 1
-#define D18F2xF0_DctAccessDone_MASK 0x80000000
-
-/// D18F2xF0
-typedef union {
- struct { ///<
- UINT32 DctOffset:28; ///<
- UINT32 Reserved_29_28:2 ; ///<
- UINT32 DctAccessWrite:1 ; ///<
- UINT32 DctAccessDone:1 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F2xF0_STRUCT;
-
-// **** D18F2xF4 Register Definition ****
-// Address
-#define D18F2xF4_ADDRESS 0xf4
-
-// Type
-#define D18F2xF4_TYPE TYPE_D18F2
-// Field Data
-#define D18F2xF4_DctExtDataPort_OFFSET 0
-#define D18F2xF4_DctExtDataPort_WIDTH 32
-#define D18F2xF4_DctExtDataPort_MASK 0xffffffff
-
-/// D18F2xF4
-typedef union {
- struct { ///<
- UINT32 DctExtDataPort:32; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F2xF4_STRUCT;
-
-// **** D18F2x110 Register Definition ****
-// Address
-#define D18F2x110_ADDRESS 0x110
-
-// Type
-#define D18F2x110_TYPE TYPE_D18F2
-// Field Data
-#define D18F2x110_Reserved_2_0_OFFSET 0
-#define D18F2x110_Reserved_2_0_WIDTH 3
-#define D18F2x110_Reserved_2_0_MASK 0x7
-#define D18F2x110_MemClrInit_OFFSET 3
-#define D18F2x110_MemClrInit_WIDTH 1
-#define D18F2x110_MemClrInit_MASK 0x8
-#define D18F2x110_Reserved_7_4_OFFSET 4
-#define D18F2x110_Reserved_7_4_WIDTH 4
-#define D18F2x110_Reserved_7_4_MASK 0xf0
-#define D18F2x110_DramEnable_OFFSET 8
-#define D18F2x110_DramEnable_WIDTH 1
-#define D18F2x110_DramEnable_MASK 0x100
-#define D18F2x110_MemClrBusy_OFFSET 9
-#define D18F2x110_MemClrBusy_WIDTH 1
-#define D18F2x110_MemClrBusy_MASK 0x200
-#define D18F2x110_MemCleared_OFFSET 10
-#define D18F2x110_MemCleared_WIDTH 1
-#define D18F2x110_MemCleared_MASK 0x400
-#define D18F2x110_Reserved_31_11_OFFSET 11
-#define D18F2x110_Reserved_31_11_WIDTH 21
-#define D18F2x110_Reserved_31_11_MASK 0xfffff800
-
-/// D18F2x110
-typedef union {
- struct { ///<
- UINT32 Reserved_2_0:3 ; ///<
- UINT32 MemClrInit:1 ; ///<
- UINT32 Reserved_7_4:4 ; ///<
- UINT32 DramEnable:1 ; ///<
- UINT32 MemClrBusy:1 ; ///<
- UINT32 MemCleared:1 ; ///<
- UINT32 Reserved_31_11:21; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F2x110_STRUCT;
-
-// **** D18F2x114 Register Definition ****
-// Address
-#define D18F2x114_ADDRESS 0x114
-
-// Type
-#define D18F2x114_TYPE TYPE_D18F2
-// Field Data
-#define D18F2x114_Reserved_8_0_OFFSET 0
-#define D18F2x114_Reserved_8_0_WIDTH 9
-#define D18F2x114_Reserved_8_0_MASK 0x1ff
-#define D18F2x114_DctSelBankSwap_OFFSET 9
-#define D18F2x114_DctSelBankSwap_WIDTH 1
-#define D18F2x114_DctSelBankSwap_MASK 0x200
-#define D18F2x114_Reserved_31_10_OFFSET 10
-#define D18F2x114_Reserved_31_10_WIDTH 22
-#define D18F2x114_Reserved_31_10_MASK 0xfffffc00
-
-/// D18F2x114
-typedef union {
- struct { ///<
- UINT32 Reserved_8_0:9 ; ///<
- UINT32 DctSelBankSwap:1 ; ///<
- UINT32 Reserved_31_10:22; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F2x114_STRUCT;
-
-// **** D18F3x64 Register Definition ****
-// Address
-#define D18F3x64_ADDRESS 0x64
-
-// Type
-#define D18F3x64_TYPE TYPE_D18F3
-// Field Data
-#define D18F3x64_HtcEn_OFFSET 0
-#define D18F3x64_HtcEn_WIDTH 1
-#define D18F3x64_HtcEn_MASK 0x1
-#define D18F3x64_Reserved_3_1_OFFSET 1
-#define D18F3x64_Reserved_3_1_WIDTH 3
-#define D18F3x64_Reserved_3_1_MASK 0xe
-#define D18F3x64_HtcAct_OFFSET 4
-#define D18F3x64_HtcAct_WIDTH 1
-#define D18F3x64_HtcAct_MASK 0x10
-#define D18F3x64_HtcActSts_OFFSET 5
-#define D18F3x64_HtcActSts_WIDTH 1
-#define D18F3x64_HtcActSts_MASK 0x20
-#define D18F3x64_PslApicHiEn_OFFSET 6
-#define D18F3x64_PslApicHiEn_WIDTH 1
-#define D18F3x64_PslApicHiEn_MASK 0x40
-#define D18F3x64_PslApicLoEn_OFFSET 7
-#define D18F3x64_PslApicLoEn_WIDTH 1
-#define D18F3x64_PslApicLoEn_MASK 0x80
-#define D18F3x64_Reserved_15_8_OFFSET 8
-#define D18F3x64_Reserved_15_8_WIDTH 8
-#define D18F3x64_Reserved_15_8_MASK 0xff00
-#define D18F3x64_HtcTmpLmt_OFFSET 16
-#define D18F3x64_HtcTmpLmt_WIDTH 7
-#define D18F3x64_HtcTmpLmt_MASK 0x7f0000
-#define D18F3x64_HtcSlewSel_OFFSET 23
-#define D18F3x64_HtcSlewSel_WIDTH 1
-#define D18F3x64_HtcSlewSel_MASK 0x800000
-#define D18F3x64_HtcHystLmt_OFFSET 24
-#define D18F3x64_HtcHystLmt_WIDTH 4
-#define D18F3x64_HtcHystLmt_MASK 0xf000000
-#define D18F3x64_HtcPstateLimit_OFFSET 28
-#define D18F3x64_HtcPstateLimit_WIDTH 3
-#define D18F3x64_HtcPstateLimit_MASK 0x70000000
-#define D18F3x64_HtcLock_OFFSET 31
-#define D18F3x64_HtcLock_WIDTH 1
-#define D18F3x64_HtcLock_MASK 0x80000000
-
-/// D18F3x64
-typedef union {
- struct { ///<
- UINT32 HtcEn:1 ; ///<
- UINT32 Reserved_3_1:3 ; ///<
- UINT32 HtcAct:1 ; ///<
- UINT32 HtcActSts:1 ; ///<
- UINT32 PslApicHiEn:1 ; ///<
- UINT32 PslApicLoEn:1 ; ///<
- UINT32 Reserved_15_8:8 ; ///<
- UINT32 HtcTmpLmt:7 ; ///<
- UINT32 HtcSlewSel:1 ; ///<
- UINT32 HtcHystLmt:4 ; ///<
- UINT32 HtcPstateLimit:3 ; ///<
- UINT32 HtcLock:1 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F3x64_STRUCT;
-
-// **** D18F3x6C Register Definition ****
-// Address
-#define D18F3x6C_ADDRESS 0x6c
-
-// Type
-#define D18F3x6C_TYPE TYPE_D18F3
-// Field Data
-#define D18F3x6C_UpLoPreqDBC_OFFSET 0
-#define D18F3x6C_UpLoPreqDBC_WIDTH 4
-#define D18F3x6C_UpLoPreqDBC_MASK 0xf
-#define D18F3x6C_UpLoNpreqDBC_OFFSET 4
-#define D18F3x6C_UpLoNpreqDBC_WIDTH 4
-#define D18F3x6C_UpLoNpreqDBC_MASK 0xf0
-#define D18F3x6C_UpLoRespDBC_OFFSET 8
-#define D18F3x6C_UpLoRespDBC_WIDTH 4
-#define D18F3x6C_UpLoRespDBC_MASK 0xf00
-#define D18F3x6C_Reserved_15_12_OFFSET 12
-#define D18F3x6C_Reserved_15_12_WIDTH 4
-#define D18F3x6C_Reserved_15_12_MASK 0xf000
-#define D18F3x6C_UpHiPreqDBC_OFFSET 16
-#define D18F3x6C_UpHiPreqDBC_WIDTH 4
-#define D18F3x6C_UpHiPreqDBC_MASK 0xf0000
-#define D18F3x6C_UpHiNpreqDBC_OFFSET 20
-#define D18F3x6C_UpHiNpreqDBC_WIDTH 4
-#define D18F3x6C_UpHiNpreqDBC_MASK 0xf00000
-#define D18F3x6C_Reserved_31_24_OFFSET 24
-#define D18F3x6C_Reserved_31_24_WIDTH 8
-#define D18F3x6C_Reserved_31_24_MASK 0xff000000
-
-/// D18F3x6C
-typedef union {
- struct { ///<
- UINT32 UpLoPreqDBC:4 ; ///<
- UINT32 UpLoNpreqDBC:4 ; ///<
- UINT32 UpLoRespDBC:4 ; ///<
- UINT32 Reserved_15_12:4 ; ///<
- UINT32 UpHiPreqDBC:4 ; ///<
- UINT32 UpHiNpreqDBC:4 ; ///<
- UINT32 Reserved_31_24:8 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F3x6C_STRUCT;
-
-// **** D18F3x74 Register Definition ****
-// Address
-#define D18F3x74_ADDRESS 0x74
-
-// Type
-#define D18F3x74_TYPE TYPE_D18F3
-// Field Data
-#define D18F3x74_UpLoPreqCBC_OFFSET 0
-#define D18F3x74_UpLoPreqCBC_WIDTH 4
-#define D18F3x74_UpLoPreqCBC_MASK 0xf
-#define D18F3x74_UpLoNpreqCBC_OFFSET 4
-#define D18F3x74_UpLoNpreqCBC_WIDTH 4
-#define D18F3x74_UpLoNpreqCBC_MASK 0xf0
-#define D18F3x74_UpLoRespCBC_OFFSET 8
-#define D18F3x74_UpLoRespCBC_WIDTH 4
-#define D18F3x74_UpLoRespCBC_MASK 0xf00
-#define D18F3x74_Reserved_15_12_OFFSET 12
-#define D18F3x74_Reserved_15_12_WIDTH 4
-#define D18F3x74_Reserved_15_12_MASK 0xf000
-#define D18F3x74_UpHiPreqCBC_OFFSET 16
-#define D18F3x74_UpHiPreqCBC_WIDTH 4
-#define D18F3x74_UpHiPreqCBC_MASK 0xf0000
-#define D18F3x74_UpHiNpreqCBC_OFFSET 20
-#define D18F3x74_UpHiNpreqCBC_WIDTH 4
-#define D18F3x74_UpHiNpreqCBC_MASK 0xf00000
-#define D18F3x74_Reserved_31_24_OFFSET 24
-#define D18F3x74_Reserved_31_24_WIDTH 8
-#define D18F3x74_Reserved_31_24_MASK 0xff000000
-
-/// D18F3x74
-typedef union {
- struct { ///<
- UINT32 UpLoPreqCBC:4 ; ///<
- UINT32 UpLoNpreqCBC:4 ; ///<
- UINT32 UpLoRespCBC:4 ; ///<
- UINT32 Reserved_15_12:4 ; ///<
- UINT32 UpHiPreqCBC:4 ; ///<
- UINT32 UpHiNpreqCBC:4 ; ///<
- UINT32 Reserved_31_24:8 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F3x74_STRUCT;
-
-// **** D18F3x7C Register Definition ****
-// Address
-#define D18F3x7C_ADDRESS 0x7c
-
-// Type
-#define D18F3x7C_TYPE TYPE_D18F3
-// Field Data
-#define D18F3x7C_CpuBC_OFFSET 0
-#define D18F3x7C_CpuBC_WIDTH 6
-#define D18F3x7C_CpuBC_MASK 0x3f
-#define D18F3x7C_Reserved_7_6_OFFSET 6
-#define D18F3x7C_Reserved_7_6_WIDTH 2
-#define D18F3x7C_Reserved_7_6_MASK 0xc0
-#define D18F3x7C_LoPriPBC_OFFSET 8
-#define D18F3x7C_LoPriPBC_WIDTH 6
-#define D18F3x7C_LoPriPBC_MASK 0x3f00
-#define D18F3x7C_Reserved_15_14_OFFSET 14
-#define D18F3x7C_Reserved_15_14_WIDTH 2
-#define D18F3x7C_Reserved_15_14_MASK 0xc000
-#define D18F3x7C_LoPriNPBC_OFFSET 16
-#define D18F3x7C_LoPriNPBC_WIDTH 6
-#define D18F3x7C_LoPriNPBC_MASK 0x3f0000
-#define D18F3x7C_Reserved_23_22_OFFSET 22
-#define D18F3x7C_Reserved_23_22_WIDTH 2
-#define D18F3x7C_Reserved_23_22_MASK 0xc00000
-#define D18F3x7C_FreePoolBC_OFFSET 24
-#define D18F3x7C_FreePoolBC_WIDTH 6
-#define D18F3x7C_FreePoolBC_MASK 0x3f000000
-#define D18F3x7C_Reserved_31_30_OFFSET 30
-#define D18F3x7C_Reserved_31_30_WIDTH 2
-#define D18F3x7C_Reserved_31_30_MASK 0xc0000000
-
-/// D18F3x7C
-typedef union {
- struct { ///<
- UINT32 CpuBC:6 ; ///<
- UINT32 Reserved_7_6:2 ; ///<
- UINT32 LoPriPBC:6 ; ///<
- UINT32 Reserved_15_14:2 ; ///<
- UINT32 LoPriNPBC:6 ; ///<
- UINT32 Reserved_23_22:2 ; ///<
- UINT32 FreePoolBC:6 ; ///<
- UINT32 Reserved_31_30:2 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F3x7C_STRUCT;
-
-// **** D18F3xD8 Register Definition ****
-// Address
-#define D18F3xD8_ADDRESS 0xd8
-
-// Type
-#define D18F3xD8_TYPE TYPE_D18F3
-// Field Data
-#define D18F3xD8_Reserved_3_0_OFFSET 0
-#define D18F3xD8_Reserved_3_0_WIDTH 4
-#define D18F3xD8_Reserved_3_0_MASK 0xf
-#define D18F3xD8_VSRampSlamTime_OFFSET 4
-#define D18F3xD8_VSRampSlamTime_WIDTH 3
-#define D18F3xD8_VSRampSlamTime_MASK 0x70
-#define D18F3xD8_ExtndTriDly_OFFSET 7
-#define D18F3xD8_ExtndTriDly_WIDTH 5
-#define D18F3xD8_ExtndTriDly_MASK 0xf80
-#define D18F3xD8_Reserved_31_12_OFFSET 12
-#define D18F3xD8_Reserved_31_12_WIDTH 20
-#define D18F3xD8_Reserved_31_12_MASK 0xfffff000
-
-/// D18F3xD8
-typedef union {
- struct { ///<
- UINT32 Reserved_3_0:4 ; ///<
- UINT32 VSRampSlamTime:3 ; ///<
- UINT32 ExtndTriDly:5 ; ///<
- UINT32 Reserved_31_12:20; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F3xD8_STRUCT;
-
-// **** D18F3xDC Register Definition ****
-// Address
-#define D18F3xDC_ADDRESS 0xdc
-
-// Type
-#define D18F3xDC_TYPE TYPE_D18F3
-// Field Data
-#define D18F3xDC_Reserved_7_0_OFFSET 0
-#define D18F3xDC_Reserved_7_0_WIDTH 8
-#define D18F3xDC_Reserved_7_0_MASK 0xff
-#define D18F3xDC_PstateMaxVal_OFFSET 8
-#define D18F3xDC_PstateMaxVal_WIDTH 3
-#define D18F3xDC_PstateMaxVal_MASK 0x700
-#define D18F3xDC_Reserved_11_11_OFFSET 11
-#define D18F3xDC_Reserved_11_11_WIDTH 1
-#define D18F3xDC_Reserved_11_11_MASK 0x800
-#define D18F3xDC_NbPs0Vid_OFFSET 12
-#define D18F3xDC_NbPs0Vid_WIDTH 7
-#define D18F3xDC_NbPs0Vid_MASK 0x7f000
-#define D18F3xDC_NclkFreqDone_OFFSET 19
-#define D18F3xDC_NclkFreqDone_WIDTH 1
-#define D18F3xDC_NclkFreqDone_MASK 0x80000
-#define D18F3xDC_NbPs0NclkDiv_OFFSET 20
-#define D18F3xDC_NbPs0NclkDiv_WIDTH 7
-#define D18F3xDC_NbPs0NclkDiv_MASK 0x7f00000
-#define D18F3xDC_NbClockGateHyst_OFFSET 27
-#define D18F3xDC_NbClockGateHyst_WIDTH 3
-#define D18F3xDC_NbClockGateHyst_MASK 0x38000000
-#define D18F3xDC_NbClockGateEn_OFFSET 30
-#define D18F3xDC_NbClockGateEn_WIDTH 1
-#define D18F3xDC_NbClockGateEn_MASK 0x40000000
-#define D18F3xDC_CnbCifClockGateEn_OFFSET 31
-#define D18F3xDC_CnbCifClockGateEn_WIDTH 1
-#define D18F3xDC_CnbCifClockGateEn_MASK 0x80000000
-
-/// D18F3xDC
-typedef union {
- struct { ///<
- UINT32 Reserved_7_0:8 ; ///<
- UINT32 PstateMaxVal:3 ; ///<
- UINT32 Reserved_11_11:1 ; ///<
- UINT32 NbPs0Vid:7 ; ///<
- UINT32 NclkFreqDone:1 ; ///<
- UINT32 NbPs0NclkDiv:7 ; ///<
- UINT32 NbClockGateHyst:3 ; ///<
- UINT32 NbClockGateEn:1 ; ///<
- UINT32 CnbCifClockGateEn:1 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F3xDC_STRUCT;
-
-// **** D18F3x15C Register Definition ****
-// Address
-#define D18F3x15C_ADDRESS 0x15c
-
-// Type
-#define D18F3x15C_TYPE TYPE_D18F3
-// Field Data
-#define D18F3x15C_SclkVidLevel0_OFFSET 0
-#define D18F3x15C_SclkVidLevel0_WIDTH 7
-#define D18F3x15C_SclkVidLevel0_MASK 0x7f
-#define D18F3x15C_Reserved_7_7_OFFSET 7
-#define D18F3x15C_Reserved_7_7_WIDTH 1
-#define D18F3x15C_Reserved_7_7_MASK 0x80
-#define D18F3x15C_SclkVidLevel1_OFFSET 8
-#define D18F3x15C_SclkVidLevel1_WIDTH 7
-#define D18F3x15C_SclkVidLevel1_MASK 0x7f00
-#define D18F3x15C_Reserved_15_15_OFFSET 15
-#define D18F3x15C_Reserved_15_15_WIDTH 1
-#define D18F3x15C_Reserved_15_15_MASK 0x8000
-#define D18F3x15C_SclkVidLevel2_OFFSET 16
-#define D18F3x15C_SclkVidLevel2_WIDTH 7
-#define D18F3x15C_SclkVidLevel2_MASK 0x7f0000
-#define D18F3x15C_Reserved_23_23_OFFSET 23
-#define D18F3x15C_Reserved_23_23_WIDTH 1
-#define D18F3x15C_Reserved_23_23_MASK 0x800000
-#define D18F3x15C_SclkVidLevel3_OFFSET 24
-#define D18F3x15C_SclkVidLevel3_WIDTH 7
-#define D18F3x15C_SclkVidLevel3_MASK 0x7f000000
-#define D18F3x15C_Reserved_31_31_OFFSET 31
-#define D18F3x15C_Reserved_31_31_WIDTH 1
-#define D18F3x15C_Reserved_31_31_MASK 0x80000000
-
-/// D18F3x15C
-typedef union {
- struct { ///<
- UINT32 SclkVidLevel0:7 ; ///<
- UINT32 Reserved_7_7:1 ; ///<
- UINT32 SclkVidLevel1:7 ; ///<
- UINT32 Reserved_15_15:1 ; ///<
- UINT32 SclkVidLevel2:7 ; ///<
- UINT32 Reserved_23_23:1 ; ///<
- UINT32 SclkVidLevel3:7 ; ///<
- UINT32 Reserved_31_31:1 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F3x15C_STRUCT;
-
-// **** D18F3x17C Register Definition ****
-// Address
-#define D18F3x17C_ADDRESS 0x17c
-
-// Type
-#define D18F3x17C_TYPE TYPE_D18F3
-// Field Data
-#define D18F3x17C_HiPriPBC_OFFSET 0
-#define D18F3x17C_HiPriPBC_WIDTH 6
-#define D18F3x17C_HiPriPBC_MASK 0x3f
-#define D18F3x17C_Reserved_7_6_OFFSET 6
-#define D18F3x17C_Reserved_7_6_WIDTH 2
-#define D18F3x17C_Reserved_7_6_MASK 0xc0
-#define D18F3x17C_HiPriNPBC_OFFSET 8
-#define D18F3x17C_HiPriNPBC_WIDTH 6
-#define D18F3x17C_HiPriNPBC_MASK 0x3f00
-#define D18F3x17C_Reserved_31_14_OFFSET 14
-#define D18F3x17C_Reserved_31_14_WIDTH 18
-#define D18F3x17C_Reserved_31_14_MASK 0xffffc000
-
-/// D18F3x17C
-typedef union {
- struct { ///<
- UINT32 HiPriPBC:6 ; ///<
- UINT32 Reserved_7_6:2 ; ///<
- UINT32 HiPriNPBC:6 ; ///<
- UINT32 Reserved_31_14:18; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F3x17C_STRUCT;
-
-// **** D18F4x12C Register Definition ****
-// Address
-#define D18F4x12C_ADDRESS 0x12c
-
-// Type
-#define D18F4x12C_TYPE TYPE_D18F4
-// Field Data
-#define D18F4x12C_C6Base_35_24__OFFSET 0
-#define D18F4x12C_C6Base_35_24__WIDTH 12
-#define D18F4x12C_C6Base_35_24__MASK 0xfff
-#define D18F4x12C_Reserved_31_12_OFFSET 12
-#define D18F4x12C_Reserved_31_12_WIDTH 20
-#define D18F4x12C_Reserved_31_12_MASK 0xfffff000
-
-/// D18F4x12C
-typedef union {
- struct { ///<
- UINT32 C6Base_35_24_:12; ///<
- UINT32 Reserved_31_12:20; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F4x12C_STRUCT;
-
-// **** D18F4x164 Register Definition ****
-// Address
-#define D18F4x164_ADDRESS 0x164
-
-// Type
-#define D18F4x164_TYPE TYPE_D18F4
-// Field Data
-#define D18F4x164_FixedErrata_OFFSET 0
-#define D18F4x164_FixedErrata_WIDTH 32
-#define D18F4x164_FixedErrata_MASK 0xffffffff
-
-/// D18F4x164
-typedef union {
- struct { ///<
- UINT32 FixedErrata:32; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F4x164_STRUCT;
-
-// **** D18F6x90 Register Definition ****
-// Address
-#define D18F6x90_ADDRESS 0x90
-
-// Type
-#define D18F6x90_TYPE TYPE_D18F6
-// Field Data
-#define D18F6x90_NbPs1NclkDiv_OFFSET 0
-#define D18F6x90_NbPs1NclkDiv_WIDTH 7
-#define D18F6x90_NbPs1NclkDiv_MASK 0x7f
-#define D18F6x90_Reserved_7_7_OFFSET 7
-#define D18F6x90_Reserved_7_7_WIDTH 1
-#define D18F6x90_Reserved_7_7_MASK 0x80
-#define D18F6x90_NbPs1Vid_OFFSET 8
-#define D18F6x90_NbPs1Vid_WIDTH 7
-#define D18F6x90_NbPs1Vid_MASK 0x7f00
-#define D18F6x90_Reserved_15_15_OFFSET 15
-#define D18F6x90_Reserved_15_15_WIDTH 1
-#define D18F6x90_Reserved_15_15_MASK 0x8000
-#define D18F6x90_NbPs1GnbSlowIgn_OFFSET 16
-#define D18F6x90_NbPs1GnbSlowIgn_WIDTH 1
-#define D18F6x90_NbPs1GnbSlowIgn_MASK 0x10000
-#define D18F6x90_Reserved_19_17_OFFSET 17
-#define D18F6x90_Reserved_19_17_WIDTH 3
-#define D18F6x90_Reserved_19_17_MASK 0xe0000
-#define D18F6x90_NbPsLock_OFFSET 20
-#define D18F6x90_NbPsLock_WIDTH 1
-#define D18F6x90_NbPsLock_MASK 0x100000
-#define D18F6x90_Reserved_27_21_OFFSET 21
-#define D18F6x90_Reserved_27_21_WIDTH 7
-#define D18F6x90_Reserved_27_21_MASK 0xfe00000
-#define D18F6x90_NbPsForceReq_OFFSET 28
-#define D18F6x90_NbPsForceReq_WIDTH 1
-#define D18F6x90_NbPsForceReq_MASK 0x10000000
-#define D18F6x90_NbPsForceSel_OFFSET 29
-#define D18F6x90_NbPsForceSel_WIDTH 1
-#define D18F6x90_NbPsForceSel_MASK 0x20000000
-#define D18F6x90_NbPsCtrlDis_OFFSET 30
-#define D18F6x90_NbPsCtrlDis_WIDTH 1
-#define D18F6x90_NbPsCtrlDis_MASK 0x40000000
-#define D18F6x90_NbPsCap_OFFSET 31
-#define D18F6x90_NbPsCap_WIDTH 1
-#define D18F6x90_NbPsCap_MASK 0x80000000
-
-/// D18F6x90
-typedef union {
- struct { ///<
- UINT32 NbPs1NclkDiv:7 ; ///<
- UINT32 Reserved_7_7:1 ; ///<
- UINT32 NbPs1Vid:7 ; ///<
- UINT32 Reserved_15_15:1 ; ///<
- UINT32 NbPs1GnbSlowIgn:1 ; ///<
- UINT32 Reserved_19_17:3 ; ///<
- UINT32 NbPsLock:1 ; ///<
- UINT32 Reserved_27_21:7 ; ///<
- UINT32 NbPsForceReq:1 ; ///<
- UINT32 NbPsForceSel:1 ; ///<
- UINT32 NbPsCtrlDis:1 ; ///<
- UINT32 NbPsCap:1 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F6x90_STRUCT;
-
-// **** D18F6x94 Register Definition ****
-// Address
-#define D18F6x94_ADDRESS 0x94
-
-// Type
-#define D18F6x94_TYPE TYPE_D18F6
-// Field Data
-#define D18F6x94_CpuPstateThr_OFFSET 0
-#define D18F6x94_CpuPstateThr_WIDTH 3
-#define D18F6x94_CpuPstateThr_MASK 0x7
-#define D18F6x94_CpuPstateThrEn_OFFSET 3
-#define D18F6x94_CpuPstateThrEn_WIDTH 1
-#define D18F6x94_CpuPstateThrEn_MASK 0x8
-#define D18F6x94_NbPsNoTransOnDma_OFFSET 4
-#define D18F6x94_NbPsNoTransOnDma_WIDTH 1
-#define D18F6x94_NbPsNoTransOnDma_MASK 0x10
-#define D18F6x94_Reserved_19_5_OFFSET 5
-#define D18F6x94_Reserved_19_5_WIDTH 15
-#define D18F6x94_Reserved_19_5_MASK 0xfffe0
-#define D18F6x94_NbPsNonC0Timer_OFFSET 20
-#define D18F6x94_NbPsNonC0Timer_WIDTH 3
-#define D18F6x94_NbPsNonC0Timer_MASK 0x700000
-#define D18F6x94_NbPsC0Timer_OFFSET 23
-#define D18F6x94_NbPsC0Timer_WIDTH 3
-#define D18F6x94_NbPsC0Timer_MASK 0x3800000
-#define D18F6x94_NbPs1ResTmrMin_OFFSET 26
-#define D18F6x94_NbPs1ResTmrMin_WIDTH 3
-#define D18F6x94_NbPs1ResTmrMin_MASK 0x1c000000
-#define D18F6x94_NbPs0ResTmrMin_OFFSET 29
-#define D18F6x94_NbPs0ResTmrMin_WIDTH 3
-#define D18F6x94_NbPs0ResTmrMin_MASK 0xe0000000
-
-/// D18F6x94
-typedef union {
- struct { ///<
- UINT32 CpuPstateThr:3 ; ///<
- UINT32 CpuPstateThrEn:1 ; ///<
- UINT32 NbPsNoTransOnDma:1 ; ///<
- UINT32 Reserved_19_5:15; ///<
- UINT32 NbPsNonC0Timer:3 ; ///<
- UINT32 NbPsC0Timer:3 ; ///<
- UINT32 NbPs1ResTmrMin:3 ; ///<
- UINT32 NbPs0ResTmrMin:3 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F6x94_STRUCT;
-
-// **** D18F6x98 Register Definition ****
-// Address
-#define D18F6x98_ADDRESS 0x98
-
-// Type
-#define D18F6x98_TYPE TYPE_D18F6
-// Field Data
-#define D18F6x98_NbPsTransInFlight_OFFSET 0
-#define D18F6x98_NbPsTransInFlight_WIDTH 1
-#define D18F6x98_NbPsTransInFlight_MASK 0x1
-#define D18F6x98_NbPs1ActSts_OFFSET 1
-#define D18F6x98_NbPs1ActSts_WIDTH 1
-#define D18F6x98_NbPs1ActSts_MASK 0x2
-#define D18F6x98_NbPs1Act_OFFSET 2
-#define D18F6x98_NbPs1Act_WIDTH 1
-#define D18F6x98_NbPs1Act_MASK 0x4
-#define D18F6x98_Reserved_29_3_OFFSET 3
-#define D18F6x98_Reserved_29_3_WIDTH 27
-#define D18F6x98_Reserved_29_3_MASK 0x3ffffff8
-#define D18F6x98_NbPsCsrAccSel_OFFSET 30
-#define D18F6x98_NbPsCsrAccSel_WIDTH 1
-#define D18F6x98_NbPsCsrAccSel_MASK 0x40000000
-#define D18F6x98_NbPsDbgEn_OFFSET 31
-#define D18F6x98_NbPsDbgEn_WIDTH 1
-#define D18F6x98_NbPsDbgEn_MASK 0x80000000
-
-/// D18F6x98
-typedef union {
- struct { ///<
- UINT32 NbPsTransInFlight:1 ; ///<
- UINT32 NbPs1ActSts:1 ; ///<
- UINT32 NbPs1Act:1 ; ///<
- UINT32 Reserved_29_3:27; ///<
- UINT32 NbPsCsrAccSel:1 ; ///<
- UINT32 NbPsDbgEn:1 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F6x98_STRUCT;
-
-// **** D18F6x9C Register Definition ****
-// Address
-#define D18F6x9C_ADDRESS 0x9c
-
-// Type
-#define D18F6x9C_TYPE TYPE_D18F6
-// Field Data
-#define D18F6x9C_NclkRedDiv_OFFSET 0
-#define D18F6x9C_NclkRedDiv_WIDTH 7
-#define D18F6x9C_NclkRedDiv_MASK 0x7f
-#define D18F6x9C_NclkRedSelfRefrAlways_OFFSET 7
-#define D18F6x9C_NclkRedSelfRefrAlways_WIDTH 1
-#define D18F6x9C_NclkRedSelfRefrAlways_MASK 0x80
-#define D18F6x9C_NclkRampWithDllRelock_OFFSET 8
-#define D18F6x9C_NclkRampWithDllRelock_WIDTH 1
-#define D18F6x9C_NclkRampWithDllRelock_MASK 0x100
-#define D18F6x9C_Reserved_31_9_OFFSET 9
-#define D18F6x9C_Reserved_31_9_WIDTH 23
-#define D18F6x9C_Reserved_31_9_MASK 0xfffffe00
-
-/// D18F6x9C
-typedef union {
- struct { ///<
- UINT32 NclkRedDiv:7 ; ///<
- UINT32 NclkRedSelfRefrAlways:1 ; ///<
- UINT32 NclkRampWithDllRelock:1 ; ///<
- UINT32 Reserved_31_9:23; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F6x9C_STRUCT;
-
-// **** DxF0x00 Register Definition ****
-// Address
-#define DxF0x00_ADDRESS 0x0
-
-// Type
-#define DxF0x00_TYPE TYPE_D4F0
-// Field Data
-#define DxF0x00_VendorID_OFFSET 0
-#define DxF0x00_VendorID_WIDTH 16
-#define DxF0x00_VendorID_MASK 0xffff
-#define DxF0x00_DeviceID_OFFSET 16
-#define DxF0x00_DeviceID_WIDTH 16
-#define DxF0x00_DeviceID_MASK 0xffff0000
-
-/// DxF0x00
-typedef union {
- struct { ///<
- UINT32 VendorID:16; ///<
- UINT32 DeviceID:16; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0x00_STRUCT;
-
-// **** DxF0x04 Register Definition ****
-// Address
-#define DxF0x04_ADDRESS 0x4
-
-// Type
-#define DxF0x04_TYPE TYPE_D4F0
-// Field Data
-#define DxF0x04_IoAccessEn_OFFSET 0
-#define DxF0x04_IoAccessEn_WIDTH 1
-#define DxF0x04_IoAccessEn_MASK 0x1
-#define DxF0x04_MemAccessEn_OFFSET 1
-#define DxF0x04_MemAccessEn_WIDTH 1
-#define DxF0x04_MemAccessEn_MASK 0x2
-#define DxF0x04_BusMasterEn_OFFSET 2
-#define DxF0x04_BusMasterEn_WIDTH 1
-#define DxF0x04_BusMasterEn_MASK 0x4
-#define DxF0x04_SpecialCycleEn_OFFSET 3
-#define DxF0x04_SpecialCycleEn_WIDTH 1
-#define DxF0x04_SpecialCycleEn_MASK 0x8
-#define DxF0x04_MemWriteInvalidateEn_OFFSET 4
-#define DxF0x04_MemWriteInvalidateEn_WIDTH 1
-#define DxF0x04_MemWriteInvalidateEn_MASK 0x10
-#define DxF0x04_PalSnoopEn_OFFSET 5
-#define DxF0x04_PalSnoopEn_WIDTH 1
-#define DxF0x04_PalSnoopEn_MASK 0x20
-#define DxF0x04_ParityErrorEn_OFFSET 6
-#define DxF0x04_ParityErrorEn_WIDTH 1
-#define DxF0x04_ParityErrorEn_MASK 0x40
-#define DxF0x04_IdselStepping_OFFSET 7
-#define DxF0x04_IdselStepping_WIDTH 1
-#define DxF0x04_IdselStepping_MASK 0x80
-#define DxF0x04_SerrEn_OFFSET 8
-#define DxF0x04_SerrEn_WIDTH 1
-#define DxF0x04_SerrEn_MASK 0x100
-#define DxF0x04_FastB2BEn_OFFSET 9
-#define DxF0x04_FastB2BEn_WIDTH 1
-#define DxF0x04_FastB2BEn_MASK 0x200
-#define DxF0x04_IntDis_OFFSET 10
-#define DxF0x04_IntDis_WIDTH 1
-#define DxF0x04_IntDis_MASK 0x400
-#define DxF0x04_Reserved_18_11_OFFSET 11
-#define DxF0x04_Reserved_18_11_WIDTH 8
-#define DxF0x04_Reserved_18_11_MASK 0x7f800
-#define DxF0x04_IntStatus_OFFSET 19
-#define DxF0x04_IntStatus_WIDTH 1
-#define DxF0x04_IntStatus_MASK 0x80000
-#define DxF0x04_CapList_OFFSET 20
-#define DxF0x04_CapList_WIDTH 1
-#define DxF0x04_CapList_MASK 0x100000
-#define DxF0x04_PCI66En_OFFSET 21
-#define DxF0x04_PCI66En_WIDTH 1
-#define DxF0x04_PCI66En_MASK 0x200000
-#define DxF0x04_UDFEn_OFFSET 22
-#define DxF0x04_UDFEn_WIDTH 1
-#define DxF0x04_UDFEn_MASK 0x400000
-#define DxF0x04_FastBackCapable_OFFSET 23
-#define DxF0x04_FastBackCapable_WIDTH 1
-#define DxF0x04_FastBackCapable_MASK 0x800000
-#define DxF0x04_MasterDataPerr_OFFSET 24
-#define DxF0x04_MasterDataPerr_WIDTH 1
-#define DxF0x04_MasterDataPerr_MASK 0x1000000
-#define DxF0x04_DevselTiming_OFFSET 25
-#define DxF0x04_DevselTiming_WIDTH 2
-#define DxF0x04_DevselTiming_MASK 0x6000000
-#define DxF0x04_SignaledTargetAbort_OFFSET 27
-#define DxF0x04_SignaledTargetAbort_WIDTH 1
-#define DxF0x04_SignaledTargetAbort_MASK 0x8000000
-#define DxF0x04_ReceivedTargetAbort_OFFSET 28
-#define DxF0x04_ReceivedTargetAbort_WIDTH 1
-#define DxF0x04_ReceivedTargetAbort_MASK 0x10000000
-#define DxF0x04_ReceivedMasterAbort_OFFSET 29
-#define DxF0x04_ReceivedMasterAbort_WIDTH 1
-#define DxF0x04_ReceivedMasterAbort_MASK 0x20000000
-#define DxF0x04_SignaledSystemError_OFFSET 30
-#define DxF0x04_SignaledSystemError_WIDTH 1
-#define DxF0x04_SignaledSystemError_MASK 0x40000000
-#define DxF0x04_ParityErrorDetected_OFFSET 31
-#define DxF0x04_ParityErrorDetected_WIDTH 1
-#define DxF0x04_ParityErrorDetected_MASK 0x80000000
-
-/// DxF0x04
-typedef union {
- struct { ///<
- UINT32 IoAccessEn:1 ; ///<
- UINT32 MemAccessEn:1 ; ///<
- UINT32 BusMasterEn:1 ; ///<
- UINT32 SpecialCycleEn:1 ; ///<
- UINT32 MemWriteInvalidateEn:1 ; ///<
- UINT32 PalSnoopEn:1 ; ///<
- UINT32 ParityErrorEn:1 ; ///<
- UINT32 IdselStepping:1 ; ///<
- UINT32 SerrEn:1 ; ///<
- UINT32 FastB2BEn:1 ; ///<
- UINT32 IntDis:1 ; ///<
- UINT32 Reserved_18_11:8 ; ///<
- UINT32 IntStatus:1 ; ///<
- UINT32 CapList:1 ; ///<
- UINT32 PCI66En:1 ; ///<
- UINT32 UDFEn:1 ; ///<
- UINT32 FastBackCapable:1 ; ///<
- UINT32 MasterDataPerr:1 ; ///<
- UINT32 DevselTiming:2 ; ///<
- UINT32 SignaledTargetAbort:1 ; ///<
- UINT32 ReceivedTargetAbort:1 ; ///<
- UINT32 ReceivedMasterAbort:1 ; ///<
- UINT32 SignaledSystemError:1 ; ///<
- UINT32 ParityErrorDetected:1 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0x04_STRUCT;
-
-// **** DxF0x08 Register Definition ****
-// Address
-#define DxF0x08_ADDRESS 0x8
-
-// Type
-#define DxF0x08_TYPE TYPE_D4F0
-// Field Data
-#define DxF0x08_RevID_OFFSET 0
-#define DxF0x08_RevID_WIDTH 8
-#define DxF0x08_RevID_MASK 0xff
-#define DxF0x08_ClassCode_OFFSET 8
-#define DxF0x08_ClassCode_WIDTH 24
-#define DxF0x08_ClassCode_MASK 0xffffff00
-
-/// DxF0x08
-typedef union {
- struct { ///<
- UINT32 RevID:8 ; ///<
- UINT32 ClassCode:24; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0x08_STRUCT;
-
-// **** DxF0x0C Register Definition ****
-// Address
-#define DxF0x0C_ADDRESS 0xc
-
-// Type
-#define DxF0x0C_TYPE TYPE_D4F0
-// Field Data
-#define DxF0x0C_CacheLineSize_OFFSET 0
-#define DxF0x0C_CacheLineSize_WIDTH 8
-#define DxF0x0C_CacheLineSize_MASK 0xff
-#define DxF0x0C_LatencyTimer_OFFSET 8
-#define DxF0x0C_LatencyTimer_WIDTH 8
-#define DxF0x0C_LatencyTimer_MASK 0xff00
-#define DxF0x0C_HeaderTypeReg_OFFSET 16
-#define DxF0x0C_HeaderTypeReg_WIDTH 8
-#define DxF0x0C_HeaderTypeReg_MASK 0xff0000
-#define DxF0x0C_BIST_OFFSET 24
-#define DxF0x0C_BIST_WIDTH 8
-#define DxF0x0C_BIST_MASK 0xff000000
-
-/// DxF0x0C
-typedef union {
- struct { ///<
- UINT32 CacheLineSize:8 ; ///<
- UINT32 LatencyTimer:8 ; ///<
- UINT32 HeaderTypeReg:8 ; ///<
- UINT32 BIST:8 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0x0C_STRUCT;
-
-// **** DxF0x18 Register Definition ****
-// Address
-#define DxF0x18_ADDRESS 0x18
-
-// Type
-#define DxF0x18_TYPE TYPE_D4F0
-// Field Data
-#define DxF0x18_PrimaryBus_OFFSET 0
-#define DxF0x18_PrimaryBus_WIDTH 8
-#define DxF0x18_PrimaryBus_MASK 0xff
-#define DxF0x18_SecondaryBus_OFFSET 8
-#define DxF0x18_SecondaryBus_WIDTH 8
-#define DxF0x18_SecondaryBus_MASK 0xff00
-#define DxF0x18_SubBusNumber_OFFSET 16
-#define DxF0x18_SubBusNumber_WIDTH 8
-#define DxF0x18_SubBusNumber_MASK 0xff0000
-#define DxF0x18_SecondaryLatencyTimer_OFFSET 24
-#define DxF0x18_SecondaryLatencyTimer_WIDTH 8
-#define DxF0x18_SecondaryLatencyTimer_MASK 0xff000000
-
-/// DxF0x18
-typedef union {
- struct { ///<
- UINT32 PrimaryBus:8 ; ///<
- UINT32 SecondaryBus:8 ; ///<
- UINT32 SubBusNumber:8 ; ///<
- UINT32 SecondaryLatencyTimer:8 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0x18_STRUCT;
-
-// **** DxF0x1C Register Definition ****
-// Address
-#define DxF0x1C_ADDRESS 0x1c
-
-// Type
-#define DxF0x1C_TYPE TYPE_D4F0
-// Field Data
-#define DxF0x1C_Reserved_3_0_OFFSET 0
-#define DxF0x1C_Reserved_3_0_WIDTH 4
-#define DxF0x1C_Reserved_3_0_MASK 0xf
-#define DxF0x1C_IOBase_15_12__OFFSET 4
-#define DxF0x1C_IOBase_15_12__WIDTH 4
-#define DxF0x1C_IOBase_15_12__MASK 0xf0
-#define DxF0x1C_Reserved_11_8_OFFSET 8
-#define DxF0x1C_Reserved_11_8_WIDTH 4
-#define DxF0x1C_Reserved_11_8_MASK 0xf00
-#define DxF0x1C_IOLimit_15_12__OFFSET 12
-#define DxF0x1C_IOLimit_15_12__WIDTH 4
-#define DxF0x1C_IOLimit_15_12__MASK 0xf000
-#define DxF0x1C_Reserved_19_16_OFFSET 16
-#define DxF0x1C_Reserved_19_16_WIDTH 4
-#define DxF0x1C_Reserved_19_16_MASK 0xf0000
-#define DxF0x1C_CapList_OFFSET 20
-#define DxF0x1C_CapList_WIDTH 1
-#define DxF0x1C_CapList_MASK 0x100000
-#define DxF0x1C_PCI66En_OFFSET 21
-#define DxF0x1C_PCI66En_WIDTH 1
-#define DxF0x1C_PCI66En_MASK 0x200000
-#define DxF0x1C_UDFEn_OFFSET 22
-#define DxF0x1C_UDFEn_WIDTH 1
-#define DxF0x1C_UDFEn_MASK 0x400000
-#define DxF0x1C_FastBackCapable_OFFSET 23
-#define DxF0x1C_FastBackCapable_WIDTH 1
-#define DxF0x1C_FastBackCapable_MASK 0x800000
-#define DxF0x1C_MasterDataPerr_OFFSET 24
-#define DxF0x1C_MasterDataPerr_WIDTH 1
-#define DxF0x1C_MasterDataPerr_MASK 0x1000000
-#define DxF0x1C_DevselTiming_OFFSET 25
-#define DxF0x1C_DevselTiming_WIDTH 2
-#define DxF0x1C_DevselTiming_MASK 0x6000000
-#define DxF0x1C_SignalTargetAbort_OFFSET 27
-#define DxF0x1C_SignalTargetAbort_WIDTH 1
-#define DxF0x1C_SignalTargetAbort_MASK 0x8000000
-#define DxF0x1C_ReceivedTargetAbort_OFFSET 28
-#define DxF0x1C_ReceivedTargetAbort_WIDTH 1
-#define DxF0x1C_ReceivedTargetAbort_MASK 0x10000000
-#define DxF0x1C_ReceivedMasterAbort_OFFSET 29
-#define DxF0x1C_ReceivedMasterAbort_WIDTH 1
-#define DxF0x1C_ReceivedMasterAbort_MASK 0x20000000
-#define DxF0x1C_ReceivedSystemError_OFFSET 30
-#define DxF0x1C_ReceivedSystemError_WIDTH 1
-#define DxF0x1C_ReceivedSystemError_MASK 0x40000000
-#define DxF0x1C_ParityErrorDetected_OFFSET 31
-#define DxF0x1C_ParityErrorDetected_WIDTH 1
-#define DxF0x1C_ParityErrorDetected_MASK 0x80000000
-
-/// DxF0x1C
-typedef union {
- struct { ///<
- UINT32 Reserved_3_0:4 ; ///<
- UINT32 IOBase_15_12_:4 ; ///<
- UINT32 Reserved_11_8:4 ; ///<
- UINT32 IOLimit_15_12_:4 ; ///<
- UINT32 Reserved_19_16:4 ; ///<
- UINT32 CapList:1 ; ///<
- UINT32 PCI66En:1 ; ///<
- UINT32 UDFEn:1 ; ///<
- UINT32 FastBackCapable:1 ; ///<
- UINT32 MasterDataPerr:1 ; ///<
- UINT32 DevselTiming:2 ; ///<
- UINT32 SignalTargetAbort:1 ; ///<
- UINT32 ReceivedTargetAbort:1 ; ///<
- UINT32 ReceivedMasterAbort:1 ; ///<
- UINT32 ReceivedSystemError:1 ; ///<
- UINT32 ParityErrorDetected:1 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0x1C_STRUCT;
-
-// **** DxF0x20 Register Definition ****
-// Address
-#define DxF0x20_ADDRESS 0x20
-
-// Type
-#define DxF0x20_TYPE TYPE_D4F0
-// Field Data
-#define DxF0x20_Reserved_3_0_OFFSET 0
-#define DxF0x20_Reserved_3_0_WIDTH 4
-#define DxF0x20_Reserved_3_0_MASK 0xf
-#define DxF0x20_MemBase_OFFSET 4
-#define DxF0x20_MemBase_WIDTH 12
-#define DxF0x20_MemBase_MASK 0xfff0
-#define DxF0x20_Reserved_19_16_OFFSET 16
-#define DxF0x20_Reserved_19_16_WIDTH 4
-#define DxF0x20_Reserved_19_16_MASK 0xf0000
-#define DxF0x20_MemLimit_OFFSET 20
-#define DxF0x20_MemLimit_WIDTH 12
-#define DxF0x20_MemLimit_MASK 0xfff00000
-
-/// DxF0x20
-typedef union {
- struct { ///<
- UINT32 Reserved_3_0:4 ; ///<
- UINT32 MemBase:12; ///<
- UINT32 Reserved_19_16:4 ; ///<
- UINT32 MemLimit:12; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0x20_STRUCT;
-
-// **** DxF0x24 Register Definition ****
-// Address
-#define DxF0x24_ADDRESS 0x24
-
-// Type
-#define DxF0x24_TYPE TYPE_D4F0
-// Field Data
-#define DxF0x24_PrefMemBaseR_OFFSET 0
-#define DxF0x24_PrefMemBaseR_WIDTH 4
-#define DxF0x24_PrefMemBaseR_MASK 0xf
-#define DxF0x24_PrefMemBase_31_20__OFFSET 4
-#define DxF0x24_PrefMemBase_31_20__WIDTH 12
-#define DxF0x24_PrefMemBase_31_20__MASK 0xfff0
-#define DxF0x24_PrefMemLimitR_OFFSET 16
-#define DxF0x24_PrefMemLimitR_WIDTH 4
-#define DxF0x24_PrefMemLimitR_MASK 0xf0000
-#define DxF0x24_PrefMemLimit_OFFSET 20
-#define DxF0x24_PrefMemLimit_WIDTH 12
-#define DxF0x24_PrefMemLimit_MASK 0xfff00000
-
-/// DxF0x24
-typedef union {
- struct { ///<
- UINT32 PrefMemBaseR:4 ; ///<
- UINT32 PrefMemBase_31_20_:12; ///<
- UINT32 PrefMemLimitR:4 ; ///<
- UINT32 PrefMemLimit:12; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0x24_STRUCT;
-
-// **** DxF0x28 Register Definition ****
-// Address
-#define DxF0x28_ADDRESS 0x28
-
-// Type
-#define DxF0x28_TYPE TYPE_D4F0
-// Field Data
-#define DxF0x28_PrefMemBase_63_32__OFFSET 0
-#define DxF0x28_PrefMemBase_63_32__WIDTH 32
-#define DxF0x28_PrefMemBase_63_32__MASK 0xffffffff
-
-/// DxF0x28
-typedef union {
- struct { ///<
- UINT32 PrefMemBase_63_32_:32; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0x28_STRUCT;
-
-// **** DxF0x2C Register Definition ****
-// Address
-#define DxF0x2C_ADDRESS 0x2c
-
-// Type
-#define DxF0x2C_TYPE TYPE_D4F0
-// Field Data
-#define DxF0x2C_PrefMemLimit_63_32__OFFSET 0
-#define DxF0x2C_PrefMemLimit_63_32__WIDTH 32
-#define DxF0x2C_PrefMemLimit_63_32__MASK 0xffffffff
-
-/// DxF0x2C
-typedef union {
- struct { ///<
- UINT32 PrefMemLimit_63_32_:32; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0x2C_STRUCT;
-
-// **** DxF0x30 Register Definition ****
-// Address
-#define DxF0x30_ADDRESS 0x30
-
-// Type
-#define DxF0x30_TYPE TYPE_D4F0
-// Field Data
-#define DxF0x30_IOBase_31_16__OFFSET 0
-#define DxF0x30_IOBase_31_16__WIDTH 16
-#define DxF0x30_IOBase_31_16__MASK 0xffff
-#define DxF0x30_IOLimit_31_16__OFFSET 16
-#define DxF0x30_IOLimit_31_16__WIDTH 16
-#define DxF0x30_IOLimit_31_16__MASK 0xffff0000
-
-/// DxF0x30
-typedef union {
- struct { ///<
- UINT32 IOBase_31_16_:16; ///<
- UINT32 IOLimit_31_16_:16; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0x30_STRUCT;
-
-// **** DxF0x34 Register Definition ****
-// Address
-#define DxF0x34_ADDRESS 0x34
-
-// Type
-#define DxF0x34_TYPE TYPE_D4F0
-// Field Data
-#define DxF0x34_CapPtr_OFFSET 0
-#define DxF0x34_CapPtr_WIDTH 8
-#define DxF0x34_CapPtr_MASK 0xff
-#define DxF0x34_Reserved_31_8_OFFSET 8
-#define DxF0x34_Reserved_31_8_WIDTH 24
-#define DxF0x34_Reserved_31_8_MASK 0xffffff00
-
-/// DxF0x34
-typedef union {
- struct { ///<
- UINT32 CapPtr:8 ; ///<
- UINT32 Reserved_31_8:24; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0x34_STRUCT;
-
-// **** DxF0x3C Register Definition ****
-// Address
-#define DxF0x3C_ADDRESS 0x3c
-
-// Type
-#define DxF0x3C_TYPE TYPE_D4F0
-// Field Data
-#define DxF0x3C_IntLine_OFFSET 0
-#define DxF0x3C_IntLine_WIDTH 8
-#define DxF0x3C_IntLine_MASK 0xff
-#define DxF0x3C_IntPin_OFFSET 8
-#define DxF0x3C_IntPin_WIDTH 3
-#define DxF0x3C_IntPin_MASK 0x700
-#define DxF0x3C_Reserved_15_11_OFFSET 11
-#define DxF0x3C_Reserved_15_11_WIDTH 5
-#define DxF0x3C_Reserved_15_11_MASK 0xf800
-#define DxF0x3C_ParityResponseEn_OFFSET 16
-#define DxF0x3C_ParityResponseEn_WIDTH 1
-#define DxF0x3C_ParityResponseEn_MASK 0x10000
-#define DxF0x3C_SerrEn_OFFSET 17
-#define DxF0x3C_SerrEn_WIDTH 1
-#define DxF0x3C_SerrEn_MASK 0x20000
-#define DxF0x3C_IsaEn_OFFSET 18
-#define DxF0x3C_IsaEn_WIDTH 1
-#define DxF0x3C_IsaEn_MASK 0x40000
-#define DxF0x3C_VgaEn_OFFSET 19
-#define DxF0x3C_VgaEn_WIDTH 1
-#define DxF0x3C_VgaEn_MASK 0x80000
-#define DxF0x3C_Vga16En_OFFSET 20
-#define DxF0x3C_Vga16En_WIDTH 1
-#define DxF0x3C_Vga16En_MASK 0x100000
-#define DxF0x3C_MasterAbortMode_OFFSET 21
-#define DxF0x3C_MasterAbortMode_WIDTH 1
-#define DxF0x3C_MasterAbortMode_MASK 0x200000
-#define DxF0x3C_SecondaryBusReset_OFFSET 22
-#define DxF0x3C_SecondaryBusReset_WIDTH 1
-#define DxF0x3C_SecondaryBusReset_MASK 0x400000
-#define DxF0x3C_FastB2BCap_OFFSET 23
-#define DxF0x3C_FastB2BCap_WIDTH 1
-#define DxF0x3C_FastB2BCap_MASK 0x800000
-#define DxF0x3C_Reserved_31_24_OFFSET 24
-#define DxF0x3C_Reserved_31_24_WIDTH 8
-#define DxF0x3C_Reserved_31_24_MASK 0xff000000
-
-/// DxF0x3C
-typedef union {
- struct { ///<
- UINT32 IntLine:8 ; ///<
- UINT32 IntPin:3 ; ///<
- UINT32 Reserved_15_11:5 ; ///<
- UINT32 ParityResponseEn:1 ; ///<
- UINT32 SerrEn:1 ; ///<
- UINT32 IsaEn:1 ; ///<
- UINT32 VgaEn:1 ; ///<
- UINT32 Vga16En:1 ; ///<
- UINT32 MasterAbortMode:1 ; ///<
- UINT32 SecondaryBusReset:1 ; ///<
- UINT32 FastB2BCap:1 ; ///<
- UINT32 Reserved_31_24:8 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0x3C_STRUCT;
-
-// **** DxF0x50 Register Definition ****
-// Address
-#define DxF0x50_ADDRESS 0x50
-
-// Type
-#define DxF0x50_TYPE TYPE_D4F0
-// Field Data
-#define DxF0x50_CapID_OFFSET 0
-#define DxF0x50_CapID_WIDTH 8
-#define DxF0x50_CapID_MASK 0xff
-#define DxF0x50_NextPtr_OFFSET 8
-#define DxF0x50_NextPtr_WIDTH 8
-#define DxF0x50_NextPtr_MASK 0xff00
-#define DxF0x50_Version_OFFSET 16
-#define DxF0x50_Version_WIDTH 3
-#define DxF0x50_Version_MASK 0x70000
-#define DxF0x50_PmeClock_OFFSET 19
-#define DxF0x50_PmeClock_WIDTH 1
-#define DxF0x50_PmeClock_MASK 0x80000
-#define DxF0x50_Reserved_20_20_OFFSET 20
-#define DxF0x50_Reserved_20_20_WIDTH 1
-#define DxF0x50_Reserved_20_20_MASK 0x100000
-#define DxF0x50_DevSpecificInit_OFFSET 21
-#define DxF0x50_DevSpecificInit_WIDTH 1
-#define DxF0x50_DevSpecificInit_MASK 0x200000
-#define DxF0x50_AuxCurrent_OFFSET 22
-#define DxF0x50_AuxCurrent_WIDTH 3
-#define DxF0x50_AuxCurrent_MASK 0x1c00000
-#define DxF0x50_D1Support_OFFSET 25
-#define DxF0x50_D1Support_WIDTH 1
-#define DxF0x50_D1Support_MASK 0x2000000
-#define DxF0x50_D2Support_OFFSET 26
-#define DxF0x50_D2Support_WIDTH 1
-#define DxF0x50_D2Support_MASK 0x4000000
-#define DxF0x50_PmeSupport_OFFSET 27
-#define DxF0x50_PmeSupport_WIDTH 5
-#define DxF0x50_PmeSupport_MASK 0xf8000000
-
-/// DxF0x50
-typedef union {
- struct { ///<
- UINT32 CapID:8 ; ///<
- UINT32 NextPtr:8 ; ///<
- UINT32 Version:3 ; ///<
- UINT32 PmeClock:1 ; ///<
- UINT32 Reserved_20_20:1 ; ///<
- UINT32 DevSpecificInit:1 ; ///<
- UINT32 AuxCurrent:3 ; ///<
- UINT32 D1Support:1 ; ///<
- UINT32 D2Support:1 ; ///<
- UINT32 PmeSupport:5 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0x50_STRUCT;
-
-// **** DxF0x54 Register Definition ****
-// Address
-#define DxF0x54_ADDRESS 0x54
-
-// Type
-#define DxF0x54_TYPE TYPE_D4F0
-// Field Data
-#define DxF0x54_PowerState_OFFSET 0
-#define DxF0x54_PowerState_WIDTH 2
-#define DxF0x54_PowerState_MASK 0x3
-#define DxF0x54_Reserved_2_2_OFFSET 2
-#define DxF0x54_Reserved_2_2_WIDTH 1
-#define DxF0x54_Reserved_2_2_MASK 0x4
-#define DxF0x54_NoSoftReset_OFFSET 3
-#define DxF0x54_NoSoftReset_WIDTH 1
-#define DxF0x54_NoSoftReset_MASK 0x8
-#define DxF0x54_Reserved_7_4_OFFSET 4
-#define DxF0x54_Reserved_7_4_WIDTH 4
-#define DxF0x54_Reserved_7_4_MASK 0xf0
-#define DxF0x54_PmeEn_OFFSET 8
-#define DxF0x54_PmeEn_WIDTH 1
-#define DxF0x54_PmeEn_MASK 0x100
-#define DxF0x54_DataSelect_OFFSET 9
-#define DxF0x54_DataSelect_WIDTH 4
-#define DxF0x54_DataSelect_MASK 0x1e00
-#define DxF0x54_DataScale_OFFSET 13
-#define DxF0x54_DataScale_WIDTH 2
-#define DxF0x54_DataScale_MASK 0x6000
-#define DxF0x54_PmeStatus_OFFSET 15
-#define DxF0x54_PmeStatus_WIDTH 1
-#define DxF0x54_PmeStatus_MASK 0x8000
-#define DxF0x54_Reserved_21_16_OFFSET 16
-#define DxF0x54_Reserved_21_16_WIDTH 6
-#define DxF0x54_Reserved_21_16_MASK 0x3f0000
-#define DxF0x54_B2B3Support_OFFSET 22
-#define DxF0x54_B2B3Support_WIDTH 1
-#define DxF0x54_B2B3Support_MASK 0x400000
-#define DxF0x54_BusPwrEn_OFFSET 23
-#define DxF0x54_BusPwrEn_WIDTH 1
-#define DxF0x54_BusPwrEn_MASK 0x800000
-#define DxF0x54_PmeData_OFFSET 24
-#define DxF0x54_PmeData_WIDTH 8
-#define DxF0x54_PmeData_MASK 0xff000000
-
-/// DxF0x54
-typedef union {
- struct { ///<
- UINT32 PowerState:2 ; ///<
- UINT32 Reserved_2_2:1 ; ///<
- UINT32 NoSoftReset:1 ; ///<
- UINT32 Reserved_7_4:4 ; ///<
- UINT32 PmeEn:1 ; ///<
- UINT32 DataSelect:4 ; ///<
- UINT32 DataScale:2 ; ///<
- UINT32 PmeStatus:1 ; ///<
- UINT32 Reserved_21_16:6 ; ///<
- UINT32 B2B3Support:1 ; ///<
- UINT32 BusPwrEn:1 ; ///<
- UINT32 PmeData:8 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0x54_STRUCT;
-
-// **** DxF0x58 Register Definition ****
-// Address
-#define DxF0x58_ADDRESS 0x58
-
-// Type
-#define DxF0x58_TYPE TYPE_D4F0
-// Field Data
-#define DxF0x58_CapID_OFFSET 0
-#define DxF0x58_CapID_WIDTH 8
-#define DxF0x58_CapID_MASK 0xff
-#define DxF0x58_NextPtr_OFFSET 8
-#define DxF0x58_NextPtr_WIDTH 8
-#define DxF0x58_NextPtr_MASK 0xff00
-#define DxF0x58_Version_OFFSET 16
-#define DxF0x58_Version_WIDTH 4
-#define DxF0x58_Version_MASK 0xf0000
-#define DxF0x58_DeviceType_OFFSET 20
-#define DxF0x58_DeviceType_WIDTH 4
-#define DxF0x58_DeviceType_MASK 0xf00000
-#define DxF0x58_SlotImplemented_OFFSET 24
-#define DxF0x58_SlotImplemented_WIDTH 1
-#define DxF0x58_SlotImplemented_MASK 0x1000000
-#define DxF0x58_IntMessageNum_OFFSET 25
-#define DxF0x58_IntMessageNum_WIDTH 5
-#define DxF0x58_IntMessageNum_MASK 0x3e000000
-#define DxF0x58_Reserved_31_30_OFFSET 30
-#define DxF0x58_Reserved_31_30_WIDTH 2
-#define DxF0x58_Reserved_31_30_MASK 0xc0000000
-
-/// DxF0x58
-typedef union {
- struct { ///<
- UINT32 CapID:8 ; ///<
- UINT32 NextPtr:8 ; ///<
- UINT32 Version:4 ; ///<
- UINT32 DeviceType:4 ; ///<
- UINT32 SlotImplemented:1 ; ///<
- UINT32 IntMessageNum:5 ; ///<
- UINT32 Reserved_31_30:2 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0x58_STRUCT;
-
-// **** DxF0x5C Register Definition ****
-// Address
-#define DxF0x5C_ADDRESS 0x5c
-
-// Type
-#define DxF0x5C_TYPE TYPE_D4F0
-// Field Data
-#define DxF0x5C_MaxPayloadSupport_OFFSET 0
-#define DxF0x5C_MaxPayloadSupport_WIDTH 3
-#define DxF0x5C_MaxPayloadSupport_MASK 0x7
-#define DxF0x5C_PhantomFunc_OFFSET 3
-#define DxF0x5C_PhantomFunc_WIDTH 2
-#define DxF0x5C_PhantomFunc_MASK 0x18
-#define DxF0x5C_ExtendedTag_OFFSET 5
-#define DxF0x5C_ExtendedTag_WIDTH 1
-#define DxF0x5C_ExtendedTag_MASK 0x20
-#define DxF0x5C_L0SAcceptableLatency_OFFSET 6
-#define DxF0x5C_L0SAcceptableLatency_WIDTH 3
-#define DxF0x5C_L0SAcceptableLatency_MASK 0x1c0
-#define DxF0x5C_L1AcceptableLatency_OFFSET 9
-#define DxF0x5C_L1AcceptableLatency_WIDTH 3
-#define DxF0x5C_L1AcceptableLatency_MASK 0xe00
-#define DxF0x5C_Reserved_14_12_OFFSET 12
-#define DxF0x5C_Reserved_14_12_WIDTH 3
-#define DxF0x5C_Reserved_14_12_MASK 0x7000
-#define DxF0x5C_RoleBasedErrReporting_OFFSET 15
-#define DxF0x5C_RoleBasedErrReporting_WIDTH 1
-#define DxF0x5C_RoleBasedErrReporting_MASK 0x8000
-#define DxF0x5C_Reserved_17_16_OFFSET 16
-#define DxF0x5C_Reserved_17_16_WIDTH 2
-#define DxF0x5C_Reserved_17_16_MASK 0x30000
-#define DxF0x5C_CapturedSlotPowerLimit_OFFSET 18
-#define DxF0x5C_CapturedSlotPowerLimit_WIDTH 8
-#define DxF0x5C_CapturedSlotPowerLimit_MASK 0x3fc0000
-#define DxF0x5C_CapturedSlotPowerScale_OFFSET 26
-#define DxF0x5C_CapturedSlotPowerScale_WIDTH 2
-#define DxF0x5C_CapturedSlotPowerScale_MASK 0xc000000
-#define DxF0x5C_FlrCapable_OFFSET 28
-#define DxF0x5C_FlrCapable_WIDTH 1
-#define DxF0x5C_FlrCapable_MASK 0x10000000
-#define DxF0x5C_Reserved_31_29_OFFSET 29
-#define DxF0x5C_Reserved_31_29_WIDTH 3
-#define DxF0x5C_Reserved_31_29_MASK 0xe0000000
-
-/// DxF0x5C
-typedef union {
- struct { ///<
- UINT32 MaxPayloadSupport:3 ; ///<
- UINT32 PhantomFunc:2 ; ///<
- UINT32 ExtendedTag:1 ; ///<
- UINT32 L0SAcceptableLatency:3 ; ///<
- UINT32 L1AcceptableLatency:3 ; ///<
- UINT32 Reserved_14_12:3 ; ///<
- UINT32 RoleBasedErrReporting:1 ; ///<
- UINT32 Reserved_17_16:2 ; ///<
- UINT32 CapturedSlotPowerLimit:8 ; ///<
- UINT32 CapturedSlotPowerScale:2 ; ///<
- UINT32 FlrCapable:1 ; ///<
- UINT32 Reserved_31_29:3 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0x5C_STRUCT;
-
-// **** DxF0x60 Register Definition ****
-// Address
-#define DxF0x60_ADDRESS 0x60
-
-// Type
-#define DxF0x60_TYPE TYPE_D4F0
-// Field Data
-#define DxF0x60_CorrErrEn_OFFSET 0
-#define DxF0x60_CorrErrEn_WIDTH 1
-#define DxF0x60_CorrErrEn_MASK 0x1
-#define DxF0x60_NonFatalErrEn_OFFSET 1
-#define DxF0x60_NonFatalErrEn_WIDTH 1
-#define DxF0x60_NonFatalErrEn_MASK 0x2
-#define DxF0x60_FatalErrEn_OFFSET 2
-#define DxF0x60_FatalErrEn_WIDTH 1
-#define DxF0x60_FatalErrEn_MASK 0x4
-#define DxF0x60_UsrReportEn_OFFSET 3
-#define DxF0x60_UsrReportEn_WIDTH 1
-#define DxF0x60_UsrReportEn_MASK 0x8
-#define DxF0x60_RelaxedOrdEn_OFFSET 4
-#define DxF0x60_RelaxedOrdEn_WIDTH 1
-#define DxF0x60_RelaxedOrdEn_MASK 0x10
-#define DxF0x60_MaxPayloadSize_OFFSET 5
-#define DxF0x60_MaxPayloadSize_WIDTH 3
-#define DxF0x60_MaxPayloadSize_MASK 0xe0
-#define DxF0x60_ExtendedTagEn_OFFSET 8
-#define DxF0x60_ExtendedTagEn_WIDTH 1
-#define DxF0x60_ExtendedTagEn_MASK 0x100
-#define DxF0x60_PhantomFuncEn_OFFSET 9
-#define DxF0x60_PhantomFuncEn_WIDTH 1
-#define DxF0x60_PhantomFuncEn_MASK 0x200
-#define DxF0x60_AuxPowerPmEn_OFFSET 10
-#define DxF0x60_AuxPowerPmEn_WIDTH 1
-#define DxF0x60_AuxPowerPmEn_MASK 0x400
-#define DxF0x60_NoSnoopEnable_OFFSET 11
-#define DxF0x60_NoSnoopEnable_WIDTH 1
-#define DxF0x60_NoSnoopEnable_MASK 0x800
-#define DxF0x60_MaxRequestSize_OFFSET 12
-#define DxF0x60_MaxRequestSize_WIDTH 3
-#define DxF0x60_MaxRequestSize_MASK 0x7000
-#define DxF0x60_BridgeCfgRetryEn_OFFSET 15
-#define DxF0x60_BridgeCfgRetryEn_WIDTH 1
-#define DxF0x60_BridgeCfgRetryEn_MASK 0x8000
-#define DxF0x60_CorrErr_OFFSET 16
-#define DxF0x60_CorrErr_WIDTH 1
-#define DxF0x60_CorrErr_MASK 0x10000
-#define DxF0x60_NonFatalErr_OFFSET 17
-#define DxF0x60_NonFatalErr_WIDTH 1
-#define DxF0x60_NonFatalErr_MASK 0x20000
-#define DxF0x60_FatalErr_OFFSET 18
-#define DxF0x60_FatalErr_WIDTH 1
-#define DxF0x60_FatalErr_MASK 0x40000
-#define DxF0x60_UsrDetected_OFFSET 19
-#define DxF0x60_UsrDetected_WIDTH 1
-#define DxF0x60_UsrDetected_MASK 0x80000
-#define DxF0x60_AuxPwr_OFFSET 20
-#define DxF0x60_AuxPwr_WIDTH 1
-#define DxF0x60_AuxPwr_MASK 0x100000
-#define DxF0x60_TransactionsPending_OFFSET 21
-#define DxF0x60_TransactionsPending_WIDTH 1
-#define DxF0x60_TransactionsPending_MASK 0x200000
-#define DxF0x60_Reserved_31_22_OFFSET 22
-#define DxF0x60_Reserved_31_22_WIDTH 10
-#define DxF0x60_Reserved_31_22_MASK 0xffc00000
-
-/// DxF0x60
-typedef union {
- struct { ///<
- UINT32 CorrErrEn:1 ; ///<
- UINT32 NonFatalErrEn:1 ; ///<
- UINT32 FatalErrEn:1 ; ///<
- UINT32 UsrReportEn:1 ; ///<
- UINT32 RelaxedOrdEn:1 ; ///<
- UINT32 MaxPayloadSize:3 ; ///<
- UINT32 ExtendedTagEn:1 ; ///<
- UINT32 PhantomFuncEn:1 ; ///<
- UINT32 AuxPowerPmEn:1 ; ///<
- UINT32 NoSnoopEnable:1 ; ///<
- UINT32 MaxRequestSize:3 ; ///<
- UINT32 BridgeCfgRetryEn:1 ; ///<
- UINT32 CorrErr:1 ; ///<
- UINT32 NonFatalErr:1 ; ///<
- UINT32 FatalErr:1 ; ///<
- UINT32 UsrDetected:1 ; ///<
- UINT32 AuxPwr:1 ; ///<
- UINT32 TransactionsPending:1 ; ///<
- UINT32 Reserved_31_22:10; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0x60_STRUCT;
-
-// **** DxF0x64 Register Definition ****
-// Address
-#define DxF0x64_ADDRESS 0x64
-
-// Type
-#define DxF0x64_TYPE TYPE_D4F0
-// Field Data
-#define DxF0x64_LinkSpeed_OFFSET 0
-#define DxF0x64_LinkSpeed_WIDTH 4
-#define DxF0x64_LinkSpeed_MASK 0xf
-#define DxF0x64_LinkWidth_OFFSET 4
-#define DxF0x64_LinkWidth_WIDTH 6
-#define DxF0x64_LinkWidth_MASK 0x3f0
-#define DxF0x64_PMSupport_OFFSET 10
-#define DxF0x64_PMSupport_WIDTH 2
-#define DxF0x64_PMSupport_MASK 0xc00
-#define DxF0x64_L0sExitLatency_OFFSET 12
-#define DxF0x64_L0sExitLatency_WIDTH 3
-#define DxF0x64_L0sExitLatency_MASK 0x7000
-#define DxF0x64_L1ExitLatency_OFFSET 15
-#define DxF0x64_L1ExitLatency_WIDTH 3
-#define DxF0x64_L1ExitLatency_MASK 0x38000
-#define DxF0x64_ClockPowerManagement_OFFSET 18
-#define DxF0x64_ClockPowerManagement_WIDTH 1
-#define DxF0x64_ClockPowerManagement_MASK 0x40000
-#define DxF0x64_Reserved_19_19_OFFSET 19
-#define DxF0x64_Reserved_19_19_WIDTH 1
-#define DxF0x64_Reserved_19_19_MASK 0x80000
-#define DxF0x64_DlActiveReportingCapable_OFFSET 20
-#define DxF0x64_DlActiveReportingCapable_WIDTH 1
-#define DxF0x64_DlActiveReportingCapable_MASK 0x100000
-#define DxF0x64_LinkBWNotificationCap_OFFSET 21
-#define DxF0x64_LinkBWNotificationCap_WIDTH 1
-#define DxF0x64_LinkBWNotificationCap_MASK 0x200000
-#define DxF0x64_Reserved_23_22_OFFSET 22
-#define DxF0x64_Reserved_23_22_WIDTH 2
-#define DxF0x64_Reserved_23_22_MASK 0xc00000
-#define DxF0x64_PortNumber_OFFSET 24
-#define DxF0x64_PortNumber_WIDTH 8
-#define DxF0x64_PortNumber_MASK 0xff000000
-
-/// DxF0x64
-typedef union {
- struct { ///<
- UINT32 LinkSpeed:4 ; ///<
- UINT32 LinkWidth:6 ; ///<
- UINT32 PMSupport:2 ; ///<
- UINT32 L0sExitLatency:3 ; ///<
- UINT32 L1ExitLatency:3 ; ///<
- UINT32 ClockPowerManagement:1 ; ///<
- UINT32 Reserved_19_19:1 ; ///<
- UINT32 DlActiveReportingCapable:1 ; ///<
- UINT32 LinkBWNotificationCap:1 ; ///<
- UINT32 Reserved_23_22:2 ; ///<
- UINT32 PortNumber:8 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0x64_STRUCT;
-
-// **** DxF0x68 Register Definition ****
-// Address
-#define DxF0x68_ADDRESS 0x68
-
-// Type
-#define DxF0x68_TYPE TYPE_D4F0
-// Field Data
-#define DxF0x68_PmControl_OFFSET 0
-#define DxF0x68_PmControl_WIDTH 2
-#define DxF0x68_PmControl_MASK 0x3
-#define DxF0x68_Reserved_2_2_OFFSET 2
-#define DxF0x68_Reserved_2_2_WIDTH 1
-#define DxF0x68_Reserved_2_2_MASK 0x4
-#define DxF0x68_ReadCplBoundary_OFFSET 3
-#define DxF0x68_ReadCplBoundary_WIDTH 1
-#define DxF0x68_ReadCplBoundary_MASK 0x8
-#define DxF0x68_LinkDis_OFFSET 4
-#define DxF0x68_LinkDis_WIDTH 1
-#define DxF0x68_LinkDis_MASK 0x10
-#define DxF0x68_RetrainLink_OFFSET 5
-#define DxF0x68_RetrainLink_WIDTH 1
-#define DxF0x68_RetrainLink_MASK 0x20
-#define DxF0x68_CommonClockCfg_OFFSET 6
-#define DxF0x68_CommonClockCfg_WIDTH 1
-#define DxF0x68_CommonClockCfg_MASK 0x40
-#define DxF0x68_ExtendedSync_OFFSET 7
-#define DxF0x68_ExtendedSync_WIDTH 1
-#define DxF0x68_ExtendedSync_MASK 0x80
-#define DxF0x68_ClockPowerManagementEn_OFFSET 8
-#define DxF0x68_ClockPowerManagementEn_WIDTH 1
-#define DxF0x68_ClockPowerManagementEn_MASK 0x100
-#define DxF0x68_HWAutonomousWidthDisable_OFFSET 9
-#define DxF0x68_HWAutonomousWidthDisable_WIDTH 1
-#define DxF0x68_HWAutonomousWidthDisable_MASK 0x200
-#define DxF0x68_LinkBWManagementEn_OFFSET 10
-#define DxF0x68_LinkBWManagementEn_WIDTH 1
-#define DxF0x68_LinkBWManagementEn_MASK 0x400
-#define DxF0x68_LinkAutonomousBWIntEn_OFFSET 11
-#define DxF0x68_LinkAutonomousBWIntEn_WIDTH 1
-#define DxF0x68_LinkAutonomousBWIntEn_MASK 0x800
-#define DxF0x68_Reserved_15_12_OFFSET 12
-#define DxF0x68_Reserved_15_12_WIDTH 4
-#define DxF0x68_Reserved_15_12_MASK 0xf000
-#define DxF0x68_LinkSpeed_OFFSET 16
-#define DxF0x68_LinkSpeed_WIDTH 4
-#define DxF0x68_LinkSpeed_MASK 0xf0000
-#define DxF0x68_NegotiatedLinkWidth_OFFSET 20
-#define DxF0x68_NegotiatedLinkWidth_WIDTH 6
-#define DxF0x68_NegotiatedLinkWidth_MASK 0x3f00000
-#define DxF0x68_Reserved_26_26_OFFSET 26
-#define DxF0x68_Reserved_26_26_WIDTH 1
-#define DxF0x68_Reserved_26_26_MASK 0x4000000
-#define DxF0x68_LinkTraining_OFFSET 27
-#define DxF0x68_LinkTraining_WIDTH 1
-#define DxF0x68_LinkTraining_MASK 0x8000000
-#define DxF0x68_SlotClockCfg_OFFSET 28
-#define DxF0x68_SlotClockCfg_WIDTH 1
-#define DxF0x68_SlotClockCfg_MASK 0x10000000
-#define DxF0x68_DlActive_OFFSET 29
-#define DxF0x68_DlActive_WIDTH 1
-#define DxF0x68_DlActive_MASK 0x20000000
-#define DxF0x68_LinkBWManagementStatus_OFFSET 30
-#define DxF0x68_LinkBWManagementStatus_WIDTH 1
-#define DxF0x68_LinkBWManagementStatus_MASK 0x40000000
-#define DxF0x68_LinkAutonomousBWStatus_OFFSET 31
-#define DxF0x68_LinkAutonomousBWStatus_WIDTH 1
-#define DxF0x68_LinkAutonomousBWStatus_MASK 0x80000000
-
-/// DxF0x68
-typedef union {
- struct { ///<
- UINT32 PmControl:2 ; ///<
- UINT32 Reserved_2_2:1 ; ///<
- UINT32 ReadCplBoundary:1 ; ///<
- UINT32 LinkDis:1 ; ///<
- UINT32 RetrainLink:1 ; ///<
- UINT32 CommonClockCfg:1 ; ///<
- UINT32 ExtendedSync:1 ; ///<
- UINT32 ClockPowerManagementEn:1 ; ///<
- UINT32 HWAutonomousWidthDisable:1 ; ///<
- UINT32 LinkBWManagementEn:1 ; ///<
- UINT32 LinkAutonomousBWIntEn:1 ; ///<
- UINT32 Reserved_15_12:4 ; ///<
- UINT32 LinkSpeed:4 ; ///<
- UINT32 NegotiatedLinkWidth:6 ; ///<
- UINT32 Reserved_26_26:1 ; ///<
- UINT32 LinkTraining:1 ; ///<
- UINT32 SlotClockCfg:1 ; ///<
- UINT32 DlActive:1 ; ///<
- UINT32 LinkBWManagementStatus:1 ; ///<
- UINT32 LinkAutonomousBWStatus:1 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0x68_STRUCT;
-
-// **** DxF0x6C Register Definition ****
-// Address
-#define DxF0x6C_ADDRESS 0x6c
-
-// Type
-#define DxF0x6C_TYPE TYPE_D4F0
-// Field Data
-#define DxF0x6C_AttnButtonPresent_OFFSET 0
-#define DxF0x6C_AttnButtonPresent_WIDTH 1
-#define DxF0x6C_AttnButtonPresent_MASK 0x1
-#define DxF0x6C_PwrControllerPresent_OFFSET 1
-#define DxF0x6C_PwrControllerPresent_WIDTH 1
-#define DxF0x6C_PwrControllerPresent_MASK 0x2
-#define DxF0x6C_MrlSensorPresent_OFFSET 2
-#define DxF0x6C_MrlSensorPresent_WIDTH 1
-#define DxF0x6C_MrlSensorPresent_MASK 0x4
-#define DxF0x6C_AttnIndicatorPresent_OFFSET 3
-#define DxF0x6C_AttnIndicatorPresent_WIDTH 1
-#define DxF0x6C_AttnIndicatorPresent_MASK 0x8
-#define DxF0x6C_PwrIndicatorPresent_OFFSET 4
-#define DxF0x6C_PwrIndicatorPresent_WIDTH 1
-#define DxF0x6C_PwrIndicatorPresent_MASK 0x10
-#define DxF0x6C_HotplugSurprise_OFFSET 5
-#define DxF0x6C_HotplugSurprise_WIDTH 1
-#define DxF0x6C_HotplugSurprise_MASK 0x20
-#define DxF0x6C_HotplugCapable_OFFSET 6
-#define DxF0x6C_HotplugCapable_WIDTH 1
-#define DxF0x6C_HotplugCapable_MASK 0x40
-#define DxF0x6C_SlotPwrLimitValue_OFFSET 7
-#define DxF0x6C_SlotPwrLimitValue_WIDTH 8
-#define DxF0x6C_SlotPwrLimitValue_MASK 0x7f80
-#define DxF0x6C_SlotPwrLimitScale_OFFSET 15
-#define DxF0x6C_SlotPwrLimitScale_WIDTH 2
-#define DxF0x6C_SlotPwrLimitScale_MASK 0x18000
-#define DxF0x6C_ElecMechIlPresent_OFFSET 17
-#define DxF0x6C_ElecMechIlPresent_WIDTH 1
-#define DxF0x6C_ElecMechIlPresent_MASK 0x20000
-#define DxF0x6C_NoCmdCplSupport_OFFSET 18
-#define DxF0x6C_NoCmdCplSupport_WIDTH 1
-#define DxF0x6C_NoCmdCplSupport_MASK 0x40000
-#define DxF0x6C_PhysicalSlotNumber_OFFSET 19
-#define DxF0x6C_PhysicalSlotNumber_WIDTH 13
-#define DxF0x6C_PhysicalSlotNumber_MASK 0xfff80000
-
-/// DxF0x6C
-typedef union {
- struct { ///<
- UINT32 AttnButtonPresent:1 ; ///<
- UINT32 PwrControllerPresent:1 ; ///<
- UINT32 MrlSensorPresent:1 ; ///<
- UINT32 AttnIndicatorPresent:1 ; ///<
- UINT32 PwrIndicatorPresent:1 ; ///<
- UINT32 HotplugSurprise:1 ; ///<
- UINT32 HotplugCapable:1 ; ///<
- UINT32 SlotPwrLimitValue:8 ; ///<
- UINT32 SlotPwrLimitScale:2 ; ///<
- UINT32 ElecMechIlPresent:1 ; ///<
- UINT32 NoCmdCplSupport:1 ; ///<
- UINT32 PhysicalSlotNumber:13; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0x6C_STRUCT;
-
-// **** DxF0x70 Register Definition ****
-// Address
-#define DxF0x70_ADDRESS 0x70
-
-// Type
-#define DxF0x70_TYPE TYPE_D4F0
-// Field Data
-#define DxF0x70_AttnButtonPressedEn_OFFSET 0
-#define DxF0x70_AttnButtonPressedEn_WIDTH 1
-#define DxF0x70_AttnButtonPressedEn_MASK 0x1
-#define DxF0x70_PwrFaultDetectedEn_OFFSET 1
-#define DxF0x70_PwrFaultDetectedEn_WIDTH 1
-#define DxF0x70_PwrFaultDetectedEn_MASK 0x2
-#define DxF0x70_MrlSensorChangedEn_OFFSET 2
-#define DxF0x70_MrlSensorChangedEn_WIDTH 1
-#define DxF0x70_MrlSensorChangedEn_MASK 0x4
-#define DxF0x70_PresenceDetectChangedEn_OFFSET 3
-#define DxF0x70_PresenceDetectChangedEn_WIDTH 1
-#define DxF0x70_PresenceDetectChangedEn_MASK 0x8
-#define DxF0x70_CmdCplIntrEn_OFFSET 4
-#define DxF0x70_CmdCplIntrEn_WIDTH 1
-#define DxF0x70_CmdCplIntrEn_MASK 0x10
-#define DxF0x70_HotplugIntrEn_OFFSET 5
-#define DxF0x70_HotplugIntrEn_WIDTH 1
-#define DxF0x70_HotplugIntrEn_MASK 0x20
-#define DxF0x70_AttnIndicatorControl_OFFSET 6
-#define DxF0x70_AttnIndicatorControl_WIDTH 2
-#define DxF0x70_AttnIndicatorControl_MASK 0xc0
-#define DxF0x70_PwrIndicatorCntl_OFFSET 8
-#define DxF0x70_PwrIndicatorCntl_WIDTH 2
-#define DxF0x70_PwrIndicatorCntl_MASK 0x300
-#define DxF0x70_PwrControllerCntl_OFFSET 10
-#define DxF0x70_PwrControllerCntl_WIDTH 1
-#define DxF0x70_PwrControllerCntl_MASK 0x400
-#define DxF0x70_ElecMechIlCntl_OFFSET 11
-#define DxF0x70_ElecMechIlCntl_WIDTH 1
-#define DxF0x70_ElecMechIlCntl_MASK 0x800
-#define DxF0x70_DlStateChangedEn_OFFSET 12
-#define DxF0x70_DlStateChangedEn_WIDTH 1
-#define DxF0x70_DlStateChangedEn_MASK 0x1000
-#define DxF0x70_Reserved_15_13_OFFSET 13
-#define DxF0x70_Reserved_15_13_WIDTH 3
-#define DxF0x70_Reserved_15_13_MASK 0xe000
-#define DxF0x70_AttnButtonPressed_OFFSET 16
-#define DxF0x70_AttnButtonPressed_WIDTH 1
-#define DxF0x70_AttnButtonPressed_MASK 0x10000
-#define DxF0x70_PwrFaultDetected_OFFSET 17
-#define DxF0x70_PwrFaultDetected_WIDTH 1
-#define DxF0x70_PwrFaultDetected_MASK 0x20000
-#define DxF0x70_MrlSensorChanged_OFFSET 18
-#define DxF0x70_MrlSensorChanged_WIDTH 1
-#define DxF0x70_MrlSensorChanged_MASK 0x40000
-#define DxF0x70_PresenceDetectChanged_OFFSET 19
-#define DxF0x70_PresenceDetectChanged_WIDTH 1
-#define DxF0x70_PresenceDetectChanged_MASK 0x80000
-#define DxF0x70_CmdCpl_OFFSET 20
-#define DxF0x70_CmdCpl_WIDTH 1
-#define DxF0x70_CmdCpl_MASK 0x100000
-#define DxF0x70_MrlSensorState_OFFSET 21
-#define DxF0x70_MrlSensorState_WIDTH 1
-#define DxF0x70_MrlSensorState_MASK 0x200000
-#define DxF0x70_PresenceDetectState_OFFSET 22
-#define DxF0x70_PresenceDetectState_WIDTH 1
-#define DxF0x70_PresenceDetectState_MASK 0x400000
-#define DxF0x70_ElecMechIlSts_OFFSET 23
-#define DxF0x70_ElecMechIlSts_WIDTH 1
-#define DxF0x70_ElecMechIlSts_MASK 0x800000
-#define DxF0x70_DlStateChanged_OFFSET 24
-#define DxF0x70_DlStateChanged_WIDTH 1
-#define DxF0x70_DlStateChanged_MASK 0x1000000
-#define DxF0x70_Reserved_31_25_OFFSET 25
-#define DxF0x70_Reserved_31_25_WIDTH 7
-#define DxF0x70_Reserved_31_25_MASK 0xfe000000
-
-/// DxF0x70
-typedef union {
- struct { ///<
- UINT32 AttnButtonPressedEn:1 ; ///<
- UINT32 PwrFaultDetectedEn:1 ; ///<
- UINT32 MrlSensorChangedEn:1 ; ///<
- UINT32 PresenceDetectChangedEn:1 ; ///<
- UINT32 CmdCplIntrEn:1 ; ///<
- UINT32 HotplugIntrEn:1 ; ///<
- UINT32 AttnIndicatorControl:2 ; ///<
- UINT32 PwrIndicatorCntl:2 ; ///<
- UINT32 PwrControllerCntl:1 ; ///<
- UINT32 ElecMechIlCntl:1 ; ///<
- UINT32 DlStateChangedEn:1 ; ///<
- UINT32 Reserved_15_13:3 ; ///<
- UINT32 AttnButtonPressed:1 ; ///<
- UINT32 PwrFaultDetected:1 ; ///<
- UINT32 MrlSensorChanged:1 ; ///<
- UINT32 PresenceDetectChanged:1 ; ///<
- UINT32 CmdCpl:1 ; ///<
- UINT32 MrlSensorState:1 ; ///<
- UINT32 PresenceDetectState:1 ; ///<
- UINT32 ElecMechIlSts:1 ; ///<
- UINT32 DlStateChanged:1 ; ///<
- UINT32 Reserved_31_25:7 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0x70_STRUCT;
-
-// **** DxF0x74 Register Definition ****
-// Address
-#define DxF0x74_ADDRESS 0x74
-
-// Type
-#define DxF0x74_TYPE TYPE_D4F0
-// Field Data
-#define DxF0x74_SerrOnCorrErrEn_OFFSET 0
-#define DxF0x74_SerrOnCorrErrEn_WIDTH 1
-#define DxF0x74_SerrOnCorrErrEn_MASK 0x1
-#define DxF0x74_SerrOnNonFatalErrEn_OFFSET 1
-#define DxF0x74_SerrOnNonFatalErrEn_WIDTH 1
-#define DxF0x74_SerrOnNonFatalErrEn_MASK 0x2
-#define DxF0x74_SerrOnFatalErrEn_OFFSET 2
-#define DxF0x74_SerrOnFatalErrEn_WIDTH 1
-#define DxF0x74_SerrOnFatalErrEn_MASK 0x4
-#define DxF0x74_PmIntEn_OFFSET 3
-#define DxF0x74_PmIntEn_WIDTH 1
-#define DxF0x74_PmIntEn_MASK 0x8
-#define DxF0x74_CrsSoftVisibilityEn_OFFSET 4
-#define DxF0x74_CrsSoftVisibilityEn_WIDTH 1
-#define DxF0x74_CrsSoftVisibilityEn_MASK 0x10
-#define DxF0x74_Reserved_15_5_OFFSET 5
-#define DxF0x74_Reserved_15_5_WIDTH 11
-#define DxF0x74_Reserved_15_5_MASK 0xffe0
-#define DxF0x74_CrsSoftVisibility_OFFSET 16
-#define DxF0x74_CrsSoftVisibility_WIDTH 1
-#define DxF0x74_CrsSoftVisibility_MASK 0x10000
-#define DxF0x74_Reserved_31_17_OFFSET 17
-#define DxF0x74_Reserved_31_17_WIDTH 15
-#define DxF0x74_Reserved_31_17_MASK 0xfffe0000
-
-/// DxF0x74
-typedef union {
- struct { ///<
- UINT32 SerrOnCorrErrEn:1 ; ///<
- UINT32 SerrOnNonFatalErrEn:1 ; ///<
- UINT32 SerrOnFatalErrEn:1 ; ///<
- UINT32 PmIntEn:1 ; ///<
- UINT32 CrsSoftVisibilityEn:1 ; ///<
- UINT32 Reserved_15_5:11; ///<
- UINT32 CrsSoftVisibility:1 ; ///<
- UINT32 Reserved_31_17:15; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0x74_STRUCT;
-
-// **** DxF0x78 Register Definition ****
-// Address
-#define DxF0x78_ADDRESS 0x78
-
-// Type
-#define DxF0x78_TYPE TYPE_D4F0
-// Field Data
-#define DxF0x78_PmeRequestorId_OFFSET 0
-#define DxF0x78_PmeRequestorId_WIDTH 16
-#define DxF0x78_PmeRequestorId_MASK 0xffff
-#define DxF0x78_PmeStatus_OFFSET 16
-#define DxF0x78_PmeStatus_WIDTH 1
-#define DxF0x78_PmeStatus_MASK 0x10000
-#define DxF0x78_PmePending_OFFSET 17
-#define DxF0x78_PmePending_WIDTH 1
-#define DxF0x78_PmePending_MASK 0x20000
-#define DxF0x78_Reserved_31_18_OFFSET 18
-#define DxF0x78_Reserved_31_18_WIDTH 14
-#define DxF0x78_Reserved_31_18_MASK 0xfffc0000
-
-/// DxF0x78
-typedef union {
- struct { ///<
- UINT32 PmeRequestorId:16; ///<
- UINT32 PmeStatus:1 ; ///<
- UINT32 PmePending:1 ; ///<
- UINT32 Reserved_31_18:14; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0x78_STRUCT;
-
-// **** DxF0x7C Register Definition ****
-// Address
-#define DxF0x7C_ADDRESS 0x7c
-
-// Type
-#define DxF0x7C_TYPE TYPE_D4F0
-// Field Data
-#define DxF0x7C_CplTimeoutRangeSup_OFFSET 0
-#define DxF0x7C_CplTimeoutRangeSup_WIDTH 4
-#define DxF0x7C_CplTimeoutRangeSup_MASK 0xf
-#define DxF0x7C_CplTimeoutDisSup_OFFSET 4
-#define DxF0x7C_CplTimeoutDisSup_WIDTH 1
-#define DxF0x7C_CplTimeoutDisSup_MASK 0x10
-#define DxF0x7C_AriForwardingSupported_OFFSET 5
-#define DxF0x7C_AriForwardingSupported_WIDTH 1
-#define DxF0x7C_AriForwardingSupported_MASK 0x20
-#define DxF0x7C_Reserved_31_6_OFFSET 6
-#define DxF0x7C_Reserved_31_6_WIDTH 26
-#define DxF0x7C_Reserved_31_6_MASK 0xffffffc0
-
-/// DxF0x7C
-typedef union {
- struct { ///<
- UINT32 CplTimeoutRangeSup:4 ; ///<
- UINT32 CplTimeoutDisSup:1 ; ///<
- UINT32 AriForwardingSupported:1 ; ///<
- UINT32 Reserved_31_6:26; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0x7C_STRUCT;
-
-// **** DxF0x80 Register Definition ****
-// Address
-#define DxF0x80_ADDRESS 0x80
-
-// Type
-#define DxF0x80_TYPE TYPE_D4F0
-// Field Data
-#define DxF0x80_CplTimeoutValue_OFFSET 0
-#define DxF0x80_CplTimeoutValue_WIDTH 4
-#define DxF0x80_CplTimeoutValue_MASK 0xf
-#define DxF0x80_CplTimeoutDis_OFFSET 4
-#define DxF0x80_CplTimeoutDis_WIDTH 1
-#define DxF0x80_CplTimeoutDis_MASK 0x10
-#define DxF0x80_AriForwardingEn_OFFSET 5
-#define DxF0x80_AriForwardingEn_WIDTH 1
-#define DxF0x80_AriForwardingEn_MASK 0x20
-#define DxF0x80_Reserved_31_6_OFFSET 6
-#define DxF0x80_Reserved_31_6_WIDTH 26
-#define DxF0x80_Reserved_31_6_MASK 0xffffffc0
-
-/// DxF0x80
-typedef union {
- struct { ///<
- UINT32 CplTimeoutValue:4 ; ///<
- UINT32 CplTimeoutDis:1 ; ///<
- UINT32 AriForwardingEn:1 ; ///<
- UINT32 Reserved_31_6:26; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0x80_STRUCT;
-
-// **** DxF0x84 Register Definition ****
-// Address
-#define DxF0x84_ADDRESS 0x84
-
-// Type
-#define DxF0x84_TYPE TYPE_D4F0
-// Field Data
-#define DxF0x84_Reserved_31_0_OFFSET 0
-#define DxF0x84_Reserved_31_0_WIDTH 32
-#define DxF0x84_Reserved_31_0_MASK 0xffffffff
-
-/// DxF0x84
-typedef union {
- struct { ///<
- UINT32 Reserved_31_0:32; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0x84_STRUCT;
-
-// **** DxF0x88 Register Definition ****
-// Address
-#define DxF0x88_ADDRESS 0x88
-
-// Type
-#define DxF0x88_TYPE TYPE_D4F0
-// Field Data
-#define DxF0x88_TargetLinkSpeed_OFFSET 0
-#define DxF0x88_TargetLinkSpeed_WIDTH 4
-#define DxF0x88_TargetLinkSpeed_MASK 0xf
-#define DxF0x88_EnterCompliance_OFFSET 4
-#define DxF0x88_EnterCompliance_WIDTH 1
-#define DxF0x88_EnterCompliance_MASK 0x10
-#define DxF0x88_HwAutonomousSpeedDisable_OFFSET 5
-#define DxF0x88_HwAutonomousSpeedDisable_WIDTH 1
-#define DxF0x88_HwAutonomousSpeedDisable_MASK 0x20
-#define DxF0x88_SelectableDeemphasis_OFFSET 6
-#define DxF0x88_SelectableDeemphasis_WIDTH 1
-#define DxF0x88_SelectableDeemphasis_MASK 0x40
-#define DxF0x88_XmitMargin_OFFSET 7
-#define DxF0x88_XmitMargin_WIDTH 3
-#define DxF0x88_XmitMargin_MASK 0x380
-#define DxF0x88_EnterModCompliance_OFFSET 10
-#define DxF0x88_EnterModCompliance_WIDTH 1
-#define DxF0x88_EnterModCompliance_MASK 0x400
-#define DxF0x88_ComplianceSOS_OFFSET 11
-#define DxF0x88_ComplianceSOS_WIDTH 1
-#define DxF0x88_ComplianceSOS_MASK 0x800
-#define DxF0x88_ComplianceDeemphasis_OFFSET 12
-#define DxF0x88_ComplianceDeemphasis_WIDTH 1
-#define DxF0x88_ComplianceDeemphasis_MASK 0x1000
-#define DxF0x88_Reserved_15_13_OFFSET 13
-#define DxF0x88_Reserved_15_13_WIDTH 3
-#define DxF0x88_Reserved_15_13_MASK 0xe000
-#define DxF0x88_CurDeemphasisLevel_OFFSET 16
-#define DxF0x88_CurDeemphasisLevel_WIDTH 1
-#define DxF0x88_CurDeemphasisLevel_MASK 0x10000
-#define DxF0x88_Reserved_31_17_OFFSET 17
-#define DxF0x88_Reserved_31_17_WIDTH 15
-#define DxF0x88_Reserved_31_17_MASK 0xfffe0000
-
-/// DxF0x88
-typedef union {
- struct { ///<
- UINT32 TargetLinkSpeed:4 ; ///<
- UINT32 EnterCompliance:1 ; ///<
- UINT32 HwAutonomousSpeedDisable:1 ; ///<
- UINT32 SelectableDeemphasis:1 ; ///<
- UINT32 XmitMargin:3 ; ///<
- UINT32 EnterModCompliance:1 ; ///<
- UINT32 ComplianceSOS:1 ; ///<
- UINT32 ComplianceDeemphasis:1 ; ///<
- UINT32 Reserved_15_13:3 ; ///<
- UINT32 CurDeemphasisLevel:1 ; ///<
- UINT32 Reserved_31_17:15; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0x88_STRUCT;
-
-// **** DxF0x8C Register Definition ****
-// Address
-#define DxF0x8C_ADDRESS 0x8c
-
-// Type
-#define DxF0x8C_TYPE TYPE_D4F0
-// Field Data
-#define DxF0x8C_Reserved_31_0_OFFSET 0
-#define DxF0x8C_Reserved_31_0_WIDTH 32
-#define DxF0x8C_Reserved_31_0_MASK 0xffffffff
-
-/// DxF0x8C
-typedef union {
- struct { ///<
- UINT32 Reserved_31_0:32; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0x8C_STRUCT;
-
-// **** DxF0x90 Register Definition ****
-// Address
-#define DxF0x90_ADDRESS 0x90
-
-// Type
-#define DxF0x90_TYPE TYPE_D4F0
-// Field Data
-#define DxF0x90_Reserved_31_0_OFFSET 0
-#define DxF0x90_Reserved_31_0_WIDTH 32
-#define DxF0x90_Reserved_31_0_MASK 0xffffffff
-
-/// DxF0x90
-typedef union {
- struct { ///<
- UINT32 Reserved_31_0:32; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0x90_STRUCT;
-
-// **** DxF0x128 Register Definition ****
-// Address
-#define DxF0x128_ADDRESS 0x128
-
-// Type
-#define DxF0x128_TYPE TYPE_D4F0
-// Field Data
-#define DxF0x128_Reserved_15_0_OFFSET 0
-#define DxF0x128_Reserved_15_0_WIDTH 16
-#define DxF0x128_Reserved_15_0_MASK 0xffff
-#define DxF0x128_PortArbTableStatus_OFFSET 16
-#define DxF0x128_PortArbTableStatus_WIDTH 1
-#define DxF0x128_PortArbTableStatus_MASK 0x10000
-#define DxF0x128_VcNegotiationPending_OFFSET 17
-#define DxF0x128_VcNegotiationPending_WIDTH 1
-#define DxF0x128_VcNegotiationPending_MASK 0x20000
-#define DxF0x128_Reserved_31_18_OFFSET 18
-#define DxF0x128_Reserved_31_18_WIDTH 14
-#define DxF0x128_Reserved_31_18_MASK 0xfffc0000
-
-/// DxF0x128
-typedef union {
- struct { ///<
- UINT32 Reserved_15_0:16; ///<
- UINT32 PortArbTableStatus:1 ; ///<
- UINT32 VcNegotiationPending:1 ; ///<
- UINT32 Reserved_31_18:14; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0x128_STRUCT;
-
-// **** FCRxFE00_6000 Register Definition ****
-// Address
-#define FCRxFE00_6000_ADDRESS 0xfe006000
-
-// Type
-#define FCRxFE00_6000_TYPE TYPE_FCR
-// Field Data
-#define FCRxFE00_6000_Reserved_6_0_OFFSET 0
-#define FCRxFE00_6000_Reserved_6_0_WIDTH 7
-#define FCRxFE00_6000_Reserved_6_0_MASK 0x7f
-#define FCRxFE00_6000_NbPs0Vid_OFFSET 7
-#define FCRxFE00_6000_NbPs0Vid_WIDTH 7
-#define FCRxFE00_6000_NbPs0Vid_MASK 0x3f80
-#define FCRxFE00_6000_NbPs1Vid_OFFSET 14
-#define FCRxFE00_6000_NbPs1Vid_WIDTH 7
-#define FCRxFE00_6000_NbPs1Vid_MASK 0x1fc000
-#define FCRxFE00_6000_Reserved_31_21_OFFSET 21
-#define FCRxFE00_6000_Reserved_31_21_WIDTH 11
-#define FCRxFE00_6000_Reserved_31_21_MASK 0xffe00000
-
-/// FCRxFE00_6000
-typedef union {
- struct { ///<
- UINT32 Reserved_6_0:7 ; ///<
- UINT32 NbPs0Vid:7 ; ///<
- UINT32 NbPs1Vid:7 ; ///<
- UINT32 Reserved_31_21:11; ///<
- } Field; ///<
- UINT32 Value; ///<
-} FCRxFE00_6000_STRUCT;
-
-// **** FCRxFE00_6002 Register Definition ****
-// Address
-#define FCRxFE00_6002_ADDRESS 0xfe006002
-
-// Type
-#define FCRxFE00_6002_TYPE TYPE_FCR
-// Field Data
-#define FCRxFE00_6002_Reserved_4_0_OFFSET 0
-#define FCRxFE00_6002_Reserved_4_0_WIDTH 5
-#define FCRxFE00_6002_Reserved_4_0_MASK 0x1f
-#define FCRxFE00_6002_NbPs1VidAddl_OFFSET 5
-#define FCRxFE00_6002_NbPs1VidAddl_WIDTH 7
-#define FCRxFE00_6002_NbPs1VidAddl_MASK 0xfe0
-#define FCRxFE00_6002_NbPs1VidHigh_OFFSET 12
-#define FCRxFE00_6002_NbPs1VidHigh_WIDTH 7
-#define FCRxFE00_6002_NbPs1VidHigh_MASK 0x7f000
-#define FCRxFE00_6002_Reserved_31_19_OFFSET 19
-#define FCRxFE00_6002_Reserved_31_19_WIDTH 13
-#define FCRxFE00_6002_Reserved_31_19_MASK 0xfff80000
-
-/// FCRxFE00_6002
-typedef union {
- struct { ///<
- UINT32 Reserved_4_0:5 ; ///<
- UINT32 NbPs1VidAddl:7 ; ///<
- UINT32 NbPs1VidHigh:7 ; ///<
- UINT32 Reserved_31_19:13; ///<
- } Field; ///<
- UINT32 Value; ///<
-} FCRxFE00_6002_STRUCT;
-
-// **** FCRxFE00_7006 Register Definition ****
-// Address
-#define FCRxFE00_7006_ADDRESS 0xfe007006
-
-// Type
-#define FCRxFE00_7006_TYPE TYPE_FCR
-// Field Data
-#define FCRxFE00_7006_Reserved_13_0_OFFSET 0
-#define FCRxFE00_7006_Reserved_13_0_WIDTH 14
-#define FCRxFE00_7006_Reserved_13_0_MASK 0x3fff
-#define FCRxFE00_7006_NbPs1NclkDiv_OFFSET 14
-#define FCRxFE00_7006_NbPs1NclkDiv_WIDTH 7
-#define FCRxFE00_7006_NbPs1NclkDiv_MASK 0x1fc000
-#define FCRxFE00_7006_MaxNbFreqAtMinVid_OFFSET 21
-#define FCRxFE00_7006_MaxNbFreqAtMinVid_WIDTH 5
-#define FCRxFE00_7006_MaxNbFreqAtMinVid_MASK 0x3e00000
-#define FCRxFE00_7006_Reserved_31_26_OFFSET 26
-#define FCRxFE00_7006_Reserved_31_26_WIDTH 6
-#define FCRxFE00_7006_Reserved_31_26_MASK 0xfc000000
-
-/// FCRxFE00_7006
-typedef union {
- struct { ///<
- UINT32 Reserved_13_0:14; ///<
- UINT32 NbPs1NclkDiv:7 ; ///<
- UINT32 MaxNbFreqAtMinVid:5 ; ///<
- UINT32 Reserved_31_26:6 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} FCRxFE00_7006_STRUCT;
-
-// **** FCRxFE00_7009 Register Definition ****
-// Address
-#define FCRxFE00_7009_ADDRESS 0xfe007009
-
-// Type
-#define FCRxFE00_7009_TYPE TYPE_FCR
-// Field Data
-#define FCRxFE00_7009_Reserved_1_0_OFFSET 0
-#define FCRxFE00_7009_Reserved_1_0_WIDTH 2
-#define FCRxFE00_7009_Reserved_1_0_MASK 0x3
-#define FCRxFE00_7009_NbPs0NclkDiv_OFFSET 2
-#define FCRxFE00_7009_NbPs0NclkDiv_WIDTH 7
-#define FCRxFE00_7009_NbPs0NclkDiv_MASK 0x1fc
-#define FCRxFE00_7009_Reserved_31_9_OFFSET 9
-#define FCRxFE00_7009_Reserved_31_9_WIDTH 23
-#define FCRxFE00_7009_Reserved_31_9_MASK 0xfffffe00
-
-/// FCRxFE00_7009
-typedef union {
- struct { ///<
- UINT32 Reserved_1_0:2 ; ///<
- UINT32 NbPs0NclkDiv:7 ; ///<
- UINT32 Reserved_31_9:23; ///<
- } Field; ///<
- UINT32 Value; ///<
-} FCRxFE00_7009_STRUCT;
-
-
-// **** D0F0x64_x00 Register Definition ****
-// Address
-#define D0F0x64_x00_ADDRESS 0x0
-
-// Type
-#define D0F0x64_x00_TYPE TYPE_D0F0x64
-// Field Data
-#define D0F0x64_x00_Reserved_5_0_OFFSET 0
-#define D0F0x64_x00_Reserved_5_0_WIDTH 6
-#define D0F0x64_x00_Reserved_5_0_MASK 0x3f
-#define D0F0x64_x00_NbFchCfgEn_OFFSET 6
-#define D0F0x64_x00_NbFchCfgEn_WIDTH 1
-#define D0F0x64_x00_NbFchCfgEn_MASK 0x40
-#define D0F0x64_x00_HwInitWrLock_OFFSET 7
-#define D0F0x64_x00_HwInitWrLock_WIDTH 1
-#define D0F0x64_x00_HwInitWrLock_MASK 0x80
-#define D0F0x64_x00_Reserved_31_8_OFFSET 8
-#define D0F0x64_x00_Reserved_31_8_WIDTH 24
-#define D0F0x64_x00_Reserved_31_8_MASK 0xffffff00
-
-/// D0F0x64_x00
-typedef union {
- struct { ///<
- UINT32 Reserved_5_0:6 ; ///<
- UINT32 NbFchCfgEn:1 ; ///<
- UINT32 HwInitWrLock:1 ; ///<
- UINT32 Reserved_31_8:24; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x64_x00_STRUCT;
-
-// **** D0F0x64_x0B Register Definition ****
-// Address
-#define D0F0x64_x0B_ADDRESS 0xb
-
-// Type
-#define D0F0x64_x0B_TYPE TYPE_D0F0x64
-// Field Data
-#define D0F0x64_x0B_Reserved_19_0_OFFSET 0
-#define D0F0x64_x0B_Reserved_19_0_WIDTH 20
-#define D0F0x64_x0B_Reserved_19_0_MASK 0xfffff
-#define D0F0x64_x0B_SetPowEn_OFFSET 20
-#define D0F0x64_x0B_SetPowEn_WIDTH 1
-#define D0F0x64_x0B_SetPowEn_MASK 0x100000
-#define D0F0x64_x0B_IocFchSetPowEn_OFFSET 21
-#define D0F0x64_x0B_IocFchSetPowEn_WIDTH 1
-#define D0F0x64_x0B_IocFchSetPowEn_MASK 0x200000
-#define D0F0x64_x0B_Reserved_22_22_OFFSET 22
-#define D0F0x64_x0B_Reserved_22_22_WIDTH 1
-#define D0F0x64_x0B_Reserved_22_22_MASK 0x400000
-#define D0F0x64_x0B_IocFchSetPmeTurnOffEn_OFFSET 23
-#define D0F0x64_x0B_IocFchSetPmeTurnOffEn_WIDTH 1
-#define D0F0x64_x0B_IocFchSetPmeTurnOffEn_MASK 0x800000
-#define D0F0x64_x0B_Reserved_31_24_OFFSET 24
-#define D0F0x64_x0B_Reserved_31_24_WIDTH 8
-#define D0F0x64_x0B_Reserved_31_24_MASK 0xff000000
-
-/// D0F0x64_x0B
-typedef union {
- struct { ///<
- UINT32 Reserved_19_0:20; ///<
- UINT32 SetPowEn:1 ; ///<
- UINT32 IocFchSetPowEn:1 ; ///<
- UINT32 Reserved_22_22:1 ; ///<
- UINT32 IocFchSetPmeTurnOffEn:1 ; ///<
- UINT32 Reserved_31_24:8 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x64_x0B_STRUCT;
-
-// **** D0F0x64_x0C Register Definition ****
-// Address
-#define D0F0x64_x0C_ADDRESS 0xc
-
-// Type
-#define D0F0x64_x0C_TYPE TYPE_D0F0x64
-// Field Data
-#define D0F0x64_x0C_Reserved_3_0_OFFSET 0
-#define D0F0x64_x0C_Reserved_3_0_WIDTH 4
-#define D0F0x64_x0C_Reserved_3_0_MASK 0xf
-#define D0F0x64_x0C_Dev4BridgeDis_OFFSET 4
-#define D0F0x64_x0C_Dev4BridgeDis_WIDTH 1
-#define D0F0x64_x0C_Dev4BridgeDis_MASK 0x10
-#define D0F0x64_x0C_Dev5BridgeDis_OFFSET 5
-#define D0F0x64_x0C_Dev5BridgeDis_WIDTH 1
-#define D0F0x64_x0C_Dev5BridgeDis_MASK 0x20
-#define D0F0x64_x0C_Dev6BridgeDis_OFFSET 6
-#define D0F0x64_x0C_Dev6BridgeDis_WIDTH 1
-#define D0F0x64_x0C_Dev6BridgeDis_MASK 0x40
-#define D0F0x64_x0C_Dev7BridgeDis_OFFSET 7
-#define D0F0x64_x0C_Dev7BridgeDis_WIDTH 1
-#define D0F0x64_x0C_Dev7BridgeDis_MASK 0x80
-#define D0F0x64_x0C_Reserved_31_8_OFFSET 8
-#define D0F0x64_x0C_Reserved_31_8_WIDTH 24
-#define D0F0x64_x0C_Reserved_31_8_MASK 0xffffff00
-
-/// D0F0x64_x0C
-typedef union {
- struct { ///<
- UINT32 Reserved_3_0:4 ; ///<
- UINT32 Dev4BridgeDis:1 ; ///<
- UINT32 Dev5BridgeDis:1 ; ///<
- UINT32 Dev6BridgeDis:1 ; ///<
- UINT32 Dev7BridgeDis:1 ; ///<
- UINT32 Reserved_31_8:24; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x64_x0C_STRUCT;
-
-// **** D0F0x64_x16 Register Definition ****
-// Address
-#define D0F0x64_x16_ADDRESS 0x16
-
-// Type
-#define D0F0x64_x16_TYPE TYPE_D0F0x64
-// Field Data
-#define D0F0x64_x16_AerUrMsgEn_OFFSET 0
-#define D0F0x64_x16_AerUrMsgEn_WIDTH 1
-#define D0F0x64_x16_AerUrMsgEn_MASK 0x1
-#define D0F0x64_x16_Reserved_31_1_OFFSET 1
-#define D0F0x64_x16_Reserved_31_1_WIDTH 31
-#define D0F0x64_x16_Reserved_31_1_MASK 0xfffffffe
-
-/// D0F0x64_x16
-typedef union {
- struct { ///<
- UINT32 AerUrMsgEn:1 ; ///<
- UINT32 Reserved_31_1:31; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x64_x16_STRUCT;
-
-// **** D0F0x64_x19 Register Definition ****
-// Address
-#define D0F0x64_x19_ADDRESS 0x19
-
-// Type
-#define D0F0x64_x19_TYPE TYPE_D0F0x64
-// Field Data
-#define D0F0x64_x19_TomEn_OFFSET 0
-#define D0F0x64_x19_TomEn_WIDTH 1
-#define D0F0x64_x19_TomEn_MASK 0x1
-#define D0F0x64_x19_Reserved_22_1_OFFSET 1
-#define D0F0x64_x19_Reserved_22_1_WIDTH 22
-#define D0F0x64_x19_Reserved_22_1_MASK 0x7ffffe
-#define D0F0x64_x19_Tom2_31_23__OFFSET 23
-#define D0F0x64_x19_Tom2_31_23__WIDTH 9
-#define D0F0x64_x19_Tom2_31_23__MASK 0xff800000
-
-/// D0F0x64_x19
-typedef union {
- struct { ///<
- UINT32 TomEn:1 ; ///<
- UINT32 Reserved_22_1:22; ///<
- UINT32 Tom2_31_23_:9 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x64_x19_STRUCT;
-
-// **** D0F0x64_x1A Register Definition ****
-// Address
-#define D0F0x64_x1A_ADDRESS 0x1a
-
-// Type
-#define D0F0x64_x1A_TYPE TYPE_D0F0x64
-// Field Data
-#define D0F0x64_x1A_Tom2_35_32__OFFSET 0
-#define D0F0x64_x1A_Tom2_35_32__WIDTH 4
-#define D0F0x64_x1A_Tom2_35_32__MASK 0xf
-#define D0F0x64_x1A_Reserved_31_4_OFFSET 4
-#define D0F0x64_x1A_Reserved_31_4_WIDTH 28
-#define D0F0x64_x1A_Reserved_31_4_MASK 0xfffffff0
-
-/// D0F0x64_x1A
-typedef union {
- struct { ///<
- UINT32 Tom2_35_32_:4 ; ///<
- UINT32 Reserved_31_4:28; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x64_x1A_STRUCT;
-
-// **** D0F0x64_x1D Register Definition ****
-// Address
-#define D0F0x64_x1D_ADDRESS 0x1d
-
-// Type
-#define D0F0x64_x1D_TYPE TYPE_D0F0x64
-// Field Data
-#define D0F0x64_x1D_IntGfxAsPcieEn_OFFSET 0
-#define D0F0x64_x1D_IntGfxAsPcieEn_WIDTH 1
-#define D0F0x64_x1D_IntGfxAsPcieEn_MASK 0x1
-#define D0F0x64_x1D_VgaEn_OFFSET 1
-#define D0F0x64_x1D_VgaEn_WIDTH 1
-#define D0F0x64_x1D_VgaEn_MASK 0x2
-#define D0F0x64_x1D_Reserved_2_2_OFFSET 2
-#define D0F0x64_x1D_Reserved_2_2_WIDTH 1
-#define D0F0x64_x1D_Reserved_2_2_MASK 0x4
-#define D0F0x64_x1D_Vga16En_OFFSET 3
-#define D0F0x64_x1D_Vga16En_WIDTH 1
-#define D0F0x64_x1D_Vga16En_MASK 0x8
-#define D0F0x64_x1D_Reserved_31_4_OFFSET 4
-#define D0F0x64_x1D_Reserved_31_4_WIDTH 28
-#define D0F0x64_x1D_Reserved_31_4_MASK 0xfffffff0
-
-/// D0F0x64_x1D
-typedef union {
- struct { ///<
- UINT32 IntGfxAsPcieEn:1 ; ///<
- UINT32 VgaEn:1 ; ///<
- UINT32 Reserved_2_2:1 ; ///<
- UINT32 Vga16En:1 ; ///<
- UINT32 Reserved_31_4:28; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x64_x1D_STRUCT;
-
-// **** D0F0x64_x20 Register Definition ****
-// Address
-#define D0F0x64_x20_ADDRESS 0x20
-
-// Type
-#define D0F0x64_x20_TYPE TYPE_D0F0x64
-// Field Data
-#define D0F0x64_x20_Reserved_0_0_OFFSET 0
-#define D0F0x64_x20_Reserved_0_0_WIDTH 1
-#define D0F0x64_x20_Reserved_0_0_MASK 0x1
-#define D0F0x64_x20_PcieDevRemapDis_OFFSET 1
-#define D0F0x64_x20_PcieDevRemapDis_WIDTH 1
-#define D0F0x64_x20_PcieDevRemapDis_MASK 0x2
-#define D0F0x64_x20_Reserved_31_2_OFFSET 2
-#define D0F0x64_x20_Reserved_31_2_WIDTH 30
-#define D0F0x64_x20_Reserved_31_2_MASK 0xfffffffc
-
-/// D0F0x64_x20
-typedef union {
- struct { ///<
- UINT32 Reserved_0_0:1 ; ///<
- UINT32 PcieDevRemapDis:1 ; ///<
- UINT32 Reserved_31_2:30; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x64_x20_STRUCT;
-
-// **** D0F0x64_x46 Register Definition ****
-// Address
-#define D0F0x64_x46_ADDRESS 0x46
-
-// Type
-#define D0F0x64_x46_TYPE TYPE_D0F0x64
-// Field Data
-#define D0F0x64_x46_Reserved_0_0_OFFSET 0
-#define D0F0x64_x46_Reserved_0_0_WIDTH 1
-#define D0F0x64_x46_Reserved_0_0_MASK 0x1
-#define D0F0x64_x46_P2PMode_OFFSET 1
-#define D0F0x64_x46_P2PMode_WIDTH 2
-#define D0F0x64_x46_P2PMode_MASK 0x6
-#define D0F0x64_x46_Reserved_15_3_OFFSET 3
-#define D0F0x64_x46_Reserved_15_3_WIDTH 13
-#define D0F0x64_x46_Reserved_15_3_MASK 0xfff8
-#define D0F0x64_x46_Msi64bitEn_OFFSET 16
-#define D0F0x64_x46_Msi64bitEn_WIDTH 1
-#define D0F0x64_x46_Msi64bitEn_MASK 0x10000
-#define D0F0x64_x46_Reserved_31_17_OFFSET 17
-#define D0F0x64_x46_Reserved_31_17_WIDTH 15
-#define D0F0x64_x46_Reserved_31_17_MASK 0xfffe0000
-
-/// D0F0x64_x46
-typedef union {
- struct { ///<
- UINT32 Reserved_0_0:1 ; ///<
- UINT32 P2PMode:2 ; ///<
- UINT32 Reserved_15_3:13; ///<
- UINT32 Msi64bitEn:1 ; ///<
- UINT32 Reserved_31_17:15; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x64_x46_STRUCT;
-
-// **** D0F0x64_x4D Register Definition ****
-// Address
-#define D0F0x64_x4D_ADDRESS 0x4d
-
-// Type
-#define D0F0x64_x4D_TYPE TYPE_D0F0x64
-// Field Data
-#define D0F0x64_x4D_WriteData_OFFSET 0
-#define D0F0x64_x4D_WriteData_WIDTH 16
-#define D0F0x64_x4D_WriteData_MASK 0xffff
-#define D0F0x64_x4D_SmuAddr_OFFSET 16
-#define D0F0x64_x4D_SmuAddr_WIDTH 8
-#define D0F0x64_x4D_SmuAddr_MASK 0xff0000
-#define D0F0x64_x4D_ReqToggle_OFFSET 24
-#define D0F0x64_x4D_ReqToggle_WIDTH 1
-#define D0F0x64_x4D_ReqToggle_MASK 0x1000000
-#define D0F0x64_x4D_ReqType_OFFSET 25
-#define D0F0x64_x4D_ReqType_WIDTH 1
-#define D0F0x64_x4D_ReqType_MASK 0x2000000
-#define D0F0x64_x4D_Reserved_31_26_OFFSET 26
-#define D0F0x64_x4D_Reserved_31_26_WIDTH 6
-#define D0F0x64_x4D_Reserved_31_26_MASK 0xfc000000
-
-/// D0F0x64_x4D
-typedef union {
- struct { ///<
- UINT32 WriteData:16; ///<
- UINT32 SmuAddr:8 ; ///<
- UINT32 ReqToggle:1 ; ///<
- UINT32 ReqType:1 ; ///<
- UINT32 Reserved_31_26:6 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x64_x4D_STRUCT;
-
-// **** D0F0x64_x4E Register Definition ****
-// Address
-#define D0F0x64_x4E_ADDRESS 0x4e
-
-// Type
-#define D0F0x64_x4E_TYPE TYPE_D0F0x64
-// Field Data
-#define D0F0x64_x4E_SmuReadData_OFFSET 0
-#define D0F0x64_x4E_SmuReadData_WIDTH 32
-#define D0F0x64_x4E_SmuReadData_MASK 0xffffffff
-
-/// D0F0x64_x4E
-typedef union {
- struct { ///<
- UINT32 SmuReadData:32; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x64_x4E_STRUCT;
-
-// **** D0F0x64_x55 Register Definition ****
-// Address
-#define D0F0x64_x55_ADDRESS 0x55
-
-// Type
-#define D0F0x64_x55_TYPE TYPE_D0F0x64
-// Field Data
-#define D0F0x64_x55_Reserved_19_0_OFFSET 0
-#define D0F0x64_x55_Reserved_19_0_WIDTH 20
-#define D0F0x64_x55_Reserved_19_0_MASK 0xfffff
-#define D0F0x64_x55_SetPowEn_OFFSET 20
-#define D0F0x64_x55_SetPowEn_WIDTH 1
-#define D0F0x64_x55_SetPowEn_MASK 0x100000
-#define D0F0x64_x55_Reserved_31_21_OFFSET 21
-#define D0F0x64_x55_Reserved_31_21_WIDTH 11
-#define D0F0x64_x55_Reserved_31_21_MASK 0xffe00000
-
-/// D0F0x64_x55
-typedef union {
- struct { ///<
- UINT32 Reserved_19_0:20; ///<
- UINT32 SetPowEn:1 ; ///<
- UINT32 Reserved_31_21:11; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x64_x55_STRUCT;
-
-// **** D0F0x64_x57 Register Definition ****
-// Address
-#define D0F0x64_x57_ADDRESS 0x57
-
-// Type
-#define D0F0x64_x57_TYPE TYPE_D0F0x64
-// Field Data
-#define D0F0x64_x57_Reserved_19_0_OFFSET 0
-#define D0F0x64_x57_Reserved_19_0_WIDTH 20
-#define D0F0x64_x57_Reserved_19_0_MASK 0xfffff
-#define D0F0x64_x57_SetPowEn_OFFSET 20
-#define D0F0x64_x57_SetPowEn_WIDTH 1
-#define D0F0x64_x57_SetPowEn_MASK 0x100000
-#define D0F0x64_x57_Reserved_31_21_OFFSET 21
-#define D0F0x64_x57_Reserved_31_21_WIDTH 11
-#define D0F0x64_x57_Reserved_31_21_MASK 0xffe00000
-
-/// D0F0x64_x57
-typedef union {
- struct { ///<
- UINT32 Reserved_19_0:20; ///<
- UINT32 SetPowEn:1 ; ///<
- UINT32 Reserved_31_21:11; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x64_x57_STRUCT;
-
-// **** D0F0x64_x59 Register Definition ****
-// Address
-#define D0F0x64_x59_ADDRESS 0x59
-
-// Type
-#define D0F0x64_x59_TYPE TYPE_D0F0x64
-// Field Data
-#define D0F0x64_x59_Reserved_19_0_OFFSET 0
-#define D0F0x64_x59_Reserved_19_0_WIDTH 20
-#define D0F0x64_x59_Reserved_19_0_MASK 0xfffff
-#define D0F0x64_x59_SetPowEn_OFFSET 20
-#define D0F0x64_x59_SetPowEn_WIDTH 1
-#define D0F0x64_x59_SetPowEn_MASK 0x100000
-#define D0F0x64_x59_Reserved_31_21_OFFSET 21
-#define D0F0x64_x59_Reserved_31_21_WIDTH 11
-#define D0F0x64_x59_Reserved_31_21_MASK 0xffe00000
-
-/// D0F0x64_x59
-typedef union {
- struct { ///<
- UINT32 Reserved_19_0:20; ///<
- UINT32 SetPowEn:1 ; ///<
- UINT32 Reserved_31_21:11; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x64_x59_STRUCT;
-
-// **** D0F0x64_x5B Register Definition ****
-// Address
-#define D0F0x64_x5B_ADDRESS 0x5b
-
-// Type
-#define D0F0x64_x5B_TYPE TYPE_D0F0x64
-// Field Data
-#define D0F0x64_x5B_Reserved_19_0_OFFSET 0
-#define D0F0x64_x5B_Reserved_19_0_WIDTH 20
-#define D0F0x64_x5B_Reserved_19_0_MASK 0xfffff
-#define D0F0x64_x5B_SetPowEn_OFFSET 20
-#define D0F0x64_x5B_SetPowEn_WIDTH 1
-#define D0F0x64_x5B_SetPowEn_MASK 0x100000
-#define D0F0x64_x5B_Reserved_31_21_OFFSET 21
-#define D0F0x64_x5B_Reserved_31_21_WIDTH 11
-#define D0F0x64_x5B_Reserved_31_21_MASK 0xffe00000
-
-/// D0F0x64_x5B
-typedef union {
- struct { ///<
- UINT32 Reserved_19_0:20; ///<
- UINT32 SetPowEn:1 ; ///<
- UINT32 Reserved_31_21:11; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x64_x5B_STRUCT;
-
-// **** D0F0x64_x6A Register Definition ****
-// Address
-#define D0F0x64_x6A_ADDRESS 0x6a
-
-// Type
-#define D0F0x64_x6A_TYPE TYPE_D0F0x64
-// Field Data
-#define D0F0x64_x6A_VoltageForceEn_OFFSET 0
-#define D0F0x64_x6A_VoltageForceEn_WIDTH 1
-#define D0F0x64_x6A_VoltageForceEn_MASK 0x1
-#define D0F0x64_x6A_VoltageChangeEn_OFFSET 1
-#define D0F0x64_x6A_VoltageChangeEn_WIDTH 1
-#define D0F0x64_x6A_VoltageChangeEn_MASK 0x2
-#define D0F0x64_x6A_VoltageChangeReq_OFFSET 2
-#define D0F0x64_x6A_VoltageChangeReq_WIDTH 1
-#define D0F0x64_x6A_VoltageChangeReq_MASK 0x4
-#define D0F0x64_x6A_VoltageLevel_OFFSET 3
-#define D0F0x64_x6A_VoltageLevel_WIDTH 2
-#define D0F0x64_x6A_VoltageLevel_MASK 0x18
-#define D0F0x64_x6A_Reserved_31_5_OFFSET 5
-#define D0F0x64_x6A_Reserved_31_5_WIDTH 27
-#define D0F0x64_x6A_Reserved_31_5_MASK 0xffffffe0
-
-/// D0F0x64_x6A
-typedef union {
- struct { ///<
- UINT32 VoltageForceEn:1 ; ///<
- UINT32 VoltageChangeEn:1 ; ///<
- UINT32 VoltageChangeReq:1 ; ///<
- UINT32 VoltageLevel:2 ; ///<
- UINT32 Reserved_31_5:27; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x64_x6A_STRUCT;
-
-// **** D0F0x64_x6B Register Definition ****
-// Address
-#define D0F0x64_x6B_ADDRESS 0x6b
-
-// Type
-#define D0F0x64_x6B_TYPE TYPE_D0F0x64
-// Field Data
-#define D0F0x64_x6B_VoltageChangeAck_OFFSET 0
-#define D0F0x64_x6B_VoltageChangeAck_WIDTH 1
-#define D0F0x64_x6B_VoltageChangeAck_MASK 0x1
-#define D0F0x64_x6B_CurrentVoltageLevel_OFFSET 1
-#define D0F0x64_x6B_CurrentVoltageLevel_WIDTH 2
-#define D0F0x64_x6B_CurrentVoltageLevel_MASK 0x6
-#define D0F0x64_x6B_Reserved_31_3_OFFSET 3
-#define D0F0x64_x6B_Reserved_31_3_WIDTH 29
-#define D0F0x64_x6B_Reserved_31_3_MASK 0xfffffff8
-
-/// D0F0x64_x6B
-typedef union {
- struct { ///<
- UINT32 VoltageChangeAck:1 ; ///<
- UINT32 CurrentVoltageLevel:2 ; ///<
- UINT32 Reserved_31_3:29; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x64_x6B_STRUCT;
-
-// **** D0F0x98_x06 Register Definition ****
-// Address
-#define D0F0x98_x06_ADDRESS 0x6
-
-// Type
-#define D0F0x98_x06_TYPE TYPE_D0F0x98
-// Field Data
-#define D0F0x98_x06_Reserved_25_0_OFFSET 0
-#define D0F0x98_x06_Reserved_25_0_WIDTH 26
-#define D0F0x98_x06_Reserved_25_0_MASK 0x3ffffff
-#define D0F0x98_x06_UmiNpMemWrEn_OFFSET 26
-#define D0F0x98_x06_UmiNpMemWrEn_WIDTH 1
-#define D0F0x98_x06_UmiNpMemWrEn_MASK 0x4000000
-#define D0F0x98_x06_Reserved_31_27_OFFSET 27
-#define D0F0x98_x06_Reserved_31_27_WIDTH 5
-#define D0F0x98_x06_Reserved_31_27_MASK 0xf8000000
-
-/// D0F0x98_x06
-typedef union {
- struct { ///<
- UINT32 Reserved_25_0:26; ///<
- UINT32 UmiNpMemWrEn:1 ; ///<
- UINT32 Reserved_31_27:5 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x98_x06_STRUCT;
-
-// **** D0F0x98_x07 Register Definition ****
-// Address
-#define D0F0x98_x07_ADDRESS 0x7
-
-// Type
-#define D0F0x98_x07_TYPE TYPE_D0F0x98
-// Field Data
-#define D0F0x98_x07_IocBwOptEn_OFFSET 0
-#define D0F0x98_x07_IocBwOptEn_WIDTH 1
-#define D0F0x98_x07_IocBwOptEn_MASK 0x1
-#define D0F0x98_x07_Reserved_13_1_OFFSET 1
-#define D0F0x98_x07_Reserved_13_1_WIDTH 13
-#define D0F0x98_x07_Reserved_13_1_MASK 0x3ffe
-#define D0F0x98_x07_MSIHTIntConversionEn_OFFSET 14
-#define D0F0x98_x07_MSIHTIntConversionEn_WIDTH 1
-#define D0F0x98_x07_MSIHTIntConversionEn_MASK 0x4000
-#define D0F0x98_x07_DropZeroMaskWrEn_OFFSET 15
-#define D0F0x98_x07_DropZeroMaskWrEn_WIDTH 1
-#define D0F0x98_x07_DropZeroMaskWrEn_MASK 0x8000
-#define D0F0x98_x07_Reserved_31_16_OFFSET 16
-#define D0F0x98_x07_Reserved_31_16_WIDTH 16
-#define D0F0x98_x07_Reserved_31_16_MASK 0xffff0000
-
-/// D0F0x98_x07
-typedef union {
- struct { ///<
- UINT32 IocBwOptEn:1 ; ///<
- UINT32 Reserved_13_1:13; ///<
- UINT32 MSIHTIntConversionEn:1 ; ///<
- UINT32 DropZeroMaskWrEn:1 ; ///<
- UINT32 Reserved_31_16:16; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x98_x07_STRUCT;
-
-// **** D0F0x98_x08 Register Definition ****
-// Address
-#define D0F0x98_x08_ADDRESS 0x8
-
-// Type
-#define D0F0x98_x08_TYPE TYPE_D0F0x98
-// Field Data
-#define D0F0x98_x08_NpWrrLenA_OFFSET 0
-#define D0F0x98_x08_NpWrrLenA_WIDTH 8
-#define D0F0x98_x08_NpWrrLenA_MASK 0xff
-#define D0F0x98_x08_Reserved_15_8_OFFSET 8
-#define D0F0x98_x08_Reserved_15_8_WIDTH 8
-#define D0F0x98_x08_Reserved_15_8_MASK 0xff00
-#define D0F0x98_x08_NpWrrLenC_OFFSET 16
-#define D0F0x98_x08_NpWrrLenC_WIDTH 8
-#define D0F0x98_x08_NpWrrLenC_MASK 0xff0000
-#define D0F0x98_x08_Reserved_31_24_OFFSET 24
-#define D0F0x98_x08_Reserved_31_24_WIDTH 8
-#define D0F0x98_x08_Reserved_31_24_MASK 0xff000000
-
-/// D0F0x98_x08
-typedef union {
- struct { ///<
- UINT32 NpWrrLenA:8 ; ///<
- UINT32 Reserved_15_8:8 ; ///<
- UINT32 NpWrrLenC:8 ; ///<
- UINT32 Reserved_31_24:8 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x98_x08_STRUCT;
-
-// **** D0F0x98_x09 Register Definition ****
-// Address
-#define D0F0x98_x09_ADDRESS 0x9
-
-// Type
-#define D0F0x98_x09_TYPE TYPE_D0F0x98
-// Field Data
-#define D0F0x98_x09_PWrrLenA_OFFSET 0
-#define D0F0x98_x09_PWrrLenA_WIDTH 8
-#define D0F0x98_x09_PWrrLenA_MASK 0xff
-#define D0F0x98_x09_Reserved_23_8_OFFSET 8
-#define D0F0x98_x09_Reserved_23_8_WIDTH 16
-#define D0F0x98_x09_Reserved_23_8_MASK 0xffff00
-#define D0F0x98_x09_PWrrLenD_OFFSET 24
-#define D0F0x98_x09_PWrrLenD_WIDTH 8
-#define D0F0x98_x09_PWrrLenD_MASK 0xff000000
-
-/// D0F0x98_x09
-typedef union {
- struct { ///<
- UINT32 PWrrLenA:8 ; ///<
- UINT32 Reserved_23_8:16; ///<
- UINT32 PWrrLenD:8 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x98_x09_STRUCT;
-
-// **** D0F0x98_x0C Register Definition ****
-// Address
-#define D0F0x98_x0C_ADDRESS 0xc
-
-// Type
-#define D0F0x98_x0C_TYPE TYPE_D0F0x98
-// Field Data
-#define D0F0x98_x0C_GcmWrrLenA_OFFSET 0
-#define D0F0x98_x0C_GcmWrrLenA_WIDTH 8
-#define D0F0x98_x0C_GcmWrrLenA_MASK 0xff
-#define D0F0x98_x0C_GcmWrrLenB_OFFSET 8
-#define D0F0x98_x0C_GcmWrrLenB_WIDTH 8
-#define D0F0x98_x0C_GcmWrrLenB_MASK 0xff00
-#define D0F0x98_x0C_Reserved_29_16_OFFSET 16
-#define D0F0x98_x0C_Reserved_29_16_WIDTH 14
-#define D0F0x98_x0C_Reserved_29_16_MASK 0x3fff0000
-#define D0F0x98_x0C_StrictSelWinnerEn_OFFSET 30
-#define D0F0x98_x0C_StrictSelWinnerEn_WIDTH 1
-#define D0F0x98_x0C_StrictSelWinnerEn_MASK 0x40000000
-#define D0F0x98_x0C_Reserved_31_31_OFFSET 31
-#define D0F0x98_x0C_Reserved_31_31_WIDTH 1
-#define D0F0x98_x0C_Reserved_31_31_MASK 0x80000000
-
-/// D0F0x98_x0C
-typedef union {
- struct { ///<
- UINT32 GcmWrrLenA:8 ; ///<
- UINT32 GcmWrrLenB:8 ; ///<
- UINT32 Reserved_29_16:14; ///<
- UINT32 StrictSelWinnerEn:1 ; ///<
- UINT32 Reserved_31_31:1 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x98_x0C_STRUCT;
-
-// **** D0F0x98_x0E Register Definition ****
-// Address
-#define D0F0x98_x0E_ADDRESS 0xe
-
-// Type
-#define D0F0x98_x0E_TYPE TYPE_D0F0x98
-// Field Data
-#define D0F0x98_x0E_MsiHtRsvIntRemapEn_OFFSET 0
-#define D0F0x98_x0E_MsiHtRsvIntRemapEn_WIDTH 1
-#define D0F0x98_x0E_MsiHtRsvIntRemapEn_MASK 0x1
-#define D0F0x98_x0E_Reserved_1_1_OFFSET 1
-#define D0F0x98_x0E_Reserved_1_1_WIDTH 1
-#define D0F0x98_x0E_Reserved_1_1_MASK 0x2
-#define D0F0x98_x0E_MsiHtRsvIntMt_OFFSET 2
-#define D0F0x98_x0E_MsiHtRsvIntMt_WIDTH 3
-#define D0F0x98_x0E_MsiHtRsvIntMt_MASK 0x1c
-#define D0F0x98_x0E_MsiHtRsvIntRqEoi_OFFSET 5
-#define D0F0x98_x0E_MsiHtRsvIntRqEoi_WIDTH 1
-#define D0F0x98_x0E_MsiHtRsvIntRqEoi_MASK 0x20
-#define D0F0x98_x0E_MsiHtRsvIntDM_OFFSET 6
-#define D0F0x98_x0E_MsiHtRsvIntDM_WIDTH 1
-#define D0F0x98_x0E_MsiHtRsvIntDM_MASK 0x40
-#define D0F0x98_x0E_Reserved_7_7_OFFSET 7
-#define D0F0x98_x0E_Reserved_7_7_WIDTH 1
-#define D0F0x98_x0E_Reserved_7_7_MASK 0x80
-#define D0F0x98_x0E_MsiHtRsvIntDestination_OFFSET 8
-#define D0F0x98_x0E_MsiHtRsvIntDestination_WIDTH 8
-#define D0F0x98_x0E_MsiHtRsvIntDestination_MASK 0xff00
-#define D0F0x98_x0E_MsiHtRsvIntVector_OFFSET 16
-#define D0F0x98_x0E_MsiHtRsvIntVector_WIDTH 8
-#define D0F0x98_x0E_MsiHtRsvIntVector_MASK 0xff0000
-#define D0F0x98_x0E_Reserved_31_24_OFFSET 24
-#define D0F0x98_x0E_Reserved_31_24_WIDTH 8
-#define D0F0x98_x0E_Reserved_31_24_MASK 0xff000000
-
-/// D0F0x98_x0E
-typedef union {
- struct { ///<
- UINT32 MsiHtRsvIntRemapEn:1 ; ///<
- UINT32 Reserved_1_1:1 ; ///<
- UINT32 MsiHtRsvIntMt:3 ; ///<
- UINT32 MsiHtRsvIntRqEoi:1 ; ///<
- UINT32 MsiHtRsvIntDM:1 ; ///<
- UINT32 Reserved_7_7:1 ; ///<
- UINT32 MsiHtRsvIntDestination:8 ; ///<
- UINT32 MsiHtRsvIntVector:8 ; ///<
- UINT32 Reserved_31_24:8 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x98_x0E_STRUCT;
-
-// **** D0F0x98_x1E Register Definition ****
-// Address
-#define D0F0x98_x1E_ADDRESS 0x1e
-
-// Type
-#define D0F0x98_x1E_TYPE TYPE_D0F0x98
-// Field Data
-#define D0F0x98_x1E_Reserved_0_0_OFFSET 0
-#define D0F0x98_x1E_Reserved_0_0_WIDTH 1
-#define D0F0x98_x1E_Reserved_0_0_MASK 0x1
-#define D0F0x98_x1E_HiPriEn_OFFSET 1
-#define D0F0x98_x1E_HiPriEn_WIDTH 1
-#define D0F0x98_x1E_HiPriEn_MASK 0x2
-#define D0F0x98_x1E_Reserved_31_2_OFFSET 2
-#define D0F0x98_x1E_Reserved_31_2_WIDTH 30
-#define D0F0x98_x1E_Reserved_31_2_MASK 0xfffffffc
-
-/// D0F0x98_x1E
-typedef union {
- struct { ///<
- UINT32 Reserved_0_0:1 ; ///<
- UINT32 HiPriEn:1 ; ///<
- UINT32 Reserved_31_2:30; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x98_x1E_STRUCT;
-
-// **** D0F0x98_x28 Register Definition ****
-// Address
-#define D0F0x98_x28_ADDRESS 0x28
-
-// Type
-#define D0F0x98_x28_TYPE TYPE_D0F0x98
-// Field Data
-#define D0F0x98_x28_SmuPmInterfaceEn_OFFSET 0
-#define D0F0x98_x28_SmuPmInterfaceEn_WIDTH 1
-#define D0F0x98_x28_SmuPmInterfaceEn_MASK 0x1
-#define D0F0x98_x28_ForceCoherentIntr_OFFSET 1
-#define D0F0x98_x28_ForceCoherentIntr_WIDTH 1
-#define D0F0x98_x28_ForceCoherentIntr_MASK 0x2
-#define D0F0x98_x28_Reserved_31_2_OFFSET 2
-#define D0F0x98_x28_Reserved_31_2_WIDTH 30
-#define D0F0x98_x28_Reserved_31_2_MASK 0xfffffffc
-
-/// D0F0x98_x28
-typedef union {
- struct { ///<
- UINT32 SmuPmInterfaceEn:1 ; ///<
- UINT32 ForceCoherentIntr:1 ; ///<
- UINT32 Reserved_31_2:30; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x98_x28_STRUCT;
-
-// **** D0F0x98_x2C Register Definition ****
-// Address
-#define D0F0x98_x2C_ADDRESS 0x2c
-
-// Type
-#define D0F0x98_x2C_TYPE TYPE_D0F0x98
-// Field Data
-#define D0F0x98_x2C_Reserved_0_0_OFFSET 0
-#define D0F0x98_x2C_Reserved_0_0_WIDTH 1
-#define D0F0x98_x2C_Reserved_0_0_MASK 0x1
-#define D0F0x98_x2C_DynWakeEn_OFFSET 1
-#define D0F0x98_x2C_DynWakeEn_WIDTH 1
-#define D0F0x98_x2C_DynWakeEn_MASK 0x2
-#define D0F0x98_x2C_Reserved_15_2_OFFSET 2
-#define D0F0x98_x2C_Reserved_15_2_WIDTH 14
-#define D0F0x98_x2C_Reserved_15_2_MASK 0xfffc
-#define D0F0x98_x2C_WakeHysteresis_OFFSET 16
-#define D0F0x98_x2C_WakeHysteresis_WIDTH 16
-#define D0F0x98_x2C_WakeHysteresis_MASK 0xffff0000
-
-/// D0F0x98_x2C
-typedef union {
- struct { ///<
- UINT32 Reserved_0_0:1 ; ///<
- UINT32 DynWakeEn:1 ; ///<
- UINT32 Reserved_15_2:14; ///<
- UINT32 WakeHysteresis:16; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x98_x2C_STRUCT;
-
-// **** D0F0xE4_WRAP_0080 Register Definition ****
-// Address
-#define D0F0xE4_WRAP_0080_ADDRESS 0x80
-
-// Type
-#define D0F0xE4_WRAP_0080_TYPE TYPE_D0F0xE4
-// Field Data
-#define D0F0xE4_WRAP_0080_StrapBifLinkConfig_OFFSET 0
-#define D0F0xE4_WRAP_0080_StrapBifLinkConfig_WIDTH 4
-#define D0F0xE4_WRAP_0080_StrapBifLinkConfig_MASK 0xf
-#define D0F0xE4_WRAP_0080_Reserved_31_4_OFFSET 4
-#define D0F0xE4_WRAP_0080_Reserved_31_4_WIDTH 28
-#define D0F0xE4_WRAP_0080_Reserved_31_4_MASK 0xfffffff0
-
-/// D0F0xE4_WRAP_0080
-typedef union {
- struct { ///<
- UINT32 StrapBifLinkConfig:4 ; ///<
- UINT32 Reserved_31_4:28; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0xE4_WRAP_0080_STRUCT;
-
-// **** D0F0xE4_WRAP_0800 Register Definition ****
-// Address
-#define D0F0xE4_WRAP_0800_ADDRESS 0x800
-
-// Type
-#define D0F0xE4_WRAP_0800_TYPE TYPE_D0F0xE4
-// Field Data
-#define D0F0xE4_WRAP_0800_HoldTraining_OFFSET 0
-#define D0F0xE4_WRAP_0800_HoldTraining_WIDTH 1
-#define D0F0xE4_WRAP_0800_HoldTraining_MASK 0x1
-#define D0F0xE4_WRAP_0800_Reserved_31_1_OFFSET 1
-#define D0F0xE4_WRAP_0800_Reserved_31_1_WIDTH 31
-#define D0F0xE4_WRAP_0800_Reserved_31_1_MASK 0xfffffffe
-
-/// D0F0xE4_WRAP_0800
-typedef union {
- struct { ///<
- UINT32 HoldTraining:1 ; ///<
- UINT32 Reserved_31_1:31; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0xE4_WRAP_0800_STRUCT;
-
-// **** D0F0xE4_WRAP_0803 Register Definition ****
-// Address
-#define D0F0xE4_WRAP_0803_ADDRESS 0x803
-
-// Type
-#define D0F0xE4_WRAP_0803_TYPE TYPE_D0F0xE4
-// Field Data
-#define D0F0xE4_WRAP_0803_Reserved_4_0_OFFSET 0
-#define D0F0xE4_WRAP_0803_Reserved_4_0_WIDTH 5
-#define D0F0xE4_WRAP_0803_Reserved_4_0_MASK 0x1f
-#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_OFFSET 5
-#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_WIDTH 1
-#define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_MASK 0x20
-#define D0F0xE4_WRAP_0803_Reserved_31_6_OFFSET 6
-#define D0F0xE4_WRAP_0803_Reserved_31_6_WIDTH 26
-#define D0F0xE4_WRAP_0803_Reserved_31_6_MASK 0xffffffc0
-
-/// D0F0xE4_WRAP_0803
-typedef union {
- struct { ///<
- UINT32 Reserved_4_0:5 ; ///<
- UINT32 StrapBifDeemphasisSel:1 ; ///<
- UINT32 Reserved_31_6:26; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0xE4_WRAP_0803_STRUCT;
-
-// **** D0F0xE4_WRAP_0903 Register Definition ****
-// Address
-#define D0F0xE4_WRAP_0903_ADDRESS 0x903
-
-// Type
-#define D0F0xE4_WRAP_0903_TYPE TYPE_D0F0xE4
-// Field Data
-#define D0F0xE4_WRAP_0903_Reserved_4_0_OFFSET 0
-#define D0F0xE4_WRAP_0903_Reserved_4_0_WIDTH 5
-#define D0F0xE4_WRAP_0903_Reserved_4_0_MASK 0x1f
-#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_OFFSET 5
-#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_WIDTH 1
-#define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_MASK 0x20
-#define D0F0xE4_WRAP_0903_Reserved_31_6_OFFSET 6
-#define D0F0xE4_WRAP_0903_Reserved_31_6_WIDTH 26
-#define D0F0xE4_WRAP_0903_Reserved_31_6_MASK 0xffffffc0
-
-/// D0F0xE4_WRAP_0903
-typedef union {
- struct { ///<
- UINT32 Reserved_4_0:5 ; ///<
- UINT32 StrapBifDeemphasisSel:1 ; ///<
- UINT32 Reserved_31_6:26; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0xE4_WRAP_0903_STRUCT;
-
-// **** D0F0xE4_WRAP_8002 Register Definition ****
-// Address
-#define D0F0xE4_WRAP_8002_ADDRESS 0x8002
-
-// Type
-#define D0F0xE4_WRAP_8002_TYPE TYPE_D0F0xE4
-// Field Data
-#define D0F0xE4_WRAP_8002_SubsystemVendorID_OFFSET 0
-#define D0F0xE4_WRAP_8002_SubsystemVendorID_WIDTH 16
-#define D0F0xE4_WRAP_8002_SubsystemVendorID_MASK 0xffff
-#define D0F0xE4_WRAP_8002_SubsystemID_OFFSET 16
-#define D0F0xE4_WRAP_8002_SubsystemID_WIDTH 16
-#define D0F0xE4_WRAP_8002_SubsystemID_MASK 0xffff0000
-
-/// D0F0xE4_WRAP_8002
-typedef union {
- struct { ///<
- UINT32 SubsystemVendorID:16; ///<
- UINT32 SubsystemID:16; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0xE4_WRAP_8002_STRUCT;
-
-// **** D0F0xE4_WRAP_8021 Register Definition ****
-// Address
-#define D0F0xE4_WRAP_8021_ADDRESS 0x8021
-
-// Type
-#define D0F0xE4_WRAP_8021_TYPE TYPE_D0F0xE4
-// Field Data
-#define D0F0xE4_WRAP_8021_Lanes10_OFFSET 0
-#define D0F0xE4_WRAP_8021_Lanes10_WIDTH 4
-#define D0F0xE4_WRAP_8021_Lanes10_MASK 0xf
-#define D0F0xE4_WRAP_8021_Lanes32_OFFSET 4
-#define D0F0xE4_WRAP_8021_Lanes32_WIDTH 4
-#define D0F0xE4_WRAP_8021_Lanes32_MASK 0xf0
-#define D0F0xE4_WRAP_8021_Lanes54_OFFSET 8
-#define D0F0xE4_WRAP_8021_Lanes54_WIDTH 4
-#define D0F0xE4_WRAP_8021_Lanes54_MASK 0xf00
-#define D0F0xE4_WRAP_8021_Lanes76_OFFSET 12
-#define D0F0xE4_WRAP_8021_Lanes76_WIDTH 4
-#define D0F0xE4_WRAP_8021_Lanes76_MASK 0xf000
-#define D0F0xE4_WRAP_8021_Lanes98_OFFSET 16
-#define D0F0xE4_WRAP_8021_Lanes98_WIDTH 4
-#define D0F0xE4_WRAP_8021_Lanes98_MASK 0xf0000
-#define D0F0xE4_WRAP_8021_Lanes1110_OFFSET 20
-#define D0F0xE4_WRAP_8021_Lanes1110_WIDTH 4
-#define D0F0xE4_WRAP_8021_Lanes1110_MASK 0xf00000
-#define D0F0xE4_WRAP_8021_Lanes1312_OFFSET 24
-#define D0F0xE4_WRAP_8021_Lanes1312_WIDTH 4
-#define D0F0xE4_WRAP_8021_Lanes1312_MASK 0xf000000
-#define D0F0xE4_WRAP_8021_Lanes1514_OFFSET 28
-#define D0F0xE4_WRAP_8021_Lanes1514_WIDTH 4
-#define D0F0xE4_WRAP_8021_Lanes1514_MASK 0xf0000000
-
-/// D0F0xE4_WRAP_8021
-typedef union {
- struct { ///<
- UINT32 Lanes10:4 ; ///<
- UINT32 Lanes32:4 ; ///<
- UINT32 Lanes54:4 ; ///<
- UINT32 Lanes76:4 ; ///<
- UINT32 Lanes98:4 ; ///<
- UINT32 Lanes1110:4 ; ///<
- UINT32 Lanes1312:4 ; ///<
- UINT32 Lanes1514:4 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0xE4_WRAP_8021_STRUCT;
-
-// **** D0F0xE4_WRAP_8022 Register Definition ****
-// Address
-#define D0F0xE4_WRAP_8022_ADDRESS 0x8022
-
-// Type
-#define D0F0xE4_WRAP_8022_TYPE TYPE_D0F0xE4
-// Field Data
-#define D0F0xE4_WRAP_8022_Lanes10_OFFSET 0
-#define D0F0xE4_WRAP_8022_Lanes10_WIDTH 4
-#define D0F0xE4_WRAP_8022_Lanes10_MASK 0xf
-#define D0F0xE4_WRAP_8022_Lanes32_OFFSET 4
-#define D0F0xE4_WRAP_8022_Lanes32_WIDTH 4
-#define D0F0xE4_WRAP_8022_Lanes32_MASK 0xf0
-#define D0F0xE4_WRAP_8022_Lanes54_OFFSET 8
-#define D0F0xE4_WRAP_8022_Lanes54_WIDTH 4
-#define D0F0xE4_WRAP_8022_Lanes54_MASK 0xf00
-#define D0F0xE4_WRAP_8022_Lanes76_OFFSET 12
-#define D0F0xE4_WRAP_8022_Lanes76_WIDTH 4
-#define D0F0xE4_WRAP_8022_Lanes76_MASK 0xf000
-#define D0F0xE4_WRAP_8022_Lanes98_OFFSET 16
-#define D0F0xE4_WRAP_8022_Lanes98_WIDTH 4
-#define D0F0xE4_WRAP_8022_Lanes98_MASK 0xf0000
-#define D0F0xE4_WRAP_8022_Lanes1110_OFFSET 20
-#define D0F0xE4_WRAP_8022_Lanes1110_WIDTH 4
-#define D0F0xE4_WRAP_8022_Lanes1110_MASK 0xf00000
-#define D0F0xE4_WRAP_8022_Lanes1312_OFFSET 24
-#define D0F0xE4_WRAP_8022_Lanes1312_WIDTH 4
-#define D0F0xE4_WRAP_8022_Lanes1312_MASK 0xf000000
-#define D0F0xE4_WRAP_8022_Lanes1514_OFFSET 28
-#define D0F0xE4_WRAP_8022_Lanes1514_WIDTH 4
-#define D0F0xE4_WRAP_8022_Lanes1514_MASK 0xf0000000
-
-/// D0F0xE4_WRAP_8022
-typedef union {
- struct { ///<
- UINT32 Lanes10:4 ; ///<
- UINT32 Lanes32:4 ; ///<
- UINT32 Lanes54:4 ; ///<
- UINT32 Lanes76:4 ; ///<
- UINT32 Lanes98:4 ; ///<
- UINT32 Lanes1110:4 ; ///<
- UINT32 Lanes1312:4 ; ///<
- UINT32 Lanes1514:4 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0xE4_WRAP_8022_STRUCT;
-
-// **** D0F0xE4_WRAP_8023 Register Definition ****
-// Address
-#define D0F0xE4_WRAP_8023_ADDRESS 0x8023
-
-// Type
-#define D0F0xE4_WRAP_8023_TYPE TYPE_D0F0xE4
-// Field Data
-#define D0F0xE4_WRAP_8023_LaneEnable_OFFSET 0
-#define D0F0xE4_WRAP_8023_LaneEnable_WIDTH 16
-#define D0F0xE4_WRAP_8023_LaneEnable_MASK 0xffff
-#define D0F0xE4_WRAP_8023_Reserved_31_16_OFFSET 16
-#define D0F0xE4_WRAP_8023_Reserved_31_16_WIDTH 16
-#define D0F0xE4_WRAP_8023_Reserved_31_16_MASK 0xffff0000
-
-/// D0F0xE4_WRAP_8023
-typedef union {
- struct { ///<
- UINT32 LaneEnable:16; ///<
- UINT32 Reserved_31_16:16; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0xE4_WRAP_8023_STRUCT;
-
-// **** D0F0xE4_WRAP_8025 Register Definition ****
-// Address
-#define D0F0xE4_WRAP_8025_ADDRESS 0x8025
-
-// Type
-#define D0F0xE4_WRAP_8025_TYPE TYPE_D0F0xE4
-// Field Data
-#define D0F0xE4_WRAP_8025_LMTxPhyCmd0_OFFSET 0
-#define D0F0xE4_WRAP_8025_LMTxPhyCmd0_WIDTH 3
-#define D0F0xE4_WRAP_8025_LMTxPhyCmd0_MASK 0x7
-#define D0F0xE4_WRAP_8025_LMRxPhyCmd0_OFFSET 3
-#define D0F0xE4_WRAP_8025_LMRxPhyCmd0_WIDTH 2
-#define D0F0xE4_WRAP_8025_LMRxPhyCmd0_MASK 0x18
-#define D0F0xE4_WRAP_8025_LMLinkSpeed0_OFFSET 5
-#define D0F0xE4_WRAP_8025_LMLinkSpeed0_WIDTH 1
-#define D0F0xE4_WRAP_8025_LMLinkSpeed0_MASK 0x20
-#define D0F0xE4_WRAP_8025_Reserved_7_6_OFFSET 6
-#define D0F0xE4_WRAP_8025_Reserved_7_6_WIDTH 2
-#define D0F0xE4_WRAP_8025_Reserved_7_6_MASK 0xc0
-#define D0F0xE4_WRAP_8025_LMTxPhyCmd1_OFFSET 8
-#define D0F0xE4_WRAP_8025_LMTxPhyCmd1_WIDTH 3
-#define D0F0xE4_WRAP_8025_LMTxPhyCmd1_MASK 0x700
-#define D0F0xE4_WRAP_8025_LMRxPhyCmd1_OFFSET 11
-#define D0F0xE4_WRAP_8025_LMRxPhyCmd1_WIDTH 2
-#define D0F0xE4_WRAP_8025_LMRxPhyCmd1_MASK 0x1800
-#define D0F0xE4_WRAP_8025_LMLinkSpeed1_OFFSET 13
-#define D0F0xE4_WRAP_8025_LMLinkSpeed1_WIDTH 1
-#define D0F0xE4_WRAP_8025_LMLinkSpeed1_MASK 0x2000
-#define D0F0xE4_WRAP_8025_Reserved_15_14_OFFSET 14
-#define D0F0xE4_WRAP_8025_Reserved_15_14_WIDTH 2
-#define D0F0xE4_WRAP_8025_Reserved_15_14_MASK 0xc000
-#define D0F0xE4_WRAP_8025_LMTxPhyCmd2_OFFSET 16
-#define D0F0xE4_WRAP_8025_LMTxPhyCmd2_WIDTH 3
-#define D0F0xE4_WRAP_8025_LMTxPhyCmd2_MASK 0x70000
-#define D0F0xE4_WRAP_8025_LMRxPhyCmd2_OFFSET 19
-#define D0F0xE4_WRAP_8025_LMRxPhyCmd2_WIDTH 2
-#define D0F0xE4_WRAP_8025_LMRxPhyCmd2_MASK 0x180000
-#define D0F0xE4_WRAP_8025_LMLinkSpeed2_OFFSET 21
-#define D0F0xE4_WRAP_8025_LMLinkSpeed2_WIDTH 1
-#define D0F0xE4_WRAP_8025_LMLinkSpeed2_MASK 0x200000
-#define D0F0xE4_WRAP_8025_Reserved_23_22_OFFSET 22
-#define D0F0xE4_WRAP_8025_Reserved_23_22_WIDTH 2
-#define D0F0xE4_WRAP_8025_Reserved_23_22_MASK 0xc00000
-#define D0F0xE4_WRAP_8025_LMTxPhyCmd3_OFFSET 24
-#define D0F0xE4_WRAP_8025_LMTxPhyCmd3_WIDTH 3
-#define D0F0xE4_WRAP_8025_LMTxPhyCmd3_MASK 0x7000000
-#define D0F0xE4_WRAP_8025_LMRxPhyCmd3_OFFSET 27
-#define D0F0xE4_WRAP_8025_LMRxPhyCmd3_WIDTH 2
-#define D0F0xE4_WRAP_8025_LMRxPhyCmd3_MASK 0x18000000
-#define D0F0xE4_WRAP_8025_LMLinkSpeed3_OFFSET 29
-#define D0F0xE4_WRAP_8025_LMLinkSpeed3_WIDTH 1
-#define D0F0xE4_WRAP_8025_LMLinkSpeed3_MASK 0x20000000
-#define D0F0xE4_WRAP_8025_Reserved_31_30_OFFSET 30
-#define D0F0xE4_WRAP_8025_Reserved_31_30_WIDTH 2
-#define D0F0xE4_WRAP_8025_Reserved_31_30_MASK 0xc0000000
-
-/// D0F0xE4_WRAP_8025
-typedef union {
- struct { ///<
- UINT32 LMTxPhyCmd0:3 ; ///<
- UINT32 LMRxPhyCmd0:2 ; ///<
- UINT32 LMLinkSpeed0:1 ; ///<
- UINT32 Reserved_7_6:2 ; ///<
- UINT32 LMTxPhyCmd1:3 ; ///<
- UINT32 LMRxPhyCmd1:2 ; ///<
- UINT32 LMLinkSpeed1:1 ; ///<
- UINT32 Reserved_15_14:2 ; ///<
- UINT32 LMTxPhyCmd2:3 ; ///<
- UINT32 LMRxPhyCmd2:2 ; ///<
- UINT32 LMLinkSpeed2:1 ; ///<
- UINT32 Reserved_23_22:2 ; ///<
- UINT32 LMTxPhyCmd3:3 ; ///<
- UINT32 LMRxPhyCmd3:2 ; ///<
- UINT32 LMLinkSpeed3:1 ; ///<
- UINT32 Reserved_31_30:2 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0xE4_WRAP_8025_STRUCT;
-
-// **** D0F0xE4_WRAP_8031 Register Definition ****
-// Address
-#define D0F0xE4_WRAP_8031_ADDRESS 0x8031
-
-// Type
-#define D0F0xE4_WRAP_8031_TYPE TYPE_D0F0xE4
-// Field Data
-#define D0F0xE4_WRAP_8031_LnCntBandwidth_OFFSET 0
-#define D0F0xE4_WRAP_8031_LnCntBandwidth_WIDTH 10
-#define D0F0xE4_WRAP_8031_LnCntBandwidth_MASK 0x3ff
-#define D0F0xE4_WRAP_8031_Reserved_15_10_OFFSET 10
-#define D0F0xE4_WRAP_8031_Reserved_15_10_WIDTH 6
-#define D0F0xE4_WRAP_8031_Reserved_15_10_MASK 0xfc00
-#define D0F0xE4_WRAP_8031_LnCntValid_OFFSET 16
-#define D0F0xE4_WRAP_8031_LnCntValid_WIDTH 1
-#define D0F0xE4_WRAP_8031_LnCntValid_MASK 0x10000
-#define D0F0xE4_WRAP_8031_Reserved_31_17_OFFSET 17
-#define D0F0xE4_WRAP_8031_Reserved_31_17_WIDTH 15
-#define D0F0xE4_WRAP_8031_Reserved_31_17_MASK 0xfffe0000
-
-/// D0F0xE4_WRAP_8031
-typedef union {
- struct { ///<
- UINT32 LnCntBandwidth:10; ///<
- UINT32 Reserved_15_10:6 ; ///<
- UINT32 LnCntValid:1 ; ///<
- UINT32 Reserved_31_17:15; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0xE4_WRAP_8031_STRUCT;
-
-// **** D0F0xE4_WRAP_8060 Register Definition ****
-// Address
-#define D0F0xE4_WRAP_8060_ADDRESS 0x8060
-
-// Type
-#define D0F0xE4_WRAP_8060_TYPE TYPE_D0F0xE4
-// Field Data
-#define D0F0xE4_WRAP_8060_Reconfigure_OFFSET 0
-#define D0F0xE4_WRAP_8060_Reconfigure_WIDTH 1
-#define D0F0xE4_WRAP_8060_Reconfigure_MASK 0x1
-#define D0F0xE4_WRAP_8060_Reserved_1_1_OFFSET 1
-#define D0F0xE4_WRAP_8060_Reserved_1_1_WIDTH 1
-#define D0F0xE4_WRAP_8060_Reserved_1_1_MASK 0x2
-#define D0F0xE4_WRAP_8060_ResetComplete_OFFSET 2
-#define D0F0xE4_WRAP_8060_ResetComplete_WIDTH 1
-#define D0F0xE4_WRAP_8060_ResetComplete_MASK 0x4
-#define D0F0xE4_WRAP_8060_Reserved_31_3_OFFSET 3
-#define D0F0xE4_WRAP_8060_Reserved_31_3_WIDTH 29
-#define D0F0xE4_WRAP_8060_Reserved_31_3_MASK 0xfffffff8
-
-/// D0F0xE4_WRAP_8060
-typedef union {
- struct { ///<
- UINT32 Reconfigure:1 ; ///<
- UINT32 Reserved_1_1:1 ; ///<
- UINT32 ResetComplete:1 ; ///<
- UINT32 Reserved_31_3:29; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0xE4_WRAP_8060_STRUCT;
-
-// **** D0F0xE4_WRAP_8061 Register Definition ****
-// Address
-#define D0F0xE4_WRAP_8061_ADDRESS 0x8061
-
-// Type
-#define D0F0xE4_WRAP_8061_TYPE TYPE_D0F0xE4
-// Field Data
-#define D0F0xE4_WRAP_8061_Reserved_14_0_OFFSET 0
-#define D0F0xE4_WRAP_8061_Reserved_14_0_WIDTH 15
-#define D0F0xE4_WRAP_8061_Reserved_14_0_MASK 0x7fff
-#define D0F0xE4_WRAP_8061_ResetCpm_OFFSET 15
-#define D0F0xE4_WRAP_8061_ResetCpm_WIDTH 1
-#define D0F0xE4_WRAP_8061_ResetCpm_MASK 0x8000
-#define D0F0xE4_WRAP_8061_ResetPif0_OFFSET 16
-#define D0F0xE4_WRAP_8061_ResetPif0_WIDTH 1
-#define D0F0xE4_WRAP_8061_ResetPif0_MASK 0x10000
-#define D0F0xE4_WRAP_8061_Reserved_23_17_OFFSET 17
-#define D0F0xE4_WRAP_8061_Reserved_23_17_WIDTH 7
-#define D0F0xE4_WRAP_8061_Reserved_23_17_MASK 0xfe0000
-#define D0F0xE4_WRAP_8061_ResetPhy0_OFFSET 24
-#define D0F0xE4_WRAP_8061_ResetPhy0_WIDTH 1
-#define D0F0xE4_WRAP_8061_ResetPhy0_MASK 0x1000000
-#define D0F0xE4_WRAP_8061_Reserved_31_25_OFFSET 25
-#define D0F0xE4_WRAP_8061_Reserved_31_25_WIDTH 7
-#define D0F0xE4_WRAP_8061_Reserved_31_25_MASK 0xfe000000
-
-/// D0F0xE4_WRAP_8061
-typedef union {
- struct { ///<
- UINT32 Reserved_14_0:15; ///<
- UINT32 ResetCpm:1 ; ///<
- UINT32 ResetPif0:1 ; ///<
- UINT32 Reserved_23_17:7 ; ///<
- UINT32 ResetPhy0:1 ; ///<
- UINT32 Reserved_31_25:7 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0xE4_WRAP_8061_STRUCT;
-
-// **** D0F0xE4_WRAP_8062 Register Definition ****
-// Address
-#define D0F0xE4_WRAP_8062_ADDRESS 0x8062
-
-// Type
-#define D0F0xE4_WRAP_8062_TYPE TYPE_D0F0xE4
-// Field Data
-#define D0F0xE4_WRAP_8062_ReconfigureEn_OFFSET 0
-#define D0F0xE4_WRAP_8062_ReconfigureEn_WIDTH 1
-#define D0F0xE4_WRAP_8062_ReconfigureEn_MASK 0x1
-#define D0F0xE4_WRAP_8062_Reserved_1_1_OFFSET 1
-#define D0F0xE4_WRAP_8062_Reserved_1_1_WIDTH 1
-#define D0F0xE4_WRAP_8062_Reserved_1_1_MASK 0x2
-#define D0F0xE4_WRAP_8062_ResetPeriod_OFFSET 2
-#define D0F0xE4_WRAP_8062_ResetPeriod_WIDTH 3
-#define D0F0xE4_WRAP_8062_ResetPeriod_MASK 0x1c
-#define D0F0xE4_WRAP_8062_Reserved_9_5_OFFSET 5
-#define D0F0xE4_WRAP_8062_Reserved_9_5_WIDTH 5
-#define D0F0xE4_WRAP_8062_Reserved_9_5_MASK 0x3e0
-#define D0F0xE4_WRAP_8062_BlockOnIdle_OFFSET 10
-#define D0F0xE4_WRAP_8062_BlockOnIdle_WIDTH 1
-#define D0F0xE4_WRAP_8062_BlockOnIdle_MASK 0x400
-#define D0F0xE4_WRAP_8062_ConfigXferMode_OFFSET 11
-#define D0F0xE4_WRAP_8062_ConfigXferMode_WIDTH 1
-#define D0F0xE4_WRAP_8062_ConfigXferMode_MASK 0x800
-#define D0F0xE4_WRAP_8062_Reserved_31_12_OFFSET 12
-#define D0F0xE4_WRAP_8062_Reserved_31_12_WIDTH 20
-#define D0F0xE4_WRAP_8062_Reserved_31_12_MASK 0xfffff000
-
-/// D0F0xE4_WRAP_8062
-typedef union {
- struct { ///<
- UINT32 ReconfigureEn:1 ; ///<
- UINT32 Reserved_1_1:1 ; ///<
- UINT32 ResetPeriod:3 ; ///<
- UINT32 Reserved_9_5:5 ; ///<
- UINT32 BlockOnIdle:1 ; ///<
- UINT32 ConfigXferMode:1 ; ///<
- UINT32 Reserved_31_12:20; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0xE4_WRAP_8062_STRUCT;
-
-// **** D0F0xE4_x0108_8071 Register Definition ****
-// Address
-#define D0F0xE4_x0108_8071_ADDRESS 0x1088071
-
-// Type
-#define D0F0xE4_x0108_8071_TYPE TYPE_D0F0xE4
-// Field Data
-#define D0F0xE4_x0108_8071_RxAdjust_OFFSET 0
-#define D0F0xE4_x0108_8071_RxAdjust_WIDTH 3
-#define D0F0xE4_x0108_8071_RxAdjust_MASK 0x7
-#define D0F0xE4_x0108_8071_Reserved_31_3_OFFSET 3
-#define D0F0xE4_x0108_8071_Reserved_31_3_WIDTH 29
-#define D0F0xE4_x0108_8071_Reserved_31_3_MASK 0xfffffff8
-
-/// D0F0xE4_x0108_8071
-typedef union {
- struct { ///<
- UINT32 RxAdjust:3 ; ///<
- UINT32 Reserved_31_3:29; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0xE4_x0108_8071_STRUCT;
-
-// **** D0F0xE4_x0108_8072 Register Definition ****
-// Address
-#define D0F0xE4_x0108_8072_ADDRESS 0x1088072
-
-// Type
-#define D0F0xE4_x0108_8072_TYPE TYPE_D0F0xE4
-// Field Data
-#define D0F0xE4_x0108_8072_TxAdjust_OFFSET 0
-#define D0F0xE4_x0108_8072_TxAdjust_WIDTH 3
-#define D0F0xE4_x0108_8072_TxAdjust_MASK 0x7
-#define D0F0xE4_x0108_8072_Reserved_31_3_OFFSET 3
-#define D0F0xE4_x0108_8072_Reserved_31_3_WIDTH 29
-#define D0F0xE4_x0108_8072_Reserved_31_3_MASK 0xfffffff8
-
-/// D0F0xE4_x0108_8072
-typedef union {
- struct { ///<
- UINT32 TxAdjust:3 ; ///<
- UINT32 Reserved_31_3:29; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0xE4_x0108_8072_STRUCT;
-
-// **** D0F0xE4_PIF_0010 Register Definition ****
-// Address
-#define D0F0xE4_PIF_0010_ADDRESS 0x10
-
-// Type
-#define D0F0xE4_PIF_0010_TYPE TYPE_D0F0xE4
-// Field Data
-#define D0F0xE4_PIF_0010_Reserved_3_0_OFFSET 0
-#define D0F0xE4_PIF_0010_Reserved_3_0_WIDTH 4
-#define D0F0xE4_PIF_0010_Reserved_3_0_MASK 0xf
-#define D0F0xE4_PIF_0010_EiDetCycleMode_OFFSET 4
-#define D0F0xE4_PIF_0010_EiDetCycleMode_WIDTH 1
-#define D0F0xE4_PIF_0010_EiDetCycleMode_MASK 0x10
-#define D0F0xE4_PIF_0010_Reserved_5_5_OFFSET 5
-#define D0F0xE4_PIF_0010_Reserved_5_5_WIDTH 1
-#define D0F0xE4_PIF_0010_Reserved_5_5_MASK 0x20
-#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_OFFSET 6
-#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_WIDTH 1
-#define D0F0xE4_PIF_0010_RxDetectFifoResetMode_MASK 0x40
-#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_OFFSET 7
-#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_WIDTH 1
-#define D0F0xE4_PIF_0010_RxDetectTxPwrMode_MASK 0x80
-#define D0F0xE4_PIF_0010_Reserved_16_8_OFFSET 8
-#define D0F0xE4_PIF_0010_Reserved_16_8_WIDTH 9
-#define D0F0xE4_PIF_0010_Reserved_16_8_MASK 0x1ff00
-#define D0F0xE4_PIF_0010_Ls2ExitTime_OFFSET 17
-#define D0F0xE4_PIF_0010_Ls2ExitTime_WIDTH 3
-#define D0F0xE4_PIF_0010_Ls2ExitTime_MASK 0xe0000
-#define D0F0xE4_PIF_0010_EiCycleOffTime_OFFSET 20
-#define D0F0xE4_PIF_0010_EiCycleOffTime_WIDTH 3
-#define D0F0xE4_PIF_0010_EiCycleOffTime_MASK 0x700000
-#define D0F0xE4_PIF_0010_Reserved_31_23_OFFSET 23
-#define D0F0xE4_PIF_0010_Reserved_31_23_WIDTH 9
-#define D0F0xE4_PIF_0010_Reserved_31_23_MASK 0xff800000
-
-/// D0F0xE4_PIF_0010
-typedef union {
- struct { ///<
- UINT32 Reserved_3_0:4 ; ///<
- UINT32 EiDetCycleMode:1 ; ///<
- UINT32 Reserved_5_5:1 ; ///<
- UINT32 RxDetectFifoResetMode:1 ; ///<
- UINT32 RxDetectTxPwrMode:1 ; ///<
- UINT32 Reserved_16_8:9 ; ///<
- UINT32 Ls2ExitTime:3 ; ///<
- UINT32 EiCycleOffTime:3 ; ///<
- UINT32 Reserved_31_23:9 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0xE4_PIF_0010_STRUCT;
-
-// **** D0F0xE4_PIF_0011 Register Definition ****
-// Address
-#define D0F0xE4_PIF_0011_ADDRESS 0x11
-
-// Type
-#define D0F0xE4_PIF_0011_TYPE TYPE_D0F0xE4
-// Field Data
-#define D0F0xE4_PIF_0011_X2Lane10_OFFSET 0
-#define D0F0xE4_PIF_0011_X2Lane10_WIDTH 1
-#define D0F0xE4_PIF_0011_X2Lane10_MASK 0x1
-#define D0F0xE4_PIF_0011_X2Lane32_OFFSET 1
-#define D0F0xE4_PIF_0011_X2Lane32_WIDTH 1
-#define D0F0xE4_PIF_0011_X2Lane32_MASK 0x2
-#define D0F0xE4_PIF_0011_X2Lane54_OFFSET 2
-#define D0F0xE4_PIF_0011_X2Lane54_WIDTH 1
-#define D0F0xE4_PIF_0011_X2Lane54_MASK 0x4
-#define D0F0xE4_PIF_0011_X2Lane76_OFFSET 3
-#define D0F0xE4_PIF_0011_X2Lane76_WIDTH 1
-#define D0F0xE4_PIF_0011_X2Lane76_MASK 0x8
-#define D0F0xE4_PIF_0011_Reserved_7_4_OFFSET 4
-#define D0F0xE4_PIF_0011_Reserved_7_4_WIDTH 4
-#define D0F0xE4_PIF_0011_Reserved_7_4_MASK 0xf0
-#define D0F0xE4_PIF_0011_X4Lane30_OFFSET 8
-#define D0F0xE4_PIF_0011_X4Lane30_WIDTH 1
-#define D0F0xE4_PIF_0011_X4Lane30_MASK 0x100
-#define D0F0xE4_PIF_0011_X4Lane74_OFFSET 9
-#define D0F0xE4_PIF_0011_X4Lane74_WIDTH 1
-#define D0F0xE4_PIF_0011_X4Lane74_MASK 0x200
-#define D0F0xE4_PIF_0011_Reserved_11_10_OFFSET 10
-#define D0F0xE4_PIF_0011_Reserved_11_10_WIDTH 2
-#define D0F0xE4_PIF_0011_Reserved_11_10_MASK 0xc00
-#define D0F0xE4_PIF_0011_X4Lane52_OFFSET 12
-#define D0F0xE4_PIF_0011_X4Lane52_WIDTH 1
-#define D0F0xE4_PIF_0011_X4Lane52_MASK 0x1000
-#define D0F0xE4_PIF_0011_Reserved_15_13_OFFSET 13
-#define D0F0xE4_PIF_0011_Reserved_15_13_WIDTH 3
-#define D0F0xE4_PIF_0011_Reserved_15_13_MASK 0xe000
-#define D0F0xE4_PIF_0011_X8Lane70_OFFSET 16
-#define D0F0xE4_PIF_0011_X8Lane70_WIDTH 1
-#define D0F0xE4_PIF_0011_X8Lane70_MASK 0x10000
-#define D0F0xE4_PIF_0011_Reserved_24_17_OFFSET 17
-#define D0F0xE4_PIF_0011_Reserved_24_17_WIDTH 8
-#define D0F0xE4_PIF_0011_Reserved_24_17_MASK 0x1fe0000
-#define D0F0xE4_PIF_0011_MultiPif_OFFSET 25
-#define D0F0xE4_PIF_0011_MultiPif_WIDTH 1
-#define D0F0xE4_PIF_0011_MultiPif_MASK 0x2000000
-#define D0F0xE4_PIF_0011_Reserved_31_26_OFFSET 26
-#define D0F0xE4_PIF_0011_Reserved_31_26_WIDTH 6
-#define D0F0xE4_PIF_0011_Reserved_31_26_MASK 0xfc000000
-
-/// D0F0xE4_PIF_0011
-typedef union {
- struct { ///<
- UINT32 X2Lane10:1 ; ///<
- UINT32 X2Lane32:1 ; ///<
- UINT32 X2Lane54:1 ; ///<
- UINT32 X2Lane76:1 ; ///<
- UINT32 Reserved_7_4:4 ; ///<
- UINT32 X4Lane30:1 ; ///<
- UINT32 X4Lane74:1 ; ///<
- UINT32 Reserved_11_10:2 ; ///<
- UINT32 X4Lane52:1 ; ///<
- UINT32 Reserved_15_13:3 ; ///<
- UINT32 X8Lane70:1 ; ///<
- UINT32 Reserved_24_17:8 ; ///<
- UINT32 MultiPif:1 ; ///<
- UINT32 Reserved_31_26:6 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0xE4_PIF_0011_STRUCT;
-
-// **** D0F0xE4_PIF_0012 Register Definition ****
-// Address
-#define D0F0xE4_PIF_0012_ADDRESS 0x12
-
-// Type
-#define D0F0xE4_PIF_0012_TYPE TYPE_D0F0xE4
-// Field Data
-#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_OFFSET 0
-#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_WIDTH 3
-#define D0F0xE4_PIF_0012_TxPowerStateInTxs2_MASK 0x7
-#define D0F0xE4_PIF_0012_ForceRxEnInL0s_OFFSET 3
-#define D0F0xE4_PIF_0012_ForceRxEnInL0s_WIDTH 1
-#define D0F0xE4_PIF_0012_ForceRxEnInL0s_MASK 0x8
-#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_OFFSET 4
-#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_WIDTH 3
-#define D0F0xE4_PIF_0012_RxPowerStateInRxs2_MASK 0x70
-#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_OFFSET 7
-#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_WIDTH 3
-#define D0F0xE4_PIF_0012_PllPowerStateInTxs2_MASK 0x380
-#define D0F0xE4_PIF_0012_PllPowerStateInOff_OFFSET 10
-#define D0F0xE4_PIF_0012_PllPowerStateInOff_WIDTH 3
-#define D0F0xE4_PIF_0012_PllPowerStateInOff_MASK 0x1c00
-#define D0F0xE4_PIF_0012_Reserved_15_13_OFFSET 13
-#define D0F0xE4_PIF_0012_Reserved_15_13_WIDTH 3
-#define D0F0xE4_PIF_0012_Reserved_15_13_MASK 0xe000
-#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_OFFSET 16
-#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_WIDTH 1
-#define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_MASK 0x10000
-#define D0F0xE4_PIF_0012_Reserved_23_17_OFFSET 17
-#define D0F0xE4_PIF_0012_Reserved_23_17_WIDTH 7
-#define D0F0xE4_PIF_0012_Reserved_23_17_MASK 0xfe0000
-#define D0F0xE4_PIF_0012_PllRampUpTime_OFFSET 24
-#define D0F0xE4_PIF_0012_PllRampUpTime_WIDTH 3
-#define D0F0xE4_PIF_0012_PllRampUpTime_MASK 0x7000000
-#define D0F0xE4_PIF_0012_Reserved_27_27_OFFSET 27
-#define D0F0xE4_PIF_0012_Reserved_27_27_WIDTH 1
-#define D0F0xE4_PIF_0012_Reserved_27_27_MASK 0x8000000
-#define D0F0xE4_PIF_0012_PllPwrOverrideEn_OFFSET 28
-#define D0F0xE4_PIF_0012_PllPwrOverrideEn_WIDTH 1
-#define D0F0xE4_PIF_0012_PllPwrOverrideEn_MASK 0x10000000
-#define D0F0xE4_PIF_0012_PllPwrOverrideVal_OFFSET 29
-#define D0F0xE4_PIF_0012_PllPwrOverrideVal_WIDTH 3
-#define D0F0xE4_PIF_0012_PllPwrOverrideVal_MASK 0xe0000000
-
-/// D0F0xE4_PIF_0012
-typedef union {
- struct { ///<
- UINT32 TxPowerStateInTxs2:3 ; ///<
- UINT32 ForceRxEnInL0s:1 ; ///<
- UINT32 RxPowerStateInRxs2:3 ; ///<
- UINT32 PllPowerStateInTxs2:3 ; ///<
- UINT32 PllPowerStateInOff:3 ; ///<
- UINT32 Reserved_15_13:3 ; ///<
- UINT32 Tx2p5clkClockGatingEn:1 ; ///<
- UINT32 Reserved_23_17:7 ; ///<
- UINT32 PllRampUpTime:3 ; ///<
- UINT32 Reserved_27_27:1 ; ///<
- UINT32 PllPwrOverrideEn:1 ; ///<
- UINT32 PllPwrOverrideVal:3 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0xE4_PIF_0012_STRUCT;
-
-// **** D0F0xE4_PIF_0013 Register Definition ****
-// Address
-#define D0F0xE4_PIF_0013_ADDRESS 0x13
-
-// Type
-#define D0F0xE4_PIF_0013_TYPE TYPE_D0F0xE4
-// Field Data
-#define D0F0xE4_PIF_0013_TxPowerStateInTxs2_OFFSET 0
-#define D0F0xE4_PIF_0013_TxPowerStateInTxs2_WIDTH 3
-#define D0F0xE4_PIF_0013_TxPowerStateInTxs2_MASK 0x7
-#define D0F0xE4_PIF_0013_ForceRxEnInL0s_OFFSET 3
-#define D0F0xE4_PIF_0013_ForceRxEnInL0s_WIDTH 1
-#define D0F0xE4_PIF_0013_ForceRxEnInL0s_MASK 0x8
-#define D0F0xE4_PIF_0013_RxPowerStateInRxs2_OFFSET 4
-#define D0F0xE4_PIF_0013_RxPowerStateInRxs2_WIDTH 3
-#define D0F0xE4_PIF_0013_RxPowerStateInRxs2_MASK 0x70
-#define D0F0xE4_PIF_0013_PllPowerStateInTxs2_OFFSET 7
-#define D0F0xE4_PIF_0013_PllPowerStateInTxs2_WIDTH 3
-#define D0F0xE4_PIF_0013_PllPowerStateInTxs2_MASK 0x380
-#define D0F0xE4_PIF_0013_PllPowerStateInOff_OFFSET 10
-#define D0F0xE4_PIF_0013_PllPowerStateInOff_WIDTH 3
-#define D0F0xE4_PIF_0013_PllPowerStateInOff_MASK 0x1c00
-#define D0F0xE4_PIF_0013_Reserved_15_13_OFFSET 13
-#define D0F0xE4_PIF_0013_Reserved_15_13_WIDTH 3
-#define D0F0xE4_PIF_0013_Reserved_15_13_MASK 0xe000
-#define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_OFFSET 16
-#define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_WIDTH 1
-#define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_MASK 0x10000
-#define D0F0xE4_PIF_0013_Reserved_23_17_OFFSET 17
-#define D0F0xE4_PIF_0013_Reserved_23_17_WIDTH 7
-#define D0F0xE4_PIF_0013_Reserved_23_17_MASK 0xfe0000
-#define D0F0xE4_PIF_0013_PllRampUpTime_OFFSET 24
-#define D0F0xE4_PIF_0013_PllRampUpTime_WIDTH 3
-#define D0F0xE4_PIF_0013_PllRampUpTime_MASK 0x7000000
-#define D0F0xE4_PIF_0013_Reserved_27_27_OFFSET 27
-#define D0F0xE4_PIF_0013_Reserved_27_27_WIDTH 1
-#define D0F0xE4_PIF_0013_Reserved_27_27_MASK 0x8000000
-#define D0F0xE4_PIF_0013_PllPwrOverrideEn_OFFSET 28
-#define D0F0xE4_PIF_0013_PllPwrOverrideEn_WIDTH 1
-#define D0F0xE4_PIF_0013_PllPwrOverrideEn_MASK 0x10000000
-#define D0F0xE4_PIF_0013_PllPwrOverrideVal_OFFSET 29
-#define D0F0xE4_PIF_0013_PllPwrOverrideVal_WIDTH 3
-#define D0F0xE4_PIF_0013_PllPwrOverrideVal_MASK 0xe0000000
-
-/// D0F0xE4_PIF_0013
-typedef union {
- struct { ///<
- UINT32 TxPowerStateInTxs2:3 ; ///<
- UINT32 ForceRxEnInL0s:1 ; ///<
- UINT32 RxPowerStateInRxs2:3 ; ///<
- UINT32 PllPowerStateInTxs2:3 ; ///<
- UINT32 PllPowerStateInOff:3 ; ///<
- UINT32 Reserved_15_13:3 ; ///<
- UINT32 Tx2p5clkClockGatingEn:1 ; ///<
- UINT32 Reserved_23_17:7 ; ///<
- UINT32 PllRampUpTime:3 ; ///<
- UINT32 Reserved_27_27:1 ; ///<
- UINT32 PllPwrOverrideEn:1 ; ///<
- UINT32 PllPwrOverrideVal:3 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0xE4_PIF_0013_STRUCT;
-
-// **** D0F0xE4_PIF_0015 Register Definition ****
-// Address
-#define D0F0xE4_PIF_0015_ADDRESS 0x15
-
-// Type
-#define D0F0xE4_PIF_0015_TYPE TYPE_D0F0xE4
-// Field Data
-#define D0F0xE4_PIF_0015_TxPhyStatus00_OFFSET 0
-#define D0F0xE4_PIF_0015_TxPhyStatus00_WIDTH 1
-#define D0F0xE4_PIF_0015_TxPhyStatus00_MASK 0x1
-#define D0F0xE4_PIF_0015_TxPhyStatus01_OFFSET 1
-#define D0F0xE4_PIF_0015_TxPhyStatus01_WIDTH 1
-#define D0F0xE4_PIF_0015_TxPhyStatus01_MASK 0x2
-#define D0F0xE4_PIF_0015_TxPhyStatus02_OFFSET 2
-#define D0F0xE4_PIF_0015_TxPhyStatus02_WIDTH 1
-#define D0F0xE4_PIF_0015_TxPhyStatus02_MASK 0x4
-#define D0F0xE4_PIF_0015_TxPhyStatus03_OFFSET 3
-#define D0F0xE4_PIF_0015_TxPhyStatus03_WIDTH 1
-#define D0F0xE4_PIF_0015_TxPhyStatus03_MASK 0x8
-#define D0F0xE4_PIF_0015_TxPhyStatus04_OFFSET 4
-#define D0F0xE4_PIF_0015_TxPhyStatus04_WIDTH 1
-#define D0F0xE4_PIF_0015_TxPhyStatus04_MASK 0x10
-#define D0F0xE4_PIF_0015_TxPhyStatus05_OFFSET 5
-#define D0F0xE4_PIF_0015_TxPhyStatus05_WIDTH 1
-#define D0F0xE4_PIF_0015_TxPhyStatus05_MASK 0x20
-#define D0F0xE4_PIF_0015_TxPhyStatus06_OFFSET 6
-#define D0F0xE4_PIF_0015_TxPhyStatus06_WIDTH 1
-#define D0F0xE4_PIF_0015_TxPhyStatus06_MASK 0x40
-#define D0F0xE4_PIF_0015_TxPhyStatus07_OFFSET 7
-#define D0F0xE4_PIF_0015_TxPhyStatus07_WIDTH 1
-#define D0F0xE4_PIF_0015_TxPhyStatus07_MASK 0x80
-#define D0F0xE4_PIF_0015_Reserved_31_8_OFFSET 8
-#define D0F0xE4_PIF_0015_Reserved_31_8_WIDTH 24
-#define D0F0xE4_PIF_0015_Reserved_31_8_MASK 0xffffff00
-
-/// D0F0xE4_PIF_0015
-typedef union {
- struct { ///<
- UINT32 TxPhyStatus00:1 ; ///<
- UINT32 TxPhyStatus01:1 ; ///<
- UINT32 TxPhyStatus02:1 ; ///<
- UINT32 TxPhyStatus03:1 ; ///<
- UINT32 TxPhyStatus04:1 ; ///<
- UINT32 TxPhyStatus05:1 ; ///<
- UINT32 TxPhyStatus06:1 ; ///<
- UINT32 TxPhyStatus07:1 ; ///<
- UINT32 Reserved_31_8:24; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0xE4_PIF_0015_STRUCT;
-
-// **** D0F0xE4_CORE_0002 Register Definition ****
-// Address
-#define D0F0xE4_CORE_0002_ADDRESS 0x2
-
-// Type
-#define D0F0xE4_CORE_0002_TYPE TYPE_D0F0xE4
-// Field Data
-#define D0F0xE4_CORE_0002_HwDebug_0__OFFSET 0
-#define D0F0xE4_CORE_0002_HwDebug_0__WIDTH 1
-#define D0F0xE4_CORE_0002_HwDebug_0__MASK 0x1
-#define D0F0xE4_CORE_0002_Reserved_31_1_OFFSET 1
-#define D0F0xE4_CORE_0002_Reserved_31_1_WIDTH 31
-#define D0F0xE4_CORE_0002_Reserved_31_1_MASK 0xfffffffe
-
-/// D0F0xE4_CORE_0002
-typedef union {
- struct { ///<
- UINT32 HwDebug_0_:1 ; ///<
- UINT32 Reserved_31_1:31; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0xE4_CORE_0002_STRUCT;
-
-// **** D0F0xE4_CORE_0011 Register Definition ****
-// Address
-#define D0F0xE4_CORE_0011_ADDRESS 0x11
-
-// Type
-#define D0F0xE4_CORE_0011_TYPE TYPE_D0F0xE4
-// Field Data
-#define D0F0xE4_CORE_0011_DynClkLatency_OFFSET 0
-#define D0F0xE4_CORE_0011_DynClkLatency_WIDTH 4
-#define D0F0xE4_CORE_0011_DynClkLatency_MASK 0xf
-#define D0F0xE4_CORE_0011_Reserved_31_4_OFFSET 4
-#define D0F0xE4_CORE_0011_Reserved_31_4_WIDTH 28
-#define D0F0xE4_CORE_0011_Reserved_31_4_MASK 0xfffffff0
-
-/// D0F0xE4_CORE_0011
-typedef union {
- struct { ///<
- UINT32 DynClkLatency:4 ; ///<
- UINT32 Reserved_31_4:28; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0xE4_CORE_0011_STRUCT;
-
-// **** D0F0xE4_CORE_001C Register Definition ****
-// Address
-#define D0F0xE4_CORE_001C_ADDRESS 0x1c
-
-// Type
-#define D0F0xE4_CORE_001C_TYPE TYPE_D0F0xE4
-// Field Data
-#define D0F0xE4_CORE_001C_TxArbRoundRobinEn_OFFSET 0
-#define D0F0xE4_CORE_001C_TxArbRoundRobinEn_WIDTH 1
-#define D0F0xE4_CORE_001C_TxArbRoundRobinEn_MASK 0x1
-#define D0F0xE4_CORE_001C_TxArbSlvLimit_OFFSET 1
-#define D0F0xE4_CORE_001C_TxArbSlvLimit_WIDTH 5
-#define D0F0xE4_CORE_001C_TxArbSlvLimit_MASK 0x3e
-#define D0F0xE4_CORE_001C_TxArbMstLimit_OFFSET 6
-#define D0F0xE4_CORE_001C_TxArbMstLimit_WIDTH 5
-#define D0F0xE4_CORE_001C_TxArbMstLimit_MASK 0x7c0
-#define D0F0xE4_CORE_001C_Reserved_31_11_OFFSET 11
-#define D0F0xE4_CORE_001C_Reserved_31_11_WIDTH 21
-#define D0F0xE4_CORE_001C_Reserved_31_11_MASK 0xfffff800
-
-/// D0F0xE4_CORE_001C
-typedef union {
- struct { ///<
- UINT32 TxArbRoundRobinEn:1 ; ///<
- UINT32 TxArbSlvLimit:5 ; ///<
- UINT32 TxArbMstLimit:5 ; ///<
- UINT32 Reserved_31_11:21; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0xE4_CORE_001C_STRUCT;
-
-// **** D0F0xE4_CORE_0040 Register Definition ****
-// Address
-#define D0F0xE4_CORE_0040_ADDRESS 0x40
-
-// Type
-#define D0F0xE4_CORE_0040_TYPE TYPE_D0F0xE4
-// Field Data
-#define D0F0xE4_CORE_0040_Reserved_13_0_OFFSET 0
-#define D0F0xE4_CORE_0040_Reserved_13_0_WIDTH 14
-#define D0F0xE4_CORE_0040_Reserved_13_0_MASK 0x3fff
-#define D0F0xE4_CORE_0040_PElecIdleMode_OFFSET 14
-#define D0F0xE4_CORE_0040_PElecIdleMode_WIDTH 2
-#define D0F0xE4_CORE_0040_PElecIdleMode_MASK 0xc000
-#define D0F0xE4_CORE_0040_Reserved_31_16_OFFSET 16
-#define D0F0xE4_CORE_0040_Reserved_31_16_WIDTH 16
-#define D0F0xE4_CORE_0040_Reserved_31_16_MASK 0xffff0000
-
-/// D0F0xE4_CORE_0040
-typedef union {
- struct { ///<
- UINT32 Reserved_13_0:14; ///<
- UINT32 PElecIdleMode:2 ; ///<
- UINT32 Reserved_31_16:16; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0xE4_CORE_0040_STRUCT;
-
-// **** D0F0xE4_CORE_00C0 Register Definition ****
-// Address
-#define D0F0xE4_CORE_00C0_ADDRESS 0xc0
-
-// Type
-#define D0F0xE4_CORE_00C0_TYPE TYPE_D0F0xE4
-// Field Data
-#define D0F0xE4_CORE_00C0_Reserved_27_0_OFFSET 0
-#define D0F0xE4_CORE_00C0_Reserved_27_0_WIDTH 28
-#define D0F0xE4_CORE_00C0_Reserved_27_0_MASK 0xfffffff
-#define D0F0xE4_CORE_00C0_StrapReverseAll_OFFSET 28
-#define D0F0xE4_CORE_00C0_StrapReverseAll_WIDTH 1
-#define D0F0xE4_CORE_00C0_StrapReverseAll_MASK 0x10000000
-#define D0F0xE4_CORE_00C0_StrapMstAdr64En_OFFSET 29
-#define D0F0xE4_CORE_00C0_StrapMstAdr64En_WIDTH 1
-#define D0F0xE4_CORE_00C0_StrapMstAdr64En_MASK 0x20000000
-#define D0F0xE4_CORE_00C0_Reserved_31_30_OFFSET 30
-#define D0F0xE4_CORE_00C0_Reserved_31_30_WIDTH 2
-#define D0F0xE4_CORE_00C0_Reserved_31_30_MASK 0xc0000000
-
-/// D0F0xE4_CORE_00C0
-typedef union {
- struct { ///<
- UINT32 Reserved_27_0:28; ///<
- UINT32 StrapReverseAll:1 ; ///<
- UINT32 StrapMstAdr64En:1 ; ///<
- UINT32 Reserved_31_30:2 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0xE4_CORE_00C0_STRUCT;
-
-// **** D0F0xE4_CORE_00C1 Register Definition ****
-// Address
-#define D0F0xE4_CORE_00C1_ADDRESS 0xc1
-
-// Type
-#define D0F0xE4_CORE_00C1_TYPE TYPE_D0F0xE4
-// Field Data
-#define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_OFFSET 0
-#define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_WIDTH 1
-#define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_MASK 0x1
-#define D0F0xE4_CORE_00C1_StrapGen2Compliance_OFFSET 1
-#define D0F0xE4_CORE_00C1_StrapGen2Compliance_WIDTH 1
-#define D0F0xE4_CORE_00C1_StrapGen2Compliance_MASK 0x2
-#define D0F0xE4_CORE_00C1_Reserved_31_2_OFFSET 2
-#define D0F0xE4_CORE_00C1_Reserved_31_2_WIDTH 30
-#define D0F0xE4_CORE_00C1_Reserved_31_2_MASK 0xfffffffc
-
-/// D0F0xE4_CORE_00C1
-typedef union {
- struct { ///<
- UINT32 StrapLinkBwNotificationCapEn:1 ; ///<
- UINT32 StrapGen2Compliance:1 ; ///<
- UINT32 Reserved_31_2:30; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0xE4_CORE_00C1_STRUCT;
-
-// **** D0F0xE4_PHY_4004 Register Definition ****
-// Address
-#define D0F0xE4_PHY_4004_ADDRESS 0x4004
-
-// Type
-#define D0F0xE4_PHY_4004_TYPE TYPE_D0F0xE4
-// Field Data
-#define D0F0xE4_PHY_4004_PllBiasGenPdnbOvrdEn_OFFSET 0
-#define D0F0xE4_PHY_4004_PllBiasGenPdnbOvrdEn_WIDTH 1
-#define D0F0xE4_PHY_4004_PllBiasGenPdnbOvrdEn_MASK 0x1
-#define D0F0xE4_PHY_4004_PllBiasGenPdnbOvrdVal_OFFSET 1
-#define D0F0xE4_PHY_4004_PllBiasGenPdnbOvrdVal_WIDTH 1
-#define D0F0xE4_PHY_4004_PllBiasGenPdnbOvrdVal_MASK 0x2
-#define D0F0xE4_PHY_4004_Reserved_31_2_OFFSET 2
-#define D0F0xE4_PHY_4004_Reserved_31_2_WIDTH 30
-#define D0F0xE4_PHY_4004_Reserved_31_2_MASK 0xfffffffc
-
-/// D0F0xE4_PHY_4004
-typedef union {
- struct { ///<
- UINT32 PllBiasGenPdnbOvrdEn:1 ; ///<
- UINT32 PllBiasGenPdnbOvrdVal:1 ; ///<
- UINT32 Reserved_31_2:30; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0xE4_PHY_4004_STRUCT;
-
-// **** DxF0xE4_x02 Register Definition ****
-// Address
-#define DxF0xE4_x02_ADDRESS 0x2
-
-// Type
-#define DxF0xE4_x02_TYPE TYPE_D4F0xE4
-// Field Data
-#define DxF0xE4_x02_Reserved_14_0_OFFSET 0
-#define DxF0xE4_x02_Reserved_14_0_WIDTH 15
-#define DxF0xE4_x02_Reserved_14_0_MASK 0x7fff
-#define DxF0xE4_x02_RegsLcAllowTxL1Control_OFFSET 15
-#define DxF0xE4_x02_RegsLcAllowTxL1Control_WIDTH 1
-#define DxF0xE4_x02_RegsLcAllowTxL1Control_MASK 0x8000
-#define DxF0xE4_x02_Reserved_31_16_OFFSET 16
-#define DxF0xE4_x02_Reserved_31_16_WIDTH 16
-#define DxF0xE4_x02_Reserved_31_16_MASK 0xffff0000
-
-/// DxF0xE4_x02
-typedef union {
- struct { ///<
- UINT32 Reserved_14_0:15; ///<
- UINT32 RegsLcAllowTxL1Control:1 ; ///<
- UINT32 Reserved_31_16:16; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0xE4_x02_STRUCT;
-
-// **** DxF0xE4_x20 Register Definition ****
-// Address
-#define DxF0xE4_x20_ADDRESS 0x20
-
-// Type
-#define DxF0xE4_x20_TYPE TYPE_D4F0xE4
-// Field Data
-#define DxF0xE4_x20_Reserved_14_0_OFFSET 0
-#define DxF0xE4_x20_Reserved_14_0_WIDTH 15
-#define DxF0xE4_x20_Reserved_14_0_MASK 0x7fff
-#define DxF0xE4_x20_TxFlushTlpDis_OFFSET 15
-#define DxF0xE4_x20_TxFlushTlpDis_WIDTH 1
-#define DxF0xE4_x20_TxFlushTlpDis_MASK 0x8000
-#define DxF0xE4_x20_Reserved_31_16_OFFSET 16
-#define DxF0xE4_x20_Reserved_31_16_WIDTH 16
-#define DxF0xE4_x20_Reserved_31_16_MASK 0xffff0000
-
-/// DxF0xE4_x20
-typedef union {
- struct { ///<
- UINT32 Reserved_14_0:15; ///<
- UINT32 TxFlushTlpDis:1 ; ///<
- UINT32 Reserved_31_16:16; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0xE4_x20_STRUCT;
-
-// **** DxF0xE4_x50 Register Definition ****
-// Address
-#define DxF0xE4_x50_ADDRESS 0x50
-
-// Type
-#define DxF0xE4_x50_TYPE TYPE_D4F0xE4
-// Field Data
-#define DxF0xE4_x50_PortLaneReversal_OFFSET 0
-#define DxF0xE4_x50_PortLaneReversal_WIDTH 1
-#define DxF0xE4_x50_PortLaneReversal_MASK 0x1
-#define DxF0xE4_x50_PhyLinkWidth_OFFSET 1
-#define DxF0xE4_x50_PhyLinkWidth_WIDTH 6
-#define DxF0xE4_x50_PhyLinkWidth_MASK 0x7e
-#define DxF0xE4_x50_Reserved_31_7_OFFSET 7
-#define DxF0xE4_x50_Reserved_31_7_WIDTH 25
-#define DxF0xE4_x50_Reserved_31_7_MASK 0xffffff80
-
-/// DxF0xE4_x50
-typedef union {
- struct { ///<
- UINT32 PortLaneReversal:1 ; ///<
- UINT32 PhyLinkWidth:6 ; ///<
- UINT32 Reserved_31_7:25; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0xE4_x50_STRUCT;
-
-// **** DxF0xE4_x70 Register Definition ****
-// Address
-#define DxF0xE4_x70_ADDRESS 0x70
-
-// Type
-#define DxF0xE4_x70_TYPE TYPE_D4F0xE4
-// Field Data
-#define DxF0xE4_x70_Reserved_15_0_OFFSET 0
-#define DxF0xE4_x70_Reserved_15_0_WIDTH 16
-#define DxF0xE4_x70_Reserved_15_0_MASK 0xffff
-#define DxF0xE4_x70_RxRcbCplTimeout_OFFSET 16
-#define DxF0xE4_x70_RxRcbCplTimeout_WIDTH 3
-#define DxF0xE4_x70_RxRcbCplTimeout_MASK 0x70000
-#define DxF0xE4_x70_RxRcbCplTimeoutMode_OFFSET 19
-#define DxF0xE4_x70_RxRcbCplTimeoutMode_WIDTH 1
-#define DxF0xE4_x70_RxRcbCplTimeoutMode_MASK 0x80000
-#define DxF0xE4_x70_Reserved_31_20_OFFSET 20
-#define DxF0xE4_x70_Reserved_31_20_WIDTH 12
-#define DxF0xE4_x70_Reserved_31_20_MASK 0xfff00000
-
-/// DxF0xE4_x70
-typedef union {
- struct { ///<
- UINT32 Reserved_15_0:16; ///<
- UINT32 RxRcbCplTimeout:3 ; ///<
- UINT32 RxRcbCplTimeoutMode:1 ; ///<
- UINT32 Reserved_31_20:12; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0xE4_x70_STRUCT;
-
-// **** DxF0xE4_xA0 Register Definition ****
-// Address
-#define DxF0xE4_xA0_ADDRESS 0xa0
-
-// Type
-#define DxF0xE4_xA0_TYPE TYPE_D4F0xE4
-// Field Data
-#define DxF0xE4_xA0_Reserved_3_0_OFFSET 0
-#define DxF0xE4_xA0_Reserved_3_0_WIDTH 4
-#define DxF0xE4_xA0_Reserved_3_0_MASK 0xf
-#define DxF0xE4_xA0_Lc16xClearTxPipe_OFFSET 4
-#define DxF0xE4_xA0_Lc16xClearTxPipe_WIDTH 4
-#define DxF0xE4_xA0_Lc16xClearTxPipe_MASK 0xf0
-#define DxF0xE4_xA0_LcL0sInactivity_OFFSET 8
-#define DxF0xE4_xA0_LcL0sInactivity_WIDTH 4
-#define DxF0xE4_xA0_LcL0sInactivity_MASK 0xf00
-#define DxF0xE4_xA0_LcL1Inactivity_OFFSET 12
-#define DxF0xE4_xA0_LcL1Inactivity_WIDTH 4
-#define DxF0xE4_xA0_LcL1Inactivity_MASK 0xf000
-#define DxF0xE4_xA0_Reserved_22_16_OFFSET 16
-#define DxF0xE4_xA0_Reserved_22_16_WIDTH 7
-#define DxF0xE4_xA0_Reserved_22_16_MASK 0x7f0000
-#define DxF0xE4_xA0_LcL1ImmediateAck_OFFSET 23
-#define DxF0xE4_xA0_LcL1ImmediateAck_WIDTH 1
-#define DxF0xE4_xA0_LcL1ImmediateAck_MASK 0x800000
-#define DxF0xE4_xA0_Reserved_31_24_OFFSET 24
-#define DxF0xE4_xA0_Reserved_31_24_WIDTH 8
-#define DxF0xE4_xA0_Reserved_31_24_MASK 0xff000000
-
-/// DxF0xE4_xA0
-typedef union {
- struct { ///<
- UINT32 Reserved_3_0:4 ; ///<
- UINT32 Lc16xClearTxPipe:4 ; ///<
- UINT32 LcL0sInactivity:4 ; ///<
- UINT32 LcL1Inactivity:4 ; ///<
- UINT32 Reserved_22_16:7 ; ///<
- UINT32 LcL1ImmediateAck:1 ; ///<
- UINT32 Reserved_31_24:8 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0xE4_xA0_STRUCT;
-
-// **** DxF0xE4_xA1 Register Definition ****
-// Address
-#define DxF0xE4_xA1_ADDRESS 0xa1
-
-// Type
-#define DxF0xE4_xA1_TYPE TYPE_D4F0xE4
-// Field Data
-#define DxF0xE4_xA1_Reserved_10_0_OFFSET 0
-#define DxF0xE4_xA1_Reserved_10_0_WIDTH 11
-#define DxF0xE4_xA1_Reserved_10_0_MASK 0x7ff
-#define DxF0xE4_xA1_LcDontGotoL0sifL1Armed_OFFSET 11
-#define DxF0xE4_xA1_LcDontGotoL0sifL1Armed_WIDTH 1
-#define DxF0xE4_xA1_LcDontGotoL0sifL1Armed_MASK 0x800
-#define DxF0xE4_xA1_LcInitSpdChgWithCsrEn_OFFSET 12
-#define DxF0xE4_xA1_LcInitSpdChgWithCsrEn_WIDTH 1
-#define DxF0xE4_xA1_LcInitSpdChgWithCsrEn_MASK 0x1000
-#define DxF0xE4_xA1_Reserved_31_13_OFFSET 13
-#define DxF0xE4_xA1_Reserved_31_13_WIDTH 19
-#define DxF0xE4_xA1_Reserved_31_13_MASK 0xffffe000
-
-/// DxF0xE4_xA1
-typedef union {
- struct { ///<
- UINT32 Reserved_10_0:11; ///<
- UINT32 LcDontGotoL0sifL1Armed:1 ; ///<
- UINT32 LcInitSpdChgWithCsrEn:1 ; ///<
- UINT32 Reserved_31_13:19; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0xE4_xA1_STRUCT;
-
-// **** DxF0xE4_xA2 Register Definition ****
-// Address
-#define DxF0xE4_xA2_ADDRESS 0xa2
-
-// Type
-#define DxF0xE4_xA2_TYPE TYPE_D4F0xE4
-// Field Data
-#define DxF0xE4_xA2_LcLinkWidth_OFFSET 0
-#define DxF0xE4_xA2_LcLinkWidth_WIDTH 3
-#define DxF0xE4_xA2_LcLinkWidth_MASK 0x7
-#define DxF0xE4_xA2_Reserved_3_3_OFFSET 3
-#define DxF0xE4_xA2_Reserved_3_3_WIDTH 1
-#define DxF0xE4_xA2_Reserved_3_3_MASK 0x8
-#define DxF0xE4_xA2_LcLinkWidthRd_OFFSET 4
-#define DxF0xE4_xA2_LcLinkWidthRd_WIDTH 3
-#define DxF0xE4_xA2_LcLinkWidthRd_MASK 0x70
-#define DxF0xE4_xA2_LcReconfigArcMissingEscape_OFFSET 7
-#define DxF0xE4_xA2_LcReconfigArcMissingEscape_WIDTH 1
-#define DxF0xE4_xA2_LcReconfigArcMissingEscape_MASK 0x80
-#define DxF0xE4_xA2_LcReconfigNow_OFFSET 8
-#define DxF0xE4_xA2_LcReconfigNow_WIDTH 1
-#define DxF0xE4_xA2_LcReconfigNow_MASK 0x100
-#define DxF0xE4_xA2_LcRenegotiationSupport_OFFSET 9
-#define DxF0xE4_xA2_LcRenegotiationSupport_WIDTH 1
-#define DxF0xE4_xA2_LcRenegotiationSupport_MASK 0x200
-#define DxF0xE4_xA2_LcRenegotiateEn_OFFSET 10
-#define DxF0xE4_xA2_LcRenegotiateEn_WIDTH 1
-#define DxF0xE4_xA2_LcRenegotiateEn_MASK 0x400
-#define DxF0xE4_xA2_LcShortReconfigEn_OFFSET 11
-#define DxF0xE4_xA2_LcShortReconfigEn_WIDTH 1
-#define DxF0xE4_xA2_LcShortReconfigEn_MASK 0x800
-#define DxF0xE4_xA2_LcUpconfigureSupport_OFFSET 12
-#define DxF0xE4_xA2_LcUpconfigureSupport_WIDTH 1
-#define DxF0xE4_xA2_LcUpconfigureSupport_MASK 0x1000
-#define DxF0xE4_xA2_LcUpconfigureDis_OFFSET 13
-#define DxF0xE4_xA2_LcUpconfigureDis_WIDTH 1
-#define DxF0xE4_xA2_LcUpconfigureDis_MASK 0x2000
-#define DxF0xE4_xA2_Reserved_19_14_OFFSET 14
-#define DxF0xE4_xA2_Reserved_19_14_WIDTH 6
-#define DxF0xE4_xA2_Reserved_19_14_MASK 0xfc000
-#define DxF0xE4_xA2_LcUpconfigCapable_OFFSET 20
-#define DxF0xE4_xA2_LcUpconfigCapable_WIDTH 1
-#define DxF0xE4_xA2_LcUpconfigCapable_MASK 0x100000
-#define DxF0xE4_xA2_LcDynLanesPwrState_OFFSET 21
-#define DxF0xE4_xA2_LcDynLanesPwrState_WIDTH 2
-#define DxF0xE4_xA2_LcDynLanesPwrState_MASK 0x600000
-#define DxF0xE4_xA2_Reserved_31_23_OFFSET 23
-#define DxF0xE4_xA2_Reserved_31_23_WIDTH 9
-#define DxF0xE4_xA2_Reserved_31_23_MASK 0xff800000
-
-/// DxF0xE4_xA2
-typedef union {
- struct { ///<
- UINT32 LcLinkWidth:3 ; ///<
- UINT32 Reserved_3_3:1 ; ///<
- UINT32 LcLinkWidthRd:3 ; ///<
- UINT32 LcReconfigArcMissingEscape:1 ; ///<
- UINT32 LcReconfigNow:1 ; ///<
- UINT32 LcRenegotiationSupport:1 ; ///<
- UINT32 LcRenegotiateEn:1 ; ///<
- UINT32 LcShortReconfigEn:1 ; ///<
- UINT32 LcUpconfigureSupport:1 ; ///<
- UINT32 LcUpconfigureDis:1 ; ///<
- UINT32 Reserved_19_14:6 ; ///<
- UINT32 LcUpconfigCapable:1 ; ///<
- UINT32 LcDynLanesPwrState:2 ; ///<
- UINT32 Reserved_31_23:9 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0xE4_xA2_STRUCT;
-
-// **** DxF0xE4_xA3 Register Definition ****
-// Address
-#define DxF0xE4_xA3_ADDRESS 0xa3
-
-// Type
-#define DxF0xE4_xA3_TYPE TYPE_D4F0xE4
-// Field Data
-#define DxF0xE4_xA3_Reserved_8_0_OFFSET 0
-#define DxF0xE4_xA3_Reserved_8_0_WIDTH 9
-#define DxF0xE4_xA3_Reserved_8_0_MASK 0x1ff
-#define DxF0xE4_xA3_LcXmitFtsBeforeRecovery_OFFSET 9
-#define DxF0xE4_xA3_LcXmitFtsBeforeRecovery_WIDTH 1
-#define DxF0xE4_xA3_LcXmitFtsBeforeRecovery_MASK 0x200
-#define DxF0xE4_xA3_Reserved_31_10_OFFSET 10
-#define DxF0xE4_xA3_Reserved_31_10_WIDTH 22
-#define DxF0xE4_xA3_Reserved_31_10_MASK 0xfffffc00
-
-/// DxF0xE4_xA3
-typedef union {
- struct { ///<
- UINT32 Reserved_8_0:9 ; ///<
- UINT32 LcXmitFtsBeforeRecovery:1 ; ///<
- UINT32 Reserved_31_10:22; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0xE4_xA3_STRUCT;
-
-// **** DxF0xE4_xA4 Register Definition ****
-// Address
-#define DxF0xE4_xA4_ADDRESS 0xa4
-
-// Type
-#define DxF0xE4_xA4_TYPE TYPE_D4F0xE4
-// Field Data
-#define DxF0xE4_xA4_LcGen2EnStrap_OFFSET 0
-#define DxF0xE4_xA4_LcGen2EnStrap_WIDTH 1
-#define DxF0xE4_xA4_LcGen2EnStrap_MASK 0x1
-#define DxF0xE4_xA4_Reserved_3_1_OFFSET 1
-#define DxF0xE4_xA4_Reserved_3_1_WIDTH 3
-#define DxF0xE4_xA4_Reserved_3_1_MASK 0xe
-#define DxF0xE4_xA4_LcForceDisSwSpeedChange_OFFSET 4
-#define DxF0xE4_xA4_LcForceDisSwSpeedChange_WIDTH 1
-#define DxF0xE4_xA4_LcForceDisSwSpeedChange_MASK 0x10
-#define DxF0xE4_xA4_Reserved_6_5_OFFSET 5
-#define DxF0xE4_xA4_Reserved_6_5_WIDTH 2
-#define DxF0xE4_xA4_Reserved_6_5_MASK 0x60
-#define DxF0xE4_xA4_LcInitiateLinkSpeedChange_OFFSET 7
-#define DxF0xE4_xA4_LcInitiateLinkSpeedChange_WIDTH 1
-#define DxF0xE4_xA4_LcInitiateLinkSpeedChange_MASK 0x80
-#define DxF0xE4_xA4_LcSpeedChangeAttemptsAllowed_OFFSET 8
-#define DxF0xE4_xA4_LcSpeedChangeAttemptsAllowed_WIDTH 2
-#define DxF0xE4_xA4_LcSpeedChangeAttemptsAllowed_MASK 0x300
-#define DxF0xE4_xA4_LcSpeedChangeAttemptFailed_OFFSET 10
-#define DxF0xE4_xA4_LcSpeedChangeAttemptFailed_WIDTH 1
-#define DxF0xE4_xA4_LcSpeedChangeAttemptFailed_MASK 0x400
-#define DxF0xE4_xA4_Reserved_17_11_OFFSET 11
-#define DxF0xE4_xA4_Reserved_17_11_WIDTH 7
-#define DxF0xE4_xA4_Reserved_17_11_MASK 0x3f800
-#define DxF0xE4_xA4_LcGoToRecovery_OFFSET 18
-#define DxF0xE4_xA4_LcGoToRecovery_WIDTH 1
-#define DxF0xE4_xA4_LcGoToRecovery_MASK 0x40000
-#define DxF0xE4_xA4_Reserved_23_19_OFFSET 19
-#define DxF0xE4_xA4_Reserved_23_19_WIDTH 5
-#define DxF0xE4_xA4_Reserved_23_19_MASK 0xf80000
-#define DxF0xE4_xA4_LcOtherSideSupportsGen2_OFFSET 24
-#define DxF0xE4_xA4_LcOtherSideSupportsGen2_WIDTH 1
-#define DxF0xE4_xA4_LcOtherSideSupportsGen2_MASK 0x1000000
-#define DxF0xE4_xA4_Reserved_28_25_OFFSET 25
-#define DxF0xE4_xA4_Reserved_28_25_WIDTH 4
-#define DxF0xE4_xA4_Reserved_28_25_MASK 0x1e000000
-#define DxF0xE4_xA4_LcMultUpstreamAutoSpdChngEn_OFFSET 29
-#define DxF0xE4_xA4_LcMultUpstreamAutoSpdChngEn_WIDTH 1
-#define DxF0xE4_xA4_LcMultUpstreamAutoSpdChngEn_MASK 0x20000000
-#define DxF0xE4_xA4_Reserved_31_30_OFFSET 30
-#define DxF0xE4_xA4_Reserved_31_30_WIDTH 2
-#define DxF0xE4_xA4_Reserved_31_30_MASK 0xc0000000
-
-/// DxF0xE4_xA4
-typedef union {
- struct { ///<
- UINT32 LcGen2EnStrap:1 ; ///<
- UINT32 Reserved_3_1:3 ; ///<
- UINT32 LcForceDisSwSpeedChange:1 ; ///<
- UINT32 Reserved_6_5:2 ; ///<
- UINT32 LcInitiateLinkSpeedChange:1 ; ///<
- UINT32 LcSpeedChangeAttemptsAllowed:2 ; ///<
- UINT32 LcSpeedChangeAttemptFailed:1 ; ///<
- UINT32 Reserved_17_11:7 ; ///<
- UINT32 LcGoToRecovery:1 ; ///<
- UINT32 Reserved_23_19:5 ; ///<
- UINT32 LcOtherSideSupportsGen2:1 ; ///<
- UINT32 Reserved_28_25:4 ; ///<
- UINT32 LcMultUpstreamAutoSpdChngEn:1 ; ///<
- UINT32 Reserved_31_30:2 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0xE4_xA4_STRUCT;
-
-// **** DxF0xE4_xB1 Register Definition ****
-// Address
-#define DxF0xE4_xB1_ADDRESS 0xb1
-
-// Type
-#define DxF0xE4_xB1_TYPE TYPE_D4F0xE4
-// Field Data
-#define DxF0xE4_xB1_Reserved_18_0_OFFSET 0
-#define DxF0xE4_xB1_Reserved_18_0_WIDTH 19
-#define DxF0xE4_xB1_Reserved_18_0_MASK 0x7ffff
-#define DxF0xE4_xB1_LcDeassertRxEnInL0s_OFFSET 19
-#define DxF0xE4_xB1_LcDeassertRxEnInL0s_WIDTH 1
-#define DxF0xE4_xB1_LcDeassertRxEnInL0s_MASK 0x80000
-#define DxF0xE4_xB1_LcBlockElIdleinL0_OFFSET 20
-#define DxF0xE4_xB1_LcBlockElIdleinL0_WIDTH 1
-#define DxF0xE4_xB1_LcBlockElIdleinL0_MASK 0x100000
-#define DxF0xE4_xB1_Reserved_31_21_OFFSET 21
-#define DxF0xE4_xB1_Reserved_31_21_WIDTH 11
-#define DxF0xE4_xB1_Reserved_31_21_MASK 0xffe00000
-
-/// DxF0xE4_xB1
-typedef union {
- struct { ///<
- UINT32 Reserved_18_0:19; ///<
- UINT32 LcDeassertRxEnInL0s:1 ; ///<
- UINT32 LcBlockElIdleinL0:1 ; ///<
- UINT32 Reserved_31_21:11; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0xE4_xB1_STRUCT;
-
-// **** DxF0xE4_xC0 Register Definition ****
-// Address
-#define DxF0xE4_xC0_ADDRESS 0xc0
-
-// Type
-#define DxF0xE4_xC0_TYPE TYPE_D4F0xE4
-// Field Data
-#define DxF0xE4_xC0_Reserved_12_0_OFFSET 0
-#define DxF0xE4_xC0_Reserved_12_0_WIDTH 13
-#define DxF0xE4_xC0_Reserved_12_0_MASK 0x1fff
-#define DxF0xE4_xC0_StrapForceCompliance_OFFSET 13
-#define DxF0xE4_xC0_StrapForceCompliance_WIDTH 1
-#define DxF0xE4_xC0_StrapForceCompliance_MASK 0x2000
-#define DxF0xE4_xC0_Reserved_14_14_OFFSET 14
-#define DxF0xE4_xC0_Reserved_14_14_WIDTH 1
-#define DxF0xE4_xC0_Reserved_14_14_MASK 0x4000
-#define DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_OFFSET 15
-#define DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_WIDTH 1
-#define DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_MASK 0x8000
-#define DxF0xE4_xC0_Reserved_31_16_OFFSET 16
-#define DxF0xE4_xC0_Reserved_31_16_WIDTH 16
-#define DxF0xE4_xC0_Reserved_31_16_MASK 0xffff0000
-
-/// DxF0xE4_xC0
-typedef union {
- struct { ///<
- UINT32 Reserved_12_0:13; ///<
- UINT32 StrapForceCompliance:1 ; ///<
- UINT32 Reserved_14_14:1 ; ///<
- UINT32 StrapAutoRcSpeedNegotiationDis:1 ; ///<
- UINT32 Reserved_31_16:16; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0xE4_xC0_STRUCT;
-
-// **** DxF0xE4_xC1 Register Definition ****
-// Address
-#define DxF0xE4_xC1_ADDRESS 0xc1
-
-// Type
-#define DxF0xE4_xC1_TYPE TYPE_D4F0xE4
-// Field Data
-#define DxF0xE4_xC1_Reserved_3_0_OFFSET 0
-#define DxF0xE4_xC1_Reserved_3_0_WIDTH 4
-#define DxF0xE4_xC1_Reserved_3_0_MASK 0xf
-#define DxF0xE4_xC1_StrapReverseLanes_OFFSET 4
-#define DxF0xE4_xC1_StrapReverseLanes_WIDTH 1
-#define DxF0xE4_xC1_StrapReverseLanes_MASK 0x10
-#define DxF0xE4_xC1_Reserved_31_5_OFFSET 5
-#define DxF0xE4_xC1_Reserved_31_5_WIDTH 27
-#define DxF0xE4_xC1_Reserved_31_5_MASK 0xffffffe0
-
-/// DxF0xE4_xC1
-typedef union {
- struct { ///<
- UINT32 Reserved_3_0:4 ; ///<
- UINT32 StrapReverseLanes:1 ; ///<
- UINT32 Reserved_31_5:27; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0xE4_xC1_STRUCT;
-
-// **** SMUx0B_x8600 Register Definition ****
-// Address
-#define SMUx0B_x8600_ADDRESS 0x8600
-
-// Type
-#define SMUx0B_x8600_TYPE TYPE_SMUx0B
-// Field Data
-#define SMUx0B_x8600_Txn1MBusAddr_7_0__OFFSET 0
-#define SMUx0B_x8600_Txn1MBusAddr_7_0__WIDTH 8
-#define SMUx0B_x8600_Txn1MBusAddr_7_0__MASK 0xff
-#define SMUx0B_x8600_MemAddr_7_0__OFFSET 8
-#define SMUx0B_x8600_MemAddr_7_0__WIDTH 8
-#define SMUx0B_x8600_MemAddr_7_0__MASK 0xff00
-#define SMUx0B_x8600_MemAddr_15_8__OFFSET 16
-#define SMUx0B_x8600_MemAddr_15_8__WIDTH 8
-#define SMUx0B_x8600_MemAddr_15_8__MASK 0xff0000
-#define SMUx0B_x8600_TransactionCount_OFFSET 24
-#define SMUx0B_x8600_TransactionCount_WIDTH 8
-#define SMUx0B_x8600_TransactionCount_MASK 0xff000000
-
-/// SMUx0B_x8600
-typedef union {
- struct { ///<
- UINT32 Txn1MBusAddr_7_0_:8 ; ///<
- UINT32 MemAddr_7_0_:8 ; ///<
- UINT32 MemAddr_15_8_:8 ; ///<
- UINT32 TransactionCount:8 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x8600_STRUCT;
-
-// **** SMUx0B_x8604 Register Definition ****
-// Address
-#define SMUx0B_x8604_ADDRESS 0x8604
-
-// Type
-#define SMUx0B_x8604_TYPE TYPE_SMUx0B
-// Field Data
-#define SMUx0B_x8604_Txn1TransferLength_7_0__OFFSET 0
-#define SMUx0B_x8604_Txn1TransferLength_7_0__WIDTH 8
-#define SMUx0B_x8604_Txn1TransferLength_7_0__MASK 0xff
-#define SMUx0B_x8604_Txn1MBusAddr_31_24__OFFSET 8
-#define SMUx0B_x8604_Txn1MBusAddr_31_24__WIDTH 8
-#define SMUx0B_x8604_Txn1MBusAddr_31_24__MASK 0xff00
-#define SMUx0B_x8604_Txn1MBusAddr_23_16__OFFSET 16
-#define SMUx0B_x8604_Txn1MBusAddr_23_16__WIDTH 8
-#define SMUx0B_x8604_Txn1MBusAddr_23_16__MASK 0xff0000
-#define SMUx0B_x8604_Txn1MBusAddr_15_8__OFFSET 24
-#define SMUx0B_x8604_Txn1MBusAddr_15_8__WIDTH 8
-#define SMUx0B_x8604_Txn1MBusAddr_15_8__MASK 0xff000000
-
-/// SMUx0B_x8604
-typedef union {
- struct { ///<
- UINT32 Txn1TransferLength_7_0_:8 ; ///<
- UINT32 Txn1MBusAddr_31_24_:8 ; ///<
- UINT32 Txn1MBusAddr_23_16_:8 ; ///<
- UINT32 Txn1MBusAddr_15_8_:8 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x8604_STRUCT;
-
-// **** SMUx0B_x8608 Register Definition ****
-// Address
-#define SMUx0B_x8608_ADDRESS 0x8608
-
-// Type
-#define SMUx0B_x8608_TYPE TYPE_SMUx0B
-// Field Data
-#define SMUx0B_x8608_Txn2Mbusaddr158_OFFSET 0
-#define SMUx0B_x8608_Txn2Mbusaddr158_WIDTH 8
-#define SMUx0B_x8608_Txn2Mbusaddr158_MASK 0xff
-#define SMUx0B_x8608_Txn2Mbusaddr70_OFFSET 8
-#define SMUx0B_x8608_Txn2Mbusaddr70_WIDTH 8
-#define SMUx0B_x8608_Txn2Mbusaddr70_MASK 0xff00
-#define SMUx0B_x8608_Txn1Mode_OFFSET 16
-#define SMUx0B_x8608_Txn1Mode_WIDTH 2
-#define SMUx0B_x8608_Txn1Mode_MASK 0x30000
-#define SMUx0B_x8608_Txn1Static_OFFSET 18
-#define SMUx0B_x8608_Txn1Static_WIDTH 1
-#define SMUx0B_x8608_Txn1Static_MASK 0x40000
-#define SMUx0B_x8608_Txn1Overlap_OFFSET 19
-#define SMUx0B_x8608_Txn1Overlap_WIDTH 1
-#define SMUx0B_x8608_Txn1Overlap_MASK 0x80000
-#define SMUx0B_x8608_Txn1Spare_OFFSET 20
-#define SMUx0B_x8608_Txn1Spare_WIDTH 4
-#define SMUx0B_x8608_Txn1Spare_MASK 0xf00000
-#define SMUx0B_x8608_Txn1TransferLength_13_8__OFFSET 24
-#define SMUx0B_x8608_Txn1TransferLength_13_8__WIDTH 6
-#define SMUx0B_x8608_Txn1TransferLength_13_8__MASK 0x3f000000
-#define SMUx0B_x8608_Txn1Tsize_OFFSET 30
-#define SMUx0B_x8608_Txn1Tsize_WIDTH 2
-#define SMUx0B_x8608_Txn1Tsize_MASK 0xc0000000
-
-/// SMUx0B_x8608
-typedef union {
- struct { ///<
- UINT32 Txn2Mbusaddr158:8 ; ///<
- UINT32 Txn2Mbusaddr70:8 ; ///<
- UINT32 Txn1Mode:2 ; ///<
- UINT32 Txn1Static:1 ; ///<
- UINT32 Txn1Overlap:1 ; ///<
- UINT32 Txn1Spare:4 ; ///<
- UINT32 Txn1TransferLength_13_8_:6 ; ///<
- UINT32 Txn1Tsize:2 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x8608_STRUCT;
-
-// **** SMUx0B_x860C Register Definition ****
-// Address
-#define SMUx0B_x860C_ADDRESS 0x860c
-
-// Type
-#define SMUx0B_x860C_TYPE TYPE_SMUx0B
-// Field Data
-#define SMUx0B_x860C_Txn2TransferLength138_OFFSET 0
-#define SMUx0B_x860C_Txn2TransferLength138_WIDTH 6
-#define SMUx0B_x860C_Txn2TransferLength138_MASK 0x3f
-#define SMUx0B_x860C_Txn2Tsize_OFFSET 6
-#define SMUx0B_x860C_Txn2Tsize_WIDTH 2
-#define SMUx0B_x860C_Txn2Tsize_MASK 0xc0
-#define SMUx0B_x860C_Txn2TransferLength70_OFFSET 8
-#define SMUx0B_x860C_Txn2TransferLength70_WIDTH 8
-#define SMUx0B_x860C_Txn2TransferLength70_MASK 0xff00
-#define SMUx0B_x860C_Txn2MBusAddr3124_OFFSET 16
-#define SMUx0B_x860C_Txn2MBusAddr3124_WIDTH 8
-#define SMUx0B_x860C_Txn2MBusAddr3124_MASK 0xff0000
-#define SMUx0B_x860C_Txn2MBusAddr2316_OFFSET 24
-#define SMUx0B_x860C_Txn2MBusAddr2316_WIDTH 8
-#define SMUx0B_x860C_Txn2MBusAddr2316_MASK 0xff000000
-
-/// SMUx0B_x860C
-typedef union {
- struct { ///<
- UINT32 Txn2TransferLength138:6 ; ///<
- UINT32 Txn2Tsize:2 ; ///<
- UINT32 Txn2TransferLength70:8 ; ///<
- UINT32 Txn2MBusAddr3124:8 ; ///<
- UINT32 Txn2MBusAddr2316:8 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x860C_STRUCT;
-
-// **** SMUx0B_x8610 Register Definition ****
-// Address
-#define SMUx0B_x8610_ADDRESS 0x8610
-
-// Type
-#define SMUx0B_x8610_TYPE TYPE_SMUx0B
-// Field Data
-#define SMUx0B_x8610_Txn3MBusAddr2316_OFFSET 0
-#define SMUx0B_x8610_Txn3MBusAddr2316_WIDTH 8
-#define SMUx0B_x8610_Txn3MBusAddr2316_MASK 0xff
-#define SMUx0B_x8610_Txn3MBusAddr158_OFFSET 8
-#define SMUx0B_x8610_Txn3MBusAddr158_WIDTH 8
-#define SMUx0B_x8610_Txn3MBusAddr158_MASK 0xff00
-#define SMUx0B_x8610_Txn3MBusAddr70_OFFSET 16
-#define SMUx0B_x8610_Txn3MBusAddr70_WIDTH 8
-#define SMUx0B_x8610_Txn3MBusAddr70_MASK 0xff0000
-#define SMUx0B_x8610_Txn2Mode_OFFSET 24
-#define SMUx0B_x8610_Txn2Mode_WIDTH 2
-#define SMUx0B_x8610_Txn2Mode_MASK 0x3000000
-#define SMUx0B_x8610_Txn2Static_OFFSET 26
-#define SMUx0B_x8610_Txn2Static_WIDTH 1
-#define SMUx0B_x8610_Txn2Static_MASK 0x4000000
-#define SMUx0B_x8610_Txn2Overlap_OFFSET 27
-#define SMUx0B_x8610_Txn2Overlap_WIDTH 1
-#define SMUx0B_x8610_Txn2Overlap_MASK 0x8000000
-#define SMUx0B_x8610_Txn2Spare_OFFSET 28
-#define SMUx0B_x8610_Txn2Spare_WIDTH 4
-#define SMUx0B_x8610_Txn2Spare_MASK 0xf0000000
-
-/// SMUx0B_x8610
-typedef union {
- struct { ///<
- UINT32 Txn3MBusAddr2316:8 ; ///<
- UINT32 Txn3MBusAddr158:8 ; ///<
- UINT32 Txn3MBusAddr70:8 ; ///<
- UINT32 Txn2Mode:2 ; ///<
- UINT32 Txn2Static:1 ; ///<
- UINT32 Txn2Overlap:1 ; ///<
- UINT32 Txn2Spare:4 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x8610_STRUCT;
-
-// **** SMUx0B_x8614 Register Definition ****
-// Address
-#define SMUx0B_x8614_ADDRESS 0x8614
-
-// Type
-#define SMUx0B_x8614_TYPE TYPE_SMUx0B
-// Field Data
-#define SMUx0B_x8614_Txn3Mode_OFFSET 0
-#define SMUx0B_x8614_Txn3Mode_WIDTH 2
-#define SMUx0B_x8614_Txn3Mode_MASK 0x3
-#define SMUx0B_x8614_Txn3Static_OFFSET 2
-#define SMUx0B_x8614_Txn3Static_WIDTH 1
-#define SMUx0B_x8614_Txn3Static_MASK 0x4
-#define SMUx0B_x8614_Txn3Overlap_OFFSET 3
-#define SMUx0B_x8614_Txn3Overlap_WIDTH 1
-#define SMUx0B_x8614_Txn3Overlap_MASK 0x8
-#define SMUx0B_x8614_Txn3Spare_OFFSET 4
-#define SMUx0B_x8614_Txn3Spare_WIDTH 4
-#define SMUx0B_x8614_Txn3Spare_MASK 0xf0
-#define SMUx0B_x8614_Txn3TransferLength138_OFFSET 8
-#define SMUx0B_x8614_Txn3TransferLength138_WIDTH 6
-#define SMUx0B_x8614_Txn3TransferLength138_MASK 0x3f00
-#define SMUx0B_x8614_Txn3Tsize_OFFSET 14
-#define SMUx0B_x8614_Txn3Tsize_WIDTH 2
-#define SMUx0B_x8614_Txn3Tsize_MASK 0xc000
-#define SMUx0B_x8614_Txn3TransferLength70_OFFSET 16
-#define SMUx0B_x8614_Txn3TransferLength70_WIDTH 8
-#define SMUx0B_x8614_Txn3TransferLength70_MASK 0xff0000
-#define SMUx0B_x8614_Txn3MBusAddr3124_OFFSET 24
-#define SMUx0B_x8614_Txn3MBusAddr3124_WIDTH 8
-#define SMUx0B_x8614_Txn3MBusAddr3124_MASK 0xff000000
-
-/// SMUx0B_x8614
-typedef union {
- struct { ///<
- UINT32 Txn3Mode:2 ; ///<
- UINT32 Txn3Static:1 ; ///<
- UINT32 Txn3Overlap:1 ; ///<
- UINT32 Txn3Spare:4 ; ///<
- UINT32 Txn3TransferLength138:6 ; ///<
- UINT32 Txn3Tsize:2 ; ///<
- UINT32 Txn3TransferLength70:8 ; ///<
- UINT32 Txn3MBusAddr3124:8 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x8614_STRUCT;
-
-// **** SMUx0B_x8618 Register Definition ****
-// Address
-#define SMUx0B_x8618_ADDRESS 0x8618
-
-// Type
-#define SMUx0B_x8618_TYPE TYPE_SMUx0B
-// Field Data
-#define SMUx0B_x8618_Txn4MBusAddr3124_OFFSET 0
-#define SMUx0B_x8618_Txn4MBusAddr3124_WIDTH 8
-#define SMUx0B_x8618_Txn4MBusAddr3124_MASK 0xff
-#define SMUx0B_x8618_Txn4MBusAddr2316_OFFSET 8
-#define SMUx0B_x8618_Txn4MBusAddr2316_WIDTH 8
-#define SMUx0B_x8618_Txn4MBusAddr2316_MASK 0xff00
-#define SMUx0B_x8618_Txn4MBusAddr158_OFFSET 16
-#define SMUx0B_x8618_Txn4MBusAddr158_WIDTH 8
-#define SMUx0B_x8618_Txn4MBusAddr158_MASK 0xff0000
-#define SMUx0B_x8618_Txn4MBusAddr70_OFFSET 24
-#define SMUx0B_x8618_Txn4MBusAddr70_WIDTH 8
-#define SMUx0B_x8618_Txn4MBusAddr70_MASK 0xff000000
-
-/// SMUx0B_x8618
-typedef union {
- struct { ///<
- UINT32 Txn4MBusAddr3124:8 ; ///<
- UINT32 Txn4MBusAddr2316:8 ; ///<
- UINT32 Txn4MBusAddr158:8 ; ///<
- UINT32 Txn4MBusAddr70:8 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x8618_STRUCT;
-
-// **** SMUx0B_x861C Register Definition ****
-// Address
-#define SMUx0B_x861C_ADDRESS 0x861c
-
-// Type
-#define SMUx0B_x861C_TYPE TYPE_SMUx0B
-// Field Data
-#define SMUx0B_x861C_Txn5Mbusaddr70_OFFSET 0
-#define SMUx0B_x861C_Txn5Mbusaddr70_WIDTH 8
-#define SMUx0B_x861C_Txn5Mbusaddr70_MASK 0xff
-#define SMUx0B_x861C_Txn4Mode_OFFSET 8
-#define SMUx0B_x861C_Txn4Mode_WIDTH 2
-#define SMUx0B_x861C_Txn4Mode_MASK 0x300
-#define SMUx0B_x861C_Txn4Static_OFFSET 10
-#define SMUx0B_x861C_Txn4Static_WIDTH 1
-#define SMUx0B_x861C_Txn4Static_MASK 0x400
-#define SMUx0B_x861C_Txn4Overlap_OFFSET 11
-#define SMUx0B_x861C_Txn4Overlap_WIDTH 1
-#define SMUx0B_x861C_Txn4Overlap_MASK 0x800
-#define SMUx0B_x861C_Txn4Spare_OFFSET 12
-#define SMUx0B_x861C_Txn4Spare_WIDTH 4
-#define SMUx0B_x861C_Txn4Spare_MASK 0xf000
-#define SMUx0B_x861C_Txn4TransferLength138_OFFSET 16
-#define SMUx0B_x861C_Txn4TransferLength138_WIDTH 6
-#define SMUx0B_x861C_Txn4TransferLength138_MASK 0x3f0000
-#define SMUx0B_x861C_Txn4Tsize_OFFSET 22
-#define SMUx0B_x861C_Txn4Tsize_WIDTH 2
-#define SMUx0B_x861C_Txn4Tsize_MASK 0xc00000
-#define SMUx0B_x861C_Txn4TransferLength70_OFFSET 24
-#define SMUx0B_x861C_Txn4TransferLength70_WIDTH 8
-#define SMUx0B_x861C_Txn4TransferLength70_MASK 0xff000000
-
-/// SMUx0B_x861C
-typedef union {
- struct { ///<
- UINT32 Txn5Mbusaddr70:8 ; ///<
- UINT32 Txn4Mode:2 ; ///<
- UINT32 Txn4Static:1 ; ///<
- UINT32 Txn4Overlap:1 ; ///<
- UINT32 Txn4Spare:4 ; ///<
- UINT32 Txn4TransferLength138:6 ; ///<
- UINT32 Txn4Tsize:2 ; ///<
- UINT32 Txn4TransferLength70:8 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x861C_STRUCT;
-
-// **** SMUx0B_x8620 Register Definition ****
-// Address
-#define SMUx0B_x8620_ADDRESS 0x8620
-
-// Type
-#define SMUx0B_x8620_TYPE TYPE_SMUx0B
-// Field Data
-#define SMUx0B_x8620_Txn5TransferLength70_OFFSET 0
-#define SMUx0B_x8620_Txn5TransferLength70_WIDTH 8
-#define SMUx0B_x8620_Txn5TransferLength70_MASK 0xff
-#define SMUx0B_x8620_Txn5MBusAddr3124_OFFSET 8
-#define SMUx0B_x8620_Txn5MBusAddr3124_WIDTH 8
-#define SMUx0B_x8620_Txn5MBusAddr3124_MASK 0xff00
-#define SMUx0B_x8620_Txn5MBusAddr2316_OFFSET 16
-#define SMUx0B_x8620_Txn5MBusAddr2316_WIDTH 8
-#define SMUx0B_x8620_Txn5MBusAddr2316_MASK 0xff0000
-#define SMUx0B_x8620_Txn5MBusAddr158_OFFSET 24
-#define SMUx0B_x8620_Txn5MBusAddr158_WIDTH 8
-#define SMUx0B_x8620_Txn5MBusAddr158_MASK 0xff000000
-
-/// SMUx0B_x8620
-typedef union {
- struct { ///<
- UINT32 Txn5TransferLength70:8 ; ///<
- UINT32 Txn5MBusAddr3124:8 ; ///<
- UINT32 Txn5MBusAddr2316:8 ; ///<
- UINT32 Txn5MBusAddr158:8 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x8620_STRUCT;
-
-// **** SMUx0B_x8624 Register Definition ****
-// Address
-#define SMUx0B_x8624_ADDRESS 0x8624
-
-// Type
-#define SMUx0B_x8624_TYPE TYPE_SMUx0B
-// Field Data
-#define SMUx0B_x8624_Txn6MBusAddr158_OFFSET 0
-#define SMUx0B_x8624_Txn6MBusAddr158_WIDTH 8
-#define SMUx0B_x8624_Txn6MBusAddr158_MASK 0xff
-#define SMUx0B_x8624_Txn6MBusAddr70_OFFSET 8
-#define SMUx0B_x8624_Txn6MBusAddr70_WIDTH 8
-#define SMUx0B_x8624_Txn6MBusAddr70_MASK 0xff00
-#define SMUx0B_x8624_Txn5Mode_OFFSET 16
-#define SMUx0B_x8624_Txn5Mode_WIDTH 2
-#define SMUx0B_x8624_Txn5Mode_MASK 0x30000
-#define SMUx0B_x8624_Txn5Static_OFFSET 18
-#define SMUx0B_x8624_Txn5Static_WIDTH 1
-#define SMUx0B_x8624_Txn5Static_MASK 0x40000
-#define SMUx0B_x8624_Txn5Overlap_OFFSET 19
-#define SMUx0B_x8624_Txn5Overlap_WIDTH 1
-#define SMUx0B_x8624_Txn5Overlap_MASK 0x80000
-#define SMUx0B_x8624_Txn5Spare_OFFSET 20
-#define SMUx0B_x8624_Txn5Spare_WIDTH 4
-#define SMUx0B_x8624_Txn5Spare_MASK 0xf00000
-#define SMUx0B_x8624_Txn5TransferLength138_OFFSET 24
-#define SMUx0B_x8624_Txn5TransferLength138_WIDTH 6
-#define SMUx0B_x8624_Txn5TransferLength138_MASK 0x3f000000
-#define SMUx0B_x8624_Txn5Tsize_OFFSET 30
-#define SMUx0B_x8624_Txn5Tsize_WIDTH 2
-#define SMUx0B_x8624_Txn5Tsize_MASK 0xc0000000
-
-/// SMUx0B_x8624
-typedef union {
- struct { ///<
- UINT32 Txn6MBusAddr158:8 ; ///<
- UINT32 Txn6MBusAddr70:8 ; ///<
- UINT32 Txn5Mode:2 ; ///<
- UINT32 Txn5Static:1 ; ///<
- UINT32 Txn5Overlap:1 ; ///<
- UINT32 Txn5Spare:4 ; ///<
- UINT32 Txn5TransferLength138:6 ; ///<
- UINT32 Txn5Tsize:2 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x8624_STRUCT;
-
-// **** SMUx0B_x8628 Register Definition ****
-// Address
-#define SMUx0B_x8628_ADDRESS 0x8628
-
-// Type
-#define SMUx0B_x8628_TYPE TYPE_SMUx0B
-// Field Data
-#define SMUx0B_x8628_Txn6TransferLength138_OFFSET 0
-#define SMUx0B_x8628_Txn6TransferLength138_WIDTH 6
-#define SMUx0B_x8628_Txn6TransferLength138_MASK 0x3f
-#define SMUx0B_x8628_Txn6Tsize_OFFSET 6
-#define SMUx0B_x8628_Txn6Tsize_WIDTH 2
-#define SMUx0B_x8628_Txn6Tsize_MASK 0xc0
-#define SMUx0B_x8628_Txn6TransferLength70_OFFSET 8
-#define SMUx0B_x8628_Txn6TransferLength70_WIDTH 8
-#define SMUx0B_x8628_Txn6TransferLength70_MASK 0xff00
-#define SMUx0B_x8628_Txn6MBusAddr3124_OFFSET 16
-#define SMUx0B_x8628_Txn6MBusAddr3124_WIDTH 8
-#define SMUx0B_x8628_Txn6MBusAddr3124_MASK 0xff0000
-#define SMUx0B_x8628_Txn6MBusAddr2316_OFFSET 24
-#define SMUx0B_x8628_Txn6MBusAddr2316_WIDTH 8
-#define SMUx0B_x8628_Txn6MBusAddr2316_MASK 0xff000000
-
-/// SMUx0B_x8628
-typedef union {
- struct { ///<
- UINT32 Txn6TransferLength138:6 ; ///<
- UINT32 Txn6Tsize:2 ; ///<
- UINT32 Txn6TransferLength70:8 ; ///<
- UINT32 Txn6MBusAddr3124:8 ; ///<
- UINT32 Txn6MBusAddr2316:8 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x8628_STRUCT;
-
-// **** SMUx0B_x862C Register Definition ****
-// Address
-#define SMUx0B_x862C_ADDRESS 0x862c
-
-// Type
-#define SMUx0B_x862C_TYPE TYPE_SMUx0B
-// Field Data
-#define SMUx0B_x862C_Txn7MBusAddr2316_OFFSET 0
-#define SMUx0B_x862C_Txn7MBusAddr2316_WIDTH 8
-#define SMUx0B_x862C_Txn7MBusAddr2316_MASK 0xff
-#define SMUx0B_x862C_Txn7MBusAddr158_OFFSET 8
-#define SMUx0B_x862C_Txn7MBusAddr158_WIDTH 8
-#define SMUx0B_x862C_Txn7MBusAddr158_MASK 0xff00
-#define SMUx0B_x862C_Txn7MBusAddr70_OFFSET 16
-#define SMUx0B_x862C_Txn7MBusAddr70_WIDTH 8
-#define SMUx0B_x862C_Txn7MBusAddr70_MASK 0xff0000
-#define SMUx0B_x862C_Txn6Mode_OFFSET 24
-#define SMUx0B_x862C_Txn6Mode_WIDTH 2
-#define SMUx0B_x862C_Txn6Mode_MASK 0x3000000
-#define SMUx0B_x862C_Txn6Static_OFFSET 26
-#define SMUx0B_x862C_Txn6Static_WIDTH 1
-#define SMUx0B_x862C_Txn6Static_MASK 0x4000000
-#define SMUx0B_x862C_Txn6Overlap_OFFSET 27
-#define SMUx0B_x862C_Txn6Overlap_WIDTH 1
-#define SMUx0B_x862C_Txn6Overlap_MASK 0x8000000
-#define SMUx0B_x862C_Txn6Spare_OFFSET 28
-#define SMUx0B_x862C_Txn6Spare_WIDTH 4
-#define SMUx0B_x862C_Txn6Spare_MASK 0xf0000000
-
-/// SMUx0B_x862C
-typedef union {
- struct { ///<
- UINT32 Txn7MBusAddr2316:8 ; ///<
- UINT32 Txn7MBusAddr158:8 ; ///<
- UINT32 Txn7MBusAddr70:8 ; ///<
- UINT32 Txn6Mode:2 ; ///<
- UINT32 Txn6Static:1 ; ///<
- UINT32 Txn6Overlap:1 ; ///<
- UINT32 Txn6Spare:4 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x862C_STRUCT;
-
-// **** SMUx0B_x8630 Register Definition ****
-// Address
-#define SMUx0B_x8630_ADDRESS 0x8630
-
-// Type
-#define SMUx0B_x8630_TYPE TYPE_SMUx0B
-// Field Data
-#define SMUx0B_x8630_Txn7Mode_OFFSET 0
-#define SMUx0B_x8630_Txn7Mode_WIDTH 2
-#define SMUx0B_x8630_Txn7Mode_MASK 0x3
-#define SMUx0B_x8630_Txn7Static_OFFSET 2
-#define SMUx0B_x8630_Txn7Static_WIDTH 1
-#define SMUx0B_x8630_Txn7Static_MASK 0x4
-#define SMUx0B_x8630_Txn7Overlap_OFFSET 3
-#define SMUx0B_x8630_Txn7Overlap_WIDTH 1
-#define SMUx0B_x8630_Txn7Overlap_MASK 0x8
-#define SMUx0B_x8630_Txn7Spare_OFFSET 4
-#define SMUx0B_x8630_Txn7Spare_WIDTH 4
-#define SMUx0B_x8630_Txn7Spare_MASK 0xf0
-#define SMUx0B_x8630_Txn7TransferLength138_OFFSET 8
-#define SMUx0B_x8630_Txn7TransferLength138_WIDTH 6
-#define SMUx0B_x8630_Txn7TransferLength138_MASK 0x3f00
-#define SMUx0B_x8630_Txn7Tsize_OFFSET 14
-#define SMUx0B_x8630_Txn7Tsize_WIDTH 2
-#define SMUx0B_x8630_Txn7Tsize_MASK 0xc000
-#define SMUx0B_x8630_Txn7TransferLength70_OFFSET 16
-#define SMUx0B_x8630_Txn7TransferLength70_WIDTH 8
-#define SMUx0B_x8630_Txn7TransferLength70_MASK 0xff0000
-#define SMUx0B_x8630_Txn7MBusAddr3124_OFFSET 24
-#define SMUx0B_x8630_Txn7MBusAddr3124_WIDTH 8
-#define SMUx0B_x8630_Txn7MBusAddr3124_MASK 0xff000000
-
-/// SMUx0B_x8630
-typedef union {
- struct { ///<
- UINT32 Txn7Mode:2 ; ///<
- UINT32 Txn7Static:1 ; ///<
- UINT32 Txn7Overlap:1 ; ///<
- UINT32 Txn7Spare:4 ; ///<
- UINT32 Txn7TransferLength138:6 ; ///<
- UINT32 Txn7Tsize:2 ; ///<
- UINT32 Txn7TransferLength70:8 ; ///<
- UINT32 Txn7MBusAddr3124:8 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x8630_STRUCT;
-
-// **** SMUx0B_x8634 Register Definition ****
-// Address
-#define SMUx0B_x8634_ADDRESS 0x8634
-
-// Type
-#define SMUx0B_x8634_TYPE TYPE_SMUx0B
-// Field Data
-#define SMUx0B_x8634_Txn8MBusAddr3124_OFFSET 0
-#define SMUx0B_x8634_Txn8MBusAddr3124_WIDTH 8
-#define SMUx0B_x8634_Txn8MBusAddr3124_MASK 0xff
-#define SMUx0B_x8634_Txn8MBusAddr2316_OFFSET 8
-#define SMUx0B_x8634_Txn8MBusAddr2316_WIDTH 8
-#define SMUx0B_x8634_Txn8MBusAddr2316_MASK 0xff00
-#define SMUx0B_x8634_Txn8MBusAddr158_OFFSET 16
-#define SMUx0B_x8634_Txn8MBusAddr158_WIDTH 8
-#define SMUx0B_x8634_Txn8MBusAddr158_MASK 0xff0000
-#define SMUx0B_x8634_Txn8MBusAddr70_OFFSET 24
-#define SMUx0B_x8634_Txn8MBusAddr70_WIDTH 8
-#define SMUx0B_x8634_Txn8MBusAddr70_MASK 0xff000000
-
-/// SMUx0B_x8634
-typedef union {
- struct { ///<
- UINT32 Txn8MBusAddr3124:8 ; ///<
- UINT32 Txn8MBusAddr2316:8 ; ///<
- UINT32 Txn8MBusAddr158:8 ; ///<
- UINT32 Txn8MBusAddr70:8 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x8634_STRUCT;
-
-// **** SMUx0B_x8638 Register Definition ****
-// Address
-#define SMUx0B_x8638_ADDRESS 0x8638
-
-// Type
-#define SMUx0B_x8638_TYPE TYPE_SMUx0B
-// Field Data
-#define SMUx0B_x8638_Txn9MBusAddr70_OFFSET 0
-#define SMUx0B_x8638_Txn9MBusAddr70_WIDTH 8
-#define SMUx0B_x8638_Txn9MBusAddr70_MASK 0xff
-#define SMUx0B_x8638_Txn8Mode_OFFSET 8
-#define SMUx0B_x8638_Txn8Mode_WIDTH 2
-#define SMUx0B_x8638_Txn8Mode_MASK 0x300
-#define SMUx0B_x8638_Txn8Static_OFFSET 10
-#define SMUx0B_x8638_Txn8Static_WIDTH 1
-#define SMUx0B_x8638_Txn8Static_MASK 0x400
-#define SMUx0B_x8638_Txn8Overlap_OFFSET 11
-#define SMUx0B_x8638_Txn8Overlap_WIDTH 1
-#define SMUx0B_x8638_Txn8Overlap_MASK 0x800
-#define SMUx0B_x8638_Txn8Spare_OFFSET 12
-#define SMUx0B_x8638_Txn8Spare_WIDTH 4
-#define SMUx0B_x8638_Txn8Spare_MASK 0xf000
-#define SMUx0B_x8638_Txn8TransferLength138_OFFSET 16
-#define SMUx0B_x8638_Txn8TransferLength138_WIDTH 6
-#define SMUx0B_x8638_Txn8TransferLength138_MASK 0x3f0000
-#define SMUx0B_x8638_Txn8Tsize_OFFSET 22
-#define SMUx0B_x8638_Txn8Tsize_WIDTH 2
-#define SMUx0B_x8638_Txn8Tsize_MASK 0xc00000
-#define SMUx0B_x8638_Txn8TransferLength70_OFFSET 24
-#define SMUx0B_x8638_Txn8TransferLength70_WIDTH 8
-#define SMUx0B_x8638_Txn8TransferLength70_MASK 0xff000000
-
-/// SMUx0B_x8638
-typedef union {
- struct { ///<
- UINT32 Txn9MBusAddr70:8 ; ///<
- UINT32 Txn8Mode:2 ; ///<
- UINT32 Txn8Static:1 ; ///<
- UINT32 Txn8Overlap:1 ; ///<
- UINT32 Txn8Spare:4 ; ///<
- UINT32 Txn8TransferLength138:6 ; ///<
- UINT32 Txn8Tsize:2 ; ///<
- UINT32 Txn8TransferLength70:8 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x8638_STRUCT;
-
-// **** SMUx0B_x863C Register Definition ****
-// Address
-#define SMUx0B_x863C_ADDRESS 0x863c
-
-// Type
-#define SMUx0B_x863C_TYPE TYPE_SMUx0B
-// Field Data
-#define SMUx0B_x863C_Txn9TransferLength70_OFFSET 0
-#define SMUx0B_x863C_Txn9TransferLength70_WIDTH 8
-#define SMUx0B_x863C_Txn9TransferLength70_MASK 0xff
-#define SMUx0B_x863C_Txn9MBusAddr3124_OFFSET 8
-#define SMUx0B_x863C_Txn9MBusAddr3124_WIDTH 8
-#define SMUx0B_x863C_Txn9MBusAddr3124_MASK 0xff00
-#define SMUx0B_x863C_Txn9MBuAaddr2316_OFFSET 16
-#define SMUx0B_x863C_Txn9MBuAaddr2316_WIDTH 8
-#define SMUx0B_x863C_Txn9MBuAaddr2316_MASK 0xff0000
-#define SMUx0B_x863C_Txn9MBusAddr158_OFFSET 24
-#define SMUx0B_x863C_Txn9MBusAddr158_WIDTH 8
-#define SMUx0B_x863C_Txn9MBusAddr158_MASK 0xff000000
-
-/// SMUx0B_x863C
-typedef union {
- struct { ///<
- UINT32 Txn9TransferLength70:8 ; ///<
- UINT32 Txn9MBusAddr3124:8 ; ///<
- UINT32 Txn9MBuAaddr2316:8 ; ///<
- UINT32 Txn9MBusAddr158:8 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x863C_STRUCT;
-
-// **** SMUx0B_x8640 Register Definition ****
-// Address
-#define SMUx0B_x8640_ADDRESS 0x8640
-
-// Type
-#define SMUx0B_x8640_TYPE TYPE_SMUx0B
-// Field Data
-#define SMUx0B_x8640_Txn10MBusAddr158_OFFSET 0
-#define SMUx0B_x8640_Txn10MBusAddr158_WIDTH 8
-#define SMUx0B_x8640_Txn10MBusAddr158_MASK 0xff
-#define SMUx0B_x8640_Txn10MBusAddr70_OFFSET 8
-#define SMUx0B_x8640_Txn10MBusAddr70_WIDTH 8
-#define SMUx0B_x8640_Txn10MBusAddr70_MASK 0xff00
-#define SMUx0B_x8640_Txn9Mode_OFFSET 16
-#define SMUx0B_x8640_Txn9Mode_WIDTH 2
-#define SMUx0B_x8640_Txn9Mode_MASK 0x30000
-#define SMUx0B_x8640_Txn9Static_OFFSET 18
-#define SMUx0B_x8640_Txn9Static_WIDTH 1
-#define SMUx0B_x8640_Txn9Static_MASK 0x40000
-#define SMUx0B_x8640_Txn9Overlap_OFFSET 19
-#define SMUx0B_x8640_Txn9Overlap_WIDTH 1
-#define SMUx0B_x8640_Txn9Overlap_MASK 0x80000
-#define SMUx0B_x8640_Txn9Spare_OFFSET 20
-#define SMUx0B_x8640_Txn9Spare_WIDTH 4
-#define SMUx0B_x8640_Txn9Spare_MASK 0xf00000
-#define SMUx0B_x8640_Txn9TransferLength138_OFFSET 24
-#define SMUx0B_x8640_Txn9TransferLength138_WIDTH 6
-#define SMUx0B_x8640_Txn9TransferLength138_MASK 0x3f000000
-#define SMUx0B_x8640_Txn9Tsize_OFFSET 30
-#define SMUx0B_x8640_Txn9Tsize_WIDTH 2
-#define SMUx0B_x8640_Txn9Tsize_MASK 0xc0000000
-
-/// SMUx0B_x8640
-typedef union {
- struct { ///<
- UINT32 Txn10MBusAddr158:8 ; ///<
- UINT32 Txn10MBusAddr70:8 ; ///<
- UINT32 Txn9Mode:2 ; ///<
- UINT32 Txn9Static:1 ; ///<
- UINT32 Txn9Overlap:1 ; ///<
- UINT32 Txn9Spare:4 ; ///<
- UINT32 Txn9TransferLength138:6 ; ///<
- UINT32 Txn9Tsize:2 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x8640_STRUCT;
-
-// **** SMUx0B_x8650 Register Definition ****
-// Address
-#define SMUx0B_x8650_ADDRESS 0x8650
-
-// Type
-#define SMUx0B_x8650_TYPE TYPE_SMUx0B
-// Field Data
-#define SMUx0B_x8650_Data_OFFSET 0
-#define SMUx0B_x8650_Data_WIDTH 32
-#define SMUx0B_x8650_Data_MASK 0xffffffff
-
-/// SMUx0B_x8650
-typedef union {
- struct { ///<
- UINT32 Data:32; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x8650_STRUCT;
-
-// **** SMUx0B_x8654 Register Definition ****
-// Address
-#define SMUx0B_x8654_ADDRESS 0x8654
-
-// Type
-#define SMUx0B_x8654_TYPE TYPE_SMUx0B
-// Field Data
-#define SMUx0B_x8654_Data_OFFSET 0
-#define SMUx0B_x8654_Data_WIDTH 32
-#define SMUx0B_x8654_Data_MASK 0xffffffff
-
-/// SMUx0B_x8654
-typedef union {
- struct { ///<
- UINT32 Data:32; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x8654_STRUCT;
-
-// **** SMUx0B_x8658 Register Definition ****
-// Address
-#define SMUx0B_x8658_ADDRESS 0x8658
-
-// Type
-#define SMUx0B_x8658_TYPE TYPE_SMUx0B
-// Field Data
-#define SMUx0B_x8658_Data_OFFSET 0
-#define SMUx0B_x8658_Data_WIDTH 32
-#define SMUx0B_x8658_Data_MASK 0xffffffff
-
-/// SMUx0B_x8658
-typedef union {
- struct { ///<
- UINT32 Data:32; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x8658_STRUCT;
-
-// **** SMUx0B_x865C Register Definition ****
-// Address
-#define SMUx0B_x865C_ADDRESS 0x865c
-
-// Type
-#define SMUx0B_x865C_TYPE TYPE_SMUx0B
-// Field Data
-#define SMUx0B_x865C_Data_OFFSET 0
-#define SMUx0B_x865C_Data_WIDTH 32
-#define SMUx0B_x865C_Data_MASK 0xffffffff
-
-/// SMUx0B_x865C
-typedef union {
- struct { ///<
- UINT32 Data:32; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x865C_STRUCT;
-
-// **** SMUx0B_x8660 Register Definition ****
-// Address
-#define SMUx0B_x8660_ADDRESS 0x8660
-
-// Type
-#define SMUx0B_x8660_TYPE TYPE_SMUx0B
-// Field Data
-#define SMUx0B_x8660_Data_OFFSET 0
-#define SMUx0B_x8660_Data_WIDTH 32
-#define SMUx0B_x8660_Data_MASK 0xffffffff
-
-/// SMUx0B_x8660
-typedef union {
- struct { ///<
- UINT32 Data:32; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x8660_STRUCT;
-
-// **** SMUx0B_x8664 Register Definition ****
-// Address
-#define SMUx0B_x8664_ADDRESS 0x8664
-
-// Type
-#define SMUx0B_x8664_TYPE TYPE_SMUx0B
-// Field Data
-#define SMUx0B_x8664_Data_OFFSET 0
-#define SMUx0B_x8664_Data_WIDTH 32
-#define SMUx0B_x8664_Data_MASK 0xffffffff
-
-/// SMUx0B_x8664
-typedef union {
- struct { ///<
- UINT32 Data:32; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x8664_STRUCT;
-
-// **** SMUx0B_x8668 Register Definition ****
-// Address
-#define SMUx0B_x8668_ADDRESS 0x8668
-
-// Type
-#define SMUx0B_x8668_TYPE TYPE_SMUx0B
-// Field Data
-#define SMUx0B_x8668_Data_OFFSET 0
-#define SMUx0B_x8668_Data_WIDTH 32
-#define SMUx0B_x8668_Data_MASK 0xffffffff
-
-/// SMUx0B_x8668
-typedef union {
- struct { ///<
- UINT32 Data:32; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x8668_STRUCT;
-
-// **** SMUx0B_x866C Register Definition ****
-// Address
-#define SMUx0B_x866C_ADDRESS 0x866c
-
-// Type
-#define SMUx0B_x866C_TYPE TYPE_SMUx0B
-// Field Data
-#define SMUx0B_x866C_Data_OFFSET 0
-#define SMUx0B_x866C_Data_WIDTH 32
-#define SMUx0B_x866C_Data_MASK 0xffffffff
-
-/// SMUx0B_x866C
-typedef union {
- struct { ///<
- UINT32 Data:32; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x866C_STRUCT;
-
-// **** SMUx0B_x8670 Register Definition ****
-// Address
-#define SMUx0B_x8670_ADDRESS 0x8670
-
-// Type
-#define SMUx0B_x8670_TYPE TYPE_SMUx0B
-// Field Data
-#define SMUx0B_x8670_Data_OFFSET 0
-#define SMUx0B_x8670_Data_WIDTH 32
-#define SMUx0B_x8670_Data_MASK 0xffffffff
-
-/// SMUx0B_x8670
-typedef union {
- struct { ///<
- UINT32 Data:32; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x8670_STRUCT;
-
-// **** SMUx0B_x8674 Register Definition ****
-// Address
-#define SMUx0B_x8674_ADDRESS 0x8674
-
-// Type
-#define SMUx0B_x8674_TYPE TYPE_SMUx0B
-// Field Data
-#define SMUx0B_x8674_Data_OFFSET 0
-#define SMUx0B_x8674_Data_WIDTH 32
-#define SMUx0B_x8674_Data_MASK 0xffffffff
-
-/// SMUx0B_x8674
-typedef union {
- struct { ///<
- UINT32 Data:32; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x8674_STRUCT;
-
-// **** SMUx0B_x8678 Register Definition ****
-// Address
-#define SMUx0B_x8678_ADDRESS 0x8678
-
-// Type
-#define SMUx0B_x8678_TYPE TYPE_SMUx0B
-// Field Data
-#define SMUx0B_x8678_Data_OFFSET 0
-#define SMUx0B_x8678_Data_WIDTH 32
-#define SMUx0B_x8678_Data_MASK 0xffffffff
-
-/// SMUx0B_x8678
-typedef union {
- struct { ///<
- UINT32 Data:32; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x8678_STRUCT;
-
-// **** SMUx0B_x867C Register Definition ****
-// Address
-#define SMUx0B_x867C_ADDRESS 0x867c
-
-// Type
-#define SMUx0B_x867C_TYPE TYPE_SMUx0B
-// Field Data
-#define SMUx0B_x867C_Data_OFFSET 0
-#define SMUx0B_x867C_Data_WIDTH 32
-#define SMUx0B_x867C_Data_MASK 0xffffffff
-
-/// SMUx0B_x867C
-typedef union {
- struct { ///<
- UINT32 Data:32; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x867C_STRUCT;
-
-// **** SMUx0B_x8680 Register Definition ****
-// Address
-#define SMUx0B_x8680_ADDRESS 0x8680
-
-// Type
-#define SMUx0B_x8680_TYPE TYPE_SMUx0B
-// Field Data
-#define SMUx0B_x8680_Data_OFFSET 0
-#define SMUx0B_x8680_Data_WIDTH 32
-#define SMUx0B_x8680_Data_MASK 0xffffffff
-
-/// SMUx0B_x8680
-typedef union {
- struct { ///<
- UINT32 Data:32; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x8680_STRUCT;
-
-// **** SMUx0B_x8684 Register Definition ****
-// Address
-#define SMUx0B_x8684_ADDRESS 0x8684
-
-// Type
-#define SMUx0B_x8684_TYPE TYPE_SMUx0B
-// Field Data
-#define SMUx0B_x8684_Data_OFFSET 0
-#define SMUx0B_x8684_Data_WIDTH 32
-#define SMUx0B_x8684_Data_MASK 0xffffffff
-
-/// SMUx0B_x8684
-typedef union {
- struct { ///<
- UINT32 Data:32; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x8684_STRUCT;
-
-// **** SMUx0B_x8688 Register Definition ****
-// Address
-#define SMUx0B_x8688_ADDRESS 0x8688
-
-// Type
-#define SMUx0B_x8688_TYPE TYPE_SMUx0B
-// Field Data
-#define SMUx0B_x8688_Data_OFFSET 0
-#define SMUx0B_x8688_Data_WIDTH 32
-#define SMUx0B_x8688_Data_MASK 0xffffffff
-
-/// SMUx0B_x8688
-typedef union {
- struct { ///<
- UINT32 Data:32; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x8688_STRUCT;
-
-// **** SMUx0B_x868C Register Definition ****
-// Address
-#define SMUx0B_x868C_ADDRESS 0x868c
-
-// Type
-#define SMUx0B_x868C_TYPE TYPE_SMUx0B
-// Field Data
-#define SMUx0B_x868C_Data_OFFSET 0
-#define SMUx0B_x868C_Data_WIDTH 32
-#define SMUx0B_x868C_Data_MASK 0xffffffff
-
-/// SMUx0B_x868C
-typedef union {
- struct { ///<
- UINT32 Data:32; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x868C_STRUCT;
-
-// **** SMUx0B_x8690 Register Definition ****
-// Address
-#define SMUx0B_x8690_ADDRESS 0x8690
-
-// Type
-#define SMUx0B_x8690_TYPE TYPE_SMUx0B
-// Field Data
-#define SMUx0B_x8690_Data_OFFSET 0
-#define SMUx0B_x8690_Data_WIDTH 32
-#define SMUx0B_x8690_Data_MASK 0xffffffff
-
-/// SMUx0B_x8690
-typedef union {
- struct { ///<
- UINT32 Data:32; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x8690_STRUCT;
-
-// **** SMUx0B_x8694 Register Definition ****
-// Address
-#define SMUx0B_x8694_ADDRESS 0x8694
-
-// Type
-#define SMUx0B_x8694_TYPE TYPE_SMUx0B
-// Field Data
-#define SMUx0B_x8694_Data_OFFSET 0
-#define SMUx0B_x8694_Data_WIDTH 32
-#define SMUx0B_x8694_Data_MASK 0xffffffff
-
-/// SMUx0B_x8694
-typedef union {
- struct { ///<
- UINT32 Data:32; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x8694_STRUCT;
-
-// **** SMUx0B_x8698 Register Definition ****
-// Address
-#define SMUx0B_x8698_ADDRESS 0x8698
-
-// Type
-#define SMUx0B_x8698_TYPE TYPE_SMUx0B
-// Field Data
-#define SMUx0B_x8698_Data_OFFSET 0
-#define SMUx0B_x8698_Data_WIDTH 32
-#define SMUx0B_x8698_Data_MASK 0xffffffff
-
-/// SMUx0B_x8698
-typedef union {
- struct { ///<
- UINT32 Data:32; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x8698_STRUCT;
-
-// **** SMUx0B_x869C Register Definition ****
-// Address
-#define SMUx0B_x869C_ADDRESS 0x869c
-
-// Type
-#define SMUx0B_x869C_TYPE TYPE_SMUx0B
-// Field Data
-#define SMUx0B_x869C_Data_OFFSET 0
-#define SMUx0B_x869C_Data_WIDTH 32
-#define SMUx0B_x869C_Data_MASK 0xffffffff
-
-/// SMUx0B_x869C
-typedef union {
- struct { ///<
- UINT32 Data:32; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x869C_STRUCT;
-
-// **** SMUx0B_x86A0 Register Definition ****
-// Address
-#define SMUx0B_x86A0_ADDRESS 0x86a0
-
-// Type
-#define SMUx0B_x86A0_TYPE TYPE_SMUx0B
-// Field Data
-#define SMUx0B_x86A0_Data_OFFSET 0
-#define SMUx0B_x86A0_Data_WIDTH 32
-#define SMUx0B_x86A0_Data_MASK 0xffffffff
-
-/// SMUx0B_x86A0
-typedef union {
- struct { ///<
- UINT32 Data:32; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x86A0_STRUCT;
-
-// **** GMMx00 Register Definition ****
-// Address
-#define GMMx00_ADDRESS 0x0
-
-// Type
-#define GMMx00_TYPE TYPE_GMM
-// Field Data
-#define GMMx00_Offset_OFFSET 0
-#define GMMx00_Offset_WIDTH 31
-#define GMMx00_Offset_MASK 0x7fffffff
-#define GMMx00_Aper_OFFSET 31
-#define GMMx00_Aper_WIDTH 1
-#define GMMx00_Aper_MASK 0x80000000
-
-/// GMMx00
-typedef union {
- struct { ///<
- UINT32 Offset:31; ///<
- UINT32 Aper:1 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx00_STRUCT;
-
-// **** GMMx04 Register Definition ****
-// Address
-#define GMMx04_ADDRESS 0x4
-
-// Type
-#define GMMx04_TYPE TYPE_GMM
-// Field Data
-#define GMMx04_Data_OFFSET 0
-#define GMMx04_Data_WIDTH 32
-#define GMMx04_Data_MASK 0xffffffff
-
-/// GMMx04
-typedef union {
- struct { ///<
- UINT32 Data:32; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx04_STRUCT;
-
-// **** GMMx770 Register Definition ****
-// Address
-#define GMMx770_ADDRESS 0x770
-
-// Type
-#define GMMx770_TYPE TYPE_GMM
-// Field Data
-#define GMMx770_VoltageChangeReq_OFFSET 0
-#define GMMx770_VoltageChangeReq_WIDTH 1
-#define GMMx770_VoltageChangeReq_MASK 0x1
-#define GMMx770_VoltageLevel_OFFSET 1
-#define GMMx770_VoltageLevel_WIDTH 2
-#define GMMx770_VoltageLevel_MASK 0x6
-#define GMMx770_VoltageChangeEn_OFFSET 3
-#define GMMx770_VoltageChangeEn_WIDTH 1
-#define GMMx770_VoltageChangeEn_MASK 0x8
-#define GMMx770_VoltageForceEn_OFFSET 4
-#define GMMx770_VoltageForceEn_WIDTH 1
-#define GMMx770_VoltageForceEn_MASK 0x10
-#define GMMx770_Reserved_31_5_OFFSET 5
-#define GMMx770_Reserved_31_5_WIDTH 27
-#define GMMx770_Reserved_31_5_MASK 0xffffffe0
-
-/// GMMx770
-typedef union {
- struct { ///<
- UINT32 VoltageChangeReq:1 ; ///<
- UINT32 VoltageLevel:2 ; ///<
- UINT32 VoltageChangeEn:1 ; ///<
- UINT32 VoltageForceEn:1 ; ///<
- UINT32 Reserved_31_5:27; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx770_STRUCT;
-
-// **** GMMx774 Register Definition ****
-// Address
-#define GMMx774_ADDRESS 0x774
-
-// Type
-#define GMMx774_TYPE TYPE_GMM
-// Field Data
-#define GMMx774_VoltageChangeAck_OFFSET 0
-#define GMMx774_VoltageChangeAck_WIDTH 1
-#define GMMx774_VoltageChangeAck_MASK 0x1
-#define GMMx774_CurrentVoltageLevel_OFFSET 1
-#define GMMx774_CurrentVoltageLevel_WIDTH 2
-#define GMMx774_CurrentVoltageLevel_MASK 0x6
-#define GMMx774_Reserved_31_3_OFFSET 3
-#define GMMx774_Reserved_31_3_WIDTH 29
-#define GMMx774_Reserved_31_3_MASK 0xfffffff8
-
-/// GMMx774
-typedef union {
- struct { ///<
- UINT32 VoltageChangeAck:1 ; ///<
- UINT32 CurrentVoltageLevel:2 ; ///<
- UINT32 Reserved_31_3:29; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx774_STRUCT;
-
-// **** GMMx15C0 Register Definition ****
-// Address
-#define GMMx15C0_ADDRESS 0x15c0
-
-// Type
-#define GMMx15C0_TYPE TYPE_GMM
-// Field Data
-#define GMMx15C0_Reserved_17_0_OFFSET 0
-#define GMMx15C0_Reserved_17_0_WIDTH 18
-#define GMMx15C0_Reserved_17_0_MASK 0x3ffff
-#define GMMx15C0_Enable_OFFSET 18
-#define GMMx15C0_Enable_WIDTH 1
-#define GMMx15C0_Enable_MASK 0x40000
-#define GMMx15C0_Reserved_31_19_OFFSET 19
-#define GMMx15C0_Reserved_31_19_WIDTH 13
-#define GMMx15C0_Reserved_31_19_MASK 0xfff80000
-
-/// GMMx15C0
-typedef union {
- struct { ///<
- UINT32 Reserved_17_0:18; ///<
- UINT32 Enable:1 ; ///<
- UINT32 Reserved_31_19:13; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx15C0_STRUCT;
-
-// **** GMMx2014 Register Definition ****
-// Address
-#define GMMx2014_ADDRESS 0x2014
-
-// Type
-#define GMMx2014_TYPE TYPE_GMM
-// Field Data
-#define GMMx2014_Rlc_OFFSET 0
-#define GMMx2014_Rlc_WIDTH 4
-#define GMMx2014_Rlc_MASK 0xf
-#define GMMx2014_Vmc_OFFSET 4
-#define GMMx2014_Vmc_WIDTH 4
-#define GMMx2014_Vmc_MASK 0xf0
-#define GMMx2014_Dmif_OFFSET 8
-#define GMMx2014_Dmif_WIDTH 4
-#define GMMx2014_Dmif_MASK 0xf00
-#define GMMx2014_Mcif_OFFSET 12
-#define GMMx2014_Mcif_WIDTH 4
-#define GMMx2014_Mcif_MASK 0xf000
-#define GMMx2014_Reserved_31_16_OFFSET 16
-#define GMMx2014_Reserved_31_16_WIDTH 16
-#define GMMx2014_Reserved_31_16_MASK 0xffff0000
-
-/// GMMx2014
-typedef union {
- struct { ///<
- UINT32 Rlc:4 ; ///<
- UINT32 Vmc:4 ; ///<
- UINT32 Dmif:4 ; ///<
- UINT32 Mcif:4 ; ///<
- UINT32 Reserved_31_16:16; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx2014_STRUCT;
-
-// **** GMMx2018 Register Definition ****
-// Address
-#define GMMx2018_ADDRESS 0x2018
-
-// Type
-#define GMMx2018_TYPE TYPE_GMM
-// Field Data
-#define GMMx2018_Ih_OFFSET 0
-#define GMMx2018_Ih_WIDTH 4
-#define GMMx2018_Ih_MASK 0xf
-#define GMMx2018_Mcif_OFFSET 4
-#define GMMx2018_Mcif_WIDTH 4
-#define GMMx2018_Mcif_MASK 0xf0
-#define GMMx2018_Rlc_OFFSET 8
-#define GMMx2018_Rlc_WIDTH 4
-#define GMMx2018_Rlc_MASK 0xf00
-#define GMMx2018_Vip_OFFSET 12
-#define GMMx2018_Vip_WIDTH 4
-#define GMMx2018_Vip_MASK 0xf000
-#define GMMx2018_Reserved_31_16_OFFSET 16
-#define GMMx2018_Reserved_31_16_WIDTH 16
-#define GMMx2018_Reserved_31_16_MASK 0xffff0000
-
-/// GMMx2018
-typedef union {
- struct { ///<
- UINT32 Ih:4 ; ///<
- UINT32 Mcif:4 ; ///<
- UINT32 Rlc:4 ; ///<
- UINT32 Vip:4 ; ///<
- UINT32 Reserved_31_16:16; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx2018_STRUCT;
-
-// **** GMMx2020 Register Definition ****
-// Address
-#define GMMx2020_ADDRESS 0x2020
-
-// Type
-#define GMMx2020_TYPE TYPE_GMM
-// Field Data
-#define GMMx2020_UvdExt0_OFFSET 0
-#define GMMx2020_UvdExt0_WIDTH 4
-#define GMMx2020_UvdExt0_MASK 0xf
-#define GMMx2020_DrmDma_OFFSET 4
-#define GMMx2020_DrmDma_WIDTH 4
-#define GMMx2020_DrmDma_MASK 0xf0
-#define GMMx2020_Hdp_OFFSET 8
-#define GMMx2020_Hdp_WIDTH 4
-#define GMMx2020_Hdp_MASK 0xf00
-#define GMMx2020_Sem_OFFSET 12
-#define GMMx2020_Sem_WIDTH 4
-#define GMMx2020_Sem_MASK 0xf000
-#define GMMx2020_Umc_OFFSET 16
-#define GMMx2020_Umc_WIDTH 4
-#define GMMx2020_Umc_MASK 0xf0000
-#define GMMx2020_Uvd_OFFSET 20
-#define GMMx2020_Uvd_WIDTH 4
-#define GMMx2020_Uvd_MASK 0xf00000
-#define GMMx2020_Xdp_OFFSET 24
-#define GMMx2020_Xdp_WIDTH 4
-#define GMMx2020_Xdp_MASK 0xf000000
-#define GMMx2020_UvdExt1_OFFSET 28
-#define GMMx2020_UvdExt1_WIDTH 4
-#define GMMx2020_UvdExt1_MASK 0xf0000000
-
-/// GMMx2020
-typedef union {
- struct { ///<
- UINT32 UvdExt0:4 ; ///<
- UINT32 DrmDma:4 ; ///<
- UINT32 Hdp:4 ; ///<
- UINT32 Sem:4 ; ///<
- UINT32 Umc:4 ; ///<
- UINT32 Uvd:4 ; ///<
- UINT32 Xdp:4 ; ///<
- UINT32 UvdExt1:4 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx2020_STRUCT;
-
-// **** GMMx2024 Register Definition ****
-// Address
-#define GMMx2024_ADDRESS 0x2024
-
-// Type
-#define GMMx2024_TYPE TYPE_GMM
-// Field Data
-#define GMMx2024_Base_OFFSET 0
-#define GMMx2024_Base_WIDTH 16
-#define GMMx2024_Base_MASK 0xffff
-#define GMMx2024_Top_OFFSET 16
-#define GMMx2024_Top_WIDTH 16
-#define GMMx2024_Top_MASK 0xffff0000
-
-/// GMMx2024
-typedef union {
- struct { ///<
- UINT32 Base:16; ///<
- UINT32 Top:16; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx2024_STRUCT;
-
-// **** GMMx2028 Register Definition ****
-// Address
-#define GMMx2028_ADDRESS 0x2028
-
-// Type
-#define GMMx2028_TYPE TYPE_GMM
-// Field Data
-#define GMMx2028_SysTop_39_22__OFFSET 0
-#define GMMx2028_SysTop_39_22__WIDTH 18
-#define GMMx2028_SysTop_39_22__MASK 0x3ffff
-#define GMMx2028_Reserved_31_18_OFFSET 18
-#define GMMx2028_Reserved_31_18_WIDTH 14
-#define GMMx2028_Reserved_31_18_MASK 0xfffc0000
-
-/// GMMx2028
-typedef union {
- struct { ///<
- UINT32 SysTop_39_22_:18; ///<
- UINT32 Reserved_31_18:14; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx2028_STRUCT;
-
-// **** GMMx202C Register Definition ****
-// Address
-#define GMMx202C_ADDRESS 0x202c
-
-// Type
-#define GMMx202C_TYPE TYPE_GMM
-// Field Data
-#define GMMx202C_SysBot_39_22__OFFSET 0
-#define GMMx202C_SysBot_39_22__WIDTH 18
-#define GMMx202C_SysBot_39_22__MASK 0x3ffff
-#define GMMx202C_Reserved_31_18_OFFSET 18
-#define GMMx202C_Reserved_31_18_WIDTH 14
-#define GMMx202C_Reserved_31_18_MASK 0xfffc0000
-
-/// GMMx202C
-typedef union {
- struct { ///<
- UINT32 SysBot_39_22_:18; ///<
- UINT32 Reserved_31_18:14; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx202C_STRUCT;
-
-// **** GMMx20B4 Register Definition ****
-// Address
-#define GMMx20B4_ADDRESS 0x20b4
-
-// Type
-#define GMMx20B4_TYPE TYPE_GMM
-// Field Data
-#define GMMx20B4_StutterMode_OFFSET 0
-#define GMMx20B4_StutterMode_WIDTH 2
-#define GMMx20B4_StutterMode_MASK 0x3
-#define GMMx20B4_GateOverride_OFFSET 2
-#define GMMx20B4_GateOverride_WIDTH 1
-#define GMMx20B4_GateOverride_MASK 0x4
-#define GMMx20B4_Reserved_31_3_OFFSET 3
-#define GMMx20B4_Reserved_31_3_WIDTH 29
-#define GMMx20B4_Reserved_31_3_MASK 0xfffffff8
-
-/// GMMx20B4
-typedef union {
- struct { ///<
- UINT32 StutterMode:2 ; ///<
- UINT32 GateOverride:1 ; ///<
- UINT32 Reserved_31_3:29; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx20B4_STRUCT;
-
-// **** GMMx20B8 Register Definition ****
-// Address
-#define GMMx20B8_ADDRESS 0x20b8
-
-// Type
-#define GMMx20B8_TYPE TYPE_GMM
-// Field Data
-#define GMMx20B8_Reserved_17_0_OFFSET 0
-#define GMMx20B8_Reserved_17_0_WIDTH 18
-#define GMMx20B8_Reserved_17_0_MASK 0x3ffff
-#define GMMx20B8_Enable_OFFSET 18
-#define GMMx20B8_Enable_WIDTH 1
-#define GMMx20B8_Enable_MASK 0x40000
-#define GMMx20B8_Reserved_31_19_OFFSET 19
-#define GMMx20B8_Reserved_31_19_WIDTH 13
-#define GMMx20B8_Reserved_31_19_MASK 0xfff80000
-
-/// GMMx20B8
-typedef union {
- struct { ///<
- UINT32 Reserved_17_0:18; ///<
- UINT32 Enable:1 ; ///<
- UINT32 Reserved_31_19:13; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx20B8_STRUCT;
-
-// **** GMMx20BC Register Definition ****
-// Address
-#define GMMx20BC_ADDRESS 0x20bc
-
-// Type
-#define GMMx20BC_TYPE TYPE_GMM
-// Field Data
-#define GMMx20BC_Reserved_17_0_OFFSET 0
-#define GMMx20BC_Reserved_17_0_WIDTH 18
-#define GMMx20BC_Reserved_17_0_MASK 0x3ffff
-#define GMMx20BC_Enable_OFFSET 18
-#define GMMx20BC_Enable_WIDTH 1
-#define GMMx20BC_Enable_MASK 0x40000
-#define GMMx20BC_Reserved_31_19_OFFSET 19
-#define GMMx20BC_Reserved_31_19_WIDTH 13
-#define GMMx20BC_Reserved_31_19_MASK 0xfff80000
-
-/// GMMx20BC
-typedef union {
- struct { ///<
- UINT32 Reserved_17_0:18; ///<
- UINT32 Enable:1 ; ///<
- UINT32 Reserved_31_19:13; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx20BC_STRUCT;
-
-// **** GMMx20C0 Register Definition ****
-// Address
-#define GMMx20C0_ADDRESS 0x20c0
-
-// Type
-#define GMMx20C0_TYPE TYPE_GMM
-// Field Data
-#define GMMx20C0_Reserved_17_0_OFFSET 0
-#define GMMx20C0_Reserved_17_0_WIDTH 18
-#define GMMx20C0_Reserved_17_0_MASK 0x3ffff
-#define GMMx20C0_Enable_OFFSET 18
-#define GMMx20C0_Enable_WIDTH 1
-#define GMMx20C0_Enable_MASK 0x40000
-#define GMMx20C0_Reserved_31_19_OFFSET 19
-#define GMMx20C0_Reserved_31_19_WIDTH 13
-#define GMMx20C0_Reserved_31_19_MASK 0xfff80000
-
-/// GMMx20C0
-typedef union {
- struct { ///<
- UINT32 Reserved_17_0:18; ///<
- UINT32 Enable:1 ; ///<
- UINT32 Reserved_31_19:13; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx20C0_STRUCT;
-
-// **** GMMx20D4 Register Definition ****
-// Address
-#define GMMx20D4_ADDRESS 0x20d4
-
-// Type
-#define GMMx20D4_TYPE TYPE_GMM
-// Field Data
-#define GMMx20D4_LocalBlackout_OFFSET 0
-#define GMMx20D4_LocalBlackout_WIDTH 1
-#define GMMx20D4_LocalBlackout_MASK 0x1
-#define GMMx20D4_Reserved_31_1_OFFSET 1
-#define GMMx20D4_Reserved_31_1_WIDTH 31
-#define GMMx20D4_Reserved_31_1_MASK 0xfffffffe
-
-/// GMMx20D4
-typedef union {
- struct { ///<
- UINT32 LocalBlackout:1 ; ///<
- UINT32 Reserved_31_1:31; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx20D4_STRUCT;
-
-// **** GMMx20EC Register Definition ****
-// Address
-#define GMMx20EC_ADDRESS 0x20ec
-
-// Type
-#define GMMx20EC_TYPE TYPE_GMM
-// Field Data
-#define GMMx20EC_RemoteBlackout_OFFSET 0
-#define GMMx20EC_RemoteBlackout_WIDTH 1
-#define GMMx20EC_RemoteBlackout_MASK 0x1
-#define GMMx20EC_LocalBlackout_OFFSET 1
-#define GMMx20EC_LocalBlackout_WIDTH 1
-#define GMMx20EC_LocalBlackout_MASK 0x2
-#define GMMx20EC_Reserved_31_2_OFFSET 2
-#define GMMx20EC_Reserved_31_2_WIDTH 30
-#define GMMx20EC_Reserved_31_2_MASK 0xfffffffc
-
-/// GMMx20EC
-typedef union {
- struct { ///<
- UINT32 RemoteBlackout:1 ; ///<
- UINT32 LocalBlackout:1 ; ///<
- UINT32 Reserved_31_2:30; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx20EC_STRUCT;
-
-// **** GMMx21A4 Register Definition ****
-// Address
-#define GMMx21A4_ADDRESS 0x21a4
-
-// Type
-#define GMMx21A4_TYPE TYPE_GMM
-// Field Data
-#define GMMx21A4_Enable_OFFSET 0
-#define GMMx21A4_Enable_WIDTH 1
-#define GMMx21A4_Enable_MASK 0x1
-#define GMMx21A4_Prescale_OFFSET 1
-#define GMMx21A4_Prescale_WIDTH 2
-#define GMMx21A4_Prescale_MASK 0x6
-#define GMMx21A4_BlackoutExempt_OFFSET 3
-#define GMMx21A4_BlackoutExempt_WIDTH 1
-#define GMMx21A4_BlackoutExempt_MASK 0x8
-#define GMMx21A4_StallMode_OFFSET 4
-#define GMMx21A4_StallMode_WIDTH 2
-#define GMMx21A4_StallMode_MASK 0x30
-#define GMMx21A4_StallOverride_OFFSET 6
-#define GMMx21A4_StallOverride_WIDTH 1
-#define GMMx21A4_StallOverride_MASK 0x40
-#define GMMx21A4_MaxBurst_OFFSET 7
-#define GMMx21A4_MaxBurst_WIDTH 4
-#define GMMx21A4_MaxBurst_MASK 0x780
-#define GMMx21A4_LazyTimer_OFFSET 11
-#define GMMx21A4_LazyTimer_WIDTH 4
-#define GMMx21A4_LazyTimer_MASK 0x7800
-#define GMMx21A4_StallOverrideWtm_OFFSET 15
-#define GMMx21A4_StallOverrideWtm_WIDTH 1
-#define GMMx21A4_StallOverrideWtm_MASK 0x8000
-#define GMMx21A4_Reserved_31_16_OFFSET 16
-#define GMMx21A4_Reserved_31_16_WIDTH 16
-#define GMMx21A4_Reserved_31_16_MASK 0xffff0000
-
-/// GMMx21A4
-typedef union {
- struct { ///<
- UINT32 Enable:1 ; ///<
- UINT32 Prescale:2 ; ///<
- UINT32 BlackoutExempt:1 ; ///<
- UINT32 StallMode:2 ; ///<
- UINT32 StallOverride:1 ; ///<
- UINT32 MaxBurst:4 ; ///<
- UINT32 LazyTimer:4 ; ///<
- UINT32 StallOverrideWtm:1 ; ///<
- UINT32 Reserved_31_16:16; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx21A4_STRUCT;
-
-// **** GMMx21A8 Register Definition ****
-// Address
-#define GMMx21A8_ADDRESS 0x21a8
-
-// Type
-#define GMMx21A8_TYPE TYPE_GMM
-// Field Data
-#define GMMx21A8_Enable_OFFSET 0
-#define GMMx21A8_Enable_WIDTH 1
-#define GMMx21A8_Enable_MASK 0x1
-#define GMMx21A8_Prescale_OFFSET 1
-#define GMMx21A8_Prescale_WIDTH 2
-#define GMMx21A8_Prescale_MASK 0x6
-#define GMMx21A8_BlackoutExempt_OFFSET 3
-#define GMMx21A8_BlackoutExempt_WIDTH 1
-#define GMMx21A8_BlackoutExempt_MASK 0x8
-#define GMMx21A8_StallMode_OFFSET 4
-#define GMMx21A8_StallMode_WIDTH 2
-#define GMMx21A8_StallMode_MASK 0x30
-#define GMMx21A8_StallOverride_OFFSET 6
-#define GMMx21A8_StallOverride_WIDTH 1
-#define GMMx21A8_StallOverride_MASK 0x40
-#define GMMx21A8_MaxBurst_OFFSET 7
-#define GMMx21A8_MaxBurst_WIDTH 4
-#define GMMx21A8_MaxBurst_MASK 0x780
-#define GMMx21A8_LazyTimer_OFFSET 11
-#define GMMx21A8_LazyTimer_WIDTH 4
-#define GMMx21A8_LazyTimer_MASK 0x7800
-#define GMMx21A8_StallOverrideWtm_OFFSET 15
-#define GMMx21A8_StallOverrideWtm_WIDTH 1
-#define GMMx21A8_StallOverrideWtm_MASK 0x8000
-#define GMMx21A8_Reserved_31_16_OFFSET 16
-#define GMMx21A8_Reserved_31_16_WIDTH 16
-#define GMMx21A8_Reserved_31_16_MASK 0xffff0000
-
-/// GMMx21A8
-typedef union {
- struct { ///<
- UINT32 Enable:1 ; ///<
- UINT32 Prescale:2 ; ///<
- UINT32 BlackoutExempt:1 ; ///<
- UINT32 StallMode:2 ; ///<
- UINT32 StallOverride:1 ; ///<
- UINT32 MaxBurst:4 ; ///<
- UINT32 LazyTimer:4 ; ///<
- UINT32 StallOverrideWtm:1 ; ///<
- UINT32 Reserved_31_16:16; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx21A8_STRUCT;
-
-// **** GMMx21AC Register Definition ****
-// Address
-#define GMMx21AC_ADDRESS 0x21ac
-
-// Type
-#define GMMx21AC_TYPE TYPE_GMM
-// Field Data
-#define GMMx21AC_Enable_OFFSET 0
-#define GMMx21AC_Enable_WIDTH 1
-#define GMMx21AC_Enable_MASK 0x1
-#define GMMx21AC_Prescale_OFFSET 1
-#define GMMx21AC_Prescale_WIDTH 2
-#define GMMx21AC_Prescale_MASK 0x6
-#define GMMx21AC_BlackoutExempt_OFFSET 3
-#define GMMx21AC_BlackoutExempt_WIDTH 1
-#define GMMx21AC_BlackoutExempt_MASK 0x8
-#define GMMx21AC_StallMode_OFFSET 4
-#define GMMx21AC_StallMode_WIDTH 2
-#define GMMx21AC_StallMode_MASK 0x30
-#define GMMx21AC_StallOverride_OFFSET 6
-#define GMMx21AC_StallOverride_WIDTH 1
-#define GMMx21AC_StallOverride_MASK 0x40
-#define GMMx21AC_MaxBurst_OFFSET 7
-#define GMMx21AC_MaxBurst_WIDTH 4
-#define GMMx21AC_MaxBurst_MASK 0x780
-#define GMMx21AC_LazyTimer_OFFSET 11
-#define GMMx21AC_LazyTimer_WIDTH 4
-#define GMMx21AC_LazyTimer_MASK 0x7800
-#define GMMx21AC_StallOverrideWtm_OFFSET 15
-#define GMMx21AC_StallOverrideWtm_WIDTH 1
-#define GMMx21AC_StallOverrideWtm_MASK 0x8000
-#define GMMx21AC_Reserved_31_16_OFFSET 16
-#define GMMx21AC_Reserved_31_16_WIDTH 16
-#define GMMx21AC_Reserved_31_16_MASK 0xffff0000
-
-/// GMMx21AC
-typedef union {
- struct { ///<
- UINT32 Enable:1 ; ///<
- UINT32 Prescale:2 ; ///<
- UINT32 BlackoutExempt:1 ; ///<
- UINT32 StallMode:2 ; ///<
- UINT32 StallOverride:1 ; ///<
- UINT32 MaxBurst:4 ; ///<
- UINT32 LazyTimer:4 ; ///<
- UINT32 StallOverrideWtm:1 ; ///<
- UINT32 Reserved_31_16:16; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx21AC_STRUCT;
-
-// **** GMMx21B0 Register Definition ****
-// Address
-#define GMMx21B0_ADDRESS 0x21b0
-
-// Type
-#define GMMx21B0_TYPE TYPE_GMM
-// Field Data
-#define GMMx21B0_Enable_OFFSET 0
-#define GMMx21B0_Enable_WIDTH 1
-#define GMMx21B0_Enable_MASK 0x1
-#define GMMx21B0_Prescale_OFFSET 1
-#define GMMx21B0_Prescale_WIDTH 2
-#define GMMx21B0_Prescale_MASK 0x6
-#define GMMx21B0_BlackoutExempt_OFFSET 3
-#define GMMx21B0_BlackoutExempt_WIDTH 1
-#define GMMx21B0_BlackoutExempt_MASK 0x8
-#define GMMx21B0_StallMode_OFFSET 4
-#define GMMx21B0_StallMode_WIDTH 2
-#define GMMx21B0_StallMode_MASK 0x30
-#define GMMx21B0_StallOverride_OFFSET 6
-#define GMMx21B0_StallOverride_WIDTH 1
-#define GMMx21B0_StallOverride_MASK 0x40
-#define GMMx21B0_MaxBurst_OFFSET 7
-#define GMMx21B0_MaxBurst_WIDTH 4
-#define GMMx21B0_MaxBurst_MASK 0x780
-#define GMMx21B0_LazyTimer_OFFSET 11
-#define GMMx21B0_LazyTimer_WIDTH 4
-#define GMMx21B0_LazyTimer_MASK 0x7800
-#define GMMx21B0_StallOverrideWtm_OFFSET 15
-#define GMMx21B0_StallOverrideWtm_WIDTH 1
-#define GMMx21B0_StallOverrideWtm_MASK 0x8000
-#define GMMx21B0_Reserved_31_16_OFFSET 16
-#define GMMx21B0_Reserved_31_16_WIDTH 16
-#define GMMx21B0_Reserved_31_16_MASK 0xffff0000
-
-/// GMMx21B0
-typedef union {
- struct { ///<
- UINT32 Enable:1 ; ///<
- UINT32 Prescale:2 ; ///<
- UINT32 BlackoutExempt:1 ; ///<
- UINT32 StallMode:2 ; ///<
- UINT32 StallOverride:1 ; ///<
- UINT32 MaxBurst:4 ; ///<
- UINT32 LazyTimer:4 ; ///<
- UINT32 StallOverrideWtm:1 ; ///<
- UINT32 Reserved_31_16:16; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx21B0_STRUCT;
-
-// **** GMMx21B4 Register Definition ****
-// Address
-#define GMMx21B4_ADDRESS 0x21b4
-
-// Type
-#define GMMx21B4_TYPE TYPE_GMM
-// Field Data
-#define GMMx21B4_Enable_OFFSET 0
-#define GMMx21B4_Enable_WIDTH 1
-#define GMMx21B4_Enable_MASK 0x1
-#define GMMx21B4_Prescale_OFFSET 1
-#define GMMx21B4_Prescale_WIDTH 2
-#define GMMx21B4_Prescale_MASK 0x6
-#define GMMx21B4_BlackoutExempt_OFFSET 3
-#define GMMx21B4_BlackoutExempt_WIDTH 1
-#define GMMx21B4_BlackoutExempt_MASK 0x8
-#define GMMx21B4_StallMode_OFFSET 4
-#define GMMx21B4_StallMode_WIDTH 2
-#define GMMx21B4_StallMode_MASK 0x30
-#define GMMx21B4_StallOverride_OFFSET 6
-#define GMMx21B4_StallOverride_WIDTH 1
-#define GMMx21B4_StallOverride_MASK 0x40
-#define GMMx21B4_MaxBurst_OFFSET 7
-#define GMMx21B4_MaxBurst_WIDTH 4
-#define GMMx21B4_MaxBurst_MASK 0x780
-#define GMMx21B4_LazyTimer_OFFSET 11
-#define GMMx21B4_LazyTimer_WIDTH 4
-#define GMMx21B4_LazyTimer_MASK 0x7800
-#define GMMx21B4_StallOverrideWtm_OFFSET 15
-#define GMMx21B4_StallOverrideWtm_WIDTH 1
-#define GMMx21B4_StallOverrideWtm_MASK 0x8000
-#define GMMx21B4_Reserved_31_16_OFFSET 16
-#define GMMx21B4_Reserved_31_16_WIDTH 16
-#define GMMx21B4_Reserved_31_16_MASK 0xffff0000
-
-/// GMMx21B4
-typedef union {
- struct { ///<
- UINT32 Enable:1 ; ///<
- UINT32 Prescale:2 ; ///<
- UINT32 BlackoutExempt:1 ; ///<
- UINT32 StallMode:2 ; ///<
- UINT32 StallOverride:1 ; ///<
- UINT32 MaxBurst:4 ; ///<
- UINT32 LazyTimer:4 ; ///<
- UINT32 StallOverrideWtm:1 ; ///<
- UINT32 Reserved_31_16:16; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx21B4_STRUCT;
-
-// **** GMMx21B8 Register Definition ****
-// Address
-#define GMMx21B8_ADDRESS 0x21b8
-
-// Type
-#define GMMx21B8_TYPE TYPE_GMM
-// Field Data
-#define GMMx21B8_Enable_OFFSET 0
-#define GMMx21B8_Enable_WIDTH 1
-#define GMMx21B8_Enable_MASK 0x1
-#define GMMx21B8_Prescale_OFFSET 1
-#define GMMx21B8_Prescale_WIDTH 2
-#define GMMx21B8_Prescale_MASK 0x6
-#define GMMx21B8_BlackoutExempt_OFFSET 3
-#define GMMx21B8_BlackoutExempt_WIDTH 1
-#define GMMx21B8_BlackoutExempt_MASK 0x8
-#define GMMx21B8_StallMode_OFFSET 4
-#define GMMx21B8_StallMode_WIDTH 2
-#define GMMx21B8_StallMode_MASK 0x30
-#define GMMx21B8_StallOverride_OFFSET 6
-#define GMMx21B8_StallOverride_WIDTH 1
-#define GMMx21B8_StallOverride_MASK 0x40
-#define GMMx21B8_MaxBurst_OFFSET 7
-#define GMMx21B8_MaxBurst_WIDTH 4
-#define GMMx21B8_MaxBurst_MASK 0x780
-#define GMMx21B8_LazyTimer_OFFSET 11
-#define GMMx21B8_LazyTimer_WIDTH 4
-#define GMMx21B8_LazyTimer_MASK 0x7800
-#define GMMx21B8_StallOverrideWtm_OFFSET 15
-#define GMMx21B8_StallOverrideWtm_WIDTH 1
-#define GMMx21B8_StallOverrideWtm_MASK 0x8000
-#define GMMx21B8_Reserved_31_16_OFFSET 16
-#define GMMx21B8_Reserved_31_16_WIDTH 16
-#define GMMx21B8_Reserved_31_16_MASK 0xffff0000
-
-/// GMMx21B8
-typedef union {
- struct { ///<
- UINT32 Enable:1 ; ///<
- UINT32 Prescale:2 ; ///<
- UINT32 BlackoutExempt:1 ; ///<
- UINT32 StallMode:2 ; ///<
- UINT32 StallOverride:1 ; ///<
- UINT32 MaxBurst:4 ; ///<
- UINT32 LazyTimer:4 ; ///<
- UINT32 StallOverrideWtm:1 ; ///<
- UINT32 Reserved_31_16:16; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx21B8_STRUCT;
-
-// **** GMMx21BC Register Definition ****
-// Address
-#define GMMx21BC_ADDRESS 0x21bc
-
-// Type
-#define GMMx21BC_TYPE TYPE_GMM
-// Field Data
-#define GMMx21BC_Enable_OFFSET 0
-#define GMMx21BC_Enable_WIDTH 1
-#define GMMx21BC_Enable_MASK 0x1
-#define GMMx21BC_Prescale_OFFSET 1
-#define GMMx21BC_Prescale_WIDTH 2
-#define GMMx21BC_Prescale_MASK 0x6
-#define GMMx21BC_BlackoutExempt_OFFSET 3
-#define GMMx21BC_BlackoutExempt_WIDTH 1
-#define GMMx21BC_BlackoutExempt_MASK 0x8
-#define GMMx21BC_StallMode_OFFSET 4
-#define GMMx21BC_StallMode_WIDTH 2
-#define GMMx21BC_StallMode_MASK 0x30
-#define GMMx21BC_StallOverride_OFFSET 6
-#define GMMx21BC_StallOverride_WIDTH 1
-#define GMMx21BC_StallOverride_MASK 0x40
-#define GMMx21BC_MaxBurst_OFFSET 7
-#define GMMx21BC_MaxBurst_WIDTH 4
-#define GMMx21BC_MaxBurst_MASK 0x780
-#define GMMx21BC_LazyTimer_OFFSET 11
-#define GMMx21BC_LazyTimer_WIDTH 4
-#define GMMx21BC_LazyTimer_MASK 0x7800
-#define GMMx21BC_StallOverrideWtm_OFFSET 15
-#define GMMx21BC_StallOverrideWtm_WIDTH 1
-#define GMMx21BC_StallOverrideWtm_MASK 0x8000
-#define GMMx21BC_Reserved_31_16_OFFSET 16
-#define GMMx21BC_Reserved_31_16_WIDTH 16
-#define GMMx21BC_Reserved_31_16_MASK 0xffff0000
-
-/// GMMx21BC
-typedef union {
- struct { ///<
- UINT32 Enable:1 ; ///<
- UINT32 Prescale:2 ; ///<
- UINT32 BlackoutExempt:1 ; ///<
- UINT32 StallMode:2 ; ///<
- UINT32 StallOverride:1 ; ///<
- UINT32 MaxBurst:4 ; ///<
- UINT32 LazyTimer:4 ; ///<
- UINT32 StallOverrideWtm:1 ; ///<
- UINT32 Reserved_31_16:16; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx21BC_STRUCT;
-
-// **** GMMx21C0 Register Definition ****
-// Address
-#define GMMx21C0_ADDRESS 0x21c0
-
-// Type
-#define GMMx21C0_TYPE TYPE_GMM
-// Field Data
-#define GMMx21C0_Enable_OFFSET 0
-#define GMMx21C0_Enable_WIDTH 1
-#define GMMx21C0_Enable_MASK 0x1
-#define GMMx21C0_Prescale_OFFSET 1
-#define GMMx21C0_Prescale_WIDTH 2
-#define GMMx21C0_Prescale_MASK 0x6
-#define GMMx21C0_BlackoutExempt_OFFSET 3
-#define GMMx21C0_BlackoutExempt_WIDTH 1
-#define GMMx21C0_BlackoutExempt_MASK 0x8
-#define GMMx21C0_StallMode_OFFSET 4
-#define GMMx21C0_StallMode_WIDTH 2
-#define GMMx21C0_StallMode_MASK 0x30
-#define GMMx21C0_StallOverride_OFFSET 6
-#define GMMx21C0_StallOverride_WIDTH 1
-#define GMMx21C0_StallOverride_MASK 0x40
-#define GMMx21C0_MaxBurst_OFFSET 7
-#define GMMx21C0_MaxBurst_WIDTH 4
-#define GMMx21C0_MaxBurst_MASK 0x780
-#define GMMx21C0_LazyTimer_OFFSET 11
-#define GMMx21C0_LazyTimer_WIDTH 4
-#define GMMx21C0_LazyTimer_MASK 0x7800
-#define GMMx21C0_StallOverrideWtm_OFFSET 15
-#define GMMx21C0_StallOverrideWtm_WIDTH 1
-#define GMMx21C0_StallOverrideWtm_MASK 0x8000
-#define GMMx21C0_Reserved_31_16_OFFSET 16
-#define GMMx21C0_Reserved_31_16_WIDTH 16
-#define GMMx21C0_Reserved_31_16_MASK 0xffff0000
-
-/// GMMx21C0
-typedef union {
- struct { ///<
- UINT32 Enable:1 ; ///<
- UINT32 Prescale:2 ; ///<
- UINT32 BlackoutExempt:1 ; ///<
- UINT32 StallMode:2 ; ///<
- UINT32 StallOverride:1 ; ///<
- UINT32 MaxBurst:4 ; ///<
- UINT32 LazyTimer:4 ; ///<
- UINT32 StallOverrideWtm:1 ; ///<
- UINT32 Reserved_31_16:16; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx21C0_STRUCT;
-
-// **** GMMx21C4 Register Definition ****
-// Address
-#define GMMx21C4_ADDRESS 0x21c4
-
-// Type
-#define GMMx21C4_TYPE TYPE_GMM
-// Field Data
-#define GMMx21C4_Enable_OFFSET 0
-#define GMMx21C4_Enable_WIDTH 1
-#define GMMx21C4_Enable_MASK 0x1
-#define GMMx21C4_Prescale_OFFSET 1
-#define GMMx21C4_Prescale_WIDTH 2
-#define GMMx21C4_Prescale_MASK 0x6
-#define GMMx21C4_BlackoutExempt_OFFSET 3
-#define GMMx21C4_BlackoutExempt_WIDTH 1
-#define GMMx21C4_BlackoutExempt_MASK 0x8
-#define GMMx21C4_StallMode_OFFSET 4
-#define GMMx21C4_StallMode_WIDTH 2
-#define GMMx21C4_StallMode_MASK 0x30
-#define GMMx21C4_StallOverride_OFFSET 6
-#define GMMx21C4_StallOverride_WIDTH 1
-#define GMMx21C4_StallOverride_MASK 0x40
-#define GMMx21C4_MaxBurst_OFFSET 7
-#define GMMx21C4_MaxBurst_WIDTH 4
-#define GMMx21C4_MaxBurst_MASK 0x780
-#define GMMx21C4_LazyTimer_OFFSET 11
-#define GMMx21C4_LazyTimer_WIDTH 4
-#define GMMx21C4_LazyTimer_MASK 0x7800
-#define GMMx21C4_StallOverrideWtm_OFFSET 15
-#define GMMx21C4_StallOverrideWtm_WIDTH 1
-#define GMMx21C4_StallOverrideWtm_MASK 0x8000
-#define GMMx21C4_Reserved_31_16_OFFSET 16
-#define GMMx21C4_Reserved_31_16_WIDTH 16
-#define GMMx21C4_Reserved_31_16_MASK 0xffff0000
-
-/// GMMx21C4
-typedef union {
- struct { ///<
- UINT32 Enable:1 ; ///<
- UINT32 Prescale:2 ; ///<
- UINT32 BlackoutExempt:1 ; ///<
- UINT32 StallMode:2 ; ///<
- UINT32 StallOverride:1 ; ///<
- UINT32 MaxBurst:4 ; ///<
- UINT32 LazyTimer:4 ; ///<
- UINT32 StallOverrideWtm:1 ; ///<
- UINT32 Reserved_31_16:16; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx21C4_STRUCT;
-
-// **** GMMx21C8 Register Definition ****
-// Address
-#define GMMx21C8_ADDRESS 0x21c8
-
-// Type
-#define GMMx21C8_TYPE TYPE_GMM
-// Field Data
-#define GMMx21C8_Enable_OFFSET 0
-#define GMMx21C8_Enable_WIDTH 1
-#define GMMx21C8_Enable_MASK 0x1
-#define GMMx21C8_Prescale_OFFSET 1
-#define GMMx21C8_Prescale_WIDTH 2
-#define GMMx21C8_Prescale_MASK 0x6
-#define GMMx21C8_BlackoutExempt_OFFSET 3
-#define GMMx21C8_BlackoutExempt_WIDTH 1
-#define GMMx21C8_BlackoutExempt_MASK 0x8
-#define GMMx21C8_StallMode_OFFSET 4
-#define GMMx21C8_StallMode_WIDTH 2
-#define GMMx21C8_StallMode_MASK 0x30
-#define GMMx21C8_StallOverride_OFFSET 6
-#define GMMx21C8_StallOverride_WIDTH 1
-#define GMMx21C8_StallOverride_MASK 0x40
-#define GMMx21C8_MaxBurst_OFFSET 7
-#define GMMx21C8_MaxBurst_WIDTH 4
-#define GMMx21C8_MaxBurst_MASK 0x780
-#define GMMx21C8_LazyTimer_OFFSET 11
-#define GMMx21C8_LazyTimer_WIDTH 4
-#define GMMx21C8_LazyTimer_MASK 0x7800
-#define GMMx21C8_StallOverrideWtm_OFFSET 15
-#define GMMx21C8_StallOverrideWtm_WIDTH 1
-#define GMMx21C8_StallOverrideWtm_MASK 0x8000
-#define GMMx21C8_Reserved_31_16_OFFSET 16
-#define GMMx21C8_Reserved_31_16_WIDTH 16
-#define GMMx21C8_Reserved_31_16_MASK 0xffff0000
-
-/// GMMx21C8
-typedef union {
- struct { ///<
- UINT32 Enable:1 ; ///<
- UINT32 Prescale:2 ; ///<
- UINT32 BlackoutExempt:1 ; ///<
- UINT32 StallMode:2 ; ///<
- UINT32 StallOverride:1 ; ///<
- UINT32 MaxBurst:4 ; ///<
- UINT32 LazyTimer:4 ; ///<
- UINT32 StallOverrideWtm:1 ; ///<
- UINT32 Reserved_31_16:16; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx21C8_STRUCT;
-
-// **** GMMx21CC Register Definition ****
-// Address
-#define GMMx21CC_ADDRESS 0x21cc
-
-// Type
-#define GMMx21CC_TYPE TYPE_GMM
-// Field Data
-#define GMMx21CC_Enable_OFFSET 0
-#define GMMx21CC_Enable_WIDTH 1
-#define GMMx21CC_Enable_MASK 0x1
-#define GMMx21CC_Prescale_OFFSET 1
-#define GMMx21CC_Prescale_WIDTH 2
-#define GMMx21CC_Prescale_MASK 0x6
-#define GMMx21CC_BlackoutExempt_OFFSET 3
-#define GMMx21CC_BlackoutExempt_WIDTH 1
-#define GMMx21CC_BlackoutExempt_MASK 0x8
-#define GMMx21CC_StallMode_OFFSET 4
-#define GMMx21CC_StallMode_WIDTH 2
-#define GMMx21CC_StallMode_MASK 0x30
-#define GMMx21CC_StallOverride_OFFSET 6
-#define GMMx21CC_StallOverride_WIDTH 1
-#define GMMx21CC_StallOverride_MASK 0x40
-#define GMMx21CC_MaxBurst_OFFSET 7
-#define GMMx21CC_MaxBurst_WIDTH 4
-#define GMMx21CC_MaxBurst_MASK 0x780
-#define GMMx21CC_LazyTimer_OFFSET 11
-#define GMMx21CC_LazyTimer_WIDTH 4
-#define GMMx21CC_LazyTimer_MASK 0x7800
-#define GMMx21CC_StallOverrideWtm_OFFSET 15
-#define GMMx21CC_StallOverrideWtm_WIDTH 1
-#define GMMx21CC_StallOverrideWtm_MASK 0x8000
-#define GMMx21CC_Reserved_31_16_OFFSET 16
-#define GMMx21CC_Reserved_31_16_WIDTH 16
-#define GMMx21CC_Reserved_31_16_MASK 0xffff0000
-
-/// GMMx21CC
-typedef union {
- struct { ///<
- UINT32 Enable:1 ; ///<
- UINT32 Prescale:2 ; ///<
- UINT32 BlackoutExempt:1 ; ///<
- UINT32 StallMode:2 ; ///<
- UINT32 StallOverride:1 ; ///<
- UINT32 MaxBurst:4 ; ///<
- UINT32 LazyTimer:4 ; ///<
- UINT32 StallOverrideWtm:1 ; ///<
- UINT32 Reserved_31_16:16; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx21CC_STRUCT;
-
-// **** GMMx21D0 Register Definition ****
-// Address
-#define GMMx21D0_ADDRESS 0x21d0
-
-// Type
-#define GMMx21D0_TYPE TYPE_GMM
-// Field Data
-#define GMMx21D0_Enable_OFFSET 0
-#define GMMx21D0_Enable_WIDTH 1
-#define GMMx21D0_Enable_MASK 0x1
-#define GMMx21D0_Prescale_OFFSET 1
-#define GMMx21D0_Prescale_WIDTH 2
-#define GMMx21D0_Prescale_MASK 0x6
-#define GMMx21D0_BlackoutExempt_OFFSET 3
-#define GMMx21D0_BlackoutExempt_WIDTH 1
-#define GMMx21D0_BlackoutExempt_MASK 0x8
-#define GMMx21D0_StallMode_OFFSET 4
-#define GMMx21D0_StallMode_WIDTH 2
-#define GMMx21D0_StallMode_MASK 0x30
-#define GMMx21D0_StallOverride_OFFSET 6
-#define GMMx21D0_StallOverride_WIDTH 1
-#define GMMx21D0_StallOverride_MASK 0x40
-#define GMMx21D0_MaxBurst_OFFSET 7
-#define GMMx21D0_MaxBurst_WIDTH 4
-#define GMMx21D0_MaxBurst_MASK 0x780
-#define GMMx21D0_LazyTimer_OFFSET 11
-#define GMMx21D0_LazyTimer_WIDTH 4
-#define GMMx21D0_LazyTimer_MASK 0x7800
-#define GMMx21D0_StallOverrideWtm_OFFSET 15
-#define GMMx21D0_StallOverrideWtm_WIDTH 1
-#define GMMx21D0_StallOverrideWtm_MASK 0x8000
-#define GMMx21D0_Reserved_31_16_OFFSET 16
-#define GMMx21D0_Reserved_31_16_WIDTH 16
-#define GMMx21D0_Reserved_31_16_MASK 0xffff0000
-
-/// GMMx21D0
-typedef union {
- struct { ///<
- UINT32 Enable:1 ; ///<
- UINT32 Prescale:2 ; ///<
- UINT32 BlackoutExempt:1 ; ///<
- UINT32 StallMode:2 ; ///<
- UINT32 StallOverride:1 ; ///<
- UINT32 MaxBurst:4 ; ///<
- UINT32 LazyTimer:4 ; ///<
- UINT32 StallOverrideWtm:1 ; ///<
- UINT32 Reserved_31_16:16; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx21D0_STRUCT;
-
-// **** GMMx25C0 Register Definition ****
-// Address
-#define GMMx25C0_ADDRESS 0x25c0
-
-// Type
-#define GMMx25C0_TYPE TYPE_GMM
-// Field Data
-#define GMMx25C0_BlackoutRd_OFFSET 0
-#define GMMx25C0_BlackoutRd_WIDTH 1
-#define GMMx25C0_BlackoutRd_MASK 0x1
-#define GMMx25C0_BlackoutWr_OFFSET 1
-#define GMMx25C0_BlackoutWr_WIDTH 1
-#define GMMx25C0_BlackoutWr_MASK 0x2
-#define GMMx25C0_Reserved_31_2_OFFSET 2
-#define GMMx25C0_Reserved_31_2_WIDTH 30
-#define GMMx25C0_Reserved_31_2_MASK 0xfffffffc
-
-/// GMMx25C0
-typedef union {
- struct { ///<
- UINT32 BlackoutRd:1 ; ///<
- UINT32 BlackoutWr:1 ; ///<
- UINT32 Reserved_31_2:30; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx25C0_STRUCT;
-
-// **** GMMx25C8 Register Definition ****
-// Address
-#define GMMx25C8_ADDRESS 0x25c8
-
-// Type
-#define GMMx25C8_TYPE TYPE_GMM
-// Field Data
-#define GMMx25C8_ReadLcl_OFFSET 0
-#define GMMx25C8_ReadLcl_WIDTH 8
-#define GMMx25C8_ReadLcl_MASK 0xff
-#define GMMx25C8_ReadHub_OFFSET 8
-#define GMMx25C8_ReadHub_WIDTH 8
-#define GMMx25C8_ReadHub_MASK 0xff00
-#define GMMx25C8_ReadPri_OFFSET 16
-#define GMMx25C8_ReadPri_WIDTH 8
-#define GMMx25C8_ReadPri_MASK 0xff0000
-#define GMMx25C8_LclPri_OFFSET 24
-#define GMMx25C8_LclPri_WIDTH 1
-#define GMMx25C8_LclPri_MASK 0x1000000
-#define GMMx25C8_HubPri_OFFSET 25
-#define GMMx25C8_HubPri_WIDTH 1
-#define GMMx25C8_HubPri_MASK 0x2000000
-#define GMMx25C8_Reserved_31_26_OFFSET 26
-#define GMMx25C8_Reserved_31_26_WIDTH 6
-#define GMMx25C8_Reserved_31_26_MASK 0xfc000000
-
-/// GMMx25C8
-typedef union {
- struct { ///<
- UINT32 ReadLcl:8 ; ///<
- UINT32 ReadHub:8 ; ///<
- UINT32 ReadPri:8 ; ///<
- UINT32 LclPri:1 ; ///<
- UINT32 HubPri:1 ; ///<
- UINT32 Reserved_31_26:6 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx25C8_STRUCT;
-
-// **** GMMx25CC Register Definition ****
-// Address
-#define GMMx25CC_ADDRESS 0x25cc
-
-// Type
-#define GMMx25CC_TYPE TYPE_GMM
-// Field Data
-#define GMMx25CC_WriteLcl_OFFSET 0
-#define GMMx25CC_WriteLcl_WIDTH 8
-#define GMMx25CC_WriteLcl_MASK 0xff
-#define GMMx25CC_WriteHub_OFFSET 8
-#define GMMx25CC_WriteHub_WIDTH 8
-#define GMMx25CC_WriteHub_MASK 0xff00
-#define GMMx25CC_HubPri_OFFSET 16
-#define GMMx25CC_HubPri_WIDTH 1
-#define GMMx25CC_HubPri_MASK 0x10000
-#define GMMx25CC_Reserved_31_17_OFFSET 17
-#define GMMx25CC_Reserved_31_17_WIDTH 15
-#define GMMx25CC_Reserved_31_17_MASK 0xfffe0000
-
-/// GMMx25CC
-typedef union {
- struct { ///<
- UINT32 WriteLcl:8 ; ///<
- UINT32 WriteHub:8 ; ///<
- UINT32 HubPri:1 ; ///<
- UINT32 Reserved_31_17:15; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx25CC_STRUCT;
-
-// **** GMMx2610 Register Definition ****
-// Address
-#define GMMx2610_ADDRESS 0x2610
-
-// Type
-#define GMMx2610_TYPE TYPE_GMM
-// Field Data
-#define GMMx2610_TctFetch0_OFFSET 0
-#define GMMx2610_TctFetch0_WIDTH 4
-#define GMMx2610_TctFetch0_MASK 0xf
-#define GMMx2610_TcvFetch0_OFFSET 4
-#define GMMx2610_TcvFetch0_WIDTH 4
-#define GMMx2610_TcvFetch0_MASK 0xf0
-#define GMMx2610_Vc0_OFFSET 8
-#define GMMx2610_Vc0_WIDTH 4
-#define GMMx2610_Vc0_MASK 0xf00
-#define GMMx2610_Cb0_OFFSET 12
-#define GMMx2610_Cb0_WIDTH 4
-#define GMMx2610_Cb0_MASK 0xf000
-#define GMMx2610_CbcMask0_OFFSET 16
-#define GMMx2610_CbcMask0_WIDTH 4
-#define GMMx2610_CbcMask0_MASK 0xf0000
-#define GMMx2610_CbfMask0_OFFSET 20
-#define GMMx2610_CbfMask0_WIDTH 4
-#define GMMx2610_CbfMask0_MASK 0xf00000
-#define GMMx2610_Db0_OFFSET 24
-#define GMMx2610_Db0_WIDTH 4
-#define GMMx2610_Db0_MASK 0xf000000
-#define GMMx2610_DbhTile0_OFFSET 28
-#define GMMx2610_DbhTile0_WIDTH 4
-#define GMMx2610_DbhTile0_MASK 0xf0000000
-
-/// GMMx2610
-typedef union {
- struct { ///<
- UINT32 TctFetch0:4 ; ///<
- UINT32 TcvFetch0:4 ; ///<
- UINT32 Vc0:4 ; ///<
- UINT32 Cb0:4 ; ///<
- UINT32 CbcMask0:4 ; ///<
- UINT32 CbfMask0:4 ; ///<
- UINT32 Db0:4 ; ///<
- UINT32 DbhTile0:4 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx2610_STRUCT;
-
-// **** GMMx2614 Register Definition ****
-// Address
-#define GMMx2614_ADDRESS 0x2614
-
-// Type
-#define GMMx2614_TYPE TYPE_GMM
-// Field Data
-#define GMMx2614_Cb0_OFFSET 0
-#define GMMx2614_Cb0_WIDTH 4
-#define GMMx2614_Cb0_MASK 0xf
-#define GMMx2614_CbcMask0_OFFSET 4
-#define GMMx2614_CbcMask0_WIDTH 4
-#define GMMx2614_CbcMask0_MASK 0xf0
-#define GMMx2614_CbfMask0_OFFSET 8
-#define GMMx2614_CbfMask0_WIDTH 4
-#define GMMx2614_CbfMask0_MASK 0xf00
-#define GMMx2614_Db0_OFFSET 12
-#define GMMx2614_Db0_WIDTH 4
-#define GMMx2614_Db0_MASK 0xf000
-#define GMMx2614_DbhTile0_OFFSET 16
-#define GMMx2614_DbhTile0_WIDTH 4
-#define GMMx2614_DbhTile0_MASK 0xf0000
-#define GMMx2614_Sx0_OFFSET 20
-#define GMMx2614_Sx0_WIDTH 4
-#define GMMx2614_Sx0_MASK 0xf00000
-#define GMMx2614_Bcast0_OFFSET 24
-#define GMMx2614_Bcast0_WIDTH 4
-#define GMMx2614_Bcast0_MASK 0xf000000
-#define GMMx2614_Cbimmed0_OFFSET 28
-#define GMMx2614_Cbimmed0_WIDTH 4
-#define GMMx2614_Cbimmed0_MASK 0xf0000000
-
-/// GMMx2614
-typedef union {
- struct { ///<
- UINT32 Cb0:4 ; ///<
- UINT32 CbcMask0:4 ; ///<
- UINT32 CbfMask0:4 ; ///<
- UINT32 Db0:4 ; ///<
- UINT32 DbhTile0:4 ; ///<
- UINT32 Sx0:4 ; ///<
- UINT32 Bcast0:4 ; ///<
- UINT32 Cbimmed0:4 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx2614_STRUCT;
-
-// **** GMMx2618 Register Definition ****
-// Address
-#define GMMx2618_ADDRESS 0x2618
-
-// Type
-#define GMMx2618_TYPE TYPE_GMM
-// Field Data
-#define GMMx2618_DbstEn0_OFFSET 0
-#define GMMx2618_DbstEn0_WIDTH 4
-#define GMMx2618_DbstEn0_MASK 0xf
-#define GMMx2618_TcvFetch1_OFFSET 4
-#define GMMx2618_TcvFetch1_WIDTH 4
-#define GMMx2618_TcvFetch1_MASK 0xf0
-#define GMMx2618_TctFetch1_OFFSET 8
-#define GMMx2618_TctFetch1_WIDTH 4
-#define GMMx2618_TctFetch1_MASK 0xf00
-#define GMMx2618_Vc1_OFFSET 12
-#define GMMx2618_Vc1_WIDTH 4
-#define GMMx2618_Vc1_MASK 0xf000
-#define GMMx2618_Reserved_31_16_OFFSET 16
-#define GMMx2618_Reserved_31_16_WIDTH 16
-#define GMMx2618_Reserved_31_16_MASK 0xffff0000
-
-/// GMMx2618
-typedef union {
- struct { ///<
- UINT32 DbstEn0:4 ; ///<
- UINT32 TcvFetch1:4 ; ///<
- UINT32 TctFetch1:4 ; ///<
- UINT32 Vc1:4 ; ///<
- UINT32 Reserved_31_16:16; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx2618_STRUCT;
-
-// **** GMMx261C Register Definition ****
-// Address
-#define GMMx261C_ADDRESS 0x261c
-
-// Type
-#define GMMx261C_TYPE TYPE_GMM
-// Field Data
-#define GMMx261C_DbstEn0_OFFSET 0
-#define GMMx261C_DbstEn0_WIDTH 4
-#define GMMx261C_DbstEn0_MASK 0xf
-#define GMMx261C_Reserved_31_4_OFFSET 4
-#define GMMx261C_Reserved_31_4_WIDTH 28
-#define GMMx261C_Reserved_31_4_MASK 0xfffffff0
-
-/// GMMx261C
-typedef union {
- struct { ///<
- UINT32 DbstEn0:4 ; ///<
- UINT32 Reserved_31_4:28; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx261C_STRUCT;
-
-// **** GMMx2638 Register Definition ****
-// Address
-#define GMMx2638_ADDRESS 0x2638
-
-// Type
-#define GMMx2638_TYPE TYPE_GMM
-// Field Data
-#define GMMx2638_Reserved_17_0_OFFSET 0
-#define GMMx2638_Reserved_17_0_WIDTH 18
-#define GMMx2638_Reserved_17_0_MASK 0x3ffff
-#define GMMx2638_Enable_OFFSET 18
-#define GMMx2638_Enable_WIDTH 1
-#define GMMx2638_Enable_MASK 0x40000
-#define GMMx2638_Reserved_31_19_OFFSET 19
-#define GMMx2638_Reserved_31_19_WIDTH 13
-#define GMMx2638_Reserved_31_19_MASK 0xfff80000
-
-/// GMMx2638
-typedef union {
- struct { ///<
- UINT32 Reserved_17_0:18; ///<
- UINT32 Enable:1 ; ///<
- UINT32 Reserved_31_19:13; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx2638_STRUCT;
-
-// **** GMMx263C Register Definition ****
-// Address
-#define GMMx263C_ADDRESS 0x263c
-
-// Type
-#define GMMx263C_TYPE TYPE_GMM
-// Field Data
-#define GMMx263C_Reserved_17_0_OFFSET 0
-#define GMMx263C_Reserved_17_0_WIDTH 18
-#define GMMx263C_Reserved_17_0_MASK 0x3ffff
-#define GMMx263C_Enable_OFFSET 18
-#define GMMx263C_Enable_WIDTH 1
-#define GMMx263C_Enable_MASK 0x40000
-#define GMMx263C_Reserved_31_19_OFFSET 19
-#define GMMx263C_Reserved_31_19_WIDTH 13
-#define GMMx263C_Reserved_31_19_MASK 0xfff80000
-
-/// GMMx263C
-typedef union {
- struct { ///<
- UINT32 Reserved_17_0:18; ///<
- UINT32 Enable:1 ; ///<
- UINT32 Reserved_31_19:13; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx263C_STRUCT;
-
-// **** GMMx2640 Register Definition ****
-// Address
-#define GMMx2640_ADDRESS 0x2640
-
-// Type
-#define GMMx2640_TYPE TYPE_GMM
-// Field Data
-#define GMMx2640_Reserved_17_0_OFFSET 0
-#define GMMx2640_Reserved_17_0_WIDTH 18
-#define GMMx2640_Reserved_17_0_MASK 0x3ffff
-#define GMMx2640_Enable_OFFSET 18
-#define GMMx2640_Enable_WIDTH 1
-#define GMMx2640_Enable_MASK 0x40000
-#define GMMx2640_Reserved_31_19_OFFSET 19
-#define GMMx2640_Reserved_31_19_WIDTH 13
-#define GMMx2640_Reserved_31_19_MASK 0xfff80000
-
-/// GMMx2640
-typedef union {
- struct { ///<
- UINT32 Reserved_17_0:18; ///<
- UINT32 Enable:1 ; ///<
- UINT32 Reserved_31_19:13; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx2640_STRUCT;
-
-// **** GMMx277C Register Definition ****
-// Address
-#define GMMx277C_ADDRESS 0x277c
-
-// Type
-#define GMMx277C_TYPE TYPE_GMM
-// Field Data
-#define GMMx277C_ActRd_OFFSET 0
-#define GMMx277C_ActRd_WIDTH 8
-#define GMMx277C_ActRd_MASK 0xff
-#define GMMx277C_ActWr_OFFSET 8
-#define GMMx277C_ActWr_WIDTH 8
-#define GMMx277C_ActWr_MASK 0xff00
-#define GMMx277C_RasMActRd_OFFSET 16
-#define GMMx277C_RasMActRd_WIDTH 8
-#define GMMx277C_RasMActRd_MASK 0xff0000
-#define GMMx277C_RasMActWr_OFFSET 24
-#define GMMx277C_RasMActWr_WIDTH 8
-#define GMMx277C_RasMActWr_MASK 0xff000000
-
-/// GMMx277C
-typedef union {
- struct { ///<
- UINT32 ActRd:8 ; ///<
- UINT32 ActWr:8 ; ///<
- UINT32 RasMActRd:8 ; ///<
- UINT32 RasMActWr:8 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx277C_STRUCT;
-
-// **** GMMx2780 Register Definition ****
-// Address
-#define GMMx2780_ADDRESS 0x2780
-
-// Type
-#define GMMx2780_TYPE TYPE_GMM
-// Field Data
-#define GMMx2780_Ras2Ras_OFFSET 0
-#define GMMx2780_Ras2Ras_WIDTH 8
-#define GMMx2780_Ras2Ras_MASK 0xff
-#define GMMx2780_Rp_OFFSET 8
-#define GMMx2780_Rp_WIDTH 8
-#define GMMx2780_Rp_MASK 0xff00
-#define GMMx2780_WrPlusRp_OFFSET 16
-#define GMMx2780_WrPlusRp_WIDTH 8
-#define GMMx2780_WrPlusRp_MASK 0xff0000
-#define GMMx2780_BusTurn_OFFSET 24
-#define GMMx2780_BusTurn_WIDTH 8
-#define GMMx2780_BusTurn_MASK 0xff000000
-
-/// GMMx2780
-typedef union {
- struct { ///<
- UINT32 Ras2Ras:8 ; ///<
- UINT32 Rp:8 ; ///<
- UINT32 WrPlusRp:8 ; ///<
- UINT32 BusTurn:8 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx2780_STRUCT;
-
-// **** GMMx2784 Register Definition ****
-// Address
-#define GMMx2784_ADDRESS 0x2784
-
-// Type
-#define GMMx2784_TYPE TYPE_GMM
-// Field Data
-#define GMMx2784_WtMode_OFFSET 0
-#define GMMx2784_WtMode_WIDTH 2
-#define GMMx2784_WtMode_MASK 0x3
-#define GMMx2784_HarshPri_OFFSET 2
-#define GMMx2784_HarshPri_WIDTH 1
-#define GMMx2784_HarshPri_MASK 0x4
-#define GMMx2784_Reserved_31_3_OFFSET 3
-#define GMMx2784_Reserved_31_3_WIDTH 29
-#define GMMx2784_Reserved_31_3_MASK 0xfffffff8
-
-/// GMMx2784
-typedef union {
- struct { ///<
- UINT32 WtMode:2 ; ///<
- UINT32 HarshPri:1 ; ///<
- UINT32 Reserved_31_3:29; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx2784_STRUCT;
-
-// **** GMMx2788 Register Definition ****
-// Address
-#define GMMx2788_ADDRESS 0x2788
-
-// Type
-#define GMMx2788_TYPE TYPE_GMM
-// Field Data
-#define GMMx2788_WtMode_OFFSET 0
-#define GMMx2788_WtMode_WIDTH 2
-#define GMMx2788_WtMode_MASK 0x3
-#define GMMx2788_HarshPri_OFFSET 2
-#define GMMx2788_HarshPri_WIDTH 1
-#define GMMx2788_HarshPri_MASK 0x4
-#define GMMx2788_Reserved_31_3_OFFSET 3
-#define GMMx2788_Reserved_31_3_WIDTH 29
-#define GMMx2788_Reserved_31_3_MASK 0xfffffff8
-
-/// GMMx2788
-typedef union {
- struct { ///<
- UINT32 WtMode:2 ; ///<
- UINT32 HarshPri:1 ; ///<
- UINT32 Reserved_31_3:29; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx2788_STRUCT;
-
-// **** GMMx279C Register Definition ****
-// Address
-#define GMMx279C_ADDRESS 0x279c
-
-// Type
-#define GMMx279C_TYPE TYPE_GMM
-// Field Data
-#define GMMx279C_Group0_OFFSET 0
-#define GMMx279C_Group0_WIDTH 8
-#define GMMx279C_Group0_MASK 0xff
-#define GMMx279C_Group1_OFFSET 8
-#define GMMx279C_Group1_WIDTH 8
-#define GMMx279C_Group1_MASK 0xff00
-#define GMMx279C_Group2_OFFSET 16
-#define GMMx279C_Group2_WIDTH 8
-#define GMMx279C_Group2_MASK 0xff0000
-#define GMMx279C_Group3_OFFSET 24
-#define GMMx279C_Group3_WIDTH 8
-#define GMMx279C_Group3_MASK 0xff000000
-
-/// GMMx279C
-typedef union {
- struct { ///<
- UINT32 Group0:8 ; ///<
- UINT32 Group1:8 ; ///<
- UINT32 Group2:8 ; ///<
- UINT32 Group3:8 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx279C_STRUCT;
-
-// **** GMMx27A0 Register Definition ****
-// Address
-#define GMMx27A0_ADDRESS 0x27a0
-
-// Type
-#define GMMx27A0_TYPE TYPE_GMM
-// Field Data
-#define GMMx27A0_Group0_OFFSET 0
-#define GMMx27A0_Group0_WIDTH 8
-#define GMMx27A0_Group0_MASK 0xff
-#define GMMx27A0_Group1_OFFSET 8
-#define GMMx27A0_Group1_WIDTH 8
-#define GMMx27A0_Group1_MASK 0xff00
-#define GMMx27A0_Group2_OFFSET 16
-#define GMMx27A0_Group2_WIDTH 8
-#define GMMx27A0_Group2_MASK 0xff0000
-#define GMMx27A0_Group3_OFFSET 24
-#define GMMx27A0_Group3_WIDTH 8
-#define GMMx27A0_Group3_MASK 0xff000000
-
-/// GMMx27A0
-typedef union {
- struct { ///<
- UINT32 Group0:8 ; ///<
- UINT32 Group1:8 ; ///<
- UINT32 Group2:8 ; ///<
- UINT32 Group3:8 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx27A0_STRUCT;
-
-// **** GMMx27CC Register Definition ****
-// Address
-#define GMMx27CC_ADDRESS 0x27cc
-
-// Type
-#define GMMx27CC_TYPE TYPE_GMM
-// Field Data
-#define GMMx27CC_StreakLimit_OFFSET 0
-#define GMMx27CC_StreakLimit_WIDTH 8
-#define GMMx27CC_StreakLimit_MASK 0xff
-#define GMMx27CC_StreakLimitUber_OFFSET 8
-#define GMMx27CC_StreakLimitUber_WIDTH 8
-#define GMMx27CC_StreakLimitUber_MASK 0xff00
-#define GMMx27CC_StreakBreak_OFFSET 16
-#define GMMx27CC_StreakBreak_WIDTH 1
-#define GMMx27CC_StreakBreak_MASK 0x10000
-#define GMMx27CC_StreakUber_OFFSET 17
-#define GMMx27CC_StreakUber_WIDTH 1
-#define GMMx27CC_StreakUber_MASK 0x20000
-#define GMMx27CC_Reserved_31_18_OFFSET 18
-#define GMMx27CC_Reserved_31_18_WIDTH 14
-#define GMMx27CC_Reserved_31_18_MASK 0xfffc0000
-
-/// GMMx27CC
-typedef union {
- struct { ///<
- UINT32 StreakLimit:8 ; ///<
- UINT32 StreakLimitUber:8 ; ///<
- UINT32 StreakBreak:1 ; ///<
- UINT32 StreakUber:1 ; ///<
- UINT32 Reserved_31_18:14; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx27CC_STRUCT;
-
-// **** GMMx27D0 Register Definition ****
-// Address
-#define GMMx27D0_ADDRESS 0x27d0
-
-// Type
-#define GMMx27D0_TYPE TYPE_GMM
-// Field Data
-#define GMMx27D0_StreakLimit_OFFSET 0
-#define GMMx27D0_StreakLimit_WIDTH 8
-#define GMMx27D0_StreakLimit_MASK 0xff
-#define GMMx27D0_StreakLimitUber_OFFSET 8
-#define GMMx27D0_StreakLimitUber_WIDTH 8
-#define GMMx27D0_StreakLimitUber_MASK 0xff00
-#define GMMx27D0_StreakBreak_OFFSET 16
-#define GMMx27D0_StreakBreak_WIDTH 1
-#define GMMx27D0_StreakBreak_MASK 0x10000
-#define GMMx27D0_StreakUber_OFFSET 17
-#define GMMx27D0_StreakUber_WIDTH 1
-#define GMMx27D0_StreakUber_MASK 0x20000
-#define GMMx27D0_Reserved_31_18_OFFSET 18
-#define GMMx27D0_Reserved_31_18_WIDTH 14
-#define GMMx27D0_Reserved_31_18_MASK 0xfffc0000
-
-/// GMMx27D0
-typedef union {
- struct { ///<
- UINT32 StreakLimit:8 ; ///<
- UINT32 StreakLimitUber:8 ; ///<
- UINT32 StreakBreak:1 ; ///<
- UINT32 StreakUber:1 ; ///<
- UINT32 Reserved_31_18:14; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx27D0_STRUCT;
-
-// **** GMMx27DC Register Definition ****
-// Address
-#define GMMx27DC_ADDRESS 0x27dc
-
-// Type
-#define GMMx27DC_TYPE TYPE_GMM
-// Field Data
-#define GMMx27DC_Lcl_OFFSET 0
-#define GMMx27DC_Lcl_WIDTH 8
-#define GMMx27DC_Lcl_MASK 0xff
-#define GMMx27DC_Hub_OFFSET 8
-#define GMMx27DC_Hub_WIDTH 8
-#define GMMx27DC_Hub_MASK 0xff00
-#define GMMx27DC_Disp_OFFSET 16
-#define GMMx27DC_Disp_WIDTH 8
-#define GMMx27DC_Disp_MASK 0xff0000
-#define GMMx27DC_Reserved_31_24_OFFSET 24
-#define GMMx27DC_Reserved_31_24_WIDTH 8
-#define GMMx27DC_Reserved_31_24_MASK 0xff000000
-
-/// GMMx27DC
-typedef union {
- struct { ///<
- UINT32 Lcl:8 ; ///<
- UINT32 Hub:8 ; ///<
- UINT32 Disp:8 ; ///<
- UINT32 Reserved_31_24:8 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx27DC_STRUCT;
-
-// **** GMMx27E0 Register Definition ****
-// Address
-#define GMMx27E0_ADDRESS 0x27e0
-
-// Type
-#define GMMx27E0_TYPE TYPE_GMM
-// Field Data
-#define GMMx27E0_Lcl_OFFSET 0
-#define GMMx27E0_Lcl_WIDTH 8
-#define GMMx27E0_Lcl_MASK 0xff
-#define GMMx27E0_Hub_OFFSET 8
-#define GMMx27E0_Hub_WIDTH 8
-#define GMMx27E0_Hub_MASK 0xff00
-#define GMMx27E0_Reserved_31_16_OFFSET 16
-#define GMMx27E0_Reserved_31_16_WIDTH 16
-#define GMMx27E0_Reserved_31_16_MASK 0xffff0000
-
-/// GMMx27E0
-typedef union {
- struct { ///<
- UINT32 Lcl:8 ; ///<
- UINT32 Hub:8 ; ///<
- UINT32 Reserved_31_16:16; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx27E0_STRUCT;
-
-// **** GMMx2814 Register Definition ****
-// Address
-#define GMMx2814_ADDRESS 0x2814
-
-// Type
-#define GMMx2814_TYPE TYPE_GMM
-// Field Data
-#define GMMx2814_WriteClks_OFFSET 0
-#define GMMx2814_WriteClks_WIDTH 9
-#define GMMx2814_WriteClks_MASK 0x1ff
-#define GMMx2814_UvdHarshPriority_OFFSET 9
-#define GMMx2814_UvdHarshPriority_WIDTH 1
-#define GMMx2814_UvdHarshPriority_MASK 0x200
-#define GMMx2814_Reserved_31_10_OFFSET 10
-#define GMMx2814_Reserved_31_10_WIDTH 22
-#define GMMx2814_Reserved_31_10_MASK 0xfffffc00
-
-/// GMMx2814
-typedef union {
- struct { ///<
- UINT32 WriteClks:9 ; ///<
- UINT32 UvdHarshPriority:1 ; ///<
- UINT32 Reserved_31_10:22; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx2814_STRUCT;
-
-// **** GMMx281C Register Definition ****
-// Address
-#define GMMx281C_ADDRESS 0x281c
-
-// Type
-#define GMMx281C_TYPE TYPE_GMM
-// Field Data
-#define GMMx281C_CSEnable_OFFSET 0
-#define GMMx281C_CSEnable_WIDTH 1
-#define GMMx281C_CSEnable_MASK 0x1
-#define GMMx281C_Reserved_4_1_OFFSET 1
-#define GMMx281C_Reserved_4_1_WIDTH 4
-#define GMMx281C_Reserved_4_1_MASK 0x1e
-#define GMMx281C_BaseAddr_21_13__OFFSET 5
-#define GMMx281C_BaseAddr_21_13__WIDTH 9
-#define GMMx281C_BaseAddr_21_13__MASK 0x3fe0
-#define GMMx281C_Reserved_18_14_OFFSET 14
-#define GMMx281C_Reserved_18_14_WIDTH 5
-#define GMMx281C_Reserved_18_14_MASK 0x7c000
-#define GMMx281C_BaseAddr_35_27__OFFSET 19
-#define GMMx281C_BaseAddr_35_27__WIDTH 9
-#define GMMx281C_BaseAddr_35_27__MASK 0xff80000
-#define GMMx281C_Reserved_31_28_OFFSET 28
-#define GMMx281C_Reserved_31_28_WIDTH 4
-#define GMMx281C_Reserved_31_28_MASK 0xf0000000
-
-/// GMMx281C
-typedef union {
- struct { ///<
- UINT32 CSEnable:1 ; ///<
- UINT32 Reserved_4_1:4 ; ///<
- UINT32 BaseAddr_21_13_:9 ; ///<
- UINT32 Reserved_18_14:5 ; ///<
- UINT32 BaseAddr_35_27_:9 ; ///<
- UINT32 Reserved_31_28:4 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx281C_STRUCT;
-
-// **** GMMx2824 Register Definition ****
-// Address
-#define GMMx2824_ADDRESS 0x2824
-
-// Type
-#define GMMx2824_TYPE TYPE_GMM
-// Field Data
-#define GMMx2824_CSEnable_OFFSET 0
-#define GMMx2824_CSEnable_WIDTH 1
-#define GMMx2824_CSEnable_MASK 0x1
-#define GMMx2824_Reserved_4_1_OFFSET 1
-#define GMMx2824_Reserved_4_1_WIDTH 4
-#define GMMx2824_Reserved_4_1_MASK 0x1e
-#define GMMx2824_BaseAddr_21_13__OFFSET 5
-#define GMMx2824_BaseAddr_21_13__WIDTH 9
-#define GMMx2824_BaseAddr_21_13__MASK 0x3fe0
-#define GMMx2824_Reserved_18_14_OFFSET 14
-#define GMMx2824_Reserved_18_14_WIDTH 5
-#define GMMx2824_Reserved_18_14_MASK 0x7c000
-#define GMMx2824_BaseAddr_35_27__OFFSET 19
-#define GMMx2824_BaseAddr_35_27__WIDTH 9
-#define GMMx2824_BaseAddr_35_27__MASK 0xff80000
-#define GMMx2824_Reserved_31_28_OFFSET 28
-#define GMMx2824_Reserved_31_28_WIDTH 4
-#define GMMx2824_Reserved_31_28_MASK 0xf0000000
-
-/// GMMx2824
-typedef union {
- struct { ///<
- UINT32 CSEnable:1 ; ///<
- UINT32 Reserved_4_1:4 ; ///<
- UINT32 BaseAddr_21_13_:9 ; ///<
- UINT32 Reserved_18_14:5 ; ///<
- UINT32 BaseAddr_35_27_:9 ; ///<
- UINT32 Reserved_31_28:4 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx2824_STRUCT;
-
-// **** GMMx282C Register Definition ****
-// Address
-#define GMMx282C_ADDRESS 0x282c
-
-// Type
-#define GMMx282C_TYPE TYPE_GMM
-// Field Data
-#define GMMx282C_CSEnable_OFFSET 0
-#define GMMx282C_CSEnable_WIDTH 1
-#define GMMx282C_CSEnable_MASK 0x1
-#define GMMx282C_Reserved_4_1_OFFSET 1
-#define GMMx282C_Reserved_4_1_WIDTH 4
-#define GMMx282C_Reserved_4_1_MASK 0x1e
-#define GMMx282C_BaseAddr_21_13__OFFSET 5
-#define GMMx282C_BaseAddr_21_13__WIDTH 9
-#define GMMx282C_BaseAddr_21_13__MASK 0x3fe0
-#define GMMx282C_Reserved_18_14_OFFSET 14
-#define GMMx282C_Reserved_18_14_WIDTH 5
-#define GMMx282C_Reserved_18_14_MASK 0x7c000
-#define GMMx282C_BaseAddr_35_27__OFFSET 19
-#define GMMx282C_BaseAddr_35_27__WIDTH 9
-#define GMMx282C_BaseAddr_35_27__MASK 0xff80000
-#define GMMx282C_Reserved_31_28_OFFSET 28
-#define GMMx282C_Reserved_31_28_WIDTH 4
-#define GMMx282C_Reserved_31_28_MASK 0xf0000000
-
-/// GMMx282C
-typedef union {
- struct { ///<
- UINT32 CSEnable:1 ; ///<
- UINT32 Reserved_4_1:4 ; ///<
- UINT32 BaseAddr_21_13_:9 ; ///<
- UINT32 Reserved_18_14:5 ; ///<
- UINT32 BaseAddr_35_27_:9 ; ///<
- UINT32 Reserved_31_28:4 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx282C_STRUCT;
-
-// **** GMMx2834 Register Definition ****
-// Address
-#define GMMx2834_ADDRESS 0x2834
-
-// Type
-#define GMMx2834_TYPE TYPE_GMM
-// Field Data
-#define GMMx2834_CSEnable_OFFSET 0
-#define GMMx2834_CSEnable_WIDTH 1
-#define GMMx2834_CSEnable_MASK 0x1
-#define GMMx2834_Reserved_4_1_OFFSET 1
-#define GMMx2834_Reserved_4_1_WIDTH 4
-#define GMMx2834_Reserved_4_1_MASK 0x1e
-#define GMMx2834_BaseAddr_21_13__OFFSET 5
-#define GMMx2834_BaseAddr_21_13__WIDTH 9
-#define GMMx2834_BaseAddr_21_13__MASK 0x3fe0
-#define GMMx2834_Reserved_18_14_OFFSET 14
-#define GMMx2834_Reserved_18_14_WIDTH 5
-#define GMMx2834_Reserved_18_14_MASK 0x7c000
-#define GMMx2834_BaseAddr_35_27__OFFSET 19
-#define GMMx2834_BaseAddr_35_27__WIDTH 9
-#define GMMx2834_BaseAddr_35_27__MASK 0xff80000
-#define GMMx2834_Reserved_31_28_OFFSET 28
-#define GMMx2834_Reserved_31_28_WIDTH 4
-#define GMMx2834_Reserved_31_28_MASK 0xf0000000
-
-/// GMMx2834
-typedef union {
- struct { ///<
- UINT32 CSEnable:1 ; ///<
- UINT32 Reserved_4_1:4 ; ///<
- UINT32 BaseAddr_21_13_:9 ; ///<
- UINT32 Reserved_18_14:5 ; ///<
- UINT32 BaseAddr_35_27_:9 ; ///<
- UINT32 Reserved_31_28:4 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx2834_STRUCT;
-
-// **** GMMx283C Register Definition ****
-// Address
-#define GMMx283C_ADDRESS 0x283c
-
-// Type
-#define GMMx283C_TYPE TYPE_GMM
-// Field Data
-#define GMMx283C_Reserved_4_0_OFFSET 0
-#define GMMx283C_Reserved_4_0_WIDTH 5
-#define GMMx283C_Reserved_4_0_MASK 0x1f
-#define GMMx283C_AddrMask_21_13__OFFSET 5
-#define GMMx283C_AddrMask_21_13__WIDTH 9
-#define GMMx283C_AddrMask_21_13__MASK 0x3fe0
-#define GMMx283C_Reserved_18_14_OFFSET 14
-#define GMMx283C_Reserved_18_14_WIDTH 5
-#define GMMx283C_Reserved_18_14_MASK 0x7c000
-#define GMMx283C_AddrMask_35_27__OFFSET 19
-#define GMMx283C_AddrMask_35_27__WIDTH 9
-#define GMMx283C_AddrMask_35_27__MASK 0xff80000
-#define GMMx283C_Reserved_28_28_OFFSET 28
-#define GMMx283C_Reserved_28_28_WIDTH 1
-#define GMMx283C_Reserved_28_28_MASK 0x10000000
-#define GMMx283C_Reserved_31_29_OFFSET 29
-#define GMMx283C_Reserved_31_29_WIDTH 3
-#define GMMx283C_Reserved_31_29_MASK 0xe0000000
-
-/// GMMx283C
-typedef union {
- struct { ///<
- UINT32 Reserved_4_0:5 ; ///<
- UINT32 AddrMask_21_13_:9 ; ///<
- UINT32 Reserved_18_14:5 ; ///<
- UINT32 AddrMask_35_27_:9 ; ///<
- UINT32 Reserved_28_28:1 ; ///<
- UINT32 Reserved_31_29:3 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx283C_STRUCT;
-
-// **** GMMx2840 Register Definition ****
-// Address
-#define GMMx2840_ADDRESS 0x2840
-
-// Type
-#define GMMx2840_TYPE TYPE_GMM
-// Field Data
-#define GMMx2840_Reserved_4_0_OFFSET 0
-#define GMMx2840_Reserved_4_0_WIDTH 5
-#define GMMx2840_Reserved_4_0_MASK 0x1f
-#define GMMx2840_AddrMask_21_13__OFFSET 5
-#define GMMx2840_AddrMask_21_13__WIDTH 9
-#define GMMx2840_AddrMask_21_13__MASK 0x3fe0
-#define GMMx2840_Reserved_18_14_OFFSET 14
-#define GMMx2840_Reserved_18_14_WIDTH 5
-#define GMMx2840_Reserved_18_14_MASK 0x7c000
-#define GMMx2840_AddrMask_35_27__OFFSET 19
-#define GMMx2840_AddrMask_35_27__WIDTH 9
-#define GMMx2840_AddrMask_35_27__MASK 0xff80000
-#define GMMx2840_Reserved_28_28_OFFSET 28
-#define GMMx2840_Reserved_28_28_WIDTH 1
-#define GMMx2840_Reserved_28_28_MASK 0x10000000
-#define GMMx2840_Reserved_31_29_OFFSET 29
-#define GMMx2840_Reserved_31_29_WIDTH 3
-#define GMMx2840_Reserved_31_29_MASK 0xe0000000
-
-/// GMMx2840
-typedef union {
- struct { ///<
- UINT32 Reserved_4_0:5 ; ///<
- UINT32 AddrMask_21_13_:9 ; ///<
- UINT32 Reserved_18_14:5 ; ///<
- UINT32 AddrMask_35_27_:9 ; ///<
- UINT32 Reserved_28_28:1 ; ///<
- UINT32 Reserved_31_29:3 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx2840_STRUCT;
-
-// **** GMMx284C Register Definition ****
-// Address
-#define GMMx284C_ADDRESS 0x284c
-
-// Type
-#define GMMx284C_TYPE TYPE_GMM
-// Field Data
-#define GMMx284C_Dimm0AddrMap_OFFSET 0
-#define GMMx284C_Dimm0AddrMap_WIDTH 4
-#define GMMx284C_Dimm0AddrMap_MASK 0xf
-#define GMMx284C_Dimm1AddrMap_OFFSET 4
-#define GMMx284C_Dimm1AddrMap_WIDTH 4
-#define GMMx284C_Dimm1AddrMap_MASK 0xf0
-#define GMMx284C_Reserved_15_8_OFFSET 8
-#define GMMx284C_Reserved_15_8_WIDTH 8
-#define GMMx284C_Reserved_15_8_MASK 0xff00
-#define GMMx284C_BankSwizzleMode_OFFSET 16
-#define GMMx284C_BankSwizzleMode_WIDTH 1
-#define GMMx284C_BankSwizzleMode_MASK 0x10000
-#define GMMx284C_Reserved_18_17_OFFSET 17
-#define GMMx284C_Reserved_18_17_WIDTH 2
-#define GMMx284C_Reserved_18_17_MASK 0x60000
-#define GMMx284C_BankSwap_OFFSET 19
-#define GMMx284C_BankSwap_WIDTH 1
-#define GMMx284C_BankSwap_MASK 0x80000
-#define GMMx284C_Reserved_31_20_OFFSET 20
-#define GMMx284C_Reserved_31_20_WIDTH 12
-#define GMMx284C_Reserved_31_20_MASK 0xfff00000
-
-/// GMMx284C
-typedef union {
- struct { ///<
- UINT32 Dimm0AddrMap:4 ; ///<
- UINT32 Dimm1AddrMap:4 ; ///<
- UINT32 Reserved_15_8:8 ; ///<
- UINT32 BankSwizzleMode:1 ; ///<
- UINT32 Reserved_18_17:2 ; ///<
- UINT32 BankSwap:1 ; ///<
- UINT32 Reserved_31_20:12; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx284C_STRUCT;
-
-// **** GMMx2858 Register Definition ****
-// Address
-#define GMMx2858_ADDRESS 0x2858
-
-// Type
-#define GMMx2858_TYPE TYPE_GMM
-// Field Data
-#define GMMx2858_Reserved_8_0_OFFSET 0
-#define GMMx2858_Reserved_8_0_WIDTH 9
-#define GMMx2858_Reserved_8_0_MASK 0x1ff
-#define GMMx2858_DctSelBankSwap_OFFSET 9
-#define GMMx2858_DctSelBankSwap_WIDTH 1
-#define GMMx2858_DctSelBankSwap_MASK 0x200
-#define GMMx2858_Reserved_31_10_OFFSET 10
-#define GMMx2858_Reserved_31_10_WIDTH 22
-#define GMMx2858_Reserved_31_10_MASK 0xfffffc00
-
-/// GMMx2858
-typedef union {
- struct { ///<
- UINT32 Reserved_8_0:9 ; ///<
- UINT32 DctSelBankSwap:1 ; ///<
- UINT32 Reserved_31_10:22; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx2858_STRUCT;
-
-// **** GMMx285C Register Definition ****
-// Address
-#define GMMx285C_ADDRESS 0x285c
-
-// Type
-#define GMMx285C_TYPE TYPE_GMM
-// Field Data
-#define GMMx285C_DramHoleValid_OFFSET 0
-#define GMMx285C_DramHoleValid_WIDTH 1
-#define GMMx285C_DramHoleValid_MASK 0x1
-#define GMMx285C_Reserved_6_1_OFFSET 1
-#define GMMx285C_Reserved_6_1_WIDTH 6
-#define GMMx285C_Reserved_6_1_MASK 0x7e
-#define GMMx285C_DramHoleOffset_31_23__OFFSET 7
-#define GMMx285C_DramHoleOffset_31_23__WIDTH 9
-#define GMMx285C_DramHoleOffset_31_23__MASK 0xff80
-#define GMMx285C_Reserved_23_16_OFFSET 16
-#define GMMx285C_Reserved_23_16_WIDTH 8
-#define GMMx285C_Reserved_23_16_MASK 0xff0000
-#define GMMx285C_DramHoleBase_31_24__OFFSET 24
-#define GMMx285C_DramHoleBase_31_24__WIDTH 8
-#define GMMx285C_DramHoleBase_31_24__MASK 0xff000000
-
-/// GMMx285C
-typedef union {
- struct { ///<
- UINT32 DramHoleValid:1 ; ///<
- UINT32 Reserved_6_1:6 ; ///<
- UINT32 DramHoleOffset_31_23_:9 ; ///<
- UINT32 Reserved_23_16:8 ; ///<
- UINT32 DramHoleBase_31_24_:8 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx285C_STRUCT;
-
-// **** GMMx2864 Register Definition ****
-// Address
-#define GMMx2864_ADDRESS 0x2864
-
-// Type
-#define GMMx2864_TYPE TYPE_GMM
-// Field Data
-#define GMMx2864_A8Map_OFFSET 0
-#define GMMx2864_A8Map_WIDTH 4
-#define GMMx2864_A8Map_MASK 0xf
-#define GMMx2864_A9Map_OFFSET 4
-#define GMMx2864_A9Map_WIDTH 4
-#define GMMx2864_A9Map_MASK 0xf0
-#define GMMx2864_A10Map_OFFSET 8
-#define GMMx2864_A10Map_WIDTH 4
-#define GMMx2864_A10Map_MASK 0xf00
-#define GMMx2864_A11Map_OFFSET 12
-#define GMMx2864_A11Map_WIDTH 4
-#define GMMx2864_A11Map_MASK 0xf000
-#define GMMx2864_A12Map_OFFSET 16
-#define GMMx2864_A12Map_WIDTH 4
-#define GMMx2864_A12Map_MASK 0xf0000
-#define GMMx2864_A13Map_OFFSET 20
-#define GMMx2864_A13Map_WIDTH 4
-#define GMMx2864_A13Map_MASK 0xf00000
-#define GMMx2864_A14Map_OFFSET 24
-#define GMMx2864_A14Map_WIDTH 4
-#define GMMx2864_A14Map_MASK 0xf000000
-#define GMMx2864_A15Map_OFFSET 28
-#define GMMx2864_A15Map_WIDTH 4
-#define GMMx2864_A15Map_MASK 0xf0000000
-
-/// GMMx2864
-typedef union {
- struct { ///<
- UINT32 A8Map:4 ; ///<
- UINT32 A9Map:4 ; ///<
- UINT32 A10Map:4 ; ///<
- UINT32 A11Map:4 ; ///<
- UINT32 A12Map:4 ; ///<
- UINT32 A13Map:4 ; ///<
- UINT32 A14Map:4 ; ///<
- UINT32 A15Map:4 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx2864_STRUCT;
-
-// **** GMMx286C Register Definition ****
-// Address
-#define GMMx286C_ADDRESS 0x286c
-
-// Type
-#define GMMx286C_TYPE TYPE_GMM
-// Field Data
-#define GMMx286C_Base_OFFSET 0
-#define GMMx286C_Base_WIDTH 20
-#define GMMx286C_Base_MASK 0xfffff
-#define GMMx286C_Reserved_31_20_OFFSET 20
-#define GMMx286C_Reserved_31_20_WIDTH 12
-#define GMMx286C_Reserved_31_20_MASK 0xfff00000
-
-/// GMMx286C
-typedef union {
- struct { ///<
- UINT32 Base:20; ///<
- UINT32 Reserved_31_20:12; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx286C_STRUCT;
-
-// **** GMMx2870 Register Definition ****
-// Address
-#define GMMx2870_ADDRESS 0x2870
-
-// Type
-#define GMMx2870_TYPE TYPE_GMM
-// Field Data
-#define GMMx2870_Base_OFFSET 0
-#define GMMx2870_Base_WIDTH 20
-#define GMMx2870_Base_MASK 0xfffff
-#define GMMx2870_Reserved_31_20_OFFSET 20
-#define GMMx2870_Reserved_31_20_WIDTH 12
-#define GMMx2870_Reserved_31_20_MASK 0xfff00000
-
-/// GMMx2870
-typedef union {
- struct { ///<
- UINT32 Base:20; ///<
- UINT32 Reserved_31_20:12; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx2870_STRUCT;
-
-// **** GMMx2874 Register Definition ****
-// Address
-#define GMMx2874_ADDRESS 0x2874
-
-// Type
-#define GMMx2874_TYPE TYPE_GMM
-// Field Data
-#define GMMx2874_Base_OFFSET 0
-#define GMMx2874_Base_WIDTH 20
-#define GMMx2874_Base_MASK 0xfffff
-#define GMMx2874_Reserved_31_20_OFFSET 20
-#define GMMx2874_Reserved_31_20_WIDTH 12
-#define GMMx2874_Reserved_31_20_MASK 0xfff00000
-
-/// GMMx2874
-typedef union {
- struct { ///<
- UINT32 Base:20; ///<
- UINT32 Reserved_31_20:12; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx2874_STRUCT;
-
-// **** GMMx2878 Register Definition ****
-// Address
-#define GMMx2878_ADDRESS 0x2878
-
-// Type
-#define GMMx2878_TYPE TYPE_GMM
-// Field Data
-#define GMMx2878_Base_OFFSET 0
-#define GMMx2878_Base_WIDTH 20
-#define GMMx2878_Base_MASK 0xfffff
-#define GMMx2878_Reserved_31_20_OFFSET 20
-#define GMMx2878_Reserved_31_20_WIDTH 12
-#define GMMx2878_Reserved_31_20_MASK 0xfff00000
-
-/// GMMx2878
-typedef union {
- struct { ///<
- UINT32 Base:20; ///<
- UINT32 Reserved_31_20:12; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx2878_STRUCT;
-
-// **** GMMx287C Register Definition ****
-// Address
-#define GMMx287C_ADDRESS 0x287c
-
-// Type
-#define GMMx287C_TYPE TYPE_GMM
-// Field Data
-#define GMMx287C_Top_OFFSET 0
-#define GMMx287C_Top_WIDTH 20
-#define GMMx287C_Top_MASK 0xfffff
-#define GMMx287C_Reserved_31_20_OFFSET 20
-#define GMMx287C_Reserved_31_20_WIDTH 12
-#define GMMx287C_Reserved_31_20_MASK 0xfff00000
-
-/// GMMx287C
-typedef union {
- struct { ///<
- UINT32 Top:20; ///<
- UINT32 Reserved_31_20:12; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx287C_STRUCT;
-
-// **** GMMx2880 Register Definition ****
-// Address
-#define GMMx2880_ADDRESS 0x2880
-
-// Type
-#define GMMx2880_TYPE TYPE_GMM
-// Field Data
-#define GMMx2880_Top_OFFSET 0
-#define GMMx2880_Top_WIDTH 20
-#define GMMx2880_Top_MASK 0xfffff
-#define GMMx2880_Reserved_31_20_OFFSET 20
-#define GMMx2880_Reserved_31_20_WIDTH 12
-#define GMMx2880_Reserved_31_20_MASK 0xfff00000
-
-/// GMMx2880
-typedef union {
- struct { ///<
- UINT32 Top:20; ///<
- UINT32 Reserved_31_20:12; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx2880_STRUCT;
-
-// **** GMMx2884 Register Definition ****
-// Address
-#define GMMx2884_ADDRESS 0x2884
-
-// Type
-#define GMMx2884_TYPE TYPE_GMM
-// Field Data
-#define GMMx2884_Top_OFFSET 0
-#define GMMx2884_Top_WIDTH 20
-#define GMMx2884_Top_MASK 0xfffff
-#define GMMx2884_Reserved_31_20_OFFSET 20
-#define GMMx2884_Reserved_31_20_WIDTH 12
-#define GMMx2884_Reserved_31_20_MASK 0xfff00000
-
-/// GMMx2884
-typedef union {
- struct { ///<
- UINT32 Top:20; ///<
- UINT32 Reserved_31_20:12; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx2884_STRUCT;
-
-// **** GMMx2888 Register Definition ****
-// Address
-#define GMMx2888_ADDRESS 0x2888
-
-// Type
-#define GMMx2888_TYPE TYPE_GMM
-// Field Data
-#define GMMx2888_Top_OFFSET 0
-#define GMMx2888_Top_WIDTH 20
-#define GMMx2888_Top_MASK 0xfffff
-#define GMMx2888_Reserved_31_20_OFFSET 20
-#define GMMx2888_Reserved_31_20_WIDTH 12
-#define GMMx2888_Reserved_31_20_MASK 0xfff00000
-
-/// GMMx2888
-typedef union {
- struct { ///<
- UINT32 Top:20; ///<
- UINT32 Reserved_31_20:12; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx2888_STRUCT;
-
-// **** GMMx288C Register Definition ****
-// Address
-#define GMMx288C_ADDRESS 0x288c
-
-// Type
-#define GMMx288C_TYPE TYPE_GMM
-// Field Data
-#define GMMx288C_Base_OFFSET 0
-#define GMMx288C_Base_WIDTH 20
-#define GMMx288C_Base_MASK 0xfffff
-#define GMMx288C_Reserved_31_20_OFFSET 20
-#define GMMx288C_Reserved_31_20_WIDTH 12
-#define GMMx288C_Reserved_31_20_MASK 0xfff00000
-
-/// GMMx288C
-typedef union {
- struct { ///<
- UINT32 Base:20; ///<
- UINT32 Reserved_31_20:12; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx288C_STRUCT;
-
-// **** GMMx2890 Register Definition ****
-// Address
-#define GMMx2890_ADDRESS 0x2890
-
-// Type
-#define GMMx2890_TYPE TYPE_GMM
-// Field Data
-#define GMMx2890_Top_OFFSET 0
-#define GMMx2890_Top_WIDTH 20
-#define GMMx2890_Top_MASK 0xfffff
-#define GMMx2890_Reserved_31_20_OFFSET 20
-#define GMMx2890_Reserved_31_20_WIDTH 12
-#define GMMx2890_Reserved_31_20_MASK 0xfff00000
-
-/// GMMx2890
-typedef union {
- struct { ///<
- UINT32 Top:20; ///<
- UINT32 Reserved_31_20:12; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx2890_STRUCT;
-
-// **** GMMx2894 Register Definition ****
-// Address
-#define GMMx2894_ADDRESS 0x2894
-
-// Type
-#define GMMx2894_TYPE TYPE_GMM
-// Field Data
-#define GMMx2894_Def_OFFSET 0
-#define GMMx2894_Def_WIDTH 28
-#define GMMx2894_Def_MASK 0xfffffff
-#define GMMx2894_Reserved_31_28_OFFSET 28
-#define GMMx2894_Reserved_31_28_WIDTH 4
-#define GMMx2894_Reserved_31_28_MASK 0xf0000000
-
-/// GMMx2894
-typedef union {
- struct { ///<
- UINT32 Def:28; ///<
- UINT32 Reserved_31_28:4 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx2894_STRUCT;
-
-// **** GMMx2898 Register Definition ****
-// Address
-#define GMMx2898_ADDRESS 0x2898
-
-// Type
-#define GMMx2898_TYPE TYPE_GMM
-// Field Data
-#define GMMx2898_Offset_OFFSET 0
-#define GMMx2898_Offset_WIDTH 20
-#define GMMx2898_Offset_MASK 0xfffff
-#define GMMx2898_Base_OFFSET 20
-#define GMMx2898_Base_WIDTH 4
-#define GMMx2898_Base_MASK 0xf00000
-#define GMMx2898_Top_OFFSET 24
-#define GMMx2898_Top_WIDTH 4
-#define GMMx2898_Top_MASK 0xf000000
-#define GMMx2898_Reserved_31_28_OFFSET 28
-#define GMMx2898_Reserved_31_28_WIDTH 4
-#define GMMx2898_Reserved_31_28_MASK 0xf0000000
-
-/// GMMx2898
-typedef union {
- struct { ///<
- UINT32 Offset:20; ///<
- UINT32 Base:4 ; ///<
- UINT32 Top:4 ; ///<
- UINT32 Reserved_31_28:4 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx2898_STRUCT;
-
-// **** GMMx28D8 Register Definition ****
-// Address
-#define GMMx28D8_ADDRESS 0x28d8
-
-// Type
-#define GMMx28D8_TYPE TYPE_GMM
-// Field Data
-#define GMMx28D8_ActRd_OFFSET 0
-#define GMMx28D8_ActRd_WIDTH 8
-#define GMMx28D8_ActRd_MASK 0xff
-#define GMMx28D8_ActWr_OFFSET 8
-#define GMMx28D8_ActWr_WIDTH 8
-#define GMMx28D8_ActWr_MASK 0xff00
-#define GMMx28D8_RasMActRd_OFFSET 16
-#define GMMx28D8_RasMActRd_WIDTH 8
-#define GMMx28D8_RasMActRd_MASK 0xff0000
-#define GMMx28D8_RasMActWr_OFFSET 24
-#define GMMx28D8_RasMActWr_WIDTH 8
-#define GMMx28D8_RasMActWr_MASK 0xff000000
-
-/// GMMx28D8
-typedef union {
- struct { ///<
- UINT32 ActRd:8 ; ///<
- UINT32 ActWr:8 ; ///<
- UINT32 RasMActRd:8 ; ///<
- UINT32 RasMActWr:8 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx28D8_STRUCT;
-
-// **** GMMx28DC Register Definition ****
-// Address
-#define GMMx28DC_ADDRESS 0x28dc
-
-// Type
-#define GMMx28DC_TYPE TYPE_GMM
-// Field Data
-#define GMMx28DC_Ras2Ras_OFFSET 0
-#define GMMx28DC_Ras2Ras_WIDTH 8
-#define GMMx28DC_Ras2Ras_MASK 0xff
-#define GMMx28DC_Rp_OFFSET 8
-#define GMMx28DC_Rp_WIDTH 8
-#define GMMx28DC_Rp_MASK 0xff00
-#define GMMx28DC_WrPlusRp_OFFSET 16
-#define GMMx28DC_WrPlusRp_WIDTH 8
-#define GMMx28DC_WrPlusRp_MASK 0xff0000
-#define GMMx28DC_BusTurn_OFFSET 24
-#define GMMx28DC_BusTurn_WIDTH 8
-#define GMMx28DC_BusTurn_MASK 0xff000000
-
-/// GMMx28DC
-typedef union {
- struct { ///<
- UINT32 Ras2Ras:8 ; ///<
- UINT32 Rp:8 ; ///<
- UINT32 WrPlusRp:8 ; ///<
- UINT32 BusTurn:8 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx28DC_STRUCT;
-
-// **** GMMx2B8C Register Definition ****
-// Address
-#define GMMx2B8C_ADDRESS 0x2b8c
-
-// Type
-#define GMMx2B8C_TYPE TYPE_GMM
-// Field Data
-#define GMMx2B8C_RengRamIndex_OFFSET 0
-#define GMMx2B8C_RengRamIndex_WIDTH 10
-#define GMMx2B8C_RengRamIndex_MASK 0x3ff
-#define GMMx2B8C_Reserved_31_10_OFFSET 10
-#define GMMx2B8C_Reserved_31_10_WIDTH 22
-#define GMMx2B8C_Reserved_31_10_MASK 0xfffffc00
-
-/// GMMx2B8C
-typedef union {
- struct { ///<
- UINT32 RengRamIndex:10; ///<
- UINT32 Reserved_31_10:22; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx2B8C_STRUCT;
-
-// **** GMMx2B90 Register Definition ****
-// Address
-#define GMMx2B90_ADDRESS 0x2b90
-
-// Type
-#define GMMx2B90_TYPE TYPE_GMM
-// Field Data
-#define GMMx2B90_RengRamData_OFFSET 0
-#define GMMx2B90_RengRamData_WIDTH 32
-#define GMMx2B90_RengRamData_MASK 0xffffffff
-
-/// GMMx2B90
-typedef union {
- struct { ///<
- UINT32 RengRamData:32; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx2B90_STRUCT;
-
-// **** GMMx2C04 Register Definition ****
-// Address
-#define GMMx2C04_ADDRESS 0x2c04
-
-// Type
-#define GMMx2C04_TYPE TYPE_GMM
-// Field Data
-#define GMMx2C04_NonsurfBase_OFFSET 0
-#define GMMx2C04_NonsurfBase_WIDTH 28
-#define GMMx2C04_NonsurfBase_MASK 0xfffffff
-#define GMMx2C04_Reserved_31_28_OFFSET 28
-#define GMMx2C04_Reserved_31_28_WIDTH 4
-#define GMMx2C04_Reserved_31_28_MASK 0xf0000000
-
-/// GMMx2C04
-typedef union {
- struct { ///<
- UINT32 NonsurfBase:28; ///<
- UINT32 Reserved_31_28:4 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx2C04_STRUCT;
-
-// **** GMMx5428 Register Definition ****
-// Address
-#define GMMx5428_ADDRESS 0x5428
-
-// Type
-#define GMMx5428_TYPE TYPE_GMM
-// Field Data
-#define GMMx5428_ConfigMemsize_OFFSET 0
-#define GMMx5428_ConfigMemsize_WIDTH 32
-#define GMMx5428_ConfigMemsize_MASK 0xffffffff
-
-/// GMMx5428
-typedef union {
- struct { ///<
- UINT32 ConfigMemsize:32; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx5428_STRUCT;
-
-// **** GMMx5490 Register Definition ****
-// Address
-#define GMMx5490_ADDRESS 0x5490
-
-// Type
-#define GMMx5490_TYPE TYPE_GMM
-// Field Data
-#define GMMx5490_FbReadEn_OFFSET 0
-#define GMMx5490_FbReadEn_WIDTH 1
-#define GMMx5490_FbReadEn_MASK 0x1
-#define GMMx5490_FbWriteEn_OFFSET 1
-#define GMMx5490_FbWriteEn_WIDTH 1
-#define GMMx5490_FbWriteEn_MASK 0x2
-#define GMMx5490_Reserved_31_2_OFFSET 2
-#define GMMx5490_Reserved_31_2_WIDTH 30
-#define GMMx5490_Reserved_31_2_MASK 0xfffffffc
-
-/// GMMx5490
-typedef union {
- struct { ///<
- UINT32 FbReadEn:1 ; ///<
- UINT32 FbWriteEn:1 ; ///<
- UINT32 Reserved_31_2:30; ///<
- } Field; ///<
- UINT32 Value; ///<
-} GMMx5490_STRUCT;
-
-// **** SMUx03 Register Definition ****
-// Address
-#define SMUx03_ADDRESS 0x3
-
-// Type
-#define SMUx03_TYPE TYPE_SMU
-// Field Data
-#define SMUx03_IntReq_OFFSET 0
-#define SMUx03_IntReq_WIDTH 1
-#define SMUx03_IntReq_MASK 0x1
-#define SMUx03_IntAck_OFFSET 1
-#define SMUx03_IntAck_WIDTH 1
-#define SMUx03_IntAck_MASK 0x2
-#define SMUx03_IntDone_OFFSET 2
-#define SMUx03_IntDone_WIDTH 1
-#define SMUx03_IntDone_MASK 0x4
-#define SMUx03_ServiceIndex_OFFSET 3
-#define SMUx03_ServiceIndex_WIDTH 8
-#define SMUx03_ServiceIndex_MASK 0x7f8
-#define SMUx03_Reserved_31_11_OFFSET 11
-#define SMUx03_Reserved_31_11_WIDTH 21
-#define SMUx03_Reserved_31_11_MASK 0xfffff800
-
-/// SMUx03
-typedef union {
- struct { ///<
- UINT32 IntReq:1 ; ///<
- UINT32 IntAck:1 ; ///<
- UINT32 IntDone:1 ; ///<
- UINT32 ServiceIndex:8 ; ///<
- UINT32 Reserved_31_11:21; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx03_STRUCT;
-
-// **** SMUx05 Register Definition ****
-// Address
-#define SMUx05_ADDRESS 0x5
-
-// Type
-#define SMUx05_TYPE TYPE_SMU
-// Field Data
-#define SMUx05_McuRam_OFFSET 0
-#define SMUx05_McuRam_WIDTH 32
-#define SMUx05_McuRam_MASK 0xffffffff
-
-/// SMUx05
-typedef union {
- struct { ///<
- UINT32 McuRam:32; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx05_STRUCT;
-
-// **** SMUx0B Register Definition ****
-// Address
-#define SMUx0B_ADDRESS 0xb
-
-// Type
-#define SMUx0B_TYPE TYPE_SMU
-// Field Data
-#define SMUx0B_MemAddr_OFFSET 0
-#define SMUx0B_MemAddr_WIDTH 16
-#define SMUx0B_MemAddr_MASK 0xffff
-
-/// SMUx0B
-typedef union {
- struct { ///<
- UINT32 MemAddr:16; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_STRUCT;
-
-// **** MSRC001_001A Register Definition ****
-// Address
-#define MSRC001_001A_ADDRESS 0xc001001a
-
-// Type
-#define MSRC001_001A_TYPE TYPE_MSR
-// Field Data
-#define MSRC001_001A_RAZ_22_0_OFFSET 0
-#define MSRC001_001A_RAZ_22_0_WIDTH 23
-#define MSRC001_001A_RAZ_22_0_MASK 0x7fffff
-#define MSRC001_001A_TOM_35_23__OFFSET 23
-#define MSRC001_001A_TOM_35_23__WIDTH 13
-#define MSRC001_001A_TOM_35_23__MASK 0xfff800000
-#define MSRC001_001A_RAZ_63_36_OFFSET 36
-#define MSRC001_001A_RAZ_63_36_WIDTH 28
-#define MSRC001_001A_RAZ_63_36_MASK 0xfffffff000000000
-
-/// MSRC001_001A
-typedef union {
- struct { ///<
- UINT64 RAZ_22_0:23; ///<
- UINT64 TOM_35_23_:13; ///<
- UINT64 RAZ_63_36:28; ///<
- } Field; ///<
- UINT64 Value; ///<
-} MSRC001_001A_STRUCT;
-
-
-// **** FCRxFF30_0AE6(GMMx2B98) Register Definition ****
-// Address
-#define FCRxFF30_0AE6_ADDRESS 0xff300AE6
-
-// Field Data
-#define FCRxFF30_0AE6_RengExecuteNonsecureStartPtr_OFFSET 0
-#define FCRxFF30_0AE6_RengExecuteNonsecureStartPtr_WIDTH 10
-#define FCRxFF30_0AE6_RengExecuteNowMode_OFFSET 10
-#define FCRxFF30_0AE6_RengExecuteNowMode_WIDTH 1
-#define FCRxFF30_0AE6_RengExecuteOnRegUpdate_OFFSET 11
-#define FCRxFF30_0AE6_RengExecuteOnRegUpdate_WIDTH 1
-#define FCRxFF30_0AE6_RengSrbmCreditsMcd_OFFSET 12
-#define FCRxFF30_0AE6_RengSrbmCreditsMcd_WIDTH 4
-#define FCRxFF30_0AE6_StctrlStutterEn_OFFSET 16
-#define FCRxFF30_0AE6_StctrlStutterEn_WIDTH 1
-#define FCRxFF30_0AE6_StctrlGmcIdleThreshold_OFFSET 17
-#define FCRxFF30_0AE6_StctrlGmcIdleThreshold_WIDTH 2
-#define FCRxFF30_0AE6_StctrlSrbmIdleThreshold_OFFSET 19
-#define FCRxFF30_0AE6_StctrlSrbmIdleThreshold_WIDTH 2
-#define FCRxFF30_0AE6_StctrlIgnorePreSr_OFFSET 21
-#define FCRxFF30_0AE6_StctrlIgnorePreSr_WIDTH 1
-#define FCRxFF30_0AE6_StctrlIgnoreAllowStop_OFFSET 22
-#define FCRxFF30_0AE6_StctrlIgnoreAllowStop_WIDTH 1
-#define FCRxFF30_0AE6_StctrlIgnoreDramOffline_OFFSET 23
-#define FCRxFF30_0AE6_StctrlIgnoreDramOffline_WIDTH 1
-#define FCRxFF30_0AE6_StctrlIgnoreProtectionFault_OFFSET 24
-#define FCRxFF30_0AE6_StctrlIgnoreProtectionFault_WIDTH 1
-#define FCRxFF30_0AE6_StctrlDisableAllowSr_OFFSET 25
-#define FCRxFF30_0AE6_StctrlDisableAllowSr_WIDTH 1
-#define FCRxFF30_0AE6_StctrlDisableGmcOffline_OFFSET 26
-#define FCRxFF30_0AE6_StctrlDisableGmcOffline_WIDTH 1
-#define FCRxFF30_0AE6_CriticalRegsLock_OFFSET 27
-#define FCRxFF30_0AE6_CriticalRegsLock_WIDTH 1
-#define FCRxFF30_0AE6_SmuExecuteOnRegUpdate_OFFSET 28
-#define FCRxFF30_0AE6_SmuExecuteOnRegUpdate_WIDTH 1
-#define FCRxFF30_0AE6_AllowDeepSleepMode_OFFSET 29
-#define FCRxFF30_0AE6_AllowDeepSleepMode_WIDTH 2
-#define FCRxFF30_0AE6_Reserved_31_31_OFFSET 31
-#define FCRxFF30_0AE6_Reserved_31_31_WIDTH 1
-
-/// FCRxFF30_0AE6
-typedef union {
- struct { ///<
- UINT32 RengExecuteNonsecureStartPtr:10; ///<
- UINT32 RengExecuteNowMode:1 ; ///<
- UINT32 RengExecuteOnRegUpdate:1 ; ///<
- UINT32 RengSrbmCreditsMcd:4 ; ///<
- UINT32 StctrlStutterEn:1 ; ///<
- UINT32 StctrlGmcIdleThreshold:2 ; ///<
- UINT32 StctrlSrbmIdleThreshold:2 ; ///<
- UINT32 StctrlIgnorePreSr:1 ; ///<
- UINT32 StctrlIgnoreAllowStop:1 ; ///<
- UINT32 StctrlIgnoreDramOffline:1 ; ///<
- UINT32 StctrlIgnoreProtectionFault:1 ; ///<
- UINT32 StctrlDisableAllowSr:1 ; ///<
- UINT32 StctrlDisableGmcOffline:1 ; ///<
- UINT32 CriticalRegsLock:1 ; ///<
- UINT32 SmuExecuteOnRegUpdate:1 ; ///<
- UINT32 AllowDeepSleepMode:2 ; ///<
- UINT32 Reserved_31_31:1 ; ///<
- } Field;
- UINT32 Value;
-} FCRxFF30_0AE6_STRUCT;
-
-// **** FCRxFF30_0134(GMMx4D0) Register Definition ****
-// Address
-#define FCRxFF30_0134_ADDRESS 0xff300134
-
-// Field Data
-#define FCRxFF30_0134_DispclkDccgGateDisable_OFFSET 0
-#define FCRxFF30_0134_DispclkDccgGateDisable_WIDTH 1
-#define FCRxFF30_0134_DispclkDccgGateDisable_MASK 0x1
-#define FCRxFF30_0134_DispclkRDccgGateDisable_OFFSET 1
-#define FCRxFF30_0134_DispclkRDccgGateDisable_WIDTH 1
-#define FCRxFF30_0134_DispclkRDccgGateDisable_MASK 0x2
-#define FCRxFF30_0134_SclkGateDisable_OFFSET 2
-#define FCRxFF30_0134_SclkGateDisable_WIDTH 1
-#define FCRxFF30_0134_SclkGateDisable_MASK 0x4
-#define FCRxFF30_0134_Reserved_7_3_OFFSET 3
-#define FCRxFF30_0134_Reserved_7_3_WIDTH 5
-#define FCRxFF30_0134_Reserved_7_3_MASK 0xf8
-#define FCRxFF30_0134_SymclkaGateDisable_OFFSET 8
-#define FCRxFF30_0134_SymclkaGateDisable_WIDTH 1
-#define FCRxFF30_0134_SymclkaGateDisable_MASK 0x100
-#define FCRxFF30_0134_SymclkbGateDisable_OFFSET 9
-#define FCRxFF30_0134_SymclkbGateDisable_WIDTH 1
-#define FCRxFF30_0134_SymclkbGateDisable_MASK 0x200
-#define FCRxFF30_0134_Reserved_31_10_OFFSET 10
-#define FCRxFF30_0134_Reserved_31_10_WIDTH 22
-#define FCRxFF30_0134_Reserved_31_10_MASK 0xfffffc00
-
-/// FCRxFF30_0134
-typedef union {
- struct { ///<
- UINT32 DispclkDccgGateDisable:1 ; ///<
- UINT32 DispclkRDccgGateDisable:1 ; ///<
- UINT32 SclkGateDisable:1 ; ///<
- UINT32 Reserved_7_3:5 ; ///<
- UINT32 SymclkaGateDisable:1 ; ///<
- UINT32 SymclkbGateDisable:1 ; ///<
- UINT32 Reserved_31_10:22; ///<
- } Field; ///<
- UINT32 Value; ///<
-} FCRxFF30_0134_STRUCT;
-
-// **** FCRxFF30_1B7C(GMMx6DF0) Register Definition ****
-// Address
-#define FCRxFF30_1B7C_ADDRESS 0xff301B7C
-
-// Field Data
-#define FCRxFF30_1B7C_Reserved_3_0_OFFSET 0
-#define FCRxFF30_1B7C_Reserved_3_0_WIDTH 4
-#define FCRxFF30_1B7C_Reserved_3_0_MASK 0xf
-#define FCRxFF30_1B7C_CrtcDispclkRDcfeGateDisable_OFFSET 4
-#define FCRxFF30_1B7C_CrtcDispclkRDcfeGateDisable_WIDTH 1
-#define FCRxFF30_1B7C_CrtcDispclkRDcfeGateDisable_MASK 0x10
-#define FCRxFF30_1B7C_Reserved_7_5_OFFSET 5
-#define FCRxFF30_1B7C_Reserved_7_5_WIDTH 3
-#define FCRxFF30_1B7C_Reserved_7_5_MASK 0xe0
-#define FCRxFF30_1B7C_CrtcDispclkGDcpGateDisable_OFFSET 8
-#define FCRxFF30_1B7C_CrtcDispclkGDcpGateDisable_WIDTH 1
-#define FCRxFF30_1B7C_CrtcDispclkGDcpGateDisable_MASK 0x100
-#define FCRxFF30_1B7C_Reserved_11_9_OFFSET 9
-#define FCRxFF30_1B7C_Reserved_11_9_WIDTH 3
-#define FCRxFF30_1B7C_Reserved_11_9_MASK 0xe00
-#define FCRxFF30_1B7C_CrtcDispclkGSclGateDisable_OFFSET 12
-#define FCRxFF30_1B7C_CrtcDispclkGSclGateDisable_WIDTH 1
-#define FCRxFF30_1B7C_CrtcDispclkGSclGateDisable_MASK 0x1000
-#define FCRxFF30_1B7C_Reserved_31_13_OFFSET 13
-#define FCRxFF30_1B7C_Reserved_31_13_WIDTH 19
-#define FCRxFF30_1B7C_Reserved_31_13_MASK 0xffffe000
-
-/// FCRxFF30_1B7C
-typedef union {
- struct { ///<
- UINT32 Reserved_3_0:4 ; ///<
- UINT32 CrtcDispclkRDcfeGateDisable:1 ; ///<
- UINT32 Reserved_7_5:3 ; ///<
- UINT32 CrtcDispclkGDcpGateDisable:1 ; ///<
- UINT32 Reserved_11_9:3 ; ///<
- UINT32 CrtcDispclkGSclGateDisable:1 ; ///<
- UINT32 Reserved_31_13:19; ///<
- } Field; ///<
- UINT32 Value; ///<
-} FCRxFF30_1B7C_STRUCT;
-
-// **** FCRxFF30_1E7C(GMMx79F0) Register Definition ****
-// Address
-#define FCRxFF30_1E7C_ADDRESS 0xff301E7C
-
-// Field Data
-#define FCRxFF30_1E7C_Reserved_3_0_OFFSET 0
-#define FCRxFF30_1E7C_Reserved_3_0_WIDTH 4
-#define FCRxFF30_1E7C_Reserved_3_0_MASK 0xf
-#define FCRxFF30_1E7C_CrtcDispclkRDcfeGateDisable_OFFSET 4
-#define FCRxFF30_1E7C_CrtcDispclkRDcfeGateDisable_WIDTH 1
-#define FCRxFF30_1E7C_CrtcDispclkRDcfeGateDisable_MASK 0x10
-#define FCRxFF30_1E7C_Reserved_7_5_OFFSET 5
-#define FCRxFF30_1E7C_Reserved_7_5_WIDTH 3
-#define FCRxFF30_1E7C_Reserved_7_5_MASK 0xe0
-#define FCRxFF30_1E7C_CrtcDispclkGDcpGateDisable_OFFSET 8
-#define FCRxFF30_1E7C_CrtcDispclkGDcpGateDisable_WIDTH 1
-#define FCRxFF30_1E7C_CrtcDispclkGDcpGateDisable_MASK 0x100
-#define FCRxFF30_1E7C_Reserved_11_9_OFFSET 9
-#define FCRxFF30_1E7C_Reserved_11_9_WIDTH 3
-#define FCRxFF30_1E7C_Reserved_11_9_MASK 0xe00
-#define FCRxFF30_1E7C_CrtcDispclkGSclGateDisable_OFFSET 12
-#define FCRxFF30_1E7C_CrtcDispclkGSclGateDisable_WIDTH 1
-#define FCRxFF30_1E7C_CrtcDispclkGSclGateDisable_MASK 0x1000
-#define FCRxFF30_1E7C_Reserved_31_13_OFFSET 13
-#define FCRxFF30_1E7C_Reserved_31_13_WIDTH 19
-#define FCRxFF30_1E7C_Reserved_31_13_MASK 0xffffe000
-
-/// FCRxFF30_1E7C
-typedef union {
- struct { ///<
- UINT32 Reserved_3_0:4 ; ///<
- UINT32 CrtcDispclkRDcfeGateDisable:1 ; ///<
- UINT32 Reserved_7_5:3 ; ///<
- UINT32 CrtcDispclkGDcpGateDisable:1 ; ///<
- UINT32 Reserved_11_9:3 ; ///<
- UINT32 CrtcDispclkGSclGateDisable:1 ; ///<
- UINT32 Reserved_31_13:19; ///<
- } Field; ///<
- UINT32 Value; ///<
-} FCRxFF30_1E7C_STRUCT;
-
-// **** FCRxFE00_600E Register Definition ****
-// Address
-#define FCRxFE00_600E_ADDRESS 0xfe00600e
-
-// Field Data
-#define FCRxFE00_600E_MainPllOpFreqIdStartup_OFFSET 0
-#define FCRxFE00_600E_MainPllOpFreqIdStartup_WIDTH 6
-#define FCRxFE00_600E_WrCkDid_OFFSET 10
-#define FCRxFE00_600E_WrCkDid_WIDTH 5
-
-/// FCRxFE00_600E
-typedef union {
- struct {
- UINT32 MainPllOpFreqIdStartup:6 ; ///<
- UINT32 Reserved:5 ; ///<
- UINT32 WrCkDid:5 ; ///<
- } Field;
- UINT32 Value;
-} FCRxFE00_600E_STRUCT;
-
-// **** SMUx0B_x8498 Register Definition ****
-// Address
-#define SMUx0B_x8498_ADDRESS 0x8498
-
-// Field Data
-#define SMUx0B_x8498_ConditionalBF_1_0_OFFSET 0
-#define SMUx0B_x8498_ConditionalBF_1_0_WIDTH 2
-#define SMUx0B_x8498_ConditionalBF_1_0_MASK 0x3
-#define SMUx0B_x8498_ConditionalBF_3_2_OFFSET 2
-#define SMUx0B_x8498_ConditionalBF_3_2_WIDTH 2
-#define SMUx0B_x8498_ConditionalBF_3_2_MASK 0xc
-#define SMUx0B_x8498_Reserved_7_4_OFFSET 4
-#define SMUx0B_x8498_Reserved_7_4_WIDTH 4
-#define SMUx0B_x8498_Reserved_7_4_MASK 0xf0
-#define SMUx0B_x8498_ConditionalBF_9_8_OFFSET 8
-#define SMUx0B_x8498_ConditionalBF_9_8_WIDTH 2
-#define SMUx0B_x8498_ConditionalBF_9_8_MASK 0x300
-#define SMUx0B_x8498_ConditionalBF_11_10_OFFSET 10
-#define SMUx0B_x8498_ConditionalBF_11_10_WIDTH 2
-#define SMUx0B_x8498_ConditionalBF_11_10_MASK 0xc00
-#define SMUx0B_x8498_Reserved_15_12_OFFSET 12
-#define SMUx0B_x8498_Reserved_15_12_WIDTH 4
-#define SMUx0B_x8498_Reserved_15_12_MASK 0xf000
-#define SMUx0B_x8498_BaseVid_5_OFFSET 16
-#define SMUx0B_x8498_BaseVid_5_WIDTH 2
-#define SMUx0B_x8498_BaseVid_5_MASK 0x30000
-#define SMUx0B_x8498_TolExcdVid_5_OFFSET 18
-#define SMUx0B_x8498_TolExcdVid_5_WIDTH 2
-#define SMUx0B_x8498_TolExcdVid_5_MASK 0xc0000
-#define SMUx0B_x8498_Reserved_23_20_OFFSET 20
-#define SMUx0B_x8498_Reserved_23_20_WIDTH 4
-#define SMUx0B_x8498_Reserved_23_20_MASK 0xf00000
-#define SMUx0B_x8498_BaseVid_4_OFFSET 24
-#define SMUx0B_x8498_BaseVid_4_WIDTH 2
-#define SMUx0B_x8498_BaseVid_4_MASK 0x3000000
-#define SMUx0B_x8498_TolExcdVid_4_OFFSET 26
-#define SMUx0B_x8498_TolExcdVid_4_WIDTH 2
-#define SMUx0B_x8498_TolExcdVid_4_MASK 0xc000000
-#define SMUx0B_x8498_Reserved_31_28_OFFSET 28
-#define SMUx0B_x8498_Reserved_31_28_WIDTH 4
-#define SMUx0B_x8498_Reserved_31_28_MASK 0xf0000000
-
-/// SMUx0B_x8498
-typedef union {
- struct { ///<
- UINT32 ConditionalBF_1_0:2 ; ///<
- UINT32 ConditionalBF_3_2:2 ; ///<
- UINT32 Reserved_7_4:4 ; ///<
- UINT32 ConditionalBF_9_8:2 ; ///<
- UINT32 ConditionalBF_11_10:2 ; ///<
- UINT32 Reserved_15_12:4 ; ///<
- UINT32 BaseVid_5:2 ; ///<
- UINT32 TolExcdVid_5:2 ; ///<
- UINT32 Reserved_23_20:4 ; ///<
- UINT32 BaseVid_4:2 ; ///<
- UINT32 TolExcdVid_4:2 ; ///<
- UINT32 Reserved_31_28:4 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x8498_STRUCT;
-
-// **** D0F0xE4_WRAP_8013 Register Definition ****
-// Address
-#define D0F0xE4_WRAP_8013_ADDRESS 0x8013
-
-// Field Data
-#define D0F0xE4_WRAP_8013_MasterPciePllA_OFFSET 0
-#define D0F0xE4_WRAP_8013_MasterPciePllA_WIDTH 1
-#define D0F0xE4_WRAP_8013_MasterPciePllA_MASK 0x1
-#define D0F0xE4_WRAP_8013_Reserved_1_1_OFFSET 1
-#define D0F0xE4_WRAP_8013_Reserved_1_1_WIDTH 1
-#define D0F0xE4_WRAP_8013_Reserved_1_1_MASK 0x2
-#define D0F0xE4_WRAP_8013_Reserved_2_2_OFFSET 2
-#define D0F0xE4_WRAP_8013_Reserved_2_2_WIDTH 1
-#define D0F0xE4_WRAP_8013_Reserved_2_2_MASK 0x4
-#define D0F0xE4_WRAP_8013_Reserved_3_3_OFFSET 3
-#define D0F0xE4_WRAP_8013_Reserved_3_3_WIDTH 1
-#define D0F0xE4_WRAP_8013_Reserved_3_3_MASK 0x8
-#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_OFFSET 4
-#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_WIDTH 1
-#define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_MASK 0x10
-#define D0F0xE4_WRAP_8013_Reserved_5_5_OFFSET 5
-#define D0F0xE4_WRAP_8013_Reserved_5_5_WIDTH 1
-#define D0F0xE4_WRAP_8013_Reserved_5_5_MASK 0x20
-#define D0F0xE4_WRAP_8013_Reserved_6_6_OFFSET 6
-#define D0F0xE4_WRAP_8013_Reserved_6_6_WIDTH 1
-#define D0F0xE4_WRAP_8013_Reserved_6_6_MASK 0x40
-#define D0F0xE4_WRAP_8013_Reserved_7_7_OFFSET 7
-#define D0F0xE4_WRAP_8013_Reserved_7_7_WIDTH 1
-#define D0F0xE4_WRAP_8013_Reserved_7_7_MASK 0x80
-#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_OFFSET 8
-#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_WIDTH 1
-#define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_MASK 0x100
-#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_OFFSET 9
-#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_WIDTH 1
-#define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_MASK 0x200
-#define D0F0xE4_WRAP_8013_Reserved_10_10_OFFSET 10
-#define D0F0xE4_WRAP_8013_Reserved_10_10_WIDTH 1
-#define D0F0xE4_WRAP_8013_Reserved_10_10_MASK 0x400
-#define D0F0xE4_WRAP_8013_Reserved_11_11_OFFSET 11
-#define D0F0xE4_WRAP_8013_Reserved_11_11_WIDTH 1
-#define D0F0xE4_WRAP_8013_Reserved_11_11_MASK 0x800
-#define D0F0xE4_WRAP_8013_Reserved_12_12_OFFSET 12
-#define D0F0xE4_WRAP_8013_Reserved_12_12_WIDTH 1
-#define D0F0xE4_WRAP_8013_Reserved_12_12_MASK 0x1000
-#define D0F0xE4_WRAP_8013_Reserved_15_13_OFFSET 13
-#define D0F0xE4_WRAP_8013_Reserved_15_13_WIDTH 3
-#define D0F0xE4_WRAP_8013_Reserved_15_13_MASK 0xe000
-#define D0F0xE4_WRAP_8013_Reserved_16_16_OFFSET 16
-#define D0F0xE4_WRAP_8013_Reserved_16_16_WIDTH 1
-#define D0F0xE4_WRAP_8013_Reserved_16_16_MASK 0x10000
-#define D0F0xE4_WRAP_8013_Reserved_19_17_OFFSET 17
-#define D0F0xE4_WRAP_8013_Reserved_19_17_WIDTH 3
-#define D0F0xE4_WRAP_8013_Reserved_19_17_MASK 0xe0000
-#define D0F0xE4_WRAP_8013_Reserved_20_20_OFFSET 20
-#define D0F0xE4_WRAP_8013_Reserved_20_20_WIDTH 1
-#define D0F0xE4_WRAP_8013_Reserved_20_20_MASK 0x100000
-#define D0F0xE4_WRAP_8013_Reserved_31_21_OFFSET 21
-#define D0F0xE4_WRAP_8013_Reserved_31_21_WIDTH 11
-#define D0F0xE4_WRAP_8013_Reserved_31_21_MASK 0xffe00000
-
-/// D0F0xE4_WRAP_8013
-typedef union {
- struct { ///<
- UINT32 MasterPciePllA:1 ; ///<
- UINT32 MasterPciePllB:1 ; ///<
- UINT32 MasterPciePllC:1 ; ///<
- UINT32 MasterPciePllD:1 ; ///<
- UINT32 ClkDividerResetOverrideA:1 ; ///<
- UINT32 Reserved_5_5:1 ; ///<
- UINT32 Reserved_6_6:1 ; ///<
- UINT32 Reserved_7_7:1 ; ///<
- UINT32 TxclkSelCoreOverride:1 ; ///<
- UINT32 TxclkSelPifAOverride:1 ; ///<
- UINT32 Reserved_10_10:1 ; ///<
- UINT32 Reserved_11_11:1 ; ///<
- UINT32 Reserved_12_12:1 ; ///<
- UINT32 Reserved_15_13:3 ; ///<
- UINT32 Reserved_16_16:1 ; ///<
- UINT32 Reserved_19_17:3 ; ///<
- UINT32 Reserved_20_20:1 ; ///<
- UINT32 Reserved_31_21:11; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0xE4_WRAP_8013_STRUCT;
-
-// **** D0F0xE4_WRAP_8014 Register Definition ****
-// Address
-#define D0F0xE4_WRAP_8014_ADDRESS 0x8014
-
-// Field Data
-#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_OFFSET 0
-#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_WIDTH 1
-#define D0F0xE4_WRAP_8014_TxclkPermGateEnable_MASK 0x1
-#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_OFFSET 1
-#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_WIDTH 1
-#define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_MASK 0x2
-#define D0F0xE4_WRAP_8014_Reserved_2_2_OFFSET 2
-#define D0F0xE4_WRAP_8014_Reserved_2_2_WIDTH 1
-#define D0F0xE4_WRAP_8014_Reserved_2_2_MASK 0x4
-#define D0F0xE4_WRAP_8014_Reserved_3_3_OFFSET 3
-#define D0F0xE4_WRAP_8014_Reserved_3_3_WIDTH 1
-#define D0F0xE4_WRAP_8014_Reserved_3_3_MASK 0x8
-#define D0F0xE4_WRAP_8014_Reserved_4_4_OFFSET 4
-#define D0F0xE4_WRAP_8014_Reserved_4_4_WIDTH 1
-#define D0F0xE4_WRAP_8014_Reserved_4_4_MASK 0x10
-#define D0F0xE4_WRAP_8014_Reserved_5_5_OFFSET 5
-#define D0F0xE4_WRAP_8014_Reserved_5_5_WIDTH 1
-#define D0F0xE4_WRAP_8014_Reserved_5_5_MASK 0x20
-#define D0F0xE4_WRAP_8014_Reserved_6_6_OFFSET 6
-#define D0F0xE4_WRAP_8014_Reserved_6_6_WIDTH 1
-#define D0F0xE4_WRAP_8014_Reserved_6_6_MASK 0x40
-#define D0F0xE4_WRAP_8014_Reserved_7_7_OFFSET 7
-#define D0F0xE4_WRAP_8014_Reserved_7_7_WIDTH 1
-#define D0F0xE4_WRAP_8014_Reserved_7_7_MASK 0x80
-#define D0F0xE4_WRAP_8014_Reserved_8_8_OFFSET 8
-#define D0F0xE4_WRAP_8014_Reserved_8_8_WIDTH 1
-#define D0F0xE4_WRAP_8014_Reserved_8_8_MASK 0x100
-#define D0F0xE4_WRAP_8014_Reserved_9_9_OFFSET 9
-#define D0F0xE4_WRAP_8014_Reserved_9_9_WIDTH 1
-#define D0F0xE4_WRAP_8014_Reserved_9_9_MASK 0x200
-#define D0F0xE4_WRAP_8014_Reserved_10_10_OFFSET 10
-#define D0F0xE4_WRAP_8014_Reserved_10_10_WIDTH 1
-#define D0F0xE4_WRAP_8014_Reserved_10_10_MASK 0x400
-#define D0F0xE4_WRAP_8014_Reserved_11_11_OFFSET 11
-#define D0F0xE4_WRAP_8014_Reserved_11_11_WIDTH 1
-#define D0F0xE4_WRAP_8014_Reserved_11_11_MASK 0x800
-#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_OFFSET 12
-#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_WIDTH 1
-#define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_MASK 0x1000
-#define D0F0xE4_WRAP_8014_Reserved_13_13_OFFSET 13
-#define D0F0xE4_WRAP_8014_Reserved_13_13_WIDTH 1
-#define D0F0xE4_WRAP_8014_Reserved_13_13_MASK 0x2000
-#define D0F0xE4_WRAP_8014_Reserved_14_14_OFFSET 14
-#define D0F0xE4_WRAP_8014_Reserved_14_14_WIDTH 1
-#define D0F0xE4_WRAP_8014_Reserved_14_14_MASK 0x4000
-#define D0F0xE4_WRAP_8014_Reserved_15_15_OFFSET 15
-#define D0F0xE4_WRAP_8014_Reserved_15_15_WIDTH 1
-#define D0F0xE4_WRAP_8014_Reserved_15_15_MASK 0x8000
-#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_OFFSET 16
-#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_WIDTH 1
-#define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_MASK 0x10000
-#define D0F0xE4_WRAP_8014_Reserved_17_17_OFFSET 17
-#define D0F0xE4_WRAP_8014_Reserved_17_17_WIDTH 1
-#define D0F0xE4_WRAP_8014_Reserved_17_17_MASK 0x20000
-#define D0F0xE4_WRAP_8014_Reserved_18_18_OFFSET 18
-#define D0F0xE4_WRAP_8014_Reserved_18_18_WIDTH 1
-#define D0F0xE4_WRAP_8014_Reserved_18_18_MASK 0x40000
-#define D0F0xE4_WRAP_8014_Reserved_19_19_OFFSET 19
-#define D0F0xE4_WRAP_8014_Reserved_19_19_WIDTH 1
-#define D0F0xE4_WRAP_8014_Reserved_19_19_MASK 0x80000
-#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_OFFSET 20
-#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_WIDTH 1
-#define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_MASK 0x100000
-#define D0F0xE4_WRAP_8014_Reserved_31_21_OFFSET 21
-#define D0F0xE4_WRAP_8014_Reserved_31_21_WIDTH 11
-#define D0F0xE4_WRAP_8014_Reserved_31_21_MASK 0xffe00000
-
-/// D0F0xE4_WRAP_8014
-typedef union {
- struct {
- UINT32 TxclkPermGateEnable:1 ; ///<
- UINT32 TxclkPrbsGateEnable:1 ; ///<
- UINT32 DdiGatePifA1xEnable:1 ; ///<
- UINT32 DdiGatePifB1xEnable:1 ; ///<
- UINT32 DdiGatePifC1xEnable:1 ; ///<
- UINT32 DdiGatePifD1xEnable:1 ; ///<
- UINT32 DdiGateDigAEnable:1 ; ///<
- UINT32 DdiGateDigBEnable:1 ; ///<
- UINT32 DdiGatePifA2p5xEnable:1 ; ///<
- UINT32 DdiGatePifB2p5xEnable:1 ; ///<
- UINT32 DdiGatePifC2p5xEnable:1 ; ///<
- UINT32 DdiGatePifD2p5xEnable:1 ; ///<
- UINT32 PcieGatePifA1xEnable:1 ; ///<
- UINT32 PcieGatePifB1xEnable:1 ; ///<
- UINT32 PcieGatePifC1xEnable:1 ; ///<
- UINT32 PcieGatePifD1xEnable:1 ; ///<
- UINT32 PcieGatePifA2p5xEnable:1 ; ///<
- UINT32 PcieGatePifB2p5xEnable:1 ; ///<
- UINT32 PcieGatePifC2p5xEnable:1 ; ///<
- UINT32 PcieGatePifD2p5xEnable:1 ; ///<
- UINT32 TxclkPermGateOnlyWhenPllPwrDn:1 ; ///<
- UINT32 Reserved_31_21:11; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0xE4_WRAP_8014_STRUCT;
-
-// **** SMUx0B_x85B0 Register Definition ****
-// Address
-#define SMUx0B_x85B0_ADDRESS 0x85B0
-
-
-// **** SMUx0B_x85D0 Register Definition ****
-// Address
-#define SMUx0B_x85D0_ADDRESS 0x85D0
-
-// **** D0F0x64_x51 Register Definition ****
-// Address
-#define D0F0x64_x51_ADDRESS 0x51
-
-// Type
-#define D0F0x64_x51_TYPE TYPE_D0F0x64
-// Field Data
-#define D0F0x64_x51_Reserved_2_0_OFFSET 0
-#define D0F0x64_x51_Reserved_2_0_WIDTH 3
-#define D0F0x64_x51_Reserved_2_0_MASK 0x7
-#define D0F0x64_x51_P2pDis_OFFSET 3
-#define D0F0x64_x51_P2pDis_WIDTH 1
-#define D0F0x64_x51_P2pDis_MASK 0x8
-#define D0F0x64_x51_Reserved_15_4_OFFSET 4
-#define D0F0x64_x51_Reserved_15_4_WIDTH 12
-#define D0F0x64_x51_Reserved_15_4_MASK 0xfff0
-#define D0F0x64_x51_ExtDevPlug_OFFSET 16
-#define D0F0x64_x51_ExtDevPlug_WIDTH 1
-#define D0F0x64_x51_ExtDevPlug_MASK 0x10000
-#define D0F0x64_x51_ExtDevCrsEn_OFFSET 17
-#define D0F0x64_x51_ExtDevCrsEn_WIDTH 1
-#define D0F0x64_x51_ExtDevCrsEn_MASK 0x20000
-#define D0F0x64_x51_CrsEn_OFFSET 18
-#define D0F0x64_x51_CrsEn_WIDTH 1
-#define D0F0x64_x51_CrsEn_MASK 0x40000
-#define D0F0x64_x51_IntSelMode_OFFSET 19
-#define D0F0x64_x51_IntSelMode_WIDTH 1
-#define D0F0x64_x51_IntSelMode_MASK 0x80000
-#define D0F0x64_x51_SetPowEn_OFFSET 20
-#define D0F0x64_x51_SetPowEn_WIDTH 1
-#define D0F0x64_x51_SetPowEn_MASK 0x100000
-#define D0F0x64_x51_Reserved_31_21_OFFSET 21
-#define D0F0x64_x51_Reserved_31_21_WIDTH 11
-#define D0F0x64_x51_Reserved_31_21_MASK 0xffe00000
-
-/// D0F0x64_x51
-typedef union {
- struct { ///<
- UINT32 Reserved_2_0:3 ; ///<
- UINT32 P2pDis:1 ; ///<
- UINT32 Reserved_15_4:12; ///<
- UINT32 ExtDevPlug:1 ; ///<
- UINT32 ExtDevCrsEn:1 ; ///<
- UINT32 CrsEn:1 ; ///<
- UINT32 IntSelMode:1 ; ///<
- UINT32 SetPowEn:1 ; ///<
- UINT32 Reserved_31_21:11; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x64_x51_STRUCT;
-
-// **** SMUx33 Register Definition ****
-// Address
-#define SMUx33_ADDRESS 0x33
-
-// Type
-#define SMUx33_TYPE TYPE_SMU
-// Field Data
-#define SMUx33_LclkActMonPrd_OFFSET 0
-#define SMUx33_LclkActMonPrd_WIDTH 16
-#define SMUx33_LclkActMonPrd_MASK 0xffff
-#define SMUx33_LclkActMonUnt_OFFSET 16
-#define SMUx33_LclkActMonUnt_WIDTH 4
-#define SMUx33_LclkActMonUnt_MASK 0xf0000
-#define SMUx33_Reserved_22_20_OFFSET 20
-#define SMUx33_Reserved_22_20_WIDTH 3
-#define SMUx33_Reserved_22_20_MASK 0x700000
-#define SMUx33_BusyCntSel_OFFSET 23
-#define SMUx33_BusyCntSel_WIDTH 2
-#define SMUx33_BusyCntSel_MASK 0x1800000
-#define SMUx33_Reserved_31_25_OFFSET 25
-#define SMUx33_Reserved_31_25_WIDTH 7
-#define SMUx33_Reserved_31_25_MASK 0xfe000000
-
-/// SMUx33
-typedef union {
- struct { ///<
- UINT32 LclkActMonPrd:16; ///<
- UINT32 LclkActMonUnt:4 ; ///<
- UINT32 Reserved_22_20:3 ; ///<
- UINT32 BusyCntSel:2 ; ///<
- UINT32 Reserved_31_25:7 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx33_STRUCT;
-
-// **** SMUx0B_x8434 Register Definition ****
-// Address
-#define SMUx0B_x8434_ADDRESS 0x8434
-
-// Type
-#define SMUx0B_x8434_TYPE TYPE_SMUx0B
-// Field Data
-#define SMUx0B_x8434_LclkDpmEn_OFFSET 0
-#define SMUx0B_x8434_LclkDpmEn_WIDTH 1
-#define SMUx0B_x8434_LclkDpmEn_MASK 0x1
-#define SMUx0B_x8434_LclkDpmType_OFFSET 1
-#define SMUx0B_x8434_LclkDpmType_WIDTH 1
-#define SMUx0B_x8434_LclkDpmType_MASK 0x2
-#define SMUx0B_x8434_Reserved_3_2_OFFSET 2
-#define SMUx0B_x8434_Reserved_3_2_WIDTH 2
-#define SMUx0B_x8434_Reserved_3_2_MASK 0xc
-#define SMUx0B_x8434_LclkTimerPrescalar_OFFSET 4
-#define SMUx0B_x8434_LclkTimerPrescalar_WIDTH 4
-#define SMUx0B_x8434_LclkTimerPrescalar_MASK 0xf0
-#define SMUx0B_x8434_Reserved_15_8_OFFSET 8
-#define SMUx0B_x8434_Reserved_15_8_WIDTH 8
-#define SMUx0B_x8434_Reserved_15_8_MASK 0xff00
-#define SMUx0B_x8434_LclkTimerPeriod_OFFSET 16
-#define SMUx0B_x8434_LclkTimerPeriod_WIDTH 16
-#define SMUx0B_x8434_LclkTimerPeriod_MASK 0xffff0000
-
-/// SMUx0B_x8434
-typedef union {
- struct { ///<
- UINT32 LclkDpmEn:1 ; ///<
- UINT32 LclkDpmType:1 ; ///<
- UINT32 Reserved_3_2:2 ; ///<
- UINT32 LclkTimerPrescalar:4 ; ///<
- UINT32 Reserved_15_8:8 ; ///<
- UINT32 LclkTimerPeriod:16; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x8434_STRUCT;
-
-// **** FCRxFF30_01E4 Register Definition ****
-// Address
-#define FCRxFF30_01E4_ADDRESS 0xff3001e4
-
-// Type
-#define FCRxFF30_01E4_TYPE TYPE_FCR
-// Field Data
-#define FCRxFF30_01E4_Reserved_19_0_OFFSET 0
-#define FCRxFF30_01E4_Reserved_19_0_WIDTH 20
-#define FCRxFF30_01E4_Reserved_19_0_MASK 0xfffff
-#define FCRxFF30_01E4_VoltageChangeEn_OFFSET 20
-#define FCRxFF30_01E4_VoltageChangeEn_WIDTH 1
-#define FCRxFF30_01E4_VoltageChangeEn_MASK 0x100000
-#define FCRxFF30_01E4_Reserved_31_21_OFFSET 21
-#define FCRxFF30_01E4_Reserved_31_21_WIDTH 11
-#define FCRxFF30_01E4_Reserved_31_21_MASK 0xffe00000
-
-/// FCRxFF30_01E4
-typedef union {
- struct { ///<
- UINT32 Reserved_19_0:20; ///<
- UINT32 VoltageChangeEn:1 ; ///<
- UINT32 Reserved_31_21:11; ///<
- } Field; ///<
- UINT32 Value; ///<
-} FCRxFF30_01E4_STRUCT;
-
-// **** SMUx0B_x8470 Register Definition ****
-// Address
-#define SMUx0B_x8470_ADDRESS 0x8470
-
-
-// **** SMUx0B_x8440 Register Definition ****
-// Address
-#define SMUx0B_x8440_ADDRESS 0x8440
-
-
-// **** SMUx0B_x848C Register Definition ****
-// Address
-#define SMUx0B_x848C_ADDRESS 0x848c
-
-
-// **** SMUx35 Register Definition ****
-// Address
-#define SMUx35_ADDRESS 0x35
-
-// Type
-#define SMUx35_TYPE TYPE_SMU
-// Field Data
-#define SMUx35_DownTrendCoef_OFFSET 0
-#define SMUx35_DownTrendCoef_WIDTH 10
-#define SMUx35_DownTrendCoef_MASK 0x3ff
-#define SMUx35_UpTrendCoef_OFFSET 10
-#define SMUx35_UpTrendCoef_WIDTH 10
-#define SMUx35_UpTrendCoef_MASK 0xffc00
-#define SMUx35_Reserved_31_20_OFFSET 20
-#define SMUx35_Reserved_31_20_WIDTH 12
-#define SMUx35_Reserved_31_20_MASK 0xfff00000
-
-/// SMUx35
-typedef union {
- struct { ///<
- UINT32 DownTrendCoef:10; ///<
- UINT32 UpTrendCoef:10; ///<
- UINT32 Reserved_31_20:12; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx35_STRUCT;
-
-// **** SMUx37 Register Definition ****
-// Address
-#define SMUx37_ADDRESS 0x37
-
-
-// **** SMUx51 Register Definition ****
-// Address
-#define SMUx51_ADDRESS 0x51
-
-
-// **** SMUx0B_x8490 Register Definition ****
-// Address
-#define SMUx0B_x8490_ADDRESS 0x8490
-
-
-// **** DxF0xE4_xB5 Register Definition ****
-// Address
-#define DxF0xE4_xB5_ADDRESS 0xb5
-
-// Type
-#define DxF0xE4_xB5_TYPE TYPE_D4F0xE4
-// Field Data
-#define DxF0xE4_xB5_Reserved_9_0_OFFSET 0
-#define DxF0xE4_xB5_Reserved_9_0_WIDTH 10
-#define DxF0xE4_xB5_Reserved_9_0_MASK 0x3ff
-#define DxF0xE4_xB5_LcEnhancedHotPlugEn_OFFSET 10
-#define DxF0xE4_xB5_LcEnhancedHotPlugEn_WIDTH 1
-#define DxF0xE4_xB5_LcEnhancedHotPlugEn_MASK 0x400
-#define DxF0xE4_xB5_Reserved_11_11_OFFSET 11
-#define DxF0xE4_xB5_Reserved_11_11_WIDTH 1
-#define DxF0xE4_xB5_Reserved_11_11_MASK 0x800
-#define DxF0xE4_xB5_LcEhpRxPhyCmd_OFFSET 12
-#define DxF0xE4_xB5_LcEhpRxPhyCmd_WIDTH 2
-#define DxF0xE4_xB5_LcEhpRxPhyCmd_MASK 0x3000
-#define DxF0xE4_xB5_LcEhpTxPhyCmd_OFFSET 14
-#define DxF0xE4_xB5_LcEhpTxPhyCmd_WIDTH 2
-#define DxF0xE4_xB5_LcEhpTxPhyCmd_MASK 0xc000
-#define DxF0xE4_xB5_Reserved_31_16_OFFSET 16
-#define DxF0xE4_xB5_Reserved_31_16_WIDTH 16
-#define DxF0xE4_xB5_Reserved_31_16_MASK 0xffff0000
-
-/// DxF0xE4_xB5
-typedef union {
- struct { ///<
- UINT32 Reserved_9_0:10; ///<
- UINT32 LcEnhancedHotPlugEn:1 ; ///<
- UINT32 Reserved_11_11:1 ; ///<
- UINT32 LcEhpRxPhyCmd:2 ; ///<
- UINT32 LcEhpTxPhyCmd:2 ; ///<
- UINT32 Reserved_31_16:16 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} DxF0xE4_xB5_STRUCT;
-
-// **** D0F0xE4_WRAP_80F0 Register Definition ****
-// Address
-#define D0F0xE4_WRAP_80F0_ADDRESS 0x80f0
-
-// Type
-#define D0F0xE4_WRAP_80F0_TYPE TYPE_D0F0xE4
-// Field Data
-#define D0F0xE4_WRAP_80F0_MicroSeconds_OFFSET 0
-#define D0F0xE4_WRAP_80F0_MicroSeconds_WIDTH 32
-#define D0F0xE4_WRAP_80F0_MicroSeconds_MASK 0xffffffff
-
-/// D0F0xE4_WRAP_80F0
-typedef union {
- struct { ///<
- UINT32 MicroSeconds:32; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0xE4_WRAP_80F0_STRUCT;
-
-// **** DxF0xE4_xA5 Register Definition ****
-// Address
-#define DxF0xE4_xA5_ADDRESS 0xa5
-
-
-// **** D0F0xE4_WRAP_8012 Register Definition ****
-// Address
-#define D0F0xE4_WRAP_8012_ADDRESS 0x8012
-
-// Type
-#define D0F0xE4_WRAP_8012_TYPE TYPE_D0F0xE4
-// Field Data
-#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_OFFSET 0
-#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_WIDTH 6
-#define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_MASK 0x3f
-#define D0F0xE4_WRAP_8012_Reserved_6_6_OFFSET 6
-#define D0F0xE4_WRAP_8012_Reserved_6_6_WIDTH 1
-#define D0F0xE4_WRAP_8012_Reserved_6_6_MASK 0x40
-#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_OFFSET 7
-#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_WIDTH 1
-#define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_MASK 0x80
-#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_OFFSET 8
-#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_WIDTH 6
-#define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_MASK 0x3f00
-#define D0F0xE4_WRAP_8012_Reserved_15_14_OFFSET 14
-#define D0F0xE4_WRAP_8012_Reserved_15_14_WIDTH 2
-#define D0F0xE4_WRAP_8012_Reserved_15_14_MASK 0xc000
-#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_OFFSET 16
-#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_WIDTH 6
-#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_MASK 0x3f0000
-#define D0F0xE4_WRAP_8012_Reserved_22_22_OFFSET 22
-#define D0F0xE4_WRAP_8012_Reserved_22_22_WIDTH 1
-#define D0F0xE4_WRAP_8012_Reserved_22_22_MASK 0x400000
-#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_OFFSET 23
-#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_WIDTH 1
-#define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_MASK 0x800000
-#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_OFFSET 24
-#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_WIDTH 6
-#define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_MASK 0x3f000000
-#define D0F0xE4_WRAP_8012_Reserved_31_30_OFFSET 30
-#define D0F0xE4_WRAP_8012_Reserved_31_30_WIDTH 2
-#define D0F0xE4_WRAP_8012_Reserved_31_30_MASK 0xc0000000
-
-/// D0F0xE4_WRAP_8012
-typedef union {
- struct { ///<
- UINT32 Pif1xIdleGateLatency:6 ; ///<
- UINT32 Reserved_6_6:1 ; ///<
- UINT32 Pif1xIdleGateEnable:1 ; ///<
- UINT32 Pif1xIdleResumeLatency:6 ; ///<
- UINT32 Reserved_15_14:2 ; ///<
- UINT32 Pif2p5xIdleGateLatency:6 ; ///<
- UINT32 Reserved_22_22:1 ; ///<
- UINT32 Pif2p5xIdleGateEnable:1 ; ///<
- UINT32 Pif2p5xIdleResumeLatency:6 ; ///<
- UINT32 Reserved_31_30:2 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0xE4_WRAP_8012_STRUCT;
-
-// **** D0F0xE4_WRAP_8011 Register Definition ****
-// Address
-#define D0F0xE4_WRAP_8011_ADDRESS 0x8011
-
-// Type
-#define D0F0xE4_WRAP_8011_TYPE TYPE_D0F0xE4
-// Field Data
-#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_OFFSET 0
-#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_WIDTH 6
-#define D0F0xE4_WRAP_8011_TxclkDynGateLatency_MASK 0x3f
-#define D0F0xE4_WRAP_8011_TxclkPermGateEven_OFFSET 6
-#define D0F0xE4_WRAP_8011_TxclkPermGateEven_WIDTH 1
-#define D0F0xE4_WRAP_8011_TxclkPermGateEven_MASK 0x40
-#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_OFFSET 7
-#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_WIDTH 1
-#define D0F0xE4_WRAP_8011_TxclkDynGateEnable_MASK 0x80
-#define D0F0xE4_WRAP_8011_Reserved_8_8_OFFSET 8
-#define D0F0xE4_WRAP_8011_Reserved_8_8_WIDTH 1
-#define D0F0xE4_WRAP_8011_Reserved_8_8_MASK 0x100
-#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_OFFSET 9
-#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_WIDTH 1
-#define D0F0xE4_WRAP_8011_TxclkRegsGateEnable_MASK 0x200
-#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_OFFSET 10
-#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_WIDTH 6
-#define D0F0xE4_WRAP_8011_TxclkRegsGateLatency_MASK 0xfc00
-#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_OFFSET 16
-#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_WIDTH 1
-#define D0F0xE4_WRAP_8011_RcvrDetClkEnable_MASK 0x10000
-#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_OFFSET 17
-#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_WIDTH 6
-#define D0F0xE4_WRAP_8011_TxclkPermGateLatency_MASK 0x7e0000
-#define D0F0xE4_WRAP_8011_Reserved_23_23_OFFSET 23
-#define D0F0xE4_WRAP_8011_Reserved_23_23_WIDTH 1
-#define D0F0xE4_WRAP_8011_Reserved_23_23_MASK 0x800000
-#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_OFFSET 24
-#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_WIDTH 1
-#define D0F0xE4_WRAP_8011_TxclkLcntGateEnable_MASK 0x1000000
-#define D0F0xE4_WRAP_8011_Reserved_31_25_OFFSET 25
-#define D0F0xE4_WRAP_8011_Reserved_31_25_WIDTH 7
-#define D0F0xE4_WRAP_8011_Reserved_31_25_MASK 0xfe000000
-
-/// D0F0xE4_WRAP_8011
-typedef union {
- struct { ///<
- UINT32 TxclkDynGateLatency:6 ; ///<
- UINT32 TxclkPermGateEven:1 ; ///<
- UINT32 TxclkDynGateEnable:1 ; ///<
- UINT32 Reserved_8_8:1 ; ///<
- UINT32 TxclkRegsGateEnable:1 ; ///<
- UINT32 TxclkRegsGateLatency:6 ; ///<
- UINT32 RcvrDetClkEnable:1 ; ///<
- UINT32 TxclkPermGateLatency:6 ; ///<
- UINT32 Reserved_23_23:1 ; ///<
- UINT32 TxclkLcntGateEnable:1 ; ///<
- UINT32 Reserved_31_25:7 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0xE4_WRAP_8011_STRUCT;
-
-// **** D0F0xE4_WRAP_8016 Register Definition ****
-// Address
-#define D0F0xE4_WRAP_8016_ADDRESS 0x8016
-
-// Type
-#define D0F0xE4_WRAP_8016_TYPE TYPE_D0F0xE4
-// Field Data
-#define D0F0xE4_WRAP_8016_CalibAckLatency_OFFSET 0
-#define D0F0xE4_WRAP_8016_CalibAckLatency_WIDTH 6
-#define D0F0xE4_WRAP_8016_CalibAckLatency_MASK 0x3f
-#define D0F0xE4_WRAP_8016_Reserved_21_6_OFFSET 6
-#define D0F0xE4_WRAP_8016_Reserved_21_6_WIDTH 16
-#define D0F0xE4_WRAP_8016_Reserved_21_6_MASK 0x3fffc0
-#define D0F0xE4_WRAP_8016_LclkGateFree_OFFSET 22
-#define D0F0xE4_WRAP_8016_LclkGateFree_WIDTH 1
-#define D0F0xE4_WRAP_8016_LclkGateFree_MASK 0x400000
-#define D0F0xE4_WRAP_8016_LclkDynGateEnable_OFFSET 23
-#define D0F0xE4_WRAP_8016_LclkDynGateEnable_WIDTH 1
-#define D0F0xE4_WRAP_8016_LclkDynGateEnable_MASK 0x800000
-#define D0F0xE4_WRAP_8016_Reserved_31_24_OFFSET 24
-#define D0F0xE4_WRAP_8016_Reserved_31_24_WIDTH 8
-#define D0F0xE4_WRAP_8016_Reserved_31_24_MASK 0xff000000
-
-/// D0F0xE4_WRAP_8016
-typedef union {
- struct { ///<
- UINT32 CalibAckLatency:6 ; ///<
- UINT32 Reserved_21_6:16; ///<
- UINT32 LclkGateFree:1 ; ///<
- UINT32 LclkDynGateEnable:1 ; ///<
- UINT32 Reserved_31_24:8 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0xE4_WRAP_8016_STRUCT;
-
-// **** D18F6x110 Register Definition ****
-// Address
-#define D18F6x110_ADDRESS 0x110
-
-// Type
-#define D18F6x110_TYPE TYPE_D18F6
-// Field Data
-#define D18F6x110_NclkFifoOff_OFFSET 0
-#define D18F6x110_NclkFifoOff_WIDTH 3
-#define D18F6x110_NclkFifoOff_MASK 0x7
-#define D18F6x110_Reserved_3_3_OFFSET 3
-#define D18F6x110_Reserved_3_3_WIDTH 1
-#define D18F6x110_Reserved_3_3_MASK 0x8
-#define D18F6x110_LclkFifoOff_OFFSET 4
-#define D18F6x110_LclkFifoOff_WIDTH 3
-#define D18F6x110_LclkFifoOff_MASK 0x70
-#define D18F6x110_Reserved_7_7_OFFSET 7
-#define D18F6x110_Reserved_7_7_WIDTH 1
-#define D18F6x110_Reserved_7_7_MASK 0x80
-#define D18F6x110_PllMult_OFFSET 8
-#define D18F6x110_PllMult_WIDTH 6
-#define D18F6x110_PllMult_MASK 0x3f00
-#define D18F6x110_Reserved_14_14_OFFSET 14
-#define D18F6x110_Reserved_14_14_WIDTH 1
-#define D18F6x110_Reserved_14_14_MASK 0x4000
-#define D18F6x110_Enable_OFFSET 15
-#define D18F6x110_Enable_WIDTH 1
-#define D18F6x110_Enable_MASK 0x8000
-#define D18F6x110_LclkFreq_OFFSET 16
-#define D18F6x110_LclkFreq_WIDTH 7
-#define D18F6x110_LclkFreq_MASK 0x7f0000
-#define D18F6x110_LclkFreqType_OFFSET 23
-#define D18F6x110_LclkFreqType_WIDTH 1
-#define D18F6x110_LclkFreqType_MASK 0x800000
-#define D18F6x110_NclkFreq_OFFSET 24
-#define D18F6x110_NclkFreq_WIDTH 7
-#define D18F6x110_NclkFreq_MASK 0x7f000000
-#define D18F6x110_NclkFreqType_OFFSET 31
-#define D18F6x110_NclkFreqType_WIDTH 1
-#define D18F6x110_NclkFreqType_MASK 0x80000000
-
-/// D18F6x110
-typedef union {
- struct { ///<
- UINT32 NclkFifoOff:3 ; ///<
- UINT32 Reserved_3_3:1 ; ///<
- UINT32 LclkFifoOff:3 ; ///<
- UINT32 Reserved_7_7:1 ; ///<
- UINT32 PllMult:6 ; ///<
- UINT32 Reserved_14_14:1 ; ///<
- UINT32 Enable:1 ; ///<
- UINT32 LclkFreq:7 ; ///<
- UINT32 LclkFreqType:1 ; ///<
- UINT32 NclkFreq:7 ; ///<
- UINT32 NclkFreqType:1 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F6x110_STRUCT;
-
-// **** D18F3xA0 Register Definition ****
-// Address
-#define D18F3xA0_ADDRESS 0xa0
-
-// Type
-#define D18F3xA0_TYPE TYPE_D18F3
-// Field Data
-#define D18F3xA0_PsiVid_OFFSET 0
-#define D18F3xA0_PsiVid_WIDTH 7
-#define D18F3xA0_PsiVid_MASK 0x7f
-#define D18F3xA0_PsiVidEn_OFFSET 7
-#define D18F3xA0_PsiVidEn_WIDTH 1
-#define D18F3xA0_PsiVidEn_MASK 0x80
-#define D18F3xA0_Reserved_8_8_OFFSET 8
-#define D18F3xA0_Reserved_8_8_WIDTH 1
-#define D18F3xA0_Reserved_8_8_MASK 0x100
-#define D18F3xA0_SviHighFreqSel_OFFSET 9
-#define D18F3xA0_SviHighFreqSel_WIDTH 1
-#define D18F3xA0_SviHighFreqSel_MASK 0x200
-#define D18F3xA0_Reserved_15_10_OFFSET 10
-#define D18F3xA0_Reserved_15_10_WIDTH 6
-#define D18F3xA0_Reserved_15_10_MASK 0xfc00
-#define D18F3xA0_ConfigId_OFFSET 16
-#define D18F3xA0_ConfigId_WIDTH 12
-#define D18F3xA0_ConfigId_MASK 0xfff0000
-#define D18F3xA0_Reserved_30_28_OFFSET 28
-#define D18F3xA0_Reserved_30_28_WIDTH 3
-#define D18F3xA0_Reserved_30_28_MASK 0x70000000
-#define D18F3xA0_CofVidProg_OFFSET 31
-#define D18F3xA0_CofVidProg_WIDTH 1
-#define D18F3xA0_CofVidProg_MASK 0x80000000
-
-/// D18F3xA0
-typedef union {
- struct { ///<
- UINT32 PsiVid:7 ; ///<
- UINT32 PsiVidEn:1 ; ///<
- UINT32 Reserved_8_8:1 ; ///<
- UINT32 SviHighFreqSel:1 ; ///<
- UINT32 Reserved_15_10:6 ; ///<
- UINT32 ConfigId:12; ///<
- UINT32 Reserved_30_28:3 ; ///<
- UINT32 CofVidProg:1 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F3xA0_STRUCT;
-
-// **** FCRxFF30_0398 Register Definition ****
-// Address
-#define FCRxFF30_0398_ADDRESS 0xff300398
-
-// Type
-#define FCRxFF30_0398_TYPE TYPE_FCR
-// Field Data
-#define FCRxFF30_0398_Reserved_4_0_OFFSET 0
-#define FCRxFF30_0398_Reserved_4_0_WIDTH 5
-#define FCRxFF30_0398_Reserved_4_0_MASK 0x1f
-#define FCRxFF30_0398_SoftResetDc_OFFSET 5
-#define FCRxFF30_0398_SoftResetDc_WIDTH 1
-#define FCRxFF30_0398_SoftResetDc_MASK 0x20
-#define FCRxFF30_0398_Reserved_6_6_OFFSET 6
-#define FCRxFF30_0398_Reserved_6_6_WIDTH 1
-#define FCRxFF30_0398_Reserved_6_6_MASK 0x40
-#define FCRxFF30_0398_SoftResetGrbm_OFFSET 8
-#define FCRxFF30_0398_SoftResetGrbm_WIDTH 1
-#define FCRxFF30_0398_SoftResetGrbm_MASK 0x100
-#define FCRxFF30_0398_SoftResetMc_OFFSET 11
-#define FCRxFF30_0398_SoftResetMc_WIDTH 1
-#define FCRxFF30_0398_SoftResetMc_MASK 0x800
-#define FCRxFF30_0398_Reserved_12_12_OFFSET 12
-#define FCRxFF30_0398_Reserved_12_12_WIDTH 1
-#define FCRxFF30_0398_Reserved_12_12_MASK 0x1000
-#define FCRxFF30_0398_SoftResetRlc_OFFSET 13
-#define FCRxFF30_0398_SoftResetRlc_WIDTH 1
-#define FCRxFF30_0398_SoftResetRlc_MASK 0x2000
-#define FCRxFF30_0398_Reserved_16_16_OFFSET 16
-#define FCRxFF30_0398_Reserved_16_16_WIDTH 1
-#define FCRxFF30_0398_Reserved_16_16_MASK 0x10000
-#define FCRxFF30_0398_SoftResetUvd_OFFSET 18
-#define FCRxFF30_0398_SoftResetUvd_WIDTH 1
-#define FCRxFF30_0398_SoftResetUvd_MASK 0x40000
-#define FCRxFF30_0398_Reserved_31_19_OFFSET 19
-#define FCRxFF30_0398_Reserved_31_19_WIDTH 13
-#define FCRxFF30_0398_Reserved_31_19_MASK 0xfff80000
-
-/// FCRxFF30_0398
-typedef union {
- struct { ///<
- UINT32 Reserved_4_0:5 ; ///<
- UINT32 SoftResetDc:1 ; ///<
- UINT32 Reserved_6_6:1 ; ///<
- UINT32 Reserved_7_7:1 ; ///<
- UINT32 SoftResetGrbm:1 ; ///<
- UINT32 Reserved_9_9:1 ; ///<
- UINT32 Reserved_10_10:1 ; ///<
- UINT32 SoftResetMc:1 ; ///<
- UINT32 Reserved_12_12:1 ; ///<
- UINT32 SoftResetRlc:1 ; ///<
- UINT32 Reserved_14_14:1 ; ///<
- UINT32 Reserved_15_15:1 ; ///<
- UINT32 Reserved_16_16:1 ; ///<
- UINT32 Reserved_17_17:1 ; ///<
- UINT32 SoftResetUvd:1 ; ///<
- UINT32 Reserved_31_19:13; ///<
- } Field; ///<
- UINT32 Value; ///<
-} FCRxFF30_0398_STRUCT;
-
-// **** SMUx0B_x8504 Register Definition ****
-// Address
-#define SMUx0B_x8504_ADDRESS 0x8504
-
-// Type
-#define SMUx0B_x8504_TYPE TYPE_SMUx0B
-// Field Data
-#define SMUx0B_x8504_SaveRestoreWidth_OFFSET 0
-#define SMUx0B_x8504_SaveRestoreWidth_WIDTH 8
-#define SMUx0B_x8504_SaveRestoreWidth_MASK 0xff
-#define SMUx0B_x8504_PsoRestoreTimer_OFFSET 8
-#define SMUx0B_x8504_PsoRestoreTimer_WIDTH 8
-#define SMUx0B_x8504_PsoRestoreTimer_MASK 0xff00
-#define SMUx0B_x8504_Reserved_31_16_OFFSET 16
-#define SMUx0B_x8504_Reserved_31_16_WIDTH 16
-#define SMUx0B_x8504_Reserved_31_16_MASK 0xffff0000
-
-/// SMUx0B_x8504
-typedef union {
- struct { ///<
- UINT32 SaveRestoreWidth:8 ; ///<
- UINT32 PsoRestoreTimer:8 ; ///<
- UINT32 Reserved_31_16:16; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x8504_STRUCT;
-
-// **** SMUx0B_x8408 Register Definition ****
-// Address
-#define SMUx0B_x8408_ADDRESS 0x8408
-
-
-// **** SMUx0B_x8410 Register Definition ****
-// Address
-#define SMUx0B_x8410_ADDRESS 0x8410
-
-// Type
-#define SMUx0B_x8410_TYPE TYPE_SMUx0B
-// Field Data
-#define SMUx0B_x8410_PwrGatingEn_OFFSET 0
-#define SMUx0B_x8410_PwrGatingEn_WIDTH 1
-#define SMUx0B_x8410_PwrGatingEn_MASK 0x1
-#define SMUx0B_x8410_Reserved_2_1_OFFSET 1
-#define SMUx0B_x8410_Reserved_2_1_WIDTH 2
-#define SMUx0B_x8410_Reserved_2_1_MASK 0x6
-#define SMUx0B_x8410_PsoControlValidNum_OFFSET 3
-#define SMUx0B_x8410_PsoControlValidNum_WIDTH 5
-#define SMUx0B_x8410_PsoControlValidNum_MASK 0xf8
-#define SMUx0B_x8410_SavePsoDelay_OFFSET 8
-#define SMUx0B_x8410_SavePsoDelay_WIDTH 4
-#define SMUx0B_x8410_SavePsoDelay_MASK 0xf00
-#define SMUx0B_x8410_Reserved_27_12_OFFSET 12
-#define SMUx0B_x8410_Reserved_27_12_WIDTH 16
-#define SMUx0B_x8410_Reserved_27_12_MASK 0xffff000
-#define SMUx0B_x8410_PwrGaterSel_OFFSET 28
-#define SMUx0B_x8410_PwrGaterSel_WIDTH 4
-#define SMUx0B_x8410_PwrGaterSel_MASK 0xf0000000
-
-/// SMUx0B_x8410
-typedef union {
- struct { ///<
- UINT32 PwrGatingEn:1 ; ///<
- UINT32 Reserved_2_1:2 ; ///<
- UINT32 PsoControlValidNum:5 ; ///<
- UINT32 SavePsoDelay:4 ; ///<
- UINT32 Reserved_27_12:16; ///<
- UINT32 PwrGaterSel:4 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx0B_x8410_STRUCT;
-
-// **** SMUx0B_x84A0 Register Definition ****
-// Address
-#define SMUx0B_x84A0_ADDRESS 0x84a0
-
-
-// **** D0F0xE4_CORE_0020 Register Definition ****
-// Address
-#define D0F0xE4_CORE_0020_ADDRESS 0x20
-
-// Type
-#define D0F0xE4_CORE_0020_TYPE TYPE_D0F0xE4
-// Field Data
-#define D0F0xE4_CORE_0020_Reserved_8_0_OFFSET 0
-#define D0F0xE4_CORE_0020_Reserved_8_0_WIDTH 9
-#define D0F0xE4_CORE_0020_Reserved_8_0_MASK 0x1ff
-#define D0F0xE4_CORE_0020_CiSlvOrderingDis_OFFSET 8
-#define D0F0xE4_CORE_0020_CiSlvOrderingDis_WIDTH 1
-#define D0F0xE4_CORE_0020_CiSlvOrderingDis_MASK 0x100
-#define D0F0xE4_CORE_0020_CiRcOrderingDis_OFFSET 9
-#define D0F0xE4_CORE_0020_CiRcOrderingDis_WIDTH 1
-#define D0F0xE4_CORE_0020_CiRcOrderingDis_MASK 0x200
-#define D0F0xE4_CORE_0020_Reserved_31_10_OFFSET 10
-#define D0F0xE4_CORE_0020_Reserved_31_10_WIDTH 22
-#define D0F0xE4_CORE_0020_Reserved_31_10_MASK 0xfffffc00
-
-/// D0F0xE4_CORE_0020
-typedef union {
- struct { ///<
- UINT32 Reserved_8_0:9 ; ///<
- UINT32 CiRcOrderingDis:1 ; ///<
- UINT32 Reserved_31_10:22; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0xE4_CORE_0020_STRUCT;
-
-// **** D0F0xE4_CORE_00B0 Register Definition ****
-// Address
-#define D0F0xE4_CORE_00B0_ADDRESS 0xb0
-
-// Type
-#define D0F0xE4_CORE_00B0_TYPE TYPE_D0F0xE4
-// Field Data
-#define D0F0xE4_CORE_00B0_Reserved_1_0_OFFSET 0
-#define D0F0xE4_CORE_00B0_Reserved_1_0_WIDTH 2
-#define D0F0xE4_CORE_00B0_Reserved_1_0_MASK 0x3
-#define D0F0xE4_CORE_00B0_StrapF0MsiEn_OFFSET 2
-#define D0F0xE4_CORE_00B0_StrapF0MsiEn_WIDTH 1
-#define D0F0xE4_CORE_00B0_StrapF0MsiEn_MASK 0x4
-#define D0F0xE4_CORE_00B0_Reserved_31_3_OFFSET 3
-#define D0F0xE4_CORE_00B0_Reserved_31_3_WIDTH 29
-#define D0F0xE4_CORE_00B0_Reserved_31_3_MASK 0xfffffff8
-
-/// D0F0xE4_CORE_00B0
-typedef union {
- struct { ///<
- UINT32 Reserved_1_0:2 ; ///<
- UINT32 StrapF0MsiEn:1 ; ///<
- UINT32 Reserved_31_3:29; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0xE4_CORE_00B0_STRUCT;
-
-// **** D0F0x64_x1C Register Definition ****
-// Address
-#define D0F0x64_x1C_ADDRESS 0x1c
-
-// Type
-#define D0F0x64_x1C_TYPE TYPE_D0F0x64
-// Field Data
-#define D0F0x64_x1C_WriteDis_OFFSET 0
-#define D0F0x64_x1C_WriteDis_WIDTH 1
-#define D0F0x64_x1C_WriteDis_MASK 0x1
-#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_OFFSET 1
-#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_WIDTH 1
-#define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_MASK 0x2
-#define D0F0x64_x1C_Reserved_2_2_OFFSET 2
-#define D0F0x64_x1C_Reserved_2_2_WIDTH 1
-#define D0F0x64_x1C_Reserved_2_2_MASK 0x4
-#define D0F0x64_x1C_MemApSize_OFFSET 3
-#define D0F0x64_x1C_MemApSize_WIDTH 3
-#define D0F0x64_x1C_MemApSize_MASK 0x38
-#define D0F0x64_x1C_RegApSize_OFFSET 6
-#define D0F0x64_x1C_RegApSize_WIDTH 1
-#define D0F0x64_x1C_RegApSize_MASK 0x40
-#define D0F0x64_x1C_Reserved_7_7_OFFSET 7
-#define D0F0x64_x1C_Reserved_7_7_WIDTH 1
-#define D0F0x64_x1C_Reserved_7_7_MASK 0x80
-#define D0F0x64_x1C_AudioEn_OFFSET 8
-#define D0F0x64_x1C_AudioEn_WIDTH 1
-#define D0F0x64_x1C_AudioEn_MASK 0x100
-#define D0F0x64_x1C_Reserved_9_9_OFFSET 9
-#define D0F0x64_x1C_Reserved_9_9_WIDTH 1
-#define D0F0x64_x1C_Reserved_9_9_MASK 0x200
-#define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_OFFSET 10
-#define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_WIDTH 1
-#define D0F0x64_x1C_AudioNonlegacyDeviceTypeEn_MASK 0x400
-#define D0F0x64_x1C_Reserved_16_11_OFFSET 11
-#define D0F0x64_x1C_Reserved_16_11_WIDTH 6
-#define D0F0x64_x1C_Reserved_16_11_MASK 0x1f800
-#define D0F0x64_x1C_F0En_OFFSET 17
-#define D0F0x64_x1C_F0En_WIDTH 1
-#define D0F0x64_x1C_F0En_MASK 0x20000
-#define D0F0x64_x1C_Reserved_22_18_OFFSET 18
-#define D0F0x64_x1C_Reserved_22_18_WIDTH 5
-#define D0F0x64_x1C_Reserved_22_18_MASK 0x7c0000
-#define D0F0x64_x1C_RcieEn_OFFSET 23
-#define D0F0x64_x1C_RcieEn_WIDTH 1
-#define D0F0x64_x1C_RcieEn_MASK 0x800000
-#define D0F0x64_x1C_Reserved_31_24_OFFSET 24
-#define D0F0x64_x1C_Reserved_31_24_WIDTH 8
-#define D0F0x64_x1C_Reserved_31_24_MASK 0xff000000
-
-/// D0F0x64_x1C
-typedef union {
- struct { ///<
- UINT32 WriteDis:1 ; ///<
- UINT32 F0NonlegacyDeviceTypeEn:1 ; ///<
- UINT32 Reserved_2_2:1 ; ///<
- UINT32 MemApSize:3 ; ///<
- UINT32 RegApSize:1 ; ///<
- UINT32 Reserved_7_7:1 ; ///<
- UINT32 AudioEn:1 ; ///<
- UINT32 Reserved_9_9:1 ; ///<
- UINT32 AudioNonlegacyDeviceTypeEn:1 ; ///<
- UINT32 Reserved_16_11:6 ; ///<
- UINT32 F0En:1 ; ///<
- UINT32 Reserved_22_18:5 ; ///<
- UINT32 RcieEn:1 ; ///<
- UINT32 Reserved_31_24:8 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x64_x1C_STRUCT;
-
-// **** D18F2x0F4_x40 Register Definition ****
-// Address
-#define D18F2x0F4_x40_ADDRESS 0x40
-
-// Type
-#define D18F2x0F4_x40_TYPE TYPE_D18F2x0F4
-// Field Data
-#define D18F2x0F4_x40_Trcd_OFFSET 0
-#define D18F2x0F4_x40_Trcd_WIDTH 4
-#define D18F2x0F4_x40_Trcd_MASK 0xf
-#define D18F2x0F4_x40_Reserved_7_4_OFFSET 4
-#define D18F2x0F4_x40_Reserved_7_4_WIDTH 4
-#define D18F2x0F4_x40_Reserved_7_4_MASK 0xf0
-#define D18F2x0F4_x40_Trp_OFFSET 8
-#define D18F2x0F4_x40_Trp_WIDTH 4
-#define D18F2x0F4_x40_Trp_MASK 0xf00
-#define D18F2x0F4_x40_Reserved_15_12_OFFSET 12
-#define D18F2x0F4_x40_Reserved_15_12_WIDTH 4
-#define D18F2x0F4_x40_Reserved_15_12_MASK 0xf000
-#define D18F2x0F4_x40_Tras_OFFSET 16
-#define D18F2x0F4_x40_Tras_WIDTH 5
-#define D18F2x0F4_x40_Tras_MASK 0x1f0000
-#define D18F2x0F4_x40_Reserved_23_21_OFFSET 21
-#define D18F2x0F4_x40_Reserved_23_21_WIDTH 3
-#define D18F2x0F4_x40_Reserved_23_21_MASK 0xe00000
-#define D18F2x0F4_x40_Trc_OFFSET 24
-#define D18F2x0F4_x40_Trc_WIDTH 6
-#define D18F2x0F4_x40_Trc_MASK 0x3f000000
-#define D18F2x0F4_x40_Reserved_31_30_OFFSET 30
-#define D18F2x0F4_x40_Reserved_31_30_WIDTH 2
-#define D18F2x0F4_x40_Reserved_31_30_MASK 0xc0000000
-
-/// D18F2x0F4_x40
-typedef union {
- struct { ///<
- UINT32 Trcd:4 ; ///<
- UINT32 Reserved_7_4:4 ; ///<
- UINT32 Trp:4 ; ///<
- UINT32 Reserved_15_12:4 ; ///<
- UINT32 Tras:5 ; ///<
- UINT32 Reserved_23_21:3 ; ///<
- UINT32 Trc:6 ; ///<
- UINT32 Reserved_31_30:2 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F2x0F4_x40_STRUCT;
-
-// **** D18F2x0F4_x41 Register Definition ****
-// Address
-#define D18F2x0F4_x41_ADDRESS 0x41
-
-// Type
-#define D18F2x0F4_x41_TYPE TYPE_D18F2x0F4
-// Field Data
-#define D18F2x0F4_x41_Trtp_OFFSET 0
-#define D18F2x0F4_x41_Trtp_WIDTH 3
-#define D18F2x0F4_x41_Trtp_MASK 0x7
-#define D18F2x0F4_x41_Reserved_7_3_OFFSET 3
-#define D18F2x0F4_x41_Reserved_7_3_WIDTH 5
-#define D18F2x0F4_x41_Reserved_7_3_MASK 0xf8
-#define D18F2x0F4_x41_Trrd_OFFSET 8
-#define D18F2x0F4_x41_Trrd_WIDTH 3
-#define D18F2x0F4_x41_Trrd_MASK 0x700
-#define D18F2x0F4_x41_Reserved_15_11_OFFSET 11
-#define D18F2x0F4_x41_Reserved_15_11_WIDTH 5
-#define D18F2x0F4_x41_Reserved_15_11_MASK 0xf800
-#define D18F2x0F4_x41_Twtr_OFFSET 16
-#define D18F2x0F4_x41_Twtr_WIDTH 3
-#define D18F2x0F4_x41_Twtr_MASK 0x70000
-#define D18F2x0F4_x41_Reserved_31_19_OFFSET 19
-#define D18F2x0F4_x41_Reserved_31_19_WIDTH 13
-#define D18F2x0F4_x41_Reserved_31_19_MASK 0xfff80000
-
-/// D18F2x0F4_x41
-typedef union {
- struct { ///<
- UINT32 Trtp:3 ; ///<
- UINT32 Reserved_7_3:5 ; ///<
- UINT32 Trrd:3 ; ///<
- UINT32 Reserved_15_11:5 ; ///<
- UINT32 Twtr:3 ; ///<
- UINT32 Reserved_31_19:13; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F2x0F4_x41_STRUCT;
-
-// **** D18F2x0F0 Register Definition ****
-// Address
-#define D18F2x0F0_ADDRESS 0xf0
-
-
-// **** D18F2x1F0 Register Definition ****
-// Address
-#define D18F2x1F0_ADDRESS 0x1f0
-
-
-// **** D18F2x184 Register Definition ****
-// Address
-#define D18F2x184_ADDRESS 0x184
-
-
-// **** D18F2x094 Register Definition ****
-// Address
-#define D18F2x094_ADDRESS 0x94
-
-// Type
-#define D18F2x094_TYPE TYPE_D18F2
-// Field Data
-#define D18F2x094_MemClkFreq_OFFSET 0
-#define D18F2x094_MemClkFreq_WIDTH 5
-#define D18F2x094_MemClkFreq_MASK 0x1f
-#define D18F2x094_Reserved_6_5_OFFSET 5
-#define D18F2x094_Reserved_6_5_WIDTH 2
-#define D18F2x094_Reserved_6_5_MASK 0x60
-#define D18F2x094_MemClkFreqVal_OFFSET 7
-#define D18F2x094_MemClkFreqVal_WIDTH 1
-#define D18F2x094_MemClkFreqVal_MASK 0x80
-#define D18F2x094_Reserved_9_8_OFFSET 8
-#define D18F2x094_Reserved_9_8_WIDTH 2
-#define D18F2x094_Reserved_9_8_MASK 0x300
-#define D18F2x094_ZqcsInterval_OFFSET 10
-#define D18F2x094_ZqcsInterval_WIDTH 2
-#define D18F2x094_ZqcsInterval_MASK 0xc00
-#define D18F2x094_Reserved_13_12_OFFSET 12
-#define D18F2x094_Reserved_13_12_WIDTH 2
-#define D18F2x094_Reserved_13_12_MASK 0x3000
-#define D18F2x094_DisDramInterface_OFFSET 14
-#define D18F2x094_DisDramInterface_WIDTH 1
-#define D18F2x094_DisDramInterface_MASK 0x4000
-#define D18F2x094_PowerDownEn_OFFSET 15
-#define D18F2x094_PowerDownEn_WIDTH 1
-#define D18F2x094_PowerDownEn_MASK 0x8000
-#define D18F2x094_PowerDownMode_OFFSET 16
-#define D18F2x094_PowerDownMode_WIDTH 1
-#define D18F2x094_PowerDownMode_MASK 0x10000
-#define D18F2x094_Reserved_19_17_OFFSET 17
-#define D18F2x094_Reserved_19_17_WIDTH 3
-#define D18F2x094_Reserved_19_17_MASK 0xe0000
-#define D18F2x094_SlowAccessMode_OFFSET 20
-#define D18F2x094_SlowAccessMode_WIDTH 1
-#define D18F2x094_SlowAccessMode_MASK 0x100000
-#define D18F2x094_Reserved_21_21_OFFSET 21
-#define D18F2x094_Reserved_21_21_WIDTH 1
-#define D18F2x094_Reserved_21_21_MASK 0x200000
-#define D18F2x094_BankSwizzleMode_OFFSET 22
-#define D18F2x094_BankSwizzleMode_WIDTH 1
-#define D18F2x094_BankSwizzleMode_MASK 0x400000
-#define D18F2x094_ProcOdtDis_OFFSET 23
-#define D18F2x094_ProcOdtDis_WIDTH 1
-#define D18F2x094_ProcOdtDis_MASK 0x800000
-#define D18F2x094_DcqBypassMax_OFFSET 24
-#define D18F2x094_DcqBypassMax_WIDTH 4
-#define D18F2x094_DcqBypassMax_MASK 0xf000000
-#define D18F2x094_FourActWindow_OFFSET 28
-#define D18F2x094_FourActWindow_WIDTH 4
-#define D18F2x094_FourActWindow_MASK 0xf0000000
-
-/// D18F2x094
-typedef union {
- struct { ///<
- UINT32 MemClkFreq:5 ; ///<
- UINT32 Reserved_6_5:2 ; ///<
- UINT32 MemClkFreqVal:1 ; ///<
- UINT32 Reserved_9_8:2 ; ///<
- UINT32 ZqcsInterval:2 ; ///<
- UINT32 Reserved_13_12:2 ; ///<
- UINT32 DisDramInterface:1 ; ///<
- UINT32 PowerDownEn:1 ; ///<
- UINT32 PowerDownMode:1 ; ///<
- UINT32 Reserved_19_17:3 ; ///<
- UINT32 SlowAccessMode:1 ; ///<
- UINT32 Reserved_21_21:1 ; ///<
- UINT32 BankSwizzleMode:1 ; ///<
- UINT32 ProcOdtDis:1 ; ///<
- UINT32 DcqBypassMax:4 ; ///<
- UINT32 FourActWindow:4 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F2x094_STRUCT;
-
-// **** D18F2x194 Register Definition ****
-// Address
-#define D18F2x194_ADDRESS 0x194
-
-
-// **** D18F2x18C Register Definition ****
-// Address
-#define D18F2x18C_ADDRESS 0x18c
-
-
-// **** D18F2x190 Register Definition ****
-// Address
-#define D18F2x190_ADDRESS 0x190
-
-
-// **** D18F2x098 Register Definition ****
-// Address
-#define D18F2x098_ADDRESS 0x98
-
-
-// **** D18F2x198 Register Definition ****
-// Address
-#define D18F2x198_ADDRESS 0x198
-
-
-// **** D18F2x09C_x0D0FE00A Register Definition ****
-// Address
-#define D18F2x09C_x0D0FE00A_ADDRESS 0x0D0FE00A
-
-// Type
-#define D18F2x09C_x0D0FE00A_TYPE TYPE_D18F2x9C
-// Field Data
-#define D18F2x09C_x0D0FE00A_Reserved_11_0_OFFSET 0
-#define D18F2x09C_x0D0FE00A_Reserved_11_0_WIDTH 12
-#define D18F2x09C_x0D0FE00A_Reserved_11_0_MASK 0xfff
-#define D18F2x09C_x0D0FE00A_CsrPhySrPllPdMode_OFFSET 12
-#define D18F2x09C_x0D0FE00A_CsrPhySrPllPdMode_WIDTH 2
-#define D18F2x09C_x0D0FE00A_CsrPhySrPllPdMode_MASK 0x3000
-#define D18F2x09C_x0D0FE00A_SelCsrPllPdMode_OFFSET 14
-#define D18F2x09C_x0D0FE00A_SelCsrPllPdMode_WIDTH 1
-#define D18F2x09C_x0D0FE00A_SelCsrPllPdMode_MASK 0x4000
-#define D18F2x09C_x0D0FE00A_Reserved_31_15_OFFSET 15
-#define D18F2x09C_x0D0FE00A_Reserved_31_15_WIDTH 17
-#define D18F2x09C_x0D0FE00A_Reserved_31_15_MASK 0xFFFF8000
-
-/// D18F2x09C_x0D0FE00A
-typedef union {
- struct { ///<
- UINT32 Reserved_11_0:12; ///<
- UINT32 CsrPhySrPllPdMode:2; ///<
- UINT32 SelCsrPllPdMode:1; ///<
- UINT32 Reserved_31_15:17; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F2x09C_x0D0FE00A_STRUCT;
-
-// **** GMMx201C Register Definition ****
-// Address
-#define GMMx201C_ADDRESS 0x201c
-
-
-// **** GMMx217C Register Definition ****
-// Address
-#define GMMx217C_ADDRESS 0x217c
-
-
-// **** GMMx2188 Register Definition ****
-// Address
-#define GMMx2188_ADDRESS 0x2188
-
-
-// **** GMMx28C8 Register Definition ****
-// Address
-#define GMMx28C8_ADDRESS 0x28c8
-
-
-// **** SMUx01 Register Definition ****
-// Address
-#define SMUx01_ADDRESS 0x1
-
-// Type
-#define SMUx01_TYPE TYPE_SMU
-// Field Data
-#define SMUx01_RamSwitch_OFFSET 0
-#define SMUx01_RamSwitch_WIDTH 1
-#define SMUx01_RamSwitch_MASK 0x1
-#define SMUx01_Reset_OFFSET 1
-#define SMUx01_Reset_WIDTH 1
-#define SMUx01_Reset_MASK 0x2
-#define SMUx01_Reserved_17_2_OFFSET 2
-#define SMUx01_Reserved_17_2_WIDTH 16
-#define SMUx01_Reserved_17_2_MASK 0x3fffc
-#define SMUx01_VectorOverride_OFFSET 18
-#define SMUx01_VectorOverride_WIDTH 1
-#define SMUx01_VectorOverride_MASK 0x40000
-#define SMUx01_Reserved_31_19_OFFSET 19
-#define SMUx01_Reserved_31_19_WIDTH 13
-#define SMUx01_Reserved_31_19_MASK 0xfff80000
-//
-/// SMUx01
-typedef union {
- struct { ///<
- UINT32 RamSwitch:1 ; ///<
- UINT32 Reset:1 ; ///<
- UINT32 Reserved_17_2:16; ///<
- UINT32 VectorOverride:1 ; ///<
- UINT32 Reserved_31_19:13; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx01_STRUCT;
-
-// **** FCRxFE00_70A4 Register Definition ****
-// Address
-#define FCRxFE00_70A4_ADDRESS 0xfe0070a4
-
-// Type
-#define FCRxFE00_70A4_TYPE TYPE_FCR
-// Field Data
-#define FCRxFE00_70A4_Reserved_3_0_OFFSET 0
-#define FCRxFE00_70A4_Reserved_3_0_WIDTH 4
-#define FCRxFE00_70A4_Reserved_3_0_MASK 0xf
-#define FCRxFE00_70A4_SclkDpmVid0_OFFSET 4
-#define FCRxFE00_70A4_SclkDpmVid0_WIDTH 2
-#define FCRxFE00_70A4_SclkDpmVid0_MASK 0x30
-#define FCRxFE00_70A4_SclkDpmVid1_OFFSET 6
-#define FCRxFE00_70A4_SclkDpmVid1_WIDTH 2
-#define FCRxFE00_70A4_SclkDpmVid1_MASK 0xc0
-#define FCRxFE00_70A4_SclkDpmVid2_OFFSET 8
-#define FCRxFE00_70A4_SclkDpmVid2_WIDTH 2
-#define FCRxFE00_70A4_SclkDpmVid2_MASK 0x300
-#define FCRxFE00_70A4_SclkDpmVid3_OFFSET 10
-#define FCRxFE00_70A4_SclkDpmVid3_WIDTH 2
-#define FCRxFE00_70A4_SclkDpmVid3_MASK 0xc00
-#define FCRxFE00_70A4_SclkDpmVid4_OFFSET 12
-#define FCRxFE00_70A4_SclkDpmVid4_WIDTH 2
-#define FCRxFE00_70A4_SclkDpmVid4_MASK 0x3000
-#define FCRxFE00_70A4_Reserved_31_14_OFFSET 14
-#define FCRxFE00_70A4_Reserved_31_14_WIDTH 18
-#define FCRxFE00_70A4_Reserved_31_14_MASK 0xffffc000
-
-/// FCRxFE00_70A4
-typedef union {
- struct { ///<
- UINT32 Reserved_3_0:4 ; ///<
- UINT32 SclkDpmVid0:2 ; ///<
- UINT32 SclkDpmVid1:2 ; ///<
- UINT32 SclkDpmVid2:2 ; ///<
- UINT32 SclkDpmVid3:2 ; ///<
- UINT32 SclkDpmVid4:2 ; ///<
- UINT32 Reserved_31_14:18; ///<
- } Field; ///<
- UINT32 Value; ///<
-} FCRxFE00_70A4_STRUCT;
-
-// **** FCRxFE00_70A5 Register Definition ****
-// Address
-#define FCRxFE00_70A5_ADDRESS 0xfe0070a5
-
-// Type
-#define FCRxFE00_70A5_TYPE TYPE_FCR
-// Field Data
-#define FCRxFE00_70A5_Reserved_5_0_OFFSET 0
-#define FCRxFE00_70A5_Reserved_5_0_WIDTH 6
-#define FCRxFE00_70A5_Reserved_5_0_MASK 0x3f
-#define FCRxFE00_70A5_SclkDpmDid0_OFFSET 6
-#define FCRxFE00_70A5_SclkDpmDid0_WIDTH 7
-#define FCRxFE00_70A5_SclkDpmDid0_MASK 0x1fc0
-#define FCRxFE00_70A5_SclkDpmDid1_OFFSET 13
-#define FCRxFE00_70A5_SclkDpmDid1_WIDTH 7
-#define FCRxFE00_70A5_SclkDpmDid1_MASK 0xfe000
-#define FCRxFE00_70A5_SclkDpmDid2_OFFSET 20
-#define FCRxFE00_70A5_SclkDpmDid2_WIDTH 7
-#define FCRxFE00_70A5_SclkDpmDid2_MASK 0x7f00000
-#define FCRxFE00_70A5_Reserved_31_27_OFFSET 27
-#define FCRxFE00_70A5_Reserved_31_27_WIDTH 5
-#define FCRxFE00_70A5_Reserved_31_27_MASK 0xf8000000
-
-/// FCRxFE00_70A5
-typedef union {
- struct { ///<
- UINT32 Reserved_5_0:6 ; ///<
- UINT32 SclkDpmDid0:7 ; ///<
- UINT32 SclkDpmDid1:7 ; ///<
- UINT32 SclkDpmDid2:7 ; ///<
- UINT32 Reserved_31_27:5 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} FCRxFE00_70A5_STRUCT;
-
-// **** FCRxFE00_70A8 Register Definition ****
-// Address
-#define FCRxFE00_70A8_ADDRESS 0xfe0070a8
-
-// Type
-#define FCRxFE00_70A8_TYPE TYPE_FCR
-// Field Data
-#define FCRxFE00_70A8_Reserved_2_0_OFFSET 0
-#define FCRxFE00_70A8_Reserved_2_0_WIDTH 3
-#define FCRxFE00_70A8_Reserved_2_0_MASK 0x7
-#define FCRxFE00_70A8_SclkDpmDid3_OFFSET 3
-#define FCRxFE00_70A8_SclkDpmDid3_WIDTH 7
-#define FCRxFE00_70A8_SclkDpmDid3_MASK 0x3f8
-#define FCRxFE00_70A8_SclkDpmDid4_OFFSET 10
-#define FCRxFE00_70A8_SclkDpmDid4_WIDTH 7
-#define FCRxFE00_70A8_SclkDpmDid4_MASK 0x1fc00
-#define FCRxFE00_70A8_Reserved_31_17_OFFSET 17
-#define FCRxFE00_70A8_Reserved_31_17_WIDTH 15
-#define FCRxFE00_70A8_Reserved_31_17_MASK 0xfffe0000
-
-/// FCRxFE00_70A8
-typedef union {
- struct { ///<
- UINT32 Reserved_2_0:3 ; ///<
- UINT32 SclkDpmDid3:7 ; ///<
- UINT32 SclkDpmDid4:7 ; ///<
- UINT32 Reserved_31_17:15; ///<
- } Field; ///<
- UINT32 Value; ///<
-} FCRxFE00_70A8_STRUCT;
-
-// **** FCRxFE00_70AE Register Definition ****
-// Address
-#define FCRxFE00_70AE_ADDRESS 0xfe0070ae
-
-// Type
-#define FCRxFE00_70AE_TYPE TYPE_FCR
-// Field Data
-#define FCRxFE00_70AE_Reserved_0_0_OFFSET 0
-#define FCRxFE00_70AE_Reserved_0_0_WIDTH 1
-#define FCRxFE00_70AE_Reserved_0_0_MASK 0x1
-#define FCRxFE00_70AE_DispClkDid0_OFFSET 1
-#define FCRxFE00_70AE_DispClkDid0_WIDTH 7
-#define FCRxFE00_70AE_DispClkDid0_MASK 0xfe
-#define FCRxFE00_70AE_DispClkDid1_OFFSET 8
-#define FCRxFE00_70AE_DispClkDid1_WIDTH 7
-#define FCRxFE00_70AE_DispClkDid1_MASK 0x7f00
-#define FCRxFE00_70AE_DispClkDid2_OFFSET 15
-#define FCRxFE00_70AE_DispClkDid2_WIDTH 7
-#define FCRxFE00_70AE_DispClkDid2_MASK 0x3f8000
-#define FCRxFE00_70AE_DispClkDid3_OFFSET 22
-#define FCRxFE00_70AE_DispClkDid3_WIDTH 7
-#define FCRxFE00_70AE_DispClkDid3_MASK 0x1fc00000
-#define FCRxFE00_70AE_Reserved_31_29_OFFSET 29
-#define FCRxFE00_70AE_Reserved_31_29_WIDTH 3
-#define FCRxFE00_70AE_Reserved_31_29_MASK 0xe0000000
-
-/// FCRxFE00_70AE
-typedef union {
- struct { ///<
- UINT32 Reserved_0_0:1 ; ///<
- UINT32 DispClkDid0:7 ; ///<
- UINT32 DispClkDid1:7 ; ///<
- UINT32 DispClkDid2:7 ; ///<
- UINT32 DispClkDid3:7 ; ///<
- UINT32 Reserved_31_29:3 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} FCRxFE00_70AE_STRUCT;
-
-// **** FCRxFE00_70B1 Register Definition ****
-// Address
-#define FCRxFE00_70B1_ADDRESS 0xfe0070b1
-
-// Type
-#define FCRxFE00_70B1_TYPE TYPE_FCR
-// Field Data
-#define FCRxFE00_70B1_Reserved_4_0_OFFSET 0
-#define FCRxFE00_70B1_Reserved_4_0_WIDTH 5
-#define FCRxFE00_70B1_Reserved_4_0_MASK 0x1f
-#define FCRxFE00_70B1_LclkDpmDid0_OFFSET 5
-#define FCRxFE00_70B1_LclkDpmDid0_WIDTH 7
-#define FCRxFE00_70B1_LclkDpmDid0_MASK 0xfe0
-#define FCRxFE00_70B1_LclkDpmDid1_OFFSET 12
-#define FCRxFE00_70B1_LclkDpmDid1_WIDTH 7
-#define FCRxFE00_70B1_LclkDpmDid1_MASK 0x7f000
-#define FCRxFE00_70B1_LclkDpmDid2_OFFSET 19
-#define FCRxFE00_70B1_LclkDpmDid2_WIDTH 7
-#define FCRxFE00_70B1_LclkDpmDid2_MASK 0x3f80000
-#define FCRxFE00_70B1_Reserved_31_26_OFFSET 26
-#define FCRxFE00_70B1_Reserved_31_26_WIDTH 6
-#define FCRxFE00_70B1_Reserved_31_26_MASK 0xfc000000
-
-/// FCRxFE00_70B1
-typedef union {
- struct { ///<
- UINT32 Reserved_4_0:5 ; ///<
- UINT32 LclkDpmDid0:7 ; ///<
- UINT32 LclkDpmDid1:7 ; ///<
- UINT32 LclkDpmDid2:7 ; ///<
- UINT32 Reserved_31_26:6 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} FCRxFE00_70B1_STRUCT;
-
-// **** FCRxFE00_70B4 Register Definition ****
-// Address
-#define FCRxFE00_70B4_ADDRESS 0xfe0070b4
-
-// Type
-#define FCRxFE00_70B4_TYPE TYPE_FCR
-// Field Data
-#define FCRxFE00_70B4_Reserved_1_0_OFFSET 0
-#define FCRxFE00_70B4_Reserved_1_0_WIDTH 2
-#define FCRxFE00_70B4_Reserved_1_0_MASK 0x3
-#define FCRxFE00_70B4_LclkDpmDid3_OFFSET 2
-#define FCRxFE00_70B4_LclkDpmDid3_WIDTH 7
-#define FCRxFE00_70B4_LclkDpmDid3_MASK 0x1fc
-#define FCRxFE00_70B4_LclkDpmValid0_OFFSET 9
-#define FCRxFE00_70B4_LclkDpmValid0_WIDTH 1
-#define FCRxFE00_70B4_LclkDpmValid0_MASK 0x200
-#define FCRxFE00_70B4_LclkDpmValid1_OFFSET 10
-#define FCRxFE00_70B4_LclkDpmValid1_WIDTH 1
-#define FCRxFE00_70B4_LclkDpmValid1_MASK 0x400
-#define FCRxFE00_70B4_LclkDpmValid2_OFFSET 11
-#define FCRxFE00_70B4_LclkDpmValid2_WIDTH 1
-#define FCRxFE00_70B4_LclkDpmValid2_MASK 0x800
-#define FCRxFE00_70B4_LclkDpmValid3_OFFSET 12
-#define FCRxFE00_70B4_LclkDpmValid3_WIDTH 1
-#define FCRxFE00_70B4_LclkDpmValid3_MASK 0x1000
-#define FCRxFE00_70B4_Reserved_31_13_OFFSET 13
-#define FCRxFE00_70B4_Reserved_31_13_WIDTH 19
-#define FCRxFE00_70B4_Reserved_31_13_MASK 0xffffe000
-
-/// FCRxFE00_70B4
-typedef union {
- struct { ///<
- UINT32 Reserved_1_0:2 ; ///<
- UINT32 LclkDpmDid3:7 ; ///<
- UINT32 LclkDpmValid0:1 ; ///<
- UINT32 LclkDpmValid1:1 ; ///<
- UINT32 LclkDpmValid2:1 ; ///<
- UINT32 LclkDpmValid3:1 ; ///<
- UINT32 Reserved_31_13:19; ///<
- } Field; ///<
- UINT32 Value; ///<
-} FCRxFE00_70B4_STRUCT;
-
-// **** FCRxFE00_70B5 Register Definition ****
-// Address
-#define FCRxFE00_70B5_ADDRESS 0xfe0070b5
-
-// Type
-#define FCRxFE00_70B5_TYPE TYPE_FCR
-// Field Data
-#define FCRxFE00_70B5_Reserved_4_0_OFFSET 0
-#define FCRxFE00_70B5_Reserved_4_0_WIDTH 5
-#define FCRxFE00_70B5_Reserved_4_0_MASK 0x1f
-#define FCRxFE00_70B5_DclkDid0_OFFSET 5
-#define FCRxFE00_70B5_DclkDid0_WIDTH 7
-#define FCRxFE00_70B5_DclkDid0_MASK 0xfe0
-#define FCRxFE00_70B5_DclkDid1_OFFSET 12
-#define FCRxFE00_70B5_DclkDid1_WIDTH 7
-#define FCRxFE00_70B5_DclkDid1_MASK 0x7f000
-#define FCRxFE00_70B5_DclkDid2_OFFSET 19
-#define FCRxFE00_70B5_DclkDid2_WIDTH 7
-#define FCRxFE00_70B5_DclkDid2_MASK 0x3f80000
-#define FCRxFE00_70B5_Reserved_31_26_OFFSET 26
-#define FCRxFE00_70B5_Reserved_31_26_WIDTH 6
-#define FCRxFE00_70B5_Reserved_31_26_MASK 0xfc000000
-
-/// FCRxFE00_70B5
-typedef union {
- struct { ///<
- UINT32 Reserved_4_0:5 ; ///<
- UINT32 DclkDid0:7 ; ///<
- UINT32 DclkDid1:7 ; ///<
- UINT32 DclkDid2:7 ; ///<
- UINT32 Reserved_31_26:6 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} FCRxFE00_70B5_STRUCT;
-
-// **** FCRxFE00_70B8 Register Definition ****
-// Address
-#define FCRxFE00_70B8_ADDRESS 0xfe0070b8
-
-// Type
-#define FCRxFE00_70B8_TYPE TYPE_FCR
-// Field Data
-#define FCRxFE00_70B8_Reserved_1_0_OFFSET 0
-#define FCRxFE00_70B8_Reserved_1_0_WIDTH 2
-#define FCRxFE00_70B8_Reserved_1_0_MASK 0x3
-#define FCRxFE00_70B8_DclkDid3_OFFSET 2
-#define FCRxFE00_70B8_DclkDid3_WIDTH 7
-#define FCRxFE00_70B8_DclkDid3_MASK 0x1fc
-#define FCRxFE00_70B8_Reserved_31_9_OFFSET 9
-#define FCRxFE00_70B8_Reserved_31_9_WIDTH 23
-#define FCRxFE00_70B8_Reserved_31_9_MASK 0xfffffe00
-
-/// FCRxFE00_70B8
-typedef union {
- struct { ///<
- UINT32 Reserved_1_0:2 ; ///<
- UINT32 DclkDid3:7 ; ///<
- UINT32 Reserved_31_9:23; ///<
- } Field; ///<
- UINT32 Value; ///<
-} FCRxFE00_70B8_STRUCT;
-
-// **** FCRxFE00_70B9 Register Definition ****
-// Address
-#define FCRxFE00_70B9_ADDRESS 0xfe0070b9
-
-// Type
-#define FCRxFE00_70B9_TYPE TYPE_FCR
-// Field Data
-#define FCRxFE00_70B9_Reserved_0_0_OFFSET 0
-#define FCRxFE00_70B9_Reserved_0_0_WIDTH 1
-#define FCRxFE00_70B9_Reserved_0_0_MASK 0x1
-#define FCRxFE00_70B9_VclkDid0_OFFSET 1
-#define FCRxFE00_70B9_VclkDid0_WIDTH 7
-#define FCRxFE00_70B9_VclkDid0_MASK 0xfe
-#define FCRxFE00_70B9_VclkDid1_OFFSET 8
-#define FCRxFE00_70B9_VclkDid1_WIDTH 7
-#define FCRxFE00_70B9_VclkDid1_MASK 0x7f00
-#define FCRxFE00_70B9_VclkDid2_OFFSET 15
-#define FCRxFE00_70B9_VclkDid2_WIDTH 7
-#define FCRxFE00_70B9_VclkDid2_MASK 0x3f8000
-#define FCRxFE00_70B9_VclkDid3_OFFSET 22
-#define FCRxFE00_70B9_VclkDid3_WIDTH 7
-#define FCRxFE00_70B9_VclkDid3_MASK 0x1fc00000
-#define FCRxFE00_70B9_Reserved_31_29_OFFSET 29
-#define FCRxFE00_70B9_Reserved_31_29_WIDTH 3
-#define FCRxFE00_70B9_Reserved_31_29_MASK 0xe0000000
-
-/// FCRxFE00_70B9
-typedef union {
- struct { ///<
- UINT32 Reserved_0_0:1 ; ///<
- UINT32 VclkDid0:7 ; ///<
- UINT32 VclkDid1:7 ; ///<
- UINT32 VclkDid2:7 ; ///<
- UINT32 VclkDid3:7 ; ///<
- UINT32 Reserved_31_29:3 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} FCRxFE00_70B9_STRUCT;
-
-// **** FCRxFE00_70BC Register Definition ****
-// Address
-#define FCRxFE00_70BC_ADDRESS 0xfe0070bc
-
-// Type
-#define FCRxFE00_70BC_TYPE TYPE_FCR
-// Field Data
-#define FCRxFE00_70BC_Reserved_4_0_OFFSET 0
-#define FCRxFE00_70BC_Reserved_4_0_WIDTH 5
-#define FCRxFE00_70BC_Reserved_4_0_MASK 0x1f
-#define FCRxFE00_70BC_SclkDpmValid0_OFFSET 5
-#define FCRxFE00_70BC_SclkDpmValid0_WIDTH 5
-#define FCRxFE00_70BC_SclkDpmValid0_MASK 0x3e0
-#define FCRxFE00_70BC_SclkDpmValid1_OFFSET 10
-#define FCRxFE00_70BC_SclkDpmValid1_WIDTH 5
-#define FCRxFE00_70BC_SclkDpmValid1_MASK 0x7c00
-#define FCRxFE00_70BC_SclkDpmValid2_OFFSET 15
-#define FCRxFE00_70BC_SclkDpmValid2_WIDTH 5
-#define FCRxFE00_70BC_SclkDpmValid2_MASK 0xf8000
-#define FCRxFE00_70BC_SclkDpmValid3_OFFSET 20
-#define FCRxFE00_70BC_SclkDpmValid3_WIDTH 5
-#define FCRxFE00_70BC_SclkDpmValid3_MASK 0x1f00000
-#define FCRxFE00_70BC_SclkDpmValid4_OFFSET 25
-#define FCRxFE00_70BC_SclkDpmValid4_WIDTH 5
-#define FCRxFE00_70BC_SclkDpmValid4_MASK 0x3e000000
-#define FCRxFE00_70BC_Reserved_31_30_OFFSET 30
-#define FCRxFE00_70BC_Reserved_31_30_WIDTH 2
-#define FCRxFE00_70BC_Reserved_31_30_MASK 0xc0000000
-
-/// FCRxFE00_70BC
-typedef union {
- struct { ///<
- UINT32 Reserved_4_0:5 ; ///<
- UINT32 SclkDpmValid0:5 ; ///<
- UINT32 SclkDpmValid1:5 ; ///<
- UINT32 SclkDpmValid2:5 ; ///<
- UINT32 SclkDpmValid3:5 ; ///<
- UINT32 SclkDpmValid4:5 ; ///<
- UINT32 Reserved_31_30:2 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} FCRxFE00_70BC_STRUCT;
-
-// **** FCRxFE00_70BF Register Definition ****
-// Address
-#define FCRxFE00_70BF_ADDRESS 0xfe0070bf
-
-// Type
-#define FCRxFE00_70BF_TYPE TYPE_FCR
-// Field Data
-#define FCRxFE00_70BF_Reserved_5_0_OFFSET 0
-#define FCRxFE00_70BF_Reserved_5_0_WIDTH 6
-#define FCRxFE00_70BF_Reserved_5_0_MASK 0x3f
-#define FCRxFE00_70BF_SclkDpmValid5_OFFSET 6
-#define FCRxFE00_70BF_SclkDpmValid5_WIDTH 5
-#define FCRxFE00_70BF_SclkDpmValid5_MASK 0x7c0
-#define FCRxFE00_70BF_Reserved_31_11_OFFSET 11
-#define FCRxFE00_70BF_Reserved_31_11_WIDTH 21
-#define FCRxFE00_70BF_Reserved_31_11_MASK 0xfffff800
-
-/// FCRxFE00_70BF
-typedef union {
- struct { ///<
- UINT32 Reserved_5_0:6 ; ///<
- UINT32 SclkDpmValid5:5 ; ///<
- UINT32 Reserved_31_11:21; ///<
- } Field; ///<
- UINT32 Value; ///<
-} FCRxFE00_70BF_STRUCT;
-
-// **** FCRxFE00_70C0 Register Definition ****
-// Address
-#define FCRxFE00_70C0_ADDRESS 0xfe0070c0
-
-// Type
-#define FCRxFE00_70C0_TYPE TYPE_FCR
-// Field Data
-#define FCRxFE00_70C0_Reserved_2_0_OFFSET 0
-#define FCRxFE00_70C0_Reserved_2_0_WIDTH 3
-#define FCRxFE00_70C0_Reserved_2_0_MASK 0x7
-#define FCRxFE00_70C0_PolicyLabel0_OFFSET 3
-#define FCRxFE00_70C0_PolicyLabel0_WIDTH 2
-#define FCRxFE00_70C0_PolicyLabel0_MASK 0x18
-#define FCRxFE00_70C0_PolicyLabel1_OFFSET 5
-#define FCRxFE00_70C0_PolicyLabel1_WIDTH 2
-#define FCRxFE00_70C0_PolicyLabel1_MASK 0x60
-#define FCRxFE00_70C0_PolicyLabel2_OFFSET 7
-#define FCRxFE00_70C0_PolicyLabel2_WIDTH 2
-#define FCRxFE00_70C0_PolicyLabel2_MASK 0x180
-#define FCRxFE00_70C0_PolicyLabel3_OFFSET 9
-#define FCRxFE00_70C0_PolicyLabel3_WIDTH 2
-#define FCRxFE00_70C0_PolicyLabel3_MASK 0x600
-#define FCRxFE00_70C0_PolicyLabel4_OFFSET 11
-#define FCRxFE00_70C0_PolicyLabel4_WIDTH 2
-#define FCRxFE00_70C0_PolicyLabel4_MASK 0x1800
-#define FCRxFE00_70C0_PolicyLabel5_OFFSET 13
-#define FCRxFE00_70C0_PolicyLabel5_WIDTH 2
-#define FCRxFE00_70C0_PolicyLabel5_MASK 0x6000
-#define FCRxFE00_70C0_Reserved_31_15_OFFSET 15
-#define FCRxFE00_70C0_Reserved_31_15_WIDTH 17
-#define FCRxFE00_70C0_Reserved_31_15_MASK 0xffff8000
-
-/// FCRxFE00_70C0
-typedef union {
- struct { ///<
- UINT32 Reserved_2_0:3 ; ///<
- UINT32 PolicyLabel0:2 ; ///<
- UINT32 PolicyLabel1:2 ; ///<
- UINT32 PolicyLabel2:2 ; ///<
- UINT32 PolicyLabel3:2 ; ///<
- UINT32 PolicyLabel4:2 ; ///<
- UINT32 PolicyLabel5:2 ; ///<
- UINT32 Reserved_31_15:17; ///<
- } Field; ///<
- UINT32 Value; ///<
-} FCRxFE00_70C0_STRUCT;
-
-// **** FCRxFE00_70C1 Register Definition ****
-// Address
-#define FCRxFE00_70C1_ADDRESS 0xfe0070c1
-
-// Type
-#define FCRxFE00_70C1_TYPE TYPE_FCR
-// Field Data
-#define FCRxFE00_70C1_Reserved_6_0_OFFSET 0
-#define FCRxFE00_70C1_Reserved_6_0_WIDTH 7
-#define FCRxFE00_70C1_Reserved_6_0_MASK 0x7f
-#define FCRxFE00_70C1_PolicyFlags0_OFFSET 7
-#define FCRxFE00_70C1_PolicyFlags0_WIDTH 7
-#define FCRxFE00_70C1_PolicyFlags0_MASK 0x3f80
-#define FCRxFE00_70C1_PolicyFlags1_OFFSET 14
-#define FCRxFE00_70C1_PolicyFlags1_WIDTH 7
-#define FCRxFE00_70C1_PolicyFlags1_MASK 0x1fc000
-#define FCRxFE00_70C1_PolicyFlags2_OFFSET 21
-#define FCRxFE00_70C1_PolicyFlags2_WIDTH 7
-#define FCRxFE00_70C1_PolicyFlags2_MASK 0xfe00000
-#define FCRxFE00_70C1_Reserved_31_28_OFFSET 28
-#define FCRxFE00_70C1_Reserved_31_28_WIDTH 4
-#define FCRxFE00_70C1_Reserved_31_28_MASK 0xf0000000
-
-/// FCRxFE00_70C1
-typedef union {
- struct { ///<
- UINT32 Reserved_6_0:7 ; ///<
- UINT32 PolicyFlags0:7 ; ///<
- UINT32 PolicyFlags1:7 ; ///<
- UINT32 PolicyFlags2:7 ; ///<
- UINT32 Reserved_31_28:4 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} FCRxFE00_70C1_STRUCT;
-
-// **** FCRxFE00_70C4 Register Definition ****
-// Address
-#define FCRxFE00_70C4_ADDRESS 0xfe0070c4
-
-// Type
-#define FCRxFE00_70C4_TYPE TYPE_FCR
-// Field Data
-#define FCRxFE00_70C4_Reserved_3_0_OFFSET 0
-#define FCRxFE00_70C4_Reserved_3_0_WIDTH 4
-#define FCRxFE00_70C4_Reserved_3_0_MASK 0xf
-#define FCRxFE00_70C4_PolicyFlags3_OFFSET 4
-#define FCRxFE00_70C4_PolicyFlags3_WIDTH 7
-#define FCRxFE00_70C4_PolicyFlags3_MASK 0x7f0
-#define FCRxFE00_70C4_PolicyFlags4_OFFSET 11
-#define FCRxFE00_70C4_PolicyFlags4_WIDTH 7
-#define FCRxFE00_70C4_PolicyFlags4_MASK 0x3f800
-#define FCRxFE00_70C4_PolicyFlags5_OFFSET 18
-#define FCRxFE00_70C4_PolicyFlags5_WIDTH 7
-#define FCRxFE00_70C4_PolicyFlags5_MASK 0x1fc0000
-#define FCRxFE00_70C4_Reserved_31_25_OFFSET 25
-#define FCRxFE00_70C4_Reserved_31_25_WIDTH 7
-#define FCRxFE00_70C4_Reserved_31_25_MASK 0xfe000000
-
-/// FCRxFE00_70C4
-typedef union {
- struct { ///<
- UINT32 Reserved_3_0:4 ; ///<
- UINT32 PolicyFlags3:7 ; ///<
- UINT32 PolicyFlags4:7 ; ///<
- UINT32 PolicyFlags5:7 ; ///<
- UINT32 Reserved_31_25:7 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} FCRxFE00_70C4_STRUCT;
-
-// **** FCRxFE00_70C7 Register Definition ****
-// Address
-#define FCRxFE00_70C7_ADDRESS 0xfe0070c7
-
-// Type
-#define FCRxFE00_70C7_TYPE TYPE_FCR
-// Field Data
-#define FCRxFE00_70C7_Reserved_0_0_OFFSET 0
-#define FCRxFE00_70C7_Reserved_0_0_WIDTH 1
-#define FCRxFE00_70C7_Reserved_0_0_MASK 0x1
-#define FCRxFE00_70C7_DclkVclkSel0_OFFSET 1
-#define FCRxFE00_70C7_DclkVclkSel0_WIDTH 2
-#define FCRxFE00_70C7_DclkVclkSel0_MASK 0x6
-#define FCRxFE00_70C7_DclkVclkSel1_OFFSET 3
-#define FCRxFE00_70C7_DclkVclkSel1_WIDTH 2
-#define FCRxFE00_70C7_DclkVclkSel1_MASK 0x18
-#define FCRxFE00_70C7_DclkVclkSel2_OFFSET 5
-#define FCRxFE00_70C7_DclkVclkSel2_WIDTH 2
-#define FCRxFE00_70C7_DclkVclkSel2_MASK 0x60
-#define FCRxFE00_70C7_DclkVclkSel3_OFFSET 7
-#define FCRxFE00_70C7_DclkVclkSel3_WIDTH 2
-#define FCRxFE00_70C7_DclkVclkSel3_MASK 0x180
-#define FCRxFE00_70C7_DclkVclkSel4_OFFSET 9
-#define FCRxFE00_70C7_DclkVclkSel4_WIDTH 2
-#define FCRxFE00_70C7_DclkVclkSel4_MASK 0x600
-#define FCRxFE00_70C7_DclkVclkSel5_OFFSET 11
-#define FCRxFE00_70C7_DclkVclkSel5_WIDTH 2
-#define FCRxFE00_70C7_DclkVclkSel5_MASK 0x1800
-#define FCRxFE00_70C7_Reserved_31_13_OFFSET 13
-#define FCRxFE00_70C7_Reserved_31_13_WIDTH 19
-#define FCRxFE00_70C7_Reserved_31_13_MASK 0xffffe000
-
-/// FCRxFE00_70C7
-typedef union {
- struct { ///<
- UINT32 Reserved_0_0:1 ; ///<
- UINT32 DclkVclkSel0:2 ; ///<
- UINT32 DclkVclkSel1:2 ; ///<
- UINT32 DclkVclkSel2:2 ; ///<
- UINT32 DclkVclkSel3:2 ; ///<
- UINT32 DclkVclkSel4:2 ; ///<
- UINT32 DclkVclkSel5:2 ; ///<
- UINT32 Reserved_31_13:19; ///<
- } Field; ///<
- UINT32 Value; ///<
-} FCRxFE00_70C7_STRUCT;
-
-// **** FCRxFE00_70A2 Register Definition ****
-// Address
-#define FCRxFE00_70A2_ADDRESS 0xfe0070a2
-
-// Type
-#define FCRxFE00_70A2_TYPE TYPE_FCR
-// Field Data
-#define FCRxFE00_70A2_Reserved_6_0_OFFSET 0
-#define FCRxFE00_70A2_Reserved_6_0_WIDTH 7
-#define FCRxFE00_70A2_Reserved_6_0_MASK 0x7f
-#define FCRxFE00_70A2_PPlayTableRev_OFFSET 7
-#define FCRxFE00_70A2_PPlayTableRev_WIDTH 4
-#define FCRxFE00_70A2_PPlayTableRev_MASK 0x780
-#define FCRxFE00_70A2_SclkThermDid_OFFSET 11
-#define FCRxFE00_70A2_SclkThermDid_WIDTH 7
-#define FCRxFE00_70A2_SclkThermDid_MASK 0x3f800
-#define FCRxFE00_70A2_PcieGen2Vid_OFFSET 18
-#define FCRxFE00_70A2_PcieGen2Vid_WIDTH 2
-#define FCRxFE00_70A2_PcieGen2Vid_MASK 0xc0000
-#define FCRxFE00_70A2_Reserved_31_20_OFFSET 20
-#define FCRxFE00_70A2_Reserved_31_20_WIDTH 12
-#define FCRxFE00_70A2_Reserved_31_20_MASK 0xfff00000
-
-/// FCRxFE00_70A2
-typedef union {
- struct { ///<
- UINT32 Reserved_6_0:7 ; ///<
- UINT32 PPlayTableRev:4 ; ///<
- UINT32 SclkThermDid:7 ; ///<
- UINT32 PcieGen2Vid:2 ; ///<
- UINT32 Reserved_31_20:12; ///<
- } Field; ///<
- UINT32 Value; ///<
-} FCRxFE00_70A2_STRUCT;
-
-// **** FCRxFE00_70AA Register Definition ****
-// Address
-#define FCRxFE00_70AA_ADDRESS 0xfe0070aa
-
-// Type
-#define FCRxFE00_70AA_TYPE TYPE_FCR
-// Field Data
-#define FCRxFE00_70AA_Reserved_0_0_OFFSET 0
-#define FCRxFE00_70AA_Reserved_0_0_WIDTH 1
-#define FCRxFE00_70AA_Reserved_0_0_MASK 0x1
-#define FCRxFE00_70AA_SclkDpmCacBase_OFFSET 1
-#define FCRxFE00_70AA_SclkDpmCacBase_WIDTH 8
-#define FCRxFE00_70AA_SclkDpmCacBase_MASK 0x1fe
-#define FCRxFE00_70AA_Reserved_31_9_OFFSET 9
-#define FCRxFE00_70AA_Reserved_31_9_WIDTH 23
-#define FCRxFE00_70AA_Reserved_31_9_MASK 0xfffffe00
-
-/// FCRxFE00_70AA
-typedef union {
- struct { ///<
- UINT32 Reserved_0_0:1 ; ///<
- UINT32 SclkDpmCacBase:8 ; ///<
- UINT32 Reserved_31_9:23; ///<
- } Field; ///<
- UINT32 Value; ///<
-} FCRxFE00_70AA_STRUCT;
-
-// **** D18F3xD4 Register Definition ****
-// Address
-#define D18F3xD4_ADDRESS 0xd4
-
-// Type
-#define D18F3xD4_TYPE TYPE_D18F3
-// Field Data
-#define D18F3xD4_MainPllOpFreqId_OFFSET 0
-#define D18F3xD4_MainPllOpFreqId_WIDTH 6
-#define D18F3xD4_MainPllOpFreqId_MASK 0x3f
-#define D18F3xD4_MainPllOpFreqIdEn_OFFSET 6
-#define D18F3xD4_MainPllOpFreqIdEn_WIDTH 1
-#define D18F3xD4_MainPllOpFreqIdEn_MASK 0x40
-#define D18F3xD4_Reserved_7_7_OFFSET 7
-#define D18F3xD4_Reserved_7_7_WIDTH 1
-#define D18F3xD4_Reserved_7_7_MASK 0x80
-#define D18F3xD4_ClkRampHystSel_OFFSET 8
-#define D18F3xD4_ClkRampHystSel_WIDTH 4
-#define D18F3xD4_ClkRampHystSel_MASK 0xf00
-#define D18F3xD4_OnionOutHyst_OFFSET 12
-#define D18F3xD4_OnionOutHyst_WIDTH 4
-#define D18F3xD4_OnionOutHyst_MASK 0xf000
-#define D18F3xD4_DisNclkGatingIdle_OFFSET 16
-#define D18F3xD4_DisNclkGatingIdle_WIDTH 1
-#define D18F3xD4_DisNclkGatingIdle_MASK 0x10000
-#define D18F3xD4_ClockGatingEnDram_OFFSET 17
-#define D18F3xD4_ClockGatingEnDram_WIDTH 1
-#define D18F3xD4_ClockGatingEnDram_MASK 0x20000
-#define D18F3xD4_Reserved_31_18_OFFSET 18
-#define D18F3xD4_Reserved_31_18_WIDTH 14
-#define D18F3xD4_Reserved_31_18_MASK 0xfffc0000
-
-/// D18F3xD4
-typedef union {
- struct { ///<
- UINT32 MainPllOpFreqId:6 ; ///<
- UINT32 MainPllOpFreqIdEn:1 ; ///<
- UINT32 Reserved_7_7:1 ; ///<
- UINT32 ClkRampHystSel:4 ; ///<
- UINT32 OnionOutHyst:4 ; ///<
- UINT32 DisNclkGatingIdle:1 ; ///<
- UINT32 ClockGatingEnDram:1 ; ///<
- UINT32 Reserved_31_18:14; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D18F3xD4_STRUCT;
-
-// **** FCRxFF30_01F4 Register Definition ****
-// Address
-#define FCRxFF30_01F4_ADDRESS 0xff3001f4
-
-// Type
-#define FCRxFF30_01F4_TYPE TYPE_FCR
-// Field Data
-#define FCRxFF30_01F4_ReservedCgttSclk_21_0_OFFSET 0
-#define FCRxFF30_01F4_ReservedCgttSclk_21_0_WIDTH 21
-#define FCRxFF30_01F4_ReservedCgttSclk_21_0_MASK 0x3fffff
-#define FCRxFF30_01F4_CgBifCgttSclkOverride_OFFSET 22
-#define FCRxFF30_01F4_CgBifCgttSclkOverride_WIDTH 1
-#define FCRxFF30_01F4_CgBifCgttSclkOverride_MASK 0x400000
-#define FCRxFF30_01F4_ReservedCgttSclk_24_23_OFFSET 23
-#define FCRxFF30_01F4_ReservedCgttSclk_24_23_WIDTH 2
-#define FCRxFF30_01F4_ReservedCgttSclk_24_23_MASK 0x1800000
-#define FCRxFF30_01F4_CgDcCgttSclkOverride_OFFSET 25
-#define FCRxFF30_01F4_CgDcCgttSclkOverride_WIDTH 1
-#define FCRxFF30_01F4_CgDcCgttSclkOverride_MASK 0x2000000
-#define FCRxFF30_01F4_ReservedCgttSclk_26_26_OFFSET 26
-#define FCRxFF30_01F4_ReservedCgttSclk_26_26_WIDTH 1
-#define FCRxFF30_01F4_ReservedCgttSclk_26_26_MASK 0x4000000
-#define FCRxFF30_01F4_CgMcbCgttSclkOverride_OFFSET 27
-#define FCRxFF30_01F4_CgMcbCgttSclkOverride_WIDTH 1
-#define FCRxFF30_01F4_CgMcbCgttSclkOverride_MASK 0x8000000
-#define FCRxFF30_01F4_CgMcdwCgttSclkOverride_OFFSET 28
-#define FCRxFF30_01F4_CgMcdwCgttSclkOverride_WIDTH 1
-#define FCRxFF30_01F4_CgMcdwCgttSclkOverride_MASK 0x10000000
-#define FCRxFF30_01F4_ReservedCgttSclk_31_29_OFFSET 29
-#define FCRxFF30_01F4_ReservedCgttSclk_31_29_WIDTH 3
-#define FCRxFF30_01F4_ReservedCgttSclk_31_29_MASK 0xe0000000
-
-/// FCRxFF30_01F4
-typedef union {
- struct { ///<
- UINT32 ReservedCgttSclk_21_0:22; ///<
- UINT32 CgBifCgttSclkOverride:1 ; ///<
- UINT32 ReservedCgttSclk_24_23:2 ; ///<
- UINT32 CgDcCgttSclkOverride:1 ; ///<
- UINT32 ReservedCgttSclk_26_26:1 ; ///<
- UINT32 CgMcbCgttSclkOverride:1 ; ///<
- UINT32 CgMcdwCgttSclkOverride:1 ; ///<
- UINT32 ReservedCgttSclk_31_29:3 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} FCRxFF30_01F4_STRUCT;
-
-// **** FCRxFF30_01F5 Register Definition ****
-// Address
-#define FCRxFF30_01F5_ADDRESS 0xff3001f5
-
-// Type
-#define FCRxFF30_01F5_TYPE TYPE_FCR
-// Field Data
-#define FCRxFF30_01F5_ReservedCgttSclk_10_0_OFFSET 0
-#define FCRxFF30_01F5_ReservedCgttSclk_10_0_WIDTH 11
-#define FCRxFF30_01F5_ReservedCgttSclk_10_0_MASK 0x7ff
-#define FCRxFF30_01F5_CgVmcCgttSclkOverride_OFFSET 11
-#define FCRxFF30_01F5_CgVmcCgttSclkOverride_WIDTH 1
-#define FCRxFF30_01F5_CgVmcCgttSclkOverride_MASK 0x800
-#define FCRxFF30_01F5_CgOrbCgttSclkOverride_OFFSET 12
-#define FCRxFF30_01F5_CgOrbCgttSclkOverride_WIDTH 1
-#define FCRxFF30_01F5_CgOrbCgttSclkOverride_MASK 0x1000
-#define FCRxFF30_01F5_CgOrbCgttLclkOverride_OFFSET 13
-#define FCRxFF30_01F5_CgOrbCgttLclkOverride_WIDTH 1
-#define FCRxFF30_01F5_CgOrbCgttLclkOverride_MASK 0x2000
-#define FCRxFF30_01F5_CgIocCgttSclkOverride_OFFSET 14
-#define FCRxFF30_01F5_CgIocCgttSclkOverride_WIDTH 1
-#define FCRxFF30_01F5_CgIocCgttSclkOverride_MASK 0x4000
-#define FCRxFF30_01F5_CgIocCgttLclkOverride_OFFSET 15
-#define FCRxFF30_01F5_CgIocCgttLclkOverride_WIDTH 1
-#define FCRxFF30_01F5_CgIocCgttLclkOverride_MASK 0x8000
-#define FCRxFF30_01F5_ReservedCgttSclk_27_16_OFFSET 16
-#define FCRxFF30_01F5_ReservedCgttSclk_27_16_WIDTH 12
-#define FCRxFF30_01F5_ReservedCgttSclk_27_16_MASK 0xfff0000
-#define FCRxFF30_01F5_CgDcCgttDispClkOverride_OFFSET 28
-#define FCRxFF30_01F5_CgDcCgttDispClkOverride_WIDTH 1
-#define FCRxFF30_01F5_CgDcCgttDispClkOverride_MASK 0x10000000
-#define FCRxFF30_01F5_ReservedCgttSclk_31_29_OFFSET 29
-#define FCRxFF30_01F5_ReservedCgttSclk_31_29_WIDTH 3
-#define FCRxFF30_01F5_ReservedCgttSclk_31_29_MASK 0xe0000000
-
-/// FCRxFF30_01F5
-typedef union {
- struct { ///<
- UINT32 ReservedCgttSclk_10_0:11; ///<
- UINT32 CgVmcCgttSclkOverride:1 ; ///<
- UINT32 CgOrbCgttSclkOverride:1 ; ///<
- UINT32 CgOrbCgttLclkOverride:1 ; ///<
- UINT32 CgIocCgttSclkOverride:1 ; ///<
- UINT32 CgIocCgttLclkOverride:1 ; ///<
- UINT32 ReservedCgttSclk_27_16:12; ///<
- UINT32 CgDcCgttDispClkOverride:1 ; ///<
- UINT32 ReservedCgttSclk_31_29:3 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} FCRxFF30_01F5_STRUCT;
-
-// **** FCRxFF30_1512 Register Definition ****
-// Address
-#define FCRxFF30_1512_ADDRESS 0xff301512
-
-// Type
-#define FCRxFF30_1512_TYPE TYPE_FCR
-// Field Data
-#define FCRxFF30_1512_Reserved_30_0_OFFSET 0
-#define FCRxFF30_1512_Reserved_30_0_WIDTH 31
-#define FCRxFF30_1512_Reserved_30_0_MASK 0x7fffffff
-#define FCRxFF30_1512_SoftOverride0_OFFSET 31
-#define FCRxFF30_1512_SoftOverride0_WIDTH 1
-#define FCRxFF30_1512_SoftOverride0_MASK 0x80000000
-
-/// FCRxFF30_1512
-typedef union {
- struct { ///<
- UINT32 Reserved_30_0:31; ///<
- UINT32 SoftOverride0:1 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} FCRxFF30_1512_STRUCT;
-
-// **** SMUx1B Register Definition ****
-// Address
-#define SMUx1B_ADDRESS 0x1b
-
-// Type
-#define SMUx1B_TYPE TYPE_SMU
-// Field Data
-#define SMUx1B_LclkDpSlpDiv_OFFSET 0
-#define SMUx1B_LclkDpSlpDiv_WIDTH 3
-#define SMUx1B_LclkDpSlpDiv_MASK 0x7
-#define SMUx1B_RampDis_OFFSET 3
-#define SMUx1B_RampDis_WIDTH 1
-#define SMUx1B_RampDis_MASK 0x8
-#define SMUx1B_Reserved_7_4_OFFSET 4
-#define SMUx1B_Reserved_7_4_WIDTH 4
-#define SMUx1B_Reserved_7_4_MASK 0xf0
-#define SMUx1B_LclkDpSlpMask_OFFSET 8
-#define SMUx1B_LclkDpSlpMask_WIDTH 8
-#define SMUx1B_LclkDpSlpMask_MASK 0xff00
-
-/// SMUx1B
-typedef union {
- struct { ///<
- UINT32 LclkDpSlpDiv:3 ; ///<
- UINT32 RampDis:1 ; ///<
- UINT32 Reserved_7_4:4 ; ///<
- UINT32 LclkDpSlpMask:8 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx1B_STRUCT;
-
-// **** SMUx1D Register Definition ****
-// Address
-#define SMUx1D_ADDRESS 0x1d
-
-// Type
-#define SMUx1D_TYPE TYPE_SMU
-// Field Data
-#define SMUx1D_LclkDpSlpHyst_OFFSET 0
-#define SMUx1D_LclkDpSlpHyst_WIDTH 12
-#define SMUx1D_LclkDpSlpHyst_MASK 0xfff
-#define SMUx1D_LclkDpSlpEn_OFFSET 12
-#define SMUx1D_LclkDpSlpEn_WIDTH 1
-#define SMUx1D_LclkDpSlpEn_MASK 0x1000
-#define SMUx1D_Reserved_15_13_OFFSET 13
-#define SMUx1D_Reserved_15_13_WIDTH 3
-#define SMUx1D_Reserved_15_13_MASK 0xe000
-
-/// SMUx1D
-typedef union {
- struct { ///<
- UINT32 LclkDpSlpHyst:12; ///<
- UINT32 LclkDpSlpEn:1 ; ///<
- UINT32 Reserved_15_13:3 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx1D_STRUCT;
-
-// **** SMUx6F Register Definition ****
-// Address
-#define SMUx6F_ADDRESS 0x6f
-
-
-// **** SMUx71 Register Definition ****
-// Address
-#define SMUx71_ADDRESS 0x71
-
-
-// **** SMUx73 Register Definition ****
-// Address
-#define SMUx73_ADDRESS 0x73
-
-// Type
-#define SMUx73_TYPE TYPE_SMU
-// Field Data
-#define SMUx73_DisLclkGating_OFFSET 0
-#define SMUx73_DisLclkGating_WIDTH 1
-#define SMUx73_DisLclkGating_MASK 0x1
-#define SMUx73_DisSclkGating_OFFSET 1
-#define SMUx73_DisSclkGating_WIDTH 1
-#define SMUx73_DisSclkGating_MASK 0x2
-#define SMUx73_Reserved_15_2_OFFSET 2
-#define SMUx73_Reserved_15_2_WIDTH 14
-#define SMUx73_Reserved_15_2_MASK 0xfffc
-
-/// SMUx73
-typedef union {
- struct { ///<
- UINT32 DisLclkGating:1 ; ///<
- UINT32 DisSclkGating:1 ; ///<
- UINT32 Reserved_15_2:14; ///<
- } Field; ///<
- UINT32 Value; ///<
-} SMUx73_STRUCT;
-
-// **** D0F0x98_x49 Register Definition ****
-// Address
-#define D0F0x98_x49_ADDRESS 0x49
-
-// Type
-#define D0F0x98_x49_TYPE TYPE_D0F0x98
-// Field Data
-#define D0F0x98_x49_Reserved_23_0_OFFSET 0
-#define D0F0x98_x49_Reserved_23_0_WIDTH 24
-#define D0F0x98_x49_Reserved_23_0_MASK 0xffffff
-#define D0F0x98_x49_SoftOverrideClk6_OFFSET 24
-#define D0F0x98_x49_SoftOverrideClk6_WIDTH 1
-#define D0F0x98_x49_SoftOverrideClk6_MASK 0x1000000
-#define D0F0x98_x49_SoftOverrideClk5_OFFSET 25
-#define D0F0x98_x49_SoftOverrideClk5_WIDTH 1
-#define D0F0x98_x49_SoftOverrideClk5_MASK 0x2000000
-#define D0F0x98_x49_SoftOverrideClk4_OFFSET 26
-#define D0F0x98_x49_SoftOverrideClk4_WIDTH 1
-#define D0F0x98_x49_SoftOverrideClk4_MASK 0x4000000
-#define D0F0x98_x49_SoftOverrideClk3_OFFSET 27
-#define D0F0x98_x49_SoftOverrideClk3_WIDTH 1
-#define D0F0x98_x49_SoftOverrideClk3_MASK 0x8000000
-#define D0F0x98_x49_SoftOverrideClk2_OFFSET 28
-#define D0F0x98_x49_SoftOverrideClk2_WIDTH 1
-#define D0F0x98_x49_SoftOverrideClk2_MASK 0x10000000
-#define D0F0x98_x49_SoftOverrideClk1_OFFSET 29
-#define D0F0x98_x49_SoftOverrideClk1_WIDTH 1
-#define D0F0x98_x49_SoftOverrideClk1_MASK 0x20000000
-#define D0F0x98_x49_SoftOverrideClk0_OFFSET 30
-#define D0F0x98_x49_SoftOverrideClk0_WIDTH 1
-#define D0F0x98_x49_SoftOverrideClk0_MASK 0x40000000
-#define D0F0x98_x49_Reserved_31_31_OFFSET 31
-#define D0F0x98_x49_Reserved_31_31_WIDTH 1
-#define D0F0x98_x49_Reserved_31_31_MASK 0x80000000
-
-/// D0F0x98_x49
-typedef union {
- struct { ///<
- UINT32 Reserved_23_0:24; ///<
- UINT32 SoftOverrideClk6:1 ; ///<
- UINT32 SoftOverrideClk5:1 ; ///<
- UINT32 SoftOverrideClk4:1 ; ///<
- UINT32 SoftOverrideClk3:1 ; ///<
- UINT32 SoftOverrideClk2:1 ; ///<
- UINT32 SoftOverrideClk1:1 ; ///<
- UINT32 SoftOverrideClk0:1 ; ///<
- UINT32 Reserved_31_31:1 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x98_x49_STRUCT;
-
-// **** D0F0x98_x4A Register Definition ****
-// Address
-#define D0F0x98_x4A_ADDRESS 0x4a
-
-// Type
-#define D0F0x98_x4A_TYPE TYPE_D0F0x98
-// Field Data
-#define D0F0x98_x4A_Reserved_23_0_OFFSET 0
-#define D0F0x98_x4A_Reserved_23_0_WIDTH 24
-#define D0F0x98_x4A_Reserved_23_0_MASK 0xffffff
-#define D0F0x98_x4A_SoftOverrideClk6_OFFSET 24
-#define D0F0x98_x4A_SoftOverrideClk6_WIDTH 1
-#define D0F0x98_x4A_SoftOverrideClk6_MASK 0x1000000
-#define D0F0x98_x4A_SoftOverrideClk5_OFFSET 25
-#define D0F0x98_x4A_SoftOverrideClk5_WIDTH 1
-#define D0F0x98_x4A_SoftOverrideClk5_MASK 0x2000000
-#define D0F0x98_x4A_SoftOverrideClk4_OFFSET 26
-#define D0F0x98_x4A_SoftOverrideClk4_WIDTH 1
-#define D0F0x98_x4A_SoftOverrideClk4_MASK 0x4000000
-#define D0F0x98_x4A_SoftOverrideClk3_OFFSET 27
-#define D0F0x98_x4A_SoftOverrideClk3_WIDTH 1
-#define D0F0x98_x4A_SoftOverrideClk3_MASK 0x8000000
-#define D0F0x98_x4A_SoftOverrideClk2_OFFSET 28
-#define D0F0x98_x4A_SoftOverrideClk2_WIDTH 1
-#define D0F0x98_x4A_SoftOverrideClk2_MASK 0x10000000
-#define D0F0x98_x4A_SoftOverrideClk1_OFFSET 29
-#define D0F0x98_x4A_SoftOverrideClk1_WIDTH 1
-#define D0F0x98_x4A_SoftOverrideClk1_MASK 0x20000000
-#define D0F0x98_x4A_SoftOverrideClk0_OFFSET 30
-#define D0F0x98_x4A_SoftOverrideClk0_WIDTH 1
-#define D0F0x98_x4A_SoftOverrideClk0_MASK 0x40000000
-#define D0F0x98_x4A_Reserved_31_31_OFFSET 31
-#define D0F0x98_x4A_Reserved_31_31_WIDTH 1
-#define D0F0x98_x4A_Reserved_31_31_MASK 0x80000000
-
-/// D0F0x98_x4A
-typedef union {
- struct { ///<
- UINT32 Reserved_23_0:24; ///<
- UINT32 SoftOverrideClk6:1 ; ///<
- UINT32 SoftOverrideClk5:1 ; ///<
- UINT32 SoftOverrideClk4:1 ; ///<
- UINT32 SoftOverrideClk3:1 ; ///<
- UINT32 SoftOverrideClk2:1 ; ///<
- UINT32 SoftOverrideClk1:1 ; ///<
- UINT32 SoftOverrideClk0:1 ; ///<
- UINT32 Reserved_31_31:1 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x98_x4A_STRUCT;
-
-// **** D0F0x98_x4B Register Definition ****
-// Address
-#define D0F0x98_x4B_ADDRESS 0x4b
-
-// Type
-#define D0F0x98_x4B_TYPE TYPE_D0F0x98
-// Field Data
-#define D0F0x98_x4B_Reserved_29_0_OFFSET 0
-#define D0F0x98_x4B_Reserved_29_0_WIDTH 30
-#define D0F0x98_x4B_Reserved_29_0_MASK 0x3fffffff
-#define D0F0x98_x4B_SoftOverrideClk_OFFSET 30
-#define D0F0x98_x4B_SoftOverrideClk_WIDTH 1
-#define D0F0x98_x4B_SoftOverrideClk_MASK 0x40000000
-#define D0F0x98_x4B_Reserved_31_31_OFFSET 31
-#define D0F0x98_x4B_Reserved_31_31_WIDTH 1
-#define D0F0x98_x4B_Reserved_31_31_MASK 0x80000000
-
-/// D0F0x98_x4B
-typedef union {
- struct { ///<
- UINT32 Reserved_29_0:30; ///<
- UINT32 SoftOverrideClk:1 ; ///<
- UINT32 Reserved_31_31:1 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x98_x4B_STRUCT;
-
-// **** D0F0x64_x22 Register Definition ****
-// Address
-#define D0F0x64_x22_ADDRESS 0x22
-
-// Type
-#define D0F0x64_x22_TYPE TYPE_D0F0x64
-// Field Data
-#define D0F0x64_x22_Reserved_25_0_OFFSET 0
-#define D0F0x64_x22_Reserved_25_0_WIDTH 26
-#define D0F0x64_x22_Reserved_25_0_MASK 0x3ffffff
-#define D0F0x64_x22_SoftOverrideClk4_OFFSET 26
-#define D0F0x64_x22_SoftOverrideClk4_WIDTH 1
-#define D0F0x64_x22_SoftOverrideClk4_MASK 0x4000000
-#define D0F0x64_x22_SoftOverrideClk3_OFFSET 27
-#define D0F0x64_x22_SoftOverrideClk3_WIDTH 1
-#define D0F0x64_x22_SoftOverrideClk3_MASK 0x8000000
-#define D0F0x64_x22_SoftOverrideClk2_OFFSET 28
-#define D0F0x64_x22_SoftOverrideClk2_WIDTH 1
-#define D0F0x64_x22_SoftOverrideClk2_MASK 0x10000000
-#define D0F0x64_x22_SoftOverrideClk1_OFFSET 29
-#define D0F0x64_x22_SoftOverrideClk1_WIDTH 1
-#define D0F0x64_x22_SoftOverrideClk1_MASK 0x20000000
-#define D0F0x64_x22_SoftOverrideClk0_OFFSET 30
-#define D0F0x64_x22_SoftOverrideClk0_WIDTH 1
-#define D0F0x64_x22_SoftOverrideClk0_MASK 0x40000000
-#define D0F0x64_x22_Reserved_31_31_OFFSET 31
-#define D0F0x64_x22_Reserved_31_31_WIDTH 1
-#define D0F0x64_x22_Reserved_31_31_MASK 0x80000000
-
-/// D0F0x64_x22
-typedef union {
- struct { ///<
- UINT32 Reserved_25_0:26; ///<
- UINT32 SoftOverrideClk4:1 ; ///<
- UINT32 SoftOverrideClk3:1 ; ///<
- UINT32 SoftOverrideClk2:1 ; ///<
- UINT32 SoftOverrideClk1:1 ; ///<
- UINT32 SoftOverrideClk0:1 ; ///<
- UINT32 Reserved_31_31:1 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x64_x22_STRUCT;
-
-// **** D0F0x64_x23 Register Definition ****
-// Address
-#define D0F0x64_x23_ADDRESS 0x23
-
-// Type
-#define D0F0x64_x23_TYPE TYPE_D0F0x64
-// Field Data
-#define D0F0x64_x23_Reserved_26_0_OFFSET 0
-#define D0F0x64_x23_Reserved_26_0_WIDTH 27
-#define D0F0x64_x23_Reserved_26_0_MASK 0x7ffffff
-#define D0F0x64_x23_SoftOverrideClk3_OFFSET 27
-#define D0F0x64_x23_SoftOverrideClk3_WIDTH 1
-#define D0F0x64_x23_SoftOverrideClk3_MASK 0x8000000
-#define D0F0x64_x23_SoftOverrideClk2_OFFSET 28
-#define D0F0x64_x23_SoftOverrideClk2_WIDTH 1
-#define D0F0x64_x23_SoftOverrideClk2_MASK 0x10000000
-#define D0F0x64_x23_SoftOverrideClk1_OFFSET 29
-#define D0F0x64_x23_SoftOverrideClk1_WIDTH 1
-#define D0F0x64_x23_SoftOverrideClk1_MASK 0x20000000
-#define D0F0x64_x23_SoftOverrideClk0_OFFSET 30
-#define D0F0x64_x23_SoftOverrideClk0_WIDTH 1
-#define D0F0x64_x23_SoftOverrideClk0_MASK 0x40000000
-#define D0F0x64_x23_Reserved_31_31_OFFSET 31
-#define D0F0x64_x23_Reserved_31_31_WIDTH 1
-#define D0F0x64_x23_Reserved_31_31_MASK 0x80000000
-
-/// D0F0x64_x23
-typedef union {
- struct { ///<
- UINT32 Reserved_26_0:27; ///<
- UINT32 SoftOverrideClk3:1 ; ///<
- UINT32 SoftOverrideClk2:1 ; ///<
- UINT32 SoftOverrideClk1:1 ; ///<
- UINT32 SoftOverrideClk0:1 ; ///<
- UINT32 Reserved_31_31:1 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x64_x23_STRUCT;
-
-// **** D0F0x64_x24 Register Definition ****
-// Address
-#define D0F0x64_x24_ADDRESS 0x24
-
-// Type
-#define D0F0x64_x24_TYPE TYPE_D0F0x64
-// Field Data
-#define D0F0x64_x24_Reserved_28_0_OFFSET 0
-#define D0F0x64_x24_Reserved_28_0_WIDTH 29
-#define D0F0x64_x24_Reserved_28_0_MASK 0x1fffffff
-#define D0F0x64_x24_SoftOverrideClk1_OFFSET 29
-#define D0F0x64_x24_SoftOverrideClk1_WIDTH 1
-#define D0F0x64_x24_SoftOverrideClk1_MASK 0x20000000
-#define D0F0x64_x24_SoftOverrideClk0_OFFSET 30
-#define D0F0x64_x24_SoftOverrideClk0_WIDTH 1
-#define D0F0x64_x24_SoftOverrideClk0_MASK 0x40000000
-#define D0F0x64_x24_Reserved_31_31_OFFSET 31
-#define D0F0x64_x24_Reserved_31_31_WIDTH 1
-#define D0F0x64_x24_Reserved_31_31_MASK 0x80000000
-
-/// D0F0x64_x24
-typedef union {
- struct { ///<
- UINT32 Reserved_28_0:29; ///<
- UINT32 SoftOverrideClk1:1 ; ///<
- UINT32 SoftOverrideClk0:1 ; ///<
- UINT32 Reserved_31_31:1 ; ///<
- } Field; ///<
- UINT32 Value; ///<
-} D0F0x64_x24_STRUCT;
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Gfx/Family/0x14/F14GfxServices.c b/src/vendorcode/amd/agesa/Proc/GNB/Gfx/Family/0x14/F14GfxServices.c
deleted file mode 100644
index 139d47c..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Gfx/Family/0x14/F14GfxServices.c
+++ /dev/null
@@ -1,524 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Graphics Controller family specific service procedure
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "GeneralServices.h"
-#include "Gnb.h"
-#include "GnbPcie.h"
-#include "GnbGfx.h"
-#include "GnbRegistersON.h"
-#include "GfxIntegratedInfoTableInit.h"
-#include "GfxRegisterAcc.h"
-#include "GfxLib.h"
-#include GNB_MODULE_DEFINITIONS (GnbGfxInitLibV1)
-#include "GnbRegistersON.h"
-#include "F14NbPowerGate.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_GFX_FAMILY_0X14_F14GFXSERVICES_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-UINT8 NumberOfChannels = 1;
-
-UINT8 DdiLaneConfigArray [][4] = {
- {8, 11, 0, 0},
- {12, 15, 1, 1},
- {11, 8, 0, 0},
- {15, 12, 1, 1},
- {16, 19, 6, 6},
- {19, 16, 6, 6}
-};
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Initialize display path for given engine
- *
- *
- *
- * @param[in] Engine Engine configuration info
- * @param[out] DisplayPathList Display path list
- * @param[in] Gfx Pointer to global GFX configuration
- */
-
-AGESA_STATUS
-GfxFmMapEngineToDisplayPath (
- IN PCIe_ENGINE_CONFIG *Engine,
- OUT EXT_DISPLAY_PATH *DisplayPathList,
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- AGESA_STATUS Status;
- UINT8 PrimaryDisplayPathId;
- UINT8 SecondaryDisplayPathId;
- UINTN DisplayPathIndex;
- PrimaryDisplayPathId = 0xff;
- SecondaryDisplayPathId = 0xff;
- for (DisplayPathIndex = 0; DisplayPathIndex < (sizeof (DdiLaneConfigArray) / 4); DisplayPathIndex++) {
- if (DdiLaneConfigArray[DisplayPathIndex][0] == Engine->EngineData.StartLane &&
- DdiLaneConfigArray[DisplayPathIndex][1] == Engine->EngineData.EndLane) {
- PrimaryDisplayPathId = DdiLaneConfigArray[DisplayPathIndex][2];
- SecondaryDisplayPathId = DdiLaneConfigArray[DisplayPathIndex][3];
- break;
- }
- }
- if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeDualLinkDVI ||
- (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeLvds && PrimaryDisplayPathId != 0)) {
- // Display config invalid for ON
- PrimaryDisplayPathId = 0xff;
- }
- if (PrimaryDisplayPathId != 0xff) {
- ASSERT (Engine->Type.Ddi.DdiData.AuxIndex <= Aux3);
- IDS_HDT_CONSOLE (GFX_MISC, " Allocate Display Connector at Primary sPath[%d]\n", PrimaryDisplayPathId);
- Engine->InitStatus |= INIT_STATUS_DDI_ACTIVE;
- if (Engine->Type.Ddi.DdiData.AuxIndex == Aux3) {
- Engine->Type.Ddi.DdiData.AuxIndex = 7;
- }
- GfxIntegratedCopyDisplayInfo (
- Engine,
- &DisplayPathList[PrimaryDisplayPathId],
- (PrimaryDisplayPathId != SecondaryDisplayPathId) ? &DisplayPathList[SecondaryDisplayPathId] : NULL,
- Gfx
- );
- if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeSingleLinkDviI) {
- LibAmdMemCopy (&DisplayPathList[6], &DisplayPathList[PrimaryDisplayPathId], sizeof (EXT_DISPLAY_PATH), GnbLibGetHeader (Gfx));
- DisplayPathList[6].usDeviceACPIEnum = 0x100;
- DisplayPathList[6].usDeviceTag = ATOM_DEVICE_CRT1_SUPPORT;
- }
- Status = AGESA_SUCCESS;
- } else {
- IDS_HDT_CONSOLE (GFX_MISC, " ERROR!!! Map DDI lanes %d - %d to display path failed\n",
- Engine->EngineData.StartLane,
- Engine->EngineData.EndLane
- );
- PutEventLog (
- AGESA_ERROR,
- GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION,
- Engine->EngineData.StartLane,
- Engine->EngineData.EndLane,
- 0,
- 0,
- GnbLibGetHeader (Gfx)
- );
- Status = AGESA_ERROR;
- }
- return Status;
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Family specific integrated info table init
- *
- *
- * @param[in] IntegratedInfoTable Integrated info table pointer
- * @param[in] Gfx Gfx configuration info
- */
-
-VOID
-GfxFmIntegratedInfoTableInit (
- IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable,
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- IntegratedInfoTable->ulDDR_DLL_PowerUpTime = 2380;
- IntegratedInfoTable->ulDDR_PLL_PowerUpTime = 30000;
- IntegratedInfoTable->ulGMCRestoreResetTime = F14NbPowerGateGmcRestoreLatency (GnbLibGetHeader (Gfx));
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Family specific address swizzle settings.
- *
- *
- * @param[in] Gfx Gfx configuration info
- */
-
-VOID
-GfxFmGmcAddressSwizzel (
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- GMMx2864_STRUCT GMMx2864;
- GMMx2864.Value = GmmRegisterRead (GMMx2864_ADDRESS, Gfx);
- if (GMMx2864.Value == 0) {
- GMMx2864.Value = 0x32100876;
-
- GmmRegisterWrite (
- GMMx2864_ADDRESS,
- GMMx2864.Value,
- TRUE,
- Gfx
- );
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Calculate COF for DFS out of Main PLL
- *
- *
- *
- * @param[in] Did Did
- * @param[in] StdHeader Standard Configuration Header
- * @retval COF in 10khz
- */
-
-AGESA_STATUS
-GfxFmCalculateClock (
- IN UINT8 Did,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 MainPllFreq10kHz;
- MainPllFreq10kHz = GfxLibGetMainPllFreq (StdHeader) * 100;
- return GfxLibCalculateClk (Did, MainPllFreq10kHz);
-}
-/*----------------------------------------------------------------------------------------
- * GMC Disable Clock Gating
- *----------------------------------------------------------------------------------------
- */
-
-GMM_REG_ENTRY GmcDisableClockGating[] = {
- { 0x20C0, 0x00000C80 },
- { 0x20B8, 0x00000400 },
- { 0x20BC, 0x00000400 },
- { 0x2640, 0x00000400 },
- { 0x263C, 0x00000400 },
- { 0x2638, 0x00000400 },
- { 0x15C0, 0x00081401 }
-};
-
-TABLE_INDIRECT_PTR GmcDisableClockGatingPtr = {
- sizeof (GmcDisableClockGating) / sizeof (GMM_REG_ENTRY),
- GmcDisableClockGating
-};
-
-/*----------------------------------------------------------------------------------------
- * GMC Enable Clock Gating
- *----------------------------------------------------------------------------------------
- */
-GMM_REG_ENTRY GmcEnableClockGating[] = {
- { 0x20C0, 0x00040C80 },
- { 0x20B8, 0x00040400 },
- { 0x20BC, 0x00040400 },
- { 0x2640, 0x00040400 },
- { 0x263C, 0x00040400 },
- { 0x2638, 0x00040400 },
- { 0x15C0, 0x000C1401 }
-};
-
-
-TABLE_INDIRECT_PTR GmcEnableClockGatingPtr = {
- sizeof (GmcEnableClockGating) / sizeof (GMM_REG_ENTRY),
- GmcEnableClockGating
-};
-
-/*----------------------------------------------------------------------------------------
- * GMC Performance Tuning
- *----------------------------------------------------------------------------------------
- */
-GMM_REG_ENTRY GmcPerformanceTuningTable [] = {
- { GMMx27CC_ADDRESS, 0x00032005 },
- { GMMx27DC_ADDRESS, 0x00734847 },
- { GMMx27D0_ADDRESS, 0x00012008 },
- { GMMx27E0_ADDRESS, 0x00003D3C },
- { GMMx2784_ADDRESS, 0x00000007 },
- { GMMx21C8_ADDRESS, 0x0000A1F1 },
- { GMMx217C_ADDRESS, 0x0000A1F1 },
- { GMMx2188_ADDRESS, 0x000221b1 },
- { GMMx2814_ADDRESS, 0x00000200 },
- { GMMx201C_ADDRESS, 0x03330003 },
- { GMMx2020_ADDRESS, 0x70760007 },
- { GMMx2018_ADDRESS, 0x00000050 },
- { GMMx2014_ADDRESS, 0x00005500 },
- { GMMx2610_ADDRESS, 0x44111222 },
- { GMMx2618_ADDRESS, 0x00006664 },
- { GMMx2614_ADDRESS, 0x11333111 },
- { GMMx261C_ADDRESS, 0x00000003 },
- { GMMx279C_ADDRESS, 0xfcfcfdfc },
- { GMMx27A0_ADDRESS, 0xfcfcfdfc }
-};
-
-TABLE_INDIRECT_PTR GmcPerformanceTuningTablePtr = {
- sizeof (GmcPerformanceTuningTable) / sizeof (GMM_REG_ENTRY),
- GmcPerformanceTuningTable
-};
-
-/*----------------------------------------------------------------------------------------
- * GMC Misc init table
- *----------------------------------------------------------------------------------------
- */
-GMM_REG_ENTRY GmcMiscInitTable [] = {
- { GMMx25C8_ADDRESS, 0x007F605F },
- { GMMx25CC_ADDRESS, 0x00007F7E },
- { 0x20B4, 0x00000000 },
- { GMMx28C8_ADDRESS, 0x00000003 },
- { GMMx202C_ADDRESS, 0x0003FFFF }
-};
-
-TABLE_INDIRECT_PTR GmcMiscInitTablePtr = {
- sizeof (GmcMiscInitTable) / sizeof (GMM_REG_ENTRY),
- GmcMiscInitTable
-};
-
-/*----------------------------------------------------------------------------------------
- * GMC Remove blackout
- *----------------------------------------------------------------------------------------
- */
-GMM_REG_ENTRY GmcRemoveBlackoutTable [] = {
- { GMMx25C0_ADDRESS, 0x00000000 },
- { 0x20EC, 0x000001FC },
- { 0x20D4, 0x00000016 }
-};
-
-TABLE_INDIRECT_PTR GmcRemoveBlackoutTablePtr = {
- sizeof (GmcRemoveBlackoutTable) / sizeof (GMM_REG_ENTRY),
- GmcRemoveBlackoutTable
-};
-
-/*----------------------------------------------------------------------------------------
- * GMC Register Engine Init Table
- *----------------------------------------------------------------------------------------
- */
-GMM_REG_ENTRY GmcRegisterEngineInitTable [] = {
- { GMMx2B8C_ADDRESS, 0x00000000 },
- { GMMx2B90_ADDRESS, 0x001e0a07 },
- { GMMx2B8C_ADDRESS, 0x00000020 },
- { GMMx2B90_ADDRESS, 0x00050500 },
- { GMMx2B8C_ADDRESS, 0x00000027 },
- { GMMx2B90_ADDRESS, 0x0001050c },
- { GMMx2B8C_ADDRESS, 0x0000002a },
- { GMMx2B90_ADDRESS, 0x0001051c },
- { GMMx2B8C_ADDRESS, 0x0000002d },
- { GMMx2B90_ADDRESS, 0x00030534 },
- { GMMx2B8C_ADDRESS, 0x00000032 },
- { GMMx2B90_ADDRESS, 0x0001053e },
- { GMMx2B8C_ADDRESS, 0x00000035 },
- { GMMx2B90_ADDRESS, 0x00010546 },
- { GMMx2B8C_ADDRESS, 0x00000038 },
- { GMMx2B90_ADDRESS, 0x0002054e },
- { GMMx2B8C_ADDRESS, 0x0000003c },
- { GMMx2B90_ADDRESS, 0x00010557 },
- { GMMx2B8C_ADDRESS, 0x0000003f },
- { GMMx2B90_ADDRESS, 0x0001055f },
- { GMMx2B8C_ADDRESS, 0x00000042 },
- { GMMx2B90_ADDRESS, 0x00010567 },
- { GMMx2B8C_ADDRESS, 0x00000045 },
- { GMMx2B90_ADDRESS, 0x0001056f },
- { GMMx2B8C_ADDRESS, 0x00000048 },
- { GMMx2B90_ADDRESS, 0x00050572 },
- { GMMx2B8C_ADDRESS, 0x0000004f },
- { GMMx2B90_ADDRESS, 0x00000800 },
- { GMMx2B8C_ADDRESS, 0x00000051 },
- { GMMx2B90_ADDRESS, 0x00260801 },
- { GMMx2B8C_ADDRESS, 0x00000079 },
- { GMMx2B90_ADDRESS, 0x004b082d },
- { GMMx2B8C_ADDRESS, 0x000000c6 },
- { GMMx2B90_ADDRESS, 0x0013088d },
- { GMMx2B8C_ADDRESS, 0x000000db },
- { GMMx2B90_ADDRESS, 0x100008a1 },
- { GMMx2B90_ADDRESS, 0x00000040 },
- { GMMx2B90_ADDRESS, 0x00000040 },
- { GMMx2B8C_ADDRESS, 0x000000df },
- { GMMx2B90_ADDRESS, 0x000008a2 },
- { GMMx2B8C_ADDRESS, 0x000000e1 },
- { GMMx2B90_ADDRESS, 0x0001094d },
- { GMMx2B8C_ADDRESS, 0x000000e4 },
- { GMMx2B90_ADDRESS, 0x00000952 },
- { GMMx2B8C_ADDRESS, 0x000000e6 },
- { GMMx2B90_ADDRESS, 0x00010954 },
- { GMMx2B8C_ADDRESS, 0x000000e9 },
- { GMMx2B90_ADDRESS, 0x0009095a },
- { GMMx2B8C_ADDRESS, 0x000000f4 },
- { GMMx2B90_ADDRESS, 0x0022096e },
- { GMMx2B8C_ADDRESS, 0x00000118 },
- { GMMx2B90_ADDRESS, 0x000e0997 },
- { GMMx2B8C_ADDRESS, 0x00000128 },
- { GMMx2B90_ADDRESS, 0x100009a6 },
- { GMMx2B90_ADDRESS, 0x00000040 },
- { GMMx2B90_ADDRESS, 0x00000040 },
- { GMMx2B8C_ADDRESS, 0x0000012c },
- { GMMx2B90_ADDRESS, 0x000009a7 },
- { GMMx2B8C_ADDRESS, 0x0000012e },
- { GMMx2B90_ADDRESS, 0x002e09d7 },
- { GMMx2B8C_ADDRESS, 0x0000015e },
- { GMMx2B90_ADDRESS, 0x00170a26 },
- { 0x2B94, 0x5d976000 },
- { 0x2B98, 0x410af020 }
-};
-
-TABLE_INDIRECT_PTR GmcRegisterEngineInitTablePtr = {
- sizeof (GmcRegisterEngineInitTable) / sizeof (GMM_REG_ENTRY),
- GmcRegisterEngineInitTable
-};
-
-/*----------------------------------------------------------------------------------------
- * GMC Address Translation Table
- *----------------------------------------------------------------------------------------
- */
-// Entries for Bank 1 will be fused out
-
-REGISTER_COPY_ENTRY CnbToGncRegisterCopyTable [] = {
- {
- MAKE_SBDFO (0, 0, 0x18, 2, D18F2x40_ADDRESS),
- GMMx281C_ADDRESS,
- 0,
- 31,
- 0,
- 31
- },
- {
- MAKE_SBDFO (0, 0, 0x18, 2, D18F2x44_ADDRESS),
- GMMx2824_ADDRESS,
- 0,
- 31,
- 0,
- 31
- },
- {
- MAKE_SBDFO (0, 0, 0x18, 2, D18F2x48_ADDRESS),
- GMMx282C_ADDRESS,
- 0,
- 31,
- 0,
- 31
- },
- {
- MAKE_SBDFO (0, 0, 0x18, 2, D18F2x4C_ADDRESS),
- GMMx2834_ADDRESS,
- 0,
- 31,
- 0,
- 31
- },
- {
- MAKE_SBDFO (0, 0, 0x18, 2, D18F2x60_ADDRESS),
- GMMx283C_ADDRESS,
- 0,
- 31,
- 0,
- 31
- },
- {
- MAKE_SBDFO (0, 0, 0x18, 2, D18F2x64_ADDRESS),
- GMMx2840_ADDRESS,
- 0,
- 31,
- 0,
- 31
- },
- {
- MAKE_SBDFO (0, 0, 0x18, 2, D18F2x80_ADDRESS),
- GMMx284C_ADDRESS,
- D18F2x80_Dimm0AddrMap_OFFSET,
- D18F2x80_Dimm0AddrMap_WIDTH + D18F2x80_Dimm1AddrMap_WIDTH,
- GMMx284C_Dimm0AddrMap_OFFSET,
- GMMx284C_Dimm0AddrMap_WIDTH + GMMx284C_Dimm1AddrMap_WIDTH
- },
- {
- MAKE_SBDFO (0, 0, 0x18, 2, D18F2x094_ADDRESS),
- GMMx284C_ADDRESS,
- D18F2x094_BankSwizzleMode_OFFSET,
- D18F2x094_BankSwizzleMode_WIDTH,
- GMMx284C_BankSwizzleMode_OFFSET,
- GMMx284C_BankSwizzleMode_WIDTH
- },
- {
- MAKE_SBDFO (0, 0, 0x18, 2, D18F2xA8_ADDRESS),
- GMMx284C_ADDRESS,
- D18F2xA8_BankSwap_OFFSET,
- D18F2xA8_BankSwap_WIDTH,
- GMMx284C_BankSwap_OFFSET,
- GMMx284C_BankSwap_WIDTH
- },
- {
- MAKE_SBDFO (0, 0, 0x18, 2, D18F2x114_ADDRESS),
- GMMx2858_ADDRESS,
- 0,
- 31,
- 0,
- 31
- },
- {
- MAKE_SBDFO (0, 0, 0x18, 1, D18F1xF0_ADDRESS),
- GMMx285C_ADDRESS,
- 0,
- 31,
- 0,
- 31
- }
-};
-
-
-TABLE_INDIRECT_PTR CnbToGncRegisterCopyTablePtr = {
- sizeof (CnbToGncRegisterCopyTable) / sizeof (REGISTER_COPY_ENTRY),
- CnbToGncRegisterCopyTable
-};
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Gfx/Family/GfxFamilyServices.h b/src/vendorcode/amd/agesa/Proc/GNB/Gfx/Family/GfxFamilyServices.h
deleted file mode 100644
index 130f5fc..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Gfx/Family/GfxFamilyServices.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Family specific service routine
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _GFXFAMILYSERVICES_H_
-#define _GFXFAMILYSERVICES_H_
-
-VOID
-GfxFmIntegratedInfoTableInit (
- IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable,
- IN GFX_PLATFORM_CONFIG *Gfx
- );
-
-VOID
-GfxFmGmcAddressSwizzel (
- IN GFX_PLATFORM_CONFIG *Gfx
- );
-
-#endif
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxConfigData.c b/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxConfigData.c
deleted file mode 100644
index 415dfb7..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxConfigData.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Initialize GFX configuration data structure.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 40151 $ @e \$Date: 2010-10-20 06:38:17 +0800 (Wed, 20 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "heapManager.h"
-#include "Gnb.h"
-#include "GnbGfx.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include "GfxStrapsInit.h"
-#include "OptionGnb.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_GFX_GFXCONFIGDATA_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-extern GNB_BUILD_OPTIONS GnbBuildOptions;
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Enable GMM Access
- *
- *
- *
- * @param[in,out] Gfx Pointer to GFX configuration
- * @retval AGESA_STATUS
- */
-
-AGESA_STATUS
-GfxEnableGmmAccess (
- IN OUT GFX_PLATFORM_CONFIG *Gfx
- )
-{
- UINT32 Value;
-
- if (!GnbLibPciIsDevicePresent (Gfx->GfxPciAddress.AddressValue, GnbLibGetHeader (Gfx))) {
- IDS_ERROR_TRAP;
- return AGESA_ERROR;
- }
-
- // Check if base address for GMM allocated
- GnbLibPciRead (Gfx->GfxPciAddress.AddressValue | 0x18, AccessWidth32, &Gfx->GmmBase, GnbLibGetHeader (Gfx));
- if (Gfx->GmmBase == 0) {
- IDS_ERROR_TRAP;
- return AGESA_ERROR;
- }
- // Check if base address for FB allocated
- GnbLibPciRead (Gfx->GfxPciAddress.AddressValue | 0x10, AccessWidth32, &Value, GnbLibGetHeader (Gfx));
- if ((Value & 0xfffffff0) == 0) {
- IDS_ERROR_TRAP;
- return AGESA_ERROR;
- }
- //Push CPU MMIO pci config to S3 script
- GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 0x18, 1, 0), 0xBC, 0x80, AccessS3SaveWidth32, GnbLibGetHeader (Gfx));
- // Turn on memory decoding on APC to enable access to GMM register space
- if (Gfx->GfxControllerMode == GfxControllerLegacyBridgeMode) {
- GnbLibPciRMW (MAKE_SBDFO (0, 0, 1, 0, 0x4), AccessWidth32, 0xffffffff, BIT1 | BIT2, GnbLibGetHeader (Gfx));
- //Push APC pci config to S3 script
- GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 1, 0, 0), 0x2C, 0x18, AccessS3SaveWidth32, GnbLibGetHeader (Gfx));
- GnbLibS3SaveConfigSpace (MAKE_SBDFO (0, 0, 1, 0, 0), 0x4, 0x4, AccessS3SaveWidth16, GnbLibGetHeader (Gfx));
- }
- // Turn on memory decoding on GFX to enable access to GMM register space
- GnbLibPciRMW (Gfx->GfxPciAddress.AddressValue | 0x4, AccessWidth32, 0xffffffff, BIT1 | BIT2, GnbLibGetHeader (Gfx));
- //Push iGPU pci config to S3 script
- GnbLibS3SaveConfigSpace (Gfx->GfxPciAddress.AddressValue, 0x24, 0x10, AccessS3SaveWidth32, GnbLibGetHeader (Gfx));
- GnbLibS3SaveConfigSpace (Gfx->GfxPciAddress.AddressValue, 0x04, 0x04, AccessS3SaveWidth16, GnbLibGetHeader (Gfx));
- return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxConfigData.h b/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxConfigData.h
deleted file mode 100644
index 024983f..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxConfigData.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Initialize GFX configuration data structure.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _GFXCONFIGDATA_H_
-#define _GFXCONFIGDATA_H_
-
-AGESA_STATUS
-GfxAllocateConfigData (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN OUT GFX_PLATFORM_CONFIG **Gfx,
- IN PLATFORM_CONFIGURATION *PlatformConfig
- );
-
-AGESA_STATUS
-GfxLocateConfigData (
- IN AMD_CONFIG_PARAMS *StdHeader,
- OUT GFX_PLATFORM_CONFIG **Gfx
- );
-
-AGESA_STATUS
-GfxEnableGmmAccess (
- IN OUT GFX_PLATFORM_CONFIG *Gfx
- );
-
-VOID
-GfxGetUmaInfo (
- OUT UMA_INFO *UmaInfo,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxGmcInit.c b/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxGmcInit.c
deleted file mode 100644
index c92e819..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxGmcInit.c
+++ /dev/null
@@ -1,722 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * GMC init services.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-//#include "heapManager.h"
-#include "Gnb.h"
-#include "GnbGfx.h"
-#include "GnbPcie.h"
-#include "GnbGfxFamServices.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include "GfxLib.h"
-#include "GfxFamilyServices.h"
-#include "GfxRegisterAcc.h"
-//#include "GfxStrapsInit.h"
-#include "OptionGnb.h"
-#include "GnbRegistersON.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_GFX_GFXGMCINIT_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/// DCT channel information
-typedef struct {
- D18F2x094_STRUCT D18F2x094; ///< Register 0x94
- D18F2x084_STRUCT D18F2x084; ///< Register 0x84
- D18F2x08C_STRUCT D18F2x08C; ///< Register 0x8C
- D18F2x0F4_x40_STRUCT D18F2x0F4_x40; ///< Register 0x40
- D18F2x0F4_x41_STRUCT D18F2x0F4_x41; ///< Register 0x41
-} DCT_CHANNEL_INFO;
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-//Family 12 or Family 14 specific tables
-
-extern TABLE_INDIRECT_PTR GmcDisableClockGatingPtr;
-extern TABLE_INDIRECT_PTR GmcEnableClockGatingPtr;
-extern TABLE_INDIRECT_PTR GmcPerformanceTuningTablePtr;
-extern TABLE_INDIRECT_PTR GmcMiscInitTablePtr;
-extern TABLE_INDIRECT_PTR GmcRemoveBlackoutTablePtr;
-extern TABLE_INDIRECT_PTR GmcRegisterEngineInitTablePtr;
-extern TABLE_INDIRECT_PTR CnbToGncRegisterCopyTablePtr;
-
-extern UINT8 NumberOfChannels;
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init GMC memory address translation
- *
- *
- *
- * @param[in] Gfx Pointer to global GFX configuration
- */
-VOID
-GfxGmcSetMemoryAddressTranslation (
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- UINTN Index;
- REGISTER_COPY_ENTRY *CnbToGncRegisterCopyTable;
- CnbToGncRegisterCopyTable = CnbToGncRegisterCopyTablePtr.TablePtr;
- for (Index = 0; Index < CnbToGncRegisterCopyTablePtr.TableLength; Index++) {
- UINT32 Value;
- GnbLibPciRead (
- CnbToGncRegisterCopyTable[Index].CpuReg,
- AccessWidth32,
- &Value,
- GnbLibGetHeader (Gfx)
- );
- Value = (Value >> CnbToGncRegisterCopyTable[Index].CpuOffset) & ((1 << CnbToGncRegisterCopyTable[Index].CpuWidth) - 1);
- GmmRegisterWriteField (
- CnbToGncRegisterCopyTable[Index].GmmReg,
- CnbToGncRegisterCopyTable[Index].GmmOffset,
- CnbToGncRegisterCopyTable[Index].GmmWidth,
- Value,
- TRUE,
- Gfx
- );
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Disable CLock Gating
- *
- *
- *
- * @param[in] Gfx Graphics configuration
- */
-
-VOID
-GfxGmcDisableClockGating (
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- GmmRegisterTableWrite (
- GmcDisableClockGatingPtr.TablePtr,
- GmcDisableClockGatingPtr.TableLength,
- TRUE,
- Gfx
- );
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Initialize Register Engine
- *
- *
- *
- * @param[in] Gfx Pointer to global GFX configuration
- */
-
-VOID
-GfxGmcInitializeRegisterEngine (
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
-
- GmmRegisterTableWrite (
- GmcRegisterEngineInitTablePtr.TablePtr,
- GmcRegisterEngineInitTablePtr.TableLength,
- TRUE,
- Gfx
- );
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get DCT channel info
- *
- *
- * @param[in] Channel DCT channel number
- * @param[out] DctChannelInfo Various DCT channel info
- * @param[in] Gfx Pointer to global GFX configuration
- */
-
-VOID
-GfxGmcDctMemoryChannelInfo (
- IN UINT8 Channel,
- OUT DCT_CHANNEL_INFO *DctChannelInfo,
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- GnbLibCpuPciIndirectRead (
- MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x0F0_ADDRESS : D18F2x1F0_ADDRESS),
- D18F2x0F4_x40_ADDRESS,
- &DctChannelInfo->D18F2x0F4_x40.Value,
- GnbLibGetHeader (Gfx)
- );
-
- GnbLibCpuPciIndirectRead (
- MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x0F0_ADDRESS : D18F2x1F0_ADDRESS),
- D18F2x0F4_x41_ADDRESS,
- &DctChannelInfo->D18F2x0F4_x41.Value,
- GnbLibGetHeader (Gfx)
- );
-
- GnbLibPciRead (
- MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x084_ADDRESS : D18F2x184_ADDRESS),
- AccessWidth32,
- &DctChannelInfo->D18F2x084.Value,
- GnbLibGetHeader (Gfx)
- );
-
- GnbLibPciRead (
- MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x094_ADDRESS : D18F2x194_ADDRESS),
- AccessWidth32,
- &DctChannelInfo->D18F2x094.Value,
- GnbLibGetHeader (Gfx)
- );
-
- GnbLibPciRead (
- MAKE_SBDFO (0, 0, 0x18, 2, (Channel == 0) ? D18F2x08C_ADDRESS : D18F2x18C_ADDRESS),
- AccessWidth32,
- &DctChannelInfo->D18F2x08C.Value,
- GnbLibGetHeader (Gfx)
- );
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Initialize Sequencer Model
- *
- *
- *
- * @param[in] Gfx Pointer to global GFX configuration
- */
-
-VOID
-GfxGmcInitializeSequencerModel (
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- GMMx277C_STRUCT GMMx277C;
- GMMx2780_STRUCT GMMx2780;
- DCT_CHANNEL_INFO DctChannel[2];
- UINT8 ActiveChannel;
-
- GfxGmcDctMemoryChannelInfo (0, &DctChannel[0], Gfx);
- if (NumberOfChannels == 2) {
- GfxGmcDctMemoryChannelInfo (1, &DctChannel[1], Gfx);
- }
-
- // Find the Active Channels. For a single channel system, Active channel is 0;
- if (NumberOfChannels == 1) {
- ActiveChannel = 0;
- } else {
- //For two channel system, Active channel could be either 0 or 1 or both (2)
- if (DctChannel[0].D18F2x094.Field.DisDramInterface == 0 &&
- DctChannel[1].D18F2x094.Field.DisDramInterface == 0) {
- ActiveChannel = 2;
- } else {
- ActiveChannel = (DctChannel[0].D18F2x094.Field.DisDramInterface == 0) ? 0 : 1;
- }
- }
-
- if (ActiveChannel == 2) {
- // Both controllers enabled
- GMMx277C.Field.ActRd = MIN (DctChannel[0].D18F2x0F4_x40.Field.Trcd, DctChannel[1].D18F2x0F4_x40.Field.Trcd) + 5;
- GMMx277C.Field.RasMActRd = MIN ((DctChannel[0].D18F2x0F4_x40.Field.Trc + 11 - (DctChannel[0].D18F2x0F4_x40.Field.Trcd + 5)),
- (DctChannel[1].D18F2x0F4_x40.Field.Trc + 11 - (DctChannel[1].D18F2x0F4_x40.Field.Trcd + 5)));
- GMMx2780.Field.Ras2Ras = MIN (DctChannel[0].D18F2x0F4_x40.Field.Trc, DctChannel[1].D18F2x0F4_x40.Field.Trc) + 11 - 1;
- GMMx2780.Field.Rp = MIN (DctChannel[0].D18F2x0F4_x40.Field.Trp, DctChannel[1].D18F2x0F4_x40.Field.Trp) + 5 - 1;
- GMMx2780.Field.WrPlusRp = MIN (
- ((DctChannel[0].D18F2x084.Field.Twr == 0) ? 16 :
- ((DctChannel[0].D18F2x084.Field.Twr < 4) ? (DctChannel[0].D18F2x084.Field.Twr + 4) :
- (DctChannel[0].D18F2x084.Field.Twr * 2)) + DctChannel[0].D18F2x0F4_x40.Field.Trp + 5),
- ((DctChannel[1].D18F2x084.Field.Twr == 0) ? 16 :
- ((DctChannel[1].D18F2x084.Field.Twr < 4) ? (DctChannel[1].D18F2x084.Field.Twr + 4) :
- (DctChannel[1].D18F2x084.Field.Twr * 2)) + DctChannel[1].D18F2x0F4_x40.Field.Trp + 5)
- ) - 1;
- GMMx2780.Field.BusTurn = (MIN (
- DctChannel[0].D18F2x084.Field.Tcwl + 5 +
- DctChannel[0].D18F2x0F4_x41.Field.Twtr + 4 +
- DctChannel[0].D18F2x08C.Field.TrwtTO + 2 ,
- DctChannel[1].D18F2x084.Field.Tcwl + 5 +
- DctChannel[1].D18F2x0F4_x41.Field.Twtr + 4 +
- DctChannel[1].D18F2x08C.Field.TrwtTO + 2
- ) + 4) / 2;
- } else {
- // Only one channel is active.
- GMMx277C.Field.ActRd = DctChannel[ActiveChannel].D18F2x0F4_x40.Field.Trcd + 5;
- GMMx277C.Field.RasMActRd = DctChannel[ActiveChannel].D18F2x0F4_x40.Field.Trc + 11 -
- (DctChannel[ActiveChannel].D18F2x0F4_x40.Field.Trcd + 5);
- GMMx2780.Field.Ras2Ras = DctChannel[ActiveChannel].D18F2x0F4_x40.Field.Trc + 11 - 1;
- GMMx2780.Field.Rp = DctChannel[ActiveChannel].D18F2x0F4_x40.Field.Trp + 5 - 1;
- GMMx2780.Field.WrPlusRp = ((DctChannel[ActiveChannel].D18F2x084.Field.Twr == 0) ? 16 :
- ((DctChannel[ActiveChannel].D18F2x084.Field.Twr < 4) ? (DctChannel[ActiveChannel].D18F2x084.Field.Twr + 4) :
- (DctChannel[ActiveChannel].D18F2x084.Field.Twr * 2)) +
- DctChannel[ActiveChannel].D18F2x0F4_x40.Field.Trp + 5) - 1;
- GMMx2780.Field.BusTurn = ((DctChannel[ActiveChannel].D18F2x084.Field.Tcwl + 5 +
- DctChannel[ActiveChannel].D18F2x0F4_x41.Field.Twtr + 4 +
- DctChannel[ActiveChannel].D18F2x08C.Field.TrwtTO + 2) + 4) / 2;
- }
- GMMx277C.Field.ActWr = GMMx277C.Field.ActRd;
- GMMx277C.Field.RasMActWr = GMMx277C.Field.RasMActRd;
-
- GmmRegisterWrite (
- GMMx277C_ADDRESS,
- GMMx277C.Value,
- TRUE,
- Gfx
- );
- GmmRegisterWrite (
- GMMx28D8_ADDRESS,
- GMMx277C.Value,
- TRUE,
- Gfx
- );
- GmmRegisterWrite (
- GMMx2780_ADDRESS,
- GMMx2780.Value,
- TRUE,
- Gfx
- );
- GmmRegisterWrite (
- GMMx28DC_ADDRESS,
- GMMx2780.Value,
- TRUE,
- Gfx
- );
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Initialize Frame Buffer Location
- *
- *
- *
- * @param[in] Gfx Pointer to global GFX configuration
- */
-
-VOID
-GfxGmcInitializeFbLocation (
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- //Logical FB location
- GMMx2024_STRUCT GMMx2024;
- GMMx2898_STRUCT GMMx2898;
- GMMx2C04_STRUCT GMMx2C04;
- GMMx5428_STRUCT GMMx5428;
- UINT64 FBBase;
- UINT64 FBTop;
- FBBase = 0x0F00000000;
- FBTop = FBBase + Gfx->UmaInfo.UmaSize - 1;
- GMMx2024.Value = 0;
- GMMx2898.Value = 0;
- GMMx2C04.Value = 0;
- GMMx5428.Value = 0;
- GMMx2024.Field.Base = (UINT16) (FBBase >> 24);
- GMMx2024.Field.Top = (UINT16) (FBTop >> 24);
- GMMx2898.Field.Offset = (UINT32) (Gfx->UmaInfo.UmaBase >> 20);
- GMMx2898.Field.Top = (UINT32) ((FBTop >> 20) & 0xf);
- GMMx2898.Field.Base = (UINT32) ((FBBase >> 20) & 0xf);
- GMMx2C04.Field.NonsurfBase = (UINT32) (FBBase >> 8);
- GMMx5428.Field.ConfigMemsize = Gfx->UmaInfo.UmaSize;
-
- GmmRegisterWrite (
- GMMx2024_ADDRESS,
- GMMx2024.Value,
- TRUE,
- Gfx
- );
- GmmRegisterWrite (
- GMMx2898_ADDRESS,
- GMMx2898.Value,
- TRUE,
- Gfx
- );
- GmmRegisterWrite (
- GMMx2C04_ADDRESS,
- GMMx2C04.Value,
- TRUE,
- Gfx
- );
- GmmRegisterWrite (
- GMMx5428_ADDRESS,
- GMMx5428.Value,
- TRUE,
- Gfx
- );
- GmmRegisterWriteField (
- GMMx5490_ADDRESS,
- GMMx5490_FbReadEn_OFFSET,
- GMMx5490_FbReadEn_WIDTH,
- 1,
- TRUE,
- Gfx
- );
- GmmRegisterWriteField (
- GMMx5490_ADDRESS,
- GMMx5490_FbWriteEn_OFFSET,
- GMMx5490_FbWriteEn_WIDTH,
- 1,
- TRUE,
- Gfx
- );
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Secure Garlic Access
- *
- *
- *
- * @param[in] Gfx Pointer to global GFX configuration
- */
-
-VOID
-GfxGmcSecureGarlicAccess (
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- GMMx286C_STRUCT GMMx286C;
- GMMx287C_STRUCT GMMx287C;
- GMMx2894_STRUCT GMMx2894;
- UINT32 Value;
- GMMx286C.Value = (UINT32) (Gfx->UmaInfo.UmaBase >> 20);
- GmmRegisterWrite (GMMx286C_ADDRESS, GMMx286C.Value, TRUE, Gfx);
- GMMx287C.Value = (UINT32) (((Gfx->UmaInfo.UmaBase + Gfx->UmaInfo.UmaSize) >> 20) - 1);
- GmmRegisterWrite (GMMx287C_ADDRESS, GMMx287C.Value, TRUE, Gfx);
- // Areag FB - 20K reserved by VBIOS for SBIOS to use
- GMMx2894.Value = (UINT32) ((Gfx->UmaInfo.UmaBase + Gfx->UmaInfo.UmaSize - 20 * 1024) >> 12);
- GmmRegisterWrite (GMMx2894_ADDRESS, GMMx2894.Value, TRUE, Gfx);
- Value = 0xfffff;
- GmmRegisterWrite (GMMx2870_ADDRESS, Value, TRUE, Gfx);
- GmmRegisterWrite (GMMx2874_ADDRESS, Value, TRUE, Gfx);
- GmmRegisterWrite (GMMx2878_ADDRESS, Value, TRUE, Gfx);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Performance setting
- *
- *
- *
- * @param[in] Gfx Pointer to global GFX configuration
- */
-
-VOID
-GfxGmcPerformanceTuning (
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- GmmRegisterTableWrite (
- GmcPerformanceTuningTablePtr.TablePtr,
- GmcPerformanceTuningTablePtr.TableLength,
- TRUE,
- Gfx
- );
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Misc. Initialization
- *
- *
- *
- * @param[in] Gfx Pointer to global GFX configuration
- */
-
-VOID
-GfxGmcMiscInit (
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- GmmRegisterTableWrite (
- GmcMiscInitTablePtr.TablePtr,
- GmcMiscInitTablePtr.TableLength,
- TRUE,
- Gfx
- );
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Lock critical registers
- *
- *
- *
- * @param[in] Gfx Graphics configuration
- */
-
-VOID
-GfxGmcLockCriticalRegisters (
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- GmmRegisterWriteField (
- 0x2B98,
- 27,
- 1,
- 1,
- TRUE,
- Gfx
- );
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Remove blackout
- *
- *
- *
- * @param[in] Gfx Pointer to global GFX configuration
- */
-
-VOID
-GfxGmcRemoveBlackout (
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- GmmRegisterTableWrite (
- GmcRemoveBlackoutTablePtr.TablePtr,
- GmcRemoveBlackoutTablePtr.TableLength,
- TRUE,
- Gfx
- );
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Enable clock Gating
- *
- *
- *
- * @param[in] Gfx Graphics configuration
- */
-
-VOID
-GfxGmcEnableClockGating (
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- GmmRegisterTableWrite (
- GmcEnableClockGatingPtr.TablePtr,
- GmcEnableClockGatingPtr.TableLength,
- TRUE,
- Gfx
- );
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * UMA steering
- *
- *
- *
- * @param[in] Gfx Graphics configuration
- */
-
-VOID
-GfxGmcUmaSteering (
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- UINT64 FBBase;
- UINT64 FBTop;
-
- if (Gfx->UmaSteering == Onion) {
-
- FBBase = Gfx->UmaInfo.UmaBase;
- FBTop = FBBase + Gfx->UmaInfo.UmaSize - 1;
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Initialize C6 aperture
- *
- *
- *
- * @param[in] Gfx Graphics configuration
- */
-
-VOID
-GfxGmcInitializeC6Aperture (
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- D18F4x12C_STRUCT D18F4x12C;
- GMMx288C_STRUCT GMMx288C;
- GMMx2890_STRUCT GMMx2890;
-
- GnbLibPciRead (
- MAKE_SBDFO (0, 0, 0x18, 4, D18F4x12C_ADDRESS),
- AccessWidth32,
- &D18F4x12C.Value,
- GnbLibGetHeader (Gfx)
- );
- GMMx288C.Value = D18F4x12C.Field.C6Base_35_24_ << 4;
- // Modify the values only if C6 Base is set
- if (GMMx288C.Value != 0) {
- GMMx2890.Value = (GMMx288C.Value + 16) - 1;
- GmmRegisterWrite (
- GMMx288C_ADDRESS,
- GMMx288C.Value,
- TRUE,
- Gfx
- );
- GmmRegisterWrite (
- GMMx2890_ADDRESS,
- GMMx2890.Value,
- TRUE,
- Gfx
- );
- }
-}
-/*----------------------------------------------------------------------------------------*/
-/**
- * Initialize Power Gating
- *
- *
- *
- * @param[in] Gfx Graphics configuration
- */
-
-VOID
-GfxGmcInitializePowerGating (
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- switch (Gfx->GmcPowerGating) {
- case GmcPowerGatingDisabled:
- break;
- case GmcPowerGatingStutterOnly:
- GmmRegisterWriteField (
- 0x2B98,
- 16,
- 1,
- 1,
- TRUE,
- Gfx
- );
- break;
- case GmcPowerGatingWidthStutter:
- GmmRegisterWriteField (
- 0x2B94,
- 0,
- 1,
- 1,
- TRUE,
- Gfx
- );
- GmmRegisterWriteField (
- 0x2B98,
- 11,
- 1,
- 1,
- TRUE,
- Gfx
- );
- break;
- default:
- ASSERT (FALSE);
- }
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init GMC
- *
- *
- *
- * @param[in] Gfx Pointer to global GFX configuration
- * @retval AGESA_STATUS Always succeeds
- */
-
-AGESA_STATUS
-GfxGmcInit (
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- AGESA_STATUS Status;
- Status = AGESA_SUCCESS;
- IDS_HDT_CONSOLE (GNB_TRACE, "GfxGmcInit Enter\n");
- GfxGmcDisableClockGating (Gfx);
- GfxGmcSetMemoryAddressTranslation (Gfx);
- GfxGmcInitializeSequencerModel (Gfx);
- GfxGmcInitializeRegisterEngine (Gfx);
- GfxGmcInitializeFbLocation (Gfx);
- GfxGmcUmaSteering (Gfx);
- GfxGmcSecureGarlicAccess (Gfx);
- GfxGmcInitializeC6Aperture (Gfx);
- GfxFmGmcAddressSwizzel (Gfx);
- IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_GMM_REGISTER_OVERRIDE, Gfx, GnbLibGetHeader (Gfx));
- GfxGmcLockCriticalRegisters (Gfx);
- GfxGmcPerformanceTuning (Gfx);
- GfxGmcMiscInit (Gfx);
- GfxGmcRemoveBlackout (Gfx);
- if (Gfx->GmcClockGating == OptionEnabled) {
- GfxGmcEnableClockGating (Gfx);
- }
- GfxGmcInitializePowerGating (Gfx);
- IDS_HDT_CONSOLE (GNB_TRACE, "GfxGmcInit Exit\n");
- return Status;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxGmcInit.h b/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxGmcInit.h
deleted file mode 100644
index c21805a..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxGmcInit.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * GMC init services.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _GFXGMCINIT_H_
-#define _GFXGMCINIT_H_
-
-
-AGESA_STATUS
-GfxGmcInit (
- IN GFX_PLATFORM_CONFIG *Gfx
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxInitAtEnvPost.c b/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxInitAtEnvPost.c
deleted file mode 100644
index 70a5b09..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxInitAtEnvPost.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Interface to initialize Graphics Controller at env POST
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 40151 $ @e \$Date: 2010-10-20 06:38:17 +0800 (Wed, 20 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Gnb.h"
-#include "GnbGfx.h"
-#include GNB_MODULE_DEFINITIONS (GnbGfxConfig)
-#include "GfxStrapsInit.h"
-#include "GfxInitAtEnvPost.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_GFX_GFXINITATENVPOST_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init GFX at Env Post.
- *
- *
- *
- * @param[in] StdHeader Standard configuration header
- * @retval AGESA_STATUS
- */
-
-
-AGESA_STATUS
-GfxInitAtEnvPost (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_STATUS Status;
- GFX_PLATFORM_CONFIG *Gfx;
- IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitAtEnvPost Enter\n");
- Status = GfxLocateConfigData (StdHeader, &Gfx);
- if (Status == AGESA_SUCCESS) {
- if (Gfx->UmaInfo.UmaMode != UMA_NONE) {
- Status = GfxStrapsInit (Gfx);
- ASSERT (Status == AGESA_SUCCESS);
- } else {
- GfxDisableController (StdHeader);
- }
- } else {
- GfxDisableController (StdHeader);
- }
- IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitAtEnvPost Exit [0x%x]\n", Status);
- return Status;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxInitAtEnvPost.h b/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxInitAtEnvPost.h
deleted file mode 100644
index 0a80457..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxInitAtEnvPost.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Interface to initialize Graphics Controller at env POST
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _GFXINITATENVPOST_H_
-#define _GFXINITATENVPOST_H_
-
-AGESA_STATUS
-GfxInitAtEnvPost (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxInitAtMidPost.c b/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxInitAtMidPost.c
deleted file mode 100644
index d9ca4c1..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxInitAtMidPost.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Interface to initialize Graphics Controller at mid POST
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 40151 $ @e \$Date: 2010-10-20 06:38:17 +0800 (Wed, 20 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Gnb.h"
-#include "GnbGfx.h"
-#include GNB_MODULE_DEFINITIONS (GnbGfxConfig)
-#include "GfxConfigData.h"
-#include "GfxStrapsInit.h"
-#include "GfxGmcInit.h"
-#include "GfxInitAtMidPost.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_GFX_GFXINITATMIDPOST_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init GFX at Mid Post.
- *
- *
- *
- * @param[in] StdHeader Standard configuration header
- * @retval AGESA_STATUS
- */
-
-AGESA_STATUS
-GfxInitAtMidPost (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_STATUS Status;
- AGESA_STATUS AgesaStatus;
- GFX_PLATFORM_CONFIG *Gfx;
- IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitAtMidPost Enter\n");
- AgesaStatus = AGESA_SUCCESS;
- Status = GfxLocateConfigData (StdHeader, &Gfx);
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
- if (Status == AGESA_FATAL) {
- GfxDisableController (StdHeader);
- } else {
- if (Gfx->UmaInfo.UmaMode != UMA_NONE) {
- Status = GfxEnableGmmAccess (Gfx);
- ASSERT (Status == AGESA_SUCCESS);
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
- if (Status != AGESA_SUCCESS) {
- // Can not initialize GMM registers going to disable GFX controller
- IDS_HDT_CONSOLE (GNB_TRACE, " Fail to establish GMM access\n");
- Gfx->UmaInfo.UmaMode = UMA_NONE;
- GfxDisableController (StdHeader);
- } else {
- Status = GfxGmcInit (Gfx);
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
-
- Status = GfxSetBootUpVoltage (Gfx);
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
-
- Status = GfxInitSsid (Gfx);
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
- }
- }
- GfxSetIdleVoltageMode (Gfx);
- }
- IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitAtMidPost Exit [0x%x]\n", AgesaStatus);
- return AgesaStatus;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxInitAtMidPost.h b/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxInitAtMidPost.h
deleted file mode 100644
index 59b8362..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxInitAtMidPost.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Interface to initialize Graphics Controller at mid POST
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _GFXINITATMIDPOST_H_
-#define _GFXINITATMIDPOST_H_
-
-AGESA_STATUS
-GfxInitAtMidPost (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxInitAtPost.c b/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxInitAtPost.c
deleted file mode 100644
index 891dcdf..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxInitAtPost.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Interface to initialize Graphics Controller at POST
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 40151 $ @e \$Date: 2010-10-20 06:38:17 +0800 (Wed, 20 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Gnb.h"
-#include "GnbPcie.h"
-#include "GnbGfx.h"
-#include GNB_MODULE_DEFINITIONS (GnbGfxInitLibV1)
-#include "GfxStrapsInit.h"
-#include "GfxLib.h"
-#include "GfxConfigData.h"
-#include "GfxInitAtPost.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_GFX_GFXINITATPOST_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init GFX at Post.
- *
- *
- *
- * @param[in] StdHeader Standard configuration header
- * @retval AGESA_STATUS
- */
-
-
-AGESA_STATUS
-GfxInitAtPost (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AMD_POST_PARAMS *PostParamsPtr;
- GFX_CARD_CARD_INFO GfxDiscreteCardInfo;
- AGESA_STATUS Status;
- GFX_PLATFORM_CONFIG *Gfx;
- PostParamsPtr = (AMD_POST_PARAMS *)StdHeader;
- IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitAtPost Enter\n");
- Status = GfxLocateConfigData (StdHeader, &Gfx);
- ASSERT (Status == AGESA_SUCCESS);
- if (Status == AGESA_SUCCESS) {
- if (GfxLibIsControllerPresent (StdHeader)) {
- if (PostParamsPtr->MemConfig.UmaMode != UMA_NONE) {
- LibAmdMemFill (&GfxDiscreteCardInfo, 0x0, sizeof (GfxDiscreteCardInfo), StdHeader);
- GfxGetDiscreteCardInfo (&GfxDiscreteCardInfo, StdHeader);
- if (GfxDiscreteCardInfo.PciGfxCardBitmap != 0 ||
- (GfxDiscreteCardInfo.AmdPcieGfxCardBitmap & GfxDiscreteCardInfo.PcieGfxCardBitmap) !=
- GfxDiscreteCardInfo.AmdPcieGfxCardBitmap) {
- PostParamsPtr->MemConfig.UmaMode = UMA_NONE;
- IDS_HDT_CONSOLE (GFX_MISC, " GfxDisabled due dGPU policy\n");
- }
- }
- } else {
- PostParamsPtr->MemConfig.UmaMode = UMA_NONE;
- Gfx->GfxFusedOff = TRUE;
- }
- } else {
- PostParamsPtr->MemConfig.UmaMode = UMA_NONE;
- }
- IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitAtPost Exit [0x%x]\n", Status);
- return Status;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxInitAtPost.h b/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxInitAtPost.h
deleted file mode 100644
index 622c645..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxInitAtPost.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Interface to initialize Graphics Controller at POST
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 38641 $ @e \$Date: 2010-09-27 23:16:17 +0800 (Mon, 27 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _GFXINITATPOST_H_
-#define _GFXINITATPOST_H_
-
-AGESA_STATUS
-GfxInitAtPost (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c b/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c
deleted file mode 100644
index 2c525fa..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c
+++ /dev/null
@@ -1,666 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Service procedure to initialize Integrated Info Table
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 41507 $ @e \$Date: 2010-11-05 23:13:47 +0800 (Fri, 05 Nov 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "heapManager.h"
-#include "Gnb.h"
-#include "GnbFuseTable.h"
-#include "GnbPcie.h"
-#include "GnbGfx.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include GNB_MODULE_DEFINITIONS (GnbPcieConfig)
-#include GNB_MODULE_DEFINITIONS (GnbGfxInitLibV1)
-#include GNB_MODULE_DEFINITIONS (GnbGfxConfig)
-#include "GfxLib.h"
-#include "GfxConfigData.h"
-#include "GfxRegisterAcc.h"
-#include "GfxFamilyServices.h"
-#include "GfxIntegratedInfoTableInit.h"
-#include "GnbRegistersON.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_GFX_GFXINTEGRATEDINFOTABLEINIT_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-ULONG ulCSR_M3_ARB_CNTL_DEFAULT[] = {
- 0x80040810,
- 0x00040810,
- 0x00040810,
- 0x00040810,
- 0x00040810,
- 0x00040810,
- 0x00204080,
- 0x00204080,
- 0x0000001E,
- 0x00000000
-};
-
-
-ULONG ulCSR_M3_ARB_CNTL_UVD[] = {
- 0x80040810,
- 0x00040810,
- 0x00040810,
- 0x00040810,
- 0x00040810,
- 0x00040810,
- 0x00204080,
- 0x00204080,
- 0x0000001E,
- 0x00000000
-};
-
-
-ULONG ulCSR_M3_ARB_CNTL_FS3D[] = {
- 0x80040810,
- 0x00040810,
- 0x00040810,
- 0x00040810,
- 0x00040810,
- 0x00040810,
- 0x00204080,
- 0x00204080,
- 0x0000001E,
- 0x00000000
-};
-
-
-VOID
-GfxIntegratedInfoInitDispclkTable (
- IN PP_FUSE_ARRAY *PpFuseArray,
- IN ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable,
- IN GFX_PLATFORM_CONFIG *Gfx
- );
-
-VOID
-GfxIntegratedInfoInitSclkTable (
- IN PP_FUSE_ARRAY *PpFuseArray,
- IN ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable,
- IN GFX_PLATFORM_CONFIG *Gfx
- );
-
-VOID
-GfxFillHtcData (
- IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable,
- IN GFX_PLATFORM_CONFIG *Gfx
- );
-
-VOID
-GfxFillNbPStateVid (
- IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable,
- IN GFX_PLATFORM_CONFIG *Gfx
- );
-
-VOID
-GfxFillM3ArbritrationControl (
- IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable,
- IN GFX_PLATFORM_CONFIG *Gfx
- );
-
-
-VOID
-GfxFillSbMmioBaseAddress (
- IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable,
- IN GFX_PLATFORM_CONFIG *Gfx
- );
-
-VOID
-GfxFillNclkInfo (
- IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable,
- IN GFX_PLATFORM_CONFIG *Gfx
- );
-
-AGESA_STATUS
-GfxIntegratedInfoTableInit (
- IN GFX_PLATFORM_CONFIG *Gfx
- );
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get CSR phy self refresh power down mode.
- *
- *
- * @param[in] Channel DCT controller index
- * @param[in] StdHeader Standard configuration header
- * @retval CsrPhySrPllPdMode
- */
-UINT32
-GfxLibGetCsrPhySrPllPdMode (
- IN UINT8 Channel,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- D18F2x09C_x0D0FE00A_STRUCT D18F2x09C_x0D0FE00A;
-
- GnbLibCpuPciIndirectRead (
- MAKE_SBDFO ( 0, 0, 0x18, 2, (Channel == 0) ? D18F2x098_ADDRESS : D18F2x198_ADDRESS),
- D18F2x09C_x0D0FE00A_ADDRESS,
- &D18F2x09C_x0D0FE00A.Value,
- StdHeader
- );
-
- return D18F2x09C_x0D0FE00A.Field.CsrPhySrPllPdMode;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get disable DLL shutdown in self-refresh mode.
- *
- *
- * @param[in] Channel DCT controller index
- * @param[in] StdHeader Standard configuration header
- * @retval DisDllShutdownSR
- */
-UINT32
-GfxLibGetDisDllShutdownSR (
- IN UINT8 Channel,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- D18F2x090_STRUCT D18F2x090;
-
- GnbLibPciRead (
- MAKE_SBDFO ( 0, 0, 0x18, 2, (Channel == 0) ? D18F2x090_ADDRESS : D18F2x190_ADDRESS),
- AccessWidth32,
- &D18F2x090.Value,
- StdHeader
- );
-
- return D18F2x090.Field.DisDllShutdownSR;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Build integrated info table
- * GMC FB access requred
- *
- *
- * @param[in] StdHeader Standard configuration header
- * @retval AGESA_STATUS
- */
-AGESA_STATUS
-GfxIntegratedInfoTableEntry (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_STATUS AgesaStatus;
- AGESA_STATUS Status;
- GFX_PLATFORM_CONFIG *Gfx;
- IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableEntry Enter\n");
- AgesaStatus = AGESA_SUCCESS;
- if (GfxLibIsControllerPresent (StdHeader)) {
- Status = GfxLocateConfigData (StdHeader, &Gfx);
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
- if (Status != AGESA_FATAL) {
- Status = GfxIntegratedInfoTableInit (Gfx);
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
- }
- }
- IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableEntry Exit[0x%x]\n", AgesaStatus);
- return AgesaStatus;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Build integrated info table
- *
- *
- *
- * @param[in] Gfx Gfx configuration info
- * @retval AGESA_STATUS
- */
-AGESA_STATUS
-GfxIntegratedInfoTableInit (
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- AGESA_STATUS Status;
- AGESA_STATUS AgesaStatus;
- ATOM_FUSION_SYSTEM_INFO_V1 SystemInfoV1Table;
- PP_FUSE_ARRAY *PpFuseArray;
- PCIe_PLATFORM_CONFIG *Pcie;
- UINT32 IntegratedInfoAddress;
- ATOM_PPLIB_POWERPLAYTABLE3 *PpTable;
- UINT8 Channel;
-
- AgesaStatus = AGESA_SUCCESS;
- IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInit Enter\n");
- LibAmdMemFill (&SystemInfoV1Table, 0x00, sizeof (ATOM_FUSION_SYSTEM_INFO_V1), GnbLibGetHeader (Gfx));
- SystemInfoV1Table.sIntegratedSysInfo.sHeader.usStructureSize = sizeof (ATOM_INTEGRATED_SYSTEM_INFO_V6);
- ASSERT (SystemInfoV1Table.sIntegratedSysInfo.sHeader.usStructureSize == 512);
- SystemInfoV1Table.sIntegratedSysInfo.sHeader.ucTableFormatRevision = 1;
- SystemInfoV1Table.sIntegratedSysInfo.sHeader.ucTableContentRevision = 6;
- SystemInfoV1Table.sIntegratedSysInfo.ulDentistVCOFreq = GfxLibGetMainPllFreq (GnbLibGetHeader (Gfx)) * 100;
- SystemInfoV1Table.sIntegratedSysInfo.ulBootUpUMAClock = Gfx->UmaInfo.MemClock * 100;
- SystemInfoV1Table.sIntegratedSysInfo.usRequestedPWMFreqInHz = Gfx->LcdBackLightControl;
- SystemInfoV1Table.sIntegratedSysInfo.ucUMAChannelNumber = ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_INTERLEAVE) == 0) ? 1 : 2;
- SystemInfoV1Table.sIntegratedSysInfo.ucMemoryType = 3; //DDR3
- SystemInfoV1Table.sIntegratedSysInfo.ulBootUpEngineClock = 200 * 100; //Set default engine clock to 200MhZ
- SystemInfoV1Table.sIntegratedSysInfo.usBootUpNBVoltage = GfxLibMaxVidIndex (GnbLibGetHeader (Gfx));
- SystemInfoV1Table.sIntegratedSysInfo.ulMinEngineClock = GfxLibGetMinSclk (GnbLibGetHeader (Gfx));
- SystemInfoV1Table.sIntegratedSysInfo.usPanelRefreshRateRange = Gfx->DynamicRefreshRate;
-
- SystemInfoV1Table.sIntegratedSysInfo.usLvdsSSPercentage = Gfx->LvdsSpreadSpectrum;
- SystemInfoV1Table.sIntegratedSysInfo.usLvdsSSpreadRateIn10Hz = Gfx->LvdsSpreadSpectrumRate;
-
- //Locate PCIe configuration data to get definitions of display connectors
- SystemInfoV1Table.sIntegratedSysInfo.sExtDispConnInfo.sHeader.usStructureSize = sizeof (ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO);
- SystemInfoV1Table.sIntegratedSysInfo.sExtDispConnInfo.sHeader.ucTableFormatRevision = 1;
- SystemInfoV1Table.sIntegratedSysInfo.sExtDispConnInfo.sHeader.ucTableContentRevision = 1;
- SystemInfoV1Table.sIntegratedSysInfo.sExtDispConnInfo.uc3DStereoPinId = Gfx->Gnb3dStereoPinIndex;
-
- ASSERT ((Gfx->UmaInfo.UmaAttributes & (UMA_ATTRIBUTE_ON_DCT0 | UMA_ATTRIBUTE_ON_DCT1)) != 0);
-
- if ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_ON_DCT0) != 0) {
- Channel = 0;
- } else {
- Channel = 1;
- }
- if (GfxLibGetCsrPhySrPllPdMode (Channel, GnbLibGetHeader (Gfx)) != 0) {
- SystemInfoV1Table.sIntegratedSysInfo.ulSystemConfig |= BIT2;
- }
- if (GfxLibGetDisDllShutdownSR (Channel, GnbLibGetHeader (Gfx)) == 0) {
- SystemInfoV1Table.sIntegratedSysInfo.ulSystemConfig |= BIT1;
- }
- Status = PcieLocateConfigurationData (GnbLibGetHeader (Gfx), &Pcie);
- ASSERT (Status == AGESA_SUCCESS);
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
- if (Status == AGESA_SUCCESS) {
- Status = GfxIntegratedEnumerateAllConnectors (
- &SystemInfoV1Table.sIntegratedSysInfo.sExtDispConnInfo.sPath[0],
- Pcie,
- Gfx
- );
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
- }
- SystemInfoV1Table.sIntegratedSysInfo.usExtDispConnInfoOffset = offsetof (ATOM_INTEGRATED_SYSTEM_INFO_V6, sExtDispConnInfo);
- // Build PP table
- PpTable = (ATOM_PPLIB_POWERPLAYTABLE3*) &SystemInfoV1Table.ulPowerplayTable;
- // Build PP table
- Status = GfxPowerPlayBuildTable (PpTable, Gfx);
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
- // Build info from fuses
- PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, GnbLibGetHeader (Gfx));
- ASSERT (PpFuseArray != NULL);
- if (PpFuseArray != NULL) {
- // Build Display clock info
- GfxIntegratedInfoInitDispclkTable (PpFuseArray, &SystemInfoV1Table.sIntegratedSysInfo, Gfx);
- // Build Sclk info table
- GfxIntegratedInfoInitSclkTable (PpFuseArray, &SystemInfoV1Table.sIntegratedSysInfo, Gfx);
- } else {
- Status = AGESA_ERROR;
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
- }
- // Fill in HTC Data
- GfxFillHtcData (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
- // Fill in NB P states VID
- GfxFillNbPStateVid (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
- // Fill in NCLK info
- GfxFillNclkInfo (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
- // Fill in the M3 arbitration control tables
- GfxFillM3ArbritrationControl (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
- // Fill South bridge MMIO Base address
- GfxFillSbMmioBaseAddress (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
- // Family specific data update
- GfxFmIntegratedInfoTableInit (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
- IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_INTEGRATED_TABLE_CONFIG, &SystemInfoV1Table.sIntegratedSysInfo, GnbLibGetHeader (Gfx));
- //Copy integrated info table to Frame Buffer. (Do not use LibAmdMemCopy, routine not guaranteed access to above 4G memory in 32 bit mode.)
- IntegratedInfoAddress = (UINT32) (Gfx->UmaInfo.UmaSize - sizeof (ATOM_FUSION_SYSTEM_INFO_V1));
- GfxLibCopyMemToFb ((VOID *) (&SystemInfoV1Table), IntegratedInfoAddress, sizeof (ATOM_FUSION_SYSTEM_INFO_V1), Gfx);
- IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInit Exit [0x%x]\n", Status);
- return Status;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- *Init Dispclk <-> VID table
- *
- *
- * @param[in] PpFuseArray Fuse array pointer
- * @param[in] IntegratedInfoTable Integrated info table pointer
- * @param[in] Gfx Gfx configuration info
- */
-
-VOID
-GfxIntegratedInfoInitDispclkTable (
- IN PP_FUSE_ARRAY *PpFuseArray,
- IN ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable,
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- UINTN Index;
- for (Index = 0; Index < 4; Index++) {
- if (PpFuseArray->DisplclkDid[Index] != 0) {
- IntegratedInfoTable->sDISPCLK_Voltage[Index].ulMaximumSupportedCLK = GfxLibCalculateClk (
- PpFuseArray->DisplclkDid[Index],
- IntegratedInfoTable->ulDentistVCOFreq
- );
- IntegratedInfoTable->sDISPCLK_Voltage[Index].ulVoltageIndex = (ULONG) Index;
- }
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- *Init Sclk <-> VID table
- *
- *
- * @param[in] PpFuseArray Fuse array pointer
- * @param[in] IntegratedInfoTable Integrated info table pointer
- * @param[in] Gfx Gfx configuration info
- */
-
-VOID
-GfxIntegratedInfoInitSclkTable (
- IN PP_FUSE_ARRAY *PpFuseArray,
- IN ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable,
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- UINTN Index;
- UINT8 SclkVidArray[4];
- UINTN AvailSclkIndex;
- ATOM_AVAILABLE_SCLK_LIST *AvailSclkList;
- BOOLEAN Sorting;
- AvailSclkList = &IntegratedInfoTable->sAvail_SCLK[0];
- GnbLibPciRead (
- MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS),
- AccessWidth32,
- &SclkVidArray[0],
- GnbLibGetHeader (Gfx)
- );
- AvailSclkIndex = 0;
- for (Index = 0; Index < MAX_NUM_OF_FUSED_DPM_STATES; Index++) {
- if (PpFuseArray->SclkDpmDid[Index] != 0) {
- AvailSclkList[AvailSclkIndex].ulSupportedSCLK = GfxLibCalculateClk (PpFuseArray->SclkDpmDid[Index], IntegratedInfoTable->ulDentistVCOFreq);
- AvailSclkList[AvailSclkIndex].usVoltageIndex = PpFuseArray->SclkDpmVid[Index];
- AvailSclkList[AvailSclkIndex].usVoltageID = SclkVidArray [PpFuseArray->SclkDpmVid[Index]];
- AvailSclkIndex++;
- }
- }
- //Sort by VoltageIndex & ulSupportedSCLK
- do {
- Sorting = FALSE;
- for (Index = 0; Index < (AvailSclkIndex - 1); Index++) {
- ATOM_AVAILABLE_SCLK_LIST Temp;
- BOOLEAN Exchange;
- Exchange = FALSE;
- if (AvailSclkList[Index].usVoltageIndex > AvailSclkList[Index + 1].usVoltageIndex) {
- Exchange = TRUE;
- }
- if ((AvailSclkList[Index].usVoltageIndex == AvailSclkList[Index + 1].usVoltageIndex) &&
- (AvailSclkList[Index].ulSupportedSCLK > AvailSclkList[Index + 1].ulSupportedSCLK)) {
- Exchange = TRUE;
- }
- if (Exchange) {
- Sorting = TRUE;
- LibAmdMemCopy (&Temp, &AvailSclkList[Index], sizeof (ATOM_AVAILABLE_SCLK_LIST), GnbLibGetHeader (Gfx));
- LibAmdMemCopy (&AvailSclkList[Index], &AvailSclkList[Index + 1], sizeof (ATOM_AVAILABLE_SCLK_LIST), GnbLibGetHeader (Gfx));
- LibAmdMemCopy (&AvailSclkList[Index + 1], &Temp, sizeof (ATOM_AVAILABLE_SCLK_LIST), GnbLibGetHeader (Gfx));
- }
- }
- } while (Sorting);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- *Init HTC Data
- *
- *
- * @param[in] IntegratedInfoTable Integrated info table pointer
- * @param[in] Gfx Gfx configuration info
- */
-
-VOID
-GfxFillHtcData (
- IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable,
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- D18F3x64_STRUCT D18F3x64;
-
- GnbLibPciRead (
- MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x64_ADDRESS),
- AccessWidth32,
- &D18F3x64.Value,
- GnbLibGetHeader (Gfx)
- );
- IntegratedInfoTable->ucHtcTmpLmt = (UCHAR)D18F3x64.Field.HtcTmpLmt;
- IntegratedInfoTable->ucHtcHystLmt = (UCHAR)D18F3x64.Field.HtcHystLmt;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- *Init NbPstateVid
- *
- *
- * @param[in] IntegratedInfoTable Integrated info table pointer
- * @param[in] Gfx Gfx configuration info
- */
-
-VOID
-GfxFillNbPStateVid (
- IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable,
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- D18F3xDC_STRUCT D18F3xDC;
- D18F6x90_STRUCT D18F6x90;
-
- GnbLibPciRead (
- MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3xDC_ADDRESS),
- AccessWidth32,
- &D18F3xDC.Value,
- GnbLibGetHeader (Gfx)
- );
- IntegratedInfoTable->usNBP0Voltage = (USHORT) D18F3xDC.Field.NbPs0Vid;
-
- GnbLibPciRead (
- MAKE_SBDFO ( 0, 0, 0x18, 6, D18F6x90_ADDRESS),
- AccessWidth32,
- &D18F6x90.Value,
- GnbLibGetHeader (Gfx)
- );
- IntegratedInfoTable->usNBP1Voltage = (USHORT) D18F6x90.Field.NbPs1Vid;
- IntegratedInfoTable->ulMinimumNClk = GfxLibCalculateClk (
- (UINT8) (((D18F6x90.Field.NbPs1NclkDiv != 0) && (D18F6x90.Field.NbPs1NclkDiv < D18F3xDC.Field.NbPs0NclkDiv)) ? D18F6x90.Field.NbPs1NclkDiv : D18F3xDC.Field.NbPs0NclkDiv),
- IntegratedInfoTable->ulDentistVCOFreq
- );
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- *Init M3 Arbitration Control values.
- *
- *
- * @param[in] IntegratedInfoTable Integrated info table pointer
- * @param[in] Gfx Gfx configuration info
- */
-
-VOID
-GfxFillM3ArbritrationControl (
- IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable,
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- LibAmdMemCopy (IntegratedInfoTable->ulCSR_M3_ARB_CNTL_DEFAULT, ulCSR_M3_ARB_CNTL_DEFAULT, sizeof (ulCSR_M3_ARB_CNTL_DEFAULT), GnbLibGetHeader (Gfx));
- LibAmdMemCopy (IntegratedInfoTable->ulCSR_M3_ARB_CNTL_UVD, ulCSR_M3_ARB_CNTL_UVD, sizeof (ulCSR_M3_ARB_CNTL_UVD), GnbLibGetHeader (Gfx));
- LibAmdMemCopy (IntegratedInfoTable->ulCSR_M3_ARB_CNTL_FS3D, ulCSR_M3_ARB_CNTL_FS3D, sizeof (ulCSR_M3_ARB_CNTL_FS3D), GnbLibGetHeader (Gfx));
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- *Init M3 Arbitration Control values.
- *
- *
- * @param[in] IntegratedInfoTable Integrated info table pointer
- * @param[in] Gfx Gfx configuration info
- */
-
-VOID
-GfxFillSbMmioBaseAddress (
- IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable,
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- UINT8 Index;
- UINT32 SbMmioBaseAddress;
- SbMmioBaseAddress = 0;
- //Read Dword from PMIO 24h. SB PMIO region supports only byte read.
- for (Index = 0x24; Index < 0x28; Index++) {
- GnbLibIoWrite (SB_IOMAP_REGCD6, AccessWidth8, &Index, GnbLibGetHeader (Gfx));
- GnbLibIoRead (SB_IOMAP_REGCD7, AccessWidth8, &(((UINT8*) &SbMmioBaseAddress)[Index - 0x24]), GnbLibGetHeader (Gfx));
- }
- // If MMIO is enabled and set for memory(not IO) then set MMIO_Base_Addr parameter.
- if ((SbMmioBaseAddress & (SB_MMIO_IO_MAPPED_ENABLE | SB_MMIO_DECODE_ENABLE)) == SB_MMIO_DECODE_ENABLE) {
- IntegratedInfoTable->ulSB_MMIO_Base_Addr = (ULONG) (SbMmioBaseAddress & (~SB_MMIO_DECODE_ENABLE)) ;
- } else {
- IntegratedInfoTable->ulSB_MMIO_Base_Addr = 0;
- }
- IDS_HDT_CONSOLE (GFX_MISC, " ulSB_MMIO_Base_Addr = 0x%x\n", IntegratedInfoTable->ulSB_MMIO_Base_Addr);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Fill in NCLK info
- *
- * set ulMinimumNClk and ulIdleNClk
- *
- * @param[in] IntegratedInfoTable Integrated info table pointer
- * @param[in] Gfx Gfx configuration info
- */
-
-VOID
-GfxFillNclkInfo (
- IN OUT ATOM_INTEGRATED_SYSTEM_INFO_V6 *IntegratedInfoTable,
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
-
- D18F3xA0_STRUCT D18F3xA0;
- D18F6x9C_STRUCT D18F6x9C;
- D18F3xDC_STRUCT D18F3xDC;
- D18F6x90_STRUCT D18F6x90;
-
- //
- // ulIdleNClk = GfxLibGetMainPllFreq (...) / F6x9C[NclkRedDiv] divisor (main PLL frequency / NCLK divisor)
- //
- GnbLibPciRead (
- MAKE_SBDFO ( 0, 0, 0x18, 6, D18F6x9C_ADDRESS),
- AccessWidth32,
- &D18F6x9C.Value,
- GnbLibGetHeader (Gfx)
- );
-
- IntegratedInfoTable->ulIdleNClk = GfxLibCalculateIdleNclk (
- (UINT8) D18F6x9C.Field.NclkRedDiv,
- IntegratedInfoTable->ulDentistVCOFreq
- );
-
- //
- // Set ulMinimumNClk depends on CPU fused and NB Pstate.
- //
- GnbLibPciRead (
- MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3xA0_ADDRESS),
- AccessWidth32,
- &D18F3xA0.Value,
- GnbLibGetHeader (Gfx)
- );
-
- if (D18F3xA0.Field.CofVidProg) {
-
- GnbLibPciRead (
- MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3xDC_ADDRESS),
- AccessWidth32,
- &D18F3xDC.Value,
- GnbLibGetHeader (Gfx)
- );
-
- GnbLibPciRead (
- MAKE_SBDFO ( 0, 0, 0x18, 6, D18F6x90_ADDRESS),
- AccessWidth32,
- &D18F6x90.Value,
- GnbLibGetHeader (Gfx)
- );
-
- //
- // Set ulMinimumNClk if (F6x90[NbPsCap]==1 && F6x90[NbPsCtrlDis]==0) then (
- // GfxLibGetMainPllFreq (...) / F6x90[NbPs1NclkDiv] divisor
- // ) else ( GfxLibGetMainPllFreq (...) / F3xDC[NbPs0NclkDiv] divisor
- // )
- //
- IntegratedInfoTable->ulMinimumNClk = GfxLibCalculateNclk (
- (UINT8) (((D18F6x90.Field.NbPsCap == 1) && (D18F6x90.Field.NbPsCtrlDis == 0)) ? D18F6x90.Field.NbPs1NclkDiv : D18F3xDC.Field.NbPs0NclkDiv),
- IntegratedInfoTable->ulDentistVCOFreq
- );
- } else {
- IntegratedInfoTable->ulMinimumNClk = 200 * 100;
- }
-
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.h b/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.h
deleted file mode 100644
index 51c4d43..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Service procedure to initialize Integrated Info Table
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _GFXINTEGRATEDINFOTABLE_H_
-#define _GFXINTEGRATEDINFOTABLE_H_
-
-
-#define SB_IOMAP_REGCD6 0x0CD6 // PM_Index
-#define SB_IOMAP_REGCD7 0x0CD7 // PM_Data
-#define SB_MMIO_BASE_REG 0x24 // PMIO register 0x24 has SB MMIO base
-#define SB_MMIO_DECODE_ENABLE BIT0
-#define SB_MMIO_IO_MAPPED_ENABLE BIT1
-
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxLib.c b/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxLib.c
deleted file mode 100644
index 70eeca8..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxLib.c
+++ /dev/null
@@ -1,364 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Initialize PP/DPM fuse table.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "heapManager.h"
-#include "Gnb.h"
-#include "GnbGfx.h"
-#include "GnbFuseTable.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include "GfxLib.h"
-#include "GnbRegistersON.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_GFX_GFXLIB_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Calculate main PLL VCO
- *
- *
- *
- * @param[in] StdHeader Standard configuration header
- * @retval main PLL COF in Mhz
- */
-
-UINT32
-GfxLibGetMainPllFreq (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 MainPllFreq;
- D18F3xD4_STRUCT D18F3xD4;
- GnbLibPciRead (
- MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3xD4_ADDRESS),
- AccessWidth32,
- &D18F3xD4.Value,
- StdHeader
- );
- if (D18F3xD4.Field.MainPllOpFreqIdEn == 1) {
- MainPllFreq = 100 * (D18F3xD4.Field.MainPllOpFreqId + 0x10);
- } else {
- MainPllFreq = 1600;
- }
- return MainPllFreq;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Calculate clock from main VCO
- *
- *
- *
- * @param[in] Did Fuse Divider
- * @param[in] MainPllVco Main Pll COF in 10KHz
- * @retval Clock in 10KHz
- */
-
-UINT32
-GfxLibCalculateClk (
- IN UINT8 Did,
- IN UINT32 MainPllVco
- )
-{
- UINT32 Divider;
- if (Did >= 8 && Did <= 0x3F) {
- Divider = Did * 25;
- } else if (Did > 0x3F && Did <= 0x5F) {
- Divider = (Did - 64) * 50 + 1600;
- } else if (Did > 0x5F && Did <= 0x7E) {
- Divider = (Did - 96) * 100 + 3200;
- } else if (Did == 0x7f) {
- Divider = 128 * 100;
- } else {
- ASSERT (FALSE);
- return 200 * 100;
- }
- ASSERT (Divider != 0);
- return (((MainPllVco * 100) + (Divider - 1)) / Divider);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Calculate did from main VCO
- *
- *
- *
- * @param[in] Vco Vco in 10Khz
- * @param[in] MainPllVco Main Pll COF in 10Khz
- * @retval DID
- */
-
-UINT8
-GfxLibCalculateDid (
- IN UINT32 Vco,
- IN UINT32 MainPllVco
- )
-{
- UINT32 Divider;
- UINT8 Did;
- ASSERT (Vco != 0);
- Divider = ((MainPllVco * 100) + (Vco - 1)) / Vco;
- Did = 0;
- if (Divider < 200) {
- } else if (Divider <= 1575) {
- Did = (UINT8) (Divider / 25);
- } else if (Divider <= 3150) {
- Did = (UINT8) ((Divider - 1600) / 50) + 64;
- } else if (Divider <= 6200) {
- Did = (UINT8) ((Divider - 3200) / 100) + 96;
- } else {
- Did = 0x7f;
- }
- return Did;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Check if GFX controller fused off
- *
- *
- * @param[in] StdHeader Standard configuration header
- * @retval TRUE Gfx controller present and available
- */
-BOOLEAN
-GfxLibIsControllerPresent (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- return GnbLibPciIsDevicePresent (MAKE_SBDFO (0, 0, 1, 0, 0), StdHeader);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get max non 0 VID index
- *
- *
- * @param[in] StdHeader Standard configuration header
- * @retval NBVDD VID index
- */
-UINT8
-GfxLibMaxVidIndex (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 MaxVid;
- UINT8 MaxVidIndex;
- UINT8 SclkVidArray[4];
- UINTN Index;
-
- GnbLibPciRead (
- MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS),
- AccessWidth32,
- &SclkVidArray[0],
- StdHeader
- );
- MaxVidIndex = 0;
- MaxVid = 0xff;
- for (Index = 0; Index < 4; Index++) {
- if (SclkVidArray[Index] != 0 && SclkVidArray[Index] < MaxVid) {
- MaxVid = SclkVidArray[Index];
- MaxVidIndex = (UINT8) Index;
- }
- }
- return MaxVidIndex;
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get min SCLK
- *
- *
- * @param[in] StdHeader Standard configuration header
- * @retval Min SCLK in 10 khz
- */
-UINT32
-GfxLibGetMinSclk (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 WrCkClk;
- UINT32 MinSclkClk;
- WrCkClk = GfxLibGetWrCk (StdHeader);
-
- if ((2 * WrCkClk) < (8 * 100)) {
- MinSclkClk = 8 * 100;
- } else {
- MinSclkClk = 2 * WrCkClk + 100;
- }
- return MinSclkClk;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get min WRCK
- *
- *
- * @param[in] StdHeader Standard configuration header
- * @retval Min WRCK in 10 khZ
- */
-UINT32
-GfxLibGetWrCk (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- PP_FUSE_ARRAY *PpFuseArray;
- UINT8 WrCk;
- PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader);
- ASSERT (PpFuseArray != NULL);
- if (PpFuseArray != NULL) {
- if (PpFuseArray->WrCkDid == 0x0) {
- WrCk = 2;
- } else if (PpFuseArray->WrCkDid <= 0x10) {
- WrCk = PpFuseArray->WrCkDid + 1;
- } else if (PpFuseArray->WrCkDid <= 0x1C) {
- WrCk = 24 + 8 * (PpFuseArray->WrCkDid - 0x10);
- } else {
- WrCk = 128;
- }
- } else {
- WrCk = 2;
- }
- return 100 * 100 / WrCk;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Calculate NCLK clock from main VCO
- *
- *
- *
- * @param[in] Did NCLK Divider
- * @param[in] MainPllVco Main Pll COF in 10KHz
- * @retval Clock in 10KHz
- */
-
-UINT32
-GfxLibCalculateNclk (
- IN UINT8 Did,
- IN UINT32 MainPllVco
- )
-{
- UINT32 Divider;
- if (Did >= 8 && Did <= 0x3F) {
- Divider = Did * 25;
- } else if (Did > 0x3F && Did <= 0x5F) {
- Divider = (Did - 64) * 50 + 1600;
- } else if (Did > 0x5F && Did <= 0x7F) {
- Divider = (Did - 64) * 100;
- } else {
- ASSERT (FALSE);
- return 200 * 100;
- }
- ASSERT (Divider != 0);
- return ((MainPllVco * 100) / Divider);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Calculate idle NCLK clock from main VCO
- *
- *
- *
- * @param[in] Did NCLK Divider
- * @param[in] MainPllVco Main Pll COF in 10KHz
- * @retval Clock in 10KHz
- */
-
-UINT32
-GfxLibCalculateIdleNclk (
- IN UINT8 Did,
- IN UINT32 MainPllVco
- )
-{
- UINT32 Divider;
- switch (Did) {
- case 0x20:
- Divider = 8;
- break;
- case 0x40:
- Divider = 16;
- break;
- case 0x60:
- Divider = 32;
- break;
- case 0x78:
- Divider = 56;
- break;
- case 0x7F:
- Divider = 128;
- break;
- default:
- ASSERT (FALSE);
- return 200 * 100;
- break;
- }
-
- return (MainPllVco / Divider);
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxLib.h b/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxLib.h
deleted file mode 100644
index 52beb6b..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxLib.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * various service procedures
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _GFXLIB_H_
-#define _GFXLIB_H_
-
-UINT32
-GfxLibGetMainPllFreq (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-UINT32
-GfxLibCalculateClk (
- IN UINT8 Did,
- IN UINT32 MainPllVco
- );
-
-UINT8
-GfxLibCalculateDid (
- IN UINT32 Vco,
- IN UINT32 MainPllVco
- );
-
-
-BOOLEAN
-GfxLibIsControllerPresent (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-UINT8
-GfxLibMaxVidIndex (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-UINT32
-GfxLibGetMinSclk (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-UINT32
-GfxLibGetWrCk (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-UINT32
-GfxLibCalculateNclk (
- IN UINT8 Did,
- IN UINT32 MainPllVco
- );
-
-UINT32
-GfxLibCalculateIdleNclk (
- IN UINT8 Did,
- IN UINT32 MainPllVco
- );
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxRegisterAcc.c b/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxRegisterAcc.c
deleted file mode 100644
index 5c341c7..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxRegisterAcc.c
+++ /dev/null
@@ -1,209 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Graphics controller access service routines.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Gnb.h"
-#include "GnbGfx.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include "GfxRegisterAcc.h"
-#include "GnbRegistersON.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_GFX_GFXREGISTERACC_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Write GMM register
- *
- *
- * @param[in] Address GMM register address
- * @param[in] Value Value
- * @param[in] S3Save Save for S3 resume
- * @param[in] Gfx Pointer to global GFX configuration
- */
-
-VOID
-GmmRegisterWrite (
- IN UINT16 Address,
- IN UINT32 Value,
- IN BOOLEAN S3Save,
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- ASSERT (Gfx->GmmBase != 0);
- GnbLibMemWrite (Gfx->GmmBase + Address, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Value, GnbLibGetHeader (Gfx));
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Read GMM register
- *
- *
- * @param[in] Address GMM register address
- * @param[in] Gfx Pointer to global GFX configuration
- * @retval Value of GMM register
- */
-
-UINT32
-GmmRegisterRead (
- IN UINT16 Address,
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- UINT32 Value;
- ASSERT (Gfx->GmmBase != 0);
- GnbLibMemRead (Gfx->GmmBase + Address, AccessWidth32, &Value, GnbLibGetHeader (Gfx));
- return Value;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Write GMM register field
- *
- *
- * @param[in] Address GMM register address
- * @param[in] FieldOffset Register field offset
- * @param[in] FieldWidth Register field width
- * @param[in] Value Field value
- * @param[in] S3Save Save for S3 resume
- * @param[in] Gfx Pointer to global GFX configuration
- */
-
-VOID
-GmmRegisterWriteField (
- IN UINT16 Address,
- IN UINT8 FieldOffset,
- IN UINT8 FieldWidth,
- IN UINT32 Value,
- IN BOOLEAN S3Save,
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- UINT32 Data;
- UINT32 Mask;
- Data = GmmRegisterRead (Address, Gfx);
- Mask = (1 << FieldWidth) - 1;
- Value &= Mask;
- Data &= (~(Mask << FieldOffset));
- GmmRegisterWrite (Address, Data | (Value << FieldOffset), S3Save, Gfx);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Write GMM registers table
- *
- *
- * @param[in] Table Pointer to table
- * @param[in] TableLength Number of entries in table
- * @param[in] S3Save Save for S3 resume
- * @param[in] Gfx Pointer to global GFX configuration
- */
-
-
-VOID
-GmmRegisterTableWrite (
- IN GMM_REG_ENTRY Table[],
- IN UINTN TableLength,
- IN BOOLEAN S3Save,
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- UINTN Index;
- for (Index = 0; Index < TableLength; Index++) {
- GmmRegisterWrite (Table[Index].GmmReg, Table[Index].GmmData, S3Save, Gfx);
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Copy memory content to FB
- *
- *
- * @param[in] Source Pointer to source
- * @param[in] FbOffset FB offset
- * @param[in] Length The length to copy
- * @param[in] Gfx Pointer to global GFX configuration
- *
- */
-VOID
-GfxLibCopyMemToFb (
- IN VOID *Source,
- IN UINT32 FbOffset,
- IN UINT32 Length,
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- GMMx00_STRUCT GMMx00;
- GMMx04_STRUCT GMMx04;
- UINT32 Index;
- for (Index = 0; Index < Length; Index = Index + 4 ) {
- GMMx00.Value = 0x80000000 | (FbOffset + Index);
- GMMx04.Value = *(UINT32*) ((UINT8*)Source + Index);
- GmmRegisterWrite (GMMx00_ADDRESS, GMMx00.Value, FALSE, Gfx);
- GmmRegisterWrite (GMMx04_ADDRESS, GMMx04.Value, FALSE, Gfx);
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxRegisterAcc.h b/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxRegisterAcc.h
deleted file mode 100644
index fffe426..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxRegisterAcc.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Graphics controller access service routines.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 38641 $ @e \$Date: 2010-09-27 23:16:17 +0800 (Mon, 27 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _GFXREGISTERACC_H_
-#define _GFXREGISTERACC_H_
-
-/// GMM Register Entry
-typedef struct {
- UINT16 GmmReg; ///< Register
- UINT32 GmmData; ///< Data
-} GMM_REG_ENTRY;
-
-/// Register to Register copy
-typedef struct {
- UINT32 CpuReg; ///< CPU Register
- UINT16 GmmReg; ///< GMM Register
- UINT8 CpuOffset; ///< CPU register field start bit
- UINT8 CpuWidth; ///< CPU register field width
- UINT8 GmmOffset; ///< GMM register field start bit
- UINT8 GmmWidth; ///< GMM register field width
-} REGISTER_COPY_ENTRY;
-
-
-/// Table length and table pointer
-typedef struct {
- UINT32 TableLength; ///< Table Length
- VOID* TablePtr; ///< Table Pointer
-} TABLE_INDIRECT_PTR;
-
-VOID
-GmmRegisterWrite (
- IN UINT16 Address,
- IN UINT32 Value,
- IN BOOLEAN S3Save,
- IN GFX_PLATFORM_CONFIG *Gfx
- );
-
-UINT32
-GmmRegisterRead (
- IN UINT16 Address,
- IN GFX_PLATFORM_CONFIG *Gfx
- );
-
-VOID
-GmmRegisterWriteField (
- IN UINT16 Address,
- IN UINT8 FieldOffset,
- IN UINT8 FieldWidth,
- IN UINT32 Value,
- IN BOOLEAN S3Save,
- IN GFX_PLATFORM_CONFIG *Gfx
- );
-
-
-VOID
-GmmRegisterTableWrite (
- IN GMM_REG_ENTRY Table[],
- IN UINTN TableLength,
- IN BOOLEAN S3Save,
- IN GFX_PLATFORM_CONFIG *Gfx
- );
-
-VOID
-GfxLibCopyMemToFb (
- IN VOID *Source,
- IN UINT32 FbOffset,
- IN UINT32 Length,
- IN GFX_PLATFORM_CONFIG *Gfx
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxStrapsInit.c b/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxStrapsInit.c
deleted file mode 100644
index 350e9b6..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxStrapsInit.c
+++ /dev/null
@@ -1,315 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Graphics controller BIF straps control services.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 40151 $ @e \$Date: 2010-10-20 06:38:17 +0800 (Wed, 20 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-//#include "heapManager.h"
-#include "Gnb.h"
-#include "GnbGfx.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include "GfxStrapsInit.h"
-#include "GfxLib.h"
-#include "GfxRegisterAcc.h"
-#include "NbSmuLib.h"
-#include "OptionGnb.h"
-#include "GnbRegistersON.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_GFX_GFXSTRAPSINIT_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-extern BUILD_OPT_CFG UserOptions;
-extern GNB_BUILD_OPTIONS GnbBuildOptions;
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init Gfx SSID Registers
- *
- *
- *
- * @param[in] Gfx Pointer to global GFX configuration
- * @retval AGESA_STATUS Always succeeds
- */
-
-AGESA_STATUS
-GfxInitSsid (
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- AGESA_STATUS Status;
- UINT32 TempData;
- PCI_ADDR IgpuAddress;
- PCI_ADDR HdaudioAddress;
-
- Status = AGESA_SUCCESS;
- TempData = 0;
-
- IgpuAddress = Gfx->GfxPciAddress;
- HdaudioAddress = Gfx->GfxPciAddress;
- HdaudioAddress.Address.Function = 1;
-
- // Set SSID for internal GPU
- if (UserOptions.CfgGnbIGPUSSID != 0) {
- GnbLibPciRMW ((IgpuAddress.AddressValue | 0x4C), AccessS3SaveWidth32, 0, UserOptions.CfgGnbIGPUSSID, GnbLibGetHeader (Gfx));
- } else {
- GnbLibPciRead (IgpuAddress.AddressValue, AccessS3SaveWidth32, &TempData, GnbLibGetHeader (Gfx));
- GnbLibPciRMW ((IgpuAddress.AddressValue | 0x4C), AccessS3SaveWidth32, 0, TempData, GnbLibGetHeader (Gfx));
- }
-
- // Set SSID for internal HD Audio
- if (UserOptions.CfgGnbHDAudioSSID != 0) {
- GnbLibPciRMW ((HdaudioAddress.AddressValue | 0x4C), AccessS3SaveWidth32, 0, UserOptions.CfgGnbHDAudioSSID, GnbLibGetHeader (Gfx));
- } else {
- GnbLibPciRead (HdaudioAddress.AddressValue, AccessS3SaveWidth32, &TempData, GnbLibGetHeader (Gfx));
- GnbLibPciRMW ((HdaudioAddress.AddressValue | 0x4C), AccessS3SaveWidth32, 0, TempData, GnbLibGetHeader (Gfx));
- }
-
- return Status;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Initialize GFX straps.
- *
- *
- * @param[in] Gfx Pointer to global GFX configuration
- * @retval AGESA_STATUS
- */
-
-AGESA_STATUS
-GfxStrapsInit (
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- D0F0x64_x1C_STRUCT D0F0x64_x1C;
- D0F0x64_x1D_STRUCT D0F0x64_x1D;
- IDS_HDT_CONSOLE (GNB_TRACE, "GfxStrapsInit Enter\n");
-
- GnbLibPciIndirectRead (
- GNB_SBDFO | D0F0x60_ADDRESS,
- D0F0x64_x1C_ADDRESS | IOC_WRITE_ENABLE,
- AccessWidth32,
- &D0F0x64_x1C.Value,
- GnbLibGetHeader (Gfx)
- );
-
- GnbLibPciIndirectRead (
- GNB_SBDFO | D0F0x60_ADDRESS,
- D0F0x64_x1D_ADDRESS | IOC_WRITE_ENABLE,
- AccessWidth32,
- &D0F0x64_x1D.Value,
- GnbLibGetHeader (Gfx)
- );
-
- D0F0x64_x1C.Field.AudioNonlegacyDeviceTypeEn = 0x0;
- D0F0x64_x1C.Field.F0NonlegacyDeviceTypeEn = 0x0;
-
- if (Gfx->GfxControllerMode == GfxControllerLegacyBridgeMode) {
- D0F0x64_x1D.Field.IntGfxAsPcieEn = 0x0;
- D0F0x64_x1C.Field.RcieEn = 0x0;
- } else {
- D0F0x64_x1D.Field.IntGfxAsPcieEn = 0x1;
- D0F0x64_x1C.Field.RcieEn = 0x1;
- //LN/ON A0 (MSI)
- GnbLibPciRMW (MAKE_SBDFO (0, 0, 1, 0, 0x4), AccessS3SaveWidth32, 0xffffffff, BIT2, GnbLibGetHeader (Gfx));
- }
- if (Gfx->ForceGfxMode == GfxEnableForceSecondary) {
- D0F0x64_x1D.Field.VgaEn = 0x0;
- } else {
- D0F0x64_x1D.Field.VgaEn = 0x1;
- }
- D0F0x64_x1C.Field.AudioEn = Gfx->GnbHdAudio;
- D0F0x64_x1C.Field.F0En = 0x1;
- D0F0x64_x1C.Field.RegApSize = 0x1;
-
- if (Gfx->UmaInfo.UmaSize > 128 * 0x100000) {
- D0F0x64_x1C.Field.MemApSize = 0x1;
- } else if (Gfx->UmaInfo.UmaSize > 64 * 0x100000) {
- D0F0x64_x1C.Field.MemApSize = 0x0;
- } else if (Gfx->UmaInfo.UmaSize > 32 * 0x100000) {
- D0F0x64_x1C.Field.MemApSize = 0x2;
- } else {
- D0F0x64_x1C.Field.MemApSize = 0x3;
- }
- GnbLibPciIndirectWrite (
- GNB_SBDFO | D0F0x60_ADDRESS,
- D0F0x64_x1D_ADDRESS | IOC_WRITE_ENABLE,
- AccessS3SaveWidth32,
- &D0F0x64_x1D.Value,
- GnbLibGetHeader (Gfx)
- );
-
- GnbLibPciIndirectWrite (
- GNB_SBDFO | D0F0x60_ADDRESS,
- D0F0x64_x1C_ADDRESS | IOC_WRITE_ENABLE,
- AccessS3SaveWidth32,
- &D0F0x64_x1C.Value,
- GnbLibGetHeader (Gfx)
- );
-
- D0F0x64_x1C.Field.WriteDis = 0x1;
-
- GnbLibPciIndirectWrite (
- GNB_SBDFO | D0F0x60_ADDRESS,
- D0F0x64_x1C_ADDRESS | IOC_WRITE_ENABLE,
- AccessS3SaveWidth32,
- &D0F0x64_x1C.Value,
- GnbLibGetHeader (Gfx)
- );
- IDS_HDT_CONSOLE (GNB_TRACE, "GfxStrapsInit Exit\n");
- return AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Disable integrated GFX controller
- *
- *
- * @param[in] StdHeader Standard configuration header
- */
-
-VOID
-GfxDisableController (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- FCRxFF30_0AE6_STRUCT FCRxFF30_0AE6;
- D18F6x90_STRUCT D18F6x90;
- IDS_HDT_CONSOLE (GNB_TRACE, "GfxDisableController Enter\n");
- GnbLibPciRMW (
- GNB_SBDFO | D0F0x7C_ADDRESS,
- AccessS3SaveWidth32,
- 0xffffffff,
- 1 << D0F0x7C_ForceIntGFXDisable_OFFSET,
- StdHeader
- );
-
- // With iGPU is disabled, Program D18F6x90[NbPs1GnbSlowIgn]=1
- GnbLibPciRead (
- MAKE_SBDFO ( 0, 0, 0x18, 6, D18F6x90_ADDRESS),
- AccessWidth32,
- &D18F6x90.Value,
- StdHeader
- );
- D18F6x90.Field.NbPs1GnbSlowIgn = 0x1;
- GnbLibPciWrite (
- MAKE_SBDFO ( 0, 0, 0x18, 6, D18F6x90_ADDRESS),
- AccessWidth32,
- &D18F6x90.Value,
- StdHeader
- );
-
- // With iGPU is disabled, Enable stutter without gmc power gating.
- NbSmuSrbmRegisterRead (FCRxFF30_0AE6_ADDRESS, &FCRxFF30_0AE6.Value, StdHeader);
- FCRxFF30_0AE6.Field.StctrlStutterEn = 0x1;
- NbSmuSrbmRegisterWrite (FCRxFF30_0AE6_ADDRESS, &FCRxFF30_0AE6.Value, TRUE, StdHeader);
- IDS_HDT_CONSOLE (GNB_TRACE, "GfxDisableController Exit\n");
-}
-
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Request GFX boot up voltage
- *
- *
- * @param[in] Gfx Pointer to global GFX configuration
- * @retval AGESA_STATUS
- */
-
-AGESA_STATUS
-GfxSetBootUpVoltage (
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- GMMx770_STRUCT GMMx770;
- GMMx774_STRUCT GMMx774;
- IDS_HDT_CONSOLE (GNB_TRACE, "GfxSetBootUpVoltage Enter\n");
-
- GMMx770.Value = GmmRegisterRead (GMMx770_ADDRESS, Gfx);
- GMMx770.Field.VoltageChangeEn = 1;
- GmmRegisterWrite (GMMx770_ADDRESS, GMMx770.Value, TRUE, Gfx);
- GMMx770.Field.VoltageLevel = GfxLibMaxVidIndex (GnbLibGetHeader (Gfx));
- GMMx770.Field.VoltageChangeReq = !GMMx770.Field.VoltageChangeReq;
- GmmRegisterWrite (GMMx770_ADDRESS, GMMx770.Value, TRUE, Gfx);
- do {
- GMMx774.Value = GmmRegisterRead (GMMx774_ADDRESS, Gfx);
- } while (GMMx774.Field.VoltageChangeAck != GMMx770.Field.VoltageChangeReq);
- IDS_HDT_CONSOLE (GNB_TRACE, "GfxSetBootUpVoltage Exit\n");
- return AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Set idle voltage mode for GFX
- *
- *
- * @param[in] Gfx Pointer to global GFX configuration
- */
-
-VOID
-GfxSetIdleVoltageMode (
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxStrapsInit.h b/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxStrapsInit.h
deleted file mode 100644
index 9954934..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Gfx/GfxStrapsInit.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Graphics controller BIF straps control services.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 40151 $ @e \$Date: 2010-10-20 06:38:17 +0800 (Wed, 20 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-#ifndef _GFXSTRAPSINIT_H_
-#define _GFXSTRAPSINIT_H_
-
-AGESA_STATUS
-GfxInitSsid (
- IN GFX_PLATFORM_CONFIG *Gfx
- );
-
-AGESA_STATUS
-GfxStrapsInit (
- IN GFX_PLATFORM_CONFIG *Gfx
- );
-
-VOID
-GfxDisableController (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-
-AGESA_STATUS
-GfxSetBootUpVoltage (
- IN GFX_PLATFORM_CONFIG *Gfx
- );
-
-VOID
-GfxSetIdleVoltageMode (
- IN GFX_PLATFORM_CONFIG *Gfx
- );
-
-#endif
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/GnbInitAtEarly.c b/src/vendorcode/amd/agesa/Proc/GNB/GnbInitAtEarly.c
deleted file mode 100644
index 730a500..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/GnbInitAtEarly.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * GNB early init interface
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 40151 $ @e \$Date: 2010-10-20 06:38:17 +0800 (Wed, 20 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "Gnb.h"
-
-#include "OptionGnb.h"
-#include "GnbLibFeatures.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_GNBINITATEARLY_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-extern OPTION_GNB_CONFIGURATION GnbEarlyFeatureTable[];
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init GNB at Early
- *
- *
- *
- * @param[in,out] EarlyParamsPtr Pointer to early configuration params.
- * @retval Initialization status.
- */
-AGESA_STATUS
-GnbInitAtEarly (
- IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr
- )
-{
- AGESA_STATUS Status;
- Status = GnbLibDispatchFeatures (&GnbEarlyFeatureTable[0], &EarlyParamsPtr->StdHeader);
- return Status;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/GnbInitAtEnv.c b/src/vendorcode/amd/agesa/Proc/GNB/GnbInitAtEnv.c
deleted file mode 100644
index cb632c8..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/GnbInitAtEnv.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * GNB env init interface
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 41504 $ @e \$Date: 2010-11-05 21:59:13 +0800 (Fri, 05 Nov 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Gnb.h"
-#include "OptionGnb.h"
-#include "GnbLibFeatures.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_GNBINITATENV_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-extern OPTION_GNB_CONFIGURATION GnbEnvFeatureTable[];
-extern BUILD_OPT_CFG UserOptions;
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Default constructor of GNB configuration at Env
- *
- *
- *
- * @param[in] GnbEnvConfigPtr Pointer to gnb env configuration params.
- * @param[in] EnvParamsPtr Pointer to env configuration params.
- */
-VOID
-GnbInitDataStructAtEnvDef (
- IN OUT GNB_ENV_CONFIGURATION *GnbEnvConfigPtr,
- IN AMD_ENV_PARAMS *EnvParamsPtr
- )
-{
- GnbEnvConfigPtr->Gnb3dStereoPinIndex = UserOptions.CfgGnb3dStereoPinIndex;
- GnbEnvConfigPtr->LvdsSpreadSpectrum = UserOptions.CfgLvdsSpreadSpectrum;
- GnbEnvConfigPtr->LvdsSpreadSpectrumRate = UserOptions.CfgLvdsSpreadSpectrumRate;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init GNB at Env
- *
- *
- *
- * @param[in] EnvParamsPtr Pointer to env configuration params.
- * @retval Initialization status.
- */
-
-AGESA_STATUS
-GnbInitAtEnv (
- IN AMD_ENV_PARAMS *EnvParamsPtr
- )
-{
- AGESA_STATUS Status;
- Status = GnbLibDispatchFeatures (&GnbEnvFeatureTable[0], &EnvParamsPtr->StdHeader);
- return Status;
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/GnbInitAtLate.c b/src/vendorcode/amd/agesa/Proc/GNB/GnbInitAtLate.c
deleted file mode 100644
index 2d3f8fc..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/GnbInitAtLate.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * GNB late init interface
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 40151 $ @e \$Date: 2010-10-20 06:38:17 +0800 (Wed, 20 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Gnb.h"
-#include "OptionGnb.h"
-#include "GnbLibFeatures.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_GNBINITATLATE_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-extern OPTION_GNB_CONFIGURATION GnbLateFeatureTable[];
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init GNB at Late post
- *
- *
- *
- * @param[in,out] LateParamsPtr Pointer to late configuration params.
- * @retval Initialization status.
- */
-
-AGESA_STATUS
-GnbInitAtLate (
- IN OUT AMD_LATE_PARAMS *LateParamsPtr
- )
-{
- AGESA_STATUS Status;
- Status = GnbLibDispatchFeatures (&GnbLateFeatureTable[0], &LateParamsPtr->StdHeader);
- return Status;
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/GnbInitAtMid.c b/src/vendorcode/amd/agesa/Proc/GNB/GnbInitAtMid.c
deleted file mode 100644
index 867691b..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/GnbInitAtMid.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * GNB mid init interface
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 40151 $ @e \$Date: 2010-10-20 06:38:17 +0800 (Wed, 20 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Gnb.h"
-#include "OptionGnb.h"
-#include "GnbLibFeatures.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_GNBINITATMID_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-extern OPTION_GNB_CONFIGURATION GnbMidFeatureTable[];
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init GNB at Mid post
- *
- *
- *
- * @param[in,out] MidParamsPtr Pointer to mid configuration params.
- * @retval Initialization status.
- */
-
-AGESA_STATUS
-GnbInitAtMid (
- IN OUT AMD_MID_PARAMS *MidParamsPtr
- )
-{
- AGESA_STATUS Status;
- Status = GnbLibDispatchFeatures (&GnbMidFeatureTable[0], &MidParamsPtr->StdHeader);
- return Status;
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/GnbInitAtPost.c b/src/vendorcode/amd/agesa/Proc/GNB/GnbInitAtPost.c
deleted file mode 100644
index bbb26c6..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/GnbInitAtPost.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * GNB POST init interface
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 40151 $ @e \$Date: 2010-10-20 06:38:17 +0800 (Wed, 20 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Gnb.h"
-#include "OptionGnb.h"
-#include "Ids.h"
-#include "GnbLibFeatures.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_GNBINITATPOST_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-extern OPTION_GNB_CONFIGURATION GnbPostFeatureTable[];
-extern OPTION_GNB_CONFIGURATION GnbPostAfterDramFeatureTable[];
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init GNB at Post
- *
- *
- *
- * @param[in] PostParamsPtr Pointer to post configuration parameters
- * @retval Initialization status.
- */
-
-AGESA_STATUS
-GnbInitAtPost (
- IN OUT AMD_POST_PARAMS *PostParamsPtr
- )
-{
- AGESA_STATUS Status;
- Status = GnbLibDispatchFeatures (&GnbPostFeatureTable[0], &PostParamsPtr->StdHeader);
- return Status;
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init GNB at Post after DRAM init
- *
- *
- *
- * @param[in] PostParamsPtr Pointer to post configuration parameters
- * @retval Initialization status.
- */
-
-AGESA_STATUS
-GnbInitAtPostAfterDram (
- IN OUT AMD_POST_PARAMS *PostParamsPtr
- )
-{
- AGESA_STATUS Status;
- Status = GnbLibDispatchFeatures (&GnbPostAfterDramFeatureTable[0], &PostParamsPtr->StdHeader);
- return Status;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/GnbInitAtReset.c b/src/vendorcode/amd/agesa/Proc/GNB/GnbInitAtReset.c
deleted file mode 100644
index 7210489..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/GnbInitAtReset.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * GNB reset init interface
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Gnb.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_GNBINITATRESET_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init GNB at Reset
- *
- *
- *
- * @param[in] StdHeader Standard configuration header
- * @retval AGESA_STATUS
- */
-
-AGESA_STATUS
-GnbInitAtReset (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_STATUS Status;
- Status = AGESA_SUCCESS;
-
- return Status;
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/GnbPage.h b/src/vendorcode/amd/agesa/Proc/GNB/GnbPage.h
deleted file mode 100644
index fec1603..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/GnbPage.h
+++ /dev/null
@@ -1,1858 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Create outline and references for GNB Component mainpage documentation.
- *
- * Design guides, maintenance guides, and general documentation, are
- * collected using this file onto the documentation mainpage.
- * This file contains doxygen comment blocks, only.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Documentation
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/**
- * @page F12PcieLaneDescription Family 0x12 PCIe/DDI Lanes
- * <TABLE border="0">
- * <TR><TD class="indexkey" width=160> Lane ID</TD><TD class="indexkey">Lane group</TD><TD class="indexkey">Pin</TD></TR>
- * <TR><TD class="indexvalue" > 0 </TD><TD class="indexvalue">SB </TD><TD class="indexvalue">P_SB_RX[P/N]/TX[P/N][0]</TD></TR>
- * <TR><TD class="indexvalue" > 1 </TD><TD class="indexvalue">SB </TD><TD class="indexvalue">P_SB_RX[P/N]/TX[P/N][1]</TD></TR>
- * <TR><TD class="indexvalue" > 2 </TD><TD class="indexvalue">SB </TD><TD class="indexvalue">P_SB_RX[P/N]/TX[P/N][2]</TD></TR>
- * <TR><TD class="indexvalue" > 3 </TD><TD class="indexvalue">SB </TD><TD class="indexvalue">P_SB_RX[P/N]/TX[P/N][3]</TD></TR>
- * <TR><TD class="indexvalue" > 4 </TD><TD class="indexvalue">GPP</TD><TD class="indexvalue">P_GPP_RX[P/N]/TX[P/N][0]</TD></TR>
- * <TR><TD class="indexvalue" > 5 </TD><TD class="indexvalue">GPP</TD><TD class="indexvalue">P_GPP_RX[P/N]/TX[P/N][1]</TD></TR>
- * <TR><TD class="indexvalue" > 6 </TD><TD class="indexvalue">GPP</TD><TD class="indexvalue">P_GPP_RX[P/N]/TX[P/N][2]</TD></TR>
- * <TR><TD class="indexvalue" > 7 </TD><TD class="indexvalue">GPP</TD><TD class="indexvalue">P_GPP_RX[P/N]/TX[P/N][3]</TD></TR>
- * <TR><TD class="indexvalue" > 8 </TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][0]</TD></TR>
- * <TR><TD class="indexvalue" > 9 </TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][1]</TD></TR>
- * <TR><TD class="indexvalue" > 10</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][2]</TD></TR>
- * <TR><TD class="indexvalue" > 11</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][3]</TD></TR>
- * <TR><TD class="indexvalue" > 12</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][4]</TD></TR>
- * <TR><TD class="indexvalue" > 13</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][5]</TD></TR>
- * <TR><TD class="indexvalue" > 14</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][6]</TD></TR>
- * <TR><TD class="indexvalue" > 15</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][7]</TD></TR>
- * <TR><TD class="indexvalue" > 16</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][8]</TD></TR>
- * <TR><TD class="indexvalue" > 17</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][9]</TD></TR>
- * <TR><TD class="indexvalue" > 18</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][10]</TD></TR>
- * <TR><TD class="indexvalue" > 19</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][11]</TD></TR>
- * <TR><TD class="indexvalue" > 20</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][12]</TD></TR>
- * <TR><TD class="indexvalue" > 21</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][13]</TD></TR>
- * <TR><TD class="indexvalue" > 22</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][14]</TD></TR>
- * <TR><TD class="indexvalue" > 23</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][15]</TD></TR>
- * <TR><TD class="indexvalue" > 24</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP1_TXP/N[0]</TD></TR>
- * <TR><TD class="indexvalue" > 25</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP1_TXP/N[1]</TD></TR>
- * <TR><TD class="indexvalue" > 26</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP1_TXP/N[2]</TD></TR>
- * <TR><TD class="indexvalue" > 27</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP1_TXP/N[3]</TD></TR>
- * <TR><TD class="indexvalue" > 28</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP0_TXP/N[0]</TD></TR>
- * <TR><TD class="indexvalue" > 29</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP0_TXP/N[1]</TD></TR>
- * <TR><TD class="indexvalue" > 30</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP0_TXP/N[2]</TD></TR>
- * <TR><TD class="indexvalue" > 31</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP0_TXP/N[3]</TD></TR>
- * </TABLE>
- *
- */
-
-
-/**
- * @page F14PcieLaneDescription Family 0x14 PCIe/DDI Lanes
- * <TABLE border="0">
- * <TR><TD class="indexkey" width=160> Lane ID</TD><TD class="indexkey">Lane group</TD><TD class="indexkey">Pin</TD></TR>
- * <TR><TD class="indexvalue" > 0 </TD><TD class="indexvalue">SB </TD><TD class="indexvalue">P_SB_RX[P/N]/TX[P/N][0]</TD></TR>
- * <TR><TD class="indexvalue" > 1 </TD><TD class="indexvalue">SB </TD><TD class="indexvalue">P_SB_RX[P/N]/TX[P/N][1]</TD></TR>
- * <TR><TD class="indexvalue" > 2 </TD><TD class="indexvalue">SB </TD><TD class="indexvalue">P_SB_RX[P/N]/TX[P/N][2]</TD></TR>
- * <TR><TD class="indexvalue" > 3 </TD><TD class="indexvalue">SB </TD><TD class="indexvalue">P_SB_RX[P/N]/TX[P/N][3]</TD></TR>
- * <TR><TD class="indexvalue" > 4 </TD><TD class="indexvalue">GPP</TD><TD class="indexvalue">P_GPP_RX[P/N]/TX[P/N][0]</TD></TR>
- * <TR><TD class="indexvalue" > 5 </TD><TD class="indexvalue">GPP</TD><TD class="indexvalue">P_GPP_RX[P/N]/TX[P/N][1]</TD></TR>
- * <TR><TD class="indexvalue" > 6 </TD><TD class="indexvalue">GPP</TD><TD class="indexvalue">P_GPP_RX[P/N]/TX[P/N][2]</TD></TR>
- * <TR><TD class="indexvalue" > 7 </TD><TD class="indexvalue">GPP</TD><TD class="indexvalue">P_GPP_RX[P/N]/TX[P/N][3]</TD></TR>
- * <TR><TD class="indexvalue" > 8</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP0_TXP/N[0]</TD></TR>
- * <TR><TD class="indexvalue" > 9</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP0_TXP/N[1]</TD></TR>
- * <TR><TD class="indexvalue" > 10</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP0_TXP/N[2]</TD></TR>
- * <TR><TD class="indexvalue" > 11</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP0_TXP/N[3]</TD></TR>
- * <TR><TD class="indexvalue" > 12</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP1_TXP/N[0]</TD></TR>
- * <TR><TD class="indexvalue" > 13</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP1_TXP/N[1]</TD></TR>
- * <TR><TD class="indexvalue" > 14</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP1_TXP/N[2]</TD></TR>
- * <TR><TD class="indexvalue" > 15</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP1_TXP/N[3]</TD></TR>
- * </TABLE>
- *
- */
-
-
-/**
- * @page F12DualLinkDviDescription Family 0x12 Dual Link DVI connector description
- * Examples of various Dual Link DVI descriptors.
- * @code
- * // Dual Link DVI on dedicated display lanes. DP1_TXP/N[0]..DP1_TXP/N[3] - master, DP0_TXP/N[0]..DP0_TXP/N[3] - slave.
- * PCIe_PORT_DESCRIPTOR DdiList [] = {
- * {
- * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
- * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 32),
- * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0)
- * }
- * }
- * // Dual Link DVI on dedicated display lanes. DP0_TXP/N[0]..DP0_TXP/N[3] - master, DP1_TXP/N[0]..DP1_TXP/N[3] - slave.
- * PCIe_PORT_DESCRIPTOR DdiList [] = {
- * {
- * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
- * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 24),
- * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0)
- * }
- * }
- * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[0]..P_GFX_TXP/N[3] - master, P_GFX_TXP/N[4]..P_GFX_TXP/N[7] - slave.
- * PCIe_PORT_DESCRIPTOR DdiList [] = {
- * {
- * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
- * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 15),
- * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0)
- * }
- * }
- * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[7]..P_GFX_TXP/N[4] - master, P_GFX_TXP/N[0]..P_GFX_TXP/N[3] - slave.
- * PCIe_PORT_DESCRIPTOR DdiList [] = {
- * {
- * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
- * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 15, 8),
- * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0)
- * }
- * }
- * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[8]..P_GFX_TXP/N[11] - master, P_GFX_TXP/N[12]..P_GFX_TXP/N[15] - slave.
- * PCIe_PORT_DESCRIPTOR DdiList [] = {
- * {
- * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
- * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 23),
- * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0)
- * }
- * }
- * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[12]..P_GFX_TXP/N[15] - master, P_GFX_TXP/N[8]..P_GFX_TXP/N[11] - slave.
- * PCIe_PORT_DESCRIPTOR DdiList [] = {
- * {
- * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags
- * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 23, 16),
- * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0)
- * }
- * }
- * @endcode
- */
-
-
-/**
- * @page gnbmain GNB Component Documentation
- *
- * Additional documentation for the GNB component consists of
- *
- * - Maintenance Guides:
- * - @subpage F12PcieLaneDescription "Family 0x12 PCIe/DDI Lane description table"
- * - @subpage F14PcieLaneDescription "Family 0x14 PCIe/DDI Lane description table"
- * - @subpage F12LaneConfigurations "Family 0x12 PCIe port/DDI link configurations"
- * - @subpage F14LaneConfigurations "Family 0x14 PCIe port/DDI link configurations"
- * - @subpage F12DualLinkDviDescription "Family 0x12 Dual Link DVI connector description"
- * - add here >>>
- * - Design Guides:
- * - add here >>>
- *
- */
-
-
-/**
- * @page F12LaneConfigurations Family 0x12 PCIe port/DDI link configurations
- *
- *<div class=Section1>
- *
- *<p class=MsoNormal><span style='font-size:14.0pt;line-height:115%'>PCIe port configurations
- *for lanes 8 through 23. </span></p>
- *
- *<table class=MsoTableGrid border=1 cellspacing=0 cellpadding=0
- * style='border-collapse:collapse;border:none'>
- * <tr>
- * <td width=208 valign=top style='width:125.0pt;border:solid windowtext 1.5pt;
- * background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
- * normal'>Configuration</p>
- * </td>
- * <td width=168 valign=top style='width:100.9pt;border:solid windowtext 1.5pt;
- * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>PCIe Port Device Number</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border:solid windowtext 1.5pt;
- * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Start Lane (Start Lane in reverse
- * configuration)</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border:solid windowtext 1.5pt;
- * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>End Line (End lane in reverse
- * configuration)</p>
- * </td>
- * </tr>
- * <tr style='height:15.15pt'>
- * <td width=208 valign=top style='width:125.0pt;border-top:none;border-left:
- * solid windowtext 1.5pt;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:15.15pt'>
- * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
- * normal'>Config A</p>
- * </td>
- * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:15.15pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>2</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:15.15pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>8(23)</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:15.15pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>23(8)</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=208 rowspan=14 valign=top style='width:125.0pt;border:solid windowtext 1.5pt;
- * border-top:none;padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
- * normal'>Config B</p>
- * </td>
- * <td width=168 rowspan=7 valign=top style='width:100.9pt;border-top:none;
- * border-left:none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>2</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>8(15)</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>15(8)</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>8(11)</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>11(8)</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>8(9)</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>9(8)</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>10(11)</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>11(10)</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>12(15)</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>15(12)</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>12(13)</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>13(12)</p>
- * </td>
- * </tr>
- * <tr style='height:15.25pt'>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:15.25pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>14(15)</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:15.25pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>15(14)</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=168 rowspan=7 valign=top style='width:100.9pt;border-top:none;
- * border-left:none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>3</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>16(23)</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>23(16)</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>16(19)</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>19(16)</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>16(17)</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>17(16)</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>18(19)</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>19(18)</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>20(23)</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>23(20)</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>20(21)</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>21(20)</p>
- * </td>
- * </tr>
- * <tr style='height:15.25pt'>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:15.25pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>22(23)</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:15.25pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>23(22)</p>
- * </td>
- * </tr>
- *</table>
- *
- *<p class=MsoNormal> </p>
- *
- *<p class=MsoNormal><span style='font-size:14.0pt;line-height:115%'>PCIe port configurations
- *for lanes 4 through 7.</span></p>
- *
- *<table class=MsoTableGrid border=1 cellspacing=0 cellpadding=0
- * style='border-collapse:collapse;border:none'>
- * <tr>
- * <td width=208 valign=top style='width:125.0pt;border:solid windowtext 1.5pt;
- * background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
- * normal'>Configuration</p>
- * </td>
- * <td width=168 valign=top style='width:100.9pt;border:solid windowtext 1.5pt;
- * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>PCIe Port Device Number</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border:solid windowtext 1.5pt;
- * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Start Lane (Start Lane in reverse
- * configuration)</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border:solid windowtext 1.5pt;
- * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>End Line (End lane in reverse
- * configuration)</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=208 rowspan=2 valign=top style='width:125.0pt;border:solid windowtext 1.5pt;
- * border-top:none;padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
- * normal'>Config A</p>
- * </td>
- * <td width=168 rowspan=2 valign=top style='width:100.9pt;border-top:none;
- * border-left:none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>4</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>4(7)</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>7(4)</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'> </p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'> </p>
- * </td>
- * </tr>
- * <tr>
- * <td width=208 rowspan=6 valign=top style='width:125.0pt;border-top:none;
- * border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt;
- * border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
- * normal'>Config B</p>
- * </td>
- * <td width=168 rowspan=3 valign=top style='width:100.9pt;border-top:none;
- * border-left:none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>4</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>4(5)</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>5(4)</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>4</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>4</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>5</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>5</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=168 rowspan=3 valign=top style='width:100.9pt;border-top:none;
- * border-left:none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>5</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>6(7)</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>7(6)</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>6</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>6</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>7</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>7</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=208 rowspan=5 valign=top style='width:125.0pt;border-top:none;
- * border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt;
- * border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
- * normal'>Config C</p>
- * </td>
- * <td width=168 rowspan=3 valign=top style='width:100.9pt;border-top:none;
- * border-left:none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>4</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>4(5)</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>5(4)</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>4</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>4</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>5</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>5</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>5</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>6</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>6</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>6</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>7</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>7</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=208 rowspan=4 valign=top style='width:125.0pt;border:solid windowtext 1.5pt;
- * border-top:none;padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
- * normal'>Config D</p>
- * </td>
- * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>4</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>4</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>4</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>5</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>5</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>5</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>6</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>6</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>6</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>7</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>7</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>7</p>
- * </td>
- * </tr>
- *</table>
- *
- *<p class=MsoNormal> </p>
- *<p class=MsoNormal> </p>
- *
- *<p class=MsoNormal><span style='font-size:14.0pt;line-height:115%'>DDI link configurations
- *for lanes 24 through 31.</span></p>
- *
- *<table class=MsoTableGrid border=1 cellspacing=0 cellpadding=0
- * style='border-collapse:collapse;border:none'>
- * <tr>
- * <td width=208 valign=top style='width:125.0pt;border:solid windowtext 1.5pt;
- * background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
- * normal'>Configuration</p>
- * </td>
- * <td width=168 valign=top style='width:100.9pt;border:solid windowtext 1.5pt;
- * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Connector type</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border:solid windowtext 1.5pt;
- * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Start Lane (Start Lane in reverse
- * configuration)</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border:solid windowtext 1.5pt;
- * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>End Line (End lane in reverse
- * configuration)</p>
- * </td>
- * </tr>
- * <tr style='height:28.35pt'>
- * <td width=208 valign=top style='width:125.0pt;border-top:none;border-left:
- * solid windowtext 1.5pt;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:28.35pt'>
- * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
- * normal'>Config A</p>
- * </td>
- * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:28.35pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Dual Link DVI-D</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:28.35pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>24(31)</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:28.35pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>31(24)</p>
- * </td>
- * </tr>
- * <tr style='height:95.0pt'>
- * <td width=208 rowspan=2 valign=top style='width:125.0pt;border:solid windowtext 1.5pt;
- * border-top:none;padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
- * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
- * normal'>Config B</p>
- * </td>
- * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>HDMI</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Single Link DVI-D</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>DP </p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>eDP</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Travis DP-to-CRT</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Travis DP-to-LVDS</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Hudson2 DP-to-CRT </p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>24</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>27</p>
- * </td>
- * </tr>
- * <tr style='height:95.0pt'>
- * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>HDMI</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Single Link DVI-D</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>DP </p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>eDP</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Travis DP-to-CRT</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Travis DP-to-LVDS</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Hudson2 DP-to-CRT</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>28</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>31</p>
- * </td>
- * </tr>
- *</table>
- *
- *<p class=MsoNormal> </p>
- *
- *<p class=MsoNormal><span style='font-size:14.0pt;line-height:115%'>DDI link configurations
- *for lanes 8 through 23.</span></p>
- *
- *<table class=MsoTableGrid border=1 cellspacing=0 cellpadding=0
- * style='border-collapse:collapse;border:none'>
- * <tr>
- * <td width=208 valign=top style='width:125.0pt;border:solid windowtext 1.5pt;
- * background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
- * normal'>Configuration</p>
- * </td>
- * <td width=168 valign=top style='width:100.9pt;border:solid windowtext 1.5pt;
- * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Connector type</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border:solid windowtext 1.5pt;
- * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Start Lane (Start Lane in reverse
- * configuration)</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border:solid windowtext 1.5pt;
- * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>End Line (End lane in reverse
- * configuration)</p>
- * </td>
- * </tr>
- * <tr style='height:16.05pt'>
- * <td width=208 valign=top style='width:125.0pt;border-top:none;border-left:
- * solid windowtext 1.5pt;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:16.05pt'>
- * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
- * normal'>Config A</p>
- * </td>
- * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:16.05pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Dual Link DVI-D</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:16.05pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>24(31)</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:16.05pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>31(24)</p>
- * </td>
- * </tr>
- * <tr style='height:17.85pt'>
- * <td width=208 rowspan=2 valign=top style='width:125.0pt;border-top:none;
- * border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt;
- * border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt;height:17.85pt'>
- * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
- * normal'>Config B</p>
- * </td>
- * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:17.85pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Dual Link DVI-D</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:17.85pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>8(15)</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:17.85pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>15(8)</p>
- * </td>
- * </tr>
- * <tr style='height:16.5pt'>
- * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:16.5pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Dual Link DVI-D</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:16.5pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>16(23)</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:16.5pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>23(16)</p>
- * </td>
- * </tr>
- * <tr style='height:16.5pt'>
- * <td width=208 rowspan=3 valign=top style='width:125.0pt;border-top:none;
- * border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt;
- * border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt;height:16.5pt'>
- * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
- * normal'>Config C</p>
- * </td>
- * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:16.5pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Dual Link DVI-D</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:16.5pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>8(15)</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:16.5pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>15(8)</p>
- * </td>
- * </tr>
- * <tr style='height:95.0pt'>
- * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>HDMI</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Single Link DVI-D</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>DP </p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>eDP</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Travis DP-to-CRT</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Travis DP-to-LVDS</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Hudson2 DP-to-CRT</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>16</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>19</p>
- * </td>
- * </tr>
- * <tr style='height:95.0pt'>
- * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>HDMI</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Single Link DVI-D</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>DP </p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>eDP</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Travis DP-to-CRT</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Travis DP-to-LVDS</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Hudson2 DP-to-CRT</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>20</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>23</p>
- * </td>
- * </tr>
- * <tr style='height:93.0pt'>
- * <td width=208 rowspan=3 valign=top style='width:125.0pt;border-top:none;
- * border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt;
- * border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt;height:93.0pt'>
- * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
- * normal'>Config D</p>
- * </td>
- * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:93.0pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>HDMI</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Single Link DVI-D</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>DP </p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>eDP</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Travis DP-to-CRT</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Travis DP-to-LVDS</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Hudson2 DP-to-CRT</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:93.0pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>8</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:93.0pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>11</p>
- * </td>
- * </tr>
- * <tr style='height:95.0pt'>
- * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>HDMI</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Single Link DVI-D</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>DP </p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>eDP</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Travis DP-to-CRT</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Travis DP-to-LVDS</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Hudson2 DP-to-CRT</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>12</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>15</p>
- * </td>
- * </tr>
- * <tr style='height:18.3pt'>
- * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:18.3pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Dual Link DVI-D</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:18.3pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>16(23)</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:18.3pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>23(16)</p>
- * </td>
- * </tr>
- * <tr style='height:95.0pt'>
- * <td width=208 rowspan=4 valign=top style='width:125.0pt;border:solid windowtext 1.5pt;
- * border-top:none;padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
- * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
- * normal'>Config E</p>
- * </td>
- * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>HDMI</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Single Link DVI-D</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>DP </p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>eDP</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Travis DP-to-CRT</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Travis DP-to-LVDS</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Hudson2 DP-to-CRT </p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>8</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>11</p>
- * </td>
- * </tr>
- * <tr style='height:95.0pt'>
- * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>HDMI</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Single Link DVI-D</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>DP </p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>eDP</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Travis DP-to-CRT</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Travis DP-to-LVDS</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Hudson2 DP-to-CRT</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>12</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>15</p>
- * </td>
- * </tr>
- * <tr style='height:95.0pt'>
- * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>HDMI</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Single Link DVI-D</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>DP </p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>eDP</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Travis DP-to-CRT</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Travis DP-to-LVDS</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Hudson2 DP-to-CRT </p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>16</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>19</p>
- * </td>
- * </tr>
- * <tr style='height:95.0pt'>
- * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>HDMI</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Single Link DVI-D</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>DP </p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>eDP</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Travis DP-to-CRT</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Travis DP-to-LVDS</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Hudson2 DP-to-CRT</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>20</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>23</p>
- * </td>
- * </tr>
- *</table>
- *</div>
- */
-
-/**
- * @page F14LaneConfigurations Family 0x14 PCIe port/DDI link configurations
- *
- * <div class=Section1>
- *
- *<p class=MsoNormal><span style='font-size:14.0pt;line-height:115%'>PCIe port
- *configurations for lanes 4 through 7.</span></p>
- *
- *<table class=MsoTableGrid border=1 cellspacing=0 cellpadding=0
- * style='border-collapse:collapse;border:none'>
- * <tr>
- * <td width=208 valign=top style='width:125.0pt;border:solid windowtext 1.5pt;
- * background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
- * normal'>Configuration</p>
- * </td>
- * <td width=168 valign=top style='width:100.9pt;border:solid windowtext 1.5pt;
- * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>PCIe Port Device Number</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border:solid windowtext 1.5pt;
- * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Start Lane (Start Lane in reverse
- * configuration)</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border:solid windowtext 1.5pt;
- * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>End Line (End lane in reverse
- * configuration)</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=208 rowspan=2 valign=top style='width:125.0pt;border:solid windowtext 1.5pt;
- * border-top:none;padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
- * normal'>Config A</p>
- * </td>
- * <td width=168 rowspan=2 valign=top style='width:100.9pt;border-top:none;
- * border-left:none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>4</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>4(7)</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>7(4)</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'> </p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'> </p>
- * </td>
- * </tr>
- * <tr>
- * <td width=208 rowspan=6 valign=top style='width:125.0pt;border-top:none;
- * border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt;
- * border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
- * normal'>Config B</p>
- * </td>
- * <td width=168 rowspan=3 valign=top style='width:100.9pt;border-top:none;
- * border-left:none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>4</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>4(5)</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>5(4)</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>4</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>4</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>5</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>5</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=168 rowspan=3 valign=top style='width:100.9pt;border-top:none;
- * border-left:none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>5</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>6(7)</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>7(6)</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>6</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>6</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>7</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>7</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=208 rowspan=5 valign=top style='width:125.0pt;border-top:none;
- * border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt;
- * border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
- * normal'>Config C</p>
- * </td>
- * <td width=168 rowspan=3 valign=top style='width:100.9pt;border-top:none;
- * border-left:none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>4</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>4(5)</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>5(4)</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>4</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>4</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>5</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>5</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>5</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>6</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>6</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>6</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>7</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>7</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=208 rowspan=4 valign=top style='width:125.0pt;border:solid windowtext 1.5pt;
- * border-top:none;padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
- * normal'>Config D</p>
- * </td>
- * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>4</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>4</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>4</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>5</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>5</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>5</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>6</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>6</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>6</p>
- * </td>
- * </tr>
- * <tr>
- * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>7</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>7</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>7</p>
- * </td>
- * </tr>
- *</table>
- *
- *<p class=MsoNormal> </p>
- *<p class=MsoNormal> </p>
- *
- *<p class=MsoNormal><span style='font-size:14.0pt;line-height:115%'>CRT/DDI link
- *configurations for lanes 8 through 19.</span></p>
- *
- *<table class=MsoTableGrid border=1 cellspacing=0 cellpadding=0
- * style='border-collapse:collapse;border:none'>
- * <tr>
- * <td width=208 valign=top style='width:125.0pt;border:solid windowtext 1.5pt;
- * background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
- * normal'>Configuration</p>
- * </td>
- * <td width=168 valign=top style='width:100.9pt;border:solid windowtext 1.5pt;
- * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Connector type</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border:solid windowtext 1.5pt;
- * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Start Lane (Start Lane in reverse
- * configuration)</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border:solid windowtext 1.5pt;
- * border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>End Line (End lane in reverse
- * configuration)</p>
- * </td>
- * </tr>
- * <tr style='height:95.0pt'>
- * <td width=208 rowspan=3 valign=top style='width:125.0pt;border-top:none;
- * border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt;
- * border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
- * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
- * normal'>Config A</p>
- * </td>
- * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>HDMI</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Single Link DVI-D</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Single Link DVI-I*</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>DP </p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>eDP</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Travis DP-to-CRT</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Travis DP-to-LVDS</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Hudson2 DP-to-CRT </p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>8</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>11</p>
- * </td>
- * </tr>
- * <tr style='height:95.0pt'>
- * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>HDMI</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Single Link DVI-D</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Single Link DVI-I*</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>DP </p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>eDP</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Travis DP-to-CRT</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Travis DP-to-LVDS</p>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>Hudson2 DP-to-CRT</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>12</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>15</p>
- * </td>
- * </tr>
- * <tr style='height:95.0pt'>
- * <td width=168 valign=top style='width:100.9pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>CRT*</p>
- * </td>
- * <td width=224 valign=top style='width:134.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>16</p>
- * </td>
- * <td width=197 valign=top style='width:118.45pt;border-top:none;border-left:
- * none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
- * padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
- * <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
- * text-align:center;line-height:normal'>19</p>
- * </td>
- * </tr>
- * <tr style='height:35.85pt'>
- * <td width=798 colspan=4 valign=top style='width:6.65in;border:solid windowtext 1.5pt;
- * border-top:none;padding:0in 5.4pt 0in 5.4pt;height:35.85pt'>
- * <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
- * normal'>* - Only one connector of this type can exist in overall configuration</p>
- * </td>
- * </tr>
- *</table>
- *</div>
- */
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCableSafe/GnbCableSafe.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCableSafe/GnbCableSafe.c
deleted file mode 100644
index 08fd84a..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCableSafe/GnbCableSafe.c
+++ /dev/null
@@ -1,222 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Cable safe module
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e $Revision: $ @e $Date: $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Gnb.h"
-#include "GnbPcie.h"
-#include GNB_MODULE_DEFINITIONS (GnbPcieConfig)
-#include "GnbRegistersON.h"
-#include "cpuFamilyTranslation.h"
-#include "NbSmuLib.h"
-#include "GnbCableSafeDefs.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_MODULES_GNBCABLESAFE_GNBCABLESAFE_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-UINT8 HdpIndexTranslationTable [] = {
- 3, 2, 1, 0, 7, 6
-};
-
-UINT8 AuxIndexTranslationTable [] = {
- 5, 4, 11, 10, 9, 8
-};
-
-UINT8 AuxDataTranslationTable [] = {
- 0x10, 0x20, 0x40, 0x01, 0x02, 0x04
-};
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-VOID
-STATIC
-GnbCableSafeGetConnectorInfoArrayCallback (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN OUT VOID *Buffer,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-BOOLEAN
-GnbCableSafeIsSupported (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Cable Safe module entry
- *
- *
- *
- * @param[in] StdHeader Standard configuration header
- * @retval AGESA_STATUS
- */
-
-AGESA_STATUS
-GnbCableSafeEntry (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_STATUS Status;
- PCIe_PLATFORM_CONFIG *Pcie;
- PCIe_ENGINE_CONFIG *DdiEngineList [MaxHdp];
- UINT8 HdpIndex;
- UINT8 CurrentIndex;
- GNB_CABLE_SAFE_DATA CableSafeData;
- IDS_HDT_CONSOLE (GNB_TRACE, "GnbCableSafeEntry Enter\n");
- Status = AGESA_SUCCESS;
- if (GnbCableSafeIsSupported (StdHeader)) {
- if (PcieLocateConfigurationData (StdHeader, &Pcie) == AGESA_SUCCESS) {
- for (HdpIndex = 0; HdpIndex < MaxHdp; HdpIndex++) {
- DdiEngineList[HdpIndex] = NULL;
- }
- LibAmdMemFill (&CableSafeData, 0, sizeof (CableSafeData), StdHeader);
- PcieConfigRunProcForAllEngines (
- DESCRIPTOR_ALLOCATED | DESCRIPTOR_DDI_ENGINE,
- GnbCableSafeGetConnectorInfoArrayCallback,
- DdiEngineList,
- Pcie
- );
- CurrentIndex = 0;
- for (HdpIndex = 0; HdpIndex < MaxHdp; HdpIndex++) {
- if (DdiEngineList [HdpIndex] != NULL) {
- CableSafeData.Data[HdpIndexTranslationTable[CurrentIndex]] = HdpIndex + 1;
- CableSafeData.Data[AuxIndexTranslationTable[CurrentIndex]] = AuxDataTranslationTable [(DdiEngineList [HdpIndex])->Type.Ddi.DdiData.AuxIndex];
- IDS_HDT_CONSOLE (NB_MISC, " Index [%d] HDP 0x%02x AUX 0x%02x\n", CurrentIndex, HdpIndex, (DdiEngineList [HdpIndex])->Type.Ddi.DdiData.AuxIndex);
- CurrentIndex++;
- }
- }
- CableSafeData.Config.Enable = 0x1;
- CableSafeData.Config.DebounceFilter = 0x2;
- CableSafeData.Config.SoftPeriod = 0x4;
- CableSafeData.Config.Unit = 0x1;
- CableSafeData.Config.Period = 0xf424;
- NbSmuRcuRegisterWrite (
- SMUx0B_x85D0_ADDRESS,
- (UINT32*) &CableSafeData,
- sizeof (CableSafeData) / sizeof (UINT32),
- TRUE,
- StdHeader
- );
- NbSmuServiceRequest (0x05, TRUE, StdHeader);
- } else {
- Status = AGESA_ERROR;
- }
- }
- IDS_HDT_CONSOLE (GNB_TRACE, "GnbCableSafeEntry Exit [Status = 0x%04x]\n", Status);
- return Status;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Callback to init max port Gen capability
- *
- *
- *
- *
- * @param[in] Engine Pointer to engine config descriptor
- * @param[in, out] Buffer Not used
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-
-VOID
-STATIC
-GnbCableSafeGetConnectorInfoArrayCallback (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN OUT VOID *Buffer,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- PCIe_ENGINE_CONFIG **EngineList;
- EngineList = (PCIe_ENGINE_CONFIG**) Buffer;
- EngineList [Engine->Type.Ddi.DdiData.HdpIndex] = Engine;
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Check if feature supported
- *
- * Module requre for LN B0 and above
- *
- *
- * @param[in] StdHeader Standard configuration header
- * @retval TRUE Cable safe needs to be enabled
- */
-
-BOOLEAN
-GnbCableSafeIsSupported (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- BOOLEAN Result;
- CPU_LOGICAL_ID LogicalId;
- SMU_FIRMWARE_REV FirmwareRev;
- Result = FALSE;
- GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
- FirmwareRev = NbSmuFirmwareRevision (StdHeader);
- if (SMI_FIRMWARE_REVISION (FirmwareRev) >= 0x010904 && LogicalId.Revision > AMD_F12_LN_A1) {
- Result = TRUE;
- }
- return Result;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCableSafe/GnbCableSafeDefs.h b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCableSafe/GnbCableSafeDefs.h
deleted file mode 100644
index d96fa0c..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCableSafe/GnbCableSafeDefs.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Cable safe module
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e $Revision: $ @e $Date: $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _GNBCABLESAFEDEFS_H_
-#define _GNBCABLESAFEDEFS_H_
-
-#pragma pack (push, 1)
-
-/// Cable safe data package
-typedef struct {
- struct {
- UINT32 Enable :1; ///< Enable cable safe
- UINT32 DebounceFilter :3; ///< Debounce filter
- UINT32 SoftPeriod :4; ///< Soft period
- UINT32 Unit :4; ///< Unit
- UINT32 Reserved :4; ///< Reserved
- UINT32 Period :16; ///< Period
- } Config; ///< Configuration package
- UINT8 Data [12]; ///< HDP/AUX info array
-} GNB_CABLE_SAFE_DATA;
-
-#pragma pack (pop)
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbCommonLib.h b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbCommonLib.h
deleted file mode 100644
index b8517a0..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbCommonLib.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * GNB register access services.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _GNBCOMMONLIB_H_
-#define _GNBCOMMONLIB_H_
-
-#include "GnbLib.h"
-#include "GnbLibCpuAcc.h"
-#include "GnbLibHeap.h"
-#include "GnbLibIoAcc.h"
-#include "GnbLibMemAcc.h"
-#include "GnbLibPci.h"
-#include "GnbLibPciAcc.h"
-
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLib.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLib.c
deleted file mode 100644
index 5e8b67e..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLib.c
+++ /dev/null
@@ -1,460 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * GNB register access services.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "Porting.h"
-#include "AMD.h"
-#include "amdlib.h"
-#include "Gnb.h"
-#include "GnbLib.h"
-#include "GnbLibIoAcc.h"
-#include "GnbLibPciAcc.h"
-#include "GnbLibMemAcc.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIB_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Read GNB indirect registers
- *
- *
- *
- * @param[in] Address PCI address of indirect register
- * @param[in] IndirectAddress Offset of indirect register
- * @param[in] Width Width
- * @param[out] Value Pointer to value
- * @param[in] Config Pointer to standard header
- */
-VOID
-GnbLibPciIndirectRead (
- IN UINT32 Address,
- IN UINT32 IndirectAddress,
- IN ACCESS_WIDTH Width,
- OUT VOID *Value,
- IN VOID *Config
- )
-{
- UINT32 IndexOffset;
- IndexOffset = LibAmdAccessWidth (Width);
- GnbLibPciWrite (Address, Width, &IndirectAddress, Config);
- GnbLibPciRead (Address + IndexOffset, Width, Value, Config);
-}
-/*----------------------------------------------------------------------------------------*/
-/**
- * Read GNB indirect registers field
- *
- *
- *
- * @param[in] Address PCI address of indirect register
- * @param[in] IndirectAddress Offset of indirect register
- * @param[in] FieldOffset Field offset
- * @param[in] FieldWidth Field width
- * @param[out] Value Pointer to value
- * @param[in] Config Pointer to standard header
- */
-VOID
-GnbLibPciIndirectReadField (
- IN UINT32 Address,
- IN UINT32 IndirectAddress,
- IN UINT8 FieldOffset,
- IN UINT8 FieldWidth,
- OUT UINT32 *Value,
- IN VOID *Config
- )
-{
- UINT32 Mask;
- GnbLibPciIndirectRead (Address, IndirectAddress, AccessWidth32, Value, Config);
- Mask = (1 << FieldWidth) - 1;
- *Value = (*Value >> FieldOffset) & Mask;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Write GNB indirect registers
- *
- *
- *
- * @param[in] Address PCI address of indirect register
- * @param[in] IndirectAddress Offset of indirect register
- * @param[in] Width Width
- * @param[in] Value Pointer to value
- * @param[in] Config Pointer to standard header
- */
-
-VOID
-GnbLibPciIndirectWrite (
- IN UINT32 Address,
- IN UINT32 IndirectAddress,
- IN ACCESS_WIDTH Width,
- IN VOID *Value,
- IN VOID *Config
- )
-{
- UINT32 IndexOffset;
- IndexOffset = LibAmdAccessWidth (Width);
- GnbLibPciWrite (Address, Width, &IndirectAddress, Config);
- GnbLibPciWrite (Address + IndexOffset, Width, Value, Config);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Write GNB indirect registers field
- *
- *
- *
- * @param[in] Address PCI address of indirect register
- * @param[in] IndirectAddress Offset of indirect register
- * @param[in] FieldOffset Field offset
- * @param[in] FieldWidth Field width
- * @param[in] Value Pointer to value
- * @param[in] S3Save Save for S3 (TRUE/FALSE)
- * @param[in] Config Pointer to standard header
- */
-VOID
-GnbLibPciIndirectWriteField (
- IN UINT32 Address,
- IN UINT32 IndirectAddress,
- IN UINT8 FieldOffset,
- IN UINT8 FieldWidth,
- IN UINT32 Value,
- IN BOOLEAN S3Save,
- IN VOID *Config
- )
-{
- UINT32 Data;
- UINT32 Mask;
- GnbLibPciIndirectRead (Address, IndirectAddress, AccessWidth32, &Data, Config);
- Mask = (1 << FieldWidth) - 1;
- Data &= (~(Mask << FieldOffset));
- Data |= ((Value & Mask) << FieldOffset);
- GnbLibPciIndirectWrite (Address, IndirectAddress, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Data, Config);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Read/Modify/Write GNB indirect registers field
- *
- *
- *
- * @param[in] Address PCI address of indirect register
- * @param[in] IndirectAddress Offset of indirect register
- * @param[in] Width Width
- * @param[in] Mask And Mask
- * @param[in] Value Or Value
- * @param[in] Config Pointer to standard header
- */
-VOID
-GnbLibPciIndirectRMW (
- IN UINT32 Address,
- IN UINT32 IndirectAddress,
- IN ACCESS_WIDTH Width,
- IN UINT32 Mask,
- IN UINT32 Value,
- IN VOID *Config
- )
-{
- UINT32 Data;
- GnbLibPciIndirectRead (
- Address,
- IndirectAddress,
- (Width >= AccessS3SaveWidth8) ? (Width - (AccessS3SaveWidth8 - AccessWidth8)) : Width,
- &Data,
- Config
- );
- Data = (Data & Mask) | Value;
- GnbLibPciIndirectWrite (Address, IndirectAddress, Width, &Data, Config);
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Read/Modify/Write PCI registers
- *
- *
- *
- * @param[in] Address PCI address
- * @param[in] Width Access width
- * @param[in] Mask AND Mask
- * @param[in] Value OR Value
- * @param[in] Config Pointer to standard header
- */
-VOID
-GnbLibPciRMW (
- IN UINT32 Address,
- IN ACCESS_WIDTH Width,
- IN UINT32 Mask,
- IN UINT32 Value,
- IN VOID *Config
- )
-{
- UINT32 Data;
- GnbLibPciRead (Address, Width, &Data, Config);
- Data = (Data & Mask) | Value;
- GnbLibPciWrite (Address, Width, &Data, Config);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Read/Modify/Write I/O registers
- *
- *
- *
- * @param[in] Address I/O Port
- * @param[in] Width Access width
- * @param[in] Mask AND Mask
- * @param[in] Value OR Mask
- * @param[in] Config Pointer to standard header
- */
-VOID
-GnbLibIoRMW (
- IN UINT16 Address,
- IN ACCESS_WIDTH Width,
- IN UINT32 Mask,
- IN UINT32 Value,
- IN VOID *Config
- )
-{
- UINT32 Data;
- GnbLibIoRead (Address, Width, &Data, Config);
- Data = (Data & Mask) | Value;
- GnbLibIoWrite (Address, Width, &Data, Config);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Read/Modify/Write MMIO registers
- *
- *
- *
- * @param[in] Address Physical address
- * @param[in] Width Access width
- * @param[in] Mask AND Mask
- * @param[in] Value OR Value
- * @param[in] Config Pointer to standard header
- */
-VOID
-GnbLibMemRMW (
- IN UINT64 Address,
- IN ACCESS_WIDTH Width,
- IN UINT32 Mask,
- IN UINT32 Value,
- IN VOID *Config
- )
-{
- UINT32 Data;
- GnbLibMemRead (Address, Width, &Data, Config);
- Data = (Data & Mask) | Value;
- GnbLibMemWrite (Address, Width, &Data, Config);
-}
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get number of sockets
- *
- *
- *
- * @param[in] StdHeader Standard configuration header
- * @retval Total number of socket on platform
- */
-
-UINT32
-GnbGetNumberOfSockets (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- return 1;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get number of Silicons on the socket
- *
- *
- *
- * @param[in] SiliconId Socket ID
- * @param[in] StdHeader Standard configuration header
- * @retval Number of silicons/modules in device in socket
- */
-
-UINT32
-GnbGetNumberOfSiliconsOnSocket (
- IN UINT32 SiliconId,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- return 1;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get PCI Address
- *
- *
- *
- * @param[in] SocketId Socket ID
- * @param[in] SiliconId Silicon device Id
- * @param[in] StdHeader Standard configuration header
- * @retval PCI address of GNB for a given socket/silicon.
- */
-
-PCI_ADDR
-GnbGetPciAddress (
- IN UINT32 SocketId,
- IN UINT32 SiliconId,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- PCI_ADDR Gnb;
- Gnb.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0);
- return Gnb;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Check if anything plugged in socket
- *
- *
- *
- * @param[in] SocketId Socket ID
- * @param[in] StdHeader Standard configuration header
- * @retval TRUE CPU present in socket.
- */
-
-BOOLEAN
-GnbIsDevicePresentInSocket (
- IN UINT32 SocketId,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- return TRUE;
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Claculate power of number
- *
- *
- *
- * @param[in] Value Number
- * @param[in] Power Power
- */
-
-UINT32
-GnbLibPowerOf (
- IN UINT32 Value,
- IN UINT32 Power
- )
-{
- UINT32 Result;
- if (Power == 0) {
- return 1;
- }
- Result = Value;
- while ((--Power) > 0) {
- Result *= Value;
- }
- return Result;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Search buffer for pattern
- *
- *
- * @param[in] Buf1 Pointer to source buffer which will be subject of search
- * @param[in] Buf1Length Length of the source buffer
- * @param[in] Buf2 Pointer to pattern buffer
- * @param[in] Buf2Length Length of the pattern buffer
- * @retval Pointer on first accurance of Buf2 in Buf1 or NULL
- */
-
-VOID*
-GnbLibFind (
- IN UINT8 *Buf1,
- IN UINTN Buf1Length,
- IN UINT8 *Buf2,
- IN UINTN Buf2Length
- )
-{
- UINT8 *CurrentBuf1Ptr;
- CurrentBuf1Ptr = Buf1;
- while (CurrentBuf1Ptr < (Buf1 + Buf1Length - Buf2Length)) {
- UINT8 *SourceBufPtr;
- UINT8 *PatternBufPtr;
- UINTN PatternBufLength;
- SourceBufPtr = CurrentBuf1Ptr;
- PatternBufPtr = Buf2;
- PatternBufLength = Buf2Length;
- while ((*SourceBufPtr++ == *PatternBufPtr++) && (PatternBufLength-- != 0));
- if (PatternBufLength == 0) {
- return CurrentBuf1Ptr;
- }
- CurrentBuf1Ptr++;
- }
- return NULL;
-}
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLib.h b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLib.h
deleted file mode 100644
index 6b106b0..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLib.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * GNB register access services.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _GNBLIB_H_
-#define _GNBLIB_H_
-
-#define IOC_WRITE_ENABLE 0x80
-
-
-VOID
-GnbLibPciIndirectWrite (
- IN UINT32 Address,
- IN UINT32 IndirectAddress,
- IN ACCESS_WIDTH Width,
- IN VOID *Value,
- IN VOID *Config
- );
-
-VOID
-GnbLibPciIndirectRead (
- IN UINT32 Address,
- IN UINT32 IndirectAddress,
- IN ACCESS_WIDTH Width,
- OUT VOID *Value,
- IN VOID *Config
- );
-
-VOID
-GnbLibPciIndirectRMW (
- IN UINT32 Address,
- IN UINT32 IndirectAddress,
- IN ACCESS_WIDTH Width,
- IN UINT32 Mask,
- IN UINT32 Value,
- IN VOID *Config
- );
-
-VOID
-GnbLibPciIndirectWriteField (
- IN UINT32 Address,
- IN UINT32 IndirectAddress,
- IN UINT8 FieldOffset,
- IN UINT8 FieldWidth,
- IN UINT32 Value,
- IN BOOLEAN S3Save,
- IN VOID *Config
- );
-
-
-VOID
-GnbLibPciRMW (
- IN UINT32 Address,
- IN ACCESS_WIDTH Width,
- IN UINT32 Mask,
- IN UINT32 Value,
- IN VOID *Config
- );
-
-VOID
-GnbLibIoRMW (
- IN UINT16 Address,
- IN ACCESS_WIDTH Width,
- IN UINT32 Mask,
- IN UINT32 Value,
- IN VOID *Config
- );
-
-UINT32
-GnbGetNumberOfSockets (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-UINT32
-GnbGetNumberOfSiliconsOnSocket (
- IN UINT32 SiliconId,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-BOOLEAN
-GnbIsDevicePresentInSocket (
- IN UINT32 SocketId,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-PCI_ADDR
-GnbGetPciAddress (
- IN UINT32 SocketId,
- IN UINT32 SiliconId,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-UINT32
-GnbLibPowerOf (
- IN UINT32 Value,
- IN UINT32 Power
- );
-
-VOID*
-GnbLibFind (
- IN UINT8 *Buf1,
- IN UINTN Buf1Length,
- IN UINT8 *Buf2,
- IN UINTN Buf2Length
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c
deleted file mode 100644
index 8b9b93f..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c
+++ /dev/null
@@ -1,130 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Service procedure to access various CPU registers.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "Porting.h"
-#include "AMD.h"
-#include "GnbLibPciAcc.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBCPUACC_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Read CPU (DCT) indirect registers
- *
- *
- *
- * @param[in] Address PCI address of DCT register
- * @param[in] IndirectAddress Offset of DCT register
- * @param[out] Value Pointer to value
- * @param[in] Config Pointer to standard header
- */
-VOID
-GnbLibCpuPciIndirectRead (
- IN UINT32 Address,
- IN UINT32 IndirectAddress,
- OUT UINT32 *Value,
- IN VOID *Config
- )
-{
- UINT32 OffsetRegisterValue;
- GnbLibPciWrite (Address, AccessWidth32, &IndirectAddress, Config);
- do {
- GnbLibPciRead (Address , AccessWidth32, &OffsetRegisterValue, Config);
- } while ((OffsetRegisterValue & BIT31) == 0);
- GnbLibPciRead (Address + 4, AccessWidth32, Value, Config);
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Write CPU (DCT) indirect registers
- *
- *
- *
- * @param[in] Address PCI address of DCT register
- * @param[in] IndirectAddress Offset of DCT register
- * @param[in] Value Pointer to value
- * @param[in] Config Pointer to standard header
- */
-VOID
-GnbLibCpuPciIndirectWrite (
- IN UINT32 Address,
- IN UINT32 IndirectAddress,
- IN UINT32 *Value,
- IN VOID *Config
- )
-{
- UINT32 OffsetRegisterValue;
- OffsetRegisterValue = IndirectAddress | BIT30;
- GnbLibPciWrite (Address + 4, AccessWidth32, Value, Config);
- GnbLibPciWrite (Address, AccessWidth32, &IndirectAddress, Config);
- do {
- GnbLibPciRead (Address , AccessWidth32, &OffsetRegisterValue, Config);
- } while ((OffsetRegisterValue & BIT31) == 0);
-}
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.h b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.h
deleted file mode 100644
index b403d70..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Service procedure to access various CPU registers.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _CPUACCLIB_H_
-#define _CPUACCLIB_H_
-
-VOID
-GnbLibCpuPciIndirectWrite (
- IN UINT32 Address,
- IN UINT32 IndirectAddress,
- IN UINT32 *Value,
- IN VOID *Config
- );
-
-VOID
-GnbLibCpuPciIndirectRead (
- IN UINT32 Address,
- IN UINT32 IndirectAddress,
- OUT UINT32 *Value,
- IN VOID *Config
- );
-
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c
deleted file mode 100644
index 5890ffe..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Service procedure to access heap.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "Porting.h"
-#include "AMD.h"
-#include "heapManager.h"
-#include "GnbLibPciAcc.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBHEAP_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Allocates space for a new buffer in the heap
- *
- *
- * @param[in] Handle Buffer handle
- * @param[in] Length Buffer length
- * @param[in] StdHeader Standard configuration header
- *
- * @retval NULL Buffer allocation fail
- *
- */
-
-VOID*
-GnbAllocateHeapBuffer (
- IN UINT32 Handle,
- IN UINTN Length,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_STATUS Status;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
- AllocHeapParams.RequestedBufferSize = (UINT32) Length;
- AllocHeapParams.BufferHandle = Handle;
- AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
- Status = HeapAllocateBuffer (&AllocHeapParams, StdHeader);
- if (Status != AGESA_SUCCESS) {
- return NULL;
- }
- return AllocHeapParams.BufferPtr;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Locates a previously allocated buffer on the heap.
- *
- *
- * @param[in] Handle Buffer handle
- * @param[in] StdHeader Standard configuration header
- *
- * @retval NULL Buffer handle not found
- *
- */
-
-VOID *
-GnbLocateHeapBuffer (
- IN UINT32 Handle,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_STATUS Status;
- LOCATE_HEAP_PTR LocHeapParams;
- LocHeapParams.BufferHandle = Handle;
- Status = HeapLocateBuffer (&LocHeapParams, StdHeader);
- if (Status != AGESA_SUCCESS) {
- return NULL;
- }
- return LocHeapParams.BufferPtr;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.h b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.h
deleted file mode 100644
index 01c4fd0..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Service procedure to access heap.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _GNBHEAPLIB_H_
-#define _GNBHEAPLIB_H_
-
-VOID *
-GnbAllocateHeapBuffer (
- IN UINT32 Handle,
- IN UINTN Length,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID *
-GnbLocateHeapBuffer (
- IN UINT32 Handle,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c
deleted file mode 100644
index d7d5242..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
-* Service procedure to access I/O registers.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "Porting.h"
-#include "AMD.h"
-#include "amdlib.h"
-#include "GnbLibIoAcc.h"
-#include "S3SaveState.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBIOACC_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------------------*/
-
-/*---------------------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------------------*/
-/**
- * Write I/O Port
- *
- *
- *
- * @param[in] Address Physical Address
- * @param[in] Width Access width
- * @param[in] Value Pointer to value
- * @param[in] StdHeader Standard configuration header
- */
-
-VOID
-GnbLibIoWrite (
- IN UINT16 Address,
- IN ACCESS_WIDTH Width,
- IN VOID *Value,
- IN VOID *StdHeader
- )
-{
- if (Width >= AccessS3SaveWidth8) {
- S3_SAVE_IO_WRITE (StdHeader, Address, Width, Value);
- }
- LibAmdIoWrite (Width, Address, Value, StdHeader);
-}
-/**
- * Read IO port
- *
- *
- *
- * @param[in] Address Physical Address
- * @param[in] Width Access width
- * @param[out] Value Pointer to value
- * @param[in] StdHeader Standard configuration header
- */
-
-VOID
-GnbLibIoRead (
- IN UINT16 Address,
- IN ACCESS_WIDTH Width,
- OUT VOID *Value,
- IN VOID *StdHeader
- )
-{
- LibAmdIoRead (Width, Address, Value, StdHeader);
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.h b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.h
deleted file mode 100644
index 9c0f4a6..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Service procedure to access I/O registers.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _IOACCLIB_H_
-#define _IOACCLIB_H_
-
-
-VOID
-GnbLibIoWrite (
- IN UINT16 Address,
- IN ACCESS_WIDTH Width,
- IN VOID *Value,
- IN VOID *StdHeader
- );
-
-VOID
-GnbLibIoRead (
- IN UINT16 Address,
- IN ACCESS_WIDTH Width,
- OUT VOID *Value,
- IN VOID *StdHeader
- );
-
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c
deleted file mode 100644
index 019d705..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Service procedure to access MMIO registers.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "Porting.h"
-#include "AMD.h"
-#include "amdlib.h"
-#include "GnbLibMemAcc.h"
-#include "S3SaveState.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBMEMACC_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Write Memory/MMIO registers
- *
- *
- *
- * @param[in] Address Physical Address
- * @param[in] Width Access width
- * @param[in] Value Pointer to value
- * @param[in] StdHeader Standard configuration header
- */
-
-VOID
-GnbLibMemWrite (
- IN UINT64 Address,
- IN ACCESS_WIDTH Width,
- IN VOID *Value,
- IN VOID *StdHeader
- )
-{
- if (Width >= AccessS3SaveWidth8) {
- S3_SAVE_MEM_WRITE (StdHeader, Address, Width, Value);
- }
- LibAmdMemWrite (Width, Address, Value, StdHeader);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Read Memory/MMIO registers
- *
- *
- *
- * @param[in] Address Physical Address
- * @param[in] Width Access width
- * @param[out] Value Pointer to value
- * @param[in] StdHeader Standard configuration header
- */
-
-VOID
-GnbLibMemRead (
- IN UINT64 Address,
- IN ACCESS_WIDTH Width,
- OUT VOID *Value,
- IN VOID *StdHeader
- )
-{
- LibAmdMemRead (Width, Address, Value, StdHeader);
-}
-
-
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.h b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.h
deleted file mode 100644
index 7acb7cd..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Service procedure to access MMIO registers.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _MEMACCLIB_H_
-#define _MEMACCLIB_H_
-
-VOID
-GnbLibMemWrite (
- IN UINT64 Address,
- IN ACCESS_WIDTH Width,
- IN VOID *Value,
- IN VOID *StdHeader
- );
-
-VOID
-GnbLibMemRead (
- IN UINT64 Address,
- IN ACCESS_WIDTH Width,
- OUT VOID *Value,
- IN VOID *StdHeader
- );
-
-VOID
-GnbLibMemRMW (
- IN UINT64 Address,
- IN ACCESS_WIDTH Width,
- IN UINT32 Mask,
- IN UINT32 Value,
- IN VOID *Config
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c
deleted file mode 100644
index 8c02a9b..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c
+++ /dev/null
@@ -1,405 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Various PCI service routines.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-#include "Porting.h"
-#include "AMD.h"
-#include "GnbLibPciAcc.h"
-#include "GnbLibPci.h"
-#include "GnbLibPci.h"
-#include "amdlib.h"
-#include "GnbLib.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCI_FILECODE
-
-/*----------------------------------------------------------------------------------------*/
-/*
- * Check if device present
- *
- *
- *
- * @param[in] Address PCI address (as described in PCI_ADDR)
- * @param[in] StdHeader Standard configuration header
- * @retval TRUE Device is present
- * @retval FALSE Device is not present
- */
-
-BOOLEAN
-GnbLibPciIsDevicePresent (
- IN UINT32 Address,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 DeviceId;
- GnbLibPciRead (Address, AccessWidth32, &DeviceId, StdHeader);
- if (DeviceId == 0xffffffff) {
- return FALSE;
- } else {
- return TRUE;
- }
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/*
- * Check if device is bridge
- *
- *
- *
- * @param[in] Address PCI address (as described in PCI_ADDR)
- * @param[in] StdHeader Standard configuration header
- * @retval TRUE Device is a bridge
- * @retval FALSE Device is not a bridge
- */
-
-BOOLEAN
-GnbLibPciIsBridgeDevice (
- IN UINT32 Address,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 Header;
- GnbLibPciRead (Address | 0xe, AccessWidth8, &Header, StdHeader);
- if ((Header & 0x7f) == 1) {
- return TRUE;
- } else {
- return FALSE;
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/*
- * Check if device is multifunction
- *
- *
- *
- * @param[in] Address PCI address (as described in PCI_ADDR)
- * @param[in] StdHeader Standard configuration header
- * @retval TRUE Device is a multifunction device.
- * @retval FALSE Device is a single function device.
- *
- */
-BOOLEAN
-GnbLibPciIsMultiFunctionDevice (
- IN UINT32 Address,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 Header;
- GnbLibPciRead (Address | 0xe, AccessWidth8, &Header, StdHeader);
- if ((Header & 0x80) != 0) {
- return TRUE;
- } else {
- return FALSE;
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/*
- * Check if device is PCIe device
- *
- *
- *
- * @param[in] Address PCI address (as described in PCI_ADDR)
- * @param[in] StdHeader Standard configuration header
- * @retval TRUE Device is a PCIe device
- * @retval FALSE Device is not a PCIe device
- *
- */
-
-BOOLEAN
-GnbLibPciIsPcieDevice (
- IN UINT32 Address,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- if (GnbLibFindPciCapability (Address, 0x10, StdHeader) != 0 ) {
- return TRUE;
- } else {
- return FALSE;
- }
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/*
- * Find PCI capability pointer
- *
- *
- *
- * @param[in] Address PCI address (as described in PCI_ADDR)
- * @param[in] CapabilityId PCI capability ID
- * @param[in] StdHeader Standard configuration header
- * @retval Register address of capability pointer
- *
- */
-
-UINT8
-GnbLibFindPciCapability (
- IN UINT32 Address,
- IN UINT8 CapabilityId,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 CapabilityPtr;
- UINT8 CurrentCapabilityId;
- CapabilityPtr = 0x34;
- if (!GnbLibPciIsDevicePresent (Address, StdHeader)) {
- return 0;
- }
- while (CapabilityPtr != 0) {
- GnbLibPciRead (Address | CapabilityPtr, AccessWidth8 , &CapabilityPtr, StdHeader);
- if (CapabilityPtr != 0) {
- GnbLibPciRead (Address | CapabilityPtr , AccessWidth8 , &CurrentCapabilityId, StdHeader);
- if (CurrentCapabilityId == CapabilityId) {
- break;
- }
- CapabilityPtr++;
- }
- }
- return CapabilityPtr;
-}
-/*----------------------------------------------------------------------------------------*/
-/*
- * Find PCIe extended capability pointer
- *
- *
- *
- * @param[in] Address PCI address (as described in PCI_ADDR)
- * @param[in] ExtendedCapabilityId Extended PCIe capability ID
- * @param[in] StdHeader Standard configuration header
- * @retval Register address of extended capability pointer
- *
- */
-
-
-UINT16
-GnbLibFindPcieExtendedCapability (
- IN UINT32 Address,
- IN UINT16 ExtendedCapabilityId,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT16 CapabilityPtr;
- UINT32 ExtendedCapabilityIdBlock;
- if (GnbLibPciIsPcieDevice (Address, StdHeader)) {
- GnbLibPciRead (Address | 0x100 , AccessWidth32 , &ExtendedCapabilityIdBlock, StdHeader);
- if ((ExtendedCapabilityIdBlock != 0) && ((UINT16)ExtendedCapabilityIdBlock != 0xffff)) {
- do {
- CapabilityPtr = (UINT16) ((ExtendedCapabilityIdBlock >> 20) & 0xfff);
- if ((UINT16)ExtendedCapabilityIdBlock == ExtendedCapabilityId) {
- return CapabilityPtr;
- }
- GnbLibPciRead (Address | CapabilityPtr , AccessWidth32 , &ExtendedCapabilityIdBlock, StdHeader);
- } while (((ExtendedCapabilityIdBlock >> 20) & 0xfff) != 0);
- }
- }
- return 0;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/*
- * Scan range of device on PCI bus.
- *
- *
- *
- * @param[in] Start Start address to start scan from
- * @param[in] End End address of scan
- * @param[in] ScanData Supporting data
- *
- */
-/*----------------------------------------------------------------------------------------*/
-VOID
-GnbLibPciScan (
- IN PCI_ADDR Start,
- IN PCI_ADDR End,
- IN GNB_PCI_SCAN_DATA *ScanData
- )
-{
- UINTN Bus;
- UINTN Device;
- UINTN LastDevice;
- UINTN Function;
- UINTN LastFunction;
- PCI_ADDR PciDevice;
- SCAN_STATUS Status;
-
- for (Bus = Start.Address.Bus; Bus <= End.Address.Bus; Bus++) {
- Device = (Bus == Start.Address.Bus) ? Start.Address.Device : 0x00;
- LastDevice = (Bus == End.Address.Bus) ? End.Address.Device : 0x1F;
- for ( ; Device <= LastDevice; Device++) {
- if ((Bus == Start.Address.Bus) && (Device == Start.Address.Device)) {
- Function = Start.Address.Function;
- } else {
- Function = 0x0;
- }
- PciDevice.AddressValue = MAKE_SBDFO (0, Bus, Device, Function, 0);
- if (!GnbLibPciIsDevicePresent (PciDevice.AddressValue, ScanData->StdHeader)) {
- continue;
- }
- if (GnbLibPciIsMultiFunctionDevice (PciDevice.AddressValue, ScanData->StdHeader)) {
- if ((Bus == End.Address.Bus) && (Device == End.Address.Device)) {
- LastFunction = Start.Address.Function;
- } else {
- LastFunction = 0x7;
- }
- } else {
- LastFunction = 0x0;
- }
- for ( ; Function <= LastFunction; Function++) {
- PciDevice.AddressValue = MAKE_SBDFO (0, Bus, Device, Function, 0);
- if (GnbLibPciIsDevicePresent (PciDevice.AddressValue, ScanData->StdHeader)) {
- Status = ScanData->GnbScanCallback (PciDevice, ScanData);
- if ((Status & SCAN_SKIP_FUNCTIONS) != 0) {
- Function = LastFunction + 1;
- }
- if ((Status & SCAN_SKIP_DEVICES) != 0) {
- Device = LastDevice + 1;
- }
- if ((Status & SCAN_SKIP_BUSES) != 0) {
- Bus = End.Address.Bus + 1;
- }
- }
- }
- }
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Scan all subordinate buses
- *
- *
- * @param[in] Bridge PCI bridge address
- * @param[in,out] ScanData Scan configuration data
- *
- */
-VOID
-GnbLibPciScanSecondaryBus (
- IN PCI_ADDR Bridge,
- IN OUT GNB_PCI_SCAN_DATA *ScanData
- )
-{
- PCI_ADDR StartRange;
- PCI_ADDR EndRange;
- UINT8 SecondaryBus;
- GnbLibPciRead (Bridge.AddressValue | 0x19, AccessWidth8, &SecondaryBus, ScanData->StdHeader);
- if (SecondaryBus != 0) {
- StartRange.AddressValue = MAKE_SBDFO (0, SecondaryBus, 0, 0, 0);
- EndRange.AddressValue = MAKE_SBDFO (0, SecondaryBus, 0x1f, 0x7, 0);
- GnbLibPciScan (StartRange, EndRange, ScanData);
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get PCIe device type
- *
- *
- *
- * @param[in] Device PCI address of device.
- * @param[in] StdHeader Northbridge configuration structure pointer.
- *
- * @retval PCIE_DEVICE_TYPE
- */
- /*----------------------------------------------------------------------------------------*/
-
-PCIE_DEVICE_TYPE
-GnbLibGetPcieDeviceType (
- IN PCI_ADDR Device,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 PcieCapPtr;
- UINT8 Value;
-
- PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, StdHeader);
- if (PcieCapPtr != 0) {
- GnbLibPciRead (Device.AddressValue | (PcieCapPtr + 0x2) , AccessWidth8, &Value, StdHeader);
- return Value >> 4;
- }
- return PcieNotPcieDevice;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Save config space area
- *
- *
- *
- * @param[in] Address PCI address of device.
- * @param[in] StartRegisterAddress Start register address.
- * @param[in] EndRegisterAddress End register address.
- * @param[in] Width Acess width.
- * @param[in] StdHeader Standard header.
- *
- */
- /*----------------------------------------------------------------------------------------*/
-
-VOID
-GnbLibS3SaveConfigSpace (
- IN UINT32 Address,
- IN UINT16 StartRegisterAddress,
- IN UINT16 EndRegisterAddress,
- IN ACCESS_WIDTH Width,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT16 Index;
- UINT16 Delta;
- UINT16 Length;
- Length = (StartRegisterAddress < EndRegisterAddress) ? (EndRegisterAddress - StartRegisterAddress) : (StartRegisterAddress - EndRegisterAddress);
- Delta = LibAmdAccessWidth (Width);
- for (Index = 0; Index <= Length; Index = Index + Delta) {
- GnbLibPciRMW (
- Address | ((StartRegisterAddress < EndRegisterAddress) ? (StartRegisterAddress + Index) : (StartRegisterAddress - Index)),
- Width,
- 0xffffffff,
- 0x0,
- StdHeader
- );
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.h b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.h
deleted file mode 100644
index df5e47e..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Various PCI service routines.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 36567 $ @e \$Date: 2010-08-20 11:35:15 -0700 (Fri, 20 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _PCILIB_H_
-#define _PCILIB_H_
-
-/// PCIe device type
-typedef enum {
- PcieDeviceEndPoint, ///< Endpoint
- PcieDeviceLegacyEndPoint, ///< Legacy endpoint
- PcieDeviceRootComplex = 4, ///< Root complex
- PcieDeviceUpstreamPort, ///< Upstream port
- PcieDeviceDownstreamPort, ///< Downstream Port
- PcieDevicePcieToPcix, ///< PCIe to PCI/PCIx bridge
- PcieDevicePcixToPcie, ///< PCI/PCIx to PCIe bridge
- PcieNotPcieDevice = 0xff ///< unknown device
-} PCIE_DEVICE_TYPE;
-
-typedef UINT32 SCAN_STATUS;
-
-#define SCAN_SKIP_FUNCTIONS 0x1
-#define SCAN_SKIP_DEVICES 0x2
-#define SCAN_SKIP_BUSES 0x4
-#define SCAN_SUCCESS 0x0
-
-// Forward declaration needed for multi-structure mutual references
-AGESA_FORWARD_DECLARATION (GNB_PCI_SCAN_DATA);
-
-typedef SCAN_STATUS (*GNB_SCAN_CALLBACK) (
- IN PCI_ADDR Device,
- IN OUT GNB_PCI_SCAN_DATA *ScanData
- );
-
-///Scan supporting data
-typedef struct _GNB_PCI_SCAN_DATA {
- GNB_SCAN_CALLBACK GnbScanCallback; ///< Callback for each found device
- AMD_CONFIG_PARAMS *StdHeader; ///< Standard configuration header
-};
-
-#define PCIE_CAP_ID 0x10
-#define PCIE_LINK_CAP_REGISTER 0x0C
-#define PCIE_LINK_CTRL_REGISTER 0x10
-#define PCIE_DEVICE_CAP_REGISTER 0x04
-#define PCIE_ASPM_L1_SUPPORT_CAP BIT11
-
-BOOLEAN
-GnbLibPciIsDevicePresent (
- IN UINT32 Address,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-BOOLEAN
-GnbLibPciIsBridgeDevice (
- IN UINT32 Address,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-BOOLEAN
-GnbLibPciIsMultiFunctionDevice (
- IN UINT32 Address,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-BOOLEAN
-GnbLibPciIsPcieDevice (
- IN UINT32 Address,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-UINT8
-GnbLibFindPciCapability (
- IN UINT32 Address,
- IN UINT8 CapabilityId,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-GnbLibPciScan (
- IN PCI_ADDR Start,
- IN PCI_ADDR End,
- IN GNB_PCI_SCAN_DATA *ScanData
- );
-
-VOID
-GnbLibPciScanSecondaryBus (
- IN PCI_ADDR Bridge,
- IN OUT GNB_PCI_SCAN_DATA *ScanData
- );
-
-PCIE_DEVICE_TYPE
-GnbLibGetPcieDeviceType (
- IN PCI_ADDR Device,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-GnbLibS3SaveConfigSpace (
- IN UINT32 Address,
- IN UINT16 StartRegisterAddress,
- IN UINT16 EndRegisterAddress,
- IN ACCESS_WIDTH Width,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c
deleted file mode 100644
index ac27a30..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Service procedure to access PCI config space registers
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "Porting.h"
-#include "AMD.h"
-#include "amdlib.h"
-#include "GnbLibPciAcc.h"
-#include "S3SaveState.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCIACC_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Write PCI registers
- *
- *
- *
- * @param[in] Address PCI address (as presented in PCI_ADDR.AddressValue)
- * @param[in] Width Access width
- * @param[in] Value Pointer to value
- * @param[in] StdHeader Pointer to standard header
- */
-VOID
-GnbLibPciWrite (
- IN UINT32 Address,
- IN ACCESS_WIDTH Width,
- IN VOID *Value,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- PCI_ADDR PciAddress;
- PciAddress.AddressValue = Address;
- if (Width >= AccessS3SaveWidth8) {
- S3_SAVE_PCI_WRITE (StdHeader, PciAddress, Width, Value);
- }
- LibAmdPciWrite (Width, PciAddress, Value, StdHeader);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Read PCI registers
- *
- *
- *
- * @param[in] Address PCI address (as presented in PCI_ADDR.AddressValue)
- * @param[in] Width Access width
- * @param[out] Value Pointer to value
- * @param[in] StdHeader Pointer to standard header
- */
-
-VOID
-GnbLibPciRead (
- IN UINT32 Address,
- IN ACCESS_WIDTH Width,
- OUT VOID *Value,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- PCI_ADDR PciAddress;
- PciAddress.AddressValue = Address;
- LibAmdPciRead (Width, PciAddress, Value, StdHeader);
-}
-
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Poll PCI reg
- *
- *
- *
- * @param[in] Address PCI address (as presented in PCI_ADDR.AddressValue)
- * @param[in] Width Access width
- * @param[in] Data Data to compare
- * @param[in] DataMask AND mask
- * @param[in] StdHeader Standard configuration header
- */
-
-VOID
-GnbLibPciPoll (
- IN UINT32 Address,
- IN ACCESS_WIDTH Width,
- IN VOID *Data,
- IN VOID *DataMask,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- PCI_ADDR PciAddress;
- PciAddress.AddressValue = Address;
- if (Width >= AccessS3SaveWidth8) {
- S3_SAVE_PCI_POLL (StdHeader, PciAddress, Width, Data, DataMask, 0xffffffff);
- }
- LibAmdPciPoll (Width, PciAddress, Data, DataMask, 0xffffffff, StdHeader);
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.h b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.h
deleted file mode 100644
index 8e3fb0d..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Service procedure to access PCI config space registers
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _PCIACCLIB_H_
-#define _PCIACCLIB_H_
-
-VOID
-GnbLibPciWrite (
- IN UINT32 Address,
- IN ACCESS_WIDTH Width,
- IN VOID *Value,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-GnbLibPciRead (
- IN UINT32 Address,
- IN ACCESS_WIDTH Width,
- OUT VOID *Value,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-GnbLibPciPoll (
- IN UINT32 Address,
- IN ACCESS_WIDTH Width,
- IN VOID *Data,
- IN VOID *DataMask,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c
deleted file mode 100644
index 38e4b6a..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Initialize GFX configuration data structure.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39255 $ @e \$Date: 2010-10-08 11:27:41 -0700 (Fri, 08 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "heapManager.h"
-#include "Gnb.h"
-#include "GnbGfx.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include "GfxConfigPost.h"
-#include "OptionGnb.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGENV_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-extern GNB_BUILD_OPTIONS GnbBuildOptions;
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get UMA info
- *
- * UMA info stored on heap by memory module
- *
- * @param[out] UmaInfo Pointer to UMA info structure
- * @param[in] StdHeader Standard configuration header
- */
-
-VOID
-GfxGetUmaInfo (
- OUT UMA_INFO *UmaInfo,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UMA_INFO *MemUmaInfo;
-
- MemUmaInfo = GnbLocateHeapBuffer (AMD_UMA_INFO_HANDLE, StdHeader);
- if (MemUmaInfo == NULL) {
- LibAmdMemFill (UmaInfo, 0x00, sizeof (UMA_INFO), StdHeader);
- UmaInfo->UmaMode = UMA_NONE;
- } else {
- LibAmdMemCopy (UmaInfo, MemUmaInfo, sizeof (UMA_INFO), StdHeader);
- if ((UmaInfo->UmaBase == 0) || (UmaInfo->UmaSize == 0)) {
- UmaInfo->UmaMode = UMA_NONE;
- }
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Locate UMA configuration data
- *
- *
- *
- * @param[in] StdHeader Standard configuration header
- * @param[in,out] Gfx Pointer to GFX configuration
- * @retval AGESA_STATUS Data located
- * @retval AGESA_FATA Data not found
- */
-
-AGESA_STATUS
-GfxLocateConfigData (
- IN AMD_CONFIG_PARAMS *StdHeader,
- OUT GFX_PLATFORM_CONFIG **Gfx
- )
-{
- *Gfx = GnbLocateHeapBuffer (AMD_GFX_PLATFORM_CONFIG_HANDLE, StdHeader);
- if (*Gfx == NULL) {
- IDS_ERROR_TRAP;
- return AGESA_FATAL;
- }
- (*Gfx)->StdHeader = (PVOID) StdHeader;
- return AGESA_SUCCESS;
-}
-
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Update GFX config info at ENV
- *
- *
- *
- * @param[in] StdHeader Standard configuration header
- * @retval AGESA_STATUS Always succeeds
- */
-
-AGESA_STATUS
-GfxConfigEnvInterface (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
-
- AMD_ENV_PARAMS *EnvParamsPtr;
- GFX_PLATFORM_CONFIG *Gfx;
- AGESA_STATUS Status;
- IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigEnvInterface Enter\n");
- Status = GfxLocateConfigData (StdHeader, &Gfx);
- ASSERT (Status == AGESA_SUCCESS);
- if (Status == AGESA_SUCCESS) {
- EnvParamsPtr = (AMD_ENV_PARAMS *)StdHeader;
- Gfx->Gnb3dStereoPinIndex = EnvParamsPtr->GnbEnvConfiguration.Gnb3dStereoPinIndex;
- Gfx->LvdsSpreadSpectrum = EnvParamsPtr->GnbEnvConfiguration.LvdsSpreadSpectrum;
- Gfx->LvdsSpreadSpectrumRate = EnvParamsPtr->GnbEnvConfiguration.LvdsSpreadSpectrumRate;
- GfxGetUmaInfo (&Gfx->UmaInfo, StdHeader);
- }
- GNB_DEBUG_CODE (
- GfxConfigDebugDump (Gfx);
- );
- IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigEnvInterface Exit [0x%x]\n", Status);
- return Status;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c
deleted file mode 100644
index 12a8dc6..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Initialize GFX configuration data structure.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39255 $ @e \$Date: 2010-10-08 11:27:41 -0700 (Fri, 08 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "heapManager.h"
-#include "Gnb.h"
-#include "GnbGfx.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include "GfxConfigPost.h"
-#include "OptionGnb.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGPOST_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-extern GNB_BUILD_OPTIONS GnbBuildOptions;
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Allocate UMA configuration data
- *
- *
- *
- * @param[in] StdHeader Standard configuration header
- * @param[in,out] Gfx Pointer to GFX configuration
- * @param[in] PlatformConfig Platform configuration
- * @retval AGESA_STATUS Always succeeds
- */
-
-AGESA_STATUS
-GfxConfigPostInterface (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- GFX_PLATFORM_CONFIG *Gfx;
- AMD_POST_PARAMS *PostParamsPtr;
- AGESA_STATUS Status;
- PostParamsPtr = (AMD_POST_PARAMS *)StdHeader;
- Status = AGESA_SUCCESS;
- IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigPostInterface Enter\n");
- Gfx = GnbAllocateHeapBuffer (AMD_GFX_PLATFORM_CONFIG_HANDLE, sizeof (GFX_PLATFORM_CONFIG), StdHeader);
- ASSERT (Gfx != NULL);
- if (Gfx != NULL) {
- LibAmdMemFill (Gfx, 0x00, sizeof (GFX_PLATFORM_CONFIG), StdHeader);
- if (GnbBuildOptions.IgfxModeAsPcieEp) {
- Gfx->GfxControllerMode = GfxControllerPcieEndpointMode;
- Gfx->GfxPciAddress.AddressValue = MAKE_SBDFO (0, 0, 1, 0, 0);
- } else {
- Gfx->GfxControllerMode = GfxControllerLegacyBridgeMode;
- Gfx->GfxPciAddress.AddressValue = MAKE_SBDFO (0, 1, 5, 0, 0);
- }
- Gfx->StdHeader = (PVOID) StdHeader;
- Gfx->GnbHdAudio = PostParamsPtr->PlatformConfig.GnbHdAudio;
- Gfx->AbmSupport = PostParamsPtr->PlatformConfig.AbmSupport;
- Gfx->DynamicRefreshRate = PostParamsPtr->PlatformConfig.DynamicRefreshRate;
- Gfx->LcdBackLightControl = PostParamsPtr->PlatformConfig.LcdBackLightControl;
- Gfx->ForceGfxMode = GfxEnableAuto;
- Gfx->AmdPlatformType = UserOptions.CfgAmdPlatformType;
- Gfx->GmcClockGating = OptionEnabled;
- Gfx->GmcPowerGating = GnbBuildOptions.GmcPowerGateStutterOnly ? GmcPowerGatingStutterOnly : GmcPowerGatingWidthStutter;
- Gfx->UmaSteering = Garlic;
- GNB_DEBUG_CODE (
- GfxConfigDebugDump (Gfx);
- );
- } else {
- Status = AGESA_ERROR;
- }
- IDS_OPTION_HOOK (IDS_GNB_PLATFORMCFG_OVERRIDE, Gfx, StdHeader);
- IDS_HDT_CONSOLE (GNB_TRACE, "GfxConfigPostInterface Exit [0x%x]\n", Status);
- return Status;
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Debug dump
- *
- *
- *
- * @param[in] Gfx Pointer to GFX configuration
- */
-
-VOID
-GfxConfigDebugDump (
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- IDS_HDT_CONSOLE (GFX_MISC, "<-------------- GFX Config Start ------------->\n");
- IDS_HDT_CONSOLE (GFX_MISC, " HD Audio - %s\n", (Gfx->GnbHdAudio == 0) ? "Disabled" : "Enabled");
- IDS_HDT_CONSOLE (GFX_MISC, " DynamicRefreshRate - 0x%x\n", Gfx->DynamicRefreshRate);
- IDS_HDT_CONSOLE (GFX_MISC, " LcdBackLightControl - 0x%x\n", Gfx->LcdBackLightControl);
- IDS_HDT_CONSOLE (GFX_MISC, " AbmSupport - %s\n", (Gfx->AbmSupport == 0) ? "Disabled" : "Enabled");
- IDS_HDT_CONSOLE (GFX_MISC, " GmcClockGating - %s\n", (Gfx->GmcClockGating == 0) ? "Disabled" : "Enabled");
- IDS_HDT_CONSOLE (GFX_MISC, " GmcPowerGating - %s\n",
- (Gfx->GmcPowerGating == GmcPowerGatingDisabled) ? "Disabled" : (
- (Gfx->GmcPowerGating == GmcPowerGatingStutterOnly) ? "GmcPowerGatingStutterOnly" : (
- (Gfx->GmcPowerGating == GmcPowerGatingWidthStutter) ? "GmcPowerGatingWidthStutter" : "Unknown"))
- );
- IDS_HDT_CONSOLE (GFX_MISC, " UmaSteering - %s\n",
- (Gfx->UmaSteering == Onion) ? "Onion" : (
- (Gfx->UmaSteering == Garlic) ? "Garlic" : "Unknown")
- );
- IDS_HDT_CONSOLE (GFX_MISC, " ForceGfxMode - %s\n",
- (Gfx->ForceGfxMode == GfxEnableAuto) ? "Auto" : (
- (Gfx->ForceGfxMode == GfxEnableForcePrimary) ? "Force Primary" : (
- (Gfx->ForceGfxMode == GfxEnableForceSecondary) ? "Force Secondary" : "Unknown"))
- );
- IDS_HDT_CONSOLE (GFX_MISC, " UmaMode - %s\n", (Gfx->UmaInfo.UmaMode == UMA_NONE) ? "No UMA" : "UMA");
- if (Gfx->UmaInfo.UmaMode != UMA_NONE) {
- IDS_HDT_CONSOLE (GFX_MISC, " UmaBase - 0x%x\n", Gfx->UmaInfo.UmaBase);
- IDS_HDT_CONSOLE (GFX_MISC, " UmaSize - 0x%x\n", Gfx->UmaInfo.UmaSize);
- IDS_HDT_CONSOLE (GFX_MISC, " UmaAttributes - 0x%x\n", Gfx->UmaInfo.UmaAttributes);
- }
- IDS_HDT_CONSOLE (GFX_MISC, "<-------------- GFX Config End --------------->\n");
-
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.h b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.h
deleted file mode 100644
index b262a4c..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Initialize GFX configuration data structure.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39255 $ @e \$Date: 2010-10-08 11:27:41 -0700 (Fri, 08 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _GFXCONFIGPOST_H_
-#define _GFXCONFIGPOST_H_
-
-VOID
-GfxConfigDebugDump (
- IN GFX_PLATFORM_CONFIG *Gfx
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbGfxConfig/GnbGfxConfig.h b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbGfxConfig/GnbGfxConfig.h
deleted file mode 100644
index 127117c..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbGfxConfig/GnbGfxConfig.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Initialize GFX configuration data structure.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39255 $ @e \$Date: 2010-10-08 11:27:41 -0700 (Fri, 08 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _GNBGFXCONFIG_H_
-#define _GNBGFXCONFIG_H_
-
-AGESA_STATUS
-GfxLocateConfigData (
- IN AMD_CONFIG_PARAMS *StdHeader,
- OUT GFX_PLATFORM_CONFIG **Gfx
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c
deleted file mode 100644
index 9b59514..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c
+++ /dev/null
@@ -1,185 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Supporting services to collect discrete GFX card info
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 38931 $ @e \$Date: 2010-10-01 15:50:05 -0700 (Fri, 01 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "amdlib.h"
-#include "Gnb.h"
-#include "GnbGfx.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include "GfxCardInfo.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXCARDINFO_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-typedef struct {
- GNB_PCI_SCAN_DATA ScanData;
- GFX_CARD_CARD_INFO *GfxCardInfo;
- PCI_ADDR BaseBridge;
- UINT8 BusNumber;
-} GFX_SCAN_DATA;
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-SCAN_STATUS
-GfxScanPcieDevice (
- IN PCI_ADDR Device,
- IN OUT GNB_PCI_SCAN_DATA *ScanData
- );
-
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get information about all discrete GFX card in system
- *
- *
- *
- * @param[out] GfxCardInfo Pointer to GFX card info structure
- * @param[in] StdHeader Standard configuration header
- */
-
-VOID
-GfxGetDiscreteCardInfo (
- OUT GFX_CARD_CARD_INFO *GfxCardInfo,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- GFX_SCAN_DATA GfxScanData;
- PCI_ADDR Start;
- PCI_ADDR End;
- IDS_HDT_CONSOLE (GNB_TRACE, "GfxGetDiscreteCardInfo Enter\n");
- Start.AddressValue = MAKE_SBDFO (0, 0, 2, 0, 0);
- End.AddressValue = MAKE_SBDFO (0, 0, 0x1f, 7, 0);
- GfxScanData.BusNumber = 5;
- GfxScanData.ScanData.GnbScanCallback = GfxScanPcieDevice;
- GfxScanData.ScanData.StdHeader = StdHeader;
- GfxScanData.GfxCardInfo = GfxCardInfo;
- GnbLibPciScan (Start, End, &GfxScanData.ScanData);
- IDS_HDT_CONSOLE (GNB_TRACE, "GfxGetDiscreteCardInfo Exit\n");
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Evaluate device
- *
- *
- *
- * @param[in] Device PCI Address
- * @param[in,out] ScanData Scan configuration data
- * @retval Scan Status of 0
- */
-
-SCAN_STATUS
-GfxScanPcieDevice (
- IN PCI_ADDR Device,
- IN OUT GNB_PCI_SCAN_DATA *ScanData
- )
-{
- UINT8 ClassCode;
- UINT32 VendorId;
-
- IDS_HDT_CONSOLE (GFX_MISC, " Evaluate device [%d:%d:%d]\n",
- Device.Address.Bus, Device.Address.Device, Device.Address.Function
- );
-
- if (GnbLibPciIsBridgeDevice (Device.AddressValue, ScanData->StdHeader)) {
- UINT32 SaveBusConfiguration;
- UINT32 Value;
-
- if (Device.Address.Bus == 0) {
- ((GFX_SCAN_DATA *) ScanData)->BaseBridge = Device;
- }
- GnbLibPciRead (Device.AddressValue | 0x18, AccessWidth32, &SaveBusConfiguration, ScanData->StdHeader);
- Value = (((0xFF << 8) | ((GFX_SCAN_DATA *) ScanData)->BusNumber) << 8) | Device.Address.Bus;
- GnbLibPciWrite (Device.AddressValue | 0x18, AccessWidth32, &Value, ScanData->StdHeader);
- ((GFX_SCAN_DATA *) ScanData)->BusNumber++;
-
- GnbLibPciScanSecondaryBus (Device, ScanData);
-
- ((GFX_SCAN_DATA *) ScanData)->BusNumber--;
- GnbLibPciWrite (Device.AddressValue | 0x18, AccessWidth32, &SaveBusConfiguration, ScanData->StdHeader);
- return 0;
- }
- GnbLibPciRead (Device.AddressValue | 0x0b, AccessWidth8, &ClassCode, ScanData->StdHeader);
- if (ClassCode == 3) {
- IDS_HDT_CONSOLE (GFX_MISC, " Found GFX Card\n"
- );
-
- GnbLibPciRead (Device.AddressValue | 0x00, AccessWidth32, &VendorId, ScanData->StdHeader);
- if (!GnbLibPciIsPcieDevice (Device.AddressValue, ScanData->StdHeader)) {
- IDS_HDT_CONSOLE (GFX_MISC, " GFX Card is PCI device\n"
- );
- ((GFX_SCAN_DATA *) ScanData)->GfxCardInfo->PciGfxCardBitmap |= (1 << ((GFX_SCAN_DATA *) ScanData)->BaseBridge.Address.Device);
- return 0;
- }
- if ((UINT16) VendorId == 0x1002) {
- IDS_HDT_CONSOLE (GFX_MISC, " GFX Card is AMD PCIe device\n"
- );
- ((GFX_SCAN_DATA *) ScanData)->GfxCardInfo->AmdPcieGfxCardBitmap |= (1 << ((GFX_SCAN_DATA *) ScanData)->BaseBridge.Address.Device);
- }
- ((GFX_SCAN_DATA *) ScanData)->GfxCardInfo->PcieGfxCardBitmap |= (1 << ((GFX_SCAN_DATA *) ScanData)->BaseBridge.Address.Device);
- }
- return 0;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.h b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.h
deleted file mode 100644
index 289c773..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Supporting services to collect discrete GFX card info
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-#ifndef _GFXCARDINFO_H_
-#define _GFXCARDINFO_H_
-
-/// Graphics card information structure
-typedef struct {
- UINT32 AmdPcieGfxCardBitmap; ///< AMD PCIE graphics card information
- UINT32 PcieGfxCardBitmap; ///< All PCIE graphics card information
- UINT32 PciGfxCardBitmap; ///< All PCI graphics card information
-} GFX_CARD_CARD_INFO;
-
-VOID
-GfxGetDiscreteCardInfo (
- OUT GFX_CARD_CARD_INFO *GfxCardInfo,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c
deleted file mode 100644
index 0a0828e..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c
+++ /dev/null
@@ -1,574 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Service procedure to initialize Integrated Info Table
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 38950 $ @e \$Date: 2010-10-03 23:49:09 -0700 (Sun, 03 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "amdlib.h"
-#include "Gnb.h"
-#include "GnbPcie.h"
-#include "GnbGfx.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1)
-#include GNB_MODULE_DEFINITIONS (GnbPcieConfig)
-#include "GnbGfxFamServices.h"
-#include "GnbRegistersON.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXENUMCONNECTORS_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-typedef struct {
- PCIE_CONNECTOR_TYPE ConnectorType;
- UINT8 DisplayDeviceEnum;
- UINT16 ConnectorEnum;
- UINT16 EncoderEnum;
- UINT8 ConnectorIndex;
-} EXT_CONNECTOR_INFO;
-
-typedef struct {
- UINT8 DisplayDeviceEnum;
- UINT8 DeviceIndex;
- UINT16 DeviceTag;
- UINT16 DeviceAcpiEnum;
-} EXT_DISPLAY_DEVICE_INFO;
-
-typedef struct {
- AGESA_STATUS Status;
- UINT8 DisplayDeviceEnum;
- UINT8 RequestedPriorityIndex;
- UINT8 CurrentPriorityIndex;
- PCIe_ENGINE_CONFIG *Engine;
-} CONNECTOR_ENUM_INFO;
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-AGESA_STATUS
-GfxIntegratedEnumConnectorsForDevice (
- IN UINT8 DisplayDeviceEnum,
- OUT EXT_DISPLAY_PATH *DisplayPathList,
- IN OUT PCIe_PLATFORM_CONFIG *Pcie,
- IN GFX_PLATFORM_CONFIG *Gfx
- );
-
-VOID
-GfxIntegratedDebugDumpDisplayPath (
- IN EXT_DISPLAY_PATH *DisplayPath,
- IN GFX_PLATFORM_CONFIG *Gfx
- );
-
-
-
-EXT_CONNECTOR_INFO ConnectorInfoTable[] = {
- {
- ConnectorTypeDP,
- DEVICE_DFP,
- CONNECTOR_DISPLAYPORT_ENUM,
- ENCODER_NOT_PRESENT,
- 0,
- },
- {
- ConnectorTypeEDP,
- DEVICE_LCD,
- CONNECTOR_eDP_ENUM,
- ENCODER_NOT_PRESENT,
- 1
- },
- {
- ConnectorTypeSingleLinkDVI,
- DEVICE_DFP,
- CONNECTOR_SINGLE_LINK_DVI_D_ENUM,
- ENCODER_NOT_PRESENT,
- 2
- },
- {
- ConnectorTypeDualLinkDVI,
- DEVICE_DFP,
- CONNECTOR_DUAL_LINK_DVI_D_ENUM,
- ENCODER_NOT_PRESENT,
- 3
- },
- {
- ConnectorTypeHDMI,
- DEVICE_DFP,
- CONNECTOR_HDMI_TYPE_A_ENUM,
- ENCODER_NOT_PRESENT,
- 4
- },
- {
- ConnectorTypeTravisDpToVga,
- DEVICE_CRT,
- CONNECTOR_VGA_ENUM,
- ENCODER_TRAVIS_ENUM_ID1,
- 5
- },
- {
- ConnectorTypeTravisDpToLvds,
- DEVICE_LCD,
- CONNECTOR_LVDS_ENUM,
- ENCODER_TRAVIS_ENUM_ID2,
- 6
- },
- {
- ConnectorTypeNutmegDpToVga,
- DEVICE_CRT,
- CONNECTOR_VGA_ENUM,
- ENCODER_ALMOND_ENUM_ID1,
- 5
- },
- {
- ConnectorTypeSingleLinkDviI,
- DEVICE_DFP,
- CONNECTOR_SINGLE_LINK_DVI_I_ENUM,
- ENCODER_NOT_PRESENT,
- 5
- },
- {
- ConnectorTypeCrt,
- DEVICE_CRT,
- CONNECTOR_VGA_ENUM,
- ENCODER_NOT_PRESENT,
- 5
- },
- {
- ConnectorTypeLvds,
- DEVICE_LCD,
- CONNECTOR_LVDS_ENUM,
- ENCODER_NOT_PRESENT,
- 6
- },
- {
- ConnectorTypeAutoDetect,
- DEVICE_LCD,
- CONNECTOR_LVDS_eDP_ENUM,
- ENCODER_TRAVIS_ENUM_ID2,
- 7
- }
-};
-
-UINT8 ConnectorNumerArray[] = {
-// DP eDP SDVI-D DDVI-D HDMI VGA LVDS Auto (eDP, LVDS, Travis LVDS)
- 6, 1, 6, 6, 6, 1, 1, 2
-};
-/*----------------------------------------------------------------------------------------*/
-/**
- * Enumerate all display connectors for specific display device type.
- *
- *
- *
- * @param[in] ConnectorType Connector type (see PCIe_DDI_DATA::ConnectorType).
- * @retval Pointer to EXT_CONNECTOR_INFO
- * @retval NULL if connector type unknown.
- */
-EXT_CONNECTOR_INFO*
-GfxIntegratedExtConnectorInfo (
- IN UINT8 ConnectorType
- )
-{
- UINTN Index;
- for (Index = 0; Index < (sizeof (ConnectorInfoTable) / sizeof (EXT_CONNECTOR_INFO)); Index++) {
- if (ConnectorInfoTable[Index].ConnectorType == ConnectorType) {
- return &ConnectorInfoTable[Index];
- }
- }
- return NULL;
-}
-
-EXT_DISPLAY_DEVICE_INFO DisplayDeviceInfoTable[] = {
- {
- DEVICE_CRT,
- 1,
- ATOM_DEVICE_CRT1_SUPPORT,
- 0x100,
- },
- {
- DEVICE_LCD,
- 1,
- ATOM_DEVICE_LCD1_SUPPORT,
- 0x110,
- },
- {
- DEVICE_DFP,
- 1,
- ATOM_DEVICE_DFP1_SUPPORT,
- 0x210,
- },
- {
- DEVICE_DFP,
- 2,
- ATOM_DEVICE_DFP2_SUPPORT,
- 0x220,
- },
- {
- DEVICE_DFP,
- 3,
- ATOM_DEVICE_DFP3_SUPPORT,
- 0x230,
- },
- {
- DEVICE_DFP,
- 4,
- ATOM_DEVICE_DFP4_SUPPORT,
- 0x240,
- },
- {
- DEVICE_DFP,
- 5,
- ATOM_DEVICE_DFP5_SUPPORT,
- 0x250,
- },
- {
- DEVICE_DFP,
- 6,
- ATOM_DEVICE_DFP6_SUPPORT,
- 0x260,
- }
-};
-/*----------------------------------------------------------------------------------------*/
-/**
- * Enumerate all display connectors for specific display device type.
- *
- *
- *
- * @param[in] DisplayDeviceEnum Display device enum
- * @param[in] DisplayDeviceIndex Display device index
- * @retval Pointer to EXT_DISPLAY_DEVICE_INFO
- * @retval NULL if can not get display device info
- */
-EXT_DISPLAY_DEVICE_INFO*
-GfxIntegratedExtDisplayDeviceInfo (
- IN UINT8 DisplayDeviceEnum,
- IN UINT8 DisplayDeviceIndex
- )
-{
- UINT8 Index;
- UINT8 LastIndex;
- LastIndex = 0xff;
- for (Index = 0; Index < (sizeof (DisplayDeviceInfoTable) / sizeof (EXT_DISPLAY_DEVICE_INFO)); Index++) {
- if (DisplayDeviceInfoTable[Index].DisplayDeviceEnum == DisplayDeviceEnum) {
- LastIndex = Index;
- if (DisplayDeviceInfoTable[Index].DeviceIndex == DisplayDeviceIndex) {
- return &DisplayDeviceInfoTable[Index];
- }
- }
- }
- if (DisplayDeviceEnum == DEVICE_LCD && LastIndex != 0xff) {
- return &DisplayDeviceInfoTable[LastIndex];
- }
- return NULL;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Enumerate all display connectors
- *
- *
- *
- * @param[out] DisplayPathList Display path list
- * @param[in,out] Pcie PCIe platform configuration info
- * @param[in] Gfx Gfx configuration info
- */
-AGESA_STATUS
-GfxIntegratedEnumerateAllConnectors (
- OUT EXT_DISPLAY_PATH *DisplayPathList,
- IN OUT PCIe_PLATFORM_CONFIG *Pcie,
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- AGESA_STATUS AgesaStatus;
- AGESA_STATUS Status;
- AgesaStatus = AGESA_SUCCESS;
- IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedEnumerateAllConnectors Enter\n");
- Status = GfxIntegratedEnumConnectorsForDevice (
- DEVICE_DFP,
- DisplayPathList,
- Pcie,
- Gfx
- );
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
-
- Status = GfxIntegratedEnumConnectorsForDevice (
- DEVICE_CRT,
- DisplayPathList,
- Pcie,
- Gfx
- );
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
-
- Status = GfxIntegratedEnumConnectorsForDevice (
- DEVICE_LCD,
- DisplayPathList,
- Pcie,
- Gfx
- );
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
- IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedEnumerateAllConnectors Exit [0x%x]\n", Status);
- return AgesaStatus;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Enumerate all display connectors for specific display device type.
- *
- *
- *
- * @param[in] Engine Engine configuration info
- * @param[in,out] Buffer Buffer pointer
- * @param[in] Pcie PCIe configuration info
- */
-VOID
-STATIC
-GfxIntegratedDdiInterfaceCallback (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN OUT VOID *Buffer,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- CONNECTOR_ENUM_INFO *ConnectorEnumInfo;
- EXT_CONNECTOR_INFO *ExtConnectorInfo;
- ConnectorEnumInfo = (CONNECTOR_ENUM_INFO*) Buffer;
- ExtConnectorInfo = GfxIntegratedExtConnectorInfo (Engine->Type.Ddi.DdiData.ConnectorType);
- if (ExtConnectorInfo == NULL) {
- AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo->Status);
- PcieConfigDisableEngine (Engine);
- return;
- }
- if (ExtConnectorInfo->DisplayDeviceEnum != ConnectorEnumInfo->DisplayDeviceEnum) {
- //Not device type we are looking for
- return;
- }
- if (Engine->Type.Ddi.DisplayPriorityIndex >= ConnectorEnumInfo->RequestedPriorityIndex &&
- Engine->Type.Ddi.DisplayPriorityIndex < ConnectorEnumInfo->CurrentPriorityIndex) {
- ConnectorEnumInfo->CurrentPriorityIndex = Engine->Type.Ddi.DisplayPriorityIndex;
- ConnectorEnumInfo->Engine = Engine;
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Enumerate all display connectors for specific display device type.
- *
- *
- *
- * @param[in] DisplayDeviceEnum Display device list
- * @param[out] DisplayPathList Display path list
- * @param[in,out] Pcie PCIe configuration info
- * @param[in] Gfx Gfx configuration info
- */
-AGESA_STATUS
-GfxIntegratedEnumConnectorsForDevice (
- IN UINT8 DisplayDeviceEnum,
- OUT EXT_DISPLAY_PATH *DisplayPathList,
- IN OUT PCIe_PLATFORM_CONFIG *Pcie,
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- UINT8 DisplayDeviceIndex;
- CONNECTOR_ENUM_INFO ConnectorEnumInfo;
- EXT_CONNECTOR_INFO *ExtConnectorInfo;
- EXT_DISPLAY_DEVICE_INFO *ExtDisplayDeviceInfo;
- AGESA_STATUS Status;
- UINT8 ConnectorIdArray[sizeof (ConnectorNumerArray)];
- ConnectorEnumInfo.Status = AGESA_SUCCESS;
- DisplayDeviceIndex = 1;
- ConnectorEnumInfo.RequestedPriorityIndex = 0;
- ConnectorEnumInfo.DisplayDeviceEnum = DisplayDeviceEnum;
- LibAmdMemFill (ConnectorIdArray, 0x00, sizeof (ConnectorIdArray), GnbLibGetHeader (Gfx));
- do {
- ConnectorEnumInfo.Engine = NULL;
- ConnectorEnumInfo.CurrentPriorityIndex = 0xff;
- PcieConfigRunProcForAllEngines (
- DESCRIPTOR_ALLOCATED | DESCRIPTOR_VIRTUAL | DESCRIPTOR_DDI_ENGINE,
- GfxIntegratedDdiInterfaceCallback,
- &ConnectorEnumInfo,
- Pcie
- );
- if (ConnectorEnumInfo.Engine == NULL) {
- break; // No more connector support this
- }
- ConnectorEnumInfo.RequestedPriorityIndex = ConnectorEnumInfo.CurrentPriorityIndex + 1;
- ExtConnectorInfo = GfxIntegratedExtConnectorInfo (ConnectorEnumInfo.Engine->Type.Ddi.DdiData.ConnectorType);
- ASSERT (ExtConnectorInfo != NULL);
- ASSERT (ExtConnectorInfo->ConnectorIndex < sizeof (ConnectorIdArray));
- if (ConnectorIdArray[ExtConnectorInfo->ConnectorIndex] >= ConnectorNumerArray[ExtConnectorInfo->ConnectorIndex]) {
- //Run out of supported connectors
- AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status);
- PcieConfigDisableEngine (ConnectorEnumInfo.Engine);
- continue;
- }
- ConnectorEnumInfo.Engine->Type.Ddi.ConnectorId = ConnectorIdArray[ExtConnectorInfo->ConnectorIndex] + 1;
- ExtDisplayDeviceInfo = GfxIntegratedExtDisplayDeviceInfo (DisplayDeviceEnum, DisplayDeviceIndex);
- if (ExtDisplayDeviceInfo == NULL) {
- //Run out of supported display device types
- AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status);
- Status = AGESA_ERROR;
- PcieConfigDisableEngine (ConnectorEnumInfo.Engine);
- }
-
- if ((Gfx->Gnb3dStereoPinIndex != 0) && (ConnectorEnumInfo.Engine->Type.Ddi.DdiData.HdpIndex == (Gfx->Gnb3dStereoPinIndex - 1))) {
- AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status);
- Status = AGESA_ERROR;
- PcieConfigDisableEngine (ConnectorEnumInfo.Engine);
- }
-
- ConnectorEnumInfo.Engine->Type.Ddi.DisplayDeviceId = DisplayDeviceIndex;
-
- Status = GfxFmMapEngineToDisplayPath (ConnectorEnumInfo.Engine, DisplayPathList, Gfx);
- AGESA_STATUS_UPDATE (Status, ConnectorEnumInfo.Status);
- if (Status != AGESA_SUCCESS) {
- continue;
- }
- ConnectorIdArray[ExtConnectorInfo->ConnectorIndex]++;
- DisplayDeviceIndex++;
- } while (ConnectorEnumInfo.Engine != NULL);
- return ConnectorEnumInfo.Status;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Initialize display path for given engine
- *
- *
- *
- * @param[in] Engine Engine configuration info
- * @param[out] DisplayPath Display path list
- * @param[out] SecondaryDisplayPath Secondary display path list
- * @param[in] Gfx Gfx configuration info
- */
-
-VOID
-GfxIntegratedCopyDisplayInfo (
- IN PCIe_ENGINE_CONFIG *Engine,
- OUT EXT_DISPLAY_PATH *DisplayPath,
- OUT EXT_DISPLAY_PATH *SecondaryDisplayPath,
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- EXT_CONNECTOR_INFO *ExtConnectorInfo;
- EXT_DISPLAY_DEVICE_INFO *ExtDisplayDeviceInfo;
- ExtConnectorInfo = GfxIntegratedExtConnectorInfo (Engine->Type.Ddi.DdiData.ConnectorType);
- ExtDisplayDeviceInfo = GfxIntegratedExtDisplayDeviceInfo (ExtConnectorInfo->DisplayDeviceEnum, Engine->Type.Ddi.DisplayDeviceId);
- DisplayPath->usDeviceConnector = ExtConnectorInfo->ConnectorEnum | (Engine->Type.Ddi.ConnectorId << 8);
- DisplayPath->usDeviceTag = ExtDisplayDeviceInfo->DeviceTag;
- DisplayPath->usDeviceACPIEnum = ExtDisplayDeviceInfo->DeviceAcpiEnum;
- DisplayPath->ucExtAUXDDCLutIndex = Engine->Type.Ddi.DdiData.AuxIndex;
- DisplayPath->ucExtHPDPINLutIndex = Engine->Type.Ddi.DdiData.HdpIndex;
- DisplayPath->usExtEncoderObjId = ExtConnectorInfo->EncoderEnum;
- if (Engine->Type.Ddi.DdiData.Mapping[0].ChannelMappingValue == 0) {
- DisplayPath->ChannelMapping.ucChannelMapping = (Engine->EngineData.StartLane < Engine->EngineData.EndLane) ? 0xE4 : 0x1B;
- } else {
- DisplayPath->ChannelMapping.ucChannelMapping = Engine->Type.Ddi.DdiData.Mapping[0].ChannelMappingValue;
- }
- GNB_DEBUG_CODE (
- GfxIntegratedDebugDumpDisplayPath (DisplayPath, Gfx);
- );
- if (Engine->Type.Ddi.DdiData.ConnectorType == ConnectorTypeDualLinkDVI) {
- ASSERT (SecondaryDisplayPath != NULL);
- GNB_DEBUG_CODE (
- GfxIntegratedDebugDumpDisplayPath (DisplayPath, Gfx);
- );
- SecondaryDisplayPath->usDeviceConnector = DisplayPath->usDeviceConnector;
- if (Engine->Type.Ddi.DdiData.Mapping[1].ChannelMappingValue == 0) {
- DisplayPath->ChannelMapping.ucChannelMapping = (Engine->EngineData.StartLane < Engine->EngineData.EndLane) ? 0xE4 : 0x1B;
- } else {
- DisplayPath->ChannelMapping.ucChannelMapping = Engine->Type.Ddi.DdiData.Mapping[1].ChannelMappingValue;
- }
- }
-}
-
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Dump display path settings
- *
- *
- *
- * @param[in] DisplayPath Display path
- * @param[in] Gfx Gfx configuration
- */
-
-VOID
-GfxIntegratedDebugDumpDisplayPath (
- IN EXT_DISPLAY_PATH *DisplayPath,
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- IDS_HDT_CONSOLE (GFX_MISC, " usDeviceConnector = 0x%x\n",
- DisplayPath->usDeviceConnector
- );
- IDS_HDT_CONSOLE (GFX_MISC, " usDeviceTag = 0x%x\n",
- DisplayPath->usDeviceTag
- );
- IDS_HDT_CONSOLE (GFX_MISC, " usDeviceACPIEnum = 0x%x\n",
- DisplayPath->usDeviceACPIEnum
- );
- IDS_HDT_CONSOLE (GFX_MISC, " usExtEncoderObjId = 0x%x\n",
- DisplayPath->usExtEncoderObjId
- );
- IDS_HDT_CONSOLE (GFX_MISC, " ucChannelMapping = 0x%x\n",
- DisplayPath->ChannelMapping.ucChannelMapping
- );
-
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.h b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.h
deleted file mode 100644
index b592965..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Service procedure to initialize Integrated Info Table
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 38519 $ @e \$Date: 2010-09-24 17:08:48 -0700 (Fri, 24 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _GFXENUMCONNECTORS_H_
-#define _GFXENUMCONNECTORS_H_
-
-
-VOID
-GfxIntegratedCopyDisplayInfo (
- IN PCIe_ENGINE_CONFIG *Engine,
- OUT EXT_DISPLAY_PATH *DisplayPath,
- OUT EXT_DISPLAY_PATH *SecondaryDisplayPath,
- IN GFX_PLATFORM_CONFIG *Gfx
- );
-
-AGESA_STATUS
-GfxIntegratedEnumerateAllConnectors (
- OUT EXT_DISPLAY_PATH *DisplayPathList,
- IN OUT PCIe_PLATFORM_CONFIG *Pcie,
- IN GFX_PLATFORM_CONFIG *Gfx
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
deleted file mode 100644
index e42a83f..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
+++ /dev/null
@@ -1,572 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Service procedure to initialize Integrated Info Table
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 38882 $ @e \$Date: 2010-09-30 18:42:57 -0700 (Thu, 30 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "amdlib.h"
-#include "heapManager.h"
-#include "Gnb.h"
-#include "GnbFuseTable.h"
-#include "GnbPcie.h"
-#include "GnbGfx.h"
-#include "GnbFuseTable.h"
-#include "GnbGfxFamServices.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include "GfxPowerPlayTable.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXPOWERPLAYTABLE_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-/// Software state
-typedef struct {
- BOOLEAN Valid; ///< State valid
- UINT16 Classification; ///< State classification
- UINT32 CapsAndSettings; ///< State capability and settings
- UINT32 Vclk; ///< UVD VCLK
- UINT32 Dclk; ///< UVD DCLK
- UINT8 NumberOfDpmStates; ///< Number of DPM states
- UINT8 DpmSatesArray[MAX_NUM_OF_DPM_STATES]; ///< DPM state index array
-} SW_STATE;
-
-/// DPM state
-typedef struct {
- BOOLEAN Valid; ///< State valid
- UINT32 Sclk; ///< Sclk in kHz
- UINT8 Vid; ///< VID index
-} DPM_STATE;
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-VOID
-GfxIntegratedDebugDumpPpTable (
- IN ATOM_PPLIB_POWERPLAYTABLE3 *PpTable,
- IN GFX_PLATFORM_CONFIG *Gfx
- );
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Create new software state
- *
- *
- * @param[in, out] SwStateArray Pointer to SW state array
- * @retval Pointer to state entry in SW state array
- */
-
-SW_STATE*
-GfxPowerPlayCreateSwState (
- IN OUT SW_STATE *SwStateArray
- )
-{
- UINTN Index;
- for (Index = 0; Index < MAX_NUM_OF_SW_STATES; Index++) {
- if (SwStateArray[Index].Valid == FALSE) {
- SwStateArray[Index].Valid = TRUE;
- return &SwStateArray[Index];
- }
- }
- return NULL;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Create new DPM state
- *
- *
- * @param[in, out] DpmStateArray Pointer to DPM state array
- * @param[in] Sclk SCLK in kHz
- * @param[in] Vid Vid index
- * @retval Index of state entry in DPM state array
- */
-
-UINT8
-GfxPowerPlayCreateDpmState (
- IN DPM_STATE *DpmStateArray,
- IN UINT32 Sclk,
- IN UINT8 Vid
- )
-{
- UINT8 Index;
- for (Index = 0; Index < MAX_NUM_OF_DPM_STATES; Index++) {
- if (DpmStateArray[Index].Valid == FALSE) {
- DpmStateArray[Index].Sclk = Sclk;
- DpmStateArray[Index].Vid = Vid;
- DpmStateArray[Index].Valid = TRUE;
- return Index;
- }
- }
- return 0;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Locate existing or Create new DPM state
- *
- *
- * @param[in, out] DpmStateArray Pointer to DPM state array
- * @param[in] Sclk SCLK in kHz
- * @param[in] Vid Vid index
- * @retval Index of state entry in DPM state array
- */
-
-UINT8
-GfxPowerPlayAddDpmState (
- IN DPM_STATE *DpmStateArray,
- IN UINT32 Sclk,
- IN UINT8 Vid
- )
-{
- UINT8 Index;
- for (Index = 0; Index < MAX_NUM_OF_DPM_STATES; Index++) {
- if (DpmStateArray[Index].Valid && Sclk == DpmStateArray[Index].Sclk && Vid == DpmStateArray[Index].Vid) {
- return Index;
- }
- }
- return GfxPowerPlayCreateDpmState (DpmStateArray, Sclk, Vid);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Add reference to DPM state for SW state
- *
- *
- * @param[in, out] SwStateArray Pointer to SW state array
- * @param[in] DpmStateIndex DPM state index
- */
-
-VOID
-GfxPowerPlayAddDpmStateToSwState (
- IN OUT SW_STATE *SwStateArray,
- IN UINT8 DpmStateIndex
- )
-{
- SwStateArray->DpmSatesArray[SwStateArray->NumberOfDpmStates++] = DpmStateIndex;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Copy SW state info to PPTable
- *
- *
- * @param[out] StateArray Pointer to PPtable SW state array
- * @param[in] SwStateArray Pointer to SW state array
- * @param[in] StdHeader Standard configuration header
- */
-UINT32
-GfxPowerPlayCopyStateInfo (
- IN OUT STATE_ARRAY *StateArray,
- IN SW_STATE *SwStateArray,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 Index;
- UINT8 SwStateIndex;
- ATOM_PPLIB_STATE_V2 *States;
- States = &StateArray->States[0];
- SwStateIndex = 0;
- for (Index = 0; Index < MAX_NUM_OF_SW_STATES; Index++) {
- if (SwStateArray[Index].Valid && SwStateArray[Index].NumberOfDpmStates != 0) {
- States->nonClockInfoIndex = SwStateIndex;
- States->ucNumDPMLevels = SwStateArray[Index].NumberOfDpmStates;
- LibAmdMemCopy (
- &States->ClockInfoIndex[0],
- SwStateArray[Index].DpmSatesArray,
- SwStateArray[Index].NumberOfDpmStates,
- StdHeader
- );
- States = (ATOM_PPLIB_STATE_V2*) ((UINT8*) States + sizeof (ATOM_PPLIB_STATE_V2) + sizeof (UINT8) * (States->ucNumDPMLevels - 1));
- SwStateIndex++;
- }
- }
- StateArray->ucNumEntries = SwStateIndex;
- return (UINT32) ((UINT8*) States - (UINT8*) StateArray);
-}
-/*----------------------------------------------------------------------------------------*/
-/**
- * Copy clock info to PPTable
- *
- *
- * @param[out] ClockInfoArray Pointer to clock info array
- * @param[in] DpmStateArray Pointer to DPM state array
- * @param[in] StdHeader Standard configuration header
- */
-
-UINT32
-GfxPowerPlayCopyClockInfo (
- IN CLOCK_INFO_ARRAY *ClockInfoArray,
- IN DPM_STATE *DpmStateArray,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 Index;
- UINT8 ClkStateIndex;
- ClkStateIndex = 0;
- for (Index = 0; Index < MAX_NUM_OF_DPM_STATES; Index++) {
- if (DpmStateArray[Index].Valid == TRUE) {
- ClockInfoArray->ClockInfo[ClkStateIndex].ucEngineClockHigh = (UINT8) (DpmStateArray[Index].Sclk >> 16);
- ClockInfoArray->ClockInfo[ClkStateIndex].usEngineClockLow = (UINT16) (DpmStateArray[Index].Sclk);
- ClockInfoArray->ClockInfo[ClkStateIndex].vddcIndex = DpmStateArray[Index].Vid;
- ClkStateIndex++;
- }
- }
- ClockInfoArray->ucNumEntries = ClkStateIndex;
- ClockInfoArray->ucEntrySize = sizeof (ATOM_PPLIB_SUMO_CLOCK_INFO);
- return sizeof (CLOCK_INFO_ARRAY) + sizeof (ATOM_PPLIB_SUMO_CLOCK_INFO) * (ClkStateIndex) - sizeof (ATOM_PPLIB_SUMO_CLOCK_INFO);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Copy non clock info to PPTable
- *
- *
- * @param[out] NonClockInfoArray Pointer to PPtable Non clock array
- * @param[in] SwStateArray Pointer to SW state array
- * @param[in] StdHeader Standard configuration header
- */
-
-UINT32
-GfxPowerPlayCopyNonClockInfo (
- IN NON_CLOCK_INFO_ARRAY *NonClockInfoArray,
- IN SW_STATE *SwStateArray,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 Index;
- UINT8 NonClkStateIndex;
- NonClkStateIndex = 0;
- for (Index = 0; Index < MAX_NUM_OF_SW_STATES; Index++) {
- if (SwStateArray[Index].Valid && SwStateArray[Index].NumberOfDpmStates != 0) {
- NonClockInfoArray->NonClockInfo[NonClkStateIndex].usClassification = SwStateArray[Index].Classification;
- NonClockInfoArray->NonClockInfo[NonClkStateIndex].ulCapsAndSettings = SwStateArray[Index].CapsAndSettings;
- NonClockInfoArray->NonClockInfo[NonClkStateIndex].ulDCLK = SwStateArray[Index].Dclk;
- NonClockInfoArray->NonClockInfo[NonClkStateIndex].ulVCLK = SwStateArray[Index].Vclk;
- NonClkStateIndex++;
- }
- }
- NonClockInfoArray->ucNumEntries = NonClkStateIndex;
- NonClockInfoArray->ucEntrySize = sizeof (ATOM_PPLIB_NONCLOCK_INFO);
- return sizeof (NON_CLOCK_INFO_ARRAY) + sizeof (ATOM_PPLIB_NONCLOCK_INFO) * NonClkStateIndex - sizeof (ATOM_PPLIB_NONCLOCK_INFO);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Check if fused state valid
- *
- *
- * @param[out] Index State index
- * @param[in] PpFuses Pointer to fuse table
- * @param[in] Gfx Gfx configuration info
- * @retval TRUE State is valid
- */
-BOOLEAN
-GfxPowerPlayIsFusedStateValid (
- IN UINT8 Index,
- IN PP_FUSE_ARRAY *PpFuses,
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- BOOLEAN Result;
- Result = FALSE;
- if (PpFuses->SclkDpmValid[Index] != 0) {
- Result = TRUE;
- if (PpFuses->PolicyLabel[Index] == POLICY_LABEL_BATTERY && (Gfx->AmdPlatformType & AMD_PLATFORM_MOBILE) == 0) {
- Result = FALSE;
- }
- }
- return Result;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get SW state calssification from fuses
- *
- *
- * @param[out] Index State index
- * @param[in] PpFuses Pointer to fuse table
- * @param[in] Gfx Gfx configuration info
- * @retval State classification
- */
-
-UINT16
-GfxPowerPlayGetClassificationFromFuses (
- IN UINT8 Index,
- IN PP_FUSE_ARRAY *PpFuses,
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- UINT16 Classification;
- Classification = 0;
- switch (PpFuses->PolicyFlags[Index]) {
- case 0x1:
- Classification |= ATOM_PPLIB_CLASSIFICATION_NONUVDSTATE;
- break;
- case 0x2:
- Classification |= ATOM_PPLIB_CLASSIFICATION_UVDSTATE;
- break;
- case 0x4:
- //Possible SD + HD state
- break;
- case 0x8:
- Classification |= ATOM_PPLIB_CLASSIFICATION_HDSTATE;
- break;
- case 0x10:
- Classification |= ATOM_PPLIB_CLASSIFICATION_SDSTATE;
- break;
- default:
- break;
- }
- switch (PpFuses->PolicyLabel[Index]) {
- case POLICY_LABEL_BATTERY:
- Classification |= ATOM_PPLIB_CLASSIFICATION_UI_BATTERY;
- break;
- case POLICY_LABEL_PERFORMANCE:
- Classification |= ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE;
- break;
- default:
- break;
- }
- return Classification;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Build PP table
- *
- *
- * @param[out] Buffer Buffer to create PP table
- * @param[in] Gfx Gfx configuration info
- * @retval AGESA_SUCCESS
- * @retval AGESA_ERROR
- */
-
-AGESA_STATUS
-GfxPowerPlayBuildTable (
- OUT VOID *Buffer,
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- ATOM_PPLIB_POWERPLAYTABLE3 *PpTable;
- SW_STATE SwStateArray [MAX_NUM_OF_SW_STATES];
- DPM_STATE DpmStateArray[MAX_NUM_OF_DPM_STATES];
- UINT8 ClkStateIndex;
- UINT8 DpmFuseIndex;
- UINT8 Index;
- UINT32 StateArrayLength;
- UINT32 ClockArrayLength;
- UINT32 NonClockArrayLength;
- SW_STATE *State;
- PP_FUSE_ARRAY *PpFuses;
-
- PpFuses = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, GnbLibGetHeader (Gfx));
- ASSERT (PpFuses != NULL);
- if (PpFuses == NULL) {
- return AGESA_ERROR;
- }
-
- PpTable = (ATOM_PPLIB_POWERPLAYTABLE3 *) Buffer;
- LibAmdMemFill (SwStateArray, 0x00, sizeof (SwStateArray), GnbLibGetHeader (Gfx));
- LibAmdMemFill (DpmStateArray, 0x00, sizeof (DpmStateArray), GnbLibGetHeader (Gfx));
- // Create States from Fuses
- for (Index = 0; Index < MAX_NUM_OF_FUSED_SW_STATES; Index++) {
- if (GfxPowerPlayIsFusedStateValid (Index, PpFuses, Gfx)) {
- //Create new SW State;
- State = GfxPowerPlayCreateSwState (SwStateArray);
- State->Classification = GfxPowerPlayGetClassificationFromFuses (Index, PpFuses, Gfx);
- if ((State->Classification & (ATOM_PPLIB_CLASSIFICATION_HDSTATE | ATOM_PPLIB_CLASSIFICATION_UVDSTATE)) != 0) {
- State->Vclk = (PpFuses->VclkDid[PpFuses->VclkDclkSel[Index]] != 0) ? GfxFmCalculateClock (PpFuses->VclkDid[PpFuses->VclkDclkSel[Index]], GnbLibGetHeader (Gfx)) : 0;
- State->Dclk = (PpFuses->DclkDid[PpFuses->VclkDclkSel[Index]] != 0) ? GfxFmCalculateClock (PpFuses->DclkDid[PpFuses->VclkDclkSel[Index]], GnbLibGetHeader (Gfx)) : 0;
- }
- if ((State->Classification & 0x7) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
- if (Gfx->AbmSupport != 0) {
- State->CapsAndSettings |= ATOM_PPLIB_ENABLE_VARIBRIGHT;
- }
- if (Gfx->DynamicRefreshRate != 0) {
- State->CapsAndSettings |= ATOM_PPLIB_ENABLE_DRR;
- }
- }
- for (DpmFuseIndex = 0; DpmFuseIndex < MAX_NUM_OF_FUSED_DPM_STATES; DpmFuseIndex++) {
- if ((PpFuses->SclkDpmValid[Index] & (1 << DpmFuseIndex)) != 0 ) {
- UINT32 Sclk;
- Sclk = (PpFuses->SclkDpmDid[DpmFuseIndex] != 0) ? GfxFmCalculateClock (PpFuses->SclkDpmDid[DpmFuseIndex], GnbLibGetHeader (Gfx)) : 0;
- if (Sclk != 0) {
- ClkStateIndex = GfxPowerPlayAddDpmState (DpmStateArray, Sclk, PpFuses->SclkDpmVid[DpmFuseIndex]);
- GfxPowerPlayAddDpmStateToSwState (State, ClkStateIndex);
- }
- }
- }
- }
- }
- // Create Boot State
- State = GfxPowerPlayCreateSwState (SwStateArray);
- State->Classification = ATOM_PPLIB_CLASSIFICATION_BOOT;
- ClkStateIndex = GfxPowerPlayAddDpmState (DpmStateArray, 200 * 100, 0);
- GfxPowerPlayAddDpmStateToSwState (State, ClkStateIndex);
-
- // Create Thermal State
- State = GfxPowerPlayCreateSwState (SwStateArray);
- State->Classification = ATOM_PPLIB_CLASSIFICATION_THERMAL;
- ClkStateIndex = GfxPowerPlayAddDpmState (DpmStateArray, 200 * 100, 0);
- GfxPowerPlayAddDpmStateToSwState (State, ClkStateIndex);
-
- //Copy state info to actual PP table
- StateArrayLength = GfxPowerPlayCopyStateInfo (
- &PpTable->StateArray,
- SwStateArray,
- GnbLibGetHeader (Gfx)
- );
- ClockArrayLength = GfxPowerPlayCopyClockInfo (
- (CLOCK_INFO_ARRAY*) ((UINT8 *)&PpTable->StateArray + StateArrayLength),
- DpmStateArray,
- GnbLibGetHeader (Gfx)
- );
- NonClockArrayLength = GfxPowerPlayCopyNonClockInfo (
- (NON_CLOCK_INFO_ARRAY*) ((UINT8 *)&PpTable->StateArray + StateArrayLength + ClockArrayLength),
- SwStateArray,
- GnbLibGetHeader (Gfx)
- );
- //Fill static info
- PpTable->sHeader.ucTableFormatRevision = 6;
- PpTable->sHeader.ucTableContentRevision = 1;
- PpTable->ucDataRevision = PpFuses->PPlayTableRev;
- PpTable->sThermalController.ucType = ATOM_PP_THERMALCONTROLLER_SUMO;
- PpTable->sThermalController.ucFanParameters = ATOM_PP_FANPARAMETERS_NOFAN;
- if ((Gfx->AmdPlatformType & AMD_PLATFORM_MOBILE) != 0) {
- PpTable->ulPlatformCaps |= ATOM_PP_PLATFORM_CAP_POWERPLAY;
- }
- PpTable->usStateArrayOffset = offsetof (ATOM_PPLIB_POWERPLAYTABLE3, StateArray);
- PpTable->usClockInfoArrayOffset = (USHORT) (offsetof (ATOM_PPLIB_POWERPLAYTABLE3, StateArray) + StateArrayLength);
- PpTable->usNonClockInfoArrayOffset = (USHORT) (offsetof (ATOM_PPLIB_POWERPLAYTABLE3, StateArray) + StateArrayLength + ClockArrayLength);
- PpTable->sHeader.usStructureSize = (USHORT) (offsetof (ATOM_PPLIB_POWERPLAYTABLE3, StateArray) + StateArrayLength + ClockArrayLength + NonClockArrayLength);
- PpTable->usFormatID = 7;
- GNB_DEBUG_CODE (
- GfxIntegratedDebugDumpPpTable (PpTable, Gfx);
- );
- return AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Dump PP table
- *
- *
- *
- * @param[in] PpTable Power Play table
- * @param[in] Gfx Gfx configuration info
- */
-
-VOID
-GfxIntegratedDebugDumpPpTable (
- IN ATOM_PPLIB_POWERPLAYTABLE3 *PpTable,
- IN GFX_PLATFORM_CONFIG *Gfx
- )
-{
- UINTN Index;
- UINTN DpmIndex;
- ATOM_PPLIB_STATE_V2 *StatesPtr;
- NON_CLOCK_INFO_ARRAY *NonClockInfoArrayPtr;
- CLOCK_INFO_ARRAY *ClockInfoArrayPtr;
- IDS_HDT_CONSOLE (GFX_MISC, " < --- Power Play Table ------ > \n");
-
- IDS_HDT_CONSOLE (GFX_MISC, " Table Revision = %d\n", PpTable->ucDataRevision
- );
- StatesPtr = PpTable->StateArray.States;
- NonClockInfoArrayPtr = (NON_CLOCK_INFO_ARRAY *) ((UINT8 *) PpTable + PpTable->usNonClockInfoArrayOffset);
- ClockInfoArrayPtr = (CLOCK_INFO_ARRAY *) ((UINT8 *) PpTable + PpTable->usClockInfoArrayOffset);
- for (Index = 0; Index < PpTable->StateArray.ucNumEntries; Index++) {
- IDS_HDT_CONSOLE (GFX_MISC, " State #%d\n", Index + 1
- );
- IDS_HDT_CONSOLE (GFX_MISC, " Classification 0x%x\n",
- NonClockInfoArrayPtr->NonClockInfo[StatesPtr->nonClockInfoIndex].usClassification
- );
- IDS_HDT_CONSOLE (GFX_MISC, " VCLK = %dkHz\n",
- NonClockInfoArrayPtr->NonClockInfo[StatesPtr->nonClockInfoIndex].ulVCLK
- );
- IDS_HDT_CONSOLE (GFX_MISC, " DCLK = %dkHz\n",
- NonClockInfoArrayPtr->NonClockInfo[StatesPtr->nonClockInfoIndex].ulDCLK
- );
- IDS_HDT_CONSOLE (GFX_MISC, " DPM State Index: ");
- for (DpmIndex = 0; DpmIndex < StatesPtr->ucNumDPMLevels; DpmIndex++) {
- IDS_HDT_CONSOLE (GFX_MISC, "%d ",
- StatesPtr->ClockInfoIndex [DpmIndex]
- );
- }
- IDS_HDT_CONSOLE (GFX_MISC, "\n");
- StatesPtr = (ATOM_PPLIB_STATE_V2 *) ((UINT8 *) StatesPtr + sizeof (ATOM_PPLIB_STATE_V2) + StatesPtr->ucNumDPMLevels - 1);
- }
- for (Index = 0; Index < ClockInfoArrayPtr->ucNumEntries; Index++) {
- UINT32 Sclk;
- Sclk = ClockInfoArrayPtr->ClockInfo[Index].usEngineClockLow | (ClockInfoArrayPtr->ClockInfo[Index].ucEngineClockHigh << 16);
- IDS_HDT_CONSOLE (GFX_MISC, " DPM State #%d\n",
- Index
- );
- IDS_HDT_CONSOLE (GFX_MISC, " SCLK = %d\n",
- ClockInfoArrayPtr->ClockInfo[Index].usEngineClockLow | (ClockInfoArrayPtr->ClockInfo[Index].ucEngineClockHigh << 16)
- );
- IDS_HDT_CONSOLE (GFX_MISC, " Cac = %d\n",
- ClockInfoArrayPtr->ClockInfo[Index].leakage
- );
- IDS_HDT_CONSOLE (GFX_MISC, " VID index = %d\n",
- ClockInfoArrayPtr->ClockInfo[Index].vddcIndex
- );
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.h b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.h
deleted file mode 100644
index 6fe93d7..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.h
+++ /dev/null
@@ -1,200 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Service procedure to initialize Power Play Table
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _GFXPOWERPLAYTABLE_H_
-#define _GFXPOWERPLAYTABLE_H_
-
-#pragma pack (push, 1)
-
-#define POLICY_LABEL_BATTERY 0x1
-#define POLICY_LABEL_PERFORMANCE 0x2
-
-#define MAX_NUM_OF_SW_STATES 10
-#define MAX_NUM_OF_DPM_STATES 10
-#define MAX_NUM_OF_FUSED_DPM_STATES 5
-#define MAX_NUM_OF_FUSED_SW_STATES 6
-/// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps
-#define ATOM_PP_PLATFORM_CAP_BACKBIAS 1
-#define ATOM_PP_PLATFORM_CAP_POWERPLAY 2
-#define ATOM_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 4
-#define ATOM_PP_PLATFORM_CAP_ASPM_L0s 8
-#define ATOM_PP_PLATFORM_CAP_ASPM_L1 16
-#define ATOM_PP_PLATFORM_CAP_HARDWAREDC 32
-#define ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY 64
-#define ATOM_PP_PLATFORM_CAP_STEPVDDC 128
-#define ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL 256
-#define ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL 512
-#define ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 1024
-#define ATOM_PP_PLATFORM_CAP_HTLINKCONTROL 2048
-#define ATOM_PP_PLATFORM_CAP_MVDDCONTROL 4096
-#define ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT 0x2000 // Go to boot state on alerts, e.g. on an AC->DC transition.
-#define ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT 0x4000 // Do NOT wait for VBLANK during an alert (e.g. AC->DC transition).
-#define ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL 0x8000 // Does
-#define ATOM_PP_PLATFORM_CAP_REGULATOR_HOT 0x00010000 // Enable the 'regulator hot' feature.
-#define ATOM_PP_PLATFORM_CAP_BACO 0x00020000 // Does the driver supports BACO state.
-
-
-#define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY 1
-#define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED 3
-#define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE 5
-
-#define ATOM_PPLIB_CLASSIFICATION_BOOT 0x0008
-#define ATOM_PPLIB_CLASSIFICATION_THERMAL 0x0010
-#define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE 0x0020
-#define ATOM_PPLIB_CLASSIFICATION_REST 0x0040
-#define ATOM_PPLIB_CLASSIFICATION_FORCED 0x0080
-#define ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE 0x0100
-#define ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE 0x0200
-#define ATOM_PPLIB_CLASSIFICATION_UVDSTATE 0x0400
-#define ATOM_PPLIB_CLASSIFICATION_3DLOW 0x0800
-#define ATOM_PPLIB_CLASSIFICATION_ACPI 0x1000
-#define ATOM_PPLIB_CLASSIFICATION_HD2STATE 0x2000
-#define ATOM_PPLIB_CLASSIFICATION_HDSTATE 0x4000
-#define ATOM_PPLIB_CLASSIFICATION_SDSTATE 0x8000
-#define ATOM_PPLIB_CLASSIFICATION_NONUVDSTATE 0x0000
-
-#define ATOM_PPLIB_ENABLE_VARIBRIGHT 0x00008000
-#define ATOM_PPLIB_ENABLE_DRR 0x00080000
-
-#define ATOM_PP_FANPARAMETERS_NOFAN 0x80
-#define ATOM_PP_THERMALCONTROLLER_SUMO 0x0E
-
-/// DPM state info
-typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO {
- USHORT usEngineClockLow; ///< Sclk [15:0] (Sclk in 10khz)
- UCHAR ucEngineClockHigh; ///< Sclk [23:16](Sclk in 10khz)
- UCHAR vddcIndex; ///< 2-bit VDDC index;
- UCHAR leakage; ///< Absolute Cac value;
- UCHAR rsv; ///< Reserved
- USHORT rsv1; ///< Reserved
- ULONG rsv2[2]; ///< Reserved
-} ATOM_PPLIB_SUMO_CLOCK_INFO;
-
-/// Non clock info
-typedef struct _ATOM_PPLIB_NONCLOCK_INFO {
- USHORT usClassification; ///< State classification see ATOM_PPLIB_CLASSIFICATION_*
- UCHAR ucMinTemperature; ///< Reserved
- UCHAR ucMaxTemperature; ///< Reserved
- ULONG ulCapsAndSettings; ///< Capability Setting (ATOM_PPLIB_ENABLE_DRR or ATOM_PPLIB_ENABLE_VARIBRIGHT or 0)
- UCHAR Reserved1; ///< Reserved
- USHORT Reserved2; ///< Reserved
- ULONG ulVCLK; ///< UVD clocks VCLK unit is in 10KHz
- ULONG ulDCLK; ///< UVD clocks DCLK unit is in 10KHz
- UCHAR ucUnused[5]; ///< Reserved
-} ATOM_PPLIB_NONCLOCK_INFO;
-
-/// Thermal controller info stub
-typedef struct _ATOM_PPLIB_THERMALCONTROLLER {
- UCHAR ucType; ///< Reserved. Should be set 0xE
- UCHAR ucI2cLine; ///< Reserved. Should be set 0
- UCHAR ucI2cAddress; ///< Reserved. Should be set 0
- UCHAR ucFanParameters; ///< Reserved. Should be set 0x80
- UCHAR ucFanMinRPM; ///< Reserved. Should be set 0
- UCHAR ucFanMaxRPM; ///< Reserved. Should be set 0
- UCHAR ucReserved; ///< Reserved. Should be set 0
- UCHAR ucFlags; ///< Reserved. Should be set 0
-} ATOM_PPLIB_THERMALCONTROLLER;
-
-/// SW state info
-typedef struct _ATOM_PPLIB_STATE_V2 {
- UCHAR ucNumDPMLevels; ///< Number of valid DPM levels in this state
- UCHAR nonClockInfoIndex; ///< Index to the array of NonClockInfos
- UCHAR ClockInfoIndex[1]; ///< Array of DPM states. Actual number calculated during state enumeration
-} ATOM_PPLIB_STATE_V2;
-
-/// SW state Array
-typedef struct {
- UCHAR ucNumEntries; ///< Number of SW states
- ATOM_PPLIB_STATE_V2 States[1]; ///< SW state info. Actual number calculated during state enumeration
-} STATE_ARRAY;
-
-/// Clock info Array
-typedef struct {
- UCHAR ucNumEntries; ///< Number of ClockInfo entries
- UCHAR ucEntrySize; ///< size of ATOM_PPLIB_SUMO_CLOCK_INFO
- ATOM_PPLIB_SUMO_CLOCK_INFO ClockInfo[1]; ///< Clock info array. Size will be determined dynamically base on fuses
-} CLOCK_INFO_ARRAY;
-
-/// Non clock info Array
-typedef struct {
-
- UCHAR ucNumEntries; ///< Number of Entries;
- UCHAR ucEntrySize; ///< Size of NonClockInfo
- ATOM_PPLIB_NONCLOCK_INFO NonClockInfo[1]; ///< Non clock info array
-} NON_CLOCK_INFO_ARRAY;
-
-/// Power Play table
-typedef struct _ATOM_PPLIB_POWERPLAYTABLE3 {
- ATOM_COMMON_TABLE_HEADER sHeader; ///< Common header
- UCHAR ucDataRevision; ///< Revision of PP table
- UCHAR Reserved1[4]; ///< Reserved
- USHORT usStateArrayOffset; ///< Offset from start of this table to array of ucNumStates ATOM_PPLIB_STATE structures
- USHORT usClockInfoArrayOffset; ///< Offset from start of the table to ClockInfoArray
- USHORT usNonClockInfoArrayOffset; ///< Offset from Start of the table to NonClockInfoArray
- USHORT Reserved2[2]; ///< Reserved
- USHORT usTableSize; ///< the size of this structure, or the extended structure
- ULONG ulPlatformCaps; ///< See ATOM_PPLIB_CAPS_*
- ATOM_PPLIB_THERMALCONTROLLER sThermalController; ///< Thermal controller stub.
- USHORT Reserved4[2]; ///< Reserved
- UCHAR Reserved5; ///< Reserved
- USHORT Reserved6; ///< Reserved
- USHORT usFormatID; ///< Format ID
- USHORT Reserved7[2]; ///< Reserved
- STATE_ARRAY StateArray; ///< Array to hold the states.
- CLOCK_INFO_ARRAY ClockInfoArray; ///< Array to hold clock info.
- NON_CLOCK_INFO_ARRAY NonClockInfoArray; ///< Array to hold non clock info.
-} ATOM_PPLIB_POWERPLAYTABLE3;
-
-#pragma pack (pop)
-
-
-AGESA_STATUS
-GfxPowerPlayBuildTable (
- OUT VOID *Buffer,
- IN GFX_PLATFORM_CONFIG *Gfx
- );
-
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.h b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.h
deleted file mode 100644
index f76688b..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Gfx Library
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-#ifndef _GNBGFXINITLIBV1_H_
-#define _GNBGFXINITLIBV1_H_
-
-#include "GnbGfx.h"
-#include "GfxEnumConnectors.h"
-#include "GfxPowerPlayTable.h"
-#include "GfxCardInfo.h"
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c
deleted file mode 100644
index 468e57f..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c
+++ /dev/null
@@ -1,247 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * NB services
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 38931 $ @e \$Date: 2010-10-01 15:50:05 -0700 (Fri, 01 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "amdlib.h"
-#include "Gnb.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include "GnbRegistersON.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_MODULES_GNBNBINITLIBV1_GNBNBINITLIBV1_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init NB set top of memory
- *
- *
- *
- * @param[in] NbPciAddress Gnb PCI address
- * @param[in] StdHeader Standard Configuration Header
- */
-
-AGESA_STATUS
-GnbSetTom (
- IN PCI_ADDR NbPciAddress,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_STATUS Status;
- UINT64 MsrData;
- UINT32 Value;
- Status = AGESA_SUCCESS;
- //Read memory size below 4G from MSR C001_001A
- LibAmdMsrRead (TOP_MEM, &MsrData, StdHeader);
- //Write to NB register 0x90
- Value = (UINT32)MsrData & 0xFF800000; //Keep bits 31:23
- GnbLibPciRMW (
- NbPciAddress.AddressValue | D0F0x90_ADDRESS,
- AccessS3SaveWidth32,
- 0x007FFFFF,
- Value,
- StdHeader
- );
- if (Value == 0) {
- Status = AGESA_WARNING;
- }
-
- LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader);
- if ((MsrData & BIT21) != 0) {
- //Read memory size above 4G from MSR C001_001D
- LibAmdMsrRead (TOP_MEM2, &MsrData, StdHeader);
- // Write memory size[39:32] to indirect register 1A[7:0]
- Value = (UINT32) ((MsrData >> 32) & 0xFF);
- GnbLibPciIndirectRMW (
- NbPciAddress.AddressValue | D0F0x60_ADDRESS,
- D0F0x64_x1A_ADDRESS | IOC_WRITE_ENABLE,
- AccessS3SaveWidth32,
- 0xFFFFFF00,
- Value,
- StdHeader
- );
-
- // Write memory size[31:23] to indirect register 19[31:23] and enable memory through bit 0
- Value = (UINT32)MsrData & 0xFF800000; //Keep bits 31:23
- Value |= BIT0; // Enable top of memory
- GnbLibPciIndirectRMW (
- NbPciAddress.AddressValue | D0F0x60_ADDRESS,
- D0F0x64_x19_ADDRESS | IOC_WRITE_ENABLE,
- AccessS3SaveWidth32,
- 0x007FFFFF,
- Value,
- StdHeader
- );
- }
- return Status;
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Avoid LPC DMA transaction deadlock
- *
- *
- *
- * @param[in] NbPciAddress Gnb PCI address
- * @param[in] StdHeader Standard Configuration Header
- */
-
-VOID
-GnbLpcDmaDeadlockPrevention (
- IN PCI_ADDR NbPciAddress,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- // For GPP Link core, enable special NP memory write protocol on the processor side PCIE controller
- GnbLibPciIndirectRMW (
- NbPciAddress.AddressValue | D0F0xE0_ADDRESS,
- CORE_SPACE (1, 0x10),
- AccessWidth32,
- 0xFFFFFFFF,
- 1 << 9,
- StdHeader
- );
-
- //Enable special NP memory write protocol in ORB
- GnbLibPciIndirectRMW (
- NbPciAddress.AddressValue | D0F0x94_ADDRESS,
- D0F0x98_x06_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET),
- AccessS3SaveWidth32,
- 0xFFFFFFFF,
- 1 << D0F0x98_x06_UmiNpMemWrEn_OFFSET,
- StdHeader
- );
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * NB Dynamic Wake
- * ORB_CNB_Wake signal is used to inform the CNB NCLK controller and GNB LCLK controller
- * that ORB is (or will soon) push data into the synchronizer FIFO (i.e. wake is high).
- *
- * @param[in] NbPciAddress Gnb PCI address
- * @param[in] StdHeader Standard Configuration Header
- */
-
-VOID
-GnbOrbDynamicWake (
- IN PCI_ADDR NbPciAddress,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
-
- D0F0x98_x2C_STRUCT D0F0x98_x2C;
-
- GnbLibPciIndirectRead (
- NbPciAddress.AddressValue | D0F0x94_ADDRESS,
- D0F0x98_x2C_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET),
- AccessWidth32,
- &D0F0x98_x2C.Value,
- StdHeader
- );
-
- // Enable Dynamic wake
- // Wake Hysteresis timer value. Specifies the number of SMU pulses to count.
- D0F0x98_x2C.Field.DynWakeEn = 1;
- D0F0x98_x2C.Field.WakeHysteresis = 0x64;
-
- IDS_OPTION_HOOK (IDS_GNB_ORBDYNAMIC_WAKE, &D0F0x98_x2C, StdHeader);
-
- GnbLibPciIndirectWrite (
- NbPciAddress.AddressValue | D0F0x94_ADDRESS,
- D0F0x98_x2C_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET),
- AccessS3SaveWidth32,
- &D0F0x98_x2C.Value,
- StdHeader
- );
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Lock NB registers
- *
- *
- *
- * @param[in] NbPciAddress Gnb PCI address
- * @param[in] StdHeader Standard Configuration Header
- */
-
-VOID
-GnbLock (
- IN PCI_ADDR NbPciAddress,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- GnbLibPciIndirectWriteField (
- NbPciAddress.AddressValue | D0F0x60_ADDRESS,
- D0F0x64_x00_ADDRESS | IOC_WRITE_ENABLE,
- D0F0x64_x00_HwInitWrLock_OFFSET,
- D0F0x64_x00_HwInitWrLock_WIDTH,
- 0x1,
- TRUE,
- StdHeader
- );
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h
deleted file mode 100644
index 427fb93..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * NB services
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _GNBNBINITLIBV1_H_
-#define _GNBNBINITLIBV1_H_
-
-
-AGESA_STATUS
-GnbSetTom (
- IN PCI_ADDR NbPciAddress,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-GnbLpcDmaDeadlockPrevention (
- IN PCI_ADDR NbPciAddress,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-GnbOrbDynamicWake (
- IN PCI_ADDR NbPciAddress,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-GnbLock (
- IN PCI_ADDR NbPciAddress,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c
deleted file mode 100644
index b28e1a9..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c
+++ /dev/null
@@ -1,351 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe ALIB
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39033 $ @e \$Date: 2010-10-04 14:23:23 -0700 (Mon, 04 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "amdlib.h"
-#include "heapManager.h"
-#include "cpuLateInit.h"
-#include "cpuRegisters.h"
-#include "Gnb.h"
-#include "GnbPcie.h"
-#include "GnbPcieFamServices.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include GNB_MODULE_DEFINITIONS (GnbPcieConfig)
-#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1)
-#include "GnbRegistersON.h"
-#include "OptionGnb.h"
-#include "PcieAlib.h"
-#include "GnbFuseTable.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_MODULES_GNBPCIEALIBV1_PCIEALIB_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-extern UINT8 AlibSsdt[];
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-VOID
-STATIC
-PcieAlibSetPortGenCapabilityCallback (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN OUT VOID *Buffer,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-STATIC
-PcieAlibSetPortInfoCallback (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN OUT VOID *Buffer,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-AGESA_STATUS
-PcieAlibBuildAcpiTable (
- IN AMD_CONFIG_PARAMS *StdHeader,
- OUT VOID **AlibSsdtPtr
- );
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Create ACPI ALIB SSDT table
- *
- *
- *
- * @param[in] StdHeader Standard configuration header
- * @retval AGESA_STATUS
- */
-
-AGESA_STATUS
-PcieAlibFeature (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AMD_LATE_PARAMS *LateParamsPtr;
- LateParamsPtr = (AMD_LATE_PARAMS*) StdHeader;
- return PcieAlibBuildAcpiTable (StdHeader, &LateParamsPtr->AcpiAlib);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Build ALIB ACPI table
- *
- *
- *
- * @param[in] StdHeader Standard Configuration Header
- * @param[in,out] AlibSsdtPtr Pointer to pointer to ALIB SSDT table
- * @retval AGESA_SUCCESS
- * @retval AGESA_ERROR
- */
-
-AGESA_STATUS
-PcieAlibBuildAcpiTable (
- IN AMD_CONFIG_PARAMS *StdHeader,
- OUT VOID **AlibSsdtPtr
- )
-{
- AGESA_STATUS Status;
- UINT32 AmlObjName;
- PCIe_PLATFORM_CONFIG *Pcie;
- PP_FUSE_ARRAY *PpFuseArray;
- VOID *AlibSsdtBuffer;
- VOID *AmlObjPtr;
- UINT8 SclkVidArray[4];
- UINT8 BootUpVid;
- UINT8 BootUpVidIndex;
- UINT8 Gen1VidIndex;
- UINTN Index;
- UINTN AlibSsdtlength;
- Status = AGESA_SUCCESS;
- AlibSsdtlength = ((ACPI_TABLE_HEADER*) &AlibSsdt[0])->TableLength;
- if (*AlibSsdtPtr == NULL) {
- AlibSsdtBuffer = GnbAllocateHeapBuffer (
- AMD_ACPI_ALIB_BUFFER_HANDLE,
- AlibSsdtlength,
- StdHeader
- );
- ASSERT (AlibSsdtBuffer != NULL);
- if (AlibSsdtBuffer == NULL) {
- return AGESA_ERROR;
- }
- *AlibSsdtPtr = AlibSsdtBuffer;
- } else {
- AlibSsdtBuffer = *AlibSsdtPtr;
- }
- // Copy template to buffer
- LibAmdMemCopy (AlibSsdtBuffer, &AlibSsdt[0], AlibSsdtlength, StdHeader);
- // Set PCI MMIO configuration
- AmlObjName = '10DA';
- AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
- if (AmlObjPtr != NULL) {
- UINT64 MsrRegister;
- LibAmdMsrRead (MSR_MMIO_Cfg_Base, &MsrRegister, StdHeader);
- if ((MsrRegister & BIT0) != 0 && (MsrRegister & 0xFFFFFFFF00000000) == 0) {
- *(UINT32*)((UINT8*)AmlObjPtr + 5) = (UINT32)(MsrRegister & 0xFFFFF00000);
- } else {
- Status = AGESA_ERROR;
- }
- } else {
- Status = AGESA_ERROR;
- }
- // Set voltage configuration
- PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader);
- if (PpFuseArray != NULL) {
- AmlObjName = '30DA';
- AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
- ASSERT (AmlObjPtr != NULL);
- if (AmlObjPtr != NULL) {
- *(UINT8*)((UINT8*)AmlObjPtr + 5) = PpFuseArray->PcieGen2Vid;
- } else {
- Status = AGESA_ERROR;
- }
- } else {
- Status = AGESA_ERROR;
- }
- GnbLibPciRead (
- MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS),
- AccessWidth32,
- &SclkVidArray[0],
- StdHeader
- );
- Gen1VidIndex = 0;
- BootUpVidIndex = 0;
- BootUpVid = 0xff;
- for (Index = 0; Index < 4; Index++) {
- if (SclkVidArray[Index] > SclkVidArray[Gen1VidIndex]) {
- Gen1VidIndex = (UINT8) Index;
- }
- if (SclkVidArray[Index] != 0 && SclkVidArray[Index] < BootUpVid) {
- BootUpVid = SclkVidArray[Index];
- BootUpVidIndex = (UINT8) Index;
- }
- }
- AmlObjName = '40DA';
- AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
- ASSERT (AmlObjPtr != NULL);
- if (AmlObjPtr != NULL) {
- *(UINT8*)((UINT8*)AmlObjPtr + 5) = Gen1VidIndex;
- } else {
- Status = AGESA_ERROR;
- }
- AmlObjName = '50DA';
- AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
- ASSERT (AmlObjPtr != NULL);
- if (AmlObjPtr != NULL) {
- *(UINT8*)((UINT8*)AmlObjPtr + 5) = BootUpVidIndex;
- } else {
- Status = AGESA_ERROR;
- }
- // Set PCIe configuration
- if (PcieLocateConfigurationData (StdHeader, &Pcie) == AGESA_SUCCESS) {
- AmlObjName = '20DA';
- AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
- ASSERT (AmlObjPtr != NULL);
- if (AmlObjPtr != NULL) {
- *(UINT8*)((UINT8*)AmlObjPtr + 5) = Pcie->PsppPolicy;
- } else {
- Status = AGESA_ERROR;
- }
- AmlObjName = '60DA';
- AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
- ASSERT (AmlObjPtr != NULL);
- if (AmlObjPtr != NULL) {
- PcieConfigRunProcForAllEngines (
- DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
- PcieAlibSetPortGenCapabilityCallback,
- (UINT8*)((UINT8*)AmlObjPtr + 7),
- Pcie
- );
- } else {
- Status = AGESA_ERROR;
- }
- AmlObjName = '70DA';
- AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
- ASSERT (AmlObjPtr != NULL);
- if (AmlObjPtr != NULL) {
- PcieConfigRunProcForAllEngines (
- DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
- PcieAlibSetPortInfoCallback,
- (UINT8*)((UINT8*)AmlObjPtr + 4),
- Pcie
- );
- } else {
- Status = AGESA_ERROR;
- }
- } else {
- ASSERT (FALSE);
- Status = AGESA_ERROR;
- }
- if (Status == AGESA_ERROR) {
- //Shrink table length to size of the header
- ((ACPI_TABLE_HEADER*) AlibSsdtBuffer)->TableLength = sizeof (ACPI_TABLE_HEADER);
- }
- ChecksumAcpiTable ((ACPI_TABLE_HEADER*) AlibSsdtBuffer, StdHeader);
- return Status;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Callback to init max port Gen capability
- *
- *
- *
- *
- * @param[in] Engine Pointer to engine config descriptor
- * @param[in, out] Buffer Not used
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-
-VOID
-STATIC
-PcieAlibSetPortGenCapabilityCallback (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN OUT VOID *Buffer,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT8 *PsppMaxPortCapbilityArray;
- PsppMaxPortCapbilityArray = (UINT8*) Buffer;
- if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
- PsppMaxPortCapbilityArray[(Engine->Type.Port.Address.Address.Device - 2) * 2 + 1] = (UINT8) PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_MAX, Engine, Pcie) + 1;
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Callback to init port info
- *
- *
- *
- *
- * @param[in] Engine Pointer to engine config descriptor
- * @param[in, out] Buffer Not used
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-
-VOID
-STATIC
-PcieAlibSetPortInfoCallback (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN OUT VOID *Buffer,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- ALIB_PORT_INFO_PACKAGE *PortInfoPackage;
- UINT8 PortIndex;
- PortInfoPackage = (ALIB_PORT_INFO_PACKAGE*) Buffer;
- PortIndex = (UINT8) Engine->Type.Port.Address.Address.Device - 2;
- PortInfoPackage->PortInfo[PortIndex].StartPhyLane = (UINT8) Engine->EngineData.StartLane;
- PortInfoPackage->PortInfo[PortIndex].EndPhyLane = (UINT8) Engine->EngineData.EndLane;
- PortInfoPackage->PortInfo[PortIndex].StartCoreLane = (UINT8) Engine->Type.Port.StartCoreLane;
- PortInfoPackage->PortInfo[PortIndex].EndCoreLane = (UINT8) Engine->Type.Port.EndCoreLane;
- PortInfoPackage->PortInfo[PortIndex].PortId = Engine->Type.Port.PortId;
- PortInfoPackage->PortInfo[PortIndex].WrapperId = 0x0130 | (PcieEngineGetParentWrapper (Engine)->WrapId);
- PortInfoPackage->PortInfo[PortIndex].LinkHotplug = Engine->Type.Port.PortData.LinkHotplug;
- PortInfoPackage->PortInfo[PortIndex].MaxSpeedCap = (UINT8) PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_MAX, Engine, Pcie);
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.h b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.h
deleted file mode 100644
index ae7e774..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe ALIB
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _PCIEALIB_H_
-#define _PCIEALIB_H_
-
-#pragma pack (push, 1)
-///Port info asl buffer
-typedef struct {
- UINT8 BufferOp; ///< Opcode
- UINT8 PkgLength; ///< Package length
- UINT8 BufferSize; ///< Buffer size
- UINT8 ByteList; ///< Byte lisy
- UINT8 StartPhyLane; ///< Port Start PHY lane
- UINT8 EndPhyLane; ///< Port End PHY lane
- UINT8 StartCoreLane; ///< Port Start Core lane
- UINT8 EndCoreLane; ///< Port End Core lane
- UINT8 PortId; ///< Port ID
- UINT16 WrapperId; ///< Wrapper ID
- UINT8 LinkHotplug; ///< Link hotplug type
- UINT8 MaxSpeedCap; ///< Max port speed capability
- UINT8 Reserved[1]; ///< Reserved
-} ALIB_PORT_INFO_BUFFER;
-///Ports info asl package
-typedef struct {
- UINT8 PackageOp; ///< Opcode
- UINT8 PkgLength; ///< Package length
- UINT8 NumElements; ///< number of elements
- UINT8 PackageElementList; ///< package element list
- ALIB_PORT_INFO_BUFFER PortInfo[7]; ///< Array of port info buffers
-} ALIB_PORT_INFO_PACKAGE;
-
-#pragma pack (pop)
-
-AGESA_STATUS
-PcieAlibFeature (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl
deleted file mode 100644
index e595c28..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl
+++ /dev/null
@@ -1,68 +0,0 @@
-/**
- * @file
- *
- * ALIB PSPP config
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 25430 $ @e \$Date: 2010-01-18 22:25:55 -0800 (Mon, 18 Jan 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _PCIEALIBCONFIG_H_
-#define _PCIEALIBCONFIG_H_
-
-#define DEF_OFFSET_START_CORE_LANE 2
-#define DEF_OFFSET_END_CORE_LANE 3
-#define DEF_OFFSET_START_PHY_LANE 0
-#define DEF_OFFSET_END_PHY_LANE 1
-#define DEF_OFFSET_PORT_ID 4
-#define DEF_OFFSET_WRAPPER_ID 5
-#define DEF_OFFSET_LINK_HOTPLUG 7
-#define DEF_OFFSET_GEN2_CAP 8
-#define DEF_BASIC_HOTPLUG 1
-
-#define DEF_PSPP_POLICY_START 1
-#define DEF_PSPP_POLICY_STOP 0
-#define DEF_PSPP_POLICY_PERFORMANCE 1
-#define DEF_PSPP_POLICY_BALANCEHIGH 2
-#define DEF_PSPP_POLICY_BALANCELOW 3
-#define DEF_PSPP_POLICY_POWERSAVING 4
-#define DEF_PSPP_STATE_AC 0
-#define DEF_PSPP_STATE_DC 1
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl
deleted file mode 100644
index 7b785a8..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl
+++ /dev/null
@@ -1,373 +0,0 @@
-/**
- * @file
- *
- * ALIB ASL library
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 31805 $ @e \$Date: 2010-05-21 17:58:16 -0700 (Fri, 21 May 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * PCIe MMIO Base address
- *
- */
-
- Name (
- AD01,
- 0xE0000000
- )
-
- Alias (
- AD01,
- varPcieBase
- )
-
-
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * PCIe port info
- *
- */
-
- Name (
- AD07,
- Package () {
- Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev2
- Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev3
- Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev4
- Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev5
- Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev6
- Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev7
- Buffer () {0,0,0,0,0,0,0,0,0,0}, //dev8
- }
- )
-
- Alias (
- AD07,
- varPortInfo
- )
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * Master control method
- *
- * Arg0 - Function ID
- * Arg1 - Function specific data buffer
- */
- Method (ALIB, 2, NotSerialized) {
- If (Lequal (Arg0, 0x1)) {
- return (procPsppReportAcDsState (Arg1))
- }
- If (LEqual (Arg0, 0x2)) {
- return (procPsppPerformanceRequest (Arg1))
- }
- If (LEqual (Arg0, 0x3)) {
- return (procPsppControl (Arg1))
- }
- If (LEqual (Arg0, 0x4)) {
- return (procPcieSetBusWidth (Arg1))
- }
- If (LEqual (Arg0, 0x5)) {
- return (procAlibInit ())
- }
- If (LEqual (Arg0, 0x6)) {
- return (procPciePortHotplug (Arg1))
- }
- return (0)
- }
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * Alib Init
- *
- *
- */
- Method (procAlibInit, 0, Serialized) {
-
- return (0)
- }
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * Read PCI config register
- *
- * Arg0 - Port Index
- *
- */
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * Read PCI config register through MMIO
- *
- * Arg0 - PCI address Bus/device/func
- * Arg1 - Register offset
- */
- Method (procPciDwordRead, 2, NotSerialized) {
- Add (varPcieBase, ShiftLeft (Arg0, 12), Local0)
- Add (Arg1, Local0, Local0)
- OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4)
- Field(varOperationRegionMmio, DWordAcc, NoLock, Preserve) {
- Offset (0x0),
- varPciReg32, 32,
- }
- return (varPciReg32)
- }
- /*----------------------------------------------------------------------------------------*/
- /**
- * Write PCI config register through MMIO
- *
- * Arg0 - PCI address Bus/device/func
- * Arg1 - Register offset
- * Arg2 - Value
- */
- Method (procPciDwordWrite, 3, NotSerialized) {
- Add (varPcieBase, ShiftLeft (Arg0, 12), Local0)
- Add (Arg1, Local0, Local0)
- OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4)
- Field(varOperationRegionMmio, DWordAcc, NoLock, Preserve) {
- Offset (0x0),
- varPciReg32, 32,
- }
- Store (Arg2, varPciReg32)
- }
- /*----------------------------------------------------------------------------------------*/
- /**
- * Write PCI config register through MMIO
- *
- * Arg0 - PCI address Bus/device/func
- * Arg1 - Register offset
- * Arg2 - AND mask
- * Arg3 - OR mask
- */
- Method (procPciDwordRMW, 4, NotSerialized) {
- Store (procPciDwordRead (Arg0, Arg1), Local0)
- Or (And (Local0, Arg2), Arg3, Local0)
- procPciDwordWrite (Arg0, Arg1, Local0)
- }
-
- Mutex(varPciePortAccessMutex, 0)
- /*----------------------------------------------------------------------------------------*/
- /**
- * Read PCIe port indirect register
- *
- * Arg0 - Port Index
- * Arg1 - Register offset
- *
- */
- Method (procPciePortIndirectRegisterRead, 2, NotSerialized) {
- Acquire(varPciePortAccessMutex, 0xFFFF)
- Store (ShiftLeft (Add( Arg0, 2), 3), Local0)
- procPciDwordWrite (Local0, 0xe0, Arg1)
- Store (procPciDwordRead (Local0, 0xe4), Local0)
- Release (varPciePortAccessMutex)
- return (Local0)
- }
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * Write PCIe port indirect register
- *
- * Arg0 - Port Index
- * Arg1 - Register offset
- * Arg2 - Value
- */
- Method (procPciePortIndirectRegisterWrite, 3, NotSerialized) {
- Acquire(varPciePortAccessMutex, 0xFFFF)
- Store (ShiftLeft (Add( Arg0, 2), 3), Local0)
- procPciDwordWrite (Local0, 0xe0, Arg1)
- procPciDwordWrite (Local0, 0xe4, Arg2)
- Release (varPciePortAccessMutex)
- }
- /*----------------------------------------------------------------------------------------*/
- /**
- * Read PCIe port indirect register
- *
- * Arg0 - Port Index
- * Arg1 - Register offset
- * Arg2 - AND Mask
- * Arg3 - OR Mask
- *
- */
- Method (procPciePortIndirectRegisterRMW, 4, NotSerialized) {
- Store (procPciePortIndirectRegisterRead (Arg0, Arg1), Local0)
- Or (And (Local0, Arg2), Arg3, Local0)
- procPciePortIndirectRegisterWrite (Arg0, Arg1, Local0)
- }
- Mutex(varHostAccessMutex, 0)
- /*----------------------------------------------------------------------------------------*/
- /**
- * Read PCIe port indirect register
- *
- * Arg0 - BDF
- * Arg1 - Register offset
- * Arg2 - Register address
- *
- */
- Method (procIndirectRegisterRead, 3, NotSerialized) {
- Acquire(varHostAccessMutex, 0xFFFF)
- procPciDwordWrite (Arg0, Arg1, Arg2)
- Store (procPciDwordRead (Arg0, Add (Arg1, 4)), Local0)
- Release(varHostAccessMutex)
- return (Local0)
- }
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * Write PCIe port indirect register
- *
- * Arg0 - BDF
- * Arg1 - Register offset
- * Arg2 - Register address
- * Arg3 - Value
- */
- Method (procIndirectRegisterWrite, 4, NotSerialized) {
- Acquire(varHostAccessMutex, 0xFFFF)
- procPciDwordWrite (Arg0, Arg1, Arg2)
- procPciDwordWrite (Arg0, Add (Arg1, 4), Arg3)
- Release(varHostAccessMutex)
- }
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * Read Modify Write indirect registers
- *
- * Arg0 - BDF
- * Arg1 - Register Offset
- * Arg2 - Register Address
- * Arg3 - AND Mask
- * Arg4 - OR Mask
- *
- */
- Method (procIndirectRegisterRMW, 5, NotSerialized) {
- Store (procIndirectRegisterRead (Arg0, Arg1, Arg2), Local0)
- Or (And (Local0, Arg3), Arg4, Local0)
- procIndirectRegisterWrite (Arg0, Arg1, Arg2, Local0)
- }
-
- /*----------------------------------------------------------------------------------------*/
- /**
- *
- *
- * Arg0 - Port ID
- * Retval - buffer that represent port data set
- */
- Method (procPcieGetPortInfo, 1, NotSerialized) {
- return (DeRefOf (Index (varPortInfo, Arg0)))
- }
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * Find Pci Capability
- *
- * Arg0 - PCI address Bus/device/func
- * Arg1 - Capability id
- */
- Method (procFindPciCapability, 2, NotSerialized) {
- Store (0x34, Local1)
- if (LEqual (procPciDwordRead (Arg0, 0x0), 0xFFFFFFFF)) {
- // Device not present
- return (0)
- }
- Store (1, Local0)
- while (LEqual (Local0, 1)) {
- Store (And (procPciDwordRead (Arg0, Local1), 0xFF), Local1)
- if (LNotEqual (Local1, 0)) {
- if (LEqual (And (procPciDwordRead (Arg0, Local1), 0xFF), Arg1)) {
- Store (0, Local0)
- } else {
- Increment (Local1)
- }
- }
- }
- return (Local1)
- }
-
- /*----------------------------------------------------------------------------------------*/
- /**
- *
- *
- * Arg0 - Aspm
- * Arg1 - 0: Read, 1: Write
- */
- Method (procPcieSbAspmControl, 2, NotSerialized) {
- // Create an opregion for PM IO Registers
- OperationRegion (PMIO, SystemIO, 0xCD6, 0x2)
- Field (PMIO, ByteAcc, NoLock, Preserve)
- {
- PMRI, 8,
- PMRD, 8
- }
- IndexField (PMRI, PMRD, ByteAcc, NoLock, Preserve)
- {
- Offset(0xE0), // IO Base address of A-Link Express/ A-Link Bridge register
- ABAR, 32,
- }
- OperationRegion (ACFG, SystemIO, ABAR, 0x8)
- Field (ACFG, DWordAcc, Nolock, Preserve) //AB_INDX/AB_DATA
- {
- ABIX, 32,
- ABDA, 32
- }
-
- Store (0, Local0)
- if (LEqual (Arg1, 0)) {
- Store (0x80000068, ABIX)
- Store (ABDA, Local0)
- return (Local0)
- } else {
- Store (0x80000068, ABIX)
- Store (ABDA, Local0)
- Or (And (Local0, 0xfffffffc), Arg0, Local0)
- Store (Local0, ABDA)
- }
-
- }
-
-#ifdef ALIB_DEBUG
- Name (ABUF, Buffer (256) {})
- Name (AFUN, 0xff)
- Method (ADBG, 0, Serialized) {
- ALIB (AFUN, ABUF);
- }
- Alias (procPciDwordRead, AXPR)
-#endif
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl
deleted file mode 100644
index fead211..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl
+++ /dev/null
@@ -1,328 +0,0 @@
-/**
- * @file
- *
- * ALIB ASL library
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 31805 $ @e \$Date: 2010-05-21 17:58:16 -0700 (Fri, 21 May 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * Set PCIe Bus Width
- *
- * Arg0 - Data Buffer
- */
- Method (procPcieSetBusWidth, 1, Serialized) {
- Store (Buffer (256) {}, Local7)
- CreateWordField (Local7, 0x0, varReturnBufferLength)
- CreateWordField (Local7, 0x2, varReturnBusWidth)
- CreateByteField (Arg0, 0x2, varArgBusWidth)
- //@todo deternime correct lane bitmap (check for reversal) gate/ungate unused lanes
- Store (3, varReturnBufferLength)
- Store (varArgBusWidth, varReturnBusWidth)
- return (Local7)
- }
-
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * PCIe port hotplug
- *
- * Arg0 - Data Buffer
- * Local7 - Return buffer
- */
- Method (procPciePortHotplug, 1, Serialized) {
- Store ("PciePortHotplug Enter", Debug)
- Store (Buffer (256) {}, Local7)
- CreateWordField (Local7, 0x0, varReturnBufferLength)
- CreateByteField (Local7, 0x2, varReturnStatus)
- CreateByteField (Local7, 0x3, varReturnDeviceStatus)
- CreateWordField (Arg0, 0x2, varPortBdf)
- CreateByteField (Arg0, 0x4, varHotplugState)
- Subtract (ShiftRight (varPortBdf, 3), 2, Local1);
- if (LEqual(varHotplugState, 1)) {
- // Enable port
- Store (procPciePortEnable (Local1), varHotplugState);
- } else {
- // Disable port
- Store (procPciePortDisable (Local1), varHotplugState);
- }
- Store (0x4, varReturnBufferLength)
- Store (0x0, varReturnStatus)
- Store (varHotplugState, varReturnDeviceStatus)
- Store ("PciePortHotplug Exit", Debug)
- return (Local7)
- }
-
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * Enable PCIe port
- *
- * 1) Ungate lanes
- * 2) Enable Lanes
- * 3) Train port
- * 4) Disable unused lanes
- * 5) Gate unused lanes
- *
- * Arg0 - Port Index
- *
- */
- Method (procPciePortEnable, 1, NotSerialized) {
- Store ("PciePortEnable Enter", Debug)
- Name (varLinkIsLinkReversed, 0)
- Store (procPcieGetPortInfo (Arg0), Local7)
- CreateByteField (Local7, DEF_OFFSET_LINK_HOTPLUG, varHotplugType)
- if (LNotEqual (varHotplugType, DEF_BASIC_HOTPLUG)) {
- Store (" No action.[Hotplug type]", Debug)
- Store ("PciePortEnable Exit", Debug)
- return (1)
- }
- // Poweron phy lanes
- CreateByteField (Local7, DEF_OFFSET_START_PHY_LANE, varStartPhyLane)
- CreateByteField (Local7, DEF_OFFSET_END_PHY_LANE, varEndPhyLane)
- procPcieLanePowerControl (varStartPhyLane, varEndPhyLane, 0)
- // Enable lanes
- CreateByteField (Local7, DEF_OFFSET_START_CORE_LANE, varStartCoreLane)
- CreateByteField (Local7, DEF_OFFSET_END_CORE_LANE, varEndCoreLane)
- procPcieLaneEnableControl (Arg0, varStartPhyLane, varEndPhyLane, 0)
- //Release training
- procPcieTrainingControl (Arg0, 0)
- //Train link
- Store (procPcieCheckDevicePrecence (Arg0), Local1)
- if (LEqual (Local1, 1)) {
- Store (" Device detected", Debug)
- Store (procPcieIsPortReversed (Arg0), varLinkIsLinkReversed)
- Subtract (procPcieGetLinkWidth (Arg0, 1), procPcieGetLinkWidth (Arg0, 0), Local2)
- if (LNotEqual (Local2, 0)) {
- //There is unused lanes after device plugged
- if (LNotEqual(varLinkIsLinkReversed, 0)) {
- Add (varStartCoreLane, Local2, Local3)
- Store (varEndCoreLane, Local4)
- } else {
- Subtract (varEndCoreLane, Local2, Local4)
- Store (varStartCoreLane, Local3)
- }
- procPcieLaneEnableControl (Arg0, Local3, Local4, 1)
- if (LGreater (varStartPhyLane, varEndPhyLane)) {
- Store (varEndPhyLane, Local3)
- Store (varStartPhyLane, Local4)
- } else {
- Store (varEndPhyLane, Local4)
- Store (varStartPhyLane, Local3)
- }
- if (LNotEqual(varLinkIsLinkReversed, 0)) {
- Add (Local3, Local2, Local3)
- } else {
- Subtract (Local4, Local2, Local4)
- }
- procPcieLanePowerControl (Local3, Local4, 1)
- }
- Store ("PciePortEnable Exit", Debug)
- return (1)
- }
- Store (" Device detection fail", Debug)
- procPciePortDisable (Arg0)
- Store ("PciePortEnable Exit", Debug)
- return (0)
- }
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * Disable PCIe port
- *
- * 1) Hold training
- * 2) Disable lanes
- * 3) Gate lanes
- *
- * Arg0 - Port Index
- *
- */
- Method (procPciePortDisable, 1, NotSerialized) {
- Store ("PciePortDisable Enter", Debug)
- Store (procPcieGetPortInfo (Arg0), Local7)
- CreateByteField (Local7, DEF_OFFSET_LINK_HOTPLUG, varHotplugType)
- if (LNotEqual (varHotplugType, DEF_BASIC_HOTPLUG)) {
- Store (" No action. [Hotplug type]", Debug)
- Store ("PciePortDisable Exit", Debug)
- return (0)
- }
- //Hold training
- procPcieTrainingControl (Arg0, 1)
- CreateByteField (Local7, DEF_OFFSET_START_CORE_LANE, varStartCoreLane)
- CreateByteField (Local7, DEF_OFFSET_END_CORE_LANE, varEndCoreLane)
- // Disable lane
- procPcieLaneEnableControl (Arg0, varStartCoreLane, varEndCoreLane, 1)
- CreateByteField (Local7, DEF_OFFSET_START_PHY_LANE, varStartPhyLane)
- CreateByteField (Local7, DEF_OFFSET_END_PHY_LANE, varEndPhyLane)
- // Poweroff phy lanes
- procPcieLanePowerControl (varStartPhyLane, varEndPhyLane, 1)
-
- Store ("PciePortDisable Exit", Debug)
- return (0)
- }
- /*----------------------------------------------------------------------------------------*/
- /**
- * Is port reversed
- *
- * Arg0 - Port Index
- * Retval - 0 - Not reversed / 1 - Reversed
- */
- Method (procPcieIsPortReversed , 1, NotSerialized) {
- Store (procPcieGetPortInfo (Arg0), Local7)
- CreateByteField (Local7, DEF_OFFSET_START_PHY_LANE, varStartPhyLane)
- CreateByteField (Local7, DEF_OFFSET_END_PHY_LANE, varEndPhyLane)
- Store (0, Local0)
- if (LGreater (varStartPhyLane, varEndPhyLane)) {
- Store (1, Local0)
- }
- And (procPciePortIndirectRegisterRead (Arg0, 0x50), 0x1, Local1)
- return (Xor (Local0, Local1))
- }
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * Training Control
- *
- * Arg0 - Port Index
- * Arg1 - Hold Training (1) / Release Training (0)
- */
- Method (procPcieTrainingControl , 2, NotSerialized) {
- Store ("PcieTrainingControl Enter", Debug)
- Store (procPcieGetPortInfo (Arg0), Local7)
- CreateByteField (Local7, DEF_OFFSET_PORT_ID, varPortId)
- CreateWordField (Local7, DEF_OFFSET_WRAPPER_ID, varWrapperId)
- procIndirectRegisterRMW (0x0, 0xE0, Or (ShiftLeft (varWrapperId, 16), Add (0x800, Multiply (0x100, varPortId))), Not (0x1), Arg1);
- Store ("PcieTrainingControl Exit", Debug)
- }
-
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * Check device presence
- *
- * Arg0 - Port Index
- * Retval - 1 - Device present, 0 - Device not present
- */
- Method (procPcieCheckDevicePrecence, 1, NotSerialized) {
- Store ("PcieCheckDevicePrecence Enter", Debug)
- Store (0, Local0)
- Store (0, Local7)
- while (LLess (Local0, 320)) { // @todo for debug only should be 80
- And (procPciePortIndirectRegisterRead (Arg0, 0xa5), 0x3f, Local1)
- if (LEqual (Local1, 0x10)) {
- Store (1, Local7)
- Store (320, Local0)
- Break
- }
- Stall (250)
- Increment (Local0)
- }
- //Store (Concatenate ("Device Presence Status :", ToHexString (Local7)), Debug)
- Store ("PcieCheckDevicePrecence Exit", Debug)
- return (Local7)
- }
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * Get actual negotiated/PHY or core link width
- *
- * Arg0 - Port Index
- * Arg1 - 0/1 Negotiated/Phy
- * Retval - Link Width
- */
- Method (procPcieGetLinkWidth, 2, NotSerialized) {
- if (LEqual (Arg0, 0)){
- //Get negotiated length
- And (ShiftRight (procPciePortIndirectRegisterRead (Arg0, 0xA2), 4), 0x7, Local0)
- Store (DeRefOf (Index (Buffer (){0, 1, 2, 4, 8, 12, 16}, Local0)), Local1)
- } else {
- //Get phy length
- Store (procPcieGetPortInfo (Arg0), Local7)
- CreateByteField (Local7, DEF_OFFSET_START_PHY_LANE, varStartPhyLane)
- CreateByteField (Local7, DEF_OFFSET_END_PHY_LANE, varEndPhyLane)
- if (LGreater (varStartPhyLane, varEndPhyLane)) {
- Subtract (varStartPhyLane, varEndPhyLane, Local1)
- } else {
- Subtract (varEndPhyLane, varStartPhyLane, Local1)
- }
- Increment (Local1)
- }
- //Store (Concatenate ("Link Width :", ToHexString (Local7)), Debug)
- return (Local1)
- }
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * PCIe lane mux lane enable control (hotplug support)
- *
- * Arg0 - Port Index
- * Arg1 - Start Lane
- * Arg2 - End Lane
- * Arg3 - Enable(0) / Disable(1)
- */
- Method (procPcieLaneEnableControl, 4, NotSerialized) {
- Store ("PcieLaneEnableControl Enter", Debug)
- Name (varStartCoreLane, 0)
- Name (varEndCoreLane, 0)
- Store (procPcieGetPortInfo (Arg0), Local7)
- Store (Arg1, varStartCoreLane)
- Store (Arg2, varEndCoreLane)
- CreateWordField (Local7, DEF_OFFSET_WRAPPER_ID, varWrapperId)
- if (LGreater (varStartCoreLane, varEndCoreLane)) {
- Subtract (varStartCoreLane, varEndCoreLane, Local1)
- Store (varEndCoreLane, Local2)
- } else {
- Subtract (varEndCoreLane, varStartCoreLane, Local1)
- Store (varStartCoreLane, Local2)
- }
- ShiftLeft (Subtract (ShiftLeft (1, Add (Local1, 1)), 1), Local2, Local1)
- //Store (Concatenate ("Lane Bitmap :", ToHexString (Local1)), Debug)
- if (Lequal (Arg3, 0)) {
- procIndirectRegisterRMW (0x0, 0xE0, Or (ShiftLeft (varWrapperId, 16), 0x8023), 0xffffffff, Local1);
- } else {
- procIndirectRegisterRMW (0x0, 0xE0, Or (ShiftLeft (varWrapperId, 16), 0x8023), Not (Local1), 0x0);
- }
- Stall (10)
- Store ("PcieLaneEnableControl Exit", Debug)
- }
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl
deleted file mode 100644
index 70d6a93..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl
+++ /dev/null
@@ -1,682 +0,0 @@
-/**
-* @file
-*
-* ALIB PSPP ASL library
-*
-*
-*
-* @xrefitem bom "File Content Label" "Release Content"
-* @e project: AGESA
-* @e sub-project: GNB
-* @e \$Revision: 31805 $ @e \$Date: 2010-05-21 17:58:16 -0700 (Fri, 21 May 2010) $
-*
-*/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * PCIe Performance Policy
- *
- * varPsppPolicy - 0 Disabled
- * 1 Performance
- * 2 Balance Hight
- * 3 Balance Low
- * 4 Power Saving
- */
- Name (
- AD02,
- 0x0
- )
-
- Alias (
- AD02,
- varPsppPolicy
- )
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * GEN2 VID
- *
- */
-
- Name (
- AD03,
- 0x0
- )
-
- Alias (
- AD03,
- varGen2Vid
- )
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * GEN1 VID
- *
- */
- Name (
- AD04,
- 0x0
- )
-
- Alias (
- AD04,
- varGen1Vid
- )
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * Boot VID
- *
- */
-
- Name (
- AD05,
- 0x0
- )
-
- Alias (
- AD05,
- varBootVid
- )
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * Max Port GEN capability
- *
- */
- Name (
- AD06,
- Package () {
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00
- }
- )
-
- Alias (
- AD06,
- varPsppMaxPortCapabilityArray
- )
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * Policy service status
- *
- * varPsppPolicyService - 0 (Stopped)
- * 1 (Started)
- */
-
- Name (
- varPsppPolicyService,
- 0x0
- )
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * AC DC state
- *
- * varPsppAcDcState - 0 (AC)
- * 1 (DC)
- */
-
- Name (
- varPsppAcDcState,
- 0x0
- )
-
-
- Name (
- varPsppClientIdArray,
- Package () {
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000,
- 0x0000
- }
- )
-
- Name (
- varPsppClientCapabilityArray,
- Package () {
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00
- }
- )
-
- Name (
- varPsppCurrentCapabilityArray,
- Package () {
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00
- }
- )
- Name (
- varDefaultGen1CapabilityArray,
- Package () {
- 0x2,
- 0x2,
- 0x2,
- 0x2,
- 0x2,
- 0x2,
- 0x2
- }
- )
-
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * Report AC/DC state
- *
- * Arg0 - Data Buffer
- */
- Method (procPsppReportAcDsState, 1, Serialized) {
- Store ("PsppReportAcDsState Enter", Debug)
- CreateByteField (Arg0, 0x2, varArgAcDcState)
-
- Store ("AC/DC state = ", Debug)
- Store (varArgAcDcState, Debug)
- if (LEqual (varArgAcDcState, varPsppAcDcState)) {
- Store (" No action. [AC/DC state not changed]", Debug)
- Store ("PsppReportAcDsState Exit", Debug)
- return (0)
- }
- Store (varArgAcDcState, varPsppAcDcState)
- // Set DPM state for Power Saving, due to this policy will not attend ApplyPsppState service.
- if (LEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING)) {
- procNbLclkDpmActivate(1, varPsppAcDcState)
- }
- if (LOr (LLessEqual (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LGreaterEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) {
- Store (" No action. [Policy type]", Debug)
- Store ("PsppReportAcDsState Exit", Debug)
- return (0)
- }
- if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_STOP)) {
- Store (" No action. [Policy not started]", Debug)
- Store ("PsppReportAcDsState Exit", Debug)
- return (0)
- }
- procApplyPsppState ()
- Store ("PsppReportAcDsState Exit", Debug)
- return (0)
- }
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * PCIe Performance Request
- *
- * Arg0 - Data Buffer
- */
- Method (procPsppPerformanceRequest, 1) {
- Store ("PsppPerformanceRequest Enter", Debug)
- Name (varClientBus, 0)
- Name (varPortIndex, 0)
- Store (Buffer (256) {}, Local7)
- CreateWordField (Local7, 0x0, varReturnBufferLength)
- Store (3, varReturnBufferLength)
- CreateByteField (Local7, 0x2, varReturnStatus)
- Store (1, varReturnStatus)
- if (LOr (LLessEqual (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LGreaterEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) {
- Store (" No action. [Policy type]", Debug)
- Store ("PsppPerformanceRequest Exit", Debug)
- return (Local7)
- }
- if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_STOP)) {
- Store (" No action. [Policy not started]", Debug)
- Store ("PsppPerformanceRequest Exit", Debug)
- return (Local7)
- }
- CreateWordField (Arg0, 0x2, varClientId)
- CreateWordField (Arg0, 0x4, varValidFlag)
- CreateWordField (Arg0, 0x6, varFlag)
- CreateByteField (Arg0, 0x8, varRequestType)
- CreateByteField (Arg0, 0x9, varRequestData)
-
- Store (" Client ID:", Debug)
- Store (varClientId, Debug)
- Store (" Valid Flags:", Debug)
- Store (varValidFlag, Debug)
- Store (" Flags:", Debug)
- Store (varFlag, Debug)
- Store (" Request Type:", Debug)
- Store (varRequestType, Debug)
- Store (" Request Data:", Debug)
- Store (varRequestData, Debug)
-
- And (ShiftRight (varClientId, 8), 0xff, varClientBus)
- While (LLessEqual (varPortIndex, varMaxPortIndexNumber)) {
- if (LEqual (DeRefOf (Index (varPsppMaxPortCapabilityArray, varPortIndex)), 0)) {
- Increment (varPortIndex)
- Continue
- }
- Store (procPciDwordRead (ShiftLeft (Add( varPortIndex, 2), 3), 0x18), Local1)
- And (ShiftRight (Local1, 16), 0xff, Local2) //Local2 Port Subordinate Bus number
- And (ShiftRight (Local1, 8), 0xff, Local1) //Local1 Port Secondary Bus number
- if (LAnd (LLess (varClientBus, Local1), LGreater (varClientBus, Local2))) {
- Increment (varPortIndex)
- Continue
- }
- Store ("Performance request for port index", Debug)
- Store (varPortIndex, Debug)
-
- if (LEqual (DeRefOf (Index (varPsppClientIdArray, varPortIndex)), 0x0000)) {
- Store (varClientId, Index (varPsppClientIdArray, varPortIndex))
- } ElseIf (LNotEqual (DeRefOf (Index (varPsppClientIdArray, varPortIndex)), varClientId)) {
- // We already have registered client
- Store (" No action. [Unsupported request]", Debug)
- Store ("PsppPerformanceRequest Exit", Debug)
- return (Local7)
- }
- if (LEqual (varRequestData, 0)) {
- Store (0x0000, Index (varPsppClientIdArray, varPortIndex))
- } else {
- if (LEqual (And (varValidFlag, varFlag), 0x1)) {
- Store (DerefOf (Index (varPsppMaxPortCapabilityArray, varPortIndex)), Index (varPsppClientCapabilityArray, varPortIndex))
- } else {
- Store (varRequestData, Index (varPsppClientCapabilityArray, varPortIndex))
- }
- }
- procApplyPsppState ()
- Store (2, varReturnStatus)
- Store ("PsppPerformanceRequest Exit", Debug)
- return (Local7)
- }
- Store ("PsppPerformanceRequest Exit", Debug)
- return (Local7)
- }
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * PSPP Start/Stop Management Request
- *
- * Arg0 - Data Buffer
- */
- Method (procPsppControl, 1, Serialized) {
- Store ("PsppControl Enter", Debug)
- Store (Buffer (256) {}, Local7)
- CreateWordField (Local7, 0x0, varReturnBufferLength)
- Store (3, varReturnBufferLength)
- CreateByteField (Local7, 0x2, varReturnStatus)
- CreateByteField (Arg0, 0x2, varArgPsppRequest)
- Store (varArgPsppRequest, varPsppPolicyService)
- // Set DPM state for PSPP Power Saving, due to this policy will not attend ApplyPsppState service.
- if (LEqual (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING)) {
- procNbLclkDpmActivate(1, varPsppAcDcState)
- }
- //Reevaluate PCIe speed for all devices base on PSPP state switch to boot up voltage
- if (LAnd (LGreater (varPsppPolicy, DEF_PSPP_POLICY_PERFORMANCE), LLess (varPsppPolicy, DEF_PSPP_POLICY_POWERSAVING))) {
- // Load default speed capability state
- if (LEqual (varPsppPolicy, DEF_PSPP_POLICY_BALANCEHIGH)) {
- procCopyPackage (RefOf (varPsppMaxPortCapabilityArray), RefOf (varPsppCurrentCapabilityArray))
- } else {
- procCopyPackage (RefOf (varDefaultGen1CapabilityArray), RefOf (varPsppCurrentCapabilityArray))
- }
- // Unregister all clients
- if (LEqual (varPsppPolicyService, DEF_PSPP_POLICY_STOP)) {
- Name (varDefaultPsppClientIdArray, Package () {0x0, 0x0, 0x0, 0x0, 0x0, 0x0})
- procCopyPackage (RefOf (varDefaultPsppClientIdArray), RefOf (varPsppClientIdArray))
- }
- procApplyPsppState ()
- }
- Store (3, varReturnBufferLength)
- Store (0, varReturnStatus)
- Store ("PsppControl Exit", Debug)
- return (Local7)
- }
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * Evaluate PCIe speed on all links according to PSPP state and client requests
- *
- *
- *
- */
- Method (procApplyPsppState, 0, Serialized) {
- Store ("ApplyPsppState Enter", Debug)
- Name (varPortIndex, 0)
- Name (varLowPowerMode, 0)
- Name (varPcieCapabilityArray, Package () {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02})
-
- Store (0, varPortIndex)
- While (LLessEqual (varPortIndex, varMaxPortIndexNumber)) {
- if (LNotEqual (DeRefOf (Index (varPsppMaxPortCapabilityArray, varPortIndex)), 0)) {
- Store (procGetPortRequestedCapability (varPortIndex), Index (varPcieCapabilityArray, varPortIndex))
- }
- Increment (varPortIndex)
- }
- if (LNotEqual(Match (varPcieCapabilityArray, MEQ, 0x01, MTR, 0, 0), ONES)) {
- procCopyPackage (RefOf (varDefaultGen1CapabilityArray), RefOf (varPcieCapabilityArray))
- }
- if (LNotEqual(Match (varPcieCapabilityArray, MEQ, 0x03, MTR, 0, 0), ONES)) {
- // Set GEN2 voltage
- Store ("Set GEN2 VID", Debug)
- procPcieSetVoltage (varGen2Vid, 1)
- procPcieAdjustPll (2)
- procNbLclkDpmActivate(2, varPsppAcDcState)
- }
- Store (0, varPortIndex)
- While (LLessEqual (varPortIndex, varMaxPortIndexNumber)) {
- if (LEqual (DeRefOf (Index (varPsppMaxPortCapabilityArray, varPortIndex)), 0)) {
- Increment (varPortIndex)
- Continue
- }
- Store (procGetPortCurrentCapability (varPortIndex), Local0)
- Store (DerefOf (Index (varPcieCapabilityArray, varPortIndex)), Local2)
- if (LEqual (Local0, Local2)) {
- Increment (varPortIndex)
- Continue
- }
- procSetPortCapabilityAndSpeed (varPortIndex, Local2, 0)
- Increment (varPortIndex)
- }
- if (LEqual(Match (varPcieCapabilityArray, MEQ, 0x03, MTR, 0, 0), ONES)) {
- // Set GEN1 voltage
- Store ("Set GEN1 VID", Debug)
- procNbLclkDpmActivate(1, varPsppAcDcState)
- procPcieAdjustPll (1)
- procPcieSetVoltage (varGen1Vid, 0)
- }
- Store ("ApplyPsppState Exit", Debug)
- }
- /*----------------------------------------------------------------------------------------*/
- /**
- * Read PCI config register
- *
- * Arg0 - Port Index
- *
- */
- Method (procGetPortRequestedCapability, 1) {
- Store (0x3, Local0)
- if (LEqual (DerefOf (Index (varPsppClientIdArray, Arg0)), 0x0000)) {
- if (LOr (LEqual (varPsppAcDcState, DEF_PSPP_STATE_DC), LEqual (varPsppPolicy, DEF_PSPP_POLICY_BALANCELOW))) {
- // Default policy cap to GEN1
- Store (0x2, Local0)
- }
- } else {
- Store (DerefOf (Index (varPsppClientCapabilityArray, Arg0)), Local0)
- }
- return (Local0)
- }
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * Read PCI config register
- *
- * Arg0 - Port Index
- *
- */
- Method (procGetPortCurrentCapability, 1) {
- return (DerefOf (Index (varPsppCurrentCapabilityArray, Arg0)))
- }
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * Set capability and speed
- *
- * Arg0 - Port Index
- * Arg1 - Capability
- * Arg2 - Speed
- */
- Method (procSetPortCapabilityAndSpeed, 3) {
- Store ("SetPortCapabilityAndSpeed Enter", Debug)
- if (LOr (LEqual (Arg1, 0x2), LEqual (Arg1, 0x3))) {
- Store ("Port Index = ", Debug)
- Store (Arg0, Debug)
- Store ("Cap = ", Debug)
- Store (Arg1, Debug)
- Store ("Speed = ", Debug)
- Store (Arg2, Debug)
-
- Name (varDxF0xE4_xA4, 0x20000001)
- Name (varPortPresent, 0x00000000)
- Name (varDxF0x88, 0x00000002)
- Name (varAXCFGx68_PmCtrl, 0x00000000)
- Name (varLcCurrentDataRate,0x00000000)
- Name (varSecondaryBus, 0x00000000)
- Name (varHeaderType, 0x00000000)
- Name (varMultiFunction, 0x00000000)
- Name (varPcieLinkControlOffset, 0x00000000)
- Name (varPcieLinkControlData, 0x00000000)
- Name (varPcieLinkControlArray, Package () {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0})
-
-
- //If request for UMI unhihe port congig space
- if (LEqual (Arg0, 6)) {
- procIndirectRegisterRMW (0x0, 0x60, 0x80, Not (0x40), 0x40);
-
- }
- Store (Arg1, Index (varPsppCurrentCapabilityArray, Arg0))
- if (LEqual (Arg1, 0x2)) {
- //Gen1
- Store (0x00000000, varDxF0xE4_xA4)
- Store (0x21, varDxF0x88)
- }
-
- // Programming for LcInitSpdChgWithCsrEn
- if (LNotEqual (DeRefOf (Index (varPsppClientIdArray, Arg0)), 0x0000)) {
- // Registered port, LcInitSpdChgWithCsrEn = 0.
- procPciePortIndirectRegisterRMW (Arg0, 0xA1, Not (0x00001000), 0x0)
- } else {
- procPciePortIndirectRegisterRMW (Arg0, 0xA1, Not (0x00001000), 0x00001000)
- }
-
- // Initialize port
- procPciePortIndirectRegisterRMW (Arg0, 0xA4, Not (0x20000001), varDxF0xE4_xA4)
- //set target link speed
- Store (ShiftLeft (Add( Arg0, 2), 3), Local0)
- procPciDwordRMW (Local0, 0x88, Not (0x0000002f), varDxF0x88)
-
- // Determine port PCI address and check port present
- Store (ShiftLeft (Add( Arg0, 2), 3), Local0)
- And (procPciDwordRead (Local0, 0x70), 0x400000, varPortPresent)
- if (LNotEqual (varPortPresent, 0)) {
- //Disable ASPM on EP
- if (LNotEqual (Arg0, 6)) {
- Store (procPciDwordRead (Local0, 0x18), Local3)
- Store (And (ShiftRight (Local3, 8), 0xFF), varSecondaryBus)
- Store ("Disable EP ASPM on SecondaryBus = ", Debug)
- Store (varSecondaryBus, Debug)
- Store (ShiftLeft (varSecondaryBus, 8), Local3)
- Store (procPciDwordRead (Local3, 0xC), Local3)
- Store (And (ShiftRight (Local3, 16), 0xFF), varHeaderType)
- Store ("Header Type = ", Debug)
- Store (varHeaderType, Debug)
-
- if (LNotEqual (And (varHeaderType, 0x80), 0)) {
- Store (0x7, varMultiFunction)
- }
-
- Store (ShiftLeft (varSecondaryBus, 8), Local3)
- Store (0, Local2)
- while (LLessEqual (Local2, varMultiFunction)) {
-
- //Find PcieLinkControl register offset = PcieCapPtr + 0x10
- Store (procFindPciCapability (Local3, 0x10), varPcieLinkControlOffset)
- if (LNotEqual (varPcieLinkControlOffset, 0)) {
- Add (varPcieLinkControlOffset, 0x10, varPcieLinkControlOffset)
-
- Store ("Function number of SecondaryBus = ", Debug)
- Store (Local2, Debug)
- Store ("Find PcieLinkControl register offset = ", Debug)
- Store (varPcieLinkControlOffset, Debug)
- // Save ASPM on EP
- Store (procPciDwordRead (Local3, varPcieLinkControlOffset), varPcieLinkControlData)
- Store (And (varPcieLinkControlData, 0x3), Index (varPcieLinkControlArray, Local2))
- Store ("PcieLinkControlData = ", Debug)
- Store (varPcieLinkControlData, Debug)
- Store ("Save ASPM = ", Debug)
- Store (DerefOf (Index (varPcieLinkControlArray, Local2)), Debug)
- // Disable ASPM
- if (LNotEqual (And (varPcieLinkControlData, 0x3), 0x0)) {
- procPciDwordRMW (Local3, varPcieLinkControlOffset, Not (0x00000003), 0x00)
- Store ("Disable ASPM on EP Complete!!", Debug)
- }
- }
- Increment (Local2)
- Increment (Local3)
- }
-
- } else {
-
- Store (procPcieSbAspmControl (0, 0), varAXCFGx68_PmCtrl)
- And (varAXCFGx68_PmCtrl, 0x3, Local1)
- if (LNotEqual (Local1, 0x0)) {
- procPcieSbAspmControl (0, 1)
- }
- }
- Store (1, Local2)
- while (Local2) {
- //retrain port
- procPciDwordRMW (Local0, 0x68, Not (0x00000000), 0x20)
- Sleep (30)
- while (And (procPciDwordRead (Local0, 0x68), 0x08000000)) {Sleep (10)}
- Store (0, Local2)
- if (LEqual (Arg1, 0x2)) { // if Gen1
- Store (procPciePortIndirectRegisterRead (Arg0, 0xA4), varLcCurrentDataRate)
- if (LNotEqual (And (varLcCurrentDataRate, 0x800), 0)) {
- Store (1, Local2)
- }
- }
- }
- //restore ASPM setting
- if (LNotEqual (Arg0, 6)) {
- // Restore EP
- //if (LNotEqual (varPcieLinkControlOffset, 0)) {
- // procPciDwordWrite (Local3, varPcieLinkControlOffset, varPcieLinkControlData)
- //}
- Store (ShiftLeft (varSecondaryBus, 8), Local3)
- Store (0, Local2)
- while (LLessEqual (Local2, varMultiFunction)) {
-
- //Find PcieLinkControl register offset = PcieCapPtr + 0x10
- Store (procFindPciCapability (Local3, 0x10), varPcieLinkControlOffset)
- if (LNotEqual (varPcieLinkControlOffset, 0)) {
- Add (varPcieLinkControlOffset, 0x10, varPcieLinkControlOffset)
-
- Store ("Restore Function number of SecondaryBus = ", Debug)
- Store (Local2, Debug)
- Store ("Restore Find PcieLinkControl register offset = ", Debug)
- Store (varPcieLinkControlOffset, Debug)
- Store ("Restore ASPM = ", Debug)
- Store (DerefOf (Index (varPcieLinkControlArray, Local2)), Debug)
- procPciDwordWrite (Local3, varPcieLinkControlOffset, DerefOf (Index (varPcieLinkControlArray, Local2)))
- }
- Increment (Local2)
- Increment (Local3)
- }
-
- } else {
- // Restore SB
- procPcieSbAspmControl (varAXCFGx68_PmCtrl, 1)
- }
- } else {
- Store (" Device not present. Set capability and speed only", Debug)
- }
- //If request for UMI hide port congig space
- if (LEqual (Arg0, 6)) {
- procIndirectRegisterRMW (0x0, 0x60, 0x80, Not (0x40), 0x00);
- }
- }
- Store ("SetPortCapabilityAndSpeed Exit", Debug)
- }
- Mutex (varVoltageChangeMutex, 0)
- /*----------------------------------------------------------------------------------------*/
- /**
- * Request VID
- *
- * Arg0 - VID index
- * Arg1 - 0 = do not wait intil voltage is set
- * 1 = wait until voltage is set
- */
- Method (procPcieSetVoltage, 2) {
- Store ("PcieSetVoltage(procPcieSetVoltage) Enter", Debug)
- Acquire(varVoltageChangeMutex, 0xFFFF)
- Store (procIndirectRegisterRead (0x0, 0x60, 0xEA), Local1)
- //Enable voltage change
- Or (Local1, 0x2, Local1)
- procIndirectRegisterWrite (0x0, 0x60, 0xEA, Local1)
- //Clear voltage index
- And (Local1, Not (ShiftLeft (0x3, 3)), Local1)
- //Set new voltage index
- Store (" Voltage Index:", Debug)
- Store (Arg0, Debug)
- Or (Local1, ShiftLeft (Arg0, 3), Local1)
- //Togle request
- And (Not (Local1), 0x4, Local2)
- Or (And (Local1, Not (0x4)), Local2, Local1)
- procIndirectRegisterWrite (0x0, 0x60, 0xEA, Local1)
- if (LNotEqual (Arg1, 0)) {
- while (LNotEqual (ShiftLeft(Local1, 0x2), Local2)) {
- And (procIndirectRegisterRead (0x0, 0x60, 0xEB), 0x1, Local1)
- }
- }
- Release (varVoltageChangeMutex)
- Store ("PcieSetVoltage(procPcieSetVoltage) Exit", Debug)
- }
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * Read PCIe port indirect register
- *
- * Arg0 - Ref Source Pckage
- * Arg1 - Ref to Destination Package
- *
- */
- Method (procCopyPackage, 2, NotSerialized) {
-
- Store (SizeOf (Arg0), Local1)
- Store (0, Local0)
- While (LLess (Local0, Local1)) {
- Store (DerefOf(Index(DerefOf (Arg0), Local0)), Index(DerefOf (Arg1), Local0))
- Increment (Local0)
- }
- }
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieConfig/GnbPcieConfig.h b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieConfig/GnbPcieConfig.h
deleted file mode 100644
index d18c103..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieConfig/GnbPcieConfig.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe configuration
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _GNBPCIECONFIG_H_
-#define _GNBPCIECONFIG_H_
-
-
-#include "PcieConfigData.h"
-#include "PcieConfigLib.h"
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c
deleted file mode 100644
index 30ebb61..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c
+++ /dev/null
@@ -1,379 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * GNB function to create/locate PCIe configuration data area
- *
- * Contain code that create/locate and rebase configuration data area.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39898 $ @e \$Date: 2010-10-15 17:08:45 -0400 (Fri, 15 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "amdlib.h"
-#include "heapManager.h"
-#include "Gnb.h"
-#include "GnbPcie.h"
-#include "GnbPcieFamServices.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include GNB_MODULE_DEFINITIONS (GnbPcieConfig)
-#include "PcieMapTopology.h"
-#include "PcieInputParser.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGDATA_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-#define REBASE_PTR( Ptr, OldBase, NewBase) *(UINTN *)Ptr = (*(UINTN *)Ptr + (UINTN) NewBase - (UINTN) OldBase);
-
-extern BUILD_OPT_CFG UserOptions;
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-VOID
-PcieConfigDebugDump (
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Create internal PCIe configuration data
- *
- *
- *
- * @param[in] StdHeader Standard configuration header
- * @retval AGESA_SUCCESS Configuration data successfully allocated.
- * @retval AGESA_FATAL Configuration data allocation failed.
- */
-
-AGESA_STATUS
-PcieConfigurationInit (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AMD_EARLY_PARAMS *EarlyParamsPtr;
- PCIe_COMPLEX_DESCRIPTOR *ComplexList;
- PCIe_PLATFORM_CONFIG *Pcie;
- AGESA_STATUS AgesaStatus;
- AGESA_STATUS Status;
- PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor;
- UINTN ComplexesDataLength;
- UINTN ComplexIndex;
- UINTN NumberOfComplexes;
- VOID *Buffer;
- UINTN Index;
- UINT32 NumberOfSockets;
- UINT32 SocketId;
-
- IDS_HDT_CONSOLE (GNB_TRACE, "PcieConfigurationInit Enter\n");
- EarlyParamsPtr = (AMD_EARLY_PARAMS *) StdHeader;
- ComplexList = EarlyParamsPtr->GnbConfig.PcieComplexList;
- AgesaStatus = AGESA_SUCCESS;
- ComplexesDataLength = 0;
- NumberOfSockets = GnbGetNumberOfSockets (StdHeader);
- for (SocketId = 0; SocketId < NumberOfSockets; SocketId++) {
- if (GnbIsDevicePresentInSocket (SocketId, StdHeader)) {
- UINTN CurrentComplexesDataLength;
- Status = PcieFmGetComplexDataLength (SocketId, &CurrentComplexesDataLength);
- ASSERT (Status == AGESA_SUCCESS);
- ComplexesDataLength += CurrentComplexesDataLength;
- }
- }
- NumberOfComplexes = PcieInputParserGetNumberOfComplexes (ComplexList);
- Pcie = GnbAllocateHeapBuffer (AMD_PCIE_COMPLEX_DATA_HANDLE, sizeof (PCIe_PLATFORM_CONFIG) + ComplexesDataLength, StdHeader);
- if (Pcie == NULL) {
- IDS_ERROR_TRAP;
- return AGESA_FATAL;
- }
- LibAmdMemFill (Pcie, 0x00, sizeof (PCIe_PLATFORM_CONFIG) + ComplexesDataLength, StdHeader);
- Pcie->StdHeader = (PVOID) StdHeader;
- Pcie->This = (UINTN) (Pcie);
- Buffer = (UINT8 *) (Pcie) + sizeof (PCIe_PLATFORM_CONFIG);
- ComplexIndex = 0;
- for (SocketId = 0; SocketId < NumberOfSockets; SocketId++) {
- if (GnbIsDevicePresentInSocket (SocketId, StdHeader)) {
- UINTN CurrentComplexesDataLength;
- if (ComplexIndex > MAX_NUMBER_OF_COMPLEXES) {
- IDS_ERROR_TRAP;
- return AGESA_FATAL;
- }
- Pcie->ComplexList[ComplexIndex].SiliconList = (PPCIe_SILICON_CONFIG) Buffer;
- PcieFmBuildComplexConfiguration (Buffer, StdHeader);
- for (Index = 0; Index < NumberOfComplexes; Index++) {
- ComplexDescriptor = PcieInputParserGetComplexDescriptor (ComplexList, Index);
- if (ComplexDescriptor->SocketId == SocketId) {
- Status = PcieMapTopologyOnComplex (ComplexDescriptor, &Pcie->ComplexList[Index], Pcie);
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
- }
- }
- PcieFmGetComplexDataLength (SocketId, &CurrentComplexesDataLength);
- Buffer = (VOID *) ((UINT8 *)Buffer + CurrentComplexesDataLength);
- ComplexIndex++;
- }
- }
- Pcie->ComplexList[ComplexIndex - 1].Flags |= DESCRIPTOR_TERMINATE_LIST;
- Pcie->LinkReceiverDetectionPooling = PCIE_LINK_RECEIVER_DETECTION_POOLING;
- Pcie->LinkL0Pooling = PCIE_LINK_L0_POOLING;
- Pcie->LinkGpioResetAssertionTime = PCIE_LINK_GPIO_RESET_ASSERT_TIME;
- Pcie->LinkResetToTrainingTime = PCIE_LINK_RESET_TO_TRAINING_TIME;
- Pcie->GfxCardWorkaround = GfxWorkaroundEnable;
- if ((UserOptions.CfgAmdPlatformType & AMD_PLATFORM_MOBILE) != 0) {
- Pcie->GfxCardWorkaround = GfxWorkaroundDisable;
- }
- Pcie->PsppPolicy = EarlyParamsPtr->GnbConfig.PsppPolicy;
- IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PCIE_PLATFORM_CONFIG, Pcie, StdHeader);
- GNB_DEBUG_CODE (
- PcieConfigDebugDump (Pcie);
- );
- IDS_HDT_CONSOLE (GNB_TRACE, "PcieConfigurationInit Exit [0x%x]\n", AgesaStatus);
- return AgesaStatus;
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Locate global PCIe configuration data
- *
- *
- *
- * @param[in] StdHeader Standard configuration header
- * @param[out] Pcie Pointer to global PCIe configuration
- * @retval AGESA_SUCCESS Configuration data successfully located
- * @retval AGESA_FATAL Configuration can not be located.
- */
-AGESA_STATUS
-PcieLocateConfigurationData (
- IN AMD_CONFIG_PARAMS *StdHeader,
- OUT PCIe_PLATFORM_CONFIG **Pcie
- )
-{
- PCIe_COMPLEX_CONFIG *Complex;
- *Pcie = GnbLocateHeapBuffer (AMD_PCIE_COMPLEX_DATA_HANDLE, StdHeader);
- if (*Pcie == NULL) {
- IDS_ERROR_TRAP;
- return AGESA_FATAL;
- }
- if ((UINTN) (*Pcie) != (UINTN) (*Pcie)->This) {
- Complex = &(*Pcie)->ComplexList[0];
- while (Complex != NULL) {
- PCIe_SILICON_CONFIG *SiliconList;
- REBASE_PTR (&Complex->SiliconList, (UINTN) (*Pcie)->This, (UINTN)*Pcie);
- SiliconList = PcieComplexGetSiliconList (Complex);
- PcieRebaseConfigurationData (SiliconList, (UINTN) (*Pcie)->This, (UINTN)*Pcie);
- Complex = PcieLibGetNextDescriptor (Complex);
- }
- (*Pcie)->This = (UINTN)(*Pcie);
- }
- (*Pcie)->StdHeader = (PVOID) StdHeader;
- return AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Rebase all pointers in Complex Configuration Data
- *
- *
- *
- * @param[in] SiliconList Pointer to first silicon descriptor of the complex
- * @param[in] OldBase Old base address of the configuration data
- * @param[in] NewBase New base address of the configuration data
- */
-VOID
-PcieRebaseConfigurationData (
- IN PCIe_SILICON_CONFIG *SiliconList,
- IN UINTN OldBase,
- IN UINTN NewBase
- )
-{
- while (SiliconList != NULL) {
- PCIe_WRAPPER_CONFIG *WrapperList;
- REBASE_PTR (&SiliconList->WrapperList, OldBase, NewBase);
- REBASE_PTR (&SiliconList->FmSilicon, OldBase, NewBase);
- WrapperList = PcieSiliconGetWrapperList (SiliconList);
- while (WrapperList != NULL) {
- PCIe_ENGINE_CONFIG *EngineList;
- REBASE_PTR (&WrapperList->EngineList, OldBase, NewBase);
- REBASE_PTR (&WrapperList->FmWrapper, OldBase, NewBase);
- REBASE_PTR (&WrapperList->Silicon, OldBase, NewBase);
- EngineList = PcieWrapperGetEngineList (WrapperList);
- while (EngineList != NULL) {
- REBASE_PTR (&EngineList->Wrapper, OldBase, NewBase);
- EngineList = PcieLibGetNextDescriptor (EngineList);
- }
- WrapperList = PcieLibGetNextDescriptor (WrapperList);
- }
- SiliconList = PcieLibGetNextDescriptor (SiliconList);
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Helper function to dump configuration to debug out
- *
- *
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-VOID
-PcieConfigDebugDump (
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- PCIe_ENGINE_CONFIG *EngineList;
- PCIe_SILICON_CONFIG *SiliconList;
- PCIe_WRAPPER_CONFIG *WrapperList;
- PCIe_COMPLEX_CONFIG *ComplexList;
- ComplexList = &Pcie->ComplexList[0];
- IDS_HDT_CONSOLE (PCIE_MISC, "<-------------- PCIe Config Start----------------->\n");
- IDS_HDT_CONSOLE (PCIE_MISC, " PSPP Policy - %s\n",
- (Pcie->PsppPolicy == PsppPowerSaving) ? "Power Saving" :
- (Pcie->PsppPolicy == PsppBalanceHigh) ? "Balance-High" : (
- (Pcie->PsppPolicy == PsppBalanceLow) ? "Balance-Low" : (
- (Pcie->PsppPolicy == PsppPerformance) ? "Performance" : (
- (Pcie->PsppPolicy == PsppDisabled) ? "Disabled" : "Unknown")))
- );
- IDS_HDT_CONSOLE (PCIE_MISC, " GFX Workaround - %s\n",
- (Pcie->GfxCardWorkaround == 0) ? "Disabled" : "Enabled"
- );
- IDS_HDT_CONSOLE (PCIE_MISC, " LinkL0Pooling - %dus\n",
- Pcie->LinkL0Pooling
- );
- IDS_HDT_CONSOLE (PCIE_MISC, " LinkGpioResetAssertionTime - %dus\n",
- Pcie->LinkGpioResetAssertionTime
- );
- IDS_HDT_CONSOLE (PCIE_MISC, " LinkReceiverDetectionPooling - %dus\n",
- Pcie->LinkReceiverDetectionPooling
- );
- SiliconList = PcieComplexGetSiliconList (ComplexList);
- while (SiliconList != NULL) {
- WrapperList = PcieSiliconGetWrapperList (SiliconList);
- while (WrapperList != NULL) {
- IDS_HDT_CONSOLE (PCIE_MISC, " <---------Wrapper - %s Config -------->\n",
- PcieFmDebugGetWrapperNameString (WrapperList)
- );
- IDS_HDT_CONSOLE (PCIE_MISC, " PowerOffUnusedLanes - %x\n PowerOffUnusedPlls - %x\n ClkGating - %x\n"
- " LclkGating - %x\n TxclkGatingPllPowerDown - %x\n PllOffInL1 - %x\n",
- WrapperList->Features.PowerOffUnusedLanes,
- WrapperList->Features.PowerOffUnusedPlls,
- WrapperList->Features.ClkGating,
- WrapperList->Features.LclkGating,
- WrapperList->Features.TxclkGatingPllPowerDown,
- WrapperList->Features.PllOffInL1
- );
- IDS_HDT_CONSOLE (PCIE_MISC, " <---------Wrapper - %s Config End----->\n",
- PcieFmDebugGetWrapperNameString (WrapperList)
- );
- EngineList = PcieWrapperGetEngineList (WrapperList);
- while (EngineList != NULL) {
- if (PcieLibIsEngineAllocated (EngineList)) {
- IDS_HDT_CONSOLE (PCIE_MISC, " Engine Type - %s\n Start Phy Lane - %d\n End Phy Lane - %d\n",
- ((EngineList->EngineData.EngineType == PciePortEngine) ? "PCIe Port" : "DDI Link"),
- EngineList->EngineData.StartLane,
- EngineList->EngineData.EndLane
- );
- if (PcieLibIsPcieEngine (EngineList)) {
- IDS_HDT_CONSOLE (PCIE_MISC, " PCIe port configuration:\n");
- IDS_HDT_CONSOLE (PCIE_MISC, " Port Training - %s\n",
- (EngineList->Type.Port.PortData.PortPresent == PortDisabled) ? "Disable" : "Enabled"
- );
- IDS_HDT_CONSOLE (PCIE_MISC, " Start Core Lane - %d\n", EngineList->Type.Port.StartCoreLane);
- IDS_HDT_CONSOLE (PCIE_MISC, " End Core Lane - %d\n", EngineList->Type.Port.EndCoreLane);
- IDS_HDT_CONSOLE (PCIE_MISC, " PCI Address - %d:%d:%d\n",
- EngineList->Type.Port.Address.Address.Bus,
- EngineList->Type.Port.Address.Address.Device,
- EngineList->Type.Port.Address.Address.Function
- );
- IDS_HDT_CONSOLE (PCIE_MISC, " Native PCI Dev Number - %d\n", EngineList->Type.Port.NativeDevNumber);
- IDS_HDT_CONSOLE (PCIE_MISC, " Native PCI Func Number - %d\n", EngineList->Type.Port.NativeFunNumber);
- IDS_HDT_CONSOLE (PCIE_MISC, " Hotplug - %s\n",
- (EngineList->Type.Port.PortData.LinkHotplug == 0) ? "Disabled" : (
- (EngineList->Type.Port.PortData.LinkHotplug == 1) ? "Basic" : (
- (EngineList->Type.Port.PortData.LinkHotplug == 2) ? "Server" : (
- (EngineList->Type.Port.PortData.LinkHotplug == 2) ? "Enhanced" : "Unknown")))
- );
- IDS_HDT_CONSOLE (PCIE_MISC, " ASPM - %s\n",
- (EngineList->Type.Port.PortData.LinkAspm == 0) ? "Disabled" : (
- (EngineList->Type.Port.PortData.LinkAspm == 1) ? "L0s" : (
- (EngineList->Type.Port.PortData.LinkAspm == 2) ? "L1" : (
- (EngineList->Type.Port.PortData.LinkAspm == 3) ? "L0s & L1" : "Unknown")))
- );
- IDS_HDT_CONSOLE (PCIE_MISC, " Speed - %d\n",
- EngineList->Type.Port.PortData.LinkSpeedCapability
- );
- } else {
- IDS_HDT_CONSOLE (PCIE_MISC, " DDI configuration:\n");
- IDS_HDT_CONSOLE (PCIE_MISC, " Connector - %s\n",
- (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeDP) ? "DP" : (
- (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeEDP) ? "eDP" : (
- (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeSingleLinkDVI) ? "Single Link DVI" : (
- (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeDualLinkDVI) ? "Dual Link DVI" : (
- (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeHDMI) ? "HDMI" : (
- (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeTravisDpToVga) ? "Travis DP-to-VGA" : (
- (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeTravisDpToLvds) ? "Travis DP-to-LVDS" : (
- (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeLvds) ? "LVDS" : (
- (EngineList->Type.Ddi.DdiData.ConnectorType == ConnectorTypeNutmegDpToVga) ? "Hudson-2 Nutmeg DP-to-VGA" : "Unknown"))))))))
- );
- IDS_HDT_CONSOLE (PCIE_MISC, " Aux - Aux%d\n", EngineList->Type.Ddi.DdiData.AuxIndex + 1);
- IDS_HDT_CONSOLE (PCIE_MISC, " Hdp - Hdp%d\n", EngineList->Type.Ddi.DdiData.HdpIndex + 1);
- }
- }
- EngineList = PcieLibGetNextDescriptor (EngineList);
- }
- WrapperList = PcieLibGetNextDescriptor (WrapperList);
- }
- SiliconList = PcieLibGetNextDescriptor (SiliconList);
- }
- IDS_HDT_CONSOLE (PCIE_MISC, "<-------------- PCIe Config End------------------>\n");
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h
deleted file mode 100644
index f40a123..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * GNB function to create/locate PCIe configuration data area
- *
- * Contain code that create/locate and rebase configuration data area.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 38519 $ @e \$Date: 2010-09-24 17:08:48 -0700 (Fri, 24 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _PCIECONFIGDATA_H_
-#define _PCIECONFIGDATA_H_
-
-
-AGESA_STATUS
-PcieLocateConfigurationData (
- IN AMD_CONFIG_PARAMS *StdHeader,
- OUT PCIe_PLATFORM_CONFIG **Pcie
- );
-
-VOID
-PcieRebaseConfigurationData (
- IN PCIe_SILICON_CONFIG *SiliconList,
- IN UINTN OldBase,
- IN UINTN NewBase
- );
-
-#endif
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
deleted file mode 100644
index 616e1d5..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
+++ /dev/null
@@ -1,356 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * GNB function to create/locate PCIe configuration data area
- *
- * Contain code that create/locate and rebase configuration data area.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39898 $ @e \$Date: 2010-10-15 17:08:45 -0400 (Fri, 15 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "amdlib.h"
-#include "Gnb.h"
-#include "GnbPcie.h"
-#include "GnbPcieFamServices.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include GNB_MODULE_DEFINITIONS (GnbPcieConfig)
-#include "PcieMapTopology.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGLIB_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get number of core lanes
- *
- *
- *
- * @param[in] Engine Pointer to engine descriptor
- * @retval Number of core lane
- */
-UINT8
-PcieConfigGetNumberOfCoreLane (
- IN PCIe_ENGINE_CONFIG *Engine
- )
-{
- if (Engine->Type.Port.StartCoreLane >= UNUSED_LANE_ID || Engine->Type.Port.EndCoreLane >= UNUSED_LANE_ID) {
- return 0;
- }
- return (UINT8) (Engine->Type.Port.EndCoreLane - Engine->Type.Port.StartCoreLane + 1);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Disable engine
- *
- *
- *
- * @param[in] Engine Pointer to engine config descriptor
- */
-VOID
-PcieConfigDisableEngine (
- IN PCIe_ENGINE_CONFIG *Engine
- )
-{
- if (Engine->Type.Port.IsSB) {
- return;
- }
- Engine->Flags &= ~DESCRIPTOR_ALLOCATED;
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Disable all engines on wrapper
- *
- *
- *
- * @param[in] EngineTypeMask Engine type bitmap.
- * @param[in] Wrapper Pointer to wrapper config descriptor
- */
-VOID
-PcieConfigDisableAllEngines (
- IN UINTN EngineTypeMask,
- IN PCIe_WRAPPER_CONFIG *Wrapper
- )
-{
- PCIe_ENGINE_CONFIG *EngineList;
- EngineList = PcieWrapperGetEngineList (Wrapper);
- while (EngineList != NULL) {
- if ((EngineList->EngineData.EngineType & EngineTypeMask) != 0) {
- PcieConfigDisableEngine (EngineList);
- }
- EngineList = PcieLibGetNextDescriptor (EngineList);
- }
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get engine PHY lanes bitmap
- *
- *
- *
- * @param[in] Engine Pointer to engine config descriptor
- */
-UINT32
-PcieConfigGetEnginePhyLaneBitMap (
- IN PCIe_ENGINE_CONFIG *Engine
- )
-{
- UINT32 LaneBitMap;
- LaneBitMap = 0;
- if (PcieLibIsEngineAllocated (Engine)) {
- LaneBitMap = ((1 << PcieConfigGetNumberOfPhyLane (Engine)) - 1) << (PcieUtilGetLoPhyLane (Engine) - PcieEngineGetParentWrapper (Engine)->StartPhyLane);
- }
- return LaneBitMap;
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get number of phy lanes
- *
- *
- *
- * @param[in] Engine Pointer to engine config descriptor
- * @retval Number of Phy lane
- */
-UINT8
-PcieConfigGetNumberOfPhyLane (
- IN PCIe_ENGINE_CONFIG *Engine
- )
-{
- if (Engine->EngineData.StartLane >= UNUSED_LANE_ID || Engine->EngineData.StartLane >= UNUSED_LANE_ID) {
- return 0;
- }
- if (Engine->EngineData.StartLane > Engine->EngineData.EndLane) {
- return (UINT8) (Engine->EngineData.StartLane - Engine->EngineData.EndLane + 1);
- } else {
- return (UINT8) (Engine->EngineData.EndLane - Engine->EngineData.StartLane + 1);
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get port configuration signature for given wrapper and core
- *
- * Support for unify register access through index/data pair on GNB
- *
- * @param[in] Wrapper Pointer to wrapper config descriptor
- * @param[in] CoreId Core ID
- * @retval Configuration Signature
- */
-UINT64
-PcieConfigGetConfigurationSignature (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN UINT8 CoreId
- )
-{
- UINT64 ConfigurationSignature;
- PCIe_ENGINE_CONFIG *EngineList;
- ConfigurationSignature = 0;
- EngineList = PcieWrapperGetEngineList (Wrapper);
- while (EngineList != NULL) {
- if (EngineList->Type.Port.CoreId == CoreId) {
- ConfigurationSignature = (ConfigurationSignature << 8) | PcieConfigGetNumberOfCoreLane (EngineList);
- }
- EngineList = PcieLibGetNextDescriptor (EngineList);
- }
- return ConfigurationSignature;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Check Port Status
- *
- *
- *
- * @param[in] Engine Pointer to engine config descriptor
- * @param[in] PortStatus Check if status asserted for port
- * @retval TRUE if status asserted
- */
-BOOLEAN
-PcieConfigCheckPortStatus (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN UINT32 PortStatus
- )
-{
- return (Engine->InitStatus & PortStatus) == 0 ? FALSE : TRUE;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Set/Reset port status
- *
- *
- *
- * @param[in] Engine Pointer to engine config descriptor
- * @param[in] SetStatus SetStatus
- * @param[in] ResetStatus ResetStatus
- *
- */
-UINT32
-PcieConfigUpdatePortStatus (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN UINT32 SetStatus,
- IN UINT32 ResetStatus
- )
-{
- Engine->InitStatus |= SetStatus;
- Engine->InitStatus &= (~ResetStatus);
- return Engine->InitStatus;
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Execute callback on all engine in topology
- *
- *
- * @param[in] DescriptorFlags Wrapper Flags
- * @param[in] Callback Pointer to callback function
- * @param[in, out] Buffer Pointer to buffer to pass information to callback
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-
-AGESA_STATUS
-PcieConfigRunProcForAllWrappers (
- IN UINT32 DescriptorFlags,
- IN PCIe_RUN_ON_WRAPPER_CALLBACK Callback,
- IN OUT VOID *Buffer,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- AGESA_STATUS AgesaStatus;
- AGESA_STATUS Status;
- PCIe_COMPLEX_CONFIG *Complex;
- AgesaStatus = AGESA_SUCCESS;
- Complex = Pcie->ComplexList;
- while (Complex != NULL) {
- PCIe_SILICON_CONFIG *Silicon;
- Silicon = PcieComplexGetSiliconList (Complex);
- while (Silicon != NULL) {
- PCIe_WRAPPER_CONFIG *Wrapper;
- Wrapper = PcieSiliconGetWrapperList (Silicon);
- while (Wrapper != NULL) {
- if (!(PcieLibIsVirtualDesciptor (Wrapper) && (DescriptorFlags & DESCRIPTOR_VIRTUAL) == 0)) {
- if ((DescriptorFlags & DESCRIPTOR_ALL_WRAPPERS & Wrapper->Flags) != 0) {
- Status = Callback (Wrapper, Buffer, Pcie);
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
- }
- }
- Wrapper = PcieLibGetNextDescriptor (Wrapper);
- }
- Silicon = PcieLibGetNextDescriptor (Silicon);
- }
- Complex = PcieLibGetNextDescriptor (Complex);
- }
- return AgesaStatus;
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Execute callback on all engine in topology
- *
- *
- * @param[in] DescriptorFlags Engine flags.
- * @param[in] Callback Pointer to callback function
- * @param[in, out] Buffer Pointer to buffer to pass information to callback
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-
-VOID
-PcieConfigRunProcForAllEngines (
- IN UINT32 DescriptorFlags,
- IN PCIe_RUN_ON_ENGINE_CALLBACK Callback,
- IN OUT VOID *Buffer,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- PCIe_COMPLEX_CONFIG *Complex;
- Complex = Pcie->ComplexList;
- while (Complex != NULL) {
- PCIe_SILICON_CONFIG *Silicon;
- Silicon = PcieComplexGetSiliconList (Complex);
- while (Silicon != NULL) {
- PCIe_WRAPPER_CONFIG *Wrapper;
- Wrapper = PcieSiliconGetWrapperList (Silicon);
- while (Wrapper != NULL) {
- PCIe_ENGINE_CONFIG *Engine;
- Engine = PcieWrapperGetEngineList (Wrapper);
- while (Engine != NULL) {
- if (!(PcieLibIsVirtualDesciptor (Engine) && (DescriptorFlags & DESCRIPTOR_VIRTUAL) == 0)) {
- if (!((DescriptorFlags & DESCRIPTOR_ALLOCATED) != 0 && !PcieLibIsEngineAllocated (Engine))) {
- if ((Engine->Flags & DESCRIPTOR_ALL_ENGINES & DescriptorFlags) != 0) {
- Callback (Engine, Buffer, Pcie);
- }
- }
- }
- Engine = PcieLibGetNextDescriptor (Engine);
- }
- Wrapper = PcieLibGetNextDescriptor (Wrapper);
- }
- Silicon = PcieLibGetNextDescriptor (Silicon);
- }
- Complex = PcieLibGetNextDescriptor (Complex);
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h
deleted file mode 100644
index 18b6615..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * GNB function to create/locate PCIe configuration data area
- *
- * Contain code that create/locate and rebase configuration data area.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 38519 $ @e \$Date: 2010-09-24 17:08:48 -0700 (Fri, 24 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _PCIECONFIGLIB_H_
-#define _PCIECONFIGLIB_H_
-
-typedef VOID (*PCIe_RUN_ON_ENGINE_CALLBACK) (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN OUT VOID *Buffer,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-typedef AGESA_STATUS (*PCIe_RUN_ON_WRAPPER_CALLBACK) (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN OUT VOID *Buffer,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-UINT8
-PcieConfigGetNumberOfCoreLane (
- IN PCIe_ENGINE_CONFIG *Engine
- );
-
-VOID
-PcieConfigDisableAllEngines (
- IN UINTN EngineTypeMask,
- IN PCIe_WRAPPER_CONFIG *Wrapper
- );
-
-VOID
-PcieConfigDisableEngine (
- IN PCIe_ENGINE_CONFIG *Engine
- );
-
-UINT32
-PcieConfigGetEnginePhyLaneBitMap (
- IN PCIe_ENGINE_CONFIG *Engine
- );
-
-UINT8
-PcieConfigGetNumberOfPhyLane (
- IN PCIe_ENGINE_CONFIG *Engine
- );
-
-UINT64
-PcieConfigGetConfigurationSignature (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN UINT8 CoreId
- );
-
-BOOLEAN
-PcieConfigCheckPortStatus (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN UINT32 PortStatus
- );
-
-UINT32
-PcieConfigUpdatePortStatus (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN UINT32 SetStatus,
- IN UINT32 ResetStatus
- );
-
-VOID
-PcieConfigRunProcForAllEngines (
- IN UINT32 DescriptorFlags,
- IN PCIe_RUN_ON_ENGINE_CALLBACK Callback,
- IN OUT VOID *Buffer,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-AGESA_STATUS
-PcieConfigRunProcForAllWrappers (
- IN UINT32 DescriptorFlags,
- IN PCIe_RUN_ON_WRAPPER_CALLBACK Callback,
- IN OUT VOID *Buffer,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-#endif
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c
deleted file mode 100644
index 6a9da54..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c
+++ /dev/null
@@ -1,218 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Procedure to parse PCIe input configuration data
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39898 $ @e \$Date: 2010-10-15 17:08:45 -0400 (Fri, 15 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "Gnb.h"
-#include "GnbPcie.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_PCIEINPUTPARSER_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get number of complexes in platform topology configuration
- *
- *
- *
- * @param[in] ComplexList First complex configuration in complex configuration array
- * @retval Number of Complexes
- *
- */
-UINTN
-PcieInputParserGetNumberOfComplexes (
- IN PCIe_COMPLEX_DESCRIPTOR *ComplexList
- )
-{
- UINTN Result;
- Result = 0;
- while (ComplexList != NULL) {
- Result++;
- ComplexList = PcieLibGetNextDescriptor (ComplexList);
- }
- return Result;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get number of PCIe engines in given complex
- *
- *
- *
- * @param[in] Complex Complex configuration
- * @retval Number of Engines
- */
-UINTN
-PcieInputParserGetLengthOfPcieEnginesList (
- IN PCIe_COMPLEX_DESCRIPTOR *Complex
- )
-{
- UINTN Result;
- PCIe_PORT_DESCRIPTOR *PciePortList;
- Result = 0;
- PciePortList = Complex->PciePortList;
- while (PciePortList != NULL) {
- Result++;
- PciePortList = PcieLibGetNextDescriptor (PciePortList);
- }
- return Result;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get number of DDI engines in given complex
- *
- *
- *
- * @param[in] Complex Complex configuration
- * @retval Number of Engines
- */
-UINTN
-PcieInputParserGetLengthOfDdiEnginesList (
- IN PCIe_COMPLEX_DESCRIPTOR *Complex
- )
-{
- UINTN Result;
- PCIe_DDI_DESCRIPTOR *DdiLinkList;
- Result = 0;
- DdiLinkList = Complex->DdiLinkList;
- while (DdiLinkList != NULL) {
- Result++;
- DdiLinkList = PcieLibGetNextDescriptor (DdiLinkList);
- }
- return Result;
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get number of engines in given complex
- *
- *
- *
- * @param[in] Complex Complex configuration header
- * @retval Number of Engines
- */
-UINTN
-PcieInputParserGetNumberOfEngines (
- IN PCIe_COMPLEX_DESCRIPTOR *Complex
- )
-{
- UINTN Result;
-
- Result = PcieInputParserGetLengthOfDdiEnginesList (Complex) +
- PcieInputParserGetLengthOfPcieEnginesList (Complex);
- return Result;
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get Complex descriptor by index from given Platform configuration
- *
- *
- *
- * @param[in] ComplexList Platform topology configuration
- * @param[in] Index Complex descriptor Index
- * @retval Pointer to Complex Descriptor
- */
-PCIe_COMPLEX_DESCRIPTOR*
-PcieInputParserGetComplexDescriptor (
- IN PCIe_COMPLEX_DESCRIPTOR *ComplexList,
- IN UINTN Index
- )
-{
- ASSERT (Index < (PcieInputParserGetNumberOfComplexes (ComplexList)));
- return &ComplexList[Index];
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get Engine descriptor from given complex by index
- *
- *
- *
- * @param[in] Complex Complex descriptor
- * @param[in] Index Engine descriptor index
- * @retval Pointer to Engine Descriptor
- */
-PCIe_ENGINE_DESCRIPTOR*
-PcieInputParserGetEngineDescriptor (
- IN PCIe_COMPLEX_DESCRIPTOR *Complex,
- IN UINTN Index
- )
-{
- UINTN PcieListlength;
- ASSERT (Index < (PcieInputParserGetNumberOfEngines (Complex)));
- PcieListlength = PcieInputParserGetLengthOfPcieEnginesList (Complex);
- if (Index < PcieListlength) {
- return (PCIe_ENGINE_DESCRIPTOR*) &((Complex->PciePortList)[Index]);
- } else {
- return (PCIe_ENGINE_DESCRIPTOR*) &((Complex->DdiLinkList)[Index - PcieListlength]);
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h
deleted file mode 100644
index e30d1e1..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Procedure to parse PCIe input configuration data
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _PCIEINPUTPARSER_H_
-#define _PCIEINPUTPARSER_H_
-
-
-UINTN
-PcieInputParserGetNumberOfComplexes (
- IN PCIe_COMPLEX_DESCRIPTOR *ComplexList
- );
-
-UINTN
-PcieInputParserGetNumberOfEngines (
- IN PCIe_COMPLEX_DESCRIPTOR *Complex
- );
-
-
-PCIe_COMPLEX_DESCRIPTOR*
-PcieInputParserGetComplexDescriptor (
- IN PCIe_COMPLEX_DESCRIPTOR *ComplexList,
- IN UINTN Index
- );
-
-PCIe_ENGINE_DESCRIPTOR*
-PcieInputParserGetEngineDescriptor (
- IN PCIe_COMPLEX_DESCRIPTOR *Complex,
- IN UINTN Index
- );
-
-
-#endif
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c
deleted file mode 100644
index 7021551..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c
+++ /dev/null
@@ -1,720 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Procedure to map user define topology to processor configuration
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39898 $ @e \$Date: 2010-10-15 17:08:45 -0400 (Fri, 15 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "amdlib.h"
-#include "Gnb.h"
-#include "GnbPcie.h"
-#include "GnbPcieFamServices.h"
-#include "GeneralServices.h"
-#include "PcieInputParser.h"
-#include "PcieMapTopology.h"
-#include GNB_MODULE_DEFINITIONS (GnbPcieConfig)
-#include "Filecode.h"
-#define FILECODE PROC_GNB_MODULES_GNBPCIECONFIG_PCIEMAPTOPOLOGY_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-AGESA_STATUS
-STATIC
-PcieMapPortsPciAddresses (
- IN PCIe_SILICON_CONFIG *Silicon,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-AGESA_STATUS
-PcieMapTopologyOnWrapper (
- IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor,
- IN OUT PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PcieMapInitializeEngineData (
- IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor,
- IN OUT PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-BOOLEAN
-PcieCheckPortPciDeviceMapping (
- IN PCIe_PORT_DESCRIPTOR *PortDescriptor,
- IN PCIe_ENGINE_CONFIG *Engine
- );
-
-VOID
-PcieComplexConfigConfigDump (
- IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-BOOLEAN
-PcieIsDescriptorLinkWidthValid (
- IN PCIe_ENGINE_DESCRIPTOR *EngineDescriptor
- );
-
-BOOLEAN
-PcieCheckLanesMatch (
- IN PCIe_ENGINE_DESCRIPTOR *EngineDescriptor,
- IN PCIe_ENGINE_CONFIG *Engine
- );
-
-BOOLEAN
-PcieCheckDescriptorMapsToWrapper (
- IN PCIe_ENGINE_DESCRIPTOR *EngineDescriptor,
- IN PCIe_WRAPPER_CONFIG *Wrapper
- );
-
-VOID
-PcieAllocateEngine (
- IN UINT8 DescriptorIndex,
- IN PCIe_ENGINE_CONFIG *Engine
- );
-/*----------------------------------------------------------------------------------------*/
-/**
- * Configure engine list to support lane allocation according to configuration ID.
- *
- *
- *
- * @param[in] ComplexDescriptor Pointer to used define complex descriptor
- * @param[in] Complex Pointer to complex descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- * @retval AGESA_SUCCESS Topology successfully mapped
- * @retval AGESA_ERROR Topology can not be mapped
- */
-
-AGESA_STATUS
-PcieMapTopologyOnComplex (
- IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor,
- IN PCIe_COMPLEX_CONFIG *Complex,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- PCIe_SILICON_CONFIG *Silicon;
- PCIe_WRAPPER_CONFIG *Wrapper;
- AGESA_STATUS AgesaStatus;
- AGESA_STATUS Status;
-
- AgesaStatus = AGESA_SUCCESS;
- IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapTopologyOnComplex Enter\n");
- GNB_DEBUG_CODE (
- PcieComplexConfigConfigDump (ComplexDescriptor, Pcie);
- );
- Silicon = PcieComplexGetSiliconList (Complex);
- while (Silicon != NULL) {
- Wrapper = PcieSiliconGetWrapperList (Silicon);
- while (Wrapper != NULL) {
- Status = PcieMapTopologyOnWrapper (ComplexDescriptor, Wrapper, Pcie);
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
- if (Status == AGESA_ERROR) {
- PcieConfigDisableAllEngines (PciePortEngine | PcieDdiEngine, Wrapper);
- IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Fail to map topology on %s Wrapper\n",
- PcieFmDebugGetWrapperNameString (Wrapper)
- );
- ASSERT (FALSE);
- }
- Wrapper = PcieLibGetNextDescriptor (Wrapper);
- }
- Status = PcieMapPortsPciAddresses (Silicon, Pcie);
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
- Silicon = PcieLibGetNextDescriptor (Silicon);
- }
- IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapTopologyOnComplex Exit [%x]\n", AgesaStatus);
- return AgesaStatus;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Configure engine list to support lane allocation according to configuration ID.
- *
- *
- *
- * @param[in] EngineType Engine type
- * @param[in] ComplexDescriptor Pointer to used define complex descriptor
- * @param[in] Wrapper Pointer to wrapper config descriptor
- * @retval AGESA_SUCCESS Topology successfully mapped
- * @retval AGESA_ERROR Topology can not be mapped
- */
-AGESA_STATUS
-PcieEnginesToWrapper (
- IN PCIE_ENGINE_TYPE EngineType,
- IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor,
- IN PCIe_WRAPPER_CONFIG *Wrapper
- )
-{
- AGESA_STATUS Status;
- PCIe_ENGINE_CONFIG *EngineList;
- PCIe_ENGINE_DESCRIPTOR *EngineDescriptor;
- UINT8 ConfigurationId;
- UINT8 Allocations;
- UINTN Index;
- UINTN NumberOfDescriptors;
-
- ConfigurationId = 0;
- Allocations = 0;
- IDS_HDT_CONSOLE (GNB_TRACE, "PcieEnginesToWrapper Enter\n");
- NumberOfDescriptors = PcieInputParserGetNumberOfEngines (ComplexDescriptor);
- do {
- Status = PcieFmConfigureEnginesLaneAllocation (Wrapper, EngineType, ConfigurationId++);
-
- if (Status == AGESA_SUCCESS) {
- Allocations = 0;
- for (Index = 0; Index < NumberOfDescriptors; Index++) {
- EngineDescriptor = PcieInputParserGetEngineDescriptor (ComplexDescriptor, Index);
- if (EngineDescriptor->EngineData.EngineType == EngineType) {
- // Step 1, belongs to wrapper check.
- if (PcieCheckDescriptorMapsToWrapper (EngineDescriptor, Wrapper)) {
- ++Allocations;
- EngineList = PcieWrapperGetEngineList (Wrapper);
- while (EngineList != NULL) {
- if (!PcieLibIsEngineAllocated (EngineList)) {
- // Step 2.user descriptor less or equal to link width of engine
- if (PcieCheckLanesMatch (EngineDescriptor, EngineList)) {
- // Step 3, Check if link width is correct.x1, x2, x4, x8, x16.
- if (!PcieIsDescriptorLinkWidthValid (EngineDescriptor)) {
- PcieConfigDisableEngine (EngineList);
- return AGESA_ERROR;
- }
- if (EngineDescriptor->EngineData.EngineType == PciePortEngine) {
- // Step 4, Family specifc, port device number match engine device
- if (PcieCheckPortPciDeviceMapping ((PCIe_PORT_DESCRIPTOR*) EngineDescriptor, EngineList)) {
- //Step 5, Family specifc, lanes can be muxed.
- if (PcieFmCheckPortPcieLaneCanBeMuxed ((PCIe_PORT_DESCRIPTOR*) EngineDescriptor, EngineList)) {
- PcieAllocateEngine ((UINT8) Index, EngineList);
- --Allocations;
- }
- }
- } else {
- PcieAllocateEngine ((UINT8) Index, EngineList);
- --Allocations;
- }
- }
- }//end if PcieLibIsEngineAllocated
- EngineList = PcieLibGetNextDescriptor (EngineList);
- }
- }//end if PcieCheckDescriptorMapsToWrapper
- }// end if EngineType
- }//end for
- }
- } while (Status == AGESA_SUCCESS && Allocations != 0);
- IDS_HDT_CONSOLE (GNB_TRACE, "PcieEnginesToWrapper Exit [%x]\n", Status);
- return Status;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Check if lane from user port descriptor (PCIe_PORT_DESCRIPTOR) belongs to wrapper (PCIe_WRAPPER_CONFIG)
- *
- *
- * @param[in] EngineDescriptor Pointer to used define engine descriptor
- * @param[in] Wrapper Pointer to PCIe_WRAPPER_CONFIG
- * @retval TRUE Belongs to wrapper
- * @retval FALSE Not belongs to wrapper
- */
-BOOLEAN
-PcieCheckDescriptorMapsToWrapper (
- IN PCIe_ENGINE_DESCRIPTOR *EngineDescriptor,
- IN PCIe_WRAPPER_CONFIG *Wrapper
- )
-{
- BOOLEAN Result;
- UINT16 DescriptorHiLane;
- UINT16 DescriptorLoLane;
- UINT16 DescriptorNumberOfLanes;
-
- DescriptorLoLane = MIN (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane);
- DescriptorHiLane = MAX (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane);
- DescriptorNumberOfLanes = DescriptorHiLane - DescriptorLoLane + 1;
- Result = TRUE;
-
- if (!(DescriptorLoLane >= Wrapper->StartPhyLane && DescriptorHiLane <= Wrapper->EndPhyLane)) {
- // Lanes of descriptor does not belongs to wrapper
- Result = FALSE;
- }
- return Result;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Set Engine to be allocated.
- *
- *
- * @param[in] DescriptorIndex UINT8 index
- * @param[in] Engine Pointer to engine config
- */
-VOID
-PcieAllocateEngine (
- IN UINT8 DescriptorIndex,
- IN PCIe_ENGINE_CONFIG *Engine
- )
-{
- Engine->Flags |= DESCRIPTOR_ALLOCATED;
- Engine->Scratch = DescriptorIndex;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Configure engine list to support lane allocation according to configuration ID.
- *
- * PCIE port
- *
- *
- * 1 Check if lane from user port descriptor (PCIe_PORT_DESCRIPTOR) belongs to wrapper (PCIe_WRAPPER_CONFIG)
- * 2 Check if link width from user descriptor less or equal to link width of engine (PCIe_ENGINE_CONFIG)
- * 3 Check if link width is correct. Correct link width for PCIe port x1, x2, x4, x8, x16, correct link width for DDI x4, x8
- * 4 Check if user port device number (PCIe_PORT_DESCRIPTOR) match engine port device number (PCIe_ENGINE_CONFIG)
- * 5 Check if lane can be muxed
- *
- *
- * DDI Link
- *
- * 1 Check if lane from user port descriptor (PCIe_DDI_DESCRIPTOR) belongs to wrapper (PCIe_WRAPPER_CONFIG)
- * 2 Check lane from (PCIe_DDI_DESCRIPTOR) match exactly phy lane (PCIe_ENGINE_CONFIG)
- *
- *
- *
- * @param[in] ComplexDescriptor Pointer to used define complex descriptor
- * @param[in,out] Wrapper Pointer to wrapper config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- * @retval AGESA_SUCCESS Topology successfully mapped
- * @retval AGESA_ERROR Topology can not be mapped
- */
-AGESA_STATUS
-PcieMapTopologyOnWrapper (
- IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor,
- IN OUT PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- AGESA_STATUS AgesaStatus;
- AGESA_STATUS Status;
- PCIe_ENGINE_CONFIG *EngineList;
- UINT32 WrapperPhyLaneBitMap;
-
- AgesaStatus = AGESA_SUCCESS;
- if (PcieLibIsPcieWrapper (Wrapper)) {
- Status = PcieEnginesToWrapper (PciePortEngine, ComplexDescriptor, Wrapper);
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
- if (Status == AGESA_ERROR) {
- // If we can not map topology on wrapper we can not enable any engines.
- PutEventLog (
- AGESA_ERROR,
- GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION,
- Wrapper->WrapId,
- Wrapper->StartPhyLane,
- Wrapper->EndPhyLane,
- 0,
- GnbLibGetHeader (Pcie)
- );
- PcieConfigDisableAllEngines (PciePortEngine, Wrapper);
- }
- EngineList = PcieWrapperGetEngineList (Wrapper);
- // Assure SB is allocated
- while (EngineList != NULL) {
- if ((EngineList->EngineData.EngineType == PciePortEngine) && (EngineList->Type.Port.IsSB)) {
- EngineList->Flags |= DESCRIPTOR_ALLOCATED;
- }
- EngineList = PcieLibGetNextDescriptor (EngineList);
- }
- }
- if (PcieLibIsDdiWrapper (Wrapper)) {
- Status = PcieEnginesToWrapper (PcieDdiEngine, ComplexDescriptor, Wrapper);
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
- if (Status == AGESA_ERROR) {
- // If we can not map topology on wrapper we can not enable any engines.
- PutEventLog (
- AGESA_ERROR,
- GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION,
- Wrapper->WrapId,
- Wrapper->StartPhyLane,
- Wrapper->EndPhyLane,
- 0,
- GnbLibGetHeader (Pcie)
- );
- PcieConfigDisableAllEngines (PcieDdiEngine, Wrapper);
- }
- }
- // Copy engine data
- PcieMapInitializeEngineData (ComplexDescriptor, Wrapper, Pcie);
-
- EngineList = PcieWrapperGetEngineList (Wrapper);
- // Verify if we oversubscribe lanes and PHY link width
- WrapperPhyLaneBitMap = 0;
- while (EngineList != NULL) {
- UINT32 EnginePhyLaneBitMap;
- if (PcieLibIsEngineAllocated (EngineList)) {
- EnginePhyLaneBitMap = PcieConfigGetEnginePhyLaneBitMap (EngineList);
- if ((WrapperPhyLaneBitMap & EnginePhyLaneBitMap) != 0) {
- IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Lanes double subscribe lanes [Engine Lanes %d..%d]\n",
- EngineList->EngineData.StartLane,
- EngineList->EngineData.EndLane
- );
- PutEventLog (
- AGESA_ERROR,
- GNB_EVENT_INVALID_LANES_CONFIGURATION,
- EngineList->EngineData.StartLane,
- EngineList->EngineData.EndLane,
- 0,
- 0,
- GnbLibGetHeader (Pcie)
- );
- PcieConfigDisableEngine (EngineList);
- Status = AGESA_ERROR;
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
- } else {
- WrapperPhyLaneBitMap |= EnginePhyLaneBitMap;
- }
- }
- EngineList = PcieLibGetNextDescriptor (EngineList);
- }
- return AgesaStatus;
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Initialize engine data
- *
- *
- *
- * @param[in] ComplexDescriptor Pointer to user defined complex descriptor
- * @param[in,out] Wrapper Pointer to wrapper config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-VOID
-PcieMapInitializeEngineData (
- IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor,
- IN OUT PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- PCIe_ENGINE_CONFIG *EngineList;
- PCIe_ENGINE_DESCRIPTOR *EngineDescriptor;
-
- EngineList = PcieWrapperGetEngineList (Wrapper);
- while (EngineList != NULL) {
- if (PcieLibIsEngineAllocated (EngineList)) {
- if (EngineList->Scratch != 0xFF) {
- EngineDescriptor = PcieInputParserGetEngineDescriptor (ComplexDescriptor, EngineList->Scratch);
- LibAmdMemCopy (&EngineList->EngineData, &EngineDescriptor->EngineData, sizeof (EngineDescriptor->EngineData), GnbLibGetHeader (Pcie));
- if (PcieLibIsDdiEngine (EngineList)) {
- LibAmdMemCopy (&EngineList->Type.Ddi, &((PCIe_DDI_DESCRIPTOR*) EngineDescriptor)->Ddi, sizeof (PCIe_DDI_DATA), GnbLibGetHeader (Pcie));
- EngineList->Type.Ddi.DisplayPriorityIndex = (UINT8) EngineList->Scratch;
- } else if (PcieLibIsPcieEngine (EngineList)) {
- LibAmdMemCopy (&EngineList->Type.Port, &((PCIe_PORT_DESCRIPTOR*) EngineDescriptor)->Port, sizeof (PCIe_PORT_DATA), GnbLibGetHeader (Pcie));
- }
- }
- }
- EngineList = PcieLibGetNextDescriptor (EngineList);
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Allocate PCI addresses for all PCIe engines on silicon
- *
- *
- *
- * @param[in] PortDescriptor Pointer to user defined engine descriptor
- * @param[in] Engine Pointer engine configuration
- * @retval TRUE Descriptor can be mapped to engine
- * @retval FALSE Descriptor can NOT be mapped to engine
- */
-
-BOOLEAN
-PcieCheckPortPciDeviceMapping (
- IN PCIe_PORT_DESCRIPTOR *PortDescriptor,
- IN PCIe_ENGINE_CONFIG *Engine
- )
-{
- BOOLEAN Result;
-
- if ((PortDescriptor->Port.DeviceNumber == Engine->Type.Port.NativeDevNumber &&
- PortDescriptor->Port.FunctionNumber == Engine->Type.Port.NativeFunNumber) ||
- (PortDescriptor->Port.DeviceNumber == 0 && PortDescriptor->Port.FunctionNumber == 0)) {
- Result = TRUE;
- } else {
- Result = PcieFmCheckPortPciDeviceMapping (PortDescriptor, Engine);
- }
-
- return Result;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Allocate PCI addresses for all PCIe engines on silicon
- *
- *
- *
- * @param[in] Silicon Pointer to silicon configurration
- * @param[in] Pcie Pointer PCIe configuration
- * @retval AGESA_ERROR Fail to allocate PCI device address
- * @retval AGESA_SUCCESS Successfully allocate PCI address for all PCIe ports
- */
-
-AGESA_STATUS
-STATIC
-PcieMapPortsPciAddresses (
- IN PCIe_SILICON_CONFIG *Silicon,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- AGESA_STATUS Status;
- AGESA_STATUS AgesaStatus;
- PCIe_WRAPPER_CONFIG *WrapperList;
- PCIe_ENGINE_CONFIG *EngineList;
- AgesaStatus = AGESA_SUCCESS;
- WrapperList = PcieSiliconGetWrapperList (Silicon);
- while (WrapperList != NULL) {
- EngineList = PcieWrapperGetEngineList (WrapperList);
- while (EngineList != NULL) {
- if (PcieLibIsPcieEngine (EngineList) && PcieLibIsEngineAllocated (EngineList)) {
- Status = PcieFmMapPortPciAddress (EngineList, Pcie);
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
- if (Status == AGESA_SUCCESS) {
- EngineList->Type.Port.Address.AddressValue = MAKE_SBDFO (
- 0,
- Silicon->Address.Address.Bus,
- EngineList->Type.Port.PortData.DeviceNumber,
- EngineList->Type.Port.PortData.FunctionNumber,
- 0
- );
- } else {
- EngineList->Type.Port.PortData.PortPresent = OFF;
- IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Fail to allocate PCI address for PCIe port\n"
- );
- //Report error
- PutEventLog (
- AGESA_ERROR,
- GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION,
- EngineList->Type.Port.PortData.DeviceNumber,
- 0,
- 0,
- 0,
- GnbLibGetHeader (Pcie)
- );
- }
- }
- EngineList = PcieLibGetNextDescriptor (EngineList);
- }
- WrapperList = PcieLibGetNextDescriptor (WrapperList);
- }
- return AgesaStatus;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * If link width from user descriptor less or equal to link width of engine
- *
- *
- * @param[in] EngineDescriptor Pointer to used define engine descriptor
- * @param[in] Engine Pointer to engine config
- * @retval TRUE Descriptor can be mapped to engine
- * @retval FALSE Descriptor can NOT be mapped to engine
- */
-
-BOOLEAN
-PcieCheckLanesMatch (
- IN PCIe_ENGINE_DESCRIPTOR *EngineDescriptor,
- IN PCIe_ENGINE_CONFIG *Engine
- )
-{
- BOOLEAN Result;
- UINT16 DescriptorHiLane;
- UINT16 DescriptorLoLane;
- UINT16 DescriptorNumberOfLanes;
-
- DescriptorLoLane = MIN (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane);
- DescriptorHiLane = MAX (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane);
- DescriptorNumberOfLanes = DescriptorHiLane - DescriptorLoLane + 1;
- Result = FALSE;
-
- if (EngineDescriptor->EngineData.EngineType == PciePortEngine) {
- //
- // If link width from user descriptor less or equal to link width of engine (PCIe_ENGINE_CONFIG)
- //
- if (DescriptorNumberOfLanes <= PcieConfigGetNumberOfCoreLane (Engine)) {
- Result = TRUE;
- }
- } else if (EngineDescriptor->EngineData.EngineType == PcieDdiEngine) {
- //
- //For Ddi, check lane from (PCIe_DDI_DESCRIPTOR) match exactly phy lane (PCIe_ENGINE_CONFIG)
- //
- if ((Engine->EngineData.StartLane == DescriptorLoLane) && (Engine->EngineData.EndLane == DescriptorHiLane)) {
- Result = TRUE;
- }
- }
-
- return Result;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Correct link width for PCIe port x1, x2, x4, x8, x16, correct link width for DDI x4, x8
- *
- *
- * @param[in] EngineDescriptor A pointer of PCIe_ENGINE_DESCRIPTOR
- * @retval TRUE Descriptor can be mapped to engine
- * @retval FALSE Descriptor can NOT be mapped to engine
- */
-
-BOOLEAN
-PcieIsDescriptorLinkWidthValid (
- IN PCIe_ENGINE_DESCRIPTOR *EngineDescriptor
- )
-{
- BOOLEAN Result;
- UINT16 DescriptorHiLane;
- UINT16 DescriptorLoLane;
- UINT16 DescriptorNumberOfLanes;
-
- Result = FALSE;
- DescriptorLoLane = MIN (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane);
- DescriptorHiLane = MAX (EngineDescriptor->EngineData.StartLane, EngineDescriptor->EngineData.EndLane);
- DescriptorNumberOfLanes = DescriptorHiLane - DescriptorLoLane + 1;
-
- if (EngineDescriptor->EngineData.EngineType == PciePortEngine) {
- if (DescriptorNumberOfLanes == 1 || DescriptorNumberOfLanes == 2 || DescriptorNumberOfLanes == 4 ||
- DescriptorNumberOfLanes == 8 || DescriptorNumberOfLanes == 16) {
- Result = TRUE;
- }
- } else if (EngineDescriptor->EngineData.EngineType == PcieDdiEngine) {
- if (DescriptorNumberOfLanes == 4 || DescriptorNumberOfLanes == 8) {
- Result = TRUE;
- }
- }
-
- GNB_DEBUG_CODE (
- if (!Result) {
- IDS_HDT_CONSOLE (PCIE_MISC, " Invalid Link width [Engine Lanes %d..%d]\n",
- DescriptorLoLane,
- DescriptorHiLane
- );
- }
- );
-
- return Result;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Helper function to dump input configuration to debug out
- *
- *
- * @param[in] ComplexDescriptor Pointer to used define complex descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-VOID
-PcieComplexConfigConfigDump (
- IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- PCIe_ENGINE_DESCRIPTOR *EngineDescriptor;
- UINTN Index;
- UINTN NumberOfEngines;
- IDS_HDT_CONSOLE (PCIE_MISC, "<---------- PCIe User Config Start------------->\n");
-
- NumberOfEngines = PcieInputParserGetNumberOfEngines (ComplexDescriptor);
- IDS_HDT_CONSOLE (PCIE_MISC, " ComplexDescriptor SocketId - %d\n NumberOfEngines - %d\n",
- ComplexDescriptor->SocketId,
- NumberOfEngines
- );
-
- for (Index = 0; Index < NumberOfEngines; Index++) {
- EngineDescriptor = PcieInputParserGetEngineDescriptor (ComplexDescriptor, Index);
- IDS_HDT_CONSOLE (PCIE_MISC, " Engine Type - %s\n",
- (EngineDescriptor->EngineData.EngineType == PciePortEngine) ? "PCIe Port" : (
- (EngineDescriptor->EngineData.EngineType == PcieDdiEngine) ? "DDI Link" : (
- (EngineDescriptor->EngineData.EngineType == PcieUnusedEngine) ? "Unused" : "Invalid"))
- );
- IDS_HDT_CONSOLE (PCIE_MISC, " Start Phy Lane - %d\n End Phy Lane - %d\n",
- EngineDescriptor->EngineData.StartLane,
- EngineDescriptor->EngineData.EndLane
- );
- if (EngineDescriptor->EngineData.EngineType == PciePortEngine) {
- IDS_HDT_CONSOLE (PCIE_MISC, " PortPresent - %d\n ChannelType - %d\n DeviceNumber - %d\n FunctionNumber - %d\n LinkSpeedCapability - %d\n LinkAspm - %d\n LinkHotplug - %d\n ResetId - %d\n" ,
- ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.PortPresent,
- ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.ChannelType,
- ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.DeviceNumber,
- ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.FunctionNumber,
- ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.LinkSpeedCapability,
- ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.LinkAspm,
- ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.LinkHotplug,
- ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.ResetId
- );
- }
- if (EngineDescriptor->EngineData.EngineType == PcieDdiEngine) {
- IDS_HDT_CONSOLE (PCIE_MISC, " ConnectorType - %d\n AuxIndex - %d\n HdpIndex - %d\n" ,
- ((PCIe_DDI_DESCRIPTOR *) EngineDescriptor)->Ddi.ConnectorType,
- ((PCIe_DDI_DESCRIPTOR *) EngineDescriptor)->Ddi.AuxIndex,
- ((PCIe_DDI_DESCRIPTOR *) EngineDescriptor)->Ddi.HdpIndex
- );
- }
- }
- IDS_HDT_CONSOLE (PCIE_MISC, "<---------- PCIe User Config End-------------->\n");
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h
deleted file mode 100644
index 0155bb3..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Procedure to map user define topology to processor configuration
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _PCIEMAPTOPOLOGY_H_
-#define _PCIEMAPTOPOLOGY_H_
-
-AGESA_STATUS
-PcieMapTopologyOnComplex (
- IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor,
- IN PCIe_COMPLEX_CONFIG *Complex,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-#endif
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/GnbPcieInitLibV1.h b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/GnbPcieInitLibV1.h
deleted file mode 100644
index b941177..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/GnbPcieInitLibV1.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe Init Library
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _PCIEINITLIBV1_H_
-#define _PCIEINITLIBV1_H_
-
-#include "PciePifServices.h"
-#include "PciePortRegAcc.h"
-#include "PciePowerMgmt.h"
-#include "PcieTimer.h"
-#include "PcieTopologyServices.h"
-#include "PcieUtilityLib.h"
-#include "PcieWrapperRegAcc.h"
-#include "PcieAspmExitLatency.h"
-#include "PcieSiliconServices.h"
-#include "PciePortServices.h"
-#include "PcieAspm.h"
-#include "PcieSbLink.h"
-#include "PciePhyServices.h"
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.c
deleted file mode 100644
index 07b4231..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.c
+++ /dev/null
@@ -1,346 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe link ASPM
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 38935 $ @e \$Date: 2010-10-01 18:45:23 -0700 (Fri, 01 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "Gnb.h"
-#include "GnbPcie.h"
-#include "OptionGnb.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1)
-#include "PcieAspmBlackList.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPM_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-extern GNB_BUILD_OPTIONS GnbBuildOptions;
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-typedef struct {
- GNB_PCI_SCAN_DATA ScanData;
- PCIE_ASPM_TYPE Aspm;
- PCI_ADDR DownstreamPort;
-} PCIE_ASPM_DATA;
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-SCAN_STATUS
-PcieAspmCallback (
- IN PCI_ADDR Device,
- IN OUT GNB_PCI_SCAN_DATA *ScanData
- );
-
-VOID
-PcieAspmEnableOnLink (
- IN PCI_ADDR Downstream,
- IN PCI_ADDR Upstream,
- IN PCIE_ASPM_TYPE Aspm,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-PCIE_ASPM_TYPE
-PcieAspmGetPmCapability (
- IN PCI_ADDR Device,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Enable PCIE Advance state power management
- *
- *
- *
- * @param[in] DownstreamPort PCI Address of the downstream port
- * @param[in] Aspm ASPM type
- * @param[in] StdHeader Standard configuration header
- * @retval AGESA_STATUS
- */
-
-VOID
-PcieLinkAspmEnable (
- IN PCI_ADDR DownstreamPort,
- IN PCIE_ASPM_TYPE Aspm,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- PCIE_ASPM_DATA PcieAspmData;
- PcieAspmData.Aspm = Aspm;
- PcieAspmData.ScanData.StdHeader = StdHeader;
- PcieAspmData.ScanData.GnbScanCallback = PcieAspmCallback;
- GnbLibPciScan (DownstreamPort, DownstreamPort, &PcieAspmData.ScanData);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Evaluate device
- *
- *
- *
- * @param[in] Device PCI Address
- * @param[in,out] ScanData Scan configuration data
- * @retval Scan Status of 0
- */
-
-SCAN_STATUS
-PcieAspmCallback (
- IN PCI_ADDR Device,
- IN OUT GNB_PCI_SCAN_DATA *ScanData
- )
-{
- SCAN_STATUS ScanStatus;
- PCIE_ASPM_DATA *PcieAspmData;
- PCIE_DEVICE_TYPE DeviceType;
- ScanStatus = SCAN_SUCCESS;
- IDS_HDT_CONSOLE (GNB_TRACE, " PcieAspmCallback for Device = %d:%d:%d\n",
- Device.Address.Bus,
- Device.Address.Device,
- Device.Address.Function
- );
- PcieAspmData = (PCIE_ASPM_DATA *) ScanData;
- ScanStatus = SCAN_SUCCESS;
- DeviceType = GnbLibGetPcieDeviceType (Device, ScanData->StdHeader);
- switch (DeviceType) {
- case PcieDeviceRootComplex:
- case PcieDeviceDownstreamPort:
- PcieAspmData->DownstreamPort = Device;
- //PcieExitLatencyData->LinkCount++;
- GnbLibPciRMW (Device.AddressValue | 0x18, AccessS3SaveWidth32, 0xffffffffull, 0x0, ScanData->StdHeader);
- GnbLibPciScanSecondaryBus (Device, &PcieAspmData->ScanData);
- //PcieExitLatencyData->LinkCount--;
- break;
- case PcieDeviceUpstreamPort:
- PcieAspmEnableOnLink (
- PcieAspmData->DownstreamPort,
- Device,
- PcieAspmData->Aspm,
- ScanData->StdHeader
- );
- GnbLibPciRMW (Device.AddressValue | 0x18, AccessS3SaveWidth32, 0xffffffffull, 0x0, ScanData->StdHeader);
- GnbLibPciScanSecondaryBus (Device, &PcieAspmData->ScanData);
- ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES;
- break;
- case PcieDeviceEndPoint:
- case PcieDeviceLegacyEndPoint:
- PcieAspmEnableOnLink (
- PcieAspmData->DownstreamPort,
- Device,
- PcieAspmData->Aspm,
- ScanData->StdHeader
- );
- ScanStatus = SCAN_SKIP_FUNCTIONS | SCAN_SKIP_DEVICES | SCAN_SKIP_BUSES;
- break;
- default:
- break;
- }
- return ScanStatus;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Set ASMP State on PCIe device function
- *
- *
- *
- * @param[in] Function PCI address of function.
- * @param[in] Aspm Aspm capability to enable
- * @param[in] StdHeader Standard configuration header
- *
- */
- /*----------------------------------------------------------------------------------------*/
-VOID
-PcieAspmEnableOnFunction (
- IN PCI_ADDR Function,
- IN PCIE_ASPM_TYPE Aspm,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 PcieCapPtr;
- PcieCapPtr = GnbLibFindPciCapability (Function.AddressValue, PCIE_CAP_ID, StdHeader);
- if (PcieCapPtr != 0) {
- GnbLibPciRMW (
- Function.AddressValue | (PcieCapPtr + PCIE_LINK_CTRL_REGISTER) ,
- AccessS3SaveWidth8,
- ~(BIT0 & BIT1),
- Aspm,
- StdHeader
- );
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Set ASMP State on all function of PCI device
- *
- *
- *
- * @param[in] Device PCI address of device.
- * @param[in] Aspm Aspm capability to enable
- * @param[in] StdHeader Standard configuration header
- *
- */
- /*----------------------------------------------------------------------------------------*/
-VOID
-PcieAspmEnableOnDevice (
- IN PCI_ADDR Device,
- IN PCIE_ASPM_TYPE Aspm,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 MaxFunc;
- UINT8 CurrentFunc;
- MaxFunc = GnbLibPciIsMultiFunctionDevice (Device.AddressValue, StdHeader) ? 7 : 0;
- for (CurrentFunc = 0; CurrentFunc <= MaxFunc; CurrentFunc++) {
- Device.Address.Function = CurrentFunc;
- if (GnbLibPciIsDevicePresent (Device.AddressValue, StdHeader)) {
- PcieAspmEnableOnFunction (Device, Aspm, StdHeader);
- }
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Enable ASPM on link
- *
- *
- *
- * @param[in] Downstream PCI Address of downstrteam port
- * @param[in] Upstream PCI Address of upstream port
- * @param[in] Aspm Aspm capability to enable
- * @param[in] StdHeader Standard configuration header
- */
-
-VOID
-PcieAspmEnableOnLink (
- IN PCI_ADDR Downstream,
- IN PCI_ADDR Upstream,
- IN PCIE_ASPM_TYPE Aspm,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- PCIe_LINK_ASPM LinkAsmp;
- PCIE_ASPM_TYPE DownstreamCap;
- PCIE_ASPM_TYPE UpstreamCap;
- LinkAsmp.DownstreamPort = Downstream;
- DownstreamCap = PcieAspmGetPmCapability (Downstream, StdHeader);
- LinkAsmp.UpstreamPort = Upstream;
- UpstreamCap = PcieAspmGetPmCapability (Upstream, StdHeader);
- LinkAsmp.DownstreamAspm = DownstreamCap & UpstreamCap & Aspm & AspmL1;
- LinkAsmp.UpstreamAspm = LinkAsmp.DownstreamAspm;
- LinkAsmp.RequestedAspm = Aspm;
- if ((UpstreamCap & Aspm & AspmL0s) != 0) {
- LinkAsmp.UpstreamAspm |= AspmL0s;
- }
- if ((DownstreamCap & Aspm & AspmL0s) != 0) {
- LinkAsmp.DownstreamAspm |= AspmL0s;
- }
- if (GnbBuildOptions.PcieAspmBlackListEnable == 1) {
- PcieAspmBlackListFeature (&LinkAsmp, StdHeader);
- }
- //AgesaPcieLinkAspm (&LinkAsmp, StdHeader);
- IDS_HDT_CONSOLE (GNB_TRACE, " Set ASPM [%d] for Device = %d:%d:%d\n",
- (LinkAsmp.UpstreamAspm) ,
- LinkAsmp.UpstreamPort.Address.Bus,
- LinkAsmp.UpstreamPort.Address.Device,
- LinkAsmp.UpstreamPort.Address.Function
- );
- IDS_HDT_CONSOLE (GNB_TRACE, " Set ASPM [%d] for Device = %d:%d:%d\n",
- (LinkAsmp.DownstreamAspm) ,
- LinkAsmp.DownstreamPort.Address.Bus,
- LinkAsmp.DownstreamPort.Address.Device,
- LinkAsmp.DownstreamPort.Address.Function
- );
- PcieAspmEnableOnDevice (Upstream, LinkAsmp.UpstreamAspm, StdHeader);
- PcieAspmEnableOnFunction (Downstream, LinkAsmp.DownstreamAspm, StdHeader);
-}
-
-
-
-/**----------------------------------------------------------------------------------------*/
-/**
- * Port/Endpoint ASMP capability
- *
- *
- *
- * @param[in] Device PCI address of downstream port
- * @param[in] StdHeader Standard configuration header
- *
- * @retval PCIE_ASPM_TYPE
- */
- /*----------------------------------------------------------------------------------------*/
-PCIE_ASPM_TYPE
-PcieAspmGetPmCapability (
- IN PCI_ADDR Device,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 PcieCapPtr;
- UINT32 Value;
- PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, StdHeader);
- if (PcieCapPtr == 0) {
- return 0;
- }
- GnbLibPciRead (
- Device.AddressValue | (PcieCapPtr + PCIE_LINK_CAP_REGISTER),
- AccessWidth32,
- &Value,
- StdHeader
- );
- return (Value >> 10) & 3;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.h b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.h
deleted file mode 100644
index 101d393..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe link ASPM
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _PCIEASPM_H_
-#define _PCIEASPM_H_
-
-VOID
-PcieLinkAspmEnable (
- IN PCI_ADDR DownstreamPort,
- IN PCIE_ASPM_TYPE Aspm,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c
deleted file mode 100644
index ecb6b43..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/**
- * @file
- *
- * PCIe link ASPM Black List
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 33827 $ @e \$Date: 2010-06-24 22:11:37 +0800 (Thu, 24 Jun 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Gnb.h"
-#include "GnbPcie.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include "PcieAspmBlackList.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMBLACKLIST_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-UINT16 AspmBrDeviceTable[] = {
- 0x1002, 0x9441, (UINT16) ~(AspmL1 | AspmL0s),
- 0x10B5, 0xFFFF, (UINT16) ~(AspmL1 | AspmL0s),
- 0x10DE, 0x0402, (UINT16) ~(AspmL1 | AspmL0s),
- 0x10DE, 0x0193, (UINT16) ~(AspmL1 | AspmL0s),
- 0x10DE, 0x0422, (UINT16) ~(AspmL1 | AspmL0s),
- 0x10DE, 0x0292, (UINT16) ~(AspmL1 | AspmL0s),
- 0x10DE, 0x00F9, (UINT16) ~(AspmL1 | AspmL0s),
- 0x10DE, 0x0141, (UINT16) ~(AspmL1 | AspmL0s),
- 0x10DE, 0x0092, (UINT16) ~(AspmL1 | AspmL0s),
- 0x10DE, 0x01D0, (UINT16) ~(AspmL1 | AspmL0s),
- 0x10DE, 0x01D1, (UINT16) ~(AspmL1 | AspmL0s),
- 0x10DE, 0x01D2, (UINT16) ~(AspmL1 | AspmL0s),
- 0x10DE, 0x01D3, (UINT16) ~(AspmL1 | AspmL0s),
- 0x10DE, 0x01D5, (UINT16) ~(AspmL1 | AspmL0s),
- 0x10DE, 0x01D7, (UINT16) ~(AspmL1 | AspmL0s),
- 0x10DE, 0x01D8, (UINT16) ~(AspmL1 | AspmL0s),
- 0x10DE, 0x01DC, (UINT16) ~(AspmL1 | AspmL0s),
- 0x10DE, 0x01DE, (UINT16) ~(AspmL1 | AspmL0s),
- 0x10DE, 0x01DF, (UINT16) ~(AspmL1 | AspmL0s),
- 0x10DE, 0x016A, (UINT16) ~(AspmL1 | AspmL0s),
- 0x10DE, 0x0392, (UINT16) ~(AspmL1 | AspmL0s),
- 0x168C, 0xFFFF, (UINT16) ~(AspmL0s),
- 0x1B4B, 0x91A3, (UINT16) ~(AspmL0s)
-};
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Pcie ASPM Black List
- *
- *
- *
- * @param[in] LinkAsmp PCie ASPM black list
- * @param[in] StdHeader Standard configuration header
- * @retval AGESA_STATUS
- */
-
-AGESA_STATUS
-PcieAspmBlackListFeature (
- IN PCIe_LINK_ASPM *LinkAsmp,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 UpstreamDeviceId;
- UINT32 DownstreamDeviceId;
- UINTN i;
- GnbLibPciRead (LinkAsmp->UpstreamPort.AddressValue, AccessWidth32, &UpstreamDeviceId, StdHeader);
- GnbLibPciRead (LinkAsmp->DownstreamPort.AddressValue, AccessWidth32, &DownstreamDeviceId, StdHeader);
- for (i = 0; i < (sizeof (AspmBrDeviceTable) / sizeof (UINT16)); i = i + 3) {
- UINT32 DeviceId;
- UINT32 VendorId;
- VendorId = AspmBrDeviceTable[i];
- DeviceId = AspmBrDeviceTable[i + 1];
- if (VendorId == (UINT16)UpstreamDeviceId || VendorId == (UINT16)DownstreamDeviceId ) {
- if (DeviceId == 0xFFFF || DeviceId == (UpstreamDeviceId >> 16) || DeviceId == (DownstreamDeviceId >> 16)) {
- LinkAsmp->UpstreamAspm &= AspmBrDeviceTable[i + 2];
- LinkAsmp->DownstreamAspm &= AspmBrDeviceTable[i + 2];
- }
- }
- }
- if ((UINT16)UpstreamDeviceId == 0x168c) {
- // Atheros (Ignore dev capability enable L1 if requested)
- LinkAsmp->UpstreamAspm = LinkAsmp->RequestedAspm & AspmL1;
- LinkAsmp->DownstreamAspm = LinkAsmp->UpstreamAspm;
- GnbLibPciRMW (LinkAsmp->UpstreamPort.AddressValue | 0x70C, AccessS3SaveWidth32, 0x0, 0x0F003F01, StdHeader);
- }
- return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.h b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.h
deleted file mode 100644
index a6cebc9..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/**
- * @file
- *
- * PCIe ASPM Black List
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 24971 $ @e \$Date: 2010-01-13 10:25:06 +0800 (Wed, 13 Jan 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _PCIEASPMBLACKLIST_H_
-#define _PCIEASPMBLACKLIST_H_
-
-///PCIe ASPM Black List
-
-AGESA_STATUS
-PcieAspmBlackListFeature (
- IN PCIe_LINK_ASPM *LinkAsmp,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c
deleted file mode 100644
index 1dffc52..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Service procedure to calculate PCIe topology segment maximum exit latency
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 38298 $ @e \$Date: 2010-09-21 07:15:32 -0700 (Tue, 21 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "Gnb.h"
-#include "GnbPcie.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1)
-#include "Filecode.h"
-#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMEXITLATENCY_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-typedef struct {
- GNB_PCI_SCAN_DATA ScanData;
- PCIe_ASPM_LATENCY_INFO *AspmLatencyInfo;
- PCI_ADDR DownstreamPort;
- UINT8 LinkCount;
-} PCIE_EXIT_LATENCY_DATA;
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-SCAN_STATUS
-PcieAspmGetMaxExitLatencyCallback (
- IN PCI_ADDR Device,
- IN OUT GNB_PCI_SCAN_DATA *ScanData
- );
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Determine ASPM L-state maximum exit latency for PCIe segment
- *
- * Scan through all link in segment to determine maxim exit latency requirement by EPs.
- *
- * @param[in] DownstreamPort PCI address of PCIe port
- * @param[out] AspmLatencyInfo Latency info
- * @param[in] StdHeader Standard configuration header
- *
- */
-
-VOID
-PcieAspmGetMaxExitLatency (
- IN PCI_ADDR DownstreamPort,
- OUT PCIe_ASPM_LATENCY_INFO *AspmLatencyInfo,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- PCIE_EXIT_LATENCY_DATA PcieExitLatencyData;
- PcieExitLatencyData.AspmLatencyInfo = AspmLatencyInfo;
- PcieExitLatencyData.ScanData.StdHeader = StdHeader;
- PcieExitLatencyData.LinkCount = 0;
- PcieExitLatencyData.ScanData.GnbScanCallback = PcieAspmGetMaxExitLatencyCallback;
- GnbLibPciScan (DownstreamPort, DownstreamPort, &PcieExitLatencyData.ScanData);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Evaluate device
- *
- *
- *
- * @param[in] Device PCI Address
- * @param[in,out] ScanData Scan configuration data
- * @retval Scan Status of 0
- */
-
-SCAN_STATUS
-PcieAspmGetMaxExitLatencyCallback (
- IN PCI_ADDR Device,
- IN OUT GNB_PCI_SCAN_DATA *ScanData
- )
-{
- SCAN_STATUS ScanStatus;
- PCIE_EXIT_LATENCY_DATA *PcieExitLatencyData;
- PCIE_DEVICE_TYPE DeviceType;
- UINT32 Value;
- UINT8 PcieCapPtr;
- UINT8 L1AcceptableLatency;
-
- PcieExitLatencyData = (PCIE_EXIT_LATENCY_DATA*) ScanData;
- ScanStatus = SCAN_SUCCESS;
- DeviceType = GnbLibGetPcieDeviceType (Device, ScanData->StdHeader);
- IDS_HDT_CONSOLE (GNB_TRACE, " PcieAspmGetMaxExitLatencyCallback for Device = %d:%d:%d\n",
- Device.Address.Bus,
- Device.Address.Device,
- Device.Address.Function
- );
- switch (DeviceType) {
- case PcieDeviceRootComplex:
- case PcieDeviceDownstreamPort:
- PcieExitLatencyData->DownstreamPort = Device;
- PcieExitLatencyData->LinkCount++;
- GnbLibPciScanSecondaryBus (Device, &PcieExitLatencyData->ScanData);
- PcieExitLatencyData->LinkCount--;
- break;
- case PcieDeviceUpstreamPort:
- GnbLibPciScanSecondaryBus (Device, &PcieExitLatencyData->ScanData);
- break;
- case PcieDeviceEndPoint:
- case PcieDeviceLegacyEndPoint:
- PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, ScanData->StdHeader);
- ASSERT (PcieCapPtr != 0);
- GnbLibPciRead (
- Device.AddressValue | (PcieCapPtr + PCIE_LINK_CAP_REGISTER),
- AccessWidth32,
- &Value,
- ScanData->StdHeader
- );
- if ((Value & PCIE_ASPM_L1_SUPPORT_CAP) != 0) {
- GnbLibPciRead (
- Device.AddressValue | (PcieCapPtr + PCIE_DEVICE_CAP_REGISTER),
- AccessWidth32,
- &Value,
- ScanData->StdHeader
- );
- L1AcceptableLatency = (UINT8) (1 << ((Value >> 9) & 0x7));
- if (PcieExitLatencyData->LinkCount > 1) {
- L1AcceptableLatency = L1AcceptableLatency + PcieExitLatencyData->LinkCount;
- }
- if (PcieExitLatencyData->AspmLatencyInfo->MaxL1ExitLatency < L1AcceptableLatency) {
- PcieExitLatencyData->AspmLatencyInfo->MaxL1ExitLatency = L1AcceptableLatency;
- }
- IDS_HDT_CONSOLE (PCIE_MISC, " Device max exit latency L1 - %d us\n",
- L1AcceptableLatency
- );
- }
- break;
- default:
- break;
- }
- return SCAN_SUCCESS;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.h b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.h
deleted file mode 100644
index 5099c0f..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Service procedure to calculate PCIe topology segment maximum exit latency
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _PCIEASPMEXITLATENCY_H_
-#define _PCIEASPMEXITLATENCY_H_
-
-VOID
-PcieAspmGetMaxExitLatency (
- IN PCI_ADDR DownstreamPort,
- OUT PCIe_ASPM_LATENCY_INFO *AspmLatencyInfo,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c
deleted file mode 100644
index 3fbd2f4..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c
+++ /dev/null
@@ -1,197 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe PIF initialization routine
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 38931 $ @e \$Date: 2010-10-01 15:50:05 -0700 (Fri, 01 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "amdlib.h"
-#include "Gnb.h"
-#include "GnbPcie.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1)
-#include "GnbRegistersON.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPHYSERVICES_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-#define MAX_NUM_PHYs 2
-#define MAX_NUM_LANE_PER_PHY 8
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * PHY lane ganging
- *
- *
- *
- * @param[out] Wrapper Pointer to internal configuration data area
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-VOID
-PciePhyApplyGanging (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- PCIe_ENGINE_CONFIG *EngineList;
- UINT8 GangMatrix [MAX_NUM_PHYs][MAX_NUM_LANE_PER_PHY];
- UINT8 MasterMatrix [MAX_NUM_PHYs][MAX_NUM_LANE_PER_PHY];
- UINT16 LoPhylane;
- UINT16 HiPhylane;
- UINT8 Phy;
- UINT16 Lane;
- UINT16 PhyLinkWidth;
- IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyApplyGanging Enter\n");
- LibAmdMemFill (GangMatrix, 0, sizeof (GangMatrix), GnbLibGetHeader (Pcie));
- LibAmdMemFill (MasterMatrix, 0, sizeof (MasterMatrix), GnbLibGetHeader (Pcie));
- EngineList = PcieWrapperGetEngineList (Wrapper);
- while (EngineList != NULL) {
- if (PcieLibIsEngineAllocated (EngineList)) {
- HiPhylane = PcieUtilGetHiPhyLane (EngineList) - Wrapper->StartPhyLane;
- LoPhylane = PcieUtilGetLoPhyLane (EngineList) - Wrapper->StartPhyLane;
- PhyLinkWidth = HiPhylane - LoPhylane + 1;
-
- if (PhyLinkWidth >= 8) {
- for (Lane = LoPhylane; Lane <= HiPhylane; Lane++) {
- ((UINT8 *) GangMatrix)[Lane] = 1;
- }
- } else {
- if (PhyLinkWidth > 0 && PhyLinkWidth < 4) {
- for (Lane = (LoPhylane / 4) * 4; Lane < (((LoPhylane / 4) * 4) + 4) ; Lane++) {
- ((UINT8 *) MasterMatrix)[Lane] = 1;
- }
- }
- }
- }
- EngineList = PcieLibGetNextDescriptor (EngineList);
- }
- for (Phy = 0; Phy < Wrapper->NumberOfPIFs; Phy++) {
- for (Lane = 0; Lane < MAX_NUM_LANE_PER_PHY; Lane++) {
- D0F0xE4_PHY_6005_STRUCT D0F0xE4_PHY_6005;
- D0F0xE4_PHY_6005.Value = PcieRegisterRead (
- Wrapper,
- PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_6005_ADDRESS + Lane * 0x80),
- Pcie
- );
- D0F0xE4_PHY_6005.Field.GangedModeEn = GangMatrix [Phy][Lane];
- D0F0xE4_PHY_6005.Field.IsOwnMstr = MasterMatrix [Phy][Lane];
- PcieRegisterWrite (
- Wrapper,
- PHY_SPACE (Wrapper->WrapId, Phy, D0F0xE4_PHY_6005_ADDRESS + Lane * 0x80),
- D0F0xE4_PHY_6005.Value,
- FALSE,
- Pcie
- );
- }
- }
- IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyApplyGanging Exit\n");
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Point "virtual" PLL clock picker away from PCIe
- *
- *
- *
- * @param[in] Wrapper Pointer to internal configuration data area
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-VOID
-PciePhyAvertClockPickers (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT32 DdiLanes;
- UINT8 Nibble;
- IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyAvertClockPickers Enter\n");
- DdiLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_DDI_ALLOCATED, 0, Wrapper, Pcie);
- for (Nibble = 0; Nibble < 4; Nibble++) {
- if (DdiLanes & (0xf << (Nibble * 4))) {
- PcieRegisterRMW (
- Wrapper,
- PHY_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PHY_0009_ADDRESS + (Nibble & 0x1)),
- D0F0xE4_PHY_0009_PCIePllSel_MASK,
- 0x0 << D0F0xE4_PHY_0009_PCIePllSel_OFFSET,
- FALSE,
- Pcie
- );
- PcieRegisterRMW (
- Wrapper,
- PHY_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PHY_000B_ADDRESS + (Nibble & 0x1)),
- D0F0xE4_PHY_000B_MargPktSbiEn_MASK | D0F0xE4_PHY_000B_PcieModeSbiEn_MASK,
- (0x0 << D0F0xE4_PHY_000B_MargPktSbiEn_OFFSET) | (0x0 << D0F0xE4_PHY_000B_PcieModeSbiEn_OFFSET),
- FALSE,
- Pcie
- );
- }
- }
- IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyAvertClockPickers Exit\n");
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.h b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.h
deleted file mode 100644
index 0f28e29..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe PIF initialization routine
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _PCIEPHYSERVICES_H_
-#define _PCIEPHYSERVICES_H_
-
-VOID
-PciePhyApplyGanging (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PciePhyAvertClockPickers (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c
deleted file mode 100644
index 717a80a..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c
+++ /dev/null
@@ -1,558 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe PIF initialization routine
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 38931 $ @e \$Date: 2010-10-01 15:50:05 -0700 (Fri, 01 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "amdlib.h"
-#include "Gnb.h"
-#include "GnbPcie.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1)
-#include "GnbRegistersON.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPIFSERVICES_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-#define PIF_GANG_0to1 0x1
-#define PIF_GANG_2to3 (0x1 << 1)
-#define PIF_GANG_4to5 (0x1 << 2)
-#define PIF_GANG_6to7 (0x1 << 3)
-#define PIF_GANG_0to3 (0x1 << 4)
-#define PIF_GANG_4to7 (0x1 << 8)
-#define PIF_GANG_0to7 (0x1 << 9)
-#define PIF_GANG_ALL (0x1 << 25)
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Apply PIF ganging for all lanes for given wrapper
- *
- *
- *
- * @param[in] Wrapper Pointer to Wrapper config descriptor
- * @param[in] Pcie Pointer to PICe configuration data area
- */
-
-
-VOID
-PciePifApplyGanging (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- PCIe_ENGINE_CONFIG *EngineList;
- UINT32 LaneBitmap;
- UINT8 Pif;
- D0F0xE4_PIF_0011_STRUCT D0F0xE4_PIF_0011[2];
- IDS_HDT_CONSOLE (GNB_TRACE, "PciePifApplyGanging Enter\n");
- LibAmdMemFill (&D0F0xE4_PIF_0011, 0, sizeof (D0F0xE4_PIF_0011), GnbLibGetHeader (Pcie));
- EngineList = PcieWrapperGetEngineList (Wrapper);
- while (EngineList != NULL) {
- if (PcieLibIsEngineAllocated (EngineList)) {
- LaneBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_ALLOCATED, 0, EngineList, Pcie);
- switch (LaneBitmap) {
- case 0x0003:
- D0F0xE4_PIF_0011[0].Field.X2Lane10 = 0x1;
- break;
- case 0x000c:
- D0F0xE4_PIF_0011[0].Field.X2Lane32 = 0x1;
- break;
- case 0x0030:
- D0F0xE4_PIF_0011[0].Field.X2Lane54 = 0x1;
- break;
- case 0x00c0:
- D0F0xE4_PIF_0011[0].Field.X2Lane76 = 0x1;
- break;
- case 0x000f:
- D0F0xE4_PIF_0011[0].Field.X4Lane30 = 0x1;
- break;
- case 0x00f0:
- D0F0xE4_PIF_0011[0].Field.X4Lane74 = 0x1;
- break;
- case 0x00ff:
- D0F0xE4_PIF_0011[0].Field.X8Lane70 = 0x1;
- break;
- case 0x0300:
- D0F0xE4_PIF_0011[1].Field.X2Lane10 = 1;
- break;
- case 0x0c00:
- D0F0xE4_PIF_0011[1].Field.X2Lane32 = 0x1;
- break;
- case 0x3000:
- D0F0xE4_PIF_0011[1].Field.X2Lane54 = 0x1;
- break;
- case 0xc000:
- D0F0xE4_PIF_0011[1].Field.X2Lane76 = 0x1;
- break;
- case 0x0f00:
- D0F0xE4_PIF_0011[1].Field.X4Lane30 = 0x1;
- break;
- case 0xf000:
- D0F0xE4_PIF_0011[1].Field.X4Lane74 = 0x1;
- break;
- case 0xff00:
- D0F0xE4_PIF_0011[1].Field.X8Lane70 = 0x1;
- break;
- case 0xffff:
- D0F0xE4_PIF_0011[0].Field.MultiPif = 0x1;
- D0F0xE4_PIF_0011[1].Field.MultiPif = 0x1;
- break;
- default:
- break;
- }
- }
- EngineList = PcieLibGetNextDescriptor (EngineList);
- }
- for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
- PcieRegisterWrite (
- Wrapper,
- PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0011_ADDRESS),
- D0F0xE4_PIF_0011[Pif].Value,
- FALSE,
- Pcie
- );
- }
- IDS_HDT_CONSOLE (GNB_TRACE, "PciePifApplyGanging Exit\n");
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * PLL powerdown
- *
- *
- * @param[in] LaneBitmap Power down PLL for these lanes
- * @param[in] Wrapper Pointer to Wrapper config descriptor
- * @param[in] Pcie Pointer to PICe configuration data area
- */
-
-VOID
-PciePifPllPowerDown (
- IN UINT32 LaneBitmap,
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT8 Nibble;
- UINT16 NibbleBitmap;
- D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012;
- IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllPowerDown Enter\n");
- for (Nibble = 0; Nibble < 4; Nibble++) {
- NibbleBitmap = (0xF << (Nibble * 4));
- if ((LaneBitmap & NibbleBitmap) == NibbleBitmap) {
- D0F0xE4_PIF_0012.Value = PcieRegisterRead (
- Wrapper,
- PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)),
- Pcie
- );
-
- D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff;
- D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff;
- D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateOff;
- D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateOff;
- PcieRegisterWrite (
- Wrapper,
- PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)),
- D0F0xE4_PIF_0012.Value,
- TRUE,
- Pcie
- );
- }
- }
- IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllPowerDown Exit\n");
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * PLL init for DDI
- *
- *
- *
- * @param[in] Wrapper Pointer to Wrapper config descriptor
- * @param[in] Pcie Pointer to PICe configuration data area
- */
-
-VOID
-PciePifPllInitForDdi (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT8 Nibble;
- UINT32 LaneBitmap;
- D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012;
- IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllInitForDdi Enter\n");
- LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_DDI_ALLOCATED, 0, Wrapper, Pcie);
- for (Nibble = 0; Nibble < 4; Nibble++) {
- if (LaneBitmap & (0xF << (Nibble * 4))) {
- D0F0xE4_PIF_0012.Value = PcieRegisterRead (
- Wrapper,
- PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)),
- Pcie
- );
-
- D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff;
- D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff;
- D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x2;
- PcieRegisterWrite (
- Wrapper,
- PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)),
- D0F0xE4_PIF_0012.Value,
- FALSE,
- Pcie
- );
- }
- }
- IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllInitForDdi Exit\n");
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Poll for on PIF to indicate action completion
- *
- *
- *
- * @param[in] Wrapper Pointer to wrapper config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-VOID
-PciePollPifForCompeletion (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT32 TimeStamp;
- UINT8 Pif;
- D0F0xE4_PIF_0015_STRUCT D0F0xE4_PIF_0015;
- TimeStamp = PcieTimerGetTimeStamp (Pcie);
- for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
- do {
- D0F0xE4_PIF_0015.Value = PcieRegisterRead (
- Wrapper,
- PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0015_ADDRESS),
- Pcie
- );
- if (TIMESTAMPS_DELTA (TimeStamp, PcieTimerGetTimeStamp (Pcie)) > 100) {
- break;
- }
- } while ((D0F0xE4_PIF_0015.Value & 0xff) != 0xff);
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Disable fifo reset
- *
- *
- *
- * @param[in] Wrapper Pointer to Wrapper config descriptor
- * @param[in] Pcie Pointer to PICe configuration data area
- */
-
-
-VOID
-PciePifDisableFifoReset (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT8 Pif;
- for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
- PcieRegisterWriteField (
- Wrapper,
- PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS),
- D0F0xE4_PIF_0010_RxDetectFifoResetMode_OFFSET,
- D0F0xE4_PIF_0010_RxDetectFifoResetMode_WIDTH,
- 0,
- FALSE,
- Pcie
- );
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Program LS2 exit time
- *
- *
- *
- * @param[in] Wrapper Pointer to wrapper config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-
-VOID
-PciePifSetLs2ExitTime (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT8 Pif;
- IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetLs2ExitTime Enter\n");
- for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
- PcieRegisterWriteField (
- Wrapper,
- PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS),
- D0F0xE4_PIF_0010_Ls2ExitTime_OFFSET,
- D0F0xE4_PIF_0010_Ls2ExitTime_WIDTH,
- 0x0,
- FALSE,
- Pcie
- );
- }
- IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetLs2ExitTime Exit\n");
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Set PLL mode for L1
- *
- *
- * @param[in] LaneBitmap Power down PLL for these lanes
- * @param[in] Wrapper Pointer to Wrapper config descriptor
- * @param[in] Pcie Pointer to PICe configuration data area
- */
-
-VOID
-PciePifSetPllModeForL1 (
- IN UINT32 LaneBitmap,
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT8 Nibble;
- D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012;
- for (Nibble = 0; Nibble < 4; Nibble++) {
- if (LaneBitmap & (0xF << (Nibble * 4))) {
- D0F0xE4_PIF_0012.Value = PcieRegisterRead (
- Wrapper,
- PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)),
- Pcie
- );
- D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateLS2;
- D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateLS2;
- D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff;
- D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff;
- D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x0;
- PcieRegisterWrite (
- Wrapper,
- PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)),
- D0F0xE4_PIF_0012.Value,
- TRUE,
- Pcie
- );
- }
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Program receiver detection power mode
- *
- *
- *
- * @param[in] Wrapper Pointer to wrapper config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-
-VOID
-PciePifSetRxDetectPowerMode (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT8 Pif;
- IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetRxDetectPowerMode Enter\n");
- for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
- PcieRegisterWriteField (
- Wrapper,
- PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS),
- D0F0xE4_PIF_0010_RxDetectTxPwrMode_OFFSET,
- D0F0xE4_PIF_0010_RxDetectTxPwrMode_WIDTH,
- 0x1,
- FALSE,
- Pcie
- );
- }
- IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetRxDetectPowerMode Enter\n");
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Pll ramp up time
- *
- *
- *
- * @param[in] Rampup Ramp up time
- * @param[in] Wrapper Pointer to wrapper config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-VOID
-PciePifSetPllRampTime (
- IN PCIE_PLL_RAMPUP_TIME Rampup,
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT8 Pif;
- D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012;
- D0F0xE4_PIF_0013_STRUCT D0F0xE4_PIF_0013;
- D0F0xE4_PIF_0010_STRUCT D0F0xE4_PIF_0010;
- for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
- D0F0xE4_PIF_0012.Value = PcieRegisterRead (
- Wrapper,
- PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS),
- Pcie
- );
- D0F0xE4_PIF_0013.Value = PcieRegisterRead (
- Wrapper,
- PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS),
- Pcie
- );
- D0F0xE4_PIF_0010.Value = PcieRegisterRead (
- Wrapper,
- PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS),
- Pcie
- );
- if (Rampup == NormalRampup) {
- D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x1;
- D0F0xE4_PIF_0013.Field.PllRampUpTime = 0x1;
- D0F0xE4_PIF_0010.Field.Ls2ExitTime = 0x0;
- } else {
- D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x3;
- D0F0xE4_PIF_0013.Field.PllRampUpTime = 0x3;
- D0F0xE4_PIF_0010.Field.Ls2ExitTime = 0x6;
- }
- PcieRegisterWrite (
- Wrapper,
- PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS),
- D0F0xE4_PIF_0012.Value,
- FALSE,
- Pcie
- );
- PcieRegisterWrite (
- Wrapper,
- PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS),
- D0F0xE4_PIF_0013.Value,
- FALSE,
- Pcie
- );
- PcieRegisterWrite (
- Wrapper,
- PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS),
- D0F0xE4_PIF_0010.Value,
- FALSE,
- Pcie
- );
- }
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Power down PIFs
- *
- *
- *
- * @param[in] Control Power up or Power down control
- * @param[in] Wrapper Pointer to wrapper config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-VOID
-PciePifPllPowerControl (
- IN PCIE_PIF_POWER_CONTROL Control,
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT8 Pif;
- UINT8 PllPowerStateInOff;
- PllPowerStateInOff = (Control == PowerDownPifs) ? PifPowerStateOff : PifPowerStateL0;
- for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
- PcieRegisterWriteField (
- Wrapper,
- PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS),
- D0F0xE4_PIF_0012_PllPowerStateInOff_OFFSET,
- D0F0xE4_PIF_0012_PllPowerStateInOff_WIDTH,
- PllPowerStateInOff,
- FALSE,
- Pcie
- );
- PcieRegisterWriteField (
- Wrapper,
- PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS),
- D0F0xE4_PIF_0013_PllPowerStateInOff_OFFSET,
- D0F0xE4_PIF_0013_PllPowerStateInOff_WIDTH,
- PllPowerStateInOff,
- FALSE,
- Pcie
- );
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.h b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.h
deleted file mode 100644
index a69ed41..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe PIF initialization routine
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _PCIEPIFSERVICES_H_
-#define _PCIEPIFSERVICES_H_
-
-VOID
-PciePifApplyGanging (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PciePifPllPowerDown (
- IN UINT32 LaneBitmap,
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PciePifPllInitForDdi (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PciePollPifForCompeletion (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PciePifDisableFifoReset (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PciePifSetLs2ExitTime (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PciePifSetRxDetectPowerMode (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PciePifSetPllRampTime (
- IN PCIE_PLL_RAMPUP_TIME Rampup,
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PciePifPllPowerControl (
- IN PCIE_PIF_POWER_CONTROL Control,
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c
deleted file mode 100644
index 491e148..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c
+++ /dev/null
@@ -1,230 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Supporting services to access PCIe port indirect register
- * space.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "Gnb.h"
-#include "GnbPcie.h"
-#include "GnbPcieFamServices.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include "Filecode.h"
-#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTREGACC_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Read PCIe port indirect register.
- *
- * Support for unify register access through index/data pair on PCIe port
- *
- * @param[in] Engine Pointer to Engine descriptor for this port
- * @param[in] Address Register address
- * @param[in] Pcie Pointer to internal configuration data area
- * @retval Register Value
- */
-
-UINT32
-PciePortRegisterRead (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN UINT16 Address,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT32 Value;
- GnbLibPciWrite (Engine->Type.Port.Address.AddressValue | 0xE0, AccessWidth32, &Address, GnbLibGetHeader (Pcie));
- GnbLibPciRead (Engine->Type.Port.Address.AddressValue | 0xE4, AccessWidth32, &Value, GnbLibGetHeader (Pcie));
- return Value;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Write PCIe Port Indirect register.
- *
- * Support for unify register access through index/data pair on GNB
- *
- * @param[in] Engine Pointer to Engine descriptor for this port
- * @param[in] Address Register address
- * @param[in] Value New register value
- * @param[in] S3Save Save for S3 flag
- * @param[in] Pcie Pointer to internal configuration data area
- */
-VOID
-PciePortRegisterWrite (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN UINT16 Address,
- IN UINT32 Value,
- IN BOOLEAN S3Save,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- ASSERT (S3Save == TRUE || S3Save == FALSE);
-
- IDS_HDT_CONSOLE (PCIE_PORTREG_TRACE, " *WR PCIEIND_P (%d:%d:%d):0x%04x = 0x%08x\n",
- Engine->Type.Port.Address.Address.Bus,
- Engine->Type.Port.Address.Address.Device,
- Engine->Type.Port.Address.Address.Function,
- Address,
- Value
- );
- GnbLibPciWrite (Engine->Type.Port.Address.AddressValue | 0xE0, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Address, GnbLibGetHeader (Pcie));
- GnbLibPciWrite (Engine->Type.Port.Address.AddressValue | 0xE4, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Value, GnbLibGetHeader (Pcie));
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Write PCIe Port Indirect register field.
- *
- * Support for unify register access through index/data pair on GNB
- *
- * @param[in] Engine Pointer to Engine descriptor for this port
- * @param[in] Address Register address
- * @param[in] FieldOffset Field offset
- * @param[in] FieldWidth Field width
- * @param[in] S3Save Save for S3 flag
- * @param[in] Value New register value
- * @param[in] Pcie Pointer to internal configuration data area
- */
-
-VOID
-PciePortRegisterWriteField (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN UINT16 Address,
- IN UINT8 FieldOffset,
- IN UINT8 FieldWidth,
- IN UINT32 Value,
- IN BOOLEAN S3Save,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT32 Data;
- UINT32 Mask;
- Data = PciePortRegisterRead (Engine, Address, Pcie);
- Mask = (1 << FieldWidth) - 1;
- Value &= Mask;
- Data &= (~(Mask << FieldOffset));
- PciePortRegisterWrite (Engine, Address, Data | (Value << FieldOffset), S3Save, Pcie);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Write PCIe Port Indirect register field.
- *
- * Support for unify register access through index/data pair on GNB
- *
- * @param[in] Engine Pointer to Engine descriptor for this port
- * @param[in] Address Register address
- * @param[in] FieldOffset Field offset
- * @param[in] FieldWidth Field width
- * @param[in] Pcie Pointer to internal configuration data area
- * @retval Register Field Value.
- */
-
-UINT32
-PciePortRegisterReadField (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN UINT16 Address,
- IN UINT8 FieldOffset,
- IN UINT8 FieldWidth,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT32 Value;
- Value = PciePortRegisterRead (Engine, Address, Pcie);
- Value = (Value >> FieldOffset) & ((1 << FieldWidth) - 1);
- return Value;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Read/Modify/Write PCIe port register.
- *
- * Support for unify register access through index/data pair on GNB
- *
- * @param[in] Engine Pointer to Engine descriptor for this port
- * @param[in] Address Register address
- * @param[in] AndMask Value & (~AndMask)
- * @param[in] OrMask Value | OrMask
- * @param[in] S3Save Save register for S3 (True/False)
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-
-VOID
-PciePortRegisterRMW (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN UINT16 Address,
- IN UINT32 AndMask,
- IN UINT32 OrMask,
- IN BOOLEAN S3Save,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT32 Value;
- Value = PciePortRegisterRead (Engine, Address, Pcie);
- Value = (Value & (~AndMask)) | OrMask;
- PciePortRegisterWrite (Engine, Address, Value, S3Save, Pcie);
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.h b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.h
deleted file mode 100644
index 244e7b5..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Supporting services to access PCIe port indirect register space.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _PCIEPORTREGACC_H_
-#define _PCIEPORTREGACC_H_
-
-UINT32
-PciePortRegisterRead (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN UINT16 Address,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PciePortRegisterWrite (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN UINT16 Address,
- IN UINT32 Value,
- IN BOOLEAN S3Save,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PciePortRegisterWriteField (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN UINT16 Address,
- IN UINT8 FieldOffset,
- IN UINT8 FieldWidth,
- IN UINT32 Value,
- IN BOOLEAN S3Save,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-UINT32
-PciePortRegisterReadField (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN UINT16 Address,
- IN UINT8 FieldOffset,
- IN UINT8 FieldWidth,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PciePortRegisterRMW (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN UINT16 Address,
- IN UINT32 AndMask,
- IN UINT32 OrMask,
- IN BOOLEAN S3Save,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c
deleted file mode 100644
index b2c490f..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c
+++ /dev/null
@@ -1,406 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe port initialization service procedure
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 38931 $ @e \$Date: 2010-10-01 15:50:05 -0700 (Fri, 01 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "amdlib.h"
-#include "Gnb.h"
-#include "GnbPcie.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1)
-#include "GnbRegistersON.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTSERVICES_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Set completion timeout
- *
- *
- *
- * @param[in] Engine Pointer to engine config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-
-VOID
-PcieCompletionTimeout (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- GnbLibPciRMW (
- Engine->Type.Port.Address.AddressValue | DxF0x80_ADDRESS,
- AccessWidth32,
- 0xffffffff,
- 0x6 << DxF0x80_CplTimeoutValue_OFFSET,
- GnbLibGetHeader (Pcie)
- );
- if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) {
- PciePortRegisterWriteField (
- Engine,
- DxF0xE4_x20_ADDRESS,
- DxF0xE4_x20_TxFlushTlpDis_OFFSET,
- DxF0xE4_x20_TxFlushTlpDis_WIDTH,
- 0x0,
- TRUE,
- Pcie
- );
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init hotplug port
- *
- *
- *
- * @param[in] Engine Pointer to engine config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-
-VOID
-PcieLinkInitHotplug (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- DxF0xE4_xB5_STRUCT DxF0xE4_xB5;
- if ((Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced) || (Engine->Type.Port.PortData.LinkHotplug == HotplugInboard)) {
- DxF0xE4_xB5.Value = PciePortRegisterRead (Engine, DxF0xE4_xB5_ADDRESS, Pcie);
- DxF0xE4_xB5.Field.LcEhpRxPhyCmd = 0x3;
- DxF0xE4_xB5.Field.LcEhpTxPhyCmd = 0x3;
- DxF0xE4_xB5.Field.LcEnhancedHotPlugEn = 0x1;
- PciePortRegisterWrite (
- Engine,
- DxF0xE4_xB5_ADDRESS,
- DxF0xE4_xB5.Value,
- TRUE,
- Pcie
- );
- PcieRegisterWriteField (
- PcieEngineGetParentWrapper (Engine),
- CORE_SPACE (Engine->Type.Port.CoreId, 0x10),
- 1,
- 3,
- 0x5,
- TRUE,
- Pcie
- );
- PcieRegisterWriteField (
- PcieEngineGetParentWrapper (Engine),
- WRAP_SPACE (PcieEngineGetParentWrapper (Engine)->WrapId, D0F0xE4_WRAP_8011_ADDRESS),
- D0F0xE4_WRAP_8011_RcvrDetClkEnable_OFFSET,
- D0F0xE4_WRAP_8011_RcvrDetClkEnable_WIDTH,
- 0x1,
- TRUE,
- Pcie
- );
- }
- if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) {
- GnbLibPciRMW (
- Engine->Type.Port.Address.AddressValue | DxF0x6C_ADDRESS,
- AccessS3SaveWidth32,
- 0xffffffff,
- 1 << DxF0x6C_HotplugCapable_OFFSET,
- GnbLibGetHeader (Pcie)
- );
- PciePortRegisterWriteField (
- Engine,
- DxF0xE4_x20_ADDRESS,
- DxF0xE4_x20_TxFlushTlpDis_OFFSET,
- DxF0xE4_x20_TxFlushTlpDis_WIDTH,
- 0x0,
- TRUE,
- Pcie
- );
- PciePortRegisterWriteField (
- Engine,
- DxF0xE4_x70_ADDRESS,
- DxF0xE4_x70_RxRcbCplTimeoutMode_OFFSET,
- DxF0xE4_x70_RxRcbCplTimeoutMode_WIDTH,
- 0x1,
- FALSE,
- Pcie
- );
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Set misc slot capability
- *
- *
- *
- * @param[in] Engine Pointer to engine config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-
-VOID
-PcieLinkSetSlotCap (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- GnbLibPciRMW (
- Engine->Type.Port.Address.AddressValue | DxF0x58_ADDRESS,
- AccessWidth32,
- 0xffffffff,
- 1 << DxF0x58_SlotImplemented_OFFSET,
- GnbLibGetHeader (Pcie)
- );
- GnbLibPciRMW (
- Engine->Type.Port.Address.AddressValue | DxF0x3C_ADDRESS,
- AccessWidth32,
- 0xffffffff,
- 1 << DxF0x3C_IntPin_OFFSET,
- GnbLibGetHeader (Pcie)
- );
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Safe mode to force link advertize Gen1 only capability in TS
- *
- *
- *
- * @param[in] Engine Pointer to engine config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-
-VOID
-PcieLinkSafeMode (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- Engine->Type.Port.PortData.LinkSpeedCapability = PcieGen1;
- PcieSetLinkSpeedCap (PcieGen1, Engine, Pcie);
- PciePortRegisterRMW (
- Engine,
- DxF0xE4_xA2_ADDRESS,
- DxF0xE4_xA2_LcUpconfigureDis_MASK,
- (1 << DxF0xE4_xA2_LcUpconfigureDis_OFFSET),
- FALSE,
- Pcie
- );
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Set current link speed
- *
- *
- * @param[in] Engine Pointer to engine configuration descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-VOID
-PcieSetLinkWidthCap (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- PciePortRegisterRMW (
- Engine,
- DxF0xE4_xA2_ADDRESS,
- DxF0xE4_xA2_LcUpconfigureDis_MASK,
- 0,
- FALSE,
- Pcie
- );
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Set current link speed
- *
- *
- * @param[in] LinkSpeedCapability Link Speed Capability
- * @param[in] Engine Pointer to engine configuration descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-VOID
-PcieSetLinkSpeedCap (
- IN PCIE_LINK_SPEED_CAP LinkSpeedCapability,
- IN PCIe_ENGINE_CONFIG *Engine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- DxF0xE4_xA4_STRUCT DxF0xE4_xA4;
- DxF0xE4_xC0_STRUCT DxF0xE4_xC0;
- DxF0x88_STRUCT DxF0x88;
- GnbLibPciRead (
- Engine->Type.Port.Address.AddressValue | DxF0x88_ADDRESS,
- AccessWidth32,
- &DxF0x88.Value,
- GnbLibGetHeader (Pcie)
- );
- DxF0xE4_xA4.Value = PciePortRegisterRead (
- Engine,
- DxF0xE4_xA4_ADDRESS,
- Pcie
- );
- DxF0xE4_xC0.Value = PciePortRegisterRead (
- Engine,
- DxF0xE4_xC0_ADDRESS,
- Pcie
- );
-
- switch (LinkSpeedCapability) {
- case PcieGen2:
- DxF0xE4_xA4.Field.LcGen2EnStrap = 0x1;
- DxF0xE4_xA4.Field.LcMultUpstreamAutoSpdChngEn = 0x1;
- DxF0xE4_xC0.Field.StrapAutoRcSpeedNegotiationDis = 0x0;
- DxF0x88.Field.TargetLinkSpeed = 0x2;
- DxF0x88.Field.HwAutonomousSpeedDisable = 0x0;
- break;
- case PcieGen1:
- DxF0xE4_xA4.Field.LcGen2EnStrap = 0x0;
- DxF0xE4_xA4.Field.LcMultUpstreamAutoSpdChngEn = 0x0;
- DxF0xE4_xC0.Field.StrapAutoRcSpeedNegotiationDis = 0x1;
- DxF0x88.Field.TargetLinkSpeed = 0x1;
- DxF0x88.Field.HwAutonomousSpeedDisable = 0x1;
- PcieRegisterWriteField (
- PcieEngineGetParentWrapper (Engine),
- WRAP_SPACE (PcieEngineGetParentWrapper (Engine)->WrapId, D0F0xE4_WRAP_0803_ADDRESS + 0x100 * Engine->Type.Port.PortId),
- D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_OFFSET,
- D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_WIDTH,
- 0,
- FALSE,
- Pcie
- );
- break;
- default:
- ASSERT (FALSE);
- break;
- }
- PciePortRegisterWrite (
- Engine,
- DxF0xE4_xA4_ADDRESS,
- DxF0xE4_xA4.Value,
- FALSE,
- Pcie
- );
- PciePortRegisterWrite (
- Engine,
- DxF0xE4_xC0_ADDRESS,
- DxF0xE4_xC0.Value,
- FALSE,
- Pcie
- );
- GnbLibPciWrite (
- Engine->Type.Port.Address.AddressValue | DxF0x88_ADDRESS,
- AccessWidth32,
- &DxF0x88.Value,
- GnbLibGetHeader (Pcie)
- );
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Force compliance
- *
- *
- *
- * @param[in] Engine Pointer to engine config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-
-VOID
-PcieForceCompliance (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- if (Engine->Type.Port.PortData.LinkSpeedCapability >= PcieGen2) {
- GnbLibPciRMW (
- Engine->Type.Port.Address.AddressValue | DxF0x88_ADDRESS,
- AccessWidth32,
- 0xffffffff,
- 0x1 << DxF0x88_EnterCompliance_OFFSET,
- GnbLibGetHeader (Pcie)
- );
- } else if (Engine->Type.Port.PortData.LinkSpeedCapability == PcieGen1) {
- PciePortRegisterWriteField (
- Engine,
- DxF0xE4_xC0_ADDRESS,
- DxF0xE4_xC0_StrapForceCompliance_OFFSET,
- DxF0xE4_xC0_StrapForceCompliance_WIDTH,
- 0x1,
- FALSE,
- Pcie
- );
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h
deleted file mode 100644
index fe72677..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe port initialization service procedure
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 38728 $ @e \$Date: 2010-09-28 14:25:41 -0700 (Tue, 28 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _PCIEPORTSERVICES_H_
-#define _PCIEPORTSERVICES_H_
-
-
-VOID
-PcieSetLinkSpeedCap (
- IN PCIE_LINK_SPEED_CAP LinkSpeedCapability,
- IN PCIe_ENGINE_CONFIG *Engine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PcieSetLinkWidthCap (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PcieLinkSafeMode (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PcieCompletionTimeout (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PcieLinkSetSlotCap (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PcieLinkInitHotplug (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PcieForceCompliance (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PciePifSetPllModeForL1 (
- IN UINT32 LaneBitmap,
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-#endif
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c
deleted file mode 100644
index 0dae507..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c
+++ /dev/null
@@ -1,350 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Power saving features/services
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 38931 $ @e \$Date: 2010-10-01 15:50:05 -0700 (Fri, 01 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "amdlib.h"
-#include "Gnb.h"
-#include "GnbPcie.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1)
-#include "GnbRegistersON.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPOWERMGMT_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Power down unused lanes and plls
- *
- *
- * @param[in] Wrapper Pointer to wrapper config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-
-VOID
-PciePwrPowerDownUnusedLanes (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT32 UnusedLanes;
- IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownUnusedLanes Enter\n");
- UnusedLanes = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_ALL, LANE_TYPE_ACTIVE, Wrapper, Pcie);
- if (Wrapper->Features.PowerOffUnusedLanes != 0) {
- PcieTopologyLaneControl (
- DisableLanes,
- UnusedLanes,
- Wrapper,
- Pcie
- );
- }
- if (Wrapper->Features.PowerOffUnusedPlls != 0) {
- PciePifPllPowerDown (
- UnusedLanes,
- Wrapper,
- Pcie
- );
- }
- IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownUnusedLanes Exit\n");
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Lane bitmam to enable PLL power down in L1
- *
- *
- * @param[in] PllPowerUpLatency Pointer to wrapper config descriptor
- * @param[in] Wrapper Pointer to wrapper config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- * @retval Lane bitmap for which PLL can be powered down in L1
- */
-
-UINT32
-PcieLanesToPowerDownPllInL1 (
- IN UINT8 PllPowerUpLatency,
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT8 LaneGroupExitLatency [4];
- UINT32 LaneBitmapForPllOffInL1;
- PCIe_ENGINE_CONFIG *EngineList;
- UINTN Index;
- IDS_HDT_CONSOLE (GNB_TRACE, "PcieLanesToPowerDownPllInL1 Enter\n");
- LaneBitmapForPllOffInL1 = 0;
- if (Wrapper->Features.PllOffInL1 != 0) {
- LibAmdMemFill (&LaneGroupExitLatency[0], 0xFF, sizeof (LaneGroupExitLatency), GnbLibGetHeader (Pcie));
- EngineList = PcieWrapperGetEngineList (Wrapper);
- while (EngineList != NULL) {
- PCIe_ASPM_LATENCY_INFO LinkLatencyInfo;
- UINT32 ActiveLanesBitmap;
- UINT32 HotplugLanesBitmap;
- if (EngineList->EngineData.EngineType == PciePortEngine) {
- LinkLatencyInfo.MaxL1ExitLatency = 0;
- LinkLatencyInfo.MaxL0sExitLatency = 0;
- ActiveLanesBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_ACTIVE, 0, EngineList, Pcie);
- HotplugLanesBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_HOTPLUG, 0, EngineList, Pcie);
- if (ActiveLanesBitmap != 0 && HotplugLanesBitmap == 0 && !EngineList->Type.Port.IsSB) {
- PcieAspmGetMaxExitLatency (EngineList->Type.Port.Address, &LinkLatencyInfo, GnbLibGetHeader (Pcie));
- }
- if (HotplugLanesBitmap != 0 || EngineList->Type.Port.IsSB) {
- LinkLatencyInfo.MaxL1ExitLatency = 0xff;
- }
- IDS_HDT_CONSOLE (GNB_TRACE, " Engine %d Active Lanes 0x%x, Hotplug Lanes 0x%x\n", EngineList->Type.Port.NativeDevNumber, ActiveLanesBitmap, HotplugLanesBitmap);
- for (Index = 0; Index < 4; Index++) {
- if ((ActiveLanesBitmap & (0xF << (Index * 4))) != 0) {
- if (LaneGroupExitLatency [Index] > LinkLatencyInfo.MaxL1ExitLatency) {
- IDS_HDT_CONSOLE (GNB_TRACE, " Index %d Latency %d\n", Index, LinkLatencyInfo.MaxL1ExitLatency);
- LaneGroupExitLatency [Index] = LinkLatencyInfo.MaxL1ExitLatency;
- }
- }
- }
- }
- EngineList = PcieLibGetNextDescriptor (EngineList);
- }
- LaneBitmapForPllOffInL1 = 0;
- for (Index = 0; Index < 4; Index++) {
- IDS_HDT_CONSOLE (GNB_TRACE, " Index %d Final Latency %d\n", Index, LaneGroupExitLatency[Index]);
- if (LaneGroupExitLatency[Index] > PllPowerUpLatency) {
- LaneBitmapForPllOffInL1 |= (0xF << (Index * 4));
- }
- }
- }
- IDS_HDT_CONSOLE (GNB_TRACE, " Lane bitmap %04x\n", LaneBitmapForPllOffInL1);
- IDS_HDT_CONSOLE (GNB_TRACE, "PcieLanesToPowerDownPllInL1 Exit\n");
- return LaneBitmapForPllOffInL1;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Auto-Power Down electrical Idle detector
- *
- *
- * @param[in] Wrapper Pointer to wrapper config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-
-VOID
-PciePwrAutoPowerDownElectricalIdleDetector (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT8 Pif;
- IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrAutoPowerDownElectricalIdleDetector Enter\n");
- for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) {
- PcieRegisterWriteField (
- Wrapper,
- PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS),
- D0F0xE4_PIF_0010_EiDetCycleMode_OFFSET,
- D0F0xE4_PIF_0010_EiDetCycleMode_WIDTH,
- 0x0,
- TRUE,
- Pcie
- );
-
- PcieRegisterWriteField (
- Wrapper,
- PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS),
- D0F0xE4_PIF_0010_EiCycleOffTime_OFFSET,
- D0F0xE4_PIF_0010_EiCycleOffTime_WIDTH,
- 0x2,
- TRUE,
- Pcie
- );
-
- PcieRegisterWriteField (
- Wrapper,
- PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS),
- D0F0xE4_PIF_0010_EiDetCycleMode_OFFSET,
- D0F0xE4_PIF_0010_EiDetCycleMode_WIDTH,
- 0x1,
- TRUE,
- Pcie
- );
- }
- IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrAutoPowerDownElectricalIdleDetector Exit\n");
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Clock gating
- *
- *
- *
- * @param[in] Wrapper Pointer to wrapper config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-
-VOID
-PciePwrClockGating (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- D0F0xE4_WRAP_8011_STRUCT D0F0xE4_WRAP_8011;
- D0F0xE4_WRAP_8012_STRUCT D0F0xE4_WRAP_8012;
- D0F0xE4_WRAP_8014_STRUCT D0F0xE4_WRAP_8014;
- D0F0xE4_WRAP_8016_STRUCT D0F0xE4_WRAP_8016;
- UINT8 CoreId;
- IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGating Enter\n");
- D0F0xE4_WRAP_8014.Value = PcieRegisterRead (
- Wrapper,
- WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8014_ADDRESS),
- Pcie
- );
- D0F0xE4_WRAP_8012.Value = PcieRegisterRead (
- Wrapper,
- WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8012_ADDRESS),
- Pcie
- );
-
- D0F0xE4_WRAP_8011.Value = PcieRegisterRead (
- Wrapper,
- WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8011_ADDRESS),
- Pcie
- );
-
- if (Wrapper->Features.ClkGating == 0x1) {
- D0F0xE4_WRAP_8014.Field.TxclkPermGateEnable = 0x1;
- D0F0xE4_WRAP_8014.Field.TxclkPrbsGateEnable = 0x1;
-
- D0F0xE4_WRAP_8014.Field.PcieGatePifA1xEnable = 0x1;
- D0F0xE4_WRAP_8014.Field.PcieGatePifA2p5xEnable = 0x1;
-
- D0F0xE4_WRAP_8011.Field.TxclkDynGateEnable = 0x1;
- D0F0xE4_WRAP_8011.Field.TxclkRegsGateEnable = 0x1;
- D0F0xE4_WRAP_8011.Field.TxclkLcntGateEnable = 0x1;
- D0F0xE4_WRAP_8011.Field.RcvrDetClkEnable = 0x1;
- D0F0xE4_WRAP_8011.Field.TxclkPermGateEven = 0x1;
- D0F0xE4_WRAP_8011.Field.TxclkDynGateLatency = 0x3f;
- D0F0xE4_WRAP_8011.Field.TxclkRegsGateLatency = 0x3f;
- D0F0xE4_WRAP_8011.Field.TxclkPermGateLatency = 0x3f;
-
- D0F0xE4_WRAP_8012.Field.Pif2p5xIdleResumeLatency = 0x7;
- D0F0xE4_WRAP_8012.Field.Pif2p5xIdleGateEnable = 0x1;
- D0F0xE4_WRAP_8012.Field.Pif2p5xIdleGateLatency = 0x1;
- D0F0xE4_WRAP_8012.Field.Pif1xIdleResumeLatency = 0x7;
- D0F0xE4_WRAP_8012.Field.Pif1xIdleGateEnable = 0x1;
- D0F0xE4_WRAP_8012.Field.Pif1xIdleGateLatency = 0x1;
- }
- if (Wrapper->Features.TxclkGatingPllPowerDown == 0x1) {
- D0F0xE4_WRAP_8014.Field.TxclkPermGateOnlyWhenPllPwrDn = 0x1;
- }
- PcieRegisterWrite (
- Wrapper,
- WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8014_ADDRESS),
- D0F0xE4_WRAP_8014.Value,
- TRUE,
- Pcie
- );
- PcieRegisterWrite (
- Wrapper,
- WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8012_ADDRESS),
- D0F0xE4_WRAP_8012.Value,
- TRUE,
- Pcie
- );
- PcieRegisterWrite (
- Wrapper,
- WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8011_ADDRESS),
- D0F0xE4_WRAP_8011.Value,
- TRUE,
- Pcie
- );
- for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
- PcieRegisterWriteField (
- Wrapper,
- CORE_SPACE (CoreId, D0F0xE4_CORE_0011_ADDRESS),
- D0F0xE4_CORE_0011_DynClkLatency_OFFSET,
- D0F0xE4_CORE_0011_DynClkLatency_WIDTH,
- 0xf,
- TRUE,
- Pcie
- );
- }
- if (Wrapper->Features.LclkGating == 0x1) {
- D0F0xE4_WRAP_8016.Value = PcieRegisterRead (
- Wrapper,
- WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8016_ADDRESS),
- Pcie
- );
- D0F0xE4_WRAP_8016.Field.LclkDynGateEnable = 0x1;
- D0F0xE4_WRAP_8016.Field.LclkGateFree = 0x1;
- PcieRegisterWrite (
- Wrapper,
- WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8016_ADDRESS),
- D0F0xE4_WRAP_8016.Value,
- TRUE,
- Pcie
- );
- }
- IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGating Exit\n");
-}
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.h b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.h
deleted file mode 100644
index 2a17d56..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Power saving features/services
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _PCIEPOWERSAVINGFEATURES_H_
-#define _PCIEPOWERSAVINGFEATURES_H_
-
-
-VOID
-PciePwrPowerDownUnusedLanes (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-UINT32
-PcieLanesToPowerDownPllInL1 (
- IN UINT8 PllPowerUpLatency,
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PciePwrAutoPowerDownElectricalIdleDetector (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PciePwrClockGating (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSbLink.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSbLink.c
deleted file mode 100644
index 122a9e3..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSbLink.c
+++ /dev/null
@@ -1,221 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * GNB-SB link procedure
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 38931 $ @e \$Date: 2010-10-01 15:50:05 -0700 (Fri, 01 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "amdlib.h"
-#include "Gnb.h"
-#include "GnbPcie.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1)
-#include "GnbRegistersON.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIESBLINK_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Enable/Disable ASPM on GNB-SB link
- *
- *
- *
- * @param[in] Engine Pointer to engine config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-
-AGESA_STATUS
-PcieSbLinkAspmControl (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- AGESA_STATUS Status;
- UINT8 NbAspm;
-
- Status = PcieSbInitAspm (Engine->Type.Port.PortData.LinkAspm, GnbLibGetHeader (Pcie));
- if (Status != AGESA_SUCCESS) {
- return AGESA_UNSUPPORTED;
- }
-
- NbAspm = Engine->Type.Port.PortData.LinkAspm;
-
- PcieNbAspmEnable (Engine->Type.Port.Address, NbAspm, GnbLibGetHeader (Pcie));
- return AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init SB ASPM.
- * Enable ASPM states on SB
- *
- *
- * @param[in] Aspm ASPM bitmap.
- * @param[in] StdHeader Standard configuration header
- */
-/*----------------------------------------------------------------------------------------*/
-
-AGESA_STATUS
-PcieSbInitAspm (
- IN PCIE_ASPM_TYPE Aspm,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_STATUS Status;
- UINT16 AlinkPort;
-
- Status = PcieSbAgetAlinkIoAddress (&AlinkPort, StdHeader);
- if (Status != AGESA_SUCCESS) {
- return Status;
- }
- GnbLibIoRMW (AlinkPort, AccessS3SaveWidth32, 0x0, 0x40000038, StdHeader);
- GnbLibIoRMW (AlinkPort + 4, AccessS3SaveWidth32, 0x0, 0xA0, StdHeader);
- GnbLibIoRMW (AlinkPort, AccessS3SaveWidth32, 0x0, 0x4000003c, StdHeader);
- GnbLibIoRMW (AlinkPort + 4, AccessS3SaveWidth32, 0xffff00ff, 0x6900, StdHeader);
- GnbLibIoRMW (AlinkPort, AccessS3SaveWidth32, 0x0, 0x80000068, StdHeader);
- GnbLibIoRMW (AlinkPort + 4, AccessS3SaveWidth32, 0xfffffffc, Aspm, StdHeader);
- return AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get Alink config address
- *
- *
- */
-/*----------------------------------------------------------------------------------------*/
-
-AGESA_STATUS
-PcieSbAgetAlinkIoAddress (
- OUT UINT16 *AlinkPort,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 AlinkPortIndex;
- AlinkPortIndex = 0xE0;
- GnbLibIoWrite (0xCD6, AccessWidth8, &AlinkPortIndex, StdHeader);
- GnbLibIoRead (0xCD7, AccessWidth8, AlinkPort, StdHeader);
- AlinkPortIndex = 0xE1;
- GnbLibIoWrite (0xCD6, AccessWidth8, &AlinkPortIndex, StdHeader);
- GnbLibIoRead (0xCD7, AccessWidth8, (VOID*) ((UINT8*) AlinkPort + 1), StdHeader);
- if (&AlinkPort == 0) {
- return AGESA_UNSUPPORTED;
- }
- return AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Set ASMP State on PCIe device function
- *
- *
- *
- * @param[in] Function PCI address of function.
- * @param[in] Aspm ASPM bitmap.
- * @param[in] StdHeader Standard configuration header
- *
- */
- /*----------------------------------------------------------------------------------------*/
-
-VOID
-PcieNbAspmEnable (
- IN PCI_ADDR Function,
- IN PCIE_ASPM_TYPE Aspm,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 PcieCapPtr;
- PcieCapPtr = GnbLibFindPciCapability (Function.AddressValue, PCIE_CAP_ID, StdHeader);
- if (PcieCapPtr != 0) {
- GnbLibPciRMW (
- Function.AddressValue | (PcieCapPtr + PCIE_LINK_CTRL_REGISTER) ,
- AccessS3SaveWidth8,
- ~(BIT0 | BIT1),
- Aspm,
- StdHeader
- );
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Enable VC on GNB-SB link
- *
- *
- *
- * @param[in] Engine Pointer to engine config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-
-VOID
-PcieSbLinkVcEnable (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
-
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSbLink.h b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSbLink.h
deleted file mode 100644
index e389faa..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSbLink.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * GNB-SB link procedure
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _PCIESBLINK_H_
-#define _PCIESBLINK_H_
-
-
-
-
-AGESA_STATUS
-PcieSbLinkAspmControl (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PcieSbLinkVcEnable (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-AGESA_STATUS
-PcieSbInitAspm (
- IN PCIE_ASPM_TYPE Aspm,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-PcieSbAgetAlinkIoAddress (
- OUT UINT16 *AlinkPort,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-PcieNbAspmEnable (
- IN PCI_ADDR Function,
- IN PCIE_ASPM_TYPE Aspm,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c
deleted file mode 100644
index c298337..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c
+++ /dev/null
@@ -1,255 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Family specific PCIe complex initialization services
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34930 $ @e \$Date: 2010-07-14 02:57:05 -0700 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "amdlib.h"
-#include "Gnb.h"
-#include "GnbPcie.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include GNB_MODULE_DEFINITIONS (GnbPcieConfig)
-#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1)
-#include "GnbRegistersON.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIESILICONSERVICES_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get Gen1 voltage Index
- *
- *
- *
- *
- * @param[in] StdHeader Standard configuration header
- */
-UINT8
-PcieSiliconGetGen1VoltageIndex (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 Index;
- UINT8 Gen1VidIndex;
- UINT8 SclkVidArray[4];
- GnbLibPciRead (
- MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS),
- AccessWidth32,
- &SclkVidArray[0],
- StdHeader
- );
- Gen1VidIndex = 0;
- for (Index = 0; Index < 4; Index++) {
- if (SclkVidArray[Index] > SclkVidArray[Gen1VidIndex]) {
- Gen1VidIndex = Index;
- }
- }
- return Gen1VidIndex;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Request Pcie voltage change
- *
- *
- *
- * @param[in] VidIndex The request VID index
- * @param[in] StdHeader Standard configuration header
- */
-VOID
-PcieSiliconRequestVoltage (
- IN UINT8 VidIndex,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- D0F0x64_x6A_STRUCT D0F0x64_x6A;
- D0F0x64_x6B_STRUCT D0F0x64_x6B;
-
- //Enable voltage client
- GnbLibPciIndirectRead (
- MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS),
- D0F0x64_x6A_ADDRESS | IOC_WRITE_ENABLE,
- AccessS3SaveWidth32,
- &D0F0x64_x6A.Value,
- StdHeader
- );
-
- D0F0x64_x6A.Field.VoltageChangeEn = 0x1;
-
- GnbLibPciIndirectWrite (
- MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS),
- D0F0x64_x6A_ADDRESS | IOC_WRITE_ENABLE,
- AccessS3SaveWidth32,
- &D0F0x64_x6A.Value,
- StdHeader
- );
-
- D0F0x64_x6A.Field.VoltageLevel = VidIndex;
- D0F0x64_x6A.Field.VoltageChangeReq = !D0F0x64_x6A.Field.VoltageChangeReq;
-
- GnbLibPciIndirectWrite (
- MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS),
- D0F0x64_x6A_ADDRESS | IOC_WRITE_ENABLE,
- AccessS3SaveWidth32,
- &D0F0x64_x6A.Value,
- StdHeader
- );
- do {
- GnbLibPciIndirectRead (
- MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS),
- D0F0x64_x6B_ADDRESS | IOC_WRITE_ENABLE,
- AccessS3SaveWidth32,
- &D0F0x64_x6B.Value,
- StdHeader
- );
- } while (D0F0x64_x6A.Field.VoltageChangeReq != D0F0x64_x6B.Field.VoltageChangeAck);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Unhide all ports
- *
- *
- *
- * @param[in] Silicon Pointer to silicon configuration descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-
-VOID
-PcieSiliconUnHidePorts (
- IN PCIe_SILICON_CONFIG *Silicon,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- GnbLibPciIndirectRMW (
- Silicon->Address.AddressValue | D0F0x60_ADDRESS,
- D0F0x64_x0C_ADDRESS | IOC_WRITE_ENABLE,
- AccessS3SaveWidth32,
- ~(BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7),
- 0x0,
- GnbLibGetHeader (Pcie)
- );
- GnbLibPciIndirectRMW (
- Silicon->Address.AddressValue | D0F0x60_ADDRESS,
- D0F0x64_x00_ADDRESS | IOC_WRITE_ENABLE,
- AccessS3SaveWidth32,
- ~BIT6,
- BIT6,
- GnbLibGetHeader (Pcie)
- );
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Hide unused ports
- *
- *
- *
- * @param[in] Silicon Pointer to silicon configuration data area
- * @param[in] Pcie Pointer to data area up to 256 byte
- */
-
-VOID
-PcieSiliconHidePorts (
- IN PCIe_SILICON_CONFIG *Silicon,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- D0F0x64_x0C_STRUCT D0F0x64_x0C;
- PCIe_WRAPPER_CONFIG *WrapperList;
- D0F0x64_x0C.Value = 0;
- WrapperList = PcieSiliconGetWrapperList (Silicon);
- while (WrapperList != NULL) {
- PCIe_ENGINE_CONFIG *EngineList;
- EngineList = PcieWrapperGetEngineList (WrapperList);
- while (EngineList != NULL) {
- if (EngineList->EngineData.EngineType == PciePortEngine) {
- if (!PcieConfigCheckPortStatus (EngineList, INIT_STATUS_PCIE_TRAINING_SUCCESS) &&
- ((EngineList->Type.Port.PortData.LinkHotplug == HotplugDisabled) || (EngineList->Type.Port.PortData.LinkHotplug == HotplugInboard)) &&
- !EngineList->Type.Port.IsSB) {
- D0F0x64_x0C.Value |= 1 << EngineList->Type.Port.NativeDevNumber;
- }
- }
- EngineList = PcieLibGetNextDescriptor (EngineList);
- }
- WrapperList = PcieLibGetNextDescriptor (WrapperList);
- }
-
- GnbLibPciIndirectRMW (
- Silicon->Address.AddressValue | D0F0x60_ADDRESS,
- D0F0x64_x0C_ADDRESS | IOC_WRITE_ENABLE,
- AccessS3SaveWidth32,
- ~(BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7),
- D0F0x64_x0C.Value,
- GnbLibGetHeader (Pcie)
- );
- GnbLibPciIndirectRMW (
- Silicon->Address.AddressValue | D0F0x60_ADDRESS,
- D0F0x64_x00_ADDRESS | IOC_WRITE_ENABLE,
- AccessS3SaveWidth32,
- ~BIT6,
- 0x0,
- GnbLibGetHeader (Pcie)
- );
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.h b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.h
deleted file mode 100644
index 2169e49..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe Complex Services
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _PCIESILICONSERVICES_H_
-#define _PCIESILICONSERVICES_H_
-
-UINT8
-PcieSiliconGetGen1VoltageIndex (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-PcieSiliconRequestVoltage (
- IN UINT8 VidIndex,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-PcieSiliconUnHidePorts (
- IN PCIe_SILICON_CONFIG *Silicon,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PcieSiliconHidePorts (
- IN PCIe_SILICON_CONFIG *Silicon,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl
deleted file mode 100644
index 5ca8352..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl
+++ /dev/null
@@ -1,217 +0,0 @@
-/**
- * @file
- *
- * ALIB PSPP Pcie Smu Lib V1
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 25430 $ @e \$Date: 2010-01-18 22:25:55 -0800 (Mon, 18 Jan 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
- /*----------------------------------------------------------------------------------------*/
- /**
- * SMU indirect register read
- *
- * Arg0 - Smu register offset
- *
- */
- Method (procNbSmuIndirectRegisterRead, 1, NotSerialized) {
- Store (procIndirectRegisterRead (0x0, 0x60, 0xCD), Local0)
- // Access 32 bit width
- Increment (Arg0)
- // Reverse ReqToggle
- Or (And (Local0, 0xFEFFFFFF), And (Not (And (Local0, 0x01000000)), 0x01000000),Local0)
- // Assign Address and ReqType = 0
- Or (And (Local0, 0xFD00FFFF), ShiftLeft (Arg0, 16), Local0)
-
- procIndirectRegisterWrite (0x0, 0x60, 0xCD, Local0)
-
- Store (procIndirectRegisterRead (0x0, 0x60, 0xCE), Local0)
- return (Local0)
- }
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * SMU indirect register Write
- *
- * Arg0 - Smu register offset
- * Arg1 - Value
- * Arg2 - Width, 0 = 16, 1 = 32
- *
- */
- Method (procNbSmuIndirectRegisterWrite, 3, NotSerialized) {
- Store (procIndirectRegisterRead (0x0, 0x60, 0xCD), Local0)
- // Get low 16 bit value
- Store (And (Arg1, 0xFFFF), Local1)
- // Reverse ReqToggle
- Or (And (Local0, 0xFEFFFFFF), And (Not (And (Local0, 0x01000000)), 0x01000000),Local0)
- // Assign Address
- Or (And (Local0, 0xFD000000), ShiftLeft (Arg0, 16), Local0)
- // ReqType = 1
- Or (Local0, 0x02000000, Local0)
- // Assign Low 16 bit value
- Or (Local0, Local1, Local0)
-
- procIndirectRegisterWrite (0x0, 0x60, 0xCD, Local0)
-
- if (LEqual (Arg2, 1)) {
- // Get high 16 bit value
- Store (ShiftRight (Arg1, 16), Local1)
- // Reverse ReqToggle
- Or (And (Local0, 0xFEFFFFFF), And (Not (And (Local0, 0x01000000)), 0x01000000),Local0)
- // Assign Address
- Or (And (Local0, 0xFF000000), ShiftLeft (Add (Arg0, 1), 16), Local0)
- // Assign High 16 bit value
- Or (Local0, Local1, Local0)
-
- procIndirectRegisterWrite (0x0, 0x60, 0xCD, Local0)
- }
-
- }
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * SMU Service request
- *
- * Arg0 - Smu service id
- * Arg1 - Flags - Poll Ack = 1, Poll down = 2
- *
- */
- Method (procNbSmuServiceRequest, 2, NotSerialized) {
- Store ("NbSmuServiceRequest Enter", Debug)
- Store ("Request id =", Debug)
- Store (Arg0, Debug)
-
- Or (ShiftLeft (Arg0, 3), 0x1, Local0)
- procNbSmuIndirectRegisterWrite (0x3, Local0, 1)
-
- if (LAnd (Arg1, 1)) {
- while (LNotEqual (AND(procNbSmuIndirectRegisterRead (0x3), 0x2), 0x2)) {
- Store ("--Wait Ack--", Debug)
- }
- }
- if (LAnd (Arg1, 2)) {
- while (LNotEqual (AND(procNbSmuIndirectRegisterRead (0x3), 0x4), 0x4)) {
- Store ("--Wait Done--", Debug)
- }
- }
- // Clear IRQ register
- procNbSmuIndirectRegisterWrite (0x3, 0, 0)
- Store ("NbSmuServiceRequest Exit", Debug)
- }
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * Write RCU register
- *
- * Arg0 - Register Address
- * Arg1 - Register Data
- *
- */
- Method (procSmuRcuWrite, 2, NotSerialized) {
- procNbSmuIndirectRegisterWrite (0xB, Arg0, 0)
- procNbSmuIndirectRegisterWrite (0x5, Arg1, 1)
-
- }
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * Read RCU register
- *
- * Arg0 - Register Address
- * Retval - RCU register value
- */
- Method (procSmuRcuRead, 1, NotSerialized) {
- procNbSmuIndirectRegisterWrite (0xB, Arg0, 0)
- Store (procNbSmuIndirectRegisterRead (0x5), Local0)
- return (Local0)
- }
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * SMU SRBM Register Read
- *
- * Arg0 - FCR register address
- *
- */
- Method (procNbSmuSrbmRegisterRead, 1, NotSerialized) {
- //SMUx0B_x8600
- Store (Or (And (Arg0, 0xFF), 0x01865000), Local0)
- //SMUx0B_x8604
- Store (Or (And (Arg0, 0xFFFFFF00), 4), Local1)
- //SMUx0B_x8608
- Store (Or (ShiftLeft (3, 30), ShiftLeft (1, 18)), Local2)
- //Write SMU RCU
- procSmuRcuWrite (0x8600, Local0)
- procSmuRcuWrite (0x8604, Local1)
- procSmuRcuWrite (0x8608, Local2)
- // ServiceId
- if (LEqual (ShiftRight (Arg0, 16), 0xFE00)) {
- procNbSmuServiceRequest (0xD, 0x3)
- }
- if (LEqual (ShiftRight (Arg0, 16), 0xFE30)) {
- procNbSmuServiceRequest (0xB, 0x3)
- }
- return (procSmuRcuRead(0x8650))
- }
-
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * SMU SRBM Register Write
- *
- * Arg0 - FCR register address
- * Arg1 - Value
- *
- */
- Method (procNbSmuSrbmRegisterWrite, 2, NotSerialized) {
- //SMUx0B_x8600
- Store (Or (And (Arg0, 0xFF), 0x01865000), Local0)
- //SMUx0B_x8604
- Store (Or (And (Arg0, 0xFFFFFF00), 4), Local1)
- //SMUx0B_x8608
- Store (Or (ShiftLeft (3, 30), ShiftLeft (1, 18)), Local2)
- Or (Local2, ShiftLeft (1, 16), Local2)
- //Write SMU RCU
- procSmuRcuWrite (0x8600, Local0)
- procSmuRcuWrite (0x8604, Local1)
- procSmuRcuWrite (0x8608, Local2)
- //Write Data
- procSmuRcuWrite (0x8650, Arg1)
- // ServiceId
- procNbSmuServiceRequest (0xB, 0x3)
- }
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c
deleted file mode 100644
index 0abd677..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe timer access procedure
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 38931 $ @e \$Date: 2010-10-01 15:50:05 -0700 (Fri, 01 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "amdlib.h"
-#include "Gnb.h"
-#include "GnbPcie.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1)
-#include "GnbRegistersON.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETIMER_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get PCIe timer timestamp
- *
- *
- *
- * @param[in] Pcie Pointer to internal configuration data area
- * @retval Time stamp value
- */
-
-UINT32
-PcieTimerGetTimeStamp (
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- D0F0xE4_WRAP_80F0_STRUCT D0F0xE4_WRAP_80F0;
- D0F0xE4_WRAP_80F0.Value = PcieRegisterRead (
- (PCIe_WRAPPER_CONFIG *)(((PCIe_SILICON_CONFIG *)(Pcie->ComplexList->SiliconList))->WrapperList),
- WRAP_SPACE (0, D0F0xE4_WRAP_80F0_ADDRESS),
- Pcie
- );
- return D0F0xE4_WRAP_80F0.Value;
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.h b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.h
deleted file mode 100644
index e00cc1c..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe timer access procedure
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _PCIETIMER_H_
-#define _PCIETIMER_H_
-
-UINT32
-PcieTimerGetTimeStamp (
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-#define TIMESTAMPS_DELTA(Time2, Time1) ((Time2 > Time1) ? (Time2 - Time1) : (0xffffffffull - Time1 + Time2))
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c
deleted file mode 100644
index 2bddde4..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c
+++ /dev/null
@@ -1,692 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe topology initialization service procedures.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 38931 $ @e \$Date: 2010-10-01 15:50:05 -0700 (Fri, 01 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "amdlib.h"
-#include "Gnb.h"
-#include "GnbPcie.h"
-#include "GnbPcieFamServices.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include GNB_MODULE_DEFINITIONS (GnbPcieConfig)
-#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1)
-#include "GnbRegistersON.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETOPOLOGYSERVICES_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Prepare for reconfiguration
- *
- *
- *
- * @param[in] Wrapper Pointer to wrapper config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-VOID
-PcieTopologyPrepareForReconfig (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- D0F0xE4_WRAP_8062_STRUCT D0F0xE4_WRAP_8062;
- UINT8 CoreId;
- if (PcieLibIsPcieWrapper (Wrapper)) {
- for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
- PcieRegisterWriteField (
- Wrapper,
- CORE_SPACE (CoreId, D0F0xE4_CORE_0011_ADDRESS),
- D0F0xE4_CORE_0011_DynClkLatency_OFFSET,
- D0F0xE4_CORE_0011_DynClkLatency_WIDTH,
- 0xf,
- FALSE,
- Pcie
- );
- }
-
- D0F0xE4_WRAP_8062.Value = PcieRegisterRead (
- Wrapper,
- WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
- Pcie
- );
-
- D0F0xE4_WRAP_8062.Field.ConfigXferMode = 0x0;
- D0F0xE4_WRAP_8062.Field.BlockOnIdle = 0x0;
- PcieRegisterWrite (
- Wrapper,
- WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
- D0F0xE4_WRAP_8062.Value,
- FALSE,
- Pcie
- );
- }
-}
-
-
-UINT8 LaneMuxSelectorTable[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Locate mux array index
- *
- *
- *
- * @param[in, out] LaneMuxSelectorArrayPtr Pointer to mux selector array
- * @param[in] LaneMuxValue The value that match to array
- * @retval Index Index successfully mapped
- */
-UINT8
-PcieTopologyLocateMuxIndex (
- IN OUT UINT8 *LaneMuxSelectorArrayPtr,
- IN UINT8 LaneMuxValue
- )
-{
- UINT8 Index;
- for (Index = 0; Index < sizeof (LaneMuxSelectorTable); Index++ ) {
- if (LaneMuxSelectorArrayPtr [Index] == LaneMuxValue) {
- return Index;
- }
- }
- return 0;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Apply lane mux
- *
- *
- *
- * @param[in] Wrapper Pointer to wrapper config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-
-VOID
-PcieTopologyApplyLaneMux (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- PCIe_ENGINE_CONFIG *EngineList;
- UINT8 CurrentPhyLane;
- UINT8 CurrentCoreLane;
- UINT8 CoreLaneIndex;
- UINT8 PhyLaneIndex;
- UINT8 NumberOfPhyLane;
- UINT8 TxLaneMuxSelectorArray [sizeof (LaneMuxSelectorTable)];
- UINT8 RxLaneMuxSelectorArray [sizeof (LaneMuxSelectorTable)];
- UINT8 Index;
- UINT32 TxMaxSelectorValue;
- UINT32 RxMaxSelectorValue;
-
- IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyApplyLaneMux Enter\n");
- if (PcieLibIsPcieWrapper (Wrapper)) {
- EngineList = PcieWrapperGetEngineList (Wrapper);
- LibAmdMemCopy (
- &TxLaneMuxSelectorArray[0],
- &LaneMuxSelectorTable[0],
- sizeof (LaneMuxSelectorTable),
- GnbLibGetHeader (Pcie)
- );
- LibAmdMemCopy (
- &RxLaneMuxSelectorArray[0],
- &LaneMuxSelectorTable[0],
- sizeof (LaneMuxSelectorTable),
- GnbLibGetHeader (Pcie)
- );
- while (EngineList != NULL) {
- if (PcieLibIsPcieEngine (EngineList) && PcieLibIsEngineAllocated (EngineList)) {
- CurrentPhyLane = (UINT8) PcieUtilGetLoPhyLane (EngineList) - Wrapper->StartPhyLane;
- NumberOfPhyLane = (UINT8) PcieConfigGetNumberOfPhyLane (EngineList);
- CurrentCoreLane = (UINT8) EngineList->Type.Port.StartCoreLane;
- if (PcieUtilIsLinkReversed (FALSE, EngineList, Pcie)) {
- CurrentCoreLane = CurrentCoreLane + PcieConfigGetNumberOfCoreLane (EngineList) - NumberOfPhyLane;
- }
- for (Index = 0; Index < NumberOfPhyLane; Index = Index + 2 ) {
- CoreLaneIndex = (CurrentCoreLane + Index) / 2;
- PhyLaneIndex = (CurrentPhyLane + Index) / 2;
-
- if (RxLaneMuxSelectorArray [CoreLaneIndex] != PhyLaneIndex) {
- RxLaneMuxSelectorArray [PcieTopologyLocateMuxIndex (RxLaneMuxSelectorArray, PhyLaneIndex)] = RxLaneMuxSelectorArray [CoreLaneIndex];
- RxLaneMuxSelectorArray [CoreLaneIndex] = PhyLaneIndex;
- }
- if (TxLaneMuxSelectorArray [PhyLaneIndex] != CoreLaneIndex) {
- TxLaneMuxSelectorArray [PcieTopologyLocateMuxIndex (TxLaneMuxSelectorArray, CoreLaneIndex)] = TxLaneMuxSelectorArray [PhyLaneIndex];
- TxLaneMuxSelectorArray [PhyLaneIndex] = CoreLaneIndex;
- }
- }
- }
- EngineList = PcieLibGetNextDescriptor (EngineList);
- }
- RxMaxSelectorValue = 0;
- TxMaxSelectorValue = 0;
- for (Index = 0; Index < sizeof (LaneMuxSelectorTable); Index++) {
- RxMaxSelectorValue |= (RxLaneMuxSelectorArray[Index] << (Index * 4));
- TxMaxSelectorValue |= (TxLaneMuxSelectorArray[Index] << (Index * 4));
- }
- PcieRegisterWrite (
- Wrapper,
- WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8021_ADDRESS),
- TxMaxSelectorValue,
- FALSE,
- Pcie
- );
- PcieRegisterWrite (
- Wrapper,
- WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8022_ADDRESS),
- RxMaxSelectorValue,
- FALSE,
- Pcie
- );
- }
- IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyApplyLaneMux Exit\n");
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Select master PLL
- *
- *
- *
- * @param[in] Wrapper Pointer to wrapper config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-
-VOID
-PcieTopologySelectMasterPll (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- PCIe_ENGINE_CONFIG *EngineList;
- UINT16 MasterPhyLane;
- UINT16 MasterHotplugPhyLane;
- D0F0xE4_WRAP_8013_STRUCT D0F0xE4_WRAP_8013;
- EngineList = PcieWrapperGetEngineList (Wrapper);
- MasterPhyLane = 0xffff;
- MasterHotplugPhyLane = 0xffff;
- IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySelectMasterPll Enter\n");
- while (EngineList != NULL) {
- if (PcieLibIsEngineAllocated (EngineList)) {
- if (EngineList->EngineData.EngineType == PciePortEngine) {
- MasterPhyLane = EngineList->EngineData.StartLane;
- if (EngineList->Type.Port.PortData.LinkHotplug != HotplugDisabled) {
- MasterHotplugPhyLane = MasterPhyLane;
- }
- }
- }
- EngineList = PcieLibGetNextDescriptor (EngineList);
- }
-
- if (MasterPhyLane == 0xffff) {
- MasterPhyLane = MasterHotplugPhyLane;
- if (MasterPhyLane == 0xffff) {
- MasterPhyLane = Wrapper->StartPhyLane;
- }
- }
- D0F0xE4_WRAP_8013.Value = PcieRegisterRead (
- Wrapper,
- WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8013_ADDRESS),
- Pcie
- );
-
- MasterPhyLane = MasterPhyLane - Wrapper->StartPhyLane;
- if ( MasterPhyLane <= 3 ) {
- D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x1;
- D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x0;
- D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x0;
- D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x0;
- } else if (MasterPhyLane <= 7) {
- D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x0;
- D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x1;
- D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x0;
- D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x0;
- } else if (MasterPhyLane <= 11) {
- D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x0;
- D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x0;
- D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x1;
- D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x0;
- } else {
- D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x0;
- D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x0;
- D0F0xE4_WRAP_8013.Field.MasterPciePllC = 0x0;
- D0F0xE4_WRAP_8013.Field.MasterPciePllD = 0x1;
- }
- PcieRegisterWrite (
- Wrapper,
- WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8013_ADDRESS),
- D0F0xE4_WRAP_8013.Value,
- FALSE,
- Pcie
- );
-
- IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySelectMasterPll Enter\n");
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Execute/clean up reconfiguration
- *
- *
- * @param[in] Wrapper Pointer to wrapper config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-VOID
-PcieTopologyExecuteReconfig (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- D0F0xE4_WRAP_8062_STRUCT D0F0xE4_WRAP_8062;
- D0F0xE4_WRAP_8060_STRUCT D0F0xE4_WRAP_8060;
-
- if (PcieLibIsPcieWrapper (Wrapper)) {
- IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfig Enter\n");
-
- PcieTopologyInitSrbmReset (FALSE, Wrapper, Pcie);
-
- D0F0xE4_WRAP_8062.Value = PcieRegisterRead (
- Wrapper,
- WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
- Pcie
- );
- D0F0xE4_WRAP_8060.Value = PcieRegisterRead (
- Wrapper,
- WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8060_ADDRESS),
- Pcie
- );
-
- D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x1;
- PcieRegisterWrite (
- Wrapper,
- WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
- D0F0xE4_WRAP_8062.Value,
- FALSE,
- Pcie
- );
- D0F0xE4_WRAP_8060.Field.Reconfigure = 0x1;
- PcieRegisterWrite (
- Wrapper,
- WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8060_ADDRESS),
- D0F0xE4_WRAP_8060.Value,
- FALSE,
- Pcie
- );
- do {
- D0F0xE4_WRAP_8060.Value = PcieRegisterRead (
- Wrapper,
- WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8060_ADDRESS),
- Pcie
- );
-
- } while (D0F0xE4_WRAP_8060.Field.Reconfigure == 1);
- D0F0xE4_WRAP_8062.Field.ConfigXferMode = 0x1;
- D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x0;
- PcieRegisterWrite (
- Wrapper,
- WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
- D0F0xE4_WRAP_8062.Value,
- FALSE,
- Pcie
- );
- PcieTopologyInitSrbmReset (TRUE, Wrapper, Pcie);
- IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfig Exit\n");
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Enable lane reversal
- *
- *
- * @param[in] Wrapper Pointer to wrapper config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-VOID
-PcieTopologySetLinkReversal (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- PCIe_ENGINE_CONFIG *EngineList;
- IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySetLinkReversal Enter\n");
- EngineList = PcieWrapperGetEngineList (Wrapper);
- while (EngineList != NULL) {
- if (PcieLibIsEngineAllocated (EngineList)) {
- if (PcieLibIsPcieEngine (EngineList)) {
- if (EngineList->EngineData.StartLane > EngineList->EngineData.EndLane) {
- PciePortRegisterWriteField (
- EngineList,
- DxF0xE4_xC1_ADDRESS,
- DxF0xE4_xC1_StrapReverseLanes_OFFSET,
- DxF0xE4_xC1_StrapReverseLanes_WIDTH,
- 0x1,
- FALSE,
- Pcie
- );
- }
- }
- }
- EngineList = PcieLibGetNextDescriptor (EngineList);
- }
- IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySetLinkReversal Exit\n");
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Reduce link width
- *
- *
- * @param[in] LinkWidth Link width
- * @param[in] Engine Pointer to Engine config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-VOID
-PcieTopologyReduceLinkWidth (
- IN UINT8 LinkWidth,
- IN PCIe_ENGINE_CONFIG *Engine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- PCIe_WRAPPER_CONFIG *Wrapper;
- UINT32 LinkReversed;
- UINT8 DeltaLinkWidthBitmap;
- UINT32 LanesToDisable;
- Wrapper = PcieEngineGetParentWrapper (Engine);
- LinkReversed = PcieUtilIsLinkReversed (TRUE, Engine, Pcie);
-
- DeltaLinkWidthBitmap = (1 << (PcieConfigGetNumberOfCoreLane (Engine) - LinkWidth)) - 1;
- LanesToDisable = (DeltaLinkWidthBitmap << ((LinkReversed == 1) ? Engine->Type.Port.StartCoreLane : (Engine->Type.Port.StartCoreLane + LinkWidth)));
-
- PcieTopologyLaneControl (
- DisableLanes,
- LanesToDisable,
- Wrapper,
- Pcie
- );
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Lanes enable/disable control
- *
- * @param[in] Control Lane control action
- * @param[in] LaneBitMap Core lanes bitmap
- * @param[in] Wrapper Pointer to Wrapper config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-VOID
-PcieTopologyLaneControl (
- IN LANE_CONTROL Control,
- IN UINT32 LaneBitMap,
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- D0F0xE4_WRAP_8023_STRUCT D0F0xE4_WRAP_8023;
- D0F0xE4_WRAP_8023.Value = PcieRegisterRead (
- Wrapper,
- WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8023_ADDRESS),
- Pcie
- );
-
- if (Control == EnableLanes) {
- D0F0xE4_WRAP_8023.Value |= LaneBitMap;
- } else if (Control == DisableLanes) {
- D0F0xE4_WRAP_8023.Value &= (~LaneBitMap);
- }
- D0F0xE4_WRAP_8023.Value &= ((1 << (Wrapper->EndPhyLane - Wrapper->StartPhyLane + 1)) - 1);
- PcieRegisterWrite (
- Wrapper,
- WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8023_ADDRESS),
- D0F0xE4_WRAP_8023.Value,
- FALSE,
- Pcie
- );
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init SRBM reset
- *
- * @param[in] SrbmResetEnable SRBM reset enable flag.
- * @param[in] Wrapper Pointer to wrapper config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-VOID
-PcieTopologyInitSrbmReset (
- IN BOOLEAN SrbmResetEnable,
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT32 pcireg;
- UINT32 regmask = 0x7030;;
- pcireg = PcieRegisterRead (
- Wrapper,
- WRAP_SPACE (Wrapper->WrapId, 0x8063),
- Pcie
- );
- if (SrbmResetEnable) {
- pcireg |= regmask;
- } else {
- pcireg &= ~(regmask);
- }
- PcieRegisterWrite (
- Wrapper,
- WRAP_SPACE (Wrapper->WrapId, 0x8063),
- pcireg,
- FALSE,
- Pcie
- );
-
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Set core configuration according to PCIe port topology
- *
- *
- *
- * @param[in] Wrapper Pointer to wrapper config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- * @retval AGESA_SUCCESS Topology successfully mapped
- * @retval AGESA_ERROR Topology can not be mapped
- */
-
-AGESA_STATUS
-PcieTopologySetCoreConfig (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT8 CoreId;
- AGESA_STATUS Status;
- Status = AGESA_SUCCESS;
- if (PcieLibIsPcieWrapper (Wrapper)) {
- for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
- UINT64 ConfigurationSignature;
- UINT8 NewConfigurationValue;
- ConfigurationSignature = PcieConfigGetConfigurationSignature (Wrapper, CoreId);
- Status = PcieFmGetCoreConfigurationValue (Wrapper, CoreId, ConfigurationSignature, &NewConfigurationValue);
- if (Status == AGESA_SUCCESS) {
- IDS_HDT_CONSOLE (PCIE_MISC, " Core Configuration: Wrapper [%s], CoreID [%d] - %s\n",
- PcieFmDebugGetWrapperNameString (Wrapper),
- CoreId,
- PcieFmDebugGetCoreConfigurationString (Wrapper, NewConfigurationValue)
- );
- PcieRegisterWriteField (
- Wrapper,
- WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0080_ADDRESS),
- D0F0xE4_WRAP_0080_StrapBifLinkConfig_OFFSET,
- D0F0xE4_WRAP_0080_StrapBifLinkConfig_WIDTH,
- NewConfigurationValue,
- FALSE,
- Pcie
- );
- } else {
- IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Core Configuration : Wrapper [%s], Signature [0x%x, 0x%x]\n",
- PcieFmDebugGetWrapperNameString (Wrapper),
- ((UINT32*)&ConfigurationSignature)[1],
- ((UINT32*)&ConfigurationSignature)[0]
- );
- PcieConfigDisableAllEngines (PciePortEngine | PcieDdiEngine, Wrapper);
- }
- }
- }
- return Status;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Relinquish control to DDI for specific lanes
- *
- *
- * @param[in] Wrapper Pointer to wrapper configuration descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-VOID
-PcieSetDdiOwnPhy (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT32 LaneBitmap;
-
- if (PcieLibIsDdiWrapper (Wrapper)) {
- IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmSetDdiOwnPhy Enter\n");
- LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_DDI_ALLOCATED, 0, Wrapper, Pcie);
- IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmSetDdiOwnPhy Exit\n");
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Set TX control for PCIe lanes
- *
- *
- *
- * @param[in] Wrapper Pointer to wrapper config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-VOID
-PcieWrapSetTxS1CtrlForLaneMux (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- D0F0xE4_WRAP_8025_STRUCT D0F0xE4_WRAP_8025;
- UINT32 LaneBitmap;
- UINTN Index;
- D0F0xE4_WRAP_8025.Value = PcieRegisterRead (
- Wrapper,
- WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8025_ADDRESS),
- Pcie
- );
- Index = 0;
- LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_ALL, LANE_TYPE_PCIE_SB, Wrapper, Pcie);
- while (LaneBitmap != 0) {
- if ((LaneBitmap & 0xf) != 0) {
- D0F0xE4_WRAP_8025.Value &= (~(0xff << (Index * 8)));
- D0F0xE4_WRAP_8025.Value |= (((0x03 << 3) | 0x1) << (Index * 8));
- }
- LaneBitmap >>= 4;
- ++Index;
- }
- PcieRegisterWrite (
- Wrapper,
- WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8025_ADDRESS),
- D0F0xE4_WRAP_8025.Value,
- FALSE,
- Pcie
- );
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Set TX control for lane muxes
- *
- *
- *
- * @param[in] Wrapper Pointer to wrapper config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-VOID
-PcieWrapSetTxOffCtrlForLaneMux (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- PcieRegisterWrite (
- Wrapper,
- WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8025_ADDRESS),
- 0x1f1f1f1f,
- FALSE,
- Pcie
- );
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h
deleted file mode 100644
index e737d05..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe topology initialization service procedures.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _PCIETOPOLOGYSERVICES_H_
-#define _PCIETOPOLOGYSERVICES_H_
-
-/// Lane Control
-typedef enum {
- EnableLanes, ///< Enable Lanes
- DisableLanes ///< Disable Lanes
-} LANE_CONTROL;
-
-VOID
-PcieTopologyPrepareForReconfig (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-AGESA_STATUS
-PcieTopologySetCoreConfig (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PcieTopologyApplyLaneMux (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PcieTopologySelectMasterPll (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PcieTopologyExecuteReconfig (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PcieTopologySetLinkReversal (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-
-VOID
-PcieTopologyReduceLinkWidth (
- IN UINT8 LinkWidth,
- IN PCIe_ENGINE_CONFIG *Engine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PcieTopologyLaneControl (
- IN LANE_CONTROL Control,
- IN UINT32 LaneBitMap,
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PcieTopologyInitSrbmReset (
- IN BOOLEAN SrbmResetEnable,
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PcieSetDdiOwnPhy (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PcieWrapSetTxS1CtrlForLaneMux (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PcieWrapSetTxOffCtrlForLaneMux (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-#endif
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c
deleted file mode 100644
index ef86820..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c
+++ /dev/null
@@ -1,437 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe utility. Various supporting functions.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 38931 $ @e \$Date: 2010-10-01 15:50:05 -0700 (Fri, 01 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "amdlib.h"
-#include "Gnb.h"
-#include "GnbPcie.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include GNB_MODULE_DEFINITIONS (GnbPcieConfig)
-#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1)
-#include "GnbRegistersON.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEUTILITYLIB_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-typedef struct {
- UINT32 Flags;
- PCIE_LINK_SPEED_CAP LinkSpeedCapability;
-} PCIE_GLOBAL_GEN_CAP_WORKSPACE;
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get link state history from HW state machine
- *
- *
- *
- * @param[in] Engine Pointer to engine config descriptor
- * @param[out] History Buffer to save history
- * @param[in] Length Buffer length
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-
-VOID
-PcieUtilGetLinkHwStateHistory (
- IN PCIe_ENGINE_CONFIG *Engine,
- OUT UINT8 *History,
- IN UINT8 Length,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT8 ReadLength;
- UINT32 LocalHistory [6];
- UINT16 Index;
- ASSERT (Length <= 16);
- ASSERT (Length > 0);
- if (Length > 6*4) {
- Length = 6*4;
- }
- ReadLength = (Length + 3) / 4;
- for (Index = 0; Index < ReadLength; Index++) {
- LocalHistory[Index] = PciePortRegisterRead (
- Engine,
- DxF0xE4_xA5_ADDRESS + Index,
- Pcie
- );
- }
- LibAmdMemCopy (History, LocalHistory, Length, GnbLibGetHeader (Pcie));
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Search array for specific pattern
- *
- *
- * @param[in] Buf1 Pointer to source buffer which will be subject of search
- * @param[in] Buf1Length Length of the source buffer
- * @param[in] Buf2 Pointer to pattern buffer
- * @param[in] Buf2Length Length of the pattern buffer
- * @retval TRUE Pattern found
- * @retval TRUE Pattern not found
- */
-
-BOOLEAN
-PcieUtilSearchArray (
- IN UINT8 *Buf1,
- IN UINTN Buf1Length,
- IN UINT8 *Buf2,
- IN UINTN Buf2Length
- )
-{
- UINT8 *CurrentBuf1Ptr;
- CurrentBuf1Ptr = Buf1;
- while (CurrentBuf1Ptr < (Buf1 + Buf1Length - Buf2Length)) {
- UINT8 *SourceBufPtr;
- UINT8 *PatternBufPtr;
- UINTN PatternBufLength;
- SourceBufPtr = CurrentBuf1Ptr;
- PatternBufPtr = Buf2;
- PatternBufLength = Buf2Length;
- while ((*SourceBufPtr++ == *PatternBufPtr++) && (PatternBufLength-- != 0));
- if (PatternBufLength == 0) {
- return TRUE;
- }
- CurrentBuf1Ptr++;
- }
- return FALSE;
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Check if link reversed
- *
- *
- * @param[in] HwLinkState Check for HW auto link reversal
- * @param[in] Engine Pointer to engine config descriptor
- * @param[in] Pcie Pointer to PCIe config descriptor
- * @retval TRUE if link reversed
- */
-BOOLEAN
-PcieUtilIsLinkReversed (
- IN BOOLEAN HwLinkState,
- IN PCIe_ENGINE_CONFIG *Engine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT32 LinkReversal;
-
- LinkReversal = (Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? 1 : 0;
- if (HwLinkState) {
- DxF0xE4_x50_STRUCT DxF0xE4_x50;
- DxF0xE4_x50.Value = PciePortRegisterRead (
- Engine,
- DxF0xE4_x50_ADDRESS,
- Pcie
- );
- LinkReversal ^= DxF0xE4_x50.Field.PortLaneReversal;
- }
- return ((LinkReversal & BIT0) != 0) ? TRUE : FALSE;
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get link width detected during training
- *
- *
- *
- * @param[in] Engine Pointer to engine config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- * @retval Link width
- */
-UINT8
-PcieUtilGetLinkWidth (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT8 LinkWidth;
- DxF0xE4_xA2_STRUCT DxF0xE4_xA2;
- DxF0xE4_xA2.Value = PciePortRegisterRead (
- Engine,
- DxF0xE4_xA2_ADDRESS,
- Pcie
- );
- switch (DxF0xE4_xA2.Field.LcLinkWidthRd) {
- case 0x6:
- LinkWidth = 16;
- break;
- case 0x5:
- LinkWidth = 12;
- break;
- case 0x4:
- LinkWidth = 8;
- break;
- case 0x3:
- LinkWidth = 4;
- break;
- case 0x2:
- LinkWidth = 2;
- break;
- case 0x1:
- LinkWidth = 1;
- break;
- default:
- LinkWidth = 0;
- }
- return LinkWidth;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get bitmap of engine lane of requested type
- *
- *
- * @param[in] IncludeLaneType Include Lane type
- * @param[in] ExcludeLaneType Exclude Lane type
- * @param[in] Engine Pointer to engine config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- * @retval Lane bitmap
- */
-
-UINT32
-PcieUtilGetEngineLaneBitMap (
- IN UINT32 IncludeLaneType,
- IN UINT32 ExcludeLaneType,
- IN PCIe_ENGINE_CONFIG *Engine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT32 LaneBitmap;
- UINT16 LaneOffset;
- LaneBitmap = 0;
- if ((IncludeLaneType & LANE_TYPE_PCIE_LANES) && Engine->EngineData.EngineType == PciePortEngine) {
- if (IncludeLaneType & LANE_TYPE_PCIE_ALL) {
- LaneBitmap |= (((1 << PcieConfigGetNumberOfCoreLane (Engine)) - 1) << Engine->Type.Port.StartCoreLane);
- }
- if (PcieLibIsEngineAllocated (Engine)) {
- if (IncludeLaneType & LANE_TYPE_PCIE_ALLOCATED) {
- LaneBitmap |= (((1 << PcieConfigGetNumberOfPhyLane (Engine)) - 1) << Engine->Type.Port.StartCoreLane);
- }
- if (IncludeLaneType & LANE_TYPE_PCIE_ACTIVE) {
- if (Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced) {
- LaneBitmap |= PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_ALLOCATED, 0, Engine, Pcie);
- } else if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_PORT_IN_COMPLIANCE)) {
- LaneBitmap |= PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_ALLOCATED, 0, Engine, Pcie);
- } else if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
- UINT8 LinkWidth;
- BOOLEAN LinkReversed;
- LinkWidth = PcieUtilGetLinkWidth (Engine, Pcie);
- if (LinkWidth > PcieConfigGetNumberOfPhyLane (Engine)) {
- LinkWidth = PcieConfigGetNumberOfPhyLane (Engine);
- }
- LinkReversed = PcieUtilIsLinkReversed (TRUE, Engine, Pcie);
- LaneOffset = LinkReversed ? (Engine->Type.Port.EndCoreLane - LinkWidth + 1) : Engine->Type.Port.StartCoreLane;
- LaneBitmap |= (((1 << LinkWidth) - 1) << LaneOffset);
- }
- }
- if (IncludeLaneType & LANE_TYPE_PCIE_SB) {
- if (Engine->Type.Port.IsSB) {
- LaneBitmap |= PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_ACTIVE, 0, Engine, Pcie);
- IDS_HDT_CONSOLE (GNB_TRACE, "SB Lane Bitmap is 0x%x\n", LaneBitmap);
- }
- }
- if (IncludeLaneType & LANE_TYPE_PCIE_HOTPLUG) {
- if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) {
- LaneBitmap |= PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_ALLOCATED, 0, Engine, Pcie);
- }
- }
- }
- }
- if ((IncludeLaneType & LANE_TYPE_DDI_LANES) && Engine->EngineData.EngineType == PcieDdiEngine) {
- if (PcieLibIsEngineAllocated (Engine)) {
- if (IncludeLaneType & (LANE_TYPE_DDI_ALLOCATED | LANE_TYPE_DDI_ALL)) {
- LaneOffset = PcieUtilGetLoPhyLane (Engine) - PcieEngineGetParentWrapper (Engine)->StartPhyLane;
- LaneBitmap |= ((1 << PcieConfigGetNumberOfPhyLane (Engine)) - 1) << LaneOffset;
- }
- if (IncludeLaneType & LANE_TYPE_DDI_ACTIVE) {
- if (Engine->InitStatus & INIT_STATUS_DDI_ACTIVE) {
- LaneBitmap |= PcieUtilGetEngineLaneBitMap (LANE_TYPE_DDI_ALL, 0, Engine, Pcie);
- }
- }
- }
- }
- if (ExcludeLaneType != 0) {
- LaneBitmap &= (~PcieUtilGetEngineLaneBitMap (ExcludeLaneType, 0, Engine, Pcie));
- }
- return LaneBitmap;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get bitmap of Wrapper lane of requested type
- *
- *
- * @param[in] IncludeLaneType Include Lane type
- * @param[in] ExcludeLaneType Exclude Lane type
- * @param[in] Wrapper Pointer to wrapper config descriptor
- * @param[in] Pcie Pointer to PCIe config descriptor
- * @retval Lane bitmap
- */
-
-UINT32
-PcieUtilGetWrapperLaneBitMap (
- IN UINT32 IncludeLaneType,
- IN UINT32 ExcludeLaneType,
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- PCIe_ENGINE_CONFIG *EngineList;
- UINT32 LaneBitmap;
- EngineList = PcieWrapperGetEngineList (Wrapper);
- LaneBitmap = 0;
- if ((IncludeLaneType | ExcludeLaneType) != 0) {
- if ((IncludeLaneType & LANE_TYPE_ALL) == LANE_TYPE_ALL) {
- LaneBitmap = (1 << (Wrapper->EndPhyLane - Wrapper->StartPhyLane + 1)) - 1;
- if (ExcludeLaneType != 0) {
- LaneBitmap &= (~PcieUtilGetWrapperLaneBitMap (ExcludeLaneType, 0, Wrapper, Pcie));
- }
- } else {
- while (EngineList != NULL) {
- LaneBitmap |= PcieUtilGetEngineLaneBitMap (IncludeLaneType, ExcludeLaneType, EngineList, Pcie);
- EngineList = PcieLibGetNextDescriptor (EngineList);
- }
- }
- }
- return LaneBitmap;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Program port register table
- *
- *
- *
- * @param[in] Table Pointer to table
- * @param[in] Length number of entries
- * @param[in] Engine Pointer to engine config descriptor
- * @param[in] S3Save Save for S3 flag
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-
-VOID
-PciePortProgramRegisterTable (
- IN PCIE_PORT_REGISTER_ENTRY *Table,
- IN UINTN Length,
- IN PCIe_ENGINE_CONFIG *Engine,
- IN BOOLEAN S3Save,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINTN Index;
- UINT32 Value;
- for (Index = 0; Index < Length; Index++) {
- Value = PciePortRegisterRead (
- Engine,
- Table[Index].Reg,
- Pcie
- );
- Value &= (~Table[Index].Mask);
- Value |= Table[Index].Data;
- PciePortRegisterWrite (
- Engine,
- Table[Index].Reg,
- Value,
- S3Save,
- Pcie
- );
- }
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Lock registers
- *
- *
- * @param[in] Wrapper Pointer to wrapper config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-
-VOID
-PcieLockRegisters (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT8 CoreId;
- IDS_HDT_CONSOLE (GNB_TRACE, "PcieLockRegisters Enter\n");
- if (PcieLibIsPcieWrapper (Wrapper)) {
- for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
- PcieRegisterWriteField (
- Wrapper,
- CORE_SPACE (CoreId, 0x10),
- 0,
- 1,
- 0x1,
- TRUE,
- Pcie
- );
- }
- }
- IDS_HDT_CONSOLE (GNB_TRACE, "PcieLockRegisters Exit\n");
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h
deleted file mode 100644
index 5a8aa11..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe utility. Various supporting functions.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 38931 $ @e \$Date: 2010-10-01 15:50:05 -0700 (Fri, 01 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _PCIEUTILLIB_H_
-#define _PCIEUTILLIB_H_
-
-/// Core lanes
-typedef enum {
- AllCoreLanes, ///< All core lanes
- AllocatedCoreLanes, ///< Allocated core lanes
- ActiveCoreLanes, ///< Active core lanes
- HotplugCoreLanes, ///< Hot plug core lanes
- SbCoreLanes, ///< South bridge core lanes
-} CORE_LANES;
-
-/// DDI lanes
-typedef enum {
- DdiAllLanes, ///< All DDI Lanes
- DdiActiveLanes ///< Active DDI Lanes
-} DDI_LANES;
-
-BOOLEAN
-PcieUtilSearchArray (
- IN UINT8 *Buf1,
- IN UINTN Buf1Length,
- IN UINT8 *Buf2,
- IN UINTN Buf2Length
- );
-
-VOID
-PcieUtilGetLinkHwStateHistory (
- IN PCIe_ENGINE_CONFIG *Engine,
- OUT UINT8 *History,
- IN UINT8 Length,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-
-BOOLEAN
-PcieUtilIsLinkReversed (
- IN BOOLEAN HwLinkState,
- IN PCIe_ENGINE_CONFIG *Engine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-
-UINT8
-PcieUtilGetLinkWidth (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-
-UINT32
-PcieUtilGetEngineLaneBitMap (
- IN UINT32 IncludeLaneType,
- IN UINT32 ExcludeLaneType,
- IN PCIe_ENGINE_CONFIG *Engine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-UINT32
-PcieUtilGetWrapperLaneBitMap (
- IN UINT32 IncludeLaneType,
- IN UINT32 ExcludeLaneType,
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PciePortProgramRegisterTable (
- IN PCIE_PORT_REGISTER_ENTRY *Table,
- IN UINTN Length,
- IN PCIe_ENGINE_CONFIG *Engine,
- IN BOOLEAN S3Save,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PcieLockRegisters (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c
deleted file mode 100644
index f47e58e..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c
+++ /dev/null
@@ -1,291 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Supporting services to access PCIe wrapper/core/PIF/PHY indirect register spaces
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "Gnb.h"
-#include "GnbPcie.h"
-#include "GnbPcieFamServices.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1)
-#include "Filecode.h"
-#define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEWRAPPERREGACC_FILECODE
-/*----------------------------------------------------------------------------------------*/
-/**
- * Read PCIe register value.
- *
- * Support for unify register access through index/data pair on GNB
- *
- * @param[in] Wrapper Pointer to Wrapper descriptor
- * @param[in] Address Register address
- * @param[in] Pcie Pointer to global PCIe configuration
- * @retval Register Value
- */
-UINT32
-PcieRegisterRead (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN UINT32 Address,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- return PcieSiliconRegisterRead (PcieWrapperGetParentSilicon (Wrapper), Address, Pcie);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Read PCIe register value.
- *
- * Support for unify register access through index/data pair on GNB
- *
- * @param[in] Silicon Pointer to silicon descriptor
- * @param[in] Address Register address
- * @param[in] Pcie Pointer to global PCIe configuration
- * @retval Register Value
- */
-
-UINT32
-PcieSiliconRegisterRead (
- IN PCIe_SILICON_CONFIG *Silicon,
- IN UINT32 Address,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT32 Value;
- GnbLibPciWrite (Silicon->Address.AddressValue | 0xE0, AccessWidth32, &Address, GnbLibGetHeader (Pcie));
- GnbLibPciRead (Silicon->Address.AddressValue | 0xE4, AccessWidth32, &Value, GnbLibGetHeader (Pcie));
- return Value;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Write PCIe register value.
- *
- * Support for unify register access through index/data pair on GNB
- *
- * @param[in] Wrapper Pointer to wrapper descriptor
- * @param[in] Address Register address
- * @param[in] Value New register value
- * @param[in] S3Save Save register for S3 (True/False)
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-VOID
-PcieRegisterWrite (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN UINT32 Address,
- IN UINT32 Value,
- IN BOOLEAN S3Save,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- PcieSiliconRegisterWrite (
- PcieWrapperGetParentSilicon (Wrapper),
- Address,
- Value,
- S3Save,
- Pcie
- );
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Write PCIe register value.
- *
- * Support for unify register access through index/data pair on GNB
- *
- * @param[in] Silicon Pointer to silicon descriptor
- * @param[in] Address Register address
- * @param[in] Value New register value
- * @param[in] S3Save Save register for S3 (True/False)
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-VOID
-PcieSiliconRegisterWrite (
- IN PCIe_SILICON_CONFIG *Silicon,
- IN UINT32 Address,
- IN UINT32 Value,
- IN BOOLEAN S3Save,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- IDS_HDT_CONSOLE (PCIE_HOSTREG_TRACE, " *WR %s (%d:%d:%d):0x%08x = 0x%08x\n",
- PcieFmDebugGetHostRegAddressSpaceString ((UINT16) (Address >> 16)),
- Silicon->Address.Address.Bus,
- Silicon->Address.Address.Device,
- Silicon->Address.Address.Function,
- Address,
- Value
- );
- GnbLibPciWrite (Silicon->Address.AddressValue | 0xE0, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Address, GnbLibGetHeader (Pcie));
- GnbLibPciWrite (Silicon->Address.AddressValue | 0xE4, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Value, GnbLibGetHeader (Pcie));
-}
-/*----------------------------------------------------------------------------------------*/
-/**
- * Read PCIe register field.
- *
- * Support for unify register access through index/data pair on GNB
- *
- * @param[in] Wrapper Pointer to wrapper descriptor
- * @param[in] Address Register address
- * @param[in] FieldOffset Field offset
- * @param[in] FieldWidth Field width
- * @param[in] Pcie Pointer to global PCIe configuration
- * @retval Register field value
- */
-
-UINT32
-PcieRegisterReadField (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN UINT32 Address,
- IN UINT8 FieldOffset,
- IN UINT8 FieldWidth,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT32 Value;
- Value = PcieRegisterRead (Wrapper, Address, Pcie);
- Value = (Value >> FieldOffset) & (~(0xFFFFFFFF << FieldWidth));
- return Value;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Write PCIe register field.
- *
- * Support for unify register access through index/data pair on GNB
- *
- * @param[in] Wrapper Pointer to wrapper descriptor
- * @param[in] Address Register address
- * @param[in] FieldOffset Field offset
- * @param[in] FieldWidth Field width
- * @param[in] Value Value to write
- * @param[in] S3Save Save register for S3 (True/False)
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-
-
-VOID
-PcieRegisterWriteField (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN UINT32 Address,
- IN UINT8 FieldOffset,
- IN UINT8 FieldWidth,
- IN UINT32 Value,
- IN BOOLEAN S3Save,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT32 TempValue;
- UINT32 Mask;
- TempValue = PcieRegisterRead (Wrapper, Address, Pcie);
- Mask = (~(0xFFFFFFFF << FieldWidth));
- Value &= Mask;
- TempValue &= (~(Mask << FieldOffset));
- PcieRegisterWrite (Wrapper, Address, TempValue | (Value << FieldOffset), S3Save, Pcie);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Read/Modify/Write PCIe register.
- *
- * Support for unify register access through index/data pair on GNB
- *
- * @param[in] Wrapper Pointer to wrapper descriptor
- * @param[in] Address Register address
- * @param[in] AndMask Value & (~AndMask)
- * @param[in] OrMask Value | OrMask
- * @param[in] S3Save Save register for S3 (True/False)
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-
-VOID
-PcieRegisterRMW (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN UINT32 Address,
- IN UINT32 AndMask,
- IN UINT32 OrMask,
- IN BOOLEAN S3Save,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- PcieSiliconRegisterRMW (
- PcieWrapperGetParentSilicon (Wrapper),
- Address,
- AndMask,
- OrMask,
- S3Save,
- Pcie
- );
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Read/Modify/Write PCIe register.
- *
- * Support for unify register access through index/data pair on GNB
- *
- * @param[in] Silicon Pointer to silicon descriptor
- * @param[in] Address Register address
- * @param[in] AndMask Value & (~AndMask)
- * @param[in] OrMask Value | OrMask
- * @param[in] S3Save Save register for S3 (True/False)
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-
-VOID
-PcieSiliconRegisterRMW (
- IN PCIe_SILICON_CONFIG *Silicon,
- IN UINT32 Address,
- IN UINT32 AndMask,
- IN UINT32 OrMask,
- IN BOOLEAN S3Save,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT32 Value;
- Value = PcieSiliconRegisterRead (Silicon, Address, Pcie);
- Value = (Value & (~AndMask)) | OrMask;
- PcieSiliconRegisterWrite (Silicon, Address, Value, S3Save, Pcie);
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.h b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.h
deleted file mode 100644
index d022427..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Supporting services to access PCIe wrapper/core/PIF/PHY indirect register spaces
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 38931 $ @e \$Date: 2010-10-01 15:50:05 -0700 (Fri, 01 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _PCIEWRAPPERREGACC_H_
-#define _PCIEWRAPPERREGACC_H_
-
-//#define WRAP_SPACE(w, x) (0x01300000 | (w << 16) | (x))
-//#define CORE_SPACE(c, x) (0x00010000 | (c << 24) | (x))
-//#define PHY_SPACE(w, p, x) (0x00200000 | ((p + 1) << 24) | (w << 16) | (x))
-//#define PIF_SPACE(w, p, x) (0x00100000 | ((p + 1) << 24) | (w << 16) | (x))
-#define IMP_SPACE(x) (0x01080000 | (x))
-
-UINT32
-PcieRegisterRead (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN UINT32 Address,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PcieRegisterWrite (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN UINT32 Address,
- IN UINT32 Value,
- IN BOOLEAN S3Save,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-UINT32
-PcieRegisterReadField (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN UINT32 Address,
- IN UINT8 FieldOffset,
- IN UINT8 FieldWidth,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PcieRegisterWriteField (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN UINT32 Address,
- IN UINT8 FieldOffset,
- IN UINT8 FieldWidth,
- IN UINT32 Value,
- IN BOOLEAN S3Save,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PcieRegisterRMW (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN UINT32 Address,
- IN UINT32 AndMask,
- IN UINT32 OrMask,
- IN BOOLEAN S3Save,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-UINT32
-PcieSiliconRegisterRead (
- IN PCIe_SILICON_CONFIG *Silicon,
- IN UINT32 Address,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PcieSiliconRegisterWrite (
- IN PCIe_SILICON_CONFIG *Silicon,
- IN UINT32 Address,
- IN UINT32 Value,
- IN BOOLEAN S3Save,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PcieSiliconRegisterRMW (
- IN PCIe_SILICON_CONFIG *Silicon,
- IN UINT32 Address,
- IN UINT32 AndMask,
- IN UINT32 OrMask,
- IN BOOLEAN S3Save,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieTrainingV1/GnbPcieTrainingV1.h b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieTrainingV1/GnbPcieTrainingV1.h
deleted file mode 100644
index 4d897e4..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieTrainingV1/GnbPcieTrainingV1.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe training library
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _GNBPCIETRAININGV1_H_
-#define _GNBPCIETRAININGV1_H_
-
-#include "PcieTraining.h"
-#include "PcieWorkarounds.h"
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c
deleted file mode 100644
index ada2ccb..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c
+++ /dev/null
@@ -1,828 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe link training
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 38950 $ @e \$Date: 2010-10-03 23:49:09 -0700 (Sun, 03 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "amdlib.h"
-#include "GeneralServices.h"
-#include "Gnb.h"
-#include "GnbPcie.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include GNB_MODULE_DEFINITIONS (GnbPcieConfig)
-#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1)
-#include "PcieWorkarounds.h"
-#include "GnbRegistersON.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIETRAINING_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-VOID
-STATIC
-PcieTrainingDebugDumpPortState (
- IN PCIe_ENGINE_CONFIG *CurrentEngine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Set link State
- *
- *
- * @param[in] CurrentEngine Pointer to engine config descriptor
- * @param[in] State State to set
- * @param[in] UpdateTimeStamp Update time stamp
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-VOID
-PcieTrainingSetPortState (
- IN PCIe_ENGINE_CONFIG *CurrentEngine,
- IN UINT8 State,
- IN BOOLEAN UpdateTimeStamp,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT32 TimeStamp;
- CurrentEngine->Type.Port.State = State;
- if (UpdateTimeStamp) {
- TimeStamp = PcieTimerGetTimeStamp (Pcie);
- CurrentEngine->Type.Port.TimeStamp = TimeStamp;
- }
- GNB_DEBUG_CODE (
- PcieTrainingDebugDumpPortState (CurrentEngine, Pcie)
- );
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Set state for all engines connected to same reset ID
- *
- *
- *
- * @param[in] Engine Pointer to engine config descriptor
- * @param[in, out] Buffer Pointer to Reset Id
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-VOID
-PcieSetResetStateOnEngines (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN OUT VOID *Buffer,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT8 ResetId;
- ResetId = *(UINT8 *)Buffer;
- if (Engine->Type.Port.PortData.ResetId == ResetId) {
- PcieTrainingSetPortState (Engine, LinkStateResetDuration, TRUE, Pcie);
- }
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Assert GPIO port reset.
- *
- * Transition to LinkStateResetDuration state
- *
- * @param[in] CurrentEngine Pointer to engine config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-VOID
-STATIC
-PcieTrainingAssertReset (
- IN PCIe_ENGINE_CONFIG *CurrentEngine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- PCIe_SLOT_RESET_INFO ResetInfo;
- ResetInfo.ResetControl = AssertSlotReset;
- ResetInfo.ResetId = CurrentEngine->Type.Port.PortData.ResetId;
- LibAmdMemCopy (&ResetInfo.StdHeader, GnbLibGetHeader (Pcie), sizeof (AMD_CONFIG_PARAMS), GnbLibGetHeader (Pcie));
- AgesaPcieSlotResetControl (0, &ResetInfo);
- PcieConfigRunProcForAllEngines (
- DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
- PcieSetResetStateOnEngines,
- (VOID *)&CurrentEngine->Type.Port.PortData.ResetId,
- Pcie
- );
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Check for reset duration
- *
- * Transition to LinkStateResetDuration state
- *
- * @param[in] CurrentEngine Pointer to engine config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-VOID
-PcieTrainingCheckResetDuration (
- IN PCIe_ENGINE_CONFIG *CurrentEngine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT32 TimeStamp;
- TimeStamp = PcieTimerGetTimeStamp (Pcie);
- if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= Pcie->LinkGpioResetAssertionTime) {
- PcieTrainingSetPortState (CurrentEngine, LinkStateResetExit, FALSE, Pcie);
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Deassert GPIO port reset.
- *
- * Transition to LinkStateResetDuration state
- *
- * @param[in] CurrentEngine Pointer to engine config descriptor
- * @param[in] Pcie Platform configuration
- *
- */
-VOID
-PcieTrainingDeassertReset (
- IN PCIe_ENGINE_CONFIG *CurrentEngine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- PCIe_SLOT_RESET_INFO ResetInfo;
- ResetInfo.ResetControl = DeassertSlotReset;
- ResetInfo.ResetId = CurrentEngine->Type.Port.PortData.ResetId;
- LibAmdMemCopy (&ResetInfo.StdHeader, GnbLibGetHeader (Pcie), sizeof (AMD_CONFIG_PARAMS), GnbLibGetHeader (Pcie));
- AgesaPcieSlotResetControl (0, &ResetInfo);
- PcieTrainingSetPortState (CurrentEngine, LinkTrainingResetTimeout, TRUE, Pcie);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Check for after reset deassertion timeout
- *
- *
- * @param[in] CurrentEngine Pointer to engine config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-VOID
-STATIC
-PcieTrainingCheckResetTimeout (
- IN PCIe_ENGINE_CONFIG *CurrentEngine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT32 TimeStamp;
- TimeStamp = PcieTimerGetTimeStamp (Pcie);
- if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= Pcie->LinkResetToTrainingTime) {
- PcieTrainingSetPortState (CurrentEngine, LinkStateReleaseTraining, FALSE, Pcie);
- }
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Release training
- *
- *
- * @param[in] CurrentEngine Pointer to engine config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-VOID
-STATIC
-PcieTrainingRelease (
- IN PCIe_ENGINE_CONFIG *CurrentEngine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT8 LinkTrainingState;
- PcieRegisterWriteField (
- PcieEngineGetParentWrapper (CurrentEngine),
- WRAP_SPACE (PcieEngineGetParentWrapper (CurrentEngine)->WrapId, D0F0xE4_WRAP_0800_ADDRESS + 0x100 * CurrentEngine->Type.Port.PortId),
- D0F0xE4_WRAP_0800_HoldTraining_OFFSET,
- D0F0xE4_WRAP_0800_HoldTraining_WIDTH,
- 0,
- FALSE,
- Pcie
- );
- if (CurrentEngine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) {
- LinkTrainingState = LinkStateCompliance;
- } else {
- LinkTrainingState = LinkStateDetectPresence;
- }
- PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, TRUE, Pcie);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Detect presence of any EP on the link
- *
- *
- * @param[in] CurrentEngine Pointer to engine config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-
-VOID
-STATIC
-PcieTrainingDetectPresence (
- IN PCIe_ENGINE_CONFIG *CurrentEngine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT8 LinkHwStateHistory[4];
- UINT32 TimeStamp;
- PcieUtilGetLinkHwStateHistory (CurrentEngine, &LinkHwStateHistory[0], 4, Pcie);
- if (LinkHwStateHistory[0] > 4) {
- PcieTrainingSetPortState (CurrentEngine, LinkStateDetecting, TRUE, Pcie);
- return;
- }
- TimeStamp = PcieTimerGetTimeStamp (Pcie);
- if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= Pcie->LinkReceiverDetectionPooling) {
- PcieTrainingSetPortState (CurrentEngine, LinkStateDeviceNotPresent, FALSE, Pcie);
- }
-}
-
-UINT8 FailPattern1 [] = {0x2a, 0x6};
-UINT8 FailPattern2 [] = {0x2a, 0x9};
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Detect Link State
- *
- *
- * @param[in] CurrentEngine Pointer to engine config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-
-VOID
-STATIC
-PcieTrainingDetectLinkState (
- IN PCIe_ENGINE_CONFIG *CurrentEngine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT8 LinkHwStateHistory[16];
- UINT32 TimeStamp;
- UINT8 LinkTrainingState;
- PcieUtilGetLinkHwStateHistory (CurrentEngine, &LinkHwStateHistory[0], 4, Pcie);
- if (LinkHwStateHistory[0] == 0x10) {
- PcieTrainingSetPortState (CurrentEngine, LinkStateL0, FALSE, Pcie);
- return;
- };
- TimeStamp = PcieTimerGetTimeStamp (Pcie);
- if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= Pcie->LinkL0Pooling) {
- LinkTrainingState = LinkStateTrainingFail;
- PcieUtilGetLinkHwStateHistory (CurrentEngine, &LinkHwStateHistory[0], 16, Pcie);
- if (LinkHwStateHistory[0] == 0x7) {
- LinkTrainingState = LinkStateCompliance;
- } else if (PcieUtilSearchArray (LinkHwStateHistory, sizeof (LinkHwStateHistory), FailPattern1, sizeof (FailPattern1))) {
- LinkTrainingState = LinkStateBrokenLane;
- } else if (PcieUtilSearchArray (LinkHwStateHistory, sizeof (LinkHwStateHistory), FailPattern2, sizeof (FailPattern2))) {
- LinkTrainingState = LinkStateGen2Fail;
- }
- PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, FALSE, Pcie);
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Broken Lane
- *
- *
- * @param[in] CurrentEngine Pointer to engine config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-
-VOID
-PcieTrainingBrokenLine (
- IN PCIe_ENGINE_CONFIG *CurrentEngine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT8 CurrentLinkWidth;
- UINT8 LinkTrainingState;
- CurrentLinkWidth = PcieUtilGetLinkWidth (CurrentEngine, Pcie);
- if (CurrentLinkWidth < PcieConfigGetNumberOfPhyLane (CurrentEngine) && CurrentLinkWidth > 0) {
- CurrentEngine->InitStatus |= INIT_STATUS_PCIE_PORT_GEN2_RECOVERY;
- PcieTopologyReduceLinkWidth (CurrentLinkWidth, CurrentEngine, Pcie);
- LinkTrainingState = LinkStateResetAssert;
- PutEventLog (
- AGESA_WARNING,
- GNB_EVENT_BROKEN_LANE_RECOVERY,
- CurrentEngine->Type.Port.Address.AddressValue,
- 0,
- 0,
- 0,
- GnbLibGetHeader (Pcie)
- );
- } else {
- LinkTrainingState = LinkStateGen2Fail;
- }
- PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, FALSE, Pcie);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Check if link fail because device does not support Gen2
- *
- *
- * @param[in] CurrentEngine Pointer to engine config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-VOID
-PcieTrainingGen2Fail (
- IN PCIe_ENGINE_CONFIG *CurrentEngine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT8 LinkTrainingState;
- if (CurrentEngine->Type.Port.PortData.MiscControls.LinkSafeMode != PcieGen1) {
- PcieConfigUpdatePortStatus (CurrentEngine, INIT_STATUS_PCIE_PORT_GEN2_RECOVERY, 0);
- CurrentEngine->Type.Port.PortData.MiscControls.LinkSafeMode = PcieGen1;
- PcieLinkSafeMode (CurrentEngine, Pcie);
- LinkTrainingState = LinkStateResetAssert;
- PutEventLog (
- AGESA_WARNING,
- GNB_EVENT_BROKEN_LANE_RECOVERY,
- CurrentEngine->Type.Port.Address.AddressValue,
- 0,
- 0,
- 0,
- GnbLibGetHeader (Pcie)
- );
- } else {
- LinkTrainingState = LinkStateTrainingFail;
- }
- PcieTrainingSetPortState (CurrentEngine, LinkTrainingState, FALSE, Pcie);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Link in L0
- *
- *
- * @param[in] CurrentEngine Pointer to engine config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-VOID
-STATIC
-PcieCheckLinkL0 (
- IN PCIe_ENGINE_CONFIG *CurrentEngine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- PcieTrainingSetPortState (CurrentEngine, LinkStateVcoNegotiation, TRUE, Pcie);
-}
-/*----------------------------------------------------------------------------------------*/
-/**
- * Check if link fail because device does not support Gen X
- *
- *
- * @param[in] CurrentEngine Pointer to engine config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-VOID
-STATIC
-PcieTrainingCheckVcoNegotiation (
- IN PCIe_ENGINE_CONFIG *CurrentEngine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT32 TimeStamp;
- DxF0x128_STRUCT DxF0x128;
- TimeStamp = PcieTimerGetTimeStamp (Pcie);
- GnbLibPciRead (CurrentEngine->Type.Port.Address.AddressValue | DxF0x128_ADDRESS, AccessWidth32, &DxF0x128, GnbLibGetHeader (Pcie));
- if (DxF0x128.Field.VcNegotiationPending == 0) {
- UINT16 NumberOfPhyLane;
- NumberOfPhyLane = PcieConfigGetNumberOfPhyLane (CurrentEngine);
- if (Pcie->GfxCardWorkaround == GfxWorkaroundEnable && NumberOfPhyLane >= 8) {
- // Limit exposure of workaround to x8 and x16 port.
- PcieTrainingSetPortState (CurrentEngine, LinkStateGfxWorkaround, TRUE, Pcie);
- } else {
- PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingSuccess, FALSE, Pcie);
- }
- return;
- }
- if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= 1000 * 1000) {
- PcieTrainingSetPortState (CurrentEngine, LinkStateRetrain, FALSE, Pcie);
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Check if for GFX workaround condition
- *
- *
- * @param[in] CurrentEngine Pointer to engine config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-VOID
-STATIC
-PcieTrainingGfxWorkaround (
- IN PCIe_ENGINE_CONFIG *CurrentEngine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT32 TimeStamp;
- GFX_WORKAROUND_STATUS GfxWorkaroundStatus;
- TimeStamp = PcieTimerGetTimeStamp (Pcie);
-
- GfxWorkaroundStatus = PcieGfxCardWorkaround (CurrentEngine->Type.Port.Address, GnbLibGetHeader (Pcie));
- switch (GfxWorkaroundStatus) {
- case GFX_WORKAROUND_DEVICE_NOT_READY:
- if (TIMESTAMPS_DELTA (TimeStamp, CurrentEngine->Type.Port.TimeStamp) >= 1000 * 2000) {
- PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingFail, TRUE, Pcie);
- }
- break;
- case GFX_WORKAROUND_SUCCESS:
- PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingSuccess, FALSE, Pcie);
- break;
- case GFX_WORKAROUND_RESET_DEVICE:
- if (CurrentEngine->Type.Port.GfxWrkRetryCount < 5) {
- CurrentEngine->Type.Port.GfxWrkRetryCount++;
- PcieTrainingSetPortState (CurrentEngine, LinkStateResetAssert, TRUE, Pcie);
- } else {
- PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingFail, TRUE, Pcie);
- }
- break;
- default:
- ASSERT (FALSE);
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Retrain link
- *
- *
- * @param[in] CurrentEngine Pointer to engine config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-VOID
-STATIC
-PcieTrainingRetrainLink (
- IN PCIe_ENGINE_CONFIG *CurrentEngine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- PciePortRegisterWriteField (
- CurrentEngine,
- DxF0xE4_xA2_ADDRESS,
- DxF0xE4_xA2_LcReconfigNow_OFFSET,
- DxF0xE4_xA2_LcReconfigNow_WIDTH,
- 1,
- FALSE,
- Pcie
- );
- PcieTrainingSetPortState (CurrentEngine, LinkStateDetecting, TRUE, Pcie);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Training fail on this port
- *
- *
- * @param[in] CurrentEngine Pointer to engine config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-VOID
-STATIC
-PcieTrainingFail (
- IN PCIe_ENGINE_CONFIG *CurrentEngine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- PcieConfigUpdatePortStatus (CurrentEngine, INIT_STATUS_PCIE_PORT_TRAINING_FAIL, 0);
- PcieTrainingSetPortState (CurrentEngine, LinkStateDeviceNotPresent, FALSE, Pcie);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Links training success
- *
- *
- * @param[in] CurrentEngine Pointer to engine config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-
-VOID
-STATIC
-PcieTrainingSuccess (
- IN PCIe_ENGINE_CONFIG *CurrentEngine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- PcieConfigUpdatePortStatus (CurrentEngine, INIT_STATUS_PCIE_TRAINING_SUCCESS, 0);
- PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Links in compliance
- *
- *
- * @param[in] CurrentEngine Pointer to engine config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-VOID
-STATIC
-PcieTrainingCompliance (
- IN PCIe_ENGINE_CONFIG *CurrentEngine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- PcieConfigUpdatePortStatus (CurrentEngine, INIT_STATUS_PCIE_PORT_IN_COMPLIANCE, 0);
- PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * PCie EP not present
- *
- *
- * @param[in] CurrentEngine Pointer to engine config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-VOID
-STATIC
-PcieTrainingNotPresent (
- IN PCIe_ENGINE_CONFIG *CurrentEngine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- if ((CurrentEngine->Type.Port.PortData.LinkHotplug == HotplugEnhanced) || (CurrentEngine->Type.Port.PortData.LinkHotplug == HotplugServer)) {
- } else {
- PcieRegisterWriteField (
- PcieEngineGetParentWrapper (CurrentEngine),
- WRAP_SPACE (PcieEngineGetParentWrapper (CurrentEngine)->WrapId, D0F0xE4_WRAP_0800_ADDRESS + 0x100 * CurrentEngine->Type.Port.PortId),
- D0F0xE4_WRAP_0800_HoldTraining_OFFSET,
- D0F0xE4_WRAP_0800_HoldTraining_WIDTH,
- 1,
- FALSE,
- Pcie
- );
- }
- PcieTrainingSetPortState (CurrentEngine, LinkStateTrainingCompleted, FALSE, Pcie);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Final state. Port training completed.
- *
- * Initialization status recorded in PCIe_ENGINE_CONFIG.InitStatus
- *
- * @param[in] CurrentEngine Pointer to engine config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-VOID
-STATIC
-PcieTrainingCompleted (
- IN PCIe_ENGINE_CONFIG *CurrentEngine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Training state handling
- *
- *
- *
- * @param[in] Engine Pointer to engine config descriptor
- * @param[in, out] Buffer Indicate if engine in non final state
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-
-VOID
-STATIC
-PcieTrainingPortCallback (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN OUT VOID *Buffer,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- BOOLEAN *TrainingComplete;
- TrainingComplete = (BOOLEAN *) Buffer;
- if (Engine->Type.Port.State != LinkStateTrainingCompleted) {
- *TrainingComplete = FALSE;
- }
- switch (Engine->Type.Port.State) {
- case LinkStateResetAssert:
- PcieTrainingAssertReset (Engine, Pcie);
- break;
- case LinkStateResetDuration:
- PcieTrainingCheckResetDuration (Engine, Pcie);
- break;
- case LinkStateResetExit:
- PcieTrainingDeassertReset (Engine, Pcie);
- break;
- case LinkTrainingResetTimeout:
- PcieTrainingCheckResetTimeout (Engine, Pcie);
- break;
- case LinkStateReleaseTraining:
- PcieTrainingRelease (Engine, Pcie);
- break;
- case LinkStateDetectPresence:
- PcieTrainingDetectPresence (Engine, Pcie);
- break;
- case LinkStateDetecting:
- PcieTrainingDetectLinkState (Engine, Pcie);
- break;
- case LinkStateBrokenLane:
- PcieTrainingBrokenLine (Engine, Pcie);
- break;
- case LinkStateGen2Fail:
- PcieTrainingGen2Fail (Engine, Pcie);
- break;
- case LinkStateL0:
- PcieCheckLinkL0 (Engine, Pcie);
- break;
- case LinkStateVcoNegotiation:
- PcieTrainingCheckVcoNegotiation (Engine, Pcie);
- break;
- case LinkStateRetrain:
- PcieTrainingRetrainLink (Engine, Pcie);
- break;
- case LinkStateTrainingFail:
- PcieTrainingFail (Engine, Pcie);
- break;
- case LinkStateGfxWorkaround:
- PcieTrainingGfxWorkaround (Engine, Pcie);
- break;
- case LinkStateTrainingSuccess:
- PcieTrainingSuccess (Engine, Pcie);
- break;
- case LinkStateCompliance:
- PcieTrainingCompliance (Engine, Pcie);
- break;
- case LinkStateDeviceNotPresent:
- PcieTrainingNotPresent (Engine, Pcie);
- break;
- case LinkStateTrainingCompleted:
- PcieTrainingCompleted (Engine, Pcie);
- break;
- default:
- break;
- }
-
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Main link training procedure
- *
- * Port end up in three possible state LinkStateTrainingNotPresent/LinkStateCompliance/
- * LinkStateTrainingSuccess
- *
- * @param[in] Pcie Pointer to global PCIe configuration
- * @retval AGESA_STATUS
- *
- */
-
-AGESA_STATUS
-PcieTraining (
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- AGESA_STATUS Status;
- BOOLEAN TrainingComplete;
- Status = AGESA_SUCCESS;
- IDS_HDT_CONSOLE (GNB_TRACE, "PcieTraining Enter\n");
- do {
- TrainingComplete = TRUE;
- PcieConfigRunProcForAllEngines (
- DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
- PcieTrainingPortCallback,
- &TrainingComplete,
- Pcie
- );
- } while (!TrainingComplete);
- IDS_HDT_CONSOLE (GNB_TRACE, "PcieTraining Exit [%x]\n", Status);
- return Status;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Helper function to dump port state on state transition
- *
- *
- * @param[in] CurrentEngine Pointer to engine config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-
-VOID
-STATIC
-PcieTrainingDebugDumpPortState (
- IN PCIe_ENGINE_CONFIG *CurrentEngine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- IDS_HDT_CONSOLE (PCIE_MISC, " Port %d:%d:%d State [%s] Time Stamp [%d]\n",
- CurrentEngine->Type.Port.Address.Address.Bus,
- CurrentEngine->Type.Port.Address.Address.Device,
- CurrentEngine->Type.Port.Address.Address.Function,
- (CurrentEngine->Type.Port.State == LinkStateTrainingFail) ? "LinkStateTrainingFail " : (
- (CurrentEngine->Type.Port.State == LinkStateTrainingSuccess) ? "LinkStateTrainingSuccess " : (
- (CurrentEngine->Type.Port.State == LinkStateCompliance) ? "LinkStateCompliance " : (
- (CurrentEngine->Type.Port.State == LinkStateDeviceNotPresent) ? "LinkStateDeviceNotPresent" : (
- (CurrentEngine->Type.Port.State == LinkStateResetAssert) ? "LinkStateResetAssert " : (
- (CurrentEngine->Type.Port.State == LinkStateResetDuration) ? "LinkStateResetDuration " : (
- (CurrentEngine->Type.Port.State == LinkStateResetDuration) ? "LinkStateResetExit " : (
- (CurrentEngine->Type.Port.State == LinkTrainingResetTimeout) ? "LinkTrainingResetTimeout " : (
- (CurrentEngine->Type.Port.State == LinkStateReleaseTraining) ? "LinkStateReleaseTraining " : (
- (CurrentEngine->Type.Port.State == LinkStateDetectPresence) ? "LinkStateDetectPresence " : (
- (CurrentEngine->Type.Port.State == LinkStateDetecting) ? "LinkStateDetecting " : (
- (CurrentEngine->Type.Port.State == LinkStateBrokenLane) ? "LinkStateBrokenLane " : (
- (CurrentEngine->Type.Port.State == LinkStateGen2Fail) ? "LinkStateGen2Fail " : (
- (CurrentEngine->Type.Port.State == LinkStateL0) ? "LinkStateL0 " : (
- (CurrentEngine->Type.Port.State == LinkStateVcoNegotiation) ? "LinkStateVcoNegotiation " : (
- (CurrentEngine->Type.Port.State == LinkStateGfxWorkaround) ? "LinkStateGfxWorkaround " : (
- (CurrentEngine->Type.Port.State == LinkStateTrainingCompleted) ? "LinkStateTrainingComplete" : (
- (CurrentEngine->Type.Port.State == LinkStateRetrain) ? "LinkStateRetrain " : (
- (CurrentEngine->Type.Port.State == LinkStateResetExit) ? "LinkStateResetExit " : "Unknown")))))))))))))))))),
- CurrentEngine->Type.Port.TimeStamp
- );
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.h b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.h
deleted file mode 100644
index 96cb828..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe link training
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _PCIETRAINING_H_
-#define _PCIETRAINING_H_
-
-
-AGESA_STATUS
-PcieTraining (
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PcieTrainingSetPortState (
- IN PCIe_ENGINE_CONFIG *CurrentEngine,
- IN UINT8 State,
- IN BOOLEAN UpdateTimeStamp,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-#endif
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c
deleted file mode 100644
index 5191465..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c
+++ /dev/null
@@ -1,375 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Various workarounds
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 38931 $ @e \$Date: 2010-10-01 15:50:05 -0700 (Fri, 01 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "amdlib.h"
-#include "Gnb.h"
-#include "GnbPcie.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include GNB_MODULE_DEFINITIONS (GnbPcieConfig)
-#include "GnbRegistersON.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIEWORKAROUNDS_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-AGESA_STATUS
-PcieConfigureBridgeResources (
- IN PCI_ADDR Port,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-PcieFreeBridgeResources (
- IN PCI_ADDR Port,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-GFX_WORKAROUND_STATUS
-PcieDeskewWorkaround (
- IN PCI_ADDR Device,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-GFX_WORKAROUND_STATUS
-PcieNvWorkaround (
- IN PCI_ADDR Device,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-PcieProgramCpuMmio (
- OUT UINT32 *SaveValues,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-PcieRestoreCpuMmio (
- IN UINT32 *RestoreValues,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-BOOLEAN
-PcieIsDeskewCardDetected (
- IN UINT16 DeviceId
- );
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * ATI RV370/RV380 card workaround
- *
- *
- *
- * @param[in] Port PCI addreses of the port
- * @param[in] StdHeader Standard configuration header
- * @retval GFX_WORKAROUND_STATUS Return the GFX Card Workaround status
- */
-GFX_WORKAROUND_STATUS
-PcieGfxCardWorkaround (
- IN PCI_ADDR Port,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- GFX_WORKAROUND_STATUS Status;
- UINT16 DeviceId;
- UINT16 VendorId;
- UINT8 DevClassCode;
- UINT32 SaveValueData[2];
- PCI_ADDR Ep;
-
- Status = GFX_WORKAROUND_SUCCESS;
-
- Ep.AddressValue = MAKE_SBDFO (0, Port.Address.Bus + Port.Address.Device, 0, 0, 0);
- if (PcieConfigureBridgeResources (Port, StdHeader) == AGESA_SUCCESS) {
- GnbLibPciRead (Ep.AddressValue | 0x00, AccessWidth16, &DeviceId, StdHeader);
- Status = GFX_WORKAROUND_DEVICE_NOT_READY;
- if (DeviceId != 0xffff) {
- GnbLibPciRead (Ep.AddressValue | 0x02, AccessWidth16, &VendorId, StdHeader);
- if (VendorId != 0xffff) {
- GnbLibPciRead (Ep.AddressValue | 0x0B, AccessWidth8, &DevClassCode, StdHeader);
- Status = GFX_WORKAROUND_SUCCESS;
- if (DevClassCode == 3) {
- PcieProgramCpuMmio (SaveValueData, StdHeader);
- if (VendorId == 0x1002 && PcieIsDeskewCardDetected (DeviceId)) {
- Status = PcieDeskewWorkaround (Ep, StdHeader);
- } else if (VendorId == 0x10DE) {
- Status = PcieNvWorkaround (Ep, StdHeader);
- }
- PcieRestoreCpuMmio (SaveValueData, StdHeader);
- }
- }
- }
- PcieFreeBridgeResources (Port, StdHeader);
- }
- return Status;
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * RV370/RV380 Deskew workaround
- *
- *
- *
- * @param[in] Device Pcie Address of ATI RV370/RV380 card.
- * @param[in] StdHeader Standard configuration header
- */
-GFX_WORKAROUND_STATUS
-PcieDeskewWorkaround (
- IN PCI_ADDR Device,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINTN MmioBase;
- UINT16 MmioData1;
- UINT32 MmioData2;
-
- MmioBase = UserOptions.CfgTempPcieMmioBaseAddress;
- if (MmioBase == 0) {
- return GFX_WORKAROUND_SUCCESS;
- }
- GnbLibPciWrite (Device.AddressValue | 0x18, AccessWidth32, &MmioBase, StdHeader);
- GnbLibPciRMW (Device.AddressValue | 0x04, AccessWidth8 , ~BIT1, BIT1, StdHeader);
- GnbLibMemRMW (MmioBase + 0x120, AccessWidth16, 0, 0xb700, StdHeader);
- GnbLibMemRead (MmioBase + 0x120, AccessWidth16, &MmioData1, StdHeader);
- if (MmioData1 == 0xb700) {
- GnbLibMemRMW (MmioBase + 0x124, AccessWidth32, 0, 0x13, StdHeader);
- GnbLibMemRead (MmioBase + 0x124, AccessWidth32, &MmioData2, StdHeader);
- if (MmioData2 == 0x13) {
- GnbLibMemRead (MmioBase + 0x12C, AccessWidth32, &MmioData2, StdHeader);
- if (MmioData2 & BIT8) {
- return GFX_WORKAROUND_RESET_DEVICE;
- }
- }
- }
- GnbLibPciRMW (Device.AddressValue | 0x04, AccessWidth8, ~BIT1, 0x0, StdHeader);
- GnbLibPciRMW (Device.AddressValue | 0x18, AccessWidth32, 0x0, 0x0, StdHeader);
-
- return GFX_WORKAROUND_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * NV43 card workaround (lost SSID)
- *
- *
- *
- * @param[in] Device Pcie Address of NV43 card.
- * @param[in] StdHeader Standard configuration header
- */
-GFX_WORKAROUND_STATUS
-PcieNvWorkaround (
- IN PCI_ADDR Device,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 DeviceSSID;
- UINTN MmioBase;
- UINT32 MmioData3;
-
- MmioBase = UserOptions.CfgTempPcieMmioBaseAddress;
- if (MmioBase == 0) {
- return GFX_WORKAROUND_SUCCESS;
- }
- GnbLibPciRMW (Device.AddressValue | 0x30, AccessWidth32, 0x0, ((UINT32)MmioBase) | 1, StdHeader);
- GnbLibPciRMW (Device.AddressValue | 0x4, AccessWidth8, 0x0, 0x2, StdHeader);
- GnbLibPciRead (Device.AddressValue | 0x2c, AccessWidth32, &DeviceSSID, StdHeader);
- GnbLibMemRead (MmioBase + 0x54, AccessWidth32, &MmioData3, StdHeader);
- if (DeviceSSID != MmioData3) {
- GnbLibPciRMW (Device.AddressValue | 0x40, AccessWidth32, 0x0, MmioData3, StdHeader);
- }
- GnbLibPciRMW (Device.AddressValue | 0x30, AccessWidth32, 0x0, 0x0, StdHeader);
- GnbLibPciRMW (Device.AddressValue | 0x4, AccessWidth8, 0x0, 0x0, StdHeader);
- return GFX_WORKAROUND_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Allocate temporary resources for Pcie P2P bridge
- *
- *
- *
- * @param[in] Port Pci Address of Port to initialize.
- * @param[in] StdHeader Standard configuration header
- */
-AGESA_STATUS
-PcieConfigureBridgeResources (
- IN PCI_ADDR Port,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Value;
- UINT32 MmioBase;
-
- MmioBase = UserOptions.CfgTempPcieMmioBaseAddress;
- if (MmioBase == 0) {
- return AGESA_WARNING;
- }
- Value = Port.Address.Bus + ((Port.Address.Bus + Port.Address.Device) << 8) + ((Port.Address.Bus + Port.Address.Device) << 16);
- GnbLibPciWrite (Port.AddressValue | DxF0x18_ADDRESS, AccessWidth32, &Value, StdHeader);
- Value = MmioBase + (MmioBase >> 16);
- GnbLibPciWrite (Port.AddressValue | DxF0x20_ADDRESS, AccessWidth32, &Value, StdHeader);
- Value = 0x000fff0;
- GnbLibPciWrite (Port.AddressValue | DxF0x24_ADDRESS, AccessWidth32, &Value, StdHeader);
- Value = 0x2;
- GnbLibPciWrite (Port.AddressValue | DxF0x04_ADDRESS, AccessWidth8, &Value, StdHeader);
- return AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Free temporary resources for Pcie P2P bridge
- *
- *
- *
- * @param[in] Port Pci Address of Port to clear resource allocation.
- * @param[in] StdHeader Standard configuration header
- */
-VOID
-PcieFreeBridgeResources (
- IN PCI_ADDR Port,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Value;
-
- Value = 0;
- GnbLibPciWrite (Port.AddressValue | DxF0x04_ADDRESS, AccessWidth8, &Value, StdHeader);
- GnbLibPciWrite (Port.AddressValue | DxF0x18_ADDRESS, AccessWidth32, &Value, StdHeader);
- GnbLibPciWrite (Port.AddressValue | DxF0x20_ADDRESS, AccessWidth32, &Value, StdHeader);
- GnbLibPciWrite (Port.AddressValue | DxF0x24_ADDRESS, AccessWidth32, &Value, StdHeader);
-
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/*
- * Save CPU MMIO register
- *
- *
- *
- * @param[out] UINT32 SaveValues
- * @param[in] StdHeader Standard configuration header
- *
- */
-VOID
-PcieProgramCpuMmio (
- OUT UINT32 *SaveValues,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- //Save CPU MMIO Register
- GnbLibPciRead (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xB8), AccessWidth32, SaveValues, StdHeader);
- GnbLibPciRead (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xBC), AccessWidth32, SaveValues + 1, StdHeader);
-
- //Write Temp Pcie MMIO to CPU
- GnbLibPciRMW (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xBC), AccessWidth32, 0, (UserOptions.CfgTempPcieMmioBaseAddress >> 16) << 8, StdHeader);
- GnbLibPciRMW (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xB8), AccessWidth32, 0, ((UserOptions.CfgTempPcieMmioBaseAddress >> 16) << 8) | 0x3, StdHeader);
-
-}
-
-/*----------------------------------------------------------------------------------------*/
-/*
- * Restore CPU MMIO register
- *
- *
- *
- * @param[in] PCIe_PLATFORM_CONFIG Pcie
- * @param[in] StdHeader Standard configuration header
- */
-VOID
-PcieRestoreCpuMmio (
- IN UINT32 *RestoreValues,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- //Restore CPU MMIO Register
- GnbLibPciRMW (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xB8), AccessWidth32, 0, *RestoreValues, StdHeader);
- GnbLibPciRMW (MAKE_SBDFO (0, 0, 0x18, 0x1, 0xBC), AccessWidth32, 0, *(RestoreValues + 1), StdHeader);
-
-}
-
-/*----------------------------------------------------------------------------------------*/
-/*
- * Check if card required test for deskew workaround
- *
- *
- *
- * @param[in] DeviceId Device ID
- */
-
-BOOLEAN
-PcieIsDeskewCardDetected (
- IN UINT16 DeviceId
- )
-{
- if ((DeviceId >= 0x3150 && DeviceId <= 0x3152) || (DeviceId == 0x3154) ||
- (DeviceId == 0x3E50) || (DeviceId == 0x3E54) ||
- ((DeviceId & 0xfff8) == 0x5460) || ((DeviceId & 0xfff8) == 0x5B60)) {
- return TRUE;
- }
- return FALSE;
-}
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.h b/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.h
deleted file mode 100644
index da9330b..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Various workarounds
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-13 19:07:10 -0700 (Tue, 13 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _PCIEWORKAROUNDS_H_
-#define _PCIEWORKAROUNDS_H_
-
-GFX_WORKAROUND_STATUS
-PcieGfxCardWorkaround (
- IN PCI_ADDR Port,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbLclkDpm.c b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbLclkDpm.c
deleted file mode 100644
index 3c918aa..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbLclkDpm.c
+++ /dev/null
@@ -1,348 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * LCLK DPM initialization
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39007 $ @e \$Date: 2010-10-05 00:32:54 +0800 (Tue, 05 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "heapManager.h"
-#include "Gnb.h"
-#include "GnbFuseTable.h"
-#include "GnbPcie.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include GNB_MODULE_DEFINITIONS (GnbPcieConfig)
-#include "GnbRegistersON.h"
-#include "OptionGnb.h"
-#include "GfxLib.h"
-#include "NbConfigData.h"
-#include "NbSmuLib.h"
-#include "NbLclkDpm.h"
-#include "NbFamilyServices.h"
-#include "Filecode.h"
-
-#define FILECODE PROC_GNB_NB_FAMILY_0X14_F14NBLCLKDPM_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-extern GNB_BUILD_OPTIONS GnbBuildOptions;
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-UINT32 LclkDpmCacTable [] = {
- 0x0,
- 0x0,
- 0x0,
- 0x0
-};
-
-UINT32 LclkDpmActivityThresholdTable [] = {
- 0x100,
- 0x40FFFF,
- 0x40FFFF,
- 0x0
-};
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init NB LCLK DPM in Root Complex Activity mode
- *
- *
- *
- * @param[in] StdHeader Pointer to Standard configuration
- * @retval Initialization status
- */
-
-AGESA_STATUS
-NbFmInitLclkDpmRcActivity (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_STATUS Status;
- PP_FUSE_ARRAY *PpFuseArray;
- INT8 Index;
- UINTN LclkState;
- Status = AGESA_SUCCESS;
- IDS_HDT_CONSOLE (GNB_TRACE, "NbFmInitLclkDpmRcActivity F14 Enter\n");
- PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader);
- if (PpFuseArray != NULL) {
- UINT32 ActivityThreshold [8];
- UINT16 SamplingPeriod [10];
- UINT8 LclkScalingDid [4];
- UINT8 LclkScalingVid [4];
- UINT32 LclkDpmValid;
- UINT32 MainPllVcoKHz;
- LibAmdMemFill (&ActivityThreshold[0], 0, sizeof (ActivityThreshold), StdHeader);
- LibAmdMemFill (&SamplingPeriod[0], 0, sizeof (SamplingPeriod), StdHeader);
- MainPllVcoKHz = GfxLibGetMainPllFreq (StdHeader) * 100;
- LclkDpmValid = 0;
- LclkState = 7;
- for (Index = 3; Index >= 0; Index--) {
- if (PpFuseArray->LclkDpmValid [Index] != 0) {
- // Set valid DPM state
- LclkDpmValid |= (1 << (LclkState));
- // Set LCLK scaling DID
- LclkScalingDid [7 - LclkState] = PpFuseArray->LclkDpmDid [Index];
- // Set LCLK scaling VID
- LclkScalingVid [7 - LclkState] = PpFuseArray->LclkDpmVid [Index];
- // Set sampling period
- SamplingPeriod [LclkState] = 0xC350;
- // Changed from 0xC350 to 0x1388 for DPM 0
- if (Index == 0) {
- SamplingPeriod [LclkState] = 0x1388;
- }
- // Set activity threshold from BKDG:
- // Raising -- ActivityThreshold [LclkState] = ((102 * (GfxLibCalculateClk (LclkScalingDid [7 - LclkState], MainPllVcoKHz) / 100)) - 10) / 10;
- // Lowering -- ActivityThreshold [LclkState] |= (((407 * (GfxLibCalculateClk (LclkScalingDid [7 - LclkState], MainPllVcoKHz) / 100)) + 99) / 10) << 16;
- // For ON specific enable LCLK DPM :
- ActivityThreshold [LclkState] = LclkDpmActivityThresholdTable [Index];
-
- IDS_HDT_CONSOLE (GNB_TRACE, "Fused State Index:%d LCLK DPM State [%d]: LclkScalingDid - 0x%x, ActivityThreshold - 0x%x, SamplingPeriod - 0x%x\n",
- Index, LclkState, LclkScalingDid [7 - LclkState], ActivityThreshold [LclkState], SamplingPeriod [LclkState]
- );
- LclkState--;
- }
- }
- if (LclkState != 7) {
- SMUx33_STRUCT SMUx33;
- SMUx0B_x8434_STRUCT SMUx0B_x8434;
- FCRxFF30_01E4_STRUCT FCRxFF30_01E4;
- UINT8 CurrentUnit;
- UINT16 FinalUnit;
- UINT16 FinalPeriod;
- UINT32 Freq;
- UINT32 FreqDelta;
- UINT32 Value;
- ASSERT (LclkScalingDid [0] != 0);
- FreqDelta = 0xffffffff;
- FinalPeriod = 0;
- FinalUnit = 0;
- Freq = (65535 * 100 * 100) / GfxLibCalculateClk (LclkScalingDid [0], MainPllVcoKHz);
- for (CurrentUnit = 0; CurrentUnit < 16; CurrentUnit++) {
- UINT32 CurrentFreqDelta;
- UINT32 CurrentPeriod;
- UINT32 Temp;
- Temp = GnbLibPowerOf (4, CurrentUnit);
- CurrentPeriod = Freq / Temp;
- if (CurrentPeriod <= 0xFFFF) {
- CurrentFreqDelta = Freq - Temp * CurrentPeriod;
- if (FreqDelta > CurrentFreqDelta) {
- FinalUnit = CurrentUnit;
- FinalPeriod = (UINT16) CurrentPeriod;
- FreqDelta = CurrentFreqDelta;
- }
- }
- }
- //Process to enablement LCLK DPM States
- NbSmuIndirectRead (SMUx33_ADDRESS, AccessWidth32, &SMUx33.Value, StdHeader);
- SMUx33.Field.BusyCntSel = 0x3;
- SMUx33.Field.LclkActMonUnt = FinalUnit;
- SMUx33.Field.LclkActMonPrd = FinalPeriod;
- NbSmuIndirectWrite (SMUx33_ADDRESS, AccessS3SaveWidth32, &SMUx33.Value, StdHeader);
- SMUx0B_x8434.Value = 0;
- SMUx0B_x8434.Field.LclkDpmType = 0x1;
- SMUx0B_x8434.Field.LclkDpmEn = 0x1;
- SMUx0B_x8434.Field.LclkTimerPeriod = 0x0C350;
- SMUx0B_x8434.Field.LclkTimerPrescalar = 0x1;
- NbSmuRcuRegisterWrite (
- SMUx0B_x8434_ADDRESS,
- &SMUx0B_x8434.Value,
- 1,
- TRUE,
- StdHeader
- );
- NbSmuRcuRegisterWrite (
- 0x84AC,
- &LclkDpmCacTable[0],
- sizeof (LclkDpmCacTable) / sizeof (UINT32),
- TRUE,
- StdHeader
- );
- // Program activity threshold
- IDS_HDT_CONSOLE (GNB_TRACE, "ActivityThreshold[4] - 0x%x ActivityThreshold[5] - 0x%x ActivityThreshold[6] - 0x%x ActivityThreshold[7] - 0x%x\n",
- ActivityThreshold[4], ActivityThreshold[5], ActivityThreshold[6], ActivityThreshold [7]
- );
- NbSmuRcuRegisterWrite (
- SMUx0B_x8470_ADDRESS,
- &ActivityThreshold[4],
- 4,
- TRUE,
- StdHeader
- );
- // Program sampling period
- for (Index = 0; Index < (sizeof (SamplingPeriod) / sizeof (SamplingPeriod[0])); Index = Index + 2) {
- UINT16 Temp;
- Temp = SamplingPeriod[Index];
- SamplingPeriod[Index] = SamplingPeriod[Index + 1];
- SamplingPeriod[Index + 1] = Temp;
- }
- IDS_HDT_CONSOLE (GNB_TRACE, "SamplingPeriod[4] - 0x%x SamplingPeriod[5] - 0x%x SamplingPeriod[6] - 0x%x SamplingPeriod[7] - 0x%x \n",
- SamplingPeriod[4], SamplingPeriod[5], SamplingPeriod[6], SamplingPeriod[7]
- );
- NbSmuRcuRegisterWrite (
- SMUx0B_x8440_ADDRESS,
- (UINT32*) &SamplingPeriod[4],
- 2,
- TRUE,
- StdHeader
- );
- // Program LCK scaling DID
- NbSmuRcuRegisterWrite (
- SMUx0B_x848C_ADDRESS,
- (UINT32*) &LclkScalingDid[0],
- 1,
- TRUE,
- StdHeader
- );
- // Program LCK scaling VID
- NbSmuRcuRegisterWrite (
- SMUx0B_x8498_ADDRESS,
- (UINT32*) &LclkScalingVid[0],
- 1,
- TRUE,
- StdHeader
- );
- // Program valid LCLK DPM states
- LclkDpmValid = NbFmDpmStateBootupInit (LclkDpmValid, StdHeader);
- NbSmuRcuRegisterWrite (
- SMUx0B_x8490_ADDRESS,
- &LclkDpmValid,
- 1,
- TRUE,
- StdHeader
- );
- //Setup Activity Monitor Coefficients
- Value = (0x24 << SMUx35_DownTrendCoef_OFFSET) | (0x24 << SMUx35_UpTrendCoef_OFFSET);
- NbSmuIndirectWrite (SMUx35_ADDRESS, AccessS3SaveWidth32, &Value, StdHeader);
- Value = (0x22 << SMUx35_DownTrendCoef_OFFSET) | (0x22 << SMUx35_UpTrendCoef_OFFSET);
- for (Index = SMUx37_ADDRESS; Index <= SMUx51_ADDRESS; Index = Index + 2) {
- NbSmuIndirectWrite (Index, AccessS3SaveWidth32, &Value, StdHeader);
- }
- // Enable LCLK DPM as voltage client
- NbSmuSrbmRegisterRead (FCRxFF30_01E4_ADDRESS, &FCRxFF30_01E4.Value, StdHeader);
- FCRxFF30_01E4.Field.VoltageChangeEn = 0x1;
- NbSmuSrbmRegisterWrite (FCRxFF30_01E4_ADDRESS, &FCRxFF30_01E4.Value, TRUE, StdHeader);
- // Start LCLK service
- NbSmuServiceRequest (0x8, TRUE, StdHeader);
- }
- } else {
- IDS_HDT_CONSOLE (GNB_TRACE, " ERROR! Cannot locate fuse table\n");
- Status = AGESA_ERROR;
- }
- IDS_HDT_CONSOLE (GNB_TRACE, "NbFmInitLclkDpmRcActivity F14 Exit [0x%x]\n", Status);
- return Status;
-}
-
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Family specific check PsppPolicy to initially enable appropriate DPM states
- *
- *
- * @param[in] LclkDpmValid UINT32 Lclk Dpm Valid
- * @param[in] StdHeader Pointer to AMD_CONFIG_PARAMS
- */
-UINT32
-NbFmDpmStateBootupInit (
- IN UINT32 LclkDpmValid,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- PCIe_PLATFORM_CONFIG *Pcie;
- UINT32 LclkDpmValidState;
- UINT8 Dpm0ValidOffset;
-
- if ((LclkDpmValid & 0xFF) == 0) {
- IDS_HDT_CONSOLE (NB_MISC, " No valid DPM State Bootup Init\n");
- return 0;
- }
-
- // For ON, from DPM0(the most right non-zero bit) to highest DPM(bit 7)
- Dpm0ValidOffset = LibAmdBitScanForward (LclkDpmValid & 0xFF);
- // Enable DPM0
- LclkDpmValidState = 1 << Dpm0ValidOffset;
-
- if (PcieLocateConfigurationData (StdHeader, &Pcie) == AGESA_SUCCESS) {
- switch (Pcie->PsppPolicy) {
- case PsppDisabled:
- case PsppPerformance:
- case PsppBalanceHigh:
- if ((Dpm0ValidOffset + 2) <= 7) {
- // Enable DPM0 + DPM2
- LclkDpmValidState = LclkDpmValidState + (1 << (Dpm0ValidOffset + 2));
- }
- break;
- case PsppBalanceLow:
- if ((Dpm0ValidOffset + 1) <= 7) {
- // Enable DPM0 + DPM1
- LclkDpmValidState = LclkDpmValidState + (1 << (Dpm0ValidOffset + 1));
- }
- break;
- case PsppPowerSaving:
- // Enable DPM0
- break;
- default:
- ASSERT (FALSE);
- }
- } else {
- IDS_HDT_CONSOLE (NB_MISC, " DPM State Bootup Init Pcie Locate ConfigurationData Fail!! -- Enable DPM0 only\n");
- }
- return LclkDpmValidState;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbLclkNclkRatio.c b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbLclkNclkRatio.c
deleted file mode 100644
index 889fec3..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbLclkNclkRatio.c
+++ /dev/null
@@ -1,222 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * NB Lclk/Nclk Ratios
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 41658 $ @e \$Date: 2010-11-09 06:39:38 +0800 (Tue, 09 Nov 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "heapManager.h"
-#include "GnbFuseTable.h"
-#include "Gnb.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include "GfxLib.h"
-#include "GnbRegistersON.h"
-#include "F14NbLclkNclkRatio.h"
-#include "Filecode.h"
-
-#define FILECODE PROC_GNB_NB_FAMILY_0X14_F14NBLCLKNCLKRATIO_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-typedef struct {
- UINT8 NclkDiv;
- UINT8 LclkDid;
-} NLCK_SCLK;
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Power gate unused blocks
- *
- *
- *
- * @param[in] Nclk10kHz NCLK
- * @param[in] Lclk10kHz LCLK
- * @param[in] LclkNclk NCLK/LCLK array
- * @retval AGESA_STATUS
- */
-
-VOID
-STATIC
-F14NbLclkNclkAllocatePair (
- IN UINT8 NclkDiv,
- IN UINT8 LclkDid,
- IN OUT NLCK_SCLK *LclkNclk
- )
-{
- UINTN Index;
- for (Index = 0; Index < 8 ; Index++) {
- if (LclkNclk[Index].LclkDid == 0 && LclkNclk[Index].NclkDiv == 0) {
- LclkNclk[Index].LclkDid = LclkDid;
- LclkNclk[Index].NclkDiv = NclkDiv;
- break;
- } else if (LclkNclk[Index].LclkDid == LclkDid && LclkNclk[Index].NclkDiv == NclkDiv) {
- break;
- }
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Power gate unused blocks
- *
- *
- *
- * @param[in] StdHeader Pointer to Standard configuration
- * @retval AGESA_STATUS
- */
-
-AGESA_STATUS
-F14NbLclkNclkRatioFeature (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- PP_FUSE_ARRAY *PpFuseArray;
- D18F3xD4_STRUCT D18F3xD4;
- D18F3xDC_STRUCT D18F3xDC;
- D18F6x90_STRUCT D18F6x90;
- D18F6x110_STRUCT D18F6x110;
- UINT32 MainPllFreq10kHz;
- UINT8 NclkDiv[2];
- INT32 Nclk_offset;
- INT32 Lclk_offset;
- UINT8 Index;
- UINT8 LclkIndex;
- UINT32 Lclk_period;
- UINT32 Nclk_period;
- NLCK_SCLK LclkNclk [8];
- IDS_HDT_CONSOLE (GNB_TRACE, "F14NbLclkNclkRatioFeature Enter\n");
- PpFuseArray = (PP_FUSE_ARRAY *) GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader);
- ASSERT (PpFuseArray != NULL);
- if (PpFuseArray == NULL) {
- IDS_HDT_CONSOLE (GNB_TRACE, " ERROR!!! Heap Location\n");
- return AGESA_ERROR;
- }
-
- //main PLL COF in 10kHz
- MainPllFreq10kHz = GfxLibGetMainPllFreq (StdHeader) * 100;
-
- GnbLibPciRead (
- MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3xD4_ADDRESS),
- AccessWidth32,
- &D18F3xD4.Value,
- StdHeader
- );
- GnbLibPciRead (
- MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3xDC_ADDRESS),
- AccessWidth32,
- &D18F3xDC.Value,
- StdHeader
- );
- GnbLibPciRead (
- MAKE_SBDFO ( 0, 0, 0x18, 6, D18F6x90_ADDRESS),
- AccessWidth32,
- &D18F6x90.Value,
- StdHeader
- );
-
- NclkDiv[0] = (UINT8) D18F3xDC.Field.NbPs0NclkDiv;
- NclkDiv[1] = (UINT8) D18F6x90.Field.NbPs1NclkDiv;
-
- LibAmdMemFill(&LclkNclk, 0x0, sizeof (LclkNclk), StdHeader);
-
- for (Index = 0; Index < 2; Index++) {
- if (NclkDiv[Index] != 0) {
- for (LclkIndex = 0; LclkIndex < 4; LclkIndex++) {
- if ((PpFuseArray->LclkDpmValid[LclkIndex] != 0) && (PpFuseArray->LclkDpmDid[LclkIndex] != 0)) {
- F14NbLclkNclkAllocatePair (NclkDiv[Index], PpFuseArray->LclkDpmDid[LclkIndex], &LclkNclk[0]);
- }
- }
- }
- };
- for (Index = 0; Index < 8; Index++) {
- if (LclkNclk[Index].NclkDiv != 0 && LclkNclk[Index].LclkDid != 0) {
- UINT32 Nclk10kHz;
- UINT32 Lclk10kHz;
- Nclk10kHz = GfxLibCalculateNclk (LclkNclk[Index].NclkDiv, MainPllFreq10kHz);
- Lclk10kHz = GfxLibCalculateClk (LclkNclk[Index].LclkDid, MainPllFreq10kHz);
- IDS_HDT_CONSOLE (GNB_TRACE, " Offset for Nclk = %d Lclk = %d\n", Nclk10kHz / 100, Lclk10kHz / 100);
- Lclk_period = 100000000 / Lclk10kHz;
- Nclk_period = 100000000 / Nclk10kHz;
-
- if ((Nclk10kHz * 2) >= Lclk10kHz) {
- Nclk_offset = (Nclk_period * 35 - 30110) / (Lclk_period * 10);
- Lclk_offset = - 1 - (INT32) ((491 * 10 + Nclk_period * 65 + 3052 * 10 - 1) / (Lclk_period * 10) + 1);
- } else {
- Nclk_offset = - (INT32) (MIN (2 * (961 * 10 + 175 * Lclk_period + 3011 * 10 - 1) / (Nclk_period * 10) + 1,
- 2 * (961 * 10 + 165 * Lclk_period + 3011 * 10 - 1) / (Nclk_period * 10) + 1 + 1));
- Lclk_offset = MAX (2 * (35 * Lclk_period - 3052 * 10) / (Nclk_period * 10),
- 2 * (45 * Lclk_period - 3052 * 10) / (Nclk_period * 10) - 1);
- }
- Nclk_offset = Nclk_offset % 8;
- Lclk_offset = Lclk_offset % 8;
-
- D18F6x110.Field.NclkFreqType = 1;
- D18F6x110.Field.NclkFreq = LclkNclk[Index].NclkDiv;
- D18F6x110.Field.LclkFreqType = 1;
- D18F6x110.Field.LclkFreq = LclkNclk[Index].LclkDid;
- D18F6x110.Field.Enable = 1;
- D18F6x110.Field.PllMult = D18F3xD4.Field.MainPllOpFreqId + 16;
- D18F6x110.Field.LclkFifoOff = Lclk_offset & 0x7;
- D18F6x110.Field.NclkFifoOff = Nclk_offset & 0x7;
-
- GnbLibPciWrite (
- MAKE_SBDFO ( 0, 0, 0x18, 6, D18F6x110_ADDRESS + Index * 4),
- AccessS3SaveWidth32,
- &D18F6x110.Value,
- StdHeader
- );
- }
- }
- IDS_HDT_CONSOLE (GNB_TRACE, "F14NbLclkNclkRatioFeature Exit\n");
- return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbLclkNclkRatio.h b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbLclkNclkRatio.h
deleted file mode 100644
index 3a07f21..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbLclkNclkRatio.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * NB Lclk/Nclk Ratio
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _F14NBLCLKNCLKRATIO_H_
-#define _F14NBLCLKNCLKRATIO_H_
-
-AGESA_STATUS
-F14NbLclkNclkRatioFeature (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbPowerGate.c b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbPowerGate.c
deleted file mode 100644
index 8b717fb..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbPowerGate.c
+++ /dev/null
@@ -1,636 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * NB Power gate Gfx/Uvd/Gmc
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 41777 $ @e \$Date: 2010-11-10 22:29:39 +0800 (Wed, 10 Nov 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "heapManager.h"
-#include "Gnb.h"
-#include "GnbFuseTable.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include "GnbRegistersON.h"
-#include "GfxLib.h"
-#include "NbSmuLib.h"
-#include "NbConfigData.h"
-#include "NbFamilyServices.h"
-#include "GfxLib.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_NB_FAMILY_0x14_F14NBPOWERGATE_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-#define POWER_GATE_GMC_PSO_CONTROL_VALID_NUM 1
-#define POWER_GATE_GMC_MOTH_PSO_PWRUP 153
-#define POWER_GATE_GMC_MOTH_PSO_PWRDN 50
-#define POWER_GATE_GMC_DAUG_PSO_PWRUP 50
-#define POWER_GATE_GMC_DAUG_PSO_PWRDN 0
-#define POWER_GATE_GMC_RESET_TIMER 10
-#define POWER_GATE_GMC_ISO_TIMER 10
-#define POWER_GATE_GMC_SAVE_RESTORE_WIDTH 2
-#define POWER_GATE_GMC_RSO_RESTORE_TIMER 10
-#define POWER_GATE_GMCPSO_CONTROL_PERIOD_7to4 7
-#define POWER_GATE_GMCPSO_CONTROL_PERIOD_3to0 7
-
-
-#define POWER_GATE_UVD_MOTH_PSO_PWRUP 113
-#define POWER_GATE_UVD_MOTH_PSO_PWRDN 50
-#define POWER_GATE_UVD_DAUG_PSO_PWRUP 50
-#define POWER_GATE_UVD_DAUG_PSO_PWRDN 50
-#define POWER_GATE_UVD_RESET_TIMER 50
-#define POWER_GATE_UVD_ISO_TIMER 50
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-POWER_GATE_DATA F14NbGmcPowerGatingData = {
- POWER_GATE_GMC_MOTH_PSO_PWRUP,
- POWER_GATE_GMC_MOTH_PSO_PWRDN,
- POWER_GATE_GMC_DAUG_PSO_PWRUP,
- POWER_GATE_GMC_DAUG_PSO_PWRDN,
- POWER_GATE_GMC_RESET_TIMER,
- POWER_GATE_GMC_ISO_TIMER
-};
-
-/// GMC power gating
-UINT32 F14GmcPowerGatingTable_1[] = {
-// SMUx0B_x8408_ADDRESS
- 0,
-// SMUx0B_x840C_ADDRESS
- 0,
-// SMUx0B_x8410_ADDRESS
- (0x1 << SMUx0B_x8410_PwrGatingEn_OFFSET) |
- (0x0 << SMUx0B_x8410_Reserved_2_1_OFFSET) |
- (POWER_GATE_GMC_PSO_CONTROL_VALID_NUM << SMUx0B_x8410_PsoControlValidNum_OFFSET) |
- (((POWER_GATE_GMCPSO_CONTROL_PERIOD_7to4 << 4) | POWER_GATE_GMCPSO_CONTROL_PERIOD_3to0) << SMUx0B_x8410_SavePsoDelay_OFFSET) |
- (0x0 << SMUx0B_x8410_PwrGaterSel_OFFSET)
-};
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * GMC Power Gating
- *
- *
- * @param[in] StdHeader Standard Configuration Header
- * @param[in] PowerGateData Pointer power gate data
- * @retval AGESA_STATUS
- */
-
-AGESA_STATUS
-STATIC
-F14NbSmuGmcPowerGatingInit (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN POWER_GATE_DATA *PowerGateData
- )
-{
- SMUx0B_x8504_STRUCT SMUx0B_x8504;
-
- IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuGmcPowerGatingInit Enter\n");
- NbSmuRcuRegisterWrite (
- SMUx0B_x8408_ADDRESS,
- &F14GmcPowerGatingTable_1[0],
- sizeof (POWER_GATE_DATA) / sizeof (UINT32),
- TRUE,
- StdHeader
- );
-
- NbSmuRcuRegisterWrite (
- SMUx0B_x84A0_ADDRESS,
- (UINT32 *) PowerGateData,
- sizeof (POWER_GATE_DATA) / sizeof (UINT32),
- TRUE,
- StdHeader
- );
-
- SMUx0B_x8504.Value = 0;
- SMUx0B_x8504.Field.SaveRestoreWidth = POWER_GATE_GMC_SAVE_RESTORE_WIDTH;
- SMUx0B_x8504.Field.PsoRestoreTimer = POWER_GATE_GMC_RSO_RESTORE_TIMER;
- NbSmuRcuRegisterWrite (
- SMUx0B_x8504_ADDRESS,
- &SMUx0B_x8504.Value,
- 1,
- TRUE,
- StdHeader
- );
-
- NbSmuServiceRequest (0x01, TRUE, StdHeader);
- IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuGmcPowerGatingInit Exit\n");
- return AGESA_SUCCESS;
-}
-
-
-POWER_GATE_DATA F14NbUvdPowerGatingData = {
- POWER_GATE_UVD_MOTH_PSO_PWRUP,
- POWER_GATE_UVD_MOTH_PSO_PWRDN,
- POWER_GATE_UVD_DAUG_PSO_PWRUP,
- POWER_GATE_UVD_DAUG_PSO_PWRDN,
- POWER_GATE_UVD_RESET_TIMER,
- POWER_GATE_UVD_ISO_TIMER
-};
-
-/// UVD power gating
-UINT32 F14UvdPowerGatingTable_1[] = {
-// SMUx0B_x8408_ADDRESS
- 0,
-// SMUx0B_x840C_ADDRESS
- 0,
-// SMUx0B_x8410_ADDRESS
- (0x0 << SMUx0B_x8410_PwrGatingEn_OFFSET) |
- (0x0 << SMUx0B_x8410_Reserved_2_1_OFFSET) |
- (0x1 << SMUx0B_x8410_PsoControlValidNum_OFFSET) |
- (0x77 << SMUx0B_x8410_SavePsoDelay_OFFSET) |
- (0x2 << SMUx0B_x8410_PwrGaterSel_OFFSET)
-};
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * UVD Power Gating
- *
- *
- *
- * @param[in] StdHeader Standard Configuration Header
- * @param[in] PowerGateData Pointer power gate data
- *
- */
-
-
-VOID
-STATIC
-F14NbSmuUvdPowerGatingInit (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN POWER_GATE_DATA *PowerGateData
- )
-{
- SMUx0B_x8504_STRUCT SMUx0B_x8504;
-
- IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuUvdPowerGatingInit Enter\n");
- NbSmuRcuRegisterWrite (
- SMUx0B_x8408_ADDRESS,
- &F14UvdPowerGatingTable_1[0],
- sizeof (F14UvdPowerGatingTable_1) / sizeof (UINT32),
- TRUE,
- StdHeader
- );
-
- NbSmuRcuRegisterWrite (
- SMUx0B_x84A0_ADDRESS,
- (UINT32 *) PowerGateData,
- sizeof (POWER_GATE_DATA) / sizeof (UINT32),
- TRUE,
- StdHeader
- );
-
- SMUx0B_x8504.Value = 0;
- SMUx0B_x8504.Field.SaveRestoreWidth = 0x02;
- SMUx0B_x8504.Field.PsoRestoreTimer = 0x0A;
- NbSmuRcuRegisterWrite (
- SMUx0B_x8504_ADDRESS,
- &SMUx0B_x8504.Value,
- 1,
- TRUE,
- StdHeader
- );
-
- IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuUvdPowerGatingInit Exit\n");
- NbSmuServiceRequest (0x01, TRUE, StdHeader);
-}
-
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * UVD Power Shutdown
- *
- *
- *
- * @param[in] StdHeader Standard Configuration Header
- */
-
-
-VOID
-STATIC
-F14NbSmuUvdShutdown (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuUvdShutdown Enter\n");
- NbSmuServiceRequest (0x03, TRUE, StdHeader);
- IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuUvdShutdown Exit\n");
-}
-
-
-/// GMC shutdown table
-UINT32 F14SmuGmcShutdownTable_1[] = {
-// SMUx0B_x8600_ADDRESS,
- (0x3 << SMUx0B_x8600_TransactionCount_OFFSET) |
- (0x8650 << SMUx0B_x8600_MemAddr_7_0__OFFSET),
-// SMUx0B_x8604_ADDRESS,
- (0xFE << SMUx0B_x8604_Txn1MBusAddr_31_24__OFFSET) |
- (0x60 << SMUx0B_x8604_Txn1MBusAddr_23_16__OFFSET) |
- (0x14 << SMUx0B_x8604_Txn1TransferLength_7_0__OFFSET),
-// SMUx0B_x8608_ADDRESS,
- (0x03ull << SMUx0B_x8608_Txn1Tsize_OFFSET) |
- (0x01ull << SMUx0B_x8608_Txn1Overlap_OFFSET) |
- (0x01ull << SMUx0B_x8608_Txn1Mode_OFFSET) |
- (0x07ull << SMUx0B_x8608_Txn2Mbusaddr70_OFFSET),
-// SMUx0B_x860C_ADDRESS,
- (0xFE << SMUx0B_x860C_Txn2MBusAddr3124_OFFSET) |
- (0x60 << SMUx0B_x860C_Txn2MBusAddr2316_OFFSET) |
- (0x4 << SMUx0B_x860C_Txn2TransferLength70_OFFSET) |
- (0x3 << SMUx0B_x860C_Txn2Tsize_OFFSET),
-// SMUx0B_x8610_ADDRESS,
- (0x1 << SMUx0B_x8610_Txn2Overlap_OFFSET) |
- (0x1 << SMUx0B_x8610_Txn2Mode_OFFSET) |
- (0x60 << SMUx0B_x8610_Txn3MBusAddr2316_OFFSET) |
- (0x6 << SMUx0B_x8610_Txn3MBusAddr70_OFFSET),
-// SMUx0B_x8614_ADDRESS,
- (0xFEull << SMUx0B_x8614_Txn3MBusAddr3124_OFFSET) |
- (0x04ull << SMUx0B_x8614_Txn3TransferLength70_OFFSET) |
- (0x03ull << SMUx0B_x8614_Txn3Tsize_OFFSET) |
- (0x01ull << SMUx0B_x8614_Txn3Mode_OFFSET),
-};
-
-UINT32 F14SmuGmcShutdownTable_2[] = {
-// SMUx0B_x8650_ADDRESS,
- 0x76543210,
-// SMUx0B_x8654_ADDRESS,
- 0xFEDCBA98,
-// SMUx0B_x8658_ADDRESS,
- 0x8,
-// SMUx0B_x865C_ADDRESS,
- 0x00320032,
-// SMUx0B_x8660_ADDRESS,
- 0x00100010,
-// SMUx0B_x8664_ADDRESS,
- 0x00320032,
-// SMUx0B_x866C_ADDRESS,
- 0x00
-};
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Shutdown GMC
- *
- *
- *
- * @param[in] StdHeader Standard Configuration Header
- */
-
-VOID
-STATIC
-F14NbSmuGmcShutdown (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuGmcShutdown Enter\n");
- NbSmuRcuRegisterWrite (
- SMUx0B_x8600_ADDRESS,
- &F14SmuGmcShutdownTable_1[0],
- sizeof (F14SmuGmcShutdownTable_1) / sizeof (UINT32),
- TRUE,
- StdHeader
- );
-
- NbSmuRcuRegisterWrite (
- SMUx0B_x8650_ADDRESS,
- &F14SmuGmcShutdownTable_2[0],
- sizeof (F14SmuGmcShutdownTable_2) / sizeof (UINT32),
- TRUE,
- StdHeader
- );
-
- NbSmuServiceRequest (0x0B, TRUE, StdHeader);
- IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuGmcShutdown Exit\n");
-}
-
-/// GFX shutdown table
-UINT32 F14SmuGfxShutdownTable_1[] = {
-// SMUx0B_x8600_ADDRESS,
- (0x09ull << SMUx0B_x8600_TransactionCount_OFFSET) |
- (0x8650ull << SMUx0B_x8600_MemAddr_7_0__OFFSET) |
- (0x00ull << SMUx0B_x8600_Txn1MBusAddr_7_0__OFFSET),
-// SMUx0B_x8604_ADDRESS,
- (0xFEull << SMUx0B_x8604_Txn1MBusAddr_31_24__OFFSET) |
- (0x70ull << SMUx0B_x8604_Txn1MBusAddr_23_16__OFFSET) |
- (0x00ull << SMUx0B_x8604_Txn1MBusAddr_15_8__OFFSET) |
- (0x14ull << SMUx0B_x8604_Txn1TransferLength_7_0__OFFSET),
-// SMUx0B_x8608_ADDRESS,
- (0x03ull << SMUx0B_x8608_Txn1Tsize_OFFSET) |
- (0x00ull << SMUx0B_x8608_Txn1TransferLength_13_8__OFFSET) |
- (0x00ull << SMUx0B_x8608_Txn1Spare_OFFSET) |
- (0x01ull << SMUx0B_x8608_Txn1Overlap_OFFSET) |
- (0x00ull << SMUx0B_x8608_Txn1Static_OFFSET) |
- (0x01ull << SMUx0B_x8608_Txn1Mode_OFFSET) |
- (0x00ull << SMUx0B_x8608_Txn2Mbusaddr158_OFFSET) |
- (0x07ull << SMUx0B_x8608_Txn2Mbusaddr70_OFFSET),
-// SMUx0B_x860C_ADDRESS,
- (0xFEull << SMUx0B_x860C_Txn2MBusAddr3124_OFFSET) |
- (0x70ull << SMUx0B_x860C_Txn2MBusAddr2316_OFFSET) |
- (0x04ull << SMUx0B_x860C_Txn2TransferLength70_OFFSET) |
- (0x03ull << SMUx0B_x860C_Txn2Tsize_OFFSET) |
- (0x00ull << SMUx0B_x860C_Txn2TransferLength138_OFFSET),
-// SMUx0B_x8610_ADDRESS,
- (0x00ull << SMUx0B_x8610_Txn2Spare_OFFSET) |
- (0x01ull << SMUx0B_x8610_Txn2Overlap_OFFSET) |
- (0x00ull << SMUx0B_x8610_Txn2Static_OFFSET) |
- (0x01ull << SMUx0B_x8610_Txn2Mode_OFFSET) |
- (0x70ull << SMUx0B_x8610_Txn3MBusAddr2316_OFFSET) |
- (0x00ull << SMUx0B_x8610_Txn3MBusAddr158_OFFSET) |
- (0x06ull << SMUx0B_x8610_Txn3MBusAddr70_OFFSET),
-// SMUx0B_x8614_ADDRESS,
- (0xFEull << SMUx0B_x8614_Txn3MBusAddr3124_OFFSET) |
- (0x04ull << SMUx0B_x8614_Txn3TransferLength70_OFFSET) |
- (0x03ull << SMUx0B_x8614_Txn3Tsize_OFFSET) |
- (0x00ull << SMUx0B_x8614_Txn3TransferLength138_OFFSET) |
- (0x00ull << SMUx0B_x8614_Txn3Spare_OFFSET) |
- (0x00ull << SMUx0B_x8614_Txn3Overlap_OFFSET) |
- (0x00ull << SMUx0B_x8614_Txn3Static_OFFSET) |
- (0x01ull << SMUx0B_x8614_Txn3Mode_OFFSET),
-// SMUx0B_x8618_ADDRESS,
- (0xFEull << SMUx0B_x8618_Txn4MBusAddr3124_OFFSET) |
- (0xA0ull << SMUx0B_x8618_Txn4MBusAddr2316_OFFSET) |
- (0x00ull << SMUx0B_x8618_Txn4MBusAddr158_OFFSET) |
- (0x00ull << SMUx0B_x8618_Txn4MBusAddr70_OFFSET),
-// SMUx0B_x861C_ADDRESS,
- (0x07ull << SMUx0B_x861C_Txn5Mbusaddr70_OFFSET) |
- (0x14ull << SMUx0B_x861C_Txn4TransferLength70_OFFSET) |
- (0x03ull << SMUx0B_x861C_Txn4Tsize_OFFSET) |
- (0x00ull << SMUx0B_x861C_Txn4TransferLength138_OFFSET) |
- (0x00ull << SMUx0B_x861C_Txn4Spare_OFFSET) |
- (0x01ull << SMUx0B_x861C_Txn4Overlap_OFFSET) |
- (0x00ull << SMUx0B_x861C_Txn4Static_OFFSET) |
- (0x01ull << SMUx0B_x861C_Txn4Mode_OFFSET),
-// SMUx0B_x8620_ADDRESS,
- (0x00ull << SMUx0B_x8620_Txn5MBusAddr158_OFFSET) |
- (0xA0ull << SMUx0B_x8620_Txn5MBusAddr2316_OFFSET) |
- (0xFEull << SMUx0B_x8620_Txn5MBusAddr3124_OFFSET) |
- (0x04ull << SMUx0B_x8620_Txn5TransferLength70_OFFSET),
-// SMUx0B_x8624_ADDRESS,
- (0x03ull << SMUx0B_x8624_Txn5Tsize_OFFSET) |
- (0x00ull << SMUx0B_x8624_Txn5TransferLength138_OFFSET) |
- (0x00ull << SMUx0B_x8624_Txn5Spare_OFFSET) |
- (0x01ull << SMUx0B_x8624_Txn5Overlap_OFFSET) |
- (0x00ull << SMUx0B_x8624_Txn5Static_OFFSET) |
- (0x01ull << SMUx0B_x8624_Txn5Mode_OFFSET) |
- (0x00ull << SMUx0B_x8624_Txn6MBusAddr158_OFFSET) |
- (0x06ull << SMUx0B_x8624_Txn6MBusAddr70_OFFSET),
-// SMUx0B_x8628_ADDRESS,
- (0xFEull << SMUx0B_x8628_Txn6MBusAddr3124_OFFSET) |
- (0xA0ull << SMUx0B_x8628_Txn6MBusAddr2316_OFFSET) |
- (0x04ull << SMUx0B_x8628_Txn6TransferLength70_OFFSET) |
- (0x03ull << SMUx0B_x8628_Txn6Tsize_OFFSET) |
- (0x00ull << SMUx0B_x8628_Txn6TransferLength138_OFFSET),
-// SMUx0B_x862C_ADDRESS,
- (0xB0ull << SMUx0B_x862C_Txn7MBusAddr2316_OFFSET) |
- (0x00ull << SMUx0B_x862C_Txn7MBusAddr158_OFFSET) |
- (0x00ull << SMUx0B_x862C_Txn7MBusAddr70_OFFSET) |
- (0x00ull << SMUx0B_x862C_Txn6Spare_OFFSET) |
- (0x00ull << SMUx0B_x862C_Txn6Overlap_OFFSET) |
- (0x00ull << SMUx0B_x862C_Txn6Static_OFFSET) |
- (0x01ull << SMUx0B_x862C_Txn6Mode_OFFSET),
-// SMUx0B_x8630_ADDRESS,
- (0xFEull << SMUx0B_x8630_Txn7MBusAddr3124_OFFSET) |
- (0x14ull << SMUx0B_x8630_Txn7TransferLength70_OFFSET) |
- (0x03ull << SMUx0B_x8630_Txn7Tsize_OFFSET) |
- (0x00ull << SMUx0B_x8630_Txn7TransferLength138_OFFSET) |
- (0x00ull << SMUx0B_x8630_Txn7Spare_OFFSET) |
- (0x01ull << SMUx0B_x8630_Txn7Overlap_OFFSET) |
- (0x00ull << SMUx0B_x8630_Txn7Static_OFFSET) |
- (0x01ull << SMUx0B_x8630_Txn7Mode_OFFSET),
-// SMUx0B_x8634_ADDRESS,
- (0xFEull << SMUx0B_x8634_Txn8MBusAddr3124_OFFSET) |
- (0xB0ull << SMUx0B_x8634_Txn8MBusAddr2316_OFFSET) |
- (0x00ull << SMUx0B_x8634_Txn8MBusAddr158_OFFSET) |
- (0x07ull << SMUx0B_x8634_Txn8MBusAddr70_OFFSET),
-// SMUx0B_x8638_ADDRESS,
- (0x06ull << SMUx0B_x8638_Txn9MBusAddr70_OFFSET) |
- (0x04ull << SMUx0B_x8638_Txn8TransferLength70_OFFSET) |
- (0x03ull << SMUx0B_x8638_Txn8Tsize_OFFSET) |
- (0x00ull << SMUx0B_x8638_Txn8TransferLength138_OFFSET) |
- (0x00ull << SMUx0B_x8638_Txn8Spare_OFFSET) |
- (0x01ull << SMUx0B_x8638_Txn8Overlap_OFFSET) |
- (0x00ull << SMUx0B_x8638_Txn8Static_OFFSET) |
- (0x01ull << SMUx0B_x8638_Txn8Mode_OFFSET),
-// SMUx0B_x863C_ADDRESS,
- (0x00ull << SMUx0B_x863C_Txn9MBusAddr158_OFFSET) |
- (0xB0ull << SMUx0B_x863C_Txn9MBuAaddr2316_OFFSET) |
- (0xFEull << SMUx0B_x863C_Txn9MBusAddr3124_OFFSET) |
- (0x04ull << SMUx0B_x863C_Txn9TransferLength70_OFFSET),
-// SMUx0B_x8640_ADDRESS,
- (0x03ull << SMUx0B_x8640_Txn9Tsize_OFFSET) |
- (0x00ull << SMUx0B_x8640_Txn9TransferLength138_OFFSET) |
- (0x00ull << SMUx0B_x8640_Txn9Spare_OFFSET) |
- (0x00ull << SMUx0B_x8640_Txn9Overlap_OFFSET) |
- (0x00ull << SMUx0B_x8640_Txn9Static_OFFSET) |
- (0x01ull << SMUx0B_x8640_Txn9Mode_OFFSET) |
- (0x00ull << SMUx0B_x8640_Txn10MBusAddr158_OFFSET) |
- (0x00ull << SMUx0B_x8640_Txn10MBusAddr70_OFFSET)
-};
-UINT32 F14SmuGfxShutdownTable_2[] = {
-// SMUx0B_x8650_ADDRESS,
- 0x10103210,
-// SMUx0B_x8654_ADDRESS,
- 0x10101010,
-// SMUx0B_x8658_ADDRESS,
- 0x20,
-// SMUx0B_x865C_ADDRESS,
- 0x00320032,
-// SMUx0B_x8660_ADDRESS,
- 0x00100010,
-// SMUx0B_x8664_ADDRESS,
- 0x0032000A,
-// SMUx0B_x866C_ADDRESS,
- 0x00,
-// SMUx0B_x8670_ADDRESS,
- 0x10103210,
-// SMUx0B_x8674_ADDRESS,
- 0x10101010,
-// SMUx0B_x8678_ADDRESS,
- 0x20,
-// SMUx0B_x867C_ADDRESS,
- 0x00320032,
-// SMUx0B_x8680_ADDRESS,
- 0x00100010,
-// SMUx0B_x8684_ADDRESS,
- 0x00320010,
-// SMUx0B_x868C_ADDRESS,
- 0x00,
-// SMUx0B_x8690_ADDRESS,
- 0x10103210,
-// SMUx0B_x8694_ADDRESS,
- 0x10101010,
-// SMUx0B_x8698_ADDRESS,
- 0x20,
-// SMUx0B_x869C_ADDRESS,
- 0x00320032,
-// SMUx0B_x86A0_ADDRESS,
- 0x00100010,
-// SMUx0B_x86A4_ADDRESS,
- 0x00320016,
-// SMUx0B_x86AC_ADDRESS,
- 0x00
-};
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Shutdown GFX
- *
- *
- *
- * @param[in] StdHeader Standard Configuration Header
- */
-
-
-
-VOID
-STATIC
-F14NbSmuGfxShutdown (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuGfxShutdown Enter\n");
- NbSmuRcuRegisterWrite (
- SMUx0B_x8600_ADDRESS,
- &F14SmuGfxShutdownTable_1[0],
- sizeof (F14SmuGfxShutdownTable_1) / sizeof (UINT32),
- TRUE,
- StdHeader
- );
-
- NbSmuRcuRegisterWrite (
- SMUx0B_x8650_ADDRESS,
- &F14SmuGfxShutdownTable_2[0],
- sizeof (F14SmuGfxShutdownTable_2) / sizeof (UINT32),
- TRUE,
- StdHeader
- );
-
- NbSmuServiceRequest (0x0B, TRUE, StdHeader);
- IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuGfxShutdown Exit\n");
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Power gate unused blocks
- *
- *
- *
- * @param[in] StdHeader Pointer to Standard configuration
- * @retval AGESA_STATUS
- */
-
-AGESA_STATUS
-F14NbPowerGateFeature (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- NB_POWERGATE_CONFIG NbPowerGate;
- FCRxFF30_0398_STRUCT FCRxFF30_0398;
- IDS_HDT_CONSOLE (GNB_TRACE, "NbPowerGateFeature Enter\n");
-
- NbPowerGate.Services.GmcPowerGate = 0x1;
- NbPowerGate.Services.UvdPowerGate = 0x1;
- NbPowerGate.Services.GfxPowerGate = 0x1;
- LibAmdMemCopy (&NbPowerGate.Gmc, &F14NbGmcPowerGatingData, sizeof (POWER_GATE_DATA), StdHeader);
- LibAmdMemCopy (&NbPowerGate.Uvd, &F14NbUvdPowerGatingData, sizeof (POWER_GATE_DATA), StdHeader);
- IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_NB_POWERGATE_CONFIG, &NbPowerGate, StdHeader);
- F14NbSmuGmcPowerGatingInit (StdHeader, &NbPowerGate.Gmc);
- F14NbSmuUvdPowerGatingInit (StdHeader, &NbPowerGate.Uvd);
- if (!GfxLibIsControllerPresent (StdHeader)) {
- FCRxFF30_0398.Value = (1 << FCRxFF30_0398_SoftResetGrbm_OFFSET) | (1 << FCRxFF30_0398_SoftResetMc_OFFSET) |
- (1 << FCRxFF30_0398_SoftResetDc_OFFSET) | (1 << FCRxFF30_0398_SoftResetRlc_OFFSET) |
- (1 << FCRxFF30_0398_SoftResetUvd_OFFSET);
- NbSmuSrbmRegisterWrite (FCRxFF30_0398_ADDRESS, &FCRxFF30_0398.Value, TRUE, StdHeader);
- if (NbPowerGate.Services.GmcPowerGate == 1) {
- IDS_HDT_CONSOLE (GNB_TRACE, " Shutdown GMC\n");
- F14NbSmuGmcShutdown (StdHeader);
- }
- if (NbPowerGate.Services.UvdPowerGate == 1) {
- IDS_HDT_CONSOLE (GNB_TRACE, " Shutdown UVD\n");
- F14NbSmuUvdShutdown (StdHeader);
- }
- if (NbPowerGate.Services.GfxPowerGate == 1) {
- IDS_HDT_CONSOLE (GNB_TRACE, " Shutdown GFX\n");
- F14NbSmuGfxShutdown (StdHeader);
- }
- }
- IDS_HDT_CONSOLE (GNB_TRACE, "NbPowerGateFeature Exit\n");
- return AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get GMC restore latency
- *
- * Restore Latency = ((( DAUG_PSO_PWRUP + MOTH_PSO_PWRUP + PSO_RESTORE_TIMER + SAVE_RESTORE_WIDTH + PSO_CONTROL_PERIOD_7to4 +
- * ISO_TIMER + 10) * PSO_CONTROL_VALID_NUM) + RESET_TIMER ) * 10ns
- *
- * @param[in] StdHeader Pointer to Standard configuration
- * @retval AGESA_STATUS
- */
-
-UINT32
-F14NbPowerGateGmcRestoreLatency (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 RestoreLatency;
- //may need dynamic calculation
- RestoreLatency = ((POWER_GATE_GMC_DAUG_PSO_PWRUP + POWER_GATE_GMC_MOTH_PSO_PWRUP +
- POWER_GATE_GMC_SAVE_RESTORE_WIDTH + POWER_GATE_GMC_RSO_RESTORE_TIMER +
- POWER_GATE_GMCPSO_CONTROL_PERIOD_7to4 + POWER_GATE_GMC_ISO_TIMER + 10) *
- POWER_GATE_GMC_PSO_CONTROL_VALID_NUM + POWER_GATE_GMC_RESET_TIMER) * 10;
- return RestoreLatency;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbPowerGate.h b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbPowerGate.h
deleted file mode 100644
index 90c54db..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbPowerGate.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * NB Power gate Gfx/Uvd/Gmc
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _F14NBPOWERGATE_H_
-#define _F14NBPOWERGATE_H_
-
-AGESA_STATUS
-F14NbPowerGateFeature (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-
-UINT32
-F14NbPowerGateGmcRestoreLatency (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbServices.c b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbServices.c
deleted file mode 100644
index e6c7265..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbServices.c
+++ /dev/null
@@ -1,678 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Graphics Controller family specific service procedure
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 41363 $ @e \$Date: 2010-11-04 03:24:17 +0800 (Thu, 04 Nov 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Gnb.h"
-#include "GnbFuseTable.h"
-#include "GnbPcie.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include GNB_MODULE_DEFINITIONS (GnbGfxInitLibV1)
-#include GNB_MODULE_DEFINITIONS (GnbPcieConfig)
-#include "OptionGnb.h"
-#include "NbLclkDpm.h"
-#include "NbFamilyServices.h"
-#include "GfxLib.h"
-#include "GnbRegistersON.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_NB_FAMILY_0X14_F14NBSERVICES_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-extern GNB_BUILD_OPTIONS GnbBuildOptions;
-FUSE_TABLE FuseTable;
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * UnitID Clumping
- *
- *
- * @param[in] NbPciAddress
- * @param[in] StdHeader
- * @retval AGESA_STATUS
- */
-
-VOID
-NbFmClumpUnitID (
- IN PCI_ADDR NbPciAddress,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- return;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get Fuse translation table
- *
- *
- * @retval pointer to fuse translation table
- */
-
-FUSE_TABLE*
-NbFmGetFuseTranslationTable (
- VOID
- )
-{
- return &FuseTable;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Family specific fuse table patch
- * Is's correct behavior if we would have 4 states, it would be
- * PP_FUSE_ARRAY->LclkDpmDid[0] - Goes to State 5
- * PP_FUSE_ARRAY->LclkDpmDid[1] - Goes to State 6
- * PP_FUSE_ARRAY->LclkDpmDid[2] - Goes to State 7
- * If we would have 4 states it would be
- * PP_FUSE_ARRAY->LclkDpmDid[0] - Goes to State 4
- * PP_FUSE_ARRAY->LclkDpmDid[1] - Goes to State 5
- * PP_FUSE_ARRAY->LclkDpmDid[2] - Goes to State 6
- * PP_FUSE_ARRAY->LclkDpmDid[3] - Goes to State 7
- *
- * @param[in] PpFuseArray Pointer to PP_FUSE_ARRAY
- * @param[in] StdHeader Pointer to AMD_CONFIG_PARAMS
- */
-VOID
-NbFmFuseAdjustFuseTablePatch (
- IN OUT PP_FUSE_ARRAY *PpFuseArray,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 LclkDpmMode;
- UINT8 SwSatateIndex;
- UINT8 MaxSclkIndex;
- UINT8 DpmStateIndex;
- UINT8 CurrentSclkDpmDid;
- CPU_LOGICAL_ID LogicalId;
-
- LclkDpmMode = GnbBuildOptions.LclkDpmEn ? LclkDpmRcActivity : LclkDpmDisabled;
- GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
- if ((LogicalId.Revision & (AMD_F14_ON_A0 | AMD_F14_ON_A1)) != 0) {
- LclkDpmMode = LclkDpmDisabled;
- }
- IDS_OPTION_HOOK (IDS_GNB_LCLK_DPM_EN, &LclkDpmMode, StdHeader);
-
- //For all CPU rev LclkDpmValid[3] = 0
- PpFuseArray->LclkDpmValid[3] = 0;
- PpFuseArray->LclkDpmVid[3] = 0;
- PpFuseArray->LclkDpmDid[3] = 0;
-
- // For LCLKDPM set LclkDpmVid[0] = 0, no matter if LCLK DMP enable or disable.
- PpFuseArray->LclkDpmVid[0] = 0;
-
- if (LclkDpmMode != LclkDpmRcActivity) {
- //If LCLK DPM disable (LclkDpmMode != LclkDpmRcActivity)
- // - LclkDpmDid[1,2] = LclkDpmDid [0], LclkDpmVid[1,2] = LclkDpmVid[0]
- // - Execute LCLK DPM init
-
- PpFuseArray->LclkDpmVid[1] = PpFuseArray->LclkDpmVid[0];
- PpFuseArray->LclkDpmVid[2] = PpFuseArray->LclkDpmVid[0];
- PpFuseArray->LclkDpmDid[1] = PpFuseArray->LclkDpmDid[0];
- PpFuseArray->LclkDpmDid[2] = PpFuseArray->LclkDpmDid[0];
- IDS_HDT_CONSOLE (NB_MISC, " F14 LCLK DPM Mode Disable -- use DPM0 fusing\n");
-
- } else {
- // If LCLK DPM enabled
- // - use fused values for LclkDpmDid[0,1,2] and appropriate voltage
- // - Execute LCLK DPM init
- PpFuseArray->LclkDpmVid[2] = PpFuseArray->PcieGen2Vid;
- if (GfxLibIsControllerPresent (StdHeader)) {
- //VID index = VID index associated with highest SCLK DPM state in the Powerplay state where Label_Performance=1 // This would ignore the UVD case (where Label_Performance would be 0).
- for (SwSatateIndex = 0 ; SwSatateIndex < PP_FUSE_MAX_NUM_SW_STATE; SwSatateIndex++) {
- if (PpFuseArray->PolicyLabel[SwSatateIndex] == 1) {
- break;
- }
- }
- MaxSclkIndex = 0;
- CurrentSclkDpmDid = 0xff;
- ASSERT (PpFuseArray->SclkDpmValid[SwSatateIndex] != 0);
- for (DpmStateIndex = 0; DpmStateIndex < PP_FUSE_MAX_NUM_DPM_STATE; DpmStateIndex++) {
- if ((PpFuseArray->SclkDpmValid[SwSatateIndex] & (1 << DpmStateIndex)) != 0) {
- if (PpFuseArray->SclkDpmDid[DpmStateIndex] < CurrentSclkDpmDid) {
- CurrentSclkDpmDid = PpFuseArray->SclkDpmDid[DpmStateIndex];
- MaxSclkIndex = DpmStateIndex;
- }
- }
- }
- PpFuseArray->LclkDpmVid[1] = PpFuseArray->SclkDpmVid[MaxSclkIndex];
- } else {
- PpFuseArray->LclkDpmVid[1] = PpFuseArray->LclkDpmVid[0];
- PpFuseArray->LclkDpmDid[1] = PpFuseArray->LclkDpmDid[0];
- }
- // - use fused values for LclkDpmDid[0,1,2] and appropriate voltage
- //Keep using actual fusing
- IDS_HDT_CONSOLE (NB_MISC, " LCLK DPM use actaul fusing.\n");
- }
-
-}
-
-
-/*----------------------------------------------------------------------------------------
- * FUSE translation table
- *----------------------------------------------------------------------------------------
- */
-
-FUSE_REGISTER_ENTRY FCRxFE00_600E_TABLE [] = {
- {
- FCRxFE00_600E_MainPllOpFreqIdStartup_OFFSET,
- FCRxFE00_600E_MainPllOpFreqIdStartup_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, MainPllId)
- },
- {
- FCRxFE00_600E_WrCkDid_OFFSET,
- FCRxFE00_600E_WrCkDid_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, WrCkDid)
- }
-};
-
-FUSE_REGISTER_ENTRY FCRxFE00_70A2_TABLE [] = {
- {
- FCRxFE00_70A2_PPlayTableRev_OFFSET,
- FCRxFE00_70A2_PPlayTableRev_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, PPlayTableRev)
- },
- {
- FCRxFE00_70A2_SclkThermDid_OFFSET,
- FCRxFE00_70A2_SclkThermDid_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, SclkThermDid)
- },
- {
- FCRxFE00_70A2_PcieGen2Vid_OFFSET,
- FCRxFE00_70A2_PcieGen2Vid_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, PcieGen2Vid)
- }
-};
-
-FUSE_REGISTER_ENTRY FCRxFE00_70A4_TABLE [] = {
- {
- FCRxFE00_70A4_SclkDpmVid0_OFFSET,
- FCRxFE00_70A4_SclkDpmVid0_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmVid[0])
- },
- {
- FCRxFE00_70A4_SclkDpmVid1_OFFSET,
- FCRxFE00_70A4_SclkDpmVid1_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmVid[1])
- },
- {
- FCRxFE00_70A4_SclkDpmVid2_OFFSET,
- FCRxFE00_70A4_SclkDpmVid2_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmVid[2])
- },
- {
- FCRxFE00_70A4_SclkDpmVid3_OFFSET,
- FCRxFE00_70A4_SclkDpmVid3_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmVid[3])
- },
- {
- FCRxFE00_70A4_SclkDpmVid4_OFFSET,
- FCRxFE00_70A4_SclkDpmVid4_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmVid[4])
- },
-};
-
-FUSE_REGISTER_ENTRY FCRxFE00_70A5_TABLE [] = {
- {
- FCRxFE00_70A5_SclkDpmDid0_OFFSET,
- FCRxFE00_70A5_SclkDpmDid0_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmDid[0])
- },
- {
- FCRxFE00_70A5_SclkDpmDid1_OFFSET,
- FCRxFE00_70A5_SclkDpmDid1_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmDid[1])
- },
- {
- FCRxFE00_70A5_SclkDpmDid2_OFFSET,
- FCRxFE00_70A5_SclkDpmDid2_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmDid[2])
- }
-};
-
-FUSE_REGISTER_ENTRY FCRxFE00_70A8_TABLE [] = {
- {
- FCRxFE00_70A8_SclkDpmDid3_OFFSET,
- FCRxFE00_70A8_SclkDpmDid3_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmDid[3])
- },
- {
- FCRxFE00_70A8_SclkDpmDid4_OFFSET,
- FCRxFE00_70A8_SclkDpmDid4_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmDid[4])
- }
-};
-
-FUSE_REGISTER_ENTRY FCRxFE00_70AA_TABLE [] = {
- {
- FCRxFE00_70AA_SclkDpmCacBase_OFFSET,
- FCRxFE00_70AA_SclkDpmCacBase_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmCac[4])
- }
-};
-
-
-FUSE_REGISTER_ENTRY FCRxFE00_70AE_TABLE [] = {
- {
- FCRxFE00_70AE_DispClkDid0_OFFSET,
- FCRxFE00_70AE_DispClkDid0_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, DisplclkDid[0])
- },
- {
- FCRxFE00_70AE_DispClkDid1_OFFSET,
- FCRxFE00_70AE_DispClkDid1_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, DisplclkDid[1])
- },
- {
- FCRxFE00_70AE_DispClkDid2_OFFSET,
- FCRxFE00_70AE_DispClkDid2_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, DisplclkDid[2])
- },
- {
- FCRxFE00_70AE_DispClkDid3_OFFSET,
- FCRxFE00_70AE_DispClkDid3_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, DisplclkDid[3])
- }
-};
-
-FUSE_REGISTER_ENTRY FCRxFE00_70B1_TABLE [] = {
- {
- FCRxFE00_70B1_LclkDpmDid0_OFFSET,
- FCRxFE00_70B1_LclkDpmDid0_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmDid[0])
- },
- {
- FCRxFE00_70B1_LclkDpmDid1_OFFSET,
- FCRxFE00_70B1_LclkDpmDid1_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmDid[1])
- },
- {
- FCRxFE00_70B1_LclkDpmDid2_OFFSET,
- FCRxFE00_70B1_LclkDpmDid2_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmDid[2])
- }
-};
-
-FUSE_REGISTER_ENTRY FCRxFE00_70B4_TABLE [] = {
- {
- FCRxFE00_70B4_LclkDpmDid3_OFFSET,
- FCRxFE00_70B4_LclkDpmDid3_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmDid[3])
- },
- {
- FCRxFE00_70B4_LclkDpmValid0_OFFSET,
- FCRxFE00_70B4_LclkDpmValid0_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmValid[0])
- },
- {
- FCRxFE00_70B4_LclkDpmValid1_OFFSET,
- FCRxFE00_70B4_LclkDpmValid1_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmValid[1])
- },
- {
- FCRxFE00_70B4_LclkDpmValid2_OFFSET,
- FCRxFE00_70B4_LclkDpmValid2_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmValid[2])
- },
- {
- FCRxFE00_70B4_LclkDpmValid3_OFFSET,
- FCRxFE00_70B4_LclkDpmValid3_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, LclkDpmValid[3])
- }
-};
-
-FUSE_REGISTER_ENTRY FCRxFE00_70B5_TABLE [] = {
- {
- FCRxFE00_70B5_DclkDid0_OFFSET,
- FCRxFE00_70B5_DclkDid0_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, DclkDid[0])
- },
- {
- FCRxFE00_70B5_DclkDid1_OFFSET,
- FCRxFE00_70B5_DclkDid1_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, DclkDid[1])
- },
- {
- FCRxFE00_70B5_DclkDid2_OFFSET,
- FCRxFE00_70B5_DclkDid2_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, DclkDid[2])
- }
-};
-
-FUSE_REGISTER_ENTRY FCRxFE00_70B8_TABLE [] = {
- {
- FCRxFE00_70B8_DclkDid3_OFFSET,
- FCRxFE00_70B8_DclkDid3_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, DclkDid[3])
- }
-};
-
-FUSE_REGISTER_ENTRY FCRxFE00_70B9_TABLE [] = {
- {
- FCRxFE00_70B9_VclkDid0_OFFSET,
- FCRxFE00_70B9_VclkDid0_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, VclkDid[0])
- },
- {
- FCRxFE00_70B9_VclkDid1_OFFSET,
- FCRxFE00_70B9_VclkDid1_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, VclkDid[1])
- },
- {
- FCRxFE00_70B9_VclkDid2_OFFSET,
- FCRxFE00_70B9_VclkDid2_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, VclkDid[2])
- },
- {
- FCRxFE00_70B9_VclkDid3_OFFSET,
- FCRxFE00_70B9_VclkDid3_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, VclkDid[3])
- }
-};
-
-
-FUSE_REGISTER_ENTRY FCRxFE00_70BC_TABLE [] = {
- {
- FCRxFE00_70BC_SclkDpmValid0_OFFSET,
- FCRxFE00_70BC_SclkDpmValid0_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmValid[0])
- },
- {
- FCRxFE00_70BC_SclkDpmValid1_OFFSET,
- FCRxFE00_70BC_SclkDpmValid1_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmValid[1])
- },
- {
- FCRxFE00_70BC_SclkDpmValid2_OFFSET,
- FCRxFE00_70BC_SclkDpmValid2_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmValid[2])
- },
- {
- FCRxFE00_70BC_SclkDpmValid3_OFFSET,
- FCRxFE00_70BC_SclkDpmValid3_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmValid[3])
- },
- {
- FCRxFE00_70BC_SclkDpmValid4_OFFSET,
- FCRxFE00_70BC_SclkDpmValid4_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmValid[4])
- }
-};
-
-FUSE_REGISTER_ENTRY FCRxFE00_70BF_TABLE [] = {
- {
- FCRxFE00_70BF_SclkDpmValid5_OFFSET,
- FCRxFE00_70BF_SclkDpmValid5_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, SclkDpmValid[5])
- }
-};
-
-FUSE_REGISTER_ENTRY FCRxFE00_70C0_TABLE [] = {
- {
- FCRxFE00_70C0_PolicyLabel0_OFFSET,
- FCRxFE00_70C0_PolicyLabel0_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, PolicyLabel[0])
- },
- {
- FCRxFE00_70C0_PolicyLabel1_OFFSET,
- FCRxFE00_70C0_PolicyLabel1_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, PolicyLabel[1])
- },
- {
- FCRxFE00_70C0_PolicyLabel2_OFFSET,
- FCRxFE00_70C0_PolicyLabel2_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, PolicyLabel[2])
- },
- {
- FCRxFE00_70C0_PolicyLabel3_OFFSET,
- FCRxFE00_70C0_PolicyLabel3_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, PolicyLabel[3])
- },
- {
- FCRxFE00_70C0_PolicyLabel4_OFFSET,
- FCRxFE00_70C0_PolicyLabel4_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, PolicyLabel[4])
- },
- {
- FCRxFE00_70C0_PolicyLabel5_OFFSET,
- FCRxFE00_70C0_PolicyLabel5_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, PolicyLabel[5])
- }
-};
-
-FUSE_REGISTER_ENTRY FCRxFE00_70C1_TABLE [] = {
- {
- FCRxFE00_70C1_PolicyFlags0_OFFSET,
- FCRxFE00_70C1_PolicyFlags0_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, PolicyFlags[0])
- },
- {
- FCRxFE00_70C1_PolicyFlags1_OFFSET,
- FCRxFE00_70C1_PolicyFlags1_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, PolicyFlags[1])
- },
- {
- FCRxFE00_70C1_PolicyFlags2_OFFSET,
- FCRxFE00_70C1_PolicyFlags2_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, PolicyFlags[2])
- }
-};
-
-FUSE_REGISTER_ENTRY FCRxFE00_70C4_TABLE [] = {
- {
- FCRxFE00_70C4_PolicyFlags3_OFFSET,
- FCRxFE00_70C4_PolicyFlags3_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, PolicyFlags[3])
- },
- {
- FCRxFE00_70C4_PolicyFlags4_OFFSET,
- FCRxFE00_70C4_PolicyFlags4_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, PolicyFlags[4])
- },
- {
- FCRxFE00_70C4_PolicyFlags5_OFFSET,
- FCRxFE00_70C4_PolicyFlags5_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, PolicyFlags[5])
- }
-};
-
-
-FUSE_REGISTER_ENTRY FCRxFE00_70C7_TABLE [] = {
- {
- FCRxFE00_70C7_DclkVclkSel0_OFFSET,
- FCRxFE00_70C7_DclkVclkSel0_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, VclkDclkSel[0])
- },
- {
- FCRxFE00_70C7_DclkVclkSel1_OFFSET,
- FCRxFE00_70C7_DclkVclkSel1_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, VclkDclkSel[1])
- },
- {
- FCRxFE00_70C7_DclkVclkSel2_OFFSET,
- FCRxFE00_70C7_DclkVclkSel2_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, VclkDclkSel[2])
- },
- {
- FCRxFE00_70C7_DclkVclkSel3_OFFSET,
- FCRxFE00_70C7_DclkVclkSel3_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, VclkDclkSel[3])
- },
-
- {
- FCRxFE00_70C7_DclkVclkSel4_OFFSET,
- FCRxFE00_70C7_DclkVclkSel4_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, VclkDclkSel[4])
- },
- {
- FCRxFE00_70C7_DclkVclkSel5_OFFSET,
- FCRxFE00_70C7_DclkVclkSel5_WIDTH,
- (UINT8) offsetof (PP_FUSE_ARRAY, VclkDclkSel[5])
- },
-};
-
-
-
-
-FUSE_TABLE_ENTRY FuseRegisterTable [] = {
- {
- FCRxFE00_70A2_ADDRESS,
- sizeof (FCRxFE00_70A2_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
- FCRxFE00_70A2_TABLE
- },
- {
- FCRxFE00_70A4_ADDRESS,
- sizeof (FCRxFE00_70A4_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
- FCRxFE00_70A4_TABLE
- },
- {
- FCRxFE00_70A5_ADDRESS,
- sizeof (FCRxFE00_70A5_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
- FCRxFE00_70A5_TABLE
- },
- {
- FCRxFE00_70A8_ADDRESS,
- sizeof (FCRxFE00_70A8_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
- FCRxFE00_70A8_TABLE
- },
- {
- FCRxFE00_600E_ADDRESS,
- sizeof (FCRxFE00_600E_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
- FCRxFE00_600E_TABLE
- },
- {
- FCRxFE00_70AA_ADDRESS,
- sizeof (FCRxFE00_70AA_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
- FCRxFE00_70AA_TABLE
- },
- {
- FCRxFE00_70AE_ADDRESS,
- sizeof (FCRxFE00_70AE_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
- FCRxFE00_70AE_TABLE
- },
- {
- FCRxFE00_70B1_ADDRESS,
- sizeof (FCRxFE00_70B1_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
- FCRxFE00_70B1_TABLE
- },
- {
- FCRxFE00_70B4_ADDRESS,
- sizeof (FCRxFE00_70B4_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
- FCRxFE00_70B4_TABLE
- },
- {
- FCRxFE00_70B5_ADDRESS,
- sizeof (FCRxFE00_70B5_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
- FCRxFE00_70B5_TABLE
- },
- {
- FCRxFE00_70B8_ADDRESS,
- sizeof (FCRxFE00_70B8_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
- FCRxFE00_70B8_TABLE
- },
- {
- FCRxFE00_70B9_ADDRESS,
- sizeof (FCRxFE00_70B9_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
- FCRxFE00_70B9_TABLE
- },
- {
- FCRxFE00_70BC_ADDRESS,
- sizeof (FCRxFE00_70BC_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
- FCRxFE00_70BC_TABLE
- },
- {
- FCRxFE00_70BF_ADDRESS,
- sizeof (FCRxFE00_70BF_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
- FCRxFE00_70BF_TABLE
- },
- {
- FCRxFE00_70C0_ADDRESS,
- sizeof (FCRxFE00_70C0_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
- FCRxFE00_70C0_TABLE
- },
- {
- FCRxFE00_70C1_ADDRESS,
- sizeof (FCRxFE00_70C1_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
- FCRxFE00_70C1_TABLE
- },
- {
- FCRxFE00_70C4_ADDRESS,
- sizeof (FCRxFE00_70C4_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
- FCRxFE00_70C4_TABLE
- },
- {
- FCRxFE00_70C7_ADDRESS,
- sizeof (FCRxFE00_70C7_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
- FCRxFE00_70C7_TABLE
- },
-
-};
-
-FUSE_TABLE FuseTable = {
- sizeof (FuseRegisterTable) / sizeof (FUSE_TABLE_ENTRY),
- FuseRegisterTable
-};
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbSmu.c b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbSmu.c
deleted file mode 100644
index 014e1a3..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbSmu.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * SMU initialization
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Gnb.h"
-#include "NbSmuLib.h"
-#include "F14NbSmuFirmware.h"
-#include "Filecode.h"
-
-#define FILECODE PROC_GNB_NB_FAMILY_0X14_F14NBSMU_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * SMU Initialize
- *
- *
- *
- * @param[in] StdHeader Pointer to Standard configuration
- * @retval AGESA_STATUS
- */
-
-AGESA_STATUS
-F14NbSmuInitFeature (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- SMU_FIRMWARE_REV Revision;
- IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuInitFeature Enter\n");
- Revision = NbSmuFirmwareRevision (StdHeader);
- IDS_HDT_CONSOLE (NB_MISC, " Current SMU firmware rev %d.%x\n", Revision.MajorRev, Revision.MinorRev);
- IDS_HDT_CONSOLE (NB_MISC, " New SMU firmware rev %d.%x\n", Fm.Revision.MajorRev, Fm.Revision.MinorRev);
- if ((Revision.MajorRev < Fm.Revision.MajorRev) || (Revision.MajorRev == Fm.Revision.MajorRev && Revision.MinorRev < Fm.Revision.MinorRev)) {
- IDS_HDT_CONSOLE (NB_MISC, " Updating SMU firmware\n");
- NbSmuFirmwareDownload (&Fm, StdHeader);
- }
- IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuInitFeature Exit\n");
- return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbSmuFirmware.h b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbSmuFirmware.h
deleted file mode 100644
index 80e6830..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbSmuFirmware.h
+++ /dev/null
@@ -1,981 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * SMU firmware.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 37675 $ @e \$Date: 2010-09-09 22:33:48 +0800 (Thu, 09 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-#ifndef _F14NBSMUFIRMWARE_H_
-#define _F14NBSMUFIRMWARE_H_
-
-UINT32 DataBlock0[] = {
- 0x00020100,
- 0xbdff018e,
- 0x00ce3d9d,
- 0x00ce1810,
- 0xa6082000,
- 0x00a71800,
- 0x8c081808,
- 0xf3251000,
- 0x270000cc,
- 0xda9dce0b,
- 0x8308006f,
- 0xf8260100,
- 0x9dbd248d,
- 0x90fb2040,
- 0xde20900a,
- 0x02de3c00,
- 0x3c04de3c,
- 0x9f3c06de,
- 0x06df3806,
- 0x3804df38,
- 0xdf3802df,
- 0x06de3b00,
- 0xce069f3c,
- 0x90fc0c83,
- 0xfc02ed02,
- 0x00ed0090,
- 0x1caa7fce,
- 0x82ce0300,
- 0x3191ccda,
- 0x82ce00ed,
- 0x5d91cce2,
- 0x82ce00ed,
- 0x5b94cce4,
- 0x82ce00ed,
- 0x699bcce6,
- 0x82ce00ed,
- 0x2891cce8,
- 0x82ce00ed,
- 0xce00edea,
- 0x00edec82,
- 0xedee82ce,
- 0xf082ce00,
- 0x82ce00ed,
- 0xce00edf2,
- 0x93ccf482,
- 0xce00ed9d,
- 0x9accf682,
- 0xce00ed3c,
- 0x91ccf882,
- 0xce00edb5,
- 0x91ccfa82,
- 0xbd00edf8,
- 0x82ce349b,
- 0x6698cc9a,
- 0xce0e00ed,
- 0x01c6ed84,
- 0x02c600e7,
- 0x9dcc00e7,
- 0x659dfd44,
- 0xcfa09dfd,
- 0x00defd20,
- 0x3c02de3c,
- 0xde3c04de,
- 0x069f3c06,
- 0x3806df38,
- 0xdf3804df,
- 0x00df3802,
- 0x3c00de3b,
- 0xde3c02de,
- 0x06de3c04,
- 0x38069f3c,
- 0xdf3806df,
- 0x02df3804,
- 0x3b00df38,
- 0x9f3c06de,
- 0x06df3806,
- 0x3c06de39,
- 0x7ece069f,
- 0xe7dfc601,
- 0x647ece00,
- 0xed02ffcc,
- 0x627ece00,
- 0xed0086cc,
- 0x017ece00,
- 0x20c400e6,
- 0x95bdf727,
- 0x06df3801,
- 0x3c06de39,
- 0x85ce069f,
- 0xce00e607,
- 0x8c4f0000,
- 0x06260000,
- 0x0100831a,
- 0x008c2d27,
- 0x2b362e00,
- 0x00831a34,
- 0x8c0b2201,
- 0x29260000,
- 0x0f2700dd,
- 0x008c2320,
- 0x1a1e2600,
- 0x27020083,
- 0xcc162012,
- 0x95bd0885,
- 0xcc0e2029,
- 0x95bd3085,
- 0xcc062029,
- 0x95bd5885,
- 0x06df3829,
- 0x3c06de39,
- 0x08de069f,
- 0x3c0ade3c,
- 0x1daa7fce,
- 0x7fce0100,
- 0x10001c8f,
- 0x6b8d1bc6,
- 0x36377f84,
- 0x92bd1bc6,
- 0x8d04c6f7,
- 0x8f7fce5e,
- 0xce10001d,
- 0x001daa7f,
- 0x01001c01,
- 0xdf383131,
- 0x08df380a,
- 0x3906df38,
- 0x9f3c06de,
- 0x3c08de06,
- 0xce3c0ade,
- 0x001daa7f,
- 0x8f7fce01,
- 0xc610001c,
- 0x8a288d1b,
- 0xc6363780,
- 0xf792bd1b,
- 0x1b8d04c6,
- 0x1d8f7fce,
- 0x7fce1000,
- 0x01001daa,
- 0x3101001c,
- 0x0adf3831,
- 0x3808df38,
- 0xde3906df,
- 0x069f3c06,
- 0xde3c08de,
- 0x0cde3c0a,
- 0x3c0ede3c,
- 0x00cc0dd7,
- 0x4f36374d,
- 0xcc36375f,
- 0x02ce6000,
- 0x3697bd00,
- 0xce6400cc,
- 0x97bd0002,
- 0xcc08df14,
- 0x3637cd00,
- 0x36375f4f,
- 0xce6000cc,
- 0x97bd0002,
- 0xd68f1836,
- 0x188f180d,
- 0x007f0edf,
- 0xdd0edc0e,
- 0x0f007f0c,
- 0x180e007f,
- 0x18381838,
- 0xdc381838,
- 0x26018508,
- 0x8f0cde08,
- 0xdf8f018a,
- 0x370edc0c,
- 0x370cdc36,
- 0x6400cc36,
- 0xbd0002ce,
- 0x00cc3697,
- 0x4f36374e,
- 0xcc36375f,
- 0x02ce6000,
- 0x3697bd00,
- 0xce6400cc,
- 0x97bd0002,
- 0x18381814,
- 0x18381838,
- 0x18381838,
- 0x38180edf,
- 0x180cdf18,
- 0x0adf1838,
- 0xdf183818,
- 0x18381808,
- 0xde3906df,
- 0x069f3c06,
- 0xde3c08de,
- 0x0cde3c0a,
- 0x3c0ede3c,
- 0x00cc0dd7,
- 0x4f36374d,
- 0xcc36375f,
- 0x02ce6000,
- 0x3697bd00,
- 0xce6400cc,
- 0x97bd0002,
- 0xcc08df14,
- 0x3637cd00,
- 0x36375f4f,
- 0xce6000cc,
- 0x97bd0002,
- 0xd68f1836,
- 0x188f180d,
- 0x007f0edf,
- 0x0d007f0e,
- 0x4f0c007f,
- 0x0002ce5f,
- 0xda0e9a8f,
- 0x0edd8f0f,
- 0x06de0cdf,
- 0x0e9a05ec,
- 0x0cde0fda,
- 0x38180edd,
- 0x38183818,
- 0x08dc3818,
- 0x06260185,
- 0x8f018a8f,
- 0x0edc0cdf,
- 0x0cdc3637,
- 0x00cc3637,
- 0x0002ce64,
- 0x383697bd,
- 0x0edf3838,
- 0x380cdf38,
- 0xdf380adf,
- 0x06df3808,
- 0x3c06de39,
- 0x08de069f,
- 0x3c0ade3c,
- 0xde3c0cde,
- 0x85ce3c0e,
- 0xdd02ec90,
- 0xdd00ec0e,
- 0x5f0edc0c,
- 0x04caf084,
- 0x0edd0e8a,
- 0x1daa7fce,
- 0x0cde0100,
- 0xdd7196bd,
- 0xce08df0a,
- 0x00e69785,
- 0x0adc0626,
- 0x0420118a,
- 0xef840adc,
- 0x36370add,
- 0x363708dc,
- 0x0cde0edc,
- 0xcebc96bd,
- 0x001caa7f,
- 0x38383801,
- 0xdf380edf,
- 0x0adf380c,
- 0x3808df38,
- 0xde3906df,
- 0x069f3c06,
- 0x80ce8f18,
- 0x2600e6ff,
- 0xe704c60c,
- 0x207ece00,
- 0x2001001c,
- 0x04001c03,
- 0xc6007ece,
- 0xce00e7ef,
- 0x00ec217e,
- 0xd300df18,
- 0x277ece00,
- 0x7ece00ed,
- 0xc400e600,
- 0xcef72710,
- 0x001dff80,
- 0x2600e604,
- 0x207ece06,
- 0x3801001d,
- 0xde3906df,
- 0x069f3c06,
- 0xe68385ce,
- 0x2701c400,
- 0xb885ce74,
- 0x02ed5f4f,
- 0x85ce00ed,
- 0xed02edbc,
- 0xc085ce00,
- 0x00ed02ed,
- 0xedc485ce,
- 0xce00ed02,
- 0x02edc885,
- 0x85ce00ed,
- 0xed02edcc,
- 0x8285ce00,
- 0x08c400e6,
- 0x97bd0326,
- 0xff80ceaa,
- 0xce08001c,
- 0x00e68285,
- 0x7ecef0c4,
- 0xe701ca20,
- 0x217ece00,
- 0xce00ee1a,
- 0x00ec8085,
- 0x8f1800dd,
- 0x8f1800d3,
- 0x1a297ece,
- 0x7ece00ef,
- 0xe7dfc600,
- 0x027ece00,
- 0x2020001c,
- 0xff80ce20,
- 0xe608001d,
- 0xce062600,
- 0x001d207e,
- 0x007ece01,
- 0x00e7dfc6,
- 0x1d027ece,
- 0x99bd2000,
- 0x06df38c1,
- 0x3c08de39,
- 0xb65086ce,
- 0x19270086,
- 0x00a60897,
- 0xa703a616,
- 0xec03e700,
- 0xe702a701,
- 0x3a04c601,
- 0x2e08007a,
- 0x08df38e9,
- 0x3c08de39,
- 0xde3c0ade,
- 0x08dd3c0c,
- 0x86607ece,
- 0xcc0ba701,
- 0x0cedc015,
- 0xedc115cc,
- 0x0080cc0e,
- 0xc6cc0add,
- 0xdc0cdd54,
- 0x868f1808,
- 0xdc089709,
- 0xdc00ed0a,
- 0xa602ed0c,
- 0x27018407,
- 0x00ec18fa,
- 0xec1800ed,
- 0xa602ed02,
- 0x27018407,
- 0x8a0adcfa,
- 0xdc00ed01,
- 0xcb02ed0c,
- 0xa60cdd04,
- 0x27018407,
- 0x00ec18fa,
- 0xec1800ed,
- 0xc602ed02,
- 0xa63a1804,
- 0x27018407,
- 0x08007afa,
- 0x0adcb52e,
- 0x0cdc00ed,
- 0x07a602ed,
- 0xfa270184,
- 0xed00ec18,
- 0x02ec1800,
- 0x07a602ed,
- 0xfa270184,
- 0x380ba74f,
- 0xdf380cdf,
- 0x08df380a,
- 0x06de1839,
- 0x069f3c18,
- 0x807fce18,
- 0x3701a718,
- 0x02caf8c4,
- 0x8f00e718,
- 0xfc8a0384,
- 0x1803a718,
- 0xfd8602e7,
- 0x8604a718,
- 0x07c43301,
- 0x5a480427,
- 0xa718fc2e,
- 0x0002cc05,
- 0x1806a718,
- 0x06de07e7,
- 0x181606a6,
- 0xed1808ed,
- 0xb703860a,
- 0x7fb68c7f,
- 0x2680848c,
- 0x06df38f9,
- 0x7fce1839,
- 0x01a71880,
- 0xf8c43737,
- 0xe71804ca,
- 0x03848f00,
- 0xa718fc8a,
- 0x02e71803,
- 0xa718fd86,
- 0x33018604,
- 0x042707c4,
- 0xfc2e5a48,
- 0xcc05a718,
- 0xa7180002,
- 0x07e71806,
- 0x7fb70186,
- 0x8c7fb68c,
- 0xf9268084,
- 0x1803c433,
- 0x00e6183a,
- 0x7fce1839,
- 0x01a71880,
- 0xcaf8c437,
- 0x00e71804,
- 0x03a7188f,
- 0x4f02e718,
- 0x3304a718,
- 0x042704c4,
- 0x0220f086,
- 0xa7180f86,
- 0x0002cc05,
- 0x1806a718,
- 0x018607e7,
- 0xb68c7fb7,
- 0x80848c7f,
- 0xa618f926,
- 0x02e61803,
- 0x01a6188f,
- 0x3900e618,
- 0x1806de18,
- 0x18069f3c,
- 0x18807fce,
- 0xc43701a7,
- 0x00e718f8,
- 0x03a7188f,
- 0x4f02e718,
- 0x3304a718,
- 0x042704c4,
- 0x0220f086,
- 0xa7180f86,
- 0x0002cc05,
- 0x1806a718,
- 0x06de07e7,
- 0xe71807ec,
- 0x09a71808,
- 0xe71805ec,
- 0x0ba7180a,
- 0x7fb70386,
- 0x8c7fb68c,
- 0xf9268084,
- 0x3906df38,
- 0x807fce18,
- 0x3701a718,
- 0x04caf8c4,
- 0x8f00e718,
- 0xfc8a0384,
- 0x1803a718,
- 0xfd8602e7,
- 0x7e04a718,
- 0xde188b96,
- 0x9f3c1806,
- 0x7fce1806,
- 0x01a71880,
- 0xcaf8c437,
- 0x00e71802,
- 0x8a03848f,
- 0x03a718fc,
- 0x8602e718,
- 0x04a718fd,
- 0xeddb967e,
- 0x8407a602,
- 0x39fa2701,
- 0x018407a6,
- 0xce39fa27,
- 0x046fc010,
- 0xed8f184f,
- 0xa7078605,
- 0x6400cc09,
- 0x09a607ed,
- 0xfa270184,
- 0x0fc48f18,
- 0x17274d17,
- 0x04e740c6,
- 0x07c6056f,
- 0x04c609e7,
- 0x09e606e7,
- 0xfa2701c4,
- 0xecef2e4a,
- 0xfecc3902,
- 0xfc84fd00,
- 0xfdf370cc,
- 0x00ccfe84,
- 0xfa84fd03,
- 0x8de0d6bd,
- 0xa085f775,
- 0x8fa185b7,
- 0x86a285b7,
- 0xff84b7f6,
- 0x8de0d6bd,
- 0xa385f761,
- 0x8fa685b7,
- 0x86a785b7,
- 0xff84b7f9,
- 0x8de0d6bd,
- 0xae85fd4d,
- 0xad85b78f,
- 0x84b7fc86,
- 0xe0d6bdff,
- 0x85fd3c8d,
- 0x85b78faa,
- 0xb7ff86a9,
- 0xd6bdff84,
- 0xf72b8de0,
- 0x85b7a485,
- 0x85b78fa5,
- 0x0a71cca8,
- 0xbdfe84fd,
- 0x85cee0d6,
- 0x02ee1a00,
- 0x185401e6,
- 0x1856468f,
- 0x8f18548f,
- 0x84fd5646,
- 0x08de39be,
- 0x0085ce3c,
- 0x03a600e6,
- 0x01e608dd,
- 0x007902a6,
- 0x79495909,
- 0x00790800,
- 0x79495909,
- 0x00790800,
- 0x79495909,
- 0x08de0800,
- 0xdf183818,
- 0x08de3908,
- 0x0090cc3c,
- 0xcc5884fd,
- 0x84fde4c6,
- 0xc3e4bd5a,
- 0xb60000ce,
- 0xc4165f84,
- 0x04163a01,
- 0x3a01c404,
- 0xc4040416,
- 0x04163a01,
- 0x3a01c404,
- 0x04cb508f,
- 0xce4f08d7,
- 0x9abdb885,
- 0x4f08d60a,
- 0xbdc085ce,
- 0x85f60a9a,
- 0x1809d7a6,
- 0xbdb885ce,
- 0x85f6ee99,
- 0x1809d7a7,
- 0xbdc085ce,
- 0x8086ee99,
- 0x85b60897,
- 0x27048482,
- 0x607ece5b,
- 0x08a70386,
- 0xed70fecc,
- 0x0200cc04,
- 0x04a606ed,
- 0x018407a6,
- 0x03a6fa27,
- 0x44440484,
- 0xce5f0188,
- 0x9abdc885,
- 0xa585f60a,
- 0xce1809d7,
- 0x99bdc885,
- 0xcc85ceee,
- 0x0000ce18,
- 0x142600ec,
- 0x102602a6,
- 0x85b103a6,
- 0x18092ca4,
- 0xb6be84fe,
- 0x0897a885,
- 0xab7fff18,
- 0xad7fb74f,
- 0xf6ac85ce,
- 0xfe18a085,
- 0x2026bc85,
- 0x26be85b6,
- 0xbf85b61b,
- 0xa1a385f6,
- 0xf6112d03,
- 0x02a1a285,
- 0x85f60a2d,
- 0x2d01a1a1,
- 0xa085f603,
- 0x85ce09d7,
- 0xa085f6a8,
- 0xc485fe18,
- 0x85b61d26,
- 0xb61826c6,
- 0x01a1c785,
- 0x85f6112e,
- 0x2e02a1a1,
- 0xa285f60a,
- 0x032e03a1,
- 0xd1a385f6,
- 0xd7022e09,
- 0x4f08d609,
- 0xd68f1805,
- 0xeabd4f09,
- 0xcc09d740,
- 0x84fd0091,
- 0x0cc4cc58,
- 0xbd5a84fd,
- 0x09d6c3e4,
- 0xc65d84f7,
- 0x5884f781,
- 0xfc92e4bd,
- 0x7ef38085,
- 0x297efd21,
- 0x7eb7df86,
- 0x08df3800,
- 0x0091cc39,
- 0xcc5884fd,
- 0x84fd0cc4,
- 0xc3e4bd5a,
- 0xf7a085f6,
- 0x81c65d84,
- 0xbd5884f7,
- 0x85b692e4,
- 0x27048482,
- 0xfd4f5f08,
- 0x7fb7ab7f,
- 0xec1839ad,
- 0x02eecd00,
- 0x2709007d,
- 0x468f040a,
- 0x007a8f56,
- 0x18f62609,
- 0xefcd04ed,
- 0x58583906,
- 0x02e35858,
- 0x00ec02ed,
- 0x008900c9,
- 0x04ec00ed,
- 0x8f184353,
- 0x435306ec,
- 0x180100c3,
- 0x8900c98f,
- 0xe38f1800,
- 0x1802ed02,
- 0xa901e98f,
- 0x3900ed00,
- 0xde3c06de,
- 0x069f3c08,
- 0x1daa7fce,
- 0x7fce0100,
- 0x10001c8f,
- 0xced60ccc,
- 0x96bd0000,
- 0xc608d725,
- 0xcc3437c8,
- 0x00ced60c,
- 0xcd95bd00,
- 0xced70ccc,
- 0x96bd0000,
- 0x3720ca25,
- 0xd70ccc34,
- 0xbd0000ce,
- 0xd8c6cd95,
- 0x0ccc3437,
- 0x0000ced6,
- 0xc6cd95bd,
- 0xcc34371f,
- 0x00ced70c,
- 0xcd95bd00,
- 0x3437d9c6,
- 0xced60ccc,
- 0x95bd0000,
- 0xd70ccccd,
- 0xbd0000ce,
- 0x8f302596,
- 0x8f0a00c3,
- 0x2620c435,
- 0xd6448d02,
- 0xcc343708,
- 0x00ced60c,
- 0xcd95bd00,
- 0x00a0cc38,
- 0xbd0002ce,
- 0x20ca2596,
- 0x022722c1,
- 0xa0cc258d,
- 0x0002ce01,
- 0xc12596bd,
- 0x8d022710,
- 0x8f7fce16,
- 0xce10001d,
- 0x001daa7f,
- 0x01001c01,
- 0x3808df38,
- 0xce3906df,
- 0x0386607e,
- 0xffcc08a7,
- 0xcc04ed30,
- 0x06ede701,
- 0x00ed5f4f,
- 0x02ed7fc6,
- 0x018407a6,
- 0x01ccfa27,
- 0x5f06ede9,
- 0xed00ed4f,
- 0x8407a602,
- 0x01fa2701,
- 0x39fd20cf,
- 0xcc607ece,
- 0x04ed30ff,
- 0xed3d26cc,
- 0xfe00cc06,
- 0xbd5f00ed,
- 0x0fcc5f97,
- 0xcc06ede2,
- 0x00edfe00,
- 0x5f97bd5f,
- 0xed5422cc,
- 0xfcffcc06,
- 0xfccc00ed,
- 0x5f97bd00,
- 0x3c08de39,
- 0xde3c0ade,
- 0x0ede3c0c,
- 0xb7df863c,
- 0x7ece017e,
- 0x02ffcc60,
- 0x9dcc04ed,
- 0xb602ed64,
- 0x2084017e,
- 0x01ccf927,
- 0xcc08dd01,
- 0x0add1100,
- 0xdd0000cc,
- 0x0f00cc0c,
- 0x9cbd0edd,
- 0x3001cca9,
- 0x80cc08dd,
- 0xcc0add62,
- 0x0cddffff,
- 0xddfff7cc,
- 0xdb9cbd0e,
- 0xdd0200cc,
- 0xffffcc0a,
- 0xffcc0cdd,
- 0xbd0eddfb,
- 0x80ccdb9c,
- 0xcc0add63,
- 0x0cdd0101,
- 0xdd0080cc,
- 0xa99cbd0e,
- 0xdd6280cc,
- 0x0000cc0a,
- 0x00cc0cdd,
- 0xbd0edd01,
- 0x80cca99c,
- 0xcc0add60,
- 0x0cdd0000,
- 0xdd0100cc,
- 0xa99cbd0e,
- 0x0200ce18,
- 0x54207ef6,
- 0xbd545454,
- 0x94bd6f97,
- 0x1001cc0b,
- 0x00cc08dd,
- 0xcc0add10,
- 0x0cdd0000,
- 0xdd0100cc,
- 0xcc7e8d0e,
- 0x08dd3001,
- 0xdd6080cc,
- 0x0301cc0a,
- 0x9dbd0cdd,
- 0x3001cc0d,
- 0x80cc08dd,
- 0xcc0add62,
- 0x0cddffff,
- 0xddfeffcc,
- 0xdb9cbd0e,
- 0xdd0000cc,
- 0x0008cc0c,
- 0x498d0edd,
- 0xdd6380cc,
- 0xfefecc0a,
- 0x7fcc0cdd,
- 0x8d0eddff,
- 0x2001cc6a,
- 0x44cc08dd,
- 0xcc0add50,
- 0x0cdd0203,
- 0x860d9dbd,
- 0x017eb7df,
- 0xcc607ece,
- 0x04ed02ff,
- 0xed9f9dcc,
- 0x017eb602,
- 0xf9272084,
- 0x380edf38,
- 0xdf380cdf,
- 0x08df380a,
- 0x607ece39,
- 0xed30ffcc,
- 0x2800cc04,
- 0x08dc06ed,
- 0x0adc00ed,
- 0xcc5f97bd,
- 0x06ed2900,
- 0x97bd04a6,
- 0x9a00ec68,
- 0xed0dda0c,
- 0x9a02ec00,
- 0xbd0fda0e,
- 0xce395f97,
- 0xffcc607e,
- 0xcc04ed30,
- 0x06ed2800,
- 0x00ed08dc,
- 0x97bd0adc,
- 0x2900cc5f,
- 0x04a606ed,
- 0xec6897bd,
- 0xd40c9400,
- 0xec00ed0d,
- 0xd40e9402,
- 0x5f97bd0f,
- 0x607ece39,
- 0x607ece18,
- 0x3a180dd6,
- 0xed30ffcc,
- 0x2800cc04,
- 0x08dc06ed,
- 0x0adc00ed,
- 0xcc5f97bd,
- 0x06ed2900,
- 0x97bd04a6,
- 0x00e61868,
- 0xf4260cd4,
- 0x39064f39,
- 0xfc203e0e,
- 0x28202001,
- 0x00000000,
- 0x20202001,
- 0x00000000,
- 0x24202001,
- 0x00000000,
- 0x2c202001,
- 0x00000000,
- 0x28000008,
- 0x04ff3000,
- 0x002901c0,
- 0xc004ff30,
- 0x30002800,
- 0x01c004ff,
- 0xff300029,
- 0x2800c004,
- 0x04ff3000,
- 0x002901c0,
- 0xc004ff30,
- 0x30002800,
- 0x01c004ff,
- 0xff300029,
- 0x0800c004,
- 0x00280000,
- 0xc004ff30,
- 0x30002909,
- 0x09c004ff,
- 0xff300028,
- 0x2909c004,
- 0x04ff3000,
- 0x002809c0,
- 0xc004ff30,
- 0x30002909,
- 0x09c004ff,
- 0xff300028,
- 0x2909c004,
- 0x04ff3000,
- 0x000001c0
-};
-
-UINT32 DataBlock1[] = {
- 0x3b903b90,
- 0x3b903b90,
- 0x3b903b90,
- 0x3b903b90,
- 0x3b903b90,
- 0x3b903b90,
- 0x3b903b90,
- 0x3b903b90,
- 0x3b903b90,
- 0x3b903b90,
- 0x3b903b90,
- 0x3b903b90,
- 0x96d53b90,
- 0x3b90aed5,
- 0x04900490,
- 0x04900490
-};
-
-SMU_FIRMWARE_BLOCK FmBlockArray[] = {
- {
- 0x9000,
- 0x377,
- &DataBlock0[0]
- },
- {
- 0xbfc0,
- 0x10,
- &DataBlock1[0]
- }
-};
-
-SMU_FIRMWARE_HEADER Fm = {
- {
- 0x1, 0x200
- },
- 2,
- &FmBlockArray[0]
-};
-#endif
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/NbFamilyServices.h b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/NbFamilyServices.h
deleted file mode 100644
index 808658c..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/NbFamilyServices.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Family specific service routine
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 40044 $ @e \$Date: 2010-10-19 06:43:22 +0800 (Tue, 19 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _NBFAMILYSERVICES_H_
-#define _NBFAMILYSERVICES_H_
-
-/// Fuse field entry
-typedef struct {
- UINT8 FieldOffset; ///< Field offset in fuse register
- UINT8 FieldWidth; ///< Width of field
- UINT16 FuseOffset; ///< destination offset in translation table
-} FUSE_REGISTER_ENTRY;
-
-/// Fuse register entry
-typedef struct {
- UINT32 Register; ///< FCR register address
- UINT8 FuseRegisterTableLength; ///< Length of field table for this register
- FUSE_REGISTER_ENTRY *FuseRegisterTable; ///< Pointer to field table
-} FUSE_TABLE_ENTRY;
-
-/// Fuse translation table
-typedef struct {
- UINT8 FuseTableLength; ///< Length of translation table
- FUSE_TABLE_ENTRY *FuseTable; ///< Pointer to register table
-} FUSE_TABLE;
-
-/// NB power gate configuration
-typedef struct {
- struct {
- UINT32 GmcPowerGate:1; ///< Power Gate GMC
- UINT32 GfxPowerGate:1; ///< Power gate GFX
- UINT32 UvdPowerGate:1; ///< Power gate UVD
- } Services; ///< Power gate services
- POWER_GATE_DATA Gmc; ///< Gmc Power gating Data
- POWER_GATE_DATA Uvd; ///< Uvd Power gating Data
-} NB_POWERGATE_CONFIG;
-
-VOID
-NbFmClumpUnitID (
- IN PCI_ADDR NbPciAddress,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-FUSE_TABLE*
-NbFmGetFuseTranslationTable (
- VOID
- );
-
-VOID
-NbFmFuseAdjustFuseTablePatch (
- IN OUT PP_FUSE_ARRAY *PpFuseArray,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-UINT32
-NbFmDpmStateBootupInit (
- IN UINT32 LclkDpmValid,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-NbFmInitLclkDpmRcActivity (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-#endif
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Feature/NbFuseTable.c b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Feature/NbFuseTable.c
deleted file mode 100644
index d3f3e6c..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Feature/NbFuseTable.c
+++ /dev/null
@@ -1,401 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Fuse table initialization
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "heapManager.h"
-#include "Gnb.h"
-#include "GnbFuseTable.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include "GnbRegistersON.h"
-#include "NbSmuLib.h"
-#include "NbConfigData.h"
-#include "NbFuseTable.h"
-#include "NbFamilyServices.h"
-#include "GfxLib.h"
-#include "Filecode.h"
-
-#define FILECODE PROC_GNB_NB_FEATURE_NBFUSETABLE_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-VOID
-NbFuseLoadDefaultFuseTable (
- OUT PP_FUSE_ARRAY *PpFuseArray,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-NbFuseLoadFuseTableFromFcr (
- OUT PP_FUSE_ARRAY *PpFuseArray,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-NbFuseDebugDump (
- IN PP_FUSE_ARRAY *PpFuseArray,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-NbFuseAdjustFuseTableToCurrentMainPllVco (
- IN OUT PP_FUSE_ARRAY *PpFuseArray,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-PP_FUSE_ARRAY DefaultPpFuseArray = {
- 0, ///< PP table revision
- {1, 0, 0, 0, 0, 0}, ///< Valid DPM states
- {0x40, 0, 0, 0, 0}, ///< Sclk DPM DID
- {0, 0, 0, 0, 0}, ///< Sclk DPM VID
- {0, 0, 0, 0, 0}, ///< Sclk DPM Cac
- {1, 0, 0, 0, 0, 0}, ///< State policy flags
- {2, 0, 0, 0, 0, 0}, ///< State policy label
- {0x40, 0, 0, 0}, ///< VCLK DID
- {0x40, 0, 0, 0}, ///< DCLK DID
- 0, ///< Thermal SCLK
- {0, 0, 0, 0, 0, 0}, ///< Vclk/Dclk selector
- {0, 0, 0, 0}, ///< Valid Lclk DPM states
- {0, 0, 0, 0}, ///< Lclk DPM DID
- {0, 0, 0, 0}, ///< Lclk DPM VID
- {0, 0, 0, 0}, ///< Displclk DID
- 3, ///< Pcie Gen 2 VID
- 0x10 ///< Main PLL id for 3200 VCO
-};
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Fuse Table Init
- *
- *
- *
- * @param[in] StdHeader Pointer to Standard configuration
- * @retval AGESA_STATUS
- */
-
-AGESA_STATUS
-NbFuseTableFeature (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- PP_FUSE_ARRAY *PpFuseArray;
- D18F3xA0_STRUCT D18F3xA0;
- BOOLEAN LoadDefaultFuses;
- IDS_HDT_CONSOLE (GNB_TRACE, "NbFuseTableFeature Enter\n");
-
- PpFuseArray = (PP_FUSE_ARRAY *) GnbAllocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, sizeof (PP_FUSE_ARRAY), StdHeader);
- ASSERT (PpFuseArray != NULL);
- if (PpFuseArray == NULL) {
- IDS_HDT_CONSOLE (GNB_TRACE, " ERROR!!! Heap Allocation\n");
- return AGESA_ERROR;
- }
- LibAmdMemFill (PpFuseArray, 0x00, sizeof (PP_FUSE_ARRAY), StdHeader);
- GnbLibPciRead (
- MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3xA0_ADDRESS),
- AccessWidth32,
- &D18F3xA0.Value,
- StdHeader
- );
-
-#ifndef GNB_FORCE_DEFAULT_FUSE
- LoadDefaultFuses = FALSE;
- if (D18F3xA0.Field.CofVidProg == 1) {
- IDS_HDT_CONSOLE (NB_MISC, " Processor Fused\n");
- NbFuseLoadFuseTableFromFcr (PpFuseArray, StdHeader);
- if (PpFuseArray->PPlayTableRev == 0) {
- IDS_HDT_CONSOLE (NB_MISC, " PowerPlay Table Unfused\n");
- LoadDefaultFuses = TRUE;
- }
- } else {
- IDS_HDT_CONSOLE (NB_MISC, " Processor Unfuse\n");
- LoadDefaultFuses = TRUE;
- }
-#else
- LoadDefaultFuses = TRUE;
-#endif
- if (LoadDefaultFuses) {
- IDS_HDT_CONSOLE (NB_MISC, " Load default fuses\n");
- NbFuseLoadDefaultFuseTable (PpFuseArray, StdHeader);
- }
- NbFmFuseAdjustFuseTablePatch (PpFuseArray, StdHeader);
- NbFuseAdjustFuseTableToCurrentMainPllVco (PpFuseArray, StdHeader);
- IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PPFUSE_OVERRIDE, PpFuseArray, StdHeader);
- GNB_DEBUG_CODE (
- NbFuseDebugDump (PpFuseArray, StdHeader)
- );
- IDS_HDT_CONSOLE (GNB_TRACE, "NbFuseTableFeature Exit\n");
- return AGESA_SUCCESS;
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Load Fuse Table From FCRs
- *
- *
- * @param[out] PpFuseArray Pointer to save fuse table
- * @param[in] StdHeader Pointer to Standard configuration
- * @retval AGESA_STATUS
- */
-
-VOID
-NbFuseLoadFuseTableFromFcr (
- OUT PP_FUSE_ARRAY *PpFuseArray,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- FUSE_TABLE *FuseTable;
- UINTN RegisterIndex;
- FuseTable = NbFmGetFuseTranslationTable ();
- for (RegisterIndex = 0; RegisterIndex < FuseTable->FuseTableLength; RegisterIndex++ ) {
- UINTN FieldIndex;
- UINTN FuseRegisterTableLength;
- UINT32 FuseValue;
- FuseRegisterTableLength = FuseTable->FuseTable[RegisterIndex].FuseRegisterTableLength;
- FuseValue = NbSmuReadEfuse (
- FuseTable->FuseTable[RegisterIndex].Register,
- StdHeader
- );
- for (FieldIndex = 0; FieldIndex < FuseRegisterTableLength; FieldIndex++) {
- FUSE_REGISTER_ENTRY RegisterEntry;
- RegisterEntry = FuseTable->FuseTable[RegisterIndex].FuseRegisterTable[FieldIndex];
- *((UINT8 *) PpFuseArray + RegisterEntry.FuseOffset) = (UINT8) ((FuseValue >> RegisterEntry.FieldOffset) &
- ((1 << RegisterEntry.FieldWidth) - 1));
- }
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Load Default Fuse Table
- *
- *
- * @param[out] PpFuseArray Pointer to save fuse table
- * @param[in] StdHeader Pointer to Standard configuration
- * @retval AGESA_STATUS
- */
-
-VOID
-NbFuseLoadDefaultFuseTable (
- OUT PP_FUSE_ARRAY *PpFuseArray,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- D18F3x15C_STRUCT D18F3x15C;
- UINT8 MaxVidIndex;
- LibAmdMemCopy (PpFuseArray, &DefaultPpFuseArray, sizeof (PP_FUSE_ARRAY), StdHeader);
- GnbLibPciRead (
- MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS),
- AccessWidth32,
- &D18F3x15C.Value,
- StdHeader
- );
- if (D18F3x15C.Value == 0) {
- D18F3x15C.Value = 0x24242424;
- GnbLibPciWrite (
- MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS),
- AccessWidth32,
- &D18F3x15C.Value,
- StdHeader
- );
- }
- MaxVidIndex = GfxLibMaxVidIndex (StdHeader);
- PpFuseArray->SclkDpmVid[0] = MaxVidIndex;
- PpFuseArray->PcieGen2Vid = MaxVidIndex;
-
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Adjust DIDs to current main PLL VCO
- *
- * Main PLL VCO can be changed for debug perpouses
- *
- * @param[in,out] PpFuseArray Pointer to save fuse table
- * @param[in] StdHeader Pointer to Standard configuration
- */
-
-VOID
-NbFuseAdjustFuseTableToCurrentMainPllVco (
- IN OUT PP_FUSE_ARRAY *PpFuseArray,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 EffectiveMainPllFreq10KHz;
- UINT32 FusedMainPllFreq10KHz;
- UINT32 TempVco;
- UINTN Index;
- EffectiveMainPllFreq10KHz = GfxLibGetMainPllFreq (StdHeader) * 100;
- FusedMainPllFreq10KHz = (PpFuseArray->MainPllId + 0x10) * 100 * 100;
- if (FusedMainPllFreq10KHz != EffectiveMainPllFreq10KHz) {
- IDS_HDT_CONSOLE (NB_MISC, " WARNING! Adjusting fuse table for reprogrammed VCO\n");
- for (Index = 0; Index < 5; Index++) {
- if (PpFuseArray->SclkDpmDid[Index] != 0) {
- TempVco = GfxLibCalculateClk (PpFuseArray->SclkDpmDid[Index], FusedMainPllFreq10KHz);
- PpFuseArray->SclkDpmDid[Index] = GfxLibCalculateDid (TempVco, EffectiveMainPllFreq10KHz);
- }
- }
- for (Index = 0; Index < 4; Index++) {
- if (PpFuseArray->VclkDid[Index] != 0) {
- TempVco = GfxLibCalculateClk (PpFuseArray->VclkDid[Index], FusedMainPllFreq10KHz);
- PpFuseArray->VclkDid[Index] = GfxLibCalculateDid (TempVco, EffectiveMainPllFreq10KHz);
- }
- if (PpFuseArray->DclkDid[Index] != 0) {
- TempVco = GfxLibCalculateClk (PpFuseArray->DclkDid[Index], FusedMainPllFreq10KHz);
- PpFuseArray->DclkDid[Index] = GfxLibCalculateDid (TempVco, EffectiveMainPllFreq10KHz);
- }
- if (PpFuseArray->LclkDpmDid[Index] != 0) {
- TempVco = GfxLibCalculateClk (PpFuseArray->LclkDpmDid[Index], FusedMainPllFreq10KHz);
- PpFuseArray->LclkDpmDid[Index] = GfxLibCalculateDid (TempVco, EffectiveMainPllFreq10KHz);
- }
- if (PpFuseArray->DisplclkDid[Index] != 0) {
- TempVco = GfxLibCalculateClk (PpFuseArray->DisplclkDid[Index], FusedMainPllFreq10KHz);
- PpFuseArray->DisplclkDid[Index] = GfxLibCalculateDid (TempVco, EffectiveMainPllFreq10KHz);
- }
- }
- if (PpFuseArray->SclkThermDid != 0) {
- TempVco = GfxLibCalculateClk (PpFuseArray->SclkThermDid , FusedMainPllFreq10KHz);
- PpFuseArray->SclkThermDid = GfxLibCalculateDid (TempVco, EffectiveMainPllFreq10KHz);
- }
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Debug dump fuse table
- *
- *
- * @param[out] PpFuseArray Pointer to save fuse table
- * @param[in] StdHeader Pointer to Standard configuration
- */
-
-VOID
-NbFuseDebugDump (
- IN PP_FUSE_ARRAY *PpFuseArray,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINTN Index;
- UINT32 EffectiveMainPllFreq10KHz;
-
- EffectiveMainPllFreq10KHz = GfxLibGetMainPllFreq (StdHeader) * 100;
- IDS_HDT_CONSOLE (NB_MISC, "<------------ GNB FUSE TABLE------------>\n");
- for (Index = 0; Index < 4; Index++) {
- if (PpFuseArray->LclkDpmValid[Index] != 0) {
- IDS_HDT_CONSOLE (
- NB_MISC,
- " LCLK DID[%d] - 0x%02x (%dMHz)\n",
- Index,
- PpFuseArray->LclkDpmDid[Index],
- GfxLibCalculateClk (PpFuseArray->LclkDpmDid[Index], EffectiveMainPllFreq10KHz) / 100);
- IDS_HDT_CONSOLE (NB_MISC, " LCLK VID[%d] - 0x02%x\n", Index, PpFuseArray->LclkDpmVid[Index]);
- }
- }
- for (Index = 0; Index < 4; Index++) {
- IDS_HDT_CONSOLE (
- NB_MISC,
- " VCLK DID[%d] - 0x%02x (%dMHz)\n",
- Index,
- PpFuseArray->VclkDid[Index],
- (PpFuseArray->VclkDid[Index] != 0) ? (GfxLibCalculateClk (PpFuseArray->VclkDid[Index], EffectiveMainPllFreq10KHz) / 100) : 0
- );
- IDS_HDT_CONSOLE (
- NB_MISC,
- " DCLK DID[%d] - 0x%02x (%dMHz)\n",
- Index,
- PpFuseArray->DclkDid[Index],
- (PpFuseArray->DclkDid[Index] != 0) ? (GfxLibCalculateClk (PpFuseArray->DclkDid[Index], EffectiveMainPllFreq10KHz) / 100) : 0
- );
- }
- for (Index = 0; Index < 4; Index++) {
- IDS_HDT_CONSOLE (
- NB_MISC,
- " DISPCLK DID[%d] - 0x%02x (%dMHz)\n",
- Index,
- PpFuseArray->DisplclkDid[Index],
- (PpFuseArray->DisplclkDid[Index] != 0) ? (GfxLibCalculateClk (PpFuseArray->DisplclkDid[Index], EffectiveMainPllFreq10KHz) / 100) : 0
- );
- }
- for (Index = 0; Index < 5; Index++) {
- IDS_HDT_CONSOLE (
- NB_MISC,
- " SCLK DID[%d] - 0x%02x (%dMHz)\n",
- Index,
- PpFuseArray->SclkDpmDid[Index],
- (PpFuseArray->SclkDpmDid[Index] != 0) ? (GfxLibCalculateClk (PpFuseArray->SclkDpmDid[Index], EffectiveMainPllFreq10KHz) / 100) : 0
- );
- IDS_HDT_CONSOLE (NB_MISC, " SCLK VID[%d] - 0x%02x\n", Index, PpFuseArray->SclkDpmVid[Index]);
- }
- for (Index = 0; Index < 6; Index++) {
- IDS_HDT_CONSOLE (NB_MISC, " State #%d\n", Index);
- IDS_HDT_CONSOLE (NB_MISC, " Policy Label - 0x%x\n", PpFuseArray->PolicyLabel[Index]);
- IDS_HDT_CONSOLE (NB_MISC, " Policy Flag - 0x%x\n", PpFuseArray->PolicyFlags[Index]);
- IDS_HDT_CONSOLE (NB_MISC, " Valid SCLK - 0x%x\n", PpFuseArray->SclkDpmValid[Index]);
- IDS_HDT_CONSOLE (NB_MISC, " Vclk/Dclk Index - 0x%x\n", PpFuseArray->VclkDclkSel[Index]);
- }
- IDS_HDT_CONSOLE (NB_MISC, " GEN2 VID - 0x%x\n", PpFuseArray->PcieGen2Vid);
- IDS_HDT_CONSOLE (NB_MISC, " Main PLL Id - 0x%x\n", PpFuseArray->MainPllId);
- IDS_HDT_CONSOLE (NB_MISC, "<------------ GNB FUSE END-------------->\n");
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Feature/NbFuseTable.h b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Feature/NbFuseTable.h
deleted file mode 100644
index 876cb6a..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Feature/NbFuseTable.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Fuse table initialization
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _NBFUSETABLE_H_
-#define _NBFUSETABLE_H_
-
-AGESA_STATUS
-NbFuseTableFeature (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Feature/NbLclkDpm.c b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Feature/NbLclkDpm.c
deleted file mode 100644
index b8f683e..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Feature/NbLclkDpm.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * LCLK DPM initialization
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 40044 $ @e \$Date: 2010-10-19 06:43:22 +0800 (Tue, 19 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "heapManager.h"
-#include "Gnb.h"
-#include "GnbFuseTable.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include "GnbRegistersON.h"
-#include "OptionGnb.h"
-#include "GfxLib.h"
-#include "NbConfigData.h"
-#include "NbSmuLib.h"
-#include "NbLclkDpm.h"
-#include "NbFamilyServices.h"
-#include "Filecode.h"
-
-#define FILECODE PROC_GNB_NB_FEATURE_NBLCLKDPM_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-extern GNB_BUILD_OPTIONS GnbBuildOptions;
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * LCLK DPM init
- *
- *
- *
- * @param[in] StdHeader Pointer to Standard configuration
- * @retval Initialization status
- */
-
-AGESA_STATUS
-NbLclkDpmFeature (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_STATUS Status;
- IDS_HDT_CONSOLE (GNB_TRACE, "NbLclkDpmFeature Enter\n");
-
- Status = NbFmInitLclkDpmRcActivity (StdHeader);
-
- IDS_HDT_CONSOLE (GNB_TRACE, "NbLclkDpmFeature Exit [0x%x]\n", Status);
- return Status;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Feature/NbLclkDpm.h b/src/vendorcode/amd/agesa/Proc/GNB/Nb/Feature/NbLclkDpm.h
deleted file mode 100644
index 272fc77..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Nb/Feature/NbLclkDpm.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * NB Lclk DPM
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 38842 $ @e \$Date: 2010-10-01 05:04:55 +0800 (Fri, 01 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _NBLCLKDPM_H_
-#define _NBLCLKDPM_H_
-
-/// LCLK DPM enable control
-typedef enum {
- LclkDpmDisabled, ///<LCLK DPM disabled
- LclkDpmRcActivity, ///<LCLK DPM enabled and use Root Complex Activity monitor method
-} LCLK_DPM_MODE;
-
-AGESA_STATUS
-NbLclkDpmFeature (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbConfigData.c b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbConfigData.c
deleted file mode 100644
index 0dd2f9a..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbConfigData.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Initialize NB configuration data structure.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Gnb.h"
-#include "NbConfigData.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_NB_NBCONFIGDATA_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Create configuration data
- *
- *
- * @param[in] StdHeader Standard configuration header
- * @param[in] Gnb Pointer to global Gnb configuration
- * @retval AGESA_STATUS
- */
-
-AGESA_STATUS
-NbAllocateConfigData (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN GNB_PLATFORM_CONFIG *Gnb
- )
-{
- AGESA_STATUS Status;
- Status = AGESA_SUCCESS;
- Gnb->StdHeader = StdHeader;
- return Status;
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbConfigData.h b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbConfigData.h
deleted file mode 100644
index fc93a7a..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbConfigData.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Initialize NB configuration data structure.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _NBCONFIGDATA_H_
-#define _NBCONFIGDATA_H_
-
-/// NB register entry
-typedef struct {
- UINT16 Reg; ///< Register address
- UINT32 Mask; ///< Mask
- UINT32 Data; ///< Data
-} NB_REGISTER_ENTRY;
-
-/// GNB Platform Configuration
-typedef struct {
- AMD_CONFIG_PARAMS *StdHeader; ///< Standard configuration header
- PCI_ADDR GnbPciAddress; ///< PCI Address
-} GNB_PLATFORM_CONFIG;
-
-AGESA_STATUS
-NbAllocateConfigData (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN GNB_PLATFORM_CONFIG *Gnb
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInit.c b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInit.c
deleted file mode 100644
index 88ef6bf..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInit.c
+++ /dev/null
@@ -1,204 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Various NB initialization services
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 41506 $ @e \$Date: 2010-11-05 22:31:30 +0800 (Fri, 05 Nov 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Gnb.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include "GfxLib.h"
-#include "NbSmuLib.h"
-#include "NbConfigData.h"
-#include "GnbRegistersON.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_NB_NBINIT_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-CONST NB_REGISTER_ENTRY NbPciInitTable [] = {
- {
- D0F0x04_ADDRESS,
- 0xffffffff,
- (0x1 << D0F0x04_MemAccessEn_WIDTH) | (0x1 << D0F0x04_BusMasterEn_OFFSET)
- },
- {
- D0F0x4C_ADDRESS,
- ~(0x3ull << D0F0x4C_CfgRdTime_OFFSET),
- 0x2 << D0F0x4C_CfgRdTime_OFFSET
- },
- {
- D0F0x84_ADDRESS,
- ~(0x1ull << D0F0x84_Ev6Mode_OFFSET),
- 0x1 << D0F0x84_Ev6Mode_OFFSET
- }
-};
-
-CONST NB_REGISTER_ENTRY NbMiscInitTable [] = {
- {
- D0F0x64_x46_ADDRESS,
- ~(0x3ull << D0F0x64_x46_P2PMode_OFFSET),
- 1 << D0F0x64_x46_Msi64bitEn_OFFSET
- }
-};
-
-
-CONST NB_REGISTER_ENTRY NbOrbInitTable [] = {
- {
- D0F0x98_x07_ADDRESS,
- 0xffffffff,
- (1 << D0F0x98_x07_IocBwOptEn_OFFSET) |
- (1 << D0F0x98_x07_MSIHTIntConversionEn_OFFSET) |
- (1 << D0F0x98_x07_DropZeroMaskWrEn_OFFSET)
- },
- {
- D0F0x98_x08_ADDRESS,
- ~(0xffull << D0F0x98_x08_NpWrrLenC_OFFSET),
- 1 << D0F0x98_x08_NpWrrLenC_OFFSET
- },
- {
- D0F0x98_x09_ADDRESS,
- ~(0xffull << D0F0x98_x09_PWrrLenD_OFFSET),
- 1 << D0F0x98_x09_PWrrLenD_OFFSET
- },
- {
- D0F0x98_x0C_ADDRESS,
- 0xffffffff,
- 1 << D0F0x98_x0C_StrictSelWinnerEn_OFFSET
- },
- {
- D0F0x98_x0E_ADDRESS,
- 0xffffffff,
- 1 << D0F0x98_x0E_MsiHtRsvIntRemapEn_OFFSET
- },
- {
- D0F0x98_x28_ADDRESS,
- 0xffffffff,
- (1 << D0F0x98_x28_SmuPmInterfaceEn_OFFSET) |
- (1 << D0F0x98_x28_ForceCoherentIntr_OFFSET)
- }
-};
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init NB at Power On
- *
- *
- *
- * @param[in] Gnb Pointer to global Gnb configuration
- * @retval AGESA_STATUS
- */
-
-
-AGESA_STATUS
-NbInitOnPowerOn (
- IN GNB_PLATFORM_CONFIG *Gnb
- )
-{
- UINTN Index;
- FCRxFF30_0398_STRUCT FCRxFF30_0398;
- // Init NBCONFIG
- for (Index = 0; Index < (sizeof (NbPciInitTable) / sizeof (NB_REGISTER_ENTRY)); Index++) {
- GnbLibPciRMW (
- Gnb->GnbPciAddress.AddressValue | NbPciInitTable[Index].Reg,
- AccessWidth32,
- NbPciInitTable[Index].Mask,
- NbPciInitTable[Index].Data,
- Gnb->StdHeader
- );
- }
-
- // Init MISCIND
- for (Index = 0; Index < (sizeof (NbMiscInitTable) / sizeof (NB_REGISTER_ENTRY)); Index++) {
- GnbLibPciIndirectRMW (
- Gnb->GnbPciAddress.AddressValue | D0F0x60_ADDRESS,
- NbMiscInitTable[Index].Reg | IOC_WRITE_ENABLE,
- AccessWidth32,
- NbMiscInitTable[Index].Mask,
- NbMiscInitTable[Index].Data,
- Gnb->StdHeader
- );
- }
-
- // Init ORB
- for (Index = 0; Index < (sizeof (NbOrbInitTable) / sizeof (NB_REGISTER_ENTRY)); Index++) {
- GnbLibPciIndirectRMW (
- Gnb->GnbPciAddress.AddressValue | D0F0x94_ADDRESS,
- NbOrbInitTable[Index].Reg | (1 << D0F0x94_OrbIndWrEn_OFFSET),
- AccessWidth32,
- NbOrbInitTable[Index].Mask,
- NbOrbInitTable[Index].Data,
- Gnb->StdHeader
- );
- }
- if (!GfxLibIsControllerPresent (Gnb->StdHeader)) {
- FCRxFF30_0398.Value = (1 << FCRxFF30_0398_SoftResetGrbm_OFFSET) | (1 << FCRxFF30_0398_SoftResetMc_OFFSET) |
- (1 << FCRxFF30_0398_SoftResetDc_OFFSET) | (1 << FCRxFF30_0398_SoftResetRlc_OFFSET) |
- (1 << FCRxFF30_0398_SoftResetUvd_OFFSET);
- NbSmuSrbmRegisterWrite (FCRxFF30_0398_ADDRESS, &FCRxFF30_0398.Value, FALSE, Gnb->StdHeader);
- }
-
- return AGESA_SUCCESS;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInit.h b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInit.h
deleted file mode 100644
index 3fb65f4..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInit.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Various NB initialization services
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _NBINIT_H_
-#define _NBINIT_H_
-
-AGESA_STATUS
-NbInitOnPowerOn (
- IN GNB_PLATFORM_CONFIG *Gnb
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtEarly.c b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtEarly.c
deleted file mode 100644
index b09d192..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtEarly.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * NB early initialization interface
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Gnb.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include GNB_MODULE_DEFINITIONS (GnbNbInitLibV1)
-#include "NbConfigData.h"
-#include "NbInit.h"
-#include "NbInitAtEarly.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_NB_NBINITATEARLY_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init GNB at Reset
- *
- *
- *
- * @param[in] StdHeader Standard configuration header
- * @retval AGESA_STATUS
- */
-
-AGESA_STATUS
-NbInitAtEarly (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_STATUS Status;
- AGESA_STATUS AgesaStatus;
- GNB_PLATFORM_CONFIG Gnb;
- UINT32 NumberOfSockets;
- UINT32 SocketId;
- AgesaStatus = AGESA_SUCCESS;
- IDS_HDT_CONSOLE (GNB_TRACE, "NbInitAtEarly Enter\n");
- NbAllocateConfigData (StdHeader, &Gnb);
- NumberOfSockets = GnbGetNumberOfSockets (StdHeader);
- for (SocketId = 0; SocketId < NumberOfSockets; SocketId++) {
- UINT32 NumberOfSilicons;
- UINT32 SiliconId;
- if (!GnbIsDevicePresentInSocket (SocketId, StdHeader)) {
- continue;
- }
- NumberOfSilicons = GnbGetNumberOfSiliconsOnSocket (SocketId, StdHeader);
- for (SiliconId = 0; SiliconId < NumberOfSilicons; SiliconId++) {
- Gnb.GnbPciAddress = GnbGetPciAddress (SocketId, SiliconId, StdHeader);
- Status = NbInitOnPowerOn (&Gnb);
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
- ASSERT (Status == AGESA_SUCCESS);
- }
- }
- IDS_HDT_CONSOLE (GNB_TRACE, "NbInitAtEarly Exit[0x%x]\n", AgesaStatus);
- return AgesaStatus;
-}
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtEarly.h b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtEarly.h
deleted file mode 100644
index acc6735..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtEarly.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * NB early initialization interface
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:
- * @e sub-project:
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _NBINITATRESET_H_
-#define _NBINITATRESET_H_
-
-AGESA_STATUS
-NbInitAtEarly (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtEnv.c b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtEnv.c
deleted file mode 100644
index 0317e4c..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtEnv.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * NB init at ENV interface
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Gnb.h"
-#include "GnbFuseTable.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include GNB_MODULE_DEFINITIONS (GnbNbInitLibV1)
-#include "NbConfigData.h"
-#include "NbFamilyServices.h"
-#include "NbInitAtEnv.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_NB_NBINITATENV_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init GNB at ENV
- *
- *
- *
- * @param[in] StdHeader Standard configuration header
- * @retval AGESA_STATUS
- */
-
-AGESA_STATUS
-NbInitAtEnv (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_STATUS Status;
- AGESA_STATUS AgesaStatus;
- GNB_PLATFORM_CONFIG Gnb;
- UINT32 NumberOfSockets;
- UINT32 SocketId;
- AgesaStatus = AGESA_SUCCESS;
- IDS_HDT_CONSOLE (GNB_TRACE, "NbInitAtEnv Enter\n");
- NbAllocateConfigData (StdHeader, &Gnb);
- NumberOfSockets = GnbGetNumberOfSockets (StdHeader);
- for (SocketId = 0; SocketId < NumberOfSockets; SocketId++) {
- UINT32 NumberOfSilicons;
- UINT32 SiliconId;
- if (!GnbIsDevicePresentInSocket (SocketId, StdHeader)) {
- continue;
- }
- NumberOfSilicons = GnbGetNumberOfSiliconsOnSocket (SocketId, StdHeader);
- for (SiliconId = 0; SiliconId < NumberOfSilicons; SiliconId++) {
- Gnb.GnbPciAddress = GnbGetPciAddress (SocketId, SiliconId, StdHeader);
- GnbLpcDmaDeadlockPrevention (Gnb.GnbPciAddress, StdHeader);
- Status = GnbSetTom (Gnb.GnbPciAddress, StdHeader);
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
- ASSERT (Status == AGESA_SUCCESS);
- NbFmClumpUnitID (Gnb.GnbPciAddress, StdHeader);
- GnbOrbDynamicWake (Gnb.GnbPciAddress, StdHeader);
- }
- }
- IDS_HDT_CONSOLE (GNB_TRACE, "NbInitAtEnv Exit[0x%x]\n", AgesaStatus);
- return AgesaStatus;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtEnv.h b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtEnv.h
deleted file mode 100644
index 533cdd2..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtEnv.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * NB post init interface
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _NBINITATENV_H_
-#define _NBINITATENV_H_
-
-AGESA_STATUS
-NbInitAtEnv (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif
-
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtLatePost.c b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtLatePost.c
deleted file mode 100644
index 854f900..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtLatePost.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * NB late POST init interface
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:
- * @e sub-project:
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Gnb.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include GNB_MODULE_DEFINITIONS (GnbNbInitLibV1)
-#include "NbConfigData.h"
-#include "NbPowerMgmt.h"
-#include "NbInitAtLatePost.h"
-#include "Filecode.h"
-
-#define FILECODE PROC_GNB_NB_NBINITATLATEPOST_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init GNB at Late Post
- *
- *
- *
- * @param[in] StdHeader Standard configuration header
- * @retval AGESA_STATUS
- */
-
-AGESA_STATUS
-NbInitAtLatePost (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_STATUS Status;
- AGESA_STATUS AgesaStatus;
- GNB_PLATFORM_CONFIG Gnb;
- UINT32 NumberOfSockets;
- UINT32 SocketId;
- AgesaStatus = AGESA_SUCCESS;
- IDS_HDT_CONSOLE (GNB_TRACE, "NbInitAtLatePost Enter\n");
- Status = NbAllocateConfigData (StdHeader, &Gnb);
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
- NumberOfSockets = GnbGetNumberOfSockets (StdHeader);
- for (SocketId = 0; SocketId < NumberOfSockets; SocketId++) {
- UINT32 NumberOfSilicons;
- UINT32 SiliconId;
- if (!GnbIsDevicePresentInSocket (SocketId, StdHeader)) {
- continue;
- }
- NumberOfSilicons = GnbGetNumberOfSiliconsOnSocket (SocketId, StdHeader);
- for (SiliconId = 0; SiliconId < NumberOfSilicons; SiliconId++) {
- Gnb.GnbPciAddress = GnbGetPciAddress (SocketId, SiliconId, StdHeader);
- Status = NbInitPowerManagement (&Gnb);
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
- GnbLock (Gnb.GnbPciAddress, StdHeader);
- }
- }
- IDS_HDT_CONSOLE (GNB_TRACE, "NbInitAtLatePost Exit[0x%x]\n", Status);
- return Status;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtLatePost.h b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtLatePost.h
deleted file mode 100644
index c01b8fb..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtLatePost.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * NB late POST init interface
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:
- * @e sub-project:
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _NBINITATLATEPOST_H_
-#define _NBINITATLATEPOST_H_
-
-AGESA_STATUS
-NbInitAtLatePost (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtPost.c b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtPost.c
deleted file mode 100644
index c092f7f..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtPost.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * NB Post initialization interface
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Gnb.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include GNB_MODULE_DEFINITIONS (GnbNbInitLibV1)
-#include "NbConfigData.h"
-#include "NbInitAtPost.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_NB_NBINITATPOST_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init NB at POST
- *
- *
- *
- * @param[in] StdHeader Standard configuration header
- * @retval AGESA_STATUS
- */
-
-AGESA_STATUS
-NbInitAtPost (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_STATUS Status;
- AGESA_STATUS AgesaStatus;
- GNB_PLATFORM_CONFIG Gnb;
- UINT32 NumberOfSockets;
- UINT32 SocketId;
- AgesaStatus = AGESA_SUCCESS;
- IDS_HDT_CONSOLE (GNB_TRACE, "NbInitAtPost Enter\n");
- NbAllocateConfigData (StdHeader, &Gnb);
- NumberOfSockets = GnbGetNumberOfSockets (StdHeader);
- for (SocketId = 0; SocketId < NumberOfSockets; SocketId++) {
- UINT32 NumberOfSilicons;
- UINT32 SiliconId;
- if (!GnbIsDevicePresentInSocket (SocketId, StdHeader)) {
- continue;
- }
- NumberOfSilicons = GnbGetNumberOfSiliconsOnSocket (SocketId, StdHeader);
- for (SiliconId = 0; SiliconId < NumberOfSilicons; SiliconId++) {
- Gnb.GnbPciAddress = GnbGetPciAddress (SocketId, SiliconId, StdHeader);
- Status = GnbSetTom (Gnb.GnbPciAddress, StdHeader);
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
- ASSERT (Status == AGESA_SUCCESS);
- }
- }
- IDS_HDT_CONSOLE (GNB_TRACE, "NbInitAtPost Exit[0x%x]\n", AgesaStatus);
- return AgesaStatus;
-}
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtPost.h b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtPost.h
deleted file mode 100644
index 0106573..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtPost.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * NB Post initialization interface
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:
- * @e sub-project:
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _NBINITATPOST_H_
-#define _NBINITATPOST_H_
-
-AGESA_STATUS
-NbInitAtPost (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtReset.c b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtReset.c
deleted file mode 100644
index 1620c48..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtReset.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * NB reset init interface
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Gnb.h"
-#include "NbInitAtReset.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_NB_NBINITATRESET_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init GNB at Reset
- *
- *
- *
- * @param[in] StdHeader Standard configuration header
- * @retval AGESA_STATUS
- */
-
-AGESA_STATUS
-NbInitAtReset (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_STATUS Status;
- Status = AGESA_SUCCESS;
- return Status;
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtReset.h b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtReset.h
deleted file mode 100644
index 203ca22..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbInitAtReset.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * NB reset init interface
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project:
- * @e sub-project:
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _NBINITATRESET_H_
-#define _NBINITATRESET_H_
-
-AGESA_STATUS
-NbInitAtReset (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbPowerMgmt.c b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbPowerMgmt.c
deleted file mode 100644
index 11a8724..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbPowerMgmt.c
+++ /dev/null
@@ -1,600 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * NB power management features
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Gnb.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include "NbConfigData.h"
-#include "NbSmuLib.h"
-#include "NbPowerMgmt.h"
-#include "OptionGnb.h"
-#include "GfxLib.h"
-#include "GnbRegistersON.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_NB_NBPOWERMGMT_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-extern GNB_BUILD_OPTIONS GnbBuildOptions;
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
-*/
-
-VOID
-NbInitLclkDeepSleep (
- IN GNB_PLATFORM_CONFIG *Gnb
- );
-
-VOID
-NbInitClockGating (
- IN GNB_PLATFORM_CONFIG *Gnb
- );
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init various power management features
- *
- *
- *
- * @param[in] Gnb Pointer to global Gnb configuration
- * @retval AGESA_SUCCESS LCLK DPM initialization success
- * @retval AGESA_ERROR LCLK DPM initialization error
- */
-
-AGESA_STATUS
-NbInitPowerManagement (
- IN GNB_PLATFORM_CONFIG *Gnb
- )
-{
- AGESA_STATUS Status;
- Status = AGESA_SUCCESS;
- NbInitLclkDeepSleep (Gnb);
- NbInitClockGating (Gnb);
- return Status;
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init NB LCLK Deep Sleep
- *
- *
- *
- * @param[in] Gnb Pointer to global Gnb configuration
- */
-
-VOID
-NbInitLclkDeepSleep (
- IN GNB_PLATFORM_CONFIG *Gnb
- )
-{
- SMUx1B_STRUCT SMUx1B;
- SMUx1D_STRUCT SMUx1D;
- UINT32 LclkDpSlpEn;
- IDS_HDT_CONSOLE (GNB_TRACE, "NbInitLclkDeepSleep Enter\n");
- LclkDpSlpEn = GnbBuildOptions.LclkDeepSleepEn ? 1 : 0;
- NbSmuIndirectRead (SMUx1B_ADDRESS, AccessWidth16, &SMUx1B.Value, Gnb->StdHeader);
- NbSmuIndirectRead (SMUx1D_ADDRESS, AccessWidth16, &SMUx1D.Value, Gnb->StdHeader);
- SMUx1B.Field.LclkDpSlpDiv = 5;
- SMUx1B.Field.LclkDpSlpMask = (GfxLibIsControllerPresent (Gnb->StdHeader) ? (0xFF) : 0xEF);
- SMUx1B.Field.RampDis = 0;
- SMUx1D.Field.LclkDpSlpHyst = 0xf;
- IDS_OPTION_HOOK (IDS_GNB_LCLK_DEEP_SLEEP, &LclkDpSlpEn, Gnb->StdHeader);
- SMUx1D.Field.LclkDpSlpEn = LclkDpSlpEn;
- IDS_HDT_CONSOLE (GNB_TRACE, " LCLK Deep Sleep [%s]\n", (LclkDpSlpEn != 0) ? "Enabled" : "Disabled");
- NbSmuIndirectWrite (SMUx1B_ADDRESS, AccessS3SaveWidth16, &SMUx1B.Value, Gnb->StdHeader);
- NbSmuIndirectWrite (SMUx1D_ADDRESS, AccessS3SaveWidth16, &SMUx1D.Value, Gnb->StdHeader);
- IDS_HDT_CONSOLE (GNB_TRACE, "NbInitLclkDeepSleep Exit\n");
-}
-
-/**
- * Init NB SMU clock gating
- *
- *
- *
- * @param[in] NbClkGatingCtrl Pointer to Clock gating control structure
- * @param[in] Gnb Pointer to global Gnb configuration
- */
-
-VOID
-NbInitSmuClockGating (
- IN NB_CLK_GATING_CTRL *NbClkGatingCtrl,
- IN GNB_PLATFORM_CONFIG *Gnb
- )
-{
- BOOLEAN Smu_Lclk_Gating;
- BOOLEAN Smu_Sclk_Gating;
- SMUx73_STRUCT SMUx73;
- UINT32 Value;
-
- Smu_Lclk_Gating = NbClkGatingCtrl->Smu_Lclk_Gating;
- Smu_Sclk_Gating = NbClkGatingCtrl->Smu_Sclk_Gating;
-//SMUx6F
- Value = 0x006001F0;
- NbSmuIndirectWrite (SMUx6F_ADDRESS, AccessS3SaveWidth32, &Value, Gnb->StdHeader);
-//SMUx71
- Value = 0x007001F0;
- NbSmuIndirectWrite (SMUx71_ADDRESS, AccessS3SaveWidth32, &Value, Gnb->StdHeader);
-//SMUx73
- NbSmuIndirectRead (SMUx73_ADDRESS, AccessWidth16, &SMUx73.Value, Gnb->StdHeader);
- SMUx73.Field.DisLclkGating = Smu_Lclk_Gating ? 0 : 1;
- SMUx73.Field.DisSclkGating = Smu_Sclk_Gating ? 0 : 1;
- NbSmuIndirectWrite (SMUx73_ADDRESS, AccessS3SaveWidth16, &SMUx73.Value, Gnb->StdHeader);
-
-}
-
-/**
- * Init NB ORB clock gating
- *
- *
- *
- * @param[in] NbClkGatingCtrl Pointer to Clock gating control structure
- * @param[in] Gnb Pointer to global Gnb configuration
- */
-
-VOID
-NbInitOrbClockGating (
- IN NB_CLK_GATING_CTRL *NbClkGatingCtrl,
- IN GNB_PLATFORM_CONFIG *Gnb
- )
-{
- BOOLEAN Orb_Sclk_Gating;
- BOOLEAN Orb_Lclk_Gating;
- D0F0x98_x49_STRUCT D0F0x98_x49;
- D0F0x98_x4A_STRUCT D0F0x98_x4A;
- D0F0x98_x4B_STRUCT D0F0x98_x4B;
- FCRxFF30_01F5_STRUCT FCRxFF30_01F5;
-
- Orb_Sclk_Gating = NbClkGatingCtrl->Orb_Sclk_Gating;
- Orb_Lclk_Gating = NbClkGatingCtrl->Orb_Lclk_Gating;
-
- // ORB clock gating (Lclk)
-//D0F0x98_x4[A:9]
- GnbLibPciIndirectRead (
- Gnb->GnbPciAddress.AddressValue | D0F0x94_ADDRESS,
- D0F0x98_x49_ADDRESS,
- AccessWidth32,
- &D0F0x98_x49.Value,
- Gnb->StdHeader
- );
-
- D0F0x98_x49.Field.SoftOverrideClk6 = Orb_Lclk_Gating ? 0 : 1;
- D0F0x98_x49.Field.SoftOverrideClk5 = Orb_Lclk_Gating ? 0 : 1;
- D0F0x98_x49.Field.SoftOverrideClk4 = Orb_Lclk_Gating ? 0 : 1;
- D0F0x98_x49.Field.SoftOverrideClk3 = Orb_Lclk_Gating ? 0 : 1;
- D0F0x98_x49.Field.SoftOverrideClk2 = Orb_Lclk_Gating ? 0 : 1;
- D0F0x98_x49.Field.SoftOverrideClk1 = Orb_Lclk_Gating ? 0 : 1;
- D0F0x98_x49.Field.SoftOverrideClk0 = Orb_Lclk_Gating ? 0 : 1;
-
- GnbLibPciIndirectWrite (
- Gnb->GnbPciAddress.AddressValue | D0F0x94_ADDRESS,
- D0F0x98_x49_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET),
- AccessS3SaveWidth32,
- &D0F0x98_x49.Value,
- Gnb->StdHeader
- );
-
- GnbLibPciIndirectRead (
- Gnb->GnbPciAddress.AddressValue | D0F0x94_ADDRESS,
- D0F0x98_x4A_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET),
- AccessWidth32,
- &D0F0x98_x4A.Value,
- Gnb->StdHeader
- );
-
- D0F0x98_x4A.Field.SoftOverrideClk6 = Orb_Lclk_Gating ? 0 : 1;
- D0F0x98_x4A.Field.SoftOverrideClk5 = Orb_Lclk_Gating ? 0 : 1;
- D0F0x98_x4A.Field.SoftOverrideClk4 = Orb_Lclk_Gating ? 0 : 1;
- D0F0x98_x4A.Field.SoftOverrideClk3 = Orb_Lclk_Gating ? 0 : 1;
- D0F0x98_x4A.Field.SoftOverrideClk2 = Orb_Lclk_Gating ? 0 : 1;
- D0F0x98_x4A.Field.SoftOverrideClk1 = Orb_Lclk_Gating ? 0 : 1;
- D0F0x98_x4A.Field.SoftOverrideClk0 = Orb_Lclk_Gating ? 0 : 1;
-
-
- GnbLibPciIndirectWrite (
- Gnb->GnbPciAddress.AddressValue | D0F0x94_ADDRESS,
- D0F0x98_x4A_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET),
- AccessS3SaveWidth32,
- &D0F0x98_x4A.Value,
- Gnb->StdHeader
- );
-
-//D0F0x98_x4B
- GnbLibPciIndirectRead (
- Gnb->GnbPciAddress.AddressValue | D0F0x94_ADDRESS,
- D0F0x98_x4B_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET),
- AccessWidth32,
- &D0F0x98_x4B.Value,
- Gnb->StdHeader
- );
-
- D0F0x98_x4B.Field.SoftOverrideClk = Orb_Sclk_Gating ? 0 : 1;
-
- GnbLibPciIndirectWrite (
- Gnb->GnbPciAddress.AddressValue | D0F0x94_ADDRESS,
- D0F0x98_x4B_ADDRESS | (1 << D0F0x94_OrbIndWrEn_OFFSET),
- AccessS3SaveWidth32,
- &D0F0x98_x4B.Value,
- Gnb->StdHeader
- );
-
-//FCRxFF30_01F5[CgOrbCgttLclkOverride, CgOrbCgttSclkOverride]
- NbSmuSrbmRegisterRead (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, Gnb->StdHeader);
- FCRxFF30_01F5.Field.CgOrbCgttLclkOverride = 0;
- FCRxFF30_01F5.Field.CgOrbCgttSclkOverride = 0;
- NbSmuSrbmRegisterWrite (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, TRUE, Gnb->StdHeader);
-
-}
-
-/**
- * Init NB IOC clock gating
- *
- *
- *
- * @param[in] NbClkGatingCtrl Pointer to Clock gating control structure
- * @param[in] Gnb Pointer to global Gnb configuration
- */
-
-VOID
-NbInitIocClockGating (
- IN NB_CLK_GATING_CTRL *NbClkGatingCtrl,
- IN GNB_PLATFORM_CONFIG *Gnb
- )
-{
- BOOLEAN Ioc_Lclk_Gating;
- BOOLEAN Ioc_Sclk_Gating;
- D0F0x64_x22_STRUCT D0F0x64_x22;
- D0F0x64_x23_STRUCT D0F0x64_x23;
- D0F0x64_x24_STRUCT D0F0x64_x24;
- FCRxFF30_01F5_STRUCT FCRxFF30_01F5;
-
- Ioc_Lclk_Gating = NbClkGatingCtrl->Ioc_Lclk_Gating;
- Ioc_Sclk_Gating = NbClkGatingCtrl->Ioc_Sclk_Gating;
-
-//D0F0x64_x22
- GnbLibPciIndirectRead (
- Gnb->GnbPciAddress.AddressValue | D0F0x60_ADDRESS,
- D0F0x64_x22_ADDRESS | IOC_WRITE_ENABLE,
- AccessWidth32,
- &D0F0x64_x22.Value,
- Gnb->StdHeader
- );
-
- D0F0x64_x22.Field.SoftOverrideClk4 = Ioc_Lclk_Gating ? 0 : 1;
- D0F0x64_x22.Field.SoftOverrideClk3 = Ioc_Lclk_Gating ? 0 : 1;
- D0F0x64_x22.Field.SoftOverrideClk2 = Ioc_Lclk_Gating ? 0 : 1;
- D0F0x64_x22.Field.SoftOverrideClk1 = Ioc_Lclk_Gating ? 0 : 1;
- D0F0x64_x22.Field.SoftOverrideClk0 = Ioc_Lclk_Gating ? 0 : 1;
-
- GnbLibPciIndirectWrite (
- Gnb->GnbPciAddress.AddressValue | D0F0x60_ADDRESS,
- D0F0x64_x22_ADDRESS | IOC_WRITE_ENABLE,
- AccessS3SaveWidth32,
- &D0F0x64_x22.Value,
- Gnb->StdHeader
- );
-//D0F0x64_x23
- GnbLibPciIndirectRead (
- Gnb->GnbPciAddress.AddressValue | D0F0x60_ADDRESS,
- D0F0x64_x23_ADDRESS | IOC_WRITE_ENABLE,
- AccessWidth32,
- &D0F0x64_x23.Value,
- Gnb->StdHeader
- );
-
- //D0F0x64_x23.Field.SoftOverrideClk4 = Ioc_Lclk_Gating ? 0 : 1;
- D0F0x64_x23.Field.SoftOverrideClk3 = Ioc_Lclk_Gating ? 0 : 1;
- D0F0x64_x23.Field.SoftOverrideClk2 = Ioc_Lclk_Gating ? 0 : 1;
- D0F0x64_x23.Field.SoftOverrideClk1 = Ioc_Lclk_Gating ? 0 : 1;
- D0F0x64_x23.Field.SoftOverrideClk0 = Ioc_Lclk_Gating ? 0 : 1;
-
- GnbLibPciIndirectWrite (
- Gnb->GnbPciAddress.AddressValue | D0F0x60_ADDRESS,
- D0F0x64_x23_ADDRESS | IOC_WRITE_ENABLE,
- AccessS3SaveWidth32,
- &D0F0x64_x23.Value,
- Gnb->StdHeader
- );
- //D0F0x64_x24
- GnbLibPciIndirectRead (
- Gnb->GnbPciAddress.AddressValue | D0F0x60_ADDRESS,
- D0F0x64_x24_ADDRESS | IOC_WRITE_ENABLE,
- AccessWidth32,
- &D0F0x64_x24.Value,
- Gnb->StdHeader
- );
-
- D0F0x64_x24.Field.SoftOverrideClk1 = Ioc_Sclk_Gating ? 0 : 1;
- D0F0x64_x24.Field.SoftOverrideClk0 = Ioc_Sclk_Gating ? 0 : 1;
-
- GnbLibPciIndirectWrite (
- Gnb->GnbPciAddress.AddressValue | D0F0x60_ADDRESS,
- D0F0x64_x24_ADDRESS | IOC_WRITE_ENABLE,
- AccessS3SaveWidth32,
- &D0F0x64_x24.Value,
- Gnb->StdHeader
- );
-//FCRxFF30_01F5[CgIocCgttLclkOverride, CgIocCgttSclkOverride]
- NbSmuSrbmRegisterRead (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, Gnb->StdHeader);
- FCRxFF30_01F5.Field.CgIocCgttLclkOverride = 0;
- FCRxFF30_01F5.Field.CgIocCgttSclkOverride = 0;
- NbSmuSrbmRegisterWrite (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, TRUE, Gnb->StdHeader);
-}
-/**
- * Init NB BIF clock gating
- *
- *
- *
- * @param[in] NbClkGatingCtrl Pointer to Clock gating control structure
- * @param[in] Gnb Pointer to global Gnb configuration
- */
-
-VOID
-NbInitBifClockGating (
- IN NB_CLK_GATING_CTRL *NbClkGatingCtrl,
- IN GNB_PLATFORM_CONFIG *Gnb
- )
-{
- BOOLEAN Bif_Sclk_Gating;
- FCRxFF30_01F4_STRUCT FCRxFF30_01F4;
- FCRxFF30_1512_STRUCT FCRxFF30_1512;
-
-
- Bif_Sclk_Gating = NbClkGatingCtrl->Bif_Sclk_Gating;
-
-//FCRxFF30_01F4[CgBifCgttSclkOverride].
- NbSmuSrbmRegisterRead (FCRxFF30_01F4_ADDRESS, &FCRxFF30_01F4.Value, Gnb->StdHeader);
- FCRxFF30_01F4.Field.CgBifCgttSclkOverride = 0;
- NbSmuSrbmRegisterWrite (FCRxFF30_01F4_ADDRESS, &FCRxFF30_01F4.Value, TRUE, Gnb->StdHeader);
-//FCRxFF30_1512
- NbSmuSrbmRegisterRead (FCRxFF30_1512_ADDRESS, &FCRxFF30_1512.Value, Gnb->StdHeader);
- FCRxFF30_1512.Field.SoftOverride0 = Bif_Sclk_Gating ? 0 : 1;
- NbSmuSrbmRegisterWrite (FCRxFF30_1512_ADDRESS, &FCRxFF30_1512.Value, TRUE, Gnb->StdHeader);
-
-}
-
-/**
- * Init NB Gmc clock gating
- *
- *
- *
- * @param[in] NbClkGatingCtrl Pointer to Clock gating control structure
- * @param[in] Gnb Pointer to global Gnb configuration
- */
-
-VOID
-NbInitGmcClockGating (
- IN NB_CLK_GATING_CTRL *NbClkGatingCtrl,
- IN GNB_PLATFORM_CONFIG *Gnb
- )
-{
- BOOLEAN Gmc_Sclk_Gating;
- FCRxFF30_01F4_STRUCT FCRxFF30_01F4;
- FCRxFF30_01F5_STRUCT FCRxFF30_01F5;
-
- Gmc_Sclk_Gating = NbClkGatingCtrl->Gmc_Sclk_Gating;
-
-//FCRxFF30_01F4[CgMcdwCgttSclkOverride, CgMcbCgttSclkOverride]
- NbSmuSrbmRegisterRead (FCRxFF30_01F4_ADDRESS, &FCRxFF30_01F4.Value, Gnb->StdHeader);
- FCRxFF30_01F4.Field.CgMcbCgttSclkOverride = Gmc_Sclk_Gating ? 0 : 1;
- FCRxFF30_01F4.Field.CgMcdwCgttSclkOverride = Gmc_Sclk_Gating ? 0 : 1;
- NbSmuSrbmRegisterWrite (FCRxFF30_01F4_ADDRESS, &FCRxFF30_01F4.Value, TRUE, Gnb->StdHeader);
-
-//FCRxFF30_01F5[CgVmcCgttSclkOverride]
- NbSmuSrbmRegisterRead (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, Gnb->StdHeader);
- FCRxFF30_01F5.Field.CgVmcCgttSclkOverride = Gmc_Sclk_Gating ? 0 : 1;
- NbSmuSrbmRegisterWrite (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, TRUE, Gnb->StdHeader);
-
-}
-
-/**
- * Init NB Dce Sclk clock gating
- *
- *
- *
- * @param[in] NbClkGatingCtrl Pointer to Clock gating control structure
- * @param[in] Gnb Pointer to global Gnb configuration
- */
-
-VOID
-NbInitDceSclkClockGating (
- IN NB_CLK_GATING_CTRL *NbClkGatingCtrl,
- IN GNB_PLATFORM_CONFIG *Gnb
- )
-{
- BOOLEAN Dce_Sclk_Gating;
- FCRxFF30_0134_STRUCT FCRxFF30_0134;
- FCRxFF30_01F4_STRUCT FCRxFF30_01F4;
-
- Dce_Sclk_Gating = NbClkGatingCtrl->Dce_Sclk_Gating;
-
-//GMMx4D0[SymclkbGateDisable, SymclkaGateDisable, SclkGateDisable]
- NbSmuSrbmRegisterRead (FCRxFF30_0134_ADDRESS, &FCRxFF30_0134.Value, Gnb->StdHeader);
- FCRxFF30_0134.Field.SclkGateDisable = Dce_Sclk_Gating ? 0 : 1;
- FCRxFF30_0134.Field.SymclkaGateDisable = Dce_Sclk_Gating ? 0 : 1;
- FCRxFF30_0134.Field.SymclkbGateDisable = Dce_Sclk_Gating ? 0 : 1;
- NbSmuSrbmRegisterWrite (FCRxFF30_0134_ADDRESS, &FCRxFF30_0134.Value, TRUE, Gnb->StdHeader);
-
-//FCRxFF30_01F4[CgDcCgttSclkOverride]
- NbSmuSrbmRegisterRead (FCRxFF30_01F4_ADDRESS, &FCRxFF30_01F4.Value, Gnb->StdHeader);
- FCRxFF30_01F4.Field.CgDcCgttSclkOverride = 0;
- NbSmuSrbmRegisterWrite (FCRxFF30_01F4_ADDRESS, &FCRxFF30_01F4.Value, TRUE, Gnb->StdHeader);
-
-}
-
-/**
- * Init NB Dce Display clock gating
- *
- *
- *
- * @param[in] NbClkGatingCtrl Pointer to Clock gating control structure
- * @param[in] Gnb Pointer to global Gnb configuration
- */
-
-VOID
-NbInitDceDisplayClockGating (
- IN NB_CLK_GATING_CTRL *NbClkGatingCtrl,
- IN GNB_PLATFORM_CONFIG *Gnb
- )
-{
- BOOLEAN Dce_Dispclk_Gating;
- FCRxFF30_0134_STRUCT FCRxFF30_0134;
- FCRxFF30_1B7C_STRUCT FCRxFF30_1B7C;
- FCRxFF30_1E7C_STRUCT FCRxFF30_1E7C;
- FCRxFF30_01F5_STRUCT FCRxFF30_01F5;
-
- Dce_Dispclk_Gating = NbClkGatingCtrl->Dce_Dispclk_Gating;
-
-//GMMx4D0[DispclkRDccgGateDisable,DispclkDccgGateDisable]
- NbSmuSrbmRegisterRead (FCRxFF30_0134_ADDRESS, &FCRxFF30_0134.Value, Gnb->StdHeader);
- FCRxFF30_0134.Field.DispclkDccgGateDisable = Dce_Dispclk_Gating ? 0 : 1;
- FCRxFF30_0134.Field.DispclkRDccgGateDisable = Dce_Dispclk_Gating ? 0 : 1;
- NbSmuSrbmRegisterWrite (FCRxFF30_0134_ADDRESS, &FCRxFF30_0134.Value, TRUE, Gnb->StdHeader);
-
-//GMMx[79,6D]F0[CrtcDispclkGSclGateDisable, CrtcDispclkGDcpGateDisable, CrtcDispclkRDcfeGateDisable]
- NbSmuSrbmRegisterRead (FCRxFF30_1B7C_ADDRESS, &FCRxFF30_1B7C.Value, Gnb->StdHeader);
- FCRxFF30_1B7C.Field.CrtcDispclkRDcfeGateDisable = Dce_Dispclk_Gating ? 0 : 1;
- FCRxFF30_1B7C.Field.CrtcDispclkGDcpGateDisable = Dce_Dispclk_Gating ? 0 : 1;
- FCRxFF30_1B7C.Field.CrtcDispclkGSclGateDisable = Dce_Dispclk_Gating ? 0 : 1;
- NbSmuSrbmRegisterWrite (FCRxFF30_1B7C_ADDRESS, &FCRxFF30_1B7C.Value, TRUE, Gnb->StdHeader);
-
- NbSmuSrbmRegisterRead (FCRxFF30_1E7C_ADDRESS, &FCRxFF30_1E7C.Value, Gnb->StdHeader);
- FCRxFF30_1E7C.Field.CrtcDispclkRDcfeGateDisable = Dce_Dispclk_Gating ? 0 : 1;
- FCRxFF30_1E7C.Field.CrtcDispclkGDcpGateDisable = Dce_Dispclk_Gating ? 0 : 1;
- FCRxFF30_1E7C.Field.CrtcDispclkGSclGateDisable = Dce_Dispclk_Gating ? 0 : 1;
- NbSmuSrbmRegisterWrite (FCRxFF30_1E7C_ADDRESS, &FCRxFF30_1E7C.Value, TRUE, Gnb->StdHeader);
-
-//FCRxFF30_01F5[CgDcCgttDispclkOverride]
- NbSmuSrbmRegisterRead (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, Gnb->StdHeader);
- FCRxFF30_01F5.Field.CgDcCgttDispClkOverride = 0;
- NbSmuSrbmRegisterWrite (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, TRUE, Gnb->StdHeader);
-
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init NB clock gating
- *
- *
- *
- * @param[in] Gnb Pointer to global Gnb configuration
- */
-
-VOID
-NbInitClockGating (
- IN GNB_PLATFORM_CONFIG *Gnb
- )
-{
- NB_CLK_GATING_CTRL NbClkGatingCtrl;
-
- //Init the default value of control structure.
- NbClkGatingCtrl.Smu_Sclk_Gating = GnbBuildOptions.SmuSclkClockGatingEnable;
- NbClkGatingCtrl.Smu_Lclk_Gating = TRUE;
- NbClkGatingCtrl.Orb_Sclk_Gating = TRUE;
- NbClkGatingCtrl.Orb_Lclk_Gating = TRUE;
- NbClkGatingCtrl.Ioc_Sclk_Gating = TRUE;
- NbClkGatingCtrl.Ioc_Lclk_Gating = TRUE;
- NbClkGatingCtrl.Bif_Sclk_Gating = TRUE;
- NbClkGatingCtrl.Gmc_Sclk_Gating = TRUE;
- NbClkGatingCtrl.Dce_Sclk_Gating = TRUE;
- NbClkGatingCtrl.Dce_Dispclk_Gating = TRUE;
-
- IDS_OPTION_HOOK (IDS_GNB_CLOCK_GATING, &NbClkGatingCtrl, Gnb->StdHeader);
-
-
- IDS_HDT_CONSOLE (GNB_TRACE, "NbInitClockGating Enter\n");
-
-//SMU SCLK/LCLK clock gating
- NbInitSmuClockGating (&NbClkGatingCtrl, Gnb);
-
-// ORB clock gating
- NbInitOrbClockGating (&NbClkGatingCtrl, Gnb);
-
-//IOC clock gating
- NbInitIocClockGating (&NbClkGatingCtrl, Gnb);
-
-//BIF Clock Gating
- NbInitBifClockGating (&NbClkGatingCtrl, Gnb);
-
-//GMC Clock Gating
- NbInitGmcClockGating (&NbClkGatingCtrl, Gnb);
-
-//DCE Sclk clock gating
- NbInitDceSclkClockGating (&NbClkGatingCtrl, Gnb);
-
-//DCE Display clock gating
- NbInitDceDisplayClockGating (&NbClkGatingCtrl, Gnb);
-
- GNB_DEBUG_CODE (
- {
- FCRxFF30_01F4_STRUCT FCRxFF30_01F4;
- FCRxFF30_01F5_STRUCT FCRxFF30_01F5;
- FCRxFF30_1512_STRUCT FCRxFF30_1512;
- NbSmuSrbmRegisterRead (FCRxFF30_01F4_ADDRESS, &FCRxFF30_01F4.Value, Gnb->StdHeader);
- NbSmuSrbmRegisterRead (FCRxFF30_01F5_ADDRESS, &FCRxFF30_01F5.Value, Gnb->StdHeader);
- NbSmuSrbmRegisterRead (FCRxFF30_1512_ADDRESS, &FCRxFF30_1512.Value, Gnb->StdHeader);
- IDS_HDT_CONSOLE (NB_MISC, " Clock Gating FCRxFF30_01F4 - 0x%x\n", FCRxFF30_01F4.Value);
- IDS_HDT_CONSOLE (NB_MISC, " Clock Gating FCRxFF30_01F5 - 0x%x\n", FCRxFF30_01F5.Value);
- IDS_HDT_CONSOLE (NB_MISC, " Clock Gating FCRxFF30_1512 - 0x%x\n", FCRxFF30_1512.Value);
- }
- );
- IDS_HDT_CONSOLE (GNB_TRACE, "NbInitClockGating End\n");
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbPowerMgmt.h b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbPowerMgmt.h
deleted file mode 100644
index bb5a549..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbPowerMgmt.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * NB power management features
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _NBPOWERMGMT_H_
-#define _NBPOWERMGMT_H_
-
-
-AGESA_STATUS
-NbInitPowerManagement (
- IN GNB_PLATFORM_CONFIG *Gnb
- );
-
-///Control structure for clock gating feature
-typedef struct {
- BOOLEAN Smu_Sclk_Gating; ///<Control Smu SClk gating 1 Enable 0 Disable
- BOOLEAN Smu_Lclk_Gating; ///<Control Smu LClk gating 1 Enable 0 Disable
- BOOLEAN Orb_Sclk_Gating; ///<Control ORB SClk gating 1 Enable 0 Disable
- BOOLEAN Orb_Lclk_Gating; ///<Control ORB LClk gating 1 Enable 0 Disable
- BOOLEAN Ioc_Sclk_Gating; ///<Control IOC SClk gating 1 Enable 0 Disable
- BOOLEAN Ioc_Lclk_Gating; ///<Control IOC LClk gating 1 Enable 0 Disable
- BOOLEAN Bif_Sclk_Gating; ///<Control BIF SClk gating 1 Enable 0 Disable
- BOOLEAN Gmc_Sclk_Gating; ///<Control GMC SClk gating 1 Enable 0 Disable
- BOOLEAN Dce_Sclk_Gating; ///<Control DCE SClk gating 1 Enable 0 Disable
- BOOLEAN Dce_Dispclk_Gating; ///<Control DCE dispaly gating 1 Enable 0 Disable
-} NB_CLK_GATING_CTRL;
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbSmuLib.c b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbSmuLib.c
deleted file mode 100644
index fa3ac06..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbSmuLib.c
+++ /dev/null
@@ -1,652 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * SMU access routine
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Gnb.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include "OptionGnb.h"
-#include "NbSmuLib.h"
-#include "GnbRegistersON.h"
-#include "S3SaveState.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_NB_NBSMULIB_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/// Efuse write packet
-typedef struct {
- SMUx0B_x8600_STRUCT SMUx0B_x8600; ///< Reg SMUx0B_x8600
- SMUx0B_x8604_STRUCT SMUx0B_x8604; ///< Reg SMUx0B_x8604
- SMUx0B_x8608_STRUCT SMUx0B_x8608; ///< Reg SMUx0B_x8605
-} MBUS;
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * SMU indirect register read
- *
- *
- *
- * @param[in] Address Register Address
- * @param[in] Width Data width for read
- * @param[out] Value Pointer read value
- * @param[in] StdHeader Pointer to standard configuration
- */
-
-
-VOID
-NbSmuIndirectRead (
- IN UINT8 Address,
- IN ACCESS_WIDTH Width,
- OUT VOID *Value,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
-
- D0F0x64_x4D_STRUCT D0F0x64_x4D;
- UINT32 Data;
- GnbLibPciIndirectRead (
- MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS),
- D0F0x64_x4D_ADDRESS | IOC_WRITE_ENABLE,
- AccessWidth32,
- &D0F0x64_x4D.Value,
- StdHeader
- );
-
- D0F0x64_x4D.Field.ReqType = 0;
- D0F0x64_x4D.Field.SmuAddr = Address;
- if (Width == AccessS3SaveWidth32 || Width == AccessWidth32) {
- D0F0x64_x4D.Field.SmuAddr += 1;
- }
-
- D0F0x64_x4D.Field.ReqToggle = !D0F0x64_x4D.Field.ReqToggle;
-
- GnbLibPciIndirectWrite (
- MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS),
- D0F0x64_x4D_ADDRESS | IOC_WRITE_ENABLE,
- (Width >= AccessS3SaveWidth8) ? AccessS3SaveWidth32 : AccessWidth32,
- &D0F0x64_x4D.Value,
- StdHeader
- );
-
- GnbLibPciIndirectRead (
- MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS),
- D0F0x64_x4E_ADDRESS | IOC_WRITE_ENABLE,
- (Width >= AccessS3SaveWidth8) ? AccessS3SaveWidth32 : AccessWidth32,
- &Data,
- StdHeader
- );
-
- switch (Width) {
- case AccessWidth16:
- //no break; intended to fall through
- case AccessS3SaveWidth16:
- *(UINT16 *) Value = (UINT16) Data;
- break;
- case AccessWidth32:
- //no break; intended to fall through
- case AccessS3SaveWidth32:
- *(UINT32 *) Value = Data;
- break;
- default:
- ASSERT (FALSE);
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * SMU indirect register read
- *
- *
- *
- * @param[in] Address Register Address
- * @param[in] Width Access width
- * @param[in] Mask Data mask for compare
- * @param[in] CompateData Compare data
- * @param[in] StdHeader Pointer to standard configuration
- */
-
-
-VOID
-NbSmuIndirectPoll (
- IN UINT8 Address,
- IN ACCESS_WIDTH Width,
- IN UINT32 Mask,
- IN UINT32 CompateData,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Value;
-
- do {
- NbSmuIndirectRead (
- Address,
- Width,
- &Value,
- StdHeader
- );
- } while ((Value & Mask) != CompateData);
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * SMU indirect register write
- *
- *
- *
- * @param[in] Address Register Address
- * @param[in] Width Data width for write
- * @param[in] Value Pointer to write value
- * @param[in] StdHeader Pointer to standard configuration
- */
-
-
-VOID
-NbSmuIndirectWriteEx (
- IN UINT8 Address,
- IN ACCESS_WIDTH Width,
- IN VOID *Value,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- D0F0x64_x4D_STRUCT D0F0x64_x4D;
- ASSERT (Width != AccessWidth8);
- ASSERT (Width != AccessS3SaveWidth8);
-
- GnbLibPciIndirectRead (
- MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS),
- D0F0x64_x4D_ADDRESS | IOC_WRITE_ENABLE,
- AccessWidth32,
- &D0F0x64_x4D.Value,
- StdHeader
- );
-
- D0F0x64_x4D.Field.ReqType = 0x1;
- D0F0x64_x4D.Field.SmuAddr = Address;
- D0F0x64_x4D.Field.ReqToggle = (!D0F0x64_x4D.Field.ReqToggle);
-
- D0F0x64_x4D.Field.WriteData = ((UINT16 *) Value) [0];
-
- GnbLibPciIndirectWrite (
- MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS),
- D0F0x64_x4D_ADDRESS | IOC_WRITE_ENABLE,
- (Width >= AccessS3SaveWidth8) ? AccessS3SaveWidth32 : AccessWidth32,
- &D0F0x64_x4D.Value,
- StdHeader
- );
- if (LibAmdAccessWidth (Width) <= 2) {
- return;
- }
- D0F0x64_x4D.Field.ReqType = 0x1;
- D0F0x64_x4D.Field.SmuAddr = Address + 1;
- D0F0x64_x4D.Field.ReqToggle = (!D0F0x64_x4D.Field.ReqToggle);
- D0F0x64_x4D.Field.WriteData = ((UINT16 *) Value)[1];
-
- GnbLibPciIndirectWrite (
- MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS),
- D0F0x64_x4D_ADDRESS | IOC_WRITE_ENABLE,
- (Width >= AccessS3SaveWidth8) ? AccessS3SaveWidth32 : AccessWidth32,
- &D0F0x64_x4D.Value,
- StdHeader
- );
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * SMU indirect register write
- *
- *
- *
- * @param[in] Address Register Address
- * @param[in] Width Data width for write
- * @param[in] Value Pointer to write value
- * @param[in] StdHeader Pointer to standard configuration
- */
-
-
-VOID
-NbSmuIndirectWrite (
- IN UINT8 Address,
- IN ACCESS_WIDTH Width,
- IN VOID *Value,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- if (Width >= AccessS3SaveWidth8) {
- SMU_INDIRECT_WRITE_DATA Data;
- Data.Address = Address;
- Data.Width = Width;
- Data.Value = *((UINT32*) Value);
- S3_SAVE_DISPATCH (StdHeader, S3DispatchGnbSmuIndirectWrite, sizeof (SMU_INDIRECT_WRITE_DATA), &Data);
- Width = Width - (AccessS3SaveWidth8 - AccessWidth8);
- }
- NbSmuIndirectWriteEx (Address, Width, Value, StdHeader);
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * SMU Service request for S3 script
- *
- *
- * @param[in] StdHeader Standard configuration header
- * @param[in] ContextLength Not used
- * @param[in] Context Pointer to service request ID
- */
-
-VOID
-NbSmuIndirectWriteS3Script (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN UINT16 ContextLength,
- IN VOID* Context
- )
-{
- SMU_INDIRECT_WRITE_DATA *Data;
- Data = (SMU_INDIRECT_WRITE_DATA*) Context;
- NbSmuIndirectWriteEx (Data->Address, Data->Width, &Data->Value, StdHeader);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * SMU RAM mapped register write
- *
- *
- *
- * @param[in] Address Register Address
- * @param[in] Value Data pointer for write
- * @param[in] Count Number of registers to write
- * @param[in] S3Save Save for S3 (True/False)
- * @param[in] StdHeader Standard configuration header
- */
-
-VOID
-NbSmuRcuRegisterWrite (
- IN UINT16 Address,
- IN UINT32 *Value,
- IN UINT32 Count,
- IN BOOLEAN S3Save,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 CurrentAddress;
- CurrentAddress = Address;
- NbSmuIndirectWrite (
- SMUx0B_ADDRESS,
- S3Save ? AccessS3SaveWidth16 : AccessWidth16,
- &Address,
- StdHeader
- );
- while (Count-- > 0) {
- IDS_HDT_CONSOLE (NB_SMUREG_TRACE, " *WR SMUx0B:0x%x = 0x%x\n", CurrentAddress, *Value);
- NbSmuIndirectWrite (
- SMUx05_ADDRESS,
- S3Save ? AccessS3SaveWidth32 : AccessWidth32,
- Value++,
- StdHeader
- );
- CurrentAddress += 4;
- }
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * SMU RAM mapped register read
- *
- *
- *
- * @param[in] Address Register Address
- * @param[out] Value Pointer read value
- * @param[in] Count Number of registers to read
- * @param[in] StdHeader Pointer to standard configuration
- */
-
-VOID
-NbSmuRcuRegisterRead (
- IN UINT16 Address,
- OUT UINT32 *Value,
- IN UINT32 Count,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- NbSmuIndirectWrite (SMUx0B_ADDRESS, AccessWidth16, &Address, StdHeader);
- while (Count-- > 0) {
- NbSmuIndirectRead (SMUx05_ADDRESS, AccessWidth32, Value++, StdHeader);
- }
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * SMU Service request Ext
- *
- *
- * @param[in] RequestId request ID
- * @param[in] Flags Flags
- * @param[in] StdHeader Standard configuration header
- */
-
-VOID
-NbSmuServiceRequestEx (
- IN UINT8 RequestId,
- IN UINT8 Flags,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- SMUx03_STRUCT SMUx03;
- SMUx03.Value = 0;
- SMUx03.Field.IntReq = 1;
- SMUx03.Field.ServiceIndex = RequestId;
- NbSmuIndirectWrite (SMUx03_ADDRESS, AccessWidth32, &SMUx03.Value, StdHeader);
- if ((Flags & SMU_EXT_SERVICE_FLAGS_POLL_ACK) != 0) {
- NbSmuIndirectPoll (SMUx03_ADDRESS, AccessWidth32, BIT1, BIT1, StdHeader); // Wait till IntAck
- }
- if ((Flags & SMU_EXT_SERVICE_FLAGS_POLL_DONE) != 0) {
- NbSmuIndirectPoll (SMUx03_ADDRESS, AccessWidth32, BIT2, BIT2, StdHeader); // Wait till IntDone
- }
- SMUx03.Value = 0; // Clear IRQ register
- NbSmuIndirectWrite (SMUx03_ADDRESS, AccessWidth32, &SMUx03.Value, StdHeader);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * SMU Service request
- *
- *
- * @param[in] RequestId request ID
- * @param[in] S3Save Save for S3 (True/False)
- * @param[in] StdHeader Standard configuration header
- */
-
-VOID
-NbSmuServiceRequest (
- IN UINT8 RequestId,
- IN BOOLEAN S3Save,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuServiceRequest Enter [0x%02x]\n", RequestId);
- if (S3Save) {
- S3_SAVE_DISPATCH (StdHeader, S3DispatchGnbSmuServiceRequest, sizeof (RequestId), &RequestId);
- }
- NbSmuServiceRequestEx (
- RequestId,
- SMU_EXT_SERVICE_FLAGS_POLL_ACK | SMU_EXT_SERVICE_FLAGS_POLL_DONE,
- StdHeader
- );
- IDS_HDT_CONSOLE (GNB_TRACE, "NbSmuServiceRequest Exit\n");
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * SMU Service request for S3 script
- *
- *
- * @param[in] StdHeader Standard configuration header
- * @param[in] ContextLength Not used
- * @param[in] Context Pointer to service request ID
- */
-
-VOID
-NbSmuServiceRequestS3Script (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN UINT16 ContextLength,
- IN VOID* Context
- )
-{
- NbSmuServiceRequest (*((UINT8*) Context), FALSE, StdHeader);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * SMU Read FCR register
- *
- *
- * @param[in] Address FCR Address
- * @param[in] StdHeader Standard configuration header
- */
-
-UINT32
-NbSmuReadEfuse (
- IN UINT32 Address,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Value;
-
- NbSmuSrbmRegisterRead (Address, &Value, StdHeader);
- Value = (Value >> 24) | (Value << 24) | ((Value >> 8) & 0xFF00) | ((Value << 8) & 0xFF0000);
- return Value;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * SMU Read arbitrary fuse field
- *
- *
- * @param[in] Chain Address
- * @param[in] Offset Offcet
- * @param[in] Length Length
- * @param[in] StdHeader Standard configuration header
- */
-
-UINT32
-NbSmuReadEfuseField (
- IN UINT8 Chain,
- IN UINT16 Offset,
- IN UINT8 Length,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 Value;
- UINT32 Result;
- UINT32 Address;
- UINT16 Shift;
- ASSERT (Length <= 32);
- ASSERT (Chain <= 0xff);
- Shift = (Offset - (Offset & ~0x7));
- Address = 0xFE000000 | (Chain << 12) | (Offset >> 3);
- Value = NbSmuReadEfuse (Address, StdHeader);
- Result = Value >> Shift;
- if ((Shift + Length) > 32) {
- Value = NbSmuReadEfuse (Address + 1, StdHeader);
- Result |= (Value << (32 - Shift));
- }
- Result &= ((1 << Length) - 1);
- return Value;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * SMU SRBM (GMM) register read
- *
- *
- *
- * @param[in] Address Register Address
- * @param[out] Value Pointer read value
- * @param[in] StdHeader Pointer to standard configuration
- */
-
-VOID
-NbSmuSrbmRegisterRead (
- IN UINT32 Address,
- OUT UINT32 *Value,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- MBUS Mbus;
- Mbus.SMUx0B_x8600.Value = (0x8650 << SMUx0B_x8600_MemAddr_7_0__OFFSET) |
- (1 << SMUx0B_x8600_TransactionCount_OFFSET);
- Mbus.SMUx0B_x8604.Value = (4 << SMUx0B_x8604_Txn1TransferLength_7_0__OFFSET);
- Mbus.SMUx0B_x8608.Value = (UINT32) (3 << SMUx0B_x8608_Txn1Tsize_OFFSET);
- Mbus.SMUx0B_x8600.Field.Txn1MBusAddr_7_0_ = Address & 0xff;
- Mbus.SMUx0B_x8604.Field.Txn1MBusAddr_15_8_ = (Address >> 8) & 0xff;
- Mbus.SMUx0B_x8604.Field.Txn1MBusAddr_23_16_ = (Address >> 16) & 0xff;
- Mbus.SMUx0B_x8604.Field.Txn1MBusAddr_31_24_ = (Address >> 24) & 0xff;
- NbSmuRcuRegisterWrite (SMUx0B_x8600_ADDRESS, (UINT32*) &Mbus, 3, FALSE, StdHeader);
- NbSmuServiceRequest (0x0B, FALSE, StdHeader);
- NbSmuRcuRegisterRead (SMUx0B_x8650_ADDRESS, Value, 1, StdHeader);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * SMU SRBM (GMM) register write
- *
- *
- *
- * @param[in] Address Register Address
- * @param[in] Value Data pointer for write
- * @param[in] S3Save Save for S3 (True/False)
- * @param[in] StdHeader Standard configuration header
- */
-
-VOID
-NbSmuSrbmRegisterWrite (
- IN UINT32 Address,
- IN UINT32 *Value,
- IN BOOLEAN S3Save,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- MBUS Mbus;
- IDS_HDT_CONSOLE (NB_SMUREG_TRACE, " *WR SRBM (GMM):0x%x = 0x%x\n", Address, *Value);
- Mbus.SMUx0B_x8600.Value = (0x8650 << SMUx0B_x8600_MemAddr_7_0__OFFSET) |
- (1 << SMUx0B_x8600_TransactionCount_OFFSET);
- Mbus.SMUx0B_x8604.Value = (4 << SMUx0B_x8604_Txn1TransferLength_7_0__OFFSET);
- Mbus.SMUx0B_x8608.Value = (UINT32) (3 << SMUx0B_x8608_Txn1Tsize_OFFSET);
- Mbus.SMUx0B_x8608.Field.Txn1Mode = 0x1;
- Mbus.SMUx0B_x8600.Field.Txn1MBusAddr_7_0_ = Address & 0xff;
- Mbus.SMUx0B_x8604.Field.Txn1MBusAddr_15_8_ = (Address >> 8) & 0xff;
- Mbus.SMUx0B_x8604.Field.Txn1MBusAddr_23_16_ = (Address >> 16) & 0xff;
- Mbus.SMUx0B_x8604.Field.Txn1MBusAddr_31_24_ = (Address >> 24) & 0xff;
- NbSmuRcuRegisterWrite (SMUx0B_x8600_ADDRESS, (UINT32*) &Mbus, 3, S3Save, StdHeader);
- NbSmuRcuRegisterWrite (SMUx0B_x8650_ADDRESS, Value, 1, S3Save, StdHeader);
- NbSmuServiceRequest (0x0B, S3Save, StdHeader);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * SMU firmware download
- *
- *
- *
- * @param[in] StdHeader Pointer to Standard configuration
- * @param[in] Firmware Pointer to SMU firmware header
- * @retval AGESA_STATUS
- */
-
-VOID
-NbSmuFirmwareDownload (
- IN SMU_FIRMWARE_HEADER *Firmware,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINTN Index;
- SMUx01_STRUCT SMUx01;
- NbSmuServiceRequestEx (0x10, SMU_EXT_SERVICE_FLAGS_POLL_ACK , StdHeader);
- SMUx01.Value = (1 << SMUx01_RamSwitch_OFFSET) | (1 << SMUx01_VectorOverride_OFFSET);
- NbSmuIndirectWrite (SMUx01_ADDRESS, AccessWidth32, &SMUx01.Value, StdHeader);
- for (Index = 0; Index < Firmware->NumberOfBlock; Index++) {
- NbSmuRcuRegisterWrite (
- (Firmware->BlockArray)[Index].Address,
- (Firmware->BlockArray)[Index].Data,
- (Firmware->BlockArray)[Index].Length,
- FALSE,
- StdHeader
- );
- }
- SMUx01.Value = (1 << SMUx01_Reset_OFFSET) | (1 << SMUx01_VectorOverride_OFFSET);
- NbSmuIndirectWrite (SMUx01_ADDRESS, AccessWidth32, &SMUx01.Value, StdHeader);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * SMU firmware revision
- *
- *
- *
- * @param[in] StdHeader Pointer to Standard configuration
- * @retval Firmware revision info
- */
-
-SMU_FIRMWARE_REV
-NbSmuFirmwareRevision (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- SMU_FIRMWARE_REV Revision;
- UINT32 FmRev;
- NbSmuRcuRegisterRead (
- 0x830C,
- &FmRev,
- 1,
- StdHeader
- );
- Revision.MajorRev = ((UINT16*)&FmRev) [1];
- Revision.MinorRev = ((UINT16*)&FmRev) [0];
- return Revision;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbSmuLib.h b/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbSmuLib.h
deleted file mode 100644
index a54b7e8..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/Nb/NbSmuLib.h
+++ /dev/null
@@ -1,185 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Various NB initialization services
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _NBSMULIB_H_
-#define _NBSMULIB_H_
-
-
-#define SMU_EXT_SERVICE_FLAGS_POLL_ACK 0x1
-#define SMU_EXT_SERVICE_FLAGS_POLL_DONE 0x2
-#define SMU_GMM_TO_FCR(GmmReg) ((GmmReg >> 2) | 0xFF300000)
-
-#pragma pack (push, 1)
-/// SMU Register Entry
-typedef struct {
- UINT16 Reg; ///< Register address
- UINT32 Value; ///< Register data
-} SMU_REGISTER_ENTRY;
-
-/// SMU Firmware revision
-typedef struct {
- UINT16 MajorRev; ///< Major revision
- UINT16 MinorRev; ///< Minor revision
-} SMU_FIRMWARE_REV;
-
-/// Firmware block
-typedef struct {
- UINT16 Address; ///< Block Address
- UINT16 Length; ///< Block length in DWORD
- UINT32 *Data; ///< Pointer to data array
-} SMU_FIRMWARE_BLOCK;
-
-/// Firmware header
-typedef struct {
- SMU_FIRMWARE_REV Revision; ///< Revision info
- UINT16 NumberOfBlock; ///< Number of blocks
- SMU_FIRMWARE_BLOCK *BlockArray; ///< Pointer to block definition array
-} SMU_FIRMWARE_HEADER;
-
-/// SMU indirect register write data context
-typedef struct {
- UINT8 Address; ///< SMU indirect register address
- ACCESS_WIDTH Width; ///< SMU indirect register width
- UINT32 Value; ///< Value
-} SMU_INDIRECT_WRITE_DATA;
-#pragma pack (pop)
-
-VOID
-NbSmuIndirectRead (
- IN UINT8 Address,
- IN ACCESS_WIDTH Width,
- OUT VOID *Value,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-NbSmuIndirectPoll (
- IN UINT8 Address,
- IN ACCESS_WIDTH Width,
- IN UINT32 Mask,
- IN UINT32 CompateData,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-NbSmuIndirectWrite (
- IN UINT8 Address,
- IN ACCESS_WIDTH Width,
- IN VOID *Value,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-NbSmuRcuRegisterWrite (
- IN UINT16 Address,
- IN UINT32 *Value,
- IN UINT32 Count,
- IN BOOLEAN S3Save,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-NbSmuRcuRegisterRead (
- IN UINT16 Address,
- OUT UINT32 *Value,
- IN UINT32 Count,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-NbSmuSrbmRegisterRead (
- IN UINT32 Address,
- OUT UINT32 *Value,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-NbSmuSrbmRegisterWrite (
- IN UINT32 Address,
- IN UINT32 *Value,
- IN BOOLEAN S3Save,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-NbSmuServiceRequestEx (
- IN UINT8 RequestId,
- IN UINT8 Flags,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-NbSmuServiceRequest (
- IN UINT8 RequestId,
- IN BOOLEAN S3Save,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-NbSmuServiceRequestS3Script (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN UINT16 ContextLength,
- IN VOID* Context
- );
-
-UINT32
-NbSmuReadEfuse (
- IN UINT32 Address,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-NbSmuFirmwareDownload (
- IN SMU_FIRMWARE_HEADER *Firmware,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-SMU_FIRMWARE_REV
-NbSmuFirmwareRevision (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#define SMI_FIRMWARE_REVISION(x) ((x.MajorRev << 16) | x.MinorRev)
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.c b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.c
deleted file mode 100644
index e23cc7c..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe ALIB
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "F14PcieAlibSsdt.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_PCIE_FAMILY_0X14_F14PCIEALIB_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.esl b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.esl
deleted file mode 100644
index d33c341..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.esl
+++ /dev/null
@@ -1,126 +0,0 @@
-/**
- * @file
- *
- * ALIB ASL library
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 31805 $ @e \$Date: 2010-05-21 17:58:16 -0700 (Fri, 21 May 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-DefinitionBlock (
- "F14PcieAlibSsdt.aml",
- "SSDT",
- 2,
- "AMD",
- "ALIB",
- 0x1
- )
-{
- Scope(\_SB) {
-
- Name (varMaxPortIndexNumber, 6)
-
- include ("PcieAlibCore.asl")
- include ("PcieSmuLibV1.asl")
- include ("PcieAlibPspp.asl")
- include ("PcieAlibHotplug.asl")
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * Activate DPM state
- *
- * Arg0 - 1 - GEN1 2 - GEN2
- * Arg1 - 0 (AC) 1 (DC)
- */
- Method (procNbLclkDpmActivate, 2, NotSerialized) {
-
- Store (procSmuRcuRead (0x8490), Local0)
- // Patch state only if at least one state is enable
- if (LNotEqual (And (Local0, 0xF0), 0)) {
- if (LEqual (Arg0, 2)) {
- //If AC/DC, & Gen2 supported, activate state DPM0 and DPM2,
- //set SMUx0B_x8490[LclkDpmValid[5, 7] = 1, set SMUx0B_x8490[LclkDpmValid[6]] = 0
- //This is a battery ¡¥idle¡¦ state along with a ¡¥perf¡¦ state that will be programmed to the max LCLK achievable at the Gen2 VID
- And (Local0, 0xFFFFFFA0, Local0)
- Or (Local0, 0xA0, Local0)
-
- } else {
- if (LEqual (Arg1, 0)) {
- //If AC, & if only Gen1 supported, activate state DPM0 and DPM1
- //set SMUx0B_x8490[LclkDpmValid[6, 5]] = 1, set SMUx0B_x8490[LclkDpmValid[7]] = 0
- And (Local0, 0xFFFFFF60, Local0)
- Or (Local0, 0x60, Local0)
- } else {
- //If DC mode & Gen1 supported, activate only state DPM0
- //set SMUx0B_x8490[LclkDpmValid[7, 6]] = 0, set SMUx0B_x8490[LclkDpmValid[5]] = 1
- And (Local0, 0xFFFFFF20, Local0)
- Or (Local0, 0x20, Local0)
- }
- }
- procSmuRcuWrite (0x8490, Local0)
- }
- }
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * Power gate PCIe phy lanes (hotplug support)
- *
- * Arg0 - Start Lane ID
- * Arg1 - End Lane ID
- * Arg2 - Power ON(1) / OFF(0)
- */
- Method (procPcieLanePowerControl, 3, NotSerialized) {
- // stub function
- }
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * Read RCU register
- *
- * Arg0 - 1 - GEN1 2 - GEN2
- *
- */
- Method (procPcieAdjustPll, 1, NotSerialized) {
- //stub function
- }
-
- } //End of Scope(\_SB)
-} //End of DefinitionBlock
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h
deleted file mode 100644
index 533521b..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h
+++ /dev/null
@@ -1,660 +0,0 @@
-/**
- * @file
- *
- * ALIB SSDT table
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e $Revision:$ @e $Date:$
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _F14PCIEALIBSSDT_H_
-#define _F14PCIEALIBSSDT_H_
-
-UINT8 AlibSsdt[] = {
- 0x53, 0x53, 0x44, 0x54, 0xFA, 0x12, 0x00, 0x00,
- 0x02, 0xC9, 0x41, 0x4D, 0x44, 0x00, 0x00, 0x00,
- 0x41, 0x4C, 0x49, 0x42, 0x00, 0x00, 0x00, 0x00,
- 0x01, 0x00, 0x00, 0x00, 0x4D, 0x53, 0x46, 0x54,
- 0x00, 0x00, 0x00, 0x04, 0x10, 0x85, 0x2D, 0x01,
- 0x5C, 0x5F, 0x53, 0x42, 0x5F, 0x08, 0x41, 0x30,
- 0x30, 0x31, 0x0A, 0x06, 0x08, 0x41, 0x44, 0x30,
- 0x31, 0x0C, 0x00, 0x00, 0x00, 0xE0, 0x06, 0x41,
- 0x44, 0x30, 0x31, 0x41, 0x30, 0x39, 0x31, 0x08,
- 0x41, 0x44, 0x30, 0x37, 0x12, 0x45, 0x06, 0x07,
- 0x11, 0x0D, 0x0A, 0x0A, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x0D,
- 0x0A, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x11, 0x0D, 0x0A, 0x0A,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x11, 0x0D, 0x0A, 0x0A, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x11, 0x0D, 0x0A, 0x0A, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x0D,
- 0x0A, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x11, 0x0D, 0x0A, 0x0A,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x06, 0x41, 0x44, 0x30, 0x37, 0x41,
- 0x30, 0x39, 0x32, 0x14, 0x41, 0x05, 0x41, 0x4C,
- 0x49, 0x42, 0x02, 0xA0, 0x0B, 0x93, 0x68, 0x0A,
- 0x01, 0xA4, 0x41, 0x30, 0x31, 0x38, 0x69, 0xA0,
- 0x0B, 0x93, 0x68, 0x0A, 0x02, 0xA4, 0x41, 0x30,
- 0x32, 0x31, 0x69, 0xA0, 0x0B, 0x93, 0x68, 0x0A,
- 0x03, 0xA4, 0x41, 0x30, 0x33, 0x32, 0x69, 0xA0,
- 0x0B, 0x93, 0x68, 0x0A, 0x04, 0xA4, 0x41, 0x30,
- 0x36, 0x33, 0x69, 0xA0, 0x0A, 0x93, 0x68, 0x0A,
- 0x05, 0xA4, 0x41, 0x30, 0x39, 0x33, 0xA0, 0x0B,
- 0x93, 0x68, 0x0A, 0x06, 0xA4, 0x41, 0x30, 0x36,
- 0x36, 0x69, 0xA4, 0x0A, 0x00, 0x14, 0x09, 0x41,
- 0x30, 0x39, 0x33, 0x08, 0xA4, 0x0A, 0x00, 0x14,
- 0x31, 0x41, 0x30, 0x33, 0x31, 0x02, 0x72, 0x41,
- 0x30, 0x39, 0x31, 0x79, 0x68, 0x0A, 0x0C, 0x00,
- 0x60, 0x72, 0x69, 0x60, 0x60, 0x5B, 0x80, 0x41,
- 0x30, 0x39, 0x34, 0x00, 0x60, 0x0A, 0x04, 0x5B,
- 0x81, 0x0B, 0x41, 0x30, 0x39, 0x34, 0x03, 0x41,
- 0x30, 0x39, 0x35, 0x20, 0xA4, 0x41, 0x30, 0x39,
- 0x35, 0x14, 0x32, 0x41, 0x30, 0x35, 0x39, 0x03,
- 0x72, 0x41, 0x30, 0x39, 0x31, 0x79, 0x68, 0x0A,
- 0x0C, 0x00, 0x60, 0x72, 0x69, 0x60, 0x60, 0x5B,
- 0x80, 0x41, 0x30, 0x39, 0x34, 0x00, 0x60, 0x0A,
- 0x04, 0x5B, 0x81, 0x0B, 0x41, 0x30, 0x39, 0x34,
- 0x03, 0x41, 0x30, 0x39, 0x35, 0x20, 0x70, 0x6A,
- 0x41, 0x30, 0x39, 0x35, 0x14, 0x1C, 0x41, 0x30,
- 0x35, 0x35, 0x04, 0x70, 0x41, 0x30, 0x33, 0x31,
- 0x68, 0x69, 0x60, 0x7D, 0x7B, 0x60, 0x6A, 0x00,
- 0x6B, 0x60, 0x41, 0x30, 0x35, 0x39, 0x68, 0x69,
- 0x60, 0x5B, 0x01, 0x41, 0x30, 0x39, 0x36, 0x00,
- 0x14, 0x32, 0x41, 0x30, 0x35, 0x38, 0x02, 0x5B,
- 0x23, 0x41, 0x30, 0x39, 0x36, 0xFF, 0xFF, 0x70,
- 0x79, 0x72, 0x68, 0x0A, 0x02, 0x00, 0x0A, 0x03,
- 0x00, 0x60, 0x41, 0x30, 0x35, 0x39, 0x60, 0x0A,
- 0xE0, 0x69, 0x70, 0x41, 0x30, 0x33, 0x31, 0x60,
- 0x0A, 0xE4, 0x60, 0x5B, 0x27, 0x41, 0x30, 0x39,
- 0x36, 0xA4, 0x60, 0x14, 0x2F, 0x41, 0x30, 0x39,
- 0x37, 0x03, 0x5B, 0x23, 0x41, 0x30, 0x39, 0x36,
- 0xFF, 0xFF, 0x70, 0x79, 0x72, 0x68, 0x0A, 0x02,
- 0x00, 0x0A, 0x03, 0x00, 0x60, 0x41, 0x30, 0x35,
- 0x39, 0x60, 0x0A, 0xE0, 0x69, 0x41, 0x30, 0x35,
- 0x39, 0x60, 0x0A, 0xE4, 0x6A, 0x5B, 0x27, 0x41,
- 0x30, 0x39, 0x36, 0x14, 0x1C, 0x41, 0x30, 0x35,
- 0x34, 0x04, 0x70, 0x41, 0x30, 0x35, 0x38, 0x68,
- 0x69, 0x60, 0x7D, 0x7B, 0x60, 0x6A, 0x00, 0x6B,
- 0x60, 0x41, 0x30, 0x39, 0x37, 0x68, 0x69, 0x60,
- 0x5B, 0x01, 0x41, 0x30, 0x39, 0x38, 0x00, 0x14,
- 0x29, 0x41, 0x30, 0x36, 0x31, 0x03, 0x5B, 0x23,
- 0x41, 0x30, 0x39, 0x38, 0xFF, 0xFF, 0x41, 0x30,
- 0x35, 0x39, 0x68, 0x69, 0x6A, 0x70, 0x41, 0x30,
- 0x33, 0x31, 0x68, 0x72, 0x69, 0x0A, 0x04, 0x00,
- 0x60, 0x5B, 0x27, 0x41, 0x30, 0x39, 0x38, 0xA4,
- 0x60, 0x14, 0x26, 0x41, 0x30, 0x36, 0x32, 0x04,
- 0x5B, 0x23, 0x41, 0x30, 0x39, 0x38, 0xFF, 0xFF,
- 0x41, 0x30, 0x35, 0x39, 0x68, 0x69, 0x6A, 0x41,
- 0x30, 0x35, 0x39, 0x68, 0x72, 0x69, 0x0A, 0x04,
- 0x00, 0x6B, 0x5B, 0x27, 0x41, 0x30, 0x39, 0x38,
- 0x14, 0x1E, 0x41, 0x30, 0x35, 0x33, 0x05, 0x70,
- 0x41, 0x30, 0x36, 0x31, 0x68, 0x69, 0x6A, 0x60,
- 0x7D, 0x7B, 0x60, 0x6B, 0x00, 0x6C, 0x60, 0x41,
- 0x30, 0x36, 0x32, 0x68, 0x69, 0x6A, 0x60, 0x14,
- 0x0F, 0x41, 0x30, 0x37, 0x33, 0x01, 0xA4, 0x83,
- 0x88, 0x41, 0x30, 0x39, 0x32, 0x68, 0x00, 0x14,
- 0x42, 0x05, 0x41, 0x30, 0x35, 0x36, 0x02, 0x70,
- 0x0A, 0x34, 0x61, 0xA0, 0x11, 0x93, 0x41, 0x30,
- 0x33, 0x31, 0x68, 0x0A, 0x00, 0x0C, 0xFF, 0xFF,
- 0xFF, 0xFF, 0xA4, 0x0A, 0x00, 0x70, 0x0A, 0x01,
- 0x60, 0xA2, 0x2E, 0x93, 0x60, 0x0A, 0x01, 0x70,
- 0x7B, 0x41, 0x30, 0x33, 0x31, 0x68, 0x61, 0x0A,
- 0xFF, 0x00, 0x61, 0xA0, 0x1C, 0x92, 0x93, 0x61,
- 0x0A, 0x00, 0xA0, 0x11, 0x93, 0x7B, 0x41, 0x30,
- 0x33, 0x31, 0x68, 0x61, 0x0A, 0xFF, 0x00, 0x69,
- 0x70, 0x0A, 0x00, 0x60, 0xA1, 0x03, 0x75, 0x61,
- 0xA4, 0x61, 0x14, 0x47, 0x09, 0x41, 0x30, 0x35,
- 0x37, 0x02, 0x5B, 0x80, 0x50, 0x4D, 0x49, 0x4F,
- 0x01, 0x0B, 0xD6, 0x0C, 0x0A, 0x02, 0x5B, 0x81,
- 0x10, 0x50, 0x4D, 0x49, 0x4F, 0x01, 0x50, 0x4D,
- 0x52, 0x49, 0x08, 0x50, 0x4D, 0x52, 0x44, 0x08,
- 0x5B, 0x86, 0x12, 0x50, 0x4D, 0x52, 0x49, 0x50,
- 0x4D, 0x52, 0x44, 0x01, 0x00, 0x40, 0x70, 0x41,
- 0x42, 0x41, 0x52, 0x20, 0x5B, 0x80, 0x41, 0x43,
- 0x46, 0x47, 0x01, 0x41, 0x42, 0x41, 0x52, 0x0A,
- 0x08, 0x5B, 0x81, 0x10, 0x41, 0x43, 0x46, 0x47,
- 0x03, 0x41, 0x42, 0x49, 0x58, 0x20, 0x41, 0x42,
- 0x44, 0x41, 0x20, 0x70, 0x0A, 0x00, 0x60, 0xA0,
- 0x17, 0x93, 0x69, 0x0A, 0x00, 0x70, 0x0C, 0x68,
- 0x00, 0x00, 0x80, 0x41, 0x42, 0x49, 0x58, 0x70,
- 0x41, 0x42, 0x44, 0x41, 0x60, 0xA4, 0x60, 0xA1,
- 0x22, 0x70, 0x0C, 0x68, 0x00, 0x00, 0x80, 0x41,
- 0x42, 0x49, 0x58, 0x70, 0x41, 0x42, 0x44, 0x41,
- 0x60, 0x7D, 0x7B, 0x60, 0x0C, 0xFC, 0xFF, 0xFF,
- 0xFF, 0x00, 0x68, 0x60, 0x70, 0x60, 0x41, 0x42,
- 0x44, 0x41, 0x14, 0x48, 0x05, 0x41, 0x30, 0x38,
- 0x36, 0x01, 0x70, 0x41, 0x30, 0x36, 0x31, 0x0A,
- 0x00, 0x0A, 0x60, 0x0A, 0xCD, 0x60, 0x75, 0x68,
- 0x7D, 0x7B, 0x60, 0x0C, 0xFF, 0xFF, 0xFF, 0xFE,
- 0x00, 0x7B, 0x80, 0x7B, 0x60, 0x0C, 0x00, 0x00,
- 0x00, 0x01, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00,
- 0x01, 0x00, 0x60, 0x7D, 0x7B, 0x60, 0x0C, 0xFF,
- 0xFF, 0x00, 0xFD, 0x00, 0x79, 0x68, 0x0A, 0x10,
- 0x00, 0x60, 0x41, 0x30, 0x36, 0x32, 0x0A, 0x00,
- 0x0A, 0x60, 0x0A, 0xCD, 0x60, 0x70, 0x41, 0x30,
- 0x36, 0x31, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xCE,
- 0x60, 0xA4, 0x60, 0x14, 0x47, 0x0A, 0x41, 0x30,
- 0x38, 0x37, 0x03, 0x70, 0x41, 0x30, 0x36, 0x31,
- 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xCD, 0x60, 0x70,
- 0x7B, 0x69, 0x0B, 0xFF, 0xFF, 0x00, 0x61, 0x7D,
- 0x7B, 0x60, 0x0C, 0xFF, 0xFF, 0xFF, 0xFE, 0x00,
- 0x7B, 0x80, 0x7B, 0x60, 0x0C, 0x00, 0x00, 0x00,
- 0x01, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x01,
- 0x00, 0x60, 0x7D, 0x7B, 0x60, 0x0C, 0x00, 0x00,
- 0x00, 0xFD, 0x00, 0x79, 0x68, 0x0A, 0x10, 0x00,
- 0x60, 0x7D, 0x60, 0x0C, 0x00, 0x00, 0x00, 0x02,
- 0x60, 0x7D, 0x60, 0x61, 0x60, 0x41, 0x30, 0x36,
- 0x32, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xCD, 0x60,
- 0xA0, 0x4A, 0x04, 0x93, 0x6A, 0x0A, 0x01, 0x70,
- 0x7A, 0x69, 0x0A, 0x10, 0x00, 0x61, 0x7D, 0x7B,
- 0x60, 0x0C, 0xFF, 0xFF, 0xFF, 0xFE, 0x00, 0x7B,
- 0x80, 0x7B, 0x60, 0x0C, 0x00, 0x00, 0x00, 0x01,
- 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x01, 0x00,
- 0x60, 0x7D, 0x7B, 0x60, 0x0C, 0x00, 0x00, 0x00,
- 0xFF, 0x00, 0x79, 0x72, 0x68, 0x0A, 0x01, 0x00,
- 0x0A, 0x10, 0x00, 0x60, 0x7D, 0x60, 0x61, 0x60,
- 0x41, 0x30, 0x36, 0x32, 0x0A, 0x00, 0x0A, 0x60,
- 0x0A, 0xCD, 0x60, 0x14, 0x4F, 0x04, 0x41, 0x30,
- 0x38, 0x38, 0x02, 0x7D, 0x79, 0x68, 0x0A, 0x03,
- 0x00, 0x0A, 0x01, 0x60, 0x41, 0x30, 0x38, 0x37,
- 0x0A, 0x03, 0x60, 0x0A, 0x01, 0xA0, 0x15, 0x90,
- 0x69, 0x0A, 0x01, 0xA2, 0x0F, 0x92, 0x93, 0x7B,
- 0x41, 0x30, 0x38, 0x36, 0x0A, 0x03, 0x0A, 0x02,
- 0x00, 0x0A, 0x02, 0xA0, 0x15, 0x90, 0x69, 0x0A,
- 0x02, 0xA2, 0x0F, 0x92, 0x93, 0x7B, 0x41, 0x30,
- 0x38, 0x36, 0x0A, 0x03, 0x0A, 0x04, 0x00, 0x0A,
- 0x04, 0x41, 0x30, 0x38, 0x37, 0x0A, 0x03, 0x0A,
- 0x00, 0x0A, 0x00, 0x14, 0x18, 0x41, 0x30, 0x30,
- 0x34, 0x02, 0x41, 0x30, 0x38, 0x37, 0x0A, 0x0B,
- 0x68, 0x0A, 0x00, 0x41, 0x30, 0x38, 0x37, 0x0A,
- 0x05, 0x69, 0x0A, 0x01, 0x14, 0x19, 0x41, 0x30,
- 0x30, 0x33, 0x01, 0x41, 0x30, 0x38, 0x37, 0x0A,
- 0x0B, 0x68, 0x0A, 0x00, 0x70, 0x41, 0x30, 0x38,
- 0x36, 0x0A, 0x05, 0x60, 0xA4, 0x60, 0x14, 0x49,
- 0x07, 0x41, 0x30, 0x38, 0x39, 0x01, 0x70, 0x7D,
- 0x7B, 0x68, 0x0A, 0xFF, 0x00, 0x0C, 0x00, 0x50,
- 0x86, 0x01, 0x00, 0x60, 0x70, 0x7D, 0x7B, 0x68,
- 0x0C, 0x00, 0xFF, 0xFF, 0xFF, 0x00, 0x0A, 0x04,
- 0x00, 0x61, 0x70, 0x7D, 0x79, 0x0A, 0x03, 0x0A,
- 0x1E, 0x00, 0x79, 0x0A, 0x01, 0x0A, 0x12, 0x00,
- 0x00, 0x62, 0x41, 0x30, 0x30, 0x34, 0x0B, 0x00,
- 0x86, 0x60, 0x41, 0x30, 0x30, 0x34, 0x0B, 0x04,
- 0x86, 0x61, 0x41, 0x30, 0x30, 0x34, 0x0B, 0x08,
- 0x86, 0x62, 0xA0, 0x12, 0x93, 0x7A, 0x68, 0x0A,
- 0x10, 0x00, 0x0B, 0x00, 0xFE, 0x41, 0x30, 0x38,
- 0x38, 0x0A, 0x0D, 0x0A, 0x03, 0xA0, 0x12, 0x93,
- 0x7A, 0x68, 0x0A, 0x10, 0x00, 0x0B, 0x30, 0xFE,
- 0x41, 0x30, 0x38, 0x38, 0x0A, 0x0B, 0x0A, 0x03,
- 0xA4, 0x41, 0x30, 0x30, 0x33, 0x0B, 0x50, 0x86,
- 0x14, 0x44, 0x06, 0x41, 0x30, 0x39, 0x30, 0x02,
- 0x70, 0x7D, 0x7B, 0x68, 0x0A, 0xFF, 0x00, 0x0C,
- 0x00, 0x50, 0x86, 0x01, 0x00, 0x60, 0x70, 0x7D,
- 0x7B, 0x68, 0x0C, 0x00, 0xFF, 0xFF, 0xFF, 0x00,
- 0x0A, 0x04, 0x00, 0x61, 0x70, 0x7D, 0x79, 0x0A,
- 0x03, 0x0A, 0x1E, 0x00, 0x79, 0x0A, 0x01, 0x0A,
- 0x12, 0x00, 0x00, 0x62, 0x7D, 0x62, 0x79, 0x0A,
- 0x01, 0x0A, 0x10, 0x00, 0x62, 0x41, 0x30, 0x30,
- 0x34, 0x0B, 0x00, 0x86, 0x60, 0x41, 0x30, 0x30,
- 0x34, 0x0B, 0x04, 0x86, 0x61, 0x41, 0x30, 0x30,
- 0x34, 0x0B, 0x08, 0x86, 0x62, 0x41, 0x30, 0x30,
- 0x34, 0x0B, 0x50, 0x86, 0x69, 0x41, 0x30, 0x38,
- 0x38, 0x0A, 0x0B, 0x0A, 0x03, 0x08, 0x41, 0x44,
- 0x30, 0x32, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x30,
- 0x32, 0x41, 0x30, 0x30, 0x37, 0x08, 0x41, 0x44,
- 0x30, 0x33, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x30,
- 0x33, 0x41, 0x30, 0x30, 0x38, 0x08, 0x41, 0x44,
- 0x30, 0x34, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x30,
- 0x34, 0x41, 0x30, 0x30, 0x39, 0x08, 0x41, 0x44,
- 0x30, 0x35, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x30,
- 0x35, 0x41, 0x30, 0x31, 0x30, 0x08, 0x41, 0x44,
- 0x30, 0x36, 0x12, 0x10, 0x07, 0x0A, 0x00, 0x0A,
- 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A,
- 0x00, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x30, 0x36,
- 0x41, 0x30, 0x31, 0x31, 0x08, 0x41, 0x30, 0x31,
- 0x32, 0x0A, 0x00, 0x08, 0x41, 0x30, 0x31, 0x33,
- 0x0A, 0x00, 0x08, 0x41, 0x30, 0x31, 0x34, 0x12,
- 0x10, 0x07, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00,
- 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00,
- 0x08, 0x41, 0x30, 0x31, 0x35, 0x12, 0x10, 0x07,
- 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00,
- 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x08, 0x41,
- 0x30, 0x31, 0x36, 0x12, 0x10, 0x07, 0x0A, 0x00,
- 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00,
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- 0x63, 0xA1, 0x0B, 0x41, 0x30, 0x35, 0x37, 0x41,
- 0x30, 0x34, 0x35, 0x0A, 0x01, 0xA1, 0x01, 0xA0,
- 0x15, 0x93, 0x68, 0x0A, 0x06, 0x41, 0x30, 0x35,
- 0x33, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0x80, 0x80,
- 0x0A, 0x40, 0x00, 0x0A, 0x00, 0x5B, 0x01, 0x41,
- 0x30, 0x36, 0x30, 0x00, 0x14, 0x4F, 0x07, 0x41,
- 0x30, 0x33, 0x39, 0x02, 0x5B, 0x23, 0x41, 0x30,
- 0x36, 0x30, 0xFF, 0xFF, 0x70, 0x41, 0x30, 0x36,
- 0x31, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xEA, 0x61,
- 0x7D, 0x61, 0x0A, 0x02, 0x61, 0x41, 0x30, 0x36,
- 0x32, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xEA, 0x61,
- 0x7B, 0x61, 0x80, 0x79, 0x0A, 0x03, 0x0A, 0x03,
- 0x00, 0x00, 0x61, 0x7D, 0x61, 0x79, 0x68, 0x0A,
- 0x03, 0x00, 0x61, 0x7B, 0x80, 0x61, 0x00, 0x0A,
- 0x04, 0x62, 0x7D, 0x7B, 0x61, 0x80, 0x0A, 0x04,
- 0x00, 0x00, 0x62, 0x61, 0x41, 0x30, 0x36, 0x32,
- 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xEA, 0x61, 0xA0,
- 0x1E, 0x92, 0x93, 0x69, 0x0A, 0x00, 0xA2, 0x17,
- 0x92, 0x93, 0x79, 0x61, 0x0A, 0x02, 0x00, 0x62,
- 0x7B, 0x41, 0x30, 0x36, 0x31, 0x0A, 0x00, 0x0A,
- 0x60, 0x0A, 0xEB, 0x0A, 0x01, 0x61, 0x5B, 0x27,
- 0x41, 0x30, 0x36, 0x30, 0x14, 0x21, 0x41, 0x30,
- 0x33, 0x34, 0x02, 0x70, 0x87, 0x68, 0x61, 0x70,
- 0x0A, 0x00, 0x60, 0xA2, 0x12, 0x95, 0x60, 0x61,
- 0x70, 0x83, 0x88, 0x83, 0x68, 0x60, 0x00, 0x88,
- 0x83, 0x69, 0x60, 0x00, 0x75, 0x60, 0x14, 0x37,
- 0x41, 0x30, 0x36, 0x33, 0x09, 0x70, 0x11, 0x04,
- 0x0B, 0x00, 0x01, 0x67, 0x8B, 0x67, 0x0A, 0x00,
- 0x41, 0x30, 0x32, 0x34, 0x8B, 0x67, 0x0A, 0x02,
- 0x41, 0x30, 0x36, 0x34, 0x8C, 0x68, 0x0A, 0x02,
- 0x41, 0x30, 0x36, 0x35, 0x70, 0x0A, 0x03, 0x41,
- 0x30, 0x32, 0x34, 0x70, 0x41, 0x30, 0x36, 0x35,
- 0x41, 0x30, 0x36, 0x34, 0xA4, 0x67, 0x14, 0x4A,
- 0x07, 0x41, 0x30, 0x36, 0x36, 0x09, 0x70, 0x11,
- 0x04, 0x0B, 0x00, 0x01, 0x67, 0x8B, 0x67, 0x0A,
- 0x00, 0x41, 0x30, 0x32, 0x34, 0x8C, 0x67, 0x0A,
- 0x02, 0x41, 0x30, 0x32, 0x35, 0x8C, 0x67, 0x0A,
- 0x03, 0x41, 0x30, 0x36, 0x37, 0x8B, 0x68, 0x0A,
- 0x02, 0x41, 0x30, 0x36, 0x38, 0x8C, 0x68, 0x0A,
- 0x04, 0x41, 0x30, 0x36, 0x39, 0x74, 0x7A, 0x41,
- 0x30, 0x36, 0x38, 0x0A, 0x03, 0x00, 0x0A, 0x02,
- 0x61, 0xA0, 0x12, 0x93, 0x41, 0x30, 0x36, 0x39,
- 0x0A, 0x01, 0x70, 0x41, 0x30, 0x37, 0x30, 0x61,
- 0x41, 0x30, 0x36, 0x39, 0xA1, 0x0B, 0x70, 0x41,
- 0x30, 0x37, 0x31, 0x61, 0x41, 0x30, 0x36, 0x39,
- 0x70, 0x0A, 0x04, 0x41, 0x30, 0x32, 0x34, 0x70,
- 0x0A, 0x00, 0x41, 0x30, 0x32, 0x35, 0x70, 0x41,
- 0x30, 0x36, 0x39, 0x41, 0x30, 0x36, 0x37, 0xA4,
- 0x67, 0x14, 0x49, 0x11, 0x41, 0x30, 0x37, 0x30,
- 0x01, 0x08, 0x41, 0x30, 0x37, 0x32, 0x0A, 0x00,
- 0x70, 0x41, 0x30, 0x37, 0x33, 0x68, 0x67, 0x8C,
- 0x67, 0x0A, 0x07, 0x41, 0x30, 0x37, 0x34, 0xA0,
- 0x0C, 0x92, 0x93, 0x41, 0x30, 0x37, 0x34, 0x0A,
- 0x01, 0xA4, 0x0A, 0x01, 0x8C, 0x67, 0x0A, 0x00,
- 0x41, 0x30, 0x37, 0x35, 0x8C, 0x67, 0x0A, 0x01,
- 0x41, 0x30, 0x37, 0x36, 0x41, 0x30, 0x30, 0x35,
- 0x41, 0x30, 0x37, 0x35, 0x41, 0x30, 0x37, 0x36,
- 0x0A, 0x00, 0x8C, 0x67, 0x0A, 0x02, 0x41, 0x30,
- 0x37, 0x37, 0x8C, 0x67, 0x0A, 0x03, 0x41, 0x30,
- 0x37, 0x38, 0x41, 0x30, 0x37, 0x39, 0x68, 0x41,
- 0x30, 0x37, 0x35, 0x41, 0x30, 0x37, 0x36, 0x0A,
- 0x00, 0x41, 0x30, 0x38, 0x30, 0x68, 0x0A, 0x00,
- 0x70, 0x41, 0x30, 0x38, 0x31, 0x68, 0x61, 0xA0,
- 0x4B, 0x09, 0x93, 0x61, 0x0A, 0x01, 0x70, 0x41,
- 0x30, 0x38, 0x32, 0x68, 0x41, 0x30, 0x37, 0x32,
- 0x74, 0x41, 0x30, 0x38, 0x33, 0x68, 0x0A, 0x01,
- 0x41, 0x30, 0x38, 0x33, 0x68, 0x0A, 0x00, 0x62,
- 0xA0, 0x47, 0x07, 0x92, 0x93, 0x62, 0x0A, 0x00,
- 0xA0, 0x16, 0x92, 0x93, 0x41, 0x30, 0x37, 0x32,
- 0x0A, 0x00, 0x72, 0x41, 0x30, 0x37, 0x37, 0x62,
- 0x63, 0x70, 0x41, 0x30, 0x37, 0x38, 0x64, 0xA1,
- 0x0E, 0x74, 0x41, 0x30, 0x37, 0x38, 0x62, 0x64,
- 0x70, 0x41, 0x30, 0x37, 0x37, 0x63, 0x41, 0x30,
- 0x37, 0x39, 0x68, 0x63, 0x64, 0x0A, 0x01, 0xA0,
- 0x16, 0x94, 0x41, 0x30, 0x37, 0x35, 0x41, 0x30,
- 0x37, 0x36, 0x70, 0x41, 0x30, 0x37, 0x36, 0x63,
- 0x70, 0x41, 0x30, 0x37, 0x35, 0x64, 0xA1, 0x0D,
- 0x70, 0x41, 0x30, 0x37, 0x36, 0x64, 0x70, 0x41,
- 0x30, 0x37, 0x35, 0x63, 0xA0, 0x0D, 0x92, 0x93,
- 0x41, 0x30, 0x37, 0x32, 0x0A, 0x00, 0x72, 0x63,
- 0x62, 0x63, 0xA1, 0x05, 0x74, 0x64, 0x62, 0x64,
- 0x41, 0x30, 0x30, 0x35, 0x63, 0x64, 0x0A, 0x01,
- 0xA4, 0x0A, 0x01, 0x41, 0x30, 0x37, 0x31, 0x68,
- 0xA4, 0x0A, 0x00, 0x14, 0x4A, 0x06, 0x41, 0x30,
- 0x37, 0x31, 0x01, 0x70, 0x41, 0x30, 0x37, 0x33,
- 0x68, 0x67, 0x8C, 0x67, 0x0A, 0x07, 0x41, 0x30,
- 0x37, 0x34, 0xA0, 0x0C, 0x92, 0x93, 0x41, 0x30,
- 0x37, 0x34, 0x0A, 0x01, 0xA4, 0x0A, 0x00, 0x41,
- 0x30, 0x38, 0x30, 0x68, 0x0A, 0x01, 0x8C, 0x67,
- 0x0A, 0x02, 0x41, 0x30, 0x37, 0x37, 0x8C, 0x67,
- 0x0A, 0x03, 0x41, 0x30, 0x37, 0x38, 0x41, 0x30,
- 0x37, 0x39, 0x68, 0x41, 0x30, 0x37, 0x37, 0x41,
- 0x30, 0x37, 0x38, 0x0A, 0x01, 0x8C, 0x67, 0x0A,
- 0x00, 0x41, 0x30, 0x37, 0x35, 0x8C, 0x67, 0x0A,
- 0x01, 0x41, 0x30, 0x37, 0x36, 0x41, 0x30, 0x30,
- 0x35, 0x41, 0x30, 0x37, 0x35, 0x41, 0x30, 0x37,
- 0x36, 0x0A, 0x01, 0xA4, 0x0A, 0x00, 0x14, 0x41,
- 0x04, 0x41, 0x30, 0x38, 0x32, 0x01, 0x70, 0x41,
- 0x30, 0x37, 0x33, 0x68, 0x67, 0x8C, 0x67, 0x0A,
- 0x00, 0x41, 0x30, 0x37, 0x35, 0x8C, 0x67, 0x0A,
- 0x01, 0x41, 0x30, 0x37, 0x36, 0x70, 0x0A, 0x00,
- 0x60, 0xA0, 0x0E, 0x94, 0x41, 0x30, 0x37, 0x35,
- 0x41, 0x30, 0x37, 0x36, 0x70, 0x0A, 0x01, 0x60,
- 0x7B, 0x41, 0x30, 0x35, 0x38, 0x68, 0x0A, 0x50,
- 0x0A, 0x01, 0x61, 0xA4, 0x7F, 0x60, 0x61, 0x00,
- 0x14, 0x43, 0x04, 0x41, 0x30, 0x38, 0x30, 0x02,
- 0x70, 0x41, 0x30, 0x37, 0x33, 0x68, 0x67, 0x8C,
- 0x67, 0x0A, 0x04, 0x41, 0x30, 0x38, 0x34, 0x8B,
- 0x67, 0x0A, 0x05, 0x41, 0x30, 0x38, 0x35, 0x41,
- 0x30, 0x35, 0x33, 0x0A, 0x00, 0x0A, 0xE0, 0x7D,
- 0x79, 0x41, 0x30, 0x38, 0x35, 0x0A, 0x10, 0x00,
- 0x72, 0x0B, 0x00, 0x08, 0x77, 0x0B, 0x00, 0x01,
- 0x41, 0x30, 0x38, 0x34, 0x00, 0x00, 0x00, 0x80,
- 0x0A, 0x01, 0x00, 0x69, 0x14, 0x38, 0x41, 0x30,
- 0x38, 0x31, 0x01, 0x70, 0x0A, 0x00, 0x60, 0x70,
- 0x0A, 0x00, 0x67, 0xA2, 0x27, 0x95, 0x60, 0x0B,
- 0x40, 0x01, 0x7B, 0x41, 0x30, 0x35, 0x38, 0x68,
- 0x0A, 0xA5, 0x0A, 0x3F, 0x61, 0xA0, 0x0F, 0x93,
- 0x61, 0x0A, 0x10, 0x70, 0x0A, 0x01, 0x67, 0x70,
- 0x0B, 0x40, 0x01, 0x60, 0xA5, 0x5B, 0x21, 0x0A,
- 0xFA, 0x75, 0x60, 0xA4, 0x67, 0x14, 0x4B, 0x06,
- 0x41, 0x30, 0x38, 0x33, 0x02, 0xA0, 0x25, 0x93,
- 0x68, 0x0A, 0x00, 0x7B, 0x7A, 0x41, 0x30, 0x35,
- 0x38, 0x68, 0x0A, 0xA2, 0x0A, 0x04, 0x00, 0x0A,
- 0x07, 0x60, 0x70, 0x83, 0x88, 0x11, 0x0A, 0x0A,
- 0x07, 0x00, 0x01, 0x02, 0x04, 0x08, 0x0C, 0x10,
- 0x60, 0x00, 0x61, 0xA1, 0x3B, 0x70, 0x41, 0x30,
- 0x37, 0x33, 0x68, 0x67, 0x8C, 0x67, 0x0A, 0x00,
- 0x41, 0x30, 0x37, 0x35, 0x8C, 0x67, 0x0A, 0x01,
- 0x41, 0x30, 0x37, 0x36, 0xA0, 0x14, 0x94, 0x41,
- 0x30, 0x37, 0x35, 0x41, 0x30, 0x37, 0x36, 0x74,
- 0x41, 0x30, 0x37, 0x35, 0x41, 0x30, 0x37, 0x36,
- 0x61, 0xA1, 0x0B, 0x74, 0x41, 0x30, 0x37, 0x36,
- 0x41, 0x30, 0x37, 0x35, 0x61, 0x75, 0x61, 0xA4,
- 0x61, 0x14, 0x4E, 0x0A, 0x41, 0x30, 0x37, 0x39,
- 0x04, 0x08, 0x41, 0x30, 0x37, 0x37, 0x0A, 0x00,
- 0x08, 0x41, 0x30, 0x37, 0x38, 0x0A, 0x00, 0x70,
- 0x41, 0x30, 0x37, 0x33, 0x68, 0x67, 0x70, 0x69,
- 0x41, 0x30, 0x37, 0x37, 0x70, 0x6A, 0x41, 0x30,
- 0x37, 0x38, 0x8B, 0x67, 0x0A, 0x05, 0x41, 0x30,
- 0x38, 0x35, 0xA0, 0x1A, 0x94, 0x41, 0x30, 0x37,
- 0x37, 0x41, 0x30, 0x37, 0x38, 0x74, 0x41, 0x30,
- 0x37, 0x37, 0x41, 0x30, 0x37, 0x38, 0x61, 0x70,
- 0x41, 0x30, 0x37, 0x38, 0x62, 0xA1, 0x11, 0x74,
- 0x41, 0x30, 0x37, 0x38, 0x41, 0x30, 0x37, 0x37,
- 0x61, 0x70, 0x41, 0x30, 0x37, 0x37, 0x62, 0x79,
- 0x74, 0x79, 0x0A, 0x01, 0x72, 0x61, 0x0A, 0x01,
- 0x00, 0x00, 0x0A, 0x01, 0x00, 0x62, 0x61, 0xA0,
- 0x20, 0x93, 0x6B, 0x0A, 0x00, 0x41, 0x30, 0x35,
- 0x33, 0x0A, 0x00, 0x0A, 0xE0, 0x7D, 0x79, 0x41,
- 0x30, 0x38, 0x35, 0x0A, 0x10, 0x00, 0x0B, 0x23,
- 0x80, 0x00, 0x0C, 0xFF, 0xFF, 0xFF, 0xFF, 0x61,
- 0xA1, 0x1B, 0x41, 0x30, 0x35, 0x33, 0x0A, 0x00,
- 0x0A, 0xE0, 0x7D, 0x79, 0x41, 0x30, 0x38, 0x35,
- 0x0A, 0x10, 0x00, 0x0B, 0x23, 0x80, 0x00, 0x80,
- 0x61, 0x00, 0x0A, 0x00, 0x5B, 0x21, 0x0A, 0x0A,
- 0x14, 0x4B, 0x05, 0x41, 0x30, 0x30, 0x32, 0x02,
- 0x70, 0x41, 0x30, 0x30, 0x33, 0x0B, 0x90, 0x84,
- 0x60, 0xA0, 0x4A, 0x04, 0x92, 0x93, 0x7B, 0x60,
- 0x0A, 0xF0, 0x00, 0x0A, 0x00, 0xA0, 0x12, 0x93,
- 0x68, 0x0A, 0x02, 0x7B, 0x60, 0x0C, 0xA0, 0xFF,
- 0xFF, 0xFF, 0x60, 0x7D, 0x60, 0x0A, 0xA0, 0x60,
- 0xA1, 0x23, 0xA0, 0x12, 0x93, 0x69, 0x0A, 0x00,
- 0x7B, 0x60, 0x0C, 0x60, 0xFF, 0xFF, 0xFF, 0x60,
- 0x7D, 0x60, 0x0A, 0x60, 0x60, 0xA1, 0x0E, 0x7B,
- 0x60, 0x0C, 0x20, 0xFF, 0xFF, 0xFF, 0x60, 0x7D,
- 0x60, 0x0A, 0x20, 0x60, 0x41, 0x30, 0x30, 0x34,
- 0x0B, 0x90, 0x84, 0x60, 0x14, 0x06, 0x41, 0x30,
- 0x30, 0x35, 0x03, 0x14, 0x06, 0x41, 0x30, 0x30,
- 0x36, 0x01
-};
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PcieComplexConfig.c b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PcieComplexConfig.c
deleted file mode 100644
index c64fc4b..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PcieComplexConfig.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Family specific PCIe configuration data services
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "amdlib.h"
-#include "Gnb.h"
-#include "GnbPcie.h"
-#include GNB_MODULE_DEFINITIONS (GnbPcieConfig)
-#include "OntarioDefinitions.h"
-#include "OntarioComplexData.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_PCIE_FAMILY_0X14_F14PCIECOMPLEXCONFIG_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get total number of silicons/wrappers/engines for this complex
- *
- *
- * @param[in] SocketId Socket ID.
- * @param[out] Length Length of configuration info block
- * @retval AGESA_SUCCESS Configuration data length is correct
- */
-AGESA_STATUS
-PcieFmGetComplexDataLength (
- IN UINT32 SocketId,
- OUT UINTN *Length
- )
-{
- *Length = sizeof (ComplexData);
- return AGESA_SUCCESS;
-}
-
-
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Build configuration
- *
- *
- *
- *
- * @param[out] Buffer Pointer to buffer to build internal complex data structure
- * @param[out] StdHeader Standard configuration header.
- * @retval AGESA_SUCCESS Configuration data build successfully
- */
-AGESA_STATUS
-PcieFmBuildComplexConfiguration (
- OUT VOID *Buffer,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
-
- LibAmdMemCopy (Buffer, &ComplexData, sizeof (ComplexData), StdHeader);
- PcieRebaseConfigurationData ((PCIe_SILICON_CONFIG *) Buffer, 0, (UINTN)Buffer);
-
- return AGESA_SUCCESS;
-}
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PcieComplexServices.c b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PcieComplexServices.c
deleted file mode 100644
index 2e789aa..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PcieComplexServices.c
+++ /dev/null
@@ -1,243 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Family specific PCIe complex initialization services
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "Gnb.h"
-#include "GnbPcie.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1)
-#include GNB_MODULE_DEFINITIONS (GnbPcieConfig)
-#include "OntarioDefinitions.h"
-#include "GnbRegistersON.h"
-#include "NbSmuLib.h"
-#include "Filecode.h"
-#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1)
-#define FILECODE PROC_GNB_PCIE_FAMILY_0X14_F14PCIECOMPLEXSERVICES_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Control port visability
- *
- *
- * @param[in] Control Hide/Unhide
- * @param[in] Silicon Pointer to silicon configuration descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-
-VOID
-PcieFmPortVisabilityControl (
- IN PCIE_PORT_VISIBILITY Control,
- IN PCIe_SILICON_CONFIG *Silicon,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- switch (Control) {
- case UnhidePorts:
- PcieSiliconUnHidePorts (Silicon, Pcie);
- break;
- case HidePorts:
- PcieSiliconHidePorts (Silicon, Pcie);
- break;
- default:
- ASSERT (FALSE);
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Request boot up voltage
- *
- *
- *
- * @param[in] LinkCap Global GEN capability
- * @param[in] Pcie Pointer to PCIe configuration data area
- */
-VOID
-PcieFmSetBootUpVoltage (
- IN PCIE_LINK_SPEED_CAP LinkCap,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- FCRxFE00_70A2_STRUCT FCRxFE00_70A2;
- D18F3x15C_STRUCT D18F3x15C;
- UINT8 TargetVidIndex;
- UINT32 Temp;
- IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmSetBootUpVoltage Enter\n");
- ASSERT (LinkCap <= PcieGen2);
- GnbLibPciRead (
- MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS),
- AccessWidth32,
- &D18F3x15C.Value,
- GnbLibGetHeader (Pcie)
- );
- Temp = D18F3x15C.Value;
- if (LinkCap > PcieGen1) {
- FCRxFE00_70A2.Value = NbSmuReadEfuse (FCRxFE00_70A2_ADDRESS, GnbLibGetHeader (Pcie));
- TargetVidIndex = (UINT8) FCRxFE00_70A2.Field.PcieGen2Vid;
- } else {
- TargetVidIndex = PcieSiliconGetGen1VoltageIndex (GnbLibGetHeader (Pcie));
- }
- IDS_HDT_CONSOLE (PCIE_MISC, " Set Voltage for Gen %d, Vid Index %d\n", LinkCap, TargetVidIndex);
- if (TargetVidIndex == 3) {
- D18F3x15C.Field.SclkVidLevel2 = D18F3x15C.Field.SclkVidLevel3;
- GnbLibPciWrite (
- MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS),
- AccessWidth32,
- &D18F3x15C.Value,
- GnbLibGetHeader (Pcie)
- );
- PcieSiliconRequestVoltage (2, GnbLibGetHeader (Pcie));
- }
- GnbLibPciWrite (
- MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS),
- AccessWidth32,
- &Temp,
- GnbLibGetHeader (Pcie)
- );
- PcieSiliconRequestVoltage (TargetVidIndex, GnbLibGetHeader (Pcie));
- IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmSetBootUpVoltage Exit\n");
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Map engine to specific PCI device address
- *
- *
- *
- * @param[in] Engine Pointer to engine configuration
- * @param[in] Pcie Pointer to PCIe configuration
- * @retval AGESA_ERROR Fail to map PCI device address
- * @retval AGESA_SUCCESS Successfully allocate PCI address
- */
-
-AGESA_STATUS
-PcieFmMapPortPciAddress (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- PCIe_WRAPPER_CONFIG *Wrapper;
- UINT64 ConfigurationSignature;
-
- Wrapper = PcieEngineGetParentWrapper (Engine);
-
- if (Wrapper->WrapId == GPP_WRAP_ID) {
- ConfigurationSignature = PcieConfigGetConfigurationSignature (Wrapper, Engine->Type.Port.CoreId);
- if ((ConfigurationSignature == GPP_CORE_x4x2x1x1_ST) || (ConfigurationSignature == GPP_CORE_x4x2x2_ST)) {
- //Enable device remapping
- GnbLibPciIndirectRMW (
- MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS),
- 0x20 | IOC_WRITE_ENABLE,
- AccessS3SaveWidth32,
- ~(UINT32) (1 << 1),
- 0x0,
- GnbLibGetHeader (Pcie)
- );
- }
- }
- if (Engine->Type.Port.PortData.DeviceNumber == 0 && Engine->Type.Port.PortData.FunctionNumber == 0) {
- Engine->Type.Port.PortData.DeviceNumber = Engine->Type.Port.NativeDevNumber;
- Engine->Type.Port.PortData.FunctionNumber = Engine->Type.Port.NativeFunNumber;
- return AGESA_SUCCESS;
- }
- if (Engine->Type.Port.PortData.DeviceNumber == Engine->Type.Port.NativeDevNumber &&
- Engine->Type.Port.PortData.FunctionNumber == Engine->Type.Port.NativeFunNumber) {
- return AGESA_SUCCESS;
- }
- return AGESA_ERROR;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Map engine to specific PCI device address
- *
- *
- *
- * @param[in] Engine Pointer to engine configuration
- * @param[in] Pcie Pointer to PCIe configuration
- */
-
-
-VOID
-PcieFmEnableSlotPowerLimit (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- ASSERT (Engine->EngineData.EngineType == PciePortEngine);
- if (PcieLibIsEngineAllocated (Engine) && Engine->Type.Port.PortData.PortPresent != PortDisabled && !Engine->Type.Port.IsSB) {
- IDS_HDT_CONSOLE (PCIE_MISC, " Enable Slot Power Limit for Port % d\n", Engine->Type.Port.Address.Address.Device);
- GnbLibPciIndirectRMW (
- MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS),
- (D0F0x64_x55_ADDRESS + (Engine->Type.Port.Address.Address.Device - 4) * 2) | IOC_WRITE_ENABLE,
- AccessS3SaveWidth32,
- 0xffffffff,
- 1 << D0F0x64_x55_SetPowEn_OFFSET,
- GnbLibGetHeader (Pcie)
- );
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PciePhyServices.c b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PciePhyServices.c
deleted file mode 100644
index cb35a59..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PciePhyServices.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Family specific PCIe PHY initialization services
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "Gnb.h"
-#include "GnbPcie.h"
-#include "GnbRegistersON.h"
-#include "OntarioDefinitions.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_PCIE_FAMILY_0X14_F14PCIEPHYSERVICES_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * PHY Pll Personality Init
- *
- *
- *
- * @param[in] Wrapper Pointer to wrapper config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-AGESA_STATUS
-PcieFmPhyLetPllPersonalityInit (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- // Stub function
- return AGESA_SUCCESS;
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Port channel characteristic
- *
- *
- *
- * @param[in] Engine Pointer to engine configuration
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-VOID
-PcieFmPhyChannelCharacteristic (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Point "virtual" PLL clock picker away from PCIe
- *
- *
- *
- * @param[in] Wrapper Pointer to internal configuration data area
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-VOID
-PcieFmAvertClockPickers (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- // Stub function
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * PHY lane ganging
- *
- *
- *
- * @param[out] Wrapper Pointer to internal configuration data area
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-VOID
-PcieFmPhyApplyGanging (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- // Stub function
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Program receiver detection power mode
- *
- *
- *
- * @param[in] Wrapper Pointer to wrapper config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-
-VOID
-PcieFmPifSetRxDetectPowerMode (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- // Stub function
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PciePifServices.c b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PciePifServices.c
deleted file mode 100644
index 31ef7c8..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PciePifServices.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Family specific PCIe PHY initialization services
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 40760 $ @e \$Date: 2010-10-27 08:55:23 +0800 (Wed, 27 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "Gnb.h"
-#include "GnbPcie.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1)
-#include "GnbRegistersON.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_PCIE_FAMILY_0X14_F14PCIEPIFSERVICES_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Set PLL mode for L1
- *
- *
- * @param[in] LaneBitmap Power down PLL for these lanes
- * @param[in] Wrapper Pointer to Wrapper config descriptor
- * @param[in] Pcie Pointer to PICe configuration data area
- */
-VOID
-PcieFmPifSetPllModeForL1 (
- IN UINT32 LaneBitmap,
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT32 ActiveLaneBitmap;
- ActiveLaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_ACTIVE | LANE_TYPE_PCIE_HOTPLUG, 0, Wrapper, Pcie);
- // This limits PLL setting to be identical for all PLL on wrapper.
- if ((ActiveLaneBitmap & LaneBitmap) == ActiveLaneBitmap) {
- LaneBitmap &= PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_ALL, 0, Wrapper, Pcie);
- PciePifSetPllModeForL1 (LaneBitmap, Wrapper, Pcie);
- }
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * PLL power up latency
- *
- *
- * @param[in] Wrapper Pointer to Wrapper config descriptor
- * @param[in] Pcie Pointer to PICe configuration data area
- * @retval Pll wake up latency in us
- */
-UINT8
-PcieFmPifGetPllPowerUpLatency (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- return 30;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c
deleted file mode 100644
index 88290b1..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c
+++ /dev/null
@@ -1,631 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Family specific PCIe wrapper configuration services
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "Gnb.h"
-#include "GnbPcie.h"
-#include "PcieFamilyServices.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1)
-#include "PcieMiscLib.h"
-#include "OntarioDefinitions.h"
-#include "GnbRegistersON.h"
-#include "NbSmuLib.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_PCIE_FAMILY_0X14_F14PCIEWRAPPERSERVICES_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-extern BUILD_OPT_CFG UserOptions;
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-AGESA_STATUS
-STATIC
-PcieOnConfigureGppEnginesLaneAllocation (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN UINT8 ConfigurationId
- );
-
-AGESA_STATUS
-STATIC
-PcieOnConfigureDdiEnginesLaneAllocation (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN UINT8 ConfigurationId
- );
-
-VOID
-PcieFmExecuteNativeGen1Reconfig (
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-/*----------------------------------------------------------------------------------------
- * T A B L E S
- *----------------------------------------------------------------------------------------
- */
-PCIE_HOST_REGISTER_ENTRY PcieInitTable [] = {
- {
- WRAP_SPACE (0, D0F0xE4_WRAP_8016_ADDRESS),
- D0F0xE4_WRAP_8016_CalibAckLatency_MASK,
- 0
- },
- {
- PHY_SPACE (0, 0, D0F0xE4_PHY_4004_ADDRESS),
- D0F0xE4_PHY_4004_PllBiasGenPdnbOvrdVal_MASK | D0F0xE4_PHY_4004_PllBiasGenPdnbOvrdEn_MASK,
- (0x1 << D0F0xE4_PHY_4004_PllBiasGenPdnbOvrdVal_OFFSET) | (0x1 << D0F0xE4_PHY_4004_PllBiasGenPdnbOvrdEn_OFFSET)
- },
- {
- D0F0xE4_x0108_8071_ADDRESS,
- D0F0xE4_x0108_8071_RxAdjust_MASK,
- 0x3 << D0F0xE4_x0108_8071_RxAdjust_OFFSET
- },
- {
- D0F0xE4_x0108_8072_ADDRESS,
- D0F0xE4_x0108_8072_TxAdjust_MASK,
- 0x3 << D0F0xE4_x0108_8072_TxAdjust_OFFSET
- },
-};
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Configure engine list to support lane allocation according to configuration ID.
- *
- *
- *
- * @param[in] Wrapper Pointer to wrapper config descriptor
- * @param[in] EngineType Engine Type
- * @param[in] ConfigurationId Configuration ID
- * @retval AGESA_SUCCESS Configuration successfully applied
- * @retval AGESA_UNSUPPORTED No more configuration available for given engine type
- * @retval AGESA_ERROR Requested configuration not supported
- */
-AGESA_STATUS
-PcieFmConfigureEnginesLaneAllocation (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIE_ENGINE_TYPE EngineType,
- IN UINT8 ConfigurationId
- )
-{
- AGESA_STATUS Status;
- Status = AGESA_ERROR;
- switch (Wrapper->WrapId) {
- case GPP_WRAP_ID:
- if (EngineType != PciePortEngine) {
- return AGESA_UNSUPPORTED;
- }
- Status = PcieOnConfigureGppEnginesLaneAllocation (Wrapper, ConfigurationId);
- break;
- case DDI_WRAP_ID:
- if (EngineType != PcieDdiEngine) {
- return AGESA_UNSUPPORTED;
- }
- Status = PcieOnConfigureDdiEnginesLaneAllocation (Wrapper, ConfigurationId);
- break;
- default:
- ASSERT (FALSE);
-
- }
- return Status;
-}
-
-CONST UINT8 GppLaneConfigurationTable [][NUMBER_OF_GPP_PORTS * 2] = {
-//4 5 6 7 8 (SB)
- 4, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3,
- 4, 5, 6, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3,
- 4, 5, UNUSED_LANE_ID, UNUSED_LANE_ID, 6, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3,
- 4, 5, 6, 6, 7, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3,
- 4, 5, UNUSED_LANE_ID, UNUSED_LANE_ID, 6, 6, 7, 7, 0, 3,
- 4, 4, 5, 5, 6, 6, 7, 7, 0, 3
-};
-
-CONST UINT8 GppPortIdConfigurationTable [][NUMBER_OF_GPP_PORTS] = {
-//4 5 6 7 8 (SB)
- 1, 2, 3, 4, 0,
- 1, 2, 3, 4, 0,
- 1, 3, 2, 4, 0,
- 1, 2, 3, 4, 0,
- 1, 4, 2, 3, 0,
- 1, 2, 3, 4, 0
-};
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Configure GFX engine list to support lane allocation according to configuration ID.
- *
- *
- *
- * @param[in] Wrapper Pointer to wrapper config descriptor
- * @param[in] ConfigurationId Configuration ID
- * @retval AGESA_SUCCESS Configuration successfully applied
- * @retval AGESA_ERROR Requested configuration not supported
- */
-
-
-AGESA_STATUS
-STATIC
-PcieOnConfigureGppEnginesLaneAllocation (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN UINT8 ConfigurationId
- )
-{
- PCIe_ENGINE_CONFIG *EnginesList;
- UINTN CoreLaneIndex;
- UINTN PortIdIndex;
- if (ConfigurationId > ((sizeof (GppLaneConfigurationTable) / (NUMBER_OF_GPP_PORTS * 2)) - 1)) {
- return AGESA_ERROR;
- }
- EnginesList = PcieWrapperGetEngineList (Wrapper);
- CoreLaneIndex = 0;
- PortIdIndex = 0;
- do {
- EnginesList->Flags &= ~DESCRIPTOR_ALLOCATED;
- EnginesList->Type.Port.PortId = GppPortIdConfigurationTable [ConfigurationId][PortIdIndex++];
- EnginesList->Type.Port.StartCoreLane = GppLaneConfigurationTable [ConfigurationId][CoreLaneIndex++];
- EnginesList->Type.Port.EndCoreLane = GppLaneConfigurationTable [ConfigurationId][CoreLaneIndex++];
-
- } while (IS_LAST_DESCRIPTOR (EnginesList++));
- return AGESA_SUCCESS;
-}
-
-
-CONST UINT8 DdiLaneConfigurationTable [][NUMBER_OF_DDIS * 2] = {
- 0, 3, 4, 7, 8, 11
-};
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Configure DDI engine list to support lane allocation according to configuration ID.
- *
- *
- *
- * @param[in] Wrapper Pointer to wrapper config descriptor
- * @param[in] ConfigurationId Configuration ID
- * @retval AGESA_SUCCESS Configuration successfully applied
- * @retval AGESA_ERROR Requested configuration not supported
- */
-
-
-AGESA_STATUS
-STATIC
-PcieOnConfigureDdiEnginesLaneAllocation (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN UINT8 ConfigurationId
- )
-{
- PCIe_ENGINE_CONFIG *EnginesList;
- UINTN LaneIndex;
- EnginesList = PcieWrapperGetEngineList (Wrapper);
- if (ConfigurationId > ((sizeof (DdiLaneConfigurationTable) / (NUMBER_OF_DDIS * 2)) - 1)) {
- return AGESA_ERROR;
- }
- LaneIndex = 0;
- do {
- EnginesList->Flags &= ~DESCRIPTOR_ALLOCATED;
- EnginesList->EngineData.StartLane = DdiLaneConfigurationTable [ConfigurationId][LaneIndex++] +
- Wrapper->StartPhyLane;
- EnginesList->EngineData.EndLane = DdiLaneConfigurationTable [ConfigurationId][LaneIndex++] +
- Wrapper->StartPhyLane;
- } while (IS_LAST_DESCRIPTOR (EnginesList++));
- return AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Configure clock to run out of the wrapper at specific speed
- *
- *
- * @param[in] LinkSpeedCapability Link Speed capability
- * @param[in] Wrapper Pointer to wrapper config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-VOID
-PcieFmConfigureClock (
- IN PCIE_LINK_SPEED_CAP LinkSpeedCapability,
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get configuration Value for GPP wrapper
- *
- *
- *
- * @param[in] ConfigurationSignature Configuration signature
- * @param[out] ConfigurationValue Configuration value
- * @retval AGESA_SUCCESS Correct core configuration value returned by in *ConfigurationValue
- * @retval AGESA_ERROR ConfigurationSignature is incorrect
- */
-AGESA_STATUS
-PcieOnGetGppConfigurationValue (
- IN UINT64 ConfigurationSignature,
- OUT UINT8 *ConfigurationValue
- )
-{
- switch (ConfigurationSignature) {
- case GPP_CORE_x4x1x1x1x1:
- *ConfigurationValue = 0x4;
- break;
- case GPP_CORE_x4x2x1x1:
- case GPP_CORE_x4x2x1x1_ST:
- //Configuration 2:1:1 - Device Numbers 4:5:6
- //Configuration 2:1:1 - Device Numbers 4:6:7
- *ConfigurationValue = 0x3;
- break;
- case GPP_CORE_x4x2x2:
- case GPP_CORE_x4x2x2_ST:
- //Configuration 2:2 - Device Numbers 4:5
- //Configuration 2:2 - Device Numbers 4:6
- *ConfigurationValue = 0x2;
- break;
- case GPP_CORE_x4x4:
- *ConfigurationValue = 0x1;
- break;
- default:
- ASSERT (FALSE);
- return AGESA_ERROR;
- }
- return AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get core configuration value
- *
- *
- *
- * @param[in] Wrapper Pointer to internal configuration data area
- * @param[in] CoreId Core ID
- * @param[in] ConfigurationSignature Configuration signature
- * @param[out] ConfigurationValue Configuration value (for core configuration)
- * @retval AGESA_SUCCESS Configuration successfully applied
- * @retval AGESA_ERROR Core configuration value can not be determined
- */
-AGESA_STATUS
-PcieFmGetCoreConfigurationValue (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN UINT8 CoreId,
- IN UINT64 ConfigurationSignature,
- IN UINT8 *ConfigurationValue
- )
-{
- AGESA_STATUS Status;
-
- if (Wrapper->WrapId == GPP_WRAP_ID) {
- Status = PcieOnGetGppConfigurationValue (ConfigurationSignature, ConfigurationValue);
- } else {
- Status = AGESA_ERROR;
- }
- return Status;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get max link speed capability supported by this port
- *
- *
- *
- * @param[in] Flags See Flags PCIE_PORT_GEN_CAP_BOOT / PCIE_PORT_GEN_CAP_MAX
- * @param[in] Engine Pointer to engine config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- * @retval PcieGen1/PcieGen2 Max supported link gen capability
- */
-PCIE_LINK_SPEED_CAP
-PcieFmGetLinkSpeedCap (
- IN UINT32 Flags,
- IN PCIe_ENGINE_CONFIG *Engine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- PCIE_LINK_SPEED_CAP LinkSpeedCapability;
- ASSERT (Engine->Type.Port.PortData.LinkSpeedCapability < MaxPcieGen);
- LinkSpeedCapability = PcieGen2;
- if (Engine->Type.Port.PortData.LinkSpeedCapability == PcieGenMaxSupported) {
- Engine->Type.Port.PortData.LinkSpeedCapability = (UINT8) LinkSpeedCapability;
- }
- if (Pcie->PsppPolicy == PsppPowerSaving) {
- LinkSpeedCapability = PcieGen1;
- }
- if (Engine->Type.Port.PortData.LinkSpeedCapability < LinkSpeedCapability) {
- LinkSpeedCapability = Engine->Type.Port.PortData.LinkSpeedCapability;
- }
- if ((Flags & PCIE_PORT_GEN_CAP_BOOT) != 0) {
- if (Pcie->PsppPolicy == PsppBalanceLow) {
- LinkSpeedCapability = PcieGen1;
- }
- }
- return LinkSpeedCapability;
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Various initialization needed prior topology and configuration initialization
- *
- *
- *
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-VOID
-PcieFmPreInit (
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT32 Index;
- PCIe_SILICON_CONFIG *Silicon;
- PCIE_LINK_SPEED_CAP GlobalCapability;
- F14_PCIe_WRAPPER_CONFIG *F14PcieWrapper;
-
- Silicon = PcieComplexGetSiliconList (&Pcie->ComplexList[0]);
- F14PcieWrapper = &((F14_COMPLEX_CONFIG*) Silicon)->FmGppWrapper ;
- GlobalCapability = PcieUtilGlobalGenCapability (
- PCIE_PORT_GEN_CAP_MAX | PCIE_GLOBAL_GEN_CAP_ALL_PORTS,
- Pcie
- );
- if ((GlobalCapability == PcieGen1) && (F14PcieWrapper->NativeGen1Support == TRUE)) {
- PcieFmExecuteNativeGen1Reconfig (Pcie);
- }
- Silicon = PcieComplexGetSiliconList (&Pcie->ComplexList[0]);
- for (Index = 0; Index < (sizeof (PcieInitTable) / sizeof (PCIE_HOST_REGISTER_ENTRY)); Index++) {
- PcieSiliconRegisterRMW (
- Silicon,
- PcieInitTable[Index].Reg,
- PcieInitTable[Index].Mask,
- PcieInitTable[Index].Data,
- FALSE,
- Pcie
- );
- }
-
- // Set PCIe SSID.
- PcieSiliconRegisterRMW (
- Silicon,
- WRAP_SPACE (0, D0F0xE4_WRAP_8002_ADDRESS),
- D0F0xE4_WRAP_8002_SubsystemVendorID_MASK | D0F0xE4_WRAP_8002_SubsystemID_MASK,
- UserOptions.CfgGnbPcieSSID,
- FALSE,
- Pcie
- );
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Check if engine can be remapped to Device/function number requested by user
- * defined engine descriptor
- *
- * Function only called if requested device/function does not much native device/function
- *
- * @param[in] PortDescriptor Pointer to user defined engine descriptor
- * @param[in] Engine Pointer engine configuration
- * @retval TRUE Descriptor can be mapped to engine
- * @retval FALSE Descriptor can NOT be mapped to engine
- */
-
-BOOLEAN
-PcieFmCheckPortPciDeviceMapping (
- IN PCIe_PORT_DESCRIPTOR *PortDescriptor,
- IN PCIe_ENGINE_CONFIG *Engine
- )
-{
- return FALSE;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get core configuration string
- *
- * Debug function for logging configuration
- *
- * @param[in] Wrapper Pointer to internal configuration data area
- * @param[in] ConfigurationValue Configuration value
- * @retval Configuration string
- */
-
-CONST CHAR8*
-PcieFmDebugGetCoreConfigurationString (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN UINT8 ConfigurationValue
- )
-{
- switch (ConfigurationValue) {
- case 4:
- return "1x4, 4x1";
- case 3:
- return "1x4, 1x2, 2x1";
- case 2:
- return "1x4, 2x2";
- case 1:
- return "1x4, 1x4";
- default:
- break;
- }
- return " !!! Something Wrong !!!";
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get wrapper name
- *
- * Debug function for logging wrapper name
- *
- * @param[in] Wrapper Pointer to internal configuration data area
- * @retval Wrapper Name string
- */
-
-CONST CHAR8*
-PcieFmDebugGetWrapperNameString (
- IN PCIe_WRAPPER_CONFIG *Wrapper
- )
-{
- switch (Wrapper->WrapId) {
- case GPP_WRAP_ID:
- return "GPPSB";
- case DDI_WRAP_ID:
- return "Virtual DDI";
- default:
- break;
- }
- return " !!! Something Wrong !!!";
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get register address name
- *
- * Debug function for logging register trace
- *
- * @param[in] AddressFrame Address Frame
- * @retval Register address name
- */
-CONST CHAR8*
-PcieFmDebugGetHostRegAddressSpaceString (
- IN UINT16 AddressFrame
- )
-{
- switch (AddressFrame) {
- case 0x130:
- return "GPP WRAP";
- case 0x110:
- return "GPP PIF0";
- case 0x120:
- return "GPP PHY0";
- case 0x101:
- return "GPP CORE";
- default:
- break;
- }
- return " !!! Something Wrong !!!";
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Execute/clean up reconfiguration for Gen 1 native mode
- *
- *
- *
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-VOID
-PcieFmExecuteNativeGen1Reconfig (
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmExecuteNativeGen1Reconfig Enter\n");
- NbSmuServiceRequest (19, FALSE, GnbLibGetHeader (Pcie));
- IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmExecuteNativeGen1Reconfig Enter\n");
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Check if the lane can be muxed by link width requested by user
- * defined engine descriptor
- *
- * Check Engine StartCoreLane could be aligned by user requested link width(x1, x2, x4, x8, x16).
- * Check Engine StartCoreLane could be aligned by user requested link width x2.
- *
- * @param[in] PortDescriptor Pointer to user defined engine descriptor
- * @param[in] Engine Pointer engine configuration
- * @retval TRUE Lane can be muxed
- * @retval FALSE LAne can NOT be muxed
- */
-
-BOOLEAN
-PcieFmCheckPortPcieLaneCanBeMuxed (
- IN PCIe_PORT_DESCRIPTOR *PortDescriptor,
- IN PCIe_ENGINE_CONFIG *Engine
- )
-{
- UINT16 DescriptorHiLane;
- UINT16 DescriptorLoLane;
- UINT16 DescriptorNumberOfLanes;
- PCIe_WRAPPER_CONFIG *Wrapper;
- UINT16 NormalizedLoPhyLane;
- BOOLEAN Result;
-
- Result = FALSE;
- Wrapper = (PCIe_WRAPPER_CONFIG *)Engine->Wrapper;
- DescriptorLoLane = MIN (PortDescriptor->EngineData.StartLane, PortDescriptor->EngineData.EndLane);
- DescriptorHiLane = MAX (PortDescriptor->EngineData.StartLane, PortDescriptor->EngineData.EndLane);
- DescriptorNumberOfLanes = DescriptorHiLane - DescriptorLoLane + 1;
-
- NormalizedLoPhyLane = DescriptorLoLane - Wrapper->StartPhyLane;
-
- if (NormalizedLoPhyLane == Engine->Type.Port.StartCoreLane) {
- Result = TRUE;
- } else {
- if (((Engine->Type.Port.StartCoreLane % 2) == 0) || (Engine->Type.Port.StartCoreLane == 0)) {
- if (NormalizedLoPhyLane == 0) {
- Result = TRUE;
- } else {
- if (((NormalizedLoPhyLane % 2) == 0) && ((NormalizedLoPhyLane % DescriptorNumberOfLanes) == 0)) {
- Result = TRUE;
- }
- }
- }
- }
-
- return Result;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/OntarioComplexData.h b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/OntarioComplexData.h
deleted file mode 100644
index b9f9a04..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/OntarioComplexData.h
+++ /dev/null
@@ -1,241 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Family specific PCIe configuration data definition
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 37710 $ @e \$Date: 2010-09-10 11:08:20 +0800 (Fri, 10 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _ONTARIOCOMPLEXDATA_H_
-#define _ONTARIOCOMPLEXDATA_H_
-
-STATIC
-F14_COMPLEX_CONFIG ComplexData = {
- //Silicon
- {
- DESCRIPTOR_TERMINATE_LIST,
- {0},
- offsetof (F14_COMPLEX_CONFIG, GppWrapper),
- NULL
- },
- //Gpp Wrapper
- {
- DESCRIPTOR_PCIE_WRAPPER,
- GPP_WRAP_ID,
- GPP_NUMBER_OF_PIFs,
- GPP_START_PHY_LANE,
- GPP_END_PHY_LANE,
- GPP_CORE_ID,
- GPP_CORE_ID,
- {
- 1, //PowerOffUnusedLanesEnabled,
- 1, //PowerOffUnusedPllsEnabled
- 1, //ClkGating
- 1, //LclkGating
- 1, //TxclkGatingPllPowerDown
- 1 //PllOffInL1
- },
- offsetof (F14_COMPLEX_CONFIG, Port4),
- offsetof (F14_COMPLEX_CONFIG, Silicon),
- offsetof (F14_COMPLEX_CONFIG, FmGppWrapper)
- },
- //Virtual DDI Wrapper
- {
- DESCRIPTOR_DDI_WRAPPER | DESCRIPTOR_VIRTUAL | DESCRIPTOR_TERMINATE_LIST,
- DDI_WRAP_ID,
- 0,
- DDI_START_PHY_LANE,
- DDI_END_PHY_LANE,
- 0xff,
- 0x0,
- {
- 1, //PowerOffUnusedLanesEnabled,
- 1, //PowerOffUnusedPllsEnabled
- 1, //ClkGating
- 1, //LclkGating
- 1, //TxclkGatingPllPowerDown
- 0 //PllOffInL1
- },
- offsetof (F14_COMPLEX_CONFIG, Dpa),
- offsetof (F14_COMPLEX_CONFIG, Silicon),
- NULL
- },
- //Port 4
- {
- DESCRIPTOR_PCIE_ENGINE,
- offsetof (F14_COMPLEX_CONFIG, GppWrapper),
- { PciePortEngine, 4, 4},
- 0, //Initialization Status
- 0xFF, //Scratch
- {
- {
- {0},
- 4,
- 4,
- 4,
- 0,
- GPP_CORE_ID,
- 1,
- 0,
- FALSE,
- LinkStateResetExit
- },
- },
- },
- //Port 5
- {
- DESCRIPTOR_PCIE_ENGINE,
- offsetof (F14_COMPLEX_CONFIG, GppWrapper),
- { PciePortEngine, 5, 5},
- 0, //Initialization Status
- 0xFF, //Scratch
- {
- {
- {0},
- 5,
- 5,
- 5,
- 0,
- GPP_CORE_ID,
- 2,
- 0,
- FALSE,
- LinkStateResetExit
- },
- },
- },
- //Port 6
- {
- DESCRIPTOR_PCIE_ENGINE,
- offsetof (F14_COMPLEX_CONFIG, GppWrapper),
- { PciePortEngine, 6, 6 },
- 0, //Initialization Status
- 0xFF, //Scratch
- {
- {
- {0},
- 6,
- 6,
- 6,
- 0,
- GPP_CORE_ID,
- 3,
- 0,
- FALSE,
- LinkStateResetExit
- },
- },
- },
- //Port 7
- {
- DESCRIPTOR_PCIE_ENGINE,
- offsetof (F14_COMPLEX_CONFIG, GppWrapper),
- { PciePortEngine, 7, 7 },
- 0, //Initialization Status
- 0xFF, //Scratch
- {
- {
- {0},
- 7,
- 7,
- 7,
- 0,
- GPP_CORE_ID,
- 4,
- 0,
- FALSE,
- LinkStateResetExit
- },
- },
- },
- //Port 8
- {
- DESCRIPTOR_PCIE_ENGINE | DESCRIPTOR_TERMINATE_LIST,
- offsetof (F14_COMPLEX_CONFIG, GppWrapper),
- { PciePortEngine, 0, 3 },
- 0, //Initialization Status
- 0xFF, //Scratch
- {
- {
- {PortEnabled, 0, 8, 0, PcieGenMaxSupported, AspmL0sL1, HotplugDisabled, 0x0, {0}},
- 0,
- 3,
- 8,
- 0,
- GPP_CORE_ID,
- 0,
- MAKE_SBDFO (0, 0, 8, 0, 0),
- TRUE,
- LinkStateTrainingSuccess
- },
- },
- },
- //Virtual DpA
- {
- DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_VIRTUAL,
- offsetof (F14_COMPLEX_CONFIG, DdiWrapper),
- {PcieDdiEngine},
- 0, //Initialization Status
- 0xFF, //Scratch
- },
- //Virtual DpB
- {
- DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_VIRTUAL,
- offsetof (F14_COMPLEX_CONFIG, DdiWrapper),
- {PcieDdiEngine},
- 0, //Initialization Status
- 0xFF, //Scratch
- },
- //Virtual VGA
- {
- DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_VIRTUAL | DESCRIPTOR_TERMINATE_LIST,
- offsetof (F14_COMPLEX_CONFIG, DdiWrapper),
- {PcieDdiEngine},
- 0, //Initialization Status
- 0xFF, //Scratch
- },
- //Native Gen Support
- //Set to TRUE after bringup
- {
- TRUE,
- }
-
-};
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/OntarioDefinitions.h b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/OntarioDefinitions.h
deleted file mode 100644
index dd78ce9..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/OntarioDefinitions.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Family specific PCIe definitions
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 35664 $ @e \$Date: 2010-07-28 20:02:15 +0800 (Wed, 28 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _LLANODEFINITIONS_H_
-#define _LLANODEFINITIONS_H_
-
-#define SOCKET_ID 0
-
-#define MAX_NUM_PHYs 2
-#define MAX_NUM_LANE_PER_PHY 8
-
-
-#define NUMBER_OF_GPP_PORTS 5
-#define NUMBER_OF_DDIS 3
-#define NUMBER_OF_WRAPPERS 2
-#define NUMBER_OF_SILICONS 1
-
-#define GPP_WRAP_ID 0
-#define GPP_NUMBER_OF_PIFs 1
-#define GPP_START_PHY_LANE 0
-#define GPP_END_PHY_LANE 7
-#define GPP_CORE_ID 1
-
-#define GPP_CORE_x4x1x1x1x1 ((1ull << 32) | (1ull << 24) | (1ull << 16) | (1ull << 8) | (4ull << 0))
-#define GPP_CORE_x4x2x1x1 ((2ull << 32) | (1ull << 24) | (1ull << 16) | (0ull << 8) | (4ull << 0))
-#define GPP_CORE_x4x2x1x1_ST ((2ull << 32) | (0ull << 24) | (1ull << 16) | (1ull << 8) | (4ull << 0))
-#define GPP_CORE_x4x2x2 ((2ull << 32) | (2ull << 24) | (0ull << 16) | (0ull << 8) | (4ull << 0))
-#define GPP_CORE_x4x2x2_ST ((2ull << 32) | (0ull << 24) | (2ull << 16) | (0ull << 8) | (4ull << 0))
-#define GPP_CORE_x4x4 ((4ull << 32) | (0ull << 24) | (0ull << 16) | (0ull << 8) | (4ull << 0))
-
-#define DDI_WRAP_ID 2
-#define DDI_NUMBER_OF_PIFs 1
-#define DDI_START_PHY_LANE 8
-#define DDI_END_PHY_LANE 19
-
-
-
-/// F14 PCIe Wrapper Configuration
-typedef struct {
- BOOLEAN NativeGen1Support; ///< Native Gen1 support
-} F14_PCIe_WRAPPER_CONFIG;
-
-
-/// Complex Configuration
-typedef struct {
- PCIe_SILICON_CONFIG Silicon; ///< Silicon
- PCIe_WRAPPER_CONFIG GppWrapper; ///< GPP Wrapper
- PCIe_WRAPPER_CONFIG DdiWrapper; ///< Virtual DDI Wrapper
- PCIe_ENGINE_CONFIG Port4; ///< Port 4
- PCIe_ENGINE_CONFIG Port5; ///< Port 5
- PCIe_ENGINE_CONFIG Port6; ///< Port 6
- PCIe_ENGINE_CONFIG Port7; ///< Port 7
- PCIe_ENGINE_CONFIG Port8; ///< Port 8
- PCIe_ENGINE_CONFIG Dpa; ///< Virtual DPA
- PCIe_ENGINE_CONFIG Dpb; ///< Virtual DPB
- PCIe_ENGINE_CONFIG Vga; ///< Virtual VGA
- F14_PCIe_WRAPPER_CONFIG FmGppWrapper; ///< F14 Pcie Wrapper
-} F14_COMPLEX_CONFIG;
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/PcieFamilyServices.h b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/PcieFamilyServices.h
deleted file mode 100644
index 51fe82e..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/PcieFamilyServices.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/* $NoKeywords:$ */
-
-/**
- * @file
- *
- * Family specific PCIe services.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _PCIECOMPLEXCONFIG_H_
-#define _PCIECOMPLEXCONFIG_H_
-
-
-VOID
-PcieFmPhyApplyGanging (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-AGESA_STATUS
-PcieFmPhyLetPllPersonalityInitCallback (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN VOID *Buffer,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PcieFmPhyChannelCharacteristic (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PcieFmPortVisabilityControl (
- IN PCIE_PORT_VISIBILITY Control,
- IN PCIe_SILICON_CONFIG *Silicon,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PcieFmPreInit (
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-
-VOID
-PcieFmAvertClockPickers (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PcieFmSetBootUpVoltage (
- IN PCIE_LINK_SPEED_CAP LinkCap,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PcieFmEnableSlotPowerLimit (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PcieFmConfigureClock (
- IN PCIE_LINK_SPEED_CAP LinkSpeedCapability,
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PcieFmPifSetRxDetectPowerMode (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PcieFmPifSetPllModeForL1 (
- IN UINT32 LaneBitmap,
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-UINT8
-PcieFmPifGetPllPowerUpLatency (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-AGESA_STATUS
-PcieFmPhyLaneInitInitCallback (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN VOID *Buffer,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-#endif
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Feature/PCieSmuLibV1.esl b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Feature/PCieSmuLibV1.esl
deleted file mode 100644
index 5ca8352..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Feature/PCieSmuLibV1.esl
+++ /dev/null
@@ -1,217 +0,0 @@
-/**
- * @file
- *
- * ALIB PSPP Pcie Smu Lib V1
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 25430 $ @e \$Date: 2010-01-18 22:25:55 -0800 (Mon, 18 Jan 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
- /*----------------------------------------------------------------------------------------*/
- /**
- * SMU indirect register read
- *
- * Arg0 - Smu register offset
- *
- */
- Method (procNbSmuIndirectRegisterRead, 1, NotSerialized) {
- Store (procIndirectRegisterRead (0x0, 0x60, 0xCD), Local0)
- // Access 32 bit width
- Increment (Arg0)
- // Reverse ReqToggle
- Or (And (Local0, 0xFEFFFFFF), And (Not (And (Local0, 0x01000000)), 0x01000000),Local0)
- // Assign Address and ReqType = 0
- Or (And (Local0, 0xFD00FFFF), ShiftLeft (Arg0, 16), Local0)
-
- procIndirectRegisterWrite (0x0, 0x60, 0xCD, Local0)
-
- Store (procIndirectRegisterRead (0x0, 0x60, 0xCE), Local0)
- return (Local0)
- }
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * SMU indirect register Write
- *
- * Arg0 - Smu register offset
- * Arg1 - Value
- * Arg2 - Width, 0 = 16, 1 = 32
- *
- */
- Method (procNbSmuIndirectRegisterWrite, 3, NotSerialized) {
- Store (procIndirectRegisterRead (0x0, 0x60, 0xCD), Local0)
- // Get low 16 bit value
- Store (And (Arg1, 0xFFFF), Local1)
- // Reverse ReqToggle
- Or (And (Local0, 0xFEFFFFFF), And (Not (And (Local0, 0x01000000)), 0x01000000),Local0)
- // Assign Address
- Or (And (Local0, 0xFD000000), ShiftLeft (Arg0, 16), Local0)
- // ReqType = 1
- Or (Local0, 0x02000000, Local0)
- // Assign Low 16 bit value
- Or (Local0, Local1, Local0)
-
- procIndirectRegisterWrite (0x0, 0x60, 0xCD, Local0)
-
- if (LEqual (Arg2, 1)) {
- // Get high 16 bit value
- Store (ShiftRight (Arg1, 16), Local1)
- // Reverse ReqToggle
- Or (And (Local0, 0xFEFFFFFF), And (Not (And (Local0, 0x01000000)), 0x01000000),Local0)
- // Assign Address
- Or (And (Local0, 0xFF000000), ShiftLeft (Add (Arg0, 1), 16), Local0)
- // Assign High 16 bit value
- Or (Local0, Local1, Local0)
-
- procIndirectRegisterWrite (0x0, 0x60, 0xCD, Local0)
- }
-
- }
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * SMU Service request
- *
- * Arg0 - Smu service id
- * Arg1 - Flags - Poll Ack = 1, Poll down = 2
- *
- */
- Method (procNbSmuServiceRequest, 2, NotSerialized) {
- Store ("NbSmuServiceRequest Enter", Debug)
- Store ("Request id =", Debug)
- Store (Arg0, Debug)
-
- Or (ShiftLeft (Arg0, 3), 0x1, Local0)
- procNbSmuIndirectRegisterWrite (0x3, Local0, 1)
-
- if (LAnd (Arg1, 1)) {
- while (LNotEqual (AND(procNbSmuIndirectRegisterRead (0x3), 0x2), 0x2)) {
- Store ("--Wait Ack--", Debug)
- }
- }
- if (LAnd (Arg1, 2)) {
- while (LNotEqual (AND(procNbSmuIndirectRegisterRead (0x3), 0x4), 0x4)) {
- Store ("--Wait Done--", Debug)
- }
- }
- // Clear IRQ register
- procNbSmuIndirectRegisterWrite (0x3, 0, 0)
- Store ("NbSmuServiceRequest Exit", Debug)
- }
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * Write RCU register
- *
- * Arg0 - Register Address
- * Arg1 - Register Data
- *
- */
- Method (procSmuRcuWrite, 2, NotSerialized) {
- procNbSmuIndirectRegisterWrite (0xB, Arg0, 0)
- procNbSmuIndirectRegisterWrite (0x5, Arg1, 1)
-
- }
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * Read RCU register
- *
- * Arg0 - Register Address
- * Retval - RCU register value
- */
- Method (procSmuRcuRead, 1, NotSerialized) {
- procNbSmuIndirectRegisterWrite (0xB, Arg0, 0)
- Store (procNbSmuIndirectRegisterRead (0x5), Local0)
- return (Local0)
- }
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * SMU SRBM Register Read
- *
- * Arg0 - FCR register address
- *
- */
- Method (procNbSmuSrbmRegisterRead, 1, NotSerialized) {
- //SMUx0B_x8600
- Store (Or (And (Arg0, 0xFF), 0x01865000), Local0)
- //SMUx0B_x8604
- Store (Or (And (Arg0, 0xFFFFFF00), 4), Local1)
- //SMUx0B_x8608
- Store (Or (ShiftLeft (3, 30), ShiftLeft (1, 18)), Local2)
- //Write SMU RCU
- procSmuRcuWrite (0x8600, Local0)
- procSmuRcuWrite (0x8604, Local1)
- procSmuRcuWrite (0x8608, Local2)
- // ServiceId
- if (LEqual (ShiftRight (Arg0, 16), 0xFE00)) {
- procNbSmuServiceRequest (0xD, 0x3)
- }
- if (LEqual (ShiftRight (Arg0, 16), 0xFE30)) {
- procNbSmuServiceRequest (0xB, 0x3)
- }
- return (procSmuRcuRead(0x8650))
- }
-
-
- /*----------------------------------------------------------------------------------------*/
- /**
- * SMU SRBM Register Write
- *
- * Arg0 - FCR register address
- * Arg1 - Value
- *
- */
- Method (procNbSmuSrbmRegisterWrite, 2, NotSerialized) {
- //SMUx0B_x8600
- Store (Or (And (Arg0, 0xFF), 0x01865000), Local0)
- //SMUx0B_x8604
- Store (Or (And (Arg0, 0xFFFFFF00), 4), Local1)
- //SMUx0B_x8608
- Store (Or (ShiftLeft (3, 30), ShiftLeft (1, 18)), Local2)
- Or (Local2, ShiftLeft (1, 16), Local2)
- //Write SMU RCU
- procSmuRcuWrite (0x8600, Local0)
- procSmuRcuWrite (0x8604, Local1)
- procSmuRcuWrite (0x8608, Local2)
- //Write Data
- procSmuRcuWrite (0x8650, Arg1)
- // ServiceId
- procNbSmuServiceRequest (0xB, 0x3)
- }
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Feature/PciePowerGate.c b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Feature/PciePowerGate.c
deleted file mode 100644
index 68ce810..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Feature/PciePowerGate.c
+++ /dev/null
@@ -1,372 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe power gate
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "amdlib.h"
-#include "Gnb.h"
-#include "GnbPcie.h"
-#include "PcieInit.h"
-#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1)
-#include GNB_MODULE_DEFINITIONS (GnbPcieConfig)
-#include "PciePowerGate.h"
-#include "GnbRegistersON.h"
-#include "NbSmuLib.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_PCIE_FEATURE_PCIEPOWERGATE_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-#define FORCE_PCIE_POWERGATING_DISABLE (1 << 2)
-#define FORCE_PCIE_PHY_POWERGATING_DISABLE (1 << 1)
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-POWER_GATE_DATA PciePowerGatingData = {
- 113, 50, 50, 50, 50, 50
-};
-
-
-/// PCIe power gating
-UINT32 PciePowerGatingTable_1[] = {
-// SMUx0B_x8408_ADDRESS
- 0,
-// SMUx0B_x840C_ADDRESS
- 0,
-// SMUx0B_x8410_ADDRESS
- (0x0 << SMUx0B_x8410_PwrGatingEn_OFFSET) |
- (0x1 << SMUx0B_x8410_PsoControlValidNum_OFFSET) |
- (0x3 << SMUx0B_x8410_PwrGaterSel_OFFSET)
-};
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * PCIe Power Gating
- *
- *
- *
- * @param[in] StdHeader Standard Configuration Header
- * @param[in] Flags Force Powergating disable or Phy disable flag.
- * @param[in] PowerGateData Power Gate data
- */
-
-
-VOID
-STATIC
-PcieSmuPowerGatingInit (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN UINT8 Flags,
- IN POWER_GATE_DATA *PowerGateData
- )
-{
-
- NbSmuRcuRegisterWrite (
- SMUx0B_x8408_ADDRESS,
- &PciePowerGatingTable_1[0],
- sizeof (PciePowerGatingTable_1) / sizeof (UINT32),
- TRUE,
- StdHeader
- );
-
- NbSmuRcuRegisterWrite (
- SMUx0B_x84A0_ADDRESS,
- (UINT32 *) PowerGateData,
- sizeof (POWER_GATE_DATA) / sizeof (UINT32),
- TRUE,
- StdHeader
- );
- if (Flags != 0) {
- UINT32 Value;
- ASSERT ((Flags & (~(BIT1 | BIT2))) == 0);
- NbSmuRcuRegisterRead (SMUx0B_x8410_ADDRESS, &Value, 1, StdHeader);
- Value |= (Flags & (BIT1 | BIT2));
- NbSmuRcuRegisterWrite (SMUx0B_x8410_ADDRESS, &Value, 1, TRUE, StdHeader);
- }
- NbSmuServiceRequest (0x01, TRUE, StdHeader);
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * PCIe PowerGate PHY lanes
- *
- *
- * @param[in] WrapperLaneBitMap Lane bitmap on wrapper
- * @param[in] WrapperStartlaneId Start Line Id of the wrapper
- * @param[in] Service Power gate service
- * @param[in] Core Core power gate request
- * @param[in] Tx Tx power gate request
- * @param[in] Rx Rx power gate request
- * @param[in] Pcie PCIe configuration data
- */
-
-VOID
-STATIC
-PcieSmuPowerGateLanes (
- IN UINT32 WrapperLaneBitMap,
- IN UINT16 WrapperStartlaneId,
- IN UINT8 Service,
- IN UINT8 Core,
- IN UINT8 Tx,
- IN UINT8 Rx,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- PCIe_PHY_POWER_GATE LaneSegment;
- UINT8 NumberOfLanes;
- UINT8 Index;
- LaneSegment.Tx = Tx;
- LaneSegment.Rx = Rx;
- LaneSegment.Core = Core;
- NumberOfLanes = 0;
- for (Index = 0; Index <= 32; Index++) {
- if ((WrapperLaneBitMap & 1) != 0) {
- NumberOfLanes++;
- } else {
- if (NumberOfLanes != 0) {
- LaneSegment.LowerLaneId = Index - NumberOfLanes + WrapperStartlaneId;
- LaneSegment.UpperLaneId = Index - 1 + WrapperStartlaneId;
- IDS_HDT_CONSOLE (PCIE_MISC, " Powergate Phy Lanes %d - %d (Service = 0x%x, Core = 0x%x, Tx = 0x%x, Rx = 0x%x)\n",
- LaneSegment.LowerLaneId, LaneSegment.UpperLaneId, Service, Core, Tx, Rx
- );
- NbSmuRcuRegisterWrite (
- 0x858C,
- (UINT32*) &LaneSegment,
- 1,
- TRUE,
- GnbLibGetHeader (Pcie)
- );
- NbSmuServiceRequest (Service, TRUE, GnbLibGetHeader (Pcie));
- NumberOfLanes = 0;
- }
- }
- WrapperLaneBitMap >>= 1;
- }
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Pll access required
- *
- * @param[in] PllId Pll ID
- * @param[in] AccessRequired Access required
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-VOID
-STATIC
-PciePowerGatePllControl (
- IN UINT8 PllId,
- IN BOOLEAN AccessRequired,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT32 Value;
- IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePllControl Enter\n");
- NbSmuRcuRegisterRead (0x859C, &Value, 1, GnbLibGetHeader (Pcie));
- Value = (Value & 0xFFFFFF00) | PllId;
- NbSmuRcuRegisterWrite (0x859C, &Value, 1, TRUE, GnbLibGetHeader (Pcie));
- NbSmuServiceRequest (AccessRequired ? 0x18 : 0x17, TRUE, GnbLibGetHeader (Pcie));
- IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePllControl Exit\n");
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Report used lanes to SMU.
- *
- *
- * @param[in] Wrapper Wrapper configuration descriptor
- * @param[in, out] Buffer Not used
- * @param[in] Pcie Pointer to global PCIe configuration
- * @retval AGESA_STATUS
- */
-
-AGESA_STATUS
-STATIC
-PciePowerGateReportUsedLanesCallback (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN OUT VOID *Buffer,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT32 LaneBitmap;
- LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_ACTIVE | LANE_TYPE_DDI_ACTIVE | LANE_TYPE_PCIE_HOTPLUG, 0, Wrapper, Pcie);
- if (LaneBitmap != 0) {
- PcieSmuPowerGateLanes (LaneBitmap, Wrapper->StartPhyLane, 0x14, 0x1, 0x0, 0x0, Pcie);
- }
- return AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * PCIe PowerGate PHY lanes
- *
- *
- * @param[in] Wrapper Wrapper configuration descriptor
- * @param[out] Buffer Pointer to Boolean to report if DDI lanes present
- * @param[in] Pcie Pointer to global PCIe configuration
- * @retval AGESA_STATUS
- */
-
-AGESA_STATUS
-STATIC
-PciePowerGatePhyLaneCallback (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN OUT VOID *Buffer,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT32 LaneBitmap;
- BOOLEAN *IsDdiPresent;
- IsDdiPresent = (BOOLEAN*) Buffer;
- LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_ALL, LANE_TYPE_PCIE_ACTIVE | LANE_TYPE_DDI_ACTIVE | LANE_TYPE_PCIE_HOTPLUG, Wrapper, Pcie);
- if (LaneBitmap != 0) {
- PcieSmuPowerGateLanes (LaneBitmap, Wrapper->StartPhyLane, 0x13, 0x1, 0x1, 0x1, Pcie);
- }
- // Powergate inactive hotplug lanes
- LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_HOTPLUG, LANE_TYPE_PCIE_ACTIVE, Wrapper, Pcie);
- if (LaneBitmap != 0) {
- PcieSmuPowerGateLanes (LaneBitmap, Wrapper->StartPhyLane, 0x13, 0x0, 0x1, 0x1, Pcie);
- }
- // Powergate DDI lanes
- LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_DDI_ACTIVE, 0, Wrapper, Pcie);
- if (LaneBitmap != 0) {
- *IsDdiPresent = TRUE;
- PcieSmuPowerGateLanes (LaneBitmap, Wrapper->StartPhyLane, 0x13, 0x0, 0x0, 0x1, Pcie);
- }
- return AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * PCIe PowerGate PHY lanes
- *
- *
- *
- * @param[in] StdHeader Standard Configuration Header
- * @retval AGESA_STATUS
- */
-
-AGESA_STATUS
-STATIC
-PciePowerGatePhyLane (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_STATUS Status;
- AGESA_STATUS AgesaStatus;
- BOOLEAN IsDdiPresent;
- PCIe_PLATFORM_CONFIG *Pcie;
- AgesaStatus = AGESA_SUCCESS;
- IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePhyLane Enter\n");
- Status = PcieLocateConfigurationData (StdHeader, &Pcie);
- ASSERT (Status == AGESA_SUCCESS);
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
- if (Status == AGESA_SUCCESS) {
- PciePortsVisibilityControl (UnhidePorts, Pcie);
- IsDdiPresent = FALSE;
- Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PciePowerGateReportUsedLanesCallback, NULL, Pcie );
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
- PciePowerGatePllControl (0x1, TRUE, Pcie);
- Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PciePowerGatePhyLaneCallback, &IsDdiPresent, Pcie );
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
- if (!IsDdiPresent) {
- PciePowerGatePllControl (0x1, FALSE, Pcie);
- }
- PciePortsVisibilityControl (HidePorts, Pcie);
- }
- IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePhyLane Exit\n");
- return Status;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Power PCIe block
- *
- *
- *
- * @param[in] StdHeader Pointer to Standard configuration
- * @retval AGESA_STATUS
- */
-
-AGESA_STATUS
-PciePowerGateFeature (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- PCIE_POWERGATE_CONFIG PciePowerGate;
- AGESA_STATUS Status;
- UINT8 Flags;
- IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGateFeature Enter\n");
- Status = AGESA_SUCCESS;
- PciePowerGate.Services.PciePowerGate = 0x1;
- PciePowerGate.Services.PciePhyLanePowerGate = 0x1;
- LibAmdMemCopy (&PciePowerGate.Pcie, &PciePowerGatingData, sizeof (POWER_GATE_DATA), StdHeader);
- IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PCIE_POWERGATE_CONFIG, &PciePowerGate, StdHeader);
- Flags = 0;
- if (PciePowerGate.Services.PciePowerGate == 0x0) {
- IDS_HDT_CONSOLE (PCIE_MISC, " Pcie Power Gating - Disabled\n");
- Flags |= FORCE_PCIE_POWERGATING_DISABLE;
- }
- if (PciePowerGate.Services.PciePhyLanePowerGate == 0x0) {
- IDS_HDT_CONSOLE (PCIE_MISC, " Pcie Phy Power Gating - Disabled\n");
- Flags |= FORCE_PCIE_PHY_POWERGATING_DISABLE;
- }
- PcieSmuPowerGatingInit (StdHeader, Flags, &PciePowerGate.Pcie);
- Status = PciePowerGatePhyLane (StdHeader);
- IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGateFeature Exit [0x%x]\n", Status);
- return Status;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Feature/PciePowerGate.h b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Feature/PciePowerGate.h
deleted file mode 100644
index 34aef56..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Feature/PciePowerGate.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Service procedure to calculate PCIe topology segment maximum exit latency
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _PCIEPOWERGATE_H_
-#define _PCIEPOWERGATE_H_
-
-/// PCIe power gate configuration
-typedef struct {
- struct {
- UINT32 PciePowerGate :1; ///< Enable core power gating
- UINT32 PciePhyLanePowerGate:1; ///< Enable phy lane power gating
- } Services; ///< Power gating services
- POWER_GATE_DATA Pcie; ///< PCIe Power gating Data
-} PCIE_POWERGATE_CONFIG;
-
-/// PCIe PHY power gate config
-typedef struct {
- UINT32 Rx :1; ///< RX state
- UINT32 Tx :1; ///< TX state
- UINT32 Core :1; ///< Core
- UINT32 Reserved :13; ///< reserved
- UINT32 LowerLaneId :8; ///< Lower lane ID
- UINT32 UpperLaneId :8; ///< Upper lane ID
-} PCIe_PHY_POWER_GATE;
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInit.c b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInit.c
deleted file mode 100644
index 8b49ad8..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInit.c
+++ /dev/null
@@ -1,349 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Pre-training PCIe subsystem initialization routines.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "Gnb.h"
-#include "GnbPcie.h"
-#include "GnbPcieFamServices.h"
-#include "PcieFamilyServices.h"
-#include "PcieInit.h"
-#include "PcieMiscLib.h"
-#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1)
-#include GNB_MODULE_DEFINITIONS (GnbPcieConfig)
-#include GNB_MODULE_DEFINITIONS (GnbPcieTrainingV1)
-#include "GnbRegistersON.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_PCIE_PCIEINIT_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Control port visibility in PCI config space
- *
- *
- * @param[in] Control Make port Hide/Unhide ports
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-VOID
-PciePortsVisibilityControl (
- IN PCIE_PORT_VISIBILITY Control,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- PCIe_COMPLEX_CONFIG *ComplexList;
- ComplexList = &Pcie->ComplexList[0];
- while (ComplexList != NULL) {
- PCIe_SILICON_CONFIG *SiliconList;
- SiliconList = PcieComplexGetSiliconList (ComplexList);
- while (SiliconList != NULL) {
- PcieFmPortVisabilityControl (Control, SiliconList, Pcie);
- SiliconList = PcieLibGetNextDescriptor (SiliconList);
- }
- ComplexList = PcieLibGetNextDescriptor (ComplexList);
- }
-}
-
-
-PCIE_HOST_REGISTER_ENTRY CoreInitTable [] = {
- {
- D0F0xE4_CORE_0020_ADDRESS,
- D0F0xE4_CORE_0020_CiRcOrderingDis_MASK,
- (0x1 << D0F0xE4_CORE_0020_CiRcOrderingDis_OFFSET)
- },
- {
- 0x10,
- 0x1c00,
- (0x4 << 10)
- },
- {
- D0F0xE4_CORE_001C_ADDRESS,
- D0F0xE4_CORE_001C_TxArbRoundRobinEn_MASK |
- D0F0xE4_CORE_001C_TxArbSlvLimit_MASK |
- D0F0xE4_CORE_001C_TxArbMstLimit_MASK,
- (0x1 << D0F0xE4_CORE_001C_TxArbRoundRobinEn_OFFSET) |
- (0x4 << D0F0xE4_CORE_001C_TxArbSlvLimit_OFFSET) |
- (0x4 << D0F0xE4_CORE_001C_TxArbMstLimit_OFFSET)
- },
- {
- D0F0xE4_CORE_0040_ADDRESS,
- D0F0xE4_CORE_0040_PElecIdleMode_MASK,
- (0x2 << D0F0xE4_CORE_0040_PElecIdleMode_OFFSET)
- },
- {
- D0F0xE4_CORE_0002_ADDRESS,
- D0F0xE4_CORE_0002_HwDebug_0__MASK,
- (0x1 << D0F0xE4_CORE_0002_HwDebug_0__OFFSET)
- },
- {
- D0F0xE4_CORE_00C1_ADDRESS,
- D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_MASK |
- D0F0xE4_CORE_00C1_StrapGen2Compliance_MASK,
- (0x1 << D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_OFFSET) |
- (0x1 << D0F0xE4_CORE_00C1_StrapGen2Compliance_OFFSET)
- },
- {
- D0F0xE4_CORE_00B0_ADDRESS,
- D0F0xE4_CORE_00B0_StrapF0MsiEn_MASK,
- (0x1 << D0F0xE4_CORE_00B0_StrapF0MsiEn_OFFSET)
- }
-};
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Common Core Init
- *
- *
- * @param[in] Wrapper Pointer to wrapper configuration descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-VOID
-PcieCommonCoreInit (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- UINT8 CoreId;
- UINTN Index;
- if (PcieLibIsPcieWrapper (Wrapper)) {
- IDS_HDT_CONSOLE (GNB_TRACE, "PcieCommonCoreInit Enter\n");
- for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
- for (Index = 0; Index < sizeof (CoreInitTable) / sizeof (PCIE_HOST_REGISTER_ENTRY); Index++) {
- UINT32 Value;
- Value = PcieRegisterRead (
- Wrapper,
- CORE_SPACE (CoreId, CoreInitTable[Index].Reg),
- Pcie
- );
- Value &= (~CoreInitTable[Index].Mask);
- Value |= CoreInitTable[Index].Data;
- PcieRegisterWrite (
- Wrapper,
- CORE_SPACE (CoreId, CoreInitTable[Index].Reg),
- Value,
- FALSE,
- Pcie
- );
- }
- }
- IDS_HDT_CONSOLE (GNB_TRACE, "PcieCommonCoreInit Exit\n");
- }
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Per wrapper Pcie Init SRBM reset prior Aaccess to wrapper registers.
- *
- *
- * @param[in] Wrapper Pointer to wrapper configuration descriptor
- * @param[in] Buffer Pointer buffer
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-AGESA_STATUS
-PcieInitSrbmCallback (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN OUT VOID *Buffer,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- PcieTopologyInitSrbmReset (TRUE, Wrapper, Pcie);
- return AGESA_SUCCESS;
-}
-/*----------------------------------------------------------------------------------------*/
-/**
- * Per wrapper Pcie Init prior training.
- *
- *
- * @param[in] Wrapper Pointer to wrapper configuration descriptor
- * @param[in] Buffer Pointer buffer
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-AGESA_STATUS
-PcieInitCallback (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN OUT VOID *Buffer,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- AGESA_STATUS Status;
- PcieTopologyPrepareForReconfig (Wrapper, Pcie);
- Status = PcieTopologySetCoreConfig (Wrapper, Pcie);
- ASSERT (Status == AGESA_SUCCESS);
- PcieTopologyApplyLaneMux (Wrapper, Pcie);
- PcieFmPifSetRxDetectPowerMode (Wrapper, Pcie);
- PciePifSetLs2ExitTime (Wrapper, Pcie);
- PcieTopologySelectMasterPll (Wrapper, Pcie);
- PcieTopologyExecuteReconfig (Wrapper, Pcie);
- PcieTopologySetLinkReversal (Wrapper, Pcie);
- PciePifApplyGanging (Wrapper, Pcie);
- PcieFmPhyApplyGanging (Wrapper, Pcie);
- PciePifPllInitForDdi (Wrapper, Pcie);
- PcieTopologyLaneControl (
- DisableLanes,
- PcieUtilGetWrapperLaneBitMap (LANE_TYPE_ALL, LANE_TYPE_PCIE_ALLOCATED, Wrapper, Pcie),
- Wrapper,
- Pcie
- );
- PcieSetDdiOwnPhy (Wrapper, Pcie);
- PciePollPifForCompeletion (Wrapper, Pcie);
- PcieFmAvertClockPickers (Wrapper, Pcie);
- PcieFmConfigureClock (PcieGen1, Wrapper, Pcie);
- PcieCommonCoreInit (Wrapper, Pcie);
- PciePifDisableFifoReset (Wrapper, Pcie);
- return Status;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Pcie Init
- *
- *
- *
- * @param[in] Pcie Pointer to global PCIe configuration
- * @retval AGESA_SUCCESS Topology successfully mapped
- * @retval AGESA_ERROR Topology can not be mapped
- */
-
-AGESA_STATUS
-PcieInit (
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- AGESA_STATUS Status;
- AGESA_STATUS AgesaStatus;
- IDS_HDT_CONSOLE (GNB_TRACE, "PcieInit Enter\n");
- AgesaStatus = AGESA_SUCCESS;
- Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieInitSrbmCallback, NULL, Pcie);
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
- PcieFmPreInit (Pcie);
- Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieInitCallback, NULL, Pcie);
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
- PcieFmSetBootUpVoltage (PcieGen1, Pcie);
- IDS_HDT_CONSOLE (GNB_TRACE, "PcieInit Exit [%x]\n", AgesaStatus);
- return AgesaStatus;
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Per wrapper Pcie Init prior training.
- *
- *
- * @param[in] Wrapper Pointer to wrapper configuration descriptor
- * @param[in] Buffer Pointer buffer
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-AGESA_STATUS
-PciePostInitCallback (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN OUT VOID *Buffer,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- AGESA_STATUS Status;
-
- Status = AGESA_SUCCESS;
- PcieFmConfigureClock (
- PcieUtilGlobalGenCapability (PCIE_PORT_GEN_CAP_BOOT | PCIE_GLOBAL_GEN_CAP_ALL_PORTS, Pcie),
- Wrapper,
- Pcie
- );
- return Status;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Pcie Init
- *
- *
- *
- * @param[in] Pcie Pointer to global PCIe configuration
- * @retval AGESA_SUCCESS Topology successfully mapped
- * @retval AGESA_ERROR Topology can not be mapped
- */
-
-AGESA_STATUS
-PciePostInit (
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- AGESA_STATUS Status;
- AGESA_STATUS AgesaStatus;
-
- IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInit Enter\n");
- AgesaStatus = AGESA_SUCCESS;
- Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_PCIE_WRAPPER, PciePostInitCallback, NULL, Pcie);
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
- PcieFmSetBootUpVoltage (
- PcieUtilGlobalGenCapability (PCIE_PORT_GEN_CAP_BOOT | PCIE_GLOBAL_GEN_CAP_ALL_PORTS, Pcie),
- Pcie
- );
- IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInit Exit [%x]\n", AgesaStatus);
- return AgesaStatus;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInit.h b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInit.h
deleted file mode 100644
index 4e2f83a..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInit.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Pre-training PCIe subsystem initialization routines.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _PCIEINIT_H_
-#define _PCIEINIT_H_
-
-AGESA_STATUS
-PcieInit (
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-AGESA_STATUS
-PciePostInit (
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-VOID
-PciePortsVisibilityControl (
- IN PCIE_PORT_VISIBILITY Control,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-#endif
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtEarlyPost.c b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtEarlyPost.c
deleted file mode 100644
index 7da85e4..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtEarlyPost.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe early post initialization.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "Gnb.h"
-#include "GnbPcie.h"
-#include "PcieInit.h"
-#include "PciePortInit.h"
-#include GNB_MODULE_DEFINITIONS (GnbPcieTrainingV1)
-#include GNB_MODULE_DEFINITIONS (GnbPcieConfig)
-#include "PcieInitAtEarlyPost.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_PCIE_PCIEINITATEARLYPOST_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * PCIe Early Post Init
- *
- *
- *
- * @param[in] StdHeader Standard configuration header
- * @retval AGESA_STATUS
- */
-
-AGESA_STATUS
-PcieInitAtEarly (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_STATUS AgesaStatus;
- AGESA_STATUS Status;
- PCIe_PLATFORM_CONFIG *Pcie;
- IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtEarly Enter\n");
- AgesaStatus = AGESA_SUCCESS;
- Status = PcieLocateConfigurationData (StdHeader, &Pcie);
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
- if (Status != AGESA_FATAL) {
-
- PciePortsVisibilityControl (UnhidePorts, Pcie);
-
- Status = PcieInit (Pcie);
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
- ASSERT (Status == AGESA_SUCCESS);
-
- Status = PciePortInit (Pcie);
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
- ASSERT (Status == AGESA_SUCCESS);
-
- IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PCIE_PHY_CONFIG, Pcie, StdHeader);
-
- Status = PcieTraining (Pcie);
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
- ASSERT (Status == AGESA_SUCCESS);
-
- PciePortsVisibilityControl (HidePorts, Pcie);
- }
- IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtEarly Exit [0x%x]\n", AgesaStatus);
- return AgesaStatus;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtEarlyPost.h b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtEarlyPost.h
deleted file mode 100644
index cd3c738..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtEarlyPost.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe early post initialization.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 38641 $ @e \$Date: 2010-09-27 23:16:17 +0800 (Mon, 27 Sep 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _PCIEINITATEARLYPOST_H_
-#define _PCIEINITATEARLYPOST_H_
-
-AGESA_STATUS
-PcieInitAtEarly (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtEnv.c b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtEnv.c
deleted file mode 100644
index 3bdc2b9..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtEnv.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe late post initialization.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "Gnb.h"
-#include "GnbPcie.h"
-#include "PcieInit.h"
-#include "PcieInitAtPost.h"
-#include "PcieInitAtEnv.h"
-#include "S3SaveState.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_PCIE_PCIEINITATENV_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * PCIe Env Init
- *
- *
- *
- * @param[in] StdHeader Standard configuration header
- * @retval AGESA_STATUS
- */
-AGESA_STATUS
-PcieInitAtEnv (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- S3_SAVE_DISPATCH (StdHeader, S3DispatchGnbPcieLateRestore, 0, NULL);
- return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtEnv.h b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtEnv.h
deleted file mode 100644
index 1e1765f..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtEnv.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe late post initialization.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _PCIEINITATPOST_H_
-#define _PCIEINITATPOST_H_
-
-AGESA_STATUS
-PcieInitAtEnv (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtLatePost.c b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtLatePost.c
deleted file mode 100644
index 2aa4ff9..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtLatePost.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe late post initialization.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "Gnb.h"
-#include "GnbPcie.h"
-#include GNB_MODULE_DEFINITIONS (GnbPcieConfig)
-#include "PcieInit.h"
-#include "PcieLateInit.h"
-#include "PciePortLateInit.h"
-#include "PcieInitAtLatePost.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_PCIE_PCIEINITATLATEPOST_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * PCIe Mid Init
- *
- *
- *
- * @param[in] StdHeader Standard configuration header
- * @retval AGESA_STATUS
- */
-AGESA_STATUS
-PcieInitAtMid (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_STATUS AgesaStatus;
- AGESA_STATUS Status;
- PCIe_PLATFORM_CONFIG *Pcie;
- IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtMid Enter\n");
- AgesaStatus = AGESA_SUCCESS;
- Status = PcieLocateConfigurationData (StdHeader, &Pcie);
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
- if (Status == AGESA_SUCCESS) {
- PciePortsVisibilityControl (UnhidePorts, Pcie);
-
- Status = PciePortLateInit (Pcie);
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
- ASSERT (Status == AGESA_SUCCESS);
-
- Status = PcieLateInit (Pcie);
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
- ASSERT (Status == AGESA_SUCCESS);
-
- PciePortsVisibilityControl (HidePorts, Pcie);
- }
- IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtMid Exit [0x%x]\n", AgesaStatus);
- return AgesaStatus;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtLatePost.h b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtLatePost.h
deleted file mode 100644
index 28768d6..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtLatePost.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe late post initialization.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _PCIEINITATLATEPOST_H_
-#define _PCIEINITATLATEPOST_H_
-
-AGESA_STATUS
-PcieInitAtMid (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtPost.c b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtPost.c
deleted file mode 100644
index 0ee02f4..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtPost.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe late post initialization.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "Gnb.h"
-#include "GnbPcie.h"
-#include "PcieInit.h"
-#include "PciePortInit.h"
-#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1)
-#include GNB_MODULE_DEFINITIONS (GnbPcieConfig)
-#include GNB_MODULE_DEFINITIONS (GnbPcieTrainingV1)
-#include "Filecode.h"
-#define FILECODE PROC_GNB_PCIE_PCIEINITATPOST_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * PCIe Post Init
- *
- *
- *
- * @param[in] StdHeader Standard configuration header
- * @retval AGESA_STATUS
- */
-AGESA_STATUS
-PcieInitAtPost (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_STATUS AgesaStatus;
- AGESA_STATUS Status;
- PCIe_PLATFORM_CONFIG *Pcie;
- IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtPost Enter\n");
- AgesaStatus = AGESA_SUCCESS;
- Status = PcieLocateConfigurationData (StdHeader, &Pcie);
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
- if (Status == AGESA_SUCCESS) {
- PciePortsVisibilityControl (UnhidePorts, Pcie);
-
- Status = PciePostInit (Pcie);
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
- ASSERT (Status == AGESA_SUCCESS);
-
- Status = PciePortPostInit (Pcie);
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
- ASSERT (Status == AGESA_SUCCESS);
-
- Status = PcieTraining (Pcie);
- AGESA_STATUS_UPDATE (Status, AgesaStatus);
- ASSERT (Status == AGESA_SUCCESS);
-
- PciePortsVisibilityControl (HidePorts, Pcie);
- }
- IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtPost Exit [0x%x]\n", AgesaStatus);
- return AgesaStatus;
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * PCIe S3 restore
- *
- *
- *
- * @param[in] StdHeader Standard configuration header
- * @param[in] ContextLength Context Length (not used)
- * @param[in] Context Context pointer (not used)
- */
-VOID
-PcieLateRestoreS3Script (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN UINT16 ContextLength,
- IN VOID* Context
- )
-{
- PcieInitAtPost (StdHeader);
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtPost.h b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtPost.h
deleted file mode 100644
index 8d04b4e..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtPost.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe late post initialization.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _PCIEINITATPOST_H_
-#define _PCIEINITATPOST_H_
-
-AGESA_STATUS
-PcieInitAtPost (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-PcieLateRestoreS3Script (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN UINT16 ContextLength,
- IN VOID* Context
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieLateInit.c b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieLateInit.c
deleted file mode 100644
index a979511..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieLateInit.c
+++ /dev/null
@@ -1,154 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Pre-training PCIe subsystem initialization routines.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "Gnb.h"
-#include "GnbPcie.h"
-#include "PcieLateInit.h"
-#include "PcieFamilyServices.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1)
-#include GNB_MODULE_DEFINITIONS (GnbPcieConfig)
-#include "GnbRegistersON.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_PCIE_PCIELATEINIT_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Power down inactive lanes
- *
- *
- * @param[in] Wrapper Pointer to wrapper config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-
-VOID
-PciePwrPowerDownPllInL1 (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
-
- UINT32 LaneBitmapForPllOffInL1;
- UINT8 PllPowerUpLatency;
- IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownPllInL1 Enter\n");
- PllPowerUpLatency = PcieFmPifGetPllPowerUpLatency (Wrapper, Pcie);
- LaneBitmapForPllOffInL1 = PcieLanesToPowerDownPllInL1 (PllPowerUpLatency, Wrapper, Pcie);
- if (LaneBitmapForPllOffInL1 != 0) {
- PcieFmPifSetPllModeForL1 (LaneBitmapForPllOffInL1, Wrapper, Pcie);
- }
- IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownPllInL1 Exir\n");
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Per wrapper Pcie Late Init.
- *
- *
- * @param[in] Wrapper Pointer to wrapper configuration descriptor
- * @param[in] Buffer Pointer buffer
- * @param[in] Pcie Pointer to global PCIe configuration
- */
-AGESA_STATUS
-PcieLateInitCallback (
- IN PCIe_WRAPPER_CONFIG *Wrapper,
- IN OUT VOID *Buffer,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- PciePwrPowerDownUnusedLanes (Wrapper, Pcie);
- PciePwrPowerDownPllInL1 (Wrapper, Pcie);
- PciePwrClockGating (Wrapper, Pcie);
- PcieLockRegisters (Wrapper, Pcie);
- return AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Pcie Late Init
- *
- * Late PCIe initialization
- *
- * @param[in] Pcie Pointer to global PCIe configuration
- * @retval AGESA_SUCCESS Topology successfully mapped
- * @retval AGESA_ERROR Topology can not be mapped
- */
-
-AGESA_STATUS
-PcieLateInit (
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- AGESA_STATUS Status;
- IDS_HDT_CONSOLE (GNB_TRACE, "PcieLateInit Enter\n");
- Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieLateInitCallback, NULL, Pcie);
- IDS_HDT_CONSOLE (GNB_TRACE, "PcieLateInit Exit [0x%x]\n", Status);
- return Status;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieLateInit.h b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieLateInit.h
deleted file mode 100644
index c5fe656..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieLateInit.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Late initialization routine.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _PCIELATEINIT_H_
-#define _PCIELATEINIT_H_
-
-AGESA_STATUS
-PcieLateInit (
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-#endif
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieMiscLib.c b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieMiscLib.c
deleted file mode 100644
index 97eb370..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieMiscLib.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe utility. Various supporting functions.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 38931 $ @e \$Date: 2010-10-01 15:50:05 -0700 (Fri, 01 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "Gnb.h"
-#include "GnbPcie.h"
-#include "GnbPcieFamServices.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1)
-#include GNB_MODULE_DEFINITIONS (GnbPcieConfig)
-#include "GnbRegistersON.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_PCIE_PCIEMISCLIB_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-typedef struct {
- UINT32 Flags;
- PCIE_LINK_SPEED_CAP LinkSpeedCapability;
-} PCIE_GLOBAL_GEN_CAP_WORKSPACE;
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Training state handling
- *
- *
- *
- * @param[in] Engine Pointer to engine config descriptor
- * @param[in, out] Buffer Indicate if engine in non final state
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-
-VOID
-STATIC
-PcieUtilGlobalGenCapabilityCallback (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN OUT VOID *Buffer,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- PCIE_GLOBAL_GEN_CAP_WORKSPACE *GlobalGenCapability;
- PCIE_LINK_SPEED_CAP LinkSpeedCapability;
- PCIE_HOTPLUG_TYPE HotPlugType;
- UINT32 Flags;
-
- Flags = PCIE_GLOBAL_GEN_CAP_ALL_PORTS;
- GlobalGenCapability = (PCIE_GLOBAL_GEN_CAP_WORKSPACE*) Buffer;
- LinkSpeedCapability = PcieGen1;
- if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
- Flags |= PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS;
- }
- HotPlugType = Engine->Type.Port.PortData.LinkHotplug;
- if ((HotPlugType == HotplugBasic) || (HotPlugType == HotplugServer) || (HotPlugType == HotplugEnhanced)) {
- Flags |= PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS;
- }
- if ((GlobalGenCapability->Flags & Flags) != 0) {
- ASSERT ((GlobalGenCapability->Flags & (PCIE_PORT_GEN_CAP_MAX | PCIE_PORT_GEN_CAP_BOOT)) != 0);
- LinkSpeedCapability = PcieFmGetLinkSpeedCap (GlobalGenCapability->Flags, Engine, Pcie);
- if (GlobalGenCapability->LinkSpeedCapability < LinkSpeedCapability) {
- GlobalGenCapability->LinkSpeedCapability = LinkSpeedCapability;
- }
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Determine global GEN capability
- *
- *
- * @param[in] Flags global GEN capability flags
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-PCIE_LINK_SPEED_CAP
-PcieUtilGlobalGenCapability (
- IN UINT32 Flags,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- PCIE_LINK_SPEED_CAP GlobalCapability;
- PCIE_GLOBAL_GEN_CAP_WORKSPACE GlobalGenCap;
-
- GlobalGenCap.LinkSpeedCapability = PcieGen1;
- GlobalGenCap.Flags = Flags;
- PcieConfigRunProcForAllEngines (
- DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
- PcieUtilGlobalGenCapabilityCallback,
- &GlobalGenCap,
- Pcie
- );
-
- GlobalCapability = GlobalGenCap.LinkSpeedCapability;
-
- return GlobalCapability;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieMiscLib.h b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieMiscLib.h
deleted file mode 100644
index baf4d75..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieMiscLib.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe utility. Various supporting functions.
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 38935 $ @e \$Date: 2010-10-01 18:45:23 -0700 (Fri, 01 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _PCIEMISCLIB_H_
-#define _PCIEMISCLIB_H_
-
-PCIE_LINK_SPEED_CAP
-PcieUtilGlobalGenCapability (
- IN UINT32 Flags,
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PciePortInit.c b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PciePortInit.c
deleted file mode 100644
index 2802ba2..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PciePortInit.c
+++ /dev/null
@@ -1,256 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe port initialization service procedure
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "Gnb.h"
-#include "GnbPcie.h"
-#include "GnbPcieFamServices.h"
-#include "PcieFamilyServices.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1)
-#include GNB_MODULE_DEFINITIONS (GnbPcieConfig)
-#include GNB_MODULE_DEFINITIONS (GnbPcieTrainingV1)
-#include "GnbRegistersON.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_PCIE_PCIEPORTINIT_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-PCIE_PORT_REGISTER_ENTRY PortInitTable [] = {
- {
- DxF0xE4_x02_ADDRESS,
- DxF0xE4_x02_RegsLcAllowTxL1Control_MASK,
- (0x1 << DxF0xE4_x02_RegsLcAllowTxL1Control_OFFSET)
- },
- {
- DxF0xE4_x70_ADDRESS,
- DxF0xE4_x70_RxRcbCplTimeoutMode_MASK,
- (0x1 << DxF0xE4_x70_RxRcbCplTimeoutMode_OFFSET)
- },
- {
- DxF0xE4_xA0_ADDRESS,
- DxF0xE4_xA0_Lc16xClearTxPipe_MASK | DxF0xE4_xA0_LcL1ImmediateAck_MASK,
- (0x3 << DxF0xE4_xA0_Lc16xClearTxPipe_OFFSET) |
- (0x1 << DxF0xE4_xA0_LcL1ImmediateAck_OFFSET)
- },
- {
- DxF0xE4_xA1_ADDRESS,
- DxF0xE4_xA1_LcDontGotoL0sifL1Armed_MASK,
- (0x1 << DxF0xE4_xA1_LcDontGotoL0sifL1Armed_OFFSET)
- },
- {
- DxF0xE4_xA2_ADDRESS,
- DxF0xE4_xA2_LcRenegotiateEn_MASK | DxF0xE4_xA2_LcUpconfigureSupport_MASK,
- (0x1 << DxF0xE4_xA2_LcRenegotiateEn_OFFSET) |
- (0x1 << DxF0xE4_xA2_LcUpconfigureSupport_OFFSET)
- },
- {
- DxF0xE4_xA3_ADDRESS,
- DxF0xE4_xA3_LcXmitFtsBeforeRecovery_MASK,
- (0x1 << DxF0xE4_xA3_LcXmitFtsBeforeRecovery_OFFSET)
- },
- {
- DxF0xE4_xB1_ADDRESS,
- DxF0xE4_xB1_LcDeassertRxEnInL0s_MASK | DxF0xE4_xB1_LcBlockElIdleinL0_MASK,
- (0x1 << DxF0xE4_xB1_LcDeassertRxEnInL0s_OFFSET) |
- (0x1 << DxF0xE4_xB1_LcBlockElIdleinL0_OFFSET)
- }
-};
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Callback to init various features on all active ports
- *
- *
- *
- *
- * @param[in] Engine Pointer to engine config descriptor
- * @param[in, out] Buffer Not used
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-
-VOID
-STATIC
-PciePortInitCallback (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN OUT VOID *Buffer,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- ASSERT (Engine->EngineData.EngineType == PciePortEngine);
- PciePortProgramRegisterTable (PortInitTable, (sizeof (PortInitTable) / sizeof (PCIE_PORT_REGISTER_ENTRY)), Engine, FALSE, Pcie);
- PcieSetLinkSpeedCap (PcieGen1, Engine, Pcie);
- PcieSetLinkWidthCap (Engine, Pcie);
- PcieCompletionTimeout (Engine, Pcie);
- PcieLinkSetSlotCap (Engine, Pcie);
- PcieLinkInitHotplug (Engine, Pcie);
- PcieFmPhyChannelCharacteristic (Engine, Pcie);
- if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) {
- PcieLinkSafeMode (Engine, Pcie);
- }
- if (Engine->Type.Port.PortData.PortPresent == PortDisabled) {
- ASSERT (Engine->Type.Port.IsSB == FALSE);
- PcieTrainingSetPortState (Engine, LinkStateDeviceNotPresent, FALSE, Pcie);
- }
- if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) {
- PcieTrainingSetPortState (Engine, LinkStateTrainingCompleted, FALSE, Pcie);
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Master procedure to init various features on all active ports
- *
- *
- *
- *
- * @param[in] Pcie Pointer to global PCIe configuration
- * @retval AGESA_STATUS
- *
- */
-
-AGESA_STATUS
-PciePortInit (
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- AGESA_STATUS Status;
- Status = AGESA_SUCCESS;
- PcieConfigRunProcForAllEngines (
- DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
- PciePortInitCallback,
- NULL,
- Pcie
- );
- return Status;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Callback to init various features on all ports
- *
- *
- *
- *
- * @param[in] Engine Pointer to engine config descriptor
- * @param[in, out] Buffer Not used
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-
-VOID
-STATIC
-PciePortPostInitCallback (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN OUT VOID *Buffer,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- PCIE_LINK_SPEED_CAP LinkSpeedCapability;
- ASSERT (Engine->EngineData.EngineType == PciePortEngine);
- if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) {
- PcieLinkSafeMode (Engine, Pcie);
- }
- LinkSpeedCapability = PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine, Pcie);
- PcieSetLinkSpeedCap (LinkSpeedCapability, Engine, Pcie);
- if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) && (LinkSpeedCapability > PcieGen1) && !Engine->Type.Port.IsSB) {
- PcieTrainingSetPortState (Engine, LinkStateRetrain, FALSE, Pcie);
- PcieConfigUpdatePortStatus (Engine, 0, INIT_STATUS_PCIE_TRAINING_SUCCESS);
- }
- if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) {
- PcieForceCompliance (Engine, Pcie);
- PcieTrainingSetPortState (Engine, LinkStateResetExit, FALSE, Pcie);
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Master procedure to init various features on all active ports
- *
- *
- *
- *
- * @param[in] Pcie Pointer to global PCIe configuration
- * @retval AGESA_STATUS
- *
- */
-
-AGESA_STATUS
-PciePortPostInit (
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- AGESA_STATUS Status;
- Status = AGESA_SUCCESS;
- PcieConfigRunProcForAllEngines (
- DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
- PciePortPostInitCallback,
- NULL,
- Pcie
- );
- return Status;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PciePortInit.h b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PciePortInit.h
deleted file mode 100644
index 6e65c8d..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PciePortInit.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe port initialization service procedure
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _PCIEPORTINITG_H_
-#define _PCIEPORTINITG_H_
-
-
-AGESA_STATUS
-PciePortInit (
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-AGESA_STATUS
-PciePortPostInit (
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-#endif
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PciePortLateInit.c b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PciePortLateInit.c
deleted file mode 100644
index e3a2b5a..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PciePortLateInit.c
+++ /dev/null
@@ -1,229 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe port initialization service procedure
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "Ids.h"
-#include "Gnb.h"
-#include "GnbPcie.h"
-#include "PcieFamilyServices.h"
-#include "PcieMiscLib.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1)
-#include GNB_MODULE_DEFINITIONS (GnbPcieConfig)
-#include "GnbRegistersON.h"
-#include "Filecode.h"
-#define FILECODE PROC_GNB_PCIE_PCIEPORTLATEINIT_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-PCIE_PORT_REGISTER_ENTRY PortLateInitTable [] = {
- {
- DxF0xE4_xA2_ADDRESS,
- DxF0xE4_xA2_LcDynLanesPwrState_MASK,
- (0x3 << DxF0xE4_xA2_LcDynLanesPwrState_OFFSET)
- },
- {
- DxF0xE4_xC0_ADDRESS,
- DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_MASK,
- (0x1 << DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_OFFSET)
- }
-};
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Enable ASPM
- *
- *
- *
- * @param[in] Engine Pointer to engine config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-
-VOID
-STATIC
-PcieEnableAspm (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- if (Engine->Type.Port.PortData.LinkAspm != AspmDisabled) {
- if (Engine->Type.Port.IsSB != 0) {
- PcieSbLinkAspmControl (Engine, Pcie);
- } else {
- PcieLinkAspmEnable (
- Engine->Type.Port.Address,
- Engine->Type.Port.PortData.LinkAspm,
- GnbLibGetHeader (Pcie)
- );
- }
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Set slot power limit
- *
- *
- *
- * @param[in] Engine Pointer to engine config descriptor
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-
-VOID
-PcieSlotPowerLimit (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- DxF0x6C_STRUCT DxF0x6C;
- GnbLibPciRead (
- Engine->Type.Port.Address.AddressValue | DxF0x6C_ADDRESS,
- AccessWidth32,
- &DxF0x6C.Value,
- GnbLibGetHeader (Pcie)
- );
-
- DxF0x6C.Field.SlotPwrLimitValue = 75;
- DxF0x6C.Field.PhysicalSlotNumber = Engine->Type.Port.Address.Address.Device;
-
- GnbLibPciWrite (
- Engine->Type.Port.Address.AddressValue | DxF0x6C_ADDRESS,
- AccessS3SaveWidth32,
- &DxF0x6C.Value,
- GnbLibGetHeader (Pcie)
- );
- PcieFmEnableSlotPowerLimit (Engine, Pcie);
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Callback to init various features on all active ports
- *
- *
- *
- *
- * @param[in] Engine Pointer to engine config descriptor
- * @param[in, out] Buffer Not used
- * @param[in] Pcie Pointer to global PCIe configuration
- *
- */
-
-VOID
-STATIC
-PciePortLateInitCallback (
- IN PCIe_ENGINE_CONFIG *Engine,
- IN OUT VOID *Buffer,
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- PciePortProgramRegisterTable (PortLateInitTable, (sizeof (PortLateInitTable) / sizeof (PCIE_PORT_REGISTER_ENTRY)), Engine, TRUE, Pcie);
- if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) || Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) {
- PcieSlotPowerLimit (Engine, Pcie);
- }
- PcieEnableAspm (Engine, Pcie);
- if (Engine->Type.Port.IsSB != 0) {
- PcieSbLinkVcEnable (Engine, Pcie);
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Master procedure to init various features on all active ports
- *
- *
- *
- *
- * @param[in] Pcie Pointer to global PCIe configuration
- * @retval AGESA_STATUS
- *
- */
-
-AGESA_STATUS
-PciePortLateInit (
- IN PCIe_PLATFORM_CONFIG *Pcie
- )
-{
- AGESA_STATUS Status;
- PCIE_LINK_SPEED_CAP GlobalSpeedCap;
-
- Status = AGESA_SUCCESS;
- PcieConfigRunProcForAllEngines (
- DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
- PciePortLateInitCallback,
- NULL,
- Pcie
- );
-
- GlobalSpeedCap = PcieUtilGlobalGenCapability (
- PCIE_PORT_GEN_CAP_BOOT | PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS | PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS,
- Pcie
- );
-
- PcieFmSetBootUpVoltage (GlobalSpeedCap, Pcie);
-
- return Status;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PciePortLateInit.h b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PciePortLateInit.h
deleted file mode 100644
index d332155..0000000
--- a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PciePortLateInit.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * PCIe port initialization service procedure
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _PCIEPORTLATEINIT_H_
-#define _PCIEPORTLATEINIT_H_
-
-AGESA_STATUS
-PciePortLateInit (
- IN PCIe_PLATFORM_CONFIG *Pcie
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/HT/Fam10/htNbCoherentFam10.c b/src/vendorcode/amd/agesa/Proc/HT/Fam10/htNbCoherentFam10.c
deleted file mode 100644
index a346e51..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/Fam10/htNbCoherentFam10.c
+++ /dev/null
@@ -1,163 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Coherent Family 10h Routines.
- *
- * Coherent feature Northbridge implementation specific to Family 10h processors.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "htNb.h"
-#include "htNbHardwareFam10.h"
-#include "htNbCoherentFam10.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_FAM10_HTNBCOHERENTFAM10_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Return whether the current configuration exceeds the capability.
- *
- * @HtNbMethod{::F_IS_EXCEEDED_CAPABLE}.
- *
- * Get Node capability and update the minimum supported system capability.
- *
- * @param[in] Node the Node
- * @param[in] State sysMpCap (updated) and NodesDiscovered
- * @param[in] Nb this northbridge
- *
- * @retval TRUE system is not capable of current config.
- * @retval FALSE system is capable of current config.
- */
-BOOLEAN
-Fam10IsExceededCapable (
- IN UINT8 Node,
- IN STATE_DATA *State,
- IN NORTHBRIDGE *Nb
- )
-{
- UINT32 Temp;
- UINT8 MaxNodes;
- PCI_ADDR Reg;
-
- ASSERT (Node < MAX_NODES);
-
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_NB_FUNC_03,
- REG_NB_CAPABILITY_3XE8);
-
- LibAmdPciReadBits (Reg, 18, 16, &Temp, Nb->ConfigHandle);
-
- if (Temp != 0) {
- MaxNodes = (UINT8) (1 << (~Temp & 0x3)); // That is, 1, 2, 4, or 8
- } else {
- MaxNodes = 8;
- }
- if (State->SysMpCap > MaxNodes) {
- State->SysMpCap = MaxNodes;
- }
- // Note since sysMpCap is one based and NodesDiscovered is zero based, equal returns true
- //
- return ((BOOLEAN) (State->SysMpCap <= State->NodesDiscovered));
-}
-
-/**
- * Stop a link, so that it is isolated from a connected device.
- *
- * @HtNbMethod{::F_STOP_LINK}.
- *
- * Use is for fatal incompatible configurations, or for user interface
- * request to power off a link (IgnoreLink, SkipRegang).
- * Set ConnDly to make the power effective at the warm reset.
- * Set XMT and RCV off.
- *
- * @param[in] Node the node to stop a link on.
- * @param[in] Link the link to stop.
- * @param[in] State access to special routine for writing link control register
- * @param[in] Nb this northbridge.
- */
-VOID
-Fam10StopLink (
- IN UINT8 Node,
- IN UINT8 Link,
- IN STATE_DATA *State,
- IN NORTHBRIDGE *Nb
- )
-{
- UINT32 Temp;
- PCI_ADDR Reg;
-
- // Set ConnDly
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_00,
- REG_LINK_GLOBAL_EXT_CONTROL_0x16C);
- Temp = 1;
- LibAmdPciWriteBits (Reg, 8, 8, &Temp, Nb->ConfigHandle);
- // Set TransOff and EndOfChain
- Reg = Nb->MakeLinkBase (Node, Link, Nb);
- Reg.Address.Register += HTHOST_LINK_CONTROL_REG;
- Temp = 3;
- State->HtFeatures->SetHtControlRegisterBits (Reg, 7, 6, &Temp, State);
-}
diff --git a/src/vendorcode/amd/agesa/Proc/HT/Fam10/htNbCoherentFam10.h b/src/vendorcode/amd/agesa/Proc/HT/Fam10/htNbCoherentFam10.h
deleted file mode 100644
index 747ffa3..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/Fam10/htNbCoherentFam10.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Coherent Family 10h specific Routines.
- *
- * Coherent feature Northbridge implementation specific to Family 10h processors.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/**
- * Return whether the current configuration exceeds the capability.
- *
- */
-BOOLEAN
-Fam10IsExceededCapable (
- IN UINT8 Node,
- IN STATE_DATA *State,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Stop a link, so that it is isolated from a connected device.
- */
-VOID
-Fam10StopLink (
- IN UINT8 Node,
- IN UINT8 Link,
- IN STATE_DATA *State,
- IN NORTHBRIDGE *Nb
- );
diff --git a/src/vendorcode/amd/agesa/Proc/HT/Fam10/htNbFam10.c b/src/vendorcode/amd/agesa/Proc/HT/Fam10/htNbFam10.c
deleted file mode 100644
index b3c6702..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/Fam10/htNbFam10.c
+++ /dev/null
@@ -1,362 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Initializers for Family 10h northbridge support.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "OptionsHt.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "htNb.h"
-#include "CommonReturns.h"
-#include "htNbCoherent.h"
-#include "htNbCoherentFam10.h"
-#include "htNbNonCoherent.h"
-#include "htNbNonCoherentFam10.h"
-#include "htNbOptimization.h"
-#include "htNbOptimizationFam10.h"
-#include "htNbSystemFam10.h"
-#include "htNbUtilities.h"
-#include "htNbUtilitiesFam10.h"
-#include "cpuFamRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_FAM10_HTNBFAM10_FILECODE
-
-extern OPTION_HT_CONFIGURATION OptionHtConfiguration;
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/***************************************************************************
- *** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS ***
- ***************************************************************************/
-
-/**
- * Map Northbridge links to package links for Family 10h, Rev D, multi-module.
- *
- * Unfortunately, there is no way to do this except to type the BKDG text into this data structure.
- * Note that there is one entry per package external sublink and each connected internal link.
- */
-CONST PACKAGE_HTLINK_MAP_ITEM ROMDATA HtFam10RevDPackageLinkMap[] =
-{
- {0, 0, 0}, ///< Module zero, link 0: package link 0
- {4, 0, 4}, ///< Module zero, link 4: package link 4
- {0, 1, 1}, ///< Module one, link 0: package link 1
- {4, 1, 5}, ///< Module one, link 4: package link 5
- {3, 0, 2}, ///< Module zero, link 3: package link 2
- {7, 0, 6}, ///< Module zero, link 7: package link 6
- {2, 0, 3}, ///< Module zero, link 2: package link 3
- {1, 1, 7}, ///< Module one, link 1: package link 7
- {1, 0, HT_LIST_MATCH_INTERNAL_LINK_0}, ///< Internal Link
- {5, 0, HT_LIST_MATCH_INTERNAL_LINK_1}, ///< Internal Link
- {6, 0, HT_LIST_MATCH_INTERNAL_LINK_2}, ///< Internal Link
- {2, 1, HT_LIST_MATCH_INTERNAL_LINK_0}, ///< Internal Link
- {6, 1, HT_LIST_MATCH_INTERNAL_LINK_1}, ///< Internal Link
- {5, 1, HT_LIST_MATCH_INTERNAL_LINK_2}, ///< Internal Link
- {HT_LIST_TERMINAL, HT_LIST_TERMINAL, HT_LIST_TERMINAL}, ///< End
-};
-
-/**
- * A default Ignore Link list for rev D to power off the 3rd internal sublink.
- */
-STATIC CONST IGNORE_LINK ROMDATA Fam10RevDIgnoreLinkList[] = {
- HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK_2, POWERED_OFF,
- HT_LIST_TERMINAL
-};
-
-/**
- * Initial construction data for Family 10h North Bridge, default, full features.
- */
-CONST NORTHBRIDGE ROMDATA HtFam10NbDefault =
-{
- 8,
- WriteRoutingTable,
- WriteNodeID,
- ReadDefaultLink,
- EnableRoutingTables,
- DisableRoutingTables,
- VerifyLinkIsCoherent,
- ReadToken,
- WriteToken,
- WriteFullRoutingTable,
- IsIllegalTypeMix,
- Fam10IsExceededCapable,
- Fam10StopLink,
- (PF_HANDLE_SPECIAL_LINK_CASE)CommonReturnFalse,
- HandleSpecialNodeCase,
- ReadSouthbridgeLink,
- VerifyLinkIsNonCoherent,
- Fam10SetConfigAddrMap,
- Fam10NorthBridgeFreqMask,
- GatherLinkFeatures,
- SetLinkRegang,
- SetLinkFrequency,
- SetLinkUnitIdClumping,
- Fam10WriteTrafficDistribution,
- Fam10WriteLinkPairDistribution,
- Fam10BufferOptimizations,
- Fam10GetNumCoresOnNode,
- SetTotalNodesAndCores,
- GetNodeCount,
- LimitNodes,
- ReadTrueLinkFailStatus,
- Fam10GetNextLink,
- GetPackageLink,
- MakeLinkBase,
- Fam10GetModuleInfo,
- Fam10PostMailbox,
- Fam10RetrieveMailbox,
- Fam10GetSocket,
- (PF_GET_ENABLED_COMPUTE_UNITS)CommonReturnZero8,
- (PF_GET_DUALCORE_COMPUTE_UNITS)CommonReturnZero8,
- 0x00000001,
- 0x00000200,
- 18,
- TRUE,
- TRUE,
- ((AMD_FAMILY_10) & ~(AMD_FAMILY_10_HY | AMD_FAMILY_10_PH)),
- NULL,
- 0,
- NULL,
- MakeKey,
- NULL
-};
-
-/**
- * Initial construction data for Family 10h North Bridge, default, full features.
- */
-CONST NORTHBRIDGE ROMDATA HtFam10RevDNbDefault =
-{
- 8,
- WriteRoutingTable,
- WriteNodeID,
- ReadDefaultLink,
- EnableRoutingTables,
- DisableRoutingTables,
- VerifyLinkIsCoherent,
- ReadToken,
- WriteToken,
- WriteFullRoutingTable,
- IsIllegalTypeMix,
- Fam10IsExceededCapable,
- Fam10StopLink,
- (PF_HANDLE_SPECIAL_LINK_CASE)CommonReturnFalse,
- HandleSpecialNodeCase,
- ReadSouthbridgeLink,
- VerifyLinkIsNonCoherent,
- Fam10SetConfigAddrMap,
- Fam10RevDNorthBridgeFreqMask,
- GatherLinkFeatures,
- SetLinkRegang,
- SetLinkFrequency,
- SetLinkUnitIdClumping,
- Fam10WriteTrafficDistribution,
- Fam10WriteLinkPairDistribution,
- Fam10RevDBufferOptimizations,
- Fam10RevDGetNumCoresOnNode,
- SetTotalNodesAndCores,
- GetNodeCount,
- LimitNodes,
- ReadTrueLinkFailStatus,
- Fam10GetNextLink,
- GetPackageLink,
- MakeLinkBase,
- Fam10GetModuleInfo,
- Fam10PostMailbox,
- Fam10RetrieveMailbox,
- Fam10RevDGetSocket,
- (PF_GET_ENABLED_COMPUTE_UNITS)CommonReturnZero8,
- (PF_GET_DUALCORE_COMPUTE_UNITS)CommonReturnZero8,
- 0x00000001,
- 0x00000200,
- 18,
- TRUE,
- TRUE,
- (AMD_FAMILY_10_HY | AMD_FAMILY_10_PH),
- (PACKAGE_HTLINK_MAP) &HtFam10RevDPackageLinkMap,
- 0,
- (IGNORE_LINK *)&Fam10RevDIgnoreLinkList,
- MakeKey,
- NULL
-};
-
-/**
- * Initial construction data for Family 10h North Bridge, for non-coherent only builds.
- */
-CONST NORTHBRIDGE ROMDATA HtFam10NbNonCoherentOnly =
-{
- 8,
- (PF_WRITE_ROUTING_TABLE)CommonVoid,
- (PF_WRITE_NODEID)CommonVoid,
- (PF_READ_DEFAULT_LINK)CommonReturnZero8,
- (PF_ENABLE_ROUTING_TABLES)CommonVoid,
- (PF_DISABLE_ROUTING_TABLES)CommonVoid,
- (PF_VERIFY_LINK_IS_COHERENT)CommonReturnFalse,
- (PF_READ_TOKEN)CommonReturnZero8,
- (PF_WRITE_TOKEN)CommonVoid,
- (PF_WRITE_FULL_ROUTING_TABLE)CommonVoid,
- (PF_IS_ILLEGAL_TYPE_MIX)CommonReturnFalse,
- (PF_IS_EXCEEDED_CAPABLE)CommonReturnFalse,
- (PF_STOP_LINK)CommonVoid,
- (PF_HANDLE_SPECIAL_LINK_CASE)CommonReturnFalse,
- (PF_HANDLE_SPECIAL_NODE_CASE)CommonReturnFalse,
- ReadSouthbridgeLink,
- VerifyLinkIsNonCoherent,
- Fam10SetConfigAddrMap,
- Fam10NorthBridgeFreqMask,
- GatherLinkFeatures,
- SetLinkRegang,
- SetLinkFrequency,
- SetLinkUnitIdClumping,
- (PF_WRITE_TRAFFIC_DISTRIBUTION)CommonVoid,
- (PF_WRITE_LINK_PAIR_DISTRIBUTION)CommonVoid,
- Fam10BufferOptimizations,
- Fam10GetNumCoresOnNode,
- SetTotalNodesAndCores,
- GetNodeCount,
- LimitNodes,
- ReadTrueLinkFailStatus,
- Fam10GetNextLink,
- GetPackageLink,
- MakeLinkBase,
- Fam10GetModuleInfo,
- Fam10PostMailbox,
- Fam10RetrieveMailbox,
- Fam10GetSocket,
- (PF_GET_ENABLED_COMPUTE_UNITS)CommonReturnZero8,
- (PF_GET_DUALCORE_COMPUTE_UNITS)CommonReturnZero8,
- 0x00000001,
- 0x00000200,
- 18,
- TRUE,
- TRUE,
- ((AMD_FAMILY_10) & ~(AMD_FAMILY_10_HY | AMD_FAMILY_10_PH)),
- NULL,
- 0,
- NULL,
- MakeKey,
- NULL
-};
-
-/**
- * Initial construction data for Family 10h North Bridge, for RevD compatible non-coherent only builds.
- */
-CONST NORTHBRIDGE ROMDATA HtFam10RevDNbNonCoherentOnly =
-{
- 8,
- (PF_WRITE_ROUTING_TABLE)CommonVoid,
- (PF_WRITE_NODEID)CommonVoid,
- (PF_READ_DEFAULT_LINK)CommonReturnZero8,
- (PF_ENABLE_ROUTING_TABLES)CommonVoid,
- (PF_DISABLE_ROUTING_TABLES)CommonVoid,
- (PF_VERIFY_LINK_IS_COHERENT)CommonReturnFalse,
- (PF_READ_TOKEN)CommonReturnZero8,
- (PF_WRITE_TOKEN)CommonVoid,
- (PF_WRITE_FULL_ROUTING_TABLE)CommonVoid,
- (PF_IS_ILLEGAL_TYPE_MIX)CommonReturnFalse,
- (PF_IS_EXCEEDED_CAPABLE)CommonReturnFalse,
- (PF_STOP_LINK)CommonVoid,
- (PF_HANDLE_SPECIAL_LINK_CASE)CommonReturnFalse,
- (PF_HANDLE_SPECIAL_NODE_CASE)CommonReturnFalse,
- ReadSouthbridgeLink,
- VerifyLinkIsNonCoherent,
- Fam10SetConfigAddrMap,
- Fam10RevDNorthBridgeFreqMask,
- GatherLinkFeatures,
- SetLinkRegang,
- SetLinkFrequency,
- SetLinkUnitIdClumping,
- (PF_WRITE_TRAFFIC_DISTRIBUTION)CommonVoid,
- (PF_WRITE_LINK_PAIR_DISTRIBUTION)CommonVoid,
- Fam10BufferOptimizations,
- Fam10RevDGetNumCoresOnNode,
- SetTotalNodesAndCores,
- GetNodeCount,
- LimitNodes,
- ReadTrueLinkFailStatus,
- Fam10GetNextLink,
- GetPackageLink,
- MakeLinkBase,
- Fam10GetModuleInfo,
- Fam10PostMailbox,
- Fam10RetrieveMailbox,
- Fam10GetSocket,
- (PF_GET_ENABLED_COMPUTE_UNITS)CommonReturnZero8,
- (PF_GET_DUALCORE_COMPUTE_UNITS)CommonReturnZero8,
- 0x00000001,
- 0x00000200,
- 18,
- TRUE,
- TRUE,
- (AMD_FAMILY_10_HY | AMD_FAMILY_10_PH),
- NULL,
- 0,
- NULL,
- MakeKey,
- NULL
-};
diff --git a/src/vendorcode/amd/agesa/Proc/HT/Fam10/htNbNonCoherentFam10.c b/src/vendorcode/amd/agesa/Proc/HT/Fam10/htNbNonCoherentFam10.c
deleted file mode 100644
index 18d6da3..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/Fam10/htNbNonCoherentFam10.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Northbridge non-coherent support for Family 10h processors.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "htNb.h"
-#include "htNbHardwareFam10.h"
-#include "htNbNonCoherentFam10.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_FAM10_HTNBNONCOHERENTFAM10_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Enable config access to a non-coherent chain for the given bus range.
- *
- * @HtNbMethod{::F_SET_CONFIG_ADDR_MAP}
- *
- * @param[in] ConfigMapIndex the map entry to set
- * @param[in] SecBus The secondary bus number to use
- * @param[in] SubBus The subordinate bus number to use
- * @param[in] TargetNode The Node that shall be the recipient of the traffic
- * @param[in] TargetLink The Link that shall be the recipient of the traffic
- * @param[in] State our global state
- * @param[in] Nb this northbridge
- */
-VOID
-Fam10SetConfigAddrMap (
- IN UINT8 ConfigMapIndex,
- IN UINT8 SecBus,
- IN UINT8 SubBus,
- IN UINT8 TargetNode,
- IN UINT8 TargetLink,
- IN STATE_DATA *State,
- IN NORTHBRIDGE *Nb
- )
-{
- UINT8 CurNode;
- PCI_ADDR Reg;
- UINT32 Temp;
-
- Reg = Nb->MakeLinkBase (TargetNode, TargetLink, Nb);
-
- ASSERT (SecBus <= SubBus);
- ASSERT (TargetNode <= State->NodesDiscovered);
- ASSERT (TargetLink < Nb->MaxLinks);
- Temp = SecBus;
- Reg.Address.Register += HTHOST_ISOC_REG;
- LibAmdPciWriteBits (Reg, 15, 8, &Temp, Nb->ConfigHandle);
-
- Temp = ((UINT32)SubBus << 24) + ((UINT32)SecBus << 16) + ((UINT32)TargetLink << 8) +
- ((UINT32)TargetNode << 4) + (UINT32)3;
- for (CurNode = 0; CurNode < (State->NodesDiscovered + 1); CurNode++) {
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (CurNode),
- MakePciBusFromNode (CurNode),
- MakePciDeviceFromNode (CurNode),
- CPU_ADDR_FUNC_01,
- REG_ADDR_CONFIG_MAP0_1XE0 + (4 * ConfigMapIndex));
- LibAmdPciWrite (AccessWidth32, Reg, &Temp, Nb->ConfigHandle);
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/HT/Fam10/htNbNonCoherentFam10.h b/src/vendorcode/amd/agesa/Proc/HT/Fam10/htNbNonCoherentFam10.h
deleted file mode 100644
index 3eb1350..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/Fam10/htNbNonCoherentFam10.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Northbridge non-coherent support for Family 10h processors.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/**
- * Enable config access to a non-coherent chain for the given bus range.
- *
- */
-VOID
-Fam10SetConfigAddrMap (
- IN UINT8 ConfigMapIndex,
- IN UINT8 SecBus,
- IN UINT8 SubBus,
- IN UINT8 TargetNode,
- IN UINT8 TargetLink,
- IN STATE_DATA *State,
- IN NORTHBRIDGE *Nb
- );
diff --git a/src/vendorcode/amd/agesa/Proc/HT/Fam10/htNbOptimizationFam10.c b/src/vendorcode/amd/agesa/Proc/HT/Fam10/htNbOptimizationFam10.c
deleted file mode 100644
index 2ae1676..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/Fam10/htNbOptimizationFam10.c
+++ /dev/null
@@ -1,222 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Link optimization support specific to family 10h processors.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "htInterface.h"
-#include "htNb.h"
-#include "htNbOptimizationFam10.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_FAM10_HTNBOPTIMIZATIONFAM10_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Northbridge specific Frequency limit.
- *
- * @HtNbMethod{::F_NORTH_BRIDGE_FREQ_MASK}
- *
- * Return a mask that eliminates HT frequencies that cannot be used due to a slow
- * northbridge frequency.
- *
- * @param[in] Node Result could (later) be for a specific Node
- * @param[in] Interface Access to non-HT support functions.
- * @param[in] PlatformConfig Platform profile/build option config structure.
- * @param[in] Nb this northbridge
- *
- * @return Frequency mask
- */
-UINT32
-Fam10NorthBridgeFreqMask (
- IN UINT8 Node,
- IN HT_INTERFACE *Interface,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN NORTHBRIDGE *Nb
- )
-{
- UINT32 NbCoreFreq;
- UINT32 Supported;
-
- ASSERT (Node < MAX_NODES);
- ASSERT (Interface != NULL);
- // The interface to power management will return a system based result.
- // So we only need to call it once, not on every link. Save the answer,
- // and check to see if we can use a saved answer on subsequent calls.
- //
- if (Nb->CoreFrequency == 0) {
- NbCoreFreq = Interface->GetMinNbCoreFreq (PlatformConfig, Nb->ConfigHandle);
- NbCoreFreq = (NbCoreFreq / 100);
- ASSERT (NbCoreFreq != 0);
- Nb->CoreFrequency = NbCoreFreq;
- } else {
- NbCoreFreq = Nb->CoreFrequency;
- }
-
- //
- // NbCoreFreq is minimum northbridge speed in hundreds of MHz.
- // HT can not go faster than the minimum speed of the northbridge.
- //
- if ((NbCoreFreq >= 6) && (NbCoreFreq <= 26)) {
- // Convert frequency to bit and all less significant bits,
- // by setting next power of 2 and subtracting 1.
- //
- Supported = ((UINT32)1 << ((NbCoreFreq >> 1) + 2)) - 1;
- } else if ((NbCoreFreq > 26) && (NbCoreFreq <= 32)) {
- // Convert frequency to bit and all less significant bits,
- // by setting next power of 2 and subtracting 1, noting that
- // next power of two is two greater than non-extended frequencies
- // (because of the register break).
- //
- Supported = ((UINT32)1 << ((NbCoreFreq >> 1) + 4)) - 1;
- } else if (NbCoreFreq > 32) {
- Supported = HT_FREQUENCY_LIMIT_MAX;
- } else if (NbCoreFreq == 4) {
- // unlikely cases, but include as a defensive measure, also avoid trick above
- Supported = HT_FREQUENCY_LIMIT_400M;
- } else if (NbCoreFreq == 2) {
- Supported = HT_FREQUENCY_LIMIT_200M;
- } else {
- ASSERT (FALSE);
- Supported = HT_FREQUENCY_LIMIT_200M;
- }
-
- return (Supported);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Northbridge specific Frequency limit.
- *
- * @HtNbMethod{::F_NORTH_BRIDGE_FREQ_MASK}
- *
- * Return a mask that eliminates HT frequencies that cannot be used due to a slow
- * northbridge frequency.
- *
- * @param[in] Node Result could (later) be for a specific Node
- * @param[in] Interface Access to non-HT support functions.
- * @param[in] PlatformConfig Platform profile/build option config structure.
- * @param[in] Nb this northbridge
- *
- * @return Frequency mask
- */
-UINT32
-Fam10RevDNorthBridgeFreqMask (
- IN UINT8 Node,
- IN HT_INTERFACE *Interface,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN NORTHBRIDGE *Nb
- )
-{
- UINT32 NbCoreFreq;
- UINT32 Supported;
-
- ASSERT (Node < MAX_NODES);
- ASSERT (Interface != NULL);
- // The interface to power management will return a system based result.
- // So we only need to call it once, not on every link. Save the answer,
- // and check to see if we can use a saved answer on subsequent calls.
- //
- if (Nb->CoreFrequency == 0) {
- NbCoreFreq = Interface->GetMinNbCoreFreq (PlatformConfig, Nb->ConfigHandle);
- NbCoreFreq = (NbCoreFreq / 100);
- ASSERT (NbCoreFreq != 0);
- Nb->CoreFrequency = NbCoreFreq;
- } else {
- NbCoreFreq = Nb->CoreFrequency;
- }
-
- // For Rev D, the Ht frequency can go twice the Nb COF, as long as it's HT3.
- // (side note: we are not speculatively upgrading HT1 at 6 .. 10 to HT3,
- // to avoid complicated recovery if the final speed is HT1.)
- if (NbCoreFreq > 10) {
- NbCoreFreq = NbCoreFreq * 2;
- }
- //
- // NbCoreFreq is minimum northbridge speed in hundreds of MHz.
- // HT can not go faster than the minimum speed of the northbridge.
- //
- if ((NbCoreFreq >= 6) && (NbCoreFreq <= 26)) {
- // Convert frequency to bit and all less significant bits,
- // by setting next power of 2 and subtracting 1.
- //
- Supported = ((UINT32)1 << ((NbCoreFreq >> 1) + 2)) - 1;
- } else if ((NbCoreFreq > 26) && (NbCoreFreq <= 32)) {
- // Convert frequency to bit and all less significant bits,
- // by setting next power of 2 and subtracting 1, noting that
- // next power of two is two greater than non-extended frequencies
- // (because of the register break).
- //
- Supported = ((UINT32)1 << ((NbCoreFreq >> 1) + 4)) - 1;
- } else if (NbCoreFreq > 32) {
- Supported = HT_FREQUENCY_LIMIT_MAX;
- } else if (NbCoreFreq == 4) {
- // unlikely cases, but include as a defensive measure, also avoid trick above
- Supported = HT_FREQUENCY_LIMIT_400M;
- } else if (NbCoreFreq == 2) {
- Supported = HT_FREQUENCY_LIMIT_200M;
- } else {
- ASSERT (FALSE);
- Supported = HT_FREQUENCY_LIMIT_200M;
- }
-
- return (Supported);
-}
diff --git a/src/vendorcode/amd/agesa/Proc/HT/Fam10/htNbOptimizationFam10.h b/src/vendorcode/amd/agesa/Proc/HT/Fam10/htNbOptimizationFam10.h
deleted file mode 100644
index 4442141..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/Fam10/htNbOptimizationFam10.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Link optimization support specific to family 10h processors.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-/**
- * Northbridge specific Frequency limit.
- *
- */
-UINT32
-Fam10NorthBridgeFreqMask (
- IN UINT8 Node,
- IN HT_INTERFACE *Interface,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Northbridge specific Frequency limit.
- *
- */
-UINT32
-Fam10RevDNorthBridgeFreqMask (
- IN UINT8 Node,
- IN HT_INTERFACE *Interface,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN NORTHBRIDGE *Nb
- );
diff --git a/src/vendorcode/amd/agesa/Proc/HT/Fam10/htNbSystemFam10.c b/src/vendorcode/amd/agesa/Proc/HT/Fam10/htNbSystemFam10.c
deleted file mode 100644
index 5fee550..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/Fam10/htNbSystemFam10.c
+++ /dev/null
@@ -1,402 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * System Tuning Family 10h specific routines
- *
- * Support for Traffic Distribution and buffer tunings which
- * can not be done in a register table.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "htInterface.h"
-#include "htNb.h"
-#include "htNbHardwareFam10.h"
-#include "htNbSystemFam10.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_FAM10_HTNBSYSTEMFAM10_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-/**
- * Register Fields for an individual link pair.
- */
-typedef struct {
- UINT32 Enable:1; ///< Enable distribution on this pair.
- UINT32 Asymmetric:1; ///< Links are different widths.
- UINT32 MasterSelect:3; ///< The master link.
- UINT32 AlternateSelect:3; ///< The alternate link.
-} PAIR_SELECT_FIELDS;
-
-/**
- * Register access union for ::PAIR_SELECT_FIELDS.
- */
-typedef union {
- UINT32 Value; ///< access as a 32 bit value or register.
- PAIR_SELECT_FIELDS Fields; ///< access individual fields.
-} PAIR_SELECT;
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/***************************************************************************
- *** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS ***
- ***************************************************************************/
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Set the traffic distribution register for the Links provided.
- *
- * @HtNbMethod{::F_WRITE_TRAFFIC_DISTRIBUTION}
- *
- * @param[in] Links01 coherent Links from Node 0 to 1
- * @param[in] Links10 coherent Links from Node 1 to 0
- * @param[in] Nb this northbridge
- */
-VOID
-Fam10WriteTrafficDistribution (
- IN UINT32 Links01,
- IN UINT32 Links10,
- IN NORTHBRIDGE *Nb
- )
-{
- UINT32 Temp;
- PCI_ADDR TrafficDistReg;
-
- TrafficDistReg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (0),
- MakePciBusFromNode (0),
- MakePciDeviceFromNode (0),
- CPU_HTNB_FUNC_00,
- REG_HT_TRAFFIC_DIST_0X164);
-
- // Node 0
- // DstLnk
- LibAmdPciWriteBits (TrafficDistReg, 23, 16, &Links01, Nb->ConfigHandle);
- // DstNode = 1, cHTPrbDistEn = 1, cHTRspDistEn = 1, cHTReqDistEn = 1
- Temp = 0x0107;
- LibAmdPciWriteBits (TrafficDistReg, 15, 0, &Temp, Nb->ConfigHandle);
-
- TrafficDistReg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (1),
- MakePciBusFromNode (1),
- MakePciDeviceFromNode (1),
- CPU_HTNB_FUNC_00,
- REG_HT_TRAFFIC_DIST_0X164);
-
- // Node 1
- // DstLnk
- LibAmdPciWriteBits (TrafficDistReg, 23, 16, &Links10, Nb->ConfigHandle);
- // DstNode = 0, cHTPrbDistEn = 1, cHTRspDistEn = 1, cHTReqDistEn = 1
- Temp = 0x0007;
- LibAmdPciWriteBits (TrafficDistReg, 15, 0, &Temp, Nb->ConfigHandle);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Write a link pair to the link pair distribution and fixups.
- *
- * @HtNbMethod{::F_WRITE_LINK_PAIR_DISTRIBUTION}
- *
- * Set the links as a pair using the link pair index provided. Set asymmetric attribute as
- * provided. If the Master Link is not currently used as the route, fixup the routes for all
- * nodes which specify the alternate link.
- *
- * @param[in] Node Set the pair on this node
- * @param[in] ConnectedNode The Node to which this link pair directly connects.
- * @param[in] Pair Using this pair set in the register
- * @param[in] Asymmetric True if different widths
- * @param[in] MasterLink Set this as the master link and in the route
- * @param[in] AlternateLink Set this as the alternate link
- * @param[in] Nb this northbridge
- *
- */
-VOID
-Fam10WriteLinkPairDistribution (
- IN UINT8 Node,
- IN UINT8 ConnectedNode,
- IN UINT8 Pair,
- IN BOOLEAN Asymmetric,
- IN UINT8 MasterLink,
- IN UINT8 AlternateLink,
- IN NORTHBRIDGE *Nb
- )
-{
- PCI_ADDR Reg;
- UINT32 CurrentRoute;
- UINT32 MasterRoute;
- UINT32 AlternateRoute;
- PAIR_SELECT Selection;
- UINT32 RouteIndex;
-
- ASSERT ((Node < MAX_NODES) && (ConnectedNode < MAX_NODES));
- ASSERT (Pair < MAX_LINK_PAIRS);
- ASSERT (MasterLink < Nb->MaxLinks);
- ASSERT (AlternateLink < Nb->MaxLinks);
-
- // Make the master link the route for all routes to or through NodeB, by replacing all occurrences of
- // Alternate link with Master link. If routing used the master link, no update is necessary.
- MasterRoute = (((1 << Nb->BroadcastSelfBit) | Nb->SelfRouteResponseMask | Nb->SelfRouteRequestMask) << (MasterLink + 1));
- AlternateRoute = (((1 << Nb->BroadcastSelfBit) | Nb->SelfRouteResponseMask | Nb->SelfRouteRequestMask) << (AlternateLink + 1));
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_00,
- REG_ROUTE0_0X40);
- for (RouteIndex = 0; RouteIndex < MAX_NODES; RouteIndex++) {
- Reg.Address.Register = REG_ROUTE0_0X40 + (RouteIndex * 4);
- LibAmdPciReadBits (Reg, 31, 0, &CurrentRoute, Nb->ConfigHandle);
- if ((CurrentRoute & AlternateRoute) != 0) {
- // Since Master and Alternate are redundant, the route must use one or the other but not both.
- ASSERT ((CurrentRoute & MasterRoute) == 0);
- // Set the master route for Request, Response or Broadcast only if the alternate was used for that case.
- // Example, use of a link as a broadcast link is typically not the same route register as its use for Request, Response.
- CurrentRoute = ((CurrentRoute & ~AlternateRoute) |
- ((((CurrentRoute & AlternateRoute) >> (AlternateLink + 1)) << (MasterLink + 1)) & MasterRoute));
- LibAmdPciWriteBits (Reg, 31, 0, &CurrentRoute, Nb->ConfigHandle);
- }
- }
-
- // Set the Link Pair and Enable it
- Selection.Fields.Enable = 1;
- Selection.Fields.Asymmetric = Asymmetric;
- Selection.Fields.MasterSelect = MasterLink;
- Selection.Fields.AlternateSelect = AlternateLink;
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_00,
- REG_HT_LINK_PAIR_DIST_0X1E0);
- LibAmdPciWriteBits (
- Reg,
- ((PAIR_SELECT_OFFSET * (Pair + 1)) - 1),
- (PAIR_SELECT_OFFSET * Pair),
- &Selection.Value,
- Nb->ConfigHandle
- );
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Family 10h specific tunings.
- *
- * @HtNbMethod{::F_BUFFER_OPTIMIZATIONS}
- *
- * Buffer tunings are inherently northbridge specific. Check for specific configs
- * which require adjustments and apply any standard workarounds to this Node.
- *
- * @param[in] Node the Node to tune
- * @param[in] State global state
- * @param[in] Nb this northbridge
- */
-VOID
-Fam10BufferOptimizations (
- IN UINT8 Node,
- IN STATE_DATA *State,
- IN NORTHBRIDGE *Nb
- )
-{
- UINT32 Temp;
- PCI_ADDR currentPtr;
- PCI_ADDR GangedReg;
- UINT8 i;
-
- ASSERT (Node < MAX_NODES);
-
- //
- // Link to XCS Token Count Tuning
- //
- // For each active Link that we reganged (so this unfortunately can't go into the PCI reg
- // table), we have to switch the Link to XCS Token Counts to the ganged state.
- // We do this here for the non - uma case, which is to write the values that would have
- // been power on defaults if the Link was ganged at cold reset.
- //
- for (i = 0; i < (State->TotalLinks * 2); i++) {
- if (((*State->PortList)[i].NodeID == Node) && ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU)) {
- // If the Link is greater than 4, this is a subLink 1, so it is not reganged.
- if ((*State->PortList)[i].Link < 4) {
- currentPtr.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_NB_FUNC_03,
- REG_NB_LINK_XCS_TOKEN0_3X148 + (4 * (*State->PortList)[i].Link)
- );
- if ((*State->PortList)[i].SelRegang) {
- // Handle all the regang Token count adjustments
-
- // SubLink 0: [Probe0tok] = 2 [Rsp0tok] = 2 [PReq0tok] = 2 [Req0tok] = 2
- Temp = 0xAA;
- LibAmdPciWriteBits (currentPtr, 7, 0, &Temp, Nb->ConfigHandle);
- // SubLink 1: [Probe1tok] = 0 [Rsp1tok] = 0 [PReq1tok] = 0 [Req1tok] = 0
- Temp = 0;
- LibAmdPciWriteBits (currentPtr, 23, 16, &Temp, Nb->ConfigHandle);
- // [FreeTok] = 3
- Temp = 3;
- LibAmdPciWriteBits (currentPtr, 15, 14, &Temp, Nb->ConfigHandle);
-
- } else {
- // Read the regang bit in hardware
- GangedReg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode ((*State->PortList)[i].NodeID),
- MakePciBusFromNode ((*State->PortList)[i].NodeID),
- MakePciDeviceFromNode ((*State->PortList)[i].NodeID),
- CPU_HTNB_FUNC_00,
- REG_HT_LINK_EXT_CONTROL0_0X170 + (4 * (*State->PortList)[i].Link));
- LibAmdPciReadBits (GangedReg, 0, 0, &Temp, Nb->ConfigHandle);
- if (Temp == 1) {
- // handle a minor adjustment for strapped ganged Links. If SelRegang is false we
- // didn't do the regang, so if the bit is on then it's hardware strapped.
- //
-
- // [FreeTok] = 3
- Temp = 3;
- LibAmdPciWriteBits (currentPtr, 15, 14, &Temp, Nb->ConfigHandle);
- }
- }
- }
- }
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Family 10h specific tunings.
- *
- * @HtNbMethod{::F_BUFFER_OPTIMIZATIONS}
- *
- * Buffer tunings are inherently northbridge specific. Check for specific configs
- * which require adjustments and apply any standard workarounds to this Node.
- *
- * @param[in] Node the Node to tune
- * @param[in] State global state
- * @param[in] Nb this northbridge
- */
-VOID
-Fam10RevDBufferOptimizations (
- IN UINT8 Node,
- IN STATE_DATA *State,
- IN NORTHBRIDGE *Nb
- )
-{
- UINT32 Temp;
- PCI_ADDR Reg;
- UINT8 i;
- FINAL_LINK_STATE FinalLinkState;
- UINT32 WidthIn;
- UINT32 WidthOut;
-
- ASSERT (Node < MAX_NODES);
-
- //
- // Internal link fixup.
- // When powering off internal link 2, a performance optimization may be possible where its buffers
- // can be made available to the external paired sublink. If the conditions are met, do the fix up here.
- //
- for (i = 0; i < (State->TotalLinks * 2); i++) {
- if (((*State->PortList)[i].NodeID == Node) && ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU)) {
- // Is this a sublink 0 paired with internal link 2?
- if (((*State->PortList)[i].Link < 4) &&
- (Nb->GetPackageLink (Node, ((*State->PortList)[i].Link + 4), Nb) == HT_LIST_MATCH_INTERNAL_LINK_2)) {
- FinalLinkState = State->HtInterface->GetIgnoreLink (Node, ((*State->PortList)[i].Link + 4), Nb->DefaultIgnoreLinkList, State);
- // Are we ignoring the internal link 2 with Power Off?
- if (FinalLinkState == POWERED_OFF) {
- // Read the regang bit in hardware.
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_00,
- REG_HT_LINK_EXT_CONTROL0_0X170 + (4 * (*State->PortList)[i].Link));
- LibAmdPciReadBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
- // If it's already ganged, skip to the width fix up.
- if (Temp == 0) {
- // Clear EndOfChain / XmitOff on internal sublink
- Reg = Nb->MakeLinkBase (Node, ((*State->PortList)[i].Link + 4), Nb);
- Reg.Address.Register += HTHOST_LINK_CONTROL_REG;
- Temp = 0;
- State->HtFeatures->SetHtControlRegisterBits (Reg, 7, 6, &Temp, State);
-
- // Gang the link
- Nb->SetLinkRegang (Node, (*State->PortList)[i].Link, Nb);
- }
-
- // Set InLnSt = PHY_OFF in register table.
- // Set sublink 0 widths to 8 bits
- if ((*State->PortList)[i].SelWidthOut > 8) {
- (*State->PortList)[i].SelWidthOut = 8;
- }
- if ((*State->PortList)[i].SelWidthIn > 8) {
- (*State->PortList)[i].SelWidthIn = 8;
- }
- WidthOut = State->HtFeatures->ConvertWidthToBits ((*State->PortList)[i].SelWidthOut);
- WidthIn = State->HtFeatures->ConvertWidthToBits ((*State->PortList)[i].SelWidthIn);
- Temp = (WidthIn & 7) | ((WidthOut & 7) << 4);
- Reg = Nb->MakeLinkBase (Node, (*State->PortList)[i].Link, Nb);
- Reg.Address.Register += HTHOST_LINK_CONTROL_REG;
- State->HtFeatures->SetHtControlRegisterBits (Reg, 31, 24, &Temp, State);
- }
- }
- }
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/HT/Fam10/htNbSystemFam10.h b/src/vendorcode/amd/agesa/Proc/HT/Fam10/htNbSystemFam10.h
deleted file mode 100644
index 50b7820..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/Fam10/htNbSystemFam10.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * System Tuning Family 10h specific routines
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/**
- * Set the traffic distribution register for the Links provided.
- *
- */
-VOID
-Fam10WriteTrafficDistribution (
- IN UINT32 Links01,
- IN UINT32 Links10,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Write a link pair to the link pair distribution and fixups.
- *
- */
-VOID
-Fam10WriteLinkPairDistribution (
- IN UINT8 Node,
- IN UINT8 ConnectedNode,
- IN UINT8 Pair,
- IN BOOLEAN Asymmetric,
- IN UINT8 MasterLink,
- IN UINT8 AlternateLink,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Family 10h specific tunings.
- *
- */
-VOID
-Fam10BufferOptimizations (
- IN UINT8 Node,
- IN STATE_DATA *State,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Family 10h Rev D specific tunings.
- *
- */
-VOID
-Fam10RevDBufferOptimizations (
- IN UINT8 Node,
- IN STATE_DATA *State,
- IN NORTHBRIDGE *Nb
- );
diff --git a/src/vendorcode/amd/agesa/Proc/HT/Fam10/htNbUtilitiesFam10.c b/src/vendorcode/amd/agesa/Proc/HT/Fam10/htNbUtilitiesFam10.c
deleted file mode 100644
index 5a089e1..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/Fam10/htNbUtilitiesFam10.c
+++ /dev/null
@@ -1,445 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Northbridge utility routines.
- *
- * These routines are needed for support of more than one feature area.
- * Collect them in this file so build options don't remove them.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "htNb.h"
-#include "htNbHardwareFam10.h"
-#include "htNbUtilitiesFam10.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_FAM10_HTNBUTILITIESFAM10_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Return the number of cores (1 based count) on Node.
- *
- * @HtNbMethod{::F_GET_NUM_CORES_ON_NODE}
- *
- * @param[in] Node the Node that will be examined
- * @param[in] Nb this northbridge
- *
- * @return the number of cores
- */
-UINT8
-Fam10GetNumCoresOnNode (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- )
-{
- UINT32 Result;
- UINT32 Leveling;
- UINT32 Cores;
- UINT8 i;
- PCI_ADDR Reg;
-
- ASSERT ((Node < MAX_NODES));
- // Read CmpCap
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_NB_FUNC_03,
- REG_NB_CAPABILITY_3XE8);
-
- LibAmdPciReadBits (Reg, 13, 12, &Cores, Nb->ConfigHandle);
-
- // Support Downcoring
- Result = Cores;
- Cores++;
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_NB_FUNC_03,
- REG_NB_DOWNCORE_3X190);
- LibAmdPciReadBits (Reg, 3, 0, &Leveling, Nb->ConfigHandle);
- for (i = 0; i < Cores; i++) {
- if ((Leveling & ((UINT32) 1 << i)) != 0) {
- Result--;
- }
- }
- return (UINT8) (Result + 1);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Return the number of cores (1 based count) on Node.
- *
- * @HtNbMethod{::F_GET_NUM_CORES_ON_NODE}.
- *
- * @param[in] Node the Node that will be examined
- * @param[in] Nb this northbridge
- *
- * @return the number of cores
- */
-UINT8
-Fam10RevDGetNumCoresOnNode (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- )
-{
- UINT32 Result;
- UINT32 Leveling;
- UINT32 Cores;
- UINT32 Cores2;
- UINT8 i;
- PCI_ADDR Reg;
-
- ASSERT ((Node < MAX_NODES));
- // Read CmpCap
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_NB_FUNC_03,
- REG_NB_CAPABILITY_3XE8);
-
- LibAmdPciReadBits (Reg, 13, 12, &Cores, Nb->ConfigHandle);
- LibAmdPciReadBits (Reg, 15, 15, &Cores2, Nb->ConfigHandle);
- Cores = Cores + (Cores2 << 2);
-
- // Support Downcoring
- Result = Cores;
- Cores++;
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_NB_FUNC_03,
- REG_NB_DOWNCORE_3X190);
- LibAmdPciReadBits (Reg, 5, 0, &Leveling, Nb->ConfigHandle);
- for (i = 0; i < Cores; i++) {
- if ((Leveling & ((UINT32) 1 << i)) != 0) {
- Result--;
- }
- }
- return (UINT8) (Result + 1);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get the next link for iterating over the links on a node in the correct order.
- *
- * @HtNbMethod{::F_GET_NEXT_LINK}
- *
- * Family 10h specific implementation use the Internal Link field in
- * the northbridge to prioritize internal links in the order.
- *
- * @param[in] Node The node on which to iterate links.
- * @param[in,out] Link IN: the current iteration context, OUT: the next link.
- * @param[in] Nb This Northbridge, access to config pointer.
- *
- * @retval LinkIteratorExternal The current Link is an external link.
- * @retval LinkIteratorInternal The current Link is an internal link.
- * @retval LinkIteratorEnd There is no next link (Link is back to BEGIN).
- *
- */
-LINK_ITERATOR_STATUS
-Fam10GetNextLink (
- IN UINT8 Node,
- IN OUT UINT8 *Link,
- IN NORTHBRIDGE *Nb
- )
-{
- PCI_ADDR Reg;
- UINT32 InternalLinks;
- UINT32 ExternalLinks;
- UINT32 HigherLinks;
- BOOLEAN IsInternalLink;
- LINK_ITERATOR_STATUS Status;
-
- ASSERT ((Node < MAX_NODES));
- ASSERT ((*Link < Nb->MaxLinks) || (*Link == LINK_ITERATOR_BEGIN));
- InternalLinks = 0;
- ExternalLinks = 0;
-
- // Read IntLnkRoute from the Link Initialization Status register.
- // (Note that this register field is not reserved prior to rev D, but should be zero.)
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_00,
- REG_HT_LINK_INITIALIZATION_0X1A0);
-
- LibAmdPciReadBits (Reg, 23, 16, &InternalLinks, Nb->ConfigHandle);
- // The external links are all possible links which are not Internal
- ExternalLinks = (((1 << Nb->MaxLinks) - 1) ^ InternalLinks);
- // Can't have no possible links!
- ASSERT ((ExternalLinks != 0) || (InternalLinks != 0));
-
-
- if (*Link == LINK_ITERATOR_BEGIN) {
- // If the request is for the first link (BEGIN), get it
- if (InternalLinks != 0) {
- *Link = LibAmdBitScanForward (InternalLinks);
- Status = LinkIteratorInternal;
- } else {
- *Link = LibAmdBitScanForward (ExternalLinks);
- Status = LinkIteratorExternal;
- }
- } else {
- // If the iterator is not at the beginning, search for the next Link starting from the
- // current link.
- HigherLinks = InternalLinks & ~((1 << (*Link + 1)) - 1);
- IsInternalLink = (BOOLEAN) ((InternalLinks & (1 << *Link)) != 0);
- if (IsInternalLink && (HigherLinks != 0)) {
- // We are still on internal links and there are more to do.
- *Link = LibAmdBitScanForward (HigherLinks);
- Status = LinkIteratorInternal;
- } else {
- if (IsInternalLink) {
- // We are transitioning now from internal to external, so get the first external link
- HigherLinks = ExternalLinks;
- } else {
- // We are already iterating over external links, so get the next one
- HigherLinks = ExternalLinks & ~((1 << (*Link + 1)) - 1);
- }
- if (HigherLinks != 0) {
- *Link = LibAmdBitScanForward (HigherLinks);
- Status = LinkIteratorExternal;
- } else {
- // The end of all links
- *Link = LINK_ITERATOR_BEGIN;
- Status = LinkIteratorEnd;
- }
- }
- }
- return Status;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get Info about Module Type of this northbridge
- *
- * @HtNbMethod{::F_GET_MODULE_INFO}
- *
- * Provide the Processor module type, single or multi, and the node's module id.
- *
- * @param[in] Node the Node
- * @param[out] ModuleType 0 for Single, 1 for Multi
- * @param[out] Module The module number of this node (0 if Single)
- * @param[in] Nb this northbridge
- *
- */
-VOID
-Fam10GetModuleInfo (
- IN UINT8 Node,
- OUT UINT8 *ModuleType,
- OUT UINT8 *Module,
- IN NORTHBRIDGE *Nb
- )
-{
- PCI_ADDR Reg;
- UINT32 MultNodeCpu;
- UINT32 IntNodeNum;
-
- ASSERT (Node < MAX_NODES);
-
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_NB_FUNC_03,
- REG_NB_CAPABILITY_3XE8);
- LibAmdPciReadBits (Reg, 29, 29, &MultNodeCpu, Nb->ConfigHandle);
- LibAmdPciReadBits (Reg, 31, 30, &IntNodeNum, Nb->ConfigHandle);
-
- *ModuleType = (UINT8) MultNodeCpu;
- *Module = (UINT8) IntNodeNum;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register.
- *
- * @HtNbMethod{::F_GET_SOCKET}
- *
- * The hardware socket naming method is not available for Family 10h prior to rev D.
- *
- * @param[in] Node The node for which we want the socket id.
- * @param[in] TempNode The temporary node id route where the node can be accessed.
- * @param[in] Nb Our Northbridge.
- *
- * @return The Socket Id
- */
-UINT8
-Fam10GetSocket (
- IN UINT8 Node,
- IN UINT8 TempNode,
- IN NORTHBRIDGE *Nb
- )
-{
- ASSERT ((Node < MAX_NODES));
- ASSERT (TempNode < MAX_NODES);
- ASSERT (Nb != NULL);
- return (Node);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register.
- *
- * @HtNbMethod{::F_GET_SOCKET}
- *
- * The Socket Id is strapped to the Sbi Control Register, F3X1E4[6:4]SbiAddr.
- *
- * @param[in] Node The node for which we want the socket id.
- * @param[in] TempNode The temporary node id route where the node can be accessed.
- * @param[in] Nb Our Northbridge.
- *
- * @return The Socket Id
- */
-UINT8
-Fam10RevDGetSocket (
- IN UINT8 Node,
- IN UINT8 TempNode,
- IN NORTHBRIDGE *Nb
- )
-{
- UINT32 Socket;
- PCI_ADDR Reg;
-
- ASSERT ((TempNode < MAX_NODES));
- ASSERT ((Node < MAX_NODES));
- // Read SbiAddr
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (TempNode),
- MakePciBusFromNode (TempNode),
- MakePciDeviceFromNode (TempNode),
- CPU_NB_FUNC_03,
- REG_NB_SBI_CONTROL_3X1E4);
- LibAmdPciReadBits (Reg, 6, 4, &Socket, Nb->ConfigHandle);
- return ((UINT8) Socket);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Post info to AP cores via a mailbox.
- *
- * @HtNbMethod{::F_POST_MAILBOX}
- *
- * Use the link MCA counter register as a PCI -> MSR mailbox, for info such as node id,
- * and module info.
- *
- * @param[in] Node the Node
- * @param[in] ApMailboxes The info to post
- * @param[in] Nb this northbridge
- *
- */
-VOID
-Fam10PostMailbox (
- IN UINT8 Node,
- IN AP_MAILBOXES ApMailboxes,
- IN NORTHBRIDGE *Nb
- )
-{
- PCI_ADDR Reg;
-
- ASSERT (Node < MAX_NODES);
-
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_NB_FUNC_03,
- REG_NB_MCA_LINK_THRESHOLD_3X168);
- LibAmdPciWriteBits (Reg, 11, 0, &ApMailboxes.ApMailInfo.Info, Nb->ConfigHandle);
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_NB_FUNC_03,
- REG_NB_MCA_L3_THRESHOLD_3X170);
- LibAmdPciWriteBits (Reg, 11, 0, &ApMailboxes.ApMailExtInfo.Info, Nb->ConfigHandle);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Retrieve info from a node's mailbox.
- *
- * @HtNbMethod{::F_RETRIEVE_MAILBOX}
- *
- * Use the link MCA counter register as a PCI -> MSR mailbox, for info such as node id,
- * and module info.
- *
- * @param[in] Node the Node
- * @param[in] Nb this northbridge
- *
- * @return The ap mailbox info
- *
- */
-AP_MAIL_INFO
-Fam10RetrieveMailbox (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- )
-{
- PCI_ADDR Reg;
- AP_MAIL_INFO ApMailInfo;
-
- ASSERT (Node < MAX_NODES);
-
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_NB_FUNC_03,
- REG_NB_MCA_LINK_THRESHOLD_3X168);
- LibAmdPciReadBits (Reg, 11, 0, &ApMailInfo.Info, Nb->ConfigHandle);
- return ApMailInfo;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/HT/Fam10/htNbUtilitiesFam10.h b/src/vendorcode/amd/agesa/Proc/HT/Fam10/htNbUtilitiesFam10.h
deleted file mode 100644
index 5b3e561..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/Fam10/htNbUtilitiesFam10.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Northbridge utility routines.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/**
- * Return the number of cores (1 based count) on Node.
- *
- */
-UINT8
-Fam10GetNumCoresOnNode (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Return the number of cores (1 based count) on Node.
- *
- */
-UINT8
-Fam10RevDGetNumCoresOnNode (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Get the next link for iterating over the links on a node in the correct order.
- *
- */
-LINK_ITERATOR_STATUS
-Fam10GetNextLink (
- IN UINT8 Node,
- IN OUT UINT8 *Link,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Get Info about Module Type of this northbridge
- *
- */
-VOID
-Fam10GetModuleInfo (
- IN UINT8 Node,
- OUT UINT8 *ModuleType,
- OUT UINT8 *Module,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register.
- *
- */
-UINT8
-Fam10GetSocket (
- IN UINT8 Node,
- IN UINT8 TempNode,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register.
- *
- */
-UINT8
-Fam10RevDGetSocket (
- IN UINT8 Node,
- IN UINT8 TempNode,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Post info to AP cores via a mailbox.
- *
- */
-VOID
-Fam10PostMailbox (
- IN UINT8 Node,
- IN AP_MAILBOXES ApMailboxes,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Retrieve info from a node's mailbox.
- *
- */
-AP_MAIL_INFO
-Fam10RetrieveMailbox (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- );
diff --git a/src/vendorcode/amd/agesa/Proc/HT/Fam14/htNbFam14.c b/src/vendorcode/amd/agesa/Proc/HT/Fam14/htNbFam14.c
deleted file mode 100644
index 97f4e0d..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/Fam14/htNbFam14.c
+++ /dev/null
@@ -1,147 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * The initializer for Family 14h northbridge support.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "OptionsHt.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "htNb.h"
-#include "CommonReturns.h"
-#include "htNbUtilitiesFam14.h"
-#include "cpuFamRegisters.h"
-#include "Filecode.h"
-
-#define FILECODE PROC_HT_FAM14_HTNBFAM14_FILECODE
-
-extern OPTION_HT_CONFIGURATION OptionHtConfiguration;
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/***************************************************************************
- *** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS ***
- ***************************************************************************/
-
-
-/**
- * Initial construction data for no HT Northbridge.
- */
-CONST NORTHBRIDGE ROMDATA HtFam14Nb =
-{
- 1,
- (PF_WRITE_ROUTING_TABLE)CommonVoid,
- (PF_WRITE_NODEID)CommonVoid,
- (PF_READ_DEFAULT_LINK)CommonReturnZero8,
- (PF_ENABLE_ROUTING_TABLES)CommonVoid,
- (PF_DISABLE_ROUTING_TABLES)CommonVoid,
- (PF_VERIFY_LINK_IS_COHERENT)CommonReturnFalse,
- (PF_READ_TOKEN)CommonReturnZero8,
- (PF_WRITE_TOKEN)CommonVoid,
- (PF_WRITE_FULL_ROUTING_TABLE)CommonVoid,
- (PF_IS_ILLEGAL_TYPE_MIX)CommonReturnFalse,
- (PF_IS_EXCEEDED_CAPABLE)CommonReturnFalse,
- (PF_STOP_LINK)CommonVoid,
- (PF_HANDLE_SPECIAL_LINK_CASE)CommonReturnFalse,
- (PF_HANDLE_SPECIAL_NODE_CASE)CommonReturnFalse,
- (PF_READ_SB_LINK)CommonReturnZero8,
- (PF_VERIFY_LINK_IS_NON_COHERENT)CommonReturnFalse,
- (PF_SET_CONFIG_ADDR_MAP)CommonVoid,
- (PF_NORTH_BRIDGE_FREQ_MASK)CommonReturnZero32,
- (PF_GATHER_LINK_FEATURES)CommonVoid,
- (PF_SET_LINK_REGANG)CommonVoid,
- (PF_SET_LINK_FREQUENCY)CommonVoid,
- (PF_SET_LINK_UNITID_CLUMPING)CommonVoid,
- (PF_WRITE_TRAFFIC_DISTRIBUTION)CommonVoid,
- (PF_WRITE_LINK_PAIR_DISTRIBUTION)CommonVoid,
- (PF_BUFFER_OPTIMIZATIONS)CommonVoid,
- Fam14GetNumCoresOnNode,
- (PF_SET_TOTAL_NODES_AND_CORES)CommonVoid,
- Fam14GetNodeCount,
- (PF_LIMIT_NODES)CommonVoid,
- (PF_READ_TRUE_LINK_FAIL_STATUS)CommonReturnFalse,
- (PF_GET_NEXT_LINK)CommonReturnZero32,
- (PF_GET_PACKAGE_LINK)CommonReturnZero8,
- (PF_MAKE_LINK_BASE)CommonReturnZero32,
- (PF_GET_MODULE_INFO)CommonVoid,
- (PF_POST_MAILBOX)CommonVoid,
- //(PF_RETRIEVE_MAILBOX)CommonReturnZero32,
- Fam14RetrieveMailbox,
- (PF_GET_SOCKET)CommonReturnZero8,
- (PF_GET_ENABLED_COMPUTE_UNITS)CommonReturnZero8,
- (PF_GET_DUALCORE_COMPUTE_UNITS)CommonReturnZero8,
- 0,
- 0,
- 0,
- TRUE,
- TRUE,
- AMD_FAMILY_14,
- NULL,
- 0,
- NULL,
- (PF_MAKE_KEY)CommonReturnZero64,
- NULL
-};
diff --git a/src/vendorcode/amd/agesa/Proc/HT/Fam14/htNbUtilitiesFam14.c b/src/vendorcode/amd/agesa/Proc/HT/Fam14/htNbUtilitiesFam14.c
deleted file mode 100644
index b780b0b..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/Fam14/htNbUtilitiesFam14.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Northbridge utility routines.
- *
- * These routines are needed for support of more than one feature area.
- * Collect them in this file so build options don't remove them.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "htNb.h"
-#include "htNbHardwareFam10.h"
-#include "htNbUtilitiesFam14.h"
-#include "Filecode.h"
-#define FILECODE PROC_HT_FAM14_HTNBUTILITIESFAM14_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Return the number of cores (1 based count) on Node.
- *
- * @HtNbMethod{::F_GET_NUM_CORES_ON_NODE}
- *
- * @param[in] Node the Node that will be examined
- * @param[in] Nb this northbridge
- *
- * @return the number of cores
- */
-UINT8
-Fam14GetNumCoresOnNode (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- )
-{
- UINT32 Cores;
- PCI_ADDR Reg;
-
- ASSERT ((Node < MAX_NODES));
- // Read CmpCap
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_NB_FUNC_03,
- REG_NB_CAPABILITY_3XE8);
-
- LibAmdPciReadBits (Reg, 13, 12, &Cores, Nb->ConfigHandle);
-
- return (UINT8) (Cores + 1);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get the Count (1 based) of Nodes in the system.
- *
- * @HtNbMethod{::F_GET_NODE_COUNT}
- *
- * This is intended to support AP Core HT init, since the Discovery State data is not
- * available (State->NodesDiscovered), there needs to be this way to find the number
- * of Nodes, which is just one.
- *
- * @param[in] Nb this northbridge
- *
- * @return The number of nodes
- */
-UINT8
-Fam14GetNodeCount (
- IN NORTHBRIDGE *Nb
- )
-{
- ASSERT (Nb != NULL);
- return (1);
-}
-
-AP_MAIL_INFO
-Fam14RetrieveMailbox (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- )
-{
- AP_MAIL_INFO NodeApMailBox;
- ASSERT (Nb != NULL);
- NodeApMailBox.Info = 0;
- return NodeApMailBox;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/HT/Fam14/htNbUtilitiesFam14.h b/src/vendorcode/amd/agesa/Proc/HT/Fam14/htNbUtilitiesFam14.h
deleted file mode 100644
index 533a79c..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/Fam14/htNbUtilitiesFam14.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Northbridge utility routines.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _HT_NB_UTILITIES_FAM14_H_
-#define _HT_NB_UTILITIES_FAM14_H_
-
-/**
- * Return the number of cores (1 based count) on Node.
- *
- */
-UINT8
-Fam14GetNumCoresOnNode (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- );
-
-UINT8
-Fam14GetNodeCount (
- IN NORTHBRIDGE *Nb
- );
-
-AP_MAIL_INFO
-Fam14RetrieveMailbox (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- );
-#endif // _HT_NB_UTILITIES_FAM14_H_
diff --git a/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatDynamicDiscovery.c b/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatDynamicDiscovery.c
deleted file mode 100644
index d6f21aa..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatDynamicDiscovery.c
+++ /dev/null
@@ -1,783 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Coherent Discovery Routines.
- *
- * Contains routines for discovery, along with Temporary routing.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "htInterface.h"
-#include "htNotify.h"
-#include "htNb.h"
-#include "htFeatDynamicDiscovery.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_FEATURES_HTFEATDYNAMICDISCOVERY_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define LOGICAL_PROCESSOR_NONE 0xFF
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-/**
- * Status result from exploring for a new node on a link.
- */
-typedef enum {
- ExploreNodeStatusNew, ///< A new node was discovered
- ExploreNodeStatusGood, ///< A new link to an already known node was discovered
- ExploreNodeStatusStop, ///< Discovery must halt now.
- ExploreNodeStatusIgnore, ///< A new node was ignored on purpose.
- ExploreNodeStatusMax ///< Use for bounds check and limit only
-} EXPLORE_NODE_STATUS;
-
-/**
- * Save all the information needed about a node at its discovery.
- *
- * When we can access the node at a known temporary route, read everything needed
- * to do node to socket mapping, post to ap mailbox at later times.
- */
-typedef struct {
- UINT8 LogicalProcessor; ///< Independent of Node,Socket group nodes into logical
- ///< processors based on discovery.
- UINT8 CurrentNode; ///< The node from which discovery occurred.
- UINT8 CurrentLink; ///< The link on that node which we explored.
- UINT8 PackageLink; ///< The package level link corresponding to CurrentLink.
- UINT8 CurrentModuleType; ///< The current node's module type, Single or Multiple.
- UINT8 CurrentModule; ///< This current node's module id.
- UINT8 HardwareSocket; ///< Save the hardware socket strap (for hardware socket method).
- UINT8 NewModuleType; ///< The new node's module type, Single or Multiple.
- UINT8 NewModule; ///< The new node's module id.
-} NEW_NODE_SAVED_INFO_ITEM;
-
-/**
- * A "no info" initializer for saved new node info.
- */
-STATIC CONST NEW_NODE_SAVED_INFO_ITEM ROMDATA NoInfoSavedYet =
-{
- LOGICAL_PROCESSOR_NONE, 0, 0, 0, 0, 0, 0, 0
-};
-
-/**
- * A list of all the new node info, indexed by each new node's nodeid.
- */
-typedef NEW_NODE_SAVED_INFO_ITEM (*NEW_NODE_SAVED_INFO_LIST) [MAX_NODES];
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/***************************************************************************
- *** GENERIC HYPERTRANSPORT DISCOVERY CODE ***
- ***************************************************************************/
-
-/*-----------------------------------------------------------------------------------*/
-/**
- * Ensure a request / response route from target Node to bsp.
- *
- * Since target Node is always a predecessor of actual target Node, each Node gets a
- * route to actual target on the Link that goes to target. The routing produced by
- * this routine is adequate for config access during discovery, but NOT for coherency.
- *
- * @param[in] TargetNode the path to actual target goes through target
- * @param[in] ActualTarget the ultimate target being routed to
- * @param[in] State our global state, port config info
- *
- */
-VOID
-STATIC
-routeFromBSP (
- IN UINT8 TargetNode,
- IN UINT8 ActualTarget,
- IN STATE_DATA *State
- )
-{
- UINT8 PredecessorNode;
- UINT8 PredecessorLink;
- UINT8 CurrentPair;
-
- if (TargetNode == 0) {
- return; // BSP has no predecessor, stop
- }
-
- // Search for the Link that connects TargetNode to its predecessor
- CurrentPair = 0;
- while ((*State->PortList)[CurrentPair*2 + 1].NodeID != TargetNode) {
- CurrentPair++;
- ASSERT (CurrentPair < State->TotalLinks);
- }
-
- PredecessorNode = (*State->PortList)[ (CurrentPair * 2)].NodeID;
- PredecessorLink = (*State->PortList)[ (CurrentPair * 2)].Link;
-
- // Recursively call self to ensure the route from the BSP to the Predecessor
- // Node is established
- routeFromBSP (PredecessorNode, ActualTarget, State);
-
- State->Nb->WriteRoutingTable (PredecessorNode, ActualTarget, PredecessorLink, State->Nb);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Test Compatibility of a new node, and handle failure.
- *
- * Make the compatibility test call for the northbridge.
- * If the new node is incompatible, force 1P. Notify the event.
- * Additionally, invoke the northbridge stop link method, to
- * implement isolation of the BSP from any incompatible node.
- *
- * @param[in] CurrentNode The node we are exploring from
- * @param[in] CurrentLink The Link on that node to explore.
- * @param[in] State Access to Northbridge interface.
- *
- * @retval TRUE Check is Ok
- * @retval FALSE Check failed and is handled
- */
-BOOLEAN
-STATIC
-CheckCompatible (
- IN UINT8 CurrentNode,
- IN UINT8 CurrentLink,
- IN STATE_DATA *State
- )
-{
- UINT8 NodeToKill;
- BOOLEAN Result;
-
- Result = TRUE;
-
- // Check the northbridge of the Node we just found, to make sure it is compatible
- // before doing anything else to it.
- //
- if (State->Nb->IsIllegalTypeMix ((CurrentNode + 1), State->Nb)) {
- IDS_ERROR_TRAP;
-
- // Notify BIOS of event
- NotifyFatalCohProcessorTypeMix (
- CurrentNode,
- CurrentLink,
- State->NodesDiscovered,
- State
- );
-
- // If Node is not compatible, force boot to 1P
- // If they are not compatible stop cHT init and:
- // 1. Disable all cHT Links on the BSP
- // 2. Configure the BSP routing tables as a UP.
- // 3. Notify main BIOS.
- //
- State->NodesDiscovered = 0;
- State->TotalLinks = 0;
- // Abandon our coherent Link data structure. At this point there may
- // be coherent Links on the BSP that are not yet in the portList, and
- // we have to turn them off anyway. So depend on the hardware to tell us.
- //
- for (CurrentLink = 0; CurrentLink < State->Nb->MaxLinks; CurrentLink++) {
- // Stop all Links which are connected, coherent, and ready
- if (State->Nb->VerifyLinkIsCoherent (0, CurrentLink, State->Nb)) {
- State->Nb->StopLink (0, CurrentLink, State, State->Nb);
- }
- }
-
- for (NodeToKill = 0; NodeToKill < MAX_NODES; NodeToKill++) {
- State->Nb->WriteFullRoutingTable (0, NodeToKill, ROUTE_TO_SELF, ROUTE_TO_SELF, 0, State->Nb);
- }
-
- State->HtInterface->CleanMapsAfterError (State);
-
- // End Coherent Discovery
- Result = FALSE;
- }
- return Result;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Check the system MP capability with a new node and handle any failure.
- *
- * Invoke the northbridge MP capability check. If it fails, notify the event and force
- * 1P. Should not need to stop links on the BSP.
- *
- * @param[in] CurrentNode The node we are exploring from
- * @param[in] CurrentLink The Link on that node to explore.
- * @param[in] State Access to Northbridge interface.
- *
- * @retval TRUE Check is Ok
- * @retval FALSE Check Failed and is handled
- */
-BOOLEAN
-STATIC
-CheckCapable (
- IN UINT8 CurrentNode,
- IN UINT8 CurrentLink,
- IN STATE_DATA *State
- )
-{
- UINT8 NodeToKill;
- BOOLEAN Result;
-
- Result = TRUE;
-
- // Check the capability of northbridges against the currently known configuration
- if (State->Nb->IsExceededCapable ((CurrentNode + 1), State, State->Nb)) {
- IDS_ERROR_TRAP;
- // Notify BIOS of event
- NotifyFatalCohMpCapMismatch (
- CurrentNode,
- CurrentLink,
- State->SysMpCap,
- State->NodesDiscovered,
- State
- );
-
- State->NodesDiscovered = 0;
- State->TotalLinks = 0;
-
- for (NodeToKill = 0; NodeToKill < MAX_NODES; NodeToKill++) {
- State->Nb->WriteFullRoutingTable (0, NodeToKill, ROUTE_TO_SELF, ROUTE_TO_SELF, 0, State->Nb);
- }
-
- State->HtInterface->CleanMapsAfterError (State);
-
- // End Coherent Discovery
- Result = FALSE;
- }
- return Result;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Make all the tests needed to determine if a link should be added to the system data structure.
- *
- * The link should be added to the system data structure if it is:
- * - not being Ignored on this boot
- * - not having a hard failure
- * - coherent and connected
- * - not already in the system data structure
- * - not subject to some special handling case.
- * .
- *
- * @param[in] CurrentNode The node we are exploring from
- * @param[in] CurrentLink The Link on that node to explore.
- * @param[in] State Access to Northbridge interface.
- *
- * @retval FALSE This link should not be added.
- * @retval TRUE This link should explored and added to the system.
- */
-BOOLEAN
-STATIC
-IsLinkToAdd (
- IN UINT8 CurrentNode,
- IN UINT8 CurrentLink,
- IN STATE_DATA *State
- )
-{
- BOOLEAN Linkfound;
- UINTN Port;
- FINAL_LINK_STATE FinalLinkState;
- BOOLEAN Result;
-
- Result = FALSE;
-
- FinalLinkState = State->HtInterface->GetIgnoreLink (CurrentNode, CurrentLink, State->Nb->DefaultIgnoreLinkList, State);
- if ((FinalLinkState != MATCHED) && (FinalLinkState != POWERED_OFF)) {
- if (!State->Nb->ReadTrueLinkFailStatus (CurrentNode, CurrentLink, State, State->Nb)) {
- // Make sure that the Link is connected, coherent, and ready
- if (State->Nb->VerifyLinkIsCoherent (CurrentNode, CurrentLink, State->Nb)) {
- // Test to see if the CurrentLink has already been explored
- Linkfound = FALSE;
- for (Port = 0; Port < State->TotalLinks; Port++) {
- if ((((*State->PortList)[ (Port * 2 + 1)].NodeID == CurrentNode) &&
- ((*State->PortList)[ (Port * 2 + 1)].Link == CurrentLink)) ||
- (((*State->PortList)[ (Port * 2)].NodeID == CurrentNode) &&
- ((*State->PortList)[ (Port * 2)].Link == CurrentLink))) {
- Linkfound = TRUE;
- break;
- }
- }
- if (!Linkfound) {
- if (!State->Nb->HandleSpecialLinkCase (CurrentNode, CurrentLink, State, State->Nb)) {
- Result = TRUE;
- }
- }
- }
- }
- } else {
- if (FinalLinkState == POWERED_OFF) {
- State->Nb->StopLink (CurrentNode, CurrentLink, State, State->Nb);
- }
- }
- return Result;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Explore for a new node over a link, handling whatever is found.
- *
- * Open a temporary route over a link on the current node.
- * Make checks for compatibility and capability in the proper sequence.
- * If the node found is new, set a token to it, so it will be recognized in the
- * future, and notify an event for finding a new node.
- * If the node is already found (token is set), just return status.
- *
- * @param[in] CurrentNode The node we are exploring from
- * @param[in] CurrentLink The Link on that node to explore.
- * @param[in] LogicalProcessor The processor to update in the maps.
- * @param[in,out] NewNodeSavedInfo The saved info for nodes in that processor.
- * @param[in] State Access to Northbridge interface.
- *
- * @retval ExploreNodeStatusNew A new node was found
- * @retval ExploreNodeStatusGood This is a good link to an already known node
- * @retval ExploreNodeStatusStop Stop Coherent Discovery
- */
-EXPLORE_NODE_STATUS
-STATIC
-ExploreNode (
- IN UINT8 CurrentNode,
- IN UINT8 CurrentLink,
- IN UINT8 LogicalProcessor,
- IN OUT NEW_NODE_SAVED_INFO_LIST NewNodeSavedInfo,
- IN STATE_DATA *State
- )
-{
- UINT8 Token;
- EXPLORE_NODE_STATUS Status;
-
- // Modify CurrentNode's routing table to use CurrentLink to send
- // traffic to CurrentNode + 1
- //
- State->Nb->WriteRoutingTable (CurrentNode, (CurrentNode + 1), CurrentLink, State->Nb);
- if (!State->Nb->HandleSpecialNodeCase ((CurrentNode + 1), CurrentLink, State, State->Nb)) {
- if (CheckCompatible (CurrentNode, CurrentLink, State)) {
- // Read Token from Current + 1
- Token = State->Nb->ReadToken ((CurrentNode + 1), State->Nb);
- ASSERT (Token <= State->NodesDiscovered);
- if (Token == 0) {
- State->NodesDiscovered++;
- ASSERT (State->NodesDiscovered < MAX_NODES);
- if (CheckCapable (CurrentNode, CurrentLink, State)) {
- Token = State->NodesDiscovered;
- State->Nb->WriteToken ((CurrentNode + 1), Token, State->Nb);
- // Fill in Saved New Node info for the discovered node.
- // We do this so we don't have to keep a temporary route open to it.
- // So we save everything that might be needed to set the socket and node
- // maps for either the software or hardware method.
- //
- (*NewNodeSavedInfo)[Token].LogicalProcessor = LogicalProcessor;
- (*NewNodeSavedInfo)[Token].CurrentNode = CurrentNode;
- (*NewNodeSavedInfo)[Token].CurrentLink = CurrentLink;
- (*NewNodeSavedInfo)[Token].PackageLink = State->Nb->GetPackageLink (CurrentNode, CurrentLink, State->Nb);
- (*NewNodeSavedInfo)[Token].HardwareSocket = State->Nb->GetSocket (Token, (CurrentNode + 1), State->Nb);
- State->Nb->GetModuleInfo (
- CurrentNode,
- &((*NewNodeSavedInfo)[Token].CurrentModuleType),
- &((*NewNodeSavedInfo)[Token].CurrentModule),
- State->Nb
- );
- State->Nb->GetModuleInfo (
- (CurrentNode + 1),
- &((*NewNodeSavedInfo)[Token].NewModuleType),
- &((*NewNodeSavedInfo)[Token].NewModule),
- State->Nb
- );
-
- // Notify BIOS with info
- NotifyInfoCohNodeDiscovered (
- CurrentNode,
- CurrentLink,
- Token,
- (CurrentNode + 1),
- State
- );
- Status = ExploreNodeStatusNew;
- } else {
- // Failed Capable
- Status = ExploreNodeStatusStop;
- }
- } else {
- // Not a new node, token already set
- Status = ExploreNodeStatusGood;
- }
- } else {
- // Failed Compatible
- Status = ExploreNodeStatusStop;
- }
- } else {
- // Ignore this node
- Status = ExploreNodeStatusIgnore;
- }
-
- return Status;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Process all the saved new node info for the current processor.
- *
- * When all nodes in the processor have been discovered, we can process all the saved
- * info about the nodes. We add each node to the socket and node maps.
- *
- * @param[in] LogicalProcessor The processor to update in the maps.
- * @param[in] NewNodeSavedInfo The saved info for nodes in that processor.
- * @param[in] State Our system representation.
- */
-VOID
-STATIC
-ProcessSavedNodeInfo (
- IN UINT8 LogicalProcessor,
- IN NEW_NODE_SAVED_INFO_LIST NewNodeSavedInfo,
- IN STATE_DATA *State
- )
-{
- UINT8 NewNode;
- UINT8 HardwareSocket;
-
- // Can't have more processors than nodes, just more (or equal) nodes than processors.
- ASSERT (LogicalProcessor <= (State->NodesDiscovered));
- HardwareSocket = 0xFF;
- // Find the Hardware Socket value to use (if we are using the hardware socket naming method).
- // The new nodes are the ones in this processor, so find the one that is module 0.
- for (NewNode = 0; NewNode < (State->NodesDiscovered + 1); NewNode++) {
- if (((*NewNodeSavedInfo)[NewNode].LogicalProcessor == LogicalProcessor) &&
- ((*NewNodeSavedInfo)[NewNode].NewModule == 0)) {
- HardwareSocket = (*NewNodeSavedInfo)[NewNode].HardwareSocket;
- break;
- }
- }
- // We must have found a result, however, the hardware socket value doesn't have to be correct
- // unless we are using the hardware socket naming method. Northbridge code should return the
- // node number for the hardware socket if hardware socket strapping is not supported (i.e. no sbi).
- ASSERT (HardwareSocket != 0xFF);
-
- // Set the node to socket maps for this processor. Node zero is always handled specially,
- // so skip it in this loop.
- for (NewNode = 1; NewNode < (State->NodesDiscovered + 1); NewNode++) {
- if ((*NewNodeSavedInfo)[NewNode].LogicalProcessor == LogicalProcessor) {
- // For the currently discovered logical processor, update node to socket
- // map for all the processor's nodes.
- State->HtInterface->SetNodeToSocketMap (
- (*NewNodeSavedInfo)[NewNode].CurrentNode,
- (*NewNodeSavedInfo)[NewNode].CurrentModule,
- (*NewNodeSavedInfo)[NewNode].PackageLink,
- NewNode,
- HardwareSocket,
- (*NewNodeSavedInfo)[NewNode].NewModule,
- State);
- }
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Create and add a new link to the system data structure.
- *
- * Add the two port list data structures, source first, initializing
- * the two node ids and the link values. The node id of the remote
- * node is its token value. Also, update the adjacency matrix and
- * node degree table.
- *
- * @param[in] CurrentNode The node we are exploring from
- * @param[in] CurrentLink The Link on that node to explore.
- * @param[in] TempRoute The temporary node route that goes over that link.
- * @param[in] State Access to Northbridge interface.
- *
- */
-VOID
-STATIC
-AddLinkToSystem (
- IN UINT8 CurrentNode,
- IN UINT8 CurrentLink,
- IN UINT8 TempRoute,
- IN STATE_DATA *State
- )
-{
- UINT8 Token;
-
- ASSERT (State->TotalLinks < MAX_PLATFORM_LINKS);
-
- Token = State->Nb->ReadToken (TempRoute, State->Nb);
-
- (*State->PortList)[State->TotalLinks * 2].Type = PORTLIST_TYPE_CPU;
- (*State->PortList)[State->TotalLinks * 2].Link = CurrentLink;
- (*State->PortList)[State->TotalLinks * 2].NodeID = CurrentNode;
-
- (*State->PortList)[State->TotalLinks * 2 + 1].Type = PORTLIST_TYPE_CPU;
- (*State->PortList)[State->TotalLinks * 2 + 1].Link = State->Nb->ReadDefaultLink (TempRoute, State->Nb);
- (*State->PortList)[State->TotalLinks * 2 + 1].NodeID = Token;
-
- State->TotalLinks++;
-
- if ( !State->Fabric->SysMatrix[CurrentNode][Token] ) {
- State->Fabric->SysDegree[CurrentNode]++;
- State->Fabric->SysDegree[Token]++;
- State->Fabric->SysMatrix[CurrentNode][Token] = TRUE;
- State->Fabric->SysMatrix[Token][CurrentNode] = TRUE;
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Start discovery from a new node.
- *
- * If the node is not the BSP, establish a route between the node and the
- * BSP for request/response.
- * Set the node id, and enable routing on this node. This gives us control
- * on that node to isolate links, by specifying each link in turn as the route
- * to a possible new node.
- *
- * @param[in] CurrentNode The node we are exploring from
- * @param[in] State Access to Northbridge interface.
- *
- */
-VOID
-STATIC
-StartFromANewNode (
- IN UINT8 CurrentNode,
- IN STATE_DATA *State
- )
-{
- if (CurrentNode != 0) {
- // Set path from BSP to CurrentNode
- routeFromBSP (CurrentNode, CurrentNode, State);
-
- // Set path from BSP to CurrentNode for CurrentNode + 1 if
- // CurrentNode + 1 != MAX_NODES
- //
- if ((CurrentNode + 1) != MAX_NODES) {
- routeFromBSP (CurrentNode, (CurrentNode + 1), State);
- }
-
- // Configure CurrentNode to route traffic to the BSP through its
- // default Link
- //
- State->Nb->WriteRoutingTable (CurrentNode, 0, State->Nb->ReadDefaultLink (CurrentNode, State->Nb), State->Nb);
- }
-
- // Set CurrentNode's NodeID field to CurrentNode
- State->Nb->WriteNodeID (CurrentNode, CurrentNode, State->Nb);
-
- // Enable routing tables on CurrentNode
- State->Nb->EnableRoutingTables (CurrentNode, State->Nb);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Back up from exploring a one-deep internal node.
- *
- * When a newly discovered node has internal package links to another
- * node in the same processor, discovery moves to that node to do the
- * internal links. Afterwards, this routine provides recovery from that.
- * The node needs to respond again using deflnk rather than routing, so
- * that connections from other nodes to that one can be identified.
- *
- * @param[in] CurrentNode The node we are exploring from
- * @param[in] State Access to Northbridge interface.
- *
- */
-VOID
-STATIC
-BackUpFromANode (
- IN UINT8 CurrentNode,
- IN STATE_DATA *State
- )
-{
- if (CurrentNode != 0) {
- // Disable routing tables on CurrentNode
- State->Nb->DisableRoutingTables (CurrentNode, State->Nb);
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Dynamically Discover all coherent devices in the system.
- *
- * @HtFeatMethod{::F_COHERENT_DISCOVERY}
- *
- * Initialize some basics like Node IDs and total Nodes found in the
- * process. As we go we also build a representation of the discovered
- * system which we will use later to program the routing tables.
- * During this step, the routing is via default Link back to BSP and
- * to each new Node on the Link it was discovered on (no coherency is
- * active yet).
- *
- * In the case of multiple nodes per processor, do a one deep exploration of internal links
- * to ensure those node pairs are always numbered n, n + 1.
- *
- * @param[in,out] State our global state
- *
- */
-VOID
-CoherentDiscovery (
- IN OUT STATE_DATA *State
- )
-{
- UINT8 CurrentNode;
- UINT8 OneDeepNode;
- UINT8 OneDeepLink;
- UINT8 CurrentLink;
- UINT8 LogicalProcessor;
- EXPLORE_NODE_STATUS ExplorationStatus;
- LINK_ITERATOR_STATUS LinkIteratorStatus;
- NEW_NODE_SAVED_INFO_ITEM NewNodeSavedInfoItems [MAX_NODES];
- NEW_NODE_SAVED_INFO_LIST NewNodeSavedInfo;
-
- // Initially no info exists for any node, but the BSP is part of logical processor zero.
- for (CurrentNode = 0; CurrentNode < MAX_NODES; CurrentNode++) {
- NewNodeSavedInfoItems [CurrentNode] = NoInfoSavedYet;
- }
- NewNodeSavedInfoItems[0].LogicalProcessor = 0;
- NewNodeSavedInfoItems[0].HardwareSocket = State->Nb->GetSocket (0, 0, State->Nb);
- State->Nb->GetModuleInfo (0, &NewNodeSavedInfoItems[0].NewModuleType, &NewNodeSavedInfoItems[0].NewModule, State->Nb);
- NewNodeSavedInfo = (NEW_NODE_SAVED_INFO_LIST) NewNodeSavedInfoItems;
-
- CurrentNode = 0;
- CurrentLink = LINK_ITERATOR_BEGIN;
- LogicalProcessor = 0;
- // An initial status, for node zero if you will.
- ExplorationStatus = ExploreNodeStatusGood;
-
- //
- // Entries are always added in pairs, the even indices are the 'source'
- // side closest to the BSP, the odd indices are the 'destination' side
- //
-
- while ((CurrentNode <= State->NodesDiscovered) && (ExplorationStatus != ExploreNodeStatusStop)) {
- StartFromANewNode (CurrentNode, State);
-
- //
- // Explore all internal links
- //
- LinkIteratorStatus = State->Nb->GetNextLink (CurrentNode, &CurrentLink, State->Nb);
-
- while ((LinkIteratorStatus == LinkIteratorInternal) &&
- (ExplorationStatus != ExploreNodeStatusStop)) {
- if (IsLinkToAdd (CurrentNode, CurrentLink, State)) {
- ExplorationStatus = ExploreNode (CurrentNode, CurrentLink, LogicalProcessor, NewNodeSavedInfo, State);
- if ((ExplorationStatus == ExploreNodeStatusGood) ||
- (ExplorationStatus == ExploreNodeStatusNew)) {
- AddLinkToSystem (CurrentNode, CurrentLink, (CurrentNode + 1), State);
- }
- }
- LinkIteratorStatus = State->Nb->GetNextLink (CurrentNode, &CurrentLink, State->Nb);
- }
- if (CurrentNode == 0) {
- // The BSP processor is completely discovered now.
- ProcessSavedNodeInfo (LogicalProcessor, NewNodeSavedInfo, State);
- LogicalProcessor++;
- }
-
- //
- // Explore all the external links from this node.
- //
-
- // Starting this iteration using the link that we last got in the iteration above.
- while ((LinkIteratorStatus == LinkIteratorExternal) &&
- (ExplorationStatus != ExploreNodeStatusStop)) {
- if (IsLinkToAdd (CurrentNode, CurrentLink, State)) {
- ExplorationStatus = ExploreNode (CurrentNode, CurrentLink, LogicalProcessor, NewNodeSavedInfo, State);
- if (ExplorationStatus == ExploreNodeStatusNew) {
- AddLinkToSystem (CurrentNode, CurrentLink, (CurrentNode + 1), State);
- // If this is a new node, we need to explore to its internal mate, if any.
- // This allows us to keep internal node pairs as ids n, n+1
- // We use special link and node variables so we can keep our context.
- OneDeepLink = 0xFF;
- OneDeepNode = State->Nb->ReadToken ((CurrentNode + 1), State->Nb);
- StartFromANewNode (OneDeepNode, State);
- LinkIteratorStatus = State->Nb->GetNextLink (OneDeepNode, &OneDeepLink, State->Nb);
- while ((LinkIteratorStatus == LinkIteratorInternal) &&
- (ExplorationStatus != ExploreNodeStatusStop)) {
- if (IsLinkToAdd (OneDeepNode, OneDeepLink, State)) {
- ExplorationStatus = ExploreNode (OneDeepNode, OneDeepLink, LogicalProcessor, NewNodeSavedInfo, State);
- if ((ExplorationStatus == ExploreNodeStatusGood) ||
- (ExplorationStatus == ExploreNodeStatusNew)) {
- AddLinkToSystem (OneDeepNode, OneDeepLink, (OneDeepNode + 1), State);
- }
- }
- LinkIteratorStatus = State->Nb->GetNextLink (OneDeepNode, &OneDeepLink, State->Nb);
- }
- // Since we completed all the node's internal links, we found all the nodes in that processor.
- ProcessSavedNodeInfo (LogicalProcessor, NewNodeSavedInfo, State);
- LogicalProcessor++;
- // Restore node to discoverable state. Otherwise you can't tell what links it is connected on.
- BackUpFromANode (OneDeepNode, State);
- } else {
- if (ExplorationStatus == ExploreNodeStatusGood) {
- AddLinkToSystem (CurrentNode, CurrentLink, (CurrentNode + 1), State);
- }
- }
- }
- LinkIteratorStatus = State->Nb->GetNextLink (CurrentNode, &CurrentLink, State->Nb);
- }
- CurrentNode++;
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatDynamicDiscovery.h b/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatDynamicDiscovery.h
deleted file mode 100644
index 3c88143..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatDynamicDiscovery.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Coherent Discovery Interface.
- *
- * Contains interface to the coherent discovery feature.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _HT_FEAT_DYNAMIC_DISCOVERY_H_
-#define _HT_FEAT_DYNAMIC_DISCOVERY_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-/**
- * Dynamically Discover all coherent devices in the system.
- *
- */
-VOID
-CoherentDiscovery (
- IN OUT STATE_DATA *State
- );
-
-#endif /* _HT_FEAT_DYNAMIC_DISCOVERY_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatGanging.c b/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatGanging.c
deleted file mode 100644
index 0b0a745..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatGanging.c
+++ /dev/null
@@ -1,218 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Routines for re-ganging Links.
- *
- * Implement the reganging feature.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "htInterface.h"
-#include "htNb.h"
-#include "htFeatGanging.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_FEATURES_HTFEATGANGING_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/***************************************************************************
- *** Link Optimization ***
- ***************************************************************************/
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Test the subLinks of a Link to see if they qualify to be reganged.
- *
- * @HtFeatMethod{::F_REGANG_LINKS}
- *
- * If they do, update the port list data to indicate that this should be done.
- * @note no actual hardware state is changed in this routine.
- *
- * @param[in,out] State Our global state
- */
-VOID
-RegangLinks (
- IN OUT STATE_DATA *State
- )
-{
- FINAL_LINK_STATE FinalLinkState;
- UINT8 i;
- UINT8 j;
- for (i = 0; i < (State->TotalLinks * 2); i += 2) {
- // Data validation
- ASSERT ((*State->PortList)[i].Type < 2 && (*State->PortList)[i].Link < State->Nb->MaxLinks);
- ASSERT ((*State->PortList)[i + 1].Type < 2 && (*State->PortList)[i + 1].Link < State->Nb->MaxLinks);
-
- // Regang is false unless we pass all conditions below
- (*State->PortList)[i].SelRegang = FALSE;
- (*State->PortList)[i + 1].SelRegang = FALSE;
-
- // Only process cpu to cpu Links
- if ( ((*State->PortList)[i].Type != PORTLIST_TYPE_CPU) ||
- ((*State->PortList)[i + 1].Type != PORTLIST_TYPE_CPU)) {
- continue;
- }
-
- for (j = i + 2; j < State->TotalLinks*2; j += 2) {
- // Only process cpu to cpu Links
- if ( ((*State->PortList)[j].Type != PORTLIST_TYPE_CPU) ||
- ((*State->PortList)[j + 1].Type != PORTLIST_TYPE_CPU) ) {
- continue;
- }
-
- // Links must be from the same source
- if ((*State->PortList)[i].NodeID != (*State->PortList)[j].NodeID) {
- continue;
- }
-
- // Link must be to the same target
- if ((*State->PortList)[i + 1].NodeID != (*State->PortList)[j + 1].NodeID) {
- continue;
- }
-
- // Ensure same source base port
- if (((*State->PortList)[i].Link & 3) != ((*State->PortList)[j].Link & 3)) {
- continue;
- }
-
- // Ensure same destination base port
- if (((*State->PortList)[i + 1].Link & 3) != ((*State->PortList)[j + 1].Link & 3)) {
- continue;
- }
-
- // Ensure subLink0 routes to subLink0
- if (((*State->PortList)[i].Link & 4) != ((*State->PortList)[i + 1].Link & 4)) {
- continue;
- }
-
- // (therefore subLink1 routes to subLink1)
- ASSERT (((*State->PortList)[j].Link & 4) == ((*State->PortList)[j + 1].Link & 4));
-
- FinalLinkState = State->HtInterface->GetSkipRegang ((*State->PortList)[i].NodeID,
- (*State->PortList)[i].Link & 0x03,
- (*State->PortList)[i + 1].NodeID,
- (*State->PortList)[i + 1].Link & 0x03,
- State);
- if (FinalLinkState == MATCHED) {
- continue;
- } else if (FinalLinkState == POWERED_OFF) {
- // StopLink will be done on the sublink 1, thus OR in 4 to the link to ensure it.
- State->Nb->StopLink ((*State->PortList)[i].NodeID, ((*State->PortList)[i].Link | 4), State, State->Nb);
- State->Nb->StopLink ((*State->PortList)[i + 1].NodeID, ((*State->PortList)[i + 1].Link | 4), State, State->Nb);
- }
-
- //
- // Create a ganged portlist entry for the two regang-able subLinks.
- //
- // All info will be that of subLink zero.
- // (If Link discovery order was other than ascending, fix the .Pointer field too.)
- //
- //
- if (((*State->PortList)[i].Link & 4) != 0) {
- (*State->PortList)[i].Pointer = (*State->PortList)[j].Pointer;
- (*State->PortList)[i + 1].Pointer = (*State->PortList)[j + 1].Pointer;
- }
- (*State->PortList)[i].Link &= 0x03; // Force to point to subLink0
- (*State->PortList)[i + 1].Link &= 0x03;
- // If powered off, sublink 1 is removed but the link is still 8 bits.
- if (FinalLinkState != POWERED_OFF) {
- (*State->PortList)[i].SelRegang = TRUE; // Enable Link reganging
- (*State->PortList)[i + 1].SelRegang = TRUE;
- (*State->PortList)[i].PrvWidthOutCap = HT_WIDTH_16_BITS;
- (*State->PortList)[i + 1].PrvWidthOutCap = HT_WIDTH_16_BITS;
- (*State->PortList)[i].PrvWidthInCap = HT_WIDTH_16_BITS;
- (*State->PortList)[i + 1].PrvWidthInCap = HT_WIDTH_16_BITS;
- }
-
- // Delete PortList[j, j + 1], slow but easy to debug implementation
- State->TotalLinks--;
- LibAmdMemCopy (&((*State->PortList)[j]),
- &((*State->PortList)[j + 2]),
- sizeof (PORT_DESCRIPTOR)*(State->TotalLinks* 2 - j),
- State->ConfigHandle);
- LibAmdMemFill (&((*State->PortList)[State->TotalLinks * 2]), INVALID_LINK, (sizeof (PORT_DESCRIPTOR) * 2), State->ConfigHandle);
-
- break; // Exit loop, advance to PortList[i + 2]
- }
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatGanging.h b/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatGanging.h
deleted file mode 100644
index a9a85b8..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatGanging.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Link Reganging Interface.
- *
- * Contains interface to the Reganging feature.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _HT_FEAT_GANGING_H_
-#define _HT_FEAT_GANGING_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-/**
- * Test the subLinks of a Link to see if they qualify to be reganged.
- *
- */
-VOID
-RegangLinks (
- IN OUT STATE_DATA *State
- );
-
-#endif /* _HT_FEAT_GANGING_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatNoncoherent.c b/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatNoncoherent.c
deleted file mode 100644
index dbef5b8..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatNoncoherent.c
+++ /dev/null
@@ -1,375 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Non-Coherent Discovery Routines.
- *
- * Contains routines for enumerating and initializing non-coherent devices.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35740 $ @e \$Date: 2010-07-30 00:04:17 +0800 (Fri, 30 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "htInterface.h"
-#include "htNotify.h"
-#include "htNb.h"
-#include "htFeatNoncoherent.h"
-#include "htFeatOptimization.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_FEATURES_HTFEATNONCOHERENT_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define NO_DEVICE 0xFFFFFFFFull
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/***************************************************************************
- *** Non-coherent init code ***
- *** Algorithms ***
- ***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
-/**
- * Process a non-coherent Link.
- *
- * @HtFeatMethod{::F_PROCESS_LINK}
- *
- * Enable a range of bus numbers, and set the device ID for all devices found. Add
- * non-coherent devices, links to the system data structure.
- *
- * @param[in] Node Node on which to process nc init
- * @param[in] Link The non-coherent Link on that Node
- * @param[in] IsCompatChain Is this the chain with the southbridge? TRUE if yes.
- * @param[in,out] State our global state
- */
-VOID
-ProcessLink (
- IN UINT8 Node,
- IN UINT8 Link,
- IN BOOLEAN IsCompatChain,
- IN OUT STATE_DATA *State
- )
-{
- UINT8 SecBus;
- UINT8 SubBus;
- UINT32 CurrentBuid;
- UINT32 Temp;
- UINT32 UnitIdCount;
- PCI_ADDR CurrentPtr;
- PCI_ADDR Link1ControlRegister;
- UINT8 Depth;
- BUID_SWAP_LIST *SwapPtr;
- UINT8 LastLink;
- BOOLEAN IsCaveDevice;
-
- ASSERT ((Node < MAX_NODES) && (Link < State->Nb->MaxLinks));
-
- if (!State->HtInterface->GetOverrideBusNumbers (Node, Link, &SecBus, &SubBus, State)) {
- // Assign Bus numbers
- if (State->AutoBusCurrent >= State->HtBlock->AutoBusMax) {
- // If we run out of Bus Numbers, notify and skip this chain
- //
- IDS_ERROR_TRAP;
- NotifyErrorNcohBusMaxExceed (Node, Link, State->AutoBusCurrent, State);
- return;
- }
-
- if (State->UsedCfgMapEntries >= 4) {
- // If we have used all the PCI Config maps we can't add another chain.
- // Notify and if call back is unimplemented or returns, skip this chain.
- //
- IDS_ERROR_TRAP;
- NotifyErrorNcohCfgMapExceed (Node, Link, State);
- return;
- }
-
- SecBus = State->AutoBusCurrent;
- SubBus = SecBus + State->HtBlock->AutoBusIncrement - 1;
- State->AutoBusCurrent = State->AutoBusCurrent + State->HtBlock->AutoBusIncrement;
- }
-
- State->Nb->SetConfigAddrMap (State->UsedCfgMapEntries, SecBus, SubBus, Node, Link, State, State->Nb);
- State->UsedCfgMapEntries++;
-
- if (State->HtInterface->GetManualBuidSwapList (Node, Link, &SwapPtr, State)) {
- // Manual non-coherent BUID assignment
- AGESA_TESTPOINT (TpProcHtManualNc, State->ConfigHandle);
-
-
- if (!IsCompatChain || !State->IsUsingRecoveryHt) {
- // If this is the not southbridge chain or Recovery HT was not used
- // then we need to assign BUIDs here.
- //
- Depth = 0;
- // Assign BUID's per manual override
- while (SwapPtr->Swaps[Depth].FromId != 0xFF) {
- CurrentPtr.AddressValue = MAKE_SBDFO (0, SecBus, SwapPtr->Swaps[Depth].FromId, 0, 0);
- if (DoesDeviceHaveHtSubtypeCap (CurrentPtr, HT_SLAVE_CAPABILITY, &CurrentPtr, State)) {
- // Set the device's BUID field [20:16] to the current buid
- CurrentBuid = SwapPtr->Swaps[Depth].ToId;
- LibAmdPciWriteBits (CurrentPtr, 20, 16, &CurrentBuid, State->ConfigHandle);
- Depth++;
- } else {
- // All non-coherent devices must have a slave interface capability.
- ASSERT (FALSE);
- break;
- }
- }
- }
-
- // Build chain of devices. Do this even if Recovery HT assign BUIDs for this chain.
- Depth = 0;
- while (SwapPtr->FinalIds[Depth] != 0xFF) {
- ASSERT (State->TotalLinks < MAX_PLATFORM_LINKS);
- (*State->PortList)[(State->TotalLinks * 2)].NodeID = Node;
- // Note: depth == 0 is true before depth > 0. This makes LastLink variable work.
- if (Depth == 0) {
- (*State->PortList)[(State->TotalLinks * 2)].Type = PORTLIST_TYPE_CPU;
- (*State->PortList)[(State->TotalLinks * 2)].Link = Link;
- } else {
- // Fill in the host side port. Link and base pointer can be deduced from the upstream link's
- // downstream port.
- (*State->PortList)[(State->TotalLinks * 2)].Type = PORTLIST_TYPE_IO;
- (*State->PortList)[(State->TotalLinks * 2)].Link = 1 - (*State->PortList)[(((State->TotalLinks - 1) * 2) + 1)].Link;
- (*State->PortList)[(State->TotalLinks * 2)].HostLink = Link;
- (*State->PortList)[(State->TotalLinks * 2)].HostDepth = Depth - 1;
- (*State->PortList)[(State->TotalLinks * 2)].Pointer = (*State->PortList)[(((State->TotalLinks - 1) * 2) + 1)].Pointer;
- }
-
- (*State->PortList)[(State->TotalLinks * 2) + 1].Type = PORTLIST_TYPE_IO;
- (*State->PortList)[(State->TotalLinks * 2) + 1].NodeID = Node;
- (*State->PortList)[(State->TotalLinks * 2) + 1].HostLink = Link;
- (*State->PortList)[(State->TotalLinks * 2) + 1].HostDepth = Depth;
-
- CurrentPtr.AddressValue = MAKE_SBDFO (0, SecBus, (SwapPtr->FinalIds[Depth] & 0x3F), 0, 0);
- if (DoesDeviceHaveHtSubtypeCap (CurrentPtr, HT_SLAVE_CAPABILITY, &CurrentPtr, State)) {
- (*State->PortList)[(State->TotalLinks * 2) + 1].Pointer = CurrentPtr;
- } else {
- // All non-coherent devices must have a slave interface capability.
- ASSERT (FALSE);
- break;
- }
-
- // Bit 6 indicates whether orientation override is desired.
- // Bit 7 indicates the upstream Link if overriding.
- //
- // assert catches at least the one known incorrect setting, that a non-zero link
- // is specified, but override desired is not set.
- ASSERT (((SwapPtr->FinalIds[Depth] & 0x40) != 0) || ((SwapPtr->FinalIds[Depth] & 0x80) == 0));
- if ((SwapPtr->FinalIds[Depth] & 0x40) != 0) {
- // Override the device's orientation
- LastLink = SwapPtr->FinalIds[Depth] >> 7;
- } else {
- // Detect the device's orientation, by reading the Master Host bit [26]
- LibAmdPciReadBits (CurrentPtr, 26, 26, &Temp, State->ConfigHandle);
- LastLink = (UINT8)Temp;
- }
- (*State->PortList)[(State->TotalLinks * 2) + 1].Link = LastLink;
-
- Depth++;
- State->TotalLinks++;
- }
- } else {
- // Automatic non-coherent device detection
- AGESA_TESTPOINT (TpProcHtAutoNc, State->ConfigHandle);
- IDS_HDT_CONSOLE (HT_TRACE, "Auto IO chain init on node=%d, link=%d, secbus=%d, subbus=%d%s.\n",
- Node, Link, SecBus, SubBus, (IsCompatChain ? ", Compat" : ""));
- Depth = 0;
- CurrentBuid = 1;
- for (; ; ) {
- CurrentPtr.AddressValue = MAKE_SBDFO (0, SecBus, 0, 0, 0);
-
- LibAmdPciRead (AccessWidth32, CurrentPtr, &Temp, State->ConfigHandle);
- if (Temp == NO_DEVICE) {
- if (IsCompatChain && State->IsUsingRecoveryHt) {
- // See if the device is aleady at a non-zero BUID because HT Init Reset aleady assigned it.
- CurrentPtr.Address.Device = CurrentBuid;
- LibAmdPciRead (AccessWidth32, CurrentPtr, &Temp, State->ConfigHandle);
- if (Temp == NO_DEVICE) {
- // No more devices already assigned.
- break;
- }
- } else {
- // No more devices found.
- break;
- }
- }
-
- ASSERT (State->TotalLinks < MAX_PLATFORM_LINKS);
-
- (*State->PortList)[(State->TotalLinks * 2)].NodeID = Node;
- if (Depth == 0) {
- (*State->PortList)[(State->TotalLinks * 2)].Type = PORTLIST_TYPE_CPU;
- (*State->PortList)[(State->TotalLinks * 2)].Link = Link;
- } else {
- // Fill in the host side port. Link and base pointer can be deduced from the upstream link's
- // downstream port.
- (*State->PortList)[(State->TotalLinks * 2)].Type = PORTLIST_TYPE_IO;
- (*State->PortList)[(State->TotalLinks * 2)].Link = 1 - (*State->PortList)[((State->TotalLinks - 1) * 2) + 1].Link;
- (*State->PortList)[(State->TotalLinks * 2)].HostLink = Link;
- (*State->PortList)[(State->TotalLinks * 2)].HostDepth = Depth - 1;
- (*State->PortList)[(State->TotalLinks * 2)].Pointer = (*State->PortList)[((State->TotalLinks - 1) * 2) + 1].Pointer;
- }
-
- (*State->PortList)[(State->TotalLinks * 2) + 1].Type = PORTLIST_TYPE_IO;
- (*State->PortList)[(State->TotalLinks * 2) + 1].NodeID = Node;
- (*State->PortList)[(State->TotalLinks * 2) + 1].HostLink = Link;
- (*State->PortList)[(State->TotalLinks * 2) + 1].HostDepth = Depth;
-
- if (DoesDeviceHaveHtSubtypeCap (CurrentPtr, HT_SLAVE_CAPABILITY, &CurrentPtr, State)) {
-
- // Get device's unit id count [25:21]
- LibAmdPciReadBits (CurrentPtr, 25, 21, &UnitIdCount, State->ConfigHandle);
- if (((UnitIdCount + CurrentBuid) > MAX_BUID) || ((SecBus == 0) && ((UnitIdCount + CurrentBuid) > 24))) {
- // An error handler for the case where we run out of BUID's on a chain
- NotifyErrorNcohBuidExceed (Node, Link, Depth, (UINT8)CurrentBuid, (UINT8)UnitIdCount, State);
- IDS_ERROR_TRAP;
- break;
- }
- // While we are still certain we are accessing this device, remember if it is a cave device.
- // This is found by reading EOC from the Link 1 Control Register.
- Link1ControlRegister = CurrentPtr;
- Link1ControlRegister.Address.Register += (HTSLAVE_LINK01_OFFSET + HTSLAVE_LINK_CONTROL_0_REG);
- LibAmdPciReadBits (Link1ControlRegister, 6, 6, &Temp, State->ConfigHandle);
- IsCaveDevice = ((Temp == 0) ? FALSE : TRUE);
-
- // Attempt to write the new BUID. Unless this chain was aleady assigned BUIDs during Init Reset,
- // then just re-discover the chain. Note this may be true whether the device was found at
- // BUID zero or not.
- IDS_HDT_CONSOLE (HT_TRACE, "Found device at depth=%d, BUID=%d.\n", Depth, CurrentPtr.Address.Device);
- if (!IsCompatChain || !State->IsUsingRecoveryHt) {
- IDS_HDT_CONSOLE (HT_TRACE, "Assigning device to BUID=%d.\n", CurrentBuid);
- LibAmdPciWriteBits (CurrentPtr, 20, 16, &CurrentBuid, State->ConfigHandle);
- }
-
- CurrentPtr.Address.Device = CurrentBuid;
- LibAmdPciReadBits (CurrentPtr, 20, 16, &Temp, State->ConfigHandle);
- if (Temp != CurrentBuid) {
- if ((Depth == 0) && IsCaveDevice) {
- // If the chain only consists of a single cave device, that device may have retained zero
- // for it's BUID.
- CurrentPtr.Address.Device = 0;
- LibAmdPciReadBits (CurrentPtr, 20, 16, &Temp, State->ConfigHandle);
- if (Temp == 0) {
- // Per HyperTransport specification, devices not accepting BUID reassignment hardwire BUID to zero.
- (*State->PortList)[(State->TotalLinks * 2) + 1].Link = 0;
- (*State->PortList)[(State->TotalLinks * 2) + 1].Pointer = CurrentPtr;
- State->TotalLinks++;
- Depth++;
- // Success!
- IDS_HDT_CONSOLE (HT_TRACE, "%s Cave left at BUID=0.\n", ((!IsCompatChain || !State->IsUsingRecoveryHt) ? "Compatible" : "Already Assigned"));
- break;
- } else if (Temp == CurrentBuid) {
- // and then, there are the other kind of devices ....
- // Restore the writable BUID field (which contains the value we just wrote) to zero.
- Temp = 0;
- LibAmdPciWriteBits (CurrentPtr, 20, 16, &Temp, State->ConfigHandle);
- (*State->PortList)[(State->TotalLinks * 2) + 1].Link = 0;
- (*State->PortList)[(State->TotalLinks * 2) + 1].Pointer = CurrentPtr;
- State->TotalLinks++;
- Depth++;
- // Success!
- IDS_HDT_CONSOLE (HT_TRACE, "Cave left at BUID=0.\n");
- break;
- }
- }
- // An error handler for this error,
- // this often occurs in new BIOS ports and it means you need to use a Manual BUID Swap List.
- NotifyErrorNcohDeviceFailed (Node, Link, Depth, (UINT8)CurrentBuid, State);
- IDS_ERROR_TRAP;
- break;
- }
-
- LibAmdPciReadBits (CurrentPtr, 26, 26, &Temp, State->ConfigHandle);
- (*State->PortList)[(State->TotalLinks * 2) + 1].Link = (UINT8)Temp;
- (*State->PortList)[(State->TotalLinks * 2) + 1].Pointer = CurrentPtr;
-
- IDS_HDT_CONSOLE (HT_TRACE, "Device assigned.\n");
- Depth++;
- State->TotalLinks++;
- CurrentBuid += UnitIdCount;
- } else {
- // All non-coherent devices must have a slave interface capability.
- ASSERT (FALSE);
- break;
- }
- }
- // Provide information on automatic device results
- NotifyInfoNcohAutoDepth (Node, Link, (Depth - 1), State);
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatNoncoherent.h b/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatNoncoherent.h
deleted file mode 100644
index 5f7c886..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatNoncoherent.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Non-Coherent Discovery Interface.
- *
- * Contains interface to the Non-Coherent Link processing feature.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _HT_FEAT_NONCOHERENT_H_
-#define _HT_FEAT_NONCOHERENT_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-/**
- * Process a non-coherent Link.
- *
- */
-VOID
-ProcessLink (
- IN UINT8 Node,
- IN UINT8 Link,
- IN BOOLEAN IsCompatChain,
- IN OUT STATE_DATA *State
- );
-
-#endif /* _HT_FEAT_NONCOHERENT_H_ */
diff --git a/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatOptimization.c b/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatOptimization.c
deleted file mode 100644
index bcd669f..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatOptimization.c
+++ /dev/null
@@ -1,886 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Link Optimization Routines.
- *
- * Contains routines for determining width, frequency, and other
- * Link features
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "IdsHt.h"
-#include "htInterface.h"
-#include "htNb.h"
-#include "htFeatOptimization.h"
-#include "htNotify.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_FEATURES_HTFEATOPTIMIZATION_FILECODE
-
-extern CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride;
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define PCI_CONFIG_COMMAND_REG04 4
-#define PCI_CONFIG_REVISION_REG08 8
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/***************************************************************************
- *** Link Optimization ***
- ***************************************************************************/
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Given the bits set in the register field, return the width it represents.
- *
- * As invalid width values or encodings are rare except during debug, catch those using
- * ASSERT(). This means theoretically we are returning an incorrect result if that
- * happens. The default chosen for the result is arbitrarily 8 bits. This is likely
- * not to be the actual correct width and may cause a crash, hang, or incorrect operation.
- * Hardware often ignores writes of invalid width encodings.
- *
- * @note This routine is used for CPUs as well as IO devices, as all comply to the
- * "HyperTransport I/O Link Specification ".
- *
- * @param[in] Value The bits for the register
- *
- * @return The width
- */
-UINT8
-STATIC
-ConvertBitsToWidth (
- IN UINT8 Value
- )
-{
- UINT8 Result;
-
- Result = 0;
-
- switch (Value) {
-
- case 1:
- Result = 16;
- break;
-
- case 0:
- Result = 8;
- break;
-
- case 3:
- Result = 32;
- break;
-
- case 5:
- Result = 4;
- break;
-
- case 4:
- Result = 2;
- break;
-
- default:
- ASSERT (FALSE);
- }
- return Result;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Translate a desired width setting to the bits to set in the register field.
- *
- * As invalid width values or encodings are rare except during debug, catch those using
- * ASSERT(). This means theoretically we are returning an incorrect result if that
- * happens. The default chosen for the result is arbitrarily 8 bits. This is likely
- * not to be the actual correct width and may cause a crash, hang, or incorrect operation.
- * Hardware often ignores writes of invalid width encodings.
- *
- * @note This routine is used for CPUs as well as IO devices, as all comply to the
- * "HyperTransport I/O Link Specification ".
- *
- * @param[in] Value the width Value
- *
- * @return The bits for the register
- */
-UINT8
-ConvertWidthToBits (
- IN UINT8 Value
- )
-{
- UINT8 Result;
-
- Result = 8;
-
- switch (Value) {
-
- case 16:
- Result = 1;
- break;
-
- case 8:
- Result = 0;
- break;
-
- case 32:
- Result = 3;
- break;
-
- case 4:
- Result = 5;
- break;
-
- case 2:
- Result = 4;
- break;
-
- default:
- ASSERT (FALSE);
- }
- return Result;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Access HT Link Control Register.
- *
- * @HtFeatMethod{::F_SET_HT_CONTROL_REGISTER_BITS}
- *
- * Provide a common routine for accessing the HT Link Control registers (84, a4, c4,
- * e4), to enforce not clearing the HT CRC error bits. Replaces direct use of
- * AmdPCIWriteBits().
- *
- * @note: This routine is called for CPUs as well as IO Devices! All comply to the
- * "HyperTransport I/O Link Specification ".
- *
- * @param[in] Reg the PCI config address the control register
- * @param[in] HiBit the high bit number
- * @param[in] LoBit the low bit number
- * @param[in] Value the value to write to that bit range. Bit 0 => loBit.
- * @param[in] State Our state, config handle for lib
- */
-VOID
-SetHtControlRegisterBits (
- IN PCI_ADDR Reg,
- IN UINT8 HiBit,
- IN UINT8 LoBit,
- IN UINT32 *Value,
- IN STATE_DATA *State
- )
-{
- UINT32 Temp;
- UINT32 mask;
-
- ASSERT ((HiBit < 32) && (LoBit < 32) && (HiBit >= LoBit) && ((Reg.AddressValue & 0x3) == 0));
- ASSERT ((HiBit < 8) || (LoBit > 9));
-
- // A 1 << 32 == 1 << 0 due to x86 SHL instruction, so skip if that is the case
- if ((HiBit - LoBit) != 31) {
- mask = (((UINT32)1 << (HiBit - LoBit + 1)) - 1);
- } else {
- mask = (UINT32)0xFFFFFFFF;
- }
-
- LibAmdPciRead (AccessWidth32, Reg, &Temp, State->ConfigHandle);
- Temp &= ~(mask << LoBit);
- Temp |= (*Value & mask) << LoBit;
- Temp &= (UINT32)HT_CONTROL_CLEAR_CRC;
- LibAmdPciWrite (AccessWidth32, Reg, &Temp, State->ConfigHandle);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Set HT Frequency register for IO Devices
- *
- * Provide a common routine for accessing the HT Link Frequency registers at offset 8
- * and 0x10, to enforce not clearing the HT Link error bits. Replaces direct use of
- * AmdPCIWriteBits().
- *
- * @note This routine is called for IO Devices only!! All comply to the
- * "HyperTransport I/O Link Specification ".
- *
- * @param[in] Reg the PCI config address the control register
- * @param[in] Hibit the high bit number
- * @param[in] Lobit the low bit number
- * @param[in] Value the value to write to that bit range. Bit 0 => loBit.
- * @param[in] State Our state, config handle for lib
- */
-VOID
-STATIC
-SetHtIoFrequencyRegisterBits (
- IN PCI_ADDR Reg,
- IN UINT8 Hibit,
- IN UINT8 Lobit,
- IN UINT32 *Value,
- IN STATE_DATA *State
- )
-{
- UINT32 Mask;
- UINT32 Temp;
-
- ASSERT ((Hibit < 32) && (Lobit < 32) && (Hibit >= Lobit) && ((Reg.AddressValue & 0x3) == 0));
- ASSERT ((Hibit < 12) || (Lobit > 14));
-
- // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
- if ((Hibit - Lobit) != 31) {
- Mask = (((UINT32)1 << ((Hibit - Lobit) + 1)) - 1);
- } else {
- Mask = (UINT32)0xFFFFFFFF;
- }
-
- LibAmdPciRead (AccessWidth32, Reg, &Temp, State->ConfigHandle);
- Temp &= ~(Mask << Lobit);
- Temp |= (*Value & Mask) << Lobit;
- Temp &= (UINT32)HT_FREQUENCY_CLEAR_LINK_ERRORS;
- LibAmdPciWrite (AccessWidth32, Reg, &Temp, State->ConfigHandle);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get Link features into system data structure.
- *
- * @HtFeatMethod{::F_GATHER_LINK_DATA}
- *
- * For all discovered Links, populate the port list with the frequency and width
- * capabilities. Gather support data for:
- * - Unit ID Clumping
- *
- * @param[in] State our global state, port list
- */
-VOID
-GatherLinkData (
- IN STATE_DATA *State
- )
-{
- UINT8 i;
- PCI_ADDR LinkBase;
- PCI_ADDR Reg;
- UINT32 Bits;
- UINT8 Revision;
-
- // Get the capability base for whatever device type the link port is on
- for (i = 0; i < (State->TotalLinks * 2); i++) {
- if ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) {
- LinkBase = State->Nb->MakeLinkBase ((*State->PortList)[i].NodeID, (*State->PortList)[i].Link, State->Nb);
- (*State->PortList)[i].Pointer = LinkBase;
- } else {
- LinkBase = (*State->PortList)[i].Pointer;
- if ((*State->PortList)[i].Link == 1) {
- LinkBase.Address.Register += HTSLAVE_LINK01_OFFSET;
- }
- }
-
- // Getting the Width is standard across device types
- Reg = LinkBase;
- Reg.Address.Register += HTSLAVE_LINK_CONTROL_0_REG;
- LibAmdPciReadBits (Reg, 22, 20, &Bits, State->ConfigHandle);
- (*State->PortList)[i].PrvWidthOutCap = ConvertBitsToWidth ((UINT8)Bits);
-
- LibAmdPciReadBits (Reg, 18, 16, &Bits, State->ConfigHandle);
- (*State->PortList)[i].PrvWidthInCap = ConvertBitsToWidth ((UINT8)Bits);
-
- // Get Frequency and other device type specific features
- if ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) {
- State->Nb->GatherLinkFeatures (&(*State->PortList)[i], State->HtInterface, State->PlatformConfiguration, State->Nb);
- } else {
- Reg = LinkBase;
- Reg.Address.Register += HTSLAVE_FREQ_REV_0_REG;
- LibAmdPciReadBits (Reg, 31, 16, &Bits, State->ConfigHandle);
- (*State->PortList)[i].PrvFrequencyCap = Bits;
-
- // Unit ID Clumping Support
- if (State->IsUsingUnitIdClumping) {
- if (DoesDeviceHaveHtSubtypeCap (LinkBase, HT_UNITID_CAPABILITY, &Reg, State)) {
- Reg.Address.Register += HTUNIT_SUPPORT_REG;
- LibAmdPciReadBits (Reg, 31, 0, &Bits, State->ConfigHandle);
- } else {
- // Not there, that's ok, we don't know that it should have one.
- // Check for Passive support. (Bit 0 won't be set if full support is implemented,
- // so we can use it to indicate passive support in our portlist struct).
- Reg = LinkBase;
- Reg.Address.Register += HTSLAVE_FEATURECAP_REG;
- Bits = 1;
- LibAmdPciWriteBits (Reg, 5, 5, &Bits, State->ConfigHandle);
- LibAmdPciReadBits (Reg, 5, 5, &Bits, State->ConfigHandle);
- }
- (*State->PortList)[i].ClumpingSupport = Bits;
- } else {
- (*State->PortList)[i].ClumpingSupport = HT_CLUMPING_DISABLE;
- }
-
- Reg = LinkBase;
- Reg.Address.Register = PCI_CONFIG_REVISION_REG08;
- LibAmdPciReadBits ( LinkBase, 7, 0, &Bits, State->ConfigHandle);
- Revision = (UINT8) Bits;
-
- LinkBase.Address.Register = 0;
- LibAmdPciRead (AccessWidth32, LinkBase, &Bits, State->ConfigHandle);
-
- State->HtInterface->GetDeviceCapOverride ((*State->PortList)[i].NodeID,
- (*State->PortList)[i].HostLink,
- (*State->PortList)[i].HostDepth,
- (*State->PortList)[i].Pointer,
- Bits,
- Revision,
- (*State->PortList)[i].Link,
- &((*State->PortList)[i].PrvWidthInCap),
- &((*State->PortList)[i].PrvWidthOutCap),
- &((*State->PortList)[i].PrvFrequencyCap),
- &((*State->PortList)[i].ClumpingSupport),
- State);
- }
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Optimize Links.
- *
- * @HtFeatMethod{::F_SELECT_OPTIMAL_WIDTH_AND_FREQUENCY}
- *
- * For all Links:
- * Examine both sides of a Link and determine the optimal frequency and width,
- * taking into account externally provided limits and enforcing any other limit
- * or matching rules as applicable except subLink balancing. Update the port
- * list data with the optimal settings.
- *
- * @note no hardware state changes in this routine.
- *
- * @param[in,out] State Process and update portlist
- */
-VOID
-SelectOptimalWidthAndFrequency (
- IN OUT STATE_DATA *State
- )
-{
- UINT8 i;
- UINT8 j;
- UINT8 Freq;
- UINT32 Temp;
- UINT32 CbPcbFreqLimit;
- UINT8 CbPcbABDownstreamWidth;
- UINT8 CbPcbBAUpstreamWidth;
-
- for (i = 0; i < (State->TotalLinks * 2); i += 2) {
- CbPcbFreqLimit = HT_FREQUENCY_NO_LIMIT;
- CbPcbABDownstreamWidth = HT_WIDTH_16_BITS;
- CbPcbBAUpstreamWidth = HT_WIDTH_16_BITS;
-
- if (((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) && ((*State->PortList)[i + 1].Type == PORTLIST_TYPE_CPU)) {
- State->HtInterface->GetCpu2CpuPcbLimits ((*State->PortList)[i].NodeID,
- (*State->PortList)[i].Link,
- (*State->PortList)[i + 1].NodeID,
- (*State->PortList)[i + 1].Link,
- &CbPcbABDownstreamWidth,
- &CbPcbBAUpstreamWidth,
- &CbPcbFreqLimit,
- State
- );
- } else {
- State->HtInterface->GetIoPcbLimits ((*State->PortList)[i + 1].NodeID,
- (*State->PortList)[i + 1].HostLink,
- (*State->PortList)[i + 1].HostDepth,
- &CbPcbABDownstreamWidth,
- &CbPcbBAUpstreamWidth,
- &CbPcbFreqLimit,
- State
- );
- }
-
- Temp = (*State->PortList)[i].PrvFrequencyCap;
- Temp &= (*State->PortList)[i + 1].PrvFrequencyCap;
- Temp &= CbPcbFreqLimit;
- (*State->PortList)[i].CompositeFrequencyCap = (UINT32)Temp;
- (*State->PortList)[i + 1].CompositeFrequencyCap = (UINT32)Temp;
-
- ASSERT (Temp != 0);
- Freq = LibAmdBitScanReverse (Temp);
- (*State->PortList)[i].SelFrequency = Freq;
- (*State->PortList)[i + 1].SelFrequency = Freq;
-
- Temp = (*State->PortList)[i].PrvWidthOutCap;
- if ((*State->PortList)[i + 1].PrvWidthInCap < Temp) {
- Temp = (*State->PortList)[i + 1].PrvWidthInCap;
- }
- if (CbPcbABDownstreamWidth < Temp) {
- Temp = CbPcbABDownstreamWidth;
- }
- (*State->PortList)[i].SelWidthOut = (UINT8)Temp;
- (*State->PortList)[i + 1].SelWidthIn = (UINT8)Temp;
-
- Temp = (*State->PortList)[i].PrvWidthInCap;
- if ((*State->PortList)[i + 1].PrvWidthOutCap < Temp) {
- Temp = (*State->PortList)[i + 1].PrvWidthOutCap;
- }
- if (CbPcbBAUpstreamWidth < Temp) {
- Temp = CbPcbBAUpstreamWidth;
- }
- (*State->PortList)[i].SelWidthIn = (UINT8)Temp;
- (*State->PortList)[i + 1].SelWidthOut = (UINT8)Temp;
- }
- // Calculate unit id clumping
- //
- // Find the root of each IO Chain, process the chain for clumping support.
- // The root is always the first link of the chain in the port list.
- // Clumping is not device link specific, so we can just look at the upstream ports (j+1). Use ASSERTs to sanity
- // check the downstream ports (j). If any device on the chain does not support clumping, the entire chain will be
- // disabled for clumping.
- // After analyzing the clumping support on the chain the CPU's portlist has the enable mask. Update all the
- // IO Devices on the chain with the enable mask. If any device's only have passive support, that is already enabled.
- //
- if (State->IsUsingUnitIdClumping) {
- for (i = 0; i < (State->TotalLinks * 2); i += 2) {
- if (((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) && ((*State->PortList)[i + 1].Type == PORTLIST_TYPE_IO)) {
- (*State->PortList)[i].ClumpingSupport = HT_CLUMPING_DISABLE;
- if ((*State->PortList)[i + 1].ClumpingSupport != HT_CLUMPING_DISABLE) {
- (*State->PortList)[i].ClumpingSupport |= (*State->PortList)[i + 1].ClumpingSupport;
- for (j = i + 2; j < (State->TotalLinks * 2); j += 2) {
- if (((*State->PortList)[j].Type == PORTLIST_TYPE_IO) && ((*State->PortList)[j + 1].Type == PORTLIST_TYPE_IO)) {
- if (((*State->PortList)[i].NodeID == (*State->PortList)[j + 1].NodeID) &&
- ((*State->PortList)[i].Link == (*State->PortList)[j + 1].HostLink)) {
- ASSERT (((*State->PortList)[i].NodeID == (*State->PortList)[j + 1].NodeID) &&
- ((*State->PortList)[i].Link == (*State->PortList)[j].HostLink));
- if ((*State->PortList)[j + 1].ClumpingSupport != HT_CLUMPING_DISABLE) {
- ASSERT ((((*State->PortList)[j + 1].ClumpingSupport & HT_CLUMPING_PASSIVE) == 0) ||
- (((*State->PortList)[j + 1].ClumpingSupport & ~(HT_CLUMPING_PASSIVE)) == 0));
- (*State->PortList)[i].ClumpingSupport |= (*State->PortList)[j + 1].ClumpingSupport;
- } else {
- (*State->PortList)[i].ClumpingSupport = HT_CLUMPING_DISABLE;
- break;
- }
- }
- }
- }
- if ((*State->PortList)[i + 1].ClumpingSupport != HT_CLUMPING_PASSIVE) {
- (*State->PortList)[i + 1].ClumpingSupport = (*State->PortList)[i].ClumpingSupport;
- }
- for (j = i + 2; j < (State->TotalLinks * 2); j += 2) {
- if (((*State->PortList)[j].Type == PORTLIST_TYPE_IO) && ((*State->PortList)[j + 1].Type == PORTLIST_TYPE_IO)) {
- if (((*State->PortList)[i].NodeID == (*State->PortList)[j + 1].NodeID) &&
- ((*State->PortList)[i].Link == (*State->PortList)[j + 1].HostLink)) {
- if ((*State->PortList)[j + 1].ClumpingSupport != HT_CLUMPING_PASSIVE) {
- (*State->PortList)[j + 1].ClumpingSupport = (*State->PortList)[i].ClumpingSupport;
- // The downstream isn't really passive, just mark it so in order to write the device only once.
- (*State->PortList)[j].ClumpingSupport = HT_CLUMPING_PASSIVE;
- }
- }
- }
- }
- }
- }
- }
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Change the hardware state for all Links according to the now optimized data in the
- * port list data structure.
- *
- * @HtFeatMethod{::F_SET_LINK_DATA}
- *
- * @param[in] State our global state, port list
- */
-VOID
-SetLinkData (
- IN STATE_DATA *State
- )
-{
- UINT8 i;
- PCI_ADDR LinkBase;
- PCI_ADDR Reg;
- UINT32 Temp;
- UINT32 Widthin;
- UINT32 Widthout;
- UINT32 Bits;
- PCI_ADDR CurrentPtr;
- HTIDS_PORT_OVERRIDE_LIST PortOverrides;
-
- PortOverrides = NULL;
-
- for (i = 0; i < (State->TotalLinks * 2); i++) {
-
- ASSERT ((*State->PortList)[i & 0xFE].SelWidthOut == (*State->PortList)[ (i & 0xFE) + 1].SelWidthIn);
- ASSERT ((*State->PortList)[i & 0xFE].SelWidthIn == (*State->PortList)[ (i & 0xFE) + 1].SelWidthOut);
- ASSERT ((*State->PortList)[i & 0xFE].SelFrequency == (*State->PortList)[ (i & 0xFE) + 1].SelFrequency);
-
- if ((*State->PortList)[i].SelRegang) {
- ASSERT ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU);
- ASSERT ((*State->PortList)[i].Link < 4);
- State->Nb->SetLinkRegang (
- (*State->PortList)[i].NodeID,
- (*State->PortList)[i].Link,
- State->Nb
- );
- }
-
- //
- // IDS port override for CPUs and IO Devices
- //
- pf_HtIdsGetPortOverride ((BOOLEAN) ((i & 1) == 0), &(*State->PortList)[i], &(*State->PortList)[i + 1], &PortOverrides, State);
-
- LinkBase = (*State->PortList)[i].Pointer;
- if (((*State->PortList)[i].Type == PORTLIST_TYPE_IO) && ((*State->PortList)[i].Link == 1)) {
- LinkBase.Address.Register += HTSLAVE_LINK01_OFFSET;
- }
-
- // HT CRC Feature, set if configured. The default is not to set it, because with some chipsets it
- // will lock up if done here.
- if (State->IsSetHtCrcFlood) {
- Temp = 1;
- Reg = LinkBase;
- Reg.Address.Register += HTHOST_LINK_CONTROL_REG;
- State->HtFeatures->SetHtControlRegisterBits (Reg, 1, 1, &Temp, State);
- if ((*State->PortList)[i].Type == PORTLIST_TYPE_IO) {
- // IO Devices also need to have SERR enabled.
- Reg = LinkBase;
- Reg.Address.Register = PCI_CONFIG_COMMAND_REG04;
- LibAmdPciWriteBits (Reg, 8, 8, &Temp, State->ConfigHandle);
- }
- }
-
- // Some IO devices don't work properly when setting widths, so write them in a single operation,
- // rather than individually.
- //
- Widthout = ConvertWidthToBits ((*State->PortList)[i].SelWidthOut);
- ASSERT (Widthout == 1 || Widthout == 0 || Widthout == 5 || Widthout == 4);
- Widthin = ConvertWidthToBits ((*State->PortList)[i].SelWidthIn);
- ASSERT (Widthin == 1 || Widthin == 0 || Widthin == 5 || Widthin == 4);
-
- Temp = (Widthin & 7) | ((Widthout & 7) << 4);
- Reg = LinkBase;
- Reg.Address.Register += HTHOST_LINK_CONTROL_REG;
- State->HtFeatures->SetHtControlRegisterBits (Reg, 31, 24, &Temp, State);
-
- Temp = (*State->PortList)[i].SelFrequency;
- if ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) {
- State->Nb->SetLinkFrequency (
- (*State->PortList)[i].NodeID,
- (*State->PortList)[i].Link,
- (UINT8)Temp,
- State->Nb
- );
- } else {
- ASSERT (Temp <= HT_FREQUENCY_2600M);
- // Write the frequency setting
- Reg = LinkBase;
- Reg.Address.Register += HTSLAVE_FREQ_REV_0_REG;
- SetHtIoFrequencyRegisterBits (Reg, 11, 8, &Temp, State);
-
- // Handle additional HT3 frequency requirements, if needed,
- // or clear them if switching down to ht1 on a warm reset.
- // Gen1 = 200Mhz -> 1000MHz, Gen3 = 1200MHz -> 2600MHz
- //
- // Even though we assert if debugging, we need to check that the capability was
- // found always, since this is an unknown hardware device, also we are taking
- // unqualified frequency from the external interface (could be trying to do ht3
- // on an ht1 IO device).
- //
-
- if (Temp > HT_FREQUENCY_1000M) {
- // Enabling features if gen 3
- Bits = 1;
- } else {
- // Disabling features if gen 1
- Bits = 0;
- }
-
- // Retry Enable
- if (DoesDeviceHaveHtSubtypeCap (LinkBase, HT_RETRY_CAPABILITY, &CurrentPtr, State)) {
- ASSERT ((*State->PortList)[i].Link < 2);
- CurrentPtr.Address.Register += HTRETRY_CONTROL_REG;
- LibAmdPciWriteBits (CurrentPtr,
- ((*State->PortList)[i].Link * 16),
- ((*State->PortList)[i].Link * 16),
- &Bits,
- State->ConfigHandle);
- } else {
- // If we are turning it off, that may mean the device was only ht1 capable,
- // so don't complain that we can't do it.
- //
- if (Bits != 0) {
- NotifyWarningOptRequiredCapRetry ((*State->PortList)[i].NodeID,
- (*State->PortList)[i].HostLink,
- (*State->PortList)[i].HostDepth,
- State);
- }
- }
-
- // Scrambling enable
- if (DoesDeviceHaveHtSubtypeCap (LinkBase, HT_GEN3_CAPABILITY, &CurrentPtr, State)) {
- ASSERT ((*State->PortList)[i].Link < 2);
- CurrentPtr.Address.Register = CurrentPtr.Address.Register +
- HTGEN3_LINK_TRAINING_0_REG +
- ((*State->PortList)[i].Link * HTGEN3_LINK01_OFFSET);
- LibAmdPciWriteBits (CurrentPtr, 3, 3, &Bits, State->ConfigHandle);
- } else {
- // If we are turning it off, that may mean the device was only ht1 capable,
- // so don't complain that we can't do it.
- //
- if (Bits != 0) {
- NotifyWarningOptRequiredCapGen3 ((*State->PortList)[i].NodeID,
- (*State->PortList)[i].HostLink,
- (*State->PortList)[i].HostDepth,
- State);
- }
- }
- }
- // Enable Unit ID Clumping if supported.
- if (State->IsUsingUnitIdClumping) {
- if (((*State->PortList)[i].ClumpingSupport != HT_CLUMPING_PASSIVE) &&
- ((*State->PortList)[i].ClumpingSupport != HT_CLUMPING_DISABLE)) {
- Bits = (*State->PortList)[i].ClumpingSupport;
- if ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) {
- State->Nb->SetLinkUnitIdClumping (
- (*State->PortList)[i].NodeID,
- (*State->PortList)[i].Link,
- (*State->PortList)[i].ClumpingSupport,
- State->Nb
- );
- } else {
- if (DoesDeviceHaveHtSubtypeCap (LinkBase, HT_UNITID_CAPABILITY, &Reg, State)) {
- Reg.Address.Register += HTUNIT_ENABLE_REG;
- LibAmdPciWriteBits (Reg, 31, 0, &Bits, State->ConfigHandle);
- } else {
- // If we found one when gathering support, we have to find one now.
- ASSERT (FALSE);
- }
- }
- }
- }
- }
-}
-
-/*------------------------------------------------------------------------------------------*/
-/**
- * Find a specific HT capability type.
- *
- * Search all the PCI Config space capabilities on any type of device for an
- * HT capability of the specific subtype.
- *
- * @param[in] DevicePointer A PCI Config address somewhere in the device config space
- * @param[in] CapSubType The HT capability subtype to find
- * @param[out] CapabilityBase The Config space base address of the capability, if found.
- * @param[in] State Our State
- *
- * @retval TRUE the capability was found
- * @retval FALSE the capability was not found
- */
-BOOLEAN
-DoesDeviceHaveHtSubtypeCap (
- IN PCI_ADDR DevicePointer,
- IN UINT8 CapSubType,
- OUT PCI_ADDR *CapabilityBase,
- IN STATE_DATA *State
- )
-{
- BOOLEAN IsFound;
- BOOLEAN IsDone;
- PCI_ADDR Reg;
- UINT32 Temp;
- UINT32 RegSubType;
- UINT32 RegSubTypeMask;
-
- // Set the PCI Config Space base and the match value.
- IsFound = FALSE;
- IsDone = FALSE;
- Reg = DevicePointer;
- Reg.Address.Register = 0;
- if (CapSubType < (HT_HOST_CAPABILITY + 1)) {
- // HT Interface sub type
- RegSubType = ((UINT32) (CapSubType << 29) | (UINT32)8);
- RegSubTypeMask = HT_INTERFACE_CAP_SUBTYPE_MASK;
- } else {
- // Other HT capability subtype
- RegSubType = ((UINT32) (CapSubType << 27) | (UINT32)8);
- RegSubTypeMask = HT_CAP_SUBTYPE_MASK;
- }
- (*CapabilityBase).AddressValue = (UINT32)ILLEGAL_SBDFO;
-
- // Find it
- do {
- LibAmdPciFindNextCap (&Reg, State->ConfigHandle);
- if (Reg.AddressValue != (UINT32)ILLEGAL_SBDFO) {
- LibAmdPciRead (AccessWidth32, Reg, &Temp, State->ConfigHandle);
- // HyperTransport and subtype capability ?
- if ((Temp & RegSubTypeMask) == RegSubType) {
- *CapabilityBase = Reg;
- IsFound = TRUE;
- }
- // Some other capability, keep looking
- } else {
- // Not there
- IsDone = TRUE;
- }
- } while (!IsFound && !IsDone);
-
- return IsFound;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Retry must be enabled on all coherent links if it is enabled on any coherent links.
- *
- * @HtFeatMethod{::F_SET_LINK_DATA}
- *
- * Effectively, this means HT3 on some links cannot be mixed with HT1 on others.
- * Scan the CPU to CPU links for this condition and limit those frequencies to HT1
- * if it is detected.
- * (Non-coherent links are independent.)
- *
- * @param[in,out] State global state, port frequency settings.
- *
- * @retval TRUE Fixup occurred, all coherent links HT1
- * @retval FALSE No changes
- */
-BOOLEAN
-IsCoherentRetryFixup (
- IN STATE_DATA *State
- )
-{
- UINT8 Freq;
- UINT8 i;
- UINT8 DetectedFrequencyState;
- BOOLEAN IsMixed;
- UINT32 Temp;
-
- //
- // detectedFrequencyState:
- // 0 - initial state
- // 1 - HT1 Frequencies detected
- // 2 - HT3 Frequencies detected
- //
- IsMixed = FALSE;
- DetectedFrequencyState = 0;
-
- // Scan coherent links for a mix of HT3 / HT1
- for (i = 0; i < (State->TotalLinks * 2); i += 2) {
- if (((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) && ((*State->PortList)[i + 1].Type == PORTLIST_TYPE_CPU)) {
- // At this point, Frequency of port [i+1] must equal [i], so just check one of them.
- switch (DetectedFrequencyState) {
- case 0:
- // Set current state to indicate what link frequency we found first
- if ((*State->PortList)[i].SelFrequency > HT_FREQUENCY_1000M) {
- // HT3 frequencies
- DetectedFrequencyState = 2;
- } else {
- // HT1 frequencies
- DetectedFrequencyState = 1;
- }
- break;
- case 1:
- // If HT1 frequency detected, fail any HT3 frequency
- if ((*State->PortList)[i].SelFrequency > HT_FREQUENCY_1000M) {
- IsMixed = TRUE;
- }
- break;
- case 2:
- // If HT3 frequency detected, fail any HT1 frequency
- if ((*State->PortList)[i].SelFrequency <= HT_FREQUENCY_1000M) {
- IsMixed = TRUE;
- }
- break;
- default:
- ASSERT (FALSE);
- }
- if (IsMixed) {
- // Don't need to keep checking after we find a mix.
- break;
- }
- }
- }
-
- if (IsMixed) {
- for (i = 0; i < (State->TotalLinks * 2); i += 2) {
- if (((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) && ((*State->PortList)[i + 1].Type == PORTLIST_TYPE_CPU)) {
- // Limit coherent links to HT 1 frequencies.
- Temp = (*State->PortList)[i].CompositeFrequencyCap & (*State->PortList)[i + 1].CompositeFrequencyCap;
- Temp &= HT_FREQUENCY_LIMIT_HT1_ONLY;
- ASSERT (Temp != 0);
- (*State->PortList)[i].CompositeFrequencyCap = Temp;
- (*State->PortList)[i + 1].CompositeFrequencyCap = Temp;
- Freq = LibAmdBitScanReverse (Temp);
- (*State->PortList)[i].SelFrequency = Freq;
- (*State->PortList)[i + 1].SelFrequency = Freq;
- }
- }
- }
- return (IsMixed);
-}
diff --git a/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatOptimization.h b/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatOptimization.h
deleted file mode 100644
index d6d4764..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatOptimization.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Link Optimization Feature.
- *
- * Contains interface for Link Optimization.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _HT_FEAT_OPTIMIZATION_H_
-#define _HT_FEAT_OPTIMIZATION_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-/**
- * Translate a desired width setting to the bits to set in the register field.
- */
-UINT8
-ConvertWidthToBits (
- IN UINT8 Value
- );
-
-/**
- * Access HT Link Control Register.
- *
- */
-VOID
-SetHtControlRegisterBits (
- IN PCI_ADDR Reg,
- IN UINT8 HiBit,
- IN UINT8 LoBit,
- IN UINT32 *Value,
- IN STATE_DATA *State
- );
-
-/**
- * Get Link features into system data structure.
- *
- */
-VOID
-GatherLinkData (
- IN STATE_DATA *State
- );
-
-/**
- * Optimize Links.
- *
- */
-VOID
-SelectOptimalWidthAndFrequency (
- IN OUT STATE_DATA *State
- );
-
-/**
- * Change the hardware state for all Links according to the now optimized data in the
- * port list data structure.
- *
- */
-VOID
-SetLinkData (
- IN STATE_DATA *State
- );
-
-/**
- * Retry must be enabled on all coherent links if it is enabled on any coherent links.
- *
- */
-BOOLEAN
-IsCoherentRetryFixup (
- IN STATE_DATA *State
- );
-
-/**
- * Find a specific HT capability type.
- *
- * @retval FALSE the capability was not found
- */
-BOOLEAN
-DoesDeviceHaveHtSubtypeCap (
- IN PCI_ADDR DevicePointer,
- IN UINT8 CapSubType,
- OUT PCI_ADDR *CapabilityBase,
- IN STATE_DATA *State
- );
-
-#endif /* _HT_FEAT_OPTIMIZATION_H_ */
diff --git a/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatRouting.c b/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatRouting.c
deleted file mode 100644
index cad0743..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatRouting.c
+++ /dev/null
@@ -1,493 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Routing Routines
- *
- * Contains routines for isomorphic topology matching,
- * routing determination, and routing initialization.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35978 $ @e \$Date: 2010-08-07 02:18:50 +0800 (Sat, 07 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "htInterface.h"
-#include "htNotify.h"
-#include "htNb.h"
-#include "htGraph.h"
-#include "htFeatRouting.h"
-#include "htTopologies.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_FEATURES_HTFEATROUTING_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-typedef struct {
- UINT8 **CurrentPosition;
- BOOLEAN IsCustomList;
-} TOPOLOGY_CONTEXT;
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/***************************************************************************
- *** ISOMORPHISM BASED ROUTING TABLE GENERATION CODE ***
- ***************************************************************************/
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Return the Link on source Node which connects to target Node
- *
- * @param[in] SourceNode The Node on which to find the Link
- * @param[in] TargetNode The Link will connect to this Node
- * @param[in] State Our global state
- *
- * @return the Link to target
- */
-UINT8
-STATIC
-FindLinkToNode (
- IN UINT8 SourceNode,
- IN UINT8 TargetNode,
- IN STATE_DATA *State
- )
-{
- UINT8 TargetLink;
- UINT8 k;
-
- // A node linked to itself is not a supported topology graph, this is probably an error in the
- // topology data. There is not going to be a portlist match for it.
- ASSERT (SourceNode != TargetNode);
- TargetLink = INVALID_LINK;
- for (k = 0; k < State->TotalLinks*2; k += 2) {
- if (((*State->PortList)[k].NodeID == SourceNode) && ((*State->PortList)[k + 1].NodeID == TargetNode)) {
- TargetLink = (*State->PortList)[k].Link;
- break;
- } else if (((*State->PortList)[k + 1].NodeID == SourceNode) && ((*State->PortList)[k].NodeID == TargetNode)) {
- TargetLink = (*State->PortList)[k + 1].Link;
- break;
- }
- }
- ASSERT (TargetLink != INVALID_LINK);
-
- return TargetLink;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Is graphA isomorphic to graphB?
- *
- * If this function returns true, then Perm will contain the permutation
- * required to transform graphB into graphA.
- * We also use the degree of each Node, that is the number of connections it has, to
- * speed up rejection of non-isomorphic graphs (if there is a Node in graphA with n
- * connections, there must be at least one unmatched in graphB with n connections).
- *
- * @param[in] Node the discovered Node which we are trying to match
- * with a permutation the topology
- * @param[in,out] State our global state, degree and adjacency matrix,
- * output a permutation if successful
- * @retval TRUE the graphs are isomorphic
- * @retval FALSE the graphs are not isomorphic
- *
- */
-BOOLEAN
-STATIC
-IsIsomorphic (
- IN UINT8 Node,
- IN OUT STATE_DATA *State
- )
-{
- UINT8 j;
- UINT8 k;
- UINT8 Nodecnt;
-
- // We have only been called if Nodecnt == pSelected->size !
- Nodecnt = State->NodesDiscovered + 1;
-
- if (Node != Nodecnt) {
- // Keep building the permutation
- for (j = 0; j < Nodecnt; j++) {
- // Make sure the degree matches
- if (State->Fabric->SysDegree[Node] != State->Fabric->DbDegree[j]) {
- continue;
- }
-
- // Make sure that j hasn't been used yet (ought to use a "used"
- // array instead, might be faster)
- for (k = 0; k < Node; k++) {
- if (State->Fabric->Perm[k] == j) {
- break;
- }
- }
- if (k != Node) {
- continue;
- }
- State->Fabric->Perm[Node] = j;
- if (IsIsomorphic (Node + 1, State)) {
- return TRUE;
- }
- }
- return FALSE;
- } else {
- // Test to see if the permutation is isomorphic
- for (j = 0; j < Nodecnt; j++) {
- for (k = 0; k < Nodecnt; k++) {
- if (State->Fabric->SysMatrix[j][k] != State->Fabric->DbMatrix[State->Fabric->Perm[j]][State->Fabric->Perm[k]] ) {
- return FALSE;
- }
- }
- }
- return TRUE;
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Set Topology List iterator context to the Beginning and provide the first topology.
- *
- * Check the interface for a custom topology list. If one is found, set context to the
- * first item, and return that item. Otherwise return the first item in the built in list.
- *
- * @param[in,out] TopologyContextHandle Initialize this context to beginning of lists.
- * @param[out] NextTopology The next topology, NULL if end.
- * @param[in] State Access to interface, handles.
- *
- */
-VOID
-STATIC
-BeginTopologies (
- OUT TOPOLOGY_CONTEXT *TopologyContextHandle,
- OUT UINT8 **NextTopology,
- IN STATE_DATA *State
- )
-{
- if (State->HtBlock->Topolist != NULL) {
- // Start with a custom list
- TopologyContextHandle->CurrentPosition = State->HtBlock->Topolist;
- TopologyContextHandle->IsCustomList = TRUE;
- } else {
- // Start with the built in list
- GetAmdTopolist (&TopologyContextHandle->CurrentPosition);
- TopologyContextHandle->IsCustomList = FALSE;
- }
- *NextTopology = *TopologyContextHandle->CurrentPosition;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Iterate through available topologies.
- *
- * Increment to the next list item. If we are doing a custom list, when we reach the end
- * switch to the built in list.
- *
- * @param[in,out] TopologyContextHandle Maintain iterator's context from one call to the next
- * @param[out] NextTopology The next topology, NULL if end.
- *
- */
-VOID
-STATIC
-GetNextTopology (
- IN OUT TOPOLOGY_CONTEXT *TopologyContextHandle,
- OUT UINT8 **NextTopology
- )
-{
- // Not valid to continue calling this routine after reaching the end.
- ASSERT (TopologyContextHandle->CurrentPosition != NULL);
-
- if (TopologyContextHandle->IsCustomList) {
- // We are iterating the custom list from the interface.
- TopologyContextHandle->CurrentPosition++;
- if (*TopologyContextHandle->CurrentPosition == NULL) {
- // We are at the end of the custom list, switch to the built in list.
- TopologyContextHandle->IsCustomList = FALSE;
- GetAmdTopolist (&TopologyContextHandle->CurrentPosition);
- }
- } else {
- // We are iterating the built in list
- TopologyContextHandle->CurrentPosition++;
- // If we are at the end of the built in list, NextTopology == NULL is the AtEnd.
- }
- *NextTopology = *TopologyContextHandle->CurrentPosition;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Using the description of the fabric topology we discovered, try to find a match
- * among the supported topologies.
- *
- * @HtFeatMethod{::F_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES}
- *
- * A supported topology description matches the discovered fabric if the Nodes can be
- * matched in such a way that all the Nodes connected in one set are exactly the
- * Nodes connected in the other (formally, that the graphs are isomorphic). Which
- * Links are used is not really important to matching. If the graphs match, then
- * there is a permutation of one that translates the Node positions and Linkages to
- * the other.
- *
- * In order to make the isomorphism test efficient, we test for matched number of Nodes
- * (a 4 Node fabric is not isomorphic to a 2 Node topology), and provide degrees of Nodes
- * to the isomorphism test.
- *
- * The generic routing table solution for any topology is predetermined and represented
- * as part of the topology. The permutation we computed tells us how to interpret the
- * routing onto the fabric we discovered. We do this working backward from the last
- * Node discovered to the BSP, writing the routing tables as we go.
- *
- * @param[in,out] State the discovered fabric, degree matrix, permutation
- *
- */
-VOID
-LookupComputeAndLoadRoutingTables (
- IN OUT STATE_DATA *State
- )
-{
- TOPOLOGY_CONTEXT TopologyContextHandle;
- UINT8 *Selected;
- UINT8 Size;
- UINT8 PairCounter;
- UINT8 ReqTargetLink;
- UINT8 RspTargetLink;
- UINT8 ReqTargetNode;
- UINT8 RspTargetNode;
- UINT8 AbstractBcTargetNodes;
- UINT32 BcTargetLinks;
- UINT8 NodeCounter;
- UINT8 NodeBeingRouted;
- UINT8 NodeRoutedTo;
- UINT8 BroadcastSourceNode;
-
- Size = State->NodesDiscovered + 1;
- BeginTopologies (&TopologyContextHandle, &Selected, State);
- while (Selected != NULL) {
- if (GraphHowManyNodes (Selected) == Size) {
- // Build Degree vector and Adjacency Matrix for this entry
- for (NodeCounter = 0; NodeCounter < Size; NodeCounter++) {
- State->Fabric->DbDegree[NodeCounter] = 0;
- for (PairCounter = 0; PairCounter < Size; PairCounter++) {
- if (GraphIsAdjacent (Selected, NodeCounter, PairCounter)) {
- State->Fabric->DbMatrix[NodeCounter][PairCounter] = TRUE;
- State->Fabric->DbDegree[NodeCounter]++;
- } else {
- State->Fabric->DbMatrix[NodeCounter][PairCounter] = FALSE;
- }
- }
- }
-
- if (IsIsomorphic (0, State)) {
- break; // A matching topology was found
- }
- }
- GetNextTopology (&TopologyContextHandle, &Selected);
- }
-
- if (Selected != NULL) {
- // Compute the reverse Permutation
- for (NodeCounter = 0; NodeCounter < Size; NodeCounter++) {
- State->Fabric->ReversePerm[State->Fabric->Perm[NodeCounter]] = NodeCounter;
- }
-
- // Start with the last discovered Node, and move towards the BSP
- for (NodeCounter = 0; NodeCounter < Size; NodeCounter++) {
- NodeBeingRouted = ((Size - 1) - NodeCounter);
- for (NodeRoutedTo = 0; NodeRoutedTo < Size; NodeRoutedTo++) {
- BcTargetLinks = 0;
- AbstractBcTargetNodes = GraphGetBc (Selected, State->Fabric->Perm[NodeBeingRouted], State->Fabric->Perm[NodeRoutedTo]);
-
- for (BroadcastSourceNode = 0; BroadcastSourceNode < MAX_NODES; BroadcastSourceNode++) {
- if ((AbstractBcTargetNodes & ((UINT32)1 << BroadcastSourceNode)) != 0) {
- // Accepting broadcast from yourself is handled in Nb, so in the topology graph it is an error.
- ASSERT (NodeBeingRouted != State->Fabric->ReversePerm[BroadcastSourceNode]);
- BcTargetLinks |= (UINT32)1 << FindLinkToNode (NodeBeingRouted, State->Fabric->ReversePerm[BroadcastSourceNode], State);
- }
- }
-
- if (NodeBeingRouted == NodeRoutedTo) {
- ReqTargetLink = ROUTE_TO_SELF;
- RspTargetLink = ROUTE_TO_SELF;
- } else {
- ReqTargetNode = GraphGetReq (Selected, State->Fabric->Perm[NodeBeingRouted], State->Fabric->Perm[NodeRoutedTo]);
- ReqTargetLink = FindLinkToNode (NodeBeingRouted, State->Fabric->ReversePerm[ReqTargetNode], State);
-
- RspTargetNode = GraphGetRsp (Selected, State->Fabric->Perm[NodeBeingRouted], State->Fabric->Perm[NodeRoutedTo]);
- RspTargetLink = FindLinkToNode (NodeBeingRouted, State->Fabric->ReversePerm[RspTargetNode], State);
- }
- State->Nb->WriteFullRoutingTable (NodeBeingRouted, NodeRoutedTo, ReqTargetLink, RspTargetLink, BcTargetLinks, State->Nb);
- }
- // Clean up discovery 'footprint' that otherwise remains in the routing table. It didn't hurt
- // anything, but might cause confusion during debug and validation. Do this by setting the
- // route back to all self routes. Since it's the Node that would be one more than actually installed,
- // this only applies if less than MaxNodes were found.
- //
- if (Size < MAX_NODES) {
- State->Nb->WriteFullRoutingTable (NodeBeingRouted, Size, ROUTE_TO_SELF, ROUTE_TO_SELF, 0, State->Nb);
- }
- }
- } else {
- //
- // No Matching Topology was found
- // Error Strategy:
- // Auto recovery doesn't seem likely, Force boot as 1P.
- // For reporting, logging, provide number of Nodes
- // If not implemented or returns, boot as BSP uniprocessor.
- //
- // This can be caused by not supplying an additional topology list, if your board is not one of the built-in topologies.
- //
- NotifyErrorCohNoTopology (State->NodesDiscovered, State);
- IDS_ERROR_TRAP;
- // Force 1P
- State->NodesDiscovered = 0;
- State->TotalLinks = 0;
- State->Nb->EnableRoutingTables (0, State->Nb);
- State->HtInterface->CleanMapsAfterError (State);
- }
- // Save the topology pointer, or NULL, for other features
- State->Fabric->MatchedTopology = Selected;
- IDS_HDT_CONSOLE (
- HT_TRACE,
- "System routed as %s.\n",
- ((TopologyContextHandle.IsCustomList) ?
- "custom topology" :
- (((Selected == amdHtTopologySingleNode) || (Selected == NULL)) ?
- "single node" :
- ((Selected == amdHtTopologyDualNode) ?
- "dual node" :
- ((Selected == amdHtTopologyFourSquare) ?
- "four node box" :
- ((Selected == amdHtTopologyFourKite) ?
- "four node kite" :
- ((Selected == amdHtTopologyFourFully) ?
- "fully connected four-way" :
- ((Selected == amdHtTopologyEightDoubloon) ?
- "MCM max performance" :
- ((Selected == amdHtTopologyEightTwinFullyFourWays) ?
- "MCM max I/O" :
- "AMD builtin topology"))))))))
- );
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Make a Hop Count Table for the installed topology.
- *
- * @HtFeatMethod{::F_MAKE_HOP_COUNT_TABLE}
- *
- * For SLIT, create a node x node matrix with the number of hops. We can do this
- * using the topology and the permutation, counting the nodes visited in the routes between
- * nodes.
- *
- * @param[in,out] State access topology, permutation, update hop table
- *
- */
-VOID
-MakeHopCountTable (
- IN OUT STATE_DATA *State
- )
-{
- UINT8 Origin;
- UINT8 Target;
- UINT8 Current;
- UINT8 Hops;
- UINT8 Size;
-
- ASSERT (State->Fabric != NULL);
- if (State->HopCountTable != NULL) {
- if (State->Fabric->MatchedTopology != NULL) {
- Size = GraphHowManyNodes (State->Fabric->MatchedTopology);
- State->HopCountTable->Size = Size;
- //
- // For each node, targeting each node, follow the request path through the database graph,
- // counting the number of edges.
- //
- for (Origin = 0; Origin < Size; Origin++) {
- for (Target = 0; Target < Size; Target++) {
- // If both nodes are the same the answer will be zero
- Hops = 0;
- // Current starts as the database node corresponding to system node Origin.
- Current = State->Fabric->Perm[Origin];
- // Stop if Current is the database node corresponding to system node Target
- while (Current != State->Fabric->Perm[Target]) {
- // This is a hop, so count it. Move Current to the next intermediate database node.
- Hops++;
- Current = GraphGetReq (State->Fabric->MatchedTopology, Current, State->Fabric->Perm[Target]);
- }
- // Put the hop count in the table.
- State->HopCountTable->Hops[ ((Origin * Size) + Target)] = Hops;
- }
- }
- }
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatRouting.h b/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatRouting.h
deleted file mode 100644
index 264434b..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatRouting.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Routing Feature Interface.
- *
- * Interfaces to routing and isomorphism routines.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _HT_FEAT_ROUTING_H_
-#define _HT_FEAT_ROUTING_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-/**
- * Using the description of the fabric topology we discovered, try to find a match
- * among the supported topologies.
- *
- */
-VOID
-LookupComputeAndLoadRoutingTables (
- IN OUT STATE_DATA *State
- );
-
-/**
- * Make a Hop Count Table for the installed topology.
- *
- */
-VOID
-MakeHopCountTable (
- IN OUT STATE_DATA *State
- );
-
-#endif /* _HT_FEAT_ROUTING_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatSets.c b/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatSets.c
deleted file mode 100644
index ec2f164..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatSets.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * HyperTransport feature sets initializers.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "OptionsHt.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "CommonReturns.h"
-#include "htFeatDynamicDiscovery.h"
-#include "htFeatRouting.h"
-#include "htFeatNoncoherent.h"
-#include "htFeatOptimization.h"
-#include "htFeatGanging.h"
-#include "htFeatSublinks.h"
-#include "htFeatTrafficDistribution.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_FEATURES_HTFEATSETS_FILECODE
-extern CONST OPTION_HT_CONFIGURATION OptionHtConfiguration;
-
-/**
- * Initializer for the default feature set implementation,
- * full features.
- */
-CONST HT_FEATURES ROMDATA HtFeaturesDefault =
-{
- CoherentDiscovery,
- LookupComputeAndLoadRoutingTables,
- MakeHopCountTable,
- ProcessLink,
- GatherLinkData,
- SelectOptimalWidthAndFrequency,
- RegangLinks,
- SubLinkRatioFixup,
- IsCoherentRetryFixup,
- SetLinkData,
- TrafficDistribution,
- SetHtControlRegisterBits,
- ConvertWidthToBits
-};
-
-/**
- * Initializer for the non-coherent only build option.
- */
-CONST HT_FEATURES ROMDATA HtFeaturesNonCoherentOnly =
-{
- (PF_COHERENT_DISCOVERY)CommonVoid,
- (PF_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES)CommonVoid,
- (PF_MAKE_HOP_COUNT_TABLE)CommonVoid,
- ProcessLink,
- GatherLinkData,
- SelectOptimalWidthAndFrequency,
- (PF_REGANG_LINKS)CommonVoid,
- (PF_SUBLINK_RATIO_FIXUP)CommonVoid,
- (PF_IS_COHERENT_RETRY_FIXUP)CommonReturnFalse,
- SetLinkData,
- (PF_TRAFFIC_DISTRIBUTION)CommonVoid,
- SetHtControlRegisterBits,
- ConvertWidthToBits
-};
diff --git a/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatSublinks.c b/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatSublinks.c
deleted file mode 100644
index 4c4d656..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatSublinks.c
+++ /dev/null
@@ -1,232 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * SubLink management Routines.
- *
- * Contains routines for subLink frequency ratios.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "amdlib.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "IdsHt.h"
-#include "htFeatSublinks.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_FEATURES_HTFEATSUBLINKS_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-typedef struct {
- UINT8 HiFreq;
- UINT8 LoFreq;
-} VALID_RATIO_ITEM;
-
-STATIC CONST VALID_RATIO_ITEM ROMDATA ValidRatioList[] =
-{
- {HT_FREQUENCY_3200M, HT_FREQUENCY_1600M}, // 3200MHz / 1600MHz 2:1
- {HT_FREQUENCY_3200M, HT_FREQUENCY_800M}, // 3200MHz / 800MHz 4:1
- {HT_FREQUENCY_3200M, HT_FREQUENCY_400M}, // 3200MHz / 400MHz 8:1
- {HT_FREQUENCY_2800M, HT_FREQUENCY_1400M}, // 2800MHz / 1400MHz 2:1
- {HT_FREQUENCY_2400M, HT_FREQUENCY_1200M}, // 2400MHz / 1200MHz 2:1
- {HT_FREQUENCY_2400M, HT_FREQUENCY_600M}, // 2400MHz / 600MHz 4:1
- {HT_FREQUENCY_2400M, HT_FREQUENCY_400M}, // 2400MHz / 400MHz 6:1
- {HT_FREQUENCY_2000M, HT_FREQUENCY_1000M}, // 2000MHz / 1000MHz 2:1
- {HT_FREQUENCY_1600M, HT_FREQUENCY_800M}, // 1600MHz / 800MHz 2:1
- {HT_FREQUENCY_1600M, HT_FREQUENCY_400M}, // 1600MHz / 400MHz 4:1
- {HT_FREQUENCY_1600M, HT_FREQUENCY_200M}, // 1600MHz / 200Mhz 8:1
- {HT_FREQUENCY_1200M, HT_FREQUENCY_600M}, // 1200MHz / 600MHz 2:1
- {HT_FREQUENCY_1200M, HT_FREQUENCY_200M}, // 1200MHz / 200MHz 6:1
- {HT_FREQUENCY_800M, HT_FREQUENCY_400M}, // 800MHz / 400MHz 2:1
- {HT_FREQUENCY_800M, HT_FREQUENCY_200M}, // 800MHz / 200MHz 4:1
- {HT_FREQUENCY_400M, HT_FREQUENCY_200M} // 400MHz / 200MHz 2:1
-};
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/***************************************************************************
- *** Link Optimization ***
- ***************************************************************************/
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Iterate through all Links, checking the frequency of each subLink pair.
- *
- * @HtFeatMethod{::F_SUBLINK_RATIO_FIXUP}
- *
- * Make the adjustment to the port list data so that the frequencies
- * are at a valid ratio, reducing frequency as needed to achieve
- * this. (All Links support the minimum 200 MHz frequency.) Repeat
- * the above until no adjustments are needed.
- * @note no hardware state changes in this routine.
- *
- * @param[in,out] State Link state and port list
- *
- */
-VOID
-SubLinkRatioFixup (
- IN OUT STATE_DATA *State
- )
-{
- UINT8 i;
- UINT8 j;
- UINT8 ValidRatioItem;
- BOOLEAN Changes;
- BOOLEAN Downgrade;
- UINT8 HiIndex;
- UINT8 HiFreq;
- UINT8 LoFreq;
-
- UINT32 Temp;
-
- do {
- Changes = FALSE;
- for (i = 0; i < State->TotalLinks*2; i++) {
- // Must be a CPU Link
- if ((*State->PortList)[i].Type != PORTLIST_TYPE_CPU) {
- continue;
- }
- // Only look for subLink1's
- if ((*State->PortList)[i].Link < 4) {
- continue;
- }
-
- for (j = 0; j < State->TotalLinks*2; j++) {
- // Step 1. Find the matching subLink0
- if ((*State->PortList)[j].Type != PORTLIST_TYPE_CPU) {
- continue;
- }
- if ((*State->PortList)[j].NodeID != (*State->PortList)[i].NodeID) {
- continue;
- }
- if ((*State->PortList)[j].Link != ((*State->PortList)[i].Link & 0x03)) {
- continue;
- }
-
- // Step 2. Check for an illegal frequency ratio
- if ((*State->PortList)[i].SelFrequency >= (*State->PortList)[j].SelFrequency) {
- HiIndex = i;
- HiFreq = (*State->PortList)[i].SelFrequency;
- LoFreq = (*State->PortList)[j].SelFrequency;
- } else {
- HiIndex = j;
- HiFreq = (*State->PortList)[j].SelFrequency;
- LoFreq = (*State->PortList)[i].SelFrequency;
- }
-
- // The frequencies are 1:1, no need to do anything
- if (HiFreq == LoFreq) {
- break;
- }
-
- Downgrade = TRUE;
-
- for (ValidRatioItem = 0; ValidRatioItem < (sizeof (ValidRatioList) / sizeof (VALID_RATIO_ITEM)); ValidRatioItem++) {
- if ((HiFreq == ValidRatioList[ValidRatioItem].HiFreq) &&
- (LoFreq == ValidRatioList[ValidRatioItem].LoFreq)) {
- Downgrade = FALSE;
- break;
- }
- }
-
- // Step 3. Downgrade the higher of the two frequencies, and set Changes to FALSE
- if (Downgrade) {
- // Although the problem was with the port specified by hiIndex, we need to
- // Downgrade both ends of the Link.
- HiIndex = HiIndex & 0xFE; // Select the 'upstream' (i.e. even) port
-
- Temp = (*State->PortList)[HiIndex].CompositeFrequencyCap;
-
- // Remove HiFreq from the list of valid frequencies
- Temp = Temp & ~((UINT32)1 << HiFreq);
- ASSERT (Temp != 0);
- (*State->PortList)[HiIndex].CompositeFrequencyCap = (UINT32)Temp;
- (*State->PortList)[HiIndex + 1].CompositeFrequencyCap = (UINT32)Temp;
-
- HiFreq = LibAmdBitScanReverse (Temp);
-
- (*State->PortList)[HiIndex].SelFrequency = HiFreq;
- (*State->PortList)[HiIndex + 1].SelFrequency = HiFreq;
-
- Changes = TRUE;
- }
- }
- }
- } while (Changes); // Repeat until a valid configuration is reached
-}
diff --git a/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatSublinks.h b/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatSublinks.h
deleted file mode 100644
index 864dfb5..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatSublinks.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * SubLink Interface.
- *
- * Contains interface to subLink management feature, for unganged subLinks.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _HT_FEAT_SUBLINKS_H_
-#define _HT_FEAT_SUBLINKS_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-/**
- * Iterate through all Links, checking the frequency of each subLink pair.
- *
- */
-VOID
-SubLinkRatioFixup (
- IN OUT STATE_DATA *State
- );
-
-#endif /* _HT_FEAT_SUBLINKS_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatTrafficDistribution.c b/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatTrafficDistribution.c
deleted file mode 100644
index 0513578..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatTrafficDistribution.c
+++ /dev/null
@@ -1,278 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Traffic Distribution Routines.
- *
- * Contains routines for traffic distribution
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35978 $ @e \$Date: 2010-08-07 02:18:50 +0800 (Sat, 07 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "htInterface.h"
-#include "htNb.h"
-#include "htNotify.h"
-#include "htFeatTrafficDistribution.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_FEATURES_HTFEATTRAFFICDISTRIBUTION_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Identify Links which can have traffic distribution.
- *
- * @HtFeatMethod{::F_TRAFFIC_DISTRIBUTION}
- *
- * If there are redundant links between any nodes, traffic distribution allows the
- * redundant links to be used to improve performance.
- *
- * There are two types of traffic distribution. Their use is mutually exclusive, both
- * can not be used at once.
- *
- * Coherent Traffic Distribution is for systems of exactly two nodes only. All links must
- * be symmetrical (the same width). As many links as are connected can be distributed over.
- *
- * Link Pair Traffic Distribution works with redundant pairs of links between any two nodes,
- * it does not matter how many nodes are in the system or how many have a redundant link pair.
- * A node can have redundant link pairs with more than one other node.
- * The link pair can be asymmetric, the largest link must be used as the master. However,
- * between any pair of nodes there is only one pair of redundant links, and there is a limit
- * to the total number of pairs each node can have. So not all links will necessarily be
- * made usable.
- *
- * @param[in] State port list data
- */
-VOID
-TrafficDistribution (
- IN STATE_DATA *State
- )
-{
- UINT32 Links01;
- UINT32 Links10;
- UINT8 LinkCount;
- UINT8 i;
- UINT8 LastLink;
- BOOLEAN IsAsymmetric;
- UINT8 RedundantLinkCount[MAX_NODES][MAX_NODES];
- UINT8 MasterLinkPort[MAX_NODES][MAX_NODES];
- UINT8 AlternateLinkPort[MAX_NODES][MAX_NODES];
- UINT8 NodeA;
- UINT8 NodeB;
- UINT8 PairCount;
-
- LastLink = 0xFF;
- IsAsymmetric = FALSE;
-
- // Traffic Distribution is only used when there are exactly two Nodes in the system
- // and when all the links are symmetric, same width.
- if ((State->NodesDiscovered + 1) == 2) {
- Links01 = 0;
- Links10 = 0;
- LinkCount = 0;
- for (i = 0; i < (State->TotalLinks * 2); i += 2) {
- if (((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) &&
- ((*State->PortList)[i + 1].Type == PORTLIST_TYPE_CPU)) {
- if ((LastLink != 0xFF) &&
- ((*State->PortList)[i].SelWidthOut != (*State->PortList)[LastLink].SelWidthOut) &&
- ((*State->PortList)[i + 1].SelWidthOut != (*State->PortList)[LastLink + 1].SelWidthOut)) {
- IsAsymmetric = TRUE;
- break;
- }
- Links01 |= (UINT32)1 << (*State->PortList)[i].Link;
- Links10 |= (UINT32)1 << (*State->PortList)[i + 1].Link;
- LinkCount++;
- LastLink = i;
- }
- }
- ASSERT (LinkCount != 0);
- // Don't setup Traffic Distribution if only one Link is being used or there were asymmetric widths
- if ((LinkCount != 1) && !IsAsymmetric) {
- IDS_HDT_CONSOLE (HT_TRACE, "Applying coherent traffic distribution.\n");
- State->Nb->WriteTrafficDistribution (Links01, Links10, State->Nb);
- // If we did Traffic Distribution, we must not do Link Pair, so get out of here.
- return;
- }
- }
- // Either there are more than two nodes, Asymmetric links, or no redundant links.
- // See if we can use Link Pair Traffic Distribution
- LibAmdMemFill (&RedundantLinkCount, 0, (MAX_NODES * MAX_NODES), State->ConfigHandle);
- for (i = 0; i < (State->TotalLinks * 2); i += 2) {
- if (((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) &&
- ((*State->PortList)[i + 1].Type == PORTLIST_TYPE_CPU)) {
- NodeA = (*State->PortList)[i].NodeID;
- NodeB = (*State->PortList)[i + 1].NodeID;
- if (RedundantLinkCount[NodeA][NodeB] == 0) {
- // This is the first link connecting two nodes
- ASSERT (RedundantLinkCount[NodeB][NodeA] == 0);
- MasterLinkPort[NodeA][NodeB] = i;
- MasterLinkPort[NodeB][NodeA] = i + 1;
- } else {
- // This is a redundant link. If it is larger than the current master link,
- // make it the new master link.
- //
- if (((*State->PortList)[MasterLinkPort[NodeA][NodeB]].SelWidthOut < (*State->PortList)[i].SelWidthOut) &&
- ((*State->PortList)[MasterLinkPort[NodeB][NodeA]].SelWidthOut < (*State->PortList)[i + 1].SelWidthOut)) {
- // Make the old master link the alternate, we don't need to check, it is bigger.
- AlternateLinkPort[NodeA][NodeB] = MasterLinkPort[NodeA][NodeB];
- AlternateLinkPort[NodeB][NodeA] = MasterLinkPort[NodeB][NodeA];
- MasterLinkPort[NodeA][NodeB] = i;
- MasterLinkPort[NodeB][NodeA] = i + 1;
- } else {
- // Since the new link isn't bigger than the Master, check if it is bigger than the alternate,
- // if we have an alternate. If we don't have an alternate yet, make this link the alternate.
- if (RedundantLinkCount[NodeA][NodeB] == 1) {
- AlternateLinkPort[NodeA][NodeB] = i;
- AlternateLinkPort[NodeB][NodeA] = i + 1;
- } else {
- if (((*State->PortList)[AlternateLinkPort[NodeA][NodeB]].SelWidthOut < (*State->PortList)[i].SelWidthOut) &&
- ((*State->PortList)[AlternateLinkPort[NodeB][NodeA]].SelWidthOut < (*State->PortList)[i + 1].SelWidthOut)) {
- // Warning: the alternate link is an unusable redundant link
- // Then make the new link the alternate link.
- NotifyWarningOptUnusedLinks (
- NodeA,
- (*State->PortList)[AlternateLinkPort[NodeA][NodeB]].Link,
- NodeB,
- (*State->PortList)[AlternateLinkPort[NodeB][NodeA]].Link,
- State
- );
- ASSERT (RedundantLinkCount[NodeB][NodeA] > 1);
- AlternateLinkPort[NodeA][NodeB] = i;
- AlternateLinkPort[NodeB][NodeA] = i + 1;
- } else {
- // Warning the current link is an unusable redundant link
- NotifyWarningOptUnusedLinks (NodeA, (*State->PortList)[i].Link, NodeB, (*State->PortList)[i].Link, State);
- }
- }
- }
- }
- RedundantLinkCount[NodeA][NodeB]++;
- RedundantLinkCount[NodeB][NodeA]++;
- }
- }
- // If we found any, now apply up to 4 per node
- for (NodeA = 0; NodeA < MAX_NODES; NodeA++) {
- PairCount = 0;
- for (NodeB = 0; NodeB < MAX_NODES; NodeB++) {
- if (RedundantLinkCount[NodeA][NodeB] > 1) {
- // Then there is a pair of links (at least, but we only care about the pair not the extras)
- if (PairCount < MAX_LINK_PAIRS) {
- // Program it
- if ((*State->PortList)[MasterLinkPort[NodeA][NodeB]].SelWidthOut
- != (*State->PortList)[AlternateLinkPort[NodeA][NodeB]].SelWidthOut) {
- IsAsymmetric = TRUE;
- } else {
- IsAsymmetric = FALSE;
- }
- State->Nb->WriteLinkPairDistribution (
- NodeA,
- NodeB,
- PairCount,
- IsAsymmetric,
- (*State->PortList)[MasterLinkPort[NodeA][NodeB]].Link,
- (*State->PortList)[AlternateLinkPort[NodeA][NodeB]].Link,
- State->Nb
- );
- PairCount++;
- } else {
- // Warning: More link pairs than can be distributed
- NotifyWarningOptLinkPairExceed (
- NodeA, NodeB,
- (*State->PortList)[MasterLinkPort[NodeA][NodeB]].Link,
- (*State->PortList)[AlternateLinkPort[NodeA][NodeB]].Link,
- State);
- // Disable the link pair from the other node, the analysis loop made sure there
- // can only be a single link pair between a pair of nodes.
- RedundantLinkCount[NodeB][NodeA] = 1;
- }
- }
- }
- IDS_HDT_CONSOLE (
- HT_TRACE,
- ((PairCount != 0) ?
- "Node %d applying %d link pair distributions.\n" :
- ""),
- NodeA,
- PairCount
- );
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatTrafficDistribution.h b/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatTrafficDistribution.h
deleted file mode 100644
index 963435f..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/Features/htFeatTrafficDistribution.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Traffic Distribution Interface.
- *
- * Interface to traffic distribution feature.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _HT_FEAT_TRAFFIC_DISTRIBUTION_H_
-#define _H_TFEAT_TRAFFIC_DISTRIBUTION_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-/**
- * Identify Links which can have traffic distribution.
- *
- */
-VOID
-TrafficDistribution (
- IN STATE_DATA *State
- );
-
-#endif /* _HT_FEAT_TRAFFIC_DISTRIBUTION_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/HT/Features/htIds.c b/src/vendorcode/amd/agesa/Proc/HT/Features/htIds.c
deleted file mode 100644
index 6820824..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/Features/htIds.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD IDS HyperTransport Implementation.
- *
- * Contains AMD AGESA Integrated Debug HT related support.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "IdsHt.h"
-#include "htInterface.h"
-#include "htInterfaceGeneral.h"
-#include "htNb.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-#define FILECODE PROC_HT_FEATURES_HTIDS_FILECODE
-
-
-/*-------------------------------------------------------------------------------------*/
-/**
- * Apply an IDS port override to the desired HT link.
- *
- * The IDS port override allows absolute control of a link's frequency and width, such as
- * would be used for board characterization and test. The IDS backend code is responsible
- * for handling the NV items and building them into a port override list. Here we search
- * that list for any overrides which apply, and update the data used by the HT feature code.
- *
- * @param[in] IsSourcePort Since we handle both ports on a match, only do that if TRUE.
- * @param[in,out] Port0 The PORTLIST item for the first endpoint of a link.
- * @param[in,out] Port1 The PORTLIST item for the second endpoint of a link.
- * @param[in,out] PortOverrideList IN: A pointer to the port override list or NULL,
- * OUT: A pointer to the port override list.
- * @param[in] State access to ht interface and nb support methods.
- *
- */
-VOID
-HtIdsGetPortOverride (
- IN BOOLEAN IsSourcePort,
- IN OUT PORT_DESCRIPTOR *Port0,
- IN OUT PORT_DESCRIPTOR *Port1,
- IN OUT HTIDS_PORT_OVERRIDE_LIST *PortOverrideList,
- IN STATE_DATA *State
- )
-{
- LOCATE_HEAP_PTR LocHeapParams;
- UINT8 SocketA;
- UINT8 SocketB;
- UINT8 PackageLinkA;
- UINT8 PackageLinkB;
- HTIDS_PORT_OVERRIDE_LIST p;
-
- if (IsSourcePort) {
- ASSERT (PortOverrideList != NULL);
- // The caller can cache the override list by providing the pointer (to the heap buffer).
- // If the pointer to the port override list is null, then check if it is on the heap,
- // and update the caller's pointer so it is cached.
- // If the buffer is not in heap, call the IDS backend to get the NV data (which is likely also
- // in heap).
- if (*PortOverrideList == NULL) {
- // locate the table in heap
- LocHeapParams.BufferHandle = IDS_HT_DATA_HANDLE;
- if (HeapLocateBuffer (&LocHeapParams, State->ConfigHandle) == AGESA_SUCCESS) {
- *PortOverrideList = (HTIDS_PORT_OVERRIDE_LIST)LocHeapParams.BufferPtr;
- } else {
- // Ask IDS backend code for the list
- IDS_OPTION_HOOK (IDS_HT_CONTROL, PortOverrideList, State->ConfigHandle);
- }
- }
- ASSERT (*PortOverrideList != NULL);
-
- // Search the port override list to see if there is an override that applies to this link.
- // The match criteria are if either endpoint of the current port list item matches
- // port override.
- p = *PortOverrideList;
- SocketA = State->HtInterface->GetSocketFromMap (Port0->NodeID, State);
- PackageLinkA = State->Nb->GetPackageLink (Port0->NodeID, Port0->Link, State->Nb);
- SocketB = State->HtInterface->GetSocketFromMap (Port1->NodeID, State);
- PackageLinkB = State->Nb->GetPackageLink (Port1->NodeID, Port1->Link, State->Nb);
-
- while ((p != NULL) && (p->Socket != HT_LIST_TERMINAL)) {
- if (((p->Socket == SocketA) || (p->Socket == HT_LIST_MATCH_ANY)) &&
- ((p->Link == PackageLinkA) ||
- ((p->Link == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLinkA))) ||
- ((p->Link == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLinkA)))) ||
- ((p->Socket == SocketB) || (p->Socket == HT_LIST_MATCH_ANY)) &&
- ((p->Link == PackageLinkB) ||
- ((p->Link == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLinkA))) ||
- ((p->Link == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLinkB))))) {
- // Found a match, update width and frequency of both endpoints.
- if (p->WidthIn != HT_LIST_TERMINAL) {
- Port0->SelWidthIn = p->WidthIn;
- Port1->SelWidthOut = p->WidthIn;
- }
- if (p->WidthOut != HT_LIST_TERMINAL) {
- Port0->SelWidthOut = p->WidthOut;
- Port1->SelWidthIn = p->WidthOut;
- }
- if (p->Frequency != HT_LIST_TERMINAL) {
- Port0->SelFrequency = p->Frequency;
- Port1->SelFrequency = p->Frequency;
- }
- break;
- } else {
- p++;
- }
- }
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/HT/NbCommon/htNbCoherent.c b/src/vendorcode/amd/agesa/Proc/HT/NbCommon/htNbCoherent.c
deleted file mode 100644
index d1e923f..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/NbCommon/htNbCoherent.c
+++ /dev/null
@@ -1,492 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Coherent Feature Northbridge routines.
- *
- * Provide access to hardware for routing, coherent discovery.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "htNb.h"
-#include "htNbHardwareFam10.h"
-#include "htNbCoherent.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_NBCOMMON_HTNBCOHERENT_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/***************************************************************************
- *** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS ***
- ***************************************************************************/
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Establish a Temporary route from one Node to another.
- *
- * @HtNbMethod{::F_WRITE_ROUTING_TABLE}
- *
- * This routine will modify the routing tables on the
- * SourceNode to cause it to route both request and response traffic to the
- * targetNode through the specified Link.
- *
- * @note: This routine is to be used for early discovery and initialization. The
- * final routing tables must be loaded some other way because this
- * routine does not address the issue of probes, or independent request
- * response paths.
- *
- * @param[in] Node the Node that will have it's routing tables modified.
- * @param[in] Target For routing to Node target
- * @param[in] Link Link from Node to target
- * @param[in] Nb this northbridge
- */
-VOID
-WriteRoutingTable (
- IN UINT8 Node,
- IN UINT8 Target,
- IN UINT8 Link,
- IN NORTHBRIDGE *Nb
- )
-{
- PCI_ADDR Reg;
- UINT32 Temp;
-
- ASSERT ((Node < MAX_NODES) && (Target < MAX_NODES) && (Link < Nb->MaxLinks));
- Temp = (Nb->SelfRouteResponseMask | Nb->SelfRouteRequestMask) << (Link + 1);
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_00,
- REG_ROUTE0_0X40 + (Target * 4));
- LibAmdPciWrite (AccessWidth32, Reg, &Temp, Nb->ConfigHandle);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Modifies the NodeID register on the target Node
- *
- * @HtNbMethod{::F_WRITE_NODEID}
- *
- * @param[in] Node the Node that will have its NodeID altered.
- * @param[in] NodeID the new value for NodeID
- * @param[in] Nb this northbridge
- */
-VOID
-WriteNodeID (
- IN UINT8 Node,
- IN UINT8 NodeID,
- IN NORTHBRIDGE *Nb
- )
-{
- PCI_ADDR Reg;
- UINT32 Temp;
- Temp = NodeID;
- ASSERT ((Node < MAX_NODES) && (NodeID < MAX_NODES));
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_00,
- REG_NODE_ID_0X60);
- LibAmdPciWriteBits (Reg, 2, 0, &Temp, Nb->ConfigHandle);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Read the Default Link
- *
- * @HtNbMethod{::F_READ_DEFAULT_LINK}
- *
- * Read the DefLnk (the source Link of the current packet) from Node. Since this code
- * is running on the BSP, this should be the Link pointing back towards the BSP.
- *
- * @param[in] Node the Node that will have its NodeID altered.
- * @param[in] Nb this northbridge
- *
- * @return The HyperTransport Link where the request to
- * read the default Link came from.
- */
-UINT8
-ReadDefaultLink (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- )
-{
- UINT32 DefaultLink;
- PCI_ADDR Reg;
- UINT32 Temp;
-
- DefaultLink = 0;
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_00,
- REG_LINK_INIT_CONTROL_0X6C);
-
- ASSERT ((Node < MAX_NODES));
- LibAmdPciReadBits (Reg, 3, 2, &DefaultLink, Nb->ConfigHandle);
- LibAmdPciReadBits (Reg, 8, 8, &Temp, Nb->ConfigHandle);
- DefaultLink |= (Temp << 2);
- return (UINT8)DefaultLink;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Turns routing tables on for a given Node
- *
- * @HtNbMethod{::F_ENABLE_ROUTING_TABLES}
- *
- * @param[in] Node the Node that will have it's routing tables enabled
- * @param[in] Nb this northbridge
- */
-VOID
-EnableRoutingTables (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- )
-{
- PCI_ADDR Reg;
- UINT32 Temp;
- Temp = 0;
- ASSERT ((Node < MAX_NODES));
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_00,
- REG_LINK_INIT_CONTROL_0X6C);
- LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Turns routing tables off for a given Node
- *
- * @HtNbMethod{::F_DISABLE_ROUTING_TABLES}
- *
- * @param[in] Node the Node that will have it's routing tables disabled
- * @param[in] Nb this northbridge
- */
-VOID
-DisableRoutingTables (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- )
-{
- PCI_ADDR Reg;
- UINT32 Temp;
- Temp = 1;
- ASSERT ((Node < MAX_NODES));
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_00,
- REG_LINK_INIT_CONTROL_0X6C);
- LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Verify that the Link is coherent, connected, and ready
- *
- * @HtNbMethod{::F_VERIFY_LINK_IS_COHERENT}
- *
- * @param[in] Node the Node that will be examined
- * @param[in] Link the Link on that Node to examine
- * @param[in] Nb this northbridge
- *
- * @retval TRUE The Link has the following status
- * - LinkCon=1, Link is connected
- * - InitComplete=1, Link initialization is complete
- * - NC=0, Link is coherent
- * - UniP-cLDT=0, Link is not Uniprocessor cLDT
- * - LinkConPend=0 Link connection is not pending
- * @retval FALSE The Link has some other status
-*/
-BOOLEAN
-VerifyLinkIsCoherent (
- IN UINT8 Node,
- IN UINT8 Link,
- IN NORTHBRIDGE *Nb
- )
-{
- UINT32 LinkType;
- PCI_ADDR LinkBase;
-
- ASSERT ((Node < MAX_NODES) && (Link < Nb->MaxLinks));
-
- LinkBase = Nb->MakeLinkBase (Node, Link, Nb);
-
- // FN0_98/A4/C4 = LDT Type Register
- LinkBase.Address.Register += HTHOST_LINK_TYPE_REG;
- LibAmdPciRead (AccessWidth32, LinkBase, &LinkType, Nb->ConfigHandle);
-
- // Verify LinkCon = 1, InitComplete = 1, NC = 0, UniP-cLDT = 0, LinkConPend = 0
- return (BOOLEAN) ((LinkType & HTHOST_TYPE_MASK) == HTHOST_TYPE_COHERENT);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Read the token stored in the scratchpad register field.
- *
- * @HtNbMethod{::F_READ_TOKEN}
- *
- * Use the CPU core count as a scratch pad.
- *
- * @note The location used to store the token is arbitrary. The only requirement is
- * that the location warm resets to zero, and that using it will have no ill-effects
- * during HyperTransport initialization.
- *
- * @param[in] Node the Node that will be examined
- * @param[in] Nb this northbridge
- *
- * @return the Token read from the Node
- */
-UINT8
-ReadToken (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- )
-{
- UINT32 Temp;
- PCI_ADDR Reg;
-
- ASSERT ((Node < MAX_NODES));
- // Use CpuCnt as a scratch register
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_00,
- REG_NODE_ID_0X60);
- LibAmdPciReadBits (Reg, 19, 16, &Temp, Nb->ConfigHandle);
-
- return (UINT8)Temp;
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Write the token stored in the scratchpad register
- *
- * @HtNbMethod{::F_WRITE_TOKEN}
- *
- * Use the CPU core count as a scratch pad.
- *
- * @note The location used to store the token is arbitrary. The only requirement is
- * that the location warm resets to zero, and that using it will have no ill-effects
- * during HyperTransport initialization.
- *
- * @param[in] Node the Node that marked with token
- * @param[in] Value the token Value
- * @param[in] Nb this northbridge
- */
-VOID
-WriteToken (
- IN UINT8 Node,
- IN UINT8 Value,
- IN NORTHBRIDGE *Nb
- )
-{
- PCI_ADDR Reg;
- UINT32 Temp;
- Temp = Value;
- ASSERT ((Node < MAX_NODES));
- // Use CpuCnt as a scratch register
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_00,
- REG_NODE_ID_0X60);
- LibAmdPciWriteBits (Reg, 19, 16, &Temp, Nb->ConfigHandle);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Full Routing Table Register initialization
- *
- * @HtNbMethod{::F_WRITE_FULL_ROUTING_TABLE}
- *
- * Write the routing table entry for Node to target, using the request Link, response
- * Link, and broadcast Links provided.
- *
- * @param[in] Node the Node that will be examined
- * @param[in] Target the Target Node for these routes
- * @param[in] ReqLink the Link for requests to Target
- * @param[in] RspLink the Link for responses to Target
- * @param[in] BroadcastLinks the broadcast Links
- * @param[in] Nb this northbridge
- */
-VOID
-WriteFullRoutingTable (
- IN UINT8 Node,
- IN UINT8 Target,
- IN UINT8 ReqLink,
- IN UINT8 RspLink,
- IN UINT32 BroadcastLinks,
- IN NORTHBRIDGE *Nb
- )
-{
- PCI_ADDR Reg;
- UINT32 Value;
-
- Value = 0;
- ASSERT ((Node < MAX_NODES) && (Target < MAX_NODES));
- if (ReqLink == ROUTE_TO_SELF) {
- Value |= Nb->SelfRouteRequestMask;
- } else {
- Value |= Nb->SelfRouteRequestMask << (ReqLink + 1);
- }
-
- if (RspLink == ROUTE_TO_SELF) {
- Value |= Nb->SelfRouteResponseMask;
- } else {
- Value |= Nb->SelfRouteResponseMask << (RspLink + 1);
- }
-
- // Allow us to accept a Broadcast ourselves, then set broadcasts for routes
- Value |= (UINT32)1 << Nb->BroadcastSelfBit;
- Value |= (UINT32)BroadcastLinks << (Nb->BroadcastSelfBit + 1);
-
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_00,
- REG_ROUTE0_0X40 + (Target * 4));
- LibAmdPciWrite (AccessWidth32, Reg, &Value, Nb->ConfigHandle);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Determine whether a Node is compatible with the discovered configuration so far.
- *
- * @HtNbMethod{::F_IS_ILLEGAL_TYPE_MIX}.
- *
- * Currently, that means the family, extended family of the new Node are the
- * same as the BSP's.
- *
- * @param[in] Node the Node
- * @param[in] Nb this northbridge
- *
- * @retval TRUE the new node is not compatible
- * @retval FALSE the new node is compatible
- */
-BOOLEAN
-IsIllegalTypeMix (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- )
-{
- return ((BOOLEAN) ((Nb->MakeKey (Node, Nb) & Nb->CompatibleKey) == 0));
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Fix (hopefully) exceptional conditions.
- *
- * @HtNbMethod{::F_HANDLE_SPECIAL_NODE_CASE}.
- *
- * Currently, this routine is implemented for all coherent HT families to check
- * vendor ID of coherent Node. If the vendor ID is 0x1022 then return FALSE,
- * or return TRUE.
- *
- * @param[in] Node The Node which need to be checked.
- * @param[in] Link The link to check for special conditions.
- * @param[in] State our global state.
- * @param[in] Nb this northbridge.
- *
- * @retval TRUE This node received special handling.
- * @retval FALSE This node was not handled specially, handle it normally.
- *
- */
-BOOLEAN
-HandleSpecialNodeCase (
- IN UINT8 Node,
- IN UINT8 Link,
- IN STATE_DATA *State,
- IN NORTHBRIDGE *Nb
- )
-{
- BOOLEAN Result;
- PCI_ADDR Reg;
- UINT32 VendorID;
-
- Result = TRUE;
-
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- 0,
- 0);
-
- LibAmdPciReadBits (Reg, 15, 0, &VendorID, Nb->ConfigHandle);
- if (VendorID == 0x1022) {
- Result = FALSE;
- }
-
- return Result;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/HT/NbCommon/htNbCoherent.h b/src/vendorcode/amd/agesa/Proc/HT/NbCommon/htNbCoherent.h
deleted file mode 100644
index 8e51a84..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/NbCommon/htNbCoherent.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Coherent Feature Northbridge common routines.
- *
- * Provide access to hardware for routing, coherent discovery.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-/***************************************************************************
- *** FAMILY/NORTHBRIDGE GENERIC FUNCTIONS ***
- ***************************************************************************/
-
-/**
- * Establish a Temporary route from one Node to another.
- *
- */
-VOID
-WriteRoutingTable (
- IN UINT8 Node,
- IN UINT8 Target,
- IN UINT8 Link,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Modifies the NodeID register on the target Node
- *
- */
-VOID
-WriteNodeID (
- IN UINT8 Node,
- IN UINT8 NodeID,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Read the Default Link
- *
- */
-UINT8
-ReadDefaultLink (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Turns routing tables on for a given Node
- *
- */
-VOID
-EnableRoutingTables (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Turns routing tables off for a given Node
- *
- */
-VOID
-DisableRoutingTables (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Verify that the Link is coherent, connected, and ready
- *
-*/
-BOOLEAN
-VerifyLinkIsCoherent (
- IN UINT8 Node,
- IN UINT8 Link,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Read the token stored in the scratchpad register field.
- *
- */
-UINT8
-ReadToken (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Write the token stored in the scratchpad register
- *
- */
-VOID
-WriteToken (
- IN UINT8 Node,
- IN UINT8 Value,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Full Routing Table Register initialization
- *
- */
-VOID
-WriteFullRoutingTable (
- IN UINT8 Node,
- IN UINT8 Target,
- IN UINT8 ReqLink,
- IN UINT8 RspLink,
- IN UINT32 BroadcastLinks,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Determine whether a Node is compatible with the discovered configuration so far.
- *
- */
-BOOLEAN
-IsIllegalTypeMix (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Fix (hopefully) exceptional conditions.
- *
- */
-BOOLEAN
-HandleSpecialNodeCase (
- IN UINT8 Node,
- IN UINT8 Link,
- IN STATE_DATA *State,
- IN NORTHBRIDGE *Nb
- );
-
diff --git a/src/vendorcode/amd/agesa/Proc/HT/NbCommon/htNbNonCoherent.c b/src/vendorcode/amd/agesa/Proc/HT/NbCommon/htNbNonCoherent.c
deleted file mode 100644
index 8fdd329..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/NbCommon/htNbNonCoherent.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Northbridge generic non-coherent support routines.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "htNb.h"
-#include "htNbHardwareFam10.h"
-#include "htNbNonCoherent.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_NBCOMMON_HTNBNONCOHERENT_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/***************************************************************************
- *** Non-coherent init code ***
- *** Northbridge access routines ***
- ***************************************************************************/
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Return the Link to the Southbridge
- *
- * @HtNbMethod{::F_READ_SB_LINK}
- *
- * @param[in] Nb this northbridge
- *
- * @return the Link to the southbridge
- */
-UINT8
-ReadSouthbridgeLink (
- IN NORTHBRIDGE *Nb
- )
-{
- UINT32 Temp;
- PCI_ADDR Reg;
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (0),
- MakePciBusFromNode (0),
- MakePciDeviceFromNode (0),
- CPU_HTNB_FUNC_00,
- REG_UNIT_ID_0X64);
- LibAmdPciReadBits (Reg, 10, 8, &Temp, Nb->ConfigHandle);
- return (UINT8)Temp;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Verify that the Link is non-coherent, connected, and ready
- *
- * @HtNbMethod{::F_VERIFY_LINK_IS_NON_COHERENT}
- *
- * @param[in] Node the Node that will be examined
- * @param[in] Link the Link on that Node to examine
- * @param[in] Nb this northbridge
- *
- * @retval TRUE The Link has the following status
- * - LinkCon=1, Link is connected
- * - InitComplete=1, Link initialization is complete
- * - NC=1, Link is noncoherent
- * - UniP-cLDT=0, Link is not Uniprocessor cLDT
- * - LinkConPend=0 Link connection is not pending
- * @retval FALSE The Link has some other status
- */
-BOOLEAN
-VerifyLinkIsNonCoherent (
- IN UINT8 Node,
- IN UINT8 Link,
- IN NORTHBRIDGE *Nb
- )
-{
- UINT32 LinkType;
- PCI_ADDR LinkBase;
-
- ASSERT ((Node < MAX_NODES) && (Link < MAX_NODES));
-
- LinkBase = Nb->MakeLinkBase (Node, Link, Nb);
- LinkBase.Address.Register += HTHOST_LINK_TYPE_REG;
-
- // FN0_98/A4/C4 = LDT Type Register
- LibAmdPciRead (AccessWidth32, LinkBase, &LinkType, Nb->ConfigHandle);
-
- // Verify LinkCon = 1, InitComplete = 1, NC = 1, UniP-cLDT = 0, LinkConPend = 0
- return (BOOLEAN) ((LinkType & HTHOST_TYPE_MASK) == HTHOST_TYPE_NONCOHERENT);
-}
diff --git a/src/vendorcode/amd/agesa/Proc/HT/NbCommon/htNbNonCoherent.h b/src/vendorcode/amd/agesa/Proc/HT/NbCommon/htNbNonCoherent.h
deleted file mode 100644
index 716a70f..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/NbCommon/htNbNonCoherent.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Northbridge generic non-coherent support routines.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/**
- * Return the Link to the Southbridge
- */
-UINT8
-ReadSouthbridgeLink (
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Verify that the Link is non-coherent, connected, and ready
- *
- */
-BOOLEAN
-VerifyLinkIsNonCoherent (
- IN UINT8 Node,
- IN UINT8 Link,
- IN NORTHBRIDGE *Nb
- );
diff --git a/src/vendorcode/amd/agesa/Proc/HT/NbCommon/htNbOptimization.c b/src/vendorcode/amd/agesa/Proc/HT/NbCommon/htNbOptimization.c
deleted file mode 100644
index 7c8551b..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/NbCommon/htNbOptimization.c
+++ /dev/null
@@ -1,258 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Link optimization support.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "IdsHt.h"
-#include "htInterface.h"
-#include "htInterfaceGeneral.h"
-#include "htNotify.h"
-#include "htNb.h"
-#include "htNbHardwareFam10.h"
-#include "htNbOptimization.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_NBCOMMON_HTNBOPTIMIZATION_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/***************************************************************************
- *** Link Optimization ***
- ***************************************************************************/
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get Link features into system data structure.
- *
- * @HtNbMethod{::F_GATHER_LINK_FEATURES}
- *
- * For a specific discovered CPU Link, populate the port list with the frequency
- * capabilities. Support for other link oriented capabilities, currently:
- * - Unit ID Clumping. Set to disabled. This doesn't mean the CPU doesn't support clumping,
- * it just means:
- * - The CPU doesn't clump its host unit ids, and
- * - We don't have to check as carefully in SetLinkData whether the port is an IO host link.
- *
- * @param[in,out] ThisPort The PortList structure entry for this link's port
- * @param[in] Interface Access to non-HT support functions.
- * @param[in] PlatformConfig Platform profile/build option config structure.
- * @param[in] Nb this northbridge
- */
-VOID
-GatherLinkFeatures (
- IN OUT PORT_DESCRIPTOR *ThisPort,
- IN HT_INTERFACE *Interface,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN NORTHBRIDGE *Nb
- )
-{
- PCI_ADDR Reg;
- UINT32 Frequency;
- UINT32 ExtendedFrequency;
-
- Reg = ThisPort->Pointer;
- Reg.Address.Register += HTHOST_FREQ_REV_REG;
- LibAmdPciReadBits (Reg, 30, 16, &Frequency, Nb->ConfigHandle);
- Reg = ThisPort->Pointer;
- Reg.Address.Register += HTHOST_FREQ_EXTENSION;
- LibAmdPciReadBits (Reg, 15, 1, &ExtendedFrequency, Nb->ConfigHandle);
- ThisPort->PrvFrequencyCap = ((Frequency | (ExtendedFrequency << HT_FREQUENCY_2800M)) &
- Nb->NorthBridgeFreqMask (ThisPort->NodeID, Interface, PlatformConfig, Nb));
- // Check for Internal link restriction not to run at 1000 MHz (but allow lower)
- if (IsPackageLinkInternal (Nb->GetPackageLink (ThisPort->NodeID, ThisPort->Link, Nb))) {
- ThisPort->PrvFrequencyCap &= ~(HT_FREQUENCY_LIMIT_1000M & ~HT_FREQUENCY_LIMIT_800M);
- }
- ThisPort->ClumpingSupport = HT_CLUMPING_DISABLE;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Change the hardware state for all Links according to the now optimized data in the
- * port list data structure for link reganging.
- *
- * @HtNbMethod{::F_SET_LINK_REGANG}
- *
- * @param[in] Node the node on which to regang a link
- * @param[in] Link the sublink 0 of the sublink pair to regang
- * @param[in] Nb this northbridge
- */
-VOID
-SetLinkRegang (
- IN UINT8 Node,
- IN UINT8 Link,
- IN NORTHBRIDGE *Nb
- )
-{
- PCI_ADDR Reg;
- UINT32 Temp;
-
- Temp = 1;
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_00,
- REG_HT_LINK_EXT_CONTROL0_0X170 + (4 * Link));
-
- LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Change the hardware state for all Links according to the now optimized data in the
- * port list data structure for Unit Id Clumping.
- *
- * @HtNbMethod{::F_SET_LINK_UNITID_CLUMPING}
- *
- * This applies to the host root of a non-coherent chain.
- *
- * @param[in] Node the node on which to enable clumping
- * @param[in] Link the link for which to enable clumping
- * @param[in] ClumpingEnables the unit id clumping enables
- * @param[in] Nb this northbridge
- */
-VOID
-SetLinkUnitIdClumping (
- IN UINT8 Node,
- IN UINT8 Link,
- IN UINT32 ClumpingEnables,
- IN NORTHBRIDGE *Nb
- )
-{
- PCI_ADDR Reg;
-
- // Host Unit Ids are not clumped.
- ASSERT ((ClumpingEnables & 0x3) == 0);
-
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_00,
- REG_HT_LINK_CLUMPING0_0X110 + (4 * Link));
-
- LibAmdPciWriteBits (Reg, 31, 0, &ClumpingEnables, Nb->ConfigHandle);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Change the hardware state for all Links according to the now optimized data in the
- * port list data structure for link frequency.
- *
- * @HtNbMethod{::F_SET_LINK_FREQUENCY}
- *
- * Handle extended frequencies. For HT3 frequencies, ensure Retry and Scrambling are
- * set. For HT1, clear them.
- *
- * @param[in] Node the node on which to set frequency for a link
- * @param[in] Link the link to set frequency
- * @param[in] Frequency the frequency to set
- * @param[in] Nb this northbridge
- */
-VOID
-SetLinkFrequency (
- IN UINT8 Node,
- IN UINT8 Link,
- IN UINT8 Frequency,
- IN NORTHBRIDGE *Nb
- )
-{
- UINT32 Temp;
- PCI_ADDR Reg;
-
- ASSERT ((Frequency >= HT_FREQUENCY_600M && Frequency <= HT_FREQUENCY_3200M)
- || (Frequency == HT_FREQUENCY_200M) || (Frequency == HT_FREQUENCY_400M));
-
- // Handle extended frequencies, 2800 MHz and above. 31 > Frequency > 16 in this case.
- if (Frequency > HT_FREQUENCY_2600M) {
- Temp = 1;
- } else {
- // Clear it if not extended.
- Temp = 0;
- }
- Reg = Nb->MakeLinkBase (Node, Link, Nb);
- Reg.Address.Register += HTHOST_FREQ_EXTENSION;
- LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
- Reg = Nb->MakeLinkBase (Node, Link, Nb);
- Reg.Address.Register += HTHOST_FREQ_REV_REG;
- Temp = (Frequency & 0x0F);
- LibAmdPciWriteBits (Reg, 11, 8, &Temp, Nb->ConfigHandle);
- // Gen1 = 200Mhz -> 1000MHz, Gen3 = 1200MHz -> 2600MHz
- if (Frequency > HT_FREQUENCY_1000M) {
- // Enable for Gen3 frequencies
- Temp = 1;
- } else {
- // Disable for Gen1 frequencies
- Temp = 0;
- }
- // HT3 retry mode enable / disable
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_00,
- REG_HT_LINK_RETRY0_0X130 + (4 * Link));
- LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
- // and Scrambling enable / disable
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_00,
- REG_HT_LINK_EXT_CONTROL0_0X170 + (4 * Link));
- LibAmdPciWriteBits (Reg, 3, 3, &Temp, Nb->ConfigHandle);
-}
diff --git a/src/vendorcode/amd/agesa/Proc/HT/NbCommon/htNbOptimization.h b/src/vendorcode/amd/agesa/Proc/HT/NbCommon/htNbOptimization.h
deleted file mode 100644
index a7dbacc..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/NbCommon/htNbOptimization.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Link optimization generic support.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/**
- * Get Link features into system data structure.
- *
- */
-VOID
-GatherLinkFeatures (
- IN OUT PORT_DESCRIPTOR *ThisPort,
- IN HT_INTERFACE *Interface,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Change the hardware state for all Links according to the now optimized data in the
- * port list data structure.
- *
- */
-VOID
-SetLinkRegang (
- IN UINT8 Node,
- IN UINT8 Link,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Set the link's Unit Id Clumping enable.
- *
- */
-VOID
-SetLinkUnitIdClumping (
- IN UINT8 Node,
- IN UINT8 Link,
- IN UINT32 ClumpingEnables,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Change the hardware state for all Links according to the now optimized data in the
- * port list data structure.
- */
-VOID
-SetLinkFrequency (
- IN UINT8 Node,
- IN UINT8 Link,
- IN UINT8 Frequency,
- IN NORTHBRIDGE *Nb
- );
diff --git a/src/vendorcode/amd/agesa/Proc/HT/NbCommon/htNbUtilities.c b/src/vendorcode/amd/agesa/Proc/HT/NbCommon/htNbUtilities.c
deleted file mode 100644
index 465066c..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/NbCommon/htNbUtilities.c
+++ /dev/null
@@ -1,335 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Northbridge utility routines.
- *
- * These routines are needed for support of more than one feature area.
- * Collect them in this file so build options don't remove them.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "htNotify.h"
-#include "htNb.h"
-#include "htNbHardwareFam10.h"
-#include "htNbUtilities.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_NBCOMMON_HTNBUTILITIES_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Return the HT Host capability base PCI config address for a Link.
- *
- * @HtNbMethod{::F_MAKE_LINK_BASE}
- *
- * @param[in] Node the Node this Link is on
- * @param[in] Link the Link
- * @param[in] Nb this northbridge
- *
- * @return the pci config address
- */
-PCI_ADDR
-MakeLinkBase (
- IN UINT8 Node,
- IN UINT8 Link,
- IN NORTHBRIDGE *Nb
- )
-{
- PCI_ADDR LinkBase;
-
- ASSERT (Nb != NULL);
- if (Link < 4) {
- LinkBase.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_00,
- REG_HT_CAP_BASE_0X80 + Link*HT_HOST_CAP_SIZE);
- } else {
- LinkBase.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_04,
- REG_HT_CAP_BASE_0X80 + (Link - 4)*HT_HOST_CAP_SIZE);
- }
- return LinkBase;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Return the LinkFailed status AFTER an attempt is made to clear the bit.
- *
- * @HtNbMethod{::F_READ_TRUE_LINK_FAIL_STATUS}
- *
- * Dependency!: HT_FEATURES::SetHtControlRegisterBits
- *
- * Also, call event notify if a Hardware Fault caused a sync flood on a previous boot.
- *
- * The table below summarizes correct responses of this routine.
- * <TABLE>
- * <TR><TD> Family </TD> <TD> before </TD> <TD> after </TD> <TD> unconnected </TD> <TD> Notify? </TD> <TD> return </TD></TR>
- * <TR><TD> 10 </TD> <TD> 0 </TD> <TD> 0 </TD> <TD> 0 </TD> <TD> No </TD> <TD> FALSE </TD></TR>
- * <TR><TD> 10 </TD> <TD> 1 </TD> <TD> 0 </TD> <TD> 0 </TD> <TD> Yes </TD> <TD> FALSE </TD></TR>
- * <TR><TD> 10 </TD> <TD> 1 </TD> <TD> 0 </TD> <TD> 3 </TD> <TD> No </TD> <TD> TRUE </TD></TR>
- * </TABLE>
- *
- * @param[in] Node the Node that will be examined
- * @param[in] Link the Link on that Node to examine
- * @param[in] State access to call back routine
- * @param[in] Nb this northbridge
- *
- * @retval TRUE the Link is not connected or has hard error
- * @retval FALSE the Link is connected
- */
-BOOLEAN
-ReadTrueLinkFailStatus (
- IN UINT8 Node,
- IN UINT8 Link,
- IN STATE_DATA *State,
- IN NORTHBRIDGE *Nb
- )
-{
- UINT32 Before;
- UINT32 After;
- UINT32 Unconnected;
- UINT32 Crc;
- PCI_ADDR Reg;
-
- ASSERT ((Node < MAX_NODES) && (Link < Nb->MaxLinks));
-
- Reg = Nb->MakeLinkBase (Node, Link, Nb);
- Reg.Address.Register += HTHOST_LINK_CONTROL_REG;
-
- // Save the CRC status before doing anything else.
- // Read, Clear, re-read the error bits in the Link Control Register
- // (FN0_84/A4/C4[4] = LinkFail bit),
- // and check the connection status, TransOff and EndOfChain.
- //
- LibAmdPciReadBits (Reg, 9, 8, &Crc, Nb->ConfigHandle);
- LibAmdPciReadBits (Reg, 4, 4, &Before, Nb->ConfigHandle);
- State->HtFeatures->SetHtControlRegisterBits (Reg, 4, 4, &Before, State);
- LibAmdPciReadBits (Reg, 4, 4, &After, Nb->ConfigHandle);
- LibAmdPciReadBits (Reg, 7, 6, &Unconnected, Nb->ConfigHandle);
-
- if (Before != After) {
- if (Unconnected == 0) {
- if (Crc != 0) {
- // A sync flood occurred due to HT CRC
- // Pass the Node and Link on which the generic sync flood event occurred.
- NotifyAlertHwHtCrc (Node, Link, (UINT8)Crc, State);
- } else {
- // Some sync flood occurred
- // Pass the Node and Link on which the generic sync flood event occurred.
- NotifyAlertHwSyncFlood (Node, Link, State);
- }
- }
- }
- return (BOOLEAN) ((After != 0) || (Unconnected != 0));
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Write the total number of cores and Nodes to the Node
- *
- * @HtNbMethod{::F_SET_TOTAL_NODES_AND_CORES}
- *
- * @param[in] Node the Node that will be examined
- * @param[in] TotalNodes the total number of Nodes
- * @param[in] TotalCores the total number of cores
- * @param[in] Nb this northbridge
- */
-VOID
-SetTotalNodesAndCores (
- IN UINT8 Node,
- IN UINT8 TotalNodes,
- IN UINT8 TotalCores,
- IN NORTHBRIDGE *Nb
- )
-{
- PCI_ADDR NodeIDReg;
- UINT32 Temp;
-
- ASSERT ((Node < MAX_NODES) && (TotalNodes <= MAX_NODES));
- NodeIDReg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_00,
- REG_NODE_ID_0X60);
-
- Temp = ((TotalCores - 1) & HTREG_NODE_CPUCNT_4_0);
- LibAmdPciWriteBits (NodeIDReg, 20, 16, &Temp, Nb->ConfigHandle);
- Temp = TotalNodes - 1;
- LibAmdPciWriteBits (NodeIDReg, 6, 4, &Temp, Nb->ConfigHandle);
-
- NodeIDReg.Address.Register = REG_HT_EXTENDED_NODE_ID_F0X160;
-
- Temp = (((TotalCores - 1) & HTREG_EXTNODE_CPUCNT_7_5) >> 5);
- LibAmdPciWriteBits (NodeIDReg, 18, 16, &Temp, Nb->ConfigHandle);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get the Count (1 based) of Nodes in the system.
- *
- * @HtNbMethod{::F_GET_NODE_COUNT}
- *
- * This is intended to support AP Core HT init, since the Discovery State data is not
- * available (State->NodesDiscovered), there needs to be this way to find the number
- * of Nodes. The Node count can be read from the BSP.
- *
- * @param[in] Nb this northbridge
- *
- * @return The number of nodes
- */
-UINT8
-GetNodeCount (
- IN NORTHBRIDGE *Nb
- )
-{
- PCI_ADDR NodeIDReg;
- UINT32 Temp;
-
- NodeIDReg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (0),
- MakePciBusFromNode (0),
- MakePciDeviceFromNode (0),
- CPU_HTNB_FUNC_00,
- REG_NODE_ID_0X60);
- LibAmdPciReadBits (NodeIDReg, 6, 4, &Temp, Nb->ConfigHandle);
- return ((UINT8) (++Temp));
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Limit coherent config accesses to cpus as indicated by Nodecnt.
- *
- * @HtNbMethod{::F_LIMIT_NODES}
- *
- * @param[in] Node the Node that will be examined
- * @param[in] Nb this northbridge
- */
-VOID
-LimitNodes (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- )
-{
- UINT32 Temp;
- PCI_ADDR Reg;
-
- Temp = 1;
- ASSERT ((Node < MAX_NODES));
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_HTNB_FUNC_00,
- REG_LINK_TRANS_CONTROL_0X68);
- LibAmdPciWriteBits (Reg, 15, 15, &Temp, Nb->ConfigHandle);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get the Package Link number, given the node and real link number.
- *
- * @HtNbMethod{::F_GET_PACKAGE_LINK}
- *
- * Based on the link to package link mapping from BKDG, look up package link for
- * the input link on the internal node number corresponding to Node id.
- *
- * @param[in] Node the node which has this link
- * @param[in] Link the link on that node
- * @param[in] Nb this northbridge
- *
- * @return the Package Link, HT_LIST_TERMINAL Not connected in package, HT_LIST_MATCH_INTERNAL_LINK package internal link.
- *
- */
-UINT8
-GetPackageLink (
- IN UINT8 Node,
- IN UINT8 Link,
- IN NORTHBRIDGE *Nb
- )
-{
- UINT8 ModuleType;
- UINT8 Module;
- UINTN PackageLinkMapItem;
- UINT8 PackageLink;
-
- ASSERT ((Node < MAX_NODES) && (Link < Nb->MaxLinks));
- PackageLink = HT_LIST_TERMINAL;
-
- Nb->GetModuleInfo (Node, &ModuleType, &Module, Nb);
-
- if (ModuleType != 0) {
- ASSERT (Nb->PackageLinkMap != NULL);
- // Use table to find this module's package link
- PackageLinkMapItem = 0;
- while ((*Nb->PackageLinkMap)[PackageLinkMapItem].Link != HT_LIST_TERMINAL) {
- if (((*Nb->PackageLinkMap)[PackageLinkMapItem].Module == Module) &&
- ((*Nb->PackageLinkMap)[PackageLinkMapItem].Link == Link)) {
- PackageLink = (*Nb->PackageLinkMap)[PackageLinkMapItem].PackageLink;
- break;
- }
- PackageLinkMapItem++;
- }
- } else {
- PackageLink = Link;
- }
- return PackageLink;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/HT/NbCommon/htNbUtilities.h b/src/vendorcode/amd/agesa/Proc/HT/NbCommon/htNbUtilities.h
deleted file mode 100644
index fec00e1..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/NbCommon/htNbUtilities.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Northbridge utility routines.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/**
- * Return the HT Host capability base PCI config address for a Link.
- *
- */
-PCI_ADDR
-MakeLinkBase (
- IN UINT8 Node,
- IN UINT8 Link,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Return the LinkFailed status AFTER an attempt is made to clear the bit.
- *
- */
-BOOLEAN
-ReadTrueLinkFailStatus (
- IN UINT8 Node,
- IN UINT8 Link,
- IN STATE_DATA *State,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Write the total number of cores and Nodes to the Node
- *
- */
-VOID
-SetTotalNodesAndCores (
- IN UINT8 Node,
- IN UINT8 TotalNodes,
- IN UINT8 TotalCores,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Get the Count (1 based) of Nodes in the system.
- *
- */
-UINT8
-GetNodeCount (
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Limit coherent config accesses to cpus as indicated by Nodecnt.
- *
- */
-VOID
-LimitNodes (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- );
-
-/**
- * Get the Package Link number, given the node and real link number.
- *
- */
-UINT8
-GetPackageLink (
- IN UINT8 Node,
- IN UINT8 Link,
- IN NORTHBRIDGE *Nb
- );
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htFeat.c b/src/vendorcode/amd/agesa/Proc/HT/htFeat.c
deleted file mode 100644
index 06a4b3c..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htFeat.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * HyperTransport features constructor.
- *
- * Initialize the set of available features.
- * This file implements build options using conditional compilation.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "OptionsHt.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "CommonReturns.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_HTFEAT_FILECODE
-extern CONST OPTION_HT_CONFIGURATION OptionHtConfiguration;
-
-/**
- * A no features Initializer.
- */
-CONST HT_FEATURES ROMDATA HtFeaturesNone =
-{
- (PF_COHERENT_DISCOVERY)CommonVoid,
- (PF_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES)CommonVoid,
- (PF_MAKE_HOP_COUNT_TABLE)CommonVoid,
- (PF_PROCESS_LINK)CommonVoid,
- (PF_GATHER_LINK_DATA)CommonVoid,
- (PF_SELECT_OPTIMAL_WIDTH_AND_FREQUENCY)CommonVoid,
- (PF_REGANG_LINKS)CommonVoid,
- (PF_SUBLINK_RATIO_FIXUP)CommonVoid,
- (PF_IS_COHERENT_RETRY_FIXUP)CommonReturnFalse,
- (PF_SET_LINK_DATA)CommonVoid,
- (PF_TRAFFIC_DISTRIBUTION)CommonVoid,
- (PF_SET_HT_CONTROL_REGISTER_BITS)CommonVoid,
- (PF_CONVERT_WIDTH_TO_BITS)CommonReturnZero8
-};
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Provide the current Feature set implementation.
- *
- * Initialize using the installed initializer.
- *
- * @param[in] HtFeatures A feature object to initialize
- * @param[in] StdHeader Opaque handle to standard config header
-*/
-VOID
-NewHtFeatures (
- OUT HT_FEATURES *HtFeatures,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- LibAmdMemCopy (
- (VOID *) HtFeatures,
- (VOID *) OptionHtConfiguration.HtOptionInternalFeatures ,
- (UINT32) (sizeof (HT_FEATURES)),
- StdHeader
- );
-}
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htFeat.h b/src/vendorcode/amd/agesa/Proc/HT/htFeat.h
deleted file mode 100644
index 6d5df63..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htFeat.h
+++ /dev/null
@@ -1,562 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * HT Features.
- *
- * This file provides definitions used in common by HT internal modules. The
- * data is private and not for external client access.
- * Definitions include the HT global internal state data structures, and
- * access to the available HT features from the main HT entry point.
- *
- * This file includes the feature constructor and feature support which is not
- * removed with various build options.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 39162 $ @e \$Date: 2010-10-07 22:41:37 +0800 (Thu, 07 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _HT_FEAT_H_
-#define _HT_FEAT_H_
-
-/**
- * @page htimplfeat HT Features Implementation Guide
- *
- * HT Features provides access to the HT Feature set, in a manner that isolates
- * calling code from knowledge about the Feature set implementation or which
- * features are supported in the current build. In the case of feature sets, this
- * is mostly used for build options to reduce code size by removing unneeded features.
- *
- * @par Adding a Method to HT Features
- *
- * To add a new method to the HT Features, follow these steps.
- * <ul>
- * <li> Create a typedef for the Method with the correct parameters and return type.
- *
- * <ul>
- * <li> Name the method typedef (F_METHOD_NAME)(), where METHOD_NAME is the same name as the method table item,
- * but with "_"'s and UPPERCASE, rather than mixed case.
- * @n <tt> typedef VOID (F_METHOD_NAME)(); </tt> @n
- *
- * <li> Make a reference type for references to a method implementation:
- * @n <tt> /// Reference to a Method </tt>
- * @n <tt> typedef F_METHOD_NAME *PF_METHOD_NAME </tt> @n
- * </ul>
- *
- * <li> Provide a standard doxygen function preamble for the Method typedef. Begin the
- * detailed description by providing a reference to the method instances page by including
- * the lines below:
- * @code
- * *
- * * @HtFeatInstances.
- * *
- * @endcode
- * @note It is important to provide documentation for the method type, because the method may not
- * have an implementation in any families supported by the current package. @n
- *
- * <li> Add to the _HT_FEATURES struct an item for the Method:
- * @n <tt> PF_METHOD_NAME MethodName; ///< Method: description. </tt> @n
- * </ul>
- *
- * @par Implementing an HT Features Instance of the method.
- *
- * To implement an instance of a method for a specific feature follow these steps.
- *
- * - In appropriate files, implement the method with the return type and parameters
- * matching the method typedef.
- *
- * - Name the function MethodName().
- *
- * - Create a doxygen function preamble for the method instance. Begin the detailed description with
- * an Implements command to reference the method type and add this instance to the Method Instances page.
- * @code
- * *
- * * @HtFeatMethod{::F_METHOD_NAME}.
- * *
- * @endcode
- *
- * - To access other Ht feature routines or data as part of the method implementation, the function
- * must use HtFeatures->OtherMethod(). Do not directly access other HT feature
- * routines, because in the table there may be overrides or this routine may be shared by multiple configurations.
- *
- * - Add the instance to the HT_FEATURES instances.
- *
- * - If a configuration does not need an instance of the method use one of the CommonReturns from
- * CommonReturns.h with the same return type.
- *
- * @par Invoking HT Features Methods.
- *
- * The first step is carried out only once by the top level HT entry point.
- * @n @code
- * HT_FEATURES HtFeatures;
- * // Get the current HT Feature Set
- * NewHtFeatures (&HtFeatures);
- * State->HtFeatures = &HtFeatures;
- * @endcode
- *
- * The following example shows how to invoke a HT Features method.
- * @n @code
- * State->HtFeatures->MethodName ();
- * @endcode
- *
- */
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-#define MAX_PLATFORM_LINKS 64
-#define MAX_LINK_PAIRS 4
-
-/* These following are internal definitions */
-#define ROUTE_TO_SELF 0x0F
-#define INVALID_LINK 0xCC /* Used in port list data structure to mark unused data entries.
- Can also be used for no Link found in a port list search */
-
-/* definitions for working with the port list structure */
-#define PORTLIST_TYPE_CPU 0
-#define PORTLIST_TYPE_IO 1
-
-/*
- * Hypertransport Capability definitions and macros
- *
- */
-
-#define HT_INTERFACE_CAP_SUBTYPE_MASK ((UINT32)0xE00000FF)
-#define HT_CAP_SUBTYPE_MASK ((UINT32)0xF80000FF)
-
-/* HT Host Capability */
-#define HT_HOST_CAPABILITY 1
-#define HT_HOST_CAP_SIZE 0x20
-
-/* Host CapabilityRegisters */
-#define HTHOST_LINK_CAPABILITY_REG 0x00
-#define HTHOST_LINK_CONTROL_REG 0x04
-#define HTHOST_FREQ_REV_REG 0x08
-#define HTHOST_REV_REV3 0x60
-#define HTHOST_FEATURE_CAP_REG 0x0C
-#define HTHOST_BUFFER_COUNT_REG 0x10
-#define HTHOST_ISOC_REG 0x14
-#define HTHOST_LINK_TYPE_REG 0x18
-#define HTHOST_FREQ_EXTENSION 0x1C
-#define HTHOST_TYPE_COHERENT 3
-#define HTHOST_TYPE_NONCOHERENT 7
-#define HTHOST_TYPE_MASK 0x1F
-
-/* HT Slave Capability (HT1 compat) */
-#define HT_SLAVE_CAPABILITY 0
-#define HTSLAVE_LINK01_OFFSET 4
-#define HTSLAVE_LINK_CONTROL_0_REG 4
-#define HTSLAVE_FREQ_REV_0_REG 0xC
-#define HTSLAVE_FEATURECAP_REG 0x10
-#define HT_CONTROL_CLEAR_CRC (~(3 << 8))
-#define HT_FREQUENCY_CLEAR_LINK_ERRORS (~(0x7 << 12))
-#define MAX_BUID 31
-
-/* HT3 gen Capability */
-#define HT_GEN3_CAPABILITY (0xD << 1)
-#define HTGEN3_LINK01_OFFSET 0x10
-#define HTGEN3_LINK_TRAINING_0_REG 0x10
-
-/* HT3 Retry Capability */
-#define HT_RETRY_CAPABILITY (0xC << 1)
-#define HTRETRY_CONTROL_REG 4
-
-/* Unit ID Clumping Capability */
-#define HT_UNITID_CAPABILITY (0x9 << 1)
-#define HTUNIT_SUPPORT_REG 4
-#define HTUNIT_ENABLE_REG 8
-#define HT_CLUMPING_PASSIVE 1
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-// Forward declarations.
-/// Used for forward reference.
-typedef struct _NORTHBRIDGE NORTHBRIDGE;
-/// Used for forward reference.
-typedef struct _HT_FEATURES HT_FEATURES;
-/// Used for forward reference.
-typedef struct _HT_INTERFACE HT_INTERFACE;
-
-/**
- * Coherent Init Data.
- *
- * Metrics representing the coherent fabric which was discovered: Degree of nodes, adjacency,
- * node numbering permutations, and the topology which it matched.
- */
-typedef struct {
- /** The number of coherent Links connected on each Node (the 'Degree' of the Node) */
- UINT8 SysDegree[MAX_NODES];
- /** The systems adjacency (sysMatrix[i][j] is true if Node_i has a Link to Node_j) */
- BOOLEAN SysMatrix[MAX_NODES][MAX_NODES];
-
- UINT8 DbDegree[MAX_NODES]; /**< Like sysDegree, but for the current database topology */
- BOOLEAN DbMatrix[MAX_NODES][MAX_NODES]; /**< Like sysMatrix, but for the current database topology */
-
- UINT8 Perm[MAX_NODES]; /**< The Node mapping from the system to the database */
- UINT8 ReversePerm[MAX_NODES]; /**< The Node mapping from the database to the system */
- UINT8 *MatchedTopology; /**< The topology that matched the current system or NULL */
-} COHERENT_FABRIC;
-
-/**
- * Represent the system as Links of matched port pairs.
- * A pair consists of a source Node, a Link to the destination Node, the
- * destination Node, and its Link back to source Node. The even indices are
- * the source Nodes and Links, and the odd indices are for the destination
- * Nodes and Links.
- * @note The Port pair 2*N and 2*N+1 are connected together to form a Link
- * (e.g. 0,1 and 8,9 are ports on either end of an HT Link) The lower number
- * port (2*N) is the source port. The device that owns the source port is
- * always the device closer to the BSP. (i.e. nearer the CPU in a
- * non-coherent chain, or the CPU with the lower NodeID).
- */
-typedef struct {
- /* This section is where the Link is in the system and how to find it */
- UINT8 Type; /**< 0 = CPU, 1 = Device, all others reserved */
- UINT8 Link; /**< 0-1 for devices, 0-7 for CPUs */
- UINT8 NodeID; /**< The Node, or a pointer to the devices parent Node */
- UINT8 HostLink; /**< For Devices, the root CPU's Link to the chain */
- UINT8 HostDepth; /**< Link Depth in chain, only used by devices */
- PCI_ADDR Pointer; /**< A pointer to the device's slave HT capability, so we don't have to keep searching */
-
- /* This section is for the final settings, which are written to hardware */
- BOOLEAN SelRegang; /**< Indicates to software regang Link, only used for CPU->CPU Links */
- UINT8 SelWidthIn; /**< Width in setting */
- UINT8 SelWidthOut; /**< Width out setting */
- UINT8 SelFrequency; /**< Frequency setting */
-
- /* This section is for keeping track of capabilities and possible configurations */
- BOOLEAN RegangCap; /**< Is the port capable of reganging? CPUs only */
- UINT32 PrvFrequencyCap; /**< Possible frequency settings */
- UINT8 PrvWidthInCap; /**< Possible Width setting */
- UINT8 PrvWidthOutCap; /**< Possible Width setting */
- UINT32 CompositeFrequencyCap; /**< Possible Link frequency setting */
- UINT32 ClumpingSupport; /**< Unit ID Clumping value (bit 0 = passive support) */
-} PORT_DESCRIPTOR;
-
-/// Reference to a set of PORT_DESCRIPTORs.
-typedef PORT_DESCRIPTOR (*PORT_LIST)[MAX_PLATFORM_LINKS*2];
-
-/**
- * Our global state data structure
- */
-typedef struct {
- AMD_HT_INTERFACE *HtBlock; /**< The input data structure. */
-
- UINT8 NodesDiscovered; /**< One less than the number of Nodes found in the system */
- UINT8 TotalLinks; /**< How many HT Links have we discovered so far. */
- UINT8 SysMpCap; /**< The maximum number of Nodes that all processors are capable of */
- AGESA_STATUS MaxEventClass; /**< The event class of the highest severity event generated */
-
- PORT_LIST PortList; /**< Represent the system as a set of Links, each two Ports. */
- COHERENT_FABRIC *Fabric; /**< Describe metrics about the coherent fabric.
- * Limited scope to CoherentInit(). */
- /* Data interface to other Agesa Modules */
- SOCKET_DIE_TO_NODE_MAP SocketDieToNodeMap; /**< For each Socket, Die the Node ids */
- NODE_TO_SOCKET_DIE_MAP NodeToSocketDieMap; /**< For each Node id, Socket and Die */
- HOP_COUNT_TABLE *HopCountTable; /**< Table of hops between nodes */
-
- /* Data for non-coherent initialization */
- UINT8 AutoBusCurrent; /**< The next bus number available */
- UINT8 UsedCfgMapEntries; /**< The next Config address Map set available, Limit 4 (F1X[EC:E0]) */
- BOOLEAN IsUsingRecoveryHt; /**< Manual BUID Swap List processing should assume that HT Recovery was used */
- BOOLEAN IsSetHtCrcFlood; /**< Enable setting of HT CRC Flood */
- BOOLEAN IsUsingUnitIdClumping; /**< Enable automatic Unit Id Clumping configuration. */
-
- HT_INTERFACE *HtInterface; /**< Interface for feature code to external parameters */
- HT_FEATURES *HtFeatures; /**< The current feature implementations */
- NORTHBRIDGE *Nb; /**< The current northbridge */
-
- PLATFORM_CONFIGURATION *PlatformConfiguration; /**< The platform specific configuration customizations */
- VOID *ConfigHandle; /**< Config Pointer, opaque handle for passing to lib */
-} STATE_DATA;
-
-//
-// Feature Method types
-//
-
-/**
- * Discover all coherent devices in the system.
- *
- * @HtFeatInstances.
- *
- * @param[in,out] State our global state
- *
- */
-typedef VOID F_COHERENT_DISCOVERY (
- IN OUT STATE_DATA *State
- );
-/// Reference to a method.
-typedef F_COHERENT_DISCOVERY *PF_COHERENT_DISCOVERY;
-
-/**
- * Using the description of the fabric topology we discovered, try to find a match
- * among the supported topologies.
- *
- * @HtFeatInstances.
- *
- * @param[in,out] State the discovered fabric, degree matrix, permutation
- *
- */
-typedef VOID F_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES (
- IN OUT STATE_DATA *State
- );
-/// Reference to a method.
-typedef F_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES *PF_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES;
-
-/**
- * Make a Hop Count Table for the installed topology.
- *
- * @HtFeatInstances.
- *
- * @param[in,out] State access topology, permutation, update hop table
- *
- */
-typedef VOID F_MAKE_HOP_COUNT_TABLE (
- IN OUT STATE_DATA *State
- );
-/// Reference to a method.
-typedef F_MAKE_HOP_COUNT_TABLE *PF_MAKE_HOP_COUNT_TABLE;
-
-/**
- * Process a non-coherent Link.
- *
- * @HtFeatInstances.
- *
- * @param[in] Node Node on which to process nc init
- * @param[in] Link The non-coherent Link on that Node
- * @param[in] IsCompatChain Is this the chain with the southbridge? TRUE if yes.
- * @param[in,out] State our global state
- */
-typedef VOID F_PROCESS_LINK (
- IN UINT8 Node,
- IN UINT8 Link,
- IN BOOLEAN IsCompatChain,
- IN OUT STATE_DATA *State
- );
-/// Reference to a method.
-typedef F_PROCESS_LINK *PF_PROCESS_LINK;
-
-/**
- * Get Link features into system data structure.
- *
- * @HtFeatInstances.
- *
- * @param[in] State our global state, port list
- */
-typedef VOID F_GATHER_LINK_DATA (
- IN STATE_DATA *State
- );
-/// Reference to a method.
-typedef F_GATHER_LINK_DATA *PF_GATHER_LINK_DATA;
-
-/**
- * Optimize Links.
- *
- * @HtFeatInstances.
- *
- * @param[in,out] State Process and update portlist
- */
-typedef VOID F_SELECT_OPTIMAL_WIDTH_AND_FREQUENCY (
- IN OUT STATE_DATA *State
- );
-/// Reference to a method.
-typedef F_SELECT_OPTIMAL_WIDTH_AND_FREQUENCY *PF_SELECT_OPTIMAL_WIDTH_AND_FREQUENCY;
-
-/**
- * Change the hardware state for all Links according to the now optimized data in the
- * port list data structure.
- *
- * @HtFeatInstances.
- *
- * @param[in] State our global state, port list
- */
-typedef VOID F_SET_LINK_DATA (
- IN STATE_DATA *State
- );
-/// Reference to a method.
-typedef F_SET_LINK_DATA *PF_SET_LINK_DATA;
-
-/**
- * Retry must be enabled on all coherent links if it is enabled on any coherent links.
- *
- * @HtFeatInstances.
- *
- * @param[in,out] State global state, port frequency settings.
- *
- * @retval TRUE Fixup occurred, all coherent links HT1
- * @retval FALSE No changes
- */
-typedef BOOLEAN F_IS_COHERENT_RETRY_FIXUP (
- IN STATE_DATA *State
- );
-/// Reference to a method.
-typedef F_IS_COHERENT_RETRY_FIXUP *PF_IS_COHERENT_RETRY_FIXUP;
-
-
-/**
- * Test the subLinks of a Link to see if they qualify to be reganged.
- *
- * @HtFeatInstances.
- *
- * @param[in,out] State Our global state
- */
-typedef VOID F_REGANG_LINKS (
- IN OUT STATE_DATA *State
- );
-/// Reference to a method.
-typedef F_REGANG_LINKS *PF_REGANG_LINKS;
-
-/**
- * Iterate through all Links, checking the frequency of each subLink pair.
- *
- * @HtFeatInstances.
- *
- * @param[in,out] State Link state and port list
- *
- */
-typedef VOID F_SUBLINK_RATIO_FIXUP (
- IN OUT STATE_DATA *State
- );
-/// Reference to a method.
-typedef F_SUBLINK_RATIO_FIXUP *PF_SUBLINK_RATIO_FIXUP;
-
-/**
- * Identify Links which can have traffic distribution.
- *
- * @HtFeatInstances.
- *
- * @param[in] State port list data
- */
-typedef VOID F_TRAFFIC_DISTRIBUTION (
- IN STATE_DATA *State
- );
-/// Reference to a method.
-typedef F_TRAFFIC_DISTRIBUTION *PF_TRAFFIC_DISTRIBUTION;
-
-/**
- * Access HT Link Control Register.
- *
- * @HtFeatInstances.
- *
- * @param[in] Reg the PCI config address the control register
- * @param[in] HiBit the high bit number
- * @param[in] LoBit the low bit number
- * @param[in] Value the value to write to that bit range. Bit 0 => loBit.
- * @param[in] State Our state, config handle for lib
- */
-typedef VOID F_SET_HT_CONTROL_REGISTER_BITS (
- IN PCI_ADDR Reg,
- IN UINT8 HiBit,
- IN UINT8 LoBit,
- IN UINT32 *Value,
- IN STATE_DATA *State
- );
-/// Reference to a method.
-typedef F_SET_HT_CONTROL_REGISTER_BITS *PF_SET_HT_CONTROL_REGISTER_BITS;
-
-/**
- * Translate a desired width setting to the bits to set in the register field.
- *
- * @HtFeatInstances.
- *
- * @param[in] Value the width Value
- *
- * @return The bits for the register
- */
-typedef UINT8 F_CONVERT_WIDTH_TO_BITS (
- IN UINT8 Value
- );
-/// Reference to a method.
-typedef F_CONVERT_WIDTH_TO_BITS *PF_CONVERT_WIDTH_TO_BITS;
-
-/**
- * HT Feature Methods.
- *
- * Provides abstract methods which are bound to specific feature implementations.
- */
-struct _HT_FEATURES {
- PF_COHERENT_DISCOVERY CoherentDiscovery; /**< Method: Coherent Discovery. */
- PF_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES LookupComputeAndLoadRoutingTables;
- /**< Method: Route the discovered system */
- PF_MAKE_HOP_COUNT_TABLE MakeHopCountTable; /**< Method: Compute slit hop counts */
- PF_PROCESS_LINK ProcessLink; /**< Method: Process a non-coherent Link. */
- PF_GATHER_LINK_DATA GatherLinkData; /**< Method: Gather Link Capabilities and data. */
- PF_SELECT_OPTIMAL_WIDTH_AND_FREQUENCY SelectOptimalWidthAndFrequency;
- /**< Method: Optimize link features. */
- PF_REGANG_LINKS RegangLinks; /**< Method: Regang Sublinks. */
- PF_SUBLINK_RATIO_FIXUP SubLinkRatioFixup; /**< Method: Fix Sublink Frequency ratios */
- PF_IS_COHERENT_RETRY_FIXUP IsCoherentRetryFixup;
- /**< Method: Fix Retry mixed on coherent links. */
- PF_SET_LINK_DATA SetLinkData; /**< Method: Set optimized values. */
- PF_TRAFFIC_DISTRIBUTION TrafficDistribution; /**< Method: Detect and Initialize Traffic Distribution */
- PF_SET_HT_CONTROL_REGISTER_BITS SetHtControlRegisterBits; /**< Method: Access HT Link Control Reg. */
- PF_CONVERT_WIDTH_TO_BITS ConvertWidthToBits; /**< Method: Convert a bit width to the value used for register setting. */
-} ;
-
-/*----------------------------------------------------------------------------
- * Prototypes
- *
- *----------------------------------------------------------------------------
- */
-
-/**
- * Provide the current Feature set implementation.
- *
- * Add an implementation reference for the constructor, just to make sure the page is created.
- * @HtFeatMethod{_HT_FEATURES}.
- *
- */
-VOID
-NewHtFeatures (
- OUT HT_FEATURES *HtFeatures,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-
-#endif /* _HT_FEAT_H_ */
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htGraph.h b/src/vendorcode/amd/agesa/Proc/HT/htGraph.h
deleted file mode 100644
index df59a8c..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htGraph.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Topology Interface.
- *
- * Contains interface to the topology data.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _HT_GRAPH_H_
-#define _HT_GRAPH_H_
-
-/**
- * @page htgraphdesign Graph Support routines
- *
- * These routines provide support for dealing with the graph representation
- * of the topologies, along with the routing table information for that topology.
- * The routing information is compressed and these routines currently decompress
- * 'on the fly'. A graph is represented as a set of routes. All the edges in the
- * graph are routes; a direct route from Node i to Node j exists in the graph IFF
- * there is an edge directly connecting Node i to Node j. All other routes designate
- * the edge which the route to that Node initially takes, by designating a Node
- * to which a direct connection exists. That is, the route to non-adjacent Node j
- * from Node i specifies Node k where Node i directly connects to Node k.
- *
- *@code
- * pseudo definition of compressed graph:
- * typedef struct
- * {
- * // First byte
- * UINT8 broadcast[8]:1; // that is, 8 1-bit values
- * // Second byte
- * UINT8 requestRoute:4; // [3:0]
- * UINT8 responseRoute:4; // [7:4]
- * } sRoute;
- * typedef struct
- * {
- * UINT8 size;
- * sRoute graph[size][size];
- * } sGraph;
- *@endcode
- */
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-VOID
-GetAmdTopolist (
- OUT UINT8 ***List
- );
-
-UINT8
-GraphHowManyNodes (
- IN UINT8 *Graph
- );
-
-BOOLEAN
-GraphIsAdjacent (
- IN UINT8 *Graph,
- IN UINT8 NodeA,
- IN UINT8 NodeB
- );
-
-UINT8
-GraphGetRsp (
- IN UINT8 *Graph,
- IN UINT8 NodeA,
- IN UINT8 NodeB
- );
-
-UINT8
-GraphGetReq (
- IN UINT8 *Graph,
- IN UINT8 NodeA,
- IN UINT8 NodeB
- );
-
-UINT8
-GraphGetBc (
- IN UINT8 *Graph,
- IN UINT8 NodeA,
- IN UINT8 NodeB
- );
-
-#endif /* _HT_GRAPH_H_ */
-
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph.c b/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph.c
deleted file mode 100644
index 7fcbdfa..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph.c
+++ /dev/null
@@ -1,199 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Routines to deal with topology data.
- *
- * Access the topologies and information about a topology.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "htGraph.h"
-#include "OptionsHt.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_HTGRAPH_HTGRAPH_FILECODE
-
-extern OPTION_HT_CONFIGURATION OptionHtConfiguration;
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Returns the AGESA built in topology list
- *
- * @param[out] List a pointer to the built in topology list
- */
-VOID
-GetAmdTopolist (
- OUT UINT8 ***List
- )
-{
- // Cast below to hush CONST warning. The built in list must be CONST to be in ROM statically.
- // The caller of this routine may get a topolist pointer from the interface, however, and
- // that is not CONST, since it could be on the stack.
- //
- *List = (UINT8 **)OptionHtConfiguration.HtOptionBuiltinTopologies;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Returns the number of Nodes in the compressed graph
- *
- * @param[in] Graph a compressed graph
- *
- * @return the number of Nodes in the graph
- */
-UINT8
-GraphHowManyNodes (
- IN UINT8 *Graph
- )
-{
- return Graph[0];
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Returns true if NodeA is directly connected to NodeB, false otherwise
- *
- * if NodeA == NodeB also returns false.
- * Relies on rule that directly connected Nodes always route requests directly.
- *
- * @param[in] Graph the graph to examine
- * @param[in] NodeA the Node number of the first Node
- * @param[in] NodeB the Node number of the second Node
- *
- * @retval TRUE NodeA connects to NodeB
- * @retval FALSE NodeA does not connect to NodeB
- */
-BOOLEAN
-GraphIsAdjacent (
- IN UINT8 *Graph,
- IN UINT8 NodeA,
- IN UINT8 NodeB
- )
-{
- UINT8 size;
- size = Graph[0];
- ASSERT ((NodeA < size) && (NodeB < size));
- return (Graph[1 + (NodeA*size + NodeB)*2 + 1] & 0x0F) == NodeB;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Returns the graph Node used by NodeA to route responses targeted at NodeB.
- *
- * This will be a Node directly connected to NodeA (possibly NodeB itself),
- * or "Route to Self" if NodeA and NodeB are the same Node.
- * Note that all Node numbers are abstract Node numbers of the topology graph,
- * it is the responsibility of the caller to apply any permutation needed.
- *
- * @param[in] Graph the graph to examine
- * @param[in] NodeA the Node number of the first Node
- * @param[in] NodeB the Node number of the second Node
- *
- * @return The response route Node
- */
-UINT8
-GraphGetRsp (
- IN UINT8 *Graph,
- IN UINT8 NodeA,
- IN UINT8 NodeB
- )
-{
- UINT8 size;
- size = Graph[0];
- ASSERT ((NodeA < size) && (NodeB < size));
- return (Graph[1 + (NodeA*size + NodeB)*2 + 1] & 0xF0) >> 4;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Returns the graph Node used by NodeA to route requests targeted at NodeB.
- *
- * This will be a Node directly connected to NodeA (possibly NodeB itself),
- * or "Route to Self" if NodeA and NodeB are the same Node.
- * Note that all Node numbers are abstract Node numbers of the topology graph,
- * it is the responsibility of the caller to apply any permutation needed.
- *
- * @param[in] Graph the graph to examine
- * @param[in] NodeA the Node number of the first Node
- * @param[in] NodeB the Node number of the second Node
- *
- * @return The request route Node
- */
-UINT8
-GraphGetReq (
- IN UINT8 *Graph,
- IN UINT8 NodeA,
- IN UINT8 NodeB
- )
-{
- UINT8 size;
- size = Graph[0];
- ASSERT ((NodeA < size) && (NodeB < size));
- return (Graph[1 + (NodeA*size + NodeB)*2 + 1] & 0x0F);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Returns a bit vector of Nodes that NodeA should forward a broadcast from
- * NodeB towards
- *
- * @param[in] Graph the graph to examine
- * @param[in] NodeA the Node number of the first Node
- * @param[in] NodeB the Node number of the second Node
- *
- * @return the broadcast routes for NodeA from NodeB
- */
-UINT8
-GraphGetBc (
- IN UINT8 *Graph,
- IN UINT8 NodeA,
- IN UINT8 NodeB
- )
-{
- UINT8 size;
- size = Graph[0];
- ASSERT ((NodeA < size) && (NodeB < size));
- return Graph[1 + (NodeA*size + NodeB)*2];
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph1.c b/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph1.c
deleted file mode 100644
index 5ba85b9..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph1.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Single node topology
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/*
- * 0
- */
-/**
- * single node
- */
-/**
- * @dot
- strict graph one {
- node [shape="plaintext"];
- 0;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologySingleNode[] =
-{
- 0x01,
- 0x00, 0xFF // Node 0
-};
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph2.c b/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph2.c
deleted file mode 100644
index 9caadb3..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph2.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Two nodes.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/*
- * 0---1
- */
-/**
- * Two Nodes.
- */
-/**
- * @dot
- strict graph two {
- node [shape="plaintext"];
- 0 -- 1 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologyDualNode[] =
-{
- 0x02,
- 0x02, 0xFF, 0x00, 0x11, // Node 0
- 0x00, 0x00, 0x01, 0xFF // Node 1
-};
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph3Line.c b/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph3Line.c
deleted file mode 100644
index 25df4f1..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph3Line.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Three Line.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/*
- * 2
- * |
- * |
- * 0---1
- */
-/**
- * Three Line
- */
-/**
- * @dot
- strict graph three {
- node [shape="plaintext"];
- 0 -- 1 ;
- 0 -- 2 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologyThreeLine[] =
-{
- 0x03,
- 0x06, 0xFF, 0x04, 0x11, 0x02, 0x22, // Node 0
- 0x00, 0x00, 0x01, 0xFF, 0x00, 0x00, // Node 1
- 0x00, 0x00, 0x00, 0x00, 0x01, 0xFF // Node 2
-};
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph3Triangle.c b/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph3Triangle.c
deleted file mode 100644
index 312a232..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph3Triangle.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Three Triangle Topology.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/*
- * 2
- * |\
- * | \
- * 0---1
- */
-/**
- * Three triangle
- */
-/**
- * @dot
- strict graph triangle {
- node [shape="plaintext"];
- 0 -- 1 ;
- 0 -- 2 ;
- 1 -- 2 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologyTriangle[] =
-{
- 0x03,
- 0x06, 0xFF, 0x00, 0x11, 0x00, 0x22, // Node 0
- 0x00, 0x00, 0x05, 0xFF, 0x00, 0x22, // Node 1
- 0x00, 0x00, 0x00, 0x11, 0x03, 0xFF // Node 2
-};
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph4Degenerate.c b/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph4Degenerate.c
deleted file mode 100644
index 0653728..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph4Degenerate.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Four node degenerate.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-/*
- * 2 3
- * |\ |
- * | \|
- * 0---1
- */
-/**
- * Four Node degenerate
- */
-/**
- * @dot
- strict graph degen4 {
- node [shape="plaintext"];
- {rank=same; 0; 1}
- {rank=same; 2; 3}
- 0 -- 1 ;
- 0 -- 2 ;
- 1 -- 2 ;
- 1 -- 3 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologyFourDegenerate[] =
-{
- 0x04,
- 0x06, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x11, // Node 0
- 0x08, 0x00, 0x0D, 0xFF, 0x08, 0x22, 0x05, 0x33, // Node 1
- 0x00, 0x00, 0x00, 0x11, 0x03, 0xFF, 0x00, 0x11, // Node 2
- 0x00, 0x11, 0x00, 0x11, 0x00, 0x11, 0x02, 0xFF // Node 3
-};
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph4FullyConnected.c b/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph4FullyConnected.c
deleted file mode 100644
index 1c6c0df..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph4FullyConnected.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Four node fully connected.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/*
- * 2---3
- * |\ /|
- * |/ \|
- * 0---1
- */
-/**
- * Four Node Fully
- */
-/**
- * @dot
- strict graph full4 {
- node [shape="plaintext"];
- {rank=same; 0; 1}
- {rank=same; 2; 3}
- 0 -- 1 ;
- 0 -- 2 ;
- 0 -- 3 ;
- 1 -- 2 ;
- 1 -- 3 ;
- 2 -- 3 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologyFourFully[] =
-{
- 0x04,
- 0x0E, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, // Node 0
- 0x00, 0x00, 0x0D, 0xFF, 0x00, 0x22, 0x00, 0x33, // Node 1
- 0x00, 0x00, 0x00, 0x11, 0x0B, 0xFF, 0x00, 0x33, // Node 2
- 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x07, 0xFF // Node 3
-};
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph4Kite.c b/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph4Kite.c
deleted file mode 100644
index 185a36b..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph4Kite.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Four node kite Topology.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-/*
- * 2---3
- * |\ |
- * | \|
- * 0---1
- */
-/**
- * Four Node kite
- */
-/**
- * @dot
- strict graph kite4 {
- node [shape="plaintext"];
- {rank=same; 0; 1}
- {rank=same; 2; 3}
- 0 -- 1 ;
- 0 -- 2 ;
- 1 -- 2 ;
- 1 -- 3 ;
- 2 -- 3 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologyFourKite[] =
-{
- 0x04,
- 0x06, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x11, // Node 0
- 0x08, 0x00, 0x0D, 0xFF, 0x00, 0x22, 0x00, 0x33, // Node 1
- 0x00, 0x00, 0x00, 0x11, 0x0B, 0xFF, 0x01, 0x33, // Node 2
- 0x00, 0x22, 0x00, 0x11, 0x00, 0x22, 0x06, 0xFF // Node 3
-};
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph4Line.c b/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph4Line.c
deleted file mode 100644
index 4eb36ea..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph4Line.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Four node Line Topology.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/*
- * 2 3
- * | |
- * | |
- * 0---1
- */
-/**
- * Four Node line
- */
-/**
- * @dot
- strict graph line4 {
- node [shape="plaintext"];
- {rank=same; 0; 1}
- {rank=same; 2; 3}
- 0 -- 1 ;
- 0 -- 2 ;
- 1 -- 3 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologyFourLine[] =
-{
- 0x04,
- 0x06, 0xFF, 0x04, 0x11, 0x02, 0x22, 0x04, 0x11, // Node 0
- 0x08, 0x00, 0x09, 0xFF, 0x08, 0x00, 0x01, 0x33, // Node 1
- 0x00, 0x00, 0x00, 0x00, 0x01, 0xFF, 0x00, 0x00, // Node 2
- 0x00, 0x11, 0x00, 0x11, 0x00, 0x11, 0x02, 0xFF // Node 3
-};
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph4Square.c b/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph4Square.c
deleted file mode 100644
index 223d677..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph4Square.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Four node Square Topology.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-/*
- * 2---3
- * | |
- * | |
- * 0---1
- */
-/**
- * Four Node square
- */
-/**
- * @dot
- strict graph square4 {
- node [shape="plaintext"];
- {rank=same; 0; 1}
- {rank=same; 2; 3}
- 0 -- 1 ;
- 0 -- 2 ;
- 1 -- 3 ;
- 2 -- 3 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologyFourSquare[] =
-{
- 0x04,
- 0x06, 0xFF, 0x00, 0x11, 0x02, 0x22, 0x00, 0x22, // Node 0
- 0x00, 0x00, 0x09, 0xFF, 0x00, 0x33, 0x01, 0x33, // Node 1
- 0x08, 0x00, 0x00, 0x00, 0x09, 0xFF, 0x00, 0x33, // Node 2
- 0x00, 0x11, 0x04, 0x11, 0x00, 0x22, 0x06, 0xFF // Node 3
-};
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph4Star.c b/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph4Star.c
deleted file mode 100644
index f7af9a8..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph4Star.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Four node Star Topology.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/*
- * 2---3
- * |\
- * | \
- * 0 1
- */
-/**
- * Four Node Star
- */
-/**
- * @dot
- strict graph star4 {
- node [shape="plaintext"];
- {rank=same; 0; 1}
- {rank=same; 2; 3}
- 0 -- 2 ;
- 1 -- 2 ;
- 2 -- 3 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologyFourStar[] =
-{
- 0x04,
- 0x04, 0xFF, 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, // Node 0
- 0x00, 0x22, 0x04, 0xFF, 0x00, 0x22, 0x00, 0x22, // Node 1
- 0x0A, 0x00, 0x09, 0x11, 0x0B, 0xFF, 0x03, 0x33, // Node 2
- 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, 0x04, 0xFF // Node 3
-};
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph5FullyConnected.c b/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph5FullyConnected.c
deleted file mode 100644
index 7082a99..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph5FullyConnected.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Five node Fully Connected Topology.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/**
- * Five node fully connected
- */
-/**
- * @dot
- strict graph full5 {
- node [shape="plaintext"];
- 0 -- 1 ;
- 0 -- 2 ;
- 0 -- 3 ;
- 0 -- 4 ;
- 1 -- 2 ;
- 1 -- 3 ;
- 1 -- 4 ;
- 2 -- 3 ;
- 2 -- 4 ;
- 3 -- 4 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologyFiveFully[] =
-{
- 0x05,
- 0x1E, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, // Node 0
- 0x00, 0x00, 0x1D, 0xFF, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, // Node 1
- 0x00, 0x00, 0x00, 0x11, 0x1B, 0xFF, 0x00, 0x33, 0x00, 0x44, // Node 2
- 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x17, 0xFF, 0x00, 0x44, // Node 3
- 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x0F, 0xFF // Node 4
-};
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph5TwistedLadder.c b/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph5TwistedLadder.c
deleted file mode 100644
index 2e19249..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph5TwistedLadder.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Five node pop order twisted ladder Topology.
- *
- * The population order fall back to five nodes on a twisted ladder.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/*
- *
- * 4
- * |\
- * | \
- * 2 3
- * | |
- * 0---1
- */
-/**
- * Five node twisted ladder
- */
-/**
- * @dot
- strict graph twl5 {
- node [shape="plaintext"];
- {rank=same; 0; 1}
- {rank=same; 2; 3}
- {rank=same; 4}
- 0 -- 1 ;
- 0 -- 2 ;
- 1 -- 3 ;
- 2 -- 4 ;
- 3 -- 4 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologyFiveTwistedLadder[] =
-{
- 0x05,
- 0x06, 0xFF, 0x04, 0x11, 0x02, 0x22, 0x00, 0x11, 0x00, 0x22, // Node0
- 0x08, 0x00, 0x09, 0xFF, 0x08, 0x00, 0x01, 0x33, 0x00, 0x30, // Node1
- 0x10, 0x00, 0x10, 0x00, 0x11, 0xFF, 0x00, 0x40, 0x01, 0x44, // Node2
- 0x00, 0x11, 0x00, 0x11, 0x00, 0x14, 0x12, 0xFF, 0x02, 0x44, // Node3
- 0x00, 0x22, 0x00, 0x23, 0x00, 0x22, 0x04, 0x33, 0x0C, 0xFF // Node4
-};
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph6DoubloonLower.c b/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph6DoubloonLower.c
deleted file mode 100644
index 6f5e0b5..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph6DoubloonLower.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Six node hydra Topology using "Doubloon/Drachma", Lower nodes remain.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/**
- * 6 node hydra doubloon lower nodes, 3 MCM processors.
- * For partial populations, note nodes are removed in pairs.
- */
-/**
- * @dot
- strict graph doubloon8lower {
- node [shape="plaintext"];
- 0 -- 1 ; 2 -- 3 ; 4 -- 5 ;
- 0 -- 2 ; 1 -- 2 ; 2 -- 4 ; 3 -- 5 ;
- 0 -- 4 ; 1 -- 5 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologySixDoubloonLower[] =
-{
- 0x06,
- 0x16, 0xFF, 0x00, 0x11, 0x02, 0x22, 0x00, 0x22, 0x02, 0x44, 0x00, 0x44, // Node 0
- 0x00, 0x00, 0x25, 0xFF, 0x00, 0x22, 0x00, 0x22, 0x00, 0x55, 0x01, 0x55, // Node 1
- 0x08, 0x00, 0x08, 0x11, 0x19, 0xFF, 0x03, 0x33, 0x08, 0x44, 0x00, 0x44, // Node 2
- 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, 0x24, 0xFF, 0x00, 0x55, 0x04, 0x55, // Node 3
- 0x20, 0x00, 0x00, 0x00, 0x20, 0x22, 0x00, 0x22, 0x25, 0xFF, 0x00, 0x55, // Node 4
- 0x00, 0x11, 0x10, 0x11, 0x00, 0x33, 0x10, 0x33, 0x00, 0x44, 0x1A, 0xFF, // Node 5
-};
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph6DoubloonUpper.c b/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph6DoubloonUpper.c
deleted file mode 100644
index f5467aa..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph6DoubloonUpper.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Six node hydra Topology using "Doubloon/Drachma", Upper nodes remain.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/**
- * 6 node hydra drachma, upper nodes remain, 3 MCM processors.
- * For partial population cases, note that nodes are removed in pairs.
- */
-/**
- * @dot
- strict graph doubloon6upper {
- node [shape="plaintext"];
- 0 -- 1 ; 2 -- 3 ; 4 -- 5 ;
- 0 -- 2 ; 1 -- 2 ; 2 -- 4 ; 3 -- 5 ;
- 0 -- 4 ; 1 -- 5 ; 2 -- 5 ; 3 -- 4 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologySixDoubloonUpper[] =
-{
- 0x06,
- 0x16, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x22, 0x02, 0x44, 0x00, 0x44, // Node 0
- 0x00, 0x00, 0x25, 0xFF, 0x00, 0x22, 0x00, 0x22, 0x00, 0x55, 0x01, 0x55, // Node 1
- 0x08, 0x00, 0x08, 0x11, 0x3B, 0xFF, 0x03, 0x33, 0x00, 0x44, 0x00, 0x55, // Node 2
- 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, 0x34, 0xFF, 0x00, 0x44, 0x00, 0x55, // Node 3
- 0x20, 0x00, 0x00, 0x00, 0x00, 0x22, 0x00, 0x33, 0x2D, 0xFF, 0x00, 0x55, // Node 4
- 0x00, 0x11, 0x10, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x1E, 0xFF, // Node 5
-};
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph6FullyConnected.c b/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph6FullyConnected.c
deleted file mode 100644
index 5ecabdf..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph6FullyConnected.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Six node Fully Connected Topology.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/**
- * 6 node fully connected
- */
-/**
- * @dot
- strict graph full6 {
- node [shape="plaintext"];
- 0 -- 1 ;
- 0 -- 2 ;
- 0 -- 3 ;
- 0 -- 4 ;
- 0 -- 5 ;
- 1 -- 2 ;
- 1 -- 3 ;
- 1 -- 4 ;
- 1 -- 5 ;
- 2 -- 3 ;
- 2 -- 4 ;
- 2 -- 5 ;
- 3 -- 4 ;
- 3 -- 5 ;
- 4 -- 5 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologySixFully[] =
-{
- 0x06,
- 0x3E, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, // Node 0
- 0x00, 0x00, 0x3D, 0xFF, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, // Node 1
- 0x00, 0x00, 0x00, 0x11, 0x3B, 0xFF, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, // Node 2
- 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x37, 0xFF, 0x00, 0x44, 0x00, 0x55, // Node 3
- 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x2F, 0xFF, 0x00, 0x55, // Node 4
- 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x1F, 0xFF // Node 5
-};
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph6TwinTriangles.c b/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph6TwinTriangles.c
deleted file mode 100644
index 3ab2f9c..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph6TwinTriangles.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * A six node Topology of three MCMs.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/* (2 fully connected three ways connected at the 'corners')
- *
- * 5
- * /| \
- * / 1 - 3
- * / / /
- * 4 / /
- * | \ /
- * 0 - 2-
- */
-/**
- * Six Node hydra
- */
-/**
- * @dot
- strict graph hmcm6 {
- node [shape="plaintext"];
- subgraph even {
- 0 -- 2 ; 2 -- 4 ;
- 0 -- 4 ;
- }
- subgraph odd {
- 1 -- 3 ; 3 -- 5
- 1 -- 5 ;
- }
- {rank=same; 0; 2; 1; 3}
- {rank=same; 4; 5}
- 0 -- 1 ; 2 -- 3 ; 4 -- 5 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologySixTwinTriangles[] =
-{
- 0x06,
- 0x16, 0xFF, 0x00, 0x11, 0x02, 0x22, 0x00, 0x22, 0x02, 0x44, 0x00, 0x44, // Node 0
- 0x00, 0x00, 0x29, 0xFF, 0x00, 0x33, 0x01, 0x33, 0x00, 0x55, 0x01, 0x55, // Node 1
- 0x08, 0x00, 0x00, 0x00, 0x19, 0xFF, 0x00, 0x33, 0x08, 0x44, 0x00, 0x44, // Node 2
- 0x00, 0x11, 0x04, 0x11, 0x00, 0x22, 0x26, 0xFF, 0x00, 0x55, 0x04, 0x55, // Node 3
- 0x20, 0x00, 0x00, 0x00, 0x20, 0x22, 0x00, 0x22, 0x25, 0xFF, 0x00, 0x55, // Node 4
- 0x00, 0x11, 0x10, 0x11, 0x00, 0x33, 0x10, 0x33, 0x00, 0x44, 0x1A, 0xFF, // Node 5
-};
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph6TwistedLadder.c b/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph6TwistedLadder.c
deleted file mode 100644
index e0c79f8..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph6TwistedLadder.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Six node pop order twisted ladder Topology.
- *
- * The population order fall back to Six nodes on a twisted ladder.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/*
- *
- * 4 5
- * |\ /|
- * |/ \|
- * 2 3
- * | |
- * 0---1
- */
-/**
- * 6 node twisted ladder
- */
-/**
- * @dot
- strict graph twl6 {
- node [shape="plaintext"];
- {rank=same; 0; 1}
- {rank=same; 2; 3}
- {rank=same; 4; 5}
- 0 -- 1 ;
- 0 -- 2 ;
- 1 -- 3 ;
- 2 -- 4 ;
- 2 -- 5 ;
- 3 -- 4 ;
- 3 -- 5 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologySixTwistedLadder[] =
-{
- 0x06,
- 0x06, 0xFF, 0x04, 0x11, 0x02, 0x22, 0x00, 0x11, 0x02, 0x22, 0x00, 0x12, // Node0
- 0x08, 0x00, 0x09, 0xFF, 0x00, 0x00, 0x01, 0x33, 0x00, 0x03, 0x01, 0x33, // Node1
- 0x30, 0x00, 0x00, 0x00, 0x31, 0xFF, 0x00, 0x54, 0x21, 0x44, 0x00, 0x55, // Node2
- 0x00, 0x11, 0x30, 0x11, 0x00, 0x45, 0x32, 0xFF, 0x00, 0x44, 0x12, 0x55, // Node3
- 0x00, 0x22, 0x00, 0x32, 0x08, 0x22, 0x00, 0x33, 0x0C, 0xFF, 0x00, 0x32, // Node4
- 0x00, 0x23, 0x00, 0x33, 0x00, 0x22, 0x04, 0x33, 0x00, 0x23, 0x0C, 0xFF // Node5
-};
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph7FullyConnected.c b/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph7FullyConnected.c
deleted file mode 100644
index 868ac98..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph7FullyConnected.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Seven node Fully Connected Topology.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/**
- * 7 node fully connected
- */
-/**
- * @dot
- strict graph full7 {
- node [shape="plaintext"];
- 0 -- 1 ; 1 -- 2 ; 2 -- 3 ; 3 -- 4 ; 4 -- 5 ; 5 -- 6 ;
- 0 -- 2 ; 1 -- 3 ; 2 -- 4 ; 3 -- 5 ; 4 -- 6 ;
- 0 -- 3 ; 1 -- 4 ; 2 -- 5 ; 3 -- 6 ;
- 0 -- 4 ; 1 -- 5 ; 2 -- 6 ;
- 0 -- 5 ; 1 -- 6 ;
- 0 -- 6 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologySevenFully[] =
-{
- 0x07,
- 0x7E, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, // Node 0
- 0x00, 0x00, 0x7D, 0xFF, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, // Node 1
- 0x00, 0x00, 0x00, 0x11, 0x7B, 0xFF, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, // Node 2
- 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x77, 0xFF, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, // Node 3
- 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x6F, 0xFF, 0x00, 0x55, 0x00, 0x66, // Node 4
- 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x5F, 0xFF, 0x00, 0x66, // Node 5
- 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x3F, 0xFF // Node 6
-};
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph7TwistedLadder.c b/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph7TwistedLadder.c
deleted file mode 100644
index 422c379..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph7TwistedLadder.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Seven node pop order twisted ladder Topology.
- *
- * The population order fall back to Seven nodes on a twisted ladder.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/* 6
- * |
- * 4 5
- * |\ /|
- * |/ \|
- * 2 3
- * | |
- * 0---1
- */
-/**
- * 7 node twisted ladder
- */
-/**
- * @dot
- strict graph twl7 {
- node [shape="plaintext"];
- {rank=same; 0; 1}
- {rank=same; 2; 3}
- {rank=same; 4; 5}
- {rank=same; 6}
- 0 -- 1 ;
- 0 -- 2 ;
- 1 -- 3 ;
- 2 -- 4 ;
- 2 -- 5 ;
- 3 -- 4 ;
- 3 -- 5 ;
- 4 -- 6 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologySevenTwistedLadder[] =
-{
- 0x07,
- 0x06, 0xFF, 0x00, 0x11, 0x02, 0x22, 0x00, 0x12, 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, // Node0
- 0x00, 0x00, 0x09, 0xFF, 0x00, 0x03, 0x01, 0x33, 0x00, 0x33, 0x00, 0x33, 0x00, 0x33, // Node1
- 0x30, 0x00, 0x00, 0x50, 0x31, 0xFF, 0x00, 0x54, 0x21, 0x44, 0x01, 0x55, 0x21, 0x44, // Node2
- 0x00, 0x41, 0x30, 0x11, 0x00, 0x45, 0x32, 0xFF, 0x02, 0x44, 0x12, 0x55, 0x02, 0x44, // Node3
- 0x48, 0x22, 0x40, 0x33, 0x48, 0x22, 0x40, 0x33, 0x4C, 0xFF, 0x40, 0x32, 0x0C, 0x66, // Node4
- 0x00, 0x22, 0x04, 0x33, 0x00, 0x22, 0x04, 0x33, 0x00, 0x23, 0x0C, 0xFF, 0x00, 0x23, // Node5
- 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x10, 0xFF // Node6
-};
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph8DoubloonM.c b/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph8DoubloonM.c
deleted file mode 100644
index 90f5eb1..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph8DoubloonM.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Eight node hydra Topology using "Doubloon/Drachma".
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-/**
- * 8 node hydra doubloon, 4 MCM processors.
- */
-/**
- * @dot
- strict graph doubloon8 {
- node [shape="plaintext"];
- 0 -- 1 ; 2 -- 3 ; 4 -- 5 ; 6 -- 7 ;
- 0 -- 2 ; 1 -- 2 ; 2 -- 4 ; 3 -- 5 ; 4 -- 6 ; 5 -- 6 ;
- 0 -- 4 ; 1 -- 5 ; 2 -- 6 ; 3 -- 7 ;
- 0 -- 6 ; 1 -- 7 ; 2 -- 7 ; 3 -- 6
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologyEightDoubloon[] =
-{
- 0x08,
- 0x56, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x22, 0x02, 0x44, 0x00, 0x44, 0x02, 0x66, 0x00, 0x66, // Node 0
- 0x00, 0x00, 0xA5, 0xFF, 0x00, 0x22, 0x00, 0x22, 0x00, 0x55, 0x01, 0x55, 0x00, 0x77, 0x01, 0x77, // Node 1
- 0x08, 0x00, 0x08, 0x11, 0xDB, 0xFF, 0x03, 0x33, 0x08, 0x44, 0x00, 0x44, 0x00, 0x66, 0x00, 0x77, // Node 2
- 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, 0xE4, 0xFF, 0x00, 0x55, 0x04, 0x55, 0x00, 0x66, 0x00, 0x77, // Node 3
- 0x20, 0x00, 0x00, 0x00, 0x20, 0x22, 0x00, 0x22, 0x65, 0xFF, 0x00, 0x55, 0x00, 0x66, 0x00, 0x66, // Node 4
- 0x00, 0x11, 0x10, 0x11, 0x00, 0x33, 0x10, 0x33, 0x00, 0x44, 0x5A, 0xFF, 0x00, 0x66, 0x00, 0x66, // Node 5
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x22, 0x00, 0x33, 0x80, 0x44, 0x80, 0x55, 0xBD, 0xFF, 0x30, 0x77, // Node 6
- 0x00, 0x11, 0x40, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x66, 0x00, 0x66, 0x00, 0x66, 0x4E, 0xFF // Node 7
-};
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph8FullyConnected.c b/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph8FullyConnected.c
deleted file mode 100644
index 8c165d2..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph8FullyConnected.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Eight node Fully Connected Topology.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-/**
- * 8 node fully connected
- */
-/**
- * @dot
- strict graph full8 {
- node [shape="plaintext"];
- 0 -- 1 ; 1 -- 2 ; 2 -- 3 ; 3 -- 4 ; 4 -- 5 ; 5 -- 6 ; 6 -- 7 ;
- 0 -- 2 ; 1 -- 3 ; 2 -- 4 ; 3 -- 5 ; 4 -- 6 ; 5 -- 7 ;
- 0 -- 3 ; 1 -- 4 ; 2 -- 5 ; 3 -- 6 ; 4 -- 7 ;
- 0 -- 4 ; 1 -- 5 ; 2 -- 6 ; 3 -- 7 ;
- 0 -- 5 ; 1 -- 6 ; 2 -- 7 ;
- 0 -- 6 ; 1 -- 7 ;
- 0 -- 7 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologyEightFully[] =
-{
- 0x08,
- 0xFE, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, 0x00, 0x77, // Node 0
- 0x00, 0x00, 0xFD, 0xFF, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, 0x00, 0x77, // Node 1
- 0x00, 0x00, 0x00, 0x11, 0xFB, 0xFF, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, 0x00, 0x77, // Node 2
- 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0xF7, 0xFF, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, 0x00, 0x77, // Node 3
- 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0xEF, 0xFF, 0x00, 0x55, 0x00, 0x66, 0x00, 0x77, // Node 4
- 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0xDF, 0xFF, 0x00, 0x66, 0x00, 0x77, // Node 5
- 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0xBF, 0xFF, 0x00, 0x77, // Node 6
- 0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, 0x7F, 0xFF // Node 7
-};
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph8Ladder.c b/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph8Ladder.c
deleted file mode 100644
index c1ec563..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph8Ladder.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Eight node Ladder Topology.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/* 6---7
- * | |
- * 4---5
- * | |
- * 2---3
- * | |
- * 0---1
- */
-/**
- * 8 node ladder
- */
-/**
- * @dot
- strict graph ladder8 {
- node [shape="plaintext"];
- {rank=same; 0; 1}
- {rank=same; 2; 3}
- {rank=same; 4; 5}
- {rank=same; 6; 7}
- 0 -- 1 ;
- 0 -- 2 ;
- 1 -- 3 ;
- 2 -- 4 ;
- 2 -- 3 ;
- 3 -- 5 ;
- 4 -- 5 ;
- 4 -- 6 ;
- 5 -- 7 ;
- 6 -- 7 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologyEightStraightLadder[] =
-{
- 0x08,
- 0x06, 0xFF, 0x00, 0x11, 0x02, 0x22, 0x00, 0x22, 0x02, 0x22, 0x00, 0x22, 0x02, 0x22, 0x00, 0x22, // Node0
- 0x00, 0x00, 0x09, 0xFF, 0x00, 0x33, 0x01, 0x33, 0x00, 0x33, 0x01, 0x33, 0x00, 0x33, 0x01, 0x33, // Node1
- 0x18, 0x00, 0x00, 0x00, 0x19, 0xFF, 0x00, 0x33, 0x09, 0x44, 0x00, 0x44, 0x09, 0x44, 0x00, 0x44, // Node2
- 0x00, 0x11, 0x24, 0x11, 0x00, 0x22, 0x26, 0xFF, 0x00, 0x55, 0x06, 0x55, 0x00, 0x55, 0x06, 0x55, // Node3
- 0x60, 0x22, 0x00, 0x22, 0x60, 0x22, 0x00, 0x22, 0x64, 0xFF, 0x00, 0x55, 0x24, 0x66, 0x00, 0x66, // Node4
- 0x00, 0x33, 0x90, 0x33, 0x00, 0x33, 0x90, 0x33, 0x00, 0x44, 0x98, 0xFF, 0x00, 0x77, 0x18, 0x77, // Node5
- 0x80, 0x44, 0x00, 0x44, 0x80, 0x44, 0x00, 0x44, 0x80, 0x44, 0x00, 0x44, 0x90, 0xFF, 0x00, 0x77, // Node6
- 0x00, 0x55, 0x40, 0x55, 0x00, 0x55, 0x40, 0x55, 0x00, 0x55, 0x40, 0x55, 0x00, 0x66, 0x60, 0xFF // Node7
-};
-
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph8TwinFullyFourWays.c b/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph8TwinFullyFourWays.c
deleted file mode 100644
index 44ab008..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph8TwinFullyFourWays.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Eight node Topology of two fully connected four ways.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-
-/* (2 fully connected four ways connected at the 'corners')
- *
- * 5 - 7
- * /| X |
- * / 1 - 3
- * / / / /
- * 4 - 6 /
- * | X | /
- * 0 - 2-
- */
-/**
- * 8 node twin fully connected four ways, connected by the MCM internal links.
- */
-/**
- * @dot
- strict graph hydra8 {
- node [shape="plaintext"];
- subgraph even {
- 0 -- 2 ; 2 -- 4 ; 4 -- 6 ;
- 0 -- 4 ; 2 -- 6 ;
- 0 -- 6 ;
- }
- subgraph odd {
- 1 -- 3 ; 3 -- 5 ; 5 -- 7 ;
- 1 -- 5 ; 3 -- 7 ;
- 1 -- 7 ;
- }
- {rank=same; 0; 2; 1; 3}
- {rank=same; 4; 6; 5; 7}
- 0 -- 1 ; 2 -- 3 ; 4 -- 5 ; 6 -- 7 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologyEightTwinFullyFourWays[] =
-{
- 0x08,
- 0x56, 0xFF, 0x00, 0x11, 0x02, 0x22, 0x00, 0x22, 0x02, 0x44, 0x00, 0x44, 0x02, 0x66, 0x00, 0x66, // Node 0
- 0x00, 0x00, 0xA9, 0xFF, 0x00, 0x33, 0x01, 0x33, 0x00, 0x55, 0x01, 0x55, 0x00, 0x77, 0x01, 0x77, // Node 1
- 0x08, 0x00, 0x00, 0x00, 0x59, 0xFF, 0x00, 0x33, 0x08, 0x44, 0x00, 0x44, 0x08, 0x66, 0x00, 0x66, // Node 2
- 0x00, 0x11, 0x04, 0x11, 0x00, 0x22, 0xA6, 0xFF, 0x00, 0x55, 0x04, 0x55, 0x00, 0x77, 0x04, 0x77, // Node 3
- 0x20, 0x00, 0x00, 0x00, 0x20, 0x22, 0x00, 0x22, 0x65, 0xFF, 0x00, 0x55, 0x20, 0x66, 0x00, 0x66, // Node 4
- 0x00, 0x11, 0x10, 0x11, 0x00, 0x33, 0x10, 0x33, 0x00, 0x44, 0x9A, 0xFF, 0x00, 0x77, 0x10, 0x77, // Node 5
- 0x80, 0x00, 0x00, 0x00, 0x80, 0x22, 0x00, 0x22, 0x80, 0x44, 0x00, 0x44, 0x95, 0xFF, 0x00, 0x77, // Node 6
- 0x00, 0x11, 0x40, 0x11, 0x00, 0x33, 0x40, 0x33, 0x00, 0x55, 0x40, 0x55, 0x00, 0x66, 0x6A, 0xFF // Node 7
-};
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph8TwistedLadder.c b/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph8TwistedLadder.c
deleted file mode 100644
index 88c286c..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htGraph/htGraph8TwistedLadder.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Eight node twisted ladder Topology.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "Porting.h"
-#include "htTopologies.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-/* 6---7
- * | |
- * 4 5
- * |\ /|
- * |/ \|
- * 2 3
- * | |
- * 0---1
- */
-/**
- * 8 node twisted ladder
- */
-/**
- * @dot
- strict graph twl8 {
- node [shape="plaintext"];
- {rank=same; 0; 1}
- {rank=same; 2; 3}
- {rank=same; 4; 5}
- {rank=same; 6; 7}
- 0 -- 1 ;
- 0 -- 2 ;
- 1 -- 3 ;
- 2 -- 4 ;
- 2 -- 5 ;
- 3 -- 4 ;
- 3 -- 5 ;
- 4 -- 6 ;
- 5 -- 7 ;
- 6 -- 7 ;
- }
- @enddot
- *
- */
-CONST UINT8 ROMDATA amdHtTopologyEightTwistedLadder[] =
-{
- 0x08,
- 0x06, 0xFF, 0x00, 0x11, 0x02, 0x22, 0x00, 0x12, 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, // Node0
- 0x00, 0x00, 0x09, 0xFF, 0x00, 0x03, 0x01, 0x33, 0x00, 0x33, 0x00, 0x33, 0x00, 0x33, 0x00, 0x33, // Node1
- 0x30, 0x00, 0x00, 0x50, 0x31, 0xFF, 0x00, 0x54, 0x21, 0x44, 0x01, 0x55, 0x21, 0x44, 0x01, 0x55, // Node2
- 0x00, 0x41, 0x30, 0x11, 0x00, 0x45, 0x32, 0xFF, 0x02, 0x44, 0x12, 0x55, 0x02, 0x44, 0x12, 0x55, // Node3
- 0x48, 0x22, 0x40, 0x33, 0x48, 0x22, 0x40, 0x33, 0x4C, 0xFF, 0x00, 0x32, 0x0C, 0x66, 0x00, 0x36, // Node4
- 0x80, 0x22, 0x84, 0x33, 0x80, 0x22, 0x84, 0x33, 0x00, 0x23, 0x8C, 0xFF, 0x00, 0x27, 0x0C, 0x77, // Node5
- 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x80, 0x44, 0x00, 0x74, 0x90, 0xFF, 0x00, 0x77, // Node6
- 0x00, 0x55, 0x00, 0x55, 0x00, 0x55, 0x00, 0x55, 0x00, 0x65, 0x40, 0x55, 0x00, 0x66, 0x60, 0xFF // Node7
-};
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htInterface.c b/src/vendorcode/amd/agesa/Proc/HT/htInterface.c
deleted file mode 100644
index 01cdd13..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htInterface.c
+++ /dev/null
@@ -1,242 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * External Interface implementation.
- *
- * Contains routines for implementing the interface to the client BIOS.
- * This file includes the interface access constructor.
- * This file implements build options using conditional compilation.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "OptionsHt.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "htInterface.h"
-#include "CommonReturns.h"
-#include "htInterfaceGeneral.h"
-#include "htInterfaceCoherent.h"
-#include "htInterfaceNonCoherent.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_HTINTERFACE_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-extern CONST OPTION_HT_CONFIGURATION OptionHtConfiguration;
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/**
- * The default initializer for the HT internal interface, full features.
- */
-CONST HT_INTERFACE ROMDATA HtInterfaceDefault =
-{
- GetCpu2CpuPcbLimits,
- GetSkipRegang,
- NewHopCountTable,
- GetOverrideBusNumbers,
- GetManualBuidSwapList,
- GetDeviceCapOverride,
- GetIoPcbLimits,
- GetSocketFromMap,
- GetIgnoreLink,
- PostMapToAp,
- NewNodeAndSocketTables,
- CleanMapsAfterError,
- SetNodeToSocketMap,
- GetMinNbCoreFreq
-};
-
-/**
- * The non-coherent only build option initializer for the HT internal interface.
- */
-CONST HT_INTERFACE ROMDATA HtInterfaceNonCoherentOnly =
-{
- (PF_GET_CPU_2_CPU_PCB_LIMITS)CommonVoid,
- (PF_GET_SKIP_REGANG)CommonReturnFalse,
- (PF_NEW_HOP_COUNT_TABLE)CommonVoid,
- GetOverrideBusNumbers,
- GetManualBuidSwapList,
- GetDeviceCapOverride,
- GetIoPcbLimits,
- GetSocketFromMap,
- GetIgnoreLink,
- PostMapToAp,
- NewNodeAndSocketTables,
- (PF_CLEAN_MAPS_AFTER_ERROR)CommonVoid,
- SetNodeToSocketMap,
- GetMinNbCoreFreq
-};
-
-/**
- * Topology Maps only feature build option initializer for the HT internal interface.
- */
-CONST HT_INTERFACE ROMDATA HtInterfaceMapsOnly =
-{
- (PF_GET_CPU_2_CPU_PCB_LIMITS)CommonVoid,
- (PF_GET_SKIP_REGANG)CommonReturnFalse,
- (PF_NEW_HOP_COUNT_TABLE)CommonVoid,
- (PF_GET_OVERRIDE_BUS_NUMBERS)CommonReturnFalse,
- (PF_GET_MANUAL_BUID_SWAP_LIST)CommonReturnFalse,
- (PF_GET_DEVICE_CAP_OVERRIDE)CommonVoid,
- (PF_GET_IO_PCB_LIMITS)CommonVoid,
- (PF_GET_SOCKET_FROM_MAP)CommonReturnZero8,
- (PF_GET_IGNORE_LINK)CommonReturnFalse,
- PostMapToAp,
- NewNodeAndSocketTables,
- (PF_CLEAN_MAPS_AFTER_ERROR)CommonVoid,
- SetNodeToSocketMap,
- (PF_GET_MIN_NB_CORE_FREQ)CommonReturnZero8
-};
-
-/**
- * No features build option initializer for the HT internal interface.
- */
-CONST HT_INTERFACE ROMDATA HtInterfaceNone =
-{
- (PF_GET_CPU_2_CPU_PCB_LIMITS)CommonVoid,
- (PF_GET_SKIP_REGANG)CommonReturnFalse,
- (PF_NEW_HOP_COUNT_TABLE)CommonVoid,
- (PF_GET_OVERRIDE_BUS_NUMBERS)CommonReturnFalse,
- (PF_GET_MANUAL_BUID_SWAP_LIST)CommonReturnFalse,
- (PF_GET_DEVICE_CAP_OVERRIDE)CommonVoid,
- (PF_GET_IO_PCB_LIMITS)CommonVoid,
- (PF_GET_SOCKET_FROM_MAP)CommonReturnZero8,
- (PF_GET_IGNORE_LINK)CommonReturnFalse,
- (PF_POST_MAP_TO_AP)CommonVoid,
- (PF_NEW_NODE_AND_SOCKET_TABLES)CommonVoid,
- (PF_CLEAN_MAPS_AFTER_ERROR)CommonVoid,
- (PF_SET_NODE_TO_SOCKET_MAP)CommonVoid,
- (PF_GET_MIN_NB_CORE_FREQ)CommonReturnZero8
-};
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * A constructor for the internal Ht Interface.
- *
- * The install has a reference to the initializer appropriate to the user selected build
- * options. Use the selected initializer to construct the internal interface.
- *
- * @param[in,out] HtInterface Contains pointer to HT Interface structure to initialize.
- * @param[in] StdHeader Opaque handle to standard config header
- *
-*/
-VOID
-NewHtInterface (
- OUT HT_INTERFACE *HtInterface,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- LibAmdMemCopy (
- (VOID *) HtInterface,
- (VOID *) OptionHtConfiguration.HtOptionInternalInterface,
- (sizeof (HT_INTERFACE)),
- StdHeader
- );
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * A "constructor" for the HyperTransport external interface.
- *
- * Sets inputs to valid, basic level, defaults.
- *
- * Copy the initial default values from the build options tables to the interface struct.
- *
- * @param[in] StdHeader Opaque handle to standard config header
- * @param[in] AmdHtInterface HT Interface structure to initialize.
- *
- * @retval AGESA_SUCCESS Constructors are not allowed to fail
-*/
-AGESA_STATUS
-AmdHtInterfaceConstructor (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN AMD_HT_INTERFACE *AmdHtInterface
- )
-{
- LibAmdMemCopy (
- (VOID *) AmdHtInterface,
- (VOID *) OptionHtConfiguration.HtOptionPlatformDefaults,
- (UINT32) (sizeof (AMD_HT_INTERFACE)),
- StdHeader
- );
- return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htInterface.h b/src/vendorcode/amd/agesa/Proc/HT/htInterface.h
deleted file mode 100644
index 84183b5..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htInterface.h
+++ /dev/null
@@ -1,490 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Internal access to HT Interface.
- *
- * This file provides definitions used by HT internal modules. The
- * external HT interface (in agesa.h) is accessed using these methods.
- * This keeps the HT Feature implementations abstracted from the HT
- * interface.
- *
- * This file includes the interface access constructor and interface
- * support which is not removed with various build options.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 39162 $ @e \$Date: 2010-10-07 22:41:37 +0800 (Thu, 07 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _HT_INTERFACE_H_
-#define _HT_INTERFACE_H_
-
-/**
- * @page htimplintf HT Internal Interface Implementation Guide
- *
- * HT Internal Interface provides access to the HT Component external interface (see AGESA.h),
- * in a manner that isolates calling code from knowledge about the external interface or which
- * interfaces are supported in the current build.
- *
- * @par Adding a Method to HT Internal Interface
- *
- * To add a new method to the HT Internal Interface, follow these steps.
- * <ul>
- * <li> Create a typedef for the Method with the correct parameters and return type.
- *
- * <ul>
- * <li> Name the method typedef (F_METHOD_NAME)(), where METHOD_NAME is the same name as the method table item,
- * but with "_"'s and UPPERCASE, rather than mixed case.
- * @n <tt> typedef VOID (F_METHOD_NAME)(); </tt> @n
- *
- * <li> Make a reference type for references to a method implementation:
- * @n <tt> /// Reference to a Method </tt>
- * @n <tt> typedef F_METHOD_NAME *PF_METHOD_NAME </tt> @n
- * </ul>
- *
- * <li> Provide a standard doxygen function preamble for the Method typedef. Begin the
- * detailed description by providing a reference to the method instances page by including
- * the lines below:
- * @code
- * *
- * * @HtInterfaceInstances
- * *
- * @endcode
- * @note It is important to provide documentation for the method type, because the method may not
- * have an implementation in any families supported by the current package. @n
- *
- * <li> Add to the HT_INTERFACE struct an item for the Method:
- * @n <tt> PF_METHOD_NAME MethodName; ///< Method: description. </tt> @n
- * </ul>
- *
- * @par Implementing an HT Internal Interface Instance of the method.
- *
- * To implement an instance of a method for a specific interface follow these steps.
- *
- * - In appropriate files, implement the method with the return type and parameters
- * matching the method typedef.
- *
- * - Name the function MethodName().
- *
- * - Create a doxygen function preamble for the method instance. Begin the detailed description with
- * an Implements command to reference the method type and add this instance to the Method Instances page.
- * @code
- * *
- * * @HtInterfaceMethod{::F_METHOD_NAME}.
- * *
- * @endcode
- *
- * - To access other Ht internal interface routines or data as part of the method implementation, the function
- * must use HtInterface->OtherMethod(). Do not directly access other HT internal interface
- * routines, because in the table there may be overrides or this routine may be shared by multiple families.
- *
- * - Add the instance to the HT_INTERFACE instances.
- *
- * - If a configuration does not need an instance of the method use one of the CommonReturns from
- * CommonReturns.h with the same return type.
- *
- * @par Invoking HT Internal Interface Methods.
- *
- * The first step is carried out only once by the top level HT entry point.
- * @n @code
- * HT_INTERFACE HtInterface;
- * // Get the current HT internal interface (to HtBlock data)
- * NewHtInterface (&HtInterface);
- * State->HtInterface = &HtInterface;
- * @endcode
- *
- * The following example shows how to invoke a HT Internal Interface method.
- * @n @code
- * State->HtInterface->MethodName ();
- * @endcode
- *
- */
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/**
- * Get limits for CPU to CPU Links.
- *
- * @HtInterfaceInstances.
- *
- * @param[in] NodeA One Node on which this Link is located
- * @param[in] LinkA The Link on this Node
- * @param[in] NodeB The other Node on which this Link is located
- * @param[in] LinkB The Link on that Node
- * @param[in,out] ABLinkWidthLimit modify to change the Link Width In
- * @param[in,out] BALinkWidthLimit modify to change the Link Width Out
- * @param[in,out] PcbFreqCap modify to change the Link's frequency capability
- * @param[in] State the input data
- *
- */
-typedef VOID F_GET_CPU_2_CPU_PCB_LIMITS (
- IN UINT8 NodeA,
- IN UINT8 LinkA,
- IN UINT8 NodeB,
- IN UINT8 LinkB,
- IN OUT UINT8 *ABLinkWidthLimit,
- IN OUT UINT8 *BALinkWidthLimit,
- IN OUT UINT32 *PcbFreqCap,
- IN STATE_DATA *State
- );
-/// Reference to a method.
-typedef F_GET_CPU_2_CPU_PCB_LIMITS *PF_GET_CPU_2_CPU_PCB_LIMITS;
-
-/**
- * Skip reganging of subLinks.
- *
- * @HtInterfaceInstances.
- *
- * @param[in] NodeA One Node on which this Link is located
- * @param[in] LinkA The Link on this Node
- * @param[in] NodeB The other Node on which this Link is located
- * @param[in] LinkB The Link on that Node
- * @param[in] State the input data
- *
- * @retval MATCHED leave Link unganged
- * @retval POWERED_OFF leave link unganged and power off the paired sublink
- * @retval UNMATCHED regang Link automatically
- */
-typedef FINAL_LINK_STATE F_GET_SKIP_REGANG (
- IN UINT8 NodeA,
- IN UINT8 LinkA,
- IN UINT8 NodeB,
- IN UINT8 LinkB,
- IN STATE_DATA *State
- );
-/// Reference to a method.
-typedef F_GET_SKIP_REGANG *PF_GET_SKIP_REGANG;
-
-/**
- * Manually control bus number assignment.
- *
- * @HtInterfaceInstances.
- *
- * @param[in] Node The Node on which this chain is located
- * @param[in] Link The Link on the host for this chain
- * @param[out] SecBus Secondary Bus number for this non-coherent chain
- * @param[out] SubBus Subordinate Bus number
- * @param[in] State the input data
- *
- * @retval TRUE this routine is supplying the bus numbers
- * @retval FALSE use auto Bus numbering
- */
-typedef BOOLEAN F_GET_OVERRIDE_BUS_NUMBERS (
- IN UINT8 Node,
- IN UINT8 Link,
- OUT UINT8 *SecBus,
- OUT UINT8 *SubBus,
- IN STATE_DATA *State
- );
-/// Reference to a method.
-typedef F_GET_OVERRIDE_BUS_NUMBERS *PF_GET_OVERRIDE_BUS_NUMBERS;
-
-/**
- * Get Manual BUID assignment list.
- *
- * @HtInterfaceInstances.
- *
- * @param[in] Node The Node on which this chain is located
- * @param[in] Link The Link on the host for this chain
- * @param[out] List a pointer to a list, if returns TRUE
- * @param[in] State the input data
- *
- * @retval TRUE use manual List
- * @retval FALSE initialize the Link automatically. List not valid.
- */
-typedef BOOLEAN F_GET_MANUAL_BUID_SWAP_LIST (
- IN UINT8 Node,
- IN UINT8 Link,
- OUT BUID_SWAP_LIST **List,
- IN STATE_DATA *State
- );
-/// Reference to a method.
-typedef F_GET_MANUAL_BUID_SWAP_LIST *PF_GET_MANUAL_BUID_SWAP_LIST;
-
-/**
- * Override capabilities of a device.
- *
- * @HtInterfaceInstances.
- *
- * @param[in] HostNode The Node on which this chain is located
- * @param[in] HostLink The Link on the host for this chain
- * @param[in] Depth The Depth in the I/O chain from the Host
- * @param[in] PciAddress The Device's PCI config address (for callout)
- * @param[in] DevVenId The Device's PCI Vendor + Device ID (offset 0x00)
- * @param[in] Revision The Device's PCI Revision
- * @param[in] Link The Device's Link number (0 or 1)
- * @param[in,out] LinkWidthIn modify to change the Link Width In
- * @param[in,out] LinkWidthOut modify to change the Link Width Out
- * @param[in,out] FreqCap modify to change the Link's frequency capability
- * @param[in,out] Clumping modify to change unit id clumping capability
- * @param[in] State the input data
- *
- */
-typedef VOID F_GET_DEVICE_CAP_OVERRIDE (
- IN UINT8 HostNode,
- IN UINT8 HostLink,
- IN UINT8 Depth,
- IN PCI_ADDR PciAddress,
- IN UINT32 DevVenId,
- IN UINT8 Revision,
- IN UINT8 Link,
- IN OUT UINT8 *LinkWidthIn,
- IN OUT UINT8 *LinkWidthOut,
- IN OUT UINT32 *FreqCap,
- IN OUT UINT32 *Clumping,
- IN STATE_DATA *State
- );
-/// Reference to a method.
-typedef F_GET_DEVICE_CAP_OVERRIDE *PF_GET_DEVICE_CAP_OVERRIDE;
-
-/**
- * Get limits for non-coherent Links.
- *
- * @HtInterfaceInstances.
- *
- * @param[in] HostNode The Node on which this Link is located
- * @param[in] HostLink The Link about to be initialized
- * @param[in] Depth The Depth in the I/O chain from the Host
- * @param[in,out] DownstreamLinkWidthLimit modify to change the Link Width In
- * @param[in,out] UpstreamLinkWidthLimit modify to change the Link Width Out
- * @param[in,out] PcbFreqCap modify to change the Link's frequency capability
- * @param[in] State the input data
- */
-typedef VOID F_GET_IO_PCB_LIMITS (
- IN UINT8 HostNode,
- IN UINT8 HostLink,
- IN UINT8 Depth,
- IN OUT UINT8 *DownstreamLinkWidthLimit,
- IN OUT UINT8 *UpstreamLinkWidthLimit,
- IN OUT UINT32 *PcbFreqCap,
- IN STATE_DATA *State
- );
-/// Reference to a method.
-typedef F_GET_IO_PCB_LIMITS *PF_GET_IO_PCB_LIMITS;
-
-/**
- * Get the Socket number for a given Node number.
- *
- * @HtInterfaceInstances.
- *
- * @param[in] Node Node discovered event data.
- * @param[in] State reference to Node to socket map
- *
- * @return the socket id
- *
- */
-typedef UINT8 F_GET_SOCKET_FROM_MAP (
- IN UINT8 Node,
- IN STATE_DATA *State
- );
-/// Reference to a method.
-typedef F_GET_SOCKET_FROM_MAP *PF_GET_SOCKET_FROM_MAP;
-
-/**
- * Ignore a Link.
- *
- * @HtInterfaceInstances.
- *
- * @param[in] Node The Node on which this Link is located
- * @param[in] Link The Link about to be initialized
- * @param[in] NbList The northbridge default ignore link list
- * @param[in] State the input data
- *
- * @retval MATCHED ignore this Link and skip it
- * @retval POWERED_OFF ignore this link and power it off.
- * @retval UNMATCHED initialize the Link normally
- */
-typedef FINAL_LINK_STATE F_GET_IGNORE_LINK (
- IN UINT8 Node,
- IN UINT8 Link,
- IN IGNORE_LINK *NbIgnoreLinkList,
- IN STATE_DATA *State
- );
-/// Reference to a method.
-typedef F_GET_IGNORE_LINK *PF_GET_IGNORE_LINK;
-
-/**
- * Post Node id and other context info to AP cores via mailbox.
- *
- * @HtInterfaceInstances.
- *
- * @param[in] State Our state
- */
-typedef VOID F_POST_MAP_TO_AP (
- IN STATE_DATA *State
- );
-/// Reference to a method.
-typedef F_POST_MAP_TO_AP *PF_POST_MAP_TO_AP;
-
-/**
- * Clean up the map structures after severe event has caused a fall back to 1 node.
- *
- * @HtInterfaceInstances.
- *
- * @param[in] State Our state
- */
-typedef VOID F_CLEAN_MAPS_AFTER_ERROR (
- IN STATE_DATA *State
- );
-/// Reference to a method.
-typedef F_CLEAN_MAPS_AFTER_ERROR *PF_CLEAN_MAPS_AFTER_ERROR;
-
-/**
- * Get a new Socket Die to Node Map.
- *
- * @HtInterfaceInstances.
- *
- * @param[in,out] State global state
- */
-typedef VOID F_NEW_NODE_AND_SOCKET_TABLES (
- IN OUT STATE_DATA *State
- );
-/// Reference to a method.
-typedef F_NEW_NODE_AND_SOCKET_TABLES *PF_NEW_NODE_AND_SOCKET_TABLES;
-
-/**
- * Fill in the socket's Node id when a processor is discovered in that socket.
- *
- * @HtInterfaceInstances.
- *
- * @param[in] Node Node from which a new node was discovered
- * @param[in] CurrentNodeModule The current node's module id in it's processor.
- * @param[in] PackageLink The package level link from Node to NewNode.
- * @param[in] NewNode The new node's id
- * @param[in] HardwareSocket If we use the hardware method (preferred), this is the socket of new node.
- * @param[in] Module The new node's module id in it's processor.
- * @param[in] State our State
- */
-typedef VOID F_SET_NODE_TO_SOCKET_MAP (
- IN UINT8 Node,
- IN UINT8 CurrentNodeModule,
- IN UINT8 PackageLink,
- IN UINT8 NewNode,
- IN UINT8 HardwareSocket,
- IN UINT8 Module,
- IN STATE_DATA *State
- );
-/// Reference to a method.
-typedef F_SET_NODE_TO_SOCKET_MAP *PF_SET_NODE_TO_SOCKET_MAP;
-
-/**
- * Get a new, empty Hop Count Table, to make one for the installed topology.
- *
- * @HtInterfaceInstances.
- *
- * @param[in,out] State Keep our buffer handle.
- *
- */
-typedef VOID F_NEW_HOP_COUNT_TABLE (
- IN OUT STATE_DATA *State
- );
-/// Reference to a method.
-typedef F_NEW_HOP_COUNT_TABLE *PF_NEW_HOP_COUNT_TABLE;
-
-/**
- * Get the minimum Northbridge frequency for the system.
- *
- * @HtInterfaceInstances.
- *
- * Invoke the CPU component power mgt interface.
- *
- * @param[in] PlatformConfig Platform profile/build option config structure.
- * @param[in] StdHeader Config for library and services.
- *
- * @return Frequency in MHz.
- *
- */
-typedef UINT32 F_GET_MIN_NB_CORE_FREQ (
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-/// Reference to a Method.
-typedef F_GET_MIN_NB_CORE_FREQ *PF_GET_MIN_NB_CORE_FREQ;
-
-/**
- * The HT Interface, feature code uses these methods to get interface parameters.
- */
-struct _HT_INTERFACE { // See Forward Declaration in HtFeates.h
- PF_GET_CPU_2_CPU_PCB_LIMITS GetCpu2CpuPcbLimits; /**< Method: Get link limits for coherent links. */
- PF_GET_SKIP_REGANG GetSkipRegang; /**< Method: Skip reganging for coherent links. */
- PF_NEW_HOP_COUNT_TABLE NewHopCountTable; /**< Method: Get a new hop count table. */
- PF_GET_OVERRIDE_BUS_NUMBERS GetOverrideBusNumbers; /**< Method: Control Bus number assignment. */
- PF_GET_MANUAL_BUID_SWAP_LIST GetManualBuidSwapList; /**< Method: Assign device IDs. */
- PF_GET_DEVICE_CAP_OVERRIDE GetDeviceCapOverride; /**< Method: Override Device capabilities. */
- PF_GET_IO_PCB_LIMITS GetIoPcbLimits; /**< Method: Get link limits for noncoherent links. */
- PF_GET_SOCKET_FROM_MAP GetSocketFromMap; /**< Method: Get the Socket for a node id. */
- PF_GET_IGNORE_LINK GetIgnoreLink; /**< Method: Ignore a link. */
- PF_POST_MAP_TO_AP PostMapToAp; /**< Method: Post Socket and other info to AP cores. */
- PF_NEW_NODE_AND_SOCKET_TABLES NewNodeAndSocketTables; /**< Method: Get new socket and node maps. */
- PF_CLEAN_MAPS_AFTER_ERROR CleanMapsAfterError; /**< Method: Clean up maps for forced 1P on error fall back. */
- PF_SET_NODE_TO_SOCKET_MAP SetNodeToSocketMap; /**< Method: Associate a node id with a socket. */
- PF_GET_MIN_NB_CORE_FREQ GetMinNbCoreFreq; /**< Method: Get the minimum northbridge frequency */
-} ;
-
-/*----------------------------------------------------------------------------
- * Prototypes to Interface from Feature Code
- *
- *----------------------------------------------------------------------------
- */
-
-/**
- * A constructor for the internal Ht Interface.
- *
-*/
-VOID
-NewHtInterface (
- OUT HT_INTERFACE *HtInterface,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif /* _HT_INTERFACE_H_ */
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htInterfaceCoherent.c b/src/vendorcode/amd/agesa/Proc/HT/htInterfaceCoherent.c
deleted file mode 100644
index 1d0172e..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htInterfaceCoherent.c
+++ /dev/null
@@ -1,264 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * External Interface implementation for coherent features.
- *
- * Contains routines for accessing the interface to the client BIOS,
- * for support only required for coherent features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "htInterface.h"
-#include "htInterfaceGeneral.h"
-#include "htInterfaceCoherent.h"
-#include "htNb.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_HTINTERFACECOHERENT_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get limits for CPU to CPU Links.
- *
- * @HtInterfaceMethod{::F_GET_CPU_2_CPU_PCB_LIMITS}
- *
- * For each coherent connection this routine is called once. Update the frequency
- * and width if needed for this Link (usually based on board restriction). This is
- * used with CPU device capabilities and northbridge limits to compute the default
- * settings. The input width and frequency are valid, but do not necessarily reflect
- * the minimum setting that will be chosen.
- *
- * @param[in] NodeA One Node on which this Link is located
- * @param[in] LinkA The Link on this Node
- * @param[in] NodeB The other Node on which this Link is located
- * @param[in] LinkB The Link on that Node
- * @param[in,out] ABLinkWidthLimit modify to change the Link Width In
- * @param[in,out] BALinkWidthLimit modify to change the Link Width Out
- * @param[in,out] PcbFreqCap modify to change the Link's frequency capability
- * @param[in] State the input data
- *
- */
-VOID
-GetCpu2CpuPcbLimits (
- IN UINT8 NodeA,
- IN UINT8 LinkA,
- IN UINT8 NodeB,
- IN UINT8 LinkB,
- IN OUT UINT8 *ABLinkWidthLimit,
- IN OUT UINT8 *BALinkWidthLimit,
- IN OUT UINT32 *PcbFreqCap,
- IN STATE_DATA *State
- )
-{
- CPU_TO_CPU_PCB_LIMITS *p;
- UINT8 SocketA;
- UINT8 SocketB;
- UINT8 PackageLinkA;
- UINT8 PackageLinkB;
-
- ASSERT ((NodeA < MAX_NODES) && (NodeB < MAX_NODES));
- ASSERT ((LinkA < State->Nb->MaxLinks) && (LinkB < State->Nb->MaxLinks));
-
- SocketA = State->HtInterface->GetSocketFromMap (NodeA, State);
- PackageLinkA = State->Nb->GetPackageLink (NodeA, LinkA, State->Nb);
- SocketB = State->HtInterface->GetSocketFromMap (NodeB, State);
- PackageLinkB = State->Nb->GetPackageLink (NodeB, LinkB, State->Nb);
-
- if (State->HtBlock->CpuToCpuPcbLimitsList != NULL) {
- p = State->HtBlock->CpuToCpuPcbLimitsList;
-
- while (p->SocketA != HT_LIST_TERMINAL) {
- if (((p->SocketA == SocketA) || (p->SocketA == HT_LIST_MATCH_ANY)) &&
- ((p->LinkA == PackageLinkA) || ((p->LinkA == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLinkA))) ||
- ((p->LinkA == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLinkA)))) &&
- ((p->SocketB == SocketB) || (p->SocketB == HT_LIST_MATCH_ANY)) &&
- ((p->LinkB == PackageLinkB) || ((p->LinkB == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLinkB))) ||
- ((p->LinkB == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLinkB))))) {
- // Found a match, update width and frequency
- *ABLinkWidthLimit = p->ABLinkWidthLimit;
- *BALinkWidthLimit = p->BALinkWidthLimit;
- *PcbFreqCap = p->PcbFreqCap;
- break;
- } else {
- p++;
- }
- }
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Skip reganging of subLinks.
- *
- * @HtInterfaceMethod{::F_GET_SKIP_REGANG}
- *
- * This routine is called whenever two subLinks are both connected to the same CPUs.
- * Normally, unganged sublinks between the same two CPUs are reganged. Return true
- * from this routine to leave the Links unganged.
- *
- * @param[in] NodeA One Node on which this Link is located
- * @param[in] LinkA The Link on this Node
- * @param[in] NodeB The other Node on which this Link is located
- * @param[in] LinkB The Link on that Node
- * @param[in] State the input data
- *
- * @retval MATCHED leave Link unganged
- * @retval POWERED_OFF leave link unganged and power off the paired sublink
- * @retval UNMATCHED regang Link automatically
- */
-FINAL_LINK_STATE
-GetSkipRegang (
- IN UINT8 NodeA,
- IN UINT8 LinkA,
- IN UINT8 NodeB,
- IN UINT8 LinkB,
- IN STATE_DATA *State
- )
-{
- SKIP_REGANG *p;
- FINAL_LINK_STATE Result;
- UINT8 SocketA;
- UINT8 SocketB;
- UINT8 PackageLinkA;
- UINT8 PackageLinkB;
-
- ASSERT ((NodeA < MAX_NODES) && (NodeB < MAX_NODES));
- ASSERT ((LinkA < State->Nb->MaxLinks) && (LinkB < State->Nb->MaxLinks));
-
- Result = UNMATCHED;
- SocketA = State->HtInterface->GetSocketFromMap (NodeA, State);
- PackageLinkA = State->Nb->GetPackageLink (NodeA, LinkA, State->Nb);
- SocketB = State->HtInterface->GetSocketFromMap (NodeB, State);
- PackageLinkB = State->Nb->GetPackageLink (NodeB, LinkB, State->Nb);
-
- if (State->HtBlock->SkipRegangList != NULL) {
- p = State->HtBlock->SkipRegangList;
-
- while (p->SocketA != HT_LIST_TERMINAL) {
- if (((p->SocketA == SocketA) || (p->SocketA == HT_LIST_MATCH_ANY)) &&
- ((p->LinkA == PackageLinkA) || ((p->LinkA == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLinkA))) ||
- ((p->LinkA == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLinkA)))) &&
- ((p->SocketB == SocketB) || (p->SocketB == HT_LIST_MATCH_ANY)) &&
- ((p->LinkB == PackageLinkB) || ((p->LinkB == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLinkB))) ||
- ((p->LinkB == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLinkB))))) {
- // Found a match return final link state
- Result = p->LinkState;
- break;
- } else {
- p++;
- }
- }
- }
- return Result;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get a new, empty Hop Count Table, to make one for the installed topology.
- *
- * @HtInterfaceMethod{::F_NEW_HOP_COUNT_TABLE}
- *
- * For SLIT, publish a matrix with the hop count, by allocating a buffer on heap with a
- * known signature.
- *
- * @param[in,out] State Keep our buffer handle.
- *
- */
-VOID
-NewHopCountTable (
- IN OUT STATE_DATA *State
- )
-{
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
- AllocHeapParams.RequestedBufferSize = sizeof (HOP_COUNT_TABLE);
- AllocHeapParams.BufferHandle = HOP_COUNT_TABLE_HANDLE;
- AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
- if (HeapAllocateBuffer ( &AllocHeapParams, State->ConfigHandle) == AGESA_SUCCESS) {
- State->HopCountTable = (HOP_COUNT_TABLE *)AllocHeapParams.BufferPtr;
- } else {
- State->HopCountTable = NULL;
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htInterfaceCoherent.h b/src/vendorcode/amd/agesa/Proc/HT/htInterfaceCoherent.h
deleted file mode 100644
index c9d9d1f..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htInterfaceCoherent.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Internal access to HT Interface for coherent features.
- *
- * This file provides definitions used by HT internal modules. The
- * external HT interface (in agesa.h) is accessed using these methods.
- * This keeps the HT Feature implementations abstracted from the HT
- * interface.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _HT_INTERFACE_COHERENT_H_
-#define _HT_INTERFACE_COHERENT_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * Prototypes to Interface from Feature Code
- *
- *----------------------------------------------------------------------------
- */
-
-/**
- * Get limits for CPU to CPU Links.
- *
- */
-VOID
-GetCpu2CpuPcbLimits (
- IN UINT8 NodeA,
- IN UINT8 LinkA,
- IN UINT8 NodeB,
- IN UINT8 LinkB,
- IN OUT UINT8 *ABLinkWidthLimit,
- IN OUT UINT8 *BALinkWidthLimit,
- IN OUT UINT32 *PcbFreqCap,
- IN STATE_DATA *State
- );
-
-/**
- * Skip reganging of subLinks.
- *
- */
-FINAL_LINK_STATE
-GetSkipRegang (
- IN UINT8 NodeA,
- IN UINT8 LinkA,
- IN UINT8 NodeB,
- IN UINT8 LinkB,
- IN STATE_DATA *State
- );
-
-/**
- * Get a new, empty Hop Count Table, to make one for the installed topology.
- *
- */
-VOID
-NewHopCountTable (
- IN OUT STATE_DATA *State
- );
-
-#endif /* _HT_INTERFACE_COHERENT_H_ */
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htInterfaceGeneral.c b/src/vendorcode/amd/agesa/Proc/HT/htInterfaceGeneral.c
deleted file mode 100644
index 74591f4..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htInterfaceGeneral.c
+++ /dev/null
@@ -1,539 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * External Interface implementation, general purpose features.
- *
- * Contains routines for implementing the interface to the client BIOS. This file
- * includes the interface support which is not removed with various build options.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "OptionMultiSocket.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "htInterface.h"
-#include "htInterfaceGeneral.h"
-#include "htNb.h"
-#include "cpuServices.h"
-#include "cpuFeatures.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_HTINTERFACEGENERAL_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Is PackageLink an Internal Link?
- *
- * This is a test for the logical link match codes in the user interface, not a test for
- * the actual northbridge links.
- *
- * @param[in] PackageLink The link
- *
- * @retval TRUE This is an internal link
- * @retval FALSE This is not an internal link
- */
-BOOLEAN
-IsPackageLinkInternal (
- IN UINT8 PackageLink
- )
-{
- return (BOOLEAN) ((PackageLink <= HT_LIST_MATCH_INTERNAL_LINK_2) && (PackageLink >= HT_LIST_MATCH_INTERNAL_LINK_0));
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Ignore a Link.
- *
- * @HtInterfaceMethod{::F_GET_IGNORE_LINK}
- *
- * This routine is called every time a coherent Link is found and then every time a
- * non-coherent Link from a CPU is found. Any coherent or non-coherent Link from a
- * CPU can be ignored and not used for discovery or initialization. Useful for
- * connection based systems.
- *
- * @note not called for IO device to IO Device Links.
- *
- * @param[in] Node The Node on which this Link is located
- * @param[in] Link The Link about to be initialized
- * @param[in] NbIgnoreLinkList The northbridge default ignore link list
- * @param[in] State the input data
- *
- * @retval MATCHED ignore this Link and skip it
- * @retval POWERED_OFF ignore this link and power it off.
- * @retval UNMATCHED initialize the Link normally
- */
-FINAL_LINK_STATE
-GetIgnoreLink (
- IN UINT8 Node,
- IN UINT8 Link,
- IN IGNORE_LINK *NbIgnoreLinkList,
- IN STATE_DATA *State
- )
-{
- IGNORE_LINK *p;
- FINAL_LINK_STATE Result;
- BOOLEAN IsFound;
- UINT8 Socket;
- UINT8 PackageLink;
-
- ASSERT ((Node < MAX_NODES) && (Link < MAX_NODES));
-
- Result = UNMATCHED;
- IsFound = FALSE;
- Socket = State->HtInterface->GetSocketFromMap (Node, State);
- PackageLink = State->Nb->GetPackageLink (Node, Link, State->Nb);
-
- if (State->HtBlock->IgnoreLinkList != NULL) {
- p = State->HtBlock->IgnoreLinkList;
- while (p->Socket != HT_LIST_TERMINAL) {
- if (((p->Socket == Socket) || (p->Socket == HT_LIST_MATCH_ANY)) &&
- ((p->Link == PackageLink) ||
- ((p->Link == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLink))) ||
- ((p->Link == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLink))))) {
- // Found a match return the desired link state.
- ASSERT (Result < MaxFinalLinkState);
- Result = p->LinkState;
- IsFound = TRUE;
- break;
- } else {
- p++;
- }
- }
- }
- // If there wasn't a match in the user interface, see if the northbridge provides one.
- if (!IsFound && (NbIgnoreLinkList != NULL)) {
- p = NbIgnoreLinkList;
- while (p->Socket != HT_LIST_TERMINAL) {
- if (((p->Socket == Socket) || (p->Socket == HT_LIST_MATCH_ANY)) &&
- ((p->Link == PackageLink) ||
- ((p->Link == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLink))) ||
- ((p->Link == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLink))))) {
- // Found a match return the desired link state.
- ASSERT (Result < MaxFinalLinkState);
- Result = p->LinkState;
- break;
- } else {
- p++;
- }
- }
- }
- return Result;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get the Socket number for a given Node number.
- *
- * @HtInterfaceMethod{::F_GET_SOCKET_FROM_MAP}
- *
- * Return the id.
- *
- * @param[in] Node The Node to translate
- * @param[in] State reference to Node to socket map
- *
- * @return the socket id
- *
- */
-UINT8
-GetSocketFromMap (
- IN UINT8 Node,
- IN STATE_DATA *State
- )
-{
- UINT8 Socket;
-
- ASSERT (State->NodeToSocketDieMap != NULL);
-
- Socket = (*State->NodeToSocketDieMap)[Node].Socket;
- return Socket;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get a new Socket Die to Node Map.
- *
- * @HtInterfaceMethod{::F_NEW_NODE_AND_SOCKET_TABLES}
- *
- * Put the Socket Die Table in heap with a known handle. Content will be generated as
- * each node is discovered.
- *
- * @param[in,out] State global state
- */
-VOID
-NewNodeAndSocketTables (
- IN OUT STATE_DATA *State
- )
-{
- UINT8 i;
- UINT8 j;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
- // Allocate heap for the table
- State->SocketDieToNodeMap = NULL;
- AllocHeapParams.RequestedBufferSize = (((MAX_SOCKETS) * (MAX_DIES)) * sizeof (SOCKET_DIE_TO_NODE_ITEM));
- AllocHeapParams.BufferHandle = SOCKET_DIE_MAP_HANDLE;
- AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
- if (HeapAllocateBuffer (&AllocHeapParams, State->ConfigHandle) == AGESA_SUCCESS) {
- State->SocketDieToNodeMap = (SOCKET_DIE_TO_NODE_MAP)AllocHeapParams.BufferPtr;
- // Initialize shared data structures
- for (i = 0; i < MAX_SOCKETS; i++) {
- for (j = 0; j < MAX_DIES; j++) {
- (*State->SocketDieToNodeMap)[i][j].Node = HT_LIST_TERMINAL;
- (*State->SocketDieToNodeMap)[i][j].LowCore = HT_LIST_TERMINAL;
- (*State->SocketDieToNodeMap)[i][j].HighCore = HT_LIST_TERMINAL;
- }
- }
- }
- // Allocate heap for the table
- State->NodeToSocketDieMap = NULL;
- AllocHeapParams.RequestedBufferSize = (MAX_NODES * sizeof (NODE_TO_SOCKET_DIE_ITEM));
- AllocHeapParams.BufferHandle = NODE_ID_MAP_HANDLE;
- AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
- if (HeapAllocateBuffer (&AllocHeapParams, State->ConfigHandle) == AGESA_SUCCESS) {
- State->NodeToSocketDieMap = (NODE_TO_SOCKET_DIE_MAP)AllocHeapParams.BufferPtr;
- // Initialize shared data structures
- for (i = 0; i < MAX_NODES; i++) {
- (*State->NodeToSocketDieMap)[i].Socket = HT_LIST_TERMINAL;
- (*State->NodeToSocketDieMap)[i].Die = HT_LIST_TERMINAL;
- }
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get the minimum Northbridge frequency for the system.
- *
- * @HtInterfaceMethod{::F_GET_MIN_NB_CORE_FREQ}
- *
- * Invoke the CPU component power mgt interface.
- *
- * @param[in] PlatformConfig Platform profile/build option config structure.
- * @param[in] StdHeader Config for library and services.
- *
- * @return Frequency in MHz.
- *
- */
-UINT32
-GetMinNbCoreFreq (
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- BOOLEAN Temp1;
- BOOLEAN Temp2;
- UINT32 Denominator;
- UINT32 Result;
-
- OptionMultiSocketConfiguration.GetSystemNbPstateSettings ((UINT32) 0, PlatformConfig, &Result, &Denominator, &Temp1, &Temp2, StdHeader);
- ASSERT (Denominator != 0);
- return (Result / Denominator);
-}
-
-/**
- * @page physicalsockethowto Physical Socket Map, How To Create
- *
- * To create a physical system socket map for a platform:
- *
- * - Start at the Node which will be the BSP.
- *
- * - Begin a breadth first enumeration of all the coherent Links between sockets
- * by creating a socket structure for each socket connection from the BSP.
- * For example, if the BSP is in socket zero and Link one connects to socket two,
- * create socket {0, 1, 2}.
- *
- * - When all Links from the BSP are described, go to the first socket connected
- * to the BSP and continue the breadth first enumeration.
- *
- * - It should not be necessary to describe the back Links; in the example above, there
- * should be no need to create {2, 1, 0} (assuming socket two connects back to
- * socket zero on its Link one).
- *
- * - When completed:
- *
- * - Every socket except the BSP's (usually zero) must be listed as a targetSocket,
- * at least once. Some sockets may be listed more than once.
- *
- * - There usually should be at least as many entries as Links. An exception is a
- * fully connected system, only the Links from the BSP are needed.
- *
- * - Every socket but the last one in the breadth first order should usually have one
- * or more entries listing it as a currentSocket. (The last one has only back Links.)
- *
- * There are no strict assumptions about the ordering of the socket structures.
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Update maps between Sockets and Nodes for a specific newly discovered node.
- *
- * @HtInterfaceMethod{::F_SET_NODE_TO_SOCKET_MAP}
- *
- * There are two methods for providing socket naming of nodes.
- *
- * Hardware Method (preferred): A value strapped in hardware by the board is read and
- * passed to this routine.
- *
- * Software Method: The current node's socket is looked up, since it was
- * previously a new node and went through this process. The link is converted to
- * a package level link. A user data structure describing the package level
- * layout of the system is searched for the current node's socket and package link,
- * and now we know the new node's socket.
- *
- * In either case, the Socket, Module to Node map and the Node to Socket, Module
- * map are updated with the new node, socket, and module.
- *
- * Data needed to do this is passed in to the routine as arguments rather than read by this routine,
- * so that it is not necessary to know a valid temporary route to either node at the time this code runs.
- *
- * @param[in] Node Node from which a new node was discovered
- * @param[in] CurrentNodeModule The current node's module id in it's processor.
- * @param[in] PackageLink The package link for the current node's link.
- * @param[in] NewNode The new node's id
- * @param[in] HardwareSocket If we use the hardware method (preferred), this is the socket of new node.
- * @param[in] Module The new node's module id in it's processor.
- * @param[in] State our State
- */
-VOID
-SetNodeToSocketMap (
- IN UINT8 Node,
- IN UINT8 CurrentNodeModule,
- IN UINT8 PackageLink,
- IN UINT8 NewNode,
- IN UINT8 HardwareSocket,
- IN UINT8 Module,
- IN STATE_DATA *State
- )
-{
- UINT8 SourceSocket;
- UINT8 TargetSocket;
- SYSTEM_PHYSICAL_SOCKET_MAP *Map;
-
- // While this code could be written to recover from a NULL socket map, AGESA cannot function without one.
- ASSERT (State->SocketDieToNodeMap != NULL);
-
- if (State->HtBlock->SystemPhysicalSocketMap != NULL) {
- if (NewNode != 0) {
- // Find the logical Node from which a new Node was discovered in the Node field of
- // some socket. It must already be there, Nodes are assigned ascending.
- //
- for (SourceSocket = 0; SourceSocket < MAX_SOCKETS; SourceSocket++) {
- if ((*State->SocketDieToNodeMap)[SourceSocket][CurrentNodeModule].Node == Node) {
- break;
- }
- }
- // This ASSERT should be understood as "the Node did not have a match", not as a limit check on SourceSocket.
- ASSERT (SourceSocket != MAX_SOCKETS);
-
- // Find the sourceSocket in the CurrentSocket field, for the Link on which a new Node
- // was discovered. When we find an entry with that socket and Link number, update the
- // Node for that socket.
- //
- if (IsPackageLinkInternal (PackageLink)) {
- // Internal Nodes are in the same socket, don't search the physical system map.
- TargetSocket = SourceSocket;
- } else {
- // Find the target socket in the physical system map.
- Map = State->HtBlock->SystemPhysicalSocketMap;
- while ((Map->CurrentSocket != 0xFF) &&
- ((Map->CurrentSocket != SourceSocket) || (Map->CurrentLink != PackageLink))) {
- Map++;
- }
- ASSERT (Map->CurrentSocket != 0xFF);
- TargetSocket = Map->TargetSocket;
- }
- } else {
- // The BSP (BSN, if you will) has no predecessor node from which it is discovered.
- TargetSocket = 0;
- }
- } else {
- // Use the hardware method
- // The hardware strapped socket id is passed to us in this case.
- TargetSocket = HardwareSocket;
- }
- // If the target socket, module is already mapped to something, that's not good. Socket labeling conflict.
- // Check that the board is strapped correctly. If not you need a SystemPhysicalSocketMap. If you have one,
- // check it for correctness.
- ASSERT ((*State->SocketDieToNodeMap)[TargetSocket][Module].Node == 0xFF);
- // Update the map for the rest of agesa
- (*State->SocketDieToNodeMap)[TargetSocket][Module].Node = NewNode;
- // and the node to socket map
- ASSERT (State->NodeToSocketDieMap != NULL);
- (*State->NodeToSocketDieMap)[NewNode].Socket = TargetSocket;
- (*State->NodeToSocketDieMap)[NewNode].Die = Module;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Clean up the map structures after severe event has caused a fall back to 1 node.
- *
- * @HtInterfaceMethod{::F_CLEAN_MAPS_AFTER_ERROR}
- *
- * @param[in] State Our state, access to socket, node maps
- *
- */
-VOID
-CleanMapsAfterError (
- IN STATE_DATA *State
- )
-{
- UINTN Socket;
- UINTN Module;
- UINTN Node;
-
- ASSERT (State->NodeToSocketDieMap != NULL);
- ASSERT (State->SocketDieToNodeMap != NULL);
-
- // Clear all the socket, module items except for the socket and module containing node zero.
- for (Socket = 0; Socket < MAX_SOCKETS; Socket++) {
- for (Module = 0; Module < MAX_DIES; Module++) {
- if (((*State->NodeToSocketDieMap)[0].Socket != Socket) || ((*State->NodeToSocketDieMap)[0].Die != Module)) {
- (*State->SocketDieToNodeMap)[Socket][Module].Node = HT_LIST_TERMINAL;
- (*State->SocketDieToNodeMap)[Socket][Module].LowCore = HT_LIST_TERMINAL;
- (*State->SocketDieToNodeMap)[Socket][Module].HighCore = HT_LIST_TERMINAL;
- }
- }
- }
- // Clear all the node items except for node zero.
- for (Node = 1; Node < MAX_NODES; Node++) {
- (*State->NodeToSocketDieMap)[Node].Socket = HT_LIST_TERMINAL;
- (*State->NodeToSocketDieMap)[Node].Die = HT_LIST_TERMINAL;
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Post Node id and other context info to AP cores via mailbox.
- *
- * @HtInterfaceMethod{::F_POST_MAP_TO_AP}
- *
- * Since Ap's can not view map until after mp communication is established,
- * provide them with initial context info via a mailbox register. A mailbox
- * register is one that can be written in PCI space and read in MSR space.
- *
- * @param[in] State Our state, access to socket, node maps
- */
-VOID
-PostMapToAp (
- IN STATE_DATA *State
- )
-{
- UINT8 ModuleType;
- UINT8 Module;
- AP_MAILBOXES ApMailboxes;
- UINT8 Node;
- UINT32 Degree;
- AGESA_STATUS CalledStatus;
-
- // Dispatch any features (such as Preserve Mailbox) that need to run as soon as discovery is completed.
- IDS_HDT_CONSOLE (CPU_TRACE, " Dispatch CPU features after HT discovery\n");
- CalledStatus = DispatchCpuFeatures (CPU_FEAT_AFTER_COHERENT_DISCOVERY, State->PlatformConfiguration, State->ConfigHandle);
-
- ASSERT (State->Fabric != NULL);
- Degree = 0;
- // Compute the degree of the system by finding the maximum degree of any node.
- for (Node = 0; Node < (State->NodesDiscovered + 1); Node++) {
- if (State->Fabric->SysDegree[Node] > Degree) {
- Degree = State->Fabric->SysDegree[Node];
- }
- }
- // Post the information on all nodes.
- for (Node = 0; Node < (State->NodesDiscovered + 1); Node++) {
- ModuleType = 0;
- Module = 0;
- State->Nb->GetModuleInfo (Node, &ModuleType, &Module, State->Nb);
- ApMailboxes.ApMailInfo.Info = 0;
- ApMailboxes.ApMailInfo.Fields.Node = Node;
- ApMailboxes.ApMailInfo.Fields.Socket = State->HtInterface->GetSocketFromMap (Node, State);
- ApMailboxes.ApMailInfo.Fields.ModuleType = ModuleType;
- ApMailboxes.ApMailInfo.Fields.Module = Module;
- ApMailboxes.ApMailExtInfo.Info = 0;
- ApMailboxes.ApMailExtInfo.Fields.SystemDegree = Degree;
- // other fields of the extended info are used during ap init, and will be initialized at that time.
- State->Nb->PostMailbox (Node, ApMailboxes, State->Nb);
- }
- // Now that the mailboxes have been initialized, cache the info on the BSC. The APs
- // will cache during heap initialization.
- CacheApMailbox (State->ConfigHandle);
-}
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htInterfaceGeneral.h b/src/vendorcode/amd/agesa/Proc/HT/htInterfaceGeneral.h
deleted file mode 100644
index 1c20b17..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htInterfaceGeneral.h
+++ /dev/null
@@ -1,162 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Internal access to HT Interface, general purpose features.
- *
- * This file provides definitions used by HT internal modules. The
- * external HT interface (in agesa.h) is accessed using these methods.
- * This keeps the HT Feature implementations abstracted from the HT
- * external interface.
- *
- * This file includes the interface support which is not removed with
- * various build options.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _HT_INTERFACE_GENERAL_H_
-#define _HT_INTERFACE_GENERAL_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * Prototypes to Interface from Feature Code
- *
- *----------------------------------------------------------------------------
- */
-
-/**
- * Is PackageLink an Internal Link?
- */
-BOOLEAN
-IsPackageLinkInternal (
- IN UINT8 PackageLink
- );
-
-/**
- * Get the Socket number for a given Node number.
- *
- */
-UINT8
-GetSocketFromMap (
- IN UINT8 Node,
- IN STATE_DATA *State
- );
-
-/**
- * Ignore a Link.
- *
- */
-FINAL_LINK_STATE
-GetIgnoreLink (
- IN UINT8 Node,
- IN UINT8 Link,
- IN IGNORE_LINK *NbIgnoreLinkList,
- IN STATE_DATA *State
- );
-
-/**
- * Get a new Socket Die to Node Map.
- *
- */
-VOID
-NewNodeAndSocketTables (
- IN OUT STATE_DATA *State
- );
-
-/**
- * Get the minimum Northbridge frequency for the system.
- *
- */
-UINT32
-GetMinNbCoreFreq (
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * Fill in the socket's Node id when a processor is discovered in that socket.
- *
- */
-VOID
-SetNodeToSocketMap (
- IN UINT8 Node,
- IN UINT8 CurrentNodeModule,
- IN UINT8 PackageLink,
- IN UINT8 NewNode,
- IN UINT8 HardwareSocket,
- IN UINT8 Module,
- IN STATE_DATA *State
- );
-
-/**
- * Clean up the map structures after severe event has caused a fall back to 1 node.
- *
- */
-VOID
-CleanMapsAfterError (
- IN STATE_DATA *State
- );
-
-/**
- * Post Node id and other context info to AP cores via mailbox.
- *
- */
-VOID
-PostMapToAp (
- IN STATE_DATA *State
- );
-
-#endif /* _HT_INTERFACE_GENERAL_H_ */
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htInterfaceNonCoherent.c b/src/vendorcode/amd/agesa/Proc/HT/htInterfaceNonCoherent.c
deleted file mode 100644
index 20b1e1b..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htInterfaceNonCoherent.c
+++ /dev/null
@@ -1,394 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * External Interface implementation for non-coherent features.
- *
- * Contains routines for accessing the interface to the client BIOS,
- * for non-coherent features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "htInterface.h"
-#include "htInterfaceNonCoherent.h"
-#include "htNb.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_HTINTERFACENONCOHERENT_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define UNUSED_ZERO_32 ((UINT32)0)
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get Manual BUID assignment list.
- *
- * @HtInterfaceMethod{::F_GET_MANUAL_BUID_SWAP_LIST}
- *
- * This routine is called every time a non-coherent chain is processed. BUID
- * assignment may be controlled explicitly on a non-coherent chain. Swaps controls
- * the BUID assignment and FinalIds provides the device to device Linking. Device
- * orientation can be detected automatically, or explicitly. See documentation for
- * more details.
- *
- * If a manual swap list is not supplied, automatic non-coherent init assigns BUIDs
- * starting at 1 and incrementing sequentially based on each device's unit count.
- *
- * @param[in] Node The Node on which this chain is located
- * @param[in] Link The Link on the host for this chain
- * @param[out] List supply a pointer to a list.
- * List is NOT valid unless routine returns TRUE.
- * @param[in] State the input data
- *
- * @retval TRUE use a manual list
- * @retval FALSE initialize the Link automatically
- */
-BOOLEAN
-GetManualBuidSwapList (
- IN UINT8 Node,
- IN UINT8 Link,
- OUT BUID_SWAP_LIST **List,
- IN STATE_DATA *State
- )
-{
- MANUAL_BUID_SWAP_LIST *p;
- BOOLEAN result;
- UINT8 Socket;
- UINT8 PackageLink;
-
- ASSERT ((Node < MAX_NODES) && (List != NULL));
-
- result = FALSE;
- Socket = State->HtInterface->GetSocketFromMap (Node, State);
- PackageLink = State->Nb->GetPackageLink (Node, Link, State->Nb);
-
- if (State->HtBlock->ManualBuidSwapList != NULL) {
- p = State->HtBlock->ManualBuidSwapList;
-
- while (p->Socket != HT_LIST_TERMINAL) {
- if (((p->Socket == Socket) || (p->Socket == HT_LIST_MATCH_ANY)) &&
- ((p->Link == PackageLink) || (p->Link == HT_LIST_MATCH_ANY))) {
- // Found a match implies TRUE, ignore the Link
- result = TRUE;
- *List = &(p->SwapList);
- break;
- } else {
- p++;
- }
- }
- }
- // List is not valid if Result is FALSE.
- return result;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Override capabilities of a device.
- *
- * @HtInterfaceMethod{::F_GET_DEVICE_CAP_OVERRIDE}
- *
- * This routine is called once for every Link on every IO device. Update the width
- * and frequency capability if needed for this device. This is used along with
- * device capabilities, the limit call backs, and northbridge limits to compute the
- * default settings. The components of the device's PCI config address are provided,
- * so its settings can be consulted if need be. The input width and frequency are the
- * reported device capabilities.
- *
- * @param[in] HostNode The Node on which this chain is located
- * @param[in] HostLink The Link on the host for this chain
- * @param[in] Depth The Depth in the I/O chain from the Host
- * @param[in] PciAddress The Device's PCI config address (for callout)
- * @param[in] DevVenId The Device's PCI Vendor + Device ID (offset 0x00)
- * @param[in] Revision The Device's PCI Revision
- * @param[in] Link The Device's Link number (0 or 1)
- * @param[in,out] LinkWidthIn modify to change the Link Width In
- * @param[in,out] LinkWidthOut modify to change the Link Width Out
- * @param[in,out] FreqCap modify to change the Link's frequency capability
- * @param[in,out] Clumping modify to change unit id clumping capability
- * @param[in] State the input data and config header
- *
- */
-VOID
-GetDeviceCapOverride (
- IN UINT8 HostNode,
- IN UINT8 HostLink,
- IN UINT8 Depth,
- IN PCI_ADDR PciAddress,
- IN UINT32 DevVenId,
- IN UINT8 Revision,
- IN UINT8 Link,
- IN OUT UINT8 *LinkWidthIn,
- IN OUT UINT8 *LinkWidthOut,
- IN OUT UINT32 *FreqCap,
- IN OUT UINT32 *Clumping,
- IN STATE_DATA *State
- )
-{
- DEVICE_CAP_OVERRIDE *p;
- UINT8 HostSocket;
- UINT8 PackageLink;
- DEVICE_CAP_CALLOUT_PARAMS CalloutParams;
- AGESA_STATUS CalloutStatus;
-
- ASSERT ((HostNode < MAX_NODES) && (Depth < 32) && ((Link == 0) || (Link == 1)));
-
- HostSocket = State->HtInterface->GetSocketFromMap (HostNode, State);
- PackageLink = State->Nb->GetPackageLink (HostNode, HostLink, State->Nb);
-
- if (State->HtBlock->DeviceCapOverrideList != NULL) {
- p = State->HtBlock->DeviceCapOverrideList;
-
- while (p->HostSocket != HT_LIST_TERMINAL) {
- if (((p->HostSocket == HostSocket) || (p->HostSocket == HT_LIST_MATCH_ANY)) &&
- ((p->HostLink == PackageLink) || (p->HostLink == HT_LIST_MATCH_ANY)) &&
- ((p->Depth == Depth) || (p->Depth == HT_LIST_MATCH_ANY)) &&
- ((p->Link == Link) || (p->Link == HT_LIST_MATCH_ANY)) &&
- // Found a potential match. Check the additional optional matches.
- ((p->Options.IsCheckDevVenId == 0) || (p->DevVenId == DevVenId)) &&
- ((p->Options.IsCheckRevision == 0) || (p->Revision == Revision))) {
- //
- // Found a match. Check what override actions are desired.
- // Unlike the PCB limit routines, which handle the info returned,
- // deviceCapOverride is actually overriding the settings, so we need
- // to check that the field actually has an update.
- // The Callout is a catch all for situations the data is not up to handling.
- // It is expected, but not enforced, that either the data overrides are used,
- // or the callout is used, rather than both.
- //
- if (p->Options.IsOverrideWidthIn != 0) {
- *LinkWidthIn = p->LinkWidthIn;
- }
- if (p->Options.IsOverrideWidthOut != 0) {
- *LinkWidthOut = p->LinkWidthOut;
- }
- if (p->Options.IsOverrideFreq != 0) {
- *FreqCap = p->FreqCap;
- }
- if (p->Options.IsOverrideClumping != 0) {
- *Clumping = p->Clumping;
- }
- if (p->Options.IsDoCallout != 0) {
- //
- // Pass the actual info being matched, not the matched struct data.
- // This callout is expected to be built in as part of the options file, and does not use the
- // callout interface, even though we use the consistent interface declaration for the routine.
- // So, the first two int parameters have no meaning in this case.
- // It is not meaningful for the callout to have any status but Success.
- //
- CalloutParams.HostSocket = HostSocket;
- CalloutParams.HostLink = PackageLink;
- CalloutParams.Depth = Depth;
- CalloutParams.DevVenId = DevVenId;
- CalloutParams.Revision = Revision;
- CalloutParams.Link = Link;
- CalloutParams.PciAddress = PciAddress;
- CalloutParams.LinkWidthIn = LinkWidthIn;
- CalloutParams.LinkWidthOut = LinkWidthOut;
- CalloutParams.FreqCap = FreqCap;
- CalloutParams.Clumping = Clumping;
- CalloutParams.StdHeader = *((AMD_CONFIG_PARAMS *) (State->ConfigHandle));
- CalloutStatus = p->Callout (UNUSED_ZERO_32, UNUSED_ZERO_32, (VOID *) &CalloutParams);
- ASSERT (CalloutStatus == AGESA_SUCCESS);
- }
- break;
- } else {
- p++;
- }
- }
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get limits for non-coherent Links.
- *
- * @HtInterfaceMethod{::F_GET_IO_PCB_LIMITS}
- *
- * For each non-coherent connection this routine is called once. Update the
- * frequency and width if needed for this Link (usually based on board restriction).
- * This is used with device capabilities, device overrides, and northbridge limits to
- * compute the default settings. The input width and frequency are valid, but do not
- * necessarily reflect the minimum setting that will be chosen.
- *
- * @param[in] HostNode The Node on which this Link is located
- * @param[in] HostLink The Link about to be initialized
- * @param[in] Depth The Depth in the I/O chain from the Host
- * @param[in,out] DownstreamLinkWidthLimit modify to change the Link Width In
- * @param[in,out] UpstreamLinkWidthLimit modify to change the Link Width Out
- * @param[in,out] PcbFreqCap modify to change the Link's frequency capability
- * @param[in] State the input data
- */
-VOID
-GetIoPcbLimits (
- IN UINT8 HostNode,
- IN UINT8 HostLink,
- IN UINT8 Depth,
- IN OUT UINT8 *DownstreamLinkWidthLimit,
- IN OUT UINT8 *UpstreamLinkWidthLimit,
- IN OUT UINT32 *PcbFreqCap,
- IN STATE_DATA *State
- )
-{
- IO_PCB_LIMITS *p;
- UINT8 Socket;
- UINT8 PackageLink;
-
- ASSERT ((HostNode < MAX_NODES) && (HostLink < MAX_NODES));
-
- Socket = State->HtInterface->GetSocketFromMap (HostNode, State);
- PackageLink = State->Nb->GetPackageLink (HostNode, HostLink, State->Nb);
-
- if (State->HtBlock->IoPcbLimitsList != NULL) {
- p = State->HtBlock->IoPcbLimitsList;
-
- while (p->HostSocket != HT_LIST_TERMINAL) {
- if (((p->HostSocket == Socket) || (p->HostSocket == HT_LIST_MATCH_ANY)) &&
- ((p->HostLink == PackageLink) || (p->HostLink == HT_LIST_MATCH_ANY)) &&
- ((p->Depth == Depth) || (p->Depth == HT_LIST_MATCH_ANY))) {
- // Found a match, return the override info
- *DownstreamLinkWidthLimit = p->DownstreamLinkWidthLimit;
- *UpstreamLinkWidthLimit = p->UpstreamLinkWidthLimit;
- *PcbFreqCap = p->PcbFreqCap;
- break;
- } else {
- p++;
- }
- }
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Manually control bus number assignment.
- *
- * @HtInterfaceMethod{::F_GET_OVERRIDE_BUS_NUMBERS}
- *
- * This routine is called every time a non-coherent chain is processed. If a system
- * can not use the auto Bus numbering feature for non-coherent chain bus assignments,
- * this routine can provide explicit control. For each chain, provide the bus number
- * range to use.
- *
- * The outputs SecBus and SubBus are not valid unless this routine returns TRUE
- *
- * @param[in] Node The Node on which this chain is located
- * @param[in] Link The Link on the host for this chain
- * @param[out] SecBus Secondary Bus number for this non-coherent chain
- * @param[out] SubBus Subordinate Bus number
- * @param[in] State the input data
- *
- * @retval TRUE this routine is supplying the bus numbers.
- * @retval FALSE use auto Bus numbering, bus outputs not valid.
- */
-BOOLEAN
-GetOverrideBusNumbers (
- IN UINT8 Node,
- IN UINT8 Link,
- OUT UINT8 *SecBus,
- OUT UINT8 *SubBus,
- IN STATE_DATA *State
- )
-{
- OVERRIDE_BUS_NUMBERS *p;
- BOOLEAN result;
- UINT8 Socket;
- UINT8 PackageLink;
-
- ASSERT ((Node < MAX_NODES) && (Link < MAX_NODES));
-
- result = FALSE;
- Socket = State->HtInterface->GetSocketFromMap (Node, State);
- PackageLink = State->Nb->GetPackageLink (Node, Link, State->Nb);
-
- if (State->HtBlock->OverrideBusNumbersList != NULL) {
- p = State->HtBlock->OverrideBusNumbersList;
-
- while (p->Socket != HT_LIST_TERMINAL) {
- if (((p->Socket == Socket) || (p->Socket == HT_LIST_MATCH_ANY)) &&
- ((p->Link == PackageLink) || (p->Link == HT_LIST_MATCH_ANY))) {
- // Found a match, return the bus overrides
- *SecBus = p->SecBus;
- *SubBus = p->SubBus;
- ASSERT (*SubBus > *SecBus);
- result = TRUE;
- break;
- } else {
- p++;
- }
- }
- }
- // SecBus, SubBus are not valid if Result is FALSE.
- return result;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htInterfaceNonCoherent.h b/src/vendorcode/amd/agesa/Proc/HT/htInterfaceNonCoherent.h
deleted file mode 100644
index 154ec68..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htInterfaceNonCoherent.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Internal access to HT Interface, for non-coherent features.
- *
- * This file provides definitions used by HT internal modules. The
- * external HT interface (in agesa.h) is accessed using these methods.
- * This keeps the HT Feature implementations abstracted from the HT
- * interface.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _HT_INTERFACE_NONCOHERENT_H_
-#define _HT_INTERFACE_NONCOHERENT_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * Prototypes to Interface from Feature Code
- *
- *----------------------------------------------------------------------------
- */
-
-/**
- * Manually control bus number assignment.
- *
- */
-BOOLEAN
-GetOverrideBusNumbers (
- IN UINT8 Node,
- IN UINT8 Link,
- OUT UINT8 *SecBus,
- OUT UINT8 *SubBus,
- IN STATE_DATA *State
- );
-
-/**
- * Get Manual BUID assignment list.
- *
- */
-BOOLEAN
-GetManualBuidSwapList (
- IN UINT8 Node,
- IN UINT8 Link,
- OUT BUID_SWAP_LIST **List,
- IN STATE_DATA *State
- );
-
-/**
- * Override capabilities of a device.
- *
- */
-
-VOID
-GetDeviceCapOverride (
- IN UINT8 HostNode,
- IN UINT8 HostLink,
- IN UINT8 Depth,
- IN PCI_ADDR PciAddress,
- IN UINT32 DevVenId,
- IN UINT8 Revision,
- IN UINT8 Link,
- IN OUT UINT8 *LinkWidthIn,
- IN OUT UINT8 *LinkWidthOut,
- IN OUT UINT32 *FreqCap,
- IN OUT UINT32 *Clumping,
- IN STATE_DATA *State
- );
-
-/**
- * Get limits for non-coherent Links.
- *
- */
-VOID
-GetIoPcbLimits (
- IN UINT8 HostNode,
- IN UINT8 HostLink,
- IN UINT8 Depth,
- IN OUT UINT8 *DownstreamLinkWidthLimit,
- IN OUT UINT8 *UpstreamLinkWidthLimit,
- IN OUT UINT32 *PcbFreqCap,
- IN STATE_DATA *State
- );
-
-#endif /* _HT_INTERFACE_NONCOHERENT_H_ */
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htMain.c b/src/vendorcode/amd/agesa/Proc/HT/htMain.c
deleted file mode 100644
index 99de5c5..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htMain.c
+++ /dev/null
@@ -1,579 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * HyperTransport features and sequence implementation.
- *
- * Implements the external AmdHtInitialize entry point.
- * Contains routines for directing the sequence of available features.
- * Mostly, but not exclusively, AGESA_TESTPOINT invocations should be
- * contained in this file, and not in the feature code.
- *
- * From a build option perspective, it may be that a few lines could be removed
- * from compilation in this file for certain options. It is considered that
- * the code savings from this are too small to be of concern and this file
- * should not have any explicit build option implementation.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35978 $ @e \$Date: 2010-08-07 02:18:50 +0800 (Sat, 07 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "htInterface.h"
-#include "htNb.h"
-#include "heapManager.h"
-#include "cpuServices.h"
-#include "OptionsHt.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_HTMAIN_FILECODE
-#define APIC_Base_BSP 8
-#define APIC_Base 0x1b
-
-extern OPTION_HT_CONFIGURATION OptionHtConfiguration;
-
-BOOLEAN
-STATIC
-IsBootCore (
- IN STATE_DATA *State
- );
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Update maps with the core range for each module.
- *
- * Cores are numbered relative to a Processor, but sometimes there is a need to know the
- * starting and ending core ids on a particular node. This same info is also useful for
- * supporting the Core count on a node other than the one currently executing.
- *
- * For each Processor, get the core count of each node using the family specific PCI core count
- * interface. The order of cores in a processor, and whether it is special for the BSP is family
- * specific. But whether the processor orders core ids by module or node, iterate in the right
- * order and use the counts to determine each start and end range.
- *
- * Update compute unit status for each node.
- *
- * @param[in] State number of Nodes discovered.
-*/
-VOID
-STATIC
-UpdateCoreRanges (
- IN STATE_DATA *State
- )
-{
- UINT8 Node;
- UINT8 ProcessorCores;
- UINT8 ModuleCoreCount[MAX_DIES];
- UINT8 Socket;
- UINT8 Module;
-
- ASSERT (State->SocketDieToNodeMap != NULL);
- ASSERT (State->NodeToSocketDieMap != NULL);
-
- for (Socket = 0; Socket < MAX_SOCKETS; Socket++) {
- // Is a Processor present in Socket?
- if ((*State->SocketDieToNodeMap)[Socket][0].Node != HT_LIST_TERMINAL) {
- // Get all the Module core counts for this processor
- // Note that the core counts are 1 based counts.
- // Since Compute Unit info is not module ordering dependent, write it now.
- for (Module = 0; Module < MAX_DIES; Module++) {
- if ((*State->SocketDieToNodeMap)[Socket][Module].Node != HT_LIST_TERMINAL) {
- ModuleCoreCount[Module] = State->Nb->GetNumCoresOnNode ((*State->SocketDieToNodeMap)[Socket][Module].Node, State->Nb);
- (*State->SocketDieToNodeMap)[Socket][Module].EnabledComputeUnits =
- State->Nb->GetEnabledComputeUnits ((*State->SocketDieToNodeMap)[Socket][Module].Node, State->Nb);
- (*State->SocketDieToNodeMap)[Socket][Module].DualCoreComputeUnits =
- State->Nb->GetDualCoreComputeUnits ((*State->SocketDieToNodeMap)[Socket][Module].Node, State->Nb);
- } else {
- ModuleCoreCount[Module] = 0;
- }
- }
- // Determine the core ordering rule for this processor.
- if ((((*State->NodeToSocketDieMap)[0].Socket == Socket) && State->Nb->IsOrderBSPCoresByNode) ||
- (!State->Nb->IsOrderCoresByModule)) {
- // Order core ranges on this processor by Node Id.
- ProcessorCores = 0;
- for (Node = 0; Node < State->Nb->GetNodeCount (State->Nb); Node++) {
- // Is this node a module in this processor?
- if ((*State->NodeToSocketDieMap)[Node].Socket == Socket) {
- Module = (*State->NodeToSocketDieMap)[Node].Die;
- if (ModuleCoreCount[Module] != 0) {
- (*State->SocketDieToNodeMap)[Socket][Module].LowCore = ProcessorCores;
- (*State->SocketDieToNodeMap)[Socket][Module].HighCore = ProcessorCores + (ModuleCoreCount[Module] - 1);
- IDS_HDT_CONSOLE (
- HT_TRACE,
- (IsBootCore (State) ?
- "Topology: Socket %d, Die %d, is Node %d, with Cores %d thru %d. Compute Unit status (0x%x,0x%x).\n" :
- ""),
- Socket,
- Module,
- Node,
- (*State->SocketDieToNodeMap)[Socket][Module].LowCore,
- (*State->SocketDieToNodeMap)[Socket][Module].HighCore,
- (*State->SocketDieToNodeMap)[Socket][Module].EnabledComputeUnits,
- (*State->SocketDieToNodeMap)[Socket][Module].DualCoreComputeUnits
- );
- ProcessorCores = ProcessorCores + ModuleCoreCount[Module];
- }
- }
- }
- } else {
- // Order core ranges in this processor by Module Id.
- ProcessorCores = 0;
- for (Module = 0; Module < MAX_DIES; Module++) {
- if (ModuleCoreCount[Module] != 0) {
- (*State->SocketDieToNodeMap)[Socket][Module].LowCore = ProcessorCores;
- (*State->SocketDieToNodeMap)[Socket][Module].HighCore = ProcessorCores + (ModuleCoreCount[Module] - 1);
- IDS_HDT_CONSOLE (
- HT_TRACE,
- (IsBootCore (State) ?
- "Topology: Socket %d, Die %d, is Node %d, with Cores %d thru %d. Compute Unit status (0x%x,0x%x).\n" :
- ""),
- Socket,
- Module,
- (*State->SocketDieToNodeMap)[Socket][Module].Node,
- (*State->SocketDieToNodeMap)[Socket][Module].LowCore,
- (*State->SocketDieToNodeMap)[Socket][Module].HighCore,
- (*State->SocketDieToNodeMap)[Socket][Module].EnabledComputeUnits,
- (*State->SocketDieToNodeMap)[Socket][Module].DualCoreComputeUnits
- );
- ProcessorCores = ProcessorCores + ModuleCoreCount[Module];
- }
- }
- }
- }
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Complete the coherent init with any system level initialization.
- *
- * Find the total number of cores and update the number of Nodes and cores in all cpus.
- * Limit cpu config access to installed cpus.
- *
- * @param[in] State number of Nodes discovered.
-*/
-VOID
-STATIC
-FinalizeCoherentInit (
- IN STATE_DATA *State
- )
-{
- UINT8 Node;
- UINT8 TotalCores;
-
- TotalCores = 0;
-
- for (Node = 0; Node < (State->NodesDiscovered + 1); Node++) {
- TotalCores = TotalCores + State->Nb->GetNumCoresOnNode (Node, State->Nb);
- }
-
- for (Node = 0; Node < (State->NodesDiscovered + 1); Node++) {
- State->Nb->SetTotalNodesAndCores (Node, State->NodesDiscovered + 1, TotalCores, State->Nb);
- }
-
- // Set all nodes to limit config space based on node count, after all nodes have a valid count.
- // (just being cautious, probably we could combine the loops.)
- for (Node = 0; Node < (State->NodesDiscovered + 1); Node++) {
- State->Nb->LimitNodes (Node, State->Nb);
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Initialize the coherent fabric.
- *
- * Perform discovery and initialization of the coherent fabric, for builds including
- * support for multiple coherent nodes.
- *
- * @param[in] State global state
- */
-VOID
-STATIC
-CoherentInit (
- IN OUT STATE_DATA *State
- )
-{
- UINT8 i;
- UINT8 j;
- UINT8 ModuleType;
- UINT8 Module;
- UINT8 HardwareSocket;
- COHERENT_FABRIC Fabric;
-
- // Because Node 0, the BSP, is not discovered, initialize info about it specially here.
- // Allocate Socket Die Map.
- // While the BSP is always capable of being the only processor in the system, call the
- // IsExceededCapable method to make sure the BSP's capability is included in the aggregate system
- // capability. We don't care to check the return value.
- //
- State->Fabric = &Fabric;
- State->NodesDiscovered = 0;
- State->TotalLinks = 0;
- State->SysMpCap = MAX_NODES;
- State->Nb->IsExceededCapable (0, State, State->Nb);
- HardwareSocket = State->Nb->GetSocket (0, 0, State->Nb);
- ModuleType = 0;
- Module = 0;
- State->Nb->GetModuleInfo (0, &ModuleType, &Module, State->Nb);
- // No predecessor info for BSP, so pass 0xFF for those parameters.
- State->HtInterface->SetNodeToSocketMap (0xFF, 0xFF, 0xFF, 0, HardwareSocket, Module, State);
-
- // Initialize system state data structures
- for (i = 0; i < MAX_NODES; i++) {
- State->Fabric->SysDegree[i] = 0;
- for (j = 0; j < MAX_NODES; j++) {
- State->Fabric->SysMatrix[i][j] = 0;
- }
- }
-
- //
- // Call the coherent init features
- //
-
- // Discovery
- State->HtFeatures->CoherentDiscovery (State);
- State->HtInterface->PostMapToAp (State);
- // Topology matching and Routing
- AGESA_TESTPOINT (TpProcHtTopology, State->ConfigHandle);
- State->HtFeatures->LookupComputeAndLoadRoutingTables (State);
- State->HtFeatures->MakeHopCountTable (State);
-
- // UpdateCoreRanges requires the other maps to be initialized, and the node count set.
- FinalizeCoherentInit (State);
- UpdateCoreRanges (State);
- State->Fabric = NULL;
-}
-
-/***************************************************************************
- *** Non-coherent init code ***
- *** Algorithms ***
- ***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
-/**
- * Initialize the non-coherent fabric.
- *
- * Begin with the Compat Link on the BSP, then find and initialize all other
- * non-coherent chains.
- *
- * @param[in] State our global state
- */
-VOID
-STATIC
-NcInit (
- IN STATE_DATA *State
- )
-{
- UINT8 Node;
- UINT8 Link;
- UINT8 CompatLink;
- FINAL_LINK_STATE FinalLinkState;
-
- // Initialize the southbridge chain.
- State->AutoBusCurrent = State->HtBlock->AutoBusStart;
- State->UsedCfgMapEntries = 0;
- CompatLink = State->Nb->ReadSouthbridgeLink (State->Nb);
- State->HtFeatures->ProcessLink (0, CompatLink, TRUE, State);
-
- // Find and initialize all other non-coherent chains.
- for (Node = 0; Node <= State->NodesDiscovered; Node++) {
- for (Link = 0; Link < State->Nb->MaxLinks; Link++) {
- // Skip the Link, if any of these tests indicate
- FinalLinkState = State->HtInterface->GetIgnoreLink (Node, Link, State->Nb->DefaultIgnoreLinkList, State);
- if (FinalLinkState == UNMATCHED) {
- if ( !((Node == 0) && (Link == CompatLink))) {
- if ( !(State->Nb->ReadTrueLinkFailStatus (Node, Link, State, State->Nb))) {
- if (State->Nb->VerifyLinkIsNonCoherent (Node, Link, State->Nb)) {
- State->HtFeatures->ProcessLink (Node, Link, FALSE, State);
- }
- }
- }
- }
- }
- }
-}
-
-/***************************************************************************
- *** Link Optimization ***
- ***************************************************************************/
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Optimize Link Features.
- *
- * Based on Link capabilities, apply optimization rules to come up with the best
- * settings, including several external limit decision from the interface. This includes
- * handling of subLinks. Finally, after the port list data is updated, set the hardware
- * state for all Links.
- *
- * @param[in] State our global state
- */
-VOID
-STATIC
-LinkOptimization (
- IN STATE_DATA *State
- )
-{
- AGESA_TESTPOINT (TpProcHtOptGather, State->ConfigHandle);
- State->HtFeatures->GatherLinkData (State);
-
- AGESA_TESTPOINT (TpProcHtOptRegang, State->ConfigHandle);
- State->HtFeatures->RegangLinks (State);
-
- AGESA_TESTPOINT (TpProcHtOptLinks, State->ConfigHandle);
- State->HtFeatures->SelectOptimalWidthAndFrequency (State);
-
- // A likely cause of mixed Retry settings on coherent links is sublink ratio balancing
- // so check this after doing the sublinks.
- AGESA_TESTPOINT (TpProcHtOptSubLinks, State->ConfigHandle);
- State->HtFeatures->SubLinkRatioFixup (State);
- if (State->HtFeatures->IsCoherentRetryFixup (State)) {
- // Fix sublinks again within HT1 only frequencies, as ratios may be invalid again.
- State->HtFeatures->SubLinkRatioFixup (State);
- }
-
- AGESA_TESTPOINT (TpProcHtOptFinish, State->ConfigHandle);
- State->HtFeatures->SetLinkData (State);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Handle system and performance tunings.
- *
- * Including traffic distribution, fifo and
- * buffer tuning that can't be placed in the register table,
- * and special config tunings.
- *
- * @param[in] State Total Nodes, port list data
- */
-VOID
-STATIC
-Tuning (
- IN STATE_DATA *State
- )
-{
- UINT8 Node;
-
- // See if traffic distribution can be done and do it if so.
- //
- AGESA_TESTPOINT (TpProcHtTrafficDist, State->ConfigHandle);
- State->HtFeatures->TrafficDistribution (State);
-
- // For each Node, invoke northbridge specific buffer tunings that can not be done in reg table.
- //
- AGESA_TESTPOINT (TpProcHtTuning, State->ConfigHandle);
- for (Node = 0; Node < (State->NodesDiscovered + 1); Node++) {
- State->Nb->BufferOptimizations (Node, State, State->Nb);
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Initialize the Node and Socket maps for an AP Core.
- *
- * In each core's local heap, create a Node to Socket map and a Socket/Module to Node map.
- * The mapping is filled in by reading the AP Mailboxes from PCI config on each node.
- *
- * @param[in] State global state, input data
- *
- */
-VOID
-STATIC
-InitApMaps (
- IN STATE_DATA *State
- )
-{
- UINT8 Node;
- AP_MAIL_INFO NodeApMailBox;
-
- // There is no option to not have socket - node maps, if they aren't allocated that is a fatal bug.
- ASSERT (State->SocketDieToNodeMap != NULL);
- ASSERT (State->NodeToSocketDieMap != NULL);
-
- for (Node = 0; Node < State->Nb->GetNodeCount (State->Nb); Node++) {
- NodeApMailBox = State->Nb->RetrieveMailbox (Node, State->Nb);
- (*State->SocketDieToNodeMap)[NodeApMailBox.Fields.Socket][NodeApMailBox.Fields.Module].Node = Node;
- (*State->NodeToSocketDieMap)[Node].Socket = (UINT8)NodeApMailBox.Fields.Socket;
- (*State->NodeToSocketDieMap)[Node].Die = (UINT8)NodeApMailBox.Fields.Module;
- }
- // This requires the other maps to be initialized.
- UpdateCoreRanges (State);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Is the currently running core the BSC?
- *
- * Determine whether the init steps for BSC or AP core should be run.
- *
- * @param[in] State global state, input data
- *
- * @retval TRUE This is the boot core.
- * @retval FALSE This is not the boot core.
- */
-BOOLEAN
-STATIC
-IsBootCore (
- IN STATE_DATA *State
- )
-{
- UINT64 Value;
-
- LibAmdMsrRead (APIC_Base, &Value, State->ConfigHandle);
-
- return ((BOOLEAN) (((UINT32) (Value & 0xFFFFFFFF) & ((UINT32)1 << APIC_Base_BSP)) != 0));
-}
-
-/***************************************************************************
- *** HT Initialize ***
- ***************************************************************************/
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * The top level external interface for Hypertransport Initialization.
- *
- * Create our initial internal state, initialize the coherent fabric,
- * initialize the non-coherent chains, and perform any required fabric tuning or
- * optimization.
- *
- * @param[in] StdHeader Opaque handle to standard config header
- * @param[in] PlatformConfiguration The platform configuration options.
- * @param[in] AmdHtInterface HT Interface structure.
- *
- * @retval AGESA_SUCCESS Only information events logged.
- * @retval AGESA_ALERT Sync Flood or CRC error logged.
- * @retval AGESA_WARNING Example: expected capability not found
- * @retval AGESA_ERROR logged events indicating some devices may not be available
- * @retval AGESA_FATAL Mixed Family or MP capability mismatch
- *
- */
-AGESA_STATUS
-AmdHtInitialize (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN PLATFORM_CONFIGURATION *PlatformConfiguration,
- IN AMD_HT_INTERFACE *AmdHtInterface
- )
-{
- STATE_DATA State;
- NORTHBRIDGE Nb;
- HT_FEATURES HtFeatures;
- HT_INTERFACE HtInterface;
- AGESA_STATUS DeallocateStatus;
- AP_MAIL_INFO ApMailboxInfo;
- UINT8 ApNode;
-
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
- State.HtBlock = AmdHtInterface;
- State.ConfigHandle = StdHeader;
- State.PlatformConfiguration = PlatformConfiguration;
-
- // Get the current HT internal interface (to HtBlock data)
- NewHtInterface (&HtInterface, State.ConfigHandle);
- State.HtInterface = &HtInterface;
-
- // Get the current HT Feature Set
- NewHtFeatures (&HtFeatures, State.ConfigHandle);
- State.HtFeatures = &HtFeatures;
-
- // Initialize from static options
- State.IsUsingRecoveryHt = OptionHtConfiguration.IsUsingRecoveryHt;
- State.IsSetHtCrcFlood = OptionHtConfiguration.IsSetHtCrcFlood;
- State.IsUsingUnitIdClumping = OptionHtConfiguration.IsUsingUnitIdClumping;
-
- // Initialize for status and event output
- State.MaxEventClass = AGESA_SUCCESS;
-
- // Allocate permanent heap structs that are interfaces to other AGESA services.
- State.HtInterface->NewNodeAndSocketTables (&State);
-
- if (IsBootCore (&State)) {
- AGESA_TESTPOINT (TpProcHtEntry, State.ConfigHandle);
- // Allocate Bsp only interface heap structs.
- State.HtInterface->NewHopCountTable (&State);
- // Allocate heap for our temporary working space.
- AllocHeapParams.RequestedBufferSize = (sizeof (PORT_DESCRIPTOR) * (MAX_PLATFORM_LINKS * 2));
- AllocHeapParams.BufferHandle = HT_STATE_DATA_HANDLE;
- AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
- if (HeapAllocateBuffer (&AllocHeapParams, State.ConfigHandle) == AGESA_SUCCESS) {
- State.PortList = (PORT_LIST)AllocHeapParams.BufferPtr;
- // Create the BSP's northbridge.
- NewNorthBridge (0, &State, &Nb);
- State.Nb = &Nb;
-
- CoherentInit (&State);
- NcInit (&State);
- LinkOptimization (&State);
- Tuning (&State);
-
- DeallocateStatus = HeapDeallocateBuffer (HT_STATE_DATA_HANDLE, State.ConfigHandle);
- ASSERT (DeallocateStatus == AGESA_SUCCESS);
- AGESA_TESTPOINT (TpProcHtDone, State.ConfigHandle);
- } else {
- ASSERT (FALSE);
- State.MaxEventClass = AGESA_ERROR;
- // Cannot Log entry due to heap allocate failed.
- }
- } else {
- // Do the AP HT Init, which produces Node and Socket Maps for the AP's use.
- AGESA_TESTPOINT (TpProcHtApMapEntry, State.ConfigHandle);
- GetApMailbox (&ApMailboxInfo.Info, State.ConfigHandle);
- ASSERT (ApMailboxInfo.Fields.Node < MAX_NODES);
- ApNode = (UINT8)ApMailboxInfo.Fields.Node;
- NewNorthBridge (ApNode, &State, &Nb);
- State.Nb = &Nb;
- InitApMaps (&State);
- AGESA_TESTPOINT (TpProcHtApMapDone, State.ConfigHandle);
- }
- return State.MaxEventClass;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htNb.c b/src/vendorcode/amd/agesa/Proc/HT/htNb.c
deleted file mode 100644
index 4c22149..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htNb.c
+++ /dev/null
@@ -1,247 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Construct a northbridge interface for a Node.
- *
- * Handle build options and run-time detection.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35978 $ @e \$Date: 2010-08-07 02:18:50 +0800 (Sat, 07 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "OptionsHt.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "htNb.h"
-#include "htNbHardwareFam10.h"
-#include "CommonReturns.h"
-#include "cpuRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuFamRegisters.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#include "Filecode.h"
-
-#define FILECODE PROC_HT_HTNB_FILECODE
-
-extern OPTION_HT_CONFIGURATION OptionHtConfiguration;
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/***************************************************************************
- *** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS ***
- ***************************************************************************/
-
-
-/**
- * Initial construction data for no HT Northbridge.
- */
-CONST NORTHBRIDGE ROMDATA HtFam10NbNone =
-{
- 1,
- (PF_WRITE_ROUTING_TABLE)CommonVoid,
- (PF_WRITE_NODEID)CommonVoid,
- (PF_READ_DEFAULT_LINK)CommonReturnZero8,
- (PF_ENABLE_ROUTING_TABLES)CommonVoid,
- (PF_DISABLE_ROUTING_TABLES)CommonVoid,
- (PF_VERIFY_LINK_IS_COHERENT)CommonReturnFalse,
- (PF_READ_TOKEN)CommonReturnZero8,
- (PF_WRITE_TOKEN)CommonVoid,
- (PF_WRITE_FULL_ROUTING_TABLE)CommonVoid,
- (PF_IS_ILLEGAL_TYPE_MIX)CommonReturnFalse,
- (PF_IS_EXCEEDED_CAPABLE)CommonReturnFalse,
- (PF_STOP_LINK)CommonVoid,
- (PF_HANDLE_SPECIAL_LINK_CASE)CommonReturnFalse,
- (PF_HANDLE_SPECIAL_NODE_CASE)CommonReturnFalse,
- (PF_READ_SB_LINK)CommonReturnZero8,
- (PF_VERIFY_LINK_IS_NON_COHERENT)CommonReturnFalse,
- (PF_SET_CONFIG_ADDR_MAP)CommonVoid,
- (PF_NORTH_BRIDGE_FREQ_MASK)CommonReturnZero32,
- (PF_GATHER_LINK_FEATURES)CommonVoid,
- (PF_SET_LINK_REGANG)CommonVoid,
- (PF_SET_LINK_FREQUENCY)CommonVoid,
- (PF_SET_LINK_UNITID_CLUMPING)CommonVoid,
- (PF_WRITE_TRAFFIC_DISTRIBUTION)CommonVoid,
- (PF_WRITE_LINK_PAIR_DISTRIBUTION)CommonVoid,
- (PF_BUFFER_OPTIMIZATIONS)CommonVoid,
- (PF_GET_NUM_CORES_ON_NODE)CommonReturnZero8,
- (PF_SET_TOTAL_NODES_AND_CORES)CommonVoid,
- (PF_GET_NODE_COUNT)CommonReturnZero8,
- (PF_LIMIT_NODES)CommonVoid,
- (PF_READ_TRUE_LINK_FAIL_STATUS)CommonReturnFalse,
- (PF_GET_NEXT_LINK)CommonReturnZero32,
- (PF_GET_PACKAGE_LINK)CommonReturnZero8,
- (PF_MAKE_LINK_BASE)CommonReturnZero32,
- (PF_GET_MODULE_INFO)CommonVoid,
- (PF_POST_MAILBOX)CommonVoid,
- (PF_RETRIEVE_MAILBOX)CommonReturnZero32,
- (PF_GET_SOCKET)CommonReturnZero8,
- (PF_GET_ENABLED_COMPUTE_UNITS)CommonReturnZero8,
- (PF_GET_DUALCORE_COMPUTE_UNITS)CommonReturnZero8,
- 0,
- 0,
- 0,
- TRUE,
- TRUE,
- 0,
- NULL,
- 0,
- NULL,
- (PF_MAKE_KEY)CommonReturnZero64,
- NULL
-};
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Make a compatibility key.
- *
- * @HtNbMethod{::F_MAKE_KEY}
- *
- * Private routine to northbridge code.
- * Create a key which can be used to determine whether a Node is compatible with
- * the discovered configuration so far. Currently, that means the family,
- * extended family of the new Node are the same as the BSP's. Family specific
- * implementations can add whatever else is necessary.
- *
- * @param[in] Node the Node
- * @param[in] Nb this northbridge
- *
- * @return the key
- */
-UINT64
-MakeKey (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- )
-{
- CPU_LOGICAL_ID LogicalId;
- UINT32 RawCpuId;
- PCI_ADDR Reg;
-
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_NB_FUNC_03,
- REG_NB_CPUID_3XFC);
-
- LibAmdPciReadBits (Reg, 31, 0, &RawCpuId, Nb->ConfigHandle);
- GetLogicalIdFromCpuid (RawCpuId, &LogicalId, Nb->ConfigHandle);
- return LogicalId.Family;
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Construct a new northbridge.
- *
- * This routine encapsulates knowledge of how to tell significant differences between
- * families of supported northbridges and what routines can be used in common and
- * which are unique. A fully populated northbridge interface is provided by Nb.
- *
- * @param[in] Node create a northbridge interface for this Node.
- * @param[in] State global state
- * @param[out] Nb the caller's northbridge structure to initialize.
- */
-VOID
-NewNorthBridge (
- IN UINT8 Node,
- IN STATE_DATA *State,
- OUT NORTHBRIDGE *Nb
- )
-{
- CPU_LOGICAL_ID LogicalId;
- UINT64 Match;
- UINT32 RawCpuId;
- PCI_ADDR Reg;
- NORTHBRIDGE **InitializerInstance;
-
- // Start with enough of the key to identify the northbridge interface
- Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
- MakePciBusFromNode (Node),
- MakePciDeviceFromNode (Node),
- CPU_NB_FUNC_03,
- REG_NB_CPUID_3XFC);
- LibAmdPciReadBits (Reg, 31, 0, &RawCpuId, State->ConfigHandle);
- IDS_HDT_CONSOLE (HT_TRACE, "AMD Processor at Node %d has raw CPUID=%x.\n", Node, RawCpuId);
- GetLogicalIdFromCpuid (RawCpuId, &LogicalId, State->ConfigHandle);
- Match = LogicalId.Family;
-
- // Test each Northbridge interface in turn looking for a match.
- // Use it to Init the Nb struct if a match is found.
- //
- ASSERT (OptionHtConfiguration.HtOptionFamilyNorthbridgeList != NULL);
- InitializerInstance = (NORTHBRIDGE **) (OptionHtConfiguration.HtOptionFamilyNorthbridgeList);
- while (*InitializerInstance != NULL) {
- if ((Match & (*InitializerInstance)->CompatibleKey) != 0) {
- LibAmdMemCopy ((VOID *)Nb, (VOID *)*InitializerInstance, (UINT32) sizeof (NORTHBRIDGE), State->ConfigHandle);
- break;
- }
- InitializerInstance++;
- }
- // There must be an available northbridge implementation.
- ASSERT (*InitializerInstance != NULL);
-
- // Set the config handle for passing to the library.
- Nb->ConfigHandle = State->ConfigHandle;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htNb.h b/src/vendorcode/amd/agesa/Proc/HT/htNb.h
deleted file mode 100644
index 1fe814f..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htNb.h
+++ /dev/null
@@ -1,1112 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * HT NorthBridge header
- *
- * Defines the interface to the HT NorthBridge module for use by other internal
- * HT modules. This is not a wrapper or external interface, "public" in the
- * comments below is used in the class definition style and refers to HT client
- * modules only ("private" being for use only by the HT NB module itself).
- *
- * It is expected that there will be multiple northbridge implementation files all
- * conforming to this common interface.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 39162 $ @e \$Date: 2010-10-07 22:41:37 +0800 (Thu, 07 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _HT_NB_H_
-#define _HT_NB_H_
-
-/**
- * @page htimplnb HT Northbridge Implementation Guide
- *
- * The HT Northbridge provides access to the Northbridge hardware, in a manner that
- * isolates calling code from knowledge about the hardware implementation or which
- * features are supported in the current build. This is the mechanism in the HT code for
- * supporting new Family or Model northbridges, as well as the means for supporting
- * multiple northbridges in a single build or mixed revision northbridge sets.
- *
- * @par Adding a Method to the Northbridge
- *
- * To add a new method to the Northbridge, follow these steps.
- * <ul>
- * <li> Create a typedef for the Method with the correct parameters and return type.
- *
- * <ul>
- * <li> Name the method typedef (F_METHOD_NAME)(), where METHOD_NAME is the same
- * name as the method table item, but with "_"'s and UPPERCASE, rather than mixed case.
- * @n <tt> typedef VOID (F_METHOD_NAME)(); </tt> @n
- *
- * <li> Make a reference type for references to a method implementation:
- * @n <tt> /// Reference to a Method </tt>
- * @n <tt> typedef F_METHOD_NAME *PF_METHOD_NAME </tt> @n
- * </ul>
- *
- * <li> One of the parameters to @b all northbridge Methods is @b required to be a
- * reference to its current northbridge object. By convention, this is the
- * last parameter.
- *
- * <li> Provide a standard doxygen function preamble for the Method typedef. Begin the
- * detailed description by providing a reference to the method instances page by including
- * the lines below:
- * @code
- * *
- * * @HtNbInstances
- * *
- * @endcode
- * @note It is important to provide documentation for the method type, because the method may not
- * have an implementation in any families supported by the current package. @n
- *
- * <li> Add to the NORTHBRIDGE struct an item for the Method:
- * @n <tt> PF_METHOD_NAME MethodName; ///< Method: description. </tt> @n
- * </ul>
- *
- * @par Implementing an Instance of a Northbridge method.
- *
- * To implement an instance of a method for a specific feature follow these steps.
- *
- * - In appropriate files, implement the method with the return type and parameters
- * matching the Method typedef.
- * - If the Method implementation is common to all families, use the northbridge file
- * for the function area, for example, add a new coherent initialization support method to the
- * coherent northbridge file.
- * - If the Method implementation is unique to each supported northbridge, use the
- * family specific file for that function area (create it, if it doesn't already exist).
- * The family specific files have the same name as the common one suffixed with "FamNN",
- * or "FamNNRevX" if for a model or revision.
- *
- * - Name the function MethodName(). If Family specific, FamNNMethodName().
- *
- * - Create a doxygen function preamble for the method instance. Begin the detailed description with
- * an Implements command to reference the method type and add this instance to the Method Instances page.
- * @code
- * *
- * * @HtNbMethod{::F_METHOD_NAME}.
- * *
- * @endcode
- *
- * - To access other northbridge routines or data as part of the method implementation,
- * the function must use Nb->OtherMethod(). Do not directly access other northbridge
- * routines, because in the table there may be overrides or this routine may be shared by
- * multiple configurations.
- *
- * - Add the instance, or the correct family specific instance, to the NORTHBRIDGE instances
- * used by the northbridge constructor.
- *
- * - If a northbridge does not need an instance of the method use one of the CommonReturns from
- * CommonReturns.h with the same return type.
- *
- * @par Making common Northbridge Methods.
- *
- * In some cases, Northbridge methods can easily have a common implementation because the hardware
- * is very compatible or is even standard. In other cases, where processor family northbridges
- * differ in their implementation, it may be possible to provide a single, common method
- * implementation. This can be accomplished by adding Northbridge data members.
- *
- * For example, a bit position or bit field mask can be used to accommodate different bit placement or size.
- * Another example, a small table can be used to translate index values from a common set
- * to specific sets.
- *
- * The Northbridge Method Instance must use its NORTHBRIDGE reference parameter to access
- * private data members.
- *
- * @par Invoking HT Northbridge Methods.
- *
- * Each unique northbridge is constructed based on matching the current northbridge.
- * @n @code
- * NORTHBRIDGE Nb;
- * // Create the BSP's northbridge.
- * NewNorthBridge (0, State, &Nb);
- * State->Nb = &Nb;
- * @endcode
- *
- * The following example shows how to invoke a Northbridge method.
- * @n @code
- * State->Nb->MethodName (State->Nb);
- * @endcode
- *
- */
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/** Use a macro to convert a Node number to a PCI device. If some future port of
- * this code needs to, this can easily be replaced by the function declaration:
- * UINT8 makePCIDeviceFromNode(UINT8 Node);
- */
-#define MakePciDeviceFromNode(Node) \
- ((UINT8) (24 + (Node)))
-
-/** Use a macro to convert a Node number to a PCI bus. If some future port of
- * this code needs to, this can easily be replaced by the function declaration:
- * UINT8 MakePciBusFromNode(UINT8 Node);
- */
-#define MakePciBusFromNode(Node) \
- ((UINT8) (0))
-
-/** Use a macro to convert a Node number to a PCI Segment. If some future port of
- * this code needs to, this can easily be replaced by the function declaration:
- * UINT8 MakePciSegmentFromNode(UINT8 Node);
- */
-#define MakePciSegmentFromNode(Node) \
- ((UINT8) (0))
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-/**
- * Status for iterating through internal (if supported) and external links.
- */
-typedef enum {
- LinkIteratorEnd, ///< This is the end of all links, no valid link.
- LinkIteratorExternal, ///< The next link (the one we got on this call) is an external link.
- LinkIteratorInternal, ///< The next link (the one we got on this call) is an internal link.
- LinkIteratorMax ///< For bounds checking and limit only.
-} LINK_ITERATOR_STATUS;
-
-#define LINK_ITERATOR_BEGIN 0xFF
-
-/**
- * Write a temporary Route.
- *
- * @HtNbInstances
- *
- * @param[in] Node The node on which to set a temporary route
- * @param[in] Target A route to this node, which route table entry is to be set
- * @param[in] Link The link which routes to the target node
- * @param[in] Nb This northbridge
- */
-typedef VOID F_WRITE_ROUTING_TABLE (
- IN UINT8 Node,
- IN UINT8 Target,
- IN UINT8 Link,
- IN NORTHBRIDGE *Nb
- );
-/// Reference to a method.
-typedef F_WRITE_ROUTING_TABLE *PF_WRITE_ROUTING_TABLE;
-
-/**
- * Modifies the NodeID register on the target Node
- *
- * @HtNbInstances
- *
- * @param[in] Node the Node that will have its NodeID altered.
- * @param[in] NodeID the new value for NodeID
- * @param[in] Nb this northbridge
- */
-typedef VOID F_WRITE_NODEID (
- IN UINT8 Node,
- IN UINT8 NodeID,
- IN NORTHBRIDGE *Nb
- );
-/// Reference to a method.
-typedef F_WRITE_NODEID *PF_WRITE_NODEID;
-
-/**
- * Read the Default Link
- *
- * @HtNbInstances
- *
- * @param[in] Node the Node that will have its NodeID altered.
- * @param[in] Nb this northbridge
- *
- * @return The HyperTransport Link where the request to
- * read the default Link came from. Since this code is running on the BSP,
- * this should be the Link pointing back towards the BSP.
- */
-typedef UINT8 F_READ_DEFAULT_LINK (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- );
-/// Reference to a method.
-typedef F_READ_DEFAULT_LINK *PF_READ_DEFAULT_LINK;
-
-/**
- * Turns routing tables on for a given Node
- *
- * @HtNbInstances
- *
- * @param[in] Node the Node that will have it's routing tables enabled
- * @param[in] Nb this northbridge
- */
-typedef VOID F_ENABLE_ROUTING_TABLES (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- );
-/// Reference to a method.
-typedef F_ENABLE_ROUTING_TABLES *PF_ENABLE_ROUTING_TABLES;
-
-/**
- * Turns routing tables off for a given Node
- *
- * @HtNbInstances
- *
- * @param[in] Node the Node that will have it's routing tables disabled
- * @param[in] Nb this northbridge
- */
-typedef VOID F_DISABLE_ROUTING_TABLES (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- );
-/// Reference to a method.
-typedef F_DISABLE_ROUTING_TABLES *PF_DISABLE_ROUTING_TABLES;
-
-/**
- * Verify that the Link is coherent, connected, and ready
- *
- * @HtNbInstances
- *
- * @param[in] Node the Node that will be examined
- * @param[in] Link the Link on that Node to examine
- * @param[in] Nb this northbridge
- *
- * @retval TRUE The Link is coherent
- * @retval FALSE The Link has some other status
-*/
-typedef BOOLEAN F_VERIFY_LINK_IS_COHERENT (
- IN UINT8 Node,
- IN UINT8 Link,
- IN NORTHBRIDGE *Nb
- );
-/// Reference to a method.
-typedef F_VERIFY_LINK_IS_COHERENT *PF_VERIFY_LINK_IS_COHERENT;
-
-/**
- * Read the token stored in the scratchpad register field.
- *
- * @HtNbInstances
- *
- * @param[in] Node the Node that will be examined
- * @param[in] Nb this northbridge
- *
- * @return the Token read from the Node
- */
-typedef UINT8 F_READ_TOKEN (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- );
-/// Reference to a method.
-typedef F_READ_TOKEN *PF_READ_TOKEN;
-
-/**
- * Write the token stored in the scratchpad register
- *
- * @HtNbInstances
- *
- * @param[in] Node the Node that marked with token
- * @param[in] Value the token Value
- * @param[in] Nb this northbridge
- */
-typedef VOID F_WRITE_TOKEN (
- IN UINT8 Node,
- IN UINT8 Value,
- IN NORTHBRIDGE *Nb
- );
-/// Reference to a method.
-typedef F_WRITE_TOKEN *PF_WRITE_TOKEN;
-
-/**
- * Full Routing Table Register initialization
- *
- * @HtNbInstances
- *
- * @param[in] Node the Node that will be examined
- * @param[in] Target the Target Node for these routes
- * @param[in] ReqLink the Link for requests to Target
- * @param[in] RspLink the Link for responses to Target
- * @param[in] BroadcastLinks the broadcast Links
- * @param[in] Nb this northbridge
- */
-typedef VOID F_WRITE_FULL_ROUTING_TABLE (
- IN UINT8 Node,
- IN UINT8 Target,
- IN UINT8 ReqLink,
- IN UINT8 RspLink,
- IN UINT32 BroadcastLinks,
- IN NORTHBRIDGE *Nb
- );
-/// Reference to a method.
-typedef F_WRITE_FULL_ROUTING_TABLE *PF_WRITE_FULL_ROUTING_TABLE;
-
-/**
- * Determine whether a Node is compatible with the discovered configuration so far.
- *
- * @HtNbInstances
- *
- * @param[in] Node the Node
- * @param[in] Nb this northbridge
- *
- * @retval TRUE the node is not compatible
- * @retval FALSE the node is compatible
- */
-typedef BOOLEAN F_IS_ILLEGAL_TYPE_MIX (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- );
-/// Reference to a method.
-typedef F_IS_ILLEGAL_TYPE_MIX *PF_IS_ILLEGAL_TYPE_MIX;
-
-/**
- * Return whether the current configuration exceeds the capability
- * of the nodes detected.
- *
- * @HtNbInstances
- *
- * @param[in] Node the Node
- * @param[in] State sysMpCap (updated) and NodesDiscovered
- * @param[in] Nb this northbridge
- *
- * @retval TRUE system is not capable of current config.
- * @retval FALSE system is capable of current config.
- */
-typedef BOOLEAN F_IS_EXCEEDED_CAPABLE (
- IN UINT8 Node,
- IN STATE_DATA *State,
- IN NORTHBRIDGE *Nb
- );
-/// Reference to a method.
-typedef F_IS_EXCEEDED_CAPABLE *PF_IS_EXCEEDED_CAPABLE;
-
-/**
- * Stop a link, so that it is isolated from a connected device.
- *
- * @HtNbInstances
- *
- * Use is for fatal incompatible configurations.
- * While XMIT and RCV off are HT standard, the use of these bits
- * is generally family specific.
- *
- * @param[in] Node the node to stop a link on.
- * @param[in] Link the link to stop.
- * @param[in] State access to special routine for writing link control register
- * @param[in] Nb this northbridge.
- */
-typedef VOID F_STOP_LINK (
- IN UINT8 Node,
- IN UINT8 Link,
- IN STATE_DATA *State,
- IN NORTHBRIDGE *Nb
- );
-/// Reference to a method.
-typedef F_STOP_LINK *PF_STOP_LINK;
-
-/**
- * Fix (hopefully) exceptional conditions.
- *
- * @HtNbInstances
- *
- * This routine is expected to be unimplemented for most families.
- * Some configurations may require that links be processed specially to prevent
- * serious problems, like hangs. Check for that condition in this routine,
- * handle the link both for hardware and for adding to port list, if appropriate.
- * If this routine adds the link to port list or the link should not be added, return TRUE.
- *
- * @param[in] Node The Node which has this link
- * @param[in] Link The link to check for special conditions.
- * @param[in] State our global state.
- * @param[in] Nb this northbridge.
- *
- * @retval TRUE This link received special handling.
- * @retval FALSE This link was not handled specially, handle it normally.
- *
- */
-typedef BOOLEAN F_HANDLE_SPECIAL_LINK_CASE (
- IN UINT8 Node,
- IN UINT8 Link,
- IN STATE_DATA *State,
- IN NORTHBRIDGE *Nb
- );
-/// Reference to a method.
-typedef F_HANDLE_SPECIAL_LINK_CASE *PF_HANDLE_SPECIAL_LINK_CASE;
-
-/**
- * Fix (hopefully) exceptional conditions.
- *
- * @HtNbInstances
- *
- * This routine is expected to be unimplemented for most families.
- * Some configurations may require that nodes be processed specially to prevent
- * serious problems, like hangs. Check for that condition in this routine,
- * handle the node both for hardware and for adding to port list, if appropriate.
- * If this routine adds the node to port list or the node should not be added, return TRUE.
- *
- * @param[in] Node The Node which need to be checked.
- * @param[in] Link The link to check for special conditions.
- * @param[in] State our global state.
- * @param[in] Nb this northbridge.
- *
- * @retval TRUE This node received special handling.
- * @retval FALSE This node was not handled specially, handle it normally.
- *
- */
-typedef BOOLEAN F_HANDLE_SPECIAL_NODE_CASE (
- IN UINT8 Node,
- IN UINT8 Link,
- IN STATE_DATA *State,
- IN NORTHBRIDGE *Nb
- );
-/// Reference to a method.
-typedef F_HANDLE_SPECIAL_NODE_CASE *PF_HANDLE_SPECIAL_NODE_CASE;
-
-/**
- * Get Info about Module Type of this northbridge
- *
- * @HtNbInstances
- *
- * @param[in] Node the Node
- * @param[out] ModuleType 0 for Single, 1 for Multi
- * @param[out] Module The module number of this node (0 if Single)
- * @param[in] Nb this northbridge
- *
- */
-typedef VOID F_GET_MODULE_INFO (
- IN UINT8 Node,
- OUT UINT8 *ModuleType,
- OUT UINT8 *Module,
- IN NORTHBRIDGE *Nb
- );
-/// Reference to a method.
-typedef F_GET_MODULE_INFO *PF_GET_MODULE_INFO;
-
-/**
- * Post info to AP cores via a mailbox.
- *
- * @HtNbInstances
- *
- * @param[in] Node the Node
- * @param[in] ApMailInfo The info to post
- * @param[in] Nb this northbridge
- *
- */
-typedef VOID F_POST_MAILBOX (
- IN UINT8 Node,
- IN AP_MAILBOXES ApMailInfo,
- IN NORTHBRIDGE *Nb
- );
-/// Reference to a method.
-typedef F_POST_MAILBOX *PF_POST_MAILBOX;
-
-/**
- * Retrieve info from a node's AP mailbox.
- *
- * @HtNbInstances
- *
- * @param[in] Node the Node
- * @param[in] ApMailInfo The info to post
- * @param[in] Nb this northbridge
- *
- */
-typedef AP_MAIL_INFO F_RETRIEVE_MAILBOX (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- );
-/// Reference to a method.
-typedef F_RETRIEVE_MAILBOX *PF_RETRIEVE_MAILBOX;
-
-/**
- * Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register.
- *
- * @HtNbInstances
- *
- * @param[in] Node The node for which we want the socket id.
- * @param[in] TempNode The temporary node id route where the node can be accessed.
- * @param[in] Nb Our Northbridge.
- *
- * @return The Socket Id
- */
-typedef UINT8 F_GET_SOCKET (
- IN UINT8 Node,
- IN UINT8 TempNode,
- IN NORTHBRIDGE *Nb
- );
-
-/// Reference to a method.
-typedef F_GET_SOCKET *PF_GET_SOCKET;
-
-/**
- * Get the enabled Compute Units.
- *
- * Processors which don't support compute units return zero.
- *
- * @HtNbInstances
- *
- * @param[in] Node The node for which we want the socket id.
- * @param[in] Nb Our Northbridge.
- *
- * @return The Socket Id
- */
-typedef UINT8 F_GET_ENABLED_COMPUTE_UNITS (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- );
-
-/// Reference to a method.
-typedef F_GET_ENABLED_COMPUTE_UNITS *PF_GET_ENABLED_COMPUTE_UNITS;
-
-/**
- * Get the dual core Compute Units.
- *
- * Processors which don't support compute units return zero.
- *
- * @HtNbInstances
- *
- * @param[in] Node The node for which we want the socket id.
- * @param[in] Nb Our Northbridge.
- *
- * @return The Socket Id
- */
-typedef UINT8 F_GET_DUALCORE_COMPUTE_UNITS (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- );
-
-/// Reference to a method.
-typedef F_GET_DUALCORE_COMPUTE_UNITS *PF_GET_DUALCORE_COMPUTE_UNITS;
-
-/**
- * Return the Link to the Southbridge
- *
- * @HtNbInstances
- *
- * @param[in] Nb this northbridge
- *
- * @return the Link to the southbridge
- */
-typedef UINT8 F_READ_SB_LINK (
- IN NORTHBRIDGE *Nb
- );
-/// Reference to a method.
-typedef F_READ_SB_LINK *PF_READ_SB_LINK;
-
-/**
- * Verify that the Link is non-coherent, connected, and ready
- *
- * @HtNbInstances
- *
- * @param[in] Node the Node that will be examined
- * @param[in] Link the Link on that Node to examine
- * @param[in] Nb this northbridge
- *
- * @retval TRUE The Link is non-coherent.
- * @retval FALSE The Link has some other status
- */
-typedef BOOLEAN F_VERIFY_LINK_IS_NON_COHERENT (
- IN UINT8 Node,
- IN UINT8 Link,
- IN NORTHBRIDGE *Nb
- );
-/// Reference to a method.
-typedef F_VERIFY_LINK_IS_NON_COHERENT *PF_VERIFY_LINK_IS_NON_COHERENT;
-
-/**
- * Enable config access to a non-coherent chain for the given bus range.
- *
- * @HtNbInstances
- *
- * @param[in] ConfigMapIndex the map entry to set
- * @param[in] SecBus The secondary bus number to use
- * @param[in] SubBus The subordinate bus number to use
- * @param[in] TargetNode The Node that shall be the recipient of the traffic
- * @param[in] TargetLink The Link that shall be the recipient of the traffic
- * @param[in] State our global state
- * @param[in] Nb this northbridge
- */
-typedef VOID F_SET_CONFIG_ADDR_MAP (
- IN UINT8 ConfigMapIndex,
- IN UINT8 SecBus,
- IN UINT8 SubBus,
- IN UINT8 TargetNode,
- IN UINT8 TargetLink,
- IN STATE_DATA *State,
- IN NORTHBRIDGE *Nb
- );
-/// Reference to a method.
-typedef F_SET_CONFIG_ADDR_MAP *PF_SET_CONFIG_ADDR_MAP;
-
-/**
- * Northbridge specific Frequency limit.
- *
- * @HtNbInstances
- *
- * Return a mask that eliminates HT frequencies that cannot be used due to a slow
- * northbridge frequency.
- *
- * @param[in] Node Result could (later) be for a specific Node
- * @param[in] Interface Access to non-HT support functions.
- * @param[in] PlatformConfig Platform profile/build option config structure.
- * @param[in] Nb this northbridge
- *
- * @return Frequency mask
- */
-typedef UINT32 F_NORTH_BRIDGE_FREQ_MASK (
- IN UINT8 Node,
- IN HT_INTERFACE *Interface,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN NORTHBRIDGE *Nb
- );
-/// Reference to a method.
-typedef F_NORTH_BRIDGE_FREQ_MASK *PF_NORTH_BRIDGE_FREQ_MASK;
-
-/**
- * Get Link features into system data structure.
- *
- * @HtNbInstances
- *
- * @param[in,out] ThisPort The PortList structure entry for this link's port
- * @param[in] Interface Access to non-HT support functions.
- * @param[in] PlatformConfig Platform profile/build option config structure.
- * @param[in] Nb this northbridge
- */
-typedef VOID F_GATHER_LINK_FEATURES (
- IN OUT PORT_DESCRIPTOR *ThisPort,
- IN HT_INTERFACE *Interface,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN NORTHBRIDGE *Nb
- );
-/// Reference to a method.
-typedef F_GATHER_LINK_FEATURES *PF_GATHER_LINK_FEATURES;
-
-/**
- * Change the hardware state for all Links according to the now optimized data in the
- * port list data structure.
- *
- * @HtNbInstances
- *
- * @param[in] Node the node on which to regang a link
- * @param[in] Link the sublink 0 of the sublink pair to regang
- * @param[in] Nb this northbridge
- */
-typedef VOID F_SET_LINK_REGANG (
- IN UINT8 Node,
- IN UINT8 Link,
- IN NORTHBRIDGE *Nb
- );
-/// Reference to a method.
-typedef F_SET_LINK_REGANG *PF_SET_LINK_REGANG;
-
-/**
- * Change the hardware state for all Links according to the now optimized data in the
- * port list data structure.
- *
- * @HtNbInstances
- *
- * @param[in] Node the node on which to set frequency for a link
- * @param[in] Link the link to set frequency
- * @param[in] Frequency the frequency to set
- * @param[in] Nb this northbridge
- */
-typedef VOID F_SET_LINK_FREQUENCY (
- IN UINT8 Node,
- IN UINT8 Link,
- IN UINT8 Frequency,
- IN NORTHBRIDGE *Nb
- );
-/// Reference to a method.
-typedef F_SET_LINK_FREQUENCY *PF_SET_LINK_FREQUENCY;
-
-/**
- * Set the link's Unit Id Clumping enable.
- *
- * @HtNbInstances
- *
- * This applies to the host root of a non-coherent chain.
- *
- * @param[in] Node the node on which to set frequency for a link
- * @param[in] Link the link to set frequency
- * @param[in] ClumpingEnables the unit id clumping enables to set
- * @param[in] Nb this northbridge
- */
-typedef VOID F_SET_LINK_UNITID_CLUMPING (
- IN UINT8 Node,
- IN UINT8 Link,
- IN UINT32 ClumpingEnables,
- IN NORTHBRIDGE *Nb
- );
-/// Reference to a method.
-typedef F_SET_LINK_UNITID_CLUMPING *PF_SET_LINK_UNITID_CLUMPING;
-
-/**
- * Set the traffic distribution register for the Links provided.
- *
- * @HtNbInstances
- *
- * @param[in] Links01 coherent Links from Node 0 to 1
- * @param[in] Links10 coherent Links from Node 1 to 0
- * @param[in] Nb this northbridge
- */
-typedef VOID F_WRITE_TRAFFIC_DISTRIBUTION (
- IN UINT32 Links01,
- IN UINT32 Links10,
- IN NORTHBRIDGE *Nb
- );
-/// Reference to a method.
-typedef F_WRITE_TRAFFIC_DISTRIBUTION *PF_WRITE_TRAFFIC_DISTRIBUTION;
-
-/**
- * Write a link pair to the link pair distribution and fixups.
- *
- * @HtNbInstances
- *
- * @param[in] Node Set the pair on this node
- * @param[in] ConnectedNode The Node to which this link pair directly connects.
- * @param[in] Pair Using this pair set in the register
- * @param[in] Asymmetric True if different widths
- * @param[in] MasterLink Set this as the master link and in the route
- * @param[in] AlternateLink Set this as the alternate link
- * @param[in] Nb this northbridge
- *
- */
-typedef VOID F_WRITE_LINK_PAIR_DISTRIBUTION (
- IN UINT8 Node,
- IN UINT8 ConnectedNode,
- IN UINT8 Pair,
- IN BOOLEAN Asymmetric,
- IN UINT8 MasterLink,
- IN UINT8 AlternateLink,
- IN NORTHBRIDGE *Nb
- );
-/// Pointer to method WriteLinkPairDistribution
-typedef F_WRITE_LINK_PAIR_DISTRIBUTION *PF_WRITE_LINK_PAIR_DISTRIBUTION;
-
-/**
- * Family specific tunings.
- *
- * @HtNbInstances
- *
- * Buffer tunings are inherently northbridge specific. Check for specific configs
- * which require adjustments and apply any standard workarounds to this Node.
- *
- * @param[in] Node the Node to tune
- * @param[in] State global state
- * @param[in] Nb this northbridge
- */
-typedef VOID F_BUFFER_OPTIMIZATIONS (
- IN UINT8 Node,
- IN STATE_DATA *State,
- IN NORTHBRIDGE *Nb
- );
-/// Reference to a method.
-typedef F_BUFFER_OPTIMIZATIONS *PF_BUFFER_OPTIMIZATIONS;
-
-/**
- * Return the number of cores (1 based count) on Node.
- *
- * @HtNbInstances
- *
- * @param[in] Node the Node that will be examined
- * @param[in] Nb this northbridge
- *
- * @return the number of cores
- */
-typedef UINT8 F_GET_NUM_CORES_ON_NODE (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- );
-/// Reference to a method.
-typedef F_GET_NUM_CORES_ON_NODE *PF_GET_NUM_CORES_ON_NODE;
-
-/**
- * Write the total number of cores and Nodes to the Node
- *
- * @HtNbInstances
- *
- * @param[in] Node the Node that will be examined
- * @param[in] TotalNodes the total number of Nodes
- * @param[in] TotalCores the total number of cores
- * @param[in] Nb this northbridge
- */
-typedef VOID F_SET_TOTAL_NODES_AND_CORES (
- IN UINT8 Node,
- IN UINT8 TotalNodes,
- IN UINT8 TotalCores,
- IN NORTHBRIDGE *Nb
- );
-/// Reference to a method.
-typedef F_SET_TOTAL_NODES_AND_CORES *PF_SET_TOTAL_NODES_AND_CORES;
-
-/**
- * Get the Count of Nodes in the system.
- *
- * @HtNbInstances
- *
- * @param[in] Nb This Northbridge.
- *
- * @return The Count (1 based) of Nodes in the system.
- */
-typedef UINT8 F_GET_NODE_COUNT (
- IN NORTHBRIDGE *Nb
- );
-
-/// Reference to a method.
-typedef F_GET_NODE_COUNT *PF_GET_NODE_COUNT;
-
-/**
- * Limit coherent config accesses to cpus as indicated by Nodecnt.
- *
- * @HtNbInstances
- *
- * @param[in] Node the Node that will be examined
- * @param[in] Nb this northbridge
- */
-typedef VOID F_LIMIT_NODES (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- );
-/// Reference to a method.
-typedef F_LIMIT_NODES *PF_LIMIT_NODES;
-
-/**
- * Return the LinkFailed status AFTER an attempt is made to clear the bit.
- *
- * @HtNbInstances
- *
- * @param[in] Node the Node that will be examined
- * @param[in] Link the Link on that Node to examine
- * @param[in] State access to call back routine
- * @param[in] Nb this northbridge
- *
- * @retval TRUE the Link is not connected or has hard error
- * @retval FALSE the Link is connected
- */
-typedef BOOLEAN F_READ_TRUE_LINK_FAIL_STATUS (
- IN UINT8 Node,
- IN UINT8 Link,
- IN STATE_DATA *State,
- IN NORTHBRIDGE *Nb
- );
-/// Reference to a method.
-typedef F_READ_TRUE_LINK_FAIL_STATUS *PF_READ_TRUE_LINK_FAIL_STATUS;
-
-/**
- * Get the next link for iterating over the links on a node in the correct order.
- *
- * @HtNbInstances
- *
- * @param[in] Node The node on which to iterate links.
- * @param[in,out] Link IN: the current iteration context, OUT: the next link.
- * @param[in] Nb This Northbridge, access to config pointer.
- *
- * @retval LinkIteratorEnd There is no next link (Link is back to BEGIN).
- * @retval LinkIteratorExternal The next Link is an external link.
- * @retval LinkIteratorInternal The next Link is an internal link.
- */
-typedef LINK_ITERATOR_STATUS F_GET_NEXT_LINK (
- IN UINT8 Node,
- IN OUT UINT8 *Link,
- IN NORTHBRIDGE *Nb
- );
-/// Pointer to method GetNextLink
-typedef F_GET_NEXT_LINK *PF_GET_NEXT_LINK;
-
-/**
- * Get the Package Link number, given the node and real link number.
- *
- * @HtNbInstances
- *
- * @param[in] Node the node which has this link
- * @param[in] Link the link on that node
- * @param[in] Nb this northbridge
- *
- * @return the Package Link
- *
- */
-typedef UINT8 F_GET_PACKAGE_LINK (
- IN UINT8 Node,
- IN UINT8 Link,
- IN NORTHBRIDGE *Nb
- );
-/// Reference to a method
-typedef F_GET_PACKAGE_LINK *PF_GET_PACKAGE_LINK;
-
-/**
- * Return the HT Host capability base PCI config address for a Link.
- *
- * @HtNbInstances
- *
- * @param[in] Node the Node this Link is on
- * @param[in] Link the Link
- * @param[in] Nb this northbridge
- *
- * @return the pci config address
- */
-typedef PCI_ADDR F_MAKE_LINK_BASE (
- IN UINT8 Node,
- IN UINT8 Link,
- IN NORTHBRIDGE *Nb
- );
-/// Reference to a method.
-typedef F_MAKE_LINK_BASE *PF_MAKE_LINK_BASE;
-
-/**
- * Make a compatibility key.
- *
- * @HtNbInstances
- *
- * @param[in] Node the Node
- * @param[in] Nb this northbridge
- *
- * @return the key
- */
-typedef UINT64 F_MAKE_KEY (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- );
-/// Reference to a method.
-typedef F_MAKE_KEY *PF_MAKE_KEY;
-
-/**
- * The northbridge interface.
- *
- * Abstract the hardware implementation of the processor northbridge. Feature code does
- * not need to be tailored to specific families. Also, more than a single family (or
- * model in some cases) can be supported at once. Multiple family support can be for
- * mixed revisions or for incompatible revisions where only one is used at a time.
- *
- * The northbridge object contains both HT component public and northbridge private
- * members. These sets are grouped together. Within each group, members are grouped
- * according to the function area they support.
- *
- */
-struct _NORTHBRIDGE { // See forward declaration in HtFeats.h
- /* Public data, clients of northbridge can access */
- UINT8 MaxLinks; /**< The maximum number of Links implemented by the northbridge */
-
- /* Public Interfaces for northbridge clients, coherent init*/
- PF_WRITE_ROUTING_TABLE WriteRoutingTable; /**< Method: Write a Temporary route for discovery */
- PF_WRITE_NODEID WriteNodeID; /**< Method: Assign a Node ID*/
- PF_READ_DEFAULT_LINK ReadDefaultLink; /**< Method: Which link are we connected to on a remote node? */
- PF_ENABLE_ROUTING_TABLES EnableRoutingTables; /**< Method: Make the routing table active */
- PF_DISABLE_ROUTING_TABLES DisableRoutingTables; /**< Method: Put a node back in discoverable state (deflnk) */
- PF_VERIFY_LINK_IS_COHERENT VerifyLinkIsCoherent; /**< Method: is a link connected and coherent? */
- PF_READ_TOKEN ReadToken; /**< Method: Read the enumeration token from a node */
- PF_WRITE_TOKEN WriteToken; /**< Method: Assign an enumeration token to a node */
- PF_WRITE_FULL_ROUTING_TABLE WriteFullRoutingTable; /**< Method: Set a complete routing table entry on a node */
- PF_IS_ILLEGAL_TYPE_MIX IsIllegalTypeMix; /**< Method: Is this node compatible with the system */
- PF_IS_EXCEEDED_CAPABLE IsExceededCapable; /**< Method: Is this node capable of working in this system */
- PF_STOP_LINK StopLink; /**< Method: stop a link which must be unused */
- PF_HANDLE_SPECIAL_LINK_CASE HandleSpecialLinkCase; /**< Method: Fix broken configuration designs */
- PF_HANDLE_SPECIAL_NODE_CASE HandleSpecialNodeCase; /**< Method: Fix broken configuration designs */
-
- /* Public Interfaces for northbridge clients, noncoherent init */
- PF_READ_SB_LINK ReadSouthbridgeLink; /**< Method: Which link goes to the southbridge? */
- PF_VERIFY_LINK_IS_NON_COHERENT VerifyLinkIsNonCoherent; /**< Method: is a link connected and non-coherent? */
- PF_SET_CONFIG_ADDR_MAP SetConfigAddrMap; /**< Method: Add a non-coherent chain to the PCI Config Bus Address Map */
-
- /* Public Interfaces for northbridge clients, Optimization */
- PF_NORTH_BRIDGE_FREQ_MASK NorthBridgeFreqMask; /**< Method: Check for frequency limits other than HT */
- PF_GATHER_LINK_FEATURES GatherLinkFeatures; /**< Method: Get frequency and link features */
- PF_SET_LINK_REGANG SetLinkRegang; /**< Method: Set a Link to regang */
- PF_SET_LINK_FREQUENCY SetLinkFrequency; /**< Method: Set the link Frequency */
- PF_SET_LINK_UNITID_CLUMPING SetLinkUnitIdClumping; /**< Method: Set the link's Unit Id Clumping register */
-
- /* Public Interfaces for northbridge clients, System and performance Tuning. */
- PF_WRITE_TRAFFIC_DISTRIBUTION WriteTrafficDistribution; /**< Method: traffic distribution setting */
- PF_WRITE_LINK_PAIR_DISTRIBUTION WriteLinkPairDistribution; /**< Method: Link Pair setting and fix up */
- PF_BUFFER_OPTIMIZATIONS BufferOptimizations; /**< Method: system tunings which can not be
- * done using register table */
-
- /* Public Interfaces for northbridge clients, utility routines */
- PF_GET_NUM_CORES_ON_NODE GetNumCoresOnNode; /**< Method: Count cores */
- PF_SET_TOTAL_NODES_AND_CORES SetTotalNodesAndCores; /**< Method: Set Node and Core counts */
- PF_GET_NODE_COUNT GetNodeCount; /**< Method: Get the Count (1 based) of Nodes in the system. */
- PF_LIMIT_NODES LimitNodes; /**< Method: Set the Limit Config Space feature */
- PF_READ_TRUE_LINK_FAIL_STATUS ReadTrueLinkFailStatus; /**< Method: Get Fault status and connectivity of a link */
- PF_GET_NEXT_LINK GetNextLink; /**< Method: Iterate over a node's Internal, then External links. */
- PF_GET_PACKAGE_LINK GetPackageLink; /**< Method: the package link corresponding to a node's link */
- PF_MAKE_LINK_BASE MakeLinkBase; /**< Method: Provide the PCI Config Base register offset of a CPU link */
- PF_GET_MODULE_INFO GetModuleInfo; /**< Method: Get Module Type and internal Module number */
- PF_POST_MAILBOX PostMailbox; /**< Method: Post info to the mailbox register */
- PF_RETRIEVE_MAILBOX RetrieveMailbox; /**< Method: Retrieve info from the mailbox register */
- PF_GET_SOCKET GetSocket; /**< Method: Get a node's Socket, using the hardware naming method. */
- PF_GET_ENABLED_COMPUTE_UNITS GetEnabledComputeUnits; /**< Method: Get the Enabled Compute Units */
- PF_GET_DUALCORE_COMPUTE_UNITS GetDualCoreComputeUnits; /**< Method: Get which Compute Units have two cores. */
-
- /* Private Data for northbridge implementation use only */
- UINT32 SelfRouteRequestMask; /**< Bit pattern for route request to self in routing table register */
- UINT32 SelfRouteResponseMask; /**< Bit pattern for route response to self in routing table register */
- UINT8 BroadcastSelfBit; /**< Bit offset of broadcast self bit in routing table register */
- BOOLEAN IsOrderBSPCoresByNode; /**< This processor orders Cores by Node id on the BSP, if TRUE. */
- BOOLEAN IsOrderCoresByModule; /**< Processors other than the BSP order Cores by Module, if TRUE. */
- UINT64 CompatibleKey; /**< Used for checking compatibility of northbridges in the system */
- PACKAGE_HTLINK_MAP PackageLinkMap; /**< Tell GetPackageLink() how to assign link names */
- UINT32 CoreFrequency; /**< Cache the northbridge core frequency, so repeated interface calls are avoided.
- * A value of zero, means no value yet. */
- IGNORE_LINK *DefaultIgnoreLinkList; /**< After processing the user interface ignore link, process this list. */
-
- /* Private Interfaces for northbridge implementation. */
- PF_MAKE_KEY MakeKey; /**< Method: make the compatibility key for this node */
-
- /** Config Pointer, opaque handle for passing to lib */
- VOID *ConfigHandle;
-};
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-/**
- * Make a compatibility key.
- *
- */
-UINT64
-MakeKey (
- IN UINT8 Node,
- IN NORTHBRIDGE *Nb
- );
-
-VOID
-NewNorthBridge (
- IN UINT8 Node,
- IN STATE_DATA *State,
- OUT NORTHBRIDGE *Nb
- );
-
-#endif /* _HT_NB_H_ */
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htNbHardwareFam10.h b/src/vendorcode/amd/agesa/Proc/HT/htNbHardwareFam10.h
deleted file mode 100644
index 8945635..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htNbHardwareFam10.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Northbridge hardware definitions for Family 10h.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _HT_NB_HARDWARE_FAM10_H_
-#define _HT_NB_HARDWARE_FAM10_H_
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/* CPU Northbridge Functions */
-#define CPU_HTNB_FUNC_00 0
-#define CPU_HTNB_FUNC_04 4
-#define CPU_ADDR_FUNC_01 1
-#define CPU_NB_FUNC_03 3
-#define CPU_NB_FUNC_05 5
-
-/* Function 0 registers */
-#define REG_ROUTE0_0X40 0x40
-#define REG_ROUTE1_0X44 0x44
-#define REG_NODE_ID_0X60 0x60
-#define REG_UNIT_ID_0X64 0x64
-#define REG_LINK_TRANS_CONTROL_0X68 0x68
-#define REG_LINK_INIT_CONTROL_0X6C 0x6C
-#define REG_HT_CAP_BASE_0X80 0x80
-#define REG_HT_LINK_CLUMPING0_0X110 0x110
-#define REG_HT_LINK_RETRY0_0X130 0x130
-#define REG_HT_EXTENDED_NODE_ID_F0X160 0x160
-#define HTREG_NODE_CPUCNT_4_0 0x1F
-#define HTREG_EXTNODE_CPUCNT_7_5 0xE0
-#define REG_HT_TRAFFIC_DIST_0X164 0x164
-#define REG_LINK_GLOBAL_EXT_CONTROL_0x16C 0x16C
-#define REG_HT_LINK_EXT_CONTROL0_0X170 0x170
-#define REG_HT_LINK_INITIALIZATION_0X1A0 0x1A0
-#define PAIR_SELECT_OFFSET 8
-#define REG_HT_LINK_PAIR_DIST_0X1E0 0x1E0
-
-/* Function 1 registers */
-#define REG_ADDR_CONFIG_MAP0_1XE0 0xE0
-#define CPU_ADDR_NUM_CONFIG_MAPS 4
-
-/* Function 3 registers */
-#define REG_NB_SRI_XBAR_BUF_3X70 0x70
-#define REG_NB_MCT_XBAR_BUF_3X78 0x78
-#define REG_NB_FIFOPTR_3XDC 0xDC
-#define REG_NB_CAPABILITY_3XE8 0xE8
-#define REG_NB_CPUID_3XFC 0xFC
-#define REG_NB_LINK_XCS_TOKEN0_3X148 0x148
-#define REG_NB_MCA_LINK_THRESHOLD_3X168 0x168
-#define REG_NB_MCA_L3_THRESHOLD_3X170 0x170
-#define REG_NB_DOWNCORE_3X190 0x190
-#define REG_NB_SBI_CONTROL_3X1E4 0x1E4
-
-/* Function 4 registers */
-
-/* Function 5 registers */
-#define REG_NB_COMPUTE_UNIT_5X80 0x80
-#define REG_NB_CAPABILITY_2_5X84 0x84
-
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-#endif /* _HT_NB_HARDWARE_FAM10_H_ */
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htNotify.c b/src/vendorcode/amd/agesa/Proc/HT/htNotify.c
deleted file mode 100644
index d64bada..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htNotify.c
+++ /dev/null
@@ -1,670 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Code for detailed notification of events and status.
- *
- * Routines for logging and reporting details and summary status.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35978 $ @e \$Date: 2010-08-07 02:18:50 +0800 (Sat, 07 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "htFeat.h"
-#include "htNotify.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_HT_HTNOTIFY_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Log an event.
- *
- * Errors, events, faults, warnings, and useful information are provided by
- * calling this routine as often as necessary, once for each notification.
- * @sa AGESA.h for class, and event definitions.
- * @sa htNotify.h for event data definitions.
- *
- * @param[in] EvtClass What level event is this
- * @param[in] Event A unique ID of this event
- * @param[in] EventData useful data associated with the event.
- * @param[in] State the log area and remaining free space
- */
-VOID
-STATIC
-setEventNotify (
- IN AGESA_STATUS EvtClass,
- IN UINT32 Event,
- IN CONST UINT8 *EventData,
- IN STATE_DATA *State
- )
-{
- UINT32 DataParam[NUMBER_OF_EVENT_DATA_PARAMS];
-
- // Remember the highest event class notified, that becomes our return code.
- if (State->MaxEventClass < EvtClass) {
- State->MaxEventClass = EvtClass;
- }
-
- // Copy the event data to the log data
- LibAmdMemCopy (
- DataParam,
- (VOID *)EventData,
- (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
- State->ConfigHandle
- );
-
- // Log the event
- PutEventLog (
- EvtClass,
- Event,
- DataParam[0],
- DataParam[1],
- DataParam[2],
- DataParam[3],
- State->ConfigHandle
- );
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * For event HT_EVENT_HW_SYNCFLOOD
- *
- * @param[in] Node The node on which the fault is reported
- * @param[in] Link The link from that node
- * @param[in] State our State
- *
- */
-VOID
-NotifyAlertHwSyncFlood (
- IN UINT8 Node,
- IN UINT8 Link,
- IN STATE_DATA *State
- )
-{
- HT_EVENT_DATA_HW_SYNCFLOOD Evt;
- // Zero out the event data
- LibAmdMemFill (
- &Evt,
- 0,
- (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
- State->ConfigHandle
- );
-
- IDS_HDT_CONSOLE (HT_TRACE, "Sync Flood on Node %d Link %d.\n", Node, Link);
- Evt.Node = Node;
- Evt.Link = Link;
- setEventNotify (AGESA_ALERT,
- HT_EVENT_HW_SYNCFLOOD,
- (UINT8 *)&Evt, State);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * For event HT_EVENT_HW_HTCRC
- *
- * @param[in] Node The node on which the error is reported
- * @param[in] Link The link from that node
- * @param[in] LaneMask The lanes which had CRC
- * @param[in] State our State
- *
- */
-VOID
-NotifyAlertHwHtCrc (
- IN UINT8 Node,
- IN UINT8 Link,
- IN UINT8 LaneMask,
- IN STATE_DATA *State
- )
-{
- HT_EVENT_DATA_HW_HT_CRC Evt;
- // Zero out the event data
- LibAmdMemFill (
- &Evt,
- 0,
- (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
- State->ConfigHandle
- );
-
- IDS_HDT_CONSOLE (HT_TRACE, "CRC Error on Node %d Link %d lanes %x.\n", Node, Link, LaneMask);
- Evt.Node = Node;
- Evt.Link = Link;
- Evt.LaneMask = LaneMask;
- setEventNotify (AGESA_ALERT,
- HT_EVENT_HW_HTCRC,
- (UINT8 *)&Evt, State);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * For event HT_EVENT_NCOH_BUS_MAX_EXCEED
- *
- * @param[in] Node The node on which the chain is located
- * @param[in] Link The link from that node
- * @param[in] Bus The bus number to assign
- * @param[in] State our State
- *
- */
-VOID
-NotifyErrorNcohBusMaxExceed (
- IN UINT8 Node,
- IN UINT8 Link,
- IN UINT8 Bus,
- IN STATE_DATA *State
- )
-{
- HT_EVENT_DATA_NCOH_BUS_MAX_EXCEED Evt;
- // Zero out the event data
- LibAmdMemFill (
- &Evt,
- 0,
- (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
- State->ConfigHandle
- );
-
- Evt.Node = Node;
- Evt.Link = Link;
- Evt.Bus = Bus;
- setEventNotify (AGESA_ERROR,
- HT_EVENT_NCOH_BUS_MAX_EXCEED,
- (UINT8 *)&Evt, State);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * For event HT_EVENT_NCOH_CFG_MAP_EXCEED
- *
- * @param[in] Node The node on which the chain is located
- * @param[in] Link The link from that node
- * @param[in] State our State
- *
- */
-VOID
-NotifyErrorNcohCfgMapExceed (
- IN UINT8 Node,
- IN UINT8 Link,
- IN STATE_DATA *State
- )
-{
- HT_EVENT_DATA_NCOH_CFG_MAP_EXCEED Evt;
- // Zero out the event data
- LibAmdMemFill (
- &Evt,
- 0,
- (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
- State->ConfigHandle
- );
-
- Evt.Node = Node;
- Evt.Link = Link;
- setEventNotify (AGESA_ERROR,
- HT_EVENT_NCOH_CFG_MAP_EXCEED,
- (UINT8 *)&Evt, State);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * For event HT_EVENT_NCOH_BUID_EXCEED
- *
- * @param[in] Node The node on which the chain is located
- * @param[in] Link The link from that node
- * @param[in] Depth Position on chain
- * @param[in] Id The Id which was attempted to assigned
- * @param[in] Units The number of units in this device
- * @param[in] State our State
- *
- */
-VOID
-NotifyErrorNcohBuidExceed (
- IN UINT8 Node,
- IN UINT8 Link,
- IN UINT8 Depth,
- IN UINT8 Id,
- IN UINT8 Units,
- IN STATE_DATA *State
- )
-{
- HT_EVENT_DATA_NCOH_BUID_EXCEED Evt;
- // Zero out the event data
- LibAmdMemFill (
- &Evt,
- 0,
- (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
- State->ConfigHandle
- );
-
- Evt.Node = Node;
- Evt.Link = Link;
- Evt.Depth = Depth;
- Evt.CurrentBuid = Id;
- Evt.UnitCount = Units;
- setEventNotify (AGESA_ERROR,
- HT_EVENT_NCOH_BUID_EXCEED,
- (UINT8 *)&Evt, State);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * For event HT_EVENT_NCOH_DEVICE_FAILED
- *
- * @param[in] Node The node on which the chain is located
- * @param[in] Link The link from that node
- * @param[in] Depth Position on chain
- * @param[in] Id The Id which was attempted to assigned
- * @param[in] State our State
- *
- */
-VOID
-NotifyErrorNcohDeviceFailed (
- IN UINT8 Node,
- IN UINT8 Link,
- IN UINT8 Depth,
- IN UINT8 Id,
- IN STATE_DATA *State
- )
-{
- HT_EVENT_DATA_NCOH_DEVICE_FAILED Evt;
- // Zero out the event data
- LibAmdMemFill (
- &Evt,
- 0,
- (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
- State->ConfigHandle
- );
-
- Evt.Node = Node;
- Evt.Link = Link;
- Evt.Depth = Depth;
- Evt.AttemptedBuid = Id;
- setEventNotify (AGESA_ERROR,
- HT_EVENT_NCOH_DEVICE_FAILED,
- (UINT8 *)&Evt, State);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * For event HT_EVENT_NCOH_AUTO_DEPTH
- *
- * @param[in] Node The node on which the chain is located
- * @param[in] Link The link from that node
- * @param[in] Depth Position on chain
- * @param[in] State our State
- *
- */
-VOID
-NotifyInfoNcohAutoDepth (
- IN UINT8 Node,
- IN UINT8 Link,
- IN UINT8 Depth,
- IN STATE_DATA *State
- )
-{
- HT_EVENT_DATA_NCOH_AUTO_DEPTH Evt;
- // Zero out the event data
- LibAmdMemFill (
- &Evt,
- 0,
- (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
- State->ConfigHandle
- );
-
- Evt.Node = Node;
- Evt.Link = Link;
- Evt.Depth = Depth;
- setEventNotify (AGESA_SUCCESS,
- HT_EVENT_NCOH_AUTO_DEPTH,
- (UINT8 *)&Evt, State);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * For event HT_EVENT_OPT_REQUIRED_CAP_RETRY
- *
- * @param[in] Node The node on which the chain is located
- * @param[in] Link The link from that node
- * @param[in] Depth Position on chain
- * @param[in] State our State
- *
- */
-VOID
-NotifyWarningOptRequiredCapRetry (
- IN UINT8 Node,
- IN UINT8 Link,
- IN UINT8 Depth,
- IN STATE_DATA *State
- )
-{
- HT_EVENT_DATA_OPT_REQUIRED_CAP Evt;
- // Zero out the event data
- LibAmdMemFill (
- &Evt,
- 0,
- (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
- State->ConfigHandle
- );
-
- Evt.Node = Node;
- Evt.Link = Link;
- Evt.Depth = Depth;
- setEventNotify (AGESA_WARNING,
- HT_EVENT_OPT_REQUIRED_CAP_RETRY,
- (UINT8 *)&Evt, State);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * For event HT_EVENT_OPT_REQUIRED_CAP_GEN3
- *
- * @param[in] Node The node on which the chain is located
- * @param[in] Link The link from that node
- * @param[in] Depth Position on chain
- * @param[in] State our State
- *
- */
-VOID
-NotifyWarningOptRequiredCapGen3 (
- IN UINT8 Node,
- IN UINT8 Link,
- IN UINT8 Depth,
- IN STATE_DATA *State
- )
-{
- HT_EVENT_DATA_OPT_REQUIRED_CAP Evt;
- // Zero out the event data
- LibAmdMemFill (
- &Evt,
- 0,
- (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
- State->ConfigHandle
- );
-
- Evt.Node = Node;
- Evt.Link = Link;
- Evt.Depth = Depth;
- setEventNotify (AGESA_WARNING,
- HT_EVENT_OPT_REQUIRED_CAP_GEN3,
- (UINT8 *)&Evt, State);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * For event HT_EVENT_OPT_UNUSED_LINKS
- *
- * @param[in] NodeA One of the nodes connected
- * @param[in] NodeB The other connected node
- * @param[in] LinkA its unusable link
- * @param[in] LinkB its unusable link
- * @param[in] State our State
- *
- */
-VOID
-NotifyWarningOptUnusedLinks (
- IN UINT32 NodeA,
- IN UINT32 LinkA,
- IN UINT32 NodeB,
- IN UINT32 LinkB,
- IN STATE_DATA *State
- )
-{
- HT_EVENT_DATA_OPT_UNUSED_LINKS Evt;
- // Zero out the event data
- LibAmdMemFill (
- &Evt,
- 0,
- (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
- State->ConfigHandle
- );
-
- Evt.NodeA = NodeA;
- Evt.LinkA = LinkA;
- Evt.NodeB = NodeB;
- Evt.LinkB = LinkB;
- setEventNotify (AGESA_WARNING,
- HT_EVENT_OPT_UNUSED_LINKS,
- (UINT8 *)&Evt, State);
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * For event HT_EVENT_OPT_LINK_PAIR_EXCEED
- *
- * @param[in] NodeA One of the nodes connected
- * @param[in] NodeB The other connected node
- * @param[in] MasterLink its unusable Masterlink
- * @param[in] AltLink its unusable Alternate link
- * @param[in] State our State
- *
- */
-VOID
-NotifyWarningOptLinkPairExceed (
- IN UINT32 NodeA,
- IN UINT32 NodeB,
- IN UINT32 MasterLink,
- IN UINT32 AltLink,
- IN STATE_DATA *State
- )
-{
- HT_EVENT_DATA_OPT_LINK_PAIR_EXCEED Evt;
- // Zero out the event data
- LibAmdMemFill (
- &Evt,
- 0,
- (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
- State->ConfigHandle
- );
-
- Evt.NodeA = NodeA;
- Evt.MasterLink = MasterLink;
- Evt.NodeB = NodeB;
- Evt.AltLink = AltLink;
- setEventNotify (AGESA_WARNING,
- HT_EVENT_OPT_LINK_PAIR_EXCEED,
- (UINT8 *)&Evt, State);
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * For event HT_EVENT_COH_NO_TOPOLOGY
- *
- * @param[in] Nodes The total number of nodes found so far
- * @param[in] State our State
- *
- */
-VOID
-NotifyErrorCohNoTopology (
- IN UINT8 Nodes,
- IN STATE_DATA *State
- )
-{
- HT_EVENT_DATA_COH_NO_TOPOLOGY Evt;
- // Zero out the event data
- LibAmdMemFill (
- &Evt,
- 0,
- (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
- State->ConfigHandle
- );
-
- IDS_HDT_CONSOLE (HT_TRACE, "No Topology Matched system with %d nodes found.\n", Nodes);
- Evt.TotalNodes = Nodes;
- setEventNotify (AGESA_ERROR,
- HT_EVENT_COH_NO_TOPOLOGY,
- (UINT8 *)&Evt, State);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * For event HT_EVENT_COH_PROCESSOR_TYPE_MIX
- *
- * @param[in] Node The node from which a new node was discovered
- * @param[in] Link The link from that node
- * @param[in] Nodes The total number of nodes found so far
- * @param[in] State our State
- *
- */
-VOID
-NotifyFatalCohProcessorTypeMix (
- IN UINT8 Node,
- IN UINT8 Link,
- IN UINT8 Nodes,
- IN STATE_DATA *State
- )
-{
- HT_EVENT_DATA_COH_PROCESSOR_TYPE_MIX Evt;
- // Zero out the event data
- LibAmdMemFill (
- &Evt,
- 0,
- (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
- State->ConfigHandle
- );
-
- IDS_HDT_CONSOLE (HT_TRACE, "Illegal Processor Type Mix.\n");
- Evt.Node = Node;
- Evt.Link = Link;
- Evt.TotalNodes = Nodes;
- setEventNotify (AGESA_CRITICAL,
- HT_EVENT_COH_PROCESSOR_TYPE_MIX,
- (UINT8 *)&Evt, State);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * For event HT_EVENT_COH_NODE_DISCOVERED
- *
- * @param[in] Node Node from which a new node was discovered
- * @param[in] Link The link to that new node
- * @param[in] NewNode The new node's id
- * @param[in] TempRoute Temporarily, during discovery, the new node is accessed at this id.
- * @param[in] State our State
- *
- */
-VOID
-NotifyInfoCohNodeDiscovered (
- IN UINT8 Node,
- IN UINT8 Link,
- IN UINT8 NewNode,
- IN UINT8 TempRoute,
- IN STATE_DATA *State
- )
-{
- HT_EVENT_DATA_COH_NODE_DISCOVERED Evt;
- // Zero out the event data
- LibAmdMemFill (
- &Evt,
- 0,
- (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
- State->ConfigHandle
- );
-
- IDS_HDT_CONSOLE (HT_TRACE, "Adding Node %d.\n", NewNode);
- Evt.Node = Node;
- Evt.Link = Link;
- Evt.NewNode = NewNode;
- Evt.TempRoute = TempRoute;
- setEventNotify (AGESA_SUCCESS,
- HT_EVENT_COH_NODE_DISCOVERED,
- (UINT8 *)&Evt, State);
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * For event HT_EVENT_COH_MPCAP_MISMATCH
- *
- * @param[in] Node The node from which a new node was discovered
- * @param[in] Link The link from that node
- * @param[in] Cap The aggregate system MP Capability
- * @param[in] Nodes The total number of nodes found so far
- * @param[in] State our State
- *
- */
-VOID
-NotifyFatalCohMpCapMismatch (
- IN UINT8 Node,
- IN UINT8 Link,
- IN UINT8 Cap,
- IN UINT8 Nodes,
- IN STATE_DATA *State
- )
-{
- HT_EVENT_DATA_COH_MP_CAP_MISMATCH Evt;
- // Zero out the event data
- LibAmdMemFill (
- &Evt,
- 0,
- (sizeof(UINT32) * NUMBER_OF_EVENT_DATA_PARAMS),
- State->ConfigHandle
- );
-
- IDS_HDT_CONSOLE (HT_TRACE, "Mp Capability Mismatch.\n");
- Evt.Node = Node;
- Evt.Link = Link;
- Evt.SysMpCap = Cap;
- Evt.TotalNodes = Nodes;
- setEventNotify (AGESA_CRITICAL,
- HT_EVENT_COH_MPCAP_MISMATCH,
- (UINT8 *)&Evt, State);
-}
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htNotify.h b/src/vendorcode/amd/agesa/Proc/HT/htNotify.h
deleted file mode 100644
index f7f846a..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htNotify.h
+++ /dev/null
@@ -1,298 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * HT Notify interface.
- *
- * This file provides internal interface to event and status
- * notification.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _HT_NOTIFY_H_
-#define _HT_NOTIFY_H_
-
-/*----------------------------------------------------------------------------------------*/
-/* Event specific event data definitions.
- * All structures must be 4 UINT32's in size, no more, no less.
- */
-
-/// For event ::HT_EVENT_HW_SYNCFLOOD
-typedef struct {
- UINT32 Node; ///< The Node on which observed
- UINT32 Link; ///< The Link on that Node which reported synch flood
- UINT32 Reserved1; ///< Reserved.
- UINT32 Reserved2; ///< Reserved.
-} HT_EVENT_DATA_HW_SYNCFLOOD;
-
-/// For event ::HT_EVENT_HW_HTCRC
-typedef struct {
- UINT32 Node; ///< The Node on which event is observed
- UINT32 Link; ///< The Link on that Node which reported CRC error
- UINT32 LaneMask; ///< The CRC lane mask for the Link
- UINT32 Reserved1; ///< Reserved.
-} HT_EVENT_DATA_HW_HT_CRC;
-
-/// For event ::HT_EVENT_NCOH_BUS_MAX_EXCEED
-typedef struct {
- UINT32 Node; ///< the Node with this non-coherent chain
- UINT32 Link; ///< the Link on that Node to this chain
- UINT32 Bus; ///< the current bus number
- UINT32 Reserved1; ///< Reserved.
-} HT_EVENT_DATA_NCOH_BUS_MAX_EXCEED;
-
-/// For event ::HT_EVENT_NCOH_CFG_MAP_EXCEED
-typedef struct {
- UINT32 Node; ///< the Node with this non-coherent chain
- UINT32 Link; ///< the Link on that Node to this chain
- UINT32 Reserved1; ///< Reserved.
- UINT32 Reserved2; ///< Reserved.
-} HT_EVENT_DATA_NCOH_CFG_MAP_EXCEED;
-
-/// For event ::HT_EVENT_NCOH_BUID_EXCEED
-typedef struct {
- UINT32 Node; ///< the Node with this non-coherent chain
- UINT32 Link; ///< the Link on that Node to this chain
- UINT32 Depth; ///< the position on the chain, zero is CPU host
- UINT16 CurrentBuid; ///< the current available BUID
- UINT16 UnitCount; ///< the number of ids which would be consumed by this device
-} HT_EVENT_DATA_NCOH_BUID_EXCEED;
-
-/// For event ::HT_EVENT_NCOH_DEVICE_FAILED
-typedef struct {
- UINT32 Node; ///< the Node with this non-coherent chain
- UINT32 Link; ///< the Link on that Node to this chain
- UINT32 Depth; ///< the position on the chain, zero is CPU host
- UINT32 AttemptedBuid; ///< the BUID we tried to assign to that device
-} HT_EVENT_DATA_NCOH_DEVICE_FAILED;
-
-/// For event ::HT_EVENT_NCOH_AUTO_DEPTH
-typedef struct {
- UINT32 Node; ///< the Node with this non-coherent chain
- UINT32 Link; ///< the Link on that Node to this chain
- UINT32 Depth; ///< the position on the chain of the last device, zero is CPU host
- UINT32 Reserved1; ///< Reserved.
-} HT_EVENT_DATA_NCOH_AUTO_DEPTH;
-
-/// For event ::HT_EVENT_OPT_REQUIRED_CAP_RETRY,
-/// ::HT_EVENT_OPT_REQUIRED_CAP_GEN3.
-typedef struct {
- UINT32 Node; ///< the Node with this non-coherent chain
- UINT32 Link; ///< the Link on that Node to this chain
- UINT32 Depth; ///< the position on the chain, zero is CPU host
- UINT32 Reserved1; ///< Reserved.
-} HT_EVENT_DATA_OPT_REQUIRED_CAP;
-
-/// For event ::HT_EVENT_OPT_UNUSED_LINKS
-typedef struct {
- UINT32 NodeA; ///< One of the nodes connected
- UINT32 LinkA; ///< its unusable link
- UINT32 NodeB; ///< The other connected node
- UINT32 LinkB; ///< its unusable link
-} HT_EVENT_DATA_OPT_UNUSED_LINKS;
-
-/// For event ::HT_EVENT_OPT_LINK_PAIR_EXCEED
-typedef struct {
- UINT32 NodeA; ///< One of the nodes connected
- UINT32 NodeB; ///< The other connected node
- UINT32 MasterLink; ///< NodeA's unusable Master link
- UINT32 AltLink; ///< NodeA's unusable Alternatelink
-} HT_EVENT_DATA_OPT_LINK_PAIR_EXCEED;
-
-/// For event ::HT_EVENT_COH_NO_TOPOLOGY.
-/// There is no routing for this system's topology.
-typedef struct {
- UINT32 TotalNodes; ///< the number of Nodes in the unmatched topology
- UINT32 Reserved1; ///< Reserved.
- UINT32 Reserved2; ///< Reserved.
- UINT32 Reserved3; ///< Reserved.
-} HT_EVENT_DATA_COH_NO_TOPOLOGY;
-
-/// For event ::HT_EVENT_COH_PROCESSOR_TYPE_MIX
-typedef struct {
- UINT32 Node; ///< the Node from which the incompatible family was found
- UINT32 Link; ///< the Link to the incompatible Node
- UINT32 TotalNodes; ///< the number of Nodes found at that point
- UINT32 Reserved1; ///< Reserved.
-} HT_EVENT_DATA_COH_PROCESSOR_TYPE_MIX;
-
-/// For event ::HT_EVENT_COH_NODE_DISCOVERED
-typedef struct {
- UINT32 Node; ///< the Node from which the new Node was found
- UINT32 Link; ///< the Link to the new Node
- UINT32 NewNode; ///< the Node id of the newly discovered Node
- UINT32 TempRoute; ///< the new Node is temporarily at this id
-} HT_EVENT_DATA_COH_NODE_DISCOVERED;
-
-/// For event ::HT_EVENT_COH_MPCAP_MISMATCH
-typedef struct {
- UINT32 Node; ///< the Node from which condition was observed
- UINT32 Link; ///< the Link on the current Node
- UINT32 SysMpCap; ///< the current aggregate system capability (the minimum found so far)
- UINT32 TotalNodes; ///< the number of Nodes found, before this was observed
-} HT_EVENT_DATA_COH_MP_CAP_MISMATCH;
-
-/*----------------------------------------------------------------------------------------*/
-/* Event specific Notify functions.
- */
-
-VOID
-NotifyAlertHwSyncFlood (
- IN UINT8 Node,
- IN UINT8 Link,
- IN STATE_DATA *State
- );
-
-VOID
-NotifyAlertHwHtCrc (
- IN UINT8 Node,
- IN UINT8 Link,
- IN UINT8 LaneMask,
- IN STATE_DATA *State
- );
-
-VOID
-NotifyErrorNcohBusMaxExceed (
- IN UINT8 Node,
- IN UINT8 Link,
- IN UINT8 Bus,
- IN STATE_DATA *State
- );
-
-VOID
-NotifyErrorNcohCfgMapExceed (
- IN UINT8 Node,
- IN UINT8 Link,
- IN STATE_DATA *State
- );
-
-VOID
-NotifyErrorNcohBuidExceed (
- IN UINT8 Node,
- IN UINT8 Link,
- IN UINT8 Depth,
- IN UINT8 Id,
- IN UINT8 Units,
- IN STATE_DATA *State
- );
-
-VOID
-NotifyErrorNcohDeviceFailed (
- IN UINT8 Node,
- IN UINT8 Link,
- IN UINT8 Depth,
- IN UINT8 Id,
- IN STATE_DATA *State
- );
-
-VOID
-NotifyInfoNcohAutoDepth (
- IN UINT8 Node,
- IN UINT8 Link,
- IN UINT8 Depth,
- IN STATE_DATA *State
- );
-
-VOID
-NotifyWarningOptRequiredCapRetry (
- IN UINT8 Node,
- IN UINT8 Link,
- IN UINT8 Depth,
- IN STATE_DATA *State
- );
-
-VOID
-NotifyWarningOptRequiredCapGen3 (
- IN UINT8 Node,
- IN UINT8 Link,
- IN UINT8 Depth,
- IN STATE_DATA *State
- );
-
-VOID
-NotifyWarningOptUnusedLinks (
- IN UINT32 NodeA,
- IN UINT32 LinkA,
- IN UINT32 NodeB,
- IN UINT32 LinkB,
- IN STATE_DATA *State
- );
-
-VOID
-NotifyWarningOptLinkPairExceed (
- IN UINT32 NodeA,
- IN UINT32 NodeB,
- IN UINT32 MasterLink,
- IN UINT32 AltLink,
- IN STATE_DATA *State
- );
-
-VOID
-NotifyErrorCohNoTopology (
- IN UINT8 Nodes,
- IN STATE_DATA *State
- );
-
-VOID
-NotifyFatalCohProcessorTypeMix (
- IN UINT8 Node,
- IN UINT8 Link,
- IN UINT8 Nodes,
- IN STATE_DATA *State
- );
-
-VOID
-NotifyInfoCohNodeDiscovered (
- IN UINT8 Node,
- IN UINT8 Link,
- IN UINT8 NewNode,
- IN UINT8 TempRoute,
- IN STATE_DATA *State
- );
-
-VOID
-NotifyFatalCohMpCapMismatch (
- IN UINT8 Node,
- IN UINT8 Link,
- IN UINT8 Cap,
- IN UINT8 Nodes,
- IN STATE_DATA *State
- );
-
-#endif /* _HT_NOTIFY_H_ */
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htPage.h b/src/vendorcode/amd/agesa/Proc/HT/htPage.h
deleted file mode 100644
index 6221418..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htPage.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Create outline and references for HyperTransport Component mainpage documentation.
- *
- * Design guides, maintenance guides, and general documentation, are
- * collected using this file onto the documentation mainpage.
- * This file contains doxygen comment blocks, only.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Documentation
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/**
- * @page htmain HyperTransport Component Documentation
- *
- * Additional documentation for the HyperTransport component consists of
- *
- * - Member Cross References
- * - @subpage instanceshtnb "HT Northbridge Method Instances"
- * - Maintenance Guides:
- * - @subpage htimplintf "HT Internal Interface Implementation Guide"
- * - @subpage htimplfeat "HT Feature Implementation Guide"
- * - @subpage htimplnb "HT Northbridge Implementation Guide"
- * - add here >>>
- * - Design Guides:
- * - @subpage htgraphdesign "Graph Support Design"
- * - @subpage physicalsockethowto "How to Create a Physical System Socket Map"
- * - add here >>>
- *
- */
diff --git a/src/vendorcode/amd/agesa/Proc/HT/htTopologies.h b/src/vendorcode/amd/agesa/Proc/HT/htTopologies.h
deleted file mode 100644
index 679b315..0000000
--- a/src/vendorcode/amd/agesa/Proc/HT/htTopologies.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Provide selection of available topologies.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _HT_TOPOLOGIES_H_
-#define _HT_TOPOLOGIES_H_
-
-extern CONST UINT8 ROMDATA amdHtTopologySingleNode[];
-extern CONST UINT8 ROMDATA amdHtTopologyDualNode[];
-extern CONST UINT8 ROMDATA amdHtTopologyThreeLine[];
-extern CONST UINT8 ROMDATA amdHtTopologyTriangle[];
-extern CONST UINT8 ROMDATA amdHtTopologyFourLine[];
-extern CONST UINT8 ROMDATA amdHtTopologyFourStar[];
-extern CONST UINT8 ROMDATA amdHtTopologyFourDegenerate[];
-extern CONST UINT8 ROMDATA amdHtTopologyFourSquare[];
-extern CONST UINT8 ROMDATA amdHtTopologyFourKite[];
-extern CONST UINT8 ROMDATA amdHtTopologyFourFully[];
-extern CONST UINT8 ROMDATA amdHtTopologyFiveFully[];
-extern CONST UINT8 ROMDATA amdHtTopologyFiveTwistedLadder[];
-extern CONST UINT8 ROMDATA amdHtTopologySixFully[];
-extern CONST UINT8 ROMDATA amdHtTopologySixDoubloonLower[];
-extern CONST UINT8 ROMDATA amdHtTopologySixDoubloonUpper[];
-extern CONST UINT8 ROMDATA amdHtTopologySixTwistedLadder[];
-extern CONST UINT8 ROMDATA amdHtTopologySevenFully[];
-extern CONST UINT8 ROMDATA amdHtTopologySevenTwistedLadder[];
-extern CONST UINT8 ROMDATA amdHtTopologyEightFully[];
-extern CONST UINT8 ROMDATA amdHtTopologyEightDoubloon[];
-extern CONST UINT8 ROMDATA amdHtTopologyEightTwistedLadder[];
-extern CONST UINT8 ROMDATA amdHtTopologyEightStraightLadder[];
-extern CONST UINT8 ROMDATA amdHtTopologySixTwinTriangles[];
-extern CONST UINT8 ROMDATA amdHtTopologyEightTwinFullyFourWays[];
-
-#endif // _HT_TOPOLOGIES_H_
diff --git a/src/vendorcode/amd/agesa/Proc/IDS/IdsLib.h b/src/vendorcode/amd/agesa/Proc/IDS/IdsLib.h
deleted file mode 100644
index fe90b67..0000000
--- a/src/vendorcode/amd/agesa/Proc/IDS/IdsLib.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD IDS Routines
- *
- * Contains AMD AGESA Integrated Debug Macros
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: IDS
- * @e \$Revision: 35777 $ @e \$Date: 2010-07-30 17:41:05 +0800 (Fri, 30 Jul 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _IDS_LIB_H_
-#define _IDS_LIB_H_
-#include "OptionsIds.h"
-#include "cpuRegisters.h"
-#include "cpuApicUtilities.h"
-#include "Table.h"
-///Specific time stamp performance analysis which need ids control support
-#if IDSOPT_CONTROL_ENABLED == TRUE
- #define PERF_SPEC_TS_ANALYSE(StdHeader)
-#else
- #define PERF_SPEC_TS_ANALYSE(StdHeader)
-#endif
-
-
-#define IDS_NV_READ_SKIP(NvValue, Nvid, IdsNvPtr, StdHeader)
-#define IDS_GET_MASK32(HighBit, LowBit)
-
-#define IDS_MAX_MEM_ITEMS 80 ///< Maximum IDS Mem Table Size in Heap.
-
-
-// TYPEDEFS, STRUCTURES, ENUMS
-//
-
-
-///Structure define for MSR register
-typedef struct _REG_MSR {
- UINT32 msraddr; ///< Address of MSR Register
- UINT32 andmaskhi; ///< And Mask Bit63:32
- UINT32 andmasklo; ///< And Mask Bit31:0
- UINT32 ormaskhi; ///< Or Mask Bit63:32
- UINT32 ormasklo; ///< Or Mask Bit31:0
-} REG_MSR;
-
-typedef AGESA_STATUS (*PF_IDS_AP_TASK) (VOID *AptaskPara, AMD_CONFIG_PARAMS *StdHeader);
-
-///Structure define for IdsAgesaRunFcnOnApLate
-typedef struct _IDSAPLATETASK {
- PF_IDS_AP_TASK ApTask; ///< Point function which AP need to do
- VOID *ApTaskPara; ///< Point to Ap function parameter1
-} IDSAPLATETASK;
-
-/// Data Structure defining IDS Data in HEAP
-/// This data structure contains information that is stored in HEAP and will be
-/// used in IDS backend function. It includes the size of memory to be allocated
-/// for IDS, the relative offsets of the mapping table IDS setup options, the GRA
-/// table and the register table to override mem setting. It also includes a base
-/// address of IDS override image which will be used to control the behavior of
-/// AGESA testpoint if this feature is enabled.
-typedef struct {
- BOOLEAN IgnoreIdsDefault; ///< Control ignore Default value of IDS NV list specified by IdsNvTableOffset
- UINT64 IdsImageBase; ///< IDS Override Image Base Address
- UINT32 IdsHeapMemSize; ///< IDS Total Memory Size in Heap
- UINT32 IdsNvTableOffset; ///< Offset of IDS NV Table
- UINT32 IdsMemTableOffset; ///< Offset of IDS Mem Table
- UINT32 IdsExtendOffset; ///< Offset of Ids extend heap
-} IDS_CONTROL_STRUCT;
-
-
-/// Data Structure of Parameters for TestPoint_TSC.
-typedef struct {
- UINT8 TestPoint; ///< The TestPoint of TestPoint_TSC
- UINT64 StartTsc; ///< The StartTimer of TestPoint_TSC
-} TestPoint_TSC;
-
-/// Data Structure of Parameters for TP_Perf_STRUCT.
-typedef struct {
- UINT8 Index; ///< The Index of TP_Perf_STRUCT
- UINT32 TscInMhz; ///< Tsc counter in 1 mhz
- TestPoint_TSC TP[EndAgesaTps]; ///< The TP of TP_Perf_STRUCT
-} TP_Perf_STRUCT;
-
-
-///Bus speed Optimization
-typedef enum {
- IDS_POWER_POLICY_PERFORMANCE = 0, ///< Performance
- IDS_POWER_POLICY_POWER = 1, ///< Power
- IDS_POWER_POLICY_AUTO = 3, ///< Auto
-} IDS_NV_AMDBUSSPEEDOPTIMIZATION;
-
-#define IDS_CPB_BOOST_DIS_IGNORE 0xFFFFFFFF
-
-#endif //_IDS_LIB_H_
-
diff --git a/src/vendorcode/amd/agesa/Proc/IDS/IdsPage.h b/src/vendorcode/amd/agesa/Proc/IDS/IdsPage.h
deleted file mode 100644
index 3c3aa5e..0000000
--- a/src/vendorcode/amd/agesa/Proc/IDS/IdsPage.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Create outline and references for Integrated Debug Support Component mainpage documentation.
- *
- * Design guides, maintenance guides, and general documentation, are
- * collected using this file onto the documentation mainpage.
- * This file contains doxygen comment blocks, only.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Documentation
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/**
- * @page idsmain Integrated Debug Support Component Documentation
- *
- * Additional documentation for the Integrated Debug Support component consists of
- *
- * - Maintenance Guides:
- * - add here >>>
- * - Design Guides:
- * - add here >>>
- *
- */
diff --git a/src/vendorcode/amd/agesa/Proc/IDS/OptionsIds.h b/src/vendorcode/amd/agesa/Proc/IDS/OptionsIds.h
deleted file mode 100644
index 256028b..0000000
--- a/src/vendorcode/amd/agesa/Proc/IDS/OptionsIds.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * IDS Option File
- *
- * This file is used to switch on/off IDS features.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Core
- * @e \$Revision: 38300 $ @e \$Date: 2010-09-21 22:55:23 +0800 (Tue, 21 Sep 2010) $
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _OPTION_IDS_H_
-#define _OPTION_IDS_H_
-
-/**
- *
- * This file generates the defaults tables for the Integrated Debug Support
- * Module. The documented build options are imported from a user controlled
- * file for processing. The build options for the Integrated Debug Support
- * Module are listed below:
- *
- * IDSOPT_IDS_ENABLED
- * IDSOPT_ERROR_TRAP_ENABLED
- * IDSOPT_CONTROL_ENABLED
- * IDSOPT_TRACING_ENABLED
- * IDSOPT_TRACE_BLD_CFG
- * IDSOPT_PERF_ANALYSIS
- * IDSOPT_ASSERT_ENABLED
- * IDS_DEBUG_PORT
- * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
- * IDSOPT_DEBUG_CODE_ENABLED
- * IDSOPT_C_OPTIMIZATION_DISABLED
- *
- **/
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ardk/C32/marc32_3.c b/src/vendorcode/amd/agesa/Proc/Mem/Ardk/C32/marc32_3.c
deleted file mode 100644
index 7e20815..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ardk/C32/marc32_3.c
+++ /dev/null
@@ -1,594 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * marc32_3.c
- *
- * Memory Controller, registered dimms
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ardk)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/* This file contains routine that add platform specific support AM3 */
-
-
-#include "AGESA.h"
-#include "ma.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mu.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_ARDK_C32_MARC32_3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-STATIC CONST UINT8 ROMDATA C32RDdr3CLKDis[] = {0xFF, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00};
-
-// Even chip select maps to M[B,A]_CKE[0]
-// Odd chip select maps to M[B,A]_CKE[1]
-STATIC CONST UINT8 ROMDATA C32RDdr3CKETri[] = {0x55, 0xAA};
-
-// 2 dimms per channel
-// Dimm 0: BP_MEMODTx[2,0]
-// Dimm 1: BP_MEMODTx[3,1]
-STATIC CONST UINT8 ROMDATA C32RDdr3ODTTri2D[] = {0x03, 0x0C, 0x32, 0xC8};
-// 3 dimms per channel
-// Dimm 0: BP_MEMODTx[0]
-// Dimm 1: BP_MEMODTx[3,1]
-// Dimm 2: BP_MEMODTx[2]
-STATIC CONST UINT8 ROMDATA C32RDdr3ODTTri3D[] = {0x03, 0x0C, 0x30, 0xC8};
-// 4 dimms per channel
-// Dimm 0: BP_MEMODTx[0]
-// Dimm 1: BP_MEMODTx[1]
-// Dimm 2: BP_MEMODTx[2]
-// Dimm 3: BP_MEMODTx[3]
-STATIC CONST UINT8 ROMDATA C32RDdr3ODTTri4D[] = {0x03, 0x0C, 0x30, 0xC0};
-
-// BIOS must not tri-state chip select pin corresponding to the second chip
-// select of a single rank registered dimm
-STATIC CONST UINT8 ROMDATA C32RDdr3CSTri[] = {0x01, 0x03, 0x04, 0x0C, 0x10, 0x30, 0x40, 0xC0};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for C32 DDR3 L1 system
- *
- * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE
- * @param[in] SocketID Socket number
- * @param[in] *CurrentChannel Pointer to CH_DEF_STRUCT
- *
- * @return AGESA_SUCCESS
- * @return CurrentChannel->MemClkDisMap Points this pointer to C32 MemClkDis table
- * @return CurrentChannel->ChipSelTriMap Points this pointer to C32 CS table
- * @return CurrentChannel->CKETriMap Points this pointer to C32 ODT table
- * @return CurrentChannel->ODTTriMap Points this pointer to C32 CKE table
- * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC
- * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte
- * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel
- * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel
- * @return CurrentChannel->SlowMode Slow Mode
- *
- */
-
-AGESA_STATUS
-MemAGetPsCfgRC32_3 (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- )
-{
- //
- // Address Timings and Drive Strengths for 1 DIMM per channel or 2 Dimms per Channel
- //
- // Code searches table for matching speed, then matches the current dimm
- // population and # of dimms to current config and programs the Addr Timing and RC2/RC2
- //
- // RC2/RC8 Value - This field id dependent upon the number of Registers on the Dimm, as indicated
- // in SPD Byte 63.
- // Bits 15-12 RC2 if One register
- // Bits 11-8 RC8 if One register
- // Bits 7-4 RC2 for more than one register
- // Bits 3-0 RC8 for more than one register
- //
- // Frequency, Dimm Config ,
- // Address Timing Value(F2x[1, 0]9C_x04), RC2/RC8 Value, # Dimms to match
- //
- STATIC CONST ADV_R_PSCFG_ENTRY PSCfg2DIMMs[] = {
- {DDR667_FREQUENCY, ANY_DIMM0 + ANY_DIMM1, \
- 0x00000000, 0x4004, 2},
- {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
- 0x00000000, 0x0000, 1},
- {DDR800_FREQUENCY, QR_DIMM1, \
- 0x00000000, 0x0040, 1},
- {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
- 0x00000000, 0x4004, 2},
- {DDR800_FREQUENCY, QR_DIMM0 + ANY_DIMM1, \
- 0x00000000, 0x4004, 2},
- {DDR800_FREQUENCY, ANY_DIMM0 + QR_DIMM1, \
- 0x00000000, 0x4004, 2},
- {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
- 0x003C3C3C, 0x0000,1},
- {DDR1066_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
- 0x003C3C3C, 0x0040, 1},
- {DDR1066_FREQUENCY, ANY_DIMM0 + ANY_DIMM1, \
- 0x003A3C3A, 0x4004, 2},
- {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
- 0x003A3A3A, 0x0000, 1},
- {DDR1333_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
- 0x003A3A3A, 0x0040, 1},
- {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
- 0x00383A38, 0x4040, 2},
- };
- //
- // Address Timings and Drive Strengths for 3 DIMMs per channel
- //
- // Code searches table for matching speed, then matches the current dimm
- // population and # of dimms to current config and programs the Addr Timing and RC2/RC2
- //
- // RC2/RC8 Value - This field id dependent upon the number of Registers on the Dimm, as indicated
- // in SPD Byte 63.
- // Bits 15-12 RC2 if One register
- // Bits 11-8 RC8 if One register
- // Bits 7-4 RC2 for more than one register
- // Bits 3-0 RC8 for more than one register
- //
- // Frequency, Dimm Config ,
- // Address Timing Value(F2x[1, 0]9C_x04), RC2/RC8 Value, # Dimms to match
- //
- STATIC CONST ADV_R_PSCFG_ENTRY PSCfg3DIMMs[] = {
- {DDR667_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x00000000, 0x0000, 1},
- {DDR667_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x00000000, 0x4040, 2},
- {DDR667_FREQUENCY, QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x00000000, 0x4004, 2},
- {DDR667_FREQUENCY, SR_DIMM0 + DR_DIMM0 + ANY_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x00380038, 0x4004, 3},
- {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x00000000, 0x0000, 1},
- {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, \
- 0x00000000, 0x4040, 2},
- {DDR800_FREQUENCY, QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x00000000, 0x4004, 2},
- {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x00380038, 0x4004, 3},
- {DDR800_FREQUENCY, QR_DIMM1, \
- 0x00000000, 0x0040, 1},
- {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x003C3C3C, 0x0000, 1},
- {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, \
- 0x003A3C3A, 0x4040, 2},
- {DDR1066_FREQUENCY, SR_DIMM0 + SR_DIMM1 + SR_DIMM2, \
- 0x00373C37, 0x4040, 3},
- {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x003A3A3A, 0x0000, 1},
- {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, \
- 0x00383A38, 0x4040, 2},
- };
-
- //
- // DIMM ODT Pattern (1 or 2 DIMMs per channel)
- //
- // Dimm Config ,
- // Fn2_9C 180, Fn2_9C 181, Fn2_9C 182, Fn2_9C 183, # Dimms to match
- //
- STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg2DIMMsODT[] = {
- {SR_DIMM0, \
- 0x00000000, 0x00000000, 0x00000001, 0x00000000, 1},
- {DR_DIMM0, \
- 0x00000000, 0x00000000, 0x00000104, 0x00000000, 1},
- {QR_DIMM0, \
- 0x00000000, 0x00000000, 0x00000505, 0x00000505, 1},
- {SR_DIMM1, \
- 0x00000000, 0x00000000, 0x00020000, 0x00000000, 1},
- {DR_DIMM1, \
- 0x00000000, 0x00000000, 0x02080000, 0x00000000, 1},
- {QR_DIMM1, \
- 0x00000000, 0x00000000, 0x0A0A0000, 0x0A0A0000, 1},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
- 0x01010202, 0x00000000, 0x09030603, 0x00000000, 2},
- {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, \
- 0x01010A0A, 0x01010000, 0x01030E0B, 0x01090000, 2},
- {QR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
- 0x05050202, 0x00000202, 0x0D070203, 0x00000206, 2},
- {QR_DIMM0 + QR_DIMM1, \
- 0x05050A0A, 0x05050A0A, 0x05070A0B, 0x050D0A0E, 2}
- };
- // DIMM ODT Pattern (3 DIMMs per channel)
- //
- // Dimm Config ,
- // Fn2_9C 180, Fn2_9C 181, Fn2_9C 182, Fn2_9C 183, # Dimms to match
- //
- STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg3DIMMsODT[] = {
- {SR_DIMM2 + DR_DIMM2, \
- 0x00000000, 0x00000000, 0x00000000, 0x00000404, 1},
- {SR_DIMM0 + DR_DIMM0, \
- 0x00000000, 0x00000000, 0x00000101, 0x00000000, 1},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, \
- 0x00000404, 0x00000101, 0x00000405, 0x00000105, 2},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x05050606, 0x00000303, 0x0D070607, 0x00000307, 3},
- {QR_DIMM1, \
- 0x00000000, 0x00000000, 0x080A0000, 0x020A0000, 1},
- {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x04040000, 0x04040A0A, 0x04060000, 0x040C0A0E, 2},
- {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, \
- 0x01010A0A, 0x01010000, 0x01030A0B, 0x01090000, 2},
- {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x05050E0E, 0x05050B0B, 0x05070E0F, 0x050D0B0F, 3}
- };
- //
- // DIMM ODT Pattern (4 DIMMs per channel)
- //
- // Dimm Config ,
- // Fn2_9C 180, Fn2_9C 181, Fn2_9C 182, Fn2_9C 183, # Dimms to match
- //
- STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg4DIMMsODT[] = {
- {ANY_DIMM3, \
- 0x00000000, 0x00000000, 0x00000000, 0x08080000, 1},
- {ANY_DIMM2 + ANY_DIMM3, \
- 0x00000000, 0x04040808, 0x00000000, 0x0C0C0C0C, 2},
- {ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, \
- 0x0C0C0000, 0x06060A0A, 0x0E0E0000, 0x0E0E0E0E, 3},
- {ANY_DIMM0 + ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, \
- 0x0D0D0E0E, 0x07070B0B, 0x0F0F0F0F, 0x0F0F0F0F, 4}
- };
- //
- // DIMM Write Leveling ODT Pattern 1 or 2 Dimms Per Channel
- //
- // Dimm Config, WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm, # Dimms to match
- //
- STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg2DIMMsWlODT[] = {
- {SR_DIMM0, {0x01, 0x00, 0x00, 0x00}, 1},
- {DR_DIMM0, {0x04, 0x00, 0x00, 0x00}, 1},
- {QR_DIMM0, {0x05, 0x00, 0x00, 0x00}, 1},
- {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1},
- {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1},
- {QR_DIMM1, {0x00, 0x0A, 0x00, 0x00}, 1},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2},
- {SR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2},
- {DR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2},
- {QR_DIMM0 + SR_DIMM1, {0x03, 0x07, 0x06, 0x00}, 2},
- {QR_DIMM0 + DR_DIMM1, {0x03, 0x07, 0x06, 0x00}, 2},
- {QR_DIMM0 + QR_DIMM1, {0x0B, 0x07, 0x0E, 0x0D}, 2}
- };
- //
- // DIMM Write Leveling ODT Pattern 3 Dimms Per Channel
- //
- // Dimm Config, WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm, # Dimms to match
- //
- STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg3DIMMsWlODT[] = {
- {SR_DIMM2 + DR_DIMM2, {0x00, 0x00, 0x04, 0x00}, 1},
- {SR_DIMM0 + DR_DIMM0, {0x01, 0x02, 0x00, 0x00}, 1},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, {0x05, 0x00, 0x05, 0x00}, 2},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x07, 0x07, 0x07, 0x00}, 3},
- {QR_DIMM1, {0x00, 0x0A, 0x00, 0x0A}, 1},
- {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x00, 0x06, 0x0E, 0x0C}, 2},
- {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2},
- {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x0F, 0x07, 0x0F, 0x0D}, 3}
- };
- //
- // DIMM Write Leveling ODT Pattern 4 Dimms Per Channel
- //
- // Dimm Config, WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm, # Dimms to match
- //
- STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg4DIMMsWlODT[] = {
- {ANY_DIMM3, {0x00, 0x00, 0x00, 0x08}, 1},
- {ANY_DIMM2 + ANY_DIMM3, {0x00, 0x00, 0x0C, 0x0C}, 2},
- {ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, {0x00, 0x0E, 0x0E, 0x0E}, 3},
- {ANY_DIMM0 + ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, {0x0F, 0x0F, 0x0F, 0x0F}, 4}
- };
-
-
- UINT16 i;
- UINT16 j;
- UINT8 MaxDimmPerCH;
- UINT8 Dimms;
- UINT16 Speed;
- UINT16 DIMMRankType;
- UINT16 _DIMMRankType;
- UINT8 DimmTpMatch;
- UINT32 AddrTmgCTL;
- UINT32 DctOdcCtl;
- UINT16 RC2RC8;
- UINT32 PhyRODTCSLow;
- UINT32 PhyRODTCSHigh;
- UINT32 PhyWODTCSLow;
- UINT32 PhyWODTCSHigh;
- BOOLEAN SlowMode;
- UINT8 PSCfgSize;
- UINT8 PSCfgODTSize;
- UINT8 PSCfgWlODTSize;
- UINT8 PhyWLODT[4];
-
- CONST ADV_R_PSCFG_ENTRY *PSCfgPtr;
- CONST ADV_PSCFG_ODT_ENTRY *PSCfgODTPtr;
- CONST ADV_R_PSCFG_WL_ODT_ENTRY *PSCfgWlODTPtr;
- UINT8 *DimmsPerChPtr;
-
- ASSERT (MemData != NULL);
- ASSERT (CurrentChannel != NULL);
-
- AddrTmgCTL = 0;
- DctOdcCtl = 0;
- RC2RC8 = 0;
- PhyRODTCSLow = 0;
- PhyRODTCSHigh = 0;
- PhyWODTCSLow = 0;
- PhyWODTCSHigh = 0;
- SlowMode = FALSE;
- PhyWLODT[0] = 0x0F;
- PhyWLODT[1] = 0x0F;
- PhyWLODT[2] = 0x0F;
- PhyWLODT[3] = 0x0F;
-
- if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_C32) == 0) {
- return AGESA_UNSUPPORTED;
- }
- if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
- return AGESA_UNSUPPORTED;
- }
- if (CurrentChannel->RegDimmPresent == 0) {
- return AGESA_UNSUPPORTED;
- }
-
- // Prepare inputs
- Dimms = CurrentChannel->Dimms;
- Speed = CurrentChannel->DCTPtr->Timings.Speed;
-
- DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID);
- if (DimmsPerChPtr != NULL) {
- MaxDimmPerCH = *DimmsPerChPtr;
- } else {
- MaxDimmPerCH = 2;
- }
-
- DIMMRankType = MemAGetPsRankType (CurrentChannel);
-
- if (MaxDimmPerCH == 4) {
- PSCfgPtr = NULL;
- PSCfgSize = NULL;
- PSCfgODTPtr = PSCfg4DIMMsODT;
- PSCfgWlODTPtr = PSCfg4DIMMsWlODT;
- PSCfgODTSize = sizeof (PSCfg4DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY);
- PSCfgWlODTSize = sizeof (PSCfg4DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
- } else if (MaxDimmPerCH == 3) {
- PSCfgPtr = PSCfg3DIMMs;
- PSCfgSize = sizeof (PSCfg3DIMMs) / sizeof (ADV_R_PSCFG_ENTRY);
- PSCfgODTPtr = PSCfg3DIMMsODT;
- PSCfgWlODTPtr = PSCfg3DIMMsWlODT;
- PSCfgODTSize = sizeof (PSCfg3DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY);
- PSCfgWlODTSize = sizeof (PSCfg3DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
- } else {
- PSCfgPtr = PSCfg2DIMMs;
- PSCfgSize = sizeof (PSCfg2DIMMs) / sizeof (ADV_R_PSCFG_ENTRY);
- PSCfgODTPtr = PSCfg2DIMMsODT;
- PSCfgWlODTPtr = PSCfg2DIMMsWlODT;
- PSCfgODTSize = sizeof (PSCfg2DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY);
- PSCfgWlODTSize = sizeof (PSCfg2DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
- }
-
- // AddrTmgCTL and DctOdcCtl
- if (MaxDimmPerCH != 4) {
- for (i = 0; i < PSCfgSize; i++, PSCfgPtr++) {
- if ((Speed != PSCfgPtr->Speed) || (Dimms != PSCfgPtr->Dimms)) {
- continue;
- }
- DimmTpMatch = 0;
- _DIMMRankType = DIMMRankType & PSCfgPtr->DIMMRankType;
- for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
- if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
- DimmTpMatch++;
- }
- }
- if (DimmTpMatch == PSCfgPtr->Dimms) {
- AddrTmgCTL = PSCfgPtr->AddrTmg;
- DctOdcCtl = 0x00223222;
- RC2RC8 = PSCfgPtr->RC2RC8;
- break;
- }
- }
- }
-
- //
- // Overrides and/or exceptions
- //
- //
- // Count slots with SR/DR poulated.
- //
- DimmTpMatch = 0;
- for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
- if ((DIMMRankType & (UINT16) 0x03 << (j << 2)) != 0) {
- DimmTpMatch++;
- }
- }
- //
- // DimmTpMatch is equal to the count of slot that have either an SR or DR
- // installed.
- //
- if (MaxDimmPerCH == 4) {
- //
- // Any SR/DR in 4 DPCH
- //
- if (DimmTpMatch > 0) {
- DctOdcCtl = 0x00223222;
- if ((Speed == DDR800_FREQUENCY) && (DimmTpMatch == 1)) {
- DctOdcCtl = 0x00113222;
- }
- }
- //
- // At Least 3 SR/DR in 4 DPCH
- //
- if (DimmTpMatch >= 3) {
- AddrTmgCTL |= 0x002F0000;
- }
- // At Least 2 SR/DR in 4 DPCH
- if (DimmTpMatch >= 2) {
- RC2RC8 = 0x4040;
- }
- } else {
- //
- // Less than 4 DPCH
- //
- //
- // Only 1 Dimm Populated and its a SR or DR OR
- // 3 Dimms Populated and Frequency is 800 MHz
- //
- if (((Dimms == 1) && (DimmTpMatch == 1)) ||
- ((Dimms == 3) && ((Speed == DDR800_FREQUENCY) ||
- (Speed == DDR1066_FREQUENCY)))) {
- DctOdcCtl = 0x00113222;
- }
- }
-
- //RC2 and RC8
- for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
- // CtrlWrd02(s) will contain the info. of SPD byte 63 after MemTDIMMPresence3 execution.
- if (CurrentChannel->CtrlWrd02[j] > 0) {
- if (CurrentChannel->CtrlWrd02[j] == 1) {
- // Store real RC2 and RC8 value (High byte) into CtrlWrd02(s) and CtrlWrd08(s).
- CurrentChannel->CtrlWrd02[j] = (UINT8) (RC2RC8 >> 12) & 0x000F;
- CurrentChannel->CtrlWrd08[j] = (UINT8) (RC2RC8 >> 8) & 0x000F;
- } else {
- // Store real RC2 and RC8 value (low byte) into CtrlWrd02(s) and CtrlWrd08(s).
- CurrentChannel->CtrlWrd02[j] = (UINT8) (RC2RC8 >> 4) & 0x000F;
- CurrentChannel->CtrlWrd08[j] = (UINT8) RC2RC8 & 0x000F;
- }
- }
- }
-
- //Programmable ODT
- for (i = 0; i < PSCfgODTSize; i++, PSCfgODTPtr++) {
- if (Dimms != PSCfgODTPtr->Dimms) {
- continue;
- }
- DimmTpMatch = 0;
- _DIMMRankType = DIMMRankType & PSCfgODTPtr->DIMMRankType;
- for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
- if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
- DimmTpMatch++;
- }
- }
- if (DimmTpMatch == PSCfgODTPtr->Dimms) {
- PhyRODTCSLow = PSCfgODTPtr->PhyRODTCSLow;
- PhyRODTCSHigh = PSCfgODTPtr->PhyRODTCSHigh;
- PhyWODTCSLow = PSCfgODTPtr->PhyWODTCSLow;
- PhyWODTCSHigh = PSCfgODTPtr->PhyWODTCSHigh;
- break;
- }
- }
-
- //WLODT
- for (i = 0; i < PSCfgWlODTSize; i++, PSCfgWlODTPtr++) {
- if (Dimms != PSCfgWlODTPtr->Dimms) {
- continue;
- }
- DimmTpMatch = 0;
- _DIMMRankType = DIMMRankType & PSCfgWlODTPtr->DIMMRankType;
- for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
- if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
- DimmTpMatch++;
- }
- }
- if (DimmTpMatch == PSCfgWlODTPtr->Dimms) {
- PhyWLODT[0] = PSCfgWlODTPtr->PhyWrLvOdt[0];
- PhyWLODT[1] = PSCfgWlODTPtr->PhyWrLvOdt[1];
- PhyWLODT[2] = PSCfgWlODTPtr->PhyWrLvOdt[2];
- PhyWLODT[3] = PSCfgWlODTPtr->PhyWrLvOdt[3];
- break;
- }
- }
-
- // Set ProcODT
- DctOdcCtl |= 0x20000000;
-
- CurrentChannel->MemClkDisMap = (UINT8 *) C32RDdr3CLKDis;
- CurrentChannel->CKETriMap = (UINT8 *) C32RDdr3CKETri;
- CurrentChannel->ChipSelTriMap = (UINT8 *) C32RDdr3CSTri;
-
- switch (MaxDimmPerCH) {
- case 3:
- CurrentChannel->ODTTriMap = (UINT8 *) C32RDdr3ODTTri3D;
- break;
- case 4:
- CurrentChannel->ODTTriMap = (UINT8 *) C32RDdr3ODTTri4D;
- break;
- default:
- CurrentChannel->ODTTriMap = (UINT8 *) C32RDdr3ODTTri2D; // Most conservative
- }
-
- CurrentChannel->DctAddrTmg = AddrTmgCTL;
- CurrentChannel->DctOdcCtl = DctOdcCtl;
- CurrentChannel->PhyRODTCSLow = PhyRODTCSLow;
- CurrentChannel->PhyRODTCSHigh = PhyRODTCSHigh;
- CurrentChannel->PhyWODTCSLow = PhyWODTCSLow;
- CurrentChannel->PhyWODTCSHigh = PhyWODTCSHigh;
- for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
- CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
- }
- CurrentChannel->SlowMode = SlowMode;
-
- return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ardk/C32/mauc32_3.c b/src/vendorcode/amd/agesa/Proc/Mem/Ardk/C32/mauc32_3.c
deleted file mode 100644
index 5abc720..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ardk/C32/mauc32_3.c
+++ /dev/null
@@ -1,357 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mauc32_3.c
- *
- * Platform specific settings for C32 DDR3 unbuffered dimms
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ardk)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/* This file contains routine that add platform specific support AM3 */
-
-
-#include "AGESA.h"
-#include "mport.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mu.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_ARDK_C32_MAUC32_3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-STATIC CONST UINT8 ROMDATA C32UDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
-// Even chip select maps to M[B,A]_CKE[0]
-// Odd chip select maps to M[B,A]_CKE[1]
-STATIC CONST UINT8 ROMDATA C32UDdr3CKETri[] = {0x55, 0xAA};
-// Bit 0: M[B,A]0_ODT[0]
-// Bit 1: M[B,A]1_ODT[0]
-// Bit 2: M[B,A]0_ODT[1]
-// Bit 3: M[B,A]1_ODT[1]
-STATIC CONST UINT8 ROMDATA C32UDdr3ODTTri2D[] = {0x01, 0x04, 0x02, 0x08};
-// 3 dimms per channel
-// Dimm 0: BP_MEMODTx[0]
-// Dimm 1: BP_MEMODTx[3,1]
-// Dimm 2: BP_MEMODTx[2]
-STATIC CONST UINT8 ROMDATA C32UDdr3ODTTri3D[] = {0xFF, 0xFF, 0xFF, 0xFF};
-// Bit 0: M[B,A]0_CS_H/L[0]
-// Bit 1: M[B,A]0_CS_H/L[1]
-// Bit 2: M[B,A]0_CS_H/L[2]
-// Bit 3: M[B,A]0_CS_H/L[3]
-STATIC CONST UINT8 ROMDATA C32UDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for C32 DDR3 unbuffered dimms
- *
- *
- * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE
- * @param[in] SocketID Socket number
- * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT
- *
- * @return AGESA_SUCCESS
- * @return CurrentChannel->MemClkDisMap Points this pointer to C32 MemClkDis table
- * @return CurrentChannel->ChipSelTriMap Points this pointer to C32 CS table
- * @return CurrentChannel->CKETriMap Points this pointer to C32 ODT table
- * @return CurrentChannel->ODTTriMap Points this pointer to C32 CKE table
- * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC
- * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte
- * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel
- * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel
- * @return CurrentChannel->SlowMode Slow Mode
- *
- *
- */
-
-AGESA_STATUS
-MemAGetPsCfgUC32_3 (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- )
-{
- STATIC CONST PSCFG_ENTRY PSCfg[] = {
- {DDR800_FREQUENCY, 0xFF, 0x00390039, 0x20223323},
- {DDR1066_FREQUENCY, 0xFF, 0x00350037, 0x20223323},
- {DDR1333_FREQUENCY, 0xFF, 0x00000035, 0x20223323},
- {DDR1600_FREQUENCY, 0xFF, 0x00000033, 0x20223323}
- };
-
- STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg2DIMMsODT[] = {
- {SR_DIMM0, 0x00000000, 0x00000000, 0x00000001, 0x00000000, 1},
- {DR_DIMM0, 0x00000000, 0x00000000, 0x00000104, 0x00000000, 1},
- {SR_DIMM1, 0x00000000,0x00000000,0x00020000, 0x00000000, 1},
- {DR_DIMM1, 0x00000000,0x00000000,0x02080000, 0x00000000, 1},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, 0x01010202,0x00000000,0x09030603, 0x00000000, 2},
- };
-
- STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg2DIMMsWlODT[] = {
- {SR_DIMM0, {0x01, 0x00, 0x00, 0x00}, 1},
- {DR_DIMM0, {0x04, 0x00, 0x00, 0x00}, 1},
- {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1},
- {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}
- };
-
- STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg3DIMMsODT[] = {
- {SR_DIMM2 + DR_DIMM2, 0x00000000, 0x00000000, 0x00000000, 0x00000404, 1},
- //{SR_DIMM0 + DR_DIMM0, 0x00000000, 0x00000000, 0x00000101, 0x00000000, 1},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, 0x00000404, 0x00000101, 0x00000405, 0x00000105, 2},
- //{SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, 0x05050606, 0x00000303, 0x0D070607, 0x00000307, 3},
- };
-
- STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg3DIMMsWlODT[] = {
- {SR_DIMM2 + DR_DIMM2, {0x00, 0x00, 0x04, 0x00}, 1},
- //{SR_DIMM0 + DR_DIMM0, {0x01, 0x02, 0x00, 0x00}, 1},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, {0x05, 0x00, 0x05, 0x00}, 2},
- //{SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x07, 0x07, 0x07, 0x00}, 3},
- };
-
- UINT16 i;
- UINT16 j;
- UINT8 MaxDimmPerCH;
- UINT8 Loads;
- UINT8 Dimms;
- UINT16 Speed;
- UINT16 DIMMRankType;
- UINT16 _DIMMRankType;
- UINT32 AddrTmgCTL;
- UINT32 DctOdcCtl;
- UINT32 PhyRODTCSLow;
- UINT32 PhyRODTCSHigh;
- UINT32 PhyWODTCSLow;
- UINT32 PhyWODTCSHigh;
- UINT8 PhyWLODT[4];
- UINT8 PSCfgODTSize;
- UINT8 PSCfgWlODTSize;
- BOOLEAN SlowMode;
- UINT8 DimmTpMatch;
- CONST ADV_PSCFG_ODT_ENTRY *PSCfgODTPtr;
- CONST ADV_R_PSCFG_WL_ODT_ENTRY *PSCfgWlODTPtr;
- UINT8 *DimmsPerChPtr;
-
- ASSERT (MemData != NULL);
- ASSERT (CurrentChannel != NULL);
-
- AddrTmgCTL = 0;
- DctOdcCtl = 0;
- PhyRODTCSLow = 0;
- PhyRODTCSHigh = 0;
- PhyWODTCSLow = 0;
- PhyWODTCSHigh = 0;
- PhyWLODT[0] = 0x0F;
- PhyWLODT[1] = 0x0F;
- PhyWLODT[2] = 0x0F;
- PhyWLODT[3] = 0x0F;
-
- if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_C32) == 0) {
- return AGESA_UNSUPPORTED;
- }
- if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
- return AGESA_UNSUPPORTED;
- }
- if (CurrentChannel->RegDimmPresent) {
- return AGESA_UNSUPPORTED;
- }
- // Prepare inputs
-
- DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID);
- if (DimmsPerChPtr != NULL) {
- MaxDimmPerCH = *DimmsPerChPtr;
- } else {
- MaxDimmPerCH = 2;
- }
-
- Loads = CurrentChannel->Loads;
- Dimms = CurrentChannel->Dimms;
- Speed = CurrentChannel->DCTPtr->Timings.Speed;
-
- DIMMRankType = MemAGetPsRankType (CurrentChannel);
-
- if ((Speed == DDR1333_FREQUENCY || Speed == DDR1600_FREQUENCY) && (Dimms == 2)) {
- SlowMode = TRUE; // 2T
- } else {
- SlowMode = FALSE; // 1T
- }
-
- for (i = 0; i < GET_SIZE_OF (PSCfg); i++) {
- if (Speed == PSCfg[i].Speed) {
- if (Loads <= PSCfg[i].Loads) {
- AddrTmgCTL = PSCfg[i].AddrTmg;
- DctOdcCtl = PSCfg[i].Odc;
- break;
- }
- }
- }
-
- ASSERT (i < GET_SIZE_OF (PSCfg));
-
- if (MaxDimmPerCH == 3) {
- PSCfgODTPtr = PSCfg3DIMMsODT;
- PSCfgWlODTPtr = PSCfg3DIMMsWlODT;
- PSCfgODTSize = sizeof (PSCfg3DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY);
- PSCfgWlODTSize = sizeof (PSCfg3DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
- } else {
- PSCfgODTPtr = PSCfg2DIMMsODT;
- PSCfgWlODTPtr = PSCfg2DIMMsWlODT;
- PSCfgODTSize = sizeof (PSCfg2DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY);
- PSCfgWlODTSize = sizeof (PSCfg2DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
- }
-
- // Programmable ODT
- for (i = 0; i < PSCfgODTSize; i++, PSCfgODTPtr++) {
- if (Dimms != PSCfgODTPtr->Dimms) {
- continue;
- }
- DimmTpMatch = 0;
- _DIMMRankType = DIMMRankType & PSCfgODTPtr->DIMMRankType;
- for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
- if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
- DimmTpMatch++;
- }
- }
- if (DimmTpMatch == PSCfgODTPtr->Dimms) {
- PhyRODTCSLow = PSCfgODTPtr->PhyRODTCSLow;
- PhyRODTCSHigh = PSCfgODTPtr->PhyRODTCSHigh;
- PhyWODTCSLow = PSCfgODTPtr->PhyWODTCSLow;
- PhyWODTCSHigh = PSCfgODTPtr->PhyWODTCSHigh;
- break;
- }
- }
-
- // WL ODT
- for (i = 0; i < PSCfgWlODTSize; i++, PSCfgWlODTPtr++) {
- if (Dimms != PSCfgWlODTPtr->Dimms) {
- continue;
- }
- DimmTpMatch = 0;
- _DIMMRankType = DIMMRankType & PSCfgWlODTPtr->DIMMRankType;
- for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
- if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
- DimmTpMatch++;
- }
- }
- if (DimmTpMatch == PSCfgWlODTPtr->Dimms) {
- PhyWLODT[0] = PSCfgWlODTPtr->PhyWrLvOdt[0];
- PhyWLODT[1] = PSCfgWlODTPtr->PhyWrLvOdt[1];
- PhyWLODT[2] = PSCfgWlODTPtr->PhyWrLvOdt[2];
- PhyWLODT[3] = PSCfgWlODTPtr->PhyWrLvOdt[3];
- break;
- }
- }
-
- //
- // Overrides and/or exceptions
- //
- if (Dimms == 1) {
- if (Loads >= 16) {
- if (Speed == DDR800_FREQUENCY) {
- AddrTmgCTL = 0x003B0000;
- } else if (Speed == DDR1066_FREQUENCY) {
- AddrTmgCTL = 0x00380000;
- } else if (Speed == DDR1333_FREQUENCY) {
- AddrTmgCTL = 0x00360000;
- } else {
- AddrTmgCTL = 0x00340000;
- SlowMode = TRUE;
- }
- } else {
- AddrTmgCTL = 0;
- }
- DctOdcCtl = 0x20113222;
- }
-
- CurrentChannel->MemClkDisMap = (UINT8 *) C32UDdr3CLKDis;
- CurrentChannel->CKETriMap = (UINT8 *) C32UDdr3CKETri;
- CurrentChannel->ChipSelTriMap = (UINT8 *) C32UDdr3CSTri;
-
- switch (MaxDimmPerCH) {
- case 3:
- CurrentChannel->ODTTriMap = (UINT8 *) C32UDdr3ODTTri3D;
- break;
- default:
- CurrentChannel->ODTTriMap = (UINT8 *) C32UDdr3ODTTri2D; // Most conservative
- }
-
- CurrentChannel->DctEccDqsLike = 0x0403;
- CurrentChannel->DctEccDqsScale = 0x70;
- CurrentChannel->DctAddrTmg = AddrTmgCTL;
- CurrentChannel->DctOdcCtl = DctOdcCtl;
- CurrentChannel->PhyRODTCSLow = PhyRODTCSLow;
- CurrentChannel->PhyRODTCSHigh = PhyRODTCSHigh;
- CurrentChannel->PhyWODTCSLow = PhyWODTCSLow;
- CurrentChannel->PhyWODTCSHigh = PhyWODTCSHigh;
- for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
- CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
- }
- CurrentChannel->SlowMode = SlowMode;
-
- return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ardk/DA/masda2.c b/src/vendorcode/amd/agesa/Proc/Mem/Ardk/DA/masda2.c
deleted file mode 100644
index e8ca7d2..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ardk/DA/masda2.c
+++ /dev/null
@@ -1,207 +0,0 @@
-/* $NoKeywords:$ */
-/*
- * @file
- *
- * masda2.c
- *
- * Platform specific settings for DA DDR2 SO-dimms
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ardk)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/* This file contains routine that add platform specific support S1g3 */
-
-
-#include "AGESA.h"
-#include "mport.h"
-#include "PlatformMemoryConfiguration.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_ARDK_DA_MASDA2_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-STATIC CONST UINT8 ROMDATA DASDdr2CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
-// Even chip select maps to M[B,A]_CKE[0]
-// Odd chip select maps to M[B,A]_CKE[1]
-STATIC CONST UINT8 ROMDATA DASDdr2CKETri[] = {0x55, 0xAA};
-// Bit 0: M[B,A]0_ODT[0]
-// Bit 1: M[B,A]1_ODT[0]
-// Bit 2: M[B,A]0_ODT[1]
-// Bit 3: M[B,A]1_ODT[1]
-STATIC CONST UINT8 ROMDATA DASDdr2ODTTri[] = {0x01, 0x04, 0x02, 0x08};
-// Bit 0: M[B,A]0_CS_H/L[0]
-// Bit 1: M[B,A]0_CS_H/L[1]
-// Bit 2: M[B,A]0_CS_H/L[2]
-// Bit 3: M[B,A]0_CS_H/L[3]
-STATIC CONST UINT8 ROMDATA DASDdr2CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for DA DDR2 SO-dimms
- *
- *
- * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE
- * @param[in] SocketID Socket number
- * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT
- *
- * @return AGESA_SUCCESS
- * @return CurrentChannel->MemClkDisMap Points this pointer to RB MemClkDis table
- * @return CurrentChannel->ChipSelTriMap Points this pointer to RB CS table
- * @return CurrentChannel->CKETriMap Points this pointer to RB ODT table
- * @return CurrentChannel->ODTTriMap Points this pointer to RB CKE table
- * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC
- * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte
- * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel
- * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel
- * @return CurrentChannel->SlowMode Slow Mode
- *
- *
- */
-
-AGESA_STATUS
-MemAGetPsCfgSDA2 (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- )
-{
- STATIC CONST PSCFG_ENTRY PSCfg[] = {
- {DDR400_FREQUENCY, 0xFF, 0x002F2F2F, 0x10111222},
- {DDR533_FREQUENCY, 0xFF, 0x002F2F2F, 0x10111222},
- {DDR667_FREQUENCY, 0xFF, 0x002A2A2A, 0x10111222},
- {DDR800_FREQUENCY, 0xFF, 0x002A2A2A, 0x10111222},
- };
-
- UINT16 i;
- UINT8 Loads;
- UINT8 Ranks;
- UINT16 Speed;
- UINT32 AddrTmgCTL;
- UINT32 DctOdcCtl;
- BOOLEAN SlowMode;
-
- ASSERT (MemData != 0);
- ASSERT (CurrentChannel != 0);
-
- AddrTmgCTL = 0;
- DctOdcCtl = 0;
-
- if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) {
- return AGESA_UNSUPPORTED;
- }
- if (CurrentChannel->TechType != DDR2_TECHNOLOGY) {
- return AGESA_UNSUPPORTED;
- }
- if (CurrentChannel->SODimmPresent != CurrentChannel->ChDimmValid) {
- return AGESA_UNSUPPORTED;
- }
-
- // Prepare inputs
- Loads = CurrentChannel->Loads;
- Ranks = CurrentChannel->Ranks;
- Speed = CurrentChannel->DCTPtr->Timings.Speed;
- SlowMode = FALSE; // 1T
-
- for (i = 0; i < GET_SIZE_OF (PSCfg); i++) {
- if (Speed == PSCfg[i].Speed) {
- if (Loads <= PSCfg[i].Loads) {
- AddrTmgCTL = PSCfg[i].AddrTmg;
- DctOdcCtl = PSCfg[i].Odc;
- break;
- }
- }
- }
- ASSERT (i < GET_SIZE_OF (PSCfg));
-
- //
- // Overrides and/or exceptions
- //
- if (Loads == 16) {
- if ((Speed == DDR533_FREQUENCY) && (Ranks == 2)) {
- AddrTmgCTL = 0x002C2C2C;
- } else if ((Speed == DDR667_FREQUENCY) && (Ranks == 1)) {
- AddrTmgCTL = 0x00272727;
- } else if ((Speed == DDR667_FREQUENCY) && (Ranks == 2)) {
- AddrTmgCTL = 0x00002828;
- SlowMode = TRUE; // 2T
- } else if ((Speed == DDR800_FREQUENCY) && (Ranks == 1)) {
- AddrTmgCTL = 0x00292929;
- } else if ((Speed == DDR800_FREQUENCY) && (Ranks == 2)) {
- AddrTmgCTL = 0x00002F2F;
- SlowMode = TRUE; // 2T
- }
- }
- CurrentChannel->MemClkDisMap = (UINT8 *) DASDdr2CLKDis;
- CurrentChannel->CKETriMap = (UINT8 *) DASDdr2CKETri;
- CurrentChannel->ODTTriMap = (UINT8 *) DASDdr2ODTTri;
- CurrentChannel->ChipSelTriMap = (UINT8 *) DASDdr2CSTri;
- CurrentChannel->DctAddrTmg = AddrTmgCTL;
- CurrentChannel->DctOdcCtl = DctOdcCtl;
- CurrentChannel->SlowMode = SlowMode;
-
- return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ardk/DA/masda3.c b/src/vendorcode/amd/agesa/Proc/Mem/Ardk/DA/masda3.c
deleted file mode 100644
index 8ac6b4d..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ardk/DA/masda3.c
+++ /dev/null
@@ -1,261 +0,0 @@
-/* $NoKeywords:$ */
-/*
- * @file
- *
- * masda3.c
- *
- * Platform specific settings for DA DDR3 SO-dimms
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ardk)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/* This file contains routine that add platform specific support S1g4 */
-
-
-#include "AGESA.h"
-#include "mport.h"
-#include "ma.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mu.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_ARDK_DA_MASDA3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-STATIC CONST UINT8 ROMDATA DASDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
-// Even chip select maps to M[B,A]_CKE[0]
-// Odd chip select maps to M[B,A]_CKE[1]
-STATIC CONST UINT8 ROMDATA DASDdr3CKETri[] = {0x55, 0xAA};
-// Bit 0: M[B,A]0_ODT[0]
-// Bit 1: M[B,A]1_ODT[0]
-// Bit 2: M[B,A]0_ODT[1]
-// Bit 3: M[B,A]1_ODT[1]
-STATIC CONST UINT8 ROMDATA DASDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
-// Bit 0: M[B,A]0_CS_H/L[0]
-// Bit 1: M[B,A]0_CS_H/L[1]
-// Bit 2: M[B,A]0_CS_H/L[2]
-// Bit 3: M[B,A]0_CS_H/L[3]
-STATIC CONST UINT8 ROMDATA DASDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for DA DDR3 SO-dimms
- *
- *
- * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE
- * @param[in] SocketID Socket number
- * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT
- *
- * @return AGESA_SUCCESS
- * @return CurrentChannel->MemClkDisMap Points this pointer to RB MemClkDis table
- * @return CurrentChannel->ChipSelTriMap Points this pointer to RB CS table
- * @return CurrentChannel->CKETriMap Points this pointer to RB ODT table
- * @return CurrentChannel->ODTTriMap Points this pointer to RB CKE table
- * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC
- * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte
- * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel
- * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel
- * @return CurrentChannel->SlowMode Slow Mode
- *
- *
- */
-
-AGESA_STATUS
-MemAGetPsCfgSDA3 (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- )
-{
- STATIC CONST PSCFG_ENTRY PSCfg[] = {
- {DDR800_FREQUENCY, 0xFF, 0x00000000, 0x00113222},
- {DDR1066_FREQUENCY, 0xFF, 0x00000000, 0x10113222},
- {DDR1333_FREQUENCY, 0xFF, 0x00000000, 0x20113222},
- };
-
- STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfgDIMMWlODT[] = {
- {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1},
- {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}
- };
-
- UINT16 i;
- UINT16 j;
- UINT8 Loads;
- UINT8 Dimms;
- UINT16 Speed;
- UINT32 AddrTmgCTL;
- UINT32 DctOdcCtl;
- UINT8 PhyWLODT[4];
- BOOLEAN SlowMode;
- UINT8 MaxDimmPerCH;
- UINT8 *DimmsPerChPtr;
- UINT16 DIMMRankType;
- UINT16 _DIMMRankType;
- UINT8 DimmTpMatch;
-
- ASSERT (MemData != 0);
- ASSERT (CurrentChannel != 0);
-
- AddrTmgCTL = 0;
- DctOdcCtl = 0;
- PhyWLODT[0] = 0x0F;
- PhyWLODT[1] = 0x0F;
- PhyWLODT[2] = 0x0F;
- PhyWLODT[3] = 0x0F;
- SlowMode = FALSE; // 1T
- if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) {
- return AGESA_UNSUPPORTED;
- }
- if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
- return AGESA_UNSUPPORTED;
- }
- if (CurrentChannel->SODimmPresent != CurrentChannel->ChDimmValid) {
- return AGESA_UNSUPPORTED;
- }
- // Prepare inputs
- Loads = CurrentChannel->Loads;
- Dimms = CurrentChannel->Dimms;
- Speed = CurrentChannel->DCTPtr->Timings.Speed;
-
- DIMMRankType = MemAGetPsRankType (CurrentChannel);
-
- DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID);
- if (DimmsPerChPtr != NULL) {
- MaxDimmPerCH = *DimmsPerChPtr;
- } else {
- MaxDimmPerCH = 2;
- }
-
- for (i = 0; i < GET_SIZE_OF (PSCfg); i++) {
- if (Speed == PSCfg[i].Speed) {
- if (Loads <= PSCfg[i].Loads) {
- AddrTmgCTL = PSCfg[i].AddrTmg;
- DctOdcCtl = PSCfg[i].Odc;
- break;
- }
- }
- }
-
- // WL ODT
- for (i = 0; i < GET_SIZE_OF (PSCfgDIMMWlODT); i++) {
- if (Dimms != PSCfgDIMMWlODT[i].Dimms) {
- continue;
- }
- DimmTpMatch = 0;
- _DIMMRankType = DIMMRankType & PSCfgDIMMWlODT[i].DIMMRankType;
- for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
- if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
- DimmTpMatch++;
- }
- }
- if (DimmTpMatch == PSCfgDIMMWlODT[i].Dimms) {
- PhyWLODT[0] = PSCfgDIMMWlODT[i].PhyWrLvOdt[0];
- PhyWLODT[1] = PSCfgDIMMWlODT[i].PhyWrLvOdt[1];
- PhyWLODT[2] = PSCfgDIMMWlODT[i].PhyWrLvOdt[2];
- PhyWLODT[3] = PSCfgDIMMWlODT[i].PhyWrLvOdt[3];
- break;
- }
- }
-
- //
- // Overrides and/or exceptions
- //
- if (MaxDimmPerCH == 2) {
- if (Dimms == 2) {
- DctOdcCtl = 0x20223323;
- SlowMode = TRUE;
- if (Speed == DDR800_FREQUENCY) {
- AddrTmgCTL = 0x00000039;
- } else if (Speed == DDR1066_FREQUENCY) {
- AddrTmgCTL = 0x00000037;
- }
- } else {
- DctOdcCtl = 0x20113222;
- }
- } else {
- if (CurrentChannel->DimmSRPresent != 0) {
- PhyWLODT[0] = 1;
- } else if (CurrentChannel->DimmDrPresent != 0) {
- PhyWLODT[0] = 4;
- }
- }
-
- CurrentChannel->MemClkDisMap = (UINT8 *) DASDdr3CLKDis;
- CurrentChannel->CKETriMap = (UINT8 *) DASDdr3CKETri;
- CurrentChannel->ODTTriMap = (UINT8 *) DASDdr3ODTTri;
- CurrentChannel->ChipSelTriMap = (UINT8 *) DASDdr3CSTri;
-
- CurrentChannel->DctAddrTmg = AddrTmgCTL;
- CurrentChannel->DctOdcCtl = DctOdcCtl;
- for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
- CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
- }
- CurrentChannel->SlowMode = SlowMode;
-
- return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ardk/DA/mauda3.c b/src/vendorcode/amd/agesa/Proc/Mem/Ardk/DA/mauda3.c
deleted file mode 100644
index 6913973..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ardk/DA/mauda3.c
+++ /dev/null
@@ -1,260 +0,0 @@
-/* $NoKeywords:$ */
-/*
- * @file
- *
- * mauda3.c
- *
- * Platform specific settings for DA DDR3 unbuffered dimms
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ardk)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/* This file contains routine that add platform specific support AM3 */
-
-
-#include "AGESA.h"
-#include "mport.h"
-#include "PlatformMemoryConfiguration.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_ARDK_DA_MAUDA3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-STATIC CONST UINT8 ROMDATA DAUDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
-// Even chip select maps to M[B,A]_CKE[0]
-// Odd chip select maps to M[B,A]_CKE[1]
-STATIC CONST UINT8 ROMDATA DAUDdr3CKETri[] = {0x55, 0xAA};
-// Bit 0: M[B,A]0_ODT[0]
-// Bit 1: M[B,A]1_ODT[0]
-// Bit 2: M[B,A]0_ODT[1]
-// Bit 3: M[B,A]1_ODT[1]
-STATIC CONST UINT8 ROMDATA DAUDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
-// Bit 0: M[B,A]0_CS_H/L[0]
-// Bit 1: M[B,A]0_CS_H/L[1]
-// Bit 2: M[B,A]0_CS_H/L[2]
-// Bit 3: M[B,A]0_CS_H/L[3]
-STATIC CONST UINT8 ROMDATA DAUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for DA DDR3 Unbuffered dimms
- *
- *
- * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE
- * @param[in] SocketID Socket number
- * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT
- *
- * @return AGESA_SUCCESS
- * @return CurrentChannel->MemClkDisMap Points this pointer to RB MemClkDis table
- * @return CurrentChannel->ChipSelTriMap Points this pointer to RB CS table
- * @return CurrentChannel->CKETriMap Points this pointer to RB ODT table
- * @return CurrentChannel->ODTTriMap Points this pointer to RB CKE table
- * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC
- * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte
- * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel
- * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel
- * @return CurrentChannel->SlowMode Slow Mode
- *
- */
-
-AGESA_STATUS
-MemAGetPsCfgUDA3 (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- )
-{
- STATIC CONST PSCFG_ENTRY PSCfg1Dimm[] = {
- {DDR800_FREQUENCY, 0x10, 0x003B0000, 0x20113222},
- {DDR1066_FREQUENCY, 0x10, 0x00380000, 0x20113222},
- {DDR1333_FREQUENCY, 0x10, 0x00360000, 0x20113222},
- {DDR1600_FREQUENCY, 0x10, 0x00340000, 0x20113222}
- };
- STATIC CONST PSCFG_ENTRY PSCfg2Dimm[] = {
- {DDR800_FREQUENCY, 0xFF, 0x00390039, 0x20223323},
- {DDR1066_FREQUENCY, 0xFF, 0x00350037, 0x20223323},
- {DDR1333_FREQUENCY, 0xFF, 0x00000035, 0x20223323},
- {DDR1600_FREQUENCY, 0xFF, 0x00000033, 0x20223323}
- };
-
- STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfgDIMMWlODT[] = {
- {SR_DIMM0, {0x01, 0x00, 0x00, 0x00}, 1},
- {DR_DIMM0, {0x04, 0x00, 0x00, 0x00}, 1},
- {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1},
- {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}
- };
-
- UINT16 i;
- UINT16 j;
- UINT8 Loads;
- UINT8 Dimms;
- UINT16 Speed;
- UINT16 DIMMRankType;
- UINT16 _DIMMRankType;
- UINT32 AddrTmgCTL;
- UINT32 DctOdcCtl;
- UINT8 PhyWLODT[4];
- BOOLEAN SlowMode;
- UINT8 DimmTpMatch;
-
- ASSERT (MemData != 0);
- ASSERT (CurrentChannel != 0);
-
- AddrTmgCTL = 0;
- DctOdcCtl = 0;
- PhyWLODT[0] = 0x0F;
- PhyWLODT[1] = 0x0F;
- PhyWLODT[2] = 0x0F;
- PhyWLODT[3] = 0x0F;
-
- if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) {
- return AGESA_UNSUPPORTED;
- }
- if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
- return AGESA_UNSUPPORTED;
- }
- if ((CurrentChannel->RegDimmPresent != 0) || (CurrentChannel->SODimmPresent != 0)) {
- return AGESA_UNSUPPORTED;
- }
- // Prepare inputs
- Loads = CurrentChannel->Loads;
- Dimms = CurrentChannel->Dimms;
- Speed = CurrentChannel->DCTPtr->Timings.Speed;
- DIMMRankType = MemAGetPsRankType (CurrentChannel);
-
- if ((Speed == DDR1333_FREQUENCY || Speed == DDR1600_FREQUENCY) && (Dimms == 2)) {
- SlowMode = TRUE; // 2T
- } else if ((Speed == DDR1600_FREQUENCY) && (Dimms == 1) && (Loads >= 16)) {
- SlowMode = TRUE; // 2T
- } else {
- SlowMode = FALSE; // 1T
- }
-
- if (Dimms == 1) {
- for (i = 0; i < GET_SIZE_OF (PSCfg1Dimm); i++) {
- if (Speed == PSCfg1Dimm[i].Speed) {
- if (Loads >= PSCfg1Dimm[i].Loads) {
- AddrTmgCTL = PSCfg1Dimm[i].AddrTmg;
- DctOdcCtl = PSCfg1Dimm[i].Odc;
- } else {
- DctOdcCtl = 0x20113222;
- }
- break;
- }
- }
- ASSERT (i < GET_SIZE_OF (PSCfg1Dimm));
- } else {
- for (i = 0; i < GET_SIZE_OF (PSCfg2Dimm); i++) {
- if (Speed == PSCfg2Dimm[i].Speed) {
- if (Loads <= PSCfg2Dimm[i].Loads) {
- AddrTmgCTL = PSCfg2Dimm[i].AddrTmg;
- DctOdcCtl = PSCfg2Dimm[i].Odc;
- break;
- }
- }
- }
- ASSERT (i < GET_SIZE_OF (PSCfg2Dimm));
- }
-
- // WL ODT
- for (i = 0; i < GET_SIZE_OF (PSCfgDIMMWlODT); i++) {
- if (Dimms != PSCfgDIMMWlODT[i].Dimms) {
- continue;
- }
- DimmTpMatch = 0;
- _DIMMRankType = DIMMRankType & PSCfgDIMMWlODT[i].DIMMRankType;
- for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
- if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
- DimmTpMatch++;
- }
- }
- if (DimmTpMatch == PSCfgDIMMWlODT[i].Dimms) {
- PhyWLODT[0] = PSCfgDIMMWlODT[i].PhyWrLvOdt[0];
- PhyWLODT[1] = PSCfgDIMMWlODT[i].PhyWrLvOdt[1];
- PhyWLODT[2] = PSCfgDIMMWlODT[i].PhyWrLvOdt[2];
- PhyWLODT[3] = PSCfgDIMMWlODT[i].PhyWrLvOdt[3];
- break;
- }
- }
-
- CurrentChannel->MemClkDisMap = (UINT8 *) DAUDdr3CLKDis;
- CurrentChannel->CKETriMap = (UINT8 *) DAUDdr3CKETri;
- CurrentChannel->ODTTriMap = (UINT8 *) DAUDdr3ODTTri;
- CurrentChannel->ChipSelTriMap = (UINT8 *) DAUDdr3CSTri;
-
- CurrentChannel->DctEccDqsLike = 0x0403;
- CurrentChannel->DctEccDqsScale = 0x70;
- CurrentChannel->DctAddrTmg = AddrTmgCTL;
- CurrentChannel->DctOdcCtl = DctOdcCtl;
- for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
- CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
- }
- CurrentChannel->SlowMode = SlowMode;
-
- return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ardk/DR/mardr2.c b/src/vendorcode/amd/agesa/Proc/Mem/Ardk/DR/mardr2.c
deleted file mode 100644
index 6f2249b..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ardk/DR/mardr2.c
+++ /dev/null
@@ -1,274 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mardr2.c
- *
- * Platform specific settings for DR DDR2 L1 system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ardk)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/* This file contains routine that add platform specific support L1 */
-
-
-#include "AGESA.h"
-#include "mport.h"
-#include "ma.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mu.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_ARDK_DR_MARDR2_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-STATIC CONST UINT8 ROMDATA DrRDdr2CLKDis[] = {0x00, 0x00, 0xC0, 0x30, 0x0C, 0x03, 0x00, 0x00};
-
-// Chip select 0, 1, 4, 5 maps to M[B,A]_CKE[0]
-// Chip select 2, 3, 6, 7 maps to M[B,A]_CKE[1]
-STATIC CONST UINT8 ROMDATA DrRDdr2CKETri[] = {0x33, 0xCC};
-
-// 2 dimms per channel
-// Dimm 0: BP_MEMODTx[2,0]
-// Dimm 1: BP_MEMODTx[3,1]
-STATIC CONST UINT8 ROMDATA DrRDdr2ODTTri2D[] = {0x03, 0x0C, 0x32, 0xC8};
-// 3 dimms per channel
-// Dimm 0: BP_MEMODTx[0]
-// Dimm 1: BP_MEMODTx[3,1]
-// Dimm 2: BP_MEMODTx[2]
-STATIC CONST UINT8 ROMDATA DrRDdr2ODTTri3D[] = {0x03, 0x0C, 0x30, 0xC8};
-// 4 dimms per channel
-// Dimm 0: BP_MEMODTx[0]
-// Dimm 1: BP_MEMODTx[1]
-// Dimm 2: BP_MEMODTx[2]
-// Dimm 3: BP_MEMODTx[3]
-STATIC CONST UINT8 ROMDATA DrRDdr2ODTTri4D[] = {0x03, 0x0C, 0x30, 0xC0};
-
-// BIOS must not tri-state chip select pin corresponding to the second chip
-// select of a single rank registered dimm
-STATIC CONST UINT8 ROMDATA DrRDdr2CSTri[] = {0x01, 0x03, 0x04, 0x0C, 0x10, 0x30, 0x40, 0xC0};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for DR DDR2 L1 system
- *
- * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE
- * @param[in] SocketID Socket number
- * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT
- *
- * @return AGESA_SUCCESS
- * @return CurrentChannel->MemClkDisMap Points this pointer to RB MemClkDis table
- * @return CurrentChannel->ChipSelTriMap Points this pointer to RB CS table
- * @return CurrentChannel->CKETriMap Points this pointer to RB ODT table
- * @return CurrentChannel->ODTTriMap Points this pointer to RB CKE table
- * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC
- * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte
- * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel
- * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel
- * @return CurrentChannel->SlowMode Slow Mode
- *
- */
-
-AGESA_STATUS
-MemAGetPsCfgRDr2 (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- )
-{
- STATIC CONST ADV_PSCFG_ENTRY PSCfg4D[] = {
- {ANY_, ANY_, 0x00000000, 0x00111222, 1},
- {ANY_, ANY_, 0x00370000, 0x00111222, 2}
- };
-
- STATIC CONST ADV_PSCFG_ENTRY PSCfg8D[] = {
- {ANY_, ANY_, 0x00000000, 0x00111222, 1},
- {ANY_, ANY_, 0x00370000, 0x00111222, 2},
- {ANY_, ANY_, 0x002F0000, 0x00111222, ANY_}
- };
-
- CONST ADV_PSCFG_ENTRY *PSCfgPtr;
- UINT16 i;
- UINT8 MaxDimmPerCH;
- UINT16 TabSize;
- UINT8 Loads;
- UINT8 Dimms;
- UINT16 Speed;
- UINT32 AddrTmgCTL;
- UINT32 DctOdcCtl;
- UINT16 QRPresent;
- UINT16 DRx4Present;
- BOOLEAN SlowMode;
- UINT8 *DimmsPerChPtr;
-
- ASSERT (MemData != 0);
- ASSERT (CurrentChannel != 0);
-
- if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) {
- return AGESA_UNSUPPORTED;
- }
- if (CurrentChannel->TechType != DDR2_TECHNOLOGY) {
- return AGESA_UNSUPPORTED;
- }
- if (CurrentChannel->RegDimmPresent != CurrentChannel->ChDimmValid) {
- return AGESA_UNSUPPORTED;
- }
-
- // Prepare inputs
- Loads = CurrentChannel->Loads;
- Dimms = CurrentChannel->Dimms;
- Speed = CurrentChannel->DCTPtr->Timings.Speed;
- DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID);
- if (DimmsPerChPtr != NULL) {
- MaxDimmPerCH = *DimmsPerChPtr;
- } else {
- MaxDimmPerCH = 2;
- }
- QRPresent = CurrentChannel->DimmQrPresent;
- DRx4Present = CurrentChannel->DimmDrPresent & CurrentChannel->Dimmx4Present;
- if (QRPresent) {
- Dimms = (Dimms + 1) / 2;
- }
-
- // Table look up
- if (MaxDimmPerCH <= 2) {
- PSCfgPtr = PSCfg4D;
- TabSize = GET_SIZE_OF (PSCfg4D);
- } else {
- PSCfgPtr = PSCfg8D;
- TabSize = GET_SIZE_OF (PSCfg8D);
- }
- DctOdcCtl = 0;
- AddrTmgCTL = 0;
- for (i = 0; i < TabSize; i++) {
- if ((PSCfgPtr[i].Dimms == ANY_) || (PSCfgPtr[i].Dimms == Dimms)) {
- if ((PSCfgPtr[i].Speed == ANY_) || (PSCfgPtr[i].Speed == Speed)) {
- if ((PSCfgPtr[i].Loads == ANY_) || (PSCfgPtr[i].Loads >= Loads)) {
- AddrTmgCTL = PSCfgPtr[i].AddrTmg;
- DctOdcCtl = PSCfgPtr[i].Odc;
- break;
- }
- }
- }
- }
- ASSERT (i == TabSize);
- SlowMode = FALSE; // 1T
-
- //
- // Overrides and/or exceptions
- //
-
- if (QRPresent == 0x55) {
- // QR for 4DIMM case only
- AddrTmgCTL = 0x002F0000;
- if (Speed >= DDR667_FREQUENCY) {
- DctOdcCtl = 0x00331222;
- }
- }
-
- if (Speed >= DDR667_FREQUENCY) {
- if ((QRPresent != 0) || (DRx4Present != 0)) {
- AddrTmgCTL |= 0x00002F00;
- }
- if (Dimms >= 3) {
- AddrTmgCTL |= 0x0000002F;
- }
- if (Dimms == 3 || Dimms == 4) {
- DctOdcCtl = 0x00331222;
- }
- }
-
- // Adjust Processor ODT
- if (Dimms == 1) {
- DctOdcCtl |= 0x20000000; // 75ohms
- } else {
- DctOdcCtl |= 0x10000000; // 150ohms
- }
-
- CurrentChannel->MemClkDisMap = (UINT8 *) DrRDdr2CLKDis;
- CurrentChannel->CKETriMap = (UINT8 *) DrRDdr2CKETri;
- CurrentChannel->ChipSelTriMap = (UINT8 *) DrRDdr2CSTri;
-
- switch (MaxDimmPerCH) {
- case 3:
- CurrentChannel->ODTTriMap = (UINT8 *) DrRDdr2ODTTri3D;
- break;
- case 4:
- CurrentChannel->ODTTriMap = (UINT8 *) DrRDdr2ODTTri4D;
- break;
- default:
- CurrentChannel->ODTTriMap = (UINT8 *) DrRDdr2ODTTri2D;
- }
-
- CurrentChannel->DctEccDqsLike = 0x0504;
- CurrentChannel->DctEccDqsScale = 0;
- CurrentChannel->DctAddrTmg = AddrTmgCTL;
- CurrentChannel->DctOdcCtl = DctOdcCtl;
- CurrentChannel->SlowMode = SlowMode;
-
- return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ardk/DR/mardr3.c b/src/vendorcode/amd/agesa/Proc/Mem/Ardk/DR/mardr3.c
deleted file mode 100644
index 5335b49..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ardk/DR/mardr3.c
+++ /dev/null
@@ -1,429 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mardr3.c
- *
- * Memory Controller, registered dimms
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ardk)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/* This file contains routine that add platform specific support AM3 */
-
-
-#include "AGESA.h"
-#include "ma.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mu.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_ARDK_DR_MARDR3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-STATIC CONST UINT8 ROMDATA DrRDdr3CLKDis[] = {0x00, 0x00, 0xC0, 0x30, 0x0C, 0x03, 0x00, 0x00};
-
-// Even chip select maps to M[B,A]_CKE[0]
-// Odd chip select maps to M[B,A]_CKE[1]
-STATIC CONST UINT8 ROMDATA DrRDdr3CKETri[] = {0x55, 0xAA};
-
-// 2 dimms per channel
-// Dimm 0: BP_MEMODTx[2,0]
-// Dimm 1: BP_MEMODTx[3,1]
-STATIC CONST UINT8 ROMDATA DrRDdr3ODTTri2D[] = {0x03, 0x0C, 0x32, 0xC8};
-// 3 dimms per channel
-// Dimm 0: BP_MEMODTx[0]
-// Dimm 1: BP_MEMODTx[3,1]
-// Dimm 2: BP_MEMODTx[2]
-STATIC CONST UINT8 ROMDATA DrRDdr3ODTTri3D[] = {0x03, 0x0C, 0x30, 0xC8};
-// 4 dimms per channel
-// Dimm 0: BP_MEMODTx[0]
-// Dimm 1: BP_MEMODTx[1]
-// Dimm 2: BP_MEMODTx[2]
-// Dimm 3: BP_MEMODTx[3]
-STATIC CONST UINT8 ROMDATA DrRDdr3ODTTri4D[] = {0x03, 0x0C, 0x30, 0xC0};
-
-// BIOS must not tri-state chip select pin corresponding to the second chip
-// select of a single rank registered dimm
-STATIC CONST UINT8 ROMDATA DrRDdr3CSTri[] = {0x01, 0x03, 0x04, 0x0C, 0x10, 0x30, 0x40, 0xC0};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for DR DDR3 L1 system
- *
- * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE
- * @param[in] SocketID Socket number
- * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT
- *
- * @return AGESA_SUCCESS
- * @return CurrentChannel->MemClkDisMap Points this pointer to RB MemClkDis table
- * @return CurrentChannel->ChipSelTriMap Points this pointer to RB CS table
- * @return CurrentChannel->CKETriMap Points this pointer to RB ODT table
- * @return CurrentChannel->ODTTriMap Points this pointer to RB CKE table
- * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC
- * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte
- * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel
- * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel
- * @return CurrentChannel->SlowMode Slow Mode
- *
- *
- */
-
-AGESA_STATUS
-MemAGetPsCfgRDr3 (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- )
-{
- STATIC CONST ADV_R_PSCFG_ENTRY PSCfg2DIMMs[] = {
- {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
- 0x00000000, 0x0000, 1},
- {DDR800_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
- 0x00000000, 0x0040, 1},
- {DDR800_FREQUENCY, ANY_DIMM0 + ANY_DIMM1, \
- 0x00000000, 0x4004, 2},
- {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
- 0x003C3C3C, 0x0000,1},
- {DDR1066_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
- 0x003C3C3C, 0x0040, 1},
- {DDR1066_FREQUENCY, ANY_DIMM0 + ANY_DIMM1, \
- 0x003A3C3A, 0x4004, 2},
- {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
- 0x003A3A3A, 0x0000, 1},
- {DDR1333_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
- 0x003A3A3A, 0x0040, 1},
- {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
- 0x00383A38, 0x4040, 2},
- {DDR1333_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
- 0x00383A38, 0x4004, 2},
- {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
- 0x00373937, 0x0000, 1},
- {DDR1600_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
- 0x00373937, 0x0040, 1},
- {DDR1600_FREQUENCY, ANY_DIMM0 + ANY_DIMM1, \
- 0x00353935, 0x4004, 2}
- };
-
- STATIC CONST ADV_R_PSCFG_ENTRY PSCfg3DIMMs[] = {
- {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x00000000, 0x0000, 1},
- {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x00000000, 0x4040, 2},
- {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + ANY_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x00380038, 0x4004, 3},
- {DDR800_FREQUENCY, QR_DIMM1, \
- 0x00000000, 0x0040, 1},
- {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x00000000, 0x4004, 2},
- {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x003C3C3C, 0x0000, 1},
- {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x003A3C3A, 0x4040, 2},
- {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x00373C37, 0x4040, 3},
- {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x00373C37, 0x4004, 3},
- {DDR1066_FREQUENCY, QR_DIMM1, \
- 0x003C3C3C, 0x0040, 1},
- {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x003A3C3A, 0x4004, 2},
- {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x003A3A3A, 0x0000, 1},
- {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x00383A38, 0x4040, 2},
- {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + ANY_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x00343A34, 0x4004, 3},
- {DDR1333_FREQUENCY, QR_DIMM1, \
- 0x003A3A3A, 0x0040, 1},
- {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x00383A38, 0x4004, 2},
- {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x00393939, 0x0000, 1},
- {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x00363936, 0x4040, 2},
- {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + ANY_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x00303930, 0x4004, 3},
- {DDR1600_FREQUENCY, QR_DIMM1, \
- 0x00393939, 0x0040, 1},
- {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x00363936, 0x4004, 2}
- };
-
- STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg2DIMMsWlODT[] = {
- {SR_DIMM0, {0x01, 0x00, 0x00, 0x00}, 1},
- {DR_DIMM0, {0x04, 0x00, 0x00, 0x00}, 1},
- {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1},
- {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1},
- {QR_DIMM1, {0x00, 0x0A, 0x00, 0x00}, 1},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2},
- {SR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2},
- {DR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2},
- {QR_DIMM0 + SR_DIMM1, {0x03, 0x07, 0x06, 0x00}, 2},
- {QR_DIMM0 + DR_DIMM1, {0x03, 0x07, 0x06, 0x00}, 2},
- {QR_DIMM0 + QR_DIMM1, {0x0B, 0x07, 0x0E, 0x0D}, 2}
- };
-
- STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg3DIMMsWlODT[] = {
- {SR_DIMM2 + DR_DIMM2, {0x00, 0x00, 0x04, 0x00}, 1},
- {SR_DIMM0 + DR_DIMM0, {0x01, 0x02, 0x00, 0x00}, 1},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, {0x05, 0x00, 0x05, 0x00}, 2},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x07, 0x07, 0x07, 0x00}, 3},
- {QR_DIMM1, {0x00, 0x0A, 0x00, 0x0A}, 1},
- {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x00, 0x06, 0x0E, 0x0C}, 2},
- {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2},
- {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x0F, 0x07, 0x0F, 0x0D}, 3}
- };
-
- STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg4DIMMsWlODT[] = {
- {ANY_DIMM3, {0x00, 0x00, 0x00, 0x08}, 1},
- {ANY_DIMM2 + ANY_DIMM3, {0x00, 0x00, 0x0C, 0x0C}, 2},
- {ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, {0x00, 0x0E, 0x0E, 0x0E}, 3},
- {ANY_DIMM0 + ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, {0x0F, 0x0F, 0x0F, 0x0F}, 4}
- };
- UINT16 i;
- UINT16 j;
- UINT8 MaxDimmPerCH;
- UINT8 Dimms;
- UINT16 Speed;
- UINT16 DIMMRankType;
- UINT16 _DIMMRankType;
- UINT8 DimmTpMatch;
- UINT32 AddrTmgCTL;
- UINT32 DctOdcCtl;
- UINT16 RC2RC8;
- BOOLEAN SlowMode;
- UINT8 PSCfgSize;
- UINT8 PSCfgWlODTSize;
- UINT8 PhyWLODT[4];
- CONST ADV_R_PSCFG_ENTRY *PSCfgPtr;
- CONST ADV_R_PSCFG_WL_ODT_ENTRY *PSCfgWlODTPtr;
- UINT8 *DimmsPerChPtr;
-
- AddrTmgCTL = 0;
- DctOdcCtl = 0;
- RC2RC8 = 0;
- SlowMode = FALSE;
- ASSERT (MemData != NULL);
- PhyWLODT[0] = 0x0F;
- PhyWLODT[1] = 0x0F;
- PhyWLODT[2] = 0x0F;
- PhyWLODT[3] = 0x0F;
- if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) {
- return AGESA_UNSUPPORTED;
- }
- if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
- return AGESA_UNSUPPORTED;
- }
- if (CurrentChannel->RegDimmPresent != CurrentChannel->ChDimmValid) {
- return AGESA_UNSUPPORTED;
- }
- // Prepare inputs
- Dimms = CurrentChannel->Dimms;
- Speed = CurrentChannel->DCTPtr->Timings.Speed;
-
- DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID);
- if (DimmsPerChPtr != NULL) {
- MaxDimmPerCH = *DimmsPerChPtr;
- } else {
- MaxDimmPerCH = 2;
- }
-
- DIMMRankType = MemAGetPsRankType (CurrentChannel);
-
- if (MaxDimmPerCH == 4) {
- PSCfgPtr = NULL;
- PSCfgSize = NULL;
- PSCfgWlODTPtr = PSCfg4DIMMsWlODT;
- PSCfgWlODTSize = sizeof (PSCfg4DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
- } else if (MaxDimmPerCH == 3) {
- PSCfgPtr = PSCfg3DIMMs;
- PSCfgSize = sizeof (PSCfg3DIMMs) / sizeof (ADV_R_PSCFG_ENTRY);
- PSCfgWlODTPtr = PSCfg3DIMMsWlODT;
- PSCfgWlODTSize = sizeof (PSCfg3DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
- } else {
- PSCfgPtr = PSCfg2DIMMs;
- PSCfgSize = sizeof (PSCfg2DIMMs) / sizeof (ADV_R_PSCFG_ENTRY);
- PSCfgWlODTPtr = PSCfg2DIMMsWlODT;
- PSCfgWlODTSize = sizeof (PSCfg2DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
- }
-
- // AddrTmgCTL and DctOdcCtl
- if (MaxDimmPerCH != 4) {
- for (i = 0; i < PSCfgSize; i++, PSCfgPtr++) {
- if ((Speed != PSCfgPtr->Speed) || (Dimms != PSCfgPtr->Dimms)) {
- continue;
- }
- DimmTpMatch = 0;
- _DIMMRankType = DIMMRankType & PSCfgPtr->DIMMRankType;
- for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
- if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
- DimmTpMatch++;
- }
- }
- if (DimmTpMatch == PSCfgPtr->Dimms) {
- AddrTmgCTL = PSCfgPtr->AddrTmg;
- DctOdcCtl = 0x00223222;
- RC2RC8 = PSCfgPtr->RC2RC8;
- break;
- }
- }
- }
-
- //
- // Overrides and/or exceptions
- //
- DimmTpMatch = 0;
- for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
- if ((DIMMRankType & (UINT16) 0x03 << (j << 2)) != 0) {
- DimmTpMatch++;
- }
- }
- if (MaxDimmPerCH == 4) {
- if (DimmTpMatch > 0) {
- DctOdcCtl = 0x00223222;
- if ((Speed == DDR800_FREQUENCY) && (DimmTpMatch == 1)) {
- DctOdcCtl = 0x00113222;
- }
- }
- if (DimmTpMatch >= 3) {
- AddrTmgCTL |= 0x002F0000;
- }
- if (DimmTpMatch >= 2) {
- RC2RC8 = 0x4040;
- }
- } else {
- if ((Dimms == 1) && (DimmTpMatch == 1)) {
- DctOdcCtl = 0x00113222;
- }
- }
-
- //RC2 and RC8
- for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
- // CtrlWrd02(s) will contain the info. of SPD byte 63 after MemTDIMMPresence3 execution.
- if (CurrentChannel->CtrlWrd02[j] > 0) {
- if (CurrentChannel->CtrlWrd02[j] == 1) {
- // Store real RC2 and RC8 value (High byte) into CtrlWrd02(s) and CtrlWrd08(s).
- CurrentChannel->CtrlWrd02[j] = (UINT8) (RC2RC8 >> 12) & 0x000F;
- CurrentChannel->CtrlWrd08[j] = (UINT8) (RC2RC8 >> 8) & 0x000F;
- } else {
- // Store real RC2 and RC8 value (low byte) into CtrlWrd02(s) and CtrlWrd08(s).
- CurrentChannel->CtrlWrd02[j] = (UINT8) (RC2RC8 >> 4) & 0x000F;
- CurrentChannel->CtrlWrd08[j] = (UINT8) RC2RC8 & 0x000F;
- }
- }
- }
-
-
- //WLODT
- for (i = 0; i < PSCfgWlODTSize; i++, PSCfgWlODTPtr++) {
- if (Dimms != PSCfgWlODTPtr->Dimms) {
- continue;
- }
- DimmTpMatch = 0;
- _DIMMRankType = DIMMRankType & PSCfgWlODTPtr->DIMMRankType;
- for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
- if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
- DimmTpMatch++;
- }
- }
- if (DimmTpMatch == PSCfgWlODTPtr->Dimms) {
- PhyWLODT[0] = PSCfgWlODTPtr->PhyWrLvOdt[0];
- PhyWLODT[1] = PSCfgWlODTPtr->PhyWrLvOdt[1];
- PhyWLODT[2] = PSCfgWlODTPtr->PhyWrLvOdt[2];
- PhyWLODT[3] = PSCfgWlODTPtr->PhyWrLvOdt[3];
- break;
- }
- }
-
- // Set ProcODT
- DctOdcCtl |= 0x20000000;
-
- CurrentChannel->MemClkDisMap = (UINT8 *) DrRDdr3CLKDis;
- CurrentChannel->CKETriMap = (UINT8 *) DrRDdr3CKETri;
- CurrentChannel->ChipSelTriMap = (UINT8 *) DrRDdr3CSTri;
-
- switch (MaxDimmPerCH) {
- case 3:
- CurrentChannel->ODTTriMap = (UINT8 *) DrRDdr3ODTTri3D;
- break;
- case 4:
- CurrentChannel->ODTTriMap = (UINT8 *) DrRDdr3ODTTri4D;
- break;
- default:
- CurrentChannel->ODTTriMap = (UINT8 *) DrRDdr3ODTTri2D;
- }
-
- CurrentChannel->DctAddrTmg = AddrTmgCTL;
- CurrentChannel->DctOdcCtl = DctOdcCtl;
- for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
- CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
- }
- CurrentChannel->SlowMode = SlowMode;
-
- return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ardk/DR/maudr3.c b/src/vendorcode/amd/agesa/Proc/Mem/Ardk/DR/maudr3.c
deleted file mode 100644
index 6317e56..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ardk/DR/maudr3.c
+++ /dev/null
@@ -1,260 +0,0 @@
-/* $NoKeywords:$ */
-/*
- * @file
- *
- * maudr3.c
- *
- * Platform specific settings for DR DDR3 unbuffered dimms
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ardk)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/* This file contains routine that add platform specific support AM3 */
-
-
-#include "AGESA.h"
-#include "mport.h"
-#include "PlatformMemoryConfiguration.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_ARDK_DR_MAUDR3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-STATIC CONST UINT8 ROMDATA DrUDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
-// Even chip select maps to M[B,A]_CKE[0]
-// Odd chip select maps to M[B,A]_CKE[1]
-STATIC CONST UINT8 ROMDATA DrUDdr3CKETri[] = {0x55, 0xAA};
-// Bit 0: M[B,A]0_ODT[0]
-// Bit 1: M[B,A]1_ODT[0]
-// Bit 2: M[B,A]0_ODT[1]
-// Bit 3: M[B,A]1_ODT[1]
-STATIC CONST UINT8 ROMDATA DrUDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
-// Bit 0: M[B,A]0_CS_H/L[0]
-// Bit 1: M[B,A]0_CS_H/L[1]
-// Bit 2: M[B,A]0_CS_H/L[2]
-// Bit 3: M[B,A]0_CS_H/L[3]
-STATIC CONST UINT8 ROMDATA DrUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for DR DDR3 Unbuffered dimms
- *
- *
- * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE
- * @param[in] SocketID Socket number
- * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT
- *
- * @return AGESA_SUCCESS
- * @return CurrentChannel->MemClkDisMap Points this pointer to RB MemClkDis table
- * @return CurrentChannel->ChipSelTriMap Points this pointer to RB CS table
- * @return CurrentChannel->CKETriMap Points this pointer to RB ODT table
- * @return CurrentChannel->ODTTriMap Points this pointer to RB CKE table
- * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC
- * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte
- * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel
- * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel
- * @return CurrentChannel->SlowMode Slow Mode
- *
- */
-
-AGESA_STATUS
-MemAGetPsCfgUDr3 (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- )
-{
- STATIC CONST PSCFG_ENTRY PSCfg1Dimm[] = {
- {DDR800_FREQUENCY, 0x10, 0x003B0000, 0x20113222},
- {DDR1066_FREQUENCY, 0x10, 0x00380000, 0x20113222},
- {DDR1333_FREQUENCY, 0x10, 0x00360000, 0x20113222},
- {DDR1600_FREQUENCY, 0x10, 0x00340000, 0x20113222}
- };
- STATIC CONST PSCFG_ENTRY PSCfg2Dimm[] = {
- {DDR800_FREQUENCY, 0xFF, 0x00390039, 0x20223323},
- {DDR1066_FREQUENCY, 0xFF, 0x00350037, 0x20223323},
- {DDR1333_FREQUENCY, 0xFF, 0x00000035, 0x20223323},
- {DDR1600_FREQUENCY, 0xFF, 0x00000033, 0x20223323}
- };
-
- STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfgDIMMWlODT[] = {
- {SR_DIMM0, {0x01, 0x00, 0x00, 0x00}, 1},
- {DR_DIMM0, {0x04, 0x00, 0x00, 0x00}, 1},
- {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1},
- {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}
- };
-
- UINT16 i;
- UINT16 j;
- UINT8 Loads;
- UINT8 Dimms;
- UINT16 Speed;
- UINT16 DIMMRankType;
- UINT16 _DIMMRankType;
- UINT32 AddrTmgCTL;
- UINT32 DctOdcCtl;
- UINT8 PhyWLODT[4];
- BOOLEAN SlowMode;
- UINT8 DimmTpMatch;
-
- ASSERT (MemData != 0);
- ASSERT (CurrentChannel != 0);
- AddrTmgCTL = 0;
- DctOdcCtl = 0;
- PhyWLODT[0] = 0x0F;
- PhyWLODT[1] = 0x0F;
- PhyWLODT[2] = 0x0F;
- PhyWLODT[3] = 0x0F;
-
- if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) {
- return AGESA_UNSUPPORTED;
- }
- if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
- return AGESA_UNSUPPORTED;
- }
- if (CurrentChannel->RegDimmPresent != 0) {
- return AGESA_UNSUPPORTED;
- }
- // Prepare inputs
- Loads = CurrentChannel->Loads;
- Dimms = CurrentChannel->Dimms;
- Speed = CurrentChannel->DCTPtr->Timings.Speed;
-
- DIMMRankType = MemAGetPsRankType (CurrentChannel);
-
- if ((Speed == DDR1333_FREQUENCY || Speed == DDR1600_FREQUENCY) && (Dimms == 2)) {
- SlowMode = TRUE; // 2T
- } else if ((Speed == DDR1600_FREQUENCY) && (Dimms == 1) && (Loads >= 16)) {
- SlowMode = TRUE; // 2T
- } else {
- SlowMode = FALSE; // 1T
- }
-
- if (Dimms == 1) {
- for (i = 0; i < GET_SIZE_OF (PSCfg1Dimm); i++) {
- if (Speed == PSCfg1Dimm[i].Speed) {
- if (Loads >= PSCfg1Dimm[i].Loads) {
- AddrTmgCTL = PSCfg1Dimm[i].AddrTmg;
- DctOdcCtl = PSCfg1Dimm[i].Odc;
- } else {
- DctOdcCtl = 0x20113222;
- }
- break;
- }
- }
- ASSERT (i < GET_SIZE_OF (PSCfg1Dimm));
- } else {
- for (i = 0; i < GET_SIZE_OF (PSCfg2Dimm); i++) {
- if (Speed == PSCfg2Dimm[i].Speed) {
- if (Loads <= PSCfg2Dimm[i].Loads) {
- AddrTmgCTL = PSCfg2Dimm[i].AddrTmg;
- DctOdcCtl = PSCfg2Dimm[i].Odc;
- break;
- }
- }
- }
- ASSERT (i < GET_SIZE_OF (PSCfg2Dimm));
- }
-
- // WL ODT
- for (i = 0; i < GET_SIZE_OF (PSCfgDIMMWlODT); i++) {
- if (Dimms != PSCfgDIMMWlODT[i].Dimms) {
- continue;
- }
- DimmTpMatch = 0;
- _DIMMRankType = DIMMRankType & PSCfgDIMMWlODT[i].DIMMRankType;
- for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
- if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
- DimmTpMatch++;
- }
- }
- if (DimmTpMatch == PSCfgDIMMWlODT[i].Dimms) {
- PhyWLODT[0] = PSCfgDIMMWlODT[i].PhyWrLvOdt[0];
- PhyWLODT[1] = PSCfgDIMMWlODT[i].PhyWrLvOdt[1];
- PhyWLODT[2] = PSCfgDIMMWlODT[i].PhyWrLvOdt[2];
- PhyWLODT[3] = PSCfgDIMMWlODT[i].PhyWrLvOdt[3];
- break;
- }
- }
-
- CurrentChannel->MemClkDisMap = (UINT8 *) DrUDdr3CLKDis;
- CurrentChannel->CKETriMap = (UINT8 *) DrUDdr3CKETri;
- CurrentChannel->ODTTriMap = (UINT8 *) DrUDdr3ODTTri;
- CurrentChannel->ChipSelTriMap = (UINT8 *) DrUDdr3CSTri;
-
- CurrentChannel->DctEccDqsLike = 0x0403;
- CurrentChannel->DctEccDqsScale = 0x70;
- CurrentChannel->DctAddrTmg = AddrTmgCTL;
- CurrentChannel->DctOdcCtl = DctOdcCtl;
- for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
- CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
- }
- CurrentChannel->SlowMode = SlowMode;
-
- return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ardk/HY/marhy3.c b/src/vendorcode/amd/agesa/Proc/Mem/Ardk/HY/marhy3.c
deleted file mode 100644
index 8b87ea9..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ardk/HY/marhy3.c
+++ /dev/null
@@ -1,578 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * marhy3.c
- *
- * Memory Controller, registered dimms
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ardk)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/* This file contains routine that add platform specific support AM3 */
-
-
-#include "AGESA.h"
-#include "ma.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mu.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_ARDK_HY_MARHY3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-STATIC CONST UINT8 ROMDATA HyRDdr3CLKDis[] = {0xFF, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00};
-
-// Even chip select maps to M[B,A]_CKE[0]
-// Odd chip select maps to M[B,A]_CKE[1]
-STATIC CONST UINT8 ROMDATA HyRDdr3CKETri[] = {0x55, 0xAA};
-
-// 2 dimms per channel
-// Dimm 0: BP_MEMODTx[2,0]
-// Dimm 1: BP_MEMODTx[3,1]
-STATIC CONST UINT8 ROMDATA HyRDdr3ODTTri2D[] = {0x03, 0x0C, 0x32, 0xC8};
-// 3 dimms per channel
-// Dimm 0: BP_MEMODTx[0]
-// Dimm 1: BP_MEMODTx[3,1]
-// Dimm 2: BP_MEMODTx[2]
-STATIC CONST UINT8 ROMDATA HyRDdr3ODTTri3D[] = {0x03, 0x0C, 0x30, 0xC8};
-// 4 dimms per channel
-// Dimm 0: BP_MEMODTx[0]
-// Dimm 1: BP_MEMODTx[1]
-// Dimm 2: BP_MEMODTx[2]
-// Dimm 3: BP_MEMODTx[3]
-STATIC CONST UINT8 ROMDATA HyRDdr3ODTTri4D[] = {0x03, 0x0C, 0x30, 0xC0};
-
-// BIOS must not tri-state chip select pin corresponding to the second chip
-// select of a single rank registered dimm
-STATIC CONST UINT8 ROMDATA HyRDdr3CSTri[] = {0x01, 0x03, 0x04, 0x0C, 0x10, 0x30, 0x40, 0xC0};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for HY DDR3 L1 system
- *
- * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE
- * @param[in] SocketID Socket number
- * @param[in] *CurrentChannel Pointer to CH_DEF_STRUCT
- *
- * @return AGESA_SUCCESS
- * @return CurrentChannel->MemClkDisMap Points this pointer to HY MemClkDis table
- * @return CurrentChannel->ChipSelTriMap Points this pointer to HY CS table
- * @return CurrentChannel->CKETriMap Points this pointer to HY ODT table
- * @return CurrentChannel->ODTTriMap Points this pointer to HY CKE table
- * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC
- * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte
- * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel
- * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel
- * @return CurrentChannel->SlowMode Slow Mode
- *
- */
-
-AGESA_STATUS
-MemAGetPsCfgRHy3 (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- )
-{
- //
- // Address Timings and Drive Strengths for 1 DIMM per channel or 2 Dimms per Channel
- //
- // Code searches table for matching speed, then matches the current dimm
- // population and # of dimms to current config and programs the Addr Timing and RC2/RC2
- //
- // Frequency, Dimm Config ,
- // Address Timing Value(F2x[1, 0]9C_x04), RC2/RC8 Value, # Dimms to match
- //
- STATIC CONST ADV_R_PSCFG_ENTRY PSCfg2DIMMs[] = {
- {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
- 0x00000000, 0x0000, 1},
- {DDR800_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
- 0x00000000, 0x0040, 1},
- {DDR800_FREQUENCY, ANY_DIMM0 + ANY_DIMM1, \
- 0x00000000, 0x4004, 2},
- {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
- 0x003C3C3C, 0x0000,1},
- {DDR1066_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
- 0x003C3C3C, 0x0040, 1},
- {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
- 0x003A3C3A, 0x4004, 2},
- {DDR1066_FREQUENCY, QR_DIMM0 + ANY_DIMM1, \
- 0x003A3C3A, 0x4004, 2},
- {DDR1066_FREQUENCY, ANY_DIMM0 + QR_DIMM1, \
- 0x003A3C3A, 0x4004, 2},
- {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
- 0x003A3A3A, 0x0000, 1},
- {DDR1333_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
- 0x003A3A3A, 0x0040, 1},
- {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
- 0x00383A38, 0x4040, 2},
- {DDR1333_FREQUENCY, QR_DIMM0 + ANY_DIMM1, \
- 0x00383A38, 0x4004, 2},
- {DDR1333_FREQUENCY, ANY_DIMM0 + QR_DIMM1, \
- 0x00383A38, 0x4004, 2},
- {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
- 0x00373937, 0x0000, 1},
- {DDR1600_FREQUENCY, QR_DIMM0 + QR_DIMM1, \
- 0x00373937, 0x0040, 1},
- {DDR1600_FREQUENCY, ANY_DIMM0 + ANY_DIMM1, \
- 0x00353935, 0x4004, 2}
- };
- //
- // Address Timings and Drive Strengths for 3 DIMMs per channel
- //
- // Code searches table for matching speed, then matches the current dimm
- // population and # of dimms to current config and programs the Addr Timing and RC2/RC2
- //
- // Frequency, Dimm Config ,
- // Address Timing Value(F2x[1, 0]9C_x04), RC2/RC8 Value, # Dimms to match
- //
- STATIC CONST ADV_R_PSCFG_ENTRY PSCfg3DIMMs[] = {
- {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x00000000, 0x0000, 1},
- {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x00000000, 0x4040, 2},
- {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + ANY_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x00380038, 0x4004, 3},
- {DDR800_FREQUENCY, QR_DIMM1, \
- 0x00000000, 0x0040, 1},
- {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x00000000, 0x4004, 2},
- {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x003C3C3C, 0x0000, 1},
- {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x003A3C3A, 0x4040, 2},
- {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x00373C37, 0x4040, 3},
- {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x00373C37, 0x4004, 3},
- {DDR1066_FREQUENCY, QR_DIMM1, \
- 0x003C3C3C, 0x0040, 1},
- {DDR1066_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x003A3C3A, 0x4004, 2},
- {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x003A3A3A, 0x0000, 1},
- {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x00383A38, 0x4040, 2},
- {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + ANY_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x00343A34, 0x4004, 3},
- {DDR1333_FREQUENCY, QR_DIMM1, \
- 0x003A3A3A, 0x0040, 1},
- {DDR1333_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x00383A38, 0x4004, 2},
- {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x00393939, 0x0000, 1},
- {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x00363936, 0x4040, 2},
- {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + ANY_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x00303930, 0x4004, 3},
- {DDR1600_FREQUENCY, QR_DIMM1, \
- 0x00393939, 0x0040, 1},
- {DDR1600_FREQUENCY, SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x00363936, 0x4004, 2}
- };
- //
- // DIMM ODT Pattern (1 or 2 DIMMs per channel)
- //
- // Dimm Config ,
- // Fn2_9C 180, Fn2_9C 181, Fn2_9C 182, Fn2_9C 183, # Dimms to match
- //
- STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg2DIMMsODT[] = {
- {SR_DIMM0, \
- 0x00000000, 0x00000000, 0x00000001, 0x00000000, 1},
- {DR_DIMM0, \
- 0x00000000, 0x00000000, 0x00000104, 0x00000000, 1},
- {QR_DIMM0, \
- 0x00000000, 0x00000000, 0x00000505, 0x00000505, 1},
- {SR_DIMM1, \
- 0x00000000, 0x00000000, 0x00020000, 0x00000000, 1},
- {DR_DIMM1, \
- 0x00000000, 0x00000000, 0x02080000, 0x00000000, 1},
- {QR_DIMM1, \
- 0x00000000, 0x00000000, 0x0A0A0000, 0x0A0A0000, 1},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
- 0x01010202, 0x00000000, 0x09030603, 0x00000000, 2},
- {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, \
- 0x01010A0A, 0x01010000, 0x01030E0B, 0x01090000, 2},
- {QR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
- 0x05050202, 0x00000202, 0x0D070203, 0x00000206, 2},
- {QR_DIMM0 + QR_DIMM1, \
- 0x05050A0A, 0x05050A0A, 0x05070A0B, 0x050D0A0E, 2}
- };
- // DIMM ODT Pattern (3 DIMMs per channel)
- //
- // Dimm Config ,
- // Fn2_9C 180, Fn2_9C 181, Fn2_9C 182, Fn2_9C 183, # Dimms to match
- //
- STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg3DIMMsODT[] = {
- {SR_DIMM2 + DR_DIMM2, \
- 0x00000000, 0x00000000, 0x00000000, 0x00000404, 1},
- {SR_DIMM0 + DR_DIMM0, \
- 0x00000000, 0x00000000, 0x00000101, 0x00000000, 1},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, \
- 0x00000404, 0x00000101, 0x00000405, 0x00000105, 2},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x05050606, 0x00000303, 0x0D070607, 0x00000307, 3},
- {QR_DIMM1, \
- 0x00000000, 0x00000000, 0x080A0000, 0x020A0000, 1},
- {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x04040000, 0x04040A0A, 0x04060000, 0x040C0A0E, 2},
- {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, \
- 0x01010A0A, 0x01010000, 0x01030A0B, 0x01090000, 2},
- {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, \
- 0x05050E0E, 0x05050B0B, 0x05070E0F, 0x050D0B0F, 3}
- };
- //
- // DIMM ODT Pattern (4 DIMMs per channel)
- //
- // Dimm Config ,
- // Fn2_9C 180, Fn2_9C 181, Fn2_9C 182, Fn2_9C 183, # Dimms to match
- //
- STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg4DIMMsODT[] = {
- {ANY_DIMM3, \
- 0x00000000, 0x00000000, 0x00000000, 0x08080000, 1},
- {ANY_DIMM2 + ANY_DIMM3, \
- 0x00000000, 0x04040808, 0x00000000, 0x0C0C0C0C, 2},
- {ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, \
- 0x0C0C0000, 0x06060A0A, 0x0E0E0000, 0x0E0E0E0E, 3},
- {ANY_DIMM0 + ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, \
- 0x0D0D0E0E, 0x07070B0B, 0x0F0F0F0F, 0x0F0F0F0F, 4}
- };
- //
- // DIMM Write Leveling ODT Pattern for 1 or 2 Dimms Per Channel
- //
- // Dimm Config, WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm, # Dimms to match
- //
- STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg2DIMMsWlODT[] = {
- {SR_DIMM0, {0x01, 0x00, 0x00, 0x00}, 1},
- {DR_DIMM0, {0x04, 0x00, 0x00, 0x00}, 1},
- {QR_DIMM0, {0x05, 0x00, 0x00, 0x00}, 1},
- {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1},
- {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1},
- {QR_DIMM1, {0x00, 0x0A, 0x00, 0x00}, 1},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2},
- {SR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2},
- {DR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2},
- {QR_DIMM0 + SR_DIMM1, {0x03, 0x07, 0x06, 0x00}, 2},
- {QR_DIMM0 + DR_DIMM1, {0x03, 0x07, 0x06, 0x00}, 2},
- {QR_DIMM0 + QR_DIMM1, {0x0B, 0x07, 0x0E, 0x0D}, 2}
- };
- //
- // DIMM Write Leveling ODT Pattern 3 Dimms Per Channel
- //
- // Dimm Config, WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm, # Dimms to match
- //
- STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg3DIMMsWlODT[] = {
- {SR_DIMM2 + DR_DIMM2, {0x00, 0x00, 0x04, 0x00}, 1},
- {SR_DIMM0 + DR_DIMM0, {0x01, 0x02, 0x00, 0x00}, 1},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, {0x05, 0x00, 0x05, 0x00}, 2},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x07, 0x07, 0x07, 0x00}, 3},
- {QR_DIMM1, {0x00, 0x0A, 0x00, 0x0A}, 1},
- {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x00, 0x06, 0x0E, 0x0C}, 2},
- {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2},
- {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x0F, 0x07, 0x0F, 0x0D}, 3}
- };
- //
- // DIMM Write Leveling ODT Pattern 4 Dimms Per Channel
- //
- // Dimm Config, WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm, # Dimms to match
- //
- STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg4DIMMsWlODT[] = {
- {ANY_DIMM3, {0x00, 0x00, 0x00, 0x08}, 1},
- {ANY_DIMM2 + ANY_DIMM3, {0x00, 0x00, 0x0C, 0x0C}, 2},
- {ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, {0x00, 0x0E, 0x0E, 0x0E}, 3},
- {ANY_DIMM0 + ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, {0x0F, 0x0F, 0x0F, 0x0F}, 4}
- };
-
- UINT16 i;
- UINT16 j;
- UINT8 MaxDimmPerCH;
- UINT8 Dimms;
- UINT16 Speed;
- UINT16 DIMMRankType;
- UINT16 _DIMMRankType;
- UINT8 DimmTpMatch;
- UINT32 AddrTmgCTL;
- UINT32 DctOdcCtl;
- UINT16 RC2RC8;
- UINT32 PhyRODTCSLow;
- UINT32 PhyRODTCSHigh;
- UINT32 PhyWODTCSLow;
- UINT32 PhyWODTCSHigh;
- BOOLEAN SlowMode;
- UINT8 PSCfgSize;
- UINT8 PSCfgODTSize;
- UINT8 PSCfgWlODTSize;
- UINT8 PhyWLODT[4];
-
- CONST ADV_R_PSCFG_ENTRY *PSCfgPtr;
- CONST ADV_PSCFG_ODT_ENTRY *PSCfgODTPtr;
- CONST ADV_R_PSCFG_WL_ODT_ENTRY *PSCfgWlODTPtr;
- UINT8 *DimmsPerChPtr;
-
- ASSERT (MemData != NULL);
- ASSERT (CurrentChannel != NULL);
-
- AddrTmgCTL = 0;
- DctOdcCtl = 0;
- RC2RC8 = 0;
- PhyRODTCSLow = 0;
- PhyRODTCSHigh = 0;
- PhyWODTCSLow = 0;
- PhyWODTCSHigh = 0;
- SlowMode = FALSE;
- PhyWLODT[0] = 0x0F;
- PhyWLODT[1] = 0x0F;
- PhyWLODT[2] = 0x0F;
- PhyWLODT[3] = 0x0F;
-
- if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_HY) == 0) {
- return AGESA_UNSUPPORTED;
- }
- if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
- return AGESA_UNSUPPORTED;
- }
- if (CurrentChannel->RegDimmPresent == 0) {
- return AGESA_UNSUPPORTED;
- }
-
- // Prepare inputs
- Dimms = CurrentChannel->Dimms;
- Speed = CurrentChannel->DCTPtr->Timings.Speed;
- DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID);
- if (DimmsPerChPtr != NULL) {
- MaxDimmPerCH = *DimmsPerChPtr;
- } else {
- MaxDimmPerCH = 2;
- }
-
- DIMMRankType = MemAGetPsRankType (CurrentChannel);
-
- if (MaxDimmPerCH == 4) {
- PSCfgPtr = NULL;
- PSCfgSize = NULL;
- PSCfgODTPtr = PSCfg4DIMMsODT;
- PSCfgWlODTPtr = PSCfg4DIMMsWlODT;
- PSCfgODTSize = sizeof (PSCfg4DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY);
- PSCfgWlODTSize = sizeof (PSCfg4DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
- } else if (MaxDimmPerCH == 3) {
- PSCfgPtr = PSCfg3DIMMs;
- PSCfgSize = sizeof (PSCfg3DIMMs) / sizeof (ADV_R_PSCFG_ENTRY);
- PSCfgODTPtr = PSCfg3DIMMsODT;
- PSCfgWlODTPtr = PSCfg3DIMMsWlODT;
- PSCfgODTSize = sizeof (PSCfg3DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY);
- PSCfgWlODTSize = sizeof (PSCfg3DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
- } else {
- PSCfgPtr = PSCfg2DIMMs;
- PSCfgSize = sizeof (PSCfg2DIMMs) / sizeof (ADV_R_PSCFG_ENTRY);
- PSCfgODTPtr = PSCfg2DIMMsODT;
- PSCfgWlODTPtr = PSCfg2DIMMsWlODT;
- PSCfgODTSize = sizeof (PSCfg2DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY);
- PSCfgWlODTSize = sizeof (PSCfg2DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
- }
-
- // AddrTmgCTL and DctOdcCtl
- if (MaxDimmPerCH != 4) {
- for (i = 0; i < PSCfgSize; i++, PSCfgPtr++) {
- if ((Speed != PSCfgPtr->Speed) || (Dimms != PSCfgPtr->Dimms)) {
- continue;
- }
- DimmTpMatch = 0;
- _DIMMRankType = DIMMRankType & PSCfgPtr->DIMMRankType;
- for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
- if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
- DimmTpMatch++;
- }
- }
- if (DimmTpMatch == PSCfgPtr->Dimms) {
- AddrTmgCTL = PSCfgPtr->AddrTmg;
- DctOdcCtl = 0x00223222;
- RC2RC8 = PSCfgPtr->RC2RC8;
- break;
- }
- }
- }
-
- //
- // Overrides and/or exceptions
- //
- DimmTpMatch = 0;
- for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
- if ((DIMMRankType & (UINT16) 0x03 << (j << 2)) != 0) {
- DimmTpMatch++;
- }
- }
- if (MaxDimmPerCH == 4) {
- if (DimmTpMatch > 0) {
- DctOdcCtl = 0x00223222;
- if ((Speed == DDR800_FREQUENCY) && (DimmTpMatch == 1)) {
- DctOdcCtl = 0x00113222;
- }
- }
- if (DimmTpMatch >= 3) {
- AddrTmgCTL |= 0x002F0000;
- }
- if (DimmTpMatch >= 2) {
- RC2RC8 = 0x4040;
- }
- } else if ((MaxDimmPerCH == 3) && (CurrentChannel->Dimms == 3)) {
- DctOdcCtl = 0x00113222;
- } else {
- if ((Dimms == 1) && (DimmTpMatch == 1)) {
- DctOdcCtl = 0x00113222;
- }
- }
-
- //RC2 and RC8
- for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
- // CtrlWrd02(s) will contain the info. of SPD byte 63 after MemTDIMMPresence3 execution.
- if (CurrentChannel->CtrlWrd02[j] > 0) {
- if (CurrentChannel->CtrlWrd02[j] == 1) {
- // Store real RC2 and RC8 value (High byte) into CtrlWrd02(s) and CtrlWrd08(s).
- CurrentChannel->CtrlWrd02[j] = (UINT8) (RC2RC8 >> 12) & 0x000F;
- CurrentChannel->CtrlWrd08[j] = (UINT8) (RC2RC8 >> 8) & 0x000F;
- } else {
- // Store real RC2 and RC8 value (low byte) into CtrlWrd02(s) and CtrlWrd08(s).
- CurrentChannel->CtrlWrd02[j] = (UINT8) (RC2RC8 >> 4) & 0x000F;
- CurrentChannel->CtrlWrd08[j] = (UINT8) RC2RC8 & 0x000F;
- }
- }
- }
-
- //Programmable ODT
- for (i = 0; i < PSCfgODTSize; i++, PSCfgODTPtr++) {
- if (Dimms != PSCfgODTPtr->Dimms) {
- continue;
- }
- DimmTpMatch = 0;
- _DIMMRankType = DIMMRankType & PSCfgODTPtr->DIMMRankType;
- for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
- if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
- DimmTpMatch++;
- }
- }
- if (DimmTpMatch == PSCfgODTPtr->Dimms) {
- PhyRODTCSLow = PSCfgODTPtr->PhyRODTCSLow;
- PhyRODTCSHigh = PSCfgODTPtr->PhyRODTCSHigh;
- PhyWODTCSLow = PSCfgODTPtr->PhyWODTCSLow;
- PhyWODTCSHigh = PSCfgODTPtr->PhyWODTCSHigh;
- break;
- }
- }
-
- //WLODT
- for (i = 0; i < PSCfgWlODTSize; i++, PSCfgWlODTPtr++) {
- if (Dimms != PSCfgWlODTPtr->Dimms) {
- continue;
- }
- DimmTpMatch = 0;
- _DIMMRankType = DIMMRankType & PSCfgWlODTPtr->DIMMRankType;
- for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
- if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
- DimmTpMatch++;
- }
- }
- if (DimmTpMatch == PSCfgWlODTPtr->Dimms) {
- PhyWLODT[0] = PSCfgWlODTPtr->PhyWrLvOdt[0];
- PhyWLODT[1] = PSCfgWlODTPtr->PhyWrLvOdt[1];
- PhyWLODT[2] = PSCfgWlODTPtr->PhyWrLvOdt[2];
- PhyWLODT[3] = PSCfgWlODTPtr->PhyWrLvOdt[3];
- break;
- }
- }
-
- // Set ProcODT
- DctOdcCtl |= 0x20000000;
-
- CurrentChannel->MemClkDisMap = (UINT8 *) HyRDdr3CLKDis;
- CurrentChannel->CKETriMap = (UINT8 *) HyRDdr3CKETri;
- CurrentChannel->ChipSelTriMap = (UINT8 *) HyRDdr3CSTri;
-
- switch (MaxDimmPerCH) {
- case 3:
- CurrentChannel->ODTTriMap = (UINT8 *) HyRDdr3ODTTri3D;
- break;
- case 4:
- CurrentChannel->ODTTriMap = (UINT8 *) HyRDdr3ODTTri4D;
- break;
- default:
- CurrentChannel->ODTTriMap = (UINT8 *) HyRDdr3ODTTri2D; // Most conservative
- }
-
- CurrentChannel->DctAddrTmg = AddrTmgCTL;
- CurrentChannel->DctOdcCtl = DctOdcCtl;
- CurrentChannel->PhyRODTCSLow = PhyRODTCSLow;
- CurrentChannel->PhyRODTCSHigh = PhyRODTCSHigh;
- CurrentChannel->PhyWODTCSLow = PhyWODTCSLow;
- CurrentChannel->PhyWODTCSHigh = PhyWODTCSHigh;
- for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
- CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
- }
- CurrentChannel->SlowMode = SlowMode;
-
- return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ardk/HY/mauhy3.c b/src/vendorcode/amd/agesa/Proc/Mem/Ardk/HY/mauhy3.c
deleted file mode 100644
index fc5f3c6..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ardk/HY/mauhy3.c
+++ /dev/null
@@ -1,357 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mauhy3.c
- *
- * Platform specific settings for HY DDR3 unbuffered dimms
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ardk)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/* This file contains routine that add platform specific support AM3 */
-
-
-#include "AGESA.h"
-#include "mport.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mu.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_ARDK_HY_MAUHY3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-STATIC CONST UINT8 ROMDATA HyUDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
-// Even chip select maps to M[B,A]_CKE[0]
-// Odd chip select maps to M[B,A]_CKE[1]
-STATIC CONST UINT8 ROMDATA HyUDdr3CKETri[] = {0x55, 0xAA};
-// Bit 0: M[B,A]0_ODT[0]
-// Bit 1: M[B,A]1_ODT[0]
-// Bit 2: M[B,A]0_ODT[1]
-// Bit 3: M[B,A]1_ODT[1]
-STATIC CONST UINT8 ROMDATA HyUDdr3ODTTri2D[] = {0x01, 0x04, 0x02, 0x08};
-// 3 dimms per channel
-// Dimm 0: BP_MEMODTx[0]
-// Dimm 1: BP_MEMODTx[3,1]
-// Dimm 2: BP_MEMODTx[2]
-STATIC CONST UINT8 ROMDATA HyUDdr3ODTTri3D[] = {0xFF, 0xFF, 0xFF, 0xFF};
-// Bit 0: M[B,A]0_CS_H/L[0]
-// Bit 1: M[B,A]0_CS_H/L[1]
-// Bit 2: M[B,A]0_CS_H/L[2]
-// Bit 3: M[B,A]0_CS_H/L[3]
-STATIC CONST UINT8 ROMDATA HyUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for HY DDR3 unbuffered dimms
- *
- *
- * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE
- * @param[in] SocketID Socket number
- * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT
- *
- * @return AGESA_SUCCESS
- * @return CurrentChannel->MemClkDisMap Points this pointer to HY MemClkDis table
- * @return CurrentChannel->ChipSelTriMap Points this pointer to HY CS table
- * @return CurrentChannel->CKETriMap Points this pointer to HY ODT table
- * @return CurrentChannel->ODTTriMap Points this pointer to HY CKE table
- * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC
- * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte
- * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel
- * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel
- * @return CurrentChannel->SlowMode Slow Mode
- *
- *
- */
-
-AGESA_STATUS
-MemAGetPsCfgUHy3 (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- )
-{
- STATIC CONST PSCFG_ENTRY PSCfg[] = {
- {DDR800_FREQUENCY, 0xFF, 0x00390039, 0x20223323},
- {DDR1066_FREQUENCY, 0xFF, 0x00350037, 0x20223323},
- {DDR1333_FREQUENCY, 0xFF, 0x00000035, 0x20223323},
- {DDR1600_FREQUENCY, 0xFF, 0x00000033, 0x20223323}
- };
-
- STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg2DIMMsODT[] = {
- {SR_DIMM0, 0x00000000, 0x00000000, 0x00000001, 0x00000000, 1},
- {DR_DIMM0, 0x00000000, 0x00000000, 0x00000104, 0x00000000, 1},
- {SR_DIMM1, 0x00000000,0x00000000,0x00020000, 0x00000000, 1},
- {DR_DIMM1, 0x00000000,0x00000000,0x02080000, 0x00000000, 1},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, 0x01010202,0x00000000,0x09030603, 0x00000000, 2},
- };
-
- STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg2DIMMsWlODT[] = {
- {SR_DIMM0, {0x01, 0x00, 0x00, 0x00}, 1},
- {DR_DIMM0, {0x04, 0x00, 0x00, 0x00}, 1},
- {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1},
- {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}
- };
-
- STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfg3DIMMsODT[] = {
- {SR_DIMM2 + DR_DIMM2, 0x00000000, 0x00000000, 0x00000000, 0x00000404, 1},
- //{SR_DIMM0 + DR_DIMM0, 0x00000000, 0x00000000, 0x00000101, 0x00000000, 1},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, 0x00000404, 0x00000101, 0x00000405, 0x00000105, 2},
- //{SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, 0x05050606, 0x00000303, 0x0D070607, 0x00000307, 3},
- };
-
- STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfg3DIMMsWlODT[] = {
- {SR_DIMM2 + DR_DIMM2, {0x00, 0x00, 0x04, 0x00}, 1},
- //{SR_DIMM0 + DR_DIMM0, {0x01, 0x02, 0x00, 0x00}, 1},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, {0x05, 0x00, 0x05, 0x00}, 2},
- //{SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x07, 0x07, 0x07, 0x00}, 3},
- };
-
- UINT16 i;
- UINT16 j;
- UINT8 MaxDimmPerCH;
- UINT8 Loads;
- UINT8 Dimms;
- UINT16 Speed;
- UINT16 DIMMRankType;
- UINT16 _DIMMRankType;
- UINT32 AddrTmgCTL;
- UINT32 DctOdcCtl;
- UINT32 PhyRODTCSLow;
- UINT32 PhyRODTCSHigh;
- UINT32 PhyWODTCSLow;
- UINT32 PhyWODTCSHigh;
- UINT8 PhyWLODT[4];
- UINT8 PSCfgODTSize;
- UINT8 PSCfgWlODTSize;
- BOOLEAN SlowMode;
- UINT8 DimmTpMatch;
- CONST ADV_PSCFG_ODT_ENTRY *PSCfgODTPtr;
- CONST ADV_R_PSCFG_WL_ODT_ENTRY *PSCfgWlODTPtr;
- UINT8 *DimmsPerChPtr;
-
- ASSERT (MemData != NULL);
- ASSERT (CurrentChannel != NULL);
-
- AddrTmgCTL = 0;
- DctOdcCtl = 0;
- PhyRODTCSLow = 0;
- PhyRODTCSHigh = 0;
- PhyWODTCSLow = 0;
- PhyWODTCSHigh = 0;
- PhyWLODT[0] = 0x0F;
- PhyWLODT[1] = 0x0F;
- PhyWLODT[2] = 0x0F;
- PhyWLODT[3] = 0x0F;
-
- if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_HY) == 0) {
- return AGESA_UNSUPPORTED;
- }
- if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
- return AGESA_UNSUPPORTED;
- }
- if (CurrentChannel->RegDimmPresent) {
- return AGESA_UNSUPPORTED;
- }
- // Prepare inputs
-
- DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID);
- if (DimmsPerChPtr != NULL) {
- MaxDimmPerCH = *DimmsPerChPtr;
- } else {
- MaxDimmPerCH = 2;
- }
-
- Loads = CurrentChannel->Loads;
- Dimms = CurrentChannel->Dimms;
- Speed = CurrentChannel->DCTPtr->Timings.Speed;
-
- DIMMRankType = MemAGetPsRankType (CurrentChannel);
-
- if ((Speed == DDR1333_FREQUENCY || Speed == DDR1600_FREQUENCY) && (Dimms == 2)) {
- SlowMode = TRUE; // 2T
- } else {
- SlowMode = FALSE; // 1T
- }
-
- for (i = 0; i < GET_SIZE_OF (PSCfg); i++) {
- if (Speed == PSCfg[i].Speed) {
- if (Loads <= PSCfg[i].Loads) {
- AddrTmgCTL = PSCfg[i].AddrTmg;
- DctOdcCtl = PSCfg[i].Odc;
- break;
- }
- }
- }
-
- ASSERT (i < GET_SIZE_OF (PSCfg));
-
- if (MaxDimmPerCH == 3) {
- PSCfgODTPtr = PSCfg3DIMMsODT;
- PSCfgWlODTPtr = PSCfg3DIMMsWlODT;
- PSCfgODTSize = sizeof (PSCfg3DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY);
- PSCfgWlODTSize = sizeof (PSCfg3DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
- } else {
- PSCfgODTPtr = PSCfg2DIMMsODT;
- PSCfgWlODTPtr = PSCfg2DIMMsWlODT;
- PSCfgODTSize = sizeof (PSCfg2DIMMsODT) / sizeof (ADV_PSCFG_ODT_ENTRY);
- PSCfgWlODTSize = sizeof (PSCfg2DIMMsWlODT) / sizeof (ADV_R_PSCFG_WL_ODT_ENTRY);
- }
-
- // Programmable ODT
- for (i = 0; i < PSCfgODTSize; i++, PSCfgODTPtr++) {
- if (Dimms != PSCfgODTPtr->Dimms) {
- continue;
- }
- DimmTpMatch = 0;
- _DIMMRankType = DIMMRankType & PSCfgODTPtr->DIMMRankType;
- for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
- if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
- DimmTpMatch++;
- }
- }
- if (DimmTpMatch == PSCfgODTPtr->Dimms) {
- PhyRODTCSLow = PSCfgODTPtr->PhyRODTCSLow;
- PhyRODTCSHigh = PSCfgODTPtr->PhyRODTCSHigh;
- PhyWODTCSLow = PSCfgODTPtr->PhyWODTCSLow;
- PhyWODTCSHigh = PSCfgODTPtr->PhyWODTCSHigh;
- break;
- }
- }
-
- // WL ODT
- for (i = 0; i < PSCfgWlODTSize; i++, PSCfgWlODTPtr++) {
- if (Dimms != PSCfgWlODTPtr->Dimms) {
- continue;
- }
- DimmTpMatch = 0;
- _DIMMRankType = DIMMRankType & PSCfgWlODTPtr->DIMMRankType;
- for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
- if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
- DimmTpMatch++;
- }
- }
- if (DimmTpMatch == PSCfgWlODTPtr->Dimms) {
- PhyWLODT[0] = PSCfgWlODTPtr->PhyWrLvOdt[0];
- PhyWLODT[1] = PSCfgWlODTPtr->PhyWrLvOdt[1];
- PhyWLODT[2] = PSCfgWlODTPtr->PhyWrLvOdt[2];
- PhyWLODT[3] = PSCfgWlODTPtr->PhyWrLvOdt[3];
- break;
- }
- }
-
- //
- // Overrides and/or exceptions
- //
- if (Dimms == 1) {
- if (Loads >= 16) {
- if (Speed == DDR800_FREQUENCY) {
- AddrTmgCTL = 0x003B0000;
- } else if (Speed == DDR1066_FREQUENCY) {
- AddrTmgCTL = 0x00380000;
- } else if (Speed == DDR1333_FREQUENCY) {
- AddrTmgCTL = 0x00360000;
- } else {
- AddrTmgCTL = 0x00340000;
- SlowMode = TRUE;
- }
- } else {
- AddrTmgCTL = 0;
- }
- DctOdcCtl = 0x20113222;
- }
-
- CurrentChannel->MemClkDisMap = (UINT8 *) HyUDdr3CLKDis;
- CurrentChannel->CKETriMap = (UINT8 *) HyUDdr3CKETri;
- CurrentChannel->ChipSelTriMap = (UINT8 *) HyUDdr3CSTri;
-
- switch (MaxDimmPerCH) {
- case 3:
- CurrentChannel->ODTTriMap = (UINT8 *) HyUDdr3ODTTri3D;
- break;
- default:
- CurrentChannel->ODTTriMap = (UINT8 *) HyUDdr3ODTTri2D; // Most conservative
- }
-
- CurrentChannel->DctEccDqsLike = 0x0403;
- CurrentChannel->DctEccDqsScale = 0x70;
- CurrentChannel->DctAddrTmg = AddrTmgCTL;
- CurrentChannel->DctOdcCtl = DctOdcCtl;
- CurrentChannel->PhyRODTCSLow = PhyRODTCSLow;
- CurrentChannel->PhyRODTCSHigh = PhyRODTCSHigh;
- CurrentChannel->PhyWODTCSLow = PhyWODTCSLow;
- CurrentChannel->PhyWODTCSHigh = PhyWODTCSHigh;
- for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
- CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
- }
- CurrentChannel->SlowMode = SlowMode;
-
- return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ardk/NI/masNi3.c b/src/vendorcode/amd/agesa/Proc/Mem/Ardk/NI/masNi3.c
deleted file mode 100644
index 1c27fc9..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ardk/NI/masNi3.c
+++ /dev/null
@@ -1,261 +0,0 @@
-/* $NoKeywords:$ */
-/*
- * @file
- *
- * masNi3.c
- *
- * Platform specific settings for Ni DDR3 SO-dimms
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ardk)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/* This file contains routine that add platform specific support ASB2 */
-
-
-#include "AGESA.h"
-#include "mport.h"
-#include "ma.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mu.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_ARDK_NI_MASNI3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-STATIC CONST UINT8 ROMDATA NiSDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
-// Even chip select maps to M[B,A]_CKE[0]
-// Odd chip select maps to M[B,A]_CKE[1]
-STATIC CONST UINT8 ROMDATA NiSDdr3CKETri[] = {0x55, 0xAA};
-// Bit 0: M[B,A]0_ODT[0]
-// Bit 1: M[B,A]1_ODT[0]
-// Bit 2: M[B,A]0_ODT[1]
-// Bit 3: M[B,A]1_ODT[1]
-STATIC CONST UINT8 ROMDATA NiSDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
-// Bit 0: M[B,A]0_CS_H/L[0]
-// Bit 1: M[B,A]0_CS_H/L[1]
-// Bit 2: M[B,A]0_CS_H/L[2]
-// Bit 3: M[B,A]0_CS_H/L[3]
-STATIC CONST UINT8 ROMDATA NiSDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for Ni DDR3 SO-dimms
- *
- *
- * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE
- * @param[in] SocketID Socket number
- * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT
- *
- * @return AGESA_SUCCESS
- * @return CurrentChannel->MemClkDisMap Points this pointer to RB MemClkDis table
- * @return CurrentChannel->ChipSelTriMap Points this pointer to RB CS table
- * @return CurrentChannel->CKETriMap Points this pointer to RB ODT table
- * @return CurrentChannel->ODTTriMap Points this pointer to RB CKE table
- * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC
- * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte
- * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel
- * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel
- * @return CurrentChannel->SlowMode Slow Mode
- *
- *
- */
-
-AGESA_STATUS
-MemAGetPsCfgSNi3 (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- )
-{
- STATIC CONST PSCFG_ENTRY PSCfg[] = {
- {DDR800_FREQUENCY, 0xFF, 0x00000000, 0x00113222},
- {DDR1066_FREQUENCY, 0xFF, 0x00000000, 0x10113222},
- {DDR1333_FREQUENCY, 0xFF, 0x00000000, 0x20113222},
- };
-
- STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfgDIMMWlODT[] = {
- {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1},
- {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}
- };
-
- UINT16 i;
- UINT16 j;
- UINT8 Loads;
- UINT8 Dimms;
- UINT16 Speed;
- UINT32 AddrTmgCTL;
- UINT32 DctOdcCtl;
- UINT8 PhyWLODT[4];
- BOOLEAN SlowMode;
- UINT8 MaxDimmPerCH;
- UINT8 *DimmsPerChPtr;
- UINT16 DIMMRankType;
- UINT16 _DIMMRankType;
- UINT8 DimmTpMatch;
-
- ASSERT (MemData != 0);
- ASSERT (CurrentChannel != 0);
-
- AddrTmgCTL = 0;
- DctOdcCtl = 0;
- PhyWLODT[0] = 0x0F;
- PhyWLODT[1] = 0x0F;
- PhyWLODT[2] = 0x0F;
- PhyWLODT[3] = 0x0F;
- SlowMode = FALSE; // 1T
- if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) {
- return AGESA_UNSUPPORTED;
- }
- if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
- return AGESA_UNSUPPORTED;
- }
- if (CurrentChannel->SODimmPresent != CurrentChannel->ChDimmValid) {
- return AGESA_UNSUPPORTED;
- }
- // Prepare inputs
- Loads = CurrentChannel->Loads;
- Dimms = CurrentChannel->Dimms;
- Speed = CurrentChannel->DCTPtr->Timings.Speed;
-
- DIMMRankType = MemAGetPsRankType (CurrentChannel);
-
- DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID);
- if (DimmsPerChPtr != NULL) {
- MaxDimmPerCH = *DimmsPerChPtr;
- } else {
- MaxDimmPerCH = 2;
- }
-
- for (i = 0; i < GET_SIZE_OF (PSCfg); i++) {
- if (Speed == PSCfg[i].Speed) {
- if (Loads <= PSCfg[i].Loads) {
- AddrTmgCTL = PSCfg[i].AddrTmg;
- DctOdcCtl = PSCfg[i].Odc;
- break;
- }
- }
- }
-
- // WL ODT
- for (i = 0; i < GET_SIZE_OF (PSCfgDIMMWlODT); i++) {
- if (Dimms != PSCfgDIMMWlODT[i].Dimms) {
- continue;
- }
- DimmTpMatch = 0;
- _DIMMRankType = DIMMRankType & PSCfgDIMMWlODT[i].DIMMRankType;
- for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
- if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
- DimmTpMatch++;
- }
- }
- if (DimmTpMatch == PSCfgDIMMWlODT[i].Dimms) {
- PhyWLODT[0] = PSCfgDIMMWlODT[i].PhyWrLvOdt[0];
- PhyWLODT[1] = PSCfgDIMMWlODT[i].PhyWrLvOdt[1];
- PhyWLODT[2] = PSCfgDIMMWlODT[i].PhyWrLvOdt[2];
- PhyWLODT[3] = PSCfgDIMMWlODT[i].PhyWrLvOdt[3];
- break;
- }
- }
-
- //
- // Overrides and/or exceptions
- //
- if (MaxDimmPerCH == 2) {
- if (Dimms == 2) {
- DctOdcCtl = 0x20223323;
- SlowMode = TRUE;
- if (Speed == DDR800_FREQUENCY) {
- AddrTmgCTL = 0x00000039;
- } else if (Speed == DDR1066_FREQUENCY) {
- AddrTmgCTL = 0x00000037;
- }
- } else {
- DctOdcCtl = 0x20113222;
- }
- } else {
- if (CurrentChannel->DimmSRPresent != 0) {
- PhyWLODT[0] = 1;
- } else if (CurrentChannel->DimmDrPresent != 0) {
- PhyWLODT[0] = 4;
- }
- }
-
- CurrentChannel->MemClkDisMap = (UINT8 *) NiSDdr3CLKDis;
- CurrentChannel->CKETriMap = (UINT8 *) NiSDdr3CKETri;
- CurrentChannel->ODTTriMap = (UINT8 *) NiSDdr3ODTTri;
- CurrentChannel->ChipSelTriMap = (UINT8 *) NiSDdr3CSTri;
-
- CurrentChannel->DctAddrTmg = AddrTmgCTL;
- CurrentChannel->DctOdcCtl = DctOdcCtl;
- for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
- CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
- }
- CurrentChannel->SlowMode = SlowMode;
-
- return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ardk/NI/mauNi3.c b/src/vendorcode/amd/agesa/Proc/Mem/Ardk/NI/mauNi3.c
deleted file mode 100644
index 2d0e1e0..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ardk/NI/mauNi3.c
+++ /dev/null
@@ -1,260 +0,0 @@
-/* $NoKeywords:$ */
-/*
- * @file
- *
- * mauNi3.c
- *
- * Platform specific settings for Ni DDR3 unbuffered dimms
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ardk)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/* This file contains routine that add platform specific support AM3 */
-
-
-#include "AGESA.h"
-#include "mport.h"
-#include "PlatformMemoryConfiguration.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_ARDK_NI_MAUNI3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-STATIC CONST UINT8 ROMDATA NiUDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
-// Even chip select maps to M[B,A]_CKE[0]
-// Odd chip select maps to M[B,A]_CKE[1]
-STATIC CONST UINT8 ROMDATA NiUDdr3CKETri[] = {0x55, 0xAA};
-// Bit 0: M[B,A]0_ODT[0]
-// Bit 1: M[B,A]1_ODT[0]
-// Bit 2: M[B,A]0_ODT[1]
-// Bit 3: M[B,A]1_ODT[1]
-STATIC CONST UINT8 ROMDATA NiUDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
-// Bit 0: M[B,A]0_CS_H/L[0]
-// Bit 1: M[B,A]0_CS_H/L[1]
-// Bit 2: M[B,A]0_CS_H/L[2]
-// Bit 3: M[B,A]0_CS_H/L[3]
-STATIC CONST UINT8 ROMDATA NiUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for Ni DDR3 Unbuffered dimms
- *
- *
- * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE
- * @param[in] SocketID Socket number
- * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT
- *
- * @return AGESA_SUCCESS
- * @return CurrentChannel->MemClkDisMap Points this pointer to RB MemClkDis table
- * @return CurrentChannel->ChipSelTriMap Points this pointer to RB CS table
- * @return CurrentChannel->CKETriMap Points this pointer to RB ODT table
- * @return CurrentChannel->ODTTriMap Points this pointer to RB CKE table
- * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC
- * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte
- * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel
- * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel
- * @return CurrentChannel->SlowMode Slow Mode
- *
- */
-
-AGESA_STATUS
-MemAGetPsCfgUNi3 (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- )
-{
- STATIC CONST PSCFG_ENTRY PSCfg1Dimm[] = {
- {DDR800_FREQUENCY, 0x10, 0x003B0000, 0x20113222},
- {DDR1066_FREQUENCY, 0x10, 0x00380000, 0x20113222},
- {DDR1333_FREQUENCY, 0x10, 0x00360000, 0x20113222},
- {DDR1600_FREQUENCY, 0x10, 0x00340000, 0x20113222}
- };
- STATIC CONST PSCFG_ENTRY PSCfg2Dimm[] = {
- {DDR800_FREQUENCY, 0xFF, 0x00390039, 0x20223323},
- {DDR1066_FREQUENCY, 0xFF, 0x00350037, 0x20223323},
- {DDR1333_FREQUENCY, 0xFF, 0x00000035, 0x20223323},
- {DDR1600_FREQUENCY, 0xFF, 0x00000033, 0x20223323}
- };
-
- STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfgDIMMWlODT[] = {
- {SR_DIMM0, {0x01, 0x00, 0x00, 0x00}, 1},
- {DR_DIMM0, {0x04, 0x00, 0x00, 0x00}, 1},
- {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1},
- {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}
- };
-
- UINT16 i;
- UINT16 j;
- UINT8 Loads;
- UINT8 Dimms;
- UINT16 Speed;
- UINT16 DIMMRankType;
- UINT16 _DIMMRankType;
- UINT32 AddrTmgCTL;
- UINT32 DctOdcCtl;
- UINT8 PhyWLODT[4];
- BOOLEAN SlowMode;
- UINT8 DimmTpMatch;
-
- ASSERT (MemData != 0);
- ASSERT (CurrentChannel != 0);
-
- AddrTmgCTL = 0;
- DctOdcCtl = 0;
- PhyWLODT[0] = 0x0F;
- PhyWLODT[1] = 0x0F;
- PhyWLODT[2] = 0x0F;
- PhyWLODT[3] = 0x0F;
-
- if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) {
- return AGESA_UNSUPPORTED;
- }
- if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
- return AGESA_UNSUPPORTED;
- }
- if ((CurrentChannel->RegDimmPresent != 0) || (CurrentChannel->SODimmPresent != 0)) {
- return AGESA_UNSUPPORTED;
- }
- // Prepare inputs
- Loads = CurrentChannel->Loads;
- Dimms = CurrentChannel->Dimms;
- Speed = CurrentChannel->DCTPtr->Timings.Speed;
- DIMMRankType = MemAGetPsRankType (CurrentChannel);
-
- if ((Speed == DDR1333_FREQUENCY || Speed == DDR1600_FREQUENCY) && (Dimms == 2)) {
- SlowMode = TRUE; // 2T
- } else if ((Speed == DDR1600_FREQUENCY) && (Dimms == 1) && (Loads >= 16)) {
- SlowMode = TRUE; // 2T
- } else {
- SlowMode = FALSE; // 1T
- }
-
- if (Dimms == 1) {
- for (i = 0; i < GET_SIZE_OF (PSCfg1Dimm); i++) {
- if (Speed == PSCfg1Dimm[i].Speed) {
- if (Loads >= PSCfg1Dimm[i].Loads) {
- AddrTmgCTL = PSCfg1Dimm[i].AddrTmg;
- DctOdcCtl = PSCfg1Dimm[i].Odc;
- } else {
- DctOdcCtl = 0x20113222;
- }
- break;
- }
- }
- ASSERT (i < GET_SIZE_OF (PSCfg1Dimm));
- } else {
- for (i = 0; i < GET_SIZE_OF (PSCfg2Dimm); i++) {
- if (Speed == PSCfg2Dimm[i].Speed) {
- if (Loads <= PSCfg2Dimm[i].Loads) {
- AddrTmgCTL = PSCfg2Dimm[i].AddrTmg;
- DctOdcCtl = PSCfg2Dimm[i].Odc;
- break;
- }
- }
- }
- ASSERT (i < GET_SIZE_OF (PSCfg2Dimm));
- }
-
- // WL ODT
- for (i = 0; i < GET_SIZE_OF (PSCfgDIMMWlODT); i++) {
- if (Dimms != PSCfgDIMMWlODT[i].Dimms) {
- continue;
- }
- DimmTpMatch = 0;
- _DIMMRankType = DIMMRankType & PSCfgDIMMWlODT[i].DIMMRankType;
- for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
- if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
- DimmTpMatch++;
- }
- }
- if (DimmTpMatch == PSCfgDIMMWlODT[i].Dimms) {
- PhyWLODT[0] = PSCfgDIMMWlODT[i].PhyWrLvOdt[0];
- PhyWLODT[1] = PSCfgDIMMWlODT[i].PhyWrLvOdt[1];
- PhyWLODT[2] = PSCfgDIMMWlODT[i].PhyWrLvOdt[2];
- PhyWLODT[3] = PSCfgDIMMWlODT[i].PhyWrLvOdt[3];
- break;
- }
- }
-
- CurrentChannel->MemClkDisMap = (UINT8 *) NiUDdr3CLKDis;
- CurrentChannel->CKETriMap = (UINT8 *) NiUDdr3CKETri;
- CurrentChannel->ODTTriMap = (UINT8 *) NiUDdr3ODTTri;
- CurrentChannel->ChipSelTriMap = (UINT8 *) NiUDdr3CSTri;
-
- CurrentChannel->DctEccDqsLike = 0x0403;
- CurrentChannel->DctEccDqsScale = 0x70;
- CurrentChannel->DctAddrTmg = AddrTmgCTL;
- CurrentChannel->DctOdcCtl = DctOdcCtl;
- for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
- CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
- }
- CurrentChannel->SlowMode = SlowMode;
-
- return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ardk/ON/mason3.c b/src/vendorcode/amd/agesa/Proc/Mem/Ardk/ON/mason3.c
deleted file mode 100644
index c02c006..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ardk/ON/mason3.c
+++ /dev/null
@@ -1,274 +0,0 @@
-/* $NoKeywords:$ */
-/*
- * @file
- *
- * mason3.c
- *
- * Platform specific settings for ON DDR3 SO-dimms
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ardk/ON)
- * @e \$Revision: 38442 $ @e \$Date: 2010-09-24 06:39:57 +0800 (Fri, 24 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/* This file contains routine that add platform specific support AM3 */
-
-
-#include "AGESA.h"
-#include "mport.h"
-#include "PlatformMemoryConfiguration.h"
-#include "ma.h"
-#include "mu.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "Filecode.h"
-#define FILECODE PROC_MEM_ARDK_ON_MASON3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-STATIC CONST UINT8 ROMDATA OnSDdr3CLKDis[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-STATIC CONST UINT8 ROMDATA OnSDdr3CKETri[] = {0xFF, 0xFF};
-STATIC CONST UINT8 ROMDATA OnSDdr3ODTTri[] = {0x01, 0x02, 0x04, 0x08};
-STATIC CONST UINT8 ROMDATA OnSDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for ON DDR3 SO-dimms
- *
- *
- * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE
- * @param[in] SocketID Socket number
- * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT
- *
- * @return AGESA_SUCCESS
- * @return CurrentChannel->MemClkDisMap Points this pointer to LN MemClkDis table
- * @return CurrentChannel->ChipSelTriMap Points this pointer to LN CS table
- * @return CurrentChannel->CKETriMap Points this pointer to LN ODT table
- * @return CurrentChannel->ODTTriMap Points this pointer to LN CKE table
- * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC
- * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte
- * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel
- * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel
- * @return CurrentChannel->SlowMode Slow Mode
- *
- *
- */
-
-AGESA_STATUS
-MemAGetPsCfgSON3 (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- )
-{
- CONST ADV_PSCFG_ENTRY PSCfg[] = {
- {DDR800_FREQUENCY, SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, 0x00000000, 0x00002223, 1},
- {DDR800_FREQUENCY, ANY_, 0x00000039, 0x20222323, 2},
- {DDR1066_FREQUENCY, SR_DIMM0 + SR_DIMM1, 0x003D3D3D, 0x10002223, 1},
- {DDR1066_FREQUENCY, DR_DIMM0 + DR_DIMM1, 0x00000000, 0x10002223, 1},
- {DDR1066_FREQUENCY, ANY_, 0x00000037, 0x30222323, 2},
- {DDR1333_FREQUENCY, SR_DIMM0 + SR_DIMM1, 0x003D3D3D, 0x30002223, 1},
- {DDR1333_FREQUENCY, DR_DIMM0 + DR_DIMM1, 0x00003D3D, 0x30002223, 1},
- {DDR1333_FREQUENCY, ANY_, 0x00000035, 0x30222323, 2}
- };
-
- //
- // DIMM ODT Pattern
- //
- // Dimm Config ,
- // Fn2_F4 180, Fn2_F4 181, Fn2_F4 182, Fn2_F4 183, # Dimms to match
- //
- STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfgDIMMsODT[] = {
- {SR_DIMM0, \
- 0x00000000, 0x00000000, 0x00000001, 0x00000000, 1},
- {DR_DIMM0, \
- 0x00000000, 0x00000000, 0x00000201, 0x00000000, 1},
- {SR_DIMM1, \
- 0x00000000, 0x00000000, 0x00040000, 0x00000000, 1},
- {DR_DIMM1, \
- 0x00000000, 0x00000000, 0x08040000, 0x00000000, 1},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
- 0x01010404, 0x00000000, 0x09050605, 0x00000000, 2}
- };
-
- UINT8 i;
- UINT8 j;
- UINT8 Loads;
- UINT8 Dimms;
- UINT8 DimmTpMatch;
- UINT16 Speed;
- UINT16 DIMMRankType;
- UINT16 _DIMMRankType;
- UINT32 AddrTmgCTL;
- UINT32 DctOdcCtl;
- UINT8 PhyWLODT[4];
- UINT32 PhyRODTCS;
- UINT32 PhyWODTCS;
- BOOLEAN SlowMode;
- UINT8 *DimmsPerChPtr;
- UINT8 DimmsPerCH;
-
- PhyWLODT[0] = 0x0F;
- PhyWLODT[1] = 0x0F;
- PhyWLODT[2] = 0x0F;
- PhyWLODT[3] = 0x0F;
- PhyRODTCS = 0;
- PhyWODTCS = 0;
-
- ASSERT (MemData != 0);
- ASSERT (CurrentChannel != 0);
-
- AddrTmgCTL = 0;
- DctOdcCtl = 0;
-
- if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_ON) == 0) {
- return AGESA_UNSUPPORTED;
- }
- if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
- return AGESA_UNSUPPORTED;
- }
- if (CurrentChannel->SODimmPresent != CurrentChannel->ChDimmValid) {
- return AGESA_UNSUPPORTED;
- }
-
- // Prepare inputs
- Loads = CurrentChannel->Loads;
- Dimms = CurrentChannel->Dimms;
- Speed = CurrentChannel->DCTPtr->Timings.Speed;
-
- DIMMRankType = MemAGetPsRankType (CurrentChannel);
-
- DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID);
- if (DimmsPerChPtr != NULL) {
- DimmsPerCH = *DimmsPerChPtr;
- } else {
- DimmsPerCH = 2;
- }
-
- if (Dimms == 2) {
- SlowMode = TRUE; // 2T
- } else {
- SlowMode = FALSE; // 1T
- }
-
- for (i = 0; i < GET_SIZE_OF (PSCfg); i++) {
- if ((PSCfg[i].Dimms == ANY_) || (PSCfg[i].Dimms == Dimms)) {
- if ((PSCfg[i].Speed == ANY_) || (PSCfg[i].Speed == Speed)) {
- if ((PSCfg[i].Loads == ANY_) || ((PSCfg[i].Loads & DIMMRankType) != 0)) {
- AddrTmgCTL = PSCfg[i].AddrTmg;
- DctOdcCtl = PSCfg[i].Odc;
- break;
- }
- }
- }
- }
- ASSERT (i < GET_SIZE_OF (PSCfg));
-
- //
- // Programmable Dimm ODT
- //
- for (i = 0; i < GET_SIZE_OF (PSCfgDIMMsODT); i++) {
- if (Dimms != PSCfgDIMMsODT[i].Dimms) {
- continue;
- }
- DimmTpMatch = 0;
- _DIMMRankType = DIMMRankType & PSCfgDIMMsODT[i].DIMMRankType;
- for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
- if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
- DimmTpMatch++;
- }
- }
- if (DimmTpMatch == PSCfgDIMMsODT[i].Dimms) {
- PhyRODTCS = PSCfgDIMMsODT[i].PhyRODTCSLow;
- PhyWODTCS = PSCfgDIMMsODT[i].PhyWODTCSLow;
- break;
- }
- }
-
- //
- //WL ODT
- //
- PhyWLODT[0] = (UINT8) (PhyWODTCS & 0x0F);
- PhyWLODT[1] = (UINT8) ((PhyWODTCS >> 16) & 0x0F);
- PhyWLODT[2] = PhyWLODT[3] = 0;
-
- //
- // Overrides and/or exceptions
- //
-
- CurrentChannel->MemClkDisMap = (UINT8 *) OnSDdr3CLKDis;
- CurrentChannel->CKETriMap = (UINT8 *) OnSDdr3CKETri;
- CurrentChannel->ODTTriMap = (UINT8 *) OnSDdr3ODTTri;
- CurrentChannel->ChipSelTriMap = (UINT8 *) OnSDdr3CSTri;
- CurrentChannel->DctAddrTmg = AddrTmgCTL;
- CurrentChannel->DctOdcCtl = DctOdcCtl;
- CurrentChannel->PhyRODTCSLow = PhyRODTCS;
- CurrentChannel->PhyWODTCSLow = PhyWODTCS;
- for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
- CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
- }
- CurrentChannel->SlowMode = SlowMode;
-
- if ((DimmsPerCH == 2) && (Speed == DDR1333_FREQUENCY) && (Dimms == 1)) {
- // Set Dqs and DQ drive strength to 1.0x for 1 dimm on 2 dimms per channel DDR3-1333
- CurrentChannel->DctOdcCtl |= 0x110000;
- }
-
- return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ardk/ON/mauon3.c b/src/vendorcode/amd/agesa/Proc/Mem/Ardk/ON/mauon3.c
deleted file mode 100644
index 075aae1..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ardk/ON/mauon3.c
+++ /dev/null
@@ -1,259 +0,0 @@
-/* $NoKeywords:$ */
-/*
- * @file
- *
- * mauon3.c
- *
- * Platform specific settings for ON DDR3 unbuffered dimms
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ardk/ON)
- * @e \$Revision: 38442 $ @e \$Date: 2010-09-24 06:39:57 +0800 (Fri, 24 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/* This file contains routine that add platform specific support AM3 */
-
-
-#include "AGESA.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mport.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "Filecode.h"
-#define FILECODE PROC_MEM_ARDK_ON_MAUON3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-STATIC CONST UINT8 ROMDATA OnUDdr3CLKDis[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-STATIC CONST UINT8 ROMDATA OnUDdr3CKETri[] = {0xFF, 0xFF};
-STATIC CONST UINT8 ROMDATA OnUDdr3ODTTri[] = {0x01, 0x02, 0x04, 0x08};
-STATIC CONST UINT8 ROMDATA OnUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for ON DDR3 Unbuffered dimms
- *
- *
- * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE
- * @param[in] SocketID Socket number
- * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT
- *
- * @return AGESA_SUCCESS
- * @return CurrentChannel->MemClkDisMap Points this pointer to LN MemClkDis table
- * @return CurrentChannel->ChipSelTriMap Points this pointer to LN CS table
- * @return CurrentChannel->CKETriMap Points this pointer to LN ODT table
- * @return CurrentChannel->ODTTriMap Points this pointer to LN CKE table
- * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC
- * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte
- * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel
- * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel
- * @return CurrentChannel->SlowMode Slow Mode
- *
- */
-
-AGESA_STATUS
-MemAGetPsCfgUON3 (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- )
-{
- CONST ADV_PSCFG_ENTRY PSCfg[] = {
- {DDR800_FREQUENCY, SR_DIMM0 + SR_DIMM1, 0x00000000, 0x00112223, 1},
- {DDR800_FREQUENCY, DR_DIMM0 + DR_DIMM1, 0x003B0000, 0x00112223, 1},
- {DDR800_FREQUENCY, ANY_, 0x00390039, 0x20222323, 2},
- {DDR1066_FREQUENCY, SR_DIMM0 + SR_DIMM1, 0x00000000, 0x10112223, 1},
- {DDR1066_FREQUENCY, DR_DIMM0 + DR_DIMM1, 0x00380000, 0x10112223, 1},
- {DDR1066_FREQUENCY, ANY_, 0x00350037, 0x30222323, 2},
- {DDR1333_FREQUENCY, SR_DIMM0 + SR_DIMM1, 0x00000000, 0x30112223, 1},
- {DDR1333_FREQUENCY, DR_DIMM0 + DR_DIMM1, 0x00360000, 0x30112223, 1},
- {DDR1333_FREQUENCY, ANY_, 0x00000035, 0x30222323, 2}
- };
-
- //
- // DIMM ODT Pattern
- //
- // Dimm Config ,
- // Fn2_F4 180, Fn2_F4 181, Fn2_F4 182, Fn2_F4 183, # Dimms to match
- //
- STATIC CONST ADV_PSCFG_ODT_ENTRY PSCfgDIMMsODT[] = {
- {SR_DIMM0, \
- 0x00000000, 0x00000000, 0x00000001, 0x00000000, 1},
- {DR_DIMM0, \
- 0x00000000, 0x00000000, 0x00000201, 0x00000000, 1},
- {SR_DIMM1, \
- 0x00000000, 0x00000000, 0x00040000, 0x00000000, 1},
- {DR_DIMM1, \
- 0x00000000, 0x00000000, 0x08040000, 0x00000000, 1},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, \
- 0x01010404, 0x00000000, 0x09050605, 0x00000000, 2}
- };
-
- UINT16 i;
- UINT16 j;
- UINT8 Dimms;
- UINT16 Speed;
- UINT16 DIMMRankType;
- UINT16 _DIMMRankType;
- UINT32 AddrTmgCTL;
- UINT32 DctOdcCtl;
- UINT8 PhyWLODT[4];
- UINT32 PhyRODTCS;
- UINT32 PhyWODTCS;
- BOOLEAN SlowMode;
- UINT8 DimmTpMatch;
-
- ASSERT (MemData != 0);
- ASSERT (CurrentChannel != 0);
-
- AddrTmgCTL = 0;
- DctOdcCtl = 0;
- PhyWLODT[0] = 0x0F;
- PhyWLODT[1] = 0x0F;
- PhyWLODT[2] = 0x0F;
- PhyWLODT[3] = 0x0F;
- PhyRODTCS = 0;
- PhyWODTCS = 0;
-
- if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_ON) == 0) {
- return AGESA_UNSUPPORTED;
- }
- if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
- return AGESA_UNSUPPORTED;
- }
- if ((CurrentChannel->RegDimmPresent != 0) || (CurrentChannel->SODimmPresent != 0)) {
- return AGESA_UNSUPPORTED;
- }
-
- // Prepare inputs
- Dimms = CurrentChannel->Dimms;
- Speed = CurrentChannel->DCTPtr->Timings.Speed;
-
- DIMMRankType = MemAGetPsRankType (CurrentChannel);
-
- if ((Speed == DDR1333_FREQUENCY) && (Dimms == 2)) {
- SlowMode = TRUE; // 2T
- } else {
- SlowMode = FALSE; // 1T
- }
-
- for (i = 0; i < GET_SIZE_OF (PSCfg); i++) {
- if ((PSCfg[i].Dimms == ANY_) || (PSCfg[i].Dimms == Dimms)) {
- if ((PSCfg[i].Speed == ANY_) || (PSCfg[i].Speed == Speed)) {
- if ((PSCfg[i].Loads == ANY_) || ((PSCfg[i].Loads & DIMMRankType) != 0)) {
- AddrTmgCTL = PSCfg[i].AddrTmg;
- DctOdcCtl = PSCfg[i].Odc;
- break;
- }
- }
- }
- }
-
- ASSERT (i < GET_SIZE_OF (PSCfg));
-
- //
- // Programmable Dimm ODT
- //
- for (i = 0; i < GET_SIZE_OF (PSCfgDIMMsODT); i++) {
- if (Dimms != PSCfgDIMMsODT[i].Dimms) {
- continue;
- }
- DimmTpMatch = 0;
- _DIMMRankType = DIMMRankType & PSCfgDIMMsODT[i].DIMMRankType;
- for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
- if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
- DimmTpMatch++;
- }
- }
- if (DimmTpMatch == PSCfgDIMMsODT[i].Dimms) {
- PhyRODTCS = PSCfgDIMMsODT[i].PhyRODTCSLow;
- PhyWODTCS = PSCfgDIMMsODT[i].PhyWODTCSLow;
- break;
- }
- }
-
- //
- //WL ODT
- //
- PhyWLODT[0] = (UINT8) (PhyWODTCS & 0x0F);
- PhyWLODT[1] = (UINT8) ((PhyWODTCS >> 16) & 0x0F);
- PhyWLODT[2] = PhyWLODT[3] = 0;
-
- //
- // Overrides and/or exceptions
- //
- CurrentChannel->MemClkDisMap = (UINT8 *) OnUDdr3CLKDis;
- CurrentChannel->CKETriMap = (UINT8 *) OnUDdr3CKETri;
- CurrentChannel->ODTTriMap = (UINT8 *) OnUDdr3ODTTri;
- CurrentChannel->ChipSelTriMap = (UINT8 *) OnUDdr3CSTri;
-
- CurrentChannel->DctEccDqsLike = 0x0403;
- CurrentChannel->DctEccDqsScale = 0x70;
- CurrentChannel->DctAddrTmg = AddrTmgCTL;
- CurrentChannel->DctOdcCtl = DctOdcCtl;
- CurrentChannel->PhyRODTCSLow = PhyRODTCS;
- CurrentChannel->PhyWODTCSLow = PhyWODTCS;
- for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
- CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
- }
- CurrentChannel->SlowMode = SlowMode;
-
- return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ardk/PH/masph3.c b/src/vendorcode/amd/agesa/Proc/Mem/Ardk/PH/masph3.c
deleted file mode 100644
index 9da1e94..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ardk/PH/masph3.c
+++ /dev/null
@@ -1,261 +0,0 @@
-/* $NoKeywords:$ */
-/*
- * @file
- *
- * masph3.c
- *
- * Platform specific settings for PH DDR3 SO-dimms
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ardk/PH)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/* This file contains routine that add platform specific support S1g4 */
-
-
-#include "AGESA.h"
-#include "mport.h"
-#include "ma.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mu.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_ARDK_PH_MASPH3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-STATIC CONST UINT8 ROMDATA PhSDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
-// Even chip select maps to M[B,A]_CKE[0]
-// Odd chip select maps to M[B,A]_CKE[1]
-STATIC CONST UINT8 ROMDATA PhSDdr3CKETri[] = {0x55, 0xAA};
-// Bit 0: M[B,A]0_ODT[0]
-// Bit 1: M[B,A]1_ODT[0]
-// Bit 2: M[B,A]0_ODT[1]
-// Bit 3: M[B,A]1_ODT[1]
-STATIC CONST UINT8 ROMDATA PhSDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
-// Bit 0: M[B,A]0_CS_H/L[0]
-// Bit 1: M[B,A]0_CS_H/L[1]
-// Bit 2: M[B,A]0_CS_H/L[2]
-// Bit 3: M[B,A]0_CS_H/L[3]
-STATIC CONST UINT8 ROMDATA PhSDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for PH DDR3 SO-dimms
- *
- *
- * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE
- * @param[in] SocketID Socket number
- * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT
- *
- * @return AGESA_SUCCESS
- * @return CurrentChannel->MemClkDisMap Points this pointer to RB MemClkDis table
- * @return CurrentChannel->ChipSelTriMap Points this pointer to RB CS table
- * @return CurrentChannel->CKETriMap Points this pointer to RB ODT table
- * @return CurrentChannel->ODTTriMap Points this pointer to RB CKE table
- * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC
- * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte
- * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel
- * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel
- * @return CurrentChannel->SlowMode Slow Mode
- *
- *
- */
-
-AGESA_STATUS
-MemAGetPsCfgSPh3 (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- )
-{
- STATIC CONST PSCFG_ENTRY PSCfg[] = {
- {DDR800_FREQUENCY, 0xFF, 0x00000000, 0x00113222},
- {DDR1066_FREQUENCY, 0xFF, 0x00000000, 0x10113222},
- {DDR1333_FREQUENCY, 0xFF, 0x00000000, 0x20113222},
- };
-
- STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfgDIMMWlODT[] = {
- {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1},
- {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}
- };
-
- UINT16 i;
- UINT16 j;
- UINT8 Loads;
- UINT8 Dimms;
- UINT16 Speed;
- UINT32 AddrTmgCTL;
- UINT32 DctOdcCtl;
- UINT8 PhyWLODT[4];
- BOOLEAN SlowMode;
- UINT8 MaxDimmPerCH;
- UINT8 *DimmsPerChPtr;
- UINT16 DIMMRankType;
- UINT16 _DIMMRankType;
- UINT8 DimmTpMatch;
-
- ASSERT (MemData != 0);
- ASSERT (CurrentChannel != 0);
-
- AddrTmgCTL = 0;
- DctOdcCtl = 0;
- PhyWLODT[0] = 0x0F;
- PhyWLODT[1] = 0x0F;
- PhyWLODT[2] = 0x0F;
- PhyWLODT[3] = 0x0F;
- SlowMode = FALSE; // 1T
- if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_PH) == 0) {
- return AGESA_UNSUPPORTED;
- }
- if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
- return AGESA_UNSUPPORTED;
- }
- if (CurrentChannel->SODimmPresent != CurrentChannel->ChDimmValid) {
- return AGESA_UNSUPPORTED;
- }
- // Prepare inputs
- Loads = CurrentChannel->Loads;
- Dimms = CurrentChannel->Dimms;
- Speed = CurrentChannel->DCTPtr->Timings.Speed;
-
- DIMMRankType = MemAGetPsRankType (CurrentChannel);
-
- DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID);
- if (DimmsPerChPtr != NULL) {
- MaxDimmPerCH = *DimmsPerChPtr;
- } else {
- MaxDimmPerCH = 2;
- }
-
- for (i = 0; i < GET_SIZE_OF (PSCfg); i++) {
- if (Speed == PSCfg[i].Speed) {
- if (Loads <= PSCfg[i].Loads) {
- AddrTmgCTL = PSCfg[i].AddrTmg;
- DctOdcCtl = PSCfg[i].Odc;
- break;
- }
- }
- }
-
- // WL ODT
- for (i = 0; i < GET_SIZE_OF (PSCfgDIMMWlODT); i++) {
- if (Dimms != PSCfgDIMMWlODT[i].Dimms) {
- continue;
- }
- DimmTpMatch = 0;
- _DIMMRankType = DIMMRankType & PSCfgDIMMWlODT[i].DIMMRankType;
- for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
- if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
- DimmTpMatch++;
- }
- }
- if (DimmTpMatch == PSCfgDIMMWlODT[i].Dimms) {
- PhyWLODT[0] = PSCfgDIMMWlODT[i].PhyWrLvOdt[0];
- PhyWLODT[1] = PSCfgDIMMWlODT[i].PhyWrLvOdt[1];
- PhyWLODT[2] = PSCfgDIMMWlODT[i].PhyWrLvOdt[2];
- PhyWLODT[3] = PSCfgDIMMWlODT[i].PhyWrLvOdt[3];
- break;
- }
- }
-
- //
- // Overrides and/or exceptions
- //
- if (MaxDimmPerCH == 2) {
- if (Dimms == 2) {
- DctOdcCtl = 0x20223323;
- SlowMode = TRUE;
- if (Speed == DDR800_FREQUENCY) {
- AddrTmgCTL = 0x00000039;
- } else if (Speed == DDR1066_FREQUENCY) {
- AddrTmgCTL = 0x00000037;
- }
- } else {
- DctOdcCtl = 0x20113222;
- }
- } else {
- if (CurrentChannel->DimmSRPresent != 0) {
- PhyWLODT[0] = 1;
- } else if (CurrentChannel->DimmDrPresent != 0) {
- PhyWLODT[0] = 4;
- }
- }
-
- CurrentChannel->MemClkDisMap = (UINT8 *) PhSDdr3CLKDis;
- CurrentChannel->CKETriMap = (UINT8 *) PhSDdr3CKETri;
- CurrentChannel->ODTTriMap = (UINT8 *) PhSDdr3ODTTri;
- CurrentChannel->ChipSelTriMap = (UINT8 *) PhSDdr3CSTri;
-
- CurrentChannel->DctAddrTmg = AddrTmgCTL;
- CurrentChannel->DctOdcCtl = DctOdcCtl;
- for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
- CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
- }
- CurrentChannel->SlowMode = SlowMode;
-
- return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ardk/PH/mauPh3.c b/src/vendorcode/amd/agesa/Proc/Mem/Ardk/PH/mauPh3.c
deleted file mode 100644
index 68954ed..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ardk/PH/mauPh3.c
+++ /dev/null
@@ -1,260 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mauph3.c
- *
- * Platform specific settings for PH DDR3 unbuffered dimms
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ardk/PH)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/* This file contains routine that add platform specific support AM3 */
-
-
-#include "AGESA.h"
-#include "mport.h"
-#include "PlatformMemoryConfiguration.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_ARDK_PH_MAUPH3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-STATIC CONST UINT8 ROMDATA PhUDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
-// Even chip select maps to M[B,A]_CKE[0]
-// Odd chip select maps to M[B,A]_CKE[1]
-STATIC CONST UINT8 ROMDATA PhUDdr3CKETri[] = {0x55, 0xAA};
-// Bit 0: M[B,A]0_ODT[0]
-// Bit 1: M[B,A]1_ODT[0]
-// Bit 2: M[B,A]0_ODT[1]
-// Bit 3: M[B,A]1_ODT[1]
-STATIC CONST UINT8 ROMDATA PhUDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
-// Bit 0: M[B,A]0_CS_H/L[0]
-// Bit 1: M[B,A]0_CS_H/L[1]
-// Bit 2: M[B,A]0_CS_H/L[2]
-// Bit 3: M[B,A]0_CS_H/L[3]
-STATIC CONST UINT8 ROMDATA PhUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for PH DDR3 unbuffered dimms
- *
- *
- * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE
- * @param[in] SocketID Socket number
- * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT
- *
- * @return AGESA_SUCCESS
- * @return CurrentChannel->MemClkDisMap Points this pointer to PH MemClkDis table
- * @return CurrentChannel->ChipSelTriMap Points this pointer to PH CS table
- * @return CurrentChannel->CKETriMap Points this pointer to PH ODT table
- * @return CurrentChannel->ODTTriMap Points this pointer to PH CKE table
- * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC
- * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte
- * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel
- * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel
- * @return CurrentChannel->SlowMode Slow Mode
- *
- */
-
-AGESA_STATUS
-MemAGetPsCfgUPh3 (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- )
-{
- STATIC CONST PSCFG_ENTRY PSCfg1Dimm[] = {
- {DDR800_FREQUENCY, 0x10, 0x003B0000, 0x20113222},
- {DDR1066_FREQUENCY, 0x10, 0x00380000, 0x20113222},
- {DDR1333_FREQUENCY, 0x10, 0x00360000, 0x20113222},
- {DDR1600_FREQUENCY, 0x10, 0x00340000, 0x20113222}
- };
- STATIC CONST PSCFG_ENTRY PSCfg2Dimm[] = {
- {DDR800_FREQUENCY, 0xFF, 0x00390039, 0x20223323},
- {DDR1066_FREQUENCY, 0xFF, 0x00350037, 0x20223323},
- {DDR1333_FREQUENCY, 0xFF, 0x00000035, 0x20223323},
- {DDR1600_FREQUENCY, 0xFF, 0x00000033, 0x20223323}
- };
-
- STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfgDIMMWlODT[] = {
- {SR_DIMM0, {0x01, 0x00, 0x00, 0x00}, 1},
- {DR_DIMM0, {0x04, 0x00, 0x00, 0x00}, 1},
- {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1},
- {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}
- };
-
- UINT16 i;
- UINT16 j;
- UINT8 Loads;
- UINT8 Dimms;
- UINT16 Speed;
- UINT16 DIMMRankType;
- UINT16 _DIMMRankType;
- UINT32 AddrTmgCTL;
- UINT32 DctOdcCtl;
- UINT8 PhyWLODT[4];
- BOOLEAN SlowMode;
- UINT8 DimmTpMatch;
-
- ASSERT (MemData != 0);
- ASSERT (CurrentChannel != 0);
-
- AddrTmgCTL = 0;
- DctOdcCtl = 0;
- PhyWLODT[0] = 0x0F;
- PhyWLODT[1] = 0x0F;
- PhyWLODT[2] = 0x0F;
- PhyWLODT[3] = 0x0F;
-
- if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_PH) == 0) {
- return AGESA_UNSUPPORTED;
- }
- if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
- return AGESA_UNSUPPORTED;
- }
- if ((CurrentChannel->RegDimmPresent != 0) || (CurrentChannel->SODimmPresent != 0)) {
- return AGESA_UNSUPPORTED;
- }
- // Prepare inputs
- Loads = CurrentChannel->Loads;
- Dimms = CurrentChannel->Dimms;
- Speed = CurrentChannel->DCTPtr->Timings.Speed;
- DIMMRankType = MemAGetPsRankType (CurrentChannel);
-
- if ((Speed == DDR1333_FREQUENCY || Speed == DDR1600_FREQUENCY) && (Dimms == 2)) {
- SlowMode = TRUE; // 2T
- } else if ((Speed == DDR1600_FREQUENCY) && (Dimms == 1) && (Loads >= 16)) {
- SlowMode = TRUE; // 2T
- } else {
- SlowMode = FALSE; // 1T
- }
-
- if (Dimms == 1) {
- for (i = 0; i < GET_SIZE_OF (PSCfg1Dimm); i++) {
- if (Speed == PSCfg1Dimm[i].Speed) {
- if (Loads >= PSCfg1Dimm[i].Loads) {
- AddrTmgCTL = PSCfg1Dimm[i].AddrTmg;
- DctOdcCtl = PSCfg1Dimm[i].Odc;
- } else {
- DctOdcCtl = 0x20113222;
- }
- break;
- }
- }
- ASSERT (i < GET_SIZE_OF (PSCfg1Dimm));
- } else {
- for (i = 0; i < GET_SIZE_OF (PSCfg2Dimm); i++) {
- if (Speed == PSCfg2Dimm[i].Speed) {
- if (Loads <= PSCfg2Dimm[i].Loads) {
- AddrTmgCTL = PSCfg2Dimm[i].AddrTmg;
- DctOdcCtl = PSCfg2Dimm[i].Odc;
- break;
- }
- }
- }
- ASSERT (i < GET_SIZE_OF (PSCfg2Dimm));
- }
-
- // WL ODT
- for (i = 0; i < GET_SIZE_OF (PSCfgDIMMWlODT); i++) {
- if (Dimms != PSCfgDIMMWlODT[i].Dimms) {
- continue;
- }
- DimmTpMatch = 0;
- _DIMMRankType = DIMMRankType & PSCfgDIMMWlODT[i].DIMMRankType;
- for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
- if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
- DimmTpMatch++;
- }
- }
- if (DimmTpMatch == PSCfgDIMMWlODT[i].Dimms) {
- PhyWLODT[0] = PSCfgDIMMWlODT[i].PhyWrLvOdt[0];
- PhyWLODT[1] = PSCfgDIMMWlODT[i].PhyWrLvOdt[1];
- PhyWLODT[2] = PSCfgDIMMWlODT[i].PhyWrLvOdt[2];
- PhyWLODT[3] = PSCfgDIMMWlODT[i].PhyWrLvOdt[3];
- break;
- }
- }
-
- CurrentChannel->MemClkDisMap = (UINT8 *) PhUDdr3CLKDis;
- CurrentChannel->CKETriMap = (UINT8 *) PhUDdr3CKETri;
- CurrentChannel->ODTTriMap = (UINT8 *) PhUDdr3ODTTri;
- CurrentChannel->ChipSelTriMap = (UINT8 *) PhUDdr3CSTri;
-
- CurrentChannel->DctEccDqsLike = 0x0403;
- CurrentChannel->DctEccDqsScale = 0x70;
- CurrentChannel->DctAddrTmg = AddrTmgCTL;
- CurrentChannel->DctOdcCtl = DctOdcCtl;
- for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
- CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
- }
- CurrentChannel->SlowMode = SlowMode;
-
- return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ardk/RB/masRb3.c b/src/vendorcode/amd/agesa/Proc/Mem/Ardk/RB/masRb3.c
deleted file mode 100644
index 363c52b..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ardk/RB/masRb3.c
+++ /dev/null
@@ -1,260 +0,0 @@
-/* $NoKeywords:$ */
-/*
- * @file
- *
- * masRb3.c
- *
- * Platform specific settings for RB DDR3 SO-dimms
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ardk/RB)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-
-#include "AGESA.h"
-#include "mport.h"
-#include "ma.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mu.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_ARDK_RB_MASRB3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-STATIC CONST UINT8 ROMDATA RbSDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
-// Even chip select maps to M[B,A]_CKE[0]
-// Odd chip select maps to M[B,A]_CKE[1]
-STATIC CONST UINT8 ROMDATA RbSDdr3CKETri[] = {0x55, 0xAA};
-// Bit 0: M[B,A]0_ODT[0]
-// Bit 1: M[B,A]1_ODT[0]
-// Bit 2: M[B,A]0_ODT[1]
-// Bit 3: M[B,A]1_ODT[1]
-STATIC CONST UINT8 ROMDATA RbSDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
-// Bit 0: M[B,A]0_CS_H/L[0]
-// Bit 1: M[B,A]0_CS_H/L[1]
-// Bit 2: M[B,A]0_CS_H/L[2]
-// Bit 3: M[B,A]0_CS_H/L[3]
-STATIC CONST UINT8 ROMDATA RbSDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for RB DDR3 SO-dimms
- *
- *
- * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE
- * @param[in] SocketID Socket number
- * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT
- *
- * @return AGESA_SUCCESS
- * @return CurrentChannel->MemClkDisMap Points this pointer to RB MemClkDis table
- * @return CurrentChannel->ChipSelTriMap Points this pointer to RB CS table
- * @return CurrentChannel->CKETriMap Points this pointer to RB ODT table
- * @return CurrentChannel->ODTTriMap Points this pointer to RB CKE table
- * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC
- * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte
- * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel
- * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel
- * @return CurrentChannel->SlowMode Slow Mode
- *
- *
- */
-
-AGESA_STATUS
-MemAGetPsCfgSRb3 (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- )
-{
- STATIC CONST PSCFG_ENTRY PSCfg[] = {
- {DDR800_FREQUENCY, 0xFF, 0x00000000, 0x00113222},
- {DDR1066_FREQUENCY, 0xFF, 0x00000000, 0x10113222},
- {DDR1333_FREQUENCY, 0xFF, 0x00000000, 0x20113222},
- };
-
- STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfgDIMMWlODT[] = {
- {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1},
- {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}
- };
-
- UINT16 i;
- UINT16 j;
- UINT8 Loads;
- UINT8 Dimms;
- UINT16 Speed;
- UINT32 AddrTmgCTL;
- UINT32 DctOdcCtl;
- UINT8 PhyWLODT[4];
- BOOLEAN SlowMode;
- UINT8 MaxDimmPerCH;
- UINT8 *DimmsPerChPtr;
- UINT16 DIMMRankType;
- UINT16 _DIMMRankType;
- UINT8 DimmTpMatch;
-
- ASSERT (MemData != 0);
- ASSERT (CurrentChannel != 0);
-
- AddrTmgCTL = 0;
- DctOdcCtl = 0;
- PhyWLODT[0] = 0x0F;
- PhyWLODT[1] = 0x0F;
- PhyWLODT[2] = 0x0F;
- PhyWLODT[3] = 0x0F;
- SlowMode = FALSE; // 1T
- if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) {
- return AGESA_UNSUPPORTED;
- }
- if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
- return AGESA_UNSUPPORTED;
- }
- if (CurrentChannel->SODimmPresent != CurrentChannel->ChDimmValid) {
- return AGESA_UNSUPPORTED;
- }
- // Prepare inputs
- Loads = CurrentChannel->Loads;
- Dimms = CurrentChannel->Dimms;
- Speed = CurrentChannel->DCTPtr->Timings.Speed;
-
- DIMMRankType = MemAGetPsRankType (CurrentChannel);
-
- DimmsPerChPtr = FindPSOverrideEntry (MemData->ParameterListPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, CurrentChannel->ChannelID);
- if (DimmsPerChPtr != NULL) {
- MaxDimmPerCH = *DimmsPerChPtr;
- } else {
- MaxDimmPerCH = 2;
- }
-
- for (i = 0; i < GET_SIZE_OF (PSCfg); i++) {
- if (Speed == PSCfg[i].Speed) {
- if (Loads <= PSCfg[i].Loads) {
- AddrTmgCTL = PSCfg[i].AddrTmg;
- DctOdcCtl = PSCfg[i].Odc;
- break;
- }
- }
- }
-
- // WL ODT
- for (i = 0; i < GET_SIZE_OF (PSCfgDIMMWlODT); i++) {
- if (Dimms != PSCfgDIMMWlODT[i].Dimms) {
- continue;
- }
- DimmTpMatch = 0;
- _DIMMRankType = DIMMRankType & PSCfgDIMMWlODT[i].DIMMRankType;
- for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
- if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
- DimmTpMatch++;
- }
- }
- if (DimmTpMatch == PSCfgDIMMWlODT[i].Dimms) {
- PhyWLODT[0] = PSCfgDIMMWlODT[i].PhyWrLvOdt[0];
- PhyWLODT[1] = PSCfgDIMMWlODT[i].PhyWrLvOdt[1];
- PhyWLODT[2] = PSCfgDIMMWlODT[i].PhyWrLvOdt[2];
- PhyWLODT[3] = PSCfgDIMMWlODT[i].PhyWrLvOdt[3];
- break;
- }
- }
-
- //
- // Overrides and/or exceptions
- //
- if (MaxDimmPerCH == 2) {
- if (Dimms == 2) {
- DctOdcCtl = 0x20223323;
- SlowMode = TRUE;
- if (Speed == DDR800_FREQUENCY) {
- AddrTmgCTL = 0x00000039;
- } else if (Speed == DDR1066_FREQUENCY) {
- AddrTmgCTL = 0x00000037;
- }
- } else {
- DctOdcCtl = 0x20113222;
- }
- } else {
- if (CurrentChannel->DimmSRPresent != 0) {
- PhyWLODT[0] = 1;
- } else if (CurrentChannel->DimmDrPresent != 0) {
- PhyWLODT[0] = 4;
- }
- }
-
- CurrentChannel->MemClkDisMap = (UINT8 *) RbSDdr3CLKDis;
- CurrentChannel->CKETriMap = (UINT8 *) RbSDdr3CKETri;
- CurrentChannel->ODTTriMap = (UINT8 *) RbSDdr3ODTTri;
- CurrentChannel->ChipSelTriMap = (UINT8 *) RbSDdr3CSTri;
-
- CurrentChannel->DctAddrTmg = AddrTmgCTL;
- CurrentChannel->DctOdcCtl = DctOdcCtl;
- for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
- CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
- }
- CurrentChannel->SlowMode = SlowMode;
-
- return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ardk/RB/mauRb3.c b/src/vendorcode/amd/agesa/Proc/Mem/Ardk/RB/mauRb3.c
deleted file mode 100644
index fab9631..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ardk/RB/mauRb3.c
+++ /dev/null
@@ -1,259 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mauRb3.c
- *
- * Platform specific settings for RB DDR3 unbuffered dimms
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ardk/RB)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-
-#include "AGESA.h"
-#include "mport.h"
-#include "PlatformMemoryConfiguration.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_ARDK_RB_MAURB3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-STATIC CONST UINT8 ROMDATA RbUDdr3CLKDis[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
-// Even chip select maps to M[B,A]_CKE[0]
-// Odd chip select maps to M[B,A]_CKE[1]
-STATIC CONST UINT8 ROMDATA RbUDdr3CKETri[] = {0x55, 0xAA};
-// Bit 0: M[B,A]0_ODT[0]
-// Bit 1: M[B,A]1_ODT[0]
-// Bit 2: M[B,A]0_ODT[1]
-// Bit 3: M[B,A]1_ODT[1]
-STATIC CONST UINT8 ROMDATA RbUDdr3ODTTri[] = {0x01, 0x04, 0x02, 0x08};
-// Bit 0: M[B,A]0_CS_H/L[0]
-// Bit 1: M[B,A]0_CS_H/L[1]
-// Bit 2: M[B,A]0_CS_H/L[2]
-// Bit 3: M[B,A]0_CS_H/L[3]
-STATIC CONST UINT8 ROMDATA RbUDdr3CSTri[] = {0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for RB DDR3 Unbuffered dimms
- *
- *
- * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE
- * @param[in] SocketID Socket number
- * @param[in,out] *CurrentChannel Pointer to CH_DEF_STRUCT
- *
- * @return AGESA_SUCCESS
- * @return CurrentChannel->MemClkDisMap Points this pointer to RB MemClkDis table
- * @return CurrentChannel->ChipSelTriMap Points this pointer to RB CS table
- * @return CurrentChannel->CKETriMap Points this pointer to RB ODT table
- * @return CurrentChannel->ODTTriMap Points this pointer to RB CKE table
- * @return CurrentChannel->DctEccDQSLike Indicates the bytes that should be averaged for ECC
- * @return CurrentChannel->DctEccDQSScale Indicates the scale that should be used for Averaging ECC byte
- * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel
- * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel
- * @return CurrentChannel->SlowMode Slow Mode
- *
- */
-
-AGESA_STATUS
-MemAGetPsCfgURb3 (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- )
-{
- STATIC CONST PSCFG_ENTRY PSCfg1Dimm[] = {
- {DDR800_FREQUENCY, 0x10, 0x003B0000, 0x20113222},
- {DDR1066_FREQUENCY, 0x10, 0x00380000, 0x20113222},
- {DDR1333_FREQUENCY, 0x10, 0x00360000, 0x20113222},
- {DDR1600_FREQUENCY, 0x10, 0x00340000, 0x20113222}
- };
- STATIC CONST PSCFG_ENTRY PSCfg2Dimm[] = {
- {DDR800_FREQUENCY, 0xFF, 0x00390039, 0x20223323},
- {DDR1066_FREQUENCY, 0xFF, 0x00350037, 0x20223323},
- {DDR1333_FREQUENCY, 0xFF, 0x00000035, 0x20223323},
- {DDR1600_FREQUENCY, 0xFF, 0x00000033, 0x20223323}
- };
-
- STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY PSCfgDIMMWlODT[] = {
- {SR_DIMM0, {0x01, 0x00, 0x00, 0x00}, 1},
- {DR_DIMM0, {0x04, 0x00, 0x00, 0x00}, 1},
- {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1},
- {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2}
- };
-
- UINT16 i;
- UINT16 j;
- UINT8 Loads;
- UINT8 Dimms;
- UINT16 Speed;
- UINT16 DIMMRankType;
- UINT16 _DIMMRankType;
- UINT32 AddrTmgCTL;
- UINT32 DctOdcCtl;
- UINT8 PhyWLODT[4];
- BOOLEAN SlowMode;
- UINT8 DimmTpMatch;
-
- ASSERT (MemData != 0);
- ASSERT (CurrentChannel != 0);
-
- AddrTmgCTL = 0;
- DctOdcCtl = 0;
- PhyWLODT[0] = 0x0F;
- PhyWLODT[1] = 0x0F;
- PhyWLODT[2] = 0x0F;
- PhyWLODT[3] = 0x0F;
-
- if ((CurrentChannel->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) {
- return AGESA_UNSUPPORTED;
- }
- if (CurrentChannel->TechType != DDR3_TECHNOLOGY) {
- return AGESA_UNSUPPORTED;
- }
- if ((CurrentChannel->RegDimmPresent != 0) || (CurrentChannel->SODimmPresent != 0)) {
- return AGESA_UNSUPPORTED;
- }
- // Prepare inputs
- Loads = CurrentChannel->Loads;
- Dimms = CurrentChannel->Dimms;
- Speed = CurrentChannel->DCTPtr->Timings.Speed;
- DIMMRankType = MemAGetPsRankType (CurrentChannel);
-
- if ((Speed == DDR1333_FREQUENCY || Speed == DDR1600_FREQUENCY) && (Dimms == 2)) {
- SlowMode = TRUE; // 2T
- } else if ((Speed == DDR1600_FREQUENCY) && (Dimms == 1) && (Loads >= 16)) {
- SlowMode = TRUE; // 2T
- } else {
- SlowMode = FALSE; // 1T
- }
-
- if (Dimms == 1) {
- for (i = 0; i < GET_SIZE_OF (PSCfg1Dimm); i++) {
- if (Speed == PSCfg1Dimm[i].Speed) {
- if (Loads >= PSCfg1Dimm[i].Loads) {
- AddrTmgCTL = PSCfg1Dimm[i].AddrTmg;
- DctOdcCtl = PSCfg1Dimm[i].Odc;
- } else {
- DctOdcCtl = 0x20113222;
- }
- break;
- }
- }
- ASSERT (i < GET_SIZE_OF (PSCfg1Dimm));
- } else {
- for (i = 0; i < GET_SIZE_OF (PSCfg2Dimm); i++) {
- if (Speed == PSCfg2Dimm[i].Speed) {
- if (Loads <= PSCfg2Dimm[i].Loads) {
- AddrTmgCTL = PSCfg2Dimm[i].AddrTmg;
- DctOdcCtl = PSCfg2Dimm[i].Odc;
- break;
- }
- }
- }
- ASSERT (i < GET_SIZE_OF (PSCfg2Dimm));
- }
-
- // WL ODT
- for (i = 0; i < GET_SIZE_OF (PSCfgDIMMWlODT); i++) {
- if (Dimms != PSCfgDIMMWlODT[i].Dimms) {
- continue;
- }
- DimmTpMatch = 0;
- _DIMMRankType = DIMMRankType & PSCfgDIMMWlODT[i].DIMMRankType;
- for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
- if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
- DimmTpMatch++;
- }
- }
- if (DimmTpMatch == PSCfgDIMMWlODT[i].Dimms) {
- PhyWLODT[0] = PSCfgDIMMWlODT[i].PhyWrLvOdt[0];
- PhyWLODT[1] = PSCfgDIMMWlODT[i].PhyWrLvOdt[1];
- PhyWLODT[2] = PSCfgDIMMWlODT[i].PhyWrLvOdt[2];
- PhyWLODT[3] = PSCfgDIMMWlODT[i].PhyWrLvOdt[3];
- break;
- }
- }
-
- CurrentChannel->MemClkDisMap = (UINT8 *) RbUDdr3CLKDis;
- CurrentChannel->CKETriMap = (UINT8 *) RbUDdr3CKETri;
- CurrentChannel->ODTTriMap = (UINT8 *) RbUDdr3ODTTri;
- CurrentChannel->ChipSelTriMap = (UINT8 *) RbUDdr3CSTri;
-
- CurrentChannel->DctEccDqsLike = 0x0403;
- CurrentChannel->DctEccDqsScale = 0x70;
- CurrentChannel->DctAddrTmg = AddrTmgCTL;
- CurrentChannel->DctOdcCtl = DctOdcCtl;
- for (i = 0; i < sizeof (CurrentChannel->PhyWLODT); i++) {
- CurrentChannel->PhyWLODT[i] = PhyWLODT[i];
- }
- CurrentChannel->SlowMode = SlowMode;
-
- return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ardk/ma.c b/src/vendorcode/amd/agesa/Proc/Mem/Ardk/ma.c
deleted file mode 100644
index b59bef8..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ardk/ma.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * ma.c
- *
- * Initializes ARDK Block
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ardk)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-#include "AGESA.h"
-#include "ma.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_ARDK_MA_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is the default return function of the ARDK block. The function always
- * returns AGESA_UNSUPPORTED
- *
- * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE
- * @param[in] SocketID Socket number
- * @param[in] *CurrentChannel Pointer to CH_DEF_STRUCT
- *
- * @return AGESA_UNSUPPORTED AGESA status indicating that default is unsupported
- *
- */
-
-AGESA_STATUS
-MemAGetPsCfgDef (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- )
-{
- return AGESA_UNSUPPORTED;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function returns the rank type map of a channel.
- *
- * @param[in] *CurrentChannel Pointer to CH_DEF_STRUCT
- *
- * @return UINT16 - The map of rank type.
- *
- */
-UINT16
-MemAGetPsRankType (
- IN CH_DEF_STRUCT *CurrentChannel
- )
-{
- UINT8 i;
- UINT16 DIMMRankType;
-
- DIMMRankType = 0;
- for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) {
- if ((CurrentChannel->DimmQrPresent & (UINT8) 1 << i) != 0) {
- if (i < 2) {
- DIMMRankType |= (UINT16) 4 << (i << 2);
- }
- } else if ((CurrentChannel->DimmDrPresent & (UINT8) 1 << i) != 0) {
- DIMMRankType |= (UINT16) 2 << (i << 2);
- } else if ((CurrentChannel->DimmSRPresent & (UINT8) 1 << i) != 0) {
- DIMMRankType |= (UINT16) 1 << (i << 2);
- }
- }
- return DIMMRankType;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Feat/CHINTLV/mfchi.c b/src/vendorcode/amd/agesa/Proc/Mem/Feat/CHINTLV/mfchi.c
deleted file mode 100644
index 1e74421..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Feat/CHINTLV/mfchi.c
+++ /dev/null
@@ -1,213 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mfchi.c
- *
- * Feature Channel interleaving support
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Feat/Chintlv)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "mm.h"
-#include "mn.h"
-#include "mfchi.h"
-#include "Ids.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_FEAT_CHINTLV_MFCHI_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define _4GB_ (0x10000 >> 10)
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * MemFInterleaveChannels:
- *
- * Applies DIMM channel interleaving if enabled, if not ganged mode, and
- * there are valid dimms in both channels. Called once per Node.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - This feature is enabled.
- * @return FALSE - This feature is not enabled.
- */
-
-BOOLEAN
-MemFInterleaveChannels (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT32 DramBase;
- UINT32 DctSelBase;
- UINT32 HoleSize;
- UINT32 HoleBase;
- UINT32 HoleOffset;
- UINT32 Dct0Size;
- UINT32 Dct1Size;
- UINT32 SmallerDct;
- UINT8 DctSelIntLvAddr;
- UINT8 DctSelHi;
- UINT8 DctSelHiRngEn;
- UINT32 HoleValid;
-
- MEM_PARAMETER_STRUCT *RefPtr;
- DIE_STRUCT *MCTPtr;
-
- ASSERT (NBPtr != NULL);
-
- RefPtr = NBPtr->RefPtr;
-
- DctSelIntLvAddr = NBPtr->DefDctSelIntLvAddr;
- if (RefPtr->EnableChannelIntlv) {
- HoleSize = 0;
- HoleBase = 0;
- if (RefPtr->GStatus[GsbSoftHole] || RefPtr->GStatus[GsbHWHole]) {
- // HoleBase scaled from [47:16] to [47:26]
- HoleBase = RefPtr->HoleBase >> 10;
- HoleSize = _4GB_ - HoleBase;
- }
-
- MCTPtr = NBPtr->MCTPtr;
-
- HoleValid = NBPtr->GetBitField (NBPtr, BFDramHoleValid);
- if ((!MCTPtr->GangedMode) &&
- (MCTPtr->DctData[0].Timings.DctMemSize != 0) &&
- (MCTPtr->DctData[1].Timings.DctMemSize != 0)) {
- // DramBase scaled [47:16] to [47:26]
- DramBase = MCTPtr->NodeSysBase >> 10;
- // Scale NodeSysLimit [47:16] to [47:26]
- Dct1Size = (MCTPtr->NodeSysLimit + 1) >> 10;
- Dct0Size = NBPtr->GetBitField (NBPtr, BFDctSelBaseOffset);
- if ((Dct0Size >= _4GB_) && (DramBase < HoleBase)) {
- Dct0Size -= HoleSize;
- }
- if ((Dct1Size >= _4GB_) && (DramBase < HoleBase)) {
- Dct1Size -= HoleSize;
- }
- Dct1Size -= Dct0Size;
- Dct0Size -= DramBase;
-
- // Select the bigger size DCT to put in DctSelHi
- DctSelHiRngEn = 1;
- DctSelHi = 0;
- SmallerDct = Dct1Size;
- if (Dct1Size == Dct0Size) {
- SmallerDct = 0;
- DctSelHiRngEn = 0;
- } else if (Dct1Size > Dct0Size) {
- SmallerDct = Dct0Size;
- DctSelHi = 1;
- }
-
- if (SmallerDct != 0) {
- DctSelBase = (SmallerDct * 2) + DramBase;
- } else {
- DctSelBase = 0;
- }
- if ((DctSelBase >= HoleBase) && (DramBase < HoleBase)) {
- DctSelBase += HoleSize;
- }
- IDS_OPTION_HOOK (IDS_CHANNEL_INTERLEAVE, &DctSelIntLvAddr, &(NBPtr->MemPtr->StdHeader));
- NBPtr->SetBitField (NBPtr, BFDctSelBaseAddr, DctSelBase >> 1);
- NBPtr->SetBitField (NBPtr, BFDctSelHiRngEn, DctSelHiRngEn);
- NBPtr->SetBitField (NBPtr, BFDctSelHi, DctSelHi);
- NBPtr->SetBitField (NBPtr, BFDctSelIntLvAddr, DctSelIntLvAddr);
- NBPtr->SetBitField (NBPtr, BFDctSelIntLvEn, 1);
-
- // DctSelBaseOffset = DctSelBaseAddr - Interleaved region
- NBPtr->SetBitField (NBPtr, BFDctSelBaseOffset, DctSelBase - SmallerDct);
-
- // Adjust DramHoleOffset
- if (HoleValid != 0) {
- HoleOffset = DramBase;
- if ((DctSelBase < HoleBase) && (DctSelBase != 0)) {
- HoleOffset += (DctSelBase - DramBase) >> 1;
- }
- HoleOffset += HoleSize;
- NBPtr->SetBitField (NBPtr, BFDramHoleOffset, HoleOffset << 3);
- }
- } else {
- //
- // Channel Interleaving is requested but cannot be enabled
- //
- PutEventLog (AGESA_WARNING, MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED, NBPtr->Node, 0, 0, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_WARNING, MCTPtr);
- }
-
- return TRUE;
- } else {
- return FALSE;
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Feat/CHINTLV/mfchi.h b/src/vendorcode/amd/agesa/Proc/Mem/Feat/CHINTLV/mfchi.h
deleted file mode 100644
index 6006c2b..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Feat/CHINTLV/mfchi.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mfchi.h
- *
- * Feature channel interleaving
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-#ifndef _MFCHI_H_
-#define _MFCHI_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-MemFInterleaveChannels (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-#endif /* _MFCHI_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Feat/CSINTLV/mfcsi.c b/src/vendorcode/amd/agesa/Proc/Mem/Feat/CSINTLV/mfcsi.c
deleted file mode 100644
index 812aa96..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Feat/CSINTLV/mfcsi.c
+++ /dev/null
@@ -1,341 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mfcsi.c
- *
- * Feature bank interleaving support (AKA Chip Select Interleaving )
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Feat/Csintlv)
- * @e \$Revision: 35912 $ @e \$Date: 2010-08-04 15:32:18 +0800 (Wed, 04 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/* This file contains functions for Chip Select interleaving */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mfcsi.h"
-#include "Ids.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_FEAT_CSINTLV_MFCSI_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-STATIC
-MemFDctInterleaveBanks (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-STATIC
-CsIntSwap (
- IN OUT UINT32 *BaseMaskRegPtr,
- IN UINT8 EnChipSels,
- IN UINT8 LoBit,
- IN UINT8 HiBit
- );
-
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function Applies DIMM bank (chip-select) interleaving if enabled
- * and if all criteria are met. Interleaves chip-selects on page boundaries.
- * This function calls subfunctions that sets up CS interleaving on multiple Sockets
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - This feature is enabled.
- * @return FALSE - This feature is not enabled.
- */
-
-BOOLEAN
-MemFInterleaveBanks (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 Dct;
- BOOLEAN RetFlag;
-
- ASSERT (NBPtr != NULL);
-
- RetFlag = FALSE;
- if (NBPtr->RefPtr->EnableBankIntlv) {
- if (NBPtr->MCTPtr->NodeMemSize) {
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- RetFlag |= MemFDctInterleaveBanks (NBPtr);
- }
- }
- }
- return RetFlag;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function checks if bank interleaving has been enabled or not. If yes, it will
- * undo bank interleaving. Otherwise, it does nothing.
- *
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - Bank interleaving has been enabled.
- * @return FALSE - Bank interleaving has not been enabled.
- */
-
-BOOLEAN
-MemFUndoInterleaveBanks (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 Cs;
- UINT8 Dct;
- UINT32 CSMask;
- BOOLEAN CSIntlvEnabled;
- BOOLEAN RetFlag;
-
- ASSERT (NBPtr != NULL);
-
- RetFlag = FALSE;
-
- if (NBPtr->RefPtr->EnableBankIntlv) {
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- if (NBPtr->DCTPtr->Timings.DctMemSize) {
- CSIntlvEnabled = FALSE;
- for (Cs = 0; Cs < MAX_CS_PER_CHANNEL; Cs++) {
- if ((NBPtr->GetBitField (NBPtr, BFCSBaseAddr0Reg + Cs) & 1) != 0) {
- CSMask = NBPtr->GetBitField (NBPtr, BFCSMask0Reg + (Cs / 2));
- if (((CSMask >> 5) & 0x1FF) != 0x1FF) {
- CSIntlvEnabled = TRUE;
- break;
- }
- }
- }
- if (CSIntlvEnabled) {
- MemFDctInterleaveBanks (NBPtr);
- RetFlag = TRUE;
- }
- }
- }
- }
- return RetFlag;
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function Applies DIMM bank (chip-select) interleaving if enabled
- * and if all criteria are met. Interleaves chip-selects on page boundaries.
- * This function is run once per Socket
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - Register bits have been swapped.
- * @return FALSE - Register bits have not been swapped.
- *
- */
-
-BOOLEAN
-STATIC
-MemFDctInterleaveBanks (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 Cs;
- UINT8 EnChipSels;
- UINT8 BankEncd;
- UINT8 BankEncd0;
- UINT8 i;
- UINT8 j;
- UINT32 BankAddrReg;
- UINT32 BaseRegS0;
- UINT32 BaseRegS1;
- UINT32 MaskReg;
- UINT8 Offset;
-
- ASSERT (NBPtr != NULL);
-
- // Check if CS interleaving can be enabled
- EnChipSels = 0;
- BankEncd0 = 0xFF;
- Offset = 0;
- for (Cs = 0; Cs < MAX_CS_PER_CHANNEL; Cs++) {
- if ((NBPtr->GetBitField (NBPtr, BFCSBaseAddr0Reg + Cs) & 1) != 0) {
- BankAddrReg = NBPtr->GetBitField (NBPtr, BFDramBankAddrReg);
- BankEncd = (UINT8) ((BankAddrReg >> ((Cs / 2) * 4)) & 0xF);
- if (BankEncd0 == 0xFF) {
- BankEncd0 = BankEncd;
- } else if (BankEncd0 != BankEncd) {
- break;
- }
- EnChipSels++;
- }
- }
-
- // Swap Dram Base/Mask Addr to enable CS interleaving
- if ((Cs == MAX_CS_PER_CHANNEL) && ((EnChipSels == 2) || (EnChipSels == 4) || (EnChipSels == 8))) {
- NBPtr->TechPtr->GetCSIntLvAddr (BankEncd0, &i, &j);
-
- if (NBPtr->MCTPtr->Status[Sb128bitmode]) {
- i++;
- j++;
- }
-
- for (Cs = 0; Cs < MAX_CS_PER_CHANNEL; Cs += 2) {
- //
- // LRDIMMS - Add an offset to the bit positions specified based on D18F2x[6C:60]_dct[1:0][RankDef] as follows:
- // RankDef=0xb: 0 RankDef=10b: 1 RankDef=11b: 2
- // Using RankMult information: Lo/HiBit <<= (Mult >> 1)
- //
- if (NBPtr->MCTPtr->Status[SbLrdimms]) {
- Offset = ((NBPtr->ChannelPtr->LrDimmRankMult[Cs >> 1]) >> 1);
- }
- BaseRegS0 = NBPtr->GetBitField (NBPtr, BFCSBaseAddr0Reg + Cs);
- BaseRegS1 = NBPtr->GetBitField (NBPtr, BFCSBaseAddr0Reg + Cs + 1);
- if (((BaseRegS0 | BaseRegS1) & 1) != 0) {
- // Swap Mask register bits
- MaskReg = NBPtr->GetBitField (NBPtr, BFCSMask0Reg + (Cs / 2));
- CsIntSwap (&MaskReg, EnChipSels, (i + Offset), (j + Offset));
- NBPtr->SetBitField (NBPtr, BFCSMask0Reg + (Cs / 2), MaskReg);
-
- // Swap Base register bits
- CsIntSwap (&BaseRegS0, EnChipSels, (i + Offset), (j + Offset));
- NBPtr->SetBitField (NBPtr, BFCSBaseAddr0Reg + Cs, BaseRegS0);
- CsIntSwap (&BaseRegS1, EnChipSels, (i + Offset), (j + Offset));
- NBPtr->SetBitField (NBPtr, BFCSBaseAddr0Reg + Cs + 1, BaseRegS1);
- }
- }
- return TRUE;
- } else {
- //
- // Bank Interleaving is requested but cannot be enabled
- //
- PutEventLog (AGESA_WARNING, MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_WARNING, NBPtr->MCTPtr);
- NBPtr->MCTPtr->ErrStatus[EsbBkIntDis] = TRUE;
- }
- return FALSE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This supporting function swaps Chip selects
- *
- * @param[in,out] *BaseMaskRegPtr - Pointer to the Mask Register
- * @param[in] *EnChipSels - Chip Selects to Enable
- * @param[in] *LoBit - Lowest Bit
- * @param[in] *HiBit - Highest Bit
- *
- *
- */
-
-VOID
-STATIC
-CsIntSwap (
- IN OUT UINT32 *BaseMaskRegPtr,
- IN UINT8 EnChipSels,
- IN UINT8 LoBit,
- IN UINT8 HiBit
- )
-{
- UINT8 BitDelta;
- UINT32 TempHi;
- UINT32 TempLo;
- UINT32 AddrLoMask;
- UINT32 AddrHiMask;
-
- ASSERT (BaseMaskRegPtr != NULL);
- ASSERT (HiBit > LoBit);
-
- BitDelta = HiBit - LoBit;
- AddrLoMask = (((UINT32)EnChipSels) - 1) << LoBit;
- AddrHiMask = AddrLoMask << BitDelta;
-
- TempHi = TempLo = *BaseMaskRegPtr;
- TempLo &= AddrLoMask;
- TempLo <<= BitDelta; // move lower bits to upper bit position
- TempHi &= AddrHiMask;
- TempHi >>= BitDelta; // move upper bits to lower bit position
-
- *BaseMaskRegPtr &= ~AddrLoMask;
- *BaseMaskRegPtr &= ~AddrHiMask;
- *BaseMaskRegPtr |= TempLo | TempHi;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Feat/CSINTLV/mfcsi.h b/src/vendorcode/amd/agesa/Proc/Mem/Feat/CSINTLV/mfcsi.h
deleted file mode 100644
index 1e11f94..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Feat/CSINTLV/mfcsi.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mfcsi.h
- *
- * Memory Controller
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-#ifndef _MFCSI_H_
-#define _MFCSI_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-MemFInterleaveBanks (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-#endif /* _MFCSI_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Feat/DMI/mfDMI.c b/src/vendorcode/amd/agesa/Proc/Mem/Feat/DMI/mfDMI.c
deleted file mode 100644
index b4d1719..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Feat/DMI/mfDMI.c
+++ /dev/null
@@ -1,573 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mfDMI.c
- *
- * Memory DMI table support.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Main)
- * @e \$Revision: 39742 $ @e \$Date: 2010-10-15 02:11:58 +0800 (Fri, 15 Oct 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "heapManager.h"
-#include "cpuServices.h"
-#include "mm.h"
-#include "mn.h"
-#include "mu.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_FEAT_DMI_MFDMI_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-#define MAX_DCTS_PER_DIE 2
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function gets DDR3 DMI information from SPD buffer and stores the info into heap
- *
- * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK
- *
- */
-BOOLEAN
-MemFDMISupport3 (
- IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
- )
-{
- UINT8 i;
- UINT8 Dimm;
- UINT8 Socket;
- UINT8 NodeId;
- UINT8 Dct;
- UINT8 Channel;
- UINT8 temp;
- UINT8 MaxDimms;
- UINT8 DimmIndex;
- UINT8 MaxChannelsPerSocket;
- UINT8 MaxDimmsPerChannel;
- UINT8 FormFactor;
- UINT16 TotalWidth;
- UINT16 Speed;
- UINT16 Capacity;
- UINT16 Width;
- UINT16 Rank;
- UINT16 BusWidth;
- UINT64 ManufacturerIdCode;
- UINT32 MaxSockets;
- UINT32 Address;
-
- MEM_NB_BLOCK *NBPtr;
- MEM_DATA_STRUCT *MemPtr;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
- MEM_DMI_INFO *DmiTable;
- MEM_PARAMETER_STRUCT *RefPtr;
-
- DIE_STRUCT *MCTPtr;
- CH_DEF_STRUCT *ChannelPtr;
- SPD_DEF_STRUCT *SpdDataStructure;
-
- NBPtr = MemMainPtr->NBPtr;
- MemPtr = MemMainPtr->MemPtr;
- SpdDataStructure = MemPtr->SpdDataStructure;
- MCTPtr = NBPtr->MCTPtr;
- RefPtr = MemPtr->ParameterListPtr;
-
- // Initialize local variables
- MaxDimms = 0;
-
- AGESA_TESTPOINT (TpProcMemDmi, &MemPtr->StdHeader);
-
- ASSERT (NBPtr != NULL);
-
- MaxSockets = (UINT8) (0x000000FF & GetPlatformNumberOfSockets ());
- for (Socket = 0; Socket < MaxSockets; Socket++) {
- for (Channel = 0; Channel < GetMaxChannelsPerSocket (RefPtr->PlatformMemoryConfiguration, Socket, &MemPtr->StdHeader); Channel++) {
- temp = GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, Socket, Channel);
- MaxDimms = MaxDimms + temp;
- }
- }
-
- // Allocate heap for memory DMI table 16, 17, 19, 20
- AllocHeapParams.RequestedBufferSize = MaxDimms * sizeof (MEM_DMI_INFO) + 2 + sizeof (DMI_T17_MEMORY_TYPE);
-
- AllocHeapParams.BufferHandle = AMD_DMI_MEM_DEV_INFO_HANDLE;
- AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
- if (AGESA_SUCCESS != HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader)) {
- PutEventLog (AGESA_CRITICAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader);
- SetMemError (AGESA_CRITICAL, MCTPtr);
- ASSERT(FALSE); // Could not allocate heap for memory DMI table 16,17,19 and 20 for DDR3
- return FALSE;
- }
-
- DmiTable = (MEM_DMI_INFO *) ((UINT8 *) (AllocHeapParams.BufferPtr) + 2 + sizeof (DMI_T17_MEMORY_TYPE));
- *((UINT16 *) (AllocHeapParams.BufferPtr)) = MaxDimms; // Number of memory devices
- *((DMI_T17_MEMORY_TYPE *) ((UINT8 *) (AllocHeapParams.BufferPtr) + 2)) = Ddr3MemType; // Memory type
-
- //
- // DMI TYPE 17
- //
- DimmIndex = 0;
- for (Socket = 0; Socket < MaxSockets; Socket++) {
- MaxChannelsPerSocket = GetMaxChannelsPerSocket (RefPtr->PlatformMemoryConfiguration, Socket, &MemPtr->StdHeader);
- for (Channel = 0; Channel < MaxChannelsPerSocket; Channel++) {
- //
- // Get Node number and Dct number for this channel
- //
- ChannelPtr = MemPtr->SocketList[Socket].ChannelPtr[Channel];
- NodeId = ChannelPtr->MCTPtr->NodeId;
- Dct = ChannelPtr->Dct;
- NBPtr[NodeId].SwitchDCT (&NBPtr[NodeId], Dct);
- MaxDimmsPerChannel = GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, Socket, Channel);
- for (Dimm = 0; Dimm < MaxDimmsPerChannel; Dimm++, DimmIndex++) {
- DmiTable[DimmIndex].TotalWidth = 0xFFFF;
- DmiTable[DimmIndex].DataWidth = 0xFFFF;
- DmiTable[DimmIndex].MemorySize = 0xFFFF;
- DmiTable[DimmIndex].Speed = 0;
- DmiTable[DimmIndex].ManufacturerIdCode = 0;
- DmiTable[DimmIndex].Attributes = 0;
- DmiTable[DimmIndex].StartingAddr = 0xFFFFFFFF;
- DmiTable[DimmIndex].EndingAddr = 0xFFFFFFFF;
- DmiTable[DimmIndex].DimmPresent = 0;
- DmiTable[DimmIndex].Socket = Socket;
- DmiTable[DimmIndex].Channel = Channel;
- DmiTable[DimmIndex].Dimm = Dimm;
- DmiTable[DimmIndex].ConfigSpeed = 0;
-
- for (i = 0; i < 4; i++) {
- DmiTable[DimmIndex].SerialNumber[i] = 0xFF;
- }
-
- for (i = 0; i < 18; i++) {
- DmiTable[DimmIndex].PartNumber[i] = 0xFF;
- }
-
- if (SpdDataStructure[DimmIndex].DimmPresent) {
- // Total Width (offset 08h) & Data Width (offset 0Ah)
- TotalWidth = (UINT16) SpdDataStructure[DimmIndex].Data[8];
- if ((TotalWidth & 0x18) == 0) {
- // non ECC
- if ((TotalWidth & 0x07) == 0) {
- DmiTable[DimmIndex].TotalWidth = 8; // 8 bits
- } else if ((TotalWidth & 0x07) == 1) {
- DmiTable[DimmIndex].TotalWidth = 16; // 16 bits
- } else if ((TotalWidth & 0x07) == 2) {
- DmiTable[DimmIndex].TotalWidth = 32; // 32 bits
- } else if ((TotalWidth & 0x07) == 3) {
- DmiTable[DimmIndex].TotalWidth = 64; // 64 bits
- }
- DmiTable[DimmIndex].DataWidth = DmiTable[DimmIndex].TotalWidth ;
- } else {
- // ECC
- if ((TotalWidth & 0x07) == 0) {
- DmiTable[DimmIndex].TotalWidth = 8 + 8; // 8 bits
- } else if ((TotalWidth & 0x07) == 1) {
- DmiTable[DimmIndex].TotalWidth = 16 + 8; // 16 bits
- } else if ((TotalWidth & 0x07) == 2) {
- DmiTable[DimmIndex].TotalWidth = 32 + 8; // 32 bits
- } else if ((TotalWidth & 0x07) == 3) {
- DmiTable[DimmIndex].TotalWidth = 64 + 8; // 64 bits
- }
- DmiTable[DimmIndex].DataWidth = DmiTable[DimmIndex].TotalWidth - 8;
- }
-
- // Memory Size (offset 0Ch)
- Capacity = 0;
- BusWidth = 0;
- Width = 0;
- Rank = 0;
- temp = (UINT8) SpdDataStructure[DimmIndex].Data[4];
- if ((temp & 0x0F) == 0) {
- Capacity = 0x0100; // 256M
- } else if ((temp & 0x0F) == 1) {
- Capacity = 0x0200; // 512M
- } else if ((temp & 0x0F) == 2) {
- Capacity = 0x0400; // 1G
- } else if ((temp & 0x0F) == 3) {
- Capacity = 0x0800; // 2G
- } else if ((temp & 0x0F) == 4) {
- Capacity = 0x1000; // 4G
- } else if ((temp & 0x0F) == 5) {
- Capacity = 0x2000; // 8G
- } else if ((temp & 0x0F) == 6) {
- Capacity = 0x4000; // 16G
- }
-
- temp = (UINT8) SpdDataStructure[DimmIndex].Data[8];
- if ((temp & 0x07) == 0) {
- BusWidth = 8; // 8 bits
- } else if ((temp & 0x07) == 1) {
- BusWidth = 16; // 16 bits
- } else if ((temp & 0x07) == 2) {
- BusWidth = 32; // 32 bits
- } else if ((temp & 0x07) == 3) {
- BusWidth = 64; // 64 bits
- }
-
- temp = (UINT8) SpdDataStructure[DimmIndex].Data[7];
- if ((temp & 0x07) == 0) {
- Width = 4; // 4 bits
- } else if ((temp & 0x07) == 1) {
- Width = 8; // 8 bits
- } else if ((temp & 0x07) == 2) {
- Width = 16; // 16 bits
- } else if ((temp & 0x07) == 3) {
- Width = 32; // 32 bits
- }
-
- temp = (UINT8) SpdDataStructure[DimmIndex].Data[7];
- if (((temp >> 3) & 0x07) == 0) {
- Rank = 1; // 4 bits
- DmiTable[DimmIndex].Attributes = 1; // Single Rank Dimm
- } else if (((temp >> 3) & 0x07) == 1) {
- Rank = 2; // 8 bits
- DmiTable[DimmIndex].Attributes = 2; // Dual Rank Dimm
- } else if (((temp >> 3) & 0x07) == 2) {
- Rank = 3; // 16 bits
- } else if (((temp >> 3) & 0x07) == 3) {
- Rank = 4; // 32 bits
- DmiTable[DimmIndex].Attributes = 4; // Quad Rank Dimm
- }
-
- DmiTable[DimmIndex].MemorySize = (UINT16) (Capacity / 8 * BusWidth / Width * Rank);
-
- // Form Factor (offset 0Eh)
- FormFactor = (UINT8) SpdDataStructure[DimmIndex].Data[3];
- if ((FormFactor & 0x01) == 0 || (FormFactor & 0x02) == 0) {
- DmiTable[DimmIndex].FormFactor = 0x09; // RDIMM or UDIMM
- } else if ((FormFactor & 0x03) == 0) {
- DmiTable[DimmIndex].FormFactor = 0x0D; // SO-DIMM
- }
-
- // DIMM Present
- DmiTable[DimmIndex].DimmPresent = 1;
-
- // Speed (offset 15h)
- Speed = (UINT16) SpdDataStructure[DimmIndex].Data[12];
- if (Speed == 20) {
- DmiTable[DimmIndex].Speed = 800; // DDR3-800
- } else if (Speed == 15) {
- DmiTable[DimmIndex].Speed = 1066; // DDR3-1066
- } else if (Speed == 12) {
- DmiTable[DimmIndex].Speed = 1333; // DDR3-1333
- } else if (Speed == 10) {
- DmiTable[DimmIndex].Speed = 1600; // DDR3-1600
- }
-
- // Manufacturer (offset 17h)
- ManufacturerIdCode = (UINT64) SpdDataStructure[DimmIndex].Data[118];
- DmiTable[DimmIndex].ManufacturerIdCode = (ManufacturerIdCode << 8) | ((UINT64) SpdDataStructure[DimmIndex].Data[117]);
-
- // Serial Number (offset 18h)
- for (i = 0; i < 4; i++) {
- DmiTable[DimmIndex].SerialNumber[i] = (UINT8) SpdDataStructure[DimmIndex].Data[i + 122];
- }
- // Part Number (offset 1Ah)
- for (i = 0; i < 18; i++) {
- DmiTable[DimmIndex].PartNumber[i] = (UINT8) SpdDataStructure[DimmIndex].Data[i + 128];
- }
- // Extended Size (offset 1Ch) - @todo: pending for SPD SPEC update
- DmiTable[DimmIndex].ExtSize = 0;
-
- // Configured Memory Clock Speed (offset 20h)
- DmiTable[DimmIndex].ConfigSpeed = NBPtr[NodeId].DCTPtr->Timings.Speed;
-
- // AGESA does NOT support this feature when bank interleaving is enabled.
- if (!RefPtr->EnableBankIntlv) {
- if ((NBPtr[NodeId].GetBitField (&NBPtr[NodeId], BFCSBaseAddr0Reg + 2 * Dimm) & 1) != 0) {
- Address = (NBPtr[NodeId].GetBitField (&NBPtr[NodeId], BFCSBaseAddr0Reg + 2 * Dimm)) & 0x1FF83FE0;
- Address = Address >> 2;
- DmiTable[DimmIndex].StartingAddr = Address;
- DmiTable[DimmIndex].EndingAddr = Address + (UINT32) (DmiTable[DimmIndex].MemorySize * 0x0400);
- }
- }
- } // Dimm present
- } // Dimm loop
- } // Channel loop
- } // Socket loop
-
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function gets DDR2 DMI information from SPD buffer and stores the info into heap
- *
- * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK
- *
- */
-BOOLEAN
-MemFDMISupport2 (
- IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
- )
-{
- UINT8 i;
- UINT8 Dimm;
- UINT8 Socket;
- UINT8 NodeId;
- UINT8 Dct;
- UINT8 Channel;
- UINT8 temp;
- UINT8 MaxDimms;
- UINT8 DimmIndex;
- UINT8 MaxChannelsPerSocket;
- UINT8 MaxDimmsPerChannel;
- UINT8 FormFactor;
- UINT8 Temp;
- UINT8 Rank;
- UINT16 TotalWidth;
- UINT32 Speed;
- UINT32 MaxSockets;
- UINT32 Address;
-
- MEM_NB_BLOCK *NBPtr;
- MEM_DATA_STRUCT *MemPtr;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
- MEM_DMI_INFO *DmiTable;
- DIE_STRUCT *MCTPtr;
- CH_DEF_STRUCT *ChannelPtr;
- SPD_DEF_STRUCT *SpdDataStructure;
- MEM_PARAMETER_STRUCT *RefPtr;
-
- NBPtr = MemMainPtr->NBPtr;
- MemPtr = MemMainPtr->MemPtr;
- SpdDataStructure = MemPtr->SpdDataStructure;
- MCTPtr = NBPtr->MCTPtr;
- RefPtr = MemPtr->ParameterListPtr;
-
- // Initialize local variables
- MaxDimms = 0;
-
- ASSERT (NBPtr != NULL);
-
- MaxSockets = (UINT8) (0x000000FF & GetPlatformNumberOfSockets ());
- for (Socket = 0; Socket < MaxSockets; Socket++) {
- for (Channel = 0; Channel < GetMaxChannelsPerSocket (RefPtr->PlatformMemoryConfiguration, Socket, &MemPtr->StdHeader); Channel++) {
- temp = GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, Socket, Channel);
- MaxDimms = MaxDimms + temp;
- }
- }
-
- // Allocate heap for memory DMI table 16, 17, 19, 20
- AllocHeapParams.RequestedBufferSize = MaxDimms * sizeof (MEM_DMI_INFO) + 3;
-
- AllocHeapParams.BufferHandle = AMD_DMI_MEM_DEV_INFO_HANDLE;
- AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
- if (AGESA_SUCCESS != HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader)) {
- PutEventLog (AGESA_CRITICAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader);
- SetMemError (AGESA_CRITICAL, MCTPtr);
- ASSERT(FALSE); // Could not allocate heap for memory DMI table 16,17,19 and 20 for DDR2
- return FALSE;
- }
-
- DmiTable = (MEM_DMI_INFO *) ((UINT8 *) (AllocHeapParams.BufferPtr) + 2 + sizeof (DMI_T17_MEMORY_TYPE));
- *((UINT16 *) (AllocHeapParams.BufferPtr)) = MaxDimms; // Number of memory devices
- *((DMI_T17_MEMORY_TYPE *) ((UINT8 *) (AllocHeapParams.BufferPtr) + 2)) = Ddr2MemType; // Memory type
-
- //
- // DMI TYPE 17
- //
- DimmIndex = 0;
- for (Socket = 0; Socket < MaxSockets; Socket++) {
- MaxChannelsPerSocket = GetMaxChannelsPerSocket (RefPtr->PlatformMemoryConfiguration, Socket, &MemPtr->StdHeader);
- for (Channel = 0; Channel < MaxChannelsPerSocket; Channel++) {
- //
- // Get Node number and Dct number for this channel
- //
- ChannelPtr = MemPtr->SocketList[Socket].ChannelPtr[Channel];
- NodeId = ChannelPtr->MCTPtr->NodeId;
- Dct = ChannelPtr->Dct;
- NBPtr[NodeId].SwitchDCT (&NBPtr[NodeId], Dct);
- NBPtr[NodeId].SwitchDCT (&NBPtr[NodeId], Dct);
- MaxDimmsPerChannel = GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, Socket, Channel);
- for (Dimm = 0; Dimm < MaxDimmsPerChannel; Dimm++, DimmIndex++) {
- DmiTable[DimmIndex].TotalWidth = 0xFFFF;
- DmiTable[DimmIndex].DataWidth = 0xFFFF;
- DmiTable[DimmIndex].MemorySize = 0xFFFF;
- DmiTable[DimmIndex].Speed = 0;
- DmiTable[DimmIndex].ManufacturerIdCode = 0;
- DmiTable[DimmIndex].Attributes = 0;
- DmiTable[DimmIndex].StartingAddr = 0xFFFFFFFF;
- DmiTable[DimmIndex].EndingAddr = 0xFFFFFFFF;
- DmiTable[DimmIndex].DimmPresent = 0;
- DmiTable[DimmIndex].ConfigSpeed = 0;
-
- for (i = 0; i < 4; i++) {
- DmiTable[DimmIndex].SerialNumber[i] = 0xFF;
- }
-
- for (i = 0; i < 18; i++) {
- DmiTable[DimmIndex].PartNumber[i] = 0xFF;
- }
-
- if (SpdDataStructure[DimmIndex].DimmPresent) {
- // Total Width (offset 08h) & Data Width (offset 0Ah)
- TotalWidth = (UINT16) SpdDataStructure[DimmIndex].Data[13];
- if ((TotalWidth & 0x04) != 0) {
- DmiTable[DimmIndex].TotalWidth = 4; // 4 bits
- } else if ((TotalWidth & 0x08) != 0) {
- DmiTable[DimmIndex].TotalWidth = 8; // 8 bits
- } else if ((TotalWidth & 0x10) != 0) {
- DmiTable[DimmIndex].TotalWidth = 16; // 16 bits
- } else if ((TotalWidth & 0x20) != 0) {
- DmiTable[DimmIndex].TotalWidth = 32; // 32 bits
- }
- DmiTable[DimmIndex].DataWidth = DmiTable[DimmIndex].TotalWidth;
-
- // Memory Size (offset 0Ch), Attributes (offset 1Bh)
- Rank = (UINT8) SpdDataStructure[DimmIndex].Data[5] & 0x07;
- if (Rank == 0) {
- DmiTable[DimmIndex].Attributes = 1; // Single Rank Dimm
- } else if (Rank == 1) {
- DmiTable[DimmIndex].Attributes = 2; // Dual Rank Dimm
- } else if (Rank == 3) {
- DmiTable[DimmIndex].Attributes = 4; // Quad Rank Dimm
- }
-
- Temp = (UINT8) SpdDataStructure[DimmIndex].Data[31];
- for (i = 0; i < 8; i++) {
- if ((Temp & 0x01) == 1) {
- DmiTable[DimmIndex].MemorySize = 0x80 * (i + 1) * (Rank + 1);
- }
- Temp = Temp >> 1;
- }
-
- // Form Factor (offset 0Eh)
- FormFactor = (UINT8) SpdDataStructure[DimmIndex].Data[20];
- if ((FormFactor & 0x20) == 4) {
- DmiTable[DimmIndex].FormFactor = 0x0D; // SO-DIMM
- } else {
- DmiTable[DimmIndex].FormFactor = 0x09; // RDIMM or UDIMM
- }
-
- // DIMM Present
- DmiTable[DimmIndex].DimmPresent = 1;
-
- // DIMM Index
- DmiTable[DimmIndex].Socket = Socket;
- DmiTable[DimmIndex].Channel = Channel;
- DmiTable[DimmIndex].Dimm = Dimm;
-
- // Speed (offset 15h)
- Speed = NBPtr[NodeId].GetBitField (&NBPtr[NodeId], BFDramConfigHiReg);
- Speed = Speed & 0x00000007;
- if (Speed == 0) {
- DmiTable[DimmIndex].Speed = 400; // 400MHz
- } else if (Speed == 1) {
- DmiTable[DimmIndex].Speed = 533; // 533MHz
- } else if (Speed == 2) {
- DmiTable[DimmIndex].Speed = 667; // 667MHz
- } else if (Speed == 3) {
- DmiTable[DimmIndex].Speed = 800; // 800MHz
- }
-
- // Manufacturer (offset 17h)
- DmiTable[DimmIndex].ManufacturerIdCode = (UINT64) SpdDataStructure[DimmIndex].Data[64];
-
- // Serial Number (offset 18h)
- for (i = 0; i < 4; i++) {
- DmiTable[DimmIndex].SerialNumber[i] = (UINT8) SpdDataStructure[DimmIndex].Data[i + 95];
- }
-
- // Part Number (offset 1Ah)
- for (i = 0; i < 18; i++) {
- DmiTable[DimmIndex].PartNumber[i] = (UINT8) SpdDataStructure[DimmIndex].Data[i + 73];
- }
-
- // Configured Memory Clock Speed (offset 20h)
- DmiTable[DimmIndex].ConfigSpeed = NBPtr[NodeId].DCTPtr->Timings.Speed;
-
- // AGESA does NOT support this feature when bank interleaving is enabled.
- if (!RefPtr->EnableBankIntlv) {
- if ((NBPtr[NodeId].GetBitField (&NBPtr[NodeId], BFCSBaseAddr0Reg + 2 * Dimm) & 1) != 0) {
- Address = (NBPtr[NodeId].GetBitField (&NBPtr[NodeId], BFCSBaseAddr0Reg + 2 * Dimm)) & 0x1FF83FE0;
- Address = Address >> 2;
- DmiTable[DimmIndex].StartingAddr = Address;
- DmiTable[DimmIndex].EndingAddr = Address + (UINT32) (DmiTable[DimmIndex].MemorySize * 0x0400);
- }
- }
-
- } // DIMM Present
- } // DIMM loop
- }
- }
-
- return TRUE;
-}
-
-/*---------------------------------------------------------------------------------------
- * L O C A L F U N C T I O N S
- *---------------------------------------------------------------------------------------
- */
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Feat/ECC/mfecc.c b/src/vendorcode/amd/agesa/Proc/Mem/Feat/ECC/mfecc.c
deleted file mode 100644
index 4ea95e9..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Feat/ECC/mfecc.c
+++ /dev/null
@@ -1,321 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mfecc.c
- *
- * Feature ECC initialization functions
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Feat/ECC)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "mfecc.h"
-#include "Filecode.h"
-#include "mfmemclr.h"
-#include "GeneralServices.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_FEAT_ECC_MFECC_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-UINT32
-STATIC
-MemFGetScrubAddr (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-STATIC
-InitECCOverriedeStruct (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT ECC_OVERRIDE_STRUCT *pecc_override_struct
- );
-
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function checks to see if ECC can be enabled on all nodes
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - This feature is enabled.
- * @return FALSE - This feature is not enabled.
- */
-
-BOOLEAN
-MemFCheckECC (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- DIE_STRUCT *MCTPtr;
- MEM_SHARED_DATA *SharedPtr;
-
- ASSERT (NBPtr != NULL);
-
- MCTPtr = NBPtr->MCTPtr;
- SharedPtr = NBPtr->SharedPtr;
-
- if (MCTPtr->NodeMemSize != 0) {
- if (SharedPtr->AllECC && MCTPtr->Status[SbEccDimms] && (MCTPtr->ErrCode < AGESA_ERROR)) {
- // Clear all MCA reports before using scrubber
- // to initialize ECC check bits
- //
- NBPtr->McaNbCtlReg = NBPtr->GetBitField (NBPtr, BFMcaNbCtlReg);
- NBPtr->SetBitField (NBPtr, BFMcaNbCtlReg, 0);
- NBPtr->SetBitField (NBPtr, BFSyncOnUcEccEn, 0);
- // In unganged mode, set DctDctIntlv
- if (!NBPtr->Ganged) {
- NBPtr->SetBitField (NBPtr, BFDctDatIntLv, 1);
- }
- //
- // Set Ecc Symbol Size
- //
- NBPtr->SetEccSymbolSize (NBPtr);
- // If ECC can be enabled on this node,
- // set the master ECCen bit (according to setup)
- //
- NBPtr->SetBitField (NBPtr, BFDramEccEn, 1);
- // Do mem clear on current node
- MemFMctMemClr_Init (NBPtr);
- return TRUE;
- } else {
- if (SharedPtr->AllECC) {
- SharedPtr->AllECC = FALSE;
- }
- // ECC requested but cannot be enabled
- MCTPtr->Status[SbEccDimms] = FALSE;
- MCTPtr->ErrStatus[EsbDramECCDis] = TRUE;
- PutEventLog (AGESA_ERROR, MEM_ERROR_ECC_DIS, NBPtr->Node, 0, 0, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_ERROR, MCTPtr);
- }
- }
- return FALSE;
-}
-
- /* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the ECC on all nodes
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - This feature is enabled.
- * @return FALSE - This feature is not enabled.
- */
-
-BOOLEAN
-MemFInitECC (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 Node;
- UINT32 ScrubAddrRJ16;
- DIE_STRUCT *MCTPtr;
- MEM_SHARED_DATA *SharedPtr;
- ECC_OVERRIDE_STRUCT ecc_override_struct;
- BOOLEAN Flag;
-
- InitECCOverriedeStruct (NBPtr, &ecc_override_struct);
- IDS_OPTION_HOOK (IDS_ECC, &ecc_override_struct, &(NBPtr->MemPtr->StdHeader));
-
- ASSERT (NBPtr != NULL);
-
- MCTPtr = NBPtr->MCTPtr;
- Node = MCTPtr->NodeId;
- SharedPtr = NBPtr->SharedPtr;
- Flag = TRUE;
-
- NBPtr->FamilySpecificHook[ScrubberErratum] (NBPtr, (VOID *) &Flag);
-
- if ((MCTPtr->Status[SbEccDimms]) && (SharedPtr->AllECC)) {
- // Check if the input dram scrub rate is supported or not
- ASSERT (ecc_override_struct.CfgScrubDramRate <= 0x16);
- if (ecc_override_struct.CfgScrubDramRate != 0) {
- // Program scrub address,
- // let the scrub Addr be the Base of this Node
- // Only enable Dram scrubber when there is memory on current node
- //
- NBPtr->SetBitField (NBPtr, BFScrubReDirEn, 0);
- ScrubAddrRJ16 = (NBPtr->GetBitField (NBPtr, BFDramBaseReg0 + Node) & 0xFFFF0000) >> 8;
- ScrubAddrRJ16 |= NBPtr->GetBitField (NBPtr, BFDramBaseHiReg0 + Node) << 24;
- NBPtr->SetBitField (NBPtr, BFScrubAddrLoReg, ScrubAddrRJ16 << 16);
- NBPtr->SetBitField (NBPtr, BFScrubAddrHiReg, ScrubAddrRJ16 >> 16);
- NBPtr->SetBitField (NBPtr, BFDramScrub, ecc_override_struct.CfgScrubDramRate);
- }
- }
- // Scrub CTL for Dcache, L2, L3
- // Check if the input L2 scrub rate is supported or not
- ASSERT (ecc_override_struct.CfgScrubL2Rate <= 0x16);
- NBPtr->SetBitField (NBPtr, BFL2Scrub, ecc_override_struct.CfgScrubL2Rate);
- // Check if the input Dcache scrub rate is supported or not
- ASSERT (ecc_override_struct.CfgScrubDcRate <= 0x16);
- NBPtr->SetBitField (NBPtr, BFDcacheScrub, ecc_override_struct.CfgScrubDcRate);
- // Do not enable L3 Scrub if F3xE8[L3Capable] is 0 or F3x188[DisableL3] is 1
- if ((NBPtr->GetBitField (NBPtr, BFL3Capable) == 1) && (NBPtr->GetBitField (NBPtr, BFDisableL3) == 0)) {
- // Check if input L3 scrub rate is supported or not
- ASSERT (ecc_override_struct.CfgScrubL3Rate <= 0x16);
- NBPtr->SetBitField (NBPtr, BFL3Scrub, ecc_override_struct.CfgScrubL3Rate);
- }
-
- // Check if Dcache scrubber or L2 scrubber is enabled
- if ((ecc_override_struct.CfgScrubL2Rate != 0) || (ecc_override_struct.CfgScrubDcRate!= 0)) {
- // If ClkDivisor is deeper than divide-by-16
- if (NBPtr->GetBitField (NBPtr, BFC1ClkDivisor) > 4) {
- // Set it to divide-by-16
- NBPtr->SetBitField (NBPtr, BFC1ClkDivisor, 4);
- }
- }
-
- NBPtr->SetBitField (NBPtr, BFScrubReDirEn, ecc_override_struct.CfgEccRedirection);
- NBPtr->SetBitField (NBPtr, BFSyncOnUcEccEn, ecc_override_struct.CfgEccSyncFlood);
- // Restore MCA reports after scrubber is done
- // with initializing ECC check bits
- NBPtr->SetBitField (NBPtr, BFMcaNbCtlReg, NBPtr->McaNbCtlReg);
-
- Flag = FALSE;
- NBPtr->FamilySpecificHook[ScrubberErratum] (NBPtr, (VOID *) &Flag);
-
- return TRUE;
-}
-
-VOID
-STATIC
-InitECCOverriedeStruct (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT ECC_OVERRIDE_STRUCT *pecc_override_struct
- )
-{
- pecc_override_struct->CfgEccRedirection = UserOptions.CfgEccRedirection;
- pecc_override_struct->CfgEccSyncFlood = UserOptions.CfgEccSyncFlood;
- pecc_override_struct->CfgScrubDcRate = UserOptions.CfgScrubDcRate;
-
- if (UserOptions.CfgScrubDramRate != 0xFF) {
- pecc_override_struct->CfgScrubDramRate = UserOptions.CfgScrubDramRate;
- } else {
- if (NBPtr->MCTPtr->NodeMemSize <= 0x4000) {
- pecc_override_struct->CfgScrubDramRate = 0x12; // 1 ~ 1 GB
- } else if (NBPtr->MCTPtr->NodeMemSize <= 0x8000) {
- pecc_override_struct->CfgScrubDramRate = 0x11; // 1 GB + 1 ~ 2 GB
- } else if (NBPtr->MCTPtr->NodeMemSize <= 0x10000) {
- pecc_override_struct->CfgScrubDramRate = 0x10; // 2 GB + 1 ~ 4 GB
- } else if (NBPtr->MCTPtr->NodeMemSize <= 0x20000) {
- pecc_override_struct->CfgScrubDramRate = 0x0F; // 4 GB + 1 ~ 8 GB
- } else if (NBPtr->MCTPtr->NodeMemSize <= 0x40000) {
- pecc_override_struct->CfgScrubDramRate = 0x0E; // 8 GB + 1 ~ 16 GB
- } else {
- pecc_override_struct->CfgScrubDramRate = 0x0D; //16 GB + 1 above
- }
- }
-
- pecc_override_struct->CfgScrubL2Rate = UserOptions.CfgScrubL2Rate;
- pecc_override_struct->CfgScrubL3Rate = UserOptions.CfgScrubL3Rate;
-}
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function gets the current 40-bit Scrub ADDR address, scaled to 32-bits,
- * of the specified Node.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return Scrubber Address
- */
-
-UINT32
-STATIC
-MemFGetScrubAddr (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT32 ScrubAddrHi;
- UINT32 ScrubAddrLo;
- UINT32 ScrubAddrRJ16;
-
- ASSERT (NBPtr != NULL);
-
- ScrubAddrHi = NBPtr->GetBitField (NBPtr, BFScrubAddrHiReg);
- ScrubAddrLo = NBPtr->GetBitField (NBPtr, BFScrubAddrLoReg);
- // Scrub Addr High again, detect 32-bit wrap
- ScrubAddrRJ16 = NBPtr->GetBitField (NBPtr, BFScrubAddrHiReg);
- if (ScrubAddrRJ16 != ScrubAddrHi) {
- ScrubAddrHi = ScrubAddrRJ16;
- ScrubAddrLo = NBPtr->GetBitField (NBPtr, BFScrubAddrLoReg);
- }
- return ((ScrubAddrHi << 16) | (ScrubAddrLo >> 16));
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Feat/ECC/mfecc.h b/src/vendorcode/amd/agesa/Proc/Mem/Feat/ECC/mfecc.h
deleted file mode 100644
index 16e5f7d..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Feat/ECC/mfecc.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mfecc.h
- *
- * Feature ECC initialization functions
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-#ifndef _MFECC_H_
-#define _MFECC_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-MemFInitECC (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-#endif /* _MFECC_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Feat/ECC/mfemp.c b/src/vendorcode/amd/agesa/Proc/Mem/Feat/ECC/mfemp.c
deleted file mode 100644
index cdf3568..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Feat/ECC/mfemp.c
+++ /dev/null
@@ -1,174 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mfemp.c
- *
- * Feature EMP initialization functions
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Feat/ECC)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-
-
-#include "AGESA.h"
-#include "mm.h"
-#include "mn.h"
-#include "Ids.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_FEAT_ECC_MFEMP_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-IsPowerOfTwo (
- IN UINT32 TestNumber
- );
-
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes EMP (Enhanced Memory Protection)
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - This feature is enabled.
- * @return FALSE - This feature is not enabled.
- */
-
-BOOLEAN
-MemFInitEMP (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MEM_PARAMETER_STRUCT *RefPtr;
- DIE_STRUCT *MCTPtr;
-
- ASSERT (NBPtr != NULL);
-
- RefPtr = NBPtr->RefPtr;
- MCTPtr = NBPtr->MCTPtr;
- if (RefPtr->EnableEccFeature) {
- if (NBPtr->GetBitField (NBPtr, BFEnhMemProtCap) == 0) {
- PutEventLog (AGESA_WARNING, MEM_WARNING_EMP_NOT_SUPPORTED, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader);
- MCTPtr->ErrStatus[EsbEMPNotSupported] = TRUE;
- } else if (RefPtr->EnableChannelIntlv || RefPtr->EnableBankIntlv || RefPtr->EnableBankSwizzle) {
- PutEventLog (AGESA_WARNING, MEM_WARNING_EMP_CONFLICT, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader);
- MCTPtr->ErrStatus[EsbEMPConflict] = TRUE;
- } else if ((!MCTPtr->GangedMode) &&
- (!IsPowerOfTwo (MCTPtr->DctData[0].Timings.DctMemSize) &&
- !IsPowerOfTwo (MCTPtr->DctData[1].Timings.DctMemSize))) {
- PutEventLog (AGESA_WARNING, MEM_WARNING_EMP_NOT_ENABLED, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader);
- MCTPtr->ErrStatus[EsbEMPDis] = TRUE;
- } else {
- // Reduce memory size to 7/8 of the original memory size
- ASSERT ((MCTPtr->NodeMemSize % 8) == 0);
- NBPtr->SetBitField (NBPtr, BFDramHoleValid, 0);
- MCTPtr->NodeMemSize = (MCTPtr->NodeMemSize / 8) * 7;
- NBPtr->HtMemMapInit (NBPtr);
- NBPtr->CpuMemTyping (NBPtr);
-
- // Enable EMP
- NBPtr->SetBitField (NBPtr, BFDramEccEn, 1);
-
- // Scrub CTL settings for Dcache, L2
- NBPtr->SetBitField (NBPtr, BFL2Scrub, UserOptions.CfgScrubL2Rate);
- NBPtr->SetBitField (NBPtr, BFDcacheScrub, UserOptions.CfgScrubDcRate);
-
- NBPtr->SetBitField (NBPtr, BFSyncOnUcEccEn, UserOptions.CfgEccSyncFlood);
- return TRUE;
- }
- }
- return FALSE;
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function checks to see if the input is power of two.
- *
- * @param[in] TestNumber - Value to check for power of two
- *
- * @return TRUE - is power of two
- * FALSE - is not power of two
- */
-BOOLEAN
-STATIC
-IsPowerOfTwo (
- IN UINT32 TestNumber
- )
-{
- return (BOOLEAN) ((TestNumber & (TestNumber - 1)) == 0);
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c b/src/vendorcode/amd/agesa/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
deleted file mode 100644
index c6e85ec..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
+++ /dev/null
@@ -1,195 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mfdimmexclud.c
- *
- * Feature DIMM exclude.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Feat/EXCLUDIMM)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-#include "AGESA.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "Ids.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_FEAT_EXCLUDIMM_MFDIMMEXCLUD_FILECODE
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Check and disable Chip selects that fail training for each node.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - This feature is enabled.
- * @return FALSE - This feature is not enabled.
- */
-BOOLEAN
-MemFRASExcludeDIMM (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 Dct;
- UINT8 ReserveDCT;
- UINT8 q;
- BOOLEAN Flag;
- BOOLEAN IsCSIntlvEnabled;
- UINT16 CsTestFail;
- DIE_STRUCT *MCTPtr;
- BOOLEAN RetVal;
-
- ASSERT (NBPtr != NULL);
- ReserveDCT = NBPtr->Dct;
- CsTestFail = 0;
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- if (NBPtr->DCTPtr->Timings.CsTestFail != 0) {
- // When there is no new failed dimm that needs to be excluded, then no need to go through the process.
- switch (NBPtr->SharedPtr->DimmExcludeFlag) {
- case NORMAL:
- // See there is new dimm that needs to be excluded
- if ((NBPtr->DCTPtr->Timings.CsTestFail & NBPtr->DCTPtr->Timings.CsEnabled) != 0) {
- CsTestFail |= NBPtr->DCTPtr->Timings.CsTestFail;
- }
- break;
- case TRAINING:
- // Do not do any dimm excluding during training
- // Dimm exclude will be done at the end of training
- break;
- case END_TRAINING:
- // Exclude all dimms that have failures during training
- if ((NBPtr->DCTPtr->Timings.CsTrainFail != 0) ||
- ((NBPtr->DCTPtr->Timings.CsTestFail & NBPtr->DCTPtr->Timings.CsEnabled) != 0)) {
- CsTestFail |= NBPtr->DCTPtr->Timings.CsTestFail;
- }
- break;
- default:
- IDS_ERROR_TRAP;
- }
- }
- }
-
- if (CsTestFail != 0) {
- IsCSIntlvEnabled = FALSE;
- MCTPtr = NBPtr->MCTPtr;
- MCTPtr->NodeMemSize = 0;
- NBPtr->SharedPtr->NodeMap[NBPtr->Node].IsValid = FALSE;
- NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysBase = 0;
- NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysLimit = 0;
- NBPtr->SetBitField (NBPtr, BFDramBaseAddr, 0);
- NBPtr->SetBitField (NBPtr, BFDramLimitAddr, 0);
-
- if (MCTPtr->GangedMode) {
- // if ganged mode, disable all pairs of CS that fail.
- NBPtr->DCTPtr->Timings.CsTestFail |= CsTestFail;
- }
-
- // if chip select interleaving has been enabled, need to undo it before remapping memory
- if (NBPtr->FeatPtr->UndoInterleaveBanks (NBPtr)) {
- IsCSIntlvEnabled = TRUE;
- }
-
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- if (!MCTPtr->GangedMode || (MCTPtr->Dct == 0)) {
- if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
- NBPtr->DCTPtr->Timings.DctMemSize = 0;
-
- NBPtr->DCTPtr->Timings.CsEnabled = 0;
- for (q = 0; q < MAX_CS_PER_CHANNEL; q++) {
- NBPtr->SetBitField (NBPtr, BFCSBaseAddr0Reg + q, 0);
- }
-
- Flag = NBPtr->StitchMemory (NBPtr);
- ASSERT (Flag == TRUE);
- }
- }
- }
-
- // Re-enable chip select interleaving when remapping is done.
- if (IsCSIntlvEnabled) {
- NBPtr->FeatPtr->InterleaveBanks (NBPtr);
- }
-
- RetVal = TRUE;
- } else {
- RetVal = FALSE;
- }
- NBPtr->SwitchDCT (NBPtr, ReserveDCT);
- return RetVal;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Feat/IDENDIMM/mfidendimm.c b/src/vendorcode/amd/agesa/Proc/Mem/Feat/IDENDIMM/mfidendimm.c
deleted file mode 100644
index 9576f80..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Feat/IDENDIMM/mfidendimm.c
+++ /dev/null
@@ -1,528 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mfidendimm.c
- *
- * Translate physical system address to dimm identification.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Feat)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "mm.h"
-#include "mn.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "heapManager.h"
-#include "mfidendimm.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_FEAT_IDENDIMM_MFIDENDIMM_FILECODE
-extern MEM_NB_SUPPORT memNBInstalled[];
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define MAX_DCTS_PER_DIE 2 ///< Max DCTs per die
-#define MAX_CHLS_PER_DCT 1 ///< Max Channels per DCT
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-AGESA_STATUS
-STATIC
-MemFTransSysAddrToCS (
- IN OUT AMD_IDENTIFY_DIMM *AmdDimmIdentify,
- IN MEM_MAIN_DATA_BLOCK *mmPtr
- );
-
-UINT32
-STATIC
-MemFGetPCI (
- IN MEM_NB_BLOCK *NBPtr,
- IN UINT8 NodeID,
- IN UINT8 DctNum,
- IN BIT_FIELD_NAME BitFieldName
- );
-
-UINT8
-STATIC
-MemFUnaryXOR (
- IN UINT32 address
- );
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/*-----------------------------------------------------------------------------*/
-/**
-*
-* This function identifies the dimm on which the given memory address locates.
-*
-* @param[in, out] *AmdDimmIdentify - Pointer to the parameter structure AMD_IDENTIFY_DIMM
-*
-* @retval AGESA_SUCCESS - Successfully translate physical system address
-* to dimm identification.
-* AGESA_BOUNDS_CHK - Targeted address is out of bound.
-*
-*/
-
-AGESA_STATUS
-AmdIdentifyDimm (
- IN OUT AMD_IDENTIFY_DIMM *AmdDimmIdentify
- )
-{
- UINT8 i;
- AGESA_STATUS RetVal;
- MEM_MAIN_DATA_BLOCK mmData; // Main Data block
- MEM_NB_BLOCK *NBPtr;
- MEM_DATA_STRUCT MemData;
- LOCATE_HEAP_PTR LocHeap;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
- UINT8 Node;
- UINT8 Dct;
- UINT8 Die;
- UINT8 DieCount;
-
- LibAmdMemCopy (&(MemData.StdHeader), &(AmdDimmIdentify->StdHeader), sizeof (AMD_CONFIG_PARAMS), &(AmdDimmIdentify->StdHeader));
- mmData.MemPtr = &MemData;
- RetVal = MemSocketScan (&mmData);
- if (RetVal == AGESA_FATAL) {
- return RetVal;
- }
- DieCount = mmData.DieCount;
-
- // Search for AMD_MEM_AUTO_HANDLE on the heap first.
- // Only apply for space on the heap if cannot find AMD_MEM_AUTO_HANDLE on the heap.
- LocHeap.BufferHandle = AMD_MEM_AUTO_HANDLE;
- if (HeapLocateBuffer (&LocHeap, &AmdDimmIdentify->StdHeader) == AGESA_SUCCESS) {
- // NB block has already been constructed by main block.
- // No need to construct it here.
- NBPtr = (MEM_NB_BLOCK *)LocHeap.BufferPtr;
- } else {
- AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (MEM_NB_BLOCK)));
- AllocHeapParams.BufferHandle = AMD_MEM_AUTO_HANDLE;
- AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
- if (HeapAllocateBuffer (&AllocHeapParams, &AmdDimmIdentify->StdHeader) != AGESA_SUCCESS) {
- PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK, 0, 0, 0, 0, &AmdDimmIdentify->StdHeader);
- ASSERT(FALSE); // Could not allocate heap space for NB block for Identify DIMM
- return AGESA_FATAL;
- }
- NBPtr = (MEM_NB_BLOCK *)AllocHeapParams.BufferPtr;
- mmData.NBPtr = NBPtr;
- // Construct each die.
- for (Die = 0; Die < DieCount; Die ++) {
- i = 0;
- while (memNBInstalled[i].MemIdentifyDimmConstruct != 0) {
- if (memNBInstalled[i].MemIdentifyDimmConstruct (&NBPtr[Die], &MemData, Die)) {
- break;
- }
- i++;
- };
- if (memNBInstalled[i].MemIdentifyDimmConstruct == 0) {
- PutEventLog (AGESA_FATAL, MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM, Die, 0, 0, 0, &AmdDimmIdentify->StdHeader);
- ASSERT(FALSE); // No Identify DIMM constructor found
- return AGESA_FATAL;
- }
- }
- }
-
- if ((RetVal = MemFTransSysAddrToCS (AmdDimmIdentify, &mmData)) == AGESA_SUCCESS) {
- // Translate Node, DCT and Chip select number to Socket, Channel and Dimm number.
- Node = AmdDimmIdentify->SocketId;
- Dct = AmdDimmIdentify->MemChannelId;
- AmdDimmIdentify->SocketId = MemData.DiesPerSystem[Node].SocketId;
- AmdDimmIdentify->MemChannelId = NBPtr[Node].GetSocketRelativeChannel (&NBPtr[Node], Dct, 0);
- AmdDimmIdentify->DimmId /= 2;
- }
-
- return RetVal;
-}
-
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------*/
-/**
-*
-* This function translates the given physical system address to
-* a node, channel select, chip select, bank, row, and column address.
-*
-* @param[in, out] *AmdDimmIdentify - Pointer to the parameter structure AMD_IDENTIFY_DIMM
-* @param[in, out] *mmPtr - Pointer to the MEM_MAIN_DATA_BLOCK
-*
-* @retval AGESA_SUCCESS - The chip select address is found
-* @retval AGESA_BOUNDS_CHK - Targeted address is out of bound.
-*
-*/
-AGESA_STATUS
-STATIC
-MemFTransSysAddrToCS (
- IN OUT AMD_IDENTIFY_DIMM *AmdDimmIdentify,
- IN MEM_MAIN_DATA_BLOCK *mmPtr
- )
-{
- BOOLEAN CSFound;
- BOOLEAN DctSelHiRngEn;
- BOOLEAN DctSelIntLvEn;
- BOOLEAN DctGangEn;
- BOOLEAN HiRangeSelected;
- BOOLEAN DramHoleValid;
- BOOLEAN CSEn;
- BOOLEAN SwapDone;
- BOOLEAN IntLvRgnSwapEn;
- UINT8 DctSelHi;
- UINT8 DramEn;
- UINT8 range;
- UINT8 IntlvEn;
- UINT8 IntlvSel;
- UINT8 ILog;
- UINT8 DctSelIntLvAddr;
- UINT8 DctNum;
- UINT8 cs;
- UINT8 BadDramCs;
- UINT8 spare;
- UINT8 IntLvRgnBaseAddr;
- UINT8 IntLvRgnLmtAddr;
- UINT8 IntLvRgnSize;
- UINT32 temp;
- UINT32 DramHoleOffset;
- UINT64 DramBase;
- UINT64 DramLimit;
- UINT64 DctSelBaseAddr;
- UINT64 DctSelBaseOffset;
- UINT64 ChannelAddr;
- UINT64 CSBase;
- UINT64 CSMask;
- UINT64 InputAddr;
- UINT64 ChannelOffset;
- MEM_NB_BLOCK *NBPtr;
-
- UINT64 SysAddr;
- UINT8 *NodeID;
- UINT8 *ChannelSelect;
- UINT8 *ChipSelect;
-
- SysAddr = AmdDimmIdentify->MemoryAddress;
- NodeID = &(AmdDimmIdentify->SocketId);
- ChannelSelect = &(AmdDimmIdentify->MemChannelId);
- ChipSelect = &(AmdDimmIdentify->DimmId);
- CSFound = FALSE;
- ILog = 0;
- NBPtr = mmPtr->NBPtr;
-
- // Loop to determine the dram range
- for (range = 0; range < mmPtr->DieCount; range ++) {
- // DRAM Base
- temp = MemFGetPCI (NBPtr, 0, 0, BFDramBaseReg0 + range);
- DramEn = (UINT8) (temp & 0x3);
- IntlvEn = (UINT8) ((temp >> 8) & 0x7);
-
- DramBase = ((UINT64) (MemFGetPCI (NBPtr, 0, 0, BFDramBaseHiReg0 + range) & 0xFF) << 40) |
- (((UINT64) temp & 0xFFFF0000) << 8);
-
- // DRAM Limit
- temp = MemFGetPCI (NBPtr, 0, 0, BFDramLimitReg0 + range);
- *NodeID = (UINT8) (temp & 0x7);
- IntlvSel = (UINT8) ((temp >> 8) & 0x7);
- DramLimit = ((UINT64) (MemFGetPCI (NBPtr, 0, 0, BFDramLimitHiReg0 + range) & 0xFF) << 40) |
- (((UINT64) temp << 8) | 0xFFFFFF);
-
-
- if ((DramEn != 0) && (DramBase <= SysAddr) && (SysAddr <= DramLimit) &&
- ((IntlvEn == 0) || (IntlvSel == ((SysAddr >> 12) & IntlvEn)))) {
- // Determine the number of bit positions consumed by Node Interleaving
- switch (IntlvEn) {
-
- case 0x0:
- ILog = 0;
- break;
-
- case 0x1:
- ILog = 1;
- break;
-
- case 0x3:
- ILog = 2;
- break;
-
- case 0x7:
- ILog = 3;
- break;
-
- default:
- IDS_ERROR_TRAP;
- }
-
- // F2x10C Swapped Interleaved Region
- IntLvRgnSwapEn = (BOOLEAN) MemFGetPCI (NBPtr, *NodeID, 0, BFIntLvRgnSwapEn);
- if (IntLvRgnSwapEn) {
- IntLvRgnBaseAddr = (UINT8) MemFGetPCI (NBPtr, *NodeID, 0, BFIntLvRgnBaseAddr);
- IntLvRgnLmtAddr = (UINT8) MemFGetPCI (NBPtr, *NodeID, 0, BFIntLvRgnLmtAddr);
- IntLvRgnSize = (UINT8) MemFGetPCI (NBPtr, *NodeID, 0, BFIntLvRgnSize);
- ASSERT (IntLvRgnSize == (IntLvRgnLmtAddr - IntLvRgnBaseAddr + 1));
- if (((SysAddr >> 34) == 0) &&
- ((((SysAddr >> 27) >= IntLvRgnBaseAddr) && ((SysAddr >> 27) <= IntLvRgnLmtAddr))
- || ((SysAddr >> 27) < IntLvRgnSize))) {
- SysAddr ^= (UINT64) IntLvRgnBaseAddr << 27;
- }
- }
-
- // Extract variables from F2x110 DRAM Controller Select Low Register
- DctSelHiRngEn = (BOOLEAN) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelHiRngEn);
- DctSelHi = (UINT8) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelHi);
- DctSelIntLvEn = (BOOLEAN) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelIntLvEn);
- DctGangEn = (BOOLEAN) MemFGetPCI (NBPtr, *NodeID, 0, BFDctGangEn);
- DctSelIntLvAddr = (UINT8) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelIntLvAddr);
- DctSelBaseAddr = (UINT64) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelBaseAddr) << 27;
- DctSelBaseOffset = (UINT64) MemFGetPCI (NBPtr, *NodeID, 0, BFDctSelBaseOffset) << 26;
-
-
- // Determine if high DCT address range is being selected
- if (DctSelHiRngEn && !DctGangEn && (SysAddr >= DctSelBaseAddr)) {
- HiRangeSelected = TRUE;
- } else {
- HiRangeSelected = FALSE;
- }
-
- // Determine Channel
- if (DctGangEn) {
- *ChannelSelect = (UINT8) ((SysAddr >> 3) & 0x1);
- } else if (HiRangeSelected) {
- *ChannelSelect = DctSelHi;
- } else if (DctSelIntLvEn && (DctSelIntLvAddr == 0)) {
- *ChannelSelect = (UINT8) ((SysAddr >> 6) & 0x1);
- } else if (DctSelIntLvEn && (((DctSelIntLvAddr >> 1) & 0x1) != 0)) {
- temp = MemFUnaryXOR ((UINT32) ((SysAddr >> 16) & 0x1F));
- if ((DctSelIntLvAddr & 0x1) != 0) {
- *ChannelSelect = (UINT8) (((SysAddr >> 9) & 0x1) ^ temp);
- } else {
- *ChannelSelect = (UINT8) (((SysAddr >> 6) & 0x1) ^ temp);
- }
- } else if (DctSelIntLvEn) {
- *ChannelSelect = (UINT8) ((SysAddr >> (12 + ILog)) & 0x1);
- } else if (DctSelHiRngEn) {
- *ChannelSelect = ~DctSelHi & 0x1;
- } else {
- *ChannelSelect = 0;
- }
- ASSERT (*ChannelSelect < NBPtr[*NodeID].DctCount);
-
- DramHoleOffset = MemFGetPCI (NBPtr, *NodeID, 0, BFDramHoleOffset) << 23;
- DramHoleValid = (BOOLEAN) MemFGetPCI (NBPtr, *NodeID, 0, BFDramHoleValid);
-
- // Determine base address offset
- if (HiRangeSelected) {
- if (((DctSelBaseAddr >> 32) == 0) && DramHoleValid && (SysAddr >= (UINT64) 0x100000000)) {
- ChannelOffset = (UINT64) DramHoleOffset;
- } else {
- ChannelOffset = DctSelBaseOffset;
- }
- } else {
- if (DramHoleValid && (SysAddr >= (UINT64) 0x100000000)) {
- ChannelOffset = (UINT64) DramHoleOffset;
- } else {
- ChannelOffset = DramBase;
- }
- }
-
- // Remove hoisting offset and normalize to DRAM bus addresses
- ChannelAddr = SysAddr - ChannelOffset;
-
- // Remove node interleaving
- if (IntlvEn != 0) {
- ChannelAddr = ((ChannelAddr >> (12 + ILog)) << 12) | (ChannelAddr & 0xFFF);
- }
-
- // Remove channel interleave
- if (DctSelIntLvEn && !HiRangeSelected && !DctGangEn) {
- if ((DctSelIntLvAddr & 1) != 1) {
- // A[6] Select or Hash 6
- ChannelAddr = ((ChannelAddr >> 7) << 6) | (ChannelAddr & 0x3F);
- } else if (DctSelIntLvAddr == 1) {
- // A[12]
- ChannelAddr = ((ChannelAddr >> 13) << 12) | (ChannelAddr & 0xFFF);
- } else {
- // Hash 9
- ChannelAddr = ((ChannelAddr >> 10) << 9) | (ChannelAddr & 0x1FF);
- }
- }
-
- // Determine the Chip Select
- for (cs = 0; cs < MAX_CS_PER_CHANNEL; ++ cs) {
- DctNum = DctGangEn ? 0 : *ChannelSelect;
-
- // Obtain the CS Base
- temp = MemFGetPCI (NBPtr, *NodeID, DctNum, BFCSBaseAddr0Reg + cs);
- CSEn = (BOOLEAN) (temp & 0x1);
- CSBase = ((UINT64) temp & CS_REG_MASK) << 8;
-
- // Obtain the CS Mask
- CSMask = ((UINT64) MemFGetPCI (NBPtr, *NodeID, DctNum, BFCSMask0Reg + (cs >> 1)) & CS_REG_MASK) << 8;
-
- // Adjust the Channel Addr for easy comparison
- InputAddr = ((ChannelAddr >> 8) & CS_REG_MASK) << 8;
-
- if (CSEn && ((InputAddr & ~CSMask) == (CSBase & ~CSMask))) {
- CSFound = TRUE;
-
- *ChipSelect = cs;
-
- temp = MemFGetPCI (NBPtr, *NodeID, 0, BFOnLineSpareControl);
- SwapDone = (BOOLEAN) ((temp >> (1 + 2 * (*ChannelSelect))) & 0x1);
- BadDramCs = (UINT8) ((temp >> (4 + 4 * (*ChannelSelect))) & 0x7);
- if (SwapDone && (cs == BadDramCs)) {
- // Find the spare rank for the channel
- for (spare = 0; spare < MAX_CS_PER_CHANNEL; ++spare) {
- if ((MemFGetPCI (NBPtr, *NodeID, DctNum, BFCSBaseAddr0Reg + spare) & 0x2) != 0) {
- *ChipSelect = spare;
- break;
- }
- }
- }
- ASSERT (*ChipSelect < MAX_CS_PER_CHANNEL);
-
- break;
- }
- }
- }
- if (CSFound) {
- break;
- }
- }
-
- // last ditch sanity check
- ASSERT (!CSFound || ((*NodeID < mmPtr->DieCount) && (*ChannelSelect < NBPtr[*NodeID].DctCount) && (*ChipSelect < MAX_CS_PER_CHANNEL)));
- if (CSFound) {
- return AGESA_SUCCESS;
- } else {
- return AGESA_BOUNDS_CHK;
- }
-
-}
-
-
-/*-----------------------------------------------------------------------------*/
-/**
-*
-* This function is the interface to call the PCI register access function
-* defined in NB block.
-*
-* @param[in] *NBPtr - Pointer to the parameter structure MEM_NB_BLOCK
-* @param[in] NodeID - Node ID number of the target Northbridge
-* @param[in] DctNum - DCT number if applicable, otherwise, put 0
-* @param[in] BitFieldName - targeted bitfield
-*
-* @retval UINT32 - 32 bits PCI register value
-*
-*/
-UINT32
-STATIC
-MemFGetPCI (
- IN MEM_NB_BLOCK *NBPtr,
- IN UINT8 NodeID,
- IN UINT8 DctNum,
- IN BIT_FIELD_NAME BitFieldName
- )
-{
- MEM_NB_BLOCK *LocalNBPtr;
- // Get the northbridge pointer for the targeted node.
- LocalNBPtr = &NBPtr[NodeID];
- LocalNBPtr->Dct = DctNum;
- // The caller of this function will take care of the ganged/unganged situation.
- // So Ganged is set to be false here, and do PCI read on the DCT specified by DctNum.
- return LocalNBPtr->GetBitField (LocalNBPtr, BitFieldName);
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
-*
-* This function returns an even parity bit (making the total # of 1's even)
-* {0, 1} = number of set bits in argument is {even, odd}.
-*
-* @param[in] address - the address on which the parity bit will be calculated
-*
-* @retval UINT8 - parity bit
-*
-*/
-
-UINT8
-STATIC
-MemFUnaryXOR (
- IN UINT32 address
- )
-{
- UINT8 parity;
- UINT8 index;
- parity = 0;
- for (index = 0; index < 32; ++ index) {
- parity = (UINT8) (parity ^ (address & 0x1));
- address = address >> 1;
- }
- return parity;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Feat/IDENDIMM/mfidendimm.h b/src/vendorcode/amd/agesa/Proc/Mem/Feat/IDENDIMM/mfidendimm.h
deleted file mode 100644
index 842233c..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Feat/IDENDIMM/mfidendimm.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mfidendimm.h
- *
- * Header file for address to dimm identification translator.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MFIDENDIMM_H_
-#define _MFIDENDIMM_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-#define CS_REG_MASK 0x1FF83FE0
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-MemNIdentifyDimmConstructorDr (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- );
-
-BOOLEAN
-MemNIdentifyDimmConstructorDA (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- );
-
-BOOLEAN
-MemNIdentifyDimmConstructorHy (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- );
-
-BOOLEAN
-MemNIdentifyDimmConstructorC32 (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- );
-
-BOOLEAN
-MemNIdentifyDimmConstructorLN (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- );
-
-#endif //_MFIDENDIMM_H_
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Feat/INTLVRN/mfintlvrn.c b/src/vendorcode/amd/agesa/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
deleted file mode 100644
index b14d0e8..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Feat/INTLVRN/mfintlvrn.c
+++ /dev/null
@@ -1,152 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mfrintlv.c
- *
- * Feature Region interleaving support
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Feat/Intlvrgn)
- * @e \$Revision: 38442 $ @e \$Date: 2010-09-24 06:39:57 +0800 (Fri, 24 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "mport.h"
-#include "mm.h"
-#include "mn.h"
-#include "mfintlvrn.h"
-#include "Ids.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_FEAT_INTLVRN_MFINTLVRN_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define _4GB_RJ27 ((UINT32)4 << (30 - 27))
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * MemFInterleaveRegion:
- *
- * Applies region interleaving if both DCTs have different size of memory, and
- * the channel interleaving region doesn't have UMA covered.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemFInterleaveRegion (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT32 TOM;
- UINT32 TOM2;
- UINT32 TOMused;
- UINT32 UmaBase;
- UINT32 DctSelBase;
- S_UINT64 SMsr;
-
- MEM_DATA_STRUCT *MemPtr;
- MEM_PARAMETER_STRUCT *RefPtr;
- DIE_STRUCT *MCTPtr;
-
- MemPtr = NBPtr->MemPtr;
- RefPtr = NBPtr->RefPtr;
- MCTPtr = NBPtr->MCTPtr;
-
- UmaBase = (UINT32) RefPtr->UmaBase >> (27 - 16);
-
- //TOM scaled from [47:0] to [47:27]
- LibAmdMsrRead (TOP_MEM, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- TOM = (SMsr.lo >> 27) | (SMsr.hi << (32 - 27));
-
- //TOM2 scaled from [47:0] to [47:27]
- LibAmdMsrRead (TOP_MEM2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- TOM2 = (SMsr.lo >> 27) | (SMsr.hi << (32 - 27));
-
- TOMused = (UmaBase >= _4GB_RJ27) ? TOM2 : TOM;
-
- if (UmaBase != 0) {
- //Check if channel interleaving is enabled ? if so, go to next step.
- if (NBPtr->GetBitField (NBPtr, BFDctSelIntLvEn) == 1) {
- DctSelBase = NBPtr->GetBitField (NBPtr, BFDctSelBaseAddr);
- //Skip if DctSelBase is equal to 0, because DCT0 has as the same memory size as DCT1.
- if (DctSelBase != 0) {
- //We need not enable swapped interleaved region when channel interleaving region has covered all of the UMA.
- if (DctSelBase < TOMused) {
- NBPtr->EnableSwapIntlvRgn (NBPtr, UmaBase, TOMused);
- }
- }
- }
- }
-}
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Feat/INTLVRN/mfintlvrn.h b/src/vendorcode/amd/agesa/Proc/Mem/Feat/INTLVRN/mfintlvrn.h
deleted file mode 100644
index b0c925a..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Feat/INTLVRN/mfintlvrn.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mfintlvrn.h
- *
- * Feature region interleaving
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-#ifndef _MFINTLVRN_H_
-#define _MFINTLVRN_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-VOID
-MemFInterleaveRegion (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-#endif /* _MFINTLVRN_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Feat/LVDDR3/mflvddr3.c b/src/vendorcode/amd/agesa/Proc/Mem/Feat/LVDDR3/mflvddr3.c
deleted file mode 100644
index bf503bf..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Feat/LVDDR3/mflvddr3.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * lvddr3.c
- *
- * Voltage change for DDR3 DIMMs.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Feat/LVDDR3)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_FEAT_LVDDR3_MFLVDDR3_FILECODE
-/* features */
-#include "mflvddr3.h"
-
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------*/
-/**
- *
- * This function calculate the common lowest voltage supported by all DDR3
- * DIMMs in the system. This function only needs to be called on BSP.
- *
- * @param[in, out] *NBPtr - Pointer to NB block
- *
- * @return TRUE - This feature is enabled.
- * @return FALSE - This feature is not enabled.
- */
-
-BOOLEAN
-MemFLvDdr3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- CH_DEF_STRUCT *ChannelPtr;
- MEM_TECH_BLOCK *TechPtr;
- MEM_SHARED_DATA *mmSharedPtr;
- UINT8 Dct;
- UINT8 Channel;
- UINT8 Dimm;
- UINT8 *SpdBufferPtr;
- UINT8 VDDByte;
- UINT8 VoltageMap;
-
- mmSharedPtr = NBPtr->SharedPtr;
- TechPtr = NBPtr->TechPtr;
- VoltageMap = 0xFF;
-
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) {
- NBPtr->SwitchChannel (NBPtr, Channel);
- ChannelPtr = NBPtr->ChannelPtr;
- for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
- if (TechPtr->GetDimmSpdBuffer (TechPtr, &SpdBufferPtr, Dimm)) {
- // SPD byte 6: Module Nominal Voltage, VDD
- // 1.5v - bit 0
- // 1.35v - bit 1
- // 1.2v - bit 2
- VDDByte = SpdBufferPtr[MNVVDD];
- // Reverse the 1.5V operable bit. So its encoding can be consistent
- // with that of 1.35V and 1.25V operable bit.
- VDDByte ^= 1;
- ASSERT (VDDByte != 0);
-
- if (mmSharedPtr->VoltageMap != 0) {
- // Get the common supported voltage map
- VoltageMap &= VDDByte;
- } else {
- // This is the second execution of all the loop as no common voltage is found
- if (VDDByte == (1 << VOLT1_5)) {
- // Always exclude 1.5V dimm if no common voltage is found
- ChannelPtr->DimmExclude |= (UINT16) 1 << Dimm;
- }
- }
- }
- }
- if (mmSharedPtr->VoltageMap == 0) {
- NBPtr->DCTPtr->Timings.DimmExclude |= ChannelPtr->DimmExclude;
- }
- }
- }
-
- if (mmSharedPtr->VoltageMap != 0) {
- mmSharedPtr->VoltageMap &= VoltageMap;
- }
-
- return TRUE;
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Feat/LVDDR3/mflvddr3.h b/src/vendorcode/amd/agesa/Proc/Mem/Feat/LVDDR3/mflvddr3.h
deleted file mode 100644
index 85bb6f4..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Feat/LVDDR3/mflvddr3.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mflvddr3.h
- *
- * Header file for DDR3 DIMMs voltage configuration.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MFLVDDR3_H_
-#define _MFLVDDR3_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-#define MNVVDD 6
-#define LOWEST_VOLT_BIT 2
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-MemFLvDdr3 (
- IN OUT MEM_NB_BLOCK *NBPtr
-);
-
-#endif //_MFLVDDR3_H_
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Feat/MEMCLR/mfmemclr.c b/src/vendorcode/amd/agesa/Proc/Mem/Feat/MEMCLR/mfmemclr.c
deleted file mode 100644
index 6cbe11b..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Feat/MEMCLR/mfmemclr.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mfmemclr.c
- *
- * Feature function for memory clear operation
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Feat/Memclr)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-
-
-#include "AGESA.h"
-#include "mm.h"
-#include "mn.h"
-#include "mfmemclr.h"
-#include "Ids.h"
-#include "merrhdl.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_FEAT_MEMCLR_MFMEMCLR_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * Initiates memory clear operation on one node with Dram on it.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-BOOLEAN
-MemFMctMemClr_Init (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- AGESA_TESTPOINT (TpProcMemMemClr, &NBPtr->MemPtr->StdHeader);
- if (NBPtr->RefPtr->EnableMemClr == TRUE) {
- if (NBPtr->MCTPtr->NodeMemSize != 0) {
- if (!NBPtr->MemCleared) {
- NBPtr->PollBitField (NBPtr, BFMemClrBusy, 0, SPECIAL_PCI_ACCESS_TIMEOUT, FALSE);
- if (NBPtr->GetBitField (NBPtr, BFDramEnabled) == 1) {
- NBPtr->FamilySpecificHook[BeforeMemClr] (NBPtr, NBPtr);
- NBPtr->SetBitField (NBPtr, BFDramBaseAddr, 0);
- NBPtr->SetBitField (NBPtr, BFMemClrInit, 1);
- }
- }
- }
- }
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * Ensures memory clear operation has completed on one node with Dram on it.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-BOOLEAN
-MemFMctMemClr_Sync (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- if (NBPtr->RefPtr->EnableMemClr == TRUE) {
- if (NBPtr->MCTPtr->NodeMemSize != 0) {
- if (!NBPtr->MemCleared) {
- NBPtr->PollBitField (NBPtr, BFMemClrBusy, 0, SPECIAL_PCI_ACCESS_TIMEOUT, FALSE);
- NBPtr->PollBitField (NBPtr, BFMemCleared, 1, SPECIAL_PCI_ACCESS_TIMEOUT, FALSE);
- NBPtr->SetBitField (NBPtr, BFDramBaseAddr, NBPtr->MCTPtr->NodeSysBase >> (27 - 16));
- NBPtr->MemCleared = TRUE;
- }
- }
- }
- return TRUE;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Feat/NDINTLV/mfndi.c b/src/vendorcode/amd/agesa/Proc/Mem/Feat/NDINTLV/mfndi.c
deleted file mode 100644
index 3e7a20a..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Feat/NDINTLV/mfndi.c
+++ /dev/null
@@ -1,218 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mfndi.c
- *
- * Feature applies Node memory interleaving
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Feat/Ndintlv)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "mm.h"
-#include "mn.h"
-#include "mfndi.h"
-#include "Ids.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_FEAT_NDINTLV_MFNDI_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define _4GB_ (0x10000)
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Perform a check to see if node interleaving can be enabled on each node.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - Node interleaving can be enabled.
- * @return FALSE - Node interleaving cannot be enabled.
- */
-
-BOOLEAN
-MemFCheckInterleaveNodes (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- DIE_STRUCT *MCTPtr;
-
- ASSERT (NBPtr != NULL);
-
- MCTPtr = NBPtr->MCTPtr;
-
- if (MCTPtr->NodeMemSize != 0) {
- if (!NBPtr->SharedPtr->NodeIntlv.IsValid) {
- NBPtr->SharedPtr->NodeIntlv.NodeMemSize = MCTPtr->NodeMemSize;
- NBPtr->SharedPtr->NodeIntlv.Dct0MemSize = MCTPtr->DctData[0].Timings.DctMemSize;
- NBPtr->SharedPtr->NodeIntlv.IsValid = TRUE;
- } else {
- if ((NBPtr->SharedPtr->NodeIntlv.NodeMemSize != MCTPtr->NodeMemSize) ||
- (NBPtr->SharedPtr->NodeIntlv.Dct0MemSize != MCTPtr->DctData[0].Timings.DctMemSize)) {
- return FALSE;
- }
- }
- }
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Applies Node memory interleaving for each node.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - This feature is enabled.
- * @return FALSE - This feature is not enabled.
- */
-
-BOOLEAN
-MemFInterleaveNodes (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 NodeCnt;
- UINT8 BitShift;
- UINT32 MemSize;
- UINT32 Dct0MemSize;
- UINT32 NodeSysBase;
- UINT32 NodeSysLimit;
- UINT32 HoleBase;
- UINT32 HoleSize;
- UINT32 HoleOffset;
- MEM_PARAMETER_STRUCT *RefPtr;
- DIE_STRUCT *MCTPtr;
-
- ASSERT (NBPtr != NULL);
-
- RefPtr = NBPtr->RefPtr;
- MCTPtr = NBPtr->MCTPtr;
- if (RefPtr->GStatus[GsbSoftHole] || RefPtr->GStatus[GsbHWHole]) {
- HoleBase = RefPtr->HoleBase;
- HoleSize = _4GB_ - HoleBase;
- } else {
- HoleBase = 0;
- HoleSize = 0;
- }
-
- NodeCnt = NBPtr->SharedPtr->NodeIntlv.NodeCnt;
- Dct0MemSize = NBPtr->SharedPtr->NodeIntlv.Dct0MemSize;
- MemSize = NBPtr->SharedPtr->NodeIntlv.NodeMemSize;
-
- BitShift = LibAmdBitScanForward (NodeCnt);
- Dct0MemSize <<= BitShift;
- if (HoleSize != 0) {
- RefPtr->GStatus[GsbHWHole] = TRUE;
- HoleOffset = HoleSize;
- if (Dct0MemSize >= HoleBase) {
- Dct0MemSize += HoleSize;
- } else {
- HoleOffset += Dct0MemSize;
- }
- } else {
- HoleOffset = 0;
- }
-
- MemSize = (MemSize << BitShift) + HoleSize;
-
- MCTPtr->NodeSysBase = 0;
- MCTPtr->NodeSysLimit = MemSize - 1;
-
- NBPtr->SetBitField (NBPtr, BFDramIntlvSel, NBPtr->SharedPtr->NodeIntlv.NodeIntlvSel);
- NBPtr->SetBitField (NBPtr, BFDramBaseAddr, 0);
- NBPtr->SetBitField (NBPtr, BFDramIntlvEn, NodeCnt - 1);
- NBPtr->SetBitField (NBPtr, BFDramLimitAddr, (MemSize - 1) >> (27 - 16));
-
- if (HoleSize != 0) {
- MCTPtr->Status[SbHWHole] = TRUE;
- // DramHoleBase will be set when sync address map to other nodes.
- NBPtr->SetBitField (NBPtr, BFDramHoleOffset, HoleOffset >> (23 - 16));
- NBPtr->SetBitField (NBPtr, BFDramHoleValid, 1);
- }
-
- if ((MCTPtr->DctData[1].Timings.DctMemSize != 0) && (!NBPtr->Ganged)) {
- NBPtr->SetBitField (NBPtr, BFDctSelBaseAddr, Dct0MemSize >> (27 - 16));
- NBPtr->SetBitField (NBPtr, BFDctSelBaseOffset, Dct0MemSize >> (26 - 16));
- }
-
- NodeSysBase = NodeCnt - 1;
- NodeSysLimit = ((MemSize - 1)& 0xFFFFFF00) | NBPtr->SharedPtr->NodeIntlv.NodeIntlvSel;
- NBPtr->SharedPtr->NodeMap[NBPtr->Node].IsValid = TRUE;
- NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysBase = NodeSysBase;
- NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysLimit = NodeSysLimit;
-
- NBPtr->SharedPtr->NodeIntlv.NodeIntlvSel++;
- return TRUE;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Feat/NDINTLV/mfndi.h b/src/vendorcode/amd/agesa/Proc/Mem/Feat/NDINTLV/mfndi.h
deleted file mode 100644
index 1877c35..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Feat/NDINTLV/mfndi.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mfndi.h
- *
- * Feature node interleaving
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _MFNDI_H_
-#define _MFNDI_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-MemFInterleaveNodes (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-#endif /* _MFNDI_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c b/src/vendorcode/amd/agesa/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c
deleted file mode 100644
index a3d95df..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mfodthermal.c
- *
- * On Dimm thermal management.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Feat)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "Ids.h"
-#include "mfodthermal.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_FEAT_ODTHERMAL_MFODTHERMAL_FILECODE
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/*-----------------------------------------------------------------------------*/
-/**
- *
- * This function does On-Dimm thermal management.
- *
- * @param[in, out] *NBPtr - Pointer to the MEM_NB_BLOCK.
- *
- * @return TRUE - This feature is enabled.
- * @return FALSE - This feature is not enabled.
- */
-
-BOOLEAN
-MemFOnDimmThermal (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 i;
- UINT8 Dct;
- CH_DEF_STRUCT *ChannelPtr;
- MEM_DATA_STRUCT *MemPtr;
- UINT8 *SpdBufferPtr;
- UINT8 ThermalOp;
- BOOLEAN ODTSEn;
- BOOLEAN ExtendTmp;
-
- ODTSEn = FALSE;
- ExtendTmp = FALSE;
-
- ASSERT (NBPtr != NULL);
- MemPtr = NBPtr->MemPtr;
- AGESA_TESTPOINT (TpProcMemOnDimmThermal, &MemPtr->StdHeader);
- if (NBPtr->MCTPtr->NodeMemSize != 0) {
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- // Only go through the DCT if it is not disabled.
- if (NBPtr->GetBitField (NBPtr, BFDisDramInterface) == 0) {
- ChannelPtr = NBPtr->ChannelPtr;
- // If Ganged mode is enabled, need to go through all dram devices on both DCTs.
- if (!NBPtr->Ganged || (NBPtr->Dct != 1)) {
- if (!(NBPtr->IsSupported[CheckSetSameDctODTsEn]) || (NBPtr->IsSupported[CheckSetSameDctODTsEn] && (NBPtr->Dct != 1))) {
- ODTSEn = TRUE;
- ExtendTmp = TRUE;
- }
- }
- for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i ++) {
- if (NBPtr->TechPtr->GetDimmSpdBuffer (NBPtr->TechPtr, &SpdBufferPtr, i)) {
- // Check byte 31: thermal and refresh option.
- ThermalOp = SpdBufferPtr[THERMAL_OPT];
- // Bit 3: ODTS readout
- if (!((ThermalOp >> 3) & 1)) {
- ODTSEn = FALSE;
- }
- // Bit 0: Extended Temperature Range.
- if (!(ThermalOp & 1)) {
- ExtendTmp = FALSE;
- }
- }
- }
-
- if (!NBPtr->Ganged || (NBPtr->Dct == 1)) {
- // If in ganged mode, need to switch back to DCT0 to set the registers.
- if (NBPtr->Ganged || NBPtr->IsSupported[CheckSetSameDctODTsEn]) {
- NBPtr->SwitchDCT (NBPtr, 0);
- ChannelPtr = NBPtr->ChannelPtr;
- }
- // If all dram devices on a DCT support ODTS
- if (ODTSEn) {
- NBPtr->SetBitField (NBPtr, BFODTSEn, 1);
- }
- ChannelPtr->ExtendTmp = ExtendTmp;
- }
- }
- IDS_HDT_CONSOLE (MEM_FLOW, "\tDct %d\n", Dct);
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\tODTSEn = %d\n", ODTSEn);
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\tExtendTmp = %d\n", ExtendTmp);
- }
- }
- return TRUE;
-}
-
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Feat/ODTHERMAL/mfodthermal.h b/src/vendorcode/amd/agesa/Proc/Mem/Feat/ODTHERMAL/mfodthermal.h
deleted file mode 100644
index df7603f..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Feat/ODTHERMAL/mfodthermal.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mfodthermal.h
- *
- * Header file for On-Dimm thermal management.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MFODTHERMAL_H_
-#define _MFODTHERMAL_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-MemFOnDimmThermal (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-#endif //_MFODTHERMAL_H_
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Feat/OLSPARE/mfspr.c b/src/vendorcode/amd/agesa/Proc/Mem/Feat/OLSPARE/mfspr.c
deleted file mode 100644
index 5f83000..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Feat/OLSPARE/mfspr.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mfspr.c
- *
- * Feature enable online spare
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Feat/Olspare)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "mm.h"
-#include "mn.h"
-#include "mfspr.h"
-#include "Ids.h"
-#include "amdlib.h"
-#include "Filecode.h"
-#include "GeneralServices.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_FEAT_OLSPARE_MFSPR_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Enable online spare on current node if it is requested.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - This feature is enabled.
- * @return FALSE - This feature is not enabled.
- */
-
-BOOLEAN
-MemFOnlineSpare (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 Dct;
- UINT8 q;
- UINT8 Value8;
- BOOLEAN Flag;
- BOOLEAN OnlineSprEnabled[MAX_CHANNELS_PER_SOCKET];
-
- MEM_PARAMETER_STRUCT *RefPtr;
- DIE_STRUCT *MCTPtr;
-
- ASSERT (NBPtr != NULL);
-
- RefPtr = NBPtr->RefPtr;
- Flag = FALSE;
- if (RefPtr->EnableOnLineSpareCtl != 0) {
- RefPtr->GStatus[GsbEnDIMMSpareNW] = TRUE;
- MCTPtr = NBPtr->MCTPtr;
-
- // Check if online spare can be enabled on current node
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- ASSERT (Dct < sizeof (OnlineSprEnabled));
- NBPtr->SwitchDCT (NBPtr, Dct);
- OnlineSprEnabled[Dct] = FALSE;
- if ((MCTPtr->GangedMode == 0) || (MCTPtr->Dct == 0)) {
- if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
- // Make sure at least two chip-selects are available
- Value8 = LibAmdBitScanReverse (NBPtr->DCTPtr->Timings.CsEnabled);
- if (Value8 > LibAmdBitScanForward (NBPtr->DCTPtr->Timings.CsEnabled)) {
- OnlineSprEnabled[Dct] = TRUE;
- Flag = TRUE;
- } else {
- PutEventLog (AGESA_ERROR, MEM_ERROR_DIMM_SPARING_NOT_ENABLED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- MCTPtr->ErrStatus[EsbSpareDis] = TRUE;
- }
- }
- }
- }
-
- // If we don't have spared rank on any DCT, we don't run the rest part of the code.
- if (!Flag) {
- return FALSE;
- }
-
- MCTPtr->NodeMemSize = 0;
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- if (OnlineSprEnabled[Dct]) {
- // Only run StitchMemory if we need to set a spare rank.
- NBPtr->DCTPtr->Timings.DctMemSize = 0;
- for (q = 0; q < MAX_CS_PER_CHANNEL; q++) {
- NBPtr->SetBitField (NBPtr, BFCSBaseAddr0Reg + q, 0);
- }
- Flag = NBPtr->StitchMemory (NBPtr);
- ASSERT (Flag == TRUE);
- } else if ((MCTPtr->GangedMode == 0) && (NBPtr->DCTPtr->Timings.DctMemSize != 0)) {
- // Otherwise, need to adjust the memory size on the node.
- MCTPtr->NodeMemSize += NBPtr->DCTPtr->Timings.DctMemSize;
- MCTPtr->NodeSysLimit = MCTPtr->NodeMemSize - 1;
- }
- }
- return TRUE;
- } else {
- return FALSE;
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Feat/OLSPARE/mfspr.h b/src/vendorcode/amd/agesa/Proc/Mem/Feat/OLSPARE/mfspr.h
deleted file mode 100644
index fccdb0f..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Feat/OLSPARE/mfspr.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mfspr.h
- *
- * Feature enable Online spare
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MFSPR_H_
-#define _MFSPR_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-MemFOnlineSpare (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-#endif /* _MFSPR_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Feat/PARTRN/mfParallelTraining.c b/src/vendorcode/amd/agesa/Proc/Mem/Feat/PARTRN/mfParallelTraining.c
deleted file mode 100644
index 4cc3771..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Feat/PARTRN/mfParallelTraining.c
+++ /dev/null
@@ -1,286 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mfParallelTraining.c
- *
- * This is the parallel training feature
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Feat/PARTRN)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuApicUtilities.h"
-#include "mfParallelTraining.h"
-#include "heapManager.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_FEAT_PARTRN_MFPARALLELTRAINING_FILECODE
-
-/*-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-extern MEM_TECH_CONSTRUCTOR* memTechInstalled[];
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This is the main function to perform parallel training on all nodes.
- * This is the routine which will run on the remote AP.
- *
- * @param[in,out] *EnvPtr - Pointer to the Training Environment Data
- * @param[in,out] *StdHeader - Pointer to the Standard Header of the AP
- *
- * @return TRUE - This feature is enabled.
- * @return FALSE - This feature is not enabled.
- */
-BOOLEAN
-MemFParallelTraining (
- IN OUT REMOTE_TRAINING_ENV *EnvPtr,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- MEM_PARAMETER_STRUCT ParameterList;
- MEM_NB_BLOCK NB;
- MEM_TECH_BLOCK TB;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
- MEM_DATA_STRUCT *MemPtr;
- DIE_STRUCT *MCTPtr;
- UINT8 p;
- UINT8 i;
- UINT8 Dct;
- UINT8 Channel;
- UINT8 *BufferPtr;
- UINT8 DctCount;
- UINT8 ChannelCount;
- UINT8 RowCount;
- UINT8 ColumnCount;
- UINT16 SizeOfNewBuffer;
- AP_DATA_TRANSFER ReturnData;
-
- //
- // Initialize Parameters
- //
- ReturnData.DataPtr = NULL;
- ReturnData.DataSizeInDwords = 0;
- ReturnData.DataTransferFlags = 0;
-
- ASSERT (EnvPtr != NULL);
- //
- // Replace Standard header of a AP
- //
- LibAmdMemCopy (StdHeader, &(EnvPtr->StdHeader), sizeof (AMD_CONFIG_PARAMS), &(EnvPtr->StdHeader));
-
-
- //
- // Allocate buffer for training data
- //
- BufferPtr = (UINT8 *) (&EnvPtr->DieStruct);
- DctCount = EnvPtr->DieStruct.DctCount;
- BufferPtr += sizeof (DIE_STRUCT);
- ChannelCount = ((DCT_STRUCT *) BufferPtr)->ChannelCount;
- BufferPtr += DctCount * sizeof (DCT_STRUCT);
- RowCount = ((CH_DEF_STRUCT *) BufferPtr)->RowCount;
- ColumnCount = ((CH_DEF_STRUCT *) BufferPtr)->ColumnCount;
-
- SizeOfNewBuffer = sizeof (DIE_STRUCT) +
- DctCount * (
- sizeof (DCT_STRUCT) + (
- ChannelCount * (
- sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK) + (
- RowCount * ColumnCount * NUMBER_OF_DELAY_TABLES +
- (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES)
- )
- )
- )
- );
- AllocHeapParams.RequestedBufferSize = SizeOfNewBuffer;
- AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, 0, 0, 0);
- AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
- if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
- BufferPtr = AllocHeapParams.BufferPtr;
- LibAmdMemCopy ( BufferPtr,
- &(EnvPtr->DieStruct),
- sizeof (DIE_STRUCT) + DctCount * (sizeof (DCT_STRUCT) + ChannelCount * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))),
- StdHeader
- );
-
- //
- // Fix up pointers
- //
- MCTPtr = (DIE_STRUCT *) BufferPtr;
- BufferPtr += sizeof (DIE_STRUCT);
- MCTPtr->DctData = (DCT_STRUCT *) BufferPtr;
- BufferPtr += MCTPtr->DctCount * sizeof (DCT_STRUCT);
- for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) {
- MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) BufferPtr;
- BufferPtr += MCTPtr->DctData[Dct].ChannelCount * sizeof (CH_DEF_STRUCT);
- for (Channel = 0; Channel < MCTPtr->DctData[Dct].ChannelCount; Channel++) {
- MCTPtr->DctData[Dct].ChData[Channel].MCTPtr = MCTPtr;
- MCTPtr->DctData[Dct].ChData[Channel].DCTPtr = &MCTPtr->DctData[Dct];
- }
- }
- NB.PSBlock = (MEM_PS_BLOCK *) BufferPtr;
- BufferPtr += DctCount * ChannelCount * sizeof (MEM_PS_BLOCK);
-
- ReturnData.DataPtr = AllocHeapParams.BufferPtr;
- ReturnData.DataSizeInDwords = (SizeOfNewBuffer + 3) / 4;
- ReturnData.DataTransferFlags = 0;
-
- //
- // Allocate Memory for the MEM_DATA_STRUCT we will use
- //
- AllocHeapParams.RequestedBufferSize = sizeof (MEM_DATA_STRUCT);
- AllocHeapParams.BufferHandle = AMD_MEM_DATA_HANDLE;
- AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
- if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
- MemPtr = (MEM_DATA_STRUCT *)AllocHeapParams.BufferPtr;
-
- LibAmdMemCopy (&(MemPtr->StdHeader), &(EnvPtr->StdHeader), sizeof (AMD_CONFIG_PARAMS), StdHeader);
-
- //
- // Copy Parameters from environment
- //
- ParameterList.HoleBase = EnvPtr->HoleBase;
- ParameterList.BottomIo = EnvPtr->BottomIo;
- ParameterList.UmaSize = EnvPtr->UmaSize;
- ParameterList.SysLimit = EnvPtr->SysLimit;
- ParameterList.TableBasedAlterations = EnvPtr->TableBasedAlterations;
- ParameterList.PlatformMemoryConfiguration = EnvPtr->PlatformMemoryConfiguration;
- MemPtr->ParameterListPtr = &ParameterList;
-
- for (p = 0; p < MAX_PLATFORM_TYPES; p++) {
- MemPtr->GetPlatformCfg[p] = EnvPtr->GetPlatformCfg[p];
- }
-
- MemPtr->ErrorHandling = EnvPtr->ErrorHandling;
- //
- // Create Local NBBlock and Tech Block
- //
- EnvPtr->NBBlockCtor (&NB, MCTPtr, EnvPtr->FeatPtr);
- NB.RefPtr = &ParameterList;
- NB.MemPtr = MemPtr;
- i = 0;
- while (memTechInstalled[i] != NULL) {
- if (memTechInstalled[i] (&TB, &NB)) {
- break;
- }
- i++;
- }
- NB.TechPtr = &TB;
- NB.TechBlockSwitch (&NB);
-
- //
- // Setup CPU Mem Type MSRs on the AP
- //
- NB.CpuMemTyping (&NB);
-
- IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", NB.Node);
- //
- // Call Technology Specific Training routine
- //
- NB.TrainingFlow (&NB);
- //
- // Copy training data to ReturnData buffer
- //
- LibAmdMemCopy ( BufferPtr,
- MCTPtr->DctData[0].ChData[0].RcvEnDlys,
- ((DctCount * ChannelCount) * (
- (RowCount * ColumnCount * NUMBER_OF_DELAY_TABLES) +
- (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES)
- )
- ),
- StdHeader);
-
- HeapDeallocateBuffer (AMD_MEM_DATA_HANDLE, StdHeader);
- //
- // Restore pointers
- //
- for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) {
- for (Channel = 0; Channel < MCTPtr->DctData[Dct].ChannelCount; Channel++) {
- MCTPtr->DctData[Dct].ChData[Channel].MCTPtr = &EnvPtr->DieStruct;
- MCTPtr->DctData[Dct].ChData[Channel].DCTPtr = &EnvPtr->DieStruct.DctData[Dct];
-
- MCTPtr->DctData[Dct].ChData[Channel].RcvEnDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RcvEnDlys;
- MCTPtr->DctData[Dct].ChData[Channel].WrDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDqsDlys;
- MCTPtr->DctData[Dct].ChData[Channel].RdDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsDlys;
- MCTPtr->DctData[Dct].ChData[Channel].WrDatDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatDlys;
- MCTPtr->DctData[Dct].ChData[Channel].RdDqsMinDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsMinDlys;
- MCTPtr->DctData[Dct].ChData[Channel].RdDqsMaxDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsMaxDlys;
- MCTPtr->DctData[Dct].ChData[Channel].WrDatMinDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatMinDlys;
- MCTPtr->DctData[Dct].ChData[Channel].WrDatMaxDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatMaxDlys;
- MCTPtr->DctData[Dct].ChData[Channel].FailingBitMask = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].FailingBitMask;
- }
- MCTPtr->DctData[Dct].ChData = EnvPtr->DieStruct.DctData[Dct].ChData;
- }
- MCTPtr->DctData = EnvPtr->DieStruct.DctData;
- }
-
- //
- // Signal to BSP that training is complete and Send Results
- //
- ASSERT (ReturnData.DataPtr != NULL);
- ApUtilTransmitBuffer (EnvPtr->BspSocket, EnvPtr->BspCore, &ReturnData, StdHeader);
-
- //
- // Clean up and exit.
- //
- HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, 0, 0, 0), StdHeader);
- } else {
- MCTPtr = &EnvPtr->DieStruct;
- PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA, MCTPtr->NodeId, 0, 0, 0, StdHeader);
- SetMemError (AGESA_FATAL, MCTPtr);
- ASSERT(FALSE); // Could not allocate heap for buffer for parallel training data
- }
- return TRUE;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Feat/PARTRN/mfStandardTraining.c b/src/vendorcode/amd/agesa/Proc/Mem/Feat/PARTRN/mfStandardTraining.c
deleted file mode 100644
index 9e64bcf..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Feat/PARTRN/mfStandardTraining.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mfStandardTraining.c
- *
- * This is the standard training routine which performs all training from the BSP
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Feat/PARTRN)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-
-
-#include "AGESA.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "Ids.h"
-#include "mfStandardTraining.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_FEAT_PARTRN_MFSTANDARDTRAINING_FILECODE
-/*-----------------------------------------------------------------------------
-* EXPORTED FUNCTIONS
-*
-*-----------------------------------------------------------------------------
-*/
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This is the main function to perform memory training on all nodes from
- * the BSP only.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - This feature is enabled.
- * @return FALSE - This feature is not enabled.
- */
-BOOLEAN
-MemFStandardTraining (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- ASSERT (NBPtr != NULL);
-
- NBPtr->TrainingFlow (NBPtr);
- return TRUE;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Feat/S3/mfs3.c b/src/vendorcode/amd/agesa/Proc/Mem/Feat/S3/mfs3.c
deleted file mode 100644
index b51db06..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Feat/S3/mfs3.c
+++ /dev/null
@@ -1,714 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mfs3.c
- *
- * Main S3 resume memory Entrypoint file
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/FEAT/S3)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "mport.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "S3.h"
-#include "mfs3.h"
-#include "heapManager.h"
-#include "amdlib.h"
-#include "GeneralServices.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_FEAT_S3_MFS3_FILECODE
-
-extern MEM_NB_SUPPORT memNBInstalled[];
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function is the main memory entry point for the S3 resume sequence
- * Requirements:
- *
- * Run-Time Requirements:
- * 1. Complete Hypertransport Bus Configuration
- * 4. BSP in Big Real Mode
- * 5. Stack available
- *
- * @param[in] *StdHeader - Config handle for library and services
- *
- * @return AGESA_STATUS
- * - AGESA_ALERT
- * - AGESA_FATAL
- * - AGESA_SUCCESS
- * - AGESA_WARNING
- */
-AGESA_STATUS
-AmdMemS3Resume (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_STATUS RetVal;
- MEM_MAIN_DATA_BLOCK mmData;
- S3_MEM_NB_BLOCK *S3NBPtr;
- MEM_DATA_STRUCT *MemData;
- UINT8 Die;
- UINT8 DieCount;
-
- //---------------------------------------------
- // Creation of NB Block for S3 resume
- //---------------------------------------------
- RetVal = MemS3InitNB (&S3NBPtr, &MemData, &mmData, StdHeader);
- if (RetVal == AGESA_FATAL) {
- return RetVal;
- }
- DieCount = mmData.DieCount;
-
- //---------------------------------------------
- //1. Errata Before resume sequence
- //2. S3 Resume sequence
- //3. Errata After resume sequence
- //---------------------------------------------
- for (Die = 0; Die < DieCount; Die ++) {
- if (!S3NBPtr[Die].MemS3Resume (&S3NBPtr[Die], Die)) {
- return AGESA_FATAL;
- }
- S3NBPtr[Die].MemS3RestoreScrub (S3NBPtr[Die].NBPtr, Die);
- }
-
- HeapDeallocateBuffer (AMD_MEM_S3_DATA_HANDLE, StdHeader);
- return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function deallocates heap space allocated in memory S3 resume.
- *
- * @param[in] *StdHeader - Config handle for library and services
- *
- * @return AGESA_STATUS
- * - AGESA_ALERT
- * - AGESA_FATAL
- * - AGESA_SUCCESS
- * - AGESA_WARNING
- */
-AGESA_STATUS
-MemS3Deallocate (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_STATUS RetVal;
- AGESA_STATUS tempRetVal;
-
- RetVal = AGESA_SUCCESS;
- tempRetVal = HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_DIE_STRUCT_HANDLE, 0, 0, 0), StdHeader);
- if (tempRetVal > RetVal) {
- RetVal = tempRetVal;
- }
- tempRetVal = HeapDeallocateBuffer (AMD_MEM_AUTO_HANDLE, StdHeader);
- if (tempRetVal > RetVal) {
- RetVal = tempRetVal;
- }
- RetVal = HeapDeallocateBuffer (AMD_MEM_S3_NB_HANDLE, StdHeader);
- if (tempRetVal > RetVal) {
- RetVal = tempRetVal;
- }
- RetVal = HeapDeallocateBuffer (AMD_MEM_DATA_HANDLE, StdHeader);
- if (tempRetVal > RetVal) {
- RetVal = tempRetVal;
- }
- return RetVal;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function is the entrance to get device list for memory registers.
- *
- * @param[in, out] **DeviceBlockHdrPtr - Pointer to the memory containing the
- * device descriptor list
- * @param[in] *StdHeader - Config handle for library and services
- * @return AGESA_STATUS
- * - AGESA_ALERT
- * - AGESA_FATAL
- * - AGESA_SUCCESS
- * - AGESA_WARNING
- */
-AGESA_STATUS
-MemFS3GetDeviceList (
- IN OUT DEVICE_BLOCK_HEADER **DeviceBlockHdrPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 i;
- UINT16 BufferSize;
- UINT64 BufferOffset;
- S3_MEM_NB_BLOCK *S3NBPtr;
- MEM_DATA_STRUCT *MemData;
- MEM_MAIN_DATA_BLOCK mmData;
- UINT8 Die;
- UINT8 DieCount;
- AGESA_STATUS RetVal;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
- DESCRIPTOR_GROUP DeviceDescript[MAX_NODES_SUPPORTED];
- BufferSize = 0;
-
- //---------------------------------------------
- // Creation of NB Block for S3 resume
- //---------------------------------------------
- RetVal = MemS3InitNB (&S3NBPtr, &MemData, &mmData, StdHeader);
- if (RetVal == AGESA_FATAL) {
- return RetVal;
- }
- DieCount = mmData.DieCount;
-
- // Get the mask bit and the register list for node that presents
- for (Die = 0; Die < DieCount; Die ++) {
- S3NBPtr->MemS3GetConPCIMask (S3NBPtr[Die].NBPtr, (VOID *)&DeviceDescript[Die]);
- S3NBPtr->MemS3GetConMSRMask (S3NBPtr[Die].NBPtr, (VOID *)&DeviceDescript[Die]);
- BufferSize = BufferSize + S3NBPtr->MemS3GetRegLstPtr (S3NBPtr[Die].NBPtr, (VOID *)&DeviceDescript[Die]);
- }
-
- // Base on the size of the device list, apply for a buffer for it.
- AllocHeapParams.RequestedBufferSize = BufferSize + sizeof (DEVICE_BLOCK_HEADER);
- AllocHeapParams.BufferHandle = AMD_S3_NB_INFO_BUFFER_HANDLE;
- AGESA_TESTPOINT (TpIfBeforeAllocateMemoryS3SaveBuffer, StdHeader);
- if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) != AGESA_SUCCESS) {
- return AGESA_FATAL;
- }
- AGESA_TESTPOINT (TpIfAfterAllocateMemoryS3SaveBuffer, StdHeader);
-
- *DeviceBlockHdrPtr = (DEVICE_BLOCK_HEADER *) AllocHeapParams.BufferPtr;
- (*DeviceBlockHdrPtr)->RelativeOrMaskOffset = (UINT16) AllocHeapParams.RequestedBufferSize;
-
- // Copy device list on the stack to the heap.
- BufferOffset = sizeof (DEVICE_BLOCK_HEADER) + (UINT64) AllocHeapParams.BufferPtr;
- for (Die = 0; Die < DieCount; Die ++) {
- for (i = PRESELFREF; i <= POSTSELFREF; i ++) {
- // Copy PCI device descriptor to the heap if it exists.
- if (DeviceDescript[Die].PCIDevice[i].RegisterListID != 0xFFFFFFFF) {
- LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (PCI_DEVICE_DESCRIPTOR), StdHeader);
- (*DeviceBlockHdrPtr)->NumDevices ++;
- BufferOffset += sizeof (PCI_DEVICE_DESCRIPTOR);
- }
- // Copy conditional PCI device descriptor to the heap if it exists.
- if (DeviceDescript[Die].CPCIDevice[i].RegisterListID != 0xFFFFFFFF) {
- LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].CPCIDevice[i]), sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR), StdHeader);
- (*DeviceBlockHdrPtr)->NumDevices ++;
- BufferOffset += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR);
- }
- // Copy MSR device descriptor to the heap if it exists.
- if (DeviceDescript[Die].MSRDevice[i].RegisterListID != 0xFFFFFFFF) {
- LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].MSRDevice[i]), sizeof (MSR_DEVICE_DESCRIPTOR), StdHeader);
- (*DeviceBlockHdrPtr)->NumDevices ++;
- BufferOffset += sizeof (MSR_DEVICE_DESCRIPTOR);
- }
- // Copy conditional MSR device descriptor to the heap if it exists.
- if (DeviceDescript[Die].CMSRDevice[i].RegisterListID != 0xFFFFFFFF) {
- LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR), StdHeader);
- (*DeviceBlockHdrPtr)->NumDevices ++;
- BufferOffset += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR);
- }
- }
- }
-
- return RetVal;
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initialize the northbridge block and apply for heap space
- * before any function call is made to memory component during S3 resume.
- *
- * @param[in] *StdHeader - Config handle for library and services
- * @return AGESA_STATUS
- * - AGESA_ALERT
- * - AGESA_FATAL
- * - AGESA_SUCCESS
- * - AGESA_WARNING
- */
-AGESA_STATUS
-MemS3ResumeInitNB (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_STATUS RetVal;
- MEM_MAIN_DATA_BLOCK mmData;
- S3_MEM_NB_BLOCK *S3NBPtr;
- MEM_DATA_STRUCT *MemData;
- UINT8 Die;
- UINT8 DieCount;
- UINT8 SpecialCaseHeapSize;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
- S3_SPECIAL_CASE_HEAP_HEADER SpecialHeapHeader[MAX_NODES_SUPPORTED];
-
- SpecialCaseHeapSize = 0;
-
- //---------------------------------------------
- // Creation of NB Block for S3 resume
- //---------------------------------------------
- RetVal = MemS3InitNB (&S3NBPtr, &MemData, &mmData, StdHeader);
- if (RetVal == AGESA_FATAL) {
- return RetVal;
- }
- DieCount = mmData.DieCount;
-
- //--------------------------------------------------
- // Apply for heap space for special case registers
- //--------------------------------------------------
- for (Die = 0; Die < DieCount; Die ++) {
- // Construct the header for the special case heap.
- SpecialHeapHeader[Die].Node = S3NBPtr[Die].NBPtr->Node;
- SpecialHeapHeader[Die].Offset = SpecialCaseHeapSize + (DieCount * (sizeof (S3_SPECIAL_CASE_HEAP_HEADER)));
- SpecialCaseHeapSize = SpecialCaseHeapSize + S3NBPtr->MemS3SpecialCaseHeapSize;
- }
- AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (S3_SPECIAL_CASE_HEAP_HEADER))) + SpecialCaseHeapSize;
- AllocHeapParams.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
- AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
- if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) != AGESA_SUCCESS) {
- PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS, S3NBPtr[Die].NBPtr->Node, 0, 0, 0, StdHeader);
- SetMemError (AGESA_FATAL, S3NBPtr[Die].NBPtr->MCTPtr);
- ASSERT(FALSE); // Could not allocate heap space for "S3_SPECIAL_CASE_HEAP_HEADER"
- return AGESA_FATAL;
- }
- LibAmdMemCopy ((VOID *) AllocHeapParams.BufferPtr, (VOID *) SpecialHeapHeader, (sizeof (S3_SPECIAL_CASE_HEAP_HEADER) * DieCount), StdHeader);
- return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function returns the PCI device register list according to the register
- * list ID.
- *
- * @param[in] *Device - pointer to the PCI_DEVICE_DESCRIPTOR
- * @param[out] **RegisterHdr - pointer to the address of the register list
- * @param[in] *StdHeader - Config handle for library and services
- *
- * @return AGESA_STATUS
- * - AGESA_ALERT
- * - AGESA_FATAL
- * - AGESA_SUCCESS
- * - AGESA_WARNING
- */
-AGESA_STATUS
-MemFS3GetPciDeviceRegisterList (
- IN PCI_DEVICE_DESCRIPTOR *Device,
- OUT PCI_REGISTER_BLOCK_HEADER **RegisterHdr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_STATUS RetVal;
- S3_MEM_NB_BLOCK *S3NBPtr;
- VOID *RegisterHeader;
- LOCATE_HEAP_PTR LocHeap;
- AGESA_BUFFER_PARAMS LocBufferParams;
- LocHeap.BufferHandle = AMD_MEM_S3_NB_HANDLE;
-
- LibAmdMemCopy (&LocBufferParams.StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);
- LocBufferParams.BufferHandle = AMD_MEM_S3_NB_HANDLE;
-
- AGESA_TESTPOINT (TpIfBeforeLocateS3PciBuffer, StdHeader);
- if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) {
- S3NBPtr = (S3_MEM_NB_BLOCK *)LocHeap.BufferPtr;
- } else {
- ASSERT(FALSE) ; // No match for heap status, but could not locate "AMD_MEM_S3_NB_HANDLE" in heap for S3GetMsr
- return AGESA_FATAL;
- }
- AGESA_TESTPOINT (TpIfAfterLocateS3PciBuffer, StdHeader);
-
- // NB block has already been constructed by main block.
- // No need to construct it here.
- RetVal = S3NBPtr[Device->Node].MemS3GetDeviceRegLst (Device->RegisterListID, &RegisterHeader);
- *RegisterHdr = (PCI_REGISTER_BLOCK_HEADER *)RegisterHeader;
- return RetVal;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function returns the conditional PCI device register list according
- * to the register list ID.
- *
- * @param[in] *Device - pointer to the CONDITIONAL_PCI_DEVICE_DESCRIPTOR
- * @param[out] **RegisterHdr - pointer to the address of the register list
- * @param[in] *StdHeader - Config handle for library and services
- *
- * @return AGESA_STATUS
- * - AGESA_ALERT
- * - AGESA_FATAL
- * - AGESA_SUCCESS
- * - AGESA_WARNING
- */
-AGESA_STATUS
-MemFS3GetCPciDeviceRegisterList (
- IN CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device,
- OUT CPCI_REGISTER_BLOCK_HEADER **RegisterHdr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_STATUS RetVal;
- S3_MEM_NB_BLOCK *S3NBPtr;
- VOID *RegisterHeader;
- LOCATE_HEAP_PTR LocHeap;
- AGESA_BUFFER_PARAMS LocBufferParams;
-
- LibAmdMemCopy (&LocBufferParams.StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);
- LocHeap.BufferHandle = AMD_MEM_S3_NB_HANDLE;
- LocBufferParams.BufferHandle = AMD_MEM_S3_NB_HANDLE;
-
- AGESA_TESTPOINT (TpIfBeforeLocateS3CPciBuffer, StdHeader);
- if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) {
- S3NBPtr = (S3_MEM_NB_BLOCK *)LocHeap.BufferPtr;
- } else {
- ASSERT(FALSE) ; // No match for heap status, but could not locate "AMD_MEM_S3_NB_HANDLE" in heap for S3GetMsr
- return AGESA_FATAL;
- }
- AGESA_TESTPOINT (TpIfAfterLocateS3CPciBuffer, StdHeader);
-
- // NB block has already been constructed by main block.
- // No need to construct it here.
- RetVal = S3NBPtr[Device->Node].MemS3GetDeviceRegLst (Device->RegisterListID, &RegisterHeader);
- *RegisterHdr = (CPCI_REGISTER_BLOCK_HEADER *)RegisterHeader;
- return RetVal;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function returns the MSR device register list according to the register
- * list ID.
- *
- * @param[in] *Device - pointer to the MSR_DEVICE_DESCRIPTOR
- * @param[out] **RegisterHdr - pointer to the address of the register list
- * @param[in] *StdHeader - Config handle for library and services
- *
- * @return AGESA_STATUS
- * - AGESA_ALERT
- * - AGESA_FATAL
- * - AGESA_SUCCESS
- * - AGESA_WARNING
- */
-AGESA_STATUS
-MemFS3GetMsrDeviceRegisterList (
- IN MSR_DEVICE_DESCRIPTOR *Device,
- OUT MSR_REGISTER_BLOCK_HEADER **RegisterHdr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_STATUS RetVal;
- S3_MEM_NB_BLOCK *S3NBPtr;
- VOID *RegisterHeader;
- LOCATE_HEAP_PTR LocHeap;
- AGESA_BUFFER_PARAMS LocBufferParams;
-
- LibAmdMemCopy (&LocBufferParams.StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);
- LocHeap.BufferHandle = AMD_MEM_S3_NB_HANDLE;
- LocBufferParams.BufferHandle = AMD_MEM_S3_NB_HANDLE;
-
- AGESA_TESTPOINT (TpIfBeforeLocateS3MsrBuffer, StdHeader);
- if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) {
- S3NBPtr = (S3_MEM_NB_BLOCK *)LocHeap.BufferPtr;
- } else {
- ASSERT(FALSE) ; // No match for heap status, but could not locate "AMD_MEM_S3_NB_HANDLE" in heap for S3GetMsr
- return AGESA_FATAL;
- }
- AGESA_TESTPOINT (TpIfAfterLocateS3MsrBuffer, StdHeader);
-
- // NB block has already been constructed by main block.
- // No need to construct it here.
- RetVal = S3NBPtr[BSP_DIE].MemS3GetDeviceRegLst (Device->RegisterListID, &RegisterHeader);
- *RegisterHdr = (MSR_REGISTER_BLOCK_HEADER *)RegisterHeader;
- return RetVal;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function returns the conditional MSR device register list according
- * to the register list ID.
- *
- * @param[in] *Device - pointer to the CONDITIONAL_PCI_DEVICE_DESCRIPTOR
- * @param[out] **RegisterHdr - pointer to the address of the register list
- * @param[in] *StdHeader - Config handle for library and services
- *
- * @return AGESA_STATUS
- * - AGESA_ALERT
- * - AGESA_FATAL
- * - AGESA_SUCCESS
- * - AGESA_WARNING
- */
-AGESA_STATUS
-MemFS3GetCMsrDeviceRegisterList (
- IN CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device,
- OUT CMSR_REGISTER_BLOCK_HEADER **RegisterHdr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AGESA_STATUS RetVal;
- S3_MEM_NB_BLOCK *S3NBPtr;
- VOID *RegisterHeader;
- LOCATE_HEAP_PTR LocHeap;
- AGESA_BUFFER_PARAMS LocBufferParams;
-
- LibAmdMemCopy (&LocBufferParams.StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);
- LocHeap.BufferHandle = AMD_MEM_S3_NB_HANDLE;
- LocBufferParams.BufferHandle = AMD_MEM_S3_NB_HANDLE;
-
-
- AGESA_TESTPOINT (TpIfBeforeLocateS3CMsrBuffer, StdHeader);
- if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) {
- S3NBPtr = (S3_MEM_NB_BLOCK *)LocHeap.BufferPtr;
- } else {
- ASSERT(FALSE) ; // No match for heap status, but could not locate "AMD_MEM_S3_NB_HANDLE" in heap for S3GetMsr
- return AGESA_FATAL;
- }
- AGESA_TESTPOINT (TpIfAfterLocateS3CMsrBuffer, StdHeader);
-
- // NB block has already been constructed by main block.
- // No need to construct it here.
- RetVal = S3NBPtr[BSP_DIE].MemS3GetDeviceRegLst (Device->RegisterListID, &RegisterHeader);
- *RegisterHdr = (CMSR_REGISTER_BLOCK_HEADER *)RegisterHeader;
- return RetVal;
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initialize needed data structures for S3 resume.
- *
- * @param[in, out] **S3NBPtr - Pointer to the pointer of northbridge block.
- * @param[in, out] *MemPtr - Pointer to MEM_DATA_STRUCT.
- * @param[in, out] *mmData - Pointer to MEM_MAIN_DATA_BLOCK.
- * @param[in] *StdHeader - Config handle for library and services.
- *
- * @return AGESA_STATUS
- * - AGESA_ALERT
- * - AGESA_FATAL
- * - AGESA_SUCCESS
- * - AGESA_WARNING
- */
-AGESA_STATUS
-MemS3InitNB (
- IN OUT S3_MEM_NB_BLOCK **S3NBPtr,
- IN OUT MEM_DATA_STRUCT **MemPtr,
- IN OUT MEM_MAIN_DATA_BLOCK *mmData,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 i;
- AGESA_STATUS RetVal;
- LOCATE_HEAP_PTR LocHeap;
- MEM_NB_BLOCK *NBPtr;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
- UINT8 Die;
- UINT8 DieCount;
- BOOLEAN SkipScan;
-
- SkipScan = FALSE;
- LocHeap.BufferHandle = AMD_MEM_DATA_HANDLE;
- if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) {
- // NB block has already been constructed by main block.
- // No need to construct it here.
- *MemPtr = (MEM_DATA_STRUCT *)LocHeap.BufferPtr;
- SkipScan = TRUE;
- } else {
- AllocHeapParams.RequestedBufferSize = sizeof (MEM_DATA_STRUCT);
- AllocHeapParams.BufferHandle = AMD_MEM_DATA_HANDLE;
- AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
- if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) != AGESA_SUCCESS) {
- ASSERT(FALSE); // Allocate failed for MEM_DATA_STRUCT
- return AGESA_FATAL;
- }
- *MemPtr = (MEM_DATA_STRUCT *)AllocHeapParams.BufferPtr;
- }
- LibAmdMemCopy (&(*MemPtr)->StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);
- mmData->MemPtr = *MemPtr;
-
- if (!SkipScan) {
- RetVal = MemSocketScan (mmData);
- if (RetVal == AGESA_FATAL) {
- return RetVal;
- }
- } else {
- // We already have initialize data block, no need to do it again.
- mmData->DieCount = mmData->MemPtr->DieCount;
- }
- DieCount = mmData->DieCount;
-
- //---------------------------------------------
- // Creation of NB Block for S3 resume
- //---------------------------------------------
- // Search for AMD_MEM_AUTO_HANDLE on the heap first.
- // Only apply for space on the heap if cannot find AMD_MEM_AUTO_HANDLE on the heap.
- LocHeap.BufferHandle = AMD_MEM_S3_NB_HANDLE;
- if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) {
- // NB block has already been constructed by main block.
- // No need to construct it here.
- *S3NBPtr = (S3_MEM_NB_BLOCK *)LocHeap.BufferPtr;
- } else {
- AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (S3_MEM_NB_BLOCK)));
- AllocHeapParams.BufferHandle = AMD_MEM_S3_NB_HANDLE;
- AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
- if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) != AGESA_SUCCESS) {
- ASSERT(FALSE); // Could not allocate space for "S3_MEM_NB_BLOCK"
- return AGESA_FATAL;
- }
- *S3NBPtr = (S3_MEM_NB_BLOCK *)AllocHeapParams.BufferPtr;
-
- LocHeap.BufferHandle = AMD_MEM_AUTO_HANDLE;
- if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) {
- // NB block has already been constructed by main block.
- // No need to construct it here.
- NBPtr = (MEM_NB_BLOCK *)LocHeap.BufferPtr;
- } else {
- AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (MEM_NB_BLOCK)));
- AllocHeapParams.BufferHandle = AMD_MEM_AUTO_HANDLE;
- AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
- if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) != AGESA_SUCCESS) {
- ASSERT(FALSE); // Allocate failed for "MEM_NB_BLOCK"
- return AGESA_FATAL;
- }
- NBPtr = (MEM_NB_BLOCK *)AllocHeapParams.BufferPtr;
- }
- // Construct each die.
- for (Die = 0; Die < DieCount; Die ++) {
- i = 0;
- ((*S3NBPtr)[Die]).NBPtr = &NBPtr[Die];
- while (memNBInstalled[i].MemS3ResumeConstructNBBlock != 0) {
- if (memNBInstalled[i].MemS3ResumeConstructNBBlock ((VOID *)&((*S3NBPtr)[Die]), *MemPtr, Die)) {
- break;
- }
- i++;
- };
- if (memNBInstalled[i].MemS3ResumeConstructNBBlock == 0) {
- ASSERT(FALSE); // S3 resume NB constructor not found
- return AGESA_FATAL;
- }
- }
- }
- return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Waits specified number of 10ns cycles
- * @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE
- * @param[in] Count - Number of 10ns cycles to wait
- *
- * ----------------------------------------------------------------------------
- */
-
-VOID
-MemFS3Wait10ns (
- IN UINT32 Count,
- IN OUT MEM_DATA_STRUCT *MemPtr
- )
-{
- UINT32 TscRate;
- UINT64 TargetTsc;
- UINT64 CurrentTsc;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
-
- ASSERT (Count <= 1000000);
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, &MemPtr->StdHeader);
- FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRate, &MemPtr->StdHeader);
-
- LibAmdMsrRead (TSC, &CurrentTsc, &MemPtr->StdHeader);
- TargetTsc = CurrentTsc + ((Count * TscRate + 99) / 100);
- do {
- LibAmdMsrRead (TSC, &CurrentTsc, &MemPtr->StdHeader);
- } while (CurrentTsc < TargetTsc);
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Feat/TABLE/mftds.c b/src/vendorcode/amd/agesa/Proc/Mem/Feat/TABLE/mftds.c
deleted file mode 100644
index 89df264..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Feat/TABLE/mftds.c
+++ /dev/null
@@ -1,324 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mftds.c
- *
- * Northbridge table drive support file for DR
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Feat/TABLE)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mftds.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_FEAT_TABLE_MFTDS_FILECODE
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-#define MAX_BYTELANES_PER_CHANNEL (8 + 1) ///< Max Bytelanes per channel
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-VOID
-SetTableValues (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN MEM_TABLE_ALIAS MTPtr
- );
-
-VOID
-SetTableValuesLoop (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN MEM_TABLE_ALIAS *MTPtr,
- IN UINT8 time
- );
-
-/*-----------------------------------------------------------------------------
- *
- * This function initializes bit field translation table
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_TABLE_ALIAS structure
- * @param[in] time - Indicate the timing for the register which is written.
- *
- * @return None
- * ----------------------------------------------------------------------------
- */
-VOID
-MemFInitTableDrive (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 time
- )
-{
- MEM_TABLE_ALIAS *MTPtr;
- MEM_TABLE_ALIAS *IdsMTPtr;
-
- ASSERT (NBPtr != NULL);
- IdsMTPtr = NULL;
-
- MTPtr = (MEM_TABLE_ALIAS *) NBPtr->RefPtr->TableBasedAlterations;
-
- IDS_SKIP_HOOK (IDS_GET_DRAM_TABLE, &IdsMTPtr, &(NBPtr->MemPtr->StdHeader)) {
- IDS_OPTION_HOOK (IDS_INIT_DRAM_TABLE, NBPtr, &(NBPtr->MemPtr->StdHeader));
- IDS_OPTION_HOOK (IDS_GET_DRAM_TABLE, &IdsMTPtr, &(NBPtr->MemPtr->StdHeader));
- }
-
- SetTableValuesLoop (NBPtr, MTPtr, time);
- SetTableValuesLoop (NBPtr, IdsMTPtr, time);
-}
-
-/*-----------------------------------------------------------------------------
- *
- * This function initializes bit field translation table
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *MTPtr - Pointer to the MEM_TABLE_ALIAS structure
- * @param[in] time - Indicate the timing for the register which is written.
- *
- * @return None
- * ----------------------------------------------------------------------------
- */
-VOID
-SetTableValuesLoop (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN MEM_TABLE_ALIAS *MTPtr,
- IN UINT8 time
- )
-{
- UINT8 i;
- UINT8 CurDct;
-
- if (MTPtr != NULL) {
- CurDct = NBPtr->Dct;
- for (i = 0; MTPtr[i].time != MTEnd; i++) {
- if ((MTPtr[i].attr != MTAuto) && (MTPtr[i].time == time)) {
- SetTableValues (NBPtr, MTPtr[i]);
- }
- }
- NBPtr->SwitchDCT (NBPtr, CurDct);
- }
-}
-
-/*-----------------------------------------------------------------------------
- *
- * Engine for setting Table Value.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] MTPtr - Pointer to the MEM_TABLE_ALIAS structure
- *
- * @return None
- * ----------------------------------------------------------------------------
- */
-VOID
-SetTableValues (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN MEM_TABLE_ALIAS MTPtr
- )
-{
- UINT8 AccessType;
- UINT16 ByteLane;
- UINT8 Dct;
- UINT8 i;
- UINT8 j;
- UINT32 TempVal[36];
- UINT8 *DqsSavePtr;
- UINT8 DqsOffset;
- BOOLEAN SaveDqs;
-
- AccessType = 0;
- DqsSavePtr = NULL;
- SaveDqs = TRUE;
-
- ASSERT (MTPtr.time <= MTValidTimePointLimit);
- ASSERT (MTPtr.attr <= MTAdd);
- ASSERT (MTPtr.node <= MTNodes);
- ASSERT (MTPtr.dct <= MTDcts);
- ASSERT (MTPtr.dimm <= MTDIMMs);
- ASSERT (MTPtr.data.s.bytelane <= MTBLs);
-
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- if ((MTPtr.dct == MTDcts) || (MTPtr.dct == Dct)) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- switch (MTPtr.bfindex) {
- case BFRcvEnDly:
- AccessType = AccessRcvEnDly;
- DqsSavePtr = NULL;
- break;
- case BFWrDatDly:
- AccessType = AccessWrDatDly;
- DqsSavePtr = NBPtr->ChannelPtr->WrDatDlys;
- break;
- case BFRdDqsDly:
- AccessType = AccessRdDqsDly;
- DqsSavePtr = NBPtr->ChannelPtr->RdDqsDlys;
- break;
- case BFWrDqsDly:
- AccessType = AccessWrDqsDly;
- DqsSavePtr = NBPtr->ChannelPtr->WrDqsDlys;
- break;
- case BFPhRecDly:
- AccessType = AccessPhRecDly;
- SaveDqs = FALSE;
- break;
- default:
- AccessType = 0xFF;
- break;
- }
- if (AccessType == 0xFF) {
- if (MTPtr.attr == MTOverride) {
- NBPtr->SetBitField (NBPtr, MTPtr.bfindex, MTPtr.data.s.value);
- }
- if (MTPtr.attr == MTSubtract) {
- NBPtr->SetBitField (NBPtr, MTPtr.bfindex, NBPtr->GetBitField (NBPtr, MTPtr.bfindex) - MTPtr.data.s.value);
- }
- if (MTPtr.attr == MTAdd) {
- NBPtr->SetBitField (NBPtr, MTPtr.bfindex, NBPtr->GetBitField (NBPtr, MTPtr.bfindex) + MTPtr.data.s.value);
- }
- } else {
- // Store the DQS data first
- for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) {
- for (j = 0; j < MAX_BYTELANES_PER_CHANNEL; j++) {
- TempVal[i * MAX_BYTELANES_PER_CHANNEL + j] = NBPtr->GetTrainDly (NBPtr, AccessType, DIMM_BYTE_ACCESS (i, j));
- }
- }
- //
- // Single Value with Bytleane mask option
- // Indicated by the vtype flag
- //
- if (MTPtr.vtype == VT_MSK_VALUE) {
- // set the value which defined in Memory table.
- ByteLane = MTPtr.data.s.bytelane;
- for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) {
- if ((MTPtr.dimm == MTDIMMs) || (MTPtr.dimm == i)) {
- for (j = 0; j < MAX_BYTELANES_PER_CHANNEL; j++) {
- DqsOffset = (i * MAX_BYTELANES_PER_CHANNEL + j);
- if ((ByteLane & (UINT16)1) != 0) {
- if (MTPtr.attr == MTOverride) {
- TempVal[DqsOffset] = (UINT16)MTPtr.data.s.value;
- }
- if (MTPtr.attr == MTSubtract) {
- TempVal[DqsOffset] -= (UINT16)MTPtr.data.s.value;
- }
- if (MTPtr.attr == MTAdd) {
- TempVal[DqsOffset] += (UINT16)MTPtr.data.s.value;
- }
- NBPtr->SetTrainDly (NBPtr, AccessType, DIMM_BYTE_ACCESS (i, j), (UINT16)TempVal[DqsOffset]);
- if (SaveDqs) {
- if (DqsSavePtr == NULL) {
- NBPtr->ChannelPtr->RcvEnDlys[DqsOffset] = (UINT16)TempVal[DqsOffset];
- } else {
- DqsSavePtr[DqsOffset] = (UINT8)TempVal[DqsOffset];
- }
- }
- }
- ByteLane = ByteLane >> (UINT16)1;
- }
- }
- }
- } else {
- // Multiple values specified in a byte array
- for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) {
- if ((MTPtr.dimm == MTDIMMs) || (MTPtr.dimm == i)) {
- for (j = 0; j < MAX_BYTELANES_PER_CHANNEL; j++) {
- DqsOffset = (i * MAX_BYTELANES_PER_CHANNEL + j);
- if (MTPtr.attr == MTOverride) {
- TempVal[DqsOffset] = MTPtr.data.bytelanevalue[j];
- }
- if (MTPtr.attr == MTSubtract) {
- TempVal[DqsOffset] -= MTPtr.data.bytelanevalue[j];
- }
- if (MTPtr.attr == MTAdd) {
- TempVal[DqsOffset] += MTPtr.data.bytelanevalue[j];
- }
- NBPtr->SetTrainDly (NBPtr, AccessType, DIMM_BYTE_ACCESS (i, j), (UINT16)TempVal[DqsOffset]);
- if (SaveDqs) {
- if (DqsSavePtr == NULL) {
- NBPtr->ChannelPtr->RcvEnDlys[DqsOffset] = (UINT16)TempVal[DqsOffset];
- } else {
- DqsSavePtr[DqsOffset] = (UINT8)TempVal[DqsOffset];
- }
- }
- }
- }
- }
- }
- // set the DQS value to left DIMMs.
- i = MTPtr.dimm;
- while ((i != MTDIMMs) && ((++i) < MAX_DIMMS_PER_CHANNEL)) {
- for (j = 0; j < MAX_BYTELANES_PER_CHANNEL; j++) {
- NBPtr->SetTrainDly (NBPtr, AccessType, DIMM_BYTE_ACCESS (i, j), (UINT16)TempVal[i * MAX_BYTELANES_PER_CHANNEL + j]);
- }
- }
- }
- }
- }
-}
-
-
-
-
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Main/C32/mmflowC32.c b/src/vendorcode/amd/agesa/Proc/Mem/Main/C32/mmflowC32.c
deleted file mode 100644
index 4e18e52..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Main/C32/mmflowC32.c
+++ /dev/null
@@ -1,372 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mmflowC32.c
- *
- * Main Memory initialization sequence for C32
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Main/C32)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mnc32.h"
-#include "mt.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-#include "GeneralServices.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_MAIN_C32_MMFLOWC32_FILECODE
-/* features */
-#include "mftds.h"
-
-extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function defines the memory initialization flow for
- * systems that only support C32 processors.
- *
- * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK
- *
- * @return AGESA_STATUS
- * - AGESA_ALERT
- * - AGESA_FATAL
- * - AGESA_SUCCESS
- * - AGESA_WARNING
- */
-AGESA_STATUS
-MemMFlowC32 (
- IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
- )
-{
- UINT8 Node;
- UINT8 NodeCnt;
- MEM_NB_BLOCK *NBPtr;
- MEM_TECH_BLOCK *TechPtr;
- MEM_DATA_STRUCT *MemPtr;
-
- NBPtr = MemMainPtr->NBPtr;
- TechPtr = MemMainPtr->TechPtr;
- NodeCnt = MemMainPtr->DieCount;
- MemPtr = MemMainPtr->MemPtr;
-
- GetLogicalIdOfSocket (MemPtr->DiesPerSystem[BSP_DIE].SocketId, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid), &(MemPtr->StdHeader));
- if (!MemNIsIdSupportedC32 (NBPtr, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid))) {
- MemPtr->IsFlowControlSupported = FALSE;
- return AGESA_FATAL;
- } else {
- MemPtr->IsFlowControlSupported = TRUE;
- }
-
- //----------------------------------------------------------------
- // Initialize MCT
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemInitializeMCT, &(MemMainPtr->MemPtr->StdHeader));
- for (Node = 0; Node < NodeCnt; Node++) {
- if (!NBPtr[Node].InitializeMCT (&NBPtr[Node])) {
- return AGESA_FATAL;
- }
- }
-
- //----------------------------------------------------------------
- // Low voltage DDR3
- //----------------------------------------------------------------
- // Levelize DDR3 voltage based on socket, as each socket has its own voltage for dimms.
- AGESA_TESTPOINT (TpProcMemLvDdr3, &(MemMainPtr->MemPtr->StdHeader));
- if (!MemFeatMain.LvDDR3 (MemMainPtr)) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Initialize DRAM and DCTs, and Create Memory Map
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemInitMCT, &(MemMainPtr->MemPtr->StdHeader));
- for (Node = 0; Node < NodeCnt; Node++) {
- // Initialize Memory Controller and Dram
- IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Node);
- if (!NBPtr[Node].InitMCT (&NBPtr[Node])) {
- return AGESA_FATAL; //fatalexit
- }
-
- // Create memory map
- AGESA_TESTPOINT (TpProcMemSystemMemoryMapping, &(MemMainPtr->MemPtr->StdHeader));
- if (!NBPtr[Node].HtMemMapInit (&NBPtr[Node])) {
- return AGESA_FATAL;
- }
- }
-
- //----------------------------------------------------
- // If there is no dimm on the system, do fatal exit
- //----------------------------------------------------
- if (NBPtr[BSP_DIE].RefPtr->SysLimit == 0) {
- PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader));
- ASSERT (FALSE);
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Synchronize DCTs
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemSynchronizeDcts, &(MemMainPtr->MemPtr->StdHeader));
- for (Node = 0; Node < NodeCnt; Node++) {
- if (!NBPtr[Node].SyncDctsReady (&NBPtr[Node])) {
- return AGESA_FATAL;
- }
- }
-
- //----------------------------------------------------------------
- // CpuMemTyping
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemMtrrConfiguration, &(MemMainPtr->MemPtr->StdHeader));
- if (!NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE])) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Before Training Table values
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- MemFInitTableDrive (&NBPtr[Node], MTBeforeTrn);
- }
-
- //----------------------------------------------------------------
- // Memory Context Restore
- //----------------------------------------------------------------
- if (!MemFeatMain.MemRestore (MemMainPtr)) {
- // Do DQS training only if memory context restore fails
-
- //----------------------------------------------------------------
- // Training
- //----------------------------------------------------------------
- MemMainPtr->mmSharedPtr->DimmExcludeFlag = TRAINING;
- AGESA_TESTPOINT (TpProcMemDramTraining, &(MemMainPtr->MemPtr->StdHeader));
- IDS_SKIP_HOOK (IDS_BEFORE_DQS_TRAINING, MemMainPtr, &(MemMainPtr->MemPtr->StdHeader)) {
- if (!MemFeatMain.Training (MemMainPtr)) {
- return AGESA_FATAL;
- }
- }
- IDS_HDT_CONSOLE (MEM_FLOW, "\nEnd DQS training\n\n");
- }
-
- //----------------------------------------------------------------
- // Disable chipselects that fail training
- //----------------------------------------------------------------
- MemMainPtr->mmSharedPtr->DimmExcludeFlag = END_TRAINING;
- MemFeatMain.ExcludeDIMM (MemMainPtr);
- MemMainPtr->mmSharedPtr->DimmExcludeFlag = NORMAL;
-
- //----------------------------------------------------------------
- // OtherTiming
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemOtherTiming, &(MemMainPtr->MemPtr->StdHeader));
- for (Node = 0; Node < NodeCnt; Node++) {
- if (!NBPtr[Node].OtherTiming (&NBPtr[Node])) {
- return AGESA_FATAL;
- }
- }
-
- //----------------------------------------------------------------
- // After Training Table values
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- MemFInitTableDrive (&NBPtr[Node], MTAfterTrn);
- }
-
- //----------------------------------------------------------------
- // SetDqsEccTimings
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemSetDqsEccTmgs, &(MemMainPtr->MemPtr->StdHeader));
- for (Node = 0; Node < NodeCnt; Node++) {
- if (!TechPtr[Node].SetDqsEccTmgs (&TechPtr[Node])) {
- return AGESA_FATAL;
- }
- }
-
- //----------------------------------------------------------------
- // Online Spare
- //----------------------------------------------------------------
- if (!MemFeatMain.OnlineSpare (MemMainPtr)) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Interleave banks
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- if (NBPtr[Node].FeatPtr->InterleaveBanks (&NBPtr[Node])) {
- if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
- return AGESA_FATAL;
- }
- }
- }
-
- //----------------------------------------------------------------
- // Interleave Nodes
- //----------------------------------------------------------------
- if (!MemFeatMain.InterleaveNodes (MemMainPtr)) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Interleave channels
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- if (NBPtr[Node].FeatPtr->InterleaveChannels (&NBPtr[Node])) {
- if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
- return AGESA_FATAL;
- }
- }
- }
-
- //----------------------------------------------------------------
- // After Programming Interleave registers
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- MemFInitTableDrive (&NBPtr[Node], MTAfterInterleave);
- }
-
- //----------------------------------------------------------------
- // UMA Allocation & UMAMemTyping
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemUMAMemTyping, &(MemMainPtr->MemPtr->StdHeader));
- if (!MemFeatMain.UmaAllocation (MemMainPtr)) {
- return AGESA_FATAL;
- }
-
- // ECC
- //----------------------------------------------------------------
- if (!MemFeatMain.InitEcc (MemMainPtr)) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Memory Clear
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemMemClr, &(MemMainPtr->MemPtr->StdHeader));
- if (!MemFeatMain.MemClr (MemMainPtr)) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // OnDimm Thermal
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- if (NBPtr[Node].FeatPtr->OnDimmThermal (&NBPtr[Node])) {
- if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
- return AGESA_FATAL;
- }
- }
- }
-
- //----------------------------------------------------------------
- // Finalize MCT
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- if (!NBPtr[Node].FinalizeMCT (&NBPtr[Node])) {
- return AGESA_FATAL;
- }
- }
-
- //----------------------------------------------------------------
- // After Finalize MCT
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- MemFInitTableDrive (&NBPtr[Node], MTAfterFinalizeMCT);
- }
-
- //----------------------------------------------------------------
- // Memory Context Save
- //----------------------------------------------------------------
- MemFeatMain.MemSave (MemMainPtr);
-
- //----------------------------------------------------------------
- // Memory DMI support
- //----------------------------------------------------------------
- if (!MemFeatMain.MemDmi (MemMainPtr)) {
- return AGESA_CRITICAL;
- }
-
- return AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Main/DA/mmflowda.c b/src/vendorcode/amd/agesa/Proc/Mem/Main/DA/mmflowda.c
deleted file mode 100644
index 3383e05..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Main/DA/mmflowda.c
+++ /dev/null
@@ -1,379 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mmflowda.c
- *
- * Main Memory initialization sequence for DA
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Main/DA)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mnda.h"
-#include "mt.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-#include "GeneralServices.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_MAIN_DA_MMFLOWDA_FILECODE
-/* features */
-#include "mftds.h"
-
-extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function defines the memory initialization flow for
- * systems that only support RB processors.
- *
- * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK
- *
- * @return AGESA_STATUS
- * - AGESA_ALERT
- * - AGESA_FATAL
- * - AGESA_SUCCESS
- * - AGESA_WARNING
- */
-AGESA_STATUS
-MemMFlowDA (
- IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
- )
-{
- UINT8 Node;
- UINT8 NodeCnt;
- MEM_NB_BLOCK *NBPtr;
- MEM_TECH_BLOCK *TechPtr;
- MEM_DATA_STRUCT *MemPtr;
-
- NBPtr = MemMainPtr->NBPtr;
- TechPtr = MemMainPtr->TechPtr;
- NodeCnt = MemMainPtr->DieCount;
- MemPtr = MemMainPtr->MemPtr;
-
- GetLogicalIdOfSocket (MemPtr->DiesPerSystem[BSP_DIE].SocketId, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid), &(MemPtr->StdHeader));
- if (!MemNIsIdSupportedDA (NBPtr, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid))) {
- MemPtr->IsFlowControlSupported = FALSE;
- return AGESA_FATAL;
- } else {
- MemPtr->IsFlowControlSupported = TRUE;
- }
-
- //----------------------------------------------------------------
- // Initialize MCT
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemInitializeMCT, &(MemMainPtr->MemPtr->StdHeader));
- for (Node = 0; Node < NodeCnt; Node++) {
- if (!NBPtr[Node].InitializeMCT (&NBPtr[Node])) {
- return AGESA_FATAL;
- }
- }
-
- //----------------------------------------------------------------
- // Low voltage DDR3
- //----------------------------------------------------------------
- // Levelize DDR3 voltage based on socket, as each socket has its own voltage for dimms.
- AGESA_TESTPOINT (TpProcMemLvDdr3, &(MemMainPtr->MemPtr->StdHeader));
- if (!MemFeatMain.LvDDR3 (MemMainPtr)) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Initialize DRAM and DCTs, and Create Memory Map
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemInitMCT, &(MemMainPtr->MemPtr->StdHeader));
- for (Node = 0; Node < NodeCnt; Node++) {
- // Initialize Memory Controller and Dram
- IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Node);
-
- if (!NBPtr[Node].InitMCT (&NBPtr[Node])) {
- return AGESA_FATAL; // fatalexit
- }
-
- // Create memory map
- AGESA_TESTPOINT (TpProcMemSystemMemoryMapping, &(MemMainPtr->MemPtr->StdHeader));
- if (!NBPtr[Node].HtMemMapInit (&NBPtr[Node])) {
- return AGESA_FATAL;
- }
- }
-
- //----------------------------------------------------
- // If there is no dimm on the system, do fatal exit
- //----------------------------------------------------
- if (NBPtr[BSP_DIE].RefPtr->SysLimit == 0) {
- PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader));
- ASSERT (FALSE);
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Synchronize DCTs
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemSynchronizeDcts, &(MemMainPtr->MemPtr->StdHeader));
- for (Node = 0; Node < NodeCnt; Node++) {
- if (!NBPtr[Node].SyncDctsReady (&NBPtr[Node])) {
- return AGESA_FATAL;
- }
- }
-
- //----------------------------------------------------------------
- // CpuMemTyping
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemMtrrConfiguration, &(MemMainPtr->MemPtr->StdHeader));
- if (!NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE])) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Before Training Table values
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- MemFInitTableDrive (&NBPtr[Node], MTBeforeTrn);
- }
-
- //----------------------------------------------------------------
- // Memory Context Restore
- //----------------------------------------------------------------
- if (!MemFeatMain.MemRestore (MemMainPtr)) {
- // Do DQS training only if memory context restore fails
-
- //----------------------------------------------------------------
- // Training
- //----------------------------------------------------------------
- MemMainPtr->mmSharedPtr->DimmExcludeFlag = TRAINING;
- AGESA_TESTPOINT (TpProcMemDramTraining, &(MemMainPtr->MemPtr->StdHeader));
- IDS_SKIP_HOOK (IDS_BEFORE_DQS_TRAINING, MemMainPtr, &(MemMainPtr->MemPtr->StdHeader)) {
- if (!MemFeatMain.Training (MemMainPtr)) {
- return AGESA_FATAL;
- }
- }
- IDS_HDT_CONSOLE (MEM_FLOW, "\nEnd DQS training\n\n");
- }
-
- //----------------------------------------------------------------
- // Disable chipselects that fail training
- //----------------------------------------------------------------
- MemMainPtr->mmSharedPtr->DimmExcludeFlag = END_TRAINING;
- MemFeatMain.ExcludeDIMM (MemMainPtr);
- MemMainPtr->mmSharedPtr->DimmExcludeFlag = NORMAL;
-
- //----------------------------------------------------------------
- // OtherTiming
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemOtherTiming, &(MemMainPtr->MemPtr->StdHeader));
- for (Node = 0; Node < NodeCnt; Node++) {
- if (!NBPtr[Node].OtherTiming (&NBPtr[Node])) {
- return AGESA_FATAL;
- }
- }
-
- //----------------------------------------------------------------
- // After Training Table values
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- MemFInitTableDrive (&NBPtr[Node], MTAfterTrn);
- }
-
- //----------------------------------------------------------------
- // SetDqsEccTimings
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemSetDqsEccTmgs, &(MemMainPtr->MemPtr->StdHeader));
- for (Node = 0; Node < NodeCnt; Node++) {
- if (!TechPtr[Node].SetDqsEccTmgs (&TechPtr[Node])) {
- return AGESA_FATAL;
- }
- }
-
- //----------------------------------------------------------------
- // Online Spare
- //----------------------------------------------------------------
- if (!MemFeatMain.OnlineSpare (MemMainPtr)) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Interleave banks
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- if (NBPtr[Node].FeatPtr->InterleaveBanks (&NBPtr[Node])) {
- if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
- return AGESA_FATAL;
- }
- }
- }
-
- //----------------------------------------------------------------
- // Interleave Nodes
- //----------------------------------------------------------------
- if (!MemFeatMain.InterleaveNodes (MemMainPtr)) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Interleave channels
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- if (NBPtr[Node].FeatPtr->InterleaveChannels (&NBPtr[Node])) {
- if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
- return AGESA_FATAL;
- }
- }
- }
-
- //----------------------------------------------------------------
- // After Programming Interleave registers
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- MemFInitTableDrive (&NBPtr[Node], MTAfterInterleave);
- }
-
- //----------------------------------------------------------------
- // UMA Allocation & UMAMemTyping
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemUMAMemTyping, &(MemMainPtr->MemPtr->StdHeader));
- if (!MemFeatMain.UmaAllocation (MemMainPtr)) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Interleave region
- //----------------------------------------------------------------
- NBPtr[BSP_DIE].FeatPtr->InterleaveRegion (&NBPtr[BSP_DIE]);
-
- //----------------------------------------------------------------
- // ECC
- //----------------------------------------------------------------
- if (!MemFeatMain.InitEcc (MemMainPtr)) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Memory Clear
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemMemClr, &(MemMainPtr->MemPtr->StdHeader));
- if (!MemFeatMain.MemClr (MemMainPtr)) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // OnDimm Thermal
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- if (NBPtr[Node].FeatPtr->OnDimmThermal (&NBPtr[Node])) {
- if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
- return AGESA_FATAL;
- }
- }
- }
-
- //----------------------------------------------------------------
- // Finalize MCT
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- if (!NBPtr[Node].FinalizeMCT (&NBPtr[Node])) {
- return AGESA_FATAL;
- }
- }
-
- //----------------------------------------------------------------
- // After Finalize MCT
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- MemFInitTableDrive (&NBPtr[Node], MTAfterFinalizeMCT);
- }
-
- //----------------------------------------------------------------
- // Memory Context Save
- //----------------------------------------------------------------
- MemFeatMain.MemSave (MemMainPtr);
-
- //----------------------------------------------------------------
- // Memory DMI support
- //----------------------------------------------------------------
- if (!MemFeatMain.MemDmi (MemMainPtr)) {
- return AGESA_CRITICAL;
- }
-
- return AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Main/DR/mmflowdr.c b/src/vendorcode/amd/agesa/Proc/Mem/Main/DR/mmflowdr.c
deleted file mode 100644
index 08af6d4..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Main/DR/mmflowdr.c
+++ /dev/null
@@ -1,373 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mmflowdr.c
- *
- * Main Memory initialization sequence for DR
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Main/DR)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mndr.h"
-#include "mt.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-#include "GeneralServices.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_MAIN_DR_MMFLOWDR_FILECODE
-/* features */
-#include "mftds.h"
-
-extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function defines the memory initialization flow for
- * systems that only support RB processors.
- *
- * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK
- *
- * @return AGESA_STATUS
- * - AGESA_ALERT
- * - AGESA_FATAL
- * - AGESA_SUCCESS
- * - AGESA_WARNING
- */
-AGESA_STATUS
-MemMFlowDr (
- IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
- )
-{
- UINT8 Node;
- UINT8 NodeCnt;
- MEM_NB_BLOCK *NBPtr;
- MEM_TECH_BLOCK *TechPtr;
- MEM_DATA_STRUCT *MemPtr;
-
- NBPtr = MemMainPtr->NBPtr;
- TechPtr = MemMainPtr->TechPtr;
- NodeCnt = MemMainPtr->DieCount;
- MemPtr = MemMainPtr->MemPtr;
-
- GetLogicalIdOfSocket (MemPtr->DiesPerSystem[BSP_DIE].SocketId, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid), &(MemPtr->StdHeader));
- if (!MemNIsIdSupportedDr (NBPtr, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid))) {
- MemPtr->IsFlowControlSupported = FALSE;
- return AGESA_FATAL;
- } else {
- MemPtr->IsFlowControlSupported = TRUE;
- }
-
- //----------------------------------------------------------------
- // Initialize MCT
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemInitializeMCT, &(MemMainPtr->MemPtr->StdHeader));
- for (Node = 0; Node < NodeCnt; Node++) {
- if (!NBPtr[Node].InitializeMCT (&NBPtr[Node])) {
- return AGESA_FATAL;
- }
- }
-
- //----------------------------------------------------------------
- // Low voltage DDR3
- //----------------------------------------------------------------
- // Levelize DDR3 voltage based on socket, as each socket has its own voltage for dimms.
- AGESA_TESTPOINT (TpProcMemLvDdr3, &(MemMainPtr->MemPtr->StdHeader));
- if (!MemFeatMain.LvDDR3 (MemMainPtr)) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Initialize DRAM and DCTs, and Create Memory Map
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemInitMCT, &(MemMainPtr->MemPtr->StdHeader));
- for (Node = 0; Node < NodeCnt; Node++) {
- // Initialize Memory Controller and Dram
- IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Node);
-
- if (!NBPtr[Node].InitMCT (&NBPtr[Node])) {
- return AGESA_FATAL; //fatalexit
- }
-
- // Create memory map
- AGESA_TESTPOINT (TpProcMemSystemMemoryMapping, &(MemMainPtr->MemPtr->StdHeader));
- if (!NBPtr[Node].HtMemMapInit (&NBPtr[Node])) {
- return AGESA_FATAL;
- }
- }
-
- //----------------------------------------------------
- // If there is no dimm on the system, do fatal exit
- //----------------------------------------------------
- if (NBPtr[BSP_DIE].RefPtr->SysLimit == 0) {
- PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader));
- ASSERT (FALSE);
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Synchronize DCTs
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemSynchronizeDcts, &(MemMainPtr->MemPtr->StdHeader));
- for (Node = 0; Node < NodeCnt; Node++) {
- if (!NBPtr[Node].SyncDctsReady (&NBPtr[Node])) {
- return AGESA_FATAL;
- }
- }
-
- //----------------------------------------------------------------
- // CpuMemTyping
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemMtrrConfiguration, &(MemMainPtr->MemPtr->StdHeader));
- if (!NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE])) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Before Training Table values
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- MemFInitTableDrive (&NBPtr[Node], MTBeforeTrn);
- }
-
- //----------------------------------------------------------------
- // Memory Context Restore
- //----------------------------------------------------------------
- if (!MemFeatMain.MemRestore (MemMainPtr)) {
- // Do DQS training only if memory context restore fails
-
- //----------------------------------------------------------------
- // Training
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemDramTraining, &(MemMainPtr->MemPtr->StdHeader));
- MemMainPtr->mmSharedPtr->DimmExcludeFlag = TRAINING;
- IDS_SKIP_HOOK (IDS_BEFORE_DQS_TRAINING, MemMainPtr, &(MemMainPtr->MemPtr->StdHeader)) {
- if (!MemFeatMain.Training (MemMainPtr)) {
- return AGESA_FATAL;
- }
- }
- IDS_HDT_CONSOLE (MEM_FLOW, "\nEnd DQS training\n\n");
- }
-
- //----------------------------------------------------------------
- // Disable chipselects that fail training
- //----------------------------------------------------------------
- MemMainPtr->mmSharedPtr->DimmExcludeFlag = END_TRAINING;
- MemFeatMain.ExcludeDIMM (MemMainPtr);
- MemMainPtr->mmSharedPtr->DimmExcludeFlag = NORMAL;
-
- //----------------------------------------------------------------
- // OtherTiming
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemOtherTiming, &(MemMainPtr->MemPtr->StdHeader));
- for (Node = 0; Node < NodeCnt; Node++) {
- if (!NBPtr[Node].OtherTiming (&NBPtr[Node])) {
- return AGESA_FATAL;
- }
- }
-
- //----------------------------------------------------------------
- // After Training Table values
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- MemFInitTableDrive (&NBPtr[Node], MTAfterTrn);
- }
-
- //----------------------------------------------------------------
- // SetDqsEccTimings
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemSetDqsEccTmgs, &(MemMainPtr->MemPtr->StdHeader));
- for (Node = 0; Node < NodeCnt; Node++) {
- if (!TechPtr[Node].SetDqsEccTmgs (&TechPtr[Node])) {
- return AGESA_FATAL;
- }
- }
-
- //----------------------------------------------------------------
- // Online Spare
- //----------------------------------------------------------------
- if (!MemFeatMain.OnlineSpare (MemMainPtr)) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Interleave banks
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- if (NBPtr[Node].FeatPtr->InterleaveBanks (&NBPtr[Node])) {
- if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
- return AGESA_FATAL;
- }
- }
- }
-
- //----------------------------------------------------------------
- // Interleave Nodes
- //----------------------------------------------------------------
- if (!MemFeatMain.InterleaveNodes (MemMainPtr)) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Interleave channels
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- if (NBPtr[Node].FeatPtr->InterleaveChannels (&NBPtr[Node])) {
- if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
- return AGESA_FATAL;
- }
- }
- }
-
- //----------------------------------------------------------------
- // After Programming Interleave registers
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- MemFInitTableDrive (&NBPtr[Node], MTAfterInterleave);
- }
-
- //----------------------------------------------------------------
- // UMA Allocation & UMAMemTyping
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemUMAMemTyping, &(MemMainPtr->MemPtr->StdHeader));
- if (!MemFeatMain.UmaAllocation (MemMainPtr)) {
- return AGESA_FATAL;
- }
-
- // ECC
- //----------------------------------------------------------------
- if (!MemFeatMain.InitEcc (MemMainPtr)) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Memory Clear
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemMemClr, &(MemMainPtr->MemPtr->StdHeader));
- if (!MemFeatMain.MemClr (MemMainPtr)) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // OnDimm Thermal
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- if (NBPtr[Node].FeatPtr->OnDimmThermal (&NBPtr[Node])) {
- if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
- return AGESA_FATAL;
- }
- }
- }
-
- //----------------------------------------------------------------
- // Finalize MCT
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- if (!NBPtr[Node].FinalizeMCT (&NBPtr[Node])) {
- return AGESA_FATAL;
- }
- }
-
- //----------------------------------------------------------------
- // After Finalize MCT
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- MemFInitTableDrive (&NBPtr[Node], MTAfterFinalizeMCT);
- }
-
- //----------------------------------------------------------------
- // Memory Context Save
- //----------------------------------------------------------------
- MemFeatMain.MemSave (MemMainPtr);
-
- //----------------------------------------------------------------
- // Memory DMI support
- //----------------------------------------------------------------
- if (!MemFeatMain.MemDmi (MemMainPtr)) {
- return AGESA_CRITICAL;
- }
-
- return AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Main/HY/mmflowhy.c b/src/vendorcode/amd/agesa/Proc/Mem/Main/HY/mmflowhy.c
deleted file mode 100644
index 7f7d1fb..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Main/HY/mmflowhy.c
+++ /dev/null
@@ -1,372 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mmflowhy.c
- *
- * Main Memory initialization sequence for HY
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Main/HY)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mnhy.h"
-#include "mt.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-#include "GeneralServices.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_MAIN_HY_MMFLOWHY_FILECODE
-/* features */
-#include "mftds.h"
-
-extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function defines the memory initialization flow for
- * systems that only support HY processors.
- *
- * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK
- *
- * @return AGESA_STATUS
- * - AGESA_ALERT
- * - AGESA_FATAL
- * - AGESA_SUCCESS
- * - AGESA_WARNING
- */
-AGESA_STATUS
-MemMFlowHy (
- IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
- )
-{
- UINT8 Node;
- UINT8 NodeCnt;
- MEM_NB_BLOCK *NBPtr;
- MEM_TECH_BLOCK *TechPtr;
- MEM_DATA_STRUCT *MemPtr;
-
- NBPtr = MemMainPtr->NBPtr;
- TechPtr = MemMainPtr->TechPtr;
- NodeCnt = MemMainPtr->DieCount;
- MemPtr = MemMainPtr->MemPtr;
-
- GetLogicalIdOfSocket (MemPtr->DiesPerSystem[BSP_DIE].SocketId, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid), &(MemPtr->StdHeader));
- if (!MemNIsIdSupportedHy (NBPtr, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid))) {
- MemPtr->IsFlowControlSupported = FALSE;
- return AGESA_FATAL;
- } else {
- MemPtr->IsFlowControlSupported = TRUE;
- }
-
- //----------------------------------------------------------------
- // Initialize MCT
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemInitializeMCT, &(MemMainPtr->MemPtr->StdHeader));
- for (Node = 0; Node < NodeCnt; Node++) {
- if (!NBPtr[Node].InitializeMCT (&NBPtr[Node])) {
- return AGESA_FATAL;
- }
- }
-
- //----------------------------------------------------------------
- // Low voltage DDR3
- //----------------------------------------------------------------
- // Levelize DDR3 voltage based on socket, as each socket has its own voltage for dimms.
- AGESA_TESTPOINT (TpProcMemLvDdr3, &(MemMainPtr->MemPtr->StdHeader));
- if (!MemFeatMain.LvDDR3 (MemMainPtr)) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Initialize DRAM and DCTs, and Create Memory Map
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemInitMCT, &(MemMainPtr->MemPtr->StdHeader));
- for (Node = 0; Node < NodeCnt; Node++) {
- // Initialize Memory Controller and Dram
- IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Node);
- if (!NBPtr[Node].InitMCT (&NBPtr[Node])) {
- return AGESA_FATAL; //fatalexit
- }
-
- // Create memory map
- AGESA_TESTPOINT (TpProcMemSystemMemoryMapping, &(MemMainPtr->MemPtr->StdHeader));
- if (!NBPtr[Node].HtMemMapInit (&NBPtr[Node])) {
- return AGESA_FATAL;
- }
- }
-
- //----------------------------------------------------
- // If there is no dimm on the system, do fatal exit
- //----------------------------------------------------
- if (NBPtr[BSP_DIE].RefPtr->SysLimit == 0) {
- PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader));
- ASSERT (FALSE);
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Synchronize DCTs
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemSynchronizeDcts, &(MemMainPtr->MemPtr->StdHeader));
- for (Node = 0; Node < NodeCnt; Node++) {
- if (!NBPtr[Node].SyncDctsReady (&NBPtr[Node])) {
- return AGESA_FATAL;
- }
- }
-
- //----------------------------------------------------------------
- // CpuMemTyping
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemMtrrConfiguration, &(MemMainPtr->MemPtr->StdHeader));
- if (!NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE])) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Before Training Table values
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- MemFInitTableDrive (&NBPtr[Node], MTBeforeTrn);
- }
-
- //----------------------------------------------------------------
- // Memory Context Restore
- //----------------------------------------------------------------
- if (!MemFeatMain.MemRestore (MemMainPtr)) {
- // Do DQS training only if memory context restore fails
-
- //----------------------------------------------------------------
- // Training
- //----------------------------------------------------------------
- MemMainPtr->mmSharedPtr->DimmExcludeFlag = TRAINING;
- AGESA_TESTPOINT (TpProcMemDramTraining, &(MemMainPtr->MemPtr->StdHeader));
- IDS_SKIP_HOOK (IDS_BEFORE_DQS_TRAINING, MemMainPtr, &(MemMainPtr->MemPtr->StdHeader)) {
- if (!MemFeatMain.Training (MemMainPtr)) {
- return AGESA_FATAL;
- }
- }
- IDS_HDT_CONSOLE (MEM_FLOW, "\nEnd DQS training\n\n");
- }
-
- //----------------------------------------------------------------
- // Disable chipselects that fail training
- //----------------------------------------------------------------
- MemMainPtr->mmSharedPtr->DimmExcludeFlag = END_TRAINING;
- MemFeatMain.ExcludeDIMM (MemMainPtr);
- MemMainPtr->mmSharedPtr->DimmExcludeFlag = NORMAL;
-
- //----------------------------------------------------------------
- // OtherTiming
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemOtherTiming, &(MemMainPtr->MemPtr->StdHeader));
- for (Node = 0; Node < NodeCnt; Node++) {
- if (!NBPtr[Node].OtherTiming (&NBPtr[Node])) {
- return AGESA_FATAL;
- }
- }
-
- //----------------------------------------------------------------
- // After Training Table values
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- MemFInitTableDrive (&NBPtr[Node], MTAfterTrn);
- }
-
- //----------------------------------------------------------------
- // SetDqsEccTimings
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemSetDqsEccTmgs, &(MemMainPtr->MemPtr->StdHeader));
- for (Node = 0; Node < NodeCnt; Node++) {
- if (!TechPtr[Node].SetDqsEccTmgs (&TechPtr[Node])) {
- return AGESA_FATAL;
- }
- }
-
- //----------------------------------------------------------------
- // Online Spare
- //----------------------------------------------------------------
- if (!MemFeatMain.OnlineSpare (MemMainPtr)) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Interleave banks
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- if (NBPtr[Node].FeatPtr->InterleaveBanks (&NBPtr[Node])) {
- if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
- return AGESA_FATAL;
- }
- }
- }
-
- //----------------------------------------------------------------
- // Interleave Nodes
- //----------------------------------------------------------------
- if (!MemFeatMain.InterleaveNodes (MemMainPtr)) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Interleave channels
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- if (NBPtr[Node].FeatPtr->InterleaveChannels (&NBPtr[Node])) {
- if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
- return AGESA_FATAL;
- }
- }
- }
-
- //----------------------------------------------------------------
- // After Programming Interleave registers
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- MemFInitTableDrive (&NBPtr[Node], MTAfterInterleave);
- }
-
- //----------------------------------------------------------------
- // UMA Allocation & UMAMemTyping
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemUMAMemTyping, &(MemMainPtr->MemPtr->StdHeader));
- if (!MemFeatMain.UmaAllocation (MemMainPtr)) {
- return AGESA_FATAL;
- }
-
- // ECC
- //----------------------------------------------------------------
- if (!MemFeatMain.InitEcc (MemMainPtr)) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Memory Clear
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemMemClr, &(MemMainPtr->MemPtr->StdHeader));
- if (!MemFeatMain.MemClr (MemMainPtr)) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // OnDimm Thermal
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- if (NBPtr[Node].FeatPtr->OnDimmThermal (&NBPtr[Node])) {
- if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
- return AGESA_FATAL;
- }
- }
- }
-
- //----------------------------------------------------------------
- // Finalize MCT
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- if (!NBPtr[Node].FinalizeMCT (&NBPtr[Node])) {
- return AGESA_FATAL;
- }
- }
-
- //----------------------------------------------------------------
- // After Finalize MCT
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- MemFInitTableDrive (&NBPtr[Node], MTAfterFinalizeMCT);
- }
-
- //----------------------------------------------------------------
- // Memory Context Save
- //----------------------------------------------------------------
- MemFeatMain.MemSave (MemMainPtr);
-
- //----------------------------------------------------------------
- // Memory DMI support
- //----------------------------------------------------------------
- if (!MemFeatMain.MemDmi (MemMainPtr)) {
- return AGESA_CRITICAL;
- }
-
- return AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Main/ON/mmflowon.c b/src/vendorcode/amd/agesa/Proc/Mem/Main/ON/mmflowon.c
deleted file mode 100644
index 378ca7a..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Main/ON/mmflowon.c
+++ /dev/null
@@ -1,292 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mmflowon.c
- *
- * Main Memory initialization sequence for ON
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Main/ON)
- * @e \$Revision: 38442 $ @e \$Date: 2010-09-24 06:39:57 +0800 (Fri, 24 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mnon.h"
-#include "mt.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-#include "GeneralServices.h"
-
-#define FILECODE PROC_MEM_MAIN_ON_MMFLOWON_FILECODE
-/* features */
-#include "mftds.h"
-
-extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function defines the memory initialization flow for
- * systems that only support ON processors.
- *
- * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK
- *
- * @return AGESA_STATUS
- * - AGESA_ALERT
- * - AGESA_FATAL
- * - AGESA_SUCCESS
- * - AGESA_WARNING
- */
-AGESA_STATUS
-MemMFlowON (
- IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
- )
-{
- MEM_NB_BLOCK *NBPtr;
- MEM_DATA_STRUCT *MemPtr;
-
- NBPtr = MemMainPtr->NBPtr;
- MemPtr = MemMainPtr->MemPtr;
-
- GetLogicalIdOfSocket (MemPtr->DiesPerSystem[BSP_DIE].SocketId, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid), &(MemPtr->StdHeader));
- if (!MemNIsIdSupportedON (NBPtr, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid))) {
- MemPtr->IsFlowControlSupported = FALSE;
- return AGESA_FATAL;
- } else {
- MemPtr->IsFlowControlSupported = TRUE;
- }
-
- //----------------------------------------------------------------
- // Low voltage DDR3
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemLvDdr3, &(MemMainPtr->MemPtr->StdHeader));
- if (!MemFeatMain.LvDDR3 (MemMainPtr)) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Initialize DRAM and DCTs, and Create Memory Map
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemInitMCT, &(MemMainPtr->MemPtr->StdHeader));
- // Initialize Memory Controller and Dram
- IDS_HDT_CONSOLE (MEM_STATUS, "Node 0\n");
-
- if (!NBPtr[BSP_DIE].InitMCT (&NBPtr[BSP_DIE])) {
- return AGESA_FATAL; //fatalexit
- }
-
- // Create memory map
- AGESA_TESTPOINT (TpProcMemSystemMemoryMapping, &(MemMainPtr->MemPtr->StdHeader));
- if (!NBPtr[BSP_DIE].HtMemMapInit (&NBPtr[BSP_DIE])) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------
- // If there is no dimm on the system, do fatal exit
- //----------------------------------------------------
- if (NBPtr[BSP_DIE].RefPtr->SysLimit == 0) {
- PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader));
- ASSERT(FALSE); // Size of memory on BSP = 0, so no DIMM found
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Synchronize DCTs
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemSynchronizeDcts, &(MemMainPtr->MemPtr->StdHeader));
- if (!NBPtr[BSP_DIE].SyncDctsReady (&NBPtr[BSP_DIE])) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // CpuMemTyping
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemMtrrConfiguration, &(MemMainPtr->MemPtr->StdHeader));
- if (!NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE])) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Before Training Table values
- //----------------------------------------------------------------
- MemFInitTableDrive (&NBPtr[BSP_DIE], MTBeforeTrn);
-
- //----------------------------------------------------------------
- // Memory Context Restore
- //----------------------------------------------------------------
- if (!MemFeatMain.MemRestore (MemMainPtr)) {
- // Do DQS training only if memory context restore fails
-
- //----------------------------------------------------------------
- // Training
- //----------------------------------------------------------------
- MemMainPtr->mmSharedPtr->DimmExcludeFlag = TRAINING;
- AGESA_TESTPOINT (TpProcMemDramTraining, &(MemMainPtr->MemPtr->StdHeader));
- IDS_SKIP_HOOK (IDS_BEFORE_DQS_TRAINING, MemMainPtr, &(MemMainPtr->MemPtr->StdHeader)) {
- if (!MemFeatMain.Training (MemMainPtr)) {
- return AGESA_FATAL;
- }
- }
- IDS_HDT_CONSOLE (MEM_FLOW, "\nEnd DQS training\n\n");
- }
-
- //----------------------------------------------------------------
- // Disable chipselects that fail training
- //----------------------------------------------------------------
- MemMainPtr->mmSharedPtr->DimmExcludeFlag = END_TRAINING;
- MemFeatMain.ExcludeDIMM (MemMainPtr);
- MemMainPtr->mmSharedPtr->DimmExcludeFlag = NORMAL;
-
- //----------------------------------------------------------------
- // OtherTiming
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemOtherTiming, &(MemMainPtr->MemPtr->StdHeader));
- if (!NBPtr[BSP_DIE].OtherTiming (&NBPtr[BSP_DIE])) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // After Training Table values
- //----------------------------------------------------------------
- MemFInitTableDrive (&NBPtr[BSP_DIE], MTAfterTrn);
-
-
- //----------------------------------------------------------------
- // Interleave banks
- //----------------------------------------------------------------
- if (NBPtr[BSP_DIE].FeatPtr->InterleaveBanks (&NBPtr[BSP_DIE])) {
- if (NBPtr[BSP_DIE].MCTPtr->ErrCode == AGESA_FATAL) {
- return AGESA_FATAL;
- }
- }
-
- //----------------------------------------------------------------
- // After Programming Interleave registers
- //----------------------------------------------------------------
- MemFInitTableDrive (&NBPtr[BSP_DIE], MTAfterInterleave);
-
- //----------------------------------------------------------------
- // Memory Clear
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemMemClr, &(MemMainPtr->MemPtr->StdHeader));
- if (!MemFeatMain.MemClr (MemMainPtr)) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // C6 Storage Allocation
- //----------------------------------------------------------------
- NBPtr[BSP_DIE].AllocateC6Storage (&NBPtr[BSP_DIE]);
-
- //----------------------------------------------------------------
- // UMA Allocation & UMAMemTyping
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemUMAMemTyping, &(MemMainPtr->MemPtr->StdHeader));
- if (!MemFeatMain.UmaAllocation (MemMainPtr)) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Finalize MCT
- //----------------------------------------------------------------
- if (!NBPtr[BSP_DIE].FinalizeMCT (&NBPtr[BSP_DIE])) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // After Finalize MCT
- //----------------------------------------------------------------
- MemFInitTableDrive (&NBPtr[BSP_DIE], MTAfterFinalizeMCT);
-
-
- //----------------------------------------------------------------
- // Memory Context Save
- //----------------------------------------------------------------
- MemFeatMain.MemSave (MemMainPtr);
-
- //----------------------------------------------------------------
- // Memory DMI support
- //----------------------------------------------------------------
- if (!MemFeatMain.MemDmi (MemMainPtr)) {
- return AGESA_CRITICAL;
- }
-
- return AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Main/PH/mmflowPh.c b/src/vendorcode/amd/agesa/Proc/Mem/Main/PH/mmflowPh.c
deleted file mode 100644
index 8e21684..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Main/PH/mmflowPh.c
+++ /dev/null
@@ -1,380 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mmflowPh.c
- *
- * Main Memory initialization sequence for PH
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Main/PH)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mnda.h"
-#include "mnPh.h"
-#include "mt.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-#include "GeneralServices.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_MAIN_PH_MMFLOWPH_FILECODE
-/* features */
-#include "mftds.h"
-
-extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function defines the memory initialization flow for
- * systems that only support PH processors.
- *
- * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK
- *
- * @return AGESA_STATUS
- * - AGESA_ALERT
- * - AGESA_FATAL
- * - AGESA_SUCCESS
- * - AGESA_WARNING
- */
-AGESA_STATUS
-MemMFlowPh (
- IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
- )
-{
- UINT8 Node;
- UINT8 NodeCnt;
- MEM_NB_BLOCK *NBPtr;
- MEM_TECH_BLOCK *TechPtr;
- MEM_DATA_STRUCT *MemPtr;
-
- NBPtr = MemMainPtr->NBPtr;
- TechPtr = MemMainPtr->TechPtr;
- NodeCnt = MemMainPtr->DieCount;
- MemPtr = MemMainPtr->MemPtr;
-
- GetLogicalIdOfSocket (MemPtr->DiesPerSystem[BSP_DIE].SocketId, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid), &(MemPtr->StdHeader));
- if (!MemNIsIdSupportedPh (NBPtr, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid))) {
- MemPtr->IsFlowControlSupported = FALSE;
- return AGESA_FATAL;
- } else {
- MemPtr->IsFlowControlSupported = TRUE;
- }
-
- //----------------------------------------------------------------
- // Initialize MCT
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemInitializeMCT, &(MemMainPtr->MemPtr->StdHeader));
- for (Node = 0; Node < NodeCnt; Node++) {
- if (!NBPtr[Node].InitializeMCT (&NBPtr[Node])) {
- return AGESA_FATAL;
- }
- }
-
- //----------------------------------------------------------------
- // Low voltage DDR3
- //----------------------------------------------------------------
- // Levelize DDR3 voltage based on socket, as each socket has its own voltage for dimms.
- AGESA_TESTPOINT (TpProcMemLvDdr3, &(MemMainPtr->MemPtr->StdHeader));
- if (!MemFeatMain.LvDDR3 (MemMainPtr)) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Initialize DRAM and DCTs, and Create Memory Map
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemInitMCT, &(MemMainPtr->MemPtr->StdHeader));
- for (Node = 0; Node < NodeCnt; Node++) {
- // Initialize Memory Controller and Dram
- IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Node);
-
- if (!NBPtr[Node].InitMCT (&NBPtr[Node])) {
- return AGESA_FATAL; // fatalexit
- }
-
- // Create memory map
- AGESA_TESTPOINT (TpProcMemSystemMemoryMapping, &(MemMainPtr->MemPtr->StdHeader));
- if (!NBPtr[Node].HtMemMapInit (&NBPtr[Node])) {
- return AGESA_FATAL;
- }
- }
-
- //----------------------------------------------------
- // If there is no dimm on the system, do fatal exit
- //----------------------------------------------------
- if (NBPtr[BSP_DIE].RefPtr->SysLimit == 0) {
- PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader));
- ASSERT (FALSE);
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Synchronize DCTs
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemSynchronizeDcts, &(MemMainPtr->MemPtr->StdHeader));
- for (Node = 0; Node < NodeCnt; Node++) {
- if (!NBPtr[Node].SyncDctsReady (&NBPtr[Node])) {
- return AGESA_FATAL;
- }
- }
-
- //----------------------------------------------------------------
- // CpuMemTyping
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemMtrrConfiguration, &(MemMainPtr->MemPtr->StdHeader));
- if (!NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE])) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Before Training Table values
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- MemFInitTableDrive (&NBPtr[Node], MTBeforeTrn);
- }
-
- //----------------------------------------------------------------
- // Memory Context Restore
- //----------------------------------------------------------------
- if (!MemFeatMain.MemRestore (MemMainPtr)) {
- // Do DQS training only if memory context restore fails
-
- //----------------------------------------------------------------
- // Training
- //----------------------------------------------------------------
- MemMainPtr->mmSharedPtr->DimmExcludeFlag = TRAINING;
- AGESA_TESTPOINT (TpProcMemDramTraining, &(MemMainPtr->MemPtr->StdHeader));
- IDS_SKIP_HOOK (IDS_BEFORE_DQS_TRAINING, MemMainPtr, &(MemMainPtr->MemPtr->StdHeader)) {
- if (!MemFeatMain.Training (MemMainPtr)) {
- return AGESA_FATAL;
- }
- }
- IDS_HDT_CONSOLE (MEM_FLOW, "\nEnd DQS training\n\n");
- }
-
- //----------------------------------------------------------------
- // Disable chipselects that fail training
- //----------------------------------------------------------------
- MemMainPtr->mmSharedPtr->DimmExcludeFlag = END_TRAINING;
- MemFeatMain.ExcludeDIMM (MemMainPtr);
- MemMainPtr->mmSharedPtr->DimmExcludeFlag = NORMAL;
-
- //----------------------------------------------------------------
- // OtherTiming
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemOtherTiming, &(MemMainPtr->MemPtr->StdHeader));
- for (Node = 0; Node < NodeCnt; Node++) {
- if (!NBPtr[Node].OtherTiming (&NBPtr[Node])) {
- return AGESA_FATAL;
- }
- }
-
- //----------------------------------------------------------------
- // After Training Table values
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- MemFInitTableDrive (&NBPtr[Node], MTAfterTrn);
- }
-
- //----------------------------------------------------------------
- // SetDqsEccTimings
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemSetDqsEccTmgs, &(MemMainPtr->MemPtr->StdHeader));
- for (Node = 0; Node < NodeCnt; Node++) {
- if (!TechPtr[Node].SetDqsEccTmgs (&TechPtr[Node])) {
- return AGESA_FATAL;
- }
- }
-
- //----------------------------------------------------------------
- // Online Spare
- //----------------------------------------------------------------
- if (!MemFeatMain.OnlineSpare (MemMainPtr)) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Interleave banks
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- if (NBPtr[Node].FeatPtr->InterleaveBanks (&NBPtr[Node])) {
- if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
- return AGESA_FATAL;
- }
- }
- }
-
- //----------------------------------------------------------------
- // Interleave Nodes
- //----------------------------------------------------------------
- if (!MemFeatMain.InterleaveNodes (MemMainPtr)) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Interleave channels
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- if (NBPtr[Node].FeatPtr->InterleaveChannels (&NBPtr[Node])) {
- if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
- return AGESA_FATAL;
- }
- }
- }
-
- //----------------------------------------------------------------
- // After Programming Interleave registers
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- MemFInitTableDrive (&NBPtr[Node], MTAfterInterleave);
- }
-
- //----------------------------------------------------------------
- // UMA Allocation & UMAMemTyping
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemUMAMemTyping, &(MemMainPtr->MemPtr->StdHeader));
- if (!MemFeatMain.UmaAllocation (MemMainPtr)) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Interleave region
- //----------------------------------------------------------------
- NBPtr[BSP_DIE].FeatPtr->InterleaveRegion (&NBPtr[BSP_DIE]);
-
- //----------------------------------------------------------------
- // ECC
- //----------------------------------------------------------------
- if (!MemFeatMain.InitEcc (MemMainPtr)) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Memory Clear
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemMemClr, &(MemMainPtr->MemPtr->StdHeader));
- if (!MemFeatMain.MemClr (MemMainPtr)) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // OnDimm Thermal
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- if (NBPtr[Node].FeatPtr->OnDimmThermal (&NBPtr[Node])) {
- if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
- return AGESA_FATAL;
- }
- }
- }
-
- //----------------------------------------------------------------
- // Finalize MCT
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- if (!NBPtr[Node].FinalizeMCT (&NBPtr[Node])) {
- return AGESA_FATAL;
- }
- }
-
- //----------------------------------------------------------------
- // After Finalize MCT
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- MemFInitTableDrive (&NBPtr[Node], MTAfterFinalizeMCT);
- }
-
- //----------------------------------------------------------------
- // Memory Context Save
- //----------------------------------------------------------------
- MemFeatMain.MemSave (MemMainPtr);
-
- //----------------------------------------------------------------
- // Memory DMI support
- //----------------------------------------------------------------
- if (!MemFeatMain.MemDmi (MemMainPtr)) {
- return AGESA_CRITICAL;
- }
-
- return AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Main/RB/mmflowRb.c b/src/vendorcode/amd/agesa/Proc/Mem/Main/RB/mmflowRb.c
deleted file mode 100644
index d8d5218..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Main/RB/mmflowRb.c
+++ /dev/null
@@ -1,380 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mmflowRb.c
- *
- * Main Memory initialization sequence for RB
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Main/RB)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mnda.h"
-#include "mnRb.h"
-#include "mt.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-#include "GeneralServices.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_MAIN_RB_MMFLOWRB_FILECODE
-/* features */
-#include "mftds.h"
-
-extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function defines the memory initialization flow for
- * systems that only support RB processors.
- *
- * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK
- *
- * @return AGESA_STATUS
- * - AGESA_ALERT
- * - AGESA_FATAL
- * - AGESA_SUCCESS
- * - AGESA_WARNING
- */
-AGESA_STATUS
-MemMFlowRb (
- IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
- )
-{
- UINT8 Node;
- UINT8 NodeCnt;
- MEM_NB_BLOCK *NBPtr;
- MEM_TECH_BLOCK *TechPtr;
- MEM_DATA_STRUCT *MemPtr;
-
- NBPtr = MemMainPtr->NBPtr;
- TechPtr = MemMainPtr->TechPtr;
- NodeCnt = MemMainPtr->DieCount;
- MemPtr = MemMainPtr->MemPtr;
-
- GetLogicalIdOfSocket (MemPtr->DiesPerSystem[BSP_DIE].SocketId, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid), &(MemPtr->StdHeader));
- if (!MemNIsIdSupportedRb (NBPtr, &(MemPtr->DiesPerSystem[BSP_DIE].LogicalCpuid))) {
- MemPtr->IsFlowControlSupported = FALSE;
- return AGESA_FATAL;
- } else {
- MemPtr->IsFlowControlSupported = TRUE;
- }
-
- //----------------------------------------------------------------
- // Initialize MCT
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemInitializeMCT, &(MemMainPtr->MemPtr->StdHeader));
- for (Node = 0; Node < NodeCnt; Node++) {
- if (!NBPtr[Node].InitializeMCT (&NBPtr[Node])) {
- return AGESA_FATAL;
- }
- }
-
- //----------------------------------------------------------------
- // Low voltage DDR3
- //----------------------------------------------------------------
- // Levelize DDR3 voltage based on socket, as each socket has its own voltage for dimms.
- AGESA_TESTPOINT (TpProcMemLvDdr3, &(MemMainPtr->MemPtr->StdHeader));
- if (!MemFeatMain.LvDDR3 (MemMainPtr)) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Initialize DRAM and DCTs, and Create Memory Map
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemInitMCT, &(MemMainPtr->MemPtr->StdHeader));
- for (Node = 0; Node < NodeCnt; Node++) {
- // Initialize Memory Controller and Dram
- IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Node);
-
- if (!NBPtr[Node].InitMCT (&NBPtr[Node])) {
- return AGESA_FATAL; // fatalexit
- }
-
- // Create memory map
- AGESA_TESTPOINT (TpProcMemSystemMemoryMapping, &(MemMainPtr->MemPtr->StdHeader));
- if (!NBPtr[Node].HtMemMapInit (&NBPtr[Node])) {
- return AGESA_FATAL;
- }
- }
-
- //----------------------------------------------------
- // If there is no dimm on the system, do fatal exit
- //----------------------------------------------------
- if (NBPtr[BSP_DIE].RefPtr->SysLimit == 0) {
- PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader));
- ASSERT (FALSE);
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Synchronize DCTs
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemSynchronizeDcts, &(MemMainPtr->MemPtr->StdHeader));
- for (Node = 0; Node < NodeCnt; Node++) {
- if (!NBPtr[Node].SyncDctsReady (&NBPtr[Node])) {
- return AGESA_FATAL;
- }
- }
-
- //----------------------------------------------------------------
- // CpuMemTyping
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemMtrrConfiguration, &(MemMainPtr->MemPtr->StdHeader));
- if (!NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE])) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Before Training Table values
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- MemFInitTableDrive (&NBPtr[Node], MTBeforeTrn);
- }
-
- //----------------------------------------------------------------
- // Memory Context Restore
- //----------------------------------------------------------------
- if (!MemFeatMain.MemRestore (MemMainPtr)) {
- // Do DQS training only if memory context restore fails
-
- //----------------------------------------------------------------
- // Training
- //----------------------------------------------------------------
- MemMainPtr->mmSharedPtr->DimmExcludeFlag = TRAINING;
- AGESA_TESTPOINT (TpProcMemDramTraining, &(MemMainPtr->MemPtr->StdHeader));
- IDS_SKIP_HOOK (IDS_BEFORE_DQS_TRAINING, MemMainPtr, &(MemMainPtr->MemPtr->StdHeader)) {
- if (!MemFeatMain.Training (MemMainPtr)) {
- return AGESA_FATAL;
- }
- }
- IDS_HDT_CONSOLE (MEM_FLOW, "\nEnd DQS training\n\n");
- }
-
- //----------------------------------------------------------------
- // Disable chipselects that fail training
- //----------------------------------------------------------------
- MemMainPtr->mmSharedPtr->DimmExcludeFlag = END_TRAINING;
- MemFeatMain.ExcludeDIMM (MemMainPtr);
- MemMainPtr->mmSharedPtr->DimmExcludeFlag = NORMAL;
-
- //----------------------------------------------------------------
- // OtherTiming
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemOtherTiming, &(MemMainPtr->MemPtr->StdHeader));
- for (Node = 0; Node < NodeCnt; Node++) {
- if (!NBPtr[Node].OtherTiming (&NBPtr[Node])) {
- return AGESA_FATAL;
- }
- }
-
- //----------------------------------------------------------------
- // After Training Table values
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- MemFInitTableDrive (&NBPtr[Node], MTAfterTrn);
- }
-
- //----------------------------------------------------------------
- // SetDqsEccTimings
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemSetDqsEccTmgs, &(MemMainPtr->MemPtr->StdHeader));
- for (Node = 0; Node < NodeCnt; Node++) {
- if (!TechPtr[Node].SetDqsEccTmgs (&TechPtr[Node])) {
- return AGESA_FATAL;
- }
- }
-
- //----------------------------------------------------------------
- // Online Spare
- //----------------------------------------------------------------
- if (!MemFeatMain.OnlineSpare (MemMainPtr)) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Interleave banks
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- if (NBPtr[Node].FeatPtr->InterleaveBanks (&NBPtr[Node])) {
- if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
- return AGESA_FATAL;
- }
- }
- }
-
- //----------------------------------------------------------------
- // Interleave Nodes
- //----------------------------------------------------------------
- if (!MemFeatMain.InterleaveNodes (MemMainPtr)) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Interleave channels
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- if (NBPtr[Node].FeatPtr->InterleaveChannels (&NBPtr[Node])) {
- if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
- return AGESA_FATAL;
- }
- }
- }
-
- //----------------------------------------------------------------
- // After Programming Interleave registers
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- MemFInitTableDrive (&NBPtr[Node], MTAfterInterleave);
- }
-
- //----------------------------------------------------------------
- // UMA Allocation & UMAMemTyping
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemUMAMemTyping, &(MemMainPtr->MemPtr->StdHeader));
- if (!MemFeatMain.UmaAllocation (MemMainPtr)) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Interleave region
- //----------------------------------------------------------------
- NBPtr[BSP_DIE].FeatPtr->InterleaveRegion (&NBPtr[BSP_DIE]);
-
- //----------------------------------------------------------------
- // ECC
- //----------------------------------------------------------------
- if (!MemFeatMain.InitEcc (MemMainPtr)) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // Memory Clear
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemMemClr, &(MemMainPtr->MemPtr->StdHeader));
- if (!MemFeatMain.MemClr (MemMainPtr)) {
- return AGESA_FATAL;
- }
-
- //----------------------------------------------------------------
- // OnDimm Thermal
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- if (NBPtr[Node].FeatPtr->OnDimmThermal (&NBPtr[Node])) {
- if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
- return AGESA_FATAL;
- }
- }
- }
-
- //----------------------------------------------------------------
- // Finalize MCT
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- if (!NBPtr[Node].FinalizeMCT (&NBPtr[Node])) {
- return AGESA_FATAL;
- }
- }
-
- //----------------------------------------------------------------
- // After Finalize MCT
- //----------------------------------------------------------------
- for (Node = 0; Node < NodeCnt; Node++) {
- MemFInitTableDrive (&NBPtr[Node], MTAfterFinalizeMCT);
- }
-
- //----------------------------------------------------------------
- // Memory Context Save
- //----------------------------------------------------------------
- MemFeatMain.MemSave (MemMainPtr);
-
- //----------------------------------------------------------------
- // Memory DMI support
- //----------------------------------------------------------------
- if (!MemFeatMain.MemDmi (MemMainPtr)) {
- return AGESA_CRITICAL;
- }
-
- return AGESA_SUCCESS;
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Main/mdef.c b/src/vendorcode/amd/agesa/Proc/Mem/Main/mdef.c
deleted file mode 100644
index 0d80a4e..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Main/mdef.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mdef.c
- *
- * Memory Controller header file
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Main)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "Filecode.h"
-#include "mm.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_MAIN_MDEF_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is the default return function
- */
-
-VOID
-memDefRet (VOID)
-{
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function is the default return function that returns TRUE
- *
- */
-BOOLEAN
-memDefTrue (VOID)
-{
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function is used in place of an un-supported function that returns FALSE.
- *
- */
-BOOLEAN
-memDefFalse (VOID)
-{
- return FALSE;
-}
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is the default return function for flow control
- */
-AGESA_STATUS
-MemMFlowDef (
- IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
- )
-{
- MemMainPtr->MemPtr->IsFlowControlSupported = FALSE;
- return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function is used in place of an un-supported function that returns AGESA_SUCCESS.
- *
- */
-AGESA_STATUS
-memDefRetSuccess (VOID)
-{
- return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Main/merrhdl.c b/src/vendorcode/amd/agesa/Proc/Mem/Main/merrhdl.c
deleted file mode 100644
index 0685f89..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Main/merrhdl.c
+++ /dev/null
@@ -1,189 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * merrhdl.c
- *
- * Memory error handling
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Main)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "heapManager.h"
-#include "merrhdl.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_MAIN_MERRHDL_FILECODE
-
-extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function handle errors occur in memory code.
- *
- *
- * @param[in,out] *MCTPtr - pointer to DIE_STRUCT.
- * @param[in,out] DCT - DCT that needs to be handled.
- * @param[in,out] ChipSelMask - Chip select mask that needs to be handled
- * @param[in,out] *StdHeader - pointer to AMD_CONFIG_PARAMS
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-BOOLEAN
-MemErrHandle (
- IN DIE_STRUCT *MCTPtr,
- IN UINT8 DCT,
- IN UINT16 ChipSelMask,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- BOOLEAN ErrorRecovery;
- BOOLEAN IgnoreErr;
- DCT_STRUCT *DCTPtr;
- UINT8 CurrentDCT;
- LOCATE_HEAP_PTR LocHeap;
- MEM_NB_BLOCK *NBPtr;
- MEM_MAIN_DATA_BLOCK mmData;
-
- DCTPtr = MCTPtr->DctData;
- ErrorRecovery = TRUE;
- IgnoreErr = FALSE;
- IDS_OPTION_HOOK (IDS_MEM_ERROR_RECOVERY, &ErrorRecovery, StdHeader);
-
- if (ErrorRecovery) {
- if (DCT == EXCLUDE_ALL_DCT) {
- // Exclude all DCTs on a node
- for (CurrentDCT = 0; CurrentDCT < MCTPtr->DctCount; CurrentDCT++) {
- DCTPtr[CurrentDCT].Timings.CsTestFail = DCTPtr[CurrentDCT].Timings.CsPresent;
- }
- } else if (ChipSelMask == EXCLUDE_ALL_CHIPSEL) {
- // Exclude the specified DCT
- DCTPtr[DCT].Timings.CsTestFail = DCTPtr[DCT].Timings.CsPresent;
- } else {
- // Exclude the chip select that has been marked out
- DCTPtr[DCT].Timings.CsTestFail |= ChipSelMask & DCTPtr[DCT].Timings.CsPresent;
- IDS_OPTION_HOOK (IDS_LOADCARD_ERROR_RECOVERY, &DCTPtr[DCT], StdHeader);
- }
-
- // Exclude the failed dimm to recovery from error
- if (MCTPtr->NodeMemSize != 0) {
- LocHeap.BufferHandle = AMD_MEM_AUTO_HANDLE;
- if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) {
- // NB block has already been constructed by main block.
- // No need to construct it here.
- NBPtr = (MEM_NB_BLOCK *)LocHeap.BufferPtr;
- if (!NBPtr->SharedPtr->NodeMap[MCTPtr->NodeId].IsValid) {
- // Memory map has not been calculated, no need to remap memory across node here.
- // Only need to remap memory within the node.
- NBPtr = &NBPtr[MCTPtr->NodeId];
- NBPtr->FeatPtr->ExcludeDIMM (NBPtr);
- } else {
- // Need to remap memory across the whole system.
- mmData.MemPtr = NBPtr->MemPtr;
- mmData.mmSharedPtr = NBPtr->SharedPtr;
- mmData.NBPtr = NBPtr;
- mmData.TechPtr = (MEM_TECH_BLOCK *) (&NBPtr[NBPtr->MemPtr->DieCount]);
- mmData.DieCount = NBPtr->MemPtr->DieCount;
- if (!MemFeatMain.ExcludeDIMM (&mmData)) {
- return FALSE;
- }
- }
- }
- // If allocation fails, that means the code is not running at BSP.
- // Parallel training is in process.
- // Remap for parallel training will be done when control returns to BSP.
- }
- return TRUE;
- } else {
- IDS_OPTION_HOOK (IDS_MEM_IGNORE_ERROR, &IgnoreErr, StdHeader);
- if (IgnoreErr) {
- return TRUE;
- }
- SetMemError (AGESA_FATAL, MCTPtr);
- ASSERT(FALSE); // ErrorRecovery is FALSE
- return FALSE;
- }
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Main/minit.c b/src/vendorcode/amd/agesa/Proc/Mem/Main/minit.c
deleted file mode 100644
index ba3346b..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Main/minit.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * minit.c
- *
- * Initializer support function
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Main)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "mu.h"
-#include "OptionMemory.h"
-#include "Ids.h"
-#include "merrhdl.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_MAIN_MINIT_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-extern MEM_NB_SUPPORT memNBInstalled[];
-extern MEM_PLATFORM_CFG* memPlatformTypeInstalled[];
-
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the default parameter, function pointers, build options
- * and SPD data for memory configuration
- *
- * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
- * @param[in,out] *PlatFormConfig - Platform profile/build option config structure
- *
- */
-
-VOID
-AmdMemInitDataStructDef (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT PLATFORM_CONFIGURATION *PlatFormConfig
- )
-{
- UINT8 p;
- UINT8 i;
- // We need a way of specifying default values for each particular northbridge
- // family. We also need to make sure that the IBV knows which parameter struct
- // is for which northbridge.
- //----------------------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemBeforeMemDataInit, &MemPtr->StdHeader);
-
- MemPtr->PlatFormConfig = PlatFormConfig;
-
- memNBInstalled[0].MemNInitDefaults (MemPtr);
-
- //----------------------------------------------------------------------------
- // INITIALIZE PLATFORM SPECIFIC CONFIGURATION STRUCT
- //----------------------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemPlatformSpecificConfig, &MemPtr->StdHeader);
- i = 0;
- for (p = 0; p < MAX_PLATFORM_TYPES; p++) {
- if (memPlatformTypeInstalled[i] != NULL) {
- MemPtr->GetPlatformCfg[p] = memPlatformTypeInstalled[i];
- i++;
- } else {
- MemPtr->GetPlatformCfg[p] = MemAGetPsCfgDef;
- }
- }
- AGESA_TESTPOINT (TpProcMemAfterMemDataInit, &MemPtr->StdHeader);
- MemPtr->ErrorHandling = MemErrHandle;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Main/mm.c b/src/vendorcode/amd/agesa/Proc/Mem/Main/mm.c
deleted file mode 100644
index 391b5df..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Main/mm.c
+++ /dev/null
@@ -1,240 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mm.c
- *
- * Main Memory Entrypoint file
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Main)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuServices.h"
-#include "GeneralServices.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_MAIN_MM_FILECODE
-/* features */
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function deallocates heap buffers that were allocated in AmdMemAuto
- *
- * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
- *
- * @return AGESA_STATUS
- * - AGESA_ALERT
- * - AGESA_FATAL
- * - AGESA_SUCCESS
- * - AGESA_WARNING
- */
-AGESA_STATUS
-MemAmdFinalize (
- IN OUT MEM_DATA_STRUCT *MemPtr
- )
-{
- UINT8 Die;
-
- for (Die = 0; Die < MemPtr->DieCount; Die++ ) {
- HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_TRN_DATA_HANDLE, Die, 0, 0), &MemPtr->StdHeader);
- HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, Die, 0, 0), &MemPtr->StdHeader);
- }
-
- HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_DIE_STRUCT_HANDLE, 0, 0, 0), &MemPtr->StdHeader);
- HeapDeallocateBuffer (AMD_S3_SAVE_HANDLE, &MemPtr->StdHeader);
- HeapDeallocateBuffer (AMD_MEM_SPD_HANDLE, &MemPtr->StdHeader);
- HeapDeallocateBuffer (AMD_MEM_AUTO_HANDLE, &MemPtr->StdHeader);
- return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * MemSocketScan - Scan all nodes, recording the physical Socket number,
- * Die Number (relative to the socket), and PCI Device address of each
- * populated socket.
- *
- * This information is used by the northbridge block to map a dram
- * channel on a particular DCT, on a particular CPU Die, in a particular
- * socket to a the DRAM SPD Data for the DIMMS physically connected to
- * that channel.
- *
- * Also, the customer socket map is populated with pointers to the
- * appropriate channel structures, so that the customer can locate the
- * appropriate channel configuration data.
- *
- * This socket scan will always result in Die 0 as the BSP.
- *
- * @param[in,out] *mmPtr - Pointer to the MEM_MAIN_DATA_BLOCK
- *
- */
-AGESA_STATUS
-MemSocketScan (
- IN OUT MEM_MAIN_DATA_BLOCK *mmPtr
- )
-{
- MEM_DATA_STRUCT *MemPtr;
- UINT8 DieIndex;
- UINT8 DieCount;
- UINT32 SocketId;
- UINT32 DieId;
- UINT8 Die;
- PCI_ADDR Address;
- AGESA_STATUS AgesaStatus;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
- ASSERT (mmPtr != NULL);
- ASSERT (mmPtr->MemPtr != NULL);
- MemPtr = mmPtr->MemPtr;
-
- //
- // Count the number of dies in the system
- //
- DieCount = 0;
- for (Die = 0; Die < MAX_NODES_SUPPORTED; Die++) {
- if (GetSocketModuleOfNode ((UINT32)Die, &SocketId, &DieId, (VOID *)MemPtr)) {
- DieCount++;
- }
- }
- MemPtr->DieCount = DieCount;
- mmPtr->DieCount = DieCount;
-
- if (DieCount > 0) {
- //
- // Allocate buffer for DIE_STRUCTs
- //
- AllocHeapParams.RequestedBufferSize = ((UINT16)DieCount * sizeof (DIE_STRUCT));
- AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DIE_STRUCT_HANDLE, 0, 0, 0);
- AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
- if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) == AGESA_SUCCESS) {
- MemPtr->DiesPerSystem = (DIE_STRUCT *)AllocHeapParams.BufferPtr;
- //
- // Find SocketId, DieId, and PCI address of each node
- //
- DieIndex = 0;
- for (Die = 0; Die < MAX_NODES_SUPPORTED; Die++) {
- if (GetSocketModuleOfNode ((UINT32)Die, &SocketId, &DieId, (VOID *)MemPtr)) {
- if (GetPciAddress ((VOID *)MemPtr, (UINT8)SocketId, (UINT8)DieId, &Address, &AgesaStatus)) {
- MemPtr->DiesPerSystem[DieIndex].SocketId = (UINT8)SocketId;
- MemPtr->DiesPerSystem[DieIndex].DieId = (UINT8)DieId;
- MemPtr->DiesPerSystem[DieIndex].PciAddr.AddressValue = Address.AddressValue;
-
- DieIndex++;
- }
- }
- }
- AgesaStatus = AGESA_SUCCESS;
- } else {
- ASSERT(FALSE); // Heap allocation failed for DIE_STRUCTs
- AgesaStatus = AGESA_FATAL;
- }
- } else {
- ASSERT(FALSE); // No die in the system
- AgesaStatus = AGESA_FATAL;
- }
- return AgesaStatus;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function sets memory errors into MemDataStruct
- *
- *
- * @param[in,out] *MCTPtr - Pointer to the DIE_STRUCT
- * @param[in] Errorval - Error value to update
- */
-
-VOID
-SetMemError (
- IN AGESA_STATUS Errorval,
- IN OUT DIE_STRUCT *MCTPtr
- )
-{
- if (MCTPtr->ErrCode < Errorval) {
- MCTPtr->ErrCode = Errorval;
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Main/mmConditionalPso.c b/src/vendorcode/amd/agesa/Proc/Mem/Main/mmConditionalPso.c
deleted file mode 100644
index d2477a3..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Main/mmConditionalPso.c
+++ /dev/null
@@ -1,697 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mmConditionalPso.c
- *
- * Functions to support conditional entries in the Platform Specific Override Table
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Main)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "Ids.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_MAIN_MMCONDITIONALPSO_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-#define PSO_TYPE 0
-#define PSO_LENGTH 1
-#define PSO_DATA 2
-
-typedef enum _PSO_STATE {
- PSO_FIND_CONDITION = 100, // Searching for initial Condition statement
- PSO_FIND_ACTION, // Searching for initial Action Statement
- PSO_MATCH_ACTION, // Trying to find an action that matches the caller's request
- PSO_CHECK_CONDITION, // Checking the condition that preceded the found action
- PSO_DO_ACTION, // Performing Action
- PSO_COMPLETE // Completed processing of this request
-} PSO_STATE;
-
-typedef struct _D3_CMP_CAL {
- UINT32 D3Cmp0NCal :3;
- UINT32 Reserved34 :2;
- UINT32 D3Cmp0PCal :3;
- UINT32 Reserved89 :2;
- UINT32 D3Cmp1NCal :3;
- UINT32 Reserved1314 :2;
- UINT32 D3Cmp1PCal :3;
- UINT32 Reserved1819 :2;
- UINT32 D3Cmp2NCal :3;
- UINT32 Reserved2324 :2;
- UINT32 D3Cmp2PCal :3;
- UINT32 Reserved2831 :2;
-} D3_CMP_CAL;
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
- STATIC
- MemPSODoActionODT (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 *Buffer
- );
-
- BOOLEAN
- STATIC
- MemPSODoActionAddrTmg (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 *Buffer
- );
-
- BOOLEAN
- STATIC
- MemPSODoActionODCControl (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 *Buffer
- );
-
- BOOLEAN
- STATIC
- MemPSODoActionSlewRate (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 *Buffer
- );
-
-BOOLEAN
-STATIC
-MemPSODoActionGetFreqLimit (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 *Buffer
- );
-
-BOOLEAN
-STATIC
-MemCheckRankType (
- IN CH_DEF_STRUCT *CurrentChannel,
- IN UINT16 RankType
- );
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Process Conditional Platform Specific Overrides
- *
- * @param[in] PlatformMemoryConfiguration - Pointer to Platform config table
- * @param[in] NBPtr - Pointer to Current NBBlock
- * @param[in] PsoAction - Action type
- * @param[in] Dimm - Dimm Number
- *
- * @return BOOLEAN - TRUE : Action was performed
- * FALSE: Action was not performed
- *
- * ----------------------------------------------------------------------------
- */
-BOOLEAN
-MemProcessConditionalOverrides (
- IN PSO_TABLE *PlatformMemoryConfiguration,
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 PsoAction,
- IN UINT8 Dimm
- )
-{
- BOOLEAN Result;
- MEM_TECH_BLOCK *TechPtr;
- UINT8 *Buffer;
- UINT8 *ConditionStartPtr;
- UINT8 *ActionStartPtr;
- UINT8 *SpdBufferPtr;
- UINT8 i;
- UINT8 DimmMask;
- UINT8 CurDimmMask;
- BOOLEAN Condition;
- BOOLEAN TmpCond;
- PSO_STATE State;
- ASSERT (PlatformMemoryConfiguration != NULL);
- ASSERT (NBPtr != NULL);
- ASSERT ((PsoAction >= PSO_ACTION_MIN) && (PsoAction <= PSO_ACTION_MAX));
- //
- // Set up local data
- //
- TechPtr = NBPtr->TechPtr;
- Buffer = PlatformMemoryConfiguration;
- State = PSO_FIND_CONDITION;
- ConditionStartPtr = NULL;
- ActionStartPtr = NULL;
- Condition = FALSE;
- DimmMask = 0xFF;
- CurDimmMask = 0xFF;
- Result = FALSE;
-
- if (Dimm != 0xFF) {
- DimmMask = ( 1 << Dimm);
- }
- DimmMask &= (UINT8) (NBPtr->ChannelPtr->ChDimmValid & 0xFF);
- if (DimmMask == 0) {
- return Result;
- }
-
- //
- // Search for Condition Entry
- //
- while (State != PSO_COMPLETE) {
- switch (State) {
- //
- // Searching for initial Condition statement
- //
- case PSO_FIND_CONDITION:
- ASSERT (Buffer != NULL);
- while (Buffer[PSO_TYPE] != PSO_CONDITION_AND) {
- //
- // If end of table is reached, Change state to complete and break.
- //
- if (Buffer[PSO_TYPE] == PSO_END) {
- State = PSO_COMPLETE;
- break;
- }
- //
- // Otherwise, increment Buffer Pointer to the next PSO entry.
- //
- Buffer += (Buffer[PSO_LENGTH] + 2);
- }
- //
- // If Condition statement has been found, save the Condition Start Pointer,
- // and change to next state
- //
- if (State != PSO_COMPLETE) {
- ASSERT (Buffer != NULL);
- State = PSO_FIND_ACTION;
- ConditionStartPtr = Buffer;
- Buffer += (Buffer[PSO_LENGTH] + 2);
- }
- break;
- //
- // Searching for an action that matches the caller's request
- //
- case PSO_FIND_ACTION:
- ASSERT (Buffer != NULL);
- while (Buffer[PSO_TYPE] != PsoAction) {
- //
- // If non-conditional entry, change state to complete and break.
- //
- if ((Buffer[PSO_TYPE] < CONDITIONAL_PSO_MIN) || (Buffer[PSO_TYPE] > CONDITIONAL_PSO_MAX)) {
- State = PSO_COMPLETE;
- break;
- }
- //
- // Check for the Start of a new condition block
- //
- if (Buffer[PSO_TYPE] == PSO_CONDITION_AND) {
- ConditionStartPtr = Buffer;
- }
- //
- // Otherwise, increment buffer pointer to the next PSO entry.
- //
- Buffer += (Buffer[PSO_LENGTH] + 2);
- }
- //
- // If Action statement has been found, Save the Action Start Pointer, Reset Buffer to Condition Start
- // and Change to next state.
- //
- if (State != PSO_COMPLETE) {
- State = PSO_CHECK_CONDITION;
- ASSERT (Buffer != NULL);
- ActionStartPtr = Buffer;
- Buffer = ConditionStartPtr;
- Condition = TRUE;
- }
- break;
- //
- // Checking the condition that preceded the found action
- //
- case PSO_CHECK_CONDITION:
- ASSERT (Buffer != NULL);
- //
- // Point to the next Condition
- //
- Buffer += (Buffer[PSO_LENGTH] + 2);
- ASSERT ((Buffer[PSO_TYPE] >= CONDITIONAL_PSO_MIN) && (Buffer[PSO_TYPE] <= CONDITIONAL_PSO_MAX));
- //
- // This section has already been checked for invalid statements so just exit on ACTION_xx
- //
- if ((Buffer[PSO_TYPE] >= PSO_ACTION_MIN) && (Buffer[PSO_TYPE] <= PSO_ACTION_MAX)) {
- if (Condition) {
- ASSERT (Buffer != NULL);
- State = PSO_DO_ACTION; // Perform the Action
- } else {
- State = PSO_FIND_CONDITION; // Go back and look for another condition/action
- }
- Buffer = ActionStartPtr; // Restore Action Pointer
- break;
- }
- switch (Buffer[PSO_TYPE]) {
-
- case PSO_CONDITION_AND:
- //
- // Additional CONDITION_AND is ORed with Previous ones, so if Previous result is TRUE
- // just restore action pointer and perform the action.
- //
- if (Condition) {
- State = PSO_DO_ACTION;
- Buffer = ActionStartPtr;
- } else {
- //
- // If its false, Start over and evaluate next cond.
- // reset the Current Dimm Mask
- //
- Condition = TRUE;
- CurDimmMask = 0xFF;
- }
- break;
-
- case PSO_CONDITION_LOC:
- //
- // Condition location
- //
- CurDimmMask = Buffer[4];
- Condition &= ( ((Buffer[2] & (1 << (NBPtr->MCTPtr->SocketId))) != 0) &&
- ((Buffer[3] & (1 << (NBPtr->ChannelPtr->ChannelID))) != 0) &&
- ((CurDimmMask & DimmMask) != 0) );
- break;
-
- case PSO_CONDITION_SPD:
- //
- // Condition SPD
- //
- TmpCond = FALSE;
- for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i ++) {
- if ( ((DimmMask & CurDimmMask) & ((UINT16) (1 << i))) != 0) {
- if (TechPtr->GetDimmSpdBuffer (TechPtr, &SpdBufferPtr, i)) {
- TmpCond |= ( (SpdBufferPtr[Buffer[2]] & Buffer[3]) == Buffer[4]);
- }
- }
- }
- Condition &= TmpCond;
- break;
-
- case PSO_CONDITION_REG:
- //
- // Condition Register - unsupported at this time
- //
- break;
-
- default:
- ASSERT (FALSE);
- } // End Condition Switch
- break;
-
- case PSO_DO_ACTION:
- ASSERT (Buffer != NULL);
- //
- // Performing Action
- //
- if ((Buffer[PSO_TYPE] < PSO_ACTION_MIN) || (Buffer[PSO_TYPE] > PSO_ACTION_MAX)) {
- State = PSO_COMPLETE;
- }
- if (Buffer[PSO_TYPE] == PsoAction) {
- switch (Buffer[PSO_TYPE]) {
- case PSO_ACTION_ODT:
- Result = MemPSODoActionODT (NBPtr, &Buffer[PSO_DATA]);
- break;
- case PSO_ACTION_ADDRTMG:
- Result = MemPSODoActionAddrTmg (NBPtr, &Buffer[PSO_DATA]);
- break;
- case PSO_ACTION_ODCCONTROL:
- Result = MemPSODoActionODCControl (NBPtr, &Buffer[PSO_DATA]);
- break;
- case PSO_ACTION_SLEWRATE:
- Result = MemPSODoActionSlewRate (NBPtr, &Buffer[PSO_DATA]);
- break;
- case PSO_ACTION_SPEEDLIMIT:
- Result = MemPSODoActionGetFreqLimit (NBPtr, &Buffer[PSO_DATA]);
- break;
- case PSO_ACTION_REG:
- break;
- default:
- ASSERT (FALSE);
- } // End Action Switch
- //
- // If Action was performed, mark complete.
- //
- if (Result) {
- State = PSO_COMPLETE;
- }
- }// End Action
-
- //
- // Point to the next PSO Entry
- //
- Buffer += (Buffer[PSO_LENGTH] + 2);
- break;
-
- case PSO_COMPLETE:
- //
- // Completed processing of this request
- //
- break;
-
- default:
- ASSERT (FALSE);
- } // End State Switch
-
- } // End While
-
- return Result;
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- * Perform ODT Platform Override
- *
- * @param[in] NBPtr - Pointer to Current NBBlock
- * @param[in] Buffer - Pointer to the Action Command Data (w/o Type and Len)
- *
- * @return BOOLEAN - TRUE : Action was performed
- * FALSE: Action was not performed
- *
- * ----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPSODoActionODT (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 *Buffer
- )
-{
- BOOLEAN Result;
- UINT32 Speed;
- UINT8 Dimms;
- UINT8 i;
- UINT8 QR_Dimms;
- Result = FALSE;
- Speed = ((UINT32) 1 << (NBPtr->DCTPtr->Timings.Speed / 66));
- Dimms = NBPtr->ChannelPtr->Dimms;
- QR_Dimms = 0;
- for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) {
- if (((NBPtr->ChannelPtr->DimmQrPresent & (UINT16) (1 << i)) != 0) && (i < 2)) {
- QR_Dimms ++;
- }
- }
- if ((Speed & ((UINT32 *) Buffer)[0]) != 0) {
- if ((((UINT8) (1 << (Dimms - 1)) & Buffer[4]) != 0) || (Buffer[4] == ANY_NUM)) {
- if (((QR_Dimms == 0) && (Buffer[5] == NO_DIMM)) ||
- ((QR_Dimms > 0) && (((UINT8) (1 << (QR_Dimms - 1)) & Buffer[5]) != 0)) ||
- (Buffer[5] == ANY_NUM)) {
- NBPtr->PsPtr->DramTerm = Buffer[6];
- NBPtr->PsPtr->QR_DramTerm = Buffer[7];
- NBPtr->PsPtr->DynamicDramTerm = Buffer[8];
- Result = TRUE;
- IDS_HDT_CONSOLE (MEM_FLOW, " Platform Override: DramTerm:%02x, QRDramTerm:%02x, DynDramTerm:%02x\n", Buffer[6], Buffer[7], Buffer[8]);
- }
- }
- }
- return Result;
- }
-
- /* -----------------------------------------------------------------------------*/
-/**
- * Perform Address Timing Platform Override
- *
- * @param[in] NBPtr - Pointer to Current NBBlock
- * @param[in] Buffer - Pointer to the Action Command Data (w/o Type and Len)
- *
- * @return BOOLEAN - TRUE : Action was performed
- * FALSE: Action was not performed
- *
- * ----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPSODoActionAddrTmg (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 *Buffer
- )
-{
- BOOLEAN Result;
- CH_DEF_STRUCT *ChannelPtr;
- UINT32 Speed;
- UINT16 DimmConfig;
-
- Result = FALSE;
- ChannelPtr = NBPtr->ChannelPtr;
- Speed = ((UINT32) 1 << (NBPtr->DCTPtr->Timings.Speed / 66));
- DimmConfig = *(UINT16 *) &(Buffer[4]);
-
- if ((Speed & ((UINT32 *) Buffer)[0]) != 0) {
- if (MemCheckRankType (ChannelPtr, DimmConfig)) {
- ChannelPtr->DctAddrTmg = *(UINT32*) &(Buffer[6]);
- Result = TRUE;
- IDS_HDT_CONSOLE (MEM_FLOW, " Platform Override: Address Timing:%08x\n", *(UINT32*) &(Buffer[6]));
- }
- }
- return Result;
- }
-
- /* -----------------------------------------------------------------------------*/
-/**
- * Perform Drive Strength Platform Override
- *
- * @param[in] NBPtr - Pointer to Current NBBlock
- * @param[in] Buffer - Pointer to the Action Command Data (w/o Type and Len)
- *
- * @return BOOLEAN - TRUE : Action was performed
- * FALSE: Action was not performed
- *
- * ----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPSODoActionODCControl (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 *Buffer
- )
-{
- BOOLEAN Result;
- CH_DEF_STRUCT *ChannelPtr;
- UINT32 Speed;
- UINT16 DimmConfig;
-
- Result = FALSE;
- ChannelPtr = NBPtr->ChannelPtr;
- Speed = ((UINT32) 1 << (NBPtr->DCTPtr->Timings.Speed / 66));
- DimmConfig = *(UINT16 *) &(Buffer[4]);
-
- if ((Speed & ((UINT32 *) Buffer)[0]) != 0) {
- if (MemCheckRankType (ChannelPtr, DimmConfig)) {
- ChannelPtr->DctOdcCtl = *(UINT32*) &(Buffer[6]);
- Result = TRUE;
- IDS_HDT_CONSOLE (MEM_FLOW, " Platform Override: ODC Control:%08x\n", *(UINT32*)&(Buffer[6]));
- }
- }
- return Result;
- }
-
- /* -----------------------------------------------------------------------------*/
-/**
- * Perform Slew Rate Platform Override
- *
- * @param[in] NBPtr - Pointer to Current NBBlock
- * @param[in] Buffer - Pointer to the Action Command Data (w/o Type and Len)
- *
- * @return BOOLEAN - TRUE : Action was performed
- * FALSE: Action was not performed
- *
- * ----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPSODoActionSlewRate (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 *Buffer
- )
-{
- BOOLEAN Result;
- CH_DEF_STRUCT *ChannelPtr;
- UINT32 Speed;
- UINT16 DimmConfig;
-
- Result = FALSE;
- ChannelPtr = NBPtr->ChannelPtr;
- Speed = ((UINT32) 1 << (NBPtr->DCTPtr->Timings.Speed / 66));
- DimmConfig = *(UINT16 *) &(Buffer[4]);
-
- if ((Speed & ((UINT32 *) Buffer)[0]) != 0) {
- if (MemCheckRankType (ChannelPtr, DimmConfig)) {
- MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp0NCal );
- MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp0PCal );
- MemNSetBitFieldNb (NBPtr, BFD3Cmp1NCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp1NCal );
- MemNSetBitFieldNb (NBPtr, BFD3Cmp1PCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp1PCal );
- MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp2NCal );
- MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, ((D3_CMP_CAL *) &(Buffer[6]))->D3Cmp2PCal );
- Result = TRUE;
- IDS_HDT_CONSOLE (MEM_FLOW, " Platform Override: Slew Rate:%08x\n", *(UINT32 *) &(Buffer[6]));
- }
- }
- return Result;
- }
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function overrides the POR supported speed for a specific config
- *
- * @param[in] NBPtr - Pointer to Current NBBlock
- * @param[in] Buffer - Pointer to the Action Command Data (w/o Type and Len)
- *
- * @return BOOLEAN - TRUE : Action was performed
- * FALSE: Action was not performed
- *
- */
-BOOLEAN
-STATIC
-MemPSODoActionGetFreqLimit (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 *Buffer
- )
-{
- BOOLEAN Result;
- CH_DEF_STRUCT *ChannelPtr;
- DCT_STRUCT *DCTPtr;
- UINT16 DimmConfig;
- UINT16 SpeedLimit;
-
- Result = FALSE;
- ChannelPtr = NBPtr->ChannelPtr;
- DCTPtr = NBPtr->DCTPtr;
- DimmConfig = *(UINT16*) &(Buffer[0]);
- SpeedLimit = 0;
- //
- // Match number of dimms, then Rank Type
- //
- if (ChannelPtr->Dimms == Buffer[2]) {
- if (MemCheckRankType (ChannelPtr, DimmConfig)) {
- //
- // Select speed based on current voltage
- //
- if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) {
- SpeedLimit = *(UINT16*) &(Buffer[3]);
- } else if (NBPtr->RefPtr->DDR3Voltage == VOLT1_25) {
- SpeedLimit = *(UINT16*) &(Buffer[7]);
- } else {
- SpeedLimit = *(UINT16*) &(Buffer[5]);
- }
- //
- // Set the Speed limit
- //
- if (DCTPtr->Timings.TargetSpeed > SpeedLimit) {
- DCTPtr->Timings.TargetSpeed = SpeedLimit;
- }
- Result = TRUE;
- IDS_HDT_CONSOLE (MEM_FLOW, " Platform Override: Max Memory Speed for Channel %d: %d\n", NBPtr->Channel, SpeedLimit);
- }
- }
- return Result;
-}
-
- /* -----------------------------------------------------------------------------*/
-/**
- *
- * This function matches a particular Rank Type Mask to the installed
- * DIMM configuration on the provided channel.
- *
- * @param[in] *CurrentChannel Pointer to CH_DEF_STRUCT
- * @param[in] RankType Mask of rank type to match
- *
- * @return BOOLEAN - TRUE : Rank types match
- * FALSE: Rank types do not match
- *
- */
-BOOLEAN
-STATIC
-MemCheckRankType (
- IN CH_DEF_STRUCT *CurrentChannel,
- IN UINT16 RankType
- )
-{
- BOOLEAN Result;
- UINT8 i;
- UINT16 DIMMRankType;
-
- DIMMRankType = MemAGetPsRankType (CurrentChannel);
- Result = TRUE;
- for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) {
- if ( ((DIMMRankType & (0x0F << (i << 2))) + (RankType & (0x0F << (i << 2)))) != 0) {
- Result &= (((DIMMRankType & (0x0F << (i << 2))) & ( RankType & ( 0x0F << ( i << 2)))) != 0);
- }
- if (!Result) {
- break;
- }
- }
- return Result;
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Main/mmEcc.c b/src/vendorcode/amd/agesa/Proc/Mem/Main/mmEcc.c
deleted file mode 100644
index 9105b3a..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Main/mmEcc.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mmEcc.c
- *
- * Main Memory Feature implementation file for ECC Initialization
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Main)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-#include "Porting.h"
-#include "AGESA.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "ma.h"
-#include "mfmemclr.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_MAIN_MMECC_FILECODE
-
-/*-----------------------------------------------------------------------------
-* EXPORTED FUNCTIONS
-*
-*-----------------------------------------------------------------------------
-*/
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *
- *
- * @param[in,out] *mmPtr - Pointer to the MEM_MAIN_DATA_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-BOOLEAN
-MemMEcc (
- IN OUT MEM_MAIN_DATA_BLOCK *mmPtr
- )
-{
- UINT8 Die;
- DIE_STRUCT *MCTPtr;
- MEM_SHARED_DATA *SharedPtr;
- MEM_PARAMETER_STRUCT *RefPtr;
- BOOLEAN RetVal;
-
- RetVal = TRUE;
- RefPtr = mmPtr->MemPtr->ParameterListPtr;
- SharedPtr = mmPtr->mmSharedPtr;
- MCTPtr = mmPtr->NBPtr->MCTPtr;
- //
- // Run Northbridge-specific ECC initialization feature for each die.
- //
- SharedPtr->AllECC = FALSE;
- if (MCTPtr->Status[SbEccDimms] && RefPtr->EnableEccFeature) {
- SharedPtr->AllECC = TRUE;
- AGESA_TESTPOINT (TpProcMemEccInitialization, &(mmPtr->MemPtr->StdHeader));
-
- for (Die = 0 ; Die < mmPtr->DieCount ; Die ++ ) {
- mmPtr->NBPtr[Die].FeatPtr->CheckEcc (&(mmPtr->NBPtr[Die]));
- RetVal &= (BOOLEAN) (mmPtr->NBPtr[Die].MCTPtr->ErrCode < AGESA_FATAL);
- }
- if (SharedPtr->AllECC == TRUE) {
- RefPtr->GStatus[GsbAllECCDimms] = TRUE;
- // Sync mem clear before setting scrub rate.
- for (Die = 0; Die < mmPtr->DieCount; Die++) {
- MemFMctMemClr_Sync (&(mmPtr->NBPtr[Die]));
- }
- }
- }
- // Scrubber control
- for (Die = 0 ; Die < mmPtr->DieCount ; Die ++ ) {
- mmPtr->NBPtr[Die].FeatPtr->InitEcc (&(mmPtr->NBPtr[Die]));
- }
- return RetVal;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Main/mmExcludeDimm.c b/src/vendorcode/amd/agesa/Proc/Mem/Main/mmExcludeDimm.c
deleted file mode 100644
index 9eb20bb..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Main/mmExcludeDimm.c
+++ /dev/null
@@ -1,218 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mmExcludeDimm.c
- *
- * Main Memory Feature implementation file for RAS DIMM Exclude Feature
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Main)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "mport.h"
-#include "amdlib.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_MAIN_MMEXCLUDEDIMM_FILECODE
-
-extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
-/*-----------------------------------------------------------------------------
-* EXPORTED FUNCTIONS
-*
-*-----------------------------------------------------------------------------
-*/
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Check and disable Chip selects that fail training on all nodes.
- *
- * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-BOOLEAN
-MemMRASExcludeDIMM (
- IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
- )
-{
- UINT8 Node;
- BOOLEAN IsEnabled;
- BOOLEAN RetVal;
- BOOLEAN IsChannelIntlvEnabled[MAX_NODES_SUPPORTED];
- UINT8 FirstEnabledNode;
- UINT32 BottomIO;
- MEM_NB_BLOCK *NBPtr;
- MEM_PARAMETER_STRUCT *RefPtr;
- S_UINT64 SMsr;
-
- FirstEnabledNode = 0;
- IsEnabled = FALSE;
- RetVal = TRUE;
- NBPtr = MemMainPtr->NBPtr;
- RefPtr = NBPtr[BSP_DIE].RefPtr;
- for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
- if (NBPtr[Node].FeatPtr->ExcludeDIMM (&NBPtr[Node])) {
- if (!IsEnabled) {
- // Record the first node that has exclude dimm enabled
- FirstEnabledNode = Node;
- IsEnabled = TRUE;
- }
- }
- }
-
- if (IsEnabled) {
- // Check if all nodes have all dimms excluded. If yes, fatal exit
- NBPtr[BSP_DIE].SharedPtr->CurrentNodeSysBase = 0;
- BottomIO = (NBPtr[BSP_DIE].RefPtr->BottomIo & 0xF8) << 8;
- // If the first node that has excluded dimms does not have a system base smaller
- // than bottomIO, then we don't need to reset the GStatus, as we don't need to
- // remap memory hole.
- if (NBPtr[FirstEnabledNode].MCTPtr->NodeSysBase < BottomIO) {
- RefPtr->GStatus[GsbHWHole] = FALSE;
- RefPtr->GStatus[GsbSpIntRemapHole] = FALSE;
- RefPtr->GStatus[GsbSoftHole] = FALSE;
- RefPtr->HoleBase = 0;
- RefPtr->SysLimit = 0;
- }
- // If Node Interleaving has been executed before the remapping then we need to
- // start from the first node.
- // There may be a few senarios:
- // 1. Node interleaving is not enabled before the remap, and still cannot be enabled after
- // remap
- // 2. Node interleaving cannot be enabled before the remap, but it can be enabled after
- // remap
- // 3. Node interleaving is enabled before the remap, but it cannot be enabled after the remap
- if (NBPtr->SharedPtr->NodeIntlv.IsValid) {
- FirstEnabledNode = 0;
- }
-
- for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
- IsChannelIntlvEnabled [Node] = FALSE;
- // Check if node interleaving has been enabled on this node
- // if yes, disable it.
- if (NBPtr[Node].GetBitField (&NBPtr[Node], BFDramIntlvEn) != 0) {
- NBPtr[Node].SetBitField (&NBPtr[Node], BFDramIntlvEn, 0);
- NBPtr[Node].SetBitField (&NBPtr[Node], BFDramIntlvSel, 0);
- }
- if (Node >= FirstEnabledNode) {
- // Remap memory on nodes with node number larger than the first node that has excluded dimms.
- // If channel interleaving has already been enabled, need to disable it before remapping memory.
- if (NBPtr[Node].GetBitField (&NBPtr[Node], BFDctSelIntLvEn) != 0) {
- NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelIntLvEn, 0);
- IsChannelIntlvEnabled [Node] = TRUE;
- }
- NBPtr[Node].MCTPtr->Status[SbHWHole] = FALSE;
- NBPtr[Node].MCTPtr->Status[SbSWNodeHole] = FALSE;
- NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelBaseAddr, 0);
- NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelHiRngEn, 0);
- NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelHi, 0);
- NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelBaseOffset, 0);
- NBPtr[Node].SetBitField (&NBPtr[Node], BFDramHoleAddrReg, 0);
- NBPtr[Node].HtMemMapInit (&NBPtr[Node]);
- } else if (NBPtr[Node].MCTPtr->NodeMemSize != 0) {
- // No change is needed in the memory map of this node.
- // Need to adjust the current system base for other nodes processed later.
- NBPtr[Node].SharedPtr->CurrentNodeSysBase = (NBPtr[Node].MCTPtr->NodeSysLimit + 1) & 0xFFFFFFF0;
- RefPtr->SysLimit = NBPtr[Node].MCTPtr->NodeSysLimit;
- // If the current node does not have the memory hole, then set DramHoleAddrReg to be 0.
- // If memory hoisting is enabled later by other node, SyncAddrMapToAllNodes will set the base
- // and DramMemHoistValid.
- // Otherwise, do not change the register value, as we need to keep DramHoleOffset unchanged, as well
- // DramHoleValid.
- if (!NBPtr[Node].MCTPtr->Status[SbHWHole]) {
- NBPtr[Node].SetBitField (&NBPtr[Node], BFDramHoleAddrReg, 0);
- }
- }
- }
-
- for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
- NBPtr[Node].SyncAddrMapToAllNodes (&NBPtr[Node]);
- }
-
- LibAmdMsrRead (TOP_MEM, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader);
- // Only when TOM is set can CpuMemTyping be re-run
- if (SMsr.hi == SMsr.lo == 0) {
- if (RefPtr->SysLimit != 0) {
- NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE]);
- }
- }
-
- // Re-run node interleaving if it has been exeucuted before the remap
- if (NBPtr->SharedPtr->NodeIntlv.IsValid) {
- MemFeatMain.InterleaveNodes (MemMainPtr);
- }
-
- // Re-enable channel interleaving if it was enabled before remapping memory
- for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
- if (IsChannelIntlvEnabled [Node]) {
- NBPtr[Node].FeatPtr->InterleaveChannels (&NBPtr[Node]);
- }
- }
- }
-
- // if all dimms on all nodes are excluded, do fatal exit
- if (RefPtr->SysLimit == 0) {
- PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_FATAL, NBPtr[BSP_DIE].MCTPtr);
- ASSERT (FALSE);
- }
-
- for (Node = 0; Node < MemMainPtr->DieCount; Node ++) {
- RetVal &= (BOOLEAN) (NBPtr[Node].MCTPtr->ErrCode < AGESA_FATAL);
- }
-
- return RetVal;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Main/mmLvDdr3.c b/src/vendorcode/amd/agesa/Proc/Mem/Main/mmLvDdr3.c
deleted file mode 100644
index 1fe2171..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Main/mmLvDdr3.c
+++ /dev/null
@@ -1,265 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mmLvDdr3.c
- *
- * Main Memory Feature implementation file for low voltage DDR3 support
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Main)
- * @e \$Revision: 38415 $ @e \$Date: 2010-09-24 03:30:59 +0800 (Fri, 24 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "amdlib.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_MAIN_MMLVDDR3_FILECODE
-
-extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
-/*-----------------------------------------------------------------------------
-* EXPORTED FUNCTIONS
-*
-*-----------------------------------------------------------------------------
-*/
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Find the common supported voltage on all nodes.
- *
- * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-BOOLEAN
-MemMLvDdr3 (
- IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
- )
-{
- UINT8 Node;
- BOOLEAN RetVal;
- BOOLEAN SecondLoop;
- MEM_NB_BLOCK *NBPtr;
- MEM_PARAMETER_STRUCT *ParameterPtr;
- MEM_SHARED_DATA *mmSharedPtr;
-
- NBPtr = MemMainPtr->NBPtr;
- mmSharedPtr = MemMainPtr->mmSharedPtr;
- ParameterPtr = MemMainPtr->MemPtr->ParameterListPtr;
- mmSharedPtr->VoltageMap = 0xFF;
- SecondLoop = FALSE;
- RetVal = TRUE;
-
- for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
- NBPtr[Node].FeatPtr->LvDdr3 (&NBPtr[Node]);
- // Check if there is no common supported voltage
- if ((mmSharedPtr->VoltageMap == 0) && !SecondLoop) {
- // restart node loop by setting node to 0xFF
- Node = 0xFF;
- SecondLoop = TRUE;
- }
- }
-
- if (mmSharedPtr->VoltageMap == 0) {
- ParameterPtr->DDR3Voltage = VOLT_UNSUPPORTED;
- } else {
- ParameterPtr->DDR3Voltage = (DIMM_VOLTAGE) LibAmdBitScanReverse (mmSharedPtr->VoltageMap);
- }
-
- for (Node = 0; Node < MemMainPtr->DieCount; Node ++) {
- RetVal &= (BOOLEAN) (NBPtr[Node].MCTPtr->ErrCode < AGESA_FATAL);
- }
-
- return RetVal;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Find the common supported voltage on all nodes, taken into account of the
- * user option for performance and power saving.
- *
- * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-BOOLEAN
-MemMLvDdr3PerformanceEnhPre (
- IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
- )
-{
- UINT8 Node;
- BOOLEAN RetVal;
- DIMM_VOLTAGE VDDIO;
- MEM_NB_BLOCK *NBPtr;
- MEM_PARAMETER_STRUCT *ParameterPtr;
- MEM_SHARED_DATA *mmSharedPtr;
- PLATFORM_POWER_POLICY PowerPolicy;
-
- NBPtr = MemMainPtr->NBPtr;
- mmSharedPtr = MemMainPtr->mmSharedPtr;
- ParameterPtr = MemMainPtr->MemPtr->ParameterListPtr;
- PowerPolicy = MemMainPtr->MemPtr->PlatFormConfig->PlatformProfile.PlatformPowerPolicy;
-
- IDS_OPTION_HOOK (IDS_SKIP_PERFORMANCE_OPT, &PowerPolicy, &NBPtr->MemPtr->StdHeader);
- IDS_HDT_CONSOLE (MEM_STATUS, (PowerPolicy == Performance) ? "Maximize Performance\n" : "Maximize Battery Life\n");
-
- RetVal = MemMLvDdr3 (MemMainPtr);
-
- VDDIO = ParameterPtr->DDR3Voltage;
- ParameterPtr->DDR3Voltage = VOLT_UNSUPPORTED;
-
- if (mmSharedPtr->VoltageMap == 0) {
- // When there is no commonly supported voltage, do not optimize performance
- mmSharedPtr->VoltageMap = VDDIO_DETERMINED;
- } else if (PowerPolicy == BatteryLife) {
- ParameterPtr->DDR3Voltage = VDDIO;
- }
-
- IDS_OPTION_HOOK (IDS_ENFORCE_VDDIO, &(ParameterPtr->DDR3Voltage), &NBPtr->MemPtr->StdHeader);
-
- if (ParameterPtr->DDR3Voltage != VOLT_UNSUPPORTED) {
- // When Voltage is already determined, do not have further process to choose maximum frequency to optimize performance
- mmSharedPtr->VoltageMap = VDDIO_DETERMINED;
- IDS_HDT_CONSOLE (MEM_STATUS, "VDDIO is determined. No further optimization will be done.\n");
- } else {
- for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
- NBPtr[Node].MaxFreqVDDIO[VOLT1_5] = UNSUPPORTED_DDR_FREQUENCY;
- NBPtr[Node].MaxFreqVDDIO[VOLT1_35] = UNSUPPORTED_DDR_FREQUENCY;
- NBPtr[Node].MaxFreqVDDIO[VOLT1_25] = UNSUPPORTED_DDR_FREQUENCY;
- }
- }
-
- // Reprogram the leveling result
- ParameterPtr->DDR3Voltage = VDDIO;
-
- return RetVal;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Finalize the VDDIO for the board for performance enhancement.
- *
- * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-BOOLEAN
-MemMLvDdr3PerformanceEnhFinalize (
- IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
- )
-{
- UINT8 Dct;
- UINT8 Node;
- UINT8 NodeCnt[VOLT1_25 + 1];
- UINT8 MaxCnt;
- MEM_NB_BLOCK *NBPtr;
- MEM_PARAMETER_STRUCT *ParameterPtr;
- MEM_SHARED_DATA *mmSharedPtr;
- DIMM_VOLTAGE CurrentVoltage;
- DIMM_VOLTAGE Voltage;
- MEMORY_BUS_SPEED HighestFreq;
-
- ParameterPtr = MemMainPtr->MemPtr->ParameterListPtr;
- mmSharedPtr = MemMainPtr->mmSharedPtr;
- NBPtr = MemMainPtr->NBPtr;
-
- LibAmdMemFill (NodeCnt, 0, VOLT1_25 + 1, &NBPtr->MemPtr->StdHeader);
- if (mmSharedPtr->VoltageMap != VDDIO_DETERMINED) {
- Voltage = ParameterPtr->DDR3Voltage;
- for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
- HighestFreq = 0;
- // Find out what the highest frequency that can be reached is on this node across different voltage.
- for (CurrentVoltage = VOLT1_5; CurrentVoltage <= VOLT1_25; CurrentVoltage ++) {
- if (HighestFreq < NBPtr[Node].MaxFreqVDDIO[CurrentVoltage]) {
- HighestFreq = NBPtr[Node].MaxFreqVDDIO[CurrentVoltage];
- }
- }
- // Figure out what voltage we can have when attaining the highest frequency.
- for (CurrentVoltage = VOLT1_5; CurrentVoltage <= VOLT1_25; CurrentVoltage ++) {
- if (NBPtr[Node].MaxFreqVDDIO[CurrentVoltage] == HighestFreq) {
- NodeCnt[CurrentVoltage] ++;
- }
- }
- }
- MaxCnt = 0;
- // Use the VDDIO at which most nodes can run at higher frequency
- for (CurrentVoltage = VOLT1_5; CurrentVoltage <= VOLT1_25; CurrentVoltage ++) {
- if (MaxCnt <= NodeCnt[CurrentVoltage]) {
- MaxCnt = NodeCnt[CurrentVoltage];
- ParameterPtr->DDR3Voltage = CurrentVoltage;
- }
- }
-
- mmSharedPtr->VoltageMap = VDDIO_DETERMINED;
- if (Voltage != ParameterPtr->DDR3Voltage) {
- // Finalize frequency with updated finalized VDDIO
- for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
- // Need to re-sync target speed and different VDDIO may cause different settings
- NBPtr[Node].TechPtr->SpdGetTargetSpeed (NBPtr[Node].TechPtr);
- for (Dct = 0; Dct < NBPtr[Node].DctCount; Dct++) {
- NBPtr[Node].SwitchDCT (&(NBPtr[Node]), Dct);
- if (NBPtr[Node].DCTPtr->Timings.CsEnabled != 0) {
- if (!NBPtr[Node].PlatformSpec (&(NBPtr[Node]))) {
- return FALSE;
- }
- }
- }
- }
- }
- }
- return TRUE;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Main/mmMemClr.c b/src/vendorcode/amd/agesa/Proc/Mem/Main/mmMemClr.c
deleted file mode 100644
index 55eb5a6..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Main/mmMemClr.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mmMemclr.c
- *
- * Main Memory Feature implementation file for Memory Clear.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Main)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-#include "AGESA.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "Ids.h"
-#include "mfmemclr.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_MAIN_MMMEMCLR_FILECODE
-/*-----------------------------------------------------------------------------
-* EXPORTED FUNCTIONS
-*
-*-----------------------------------------------------------------------------
-*/
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * Initiates/synchronizes memory clear on all nodes with Dram on it.
- *
- * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-BOOLEAN
-MemMMctMemClr (
- IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
- )
-{
- UINT8 Node;
- UINT8 NodeCnt;
- BOOLEAN RetVal;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = MemMainPtr->NBPtr;
- NodeCnt = MemMainPtr->DieCount;
- RetVal = TRUE;
-
- IDS_OPTION_HOOK (IDS_BEFORE_MEMCLR, NULL, &NBPtr->MemPtr->StdHeader);
-
- for (Node = 0; Node < NodeCnt; Node++) {
- MemFMctMemClr_Init (&NBPtr[Node]);
- }
-
- for (Node = 0; Node < NodeCnt; Node++) {
- MemFMctMemClr_Sync (&NBPtr[Node]);
- RetVal &= (BOOLEAN) (NBPtr[Node].MCTPtr->ErrCode < AGESA_FATAL);
- }
-
- return RetVal;
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Main/mmMemRestore.c b/src/vendorcode/amd/agesa/Proc/Mem/Main/mmMemRestore.c
deleted file mode 100644
index 3038436..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Main/mmMemRestore.c
+++ /dev/null
@@ -1,597 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mmMemRestore.c
- *
- * Main Memory Feature implementation file for Node Interleaving
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Main)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "Ids.h"
-#include "S3.h"
-#include "mfs3.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_MAIN_MMMEMRESTORE_FILECODE
-
-#define ST_PRE_ESR 0
-#define ST_POST_ESR 1
-#define ST_DONE 2
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemMRestoreDqsTimings (
- IN VOID *Storage,
- IN MEM_MAIN_DATA_BLOCK *MemMainPtr
- );
-
-BOOLEAN
-STATIC
-MemMSetCSRNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN PCI_SPECIAL_CASE *SpecialCases,
- IN PCI_ADDR PciAddr,
- IN UINT32 Value
- );
-
-VOID
-STATIC
-MemMCreateS3NbBlock (
- IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr,
- OUT S3_MEM_NB_BLOCK **S3NBPtr
- );
-/*-----------------------------------------------------------------------------
-* EXPORTED FUNCTIONS
-*
-*-----------------------------------------------------------------------------
-*/
-extern MEM_NB_SUPPORT memNBInstalled[];
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Check and save memory context if possible.
- *
- * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK
- *
- */
-VOID
-MemMContextSave (
- IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
- )
-{
- UINT8 Node;
- UINT8 i;
- MEM_PARAMETER_STRUCT *RefPtr;
- LOCATE_HEAP_PTR LocHeap;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
- DEVICE_BLOCK_HEADER *DeviceList;
- AMD_CONFIG_PARAMS *StdHeader;
- UINT32 BufferSize;
- UINT64 BufferOffset;
- MEM_NB_BLOCK *NBArray;
- S3_MEM_NB_BLOCK *S3NBPtr;
- DESCRIPTOR_GROUP DeviceDescript[MAX_NODES_SUPPORTED];
-
- NBArray = MemMainPtr->NBPtr;
- RefPtr = NBArray[BSP_DIE].RefPtr;
-
- if (RefPtr->SaveMemContextCtl) {
- RefPtr->MemContext.NvStorage = NULL;
- RefPtr->MemContext.NvStorageSize = 0;
-
- // Make sure DQS training has occurred before saving memory context
- if (!RefPtr->MemRestoreCtl) {
- StdHeader = &MemMainPtr->MemPtr->StdHeader;
-
- MemMCreateS3NbBlock (MemMainPtr, &S3NBPtr);
- if (S3NBPtr != NULL) {
- // Get the mask bit and the register list for node that presents
- BufferSize = 0;
- for (Node = 0; Node < MemMainPtr->DieCount; Node ++) {
- S3NBPtr->MemS3GetConPCIMask (&NBArray[Node], (VOID *)&DeviceDescript[Node]);
- S3NBPtr->MemS3GetConMSRMask (&NBArray[Node], (VOID *)&DeviceDescript[Node]);
- BufferSize += S3NBPtr->MemS3GetRegLstPtr (&NBArray[Node], (VOID *)&DeviceDescript[Node]);
- }
-
- // Base on the size of the device list, apply for a buffer for it.
- AllocHeapParams.RequestedBufferSize = (UINT32) (BufferSize + sizeof (DEVICE_BLOCK_HEADER));
- AllocHeapParams.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
- AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
- if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
- DeviceList = (DEVICE_BLOCK_HEADER *) AllocHeapParams.BufferPtr;
- DeviceList->RelativeOrMaskOffset = (UINT16) AllocHeapParams.RequestedBufferSize;
-
- // Copy device list on the stack to the heap.
- BufferOffset = sizeof (DEVICE_BLOCK_HEADER) + (UINT64) AllocHeapParams.BufferPtr;
- for (Node = 0; Node < MemMainPtr->DieCount; Node ++) {
- for (i = PRESELFREF; i <= POSTSELFREF; i ++) {
- // Copy PCI device descriptor to the heap if it exists.
- if (DeviceDescript[Node].PCIDevice[i].RegisterListID != 0xFFFFFFFF) {
- LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Node].PCIDevice[i]), sizeof (PCI_DEVICE_DESCRIPTOR), StdHeader);
- DeviceList->NumDevices ++;
- BufferOffset += sizeof (PCI_DEVICE_DESCRIPTOR);
- }
- // Copy conditional PCI device descriptor to the heap if it exists.
- if (DeviceDescript[Node].CPCIDevice[i].RegisterListID != 0xFFFFFFFF) {
- LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Node].CPCIDevice[i]), sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR), StdHeader);
- DeviceList->NumDevices ++;
- BufferOffset += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR);
- }
- // Copy MSR device descriptor to the heap if it exists.
- if (DeviceDescript[Node].MSRDevice[i].RegisterListID != 0xFFFFFFFF) {
- LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Node].MSRDevice[i]), sizeof (MSR_DEVICE_DESCRIPTOR), StdHeader);
- DeviceList->NumDevices ++;
- BufferOffset += sizeof (MSR_DEVICE_DESCRIPTOR);
- }
- // Copy conditional MSR device descriptor to the heap if it exists.
- if (DeviceDescript[Node].CMSRDevice[i].RegisterListID != 0xFFFFFFFF) {
- LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Node].PCIDevice[i]), sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR), StdHeader);
- DeviceList->NumDevices ++;
- BufferOffset += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR);
- }
- }
- }
-
- // Determine size needed
- BufferSize = GetWorstCaseContextSize (DeviceList, INIT_RESUME, StdHeader);
- AllocHeapParams.RequestedBufferSize = BufferSize;
- AllocHeapParams.BufferHandle = AMD_S3_SAVE_HANDLE;
- AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
- if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
- // Save memory context
- SaveDeviceListContext (DeviceList, AllocHeapParams.BufferPtr, INIT_RESUME, &BufferSize, StdHeader);
- RefPtr->MemContext.NvStorageSize = BufferSize;
- }
-
- HeapDeallocateBuffer (AMD_MEM_S3_DATA_HANDLE, StdHeader);
- }
- }
- HeapDeallocateBuffer (AMD_MEM_S3_NB_HANDLE, StdHeader);
-
- // Locate MemContext since it might have been shifted after deallocating
- LocHeap.BufferHandle = AMD_S3_SAVE_HANDLE;
- if (HeapLocateBuffer (&LocHeap, StdHeader) == AGESA_SUCCESS) {
- RefPtr->MemContext.NvStorage = LocHeap.BufferPtr;
- }
- }
- }
-
- for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
- NBArray[Node].FamilySpecificHook[AfterSaveRestore] (&NBArray[Node], &NBArray[Node]);
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Check and restore memory context if possible.
- *
- * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK
- *
- * @return TRUE - DQS timing restore succeeds.
- * @return FALSE - DQS timing restore fails.
- */
-BOOLEAN
-MemMContextRestore (
- IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
- )
-{
- UINT8 Node;
- MEM_NB_BLOCK *NBArray;
- MEM_PARAMETER_STRUCT *RefPtr;
- S3_MEM_NB_BLOCK *S3NBPtr;
-
- NBArray = MemMainPtr->NBPtr;
- RefPtr = NBArray[BSP_DIE].RefPtr;
-
- IDS_HDT_CONSOLE (MEM_STATUS, "\nStart Mem Restore\n");
- if (RefPtr->MemRestoreCtl) {
- if (RefPtr->MemContext.NvStorage != NULL) {
- MemMCreateS3NbBlock (MemMainPtr, &S3NBPtr);
- if (S3NBPtr != NULL) {
- // Check DIMM config and restore DQS timings if possible
- if (!MemMRestoreDqsTimings (RefPtr->MemContext.NvStorage, MemMainPtr)) {
- RefPtr->MemRestoreCtl = FALSE;
- }
- } else {
- RefPtr->MemRestoreCtl = FALSE;
- }
- HeapDeallocateBuffer (AMD_MEM_S3_NB_HANDLE, &(MemMainPtr->MemPtr->StdHeader));
- } else {
- RefPtr->MemRestoreCtl = FALSE;
- }
- }
-
- for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
- NBArray[Node].FamilySpecificHook[AfterSaveRestore] (&NBArray[Node], &NBArray[Node]);
- }
- IDS_HDT_CONSOLE (MEM_FLOW, RefPtr->MemRestoreCtl ? "Mem Restore Succeeds!\n" : "Mem Restore Fails!\n");
- return RefPtr->MemRestoreCtl;
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Restores all devices that contains DQS timings
- *
- * @param[in] Storage Beginning of the device list.
- * @param[in,out] MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- *
- */
-BOOLEAN
-STATIC
-MemMRestoreDqsTimings (
- IN VOID *Storage,
- IN MEM_MAIN_DATA_BLOCK *MemMainPtr
- )
-{
- AMD_CONFIG_PARAMS *StdHeader;
- UINT8 *OrMask;
- DEVICE_DESCRIPTORS Device;
- INT16 i;
- INT16 j;
- DEVICE_BLOCK_HEADER *DeviceList;
- PCI_REGISTER_BLOCK_HEADER *Reg;
- CPCI_REGISTER_BLOCK_HEADER *CReg;
- MSR_REGISTER_BLOCK_HEADER *MsrReg;
- CMSR_REGISTER_BLOCK_HEADER *CMsrReg;
- PCI_ADDR PciAddress;
- MEM_NB_BLOCK *NBArray;
- UINT8 State;
- UINT8 Node;
- UINT8 Dct;
- UINT8 MaxNode;
-
- NBArray = MemMainPtr->NBPtr;
- StdHeader = &(MemMainPtr->MemPtr->StdHeader);
- DeviceList = (DEVICE_BLOCK_HEADER *) Storage;
- Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1];
- OrMask = (UINT8 *) DeviceList + DeviceList->RelativeOrMaskOffset;
-
- if (DeviceList->NumDevices == 0) {
- return FALSE;
- }
-
- MaxNode = 0;
- State = ST_PRE_ESR;
- for (i = 0; State != ST_DONE; i++) {
- if (((State == ST_PRE_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_PCI_PRE_ESR)) ||
- ((State == ST_POST_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_PCI))) {
- MemFS3GetPciDeviceRegisterList (Device.PciDevice, &Reg, StdHeader);
- Node = Device.PciDevice->Node;
- IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Node);
- PciAddress = NBArray[Node].PciAddr;
- for (j = 0; j < Reg->NumRegisters; j++) {
- PciAddress.Address.Function = Reg->RegisterList[j].Function;
- PciAddress.Address.Register = Reg->RegisterList[j].Offset;
- PciAddress.Address.Segment = (Reg->RegisterList[j].Type.SpecialCaseFlag != 0) ?
- 0xF - Reg->RegisterList[j].Type.SpecialCaseIndex : 0;
- if (!MemMSetCSRNb (&NBArray[Node], Reg->SpecialCases, PciAddress, *((UINT32 *) OrMask) & Reg->RegisterList[j].AndMask)) {
- return FALSE; // Restore fails
- }
- OrMask += (Reg->RegisterList[j].Type.RegisterSize == 0) ? 4 : Reg->RegisterList[j].Type.RegisterSize;
- }
-
- if (MaxNode < Node) {
- MaxNode = Node;
- }
-
- } else if (((State == ST_PRE_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_CPCI_PRE_ESR)) ||
- ((State == ST_POST_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_CPCI))) {
- MemFS3GetCPciDeviceRegisterList (Device.CPciDevice, &CReg, StdHeader);
- Node = Device.CPciDevice->Node;
- IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Node);
- PciAddress = NBArray[Node].PciAddr;
- for (j = 0; j < CReg->NumRegisters; j++) {
- if (((Device.CPciDevice->Mask1 & CReg->RegisterList[j].Mask1) != 0) &&
- ((Device.CPciDevice->Mask2 & CReg->RegisterList[j].Mask2) != 0)) {
- PciAddress.Address.Function = CReg->RegisterList[j].Function;
- PciAddress.Address.Register = CReg->RegisterList[j].Offset;
- PciAddress.Address.Segment = (CReg->RegisterList[j].Type.SpecialCaseFlag != 0) ?
- 0xF - CReg->RegisterList[j].Type.SpecialCaseIndex : 0;
- if (!MemMSetCSRNb (&NBArray[Node], CReg->SpecialCases, PciAddress, *((UINT32 *) OrMask) & CReg->RegisterList[j].AndMask)) {
- return FALSE; // Restore fails
- }
- OrMask += (CReg->RegisterList[j].Type.RegisterSize == 0) ? 4 : CReg->RegisterList[j].Type.RegisterSize;
- }
- }
- } else if (((State == ST_PRE_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_MSR_PRE_ESR)) ||
- ((State == ST_POST_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_MSR))) {
- MemFS3GetMsrDeviceRegisterList (Device.MsrDevice, &MsrReg, StdHeader);
- for (j = 0; j < MsrReg->NumRegisters; j++) {
- OrMask += 8;
- }
- } else if (((State == ST_PRE_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_CMSR_PRE_ESR)) ||
- ((State == ST_POST_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_CMSR))) {
- MemFS3GetCMsrDeviceRegisterList (Device.CMsrDevice, &CMsrReg, StdHeader);
- for (j = 0; j < CMsrReg->NumRegisters; j++) {
- if (((Device.CMsrDevice->Mask1 & CMsrReg->RegisterList[j].Mask1) != 0) &&
- ((Device.CMsrDevice->Mask2 & CMsrReg->RegisterList[j].Mask2) != 0)) {
- OrMask += 8;
- }
- }
- }
-
- switch (Device.CommonDeviceHeader->Type) {
- case DEV_TYPE_PCI_PRE_ESR:
- // Fall through to advance the pointer after restoring context
- case DEV_TYPE_PCI:
- Device.PciDevice++;
- break;
- case DEV_TYPE_CPCI_PRE_ESR:
- // Fall through to advance the pointer after restoring context
- case DEV_TYPE_CPCI:
- Device.CPciDevice++;
- break;
- case DEV_TYPE_MSR_PRE_ESR:
- // Fall through to advance the pointer after restoring context
- case DEV_TYPE_MSR:
- Device.MsrDevice++;
- break;
- case DEV_TYPE_CMSR_PRE_ESR:
- // Fall through to advance the pointer after restoring context
- case DEV_TYPE_CMSR:
- Device.CMsrDevice++;
- break;
- default:
- ASSERT (FALSE);
- break;
- }
-
- if (i == (DeviceList->NumDevices - 1)) {
- // Go to next state
- State++;
- i = -1;
- Device.CommonDeviceHeader = (DEVICE_DESCRIPTOR *) &DeviceList[1];
-
- // Check to see if processor or DIMM population has changed
- if ((MaxNode + 1) != MemMainPtr->DieCount) {
- IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: Population changed\n");
- return FALSE;
- }
-
- // Perform MemClk frequency change
- for (Node = 0; Node < MemMainPtr->DieCount; Node ++) {
- if (NBArray[Node].MCTPtr->NodeMemSize != 0) {
- NBArray[Node].BeforeDqsTraining (&NBArray[Node]);
- if (NBArray[Node].DCTPtr->Timings.Speed < NBArray[Node].DCTPtr->Timings.TargetSpeed) {
- for (Dct = 0; Dct < NBArray[Node].DctCount; Dct++) {
- NBArray[Node].SwitchDCT (&NBArray[Node], Dct);
- NBArray[Node].DCTPtr->Timings.Speed = NBArray[Node].DCTPtr->Timings.TargetSpeed;
- }
- IDS_OPTION_HOOK (IDS_BEFORE_MEM_FREQ_CHG, &NBArray[Node], &(MemMainPtr->MemPtr->StdHeader));
- NBArray[Node].ChangeFrequency (&NBArray[Node]);
- }
- }
- }
- }
- }
-
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function filters out other settings and only restores DQS timings.
- *
- * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] SpecialCases - Pointer to special cases array handlers
- * @param[in] PciAddr - address of the CSR register in PCI_ADDR format.
- * @param[in] Value - Value to be programmed
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- *
- */
-
-BOOLEAN
-STATIC
-MemMSetCSRNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN PCI_SPECIAL_CASE *SpecialCases,
- IN PCI_ADDR PciAddr,
- IN UINT32 Value
- )
-{
- UINT32 Offset;
- UINT8 Dct;
- UINT32 Temp;
- BOOLEAN RetVal;
- UINT32 BOffset;
-
- RetVal = TRUE;
- if (PciAddr.Address.Segment != 0) {
- if (PciAddr.Address.Segment == 0xF) {
- PciAddr.Address.Segment = 0;
- Dct = (UINT8) ((PciAddr.Address.Register >> 10) & 1);
- Offset = PciAddr.Address.Register & 0x3FF;
- BOffset = PciAddr.Address.Register & 0xFF;
- if ((PciAddr.Address.Register & 0x800) == 0) {
- if (((BOffset >= 1) && (BOffset <= 3)) ||
- ((BOffset >= 5) && (BOffset <= 7)) ||
- ((Offset >= 0x10) && (Offset <= 0x2B)) ||
- ((Offset >= 0x30) && (Offset <= 0x4A))) {
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\tF2_%d9C_%03x = %08x\n", Dct, Offset, Value);
- //MemNS3SetCSR
- SpecialCases[0].Restore (AccessS3SaveWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
- }
- }
- }
- } else {
- Dct = (UINT8) ((PciAddr.Address.Register >> 8) & 1);
- Offset = PciAddr.Address.Register & 0xFF;
-
- if (PciAddr.Address.Function == 2) {
- if ((Offset >= 0x40) && (Offset < 0x60) && ((Value & 4) != 0)) {
- // If TestFail bit is set, set CsTestFail
- NBPtr->SwitchDCT (NBPtr, Dct);
- NBPtr->DCTPtr->Timings.CsTrainFail |= (UINT16)1 << ((Offset - 0x40) >> 2);
- IDS_HDT_CONSOLE (MEM_FLOW, "\tBad CS:%d\n", ((Offset - 0x40) >> 2));
- } else if (Offset == 0x80) {
- LibAmdPciRead (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader);
- if (Temp != Value) {
- IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: DIMM config changed\n");
- RetVal = FALSE;
- }
- } else if (Offset == 0x90) {
- LibAmdPciRead (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader);
- if ((Temp & 0x0001F000) != (Value & 0x0001F000)) {
- IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: DIMM config changed\n");
- RetVal = FALSE;
- }
- } else if (Offset == 0x94) {
- LibAmdPciRead (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader);
- if ((Temp & 0x00061000) != (Value & 0x00061000)) {
- IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: DIMM config changed\n");
- RetVal = FALSE;
- }
- if (((Value & 0x4000) == 0) && (NBPtr->GetMemClkFreqId (NBPtr, NBPtr->DCTPtr->Timings.TargetSpeed) != ((Value & 7) + 1))) {
- IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: MemClk has changed\n");
- RetVal = FALSE;
- }
- // Restore ZqcsInterval
- Temp &= 0xFFFFF3FF;
- Temp |= (Value & 0x00000C00);
- LibAmdPciWrite (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader);
- } else if (Offset == 0x78) {
- // Program MaxRdLat
- LibAmdPciRead (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader);
- Temp &= 0x0009BF0F;
- Temp |= (Value & 0xFFC00000);
- LibAmdPciWrite (AccessWidth32, PciAddr, &Temp, &NBPtr->MemPtr->StdHeader);
- } else if (PciAddr.Address.Register == 0x110) {
- if ((NBPtr->MCTPtr->NodeMemSize != 0) && (Value == 0x00000100)) {
- IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: DIMM config changed\n");
- RetVal = FALSE;
- }
- }
- }
- }
-
- if (RetVal == FALSE) {
- NBPtr->SwitchDCT (NBPtr, 0);
- NBPtr->DCTPtr->Timings.CsTrainFail = 0;
- NBPtr->SwitchDCT (NBPtr, 1);
- NBPtr->DCTPtr->Timings.CsTrainFail = 0;
- }
-
- return RetVal;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Create S3 NB Block.
- *
- * @param[in,out] MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK
- * @param[out] S3NBPtr - Pointer to the S3 NB Block pointer
- *
- */
-VOID
-STATIC
-MemMCreateS3NbBlock (
- IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr,
- OUT S3_MEM_NB_BLOCK **S3NBPtr
- )
-{
- UINT8 Node;
- UINT8 i;
- MEM_NB_BLOCK *NBArray;
- MEM_NB_BLOCK *DummyNBs;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
- NBArray = MemMainPtr->NBPtr;
-
- *S3NBPtr = NULL;
-
- // Allocate heap for S3 NB Blocks
- AllocHeapParams.RequestedBufferSize = (MemMainPtr->DieCount * (sizeof (S3_MEM_NB_BLOCK) + sizeof (MEM_NB_BLOCK)));
- AllocHeapParams.BufferHandle = AMD_MEM_S3_NB_HANDLE;
- AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
- if (HeapAllocateBuffer (&AllocHeapParams, &(MemMainPtr->MemPtr->StdHeader)) == AGESA_SUCCESS) {
- *S3NBPtr = (S3_MEM_NB_BLOCK *) AllocHeapParams.BufferPtr;
- DummyNBs = (MEM_NB_BLOCK *) (AllocHeapParams.BufferPtr + MemMainPtr->DieCount * sizeof (S3_MEM_NB_BLOCK));
-
- // Initialize S3 NB Blocks
- for (Node = 0; Node < MemMainPtr->DieCount; Node ++) {
- (*S3NBPtr)[Node].NBPtr = &DummyNBs[Node];
-
- for (i = 0; memNBInstalled[i].MemS3ResumeConstructNBBlock != 0; i++) {
- if (memNBInstalled[i].MemS3ResumeConstructNBBlock (&(*S3NBPtr)[Node], NBArray[BSP_DIE].MemPtr, Node)) {
- break;
- }
- };
- if (memNBInstalled[i].MemS3ResumeConstructNBBlock == 0) {
- *S3NBPtr = NULL;
- break;
- }
- }
- }
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Main/mmNodeInterleave.c b/src/vendorcode/amd/agesa/Proc/Mem/Main/mmNodeInterleave.c
deleted file mode 100644
index 066c38f..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Main/mmNodeInterleave.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mmNodeInterleave.c
- *
- * Main Memory Feature implementation file for Node Interleaving
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Main)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-#include "AGESA.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "Ids.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_MAIN_MMNODEINTERLEAVE_FILECODE
-
-extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
-/*-----------------------------------------------------------------------------
-* EXPORTED FUNCTIONS
-*
-*-----------------------------------------------------------------------------
-*/
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Check and enable node interleaving on all nodes.
- *
- * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-BOOLEAN
-MemMInterleaveNodes (
- IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
- )
-{
- UINT8 Node;
- UINT8 NodeCnt;
- BOOLEAN RetVal;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = MemMainPtr->NBPtr;
- NodeCnt = 0;
- RetVal = TRUE;
-
- if (NBPtr->RefPtr->EnableNodeIntlv) {
- if (!MemFeatMain.MemClr (MemMainPtr)) {
- PutEventLog (AGESA_WARNING, MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_WARNING, NBPtr->MCTPtr);
- return FALSE;
- }
-
- MemMainPtr->mmSharedPtr->NodeIntlv.IsValid = FALSE;
- MemMainPtr->mmSharedPtr->NodeIntlv.NodeIntlvSel = 0;
-
- for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
- if (!NBPtr[Node].FeatPtr->CheckInterleaveNodes (&NBPtr[Node])) {
- break;
- }
- if (NBPtr[Node].MCTPtr->NodeMemSize != 0) {
- NodeCnt ++;
- }
- }
-
- if ((Node == MemMainPtr->DieCount) && (NodeCnt != 0) && ((NodeCnt & (NodeCnt - 1)) == 0)) {
- MemMainPtr->mmSharedPtr->NodeIntlv.NodeCnt = NodeCnt;
- for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
- if (NBPtr[Node].MCTPtr->NodeMemSize != 0) {
- NBPtr[Node].FeatPtr->InterleaveNodes (&NBPtr[Node]);
- }
- }
- for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
- NBPtr[Node].SyncAddrMapToAllNodes (&NBPtr[Node]);
- RetVal &= (BOOLEAN) (NBPtr[Node].MCTPtr->ErrCode < AGESA_FATAL);
- }
- } else {
- //
- // If all nodes cannot be interleaved
- //
- PutEventLog (AGESA_WARNING, MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_WARNING, NBPtr->MCTPtr);
- }
- }
-
- return RetVal;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Main/mmOnlineSpare.c b/src/vendorcode/amd/agesa/Proc/Mem/Main/mmOnlineSpare.c
deleted file mode 100644
index f88cc15..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Main/mmOnlineSpare.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mmOnlineSpare.c
- *
- * Main Memory Feature implementation file for Node Interleaving
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Main)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-#include "AGESA.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "Ids.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_MAIN_MMONLINESPARE_FILECODE
-
-/*-----------------------------------------------------------------------------
-* EXPORTED FUNCTIONS
-*
-*-----------------------------------------------------------------------------
-*/
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Check and enable online spare on all nodes.
- *
- * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-BOOLEAN
-MemMOnlineSpare (
- IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
- )
-{
- UINT8 Node;
- BOOLEAN IsEnabled;
- UINT8 FirstEnabledNode;
- UINT32 BottomIO;
- BOOLEAN RetVal;
- MEM_NB_BLOCK *NBPtr;
- MEM_PARAMETER_STRUCT *RefPtr;
-
- AGESA_TESTPOINT (TpProcMemOnlineSpareInit, &(MemMainPtr->MemPtr->StdHeader));
- FirstEnabledNode = 0;
- IsEnabled = FALSE;
- RetVal = TRUE;
- NBPtr = MemMainPtr->NBPtr;
- RefPtr = NBPtr[BSP_DIE].RefPtr;
-
- for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
- if (NBPtr[Node].FeatPtr->OnlineSpare (&NBPtr[Node])) {
- if (!IsEnabled) {
- // Record the first node that has spared dimm enabled
- FirstEnabledNode = Node;
- IsEnabled = TRUE;
- }
- }
- }
-
- if (IsEnabled) {
- NBPtr[BSP_DIE].SharedPtr->CurrentNodeSysBase = 0;
- BottomIO = (NBPtr[BSP_DIE].RefPtr->BottomIo & 0xF8) << 8;
- // If the first node that has spared dimms does not have a system base smaller
- // than bottomIO, then we don't need to reset the GStatus, as we don't need to
- // remap memory hole.
- if (NBPtr[FirstEnabledNode].MCTPtr->NodeSysBase < BottomIO) {
- RefPtr->GStatus[GsbHWHole] = FALSE;
- RefPtr->GStatus[GsbSpIntRemapHole] = FALSE;
- RefPtr->GStatus[GsbSoftHole] = FALSE;
- RefPtr->HoleBase = 0;
- }
-
- for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
- if (Node >= FirstEnabledNode) {
- // Remap memory on nodes with node number larger than the first node that has spared dimms.
- NBPtr[Node].MCTPtr->Status[SbHWHole] = FALSE;
- NBPtr[Node].MCTPtr->Status[SbSWNodeHole] = FALSE;
- NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelBaseAddr, 0);
- NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelHiRngEn, 0);
- NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelHi, 0);
- NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelBaseOffset, 0);
- NBPtr[Node].SetBitField (&NBPtr[Node], BFDramHoleAddrReg, 0);
- NBPtr[Node].HtMemMapInit (&NBPtr[Node]);
- } else {
- // No change is needed in the memory map of this node.
- // Need to adjust the current system base for other nodes processed later.
- NBPtr[Node].SharedPtr->CurrentNodeSysBase = (NBPtr[Node].MCTPtr->NodeSysLimit + 1) & 0xFFFFFFF0;
- // If the current node does not have the memory hole, then set DramHoleAddrReg to be 0.
- // If memory hoisting is enabled later by other node, SyncAddrMapToAllNodes will set the base
- // and DramMemHoistValid.
- // Otherwise, do not change the register value, as we need to keep DramHoleOffset unchanged, as well
- // DramHoleValid.
- if (!NBPtr[Node].MCTPtr->Status[SbHWHole]) {
- NBPtr[Node].SetBitField (&NBPtr[Node], BFDramHoleAddrReg, 0);
- }
- }
- }
-
- for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
- NBPtr[Node].SyncAddrMapToAllNodes (&NBPtr[Node]);
- RetVal &= (BOOLEAN) (NBPtr[Node].MCTPtr->ErrCode < AGESA_FATAL);
- }
- NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE]);
- }
- return RetVal;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Main/mmParallelTraining.c b/src/vendorcode/amd/agesa/Proc/Mem/Main/mmParallelTraining.c
deleted file mode 100644
index f9de5c5..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Main/mmParallelTraining.c
+++ /dev/null
@@ -1,273 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mmNodeInterleave.c
- *
- * Main Memory Feature implementation file for Node Interleaving
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Main)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-#include "Porting.h"
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuServices.h"
-#include "cpuApicUtilities.h"
-#include "GeneralServices.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "ma.h"
-#include "mu.h"
-#include "mfParallelTraining.h"
-#include "GeneralServices.h"
-#include "heapManager.h"
-#include "merrhdl.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_MAIN_MMPARALLELTRAINING_FILECODE
-
-extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
-/*-----------------------------------------------------------------------------
-* EXPORTED FUNCTIONS
-*
-*-----------------------------------------------------------------------------
-*/
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- *
- *
- * @param[in,out] *mmPtr - Pointer to the MEM_MAIN_DATA_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-BOOLEAN
-MemMParallelTraining (
- IN OUT MEM_MAIN_DATA_BLOCK *mmPtr
- )
-{
- AMD_CONFIG_PARAMS *StdHeader;
- MEM_DATA_STRUCT *MemPtr;
- MEM_NB_BLOCK *NBPtr;
- DIE_INFO TrainInfo[MAX_NODES_SUPPORTED];
- AP_DATA_TRANSFER ReturnData;
- AGESA_STATUS Status;
- UINT8 ApSts;
- UINT8 Die;
- UINT8 Socket;
- UINT32 Module;
- UINT32 LowCore;
- UINT32 HighCore;
- UINT32 Time;
- UINT32 TimeOut;
- BOOLEAN StillTraining;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
- UINT8 *BufferPtr;
- BOOLEAN TimeoutEn;
-
- NBPtr = mmPtr->NBPtr;
- MemPtr = mmPtr->MemPtr;
- StdHeader = &(mmPtr->MemPtr->StdHeader);
- Time = 0;
- TimeOut = PARALLEL_TRAINING_TIMEOUT;
- TimeoutEn = TRUE;
- IDS_TIMEOUT_CTL (&TimeoutEn);
-
- IDS_HDT_CONSOLE (MEM_STATUS, "\nStart parallel training\n");
- AGESA_TESTPOINT (TpProcMemBeforeAnyTraining, StdHeader);
- //
- // Initialize Training Info Array
- //
- for (Die = 0; Die < mmPtr->DieCount; Die ++) {
- Socket = TrainInfo[Die].Socket = NBPtr[Die].MCTPtr->SocketId;
- Module = NBPtr[Die].MCTPtr->DieId;
- GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader);
- TrainInfo[Die].Core = (UINT8) (LowCore & 0x000000FF);
- IDS_HDT_CONSOLE (MEM_FLOW, "\tLaunch core %d of socket %d\n", LowCore, Socket);
- TrainInfo[Die].Training = FALSE;
- }
- //
- // Start Training on Each remote die.
- //
- for (Die = 0; Die < mmPtr->DieCount; Die ++ ) {
- if (Die != BSP_DIE) {
- NBPtr[Die].BeforeDqsTraining (&(mmPtr->NBPtr[Die]));
- if (NBPtr[Die].MCTPtr->NodeMemSize != 0) {
- if (!NBPtr[Die].FeatPtr->Training (&(mmPtr->NBPtr[Die]))) {
- // Fail to launch code on AP
- PutEventLog (AGESA_ERROR, MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_ERROR, NBPtr[Die].MCTPtr);
- MemPtr->ErrorHandling (NBPtr[Die].MCTPtr, EXCLUDE_ALL_DCT, EXCLUDE_ALL_CHIPSEL, &MemPtr->StdHeader);
- } else {
- TrainInfo[Die].Training = TRUE;
- }
- }
- }
- }
- //
- // Call training on BSP
- //
- IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", NBPtr[BSP_DIE].Node);
- NBPtr[BSP_DIE].BeforeDqsTraining (&(mmPtr->NBPtr[BSP_DIE]));
- NBPtr[BSP_DIE].TrainingFlow (&(mmPtr->NBPtr[BSP_DIE]));
- NBPtr[BSP_DIE].AfterDqsTraining (&(mmPtr->NBPtr[BSP_DIE]));
-
- //
- // Get Results from remote processors training
- //
- do {
- StillTraining = FALSE;
- for (Die = 0; Die < mmPtr->DieCount; Die ++ ) {
- //
- // For each Die that is training, read the status
- //
- if (TrainInfo[Die].Training == TRUE) {
- ApSts = ApUtilReadRemoteControlByte (TrainInfo[Die].Socket, TrainInfo[Die].Core, StdHeader);
- if ((ApSts & 0x80) == 0) {
- //
- // Allocate buffer for received data
- //
- AllocHeapParams.RequestedBufferSize = (
- sizeof (DIE_STRUCT) +
- NBPtr[Die].DctCount * (
- sizeof (DCT_STRUCT) + (
- NBPtr[Die].ChannelCount * (
- sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK) + (
- (NBPtr[Die].MCTPtr->DctData[0].ChData[0].RowCount *
- NBPtr[Die].MCTPtr->DctData[0].ChData[0].ColumnCount *
- NUMBER_OF_DELAY_TABLES) +
- (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES)
- )
- )
- )
- )
- ) + 3;
- AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, Die, 0, 0);
- AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
- if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
- //
- // Receive Training Results
- //
-
- ReturnData.DataPtr = AllocHeapParams.BufferPtr;
- ReturnData.DataSizeInDwords = (UINT16) AllocHeapParams.RequestedBufferSize / 4;
- ReturnData.DataTransferFlags = 0;
- Status = ApUtilReceiveBuffer (TrainInfo[Die].Socket, TrainInfo[Die].Core, &ReturnData, StdHeader);
- if (Status != AGESA_SUCCESS) {
- SetMemError (Status, NBPtr[Die].MCTPtr);
- }
-
- BufferPtr = AllocHeapParams.BufferPtr;
- LibAmdMemCopy (NBPtr[Die].MCTPtr, BufferPtr, sizeof (DIE_STRUCT), StdHeader);
- BufferPtr += sizeof (DIE_STRUCT);
- LibAmdMemCopy ( NBPtr[Die].MCTPtr->DctData,
- BufferPtr,
- NBPtr[Die].DctCount * (sizeof (DCT_STRUCT) + NBPtr[Die].ChannelCount * sizeof (CH_DEF_STRUCT)),
- StdHeader);
- BufferPtr += NBPtr[Die].DctCount * (sizeof (DCT_STRUCT) + NBPtr[Die].ChannelCount * sizeof (CH_DEF_STRUCT));
- LibAmdMemCopy ( NBPtr[Die].PSBlock,
- BufferPtr,
- NBPtr[Die].DctCount * NBPtr[Die].ChannelCount * sizeof (MEM_PS_BLOCK),
- StdHeader);
- BufferPtr += NBPtr[Die].DctCount * NBPtr[Die].ChannelCount * sizeof (MEM_PS_BLOCK);
- LibAmdMemCopy ( NBPtr[Die].MCTPtr->DctData[0].ChData[0].RcvEnDlys,
- BufferPtr,
- (NBPtr[Die].DctCount * NBPtr[Die].ChannelCount) *
- ((NBPtr[Die].MCTPtr->DctData[0].ChData[0].RowCount *
- NBPtr[Die].MCTPtr->DctData[0].ChData[0].ColumnCount *
- NUMBER_OF_DELAY_TABLES) +
- (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES)
- ),
- StdHeader);
-
- HeapDeallocateBuffer (AllocHeapParams.BufferHandle, StdHeader);
-
- NBPtr[Die].AfterDqsTraining (&(mmPtr->NBPtr[Die]));
- TrainInfo[Die].Training = FALSE;
- } else {
- PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA, NBPtr[Die].Node, 0, 0, 0, StdHeader);
- SetMemError (AGESA_FATAL, NBPtr[Die].MCTPtr);
- ASSERT(FALSE); // Insufficient Heap Space allocation for parallel training buffer
- }
- } else if (ApSts == CORE_IDLE) {
- // AP does not have buffer to transmit to BSP
- // AP fails to locate a buffer for data transfer
- TrainInfo[Die].Training = FALSE;
- } else {
- // Signal to loop through again
- StillTraining = TRUE;
- }
- }
- }
- // Wait for 1 us
- MemUWait10ns (100, NBPtr->MemPtr);
- Time ++;
- } while ((StillTraining) && ((Time < TimeOut) || !TimeoutEn)); // Continue until all Dies are finished
- // if cannot finish in 1 s, do fatal exit
-
- if (StillTraining && TimeoutEn) {
- // Parallel training time out, do fatal exit, as there is at least one AP hangs.
- PutEventLog (AGESA_FATAL, MEM_ERROR_PARALLEL_TRAINING_TIME_OUT, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_FATAL, NBPtr[BSP_DIE].MCTPtr);
- ASSERT(FALSE); // Timeout occurred while still training
- }
-
- for (Die = 0; Die < mmPtr->DieCount; Die ++ ) {
- if (NBPtr[Die].MCTPtr->ErrCode == AGESA_FATAL) {
- return FALSE;
- }
- }
- return TRUE;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Main/mmStandardTraining.c b/src/vendorcode/amd/agesa/Proc/Mem/Main/mmStandardTraining.c
deleted file mode 100644
index f1a6f61..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Main/mmStandardTraining.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mmStandardTraining.c
- *
- * Main Memory Feature implementation file for Standard Training
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Main)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-#include "Porting.h"
-#include "AGESA.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "ma.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_MAIN_MMSTANDARDTRAINING_FILECODE
-
-/*-----------------------------------------------------------------------------
-* EXPORTED FUNCTIONS
-*
-*-----------------------------------------------------------------------------
-*/
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * MemMStandardTraining
- *
- * This function implements standard memory training whereby training functions
- * for all nodes are run by the BSP.
- *
- *
- * @param[in,out] *mmPtr - Pointer to the MEM_MAIN_DATA_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-BOOLEAN
-MemMStandardTraining (
- IN OUT MEM_MAIN_DATA_BLOCK *mmPtr
- )
-{
- UINT8 Die;
- //
- // Run Northbridge-specific Standard Training feature for each die.
- //
- IDS_HDT_CONSOLE (MEM_STATUS, "\nStart serial training\n");
- for (Die = 0 ; Die < mmPtr->DieCount ; Die ++ ) {
- IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", Die);
- AGESA_TESTPOINT (TpProcMemBeforeAnyTraining, &(mmPtr->MemPtr->StdHeader));
- mmPtr->NBPtr[Die].BeforeDqsTraining (&mmPtr->NBPtr[Die]);
- mmPtr->NBPtr[Die].FeatPtr->Training (&mmPtr->NBPtr[Die]);
- mmPtr->NBPtr[Die].AfterDqsTraining (&mmPtr->NBPtr[Die]);
- if (mmPtr->NBPtr[Die].MCTPtr->ErrCode == AGESA_FATAL) {
- break;
- }
- }
- return (BOOLEAN) (Die == mmPtr->DieCount);
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Main/mmUmaAlloc.c b/src/vendorcode/amd/agesa/Proc/Mem/Main/mmUmaAlloc.c
deleted file mode 100644
index 0f03a05..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Main/mmUmaAlloc.c
+++ /dev/null
@@ -1,242 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mmUmaAlloc.c
- *
- * Main Memory Feature implementation file for UMA allocation.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Main)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "heapManager.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "Ids.h"
-#include "mport.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_MAIN_MMUMAALLOC_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/*-----------------------------------------------------------------------------
-* EXPORTED FUNCTIONS
-*
-*-----------------------------------------------------------------------------
-*/
-extern BUILD_OPT_CFG UserOptions;
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * UMA allocation mechanism.
- *
- * @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK
- *
- */
-BOOLEAN
-MemMUmaAlloc (
- IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
- )
-{
- UINT32 TOM;
- UINT32 TOM2;
- UINT32 UmaSize;
- UINT32 TopOfChIntlv;
- UINT32 DctSelHi;
- UINT32 UmaAlignment;
- UINT32 UmaAbove4GBase;
- UINT32 UmaBelow4GBase;
- BOOLEAN DctSelIntLvEn;
- BOOLEAN UmaAbove4GEn;
- S_UINT64 SMsr;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
- UMA_INFO *UmaInfoPtr;
-
- MEM_DATA_STRUCT *MemPtr;
- MEM_NB_BLOCK *NBPtr;
- MEM_PARAMETER_STRUCT *RefPtr;
-
- MemPtr = MemMainPtr->MemPtr;
- NBPtr = &(MemMainPtr->NBPtr[BSP_DIE]);
- RefPtr = NBPtr->RefPtr;
-
- TOM2 = 0;
- SMsr.lo = SMsr.hi = 0;
- UmaAbove4GBase = 0;
- RefPtr->UmaBase = 0;
- UmaAlignment = (UINT32) UserOptions.CfgUmaAlignment;
- UmaAbove4GEn = UserOptions.CfgUmaAbove4G;
- DctSelIntLvEn = (NBPtr->GetBitField (NBPtr, BFDctSelIntLvEn) == 1) ? TRUE : FALSE;
- TopOfChIntlv = NBPtr->GetBitField (NBPtr, BFDctSelBaseAddr) << (27 - 16);
- DctSelHi = NBPtr->GetBitField (NBPtr, BFDctSelHi);
-
- // Allocate heap for UMA_INFO
- AllocHeapParams.RequestedBufferSize = sizeof (UMA_INFO);
- AllocHeapParams.BufferHandle = AMD_UMA_INFO_HANDLE;
- AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
- if (AGESA_SUCCESS != HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader)) {
- ASSERT(FALSE); // Could not allocate heap for Uma information.
- return FALSE;
- }
- UmaInfoPtr = (UMA_INFO *) AllocHeapParams.BufferPtr;
- // Default all the fields of UMA_INFO
- UmaInfoPtr->UmaMode = (UINT8) UMA_NONE;
- UmaInfoPtr->UmaSize = 0;
- UmaInfoPtr->UmaBase = 0;
- UmaInfoPtr->UmaAttributes = 0;
- UmaInfoPtr->MemClock = NBPtr->DCTPtr->Timings.TargetSpeed;
-
- switch (RefPtr->UmaMode) {
- case UMA_NONE:
- UmaSize = 0;
- break;
- case UMA_SPECIFIED:
- UmaSize = RefPtr->UmaSize;
- break;
- case UMA_AUTO:
- UmaSize = NBPtr->GetUmaSize (NBPtr);
- break;
- default:
- UmaSize = 0;
- IDS_ERROR_TRAP;
- }
-
- if (UmaSize != 0) {
- //TOM scaled from [47:0] to [47:16]
- LibAmdMsrRead (TOP_MEM, (UINT64 *)&SMsr, &(NBPtr->MemPtr->StdHeader));
- TOM = (SMsr.lo >> 16) | (SMsr.hi << (32 - 16));
-
- UmaBelow4GBase = (TOM - UmaSize) & UmaAlignment;
- // Initialize Ref->UmaBase to UmaBelow4GBase
- RefPtr->UmaBase = UmaBelow4GBase;
-
- // Uma Above 4G support
- if (UmaAbove4GEn) {
- //TOM2 scaled from [47:0] to [47:16]
- LibAmdMsrRead (TOP_MEM2, (UINT64 *)&SMsr, &(NBPtr->MemPtr->StdHeader));
- TOM2 = (SMsr.lo >> 16) | (SMsr.hi << (32 - 16));
- if (TOM2 != 0) {
- UmaAbove4GBase = (TOM2 - UmaSize) & UmaAlignment;
- //Set UmaAbove4GBase to 0 if UmaAbove4GBase is below 4GB
- if (UmaAbove4GBase < _4GB_RJ16) {
- UmaAbove4GBase = 0;
- }
- if (UmaAbove4GBase != 0) {
- RefPtr->UmaBase = UmaAbove4GBase;
- // 1. TopOfChIntlv == 0 indicates that whole DCT0 and DCT1 memory are interleaved.
- // 2. TopOfChIntlv >= TOM tells us :
- // -All or portion of Uma region that above 4G is NOT interleaved.
- // -Whole Uma region that below 4G is interleaved.
- if (DctSelIntLvEn && (TopOfChIntlv >= TOM)) {
- RefPtr->UmaBase = UmaBelow4GBase;
- }
- }
- }
- }
-
- UmaInfoPtr->UmaMode = (UINT8) (RefPtr->UmaMode);
- UmaInfoPtr->UmaBase = (UINT64) ((UINT64) RefPtr->UmaBase << 16);
-
- if (RefPtr->UmaBase >= _4GB_RJ16) {
- // UmaSize might be extended if it is 128MB or 256MB .. aligned, so update it.
- RefPtr->UmaSize = TOM2 - UmaAbove4GBase;
- // Uma Typing
- MemNSetMTRRUmaRegionUCNb (NBPtr, &UmaAbove4GBase, &TOM2);
- if (DctSelIntLvEn && (TopOfChIntlv == 0)) {
- UmaInfoPtr->UmaAttributes = UMA_ATTRIBUTE_INTERLEAVE | UMA_ATTRIBUTE_ON_DCT0 | UMA_ATTRIBUTE_ON_DCT1;
- } else {
- // Entire UMA region is in the high DCT
- UmaInfoPtr->UmaAttributes = (DctSelHi == 0) ? UMA_ATTRIBUTE_ON_DCT0 : UMA_ATTRIBUTE_ON_DCT1;
- }
- } else {
- // UmaSize might be extended if it is 128MB or 256MB .. aligned, so update it.
- RefPtr->UmaSize = TOM - UmaBelow4GBase;
- // Uma Typing
- NBPtr->UMAMemTyping (NBPtr);
- if (DctSelIntLvEn && ((TopOfChIntlv == 0) || (TopOfChIntlv >= TOM))) {
- UmaInfoPtr->UmaAttributes = UMA_ATTRIBUTE_INTERLEAVE | UMA_ATTRIBUTE_ON_DCT0 | UMA_ATTRIBUTE_ON_DCT1;
- } else {
- if (UmaBelow4GBase >= TopOfChIntlv) {
- // Entire UMA region is in the high DCT
- UmaInfoPtr->UmaAttributes = (DctSelHi == 0) ? UMA_ATTRIBUTE_ON_DCT0 : UMA_ATTRIBUTE_ON_DCT1;
- } else if (TopOfChIntlv >= TOM) {
- // Entire UMA region is in the low DCT
- UmaInfoPtr->UmaAttributes = (DctSelHi == 1) ? UMA_ATTRIBUTE_ON_DCT0 : UMA_ATTRIBUTE_ON_DCT1;
- } else {
- // UMA region is in both DCT0 and DCT1
- UmaInfoPtr->UmaAttributes = UMA_ATTRIBUTE_ON_DCT0 | UMA_ATTRIBUTE_ON_DCT1;
- }
- }
- }
- UmaInfoPtr->UmaSize = (RefPtr->UmaSize) << 16;
- IDS_HDT_CONSOLE (MEM_FLOW, "UMA is allocated:\n\tBase: %x0000\n\tSize: %x0000\n", RefPtr->UmaBase, RefPtr->UmaSize);
- }
-
- return TRUE;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Main/mmflow.c b/src/vendorcode/amd/agesa/Proc/Mem/Main/mmflow.c
deleted file mode 100644
index d3c0541..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Main/mmflow.c
+++ /dev/null
@@ -1,384 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mmflow.c
- *
- * Main Memory Flow Entrypoint file
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Main)
- * @e \$Revision: 35735 $ @e \$Date: 2010-07-29 23:28:32 +0800 (Thu, 29 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuServices.h"
-#include "GeneralServices.h"
-#include "cpuFamilyTranslation.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mu.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_MAIN_MMFLOW_FILECODE
-/* features */
-
-extern MEM_NB_SUPPORT memNBInstalled[];
-extern MEM_TECH_CONSTRUCTOR* memTechInstalled[];
-extern MEM_FEAT_BLOCK_MAIN MemFeatMain;
-extern MEM_FLOW_CFG* memFlowControlInstalled[];
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-VOID
-STATIC
-MemSPDDataProcess (
- IN OUT MEM_DATA_STRUCT *MemPtr
- );
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function is the main memory configuration function for DR DDR3
- *
- * Requirements:
- *
- * Run-Time Requirements:
- * 1. Complete Hypertransport Bus Configuration
- * 2. AmdMemInitDataStructDef must be run to set default values
- * 3. MSR bit to allow access to high PCI regs set on all nodes
- * 4. BSP in Big Real Mode
- * 5. Stack available
- * 6. MCG_CTL=-1, MC4_EN=0 for all CPUs
- * 7. MCi_STS from shutdown/warm reset recorded (if desired) prior to entry
- * 8. All var MTRRs reset to zero
- * 9. State of NB_CFG.DisDatMsk set properly on all CPUs
- *
- * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
- *
- * @return AGESA_STATUS
- * - AGESA_ALERT
- * - AGESA_FATAL
- * - AGESA_SUCCESS
- * - AGESA_WARNING
- */
-AGESA_STATUS
-AmdMemAuto (
- IN OUT MEM_DATA_STRUCT *MemPtr
- )
-{
- MEM_SHARED_DATA mmSharedData;
- MEM_MAIN_DATA_BLOCK mmData;
- MEM_NB_BLOCK *NBPtr;
- MEM_TECH_BLOCK *TechPtr;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
- AGESA_STATUS Retval;
- UINT8 i;
- UINT8 Die;
- UINT8 DieCount;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
-
- ASSERT (MemPtr != NULL);
-
- AGESA_TESTPOINT (TpProcMemAmdMemAuto, &MemPtr->StdHeader);
-
- IDS_HDT_CONSOLE (MEM_FLOW, "MEM PARAMS:\n");
- IDS_HDT_CONSOLE (MEM_FLOW, "\tBottomIo : %04x\n", MemPtr->ParameterListPtr->BottomIo);
- IDS_HDT_CONSOLE (MEM_FLOW, "\tMemHoleRemap : %d\n", MemPtr->ParameterListPtr->MemHoleRemapping);
- IDS_HDT_CONSOLE (MEM_FLOW, "\tUserTimingMode : %d\n", MemPtr->ParameterListPtr->UserTimingMode);
- IDS_HDT_CONSOLE (MEM_FLOW, "\tMemClockValue : %d\n", MemPtr->ParameterListPtr->MemClockValue);
- IDS_HDT_CONSOLE (MEM_FLOW, "\tBankIntlv : %d\n", MemPtr->ParameterListPtr->EnableBankIntlv);
- IDS_HDT_CONSOLE (MEM_FLOW, "\tNodeIntlv : %d\n", MemPtr->ParameterListPtr->EnableNodeIntlv);
- IDS_HDT_CONSOLE (MEM_FLOW, "\tChannelIntlv : %d\n", MemPtr->ParameterListPtr->EnableChannelIntlv);
- IDS_HDT_CONSOLE (MEM_FLOW, "\tEccFeature : %d\n", MemPtr->ParameterListPtr->EnableEccFeature);
- IDS_HDT_CONSOLE (MEM_FLOW, "\tPowerDown : %d\n", MemPtr->ParameterListPtr->EnablePowerDown);
- IDS_HDT_CONSOLE (MEM_FLOW, "\tOnLineSpare : %d\n", MemPtr->ParameterListPtr->EnableOnLineSpareCtl);
- IDS_HDT_CONSOLE (MEM_FLOW, "\tParity : %d\n", MemPtr->ParameterListPtr->EnableParity);
- IDS_HDT_CONSOLE (MEM_FLOW, "\tBankSwizzle : %d\n", MemPtr->ParameterListPtr->EnableBankSwizzle);
- IDS_HDT_CONSOLE (MEM_FLOW, "\tMemClr : %d\n", MemPtr->ParameterListPtr->EnableMemClr);
- IDS_HDT_CONSOLE (MEM_FLOW, "\tUmaMode : %d\n", MemPtr->ParameterListPtr->UmaMode);
- IDS_HDT_CONSOLE (MEM_FLOW, "\tUmaSize : %d\n", MemPtr->ParameterListPtr->UmaSize);
- IDS_HDT_CONSOLE (MEM_FLOW, "\tMemRestoreCtl : %d\n", MemPtr->ParameterListPtr->MemRestoreCtl);
- IDS_HDT_CONSOLE (MEM_FLOW, "\tSaveMemContextCtl : %d\n\n", MemPtr->ParameterListPtr->SaveMemContextCtl);
-
- //----------------------------------------------------------------------------
- // Get TSC rate, which will be used later in Wait10ns routine
- //----------------------------------------------------------------------------
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, &MemPtr->StdHeader);
- FamilySpecificServices->GetTscRate (FamilySpecificServices, &MemPtr->TscRate, &MemPtr->StdHeader);
-
- //----------------------------------------------------------------------------
- // Read In SPD Data
- //----------------------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemBeforeSpdProcessing, &MemPtr->StdHeader);
- MemSPDDataProcess (MemPtr);
-
- //----------------------------------------------------------------
- // Initialize Main Data Block
- //----------------------------------------------------------------
- mmData.MemPtr = MemPtr;
- mmData.mmSharedPtr = &mmSharedData;
- LibAmdMemFill (&mmSharedData, 0, sizeof (mmSharedData), &MemPtr->StdHeader);
- mmSharedData.DimmExcludeFlag = NORMAL;
- mmSharedData.NodeIntlv.IsValid = FALSE;
- //----------------------------------------------------------------
- // Discover populated CPUs
- //
- //----------------------------------------------------------------
- Retval = MemSocketScan (&mmData);
- if (Retval == AGESA_FATAL) {
- return Retval;
- }
- DieCount = mmData.DieCount;
- //----------------------------------------------------------------
- //
- // Allocate Memory for NB and Tech Blocks
- //
- // NBPtr[Die]----+
- // |
- // V
- // +---+---+---+---+---+---+---+---+
- // | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | NB Blocks
- // +---+---+---+---+---+---+---+---+
- // | | | | | | | |
- // | | | | | | | |
- // v v v v v v v v
- // +---+---+---+---+---+---+---+---+
- // | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | Tech Blocks
- // +---+---+---+---+---+---+---+---+
- //
- //
- //----------------------------------------------------------------
- AllocHeapParams.RequestedBufferSize = (DieCount * (sizeof (MEM_NB_BLOCK) + sizeof (MEM_TECH_BLOCK)));
- AllocHeapParams.BufferHandle = AMD_MEM_AUTO_HANDLE;
- AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
- if (AGESA_SUCCESS != HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader)) {
- ASSERT(FALSE); // NB and Tech Block Heap allocate error
- return AGESA_FATAL;
- }
- NBPtr = (MEM_NB_BLOCK *)AllocHeapParams.BufferPtr;
- TechPtr = (MEM_TECH_BLOCK *) (&NBPtr[DieCount]);
- mmData.NBPtr = NBPtr;
- mmData.TechPtr = TechPtr;
-
- //----------------------------------------------------------------
- // Create NB Blocks
- //
- //----------------------------------------------------------------
- for (Die = 0 ; Die < DieCount ; Die++ ) {
- i = 0;
- while (memNBInstalled[i].MemConstructNBBlock != 0) {
- if (memNBInstalled[i].MemConstructNBBlock (&NBPtr[Die], MemPtr, memNBInstalled[i].MemFeatBlock, &mmSharedData, Die) == TRUE) {
- break;
- }
- i++;
- }
- // Couldn't find a NB which supported this family
- if (memNBInstalled[i].MemConstructNBBlock == 0) {
- return AGESA_FATAL;
- }
- }
- //----------------------------------------------------------------
- // Create Technology Blocks
- //
- //----------------------------------------------------------------
- for (Die = 0 ; Die < DieCount ; Die++ ) {
- i = 0;
- while (memTechInstalled[i] != NULL) {
- if (memTechInstalled[i] (&TechPtr[Die], &NBPtr[Die])) {
- NBPtr[Die].TechPtr = &TechPtr[Die];
- break;
- }
- i++;
- }
- // Couldn't find a Tech block which supported this family
- if (memTechInstalled[i] == NULL) {
- return AGESA_FATAL;
- }
- }
- //----------------------------------------------------------------
- //
- // MEMORY INITIALIZATION TASKS
- //
- //----------------------------------------------------------------
- i = 0;
- while (memFlowControlInstalled[i] != NULL) {
- Retval = memFlowControlInstalled[i] (&mmData);
- if (MemPtr->IsFlowControlSupported == TRUE) {
- break;
- }
- i++;
- }
-
- //----------------------------------------------------------------
- // Check for errors and return
- //----------------------------------------------------------------
- AGESA_TESTPOINT (TpProcMemEnd, &MemPtr->StdHeader);
- for (Die = 0; Die < DieCount; Die++) {
- if (NBPtr[Die].MCTPtr->ErrCode > Retval) {
- Retval = NBPtr[Die].MCTPtr->ErrCode;
- }
- }
- return Retval;
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function fills a default SPD buffer with SPD values for all DIMMs installed in the system
- *
- * The SPD Buffer is populated with a Socket-Channel-Dimm centric view of the Dimms. At this
- * point, the Memory controller type is not known, and the platform BIOS does not know the anything
- * about which DIMM is on which DCT. So the DCT relationship is abstracted from the arrangement
- * of SPD information here. We use the utility functions GetSpdSocketIndex(), GetMaxChannelsPerSocket(),
- * and GetMaxDimmsPerChannel() to Map the SPD data according to which Socket-relative channel the DIMMs
- * are connected to. The functions rely on either the maximum values in the
- * PlatformSpecificOverridingTable or if unspecified, the absolute maximums in AGESA.H.
- *
- * This mapping is translated in the Northbridge object Constructor and the Technology block constructor.
- *
- * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
- *
- */
-
-VOID
-STATIC
-MemSPDDataProcess (
- IN OUT MEM_DATA_STRUCT *MemPtr
- )
-{
- UINT8 Socket;
- UINT8 Channel;
- UINT8 Dimm;
- UINT8 DimmIndex;
- UINT32 AgesaStatus;
- UINT8 MaxSockets;
- UINT8 MaxChannelsPerSocket;
- UINT8 MaxDimmsPerChannel;
- SPD_DEF_STRUCT *DimmSPDPtr;
- PSO_TABLE *PsoTable;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
- AGESA_READ_SPD_PARAMS SpdParam;
-
- ASSERT (MemPtr != NULL);
- MaxSockets = (UINT8) (0x000000FF & GetPlatformNumberOfSockets ());
- PsoTable = MemPtr->ParameterListPtr->PlatformMemoryConfiguration;
- //
- // Allocate heap for the table
- //
- AllocHeapParams.RequestedBufferSize = (GetSpdSocketIndex (PsoTable, MaxSockets, &MemPtr->StdHeader) * sizeof (SPD_DEF_STRUCT));
- AllocHeapParams.BufferHandle = AMD_MEM_SPD_HANDLE;
- AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
- if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) == AGESA_SUCCESS) {
- MemPtr->SpdDataStructure = (SPD_DEF_STRUCT *) AllocHeapParams.BufferPtr;
- //
- // Initialize SpdParam Structure
- //
- LibAmdMemCopy ((VOID *)&SpdParam, (VOID *)MemPtr, (UINTN)sizeof (SpdParam.StdHeader), &MemPtr->StdHeader);
- //
- // Populate SPDDataBuffer
- //
- SpdParam.MemData = MemPtr;
- DimmIndex = 0;
- for (Socket = 0; Socket < (UINT16)MaxSockets; Socket++) {
- MaxChannelsPerSocket = GetMaxChannelsPerSocket (PsoTable, Socket, &MemPtr->StdHeader);
- SpdParam.SocketId = Socket;
- for (Channel = 0; Channel < MaxChannelsPerSocket; Channel++) {
- SpdParam.MemChannelId = Channel;
- MaxDimmsPerChannel = GetMaxDimmsPerChannel (PsoTable, Socket, Channel);
- for (Dimm = 0; Dimm < MaxDimmsPerChannel; Dimm++) {
- SpdParam.DimmId = Dimm;
- DimmSPDPtr = &(MemPtr->SpdDataStructure[DimmIndex++]);
- SpdParam.Buffer = DimmSPDPtr->Data;
- AGESA_TESTPOINT (TpProcMemBeforeAgesaReadSpd, &MemPtr->StdHeader);
- AgesaStatus = AgesaReadSpd (0, &SpdParam);
- AGESA_TESTPOINT (TpProcMemAfterAgesaReadSpd, &MemPtr->StdHeader);
- if (AgesaStatus == AGESA_SUCCESS) {
- DimmSPDPtr->DimmPresent = TRUE;
- IDS_HDT_CONSOLE (MEM_FLOW, "SPD Socket %d Channel %d Dimm %d: %08x\n", Socket, Channel, Dimm, SpdParam.Buffer);
- } else {
- DimmSPDPtr->DimmPresent = FALSE;
- }
- }
- }
- }
- } else {
- PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_SPD, NULL, NULL, NULL, NULL, &MemPtr->StdHeader);
- //
- // Assert here if unable to allocate heap for SPDs
- //
- IDS_ERROR_TRAP;
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Main/mmlvddr3.h b/src/vendorcode/amd/agesa/Proc/Mem/Main/mmlvddr3.h
deleted file mode 100644
index a346b13..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Main/mmlvddr3.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mmLvDdr3.h
- *
- * Main low voltage DDR3 support common header
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Main)
- * @e \$Revision: 37291 $ @e \$Date: 2010-09-01 13:55:44 -0500 (Wed, 01 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MMLVDDR3_H_
-#define _MMLVDDR3_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-MemMLvDdr3PerformanceEnhPre (
- IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
- );
-
-BOOLEAN
-MemMLvDdr3PerformanceEnhFinalize (
- IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
- );
-#endif /* _MMLVDDR3_H_ */
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Main/mu.asm b/src/vendorcode/amd/agesa/Proc/Mem/Main/mu.asm
deleted file mode 100644
index 63c85b9..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Main/mu.asm
+++ /dev/null
@@ -1,497 +0,0 @@
-;*****************************************************************************
-; AMD Generic Encapsulated Software Architecture
-;
-; $Workfile:: mu.asm $ $Revision:: 274#$ $Date: 2010-03-04 06:16:56 +0800 (Thu, 04 Mar 2010) $
-; Description: Main memory controller system configuration for AGESA
-;
-;
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-;============================================================================
-
-
- .XLIST
- .LIST
-
- .686p
- .MODEL FLAT
- .CODE
- ASSUME FS: NOTHING
-
-; Define the calling convention used for the C library modules
-;@attention - This should be in a central include file
-CALLCONV EQU NEAR C
-
-
-;===============================================================================
-;memUOutPort:
-;
-; Do a 32 Bit IO Out operation using edx.
-; NOTE: This function will be obsolete in the future.
-;
-; In: Port - port number
-; Value - value to be written
-;
-; Out:
-;
-; All registers preserved.
-;===============================================================================
-MemUOutPort PROC CALLCONV PUBLIC Port:DWORD, Value:DWORD
- pushad
- mov edx,Port
- mov eax,Value
- out dx,al
- popad
- ret
-MemUOutPort ENDP
-
-
-;----------------------------------------------------------------------------
-; _SFENCE();
-;
-_SFENCE macro
- db 0Fh,0AEh,0F8h
- endm
-
-;----------------------------------------------------------------------------
-; _MFENCE();
-;
-_MFENCE macro
- db 0Fh,0AEh,0F0h
- endm
-
-;----------------------------------------------------------------------------
-; _EXECFENCE();
-;
-_EXECFENCE macro
- out 0EDh,al ;prevent speculative execution of following instructions
- endm
-
-;===============================================================================
-;MemUWriteCachelines:
-; Write a test pattern to DRAM
-;
-; In: Pattern - pointer to the write pattern
-; Address - Physical address to be read
-; ClCount - number of cachelines to be read
-; Out:
-;
-;All registers preserved.
-;===============================================================================
-MemUWriteCachelines PROC CALLCONV PUBLIC Address:DWORD, Pattern:NEAR PTR DWORD, ClCount:WORD
- pushad
- push ds
-
- mov eax,Address
- push ss
- pop ds
- xor edx,edx
- mov edx, DWORD PTR Pattern
- mov esi,edx
- mov edx,16
- _EXECFENCE
- xor ecx, ecx
- mov cx,ClCount
- shl ecx,2
- @@:
- db 66h, 0Fh,6Fh,06 ;MOVDQA xmm0,[esi]
- db 64h, 66h, 0Fh,0E7h,00 ;MOVNTDQ fs:[eax],xmm0 (xmm0 is 128 bits)
- add eax,edx
- add esi,edx
- loop @B
-
- pop ds
- popad
- ret
-MemUWriteCachelines ENDP
-
-;===============================================================================
-;MemUReadCachelines:
-;
-; Read a pattern of 72 bit times (per DQ), to test dram functionality. The
-;pattern is a stress pattern which exercises both ISI and crosstalk. The number
-;of cache lines to fill is dependent on DCT width mode and burstlength.
-;
-; In: Buffer - pointer to a buffer where read data will be stored
-; Address - Physical address to be read
-; ClCount - number of cachelines to be read
-; Out:
-;
-;All registers preserved.
-;===============================================================================
-MemUReadCachelines PROC CALLCONV PUBLIC Buffer:NEAR PTR DWORD, Address:DWORD, ClCount:WORD
-LOCAL Count:BYTE
- pushad
- ; First, issue continuous dummy reads to fill up the cache
- mov eax,Address
- .if (ClCount > 18)
- mov cx,ClCount
- shr cx,4
- mov Count,cl
- .while (Count != 0)
- push eax
- mov edi,eax
- add edi,128 ;bias value (to account for signed displacement)
- ;clflush opcode=0F AE /7
- mov esi,edi
- mov ebx,esi
- mov ecx,esi
- mov edx,esi
- add edi,4*64 ;TestAddr+4 cache lines
- add ebx,8*64 ;TestAddr+8 cache lines
- add ecx,12*64 ;TestAddr+12 cache lines
- add edx,16*64 ;TestAddr+16 cache lines
- sub edx,128
- _EXECFENCE
- mov eax,fs:[esi-128] ;TestAddr
- _MFENCE
- mov eax,fs:[esi-64] ;TestAddr+1 cache line
- _MFENCE
- mov eax,fs:[esi] ;TestAddr+2 cache lines
- _MFENCE
- mov eax,fs:[esi+64] ;TestAddr+3 cache lines
- _MFENCE
- mov eax,fs:[edi-128] ;TestAddr+4 cache lines
- _MFENCE
- mov eax,fs:[edi-64] ;TestAddr+5 cache lines
- _MFENCE
- mov eax,fs:[edi] ;TestAddr+6 cache lines
- _MFENCE
- mov eax,fs:[edi+64] ;TestAddr+7 cache lines
- _MFENCE
- mov eax,fs:[ebx-128] ;TestAddr+8 cache lines
- _MFENCE
- mov eax,fs:[ebx-64] ;TestAddr+9 cache lines
- _MFENCE
- mov eax,fs:[ebx] ;TestAddr+10 cache lines
- _MFENCE
- mov eax,fs:[ebx+64] ;TestAddr+11 cache lines
- _MFENCE
- mov eax,fs:[ecx-128] ;TestAddr+12 cache lines
- _MFENCE
- mov eax,fs:[ecx-64] ;TestAddr+13 cache lines
- _MFENCE
- mov eax,fs:[ecx] ;TestAddr+14 cache lines
- _MFENCE
- mov eax,fs:[ecx+64] ;TestAddr+15 cache lines
- _MFENCE
- pop eax
- add eax,(16*64) ;Next 16CL
- dec Count
- .endw
- .else
- mov edi,eax
- add edi,128 ;bias value (to account for signed displacement)
- ;clflush opcode=0F AE /7
- mov esi,edi
- mov ebx,esi
- mov ecx,esi
- mov edx,esi
- add edi,4*64 ;TestAddr+4 cache lines
- add ebx,8*64 ;TestAddr+8 cache lines
- add ecx,12*64 ;TestAddr+12 cache lines
- add edx,16*64 ;TestAddr+16 cache lines
- sub edx,128
- .if(ClCount == 1)
- _MFENCE
- mov eax,fs:[esi-128] ;TestAddr
- _MFENCE
- .elseif(ClCount == 3)
- _EXECFENCE
- mov eax,fs:[esi-128] ;TestAddr
- _MFENCE
- mov eax,fs:[esi-64] ;TestAddr+1 cache line
- _MFENCE
- mov eax,fs:[esi] ;TestAddr+2 cache lines
- _MFENCE
- .elseif(ClCount == 6)
- _EXECFENCE
- mov eax,fs:[esi-128] ;TestAddr
- _MFENCE
- mov eax,fs:[esi-64] ;TestAddr+1 cache line
- _MFENCE
- mov eax,fs:[esi] ;TestAddr+2 cache lines
- _MFENCE
- mov eax,fs:[esi+64] ;TestAddr+3 cache lines
- _MFENCE
- mov eax,fs:[edi-128] ;TestAddr+4 cache lines
- _MFENCE
- mov eax,fs:[edi-64] ;TestAddr+5 cache lines
- _MFENCE
- .elseif(ClCount == 9)
- _EXECFENCE
- mov eax,fs:[esi-128] ;TestAddr
- _MFENCE
- mov eax,fs:[esi-64] ;TestAddr+1 cache line
- _MFENCE
- mov eax,fs:[esi] ;TestAddr+2 cache lines
- _MFENCE
- mov eax,fs:[esi+64] ;TestAddr+3 cache lines
- _MFENCE
- mov eax,fs:[edi-128] ;TestAddr+4 cache lines
- _MFENCE
- mov eax,fs:[edi-64] ;TestAddr+5 cache lines
- _MFENCE
- mov eax,fs:[edi] ;TestAddr+6 cache lines
- _MFENCE
- mov eax,fs:[edi+64] ;TestAddr+7 cache lines
- _MFENCE
- mov eax,fs:[ebx-128] ;TestAddr+8 cache lines
- _MFENCE
- .elseif(ClCount == 18)
- _EXECFENCE
- mov eax,fs:[esi-128] ;TestAddr
- _MFENCE
- mov eax,fs:[esi-64] ;TestAddr+1 cache line
- _MFENCE
- mov eax,fs:[esi] ;TestAddr+2 cache lines
- _MFENCE
- mov eax,fs:[esi+64] ;TestAddr+3 cache lines
- _MFENCE
- mov eax,fs:[edi-128] ;TestAddr+4 cache lines
- _MFENCE
- mov eax,fs:[edi-64] ;TestAddr+5 cache lines
- _MFENCE
- mov eax,fs:[edi] ;TestAddr+6 cache lines
- _MFENCE
- mov eax,fs:[edi+64] ;TestAddr+7 cache lines
- _MFENCE
- mov eax,fs:[ebx-128] ;TestAddr+8 cache lines
- _MFENCE
- mov eax,fs:[ebx-64] ;TestAddr+9 cache lines
- _MFENCE
- mov eax,fs:[ebx] ;TestAddr+10 cache lines
- _MFENCE
- mov eax,fs:[ebx+64] ;TestAddr+11 cache lines
- _MFENCE
- mov eax,fs:[ecx-128] ;TestAddr+12 cache lines
- _MFENCE
- mov eax,fs:[ecx-64] ;TestAddr+13 cache lines
- _MFENCE
- mov eax,fs:[ecx] ;TestAddr+14 cache lines
- _MFENCE
- mov eax,fs:[ecx+64] ;TestAddr+15 cache lines
- _MFENCE
- mov eax,fs:[edx] ;TestAddr+16 cache lines
- _MFENCE
- mov eax,fs:[edx+64] ;TestAddr+17 cache lines
- _MFENCE
- .endif
- .endif
- _MFENCE
-
- ; Then, copy data to buffer
- mov esi,Address
- xor edx,edx
- mov edx,DWORD PTR Buffer
- mov edi,edx
- xor ecx, ecx
- mov cx,ClCount
- shl ecx,6
- @@:
- mov al,fs:[esi]
- mov ss:[edi],al
- inc esi
- inc edi
- loop @B
-
- popad
- ret
-MemUReadCachelines ENDP
-
-;===============================================================================
-;MemUDummyCLRead:
-;
-; Perform a single cache line read from a given physical address.
-;
-; In: Address - Physical address to be read
-; ClCount - number of cachelines to be read
-; Out:
-;
-;All registers preserved.
-;===============================================================================
-MemUDummyCLRead PROC CALLCONV PUBLIC Address:DWORD
- _SFENCE
- pushad
- mov eax,Address
- mov dl,fs:[eax]
- popad
- ret
-MemUDummyCLRead ENDP
-
-;===============================================================================
-;MemUFlushPattern:
-;
-; Flush a pattern of 72 bit times (per DQ) from cache. This procedure is used
-;to ensure cache miss on the next read training.
-;
-; In: Address - Physical address to be flushed
-; ClCount - number of cachelines to be flushed
-; Out:
-;
-;All registers preserved.
-;===============================================================================
-MemUFlushPattern PROC CALLCONV PUBLIC Address:DWORD, ClCount:WORD
- pushad
- mov edi,Address
- movzx ecx,ClCount
- @@:
- _MFENCE ; Force strong ordering of clflush
- db 64h,0Fh,0AEh,3Fh ; MemUClFlush fs:[edi]
- _MFENCE
- add edi,64
- loop @B
- popad
- ret
-MemUFlushPattern ENDP
-
-
-;===============================================================================
-;MemUGetWrLvNblErr:
-; Read ClCount number of cachelines then return the bitmap that indicates
-; the write leveling result of each byte lane.
-;
-; IN: ErrBitmap - pointer to a DWORD that will be assigned with WL result
-; Address - Physical address to be sampled
-; ClCount - number of cachelines to be read
-;
-; OUT: ErrBitmap - WL result
-;
-;All registers preserved
-;===============================================================================
-MemUGetWrLvNblErr PROC CALLCONV PUBLIC ErrBitmap:NEAR PTR DWORD, Address:DWORD, ClCount:WORD
-LOCAL ZeroCount[32]:WORD
-
- pushad
- mov esi,Address
- _EXECFENCE
- ;Cache fill
- movzx ecx,ClCount
- @@:
- mov eax,fs:[esi]
- add esi,64
- loop @B
- _MFENCE
-
- ; Then, count the number of 0's
- ;push es
- ;push ss
- ;pop es
- lea edi,ZeroCount
- mov cx,SIZEOF ZeroCount
- mov al,0
- rep stosb
- ;pop es
-
- mov esi,Address
- lea edi,ZeroCount
- mov cx,ClCount
- shl cx,6
- .while(cx > 0)
- mov al,fs:[esi]
- test al,00Fh ;check lower nibble
- .if(ZERO?)
- inc WORD PTR [edi]
- .endif
- add edi,2
- test al,0F0h ;check upper nibble
- .if(ZERO?)
- inc WORD PTR [edi]
- .endif
- add edi,2
- inc esi
- dec cx
- test cx,07h
- .if(ZERO?)
- sub edi,(16*2)
- sub cx,8
- add esi,8
- .endif
- .endw
-
- ; Then, average and compress data to error bits
- lea esi,ZeroCount
- mov dx,ClCount
- shl dx,1
- xor eax,eax
- xor ecx,ecx
- mov cl,0
- .while(cl<16)
- .if(WORD PTR [esi] < dx)
- bts eax,ecx
- .endif
- add esi,2
- inc cl
- .endw
- xor edx,edx
- mov dx,WORD PTR ErrBitmap
- mov [edx], ax
-
- popad
- ret
-MemUGetWrLvNblErr ENDP
-
-;===============================================================================
-;AlignPointerTo16Byte:
-; Modifies BufferPtr to be 16 byte aligned
-;
-; In: BufferPtrPtr - Pointer to buffer pointer
-; Out: BufferPtrPtr - Pointer to buffer pointer that has been 16 byte aligned
-;
-;All registers preserved.
-;===============================================================================
-AlignPointerTo16Byte PROC CALLCONV PUBLIC BufferPtrPtr:NEAR PTR DWORD
- push edx
- push eax
- mov edx, BufferPtrPtr
- mov eax, [edx]
- add eax, 16
- and ax, 0FFF0h
- mov [edx], eax
- pop eax
- pop edx
- ret
-AlignPointerTo16Byte ENDP
-
-;===============================================================================
-;MemUMFenceInstr:
-; Serialize instruction
-;
-; In:
-; Out:
-;
-;All registers preserved.
-;===============================================================================
-MemUMFenceInstr PROC CALLCONV PUBLIC
- _MFENCE
- ret
-MemUMFenceInstr ENDP
-
- END
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Main/mu.c b/src/vendorcode/amd/agesa/Proc/Mem/Main/mu.c
deleted file mode 100644
index edd39dd..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Main/mu.c
+++ /dev/null
@@ -1,253 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * HyperTransport features and sequence implementation.
- *
- * Implements the external AmdHtInitialize entry point.
- * Contains routines for directing the sequence of available features.
- * Mostly, but not exclusively, AGESA_TESTPOINT invocations should be
- * contained in this file, and not in the feature code.
- *
- * From a build option perspective, it may be that a few lines could be removed
- * from compilation in this file for certain options. It is considered that
- * the code savings from this are too small to be of concern and this file
- * should not have any explicit build option implementation.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35978 $ @e \$Date: 2010-08-07 02:18:50 +0800 (Sat, 07 Aug 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Filecode.h"
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-VOID
-MemUWriteCachelines (
- IN UINT32 Address,
- IN UINT8 Pattern[],
- IN UINT16 ClCount
- );
-
-VOID
-MemUReadCachelines (
- IN UINT8 Buffer[],
- IN UINT32 Address,
- IN UINT16 ClCount
- );
-
-VOID
-MemUDummyCLRead (
- IN UINT32 Address
- );
-
-VOID
-MemUMFenceInstr (
- VOID
- );
-
-VOID
-MemUFlushPattern (
- IN UINT32 Address,
- IN UINT16 ClCount
- );
-
-VOID
-AlignPointerTo16Byte (
- IN OUT UINT8 **BufferPtrPtr
- );
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------
- * L O C A L F U N C T I O N S
- *---------------------------------------------------------------------------------------
- */
-
-
-
-//----------------------------------------------------------------------------
-
-VOID
-MemUWriteCachelines (
- IN UINT32 Address,
- IN UINT8 Pattern[],
- IN UINT16 ClCount
- )
-{
- UINTN Index;
- CHAR8 *Position;
- __m128i *Src = (void *) Pattern;
- __m128i *Dest = (void *) (size_t)Address;
-
- Position = (void *) Pattern;
-
- // ssd - important: without this, the src data may get evicted from cache
- _mm_mfence ();
-
- for (Index = 0; Index < ClCount * 4; Index++){
- _mm_stream_si128_fs (Dest, Src);
- Src++;
- Dest++;
- }
-
- // ssd - might not be required, but no measurable boot time impact
- _mm_mfence ();
-}
-
-
-//----------------------------------------------------------------------------
-// MemUReadCachelines:
-//
-// Read a pattern of 72 bit times (per DQ), to test dram functionality. The
-// pattern is a stress pattern which exercises both ISI and crosstalk. The number
-// of cache lines to fill is dependent on DCT width mode and burstlength.
-//
-// In: Buffer - pointer to a buffer where read data will be stored
-// Address - Physical address to be read
-// ClCount - number of cachelines to be read
-
-VOID
-MemUReadCachelines (
- IN UINT8 Buffer[],
- IN UINT32 Address,
- IN UINT16 ClCount
- )
-{
- UINTN Index;
- UINT32 *Dest;
-
- for (Index = 0; Index < ClCount * 16; Index++) {
- Dest = (void *) &Buffer [Index * 4];
- *Dest = __readfsdword (Address + Index * 4);
- _mm_mfence ();
- }
-}
-
-//----------------------------------------------------------------------------
-// MemUDummyCLRead:
-//
-// Perform a single cache line read from a given physical address.
-//
-// In: Address - Physical address to be read
-// ClCount - number of cachelines to be read
-
-//FUNC_ATTRIBUTE (noinline)
-VOID
-MemUDummyCLRead (
- IN UINT32 Address
- )
-{
- _mm_sfence ();
- __readfsbyte (Address);
-}
-
-//----------------------------------------------------------------------------
-
-VOID
-MemUMFenceInstr (
- VOID
- )
-{
- _mm_mfence ();
-}
-
-//----------------------------------------------------------------------------
-// MemUFlushPattern:
-//
-// Flush a pattern of 72 bit times (per DQ) from cache. This procedure is used
-// to ensure cache miss on the next read training.
-//
-// In: Address - Physical address to be flushed
-// ClCount - number of cachelines to be flushed
-//FUNC_ATTRIBUTE(noinline)
-VOID
-MemUFlushPattern (
- IN UINT32 Address,
- IN UINT16 ClCount
- )
-{
- UINTN Index;
-
- // ssd - theory: a tlb flush is needed to avoid problems with clflush
- __writemsr (0x20F, __readmsr (0x20F));
-
- for (Index = 0; Index < ClCount; Index++) {
- // mfence prevents speculative execution of the clflush
- _mm_mfence ();
- _mm_clflush_fs ((void *) (size_t) (Address + Index * 64));
- }
-}
-
-//----------------------------------------------------------------------------
-
-//FUNC_ATTRIBUTE(noinline)
-VOID
-AlignPointerTo16Byte (
- IN OUT UINT8 **BufferPtrPtr
- )
-{
- size_t Address = (size_t) *BufferPtrPtr;
- Address += 15;
- Address -= Address % 16;
- *BufferPtrPtr = (void *) Address;
-}
-
-//----------------------------------------------------------------------------
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Main/muc.c b/src/vendorcode/amd/agesa/Proc/Mem/Main/muc.c
deleted file mode 100644
index 2ddd305..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Main/muc.c
+++ /dev/null
@@ -1,652 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * muc.c
- *
- * Utility functions
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Main)
- * @e \$Revision: 38442 $ @e \$Date: 2010-09-24 06:39:57 +0800 (Fri, 24 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "cpuServices.h"
-#include "amdlib.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "Ids.h"
-#include "mport.h"
-#include "mu.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuCacheInit.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_MAIN_MUC_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-CONST UINT32 Pattern2[16] = {
- 0x12345678, 0x87654321, 0x23456789, 0x98765432,
- 0x59385824, 0x30496724, 0x24490795, 0x99938733,
- 0x40385642, 0x38465245, 0x29432163, 0x05067894,
- 0x12349045, 0x98723467, 0x12387634, 0x34587623
-};
-
-CONST UINT32 MaxLatPat[48] = {
- 0x6E0E3FAC, 0x0C3CFF52,
- 0x4A688181, 0x49C5B613,
- 0x7C780BA6, 0x5C1650E3,
- 0x0C4F9D76, 0x0C6753E6,
- 0x205535A5, 0xBABFB6CA,
- 0x610E6E5F, 0x0C5F1C87,
- 0x488493CE, 0x14C9C383,
- 0xF5B9A5CD, 0x9CE8F615,
-
- 0xAAD714B5, 0xC38F1B4C,
- 0x72ED647C, 0x669F7562,
- 0x5233F802, 0x4A898B30,
- 0x10A40617, 0x3326B465,
- 0x55386E04, 0xC807E3D3,
- 0xAB49E193, 0x14B4E63A,
- 0x67DF2495, 0xEA517C45,
- 0x7624CE51, 0xF8140C51,
-
- 0x4824BD23, 0xB61DD0C9,
- 0x072BCFBE, 0xE8F3807D,
- 0x919EA373, 0x25E30C47,
- 0xFEB12958, 0x4DA80A5A,
- 0xE9A0DDF8, 0x792B0076,
- 0xE81C73DC, 0xF025B496,
- 0x1DB7E627, 0x808594FE,
- 0x82668268, 0x655C7783
-};
-
-CONST UINT8 PatternJD[9] = {0x44, 0xA6, 0x38, 0x4F, 0x4B, 0x2E, 0xEF, 0xD5, 0x54};
-
-CONST UINT8 PatternJD_256[256] = {
- 0x00, 0xFF, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00,
- 0xFF, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0xFF,
- 0xFF, 0x00, 0xFF, 0xFF, 0xFF, 0x00, 0xFF, 0xFF,
- 0xFF, 0xFF, 0x00, 0xF7, 0x08, 0xF7, 0x00, 0xFF,
- 0x00, 0xF7, 0x00, 0xFF, 0x00, 0xF7, 0x00, 0xF7,
- 0x08, 0xF7, 0x08, 0xFF, 0x00, 0xFF, 0x08, 0xFF,
- 0x00, 0xFF, 0x08, 0xFF, 0x08, 0xF7, 0xFB, 0x04,
- 0xFB, 0xFB, 0x04, 0xFB, 0xFB, 0xFB, 0x04, 0xFB,
- 0xFB, 0xFB, 0xFB, 0x04, 0xFB, 0x04, 0x04, 0xFB,
- 0x04, 0x04, 0x04, 0xFB, 0x04, 0x04, 0x04, 0x04,
- 0xFB, 0x7F, 0x80, 0x7F, 0x00, 0xFF, 0x00, 0x7F,
- 0x00, 0xFF, 0x00, 0x7F, 0x00, 0x7F, 0x80, 0x7F,
- 0x80, 0xFF, 0x00, 0xFF, 0x80, 0xFF, 0x00, 0xFF,
- 0x80, 0xFF, 0x80, 0x7F, 0xBF, 0x40, 0xBF, 0xBF,
- 0x40, 0xBF, 0xBF, 0xBF, 0x40, 0xBF, 0xBF, 0xBF,
- 0xBF, 0x40, 0xBF, 0x40, 0x40, 0xBF, 0x40, 0x40,
- 0x40, 0xBF, 0x40, 0x40, 0x40, 0x40, 0xBF, 0xFD,
- 0x02, 0xFD, 0x00, 0xFF, 0x00, 0xFD, 0x00, 0xFF,
- 0x00, 0xFD, 0x00, 0xFD, 0x02, 0xFD, 0x02, 0xFF,
- 0x00, 0xFF, 0x02, 0xFF, 0x00, 0xFF, 0x02, 0xFF,
- 0x02, 0xFD, 0xFE, 0x01, 0xFE, 0xFE, 0x01, 0xFE,
- 0xFE, 0xFE, 0x01, 0xFE, 0xFE, 0xFE, 0xFE, 0x01,
- 0xFE, 0x01, 0x01, 0xFE, 0x01, 0x01, 0x01, 0xFE,
- 0x01, 0x01, 0x01, 0x01, 0xFE, 0xDF, 0x20, 0xDF,
- 0x00, 0xFF, 0x00, 0xDF, 0x00, 0xFF, 0x00, 0xDF,
- 0x00, 0xDF, 0x20, 0xDF, 0x20, 0xFF, 0x00, 0xFF,
- 0x20, 0xFF, 0x00, 0xFF, 0x20, 0xFF, 0x20, 0xDF,
- 0xEF, 0x10, 0xEF, 0xEF, 0x10, 0xEF, 0xEF, 0xEF,
- 0x10, 0xEF, 0xEF, 0xEF, 0xEF, 0x10, 0xEF, 0x10,
- 0x10, 0xEF, 0x10, 0x10, 0x10, 0xEF, 0x10, 0x10,
- 0x10, 0x10, 0xEF, 0xF7, 0x00, 0xFF, 0x04, 0x7F,
- 0x00, 0xFF, 0x40, 0xFD, 0x00, 0xFF, 0x01, 0xDF
-};
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function returns the (index)th UINT8
- * from an indicated test pattern.
- *
- * @param[in] Pattern - encoding of test pattern type
- * @param[in] Buffer[] - buffer to be filled
- * @param[in] Size - Size of the buffer
- *
- * ----------------------------------------------------------------------------
- */
-
-VOID
-MemUFillTrainPattern (
- IN TRAIN_PATTERN Pattern,
- IN UINT8 Buffer[],
- IN UINT16 Size
- )
-{
- UINT8 Result;
- UINT8 i;
- UINT8 Mask;
- UINT16 Index;
- UINT16 k;
-
- for (Index = 0; Index < Size; Index++) {
- k = Index;
- // get one byte from Pattern
- switch (Pattern) {
- case TestPattern0:
- Result = 0xAA;
- break;
- case TestPattern1:
- Result = 0x55;
- break;
- case TestPattern2:
- ASSERT (Index < sizeof (Pattern2));
- Result = ((UINT8 *)Pattern2)[Index];
- break;
- case TestPatternML:
- if (Size != 6 * 64) {
- Result = ((UINT8 *)MaxLatPat)[Index];
- } else {
- Result = ((UINT8 *)MaxLatPat)[Index & 0xF7];
- }
- break;
- case TestPatternJD256B:
- k >>= 1;
- // break is not being used here because TestPatternJD256B also need
- // to run TestPatternJD256A sequence.
- case TestPatternJD256A:
- k >>= 3;
- ASSERT (k < sizeof (PatternJD_256));
- Result = PatternJD_256[k];
- break;
- case TestPatternJD1B:
- k >>= 1;
- // break is not being used here because TestPatternJD1B also need
- // to run TestPatternJD1A sequence.
- case TestPatternJD1A:
- k >>= 3;
- i = (UINT8) (k >> 3);
- Mask = (UINT8) (0x80 >> (k & 7));
-
- if (i == 0) {
- Result = 0;
- } else {
- Result = (UINT16)1 << (i - 1);
- }
-
- ASSERT (i < sizeof (PatternJD));
- if (PatternJD[i] & Mask) {
- Result = ~Result;
- }
- break;
- case TestPattern3:
- Result = 0x36;
- break;
- case TestPattern4:
- Result = 0xC9;
- break;
- default:
- Result = 0;
- IDS_ERROR_TRAP;
- }
-
- // fill in the Pattern buffer
- Buffer[Index] = Result;
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function flushes cache lines
- *
- * @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE
- * @param[in] ClCount - Number of cache lines
- * @param[in] Address - System Address [47:16]
- *
- * ----------------------------------------------------------------------------
- */
-
-VOID
-MemUProcIOClFlush (
- IN UINT32 Address,
- IN UINT16 ClCount,
- IN OUT MEM_DATA_STRUCT *MemPtr
- )
-{
- MemUSetTargetWTIO (Address, MemPtr);
- MemUFlushPattern (MemUSetUpperFSbase (Address, MemPtr), ClCount);
- MemUResetTargetWTIO (MemPtr);
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the upper 32-bits of the Base address, 4GB aligned) for the FS selector.
- * @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE
- * @param[in] Address - System Address [47:16]
- *
- * @return Address - Lowest 32-bit of physical address
- * ----------------------------------------------------------------------------
- */
-
-UINT32
-MemUSetUpperFSbase (
- IN UINT32 Address,
- IN OUT MEM_DATA_STRUCT *MemPtr
- )
-{
- S_UINT64 SMsr;
-
- SMsr.lo = 0;
- SMsr.hi = Address >> 16;
- LibAmdMsrWrite (FS_BASE, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- return Address << 16;
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function resets the target address space to Write Through IO by disabling IORRs
- *
- * @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE
- *
- * ----------------------------------------------------------------------------
- */
-
-VOID
-MemUResetTargetWTIO (
- IN OUT MEM_DATA_STRUCT *MemPtr
- )
-{
- S_UINT64 SMsr;
- SMsr.hi = 0;
- SMsr.lo = 0;
- LibAmdMsrWrite (IORR0_MASK, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the target range to WT IO (using an IORR overlapping
- * the already existing
- *
- * @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE
- * @param[in] Address - System Address [47:16]
- *
- * ----------------------------------------------------------------------------
- */
-
-VOID
-MemUSetTargetWTIO (
- IN UINT32 Address,
- IN OUT MEM_DATA_STRUCT *MemPtr
- )
-{
- S_UINT64 SMsr;
-
- SMsr.lo = Address << 16;
- SMsr.hi = Address >> 16;
- LibAmdMsrWrite (IORR0_BASE,(UINT64 *)&SMsr, &MemPtr->StdHeader); // IORR0 Base
- SMsr.hi = 0xFFFF;
- SMsr.lo = 0xFC000800;
- LibAmdMsrWrite (IORR0_MASK, (UINT64 *)&SMsr, &MemPtr->StdHeader); // 64MB Mask
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Waits specified number of 10ns cycles
- * @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE
- * @param[in] Count - Number of 10ns cycles to wait; Note that Count must not exceed 1000000
- *
- * ----------------------------------------------------------------------------
- */
-
-VOID
-MemUWait10ns (
- IN UINT32 Count,
- IN OUT MEM_DATA_STRUCT *MemPtr
- )
-{
- UINT64 TargetTsc;
- UINT64 CurrentTsc;
-
- ASSERT (Count <= 1000000);
-
- MemUMFenceInstr ();
-
- LibAmdMsrRead (TSC, &CurrentTsc, &MemPtr->StdHeader);
- TargetTsc = CurrentTsc + ((Count * MemPtr->TscRate + 99) / 100);
- do {
- LibAmdMsrRead (TSC, &CurrentTsc, &MemPtr->StdHeader);
- } while (CurrentTsc < TargetTsc);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Find the entry of platform specific overriding table.
- *
- * @param[in] PlatformMemoryConfiguration - Platform config table
- * @param[in] EntryType - Entry type
- * @param[in] SocketID - Physical socket ID
- * @param[in] ChannelID - Physical channel ID
- *
- * @return NULL - entry could not be found.
- * @return Pointer - points to the entry's data.
- *
- * ----------------------------------------------------------------------------
- */
-
-VOID *
-FindPSOverrideEntry (
- IN PSO_TABLE *PlatformMemoryConfiguration,
- IN PSO_ENTRY EntryType,
- IN UINT8 SocketID,
- IN UINT8 ChannelID
- )
-{
- UINT8 *Buffer;
-
- Buffer = PlatformMemoryConfiguration;
- while (Buffer[0] != PSO_END) {
- if (Buffer[0] == EntryType) {
- if ((Buffer[2] & ((UINT8) 1 << SocketID)) != 0 ) {
- if ((Buffer[3] & ((UINT8) 1 << ChannelID)) != 0 ) {
- return &Buffer[4];
- }
- }
- }
- Buffer += Buffer[1] + 2;
- }
- return NULL;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function returns the max dimms for a given memory channel on a given
- * processor. It first searches the platform override table for the max dimms
- * value. If it is not provided, the AGESA default value is returned. The target
- * socket must be a valid present socket.
- *
- * @param[in] PlatformMemoryConfiguration - Platform config table
- * @param[in] SocketID - ID of the processor that owns the channel
- * @param[in] ChannelID - Channel to get max dimms for
- *
- *
- * @return UINT8 - Max Number of Dimms for that channel
- */
-UINT8
-GetMaxDimmsPerChannel (
- IN PSO_TABLE *PlatformMemoryConfiguration,
- IN UINT8 SocketID,
- IN UINT8 ChannelID
- )
-{
- UINT8 *DimmsPerChPtr;
- UINT8 MaxDimmPerCH;
-
- DimmsPerChPtr = FindPSOverrideEntry (PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, ChannelID);
- if (DimmsPerChPtr != NULL) {
- MaxDimmPerCH = *DimmsPerChPtr;
- } else {
- MaxDimmPerCH = MAX_DIMMS_PER_CHANNEL;
- }
- // Maximum number of dimms per channel cannot be larger than its default value.
- ASSERT (MaxDimmPerCH <= MAX_DIMMS_PER_CHANNEL);
-
- return MaxDimmPerCH;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function returns the max memory channels on a given processor.
- * It first searches the platform override table for the max channels value.
- * If it is not provided, the AGESA default value is returned.
- *
- * @param[in] PlatformMemoryConfiguration - Platform config table
- * @param[in] SocketID - ID of the processor
- * @param[in] StdHeader - Header for library and services
- *
- *
- * @return UINT8 - Max Number of Channels on that Processor
- */
-UINT8
-GetMaxChannelsPerSocket (
- IN PSO_TABLE *PlatformMemoryConfiguration,
- IN UINT8 SocketID,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 *ChannelsPerSocketPtr;
- UINT8 MaxChannelsPerSocket;
-
- if (IsProcessorPresent (SocketID, StdHeader)) {
- ChannelsPerSocketPtr = FindPSOverrideEntry (PlatformMemoryConfiguration, PSO_MAX_CHNLS, SocketID, 0);
- if (ChannelsPerSocketPtr != NULL) {
- MaxChannelsPerSocket = *ChannelsPerSocketPtr;
- } else {
- MaxChannelsPerSocket = MAX_CHANNELS_PER_SOCKET;
- }
- // Maximum number of channels per socket cannot be larger than its default value.
- ASSERT (MaxChannelsPerSocket <= MAX_CHANNELS_PER_SOCKET);
- } else {
- MaxChannelsPerSocket = 0;
- }
-
- return MaxChannelsPerSocket;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function returns the max number of chip select on a given channel of
- * a given processor. It first searches the platform override table for the max
- * chip select value. If it is not provided, the AGESA default value is returned.
- * The target socket must be a valid present socket.
- *
- * @param[in] PlatformMemoryConfiguration - Platform config table
- * @param[in] SocketID - ID of the processor
- * @param[in] ChannelID - ID of a channel
- *
- *
- * @return UINT8 - Max Number of chip selects on the channel of the Processor
- */
-UINT8
-GetMaxCSPerChannel (
- IN PSO_TABLE *PlatformMemoryConfiguration,
- IN UINT8 SocketID,
- IN UINT8 ChannelID
- )
-{
- UINT8 *CSPerSocketPtr;
- UINT8 MaxCSPerChannel;
-
- CSPerSocketPtr = FindPSOverrideEntry (PlatformMemoryConfiguration, PSO_MAX_CHIPSELS, SocketID, ChannelID);
- if (CSPerSocketPtr != NULL) {
- MaxCSPerChannel = *CSPerSocketPtr;
- } else {
- MaxCSPerChannel = MAX_CS_PER_CHANNEL;
- }
- // Max chip select per channel cannot be larger than its default value
- ASSERT (MaxCSPerChannel <= MAX_CS_PER_CHANNEL);
-
- return MaxCSPerChannel;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function returns the index of the first Dimm SPD structure for a
- * given processor socket. It checks the Max Dimms per channel for every memory
- * channel on every processor up to the current one, and adds them together.
- *
- * This function may also be used to calculate the maximum dimms per system
- * by passing the total number of dimm sockets
- *
- * @param[in] PlatformMemoryConfiguration - Platform config table
- * @param[in] SocketID - ID of the processor
- * @param[in] StdHeader - Header for library and services
- *
- * @return UINT8 - SPD Index
- */
-UINT8
-GetSpdSocketIndex (
- IN PSO_TABLE *PlatformMemoryConfiguration,
- IN UINT8 SocketID,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 SpdSocketIndex;
- UINT8 Socket;
- UINT8 Channel;
- UINT8 MaxChannelsPerSocket;
-
- SpdSocketIndex = 0;
- for (Socket = 0; Socket < SocketID; Socket++) {
- MaxChannelsPerSocket = GetMaxChannelsPerSocket (PlatformMemoryConfiguration, Socket, StdHeader);
- for (Channel = 0; Channel < MaxChannelsPerSocket; Channel++) {
- SpdSocketIndex = SpdSocketIndex + GetMaxDimmsPerChannel (PlatformMemoryConfiguration, Socket, Channel);
- }
- }
- return SpdSocketIndex;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function returns the index of the first Dimm SPD structure for a
- * given channel relative to the processor socket. It checks the Max Dimms per
- * channel for every memory channel on that processor up to the current one,
- * and adds them together.
- *
- * This function may also be used to calculate the maximum dimms per system
- * by passing the total number of DIMM sockets
- *
- * @param[in] PlatformMemoryConfiguration - Platform config table
- * @param[in] SocketID - ID of the processor
- * @param[in] ChannelID - ID of the Channel
- * @param[in] StdHeader - Header for library and services
- *
- * @return UINT8 - SPD Index
- */
-UINT8
-GetSpdChannelIndex (
- IN PSO_TABLE *PlatformMemoryConfiguration,
- IN UINT8 SocketID,
- IN UINT8 ChannelID,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 SpdChannelIndex;
- UINT8 Channel;
-
- SpdChannelIndex = 0;
- ASSERT (ChannelID < GetMaxChannelsPerSocket (PlatformMemoryConfiguration, SocketID, StdHeader))
- for (Channel = 0; Channel < ChannelID; Channel++) {
- SpdChannelIndex = SpdChannelIndex + GetMaxDimmsPerChannel (PlatformMemoryConfiguration, SocketID, Channel);
- }
- return SpdChannelIndex;
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- *
- * This function returns the upper 32 bits mask for variable MTRR based on
- * the CPU_LOGICAL_ID.
- * @param[in] *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID
- * @param[in] StdHeader - Header for library and services
- *
- * @return UINT32 - MTRR mask for upper 32 bits
- *
- */
-UINT32
-GetVarMtrrHiMsk (
- IN CPU_LOGICAL_ID *LogicalIdPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 TempNotCare;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
- CACHE_INFO *CacheInfoPtr;
-
- GetCpuServicesFromLogicalId (LogicalIdPtr, &FamilySpecificServices, StdHeader);
- FamilySpecificServices->GetCacheInfo (FamilySpecificServices, &CacheInfoPtr, &TempNotCare, StdHeader);
- return (UINT32) (CacheInfoPtr->VariableMtrrMask >> 32);
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mnParTrainc32.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mnParTrainc32.c
deleted file mode 100644
index d683da8..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mnParTrainc32.c
+++ /dev/null
@@ -1,224 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnParTrainc32.c
- *
- * Feature which performs Memory DQS training on each node with each node training
- * its own memory through code running on a core in the associated processor.
- * This way memory can be trained in parallel by more than one processor.
- *
- * This file contains the C32 specific parallel training function.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/C32)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mnc32.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuServices.h"
-#include "GeneralServices.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuApicUtilities.h"
-#include "mfParallelTraining.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_NB_C32_MNPARTRAINC32_FILECODE
-/*-----------------------------------------------------------------------------
-* EXPORTED FUNCTIONS
-*
-*-----------------------------------------------------------------------------
-*/
-BOOLEAN
-STATIC
-MemConstructRemoteNBBlockC32 (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN DIE_STRUCT *MCTPtr,
- IN MEM_FEAT_BLOCK_NB *FeatPtr
-);
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This is the training function which set up the environment for remote
- * training on the ap and launches the remote routine.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - Launch training on AP successfully.
- * @return FALSE - Fail to launch training on AP.
- */
-BOOLEAN
-MemFParallelTrainingC32 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- AMD_CONFIG_PARAMS *StdHeader;
- DIE_STRUCT *MCTPtr;
- REMOTE_TRAINING_ENV *EnvPtr;
- AP_TASK TrainingTask;
- UINT8 Socket;
- UINT8 Module;
- UINT8 APCore;
- UINT8 p;
- UINT32 LowCore;
- UINT32 HighCore;
- UINT32 BspSocket;
- UINT32 BspModule;
- UINT32 BspCore;
- AGESA_STATUS Status;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
- UINT16 MctDataSize;
- StdHeader = &(NBPtr->MemPtr->StdHeader);
- MCTPtr = NBPtr->MCTPtr;
- Socket = MCTPtr->SocketId;
- Module = MCTPtr->DieId;
-
- //
- // Allocate buffer for REMOTE_TRAINING_ENV
- //
- MctDataSize = MAX_DCTS_PER_NODE_C32 * (
- sizeof (DCT_STRUCT) + (
- MAX_CHANNELS_PER_DCT_C32 * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))
- )
- );
- AllocHeapParams.RequestedBufferSize = MctDataSize + sizeof (REMOTE_TRAINING_ENV);
- AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, Socket, Module, 0);
- AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
- if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
- EnvPtr = (REMOTE_TRAINING_ENV *) AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += sizeof (REMOTE_TRAINING_ENV);
-
- //
- // Setup Remote training environment
- //
- LibAmdMemCopy (&(EnvPtr->StdHeader), StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);
- LibAmdMemCopy (&(EnvPtr->DieStruct), MCTPtr, sizeof (DIE_STRUCT), StdHeader);
- for (p = 0; p < MAX_PLATFORM_TYPES; p++) {
- EnvPtr->GetPlatformCfg[p] = NBPtr->MemPtr->GetPlatformCfg[p];
- }
- EnvPtr->ErrorHandling = NBPtr->MemPtr->ErrorHandling;
- EnvPtr->NBBlockCtor = MemConstructRemoteNBBlockC32;
- EnvPtr->FeatPtr = NBPtr->FeatPtr;
- EnvPtr->HoleBase = NBPtr->RefPtr->HoleBase;
- EnvPtr->BottomIo = NBPtr->RefPtr->BottomIo;
- EnvPtr->UmaSize = NBPtr->RefPtr->UmaSize;
- EnvPtr->SysLimit = NBPtr->RefPtr->SysLimit;
- EnvPtr->TableBasedAlterations = NBPtr->RefPtr->TableBasedAlterations;
- EnvPtr->PlatformMemoryConfiguration = NBPtr->RefPtr->PlatformMemoryConfiguration;
-
- LibAmdMemCopy (AllocHeapParams.BufferPtr, MCTPtr->DctData, MctDataSize, StdHeader);
-
- //
- // Get Socket, Core of the BSP
- //
- IdentifyCore (StdHeader, &BspSocket, &BspModule, &BspCore, &Status);
- EnvPtr->BspSocket = ((UINT8)BspSocket & 0x000000FF);
- EnvPtr->BspCore = ((UINT8)BspCore & 0x000000FF);
-
- //
- // Set up the remote task structure
- //
- TrainingTask.DataTransfer.DataPtr = EnvPtr;
- TrainingTask.DataTransfer.DataSizeInDwords = (UINT16) (AllocHeapParams.RequestedBufferSize + 3) / 4;
- TrainingTask.DataTransfer.DataTransferFlags = 0;
- TrainingTask.ExeFlags = 0;
- TrainingTask.FuncAddress.PfApTaskI = (PF_AP_TASK_I)MemFParallelTraining;
-
- //
- // Get Target AP Core
- //
- GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader);
- APCore = (UINT8) (LowCore & 0x000000FF);
-
- //
- // Launch Remote Training
- //
- ApUtilRunCodeOnSocketCore (Socket, APCore, &TrainingTask, StdHeader);
-
- HeapDeallocateBuffer (AllocHeapParams.BufferHandle, StdHeader);
-
- return TRUE;
- } else {
- PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV, NBPtr->Node, 0, 0, 0, StdHeader);
- SetMemError (AGESA_FATAL, MCTPtr);
- ASSERT(FALSE); // Could not allocated heap space for "REMOTE_TRAINING_ENV"
- return FALSE;
- }
-}
-
-BOOLEAN
-STATIC
-MemConstructRemoteNBBlockC32 (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN DIE_STRUCT *MCTPtr,
- IN MEM_FEAT_BLOCK_NB *FeatPtr
- )
-{
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
-
- NBPtr->MCTPtr = MCTPtr;
- NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue;
-
- MemNInitNBDataC32 (NBPtr);
-
- FeatPtr->InitCPG (NBPtr);
- NBPtr->FeatPtr = FeatPtr;
- FeatPtr->InitHwRxEn (NBPtr);
- MemNSwitchDCTNb (NBPtr, 0);
-
- //----------------------------------------------------------------------------
- // Get TSC rate of the this AP
- //----------------------------------------------------------------------------
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
- FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader);
-
- return TRUE;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mnS3c32.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mnS3c32.c
deleted file mode 100644
index 25103e3..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mnS3c32.c
+++ /dev/null
@@ -1,731 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mns3c32.c
- *
- * C32 memory specific function to support S3 resume
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/C32)
- * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "S3.h"
-#include "mfs3.h"
-#include "mnc32.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "mnS3c32.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G3_DXE)
-RDATA_GROUP (G3_DXE)
-
-#define FILECODE PROC_MEM_NB_C32_MNS3C32_FILECODE
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-UINT16
-STATIC
-MemNS3GetRegLstPtrC32 (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT DESCRIPTOR_GROUP *DescriptPtr
- );
-
-AGESA_STATUS
-STATIC
-MemNS3GetDeviceRegLstC32 (
- IN UINT32 RegisterLstID,
- OUT VOID **RegisterHeader
- );
-
-VOID
-STATIC
-MemNS3SetSpecialPCIRegC32 (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR Address,
- IN VOID *Value,
- IN OUT VOID *ConfigPtr
- );
-
-VOID
-STATIC
-MemNS3ExitSelfRefRegC32 (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-PCI_SPECIAL_CASE PciSpecialCaseFuncC32[] = {
- {MemNS3GetCSRNb, MemNS3SetCSRNb},
- {MemNS3GetCSRNb, MemNS3SetSpecialPCIRegC32},
- {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb}
-};
-
-PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorC32[] = {
- {{0, 0, 0}, FUNC_2, 0x110, 0xFFFFFFFF},
- {{0, 0, 0}, FUNC_1, 0x40, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x48, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x50, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x58, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x60, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x68, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x70, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x78, 0xFFFF3F03},
- {{0, 1, 0}, FUNC_1, 0x140, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x148, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x150, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x158, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x160, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x168, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x170, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x178, 0x000000FF},
- {{0, 0, 0}, FUNC_1, 0x44, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x4C, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x54, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x5C, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x64, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x6C, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x74, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x7C, 0xFFFF07FF},
- {{0, 1, 0}, FUNC_1, 0x144, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x14C, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x154, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x15C, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x164, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x16C, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x174, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x17C, 0x000000FF},
- {{0, 0, 0}, FUNC_1, 0xF0, 0xFF00FF83},
- {{0, 0, 0}, FUNC_1, 0x120, 0x00FFFFFF},
- {{0, 0, 0}, FUNC_1, 0x124, 0x07FFFFFF},
- {{0, 0, 0}, FUNC_2, 0x114, 0xFFFFFC00},
- {{0, 0, 0}, FUNC_2, 0x118, 0xF773FFFF},
- {{0, 0, 0}, FUNC_2, 0x11C, 0xFFFFFFFF},
- {{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F}
-};
-
-CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefC32 = {
- 0,
- (sizeof (S3PciPreSelfRefDescriptorC32) / sizeof (PCI_REG_DESCRIPTOR)),
- S3PciPreSelfRefDescriptorC32,
- NULL
-};
-
-CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorC32[] = {
- // DCT 0
- {{0, 0, 0}, FUNC_2, 0x40, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x44, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x48, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x4C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x50, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x54, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x58, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x5C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x60, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x64, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x68, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x6C, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x78, 0xFFCDBF0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x7C, 0xFFF7FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 2, 0}, FUNC_2, 0x80, 0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x84, 0x07FFEFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x88, 0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x8C, 0xFFFF7FFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x90, 0x00FFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0xA4, 0x000F7B00, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0xA8, 0x0007FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x180), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x181), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x182), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x183), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), 0x30333333, DCT0_MASK, ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0x3FFFFFFF, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), 0x001FBFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), 0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhyClkConfig0, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhyClkConfig1, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhyClkConfig2, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhyClkConfig3, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- //errata 322
- {{2, 2, 1}, DCT0, BFErr322I, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFErr322II, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- //errata 263
- {{2, 2, 1}, DCT0, BFErr263, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-
- // DCT 1
- {{0, 0, 0}, FUNC_2, 0x140, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x144, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x148, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x14C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x150, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x154, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x158, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x15C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x160, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x164, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x168, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x16C, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x178, 0xFFCDBF0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x17C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 2, 0}, FUNC_2, 0x180, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x184, 0x07FFEFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x188, 0xFFFFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x18C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x190, 0x00FFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x1A4, 0x000F7B00, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x1A8, 0x0007FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x180), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x181), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x182), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x183), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), 0x30333333, DCT1_MASK, ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x001FBFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyClkConfig0, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyClkConfig1, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyClkConfig2, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyClkConfig3, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- // errata 322
- {{2, 2, 1}, DCT1, BFErr322I, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFErr322II, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- // errata 263
- {{2, 2, 1}, DCT1, BFErr263, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-
- // Restore F2x[1,0]94 right before exit self refresh
- {{0, 0, 0}, FUNC_2, 0x94, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x194, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK}
-};
-
-CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefC32 = {
- 0,
- (sizeof (S3CPciPreSelfDescriptorC32) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
- S3CPciPreSelfDescriptorC32,
- PciSpecialCaseFuncC32
-};
-
-CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorC32[] = {
- // DCT0
- {{2, 2, 1}, DCT0, BFEccDLLPwrDnConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFEccDLLConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10), 0x01FF01FF, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11), 0x01FF01FF, DCT0_MASK, 0x01},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12), 0x000001FF, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13), 0x01FF01FF, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14), 0x01FF01FF, DCT0_MASK, 0x04},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15), 0x000001FF, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16), 0x01FF01FF, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17), 0x01FF01FF, DCT0_MASK, 0x10},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18), 0x000001FF, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19), 0x01FF01FF, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A), 0x01FF01FF, DCT0_MASK, 0x40},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B), 0x000001FF, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20), 0x01FF01FF, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21), 0x01FF01FF, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23), 0x01FF01FF, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24), 0x01FF01FF, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26), 0x01FF01FF, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27), 0x01FF01FF, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29), 0x01FF01FF, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A), 0x01FF01FF, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01), 0x7F7F7F7F, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02), 0x7F7F7F7F, DCT0_MASK, 0x01},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03), 0x0000007F, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0x7F7F7F7F, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0x7F7F7F7F, DCT0_MASK, 0x04},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x0000007F, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0x7F7F7F7F, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0x7F7F7F7F, DCT0_MASK, 0x10},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x0000007F, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0x7F7F7F7F, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0x7F7F7F7F, DCT0_MASK, 0x40},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x0000007F, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05), 0x3F3F3F3F, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06), 0x3F3F3F3F, DCT0_MASK, 0x01},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x07), 0x0000003F, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3F3F3F3F, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3F3F3F3F, DCT0_MASK, 0x04},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x107), 0x0000003F, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3F3F3F3F, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3F3F3F3F, DCT0_MASK, 0x10},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x207), 0x0000003F, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3F3F3F3F, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3F3F3F3F, DCT0_MASK, 0x40},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x307), 0x0000003F, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0xFFFFFFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D), 0x23772377, DCT0_MASK, ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30), 0x00FF00FF, DCT0_DDR3_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31), 0x00FF00FF, DCT0_DDR3_MASK, 0x01},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32), 0x000000FF, DCT0_DDR3_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33), 0x00FF00FF, DCT0_DDR3_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34), 0x00FF00FF, DCT0_DDR3_MASK, 0x04},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35), 0x000000FF, DCT0_DDR3_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36), 0x00FF00FF, DCT0_DDR3_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37), 0x00FF00FF, DCT0_DDR3_MASK, 0x10},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38), 0x000000FF, DCT0_DDR3_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39), 0x00FF00FF, DCT0_DDR3_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B), 0x000000FF, DCT0_DDR3_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40), 0x00FF00FF, DCT0_DDR3_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41), 0x00FF00FF, DCT0_DDR3_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43), 0x00FF00FF, DCT0_DDR3_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44), 0x00FF00FF, DCT0_DDR3_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46), 0x00FF00FF, DCT0_DDR3_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47), 0x00FF00FF, DCT0_DDR3_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49), 0x00FF00FF, DCT0_DDR3_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40},
-
- // DCT1
- {{2, 2, 1}, DCT0, BFEccDLLPwrDnConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFEccDLLConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10), 0x01FF01FF, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11), 0x01FF01FF, DCT1_MASK, 0x02},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x12), 0x000001FF, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13), 0x01FF01FF, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14), 0x01FF01FF, DCT1_MASK, 0x08},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x15), 0x000001FF, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x16), 0x01FF01FF, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x17), 0x01FF01FF, DCT1_MASK, 0x20},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x18), 0x000001FF, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x19), 0x01FF01FF, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1A), 0x01FF01FF, DCT1_MASK, 0x80},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1B), 0x000001FF, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20), 0x01FF01FF, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21), 0x01FF01FF, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23), 0x01FF01FF, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24), 0x01FF01FF, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x26), 0x01FF01FF, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x27), 0x01FF01FF, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x29), 0x01FF01FF, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x2A), 0x01FF01FF, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01), 0x7F7F7F7F, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02), 0x7F7F7F7F, DCT1_MASK, 0x02},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x03), 0x0000007F, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101), 0x7F7F7F7F, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102), 0x7F7F7F7F, DCT1_MASK, 0x08},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x103), 0x0000007F, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x201), 0x7F7F7F7F, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x202), 0x7F7F7F7F, DCT1_MASK, 0x20},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x203), 0x0000007F, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x301), 0x7F7F7F7F, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x302), 0x7F7F7F7F, DCT1_MASK, 0x80},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x303), 0x0000007F, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05), 0x3F3F3F3F, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06), 0x3F3F3F3F, DCT1_MASK, 0x02},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x07), 0x0000003F, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105), 0x3F3F3F3F, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106), 0x3F3F3F3F, DCT1_MASK, 0x08},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x107), 0x0000003F, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x205), 0x3F3F3F3F, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x206), 0x3F3F3F3F, DCT1_MASK, 0x20},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x207), 0x0000003F, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x305), 0x3F3F3F3F, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x306), 0x3F3F3F3F, DCT1_MASK, 0x80},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x307), 0x0000003F, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D), 0x23772377, DCT1_MASK, ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30), 0x00FF00FF, DCT1_DDR3_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31), 0x00FF00FF, DCT1_DDR3_MASK, 0x02},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x32), 0x000000FF, DCT1_DDR3_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33), 0x00FF00FF, DCT1_DDR3_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34), 0x00FF00FF, DCT1_DDR3_MASK, 0x08},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x35), 0x000000FF, DCT1_DDR3_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x36), 0x00FF00FF, DCT1_DDR3_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x37), 0x00FF00FF, DCT1_DDR3_MASK, 0x20},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x38), 0x000000FF, DCT1_DDR3_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x39), 0x00FF00FF, DCT1_DDR3_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3B), 0x000000FF, DCT1_DDR3_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40), 0x00FF00FF, DCT1_DDR3_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41), 0x00FF00FF, DCT1_DDR3_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43), 0x00FF00FF, DCT1_DDR3_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44), 0x00FF00FF, DCT1_DDR3_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x46), 0x00FF00FF, DCT1_DDR3_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x47), 0x00FF00FF, DCT1_DDR3_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x49), 0x00FF00FF, DCT1_DDR3_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x4A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80},
-
- // Restore scrubber related registers after restoring training related registers
- {{0, 0, 0}, FUNC_3, 0x180, 0x027F7BFF, ANY_DIMM_MASK, ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_3, 0x44, 0xFFFFFFFE, ANY_DIMM_MASK, ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_3, 0x58, 0x1F1F1F1F, ANY_DIMM_MASK, ANY_DIMM_MASK},
- {{2, 1, 1}, DCT0, BFScrubReDirEn, 0x00000001, ANY_DIMM_MASK, ANY_DIMM_MASK}
-};
-
-CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefC32 = {
- 0,
- (sizeof (S3CPciPostSelfDescriptorC32) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
- S3CPciPostSelfDescriptorC32,
- PciSpecialCaseFuncC32
-};
-
-MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorC32[] = {
- {{0, 0, 0}, 0xC0010010, 0x00000000007F07FF},
- {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000},
- {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000},
- {{0, 0, 0}, 0xC001001F, 0xC047F87FFF527FFF}
-};
-
-CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefC32 = {
- 0,
- (sizeof (S3MSRPreSelfRefDescriptorC32) / sizeof (MSR_REG_DESCRIPTOR)),
- S3MSRPreSelfRefDescriptorC32,
- NULL
-};
-
-VOID *MemS3RegListC32[] = {
- (VOID *)&S3PciPreSelfRefC32,
- NULL,
- (VOID *)&S3CPciPreSelfRefC32,
- (VOID *)&S3CPciPostSelfRefC32,
- (VOID *)&S3MSRPreSelfRefC32,
- NULL,
- NULL,
- NULL
-};
-
-CONST UINT16 ROMDATA SpecialCasePCIRegC32[] = {
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04)
-};
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the northbridge block for S3 resume
- *
- * @param[in,out] *S3NBPtr - Pointer to MEM_NB_BLOCK.
- * @param[in,out] *MemPtr - Pointer to MEM_DATA_STRUCT.
- * @param[in] NodeID - Node ID of the target node.
- *
- * @return BOOLEAN
- * TRUE - This is the correct constructor for the targeted node.
- * FALSE - This isn't the correct constructor for the targeted node.
- */
-
-BOOLEAN
-MemS3ResumeConstructNBBlockC32 (
- IN OUT VOID *S3NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- )
-{
- INT32 i;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr;
- //
- // Determine if this is the expected NB Type
- //
- GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
- if (!MemNIsIdSupportedC32 (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
- return FALSE;
- }
-
- NBPtr->MemPtr = MemPtr;
- NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
- NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
- InitNBRegTableC32 (NBPtr, NBPtr->NBRegTable);
- NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
- NBPtr->Dct = 0;
- NBPtr->Channel = 0;
- NBPtr->Ganged = FALSE;
- NBPtr->NodeCount = MAX_NODES_SUPPORTED_C32;
- NBPtr->DctCount = MAX_DCTS_PER_NODE_C32;
-
- for (i = 0; i < EnumSize; i++) {
- NBPtr->IsSupported[i] = FALSE;
- }
-
- for (i = 0; i < NumberOfHooks; i++) {
- NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) memDefTrue;
- }
-
- LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader);
-
- NBPtr->IsSupported[CheckDllSpeedUp] = TRUE;
- NBPtr->SwitchDCT = MemNSwitchDCTNb;
- NBPtr->SwitchChannel = MemNSwitchChannelNb;
- NBPtr->GetBitField = MemNGetBitFieldNb;
- NBPtr->SetBitField = MemNSetBitFieldNb;
- NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldC32;
- NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedC32;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = MemNS3ExitSelfRefRegC32;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskNb;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK *, DESCRIPTOR_GROUP *)) memDefRet;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeNb;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = MemNS3RestoreScrubNb;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrC32;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstC32;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = (sizeof (SpecialCasePCIRegC32) / sizeof (UINT16)) * sizeof (UINT32);
-
- MemNSwitchDCTNb (NBPtr, 0);
-
- return TRUE;
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------*/
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function returns the register list for each device for C32
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP
- * @return UINT16 - size of the device descriptor on the target node.
- */
-UINT16
-STATIC
-MemNS3GetRegLstPtrC32 (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT DESCRIPTOR_GROUP *DescriptPtr
- )
-{
- UINT8 i;
- UINT16 Size;
- Size = 0;
- for (i = PRESELFREF; i <= POSTSELFREF; i ++) {
- DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i);
- DescriptPtr->PCIDevice[i].Node = NBPtr->Node;
- DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF;
- if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListC32[PCI_LST_ESR_C32 - PCI_LST_ESR_C32 + i] != NULL) {
- DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_C32 + i;
- Size += sizeof (PCI_DEVICE_DESCRIPTOR);
- }
- DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i);
- DescriptPtr->CPCIDevice[i].Node = NBPtr->Node;
- DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF;
- if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListC32[CPCI_LST_ESR_C32 - PCI_LST_ESR_C32 + i] != NULL) {
- DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_C32 + i;
- Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR);
- }
- DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i);
- DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF;
- if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListC32[MSR_LST_ESR_C32 - PCI_LST_ESR_C32 + i] != NULL) {
- DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_C32 + i;
- Size += sizeof (MSR_DEVICE_DESCRIPTOR);
- }
- DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i);
- DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF;
- if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListC32[CMSR_LST_ESR_C32 - PCI_LST_ESR_C32 + i] != NULL) {
- DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_C32 + i;
- Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR);
- }
- }
- return Size;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function return the register list according to the register ID.
- *
- * @param[in] RegisterLstID - value of the Register list ID.
- * @param[out] **RegisterHeader - pointer to the address of the register list.
- * @return none
- */
-AGESA_STATUS
-STATIC
-MemNS3GetDeviceRegLstC32 (
- IN UINT32 RegisterLstID,
- OUT VOID **RegisterHeader
- )
-{
- if (RegisterLstID >= (sizeof (MemS3RegListC32) / sizeof (VOID *))) {
- ASSERT(FALSE); // RegisterListID exceeded size of Register list
- return AGESA_FATAL;
- }
- if (MemS3RegListC32[RegisterLstID] != NULL) {
- *RegisterHeader = MemS3RegListC32[RegisterLstID];
- return AGESA_SUCCESS;
- }
- ASSERT(FALSE); // Device register list error
- return AGESA_FATAL;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function stores special case register on the heap.
- *
- * @param[in] AccessWidth - Access width of the register
- * @param[in] Address - address of the CSR register in PCI_ADDR format.
- * @param[in, out] *Value - Pointer to the value be read.
- * @param[in, out] *ConfigPtr - Pointer to Config handle.
- * @return none
- */
-VOID
-STATIC
-MemNS3SetSpecialPCIRegC32 (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR Address,
- IN VOID *Value,
- IN OUT VOID *ConfigPtr
- )
-{
- LOCATE_HEAP_PTR LocateBufferPtr;
- UINT8 i;
- UINT8 NodeID;
- UINT8 Offset;
- S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader;
-
- Offset = 0;
- LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
- if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) {
- SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr;
- // Get the node ID of the target die.
- NodeID = (UINT8) (Address.Address.Device - 24);
- for (i = 0; i < MAX_NODES_SUPPORTED_C32; i ++) {
- if (SpecialHeapHeader[i].Node == NodeID) {
- // Get the offset in the heap for the target die.
- Offset = SpecialHeapHeader[i].Offset;
- break;
- }
- }
- ASSERT (i < MAX_NODES_SUPPORTED_C32);
- // Save the value in the heap at appropriate offset based on the index
- // of the target register in the special case array.
- if (Offset != 0) {
- for (i = 0; i < (sizeof (SpecialCasePCIRegC32) / sizeof (UINT16)); i ++) {
- if (SpecialCasePCIRegC32[i] == Address.Address.Register) {
- *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)) = *(UINT32 *) Value;
- }
- }
- }
- }
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function stores special case register on the heap.
- *
- * @param[in,out] *NBPtr - Pointer to the northbridge block.
- * @param[in,out] *StdHeader - Config handle for library and services.
- * @return none
- */
-VOID
-STATIC
-MemNS3ExitSelfRefRegC32 (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- LOCATE_HEAP_PTR LocateBufferPtr;
- UINT8 i;
- PCI_ADDR PciAddr;
- UINT32 Value;
- UINT8 NodeID;
- UINT8 Offset;
- S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader;
-
- Offset = 0;
- PciAddr.Address.Device = NBPtr->PciAddr.Address.Device;
- PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus;
- PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment;
- PciAddr.Address.Function = 2;
- LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
- if (HeapLocateBuffer (&LocateBufferPtr, StdHeader) == AGESA_SUCCESS) {
- SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr;
- // Get the node ID of the target die.
- NodeID = (UINT8) (PciAddr.Address.Device - 24);
- for (i = 0; i < MAX_NODES_SUPPORTED_C32; i ++) {
- if (SpecialHeapHeader[i].Node == NodeID) {
- // Get the offset in the heap for the target die.
- Offset = SpecialHeapHeader[i].Offset;
- break;
- }
- }
- ASSERT (i < MAX_NODES_SUPPORTED_C32);
- // Restore the value one by one in the sequence of the special case register array.
- if (Offset != 0) {
- for (i = 0; i < (sizeof (SpecialCasePCIRegC32) / sizeof (UINT16)); i ++) {
- PciAddr.Address.Register = SpecialCasePCIRegC32[i];
- Value = *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2));
- MemNS3SetCSRNb (AccessS3SaveWidth32, PciAddr, &Value, StdHeader);
- }
- }
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mnS3c32.h b/src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mnS3c32.h
deleted file mode 100644
index 47d7001..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mnS3c32.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnS3c32.h
- *
- * S3 resume memory related function for C32.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/C32)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MNS3C32_H_
-#define _MNS3C32_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-/// ID for register list of C32
-typedef enum {
- PCI_LST_ESR_C32, ///< Assign 0x0000 for PCI register list for pre exit self refresh.
- PCI_LST_C32, ///< Assign 0x0001 for PCI register list for post exist self refresh.
- CPCI_LST_ESR_C32, ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh.
- CPCI_LST_C32, ///< Assign 0x0003 for conditional PCI register list for post exit self refresh.
- MSR_LST_ESR_C32, ///< Assign 0x0004 for MSR register list for pre exit self refresh.
- MSR_LST_C32, ///< Assign 0x0005 for MSR register list for post exit self refresh.
- CMSR_LST_ESR_C32, ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh.
- CMSR_LST_C32 ///< Assign 0x0007 for conditional MSR register list for post exit self refresh.
-} RegisterListIDC32;
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-#endif //_MNS3C32_H_
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mnc32.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mnc32.c
deleted file mode 100644
index a9e9e2d..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mnc32.c
+++ /dev/null
@@ -1,485 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnc32.c
- *
- * Common Northbridge functions for C32
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/C32)
- * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mnc32.h"
-#include "mu.h"
-#include "S3.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "heapManager.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_C32_MNC32_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the northbridge block
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
- * @param[in] *FeatPtr - Pointer to the MEM_FEAT_BLOCK_NB
- * @param[in] *SharedPtr - Pointer to the MEM_SHARED_DATA
- * @param[in] NodeID - UINT8 indicating node ID of the NB object.
- *
- * @return Boolean indicating that this is the correct memory
- * controller type for the node number that was passed in.
- */
-
-BOOLEAN
-MemConstructNBBlockC32 (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN MEM_FEAT_BLOCK_NB *FeatPtr,
- IN MEM_SHARED_DATA *SharedPtr,
- IN UINT8 NodeID
- )
-{
- UINT8 Dct;
- UINT8 Channel;
- UINT8 SpdSocketIndex;
- UINT8 SpdChannelIndex;
- DIE_STRUCT *MCTPtr;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
- //
- // Determine if this is the expected NB Type
- //
- GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
- if (!MemNIsIdSupportedC32 (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
- return FALSE;
- }
-
- NBPtr->MemPtr = MemPtr;
- NBPtr->RefPtr = MemPtr->ParameterListPtr;
- NBPtr->SharedPtr = SharedPtr;
-
- MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
- NBPtr->MCTPtr = MCTPtr;
- NBPtr->MCTPtr->NodeId = NodeID;
- NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue;
- NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
-
- //
- // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
- //
- AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_C32 * (
- sizeof (DCT_STRUCT) + (
- MAX_CHANNELS_PER_DCT_C32 * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))
- )
- );
- AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0);
- AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
- if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) {
- PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader);
- SetMemError (AGESA_FATAL, MCTPtr);
- ASSERT(FALSE); // Could not allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
- return FALSE;
- }
-
- MCTPtr->DctCount = MAX_DCTS_PER_NODE_C32;
- MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_C32 * sizeof (DCT_STRUCT);
- for (Dct = 0; Dct < MAX_DCTS_PER_NODE_C32; Dct++) {
- MCTPtr->DctData[Dct].Dct = Dct;
- MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_C32;
- MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr;
- MCTPtr->DctData[Dct].ChData[0].Dct = Dct;
- AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_C32 * sizeof (CH_DEF_STRUCT);
- }
- NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr;
-
- //
- // Initialize Socket List
- //
- for (Dct = 0; Dct < MAX_DCTS_PER_NODE_C32; Dct++) {
- MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr[(MCTPtr->DieId * 2) + Dct] = &(MCTPtr->DctData[Dct].ChData[0]);
- MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr[(MCTPtr->DieId * 2) + Dct] = &(MCTPtr->DctData[Dct].Timings);
- MCTPtr->DctData[Dct].ChData[0].ChannelID = (MCTPtr->DieId * 2) + Dct;
- }
-
- MemNInitNBDataC32 (NBPtr);
-
- FeatPtr->InitCPG (NBPtr);
- NBPtr->FeatPtr = FeatPtr;
- FeatPtr->InitHwRxEn (NBPtr);
- //
- // Calculate SPD Offsets per channel and assign pointers to the data. At this point, we calculate the Node-Dct-Channel
- // centric offsets and store the pointers to the first DIMM of each channel in the Channel Definition struct for that
- // channel. This pointer is then used later to calculate the offsets to be used for each logical dimm once the
- // dimm types(QR or not) are known. This is done in the Technology block constructor.
- //
- // Calculate the SpdSocketIndex separately from the SpdChannelIndex.
- // This will facilitate modifications due to some processors that might
- // map the DCT-CHANNEL differently.
- //
- SpdSocketIndex = GetSpdSocketIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, &MemPtr->StdHeader);
- //
- // Traverse the Dct/Channel structures
- //
- for (Dct = 0; Dct < MAX_DCTS_PER_NODE_C32; Dct++) {
- for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_C32; Channel++) {
- //
- // Calculate the number of Dimms on this channel using the
- // die/dct/channel to Socket/channel conversion.
- //
- SpdChannelIndex = GetSpdChannelIndex (NBPtr->RefPtr->PlatformMemoryConfiguration,
- NBPtr->MCTPtr->SocketId,
- MemNGetSocketRelativeChannelC32 (NBPtr, Dct, Channel),
- &MemPtr->StdHeader);
- NBPtr->MCTPtr->DctData[Dct].ChData[Channel].SpdPtr = &(MemPtr->SpdDataStructure[SpdSocketIndex + SpdChannelIndex]);
- }
- }
-
- MemNSwitchDCTNb (NBPtr, 0);
-
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initializes member functions and variables of NB block.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNInitNBDataC32 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- NBPtr->DctCachePtr = NBPtr->DctCache;
- NBPtr->PsPtr = NBPtr->PSBlock;
-
- InitNBRegTableC32 (NBPtr, NBPtr->NBRegTable);
- NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
- NBPtr->Dct = 0;
- NBPtr->Channel = 0;
- NBPtr->DctCount = MAX_DCTS_PER_NODE_C32;
- NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_C32;
- NBPtr->NodeCount = MAX_NODES_SUPPORTED_C32;
- NBPtr->Ganged = FALSE;
- NBPtr->PosTrnPattern = POS_PATTERN_256B;
- NBPtr->MemCleared = FALSE;
- NBPtr->StartupSpeed = DDR800_FREQUENCY;
- NBPtr->RcvrEnDlyLimit = 0x1FF;
- NBPtr->DefDctSelIntLvAddr = 3;
-
- LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader);
-
- NBPtr->SetMaxLatency = MemNSetMaxLatencyNb;
- NBPtr->getMaxLatParams = MemNGetMaxLatParamsNb;
- NBPtr->InitializeMCT = MemNInitializeMctC32;
- NBPtr->FinalizeMCT = MemNFinalizeMctC32;
- NBPtr->SendMrsCmd = MemNSendMrsCmdC32;
- NBPtr->sendZQCmd = MemNSendZQCmdNb;
- NBPtr->WritePattern = MemNWritePatternC32;
- NBPtr->ReadPattern = MemNReadPatternC32;
- NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet;
- NBPtr->CompareTestPattern = MemNCompareTestPatternNb;
- NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb;
- NBPtr->StitchMemory = MemNStitchMemoryNb;
- NBPtr->AutoConfig = MemNAutoConfigC32;
- NBPtr->PlatformSpec = MemNPlatformSpecNb;
- NBPtr->InitMCT = MemNInitMCTNb;
- NBPtr->DisableDCT = MemNDisableDCTNb;
- NBPtr->StartupDCT = MemNStartupDCTNb;
- NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb;
- NBPtr->ChangeFrequency = MemNChangeFrequencyNb;
- NBPtr->RampUpFrequency = MemNRampUpFrequencyNb;
- NBPtr->ChangeNbFrequency = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefFalse;
- NBPtr->ProgramCycTimings = MemNProgramCycTimingsNb;
- NBPtr->SyncDctsReady = MemNSyncDctsReadyNb;
- NBPtr->HtMemMapInit = MemNHtMemMapInitNb;
- NBPtr->SyncAddrMapToAllNodes = MemNSyncAddrMapToAllNodesNb;
- NBPtr->CpuMemTyping = MemNCPUMemTypingNb;
- NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingNb;
- NBPtr->AfterDqsTraining = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
- NBPtr->OtherTiming = MemNOtherTimingC32;
- NBPtr->UMAMemTyping = MemNUMAMemTypingNb;
- NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelC32;
- NBPtr->TechBlockSwitch = MemNTechBlockSwitchNb;
- NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldC32;
- NBPtr->SetEccSymbolSize = MemNSetEccSymbolSizeNb;
- NBPtr->TrainingFlow = MemNTrainingFlowNb;
- MemNInitNBDataNb (NBPtr);
-
- NBPtr->PollBitField = MemNPollBitFieldNb;
- NBPtr->BrdcstCheck = MemNBrdcstCheckNb;
- NBPtr->BrdcstSet = MemNBrdcstSetNb;
- NBPtr->GetTrainDly = MemNGetTrainDlyNb;
- NBPtr->SetTrainDly = MemNSetTrainDlyNb;
- NBPtr->PhyFenceTraining = MemNPhyFenceTrainingNb;
- NBPtr->GetSysAddr = MemNGetMCTSysAddrNb;
- NBPtr->RankEnabled = MemNRankEnabledNb;
- NBPtr->MemNBeforeDramInitNb = MemNBeforeDramInitC32;
- NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyNb;
- NBPtr->MemPPhyFenceTrainingNb = MemNTrainPhyFenceNb;
- NBPtr->MemNInitPhyComp = MemNInitPhyCompC32;
- NBPtr->MemNBeforePlatformSpecNb = MemNBeforePlatformSpecC32;
- NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitC32;
- NBPtr->MemNPFenceAdjustNb = (VOID (*) (MEM_NB_BLOCK *, UINT16 *)) memDefRet;
- NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsNb;
- NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb;
- NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb;
- NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb;
- NBPtr->CSPerChannel = MemNCSPerChannelNb;
- NBPtr->CSPerDelay = MemNCSPerDelayNb;
- NBPtr->FlushPattern = MemNFlushPatternNb;
- NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb;
- NBPtr->MemNCapSpeedBatteryLife = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
- NBPtr->GetUmaSize = MemNGetUmaSizeNb;
- NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdNb;
- NBPtr->EnableSwapIntlvRgn = (VOID (*) (MEM_NB_BLOCK *, UINT32, UINT32)) memDefRet;
- NBPtr->WaitXMemClks = MemNWaitXMemClksNb;
- NBPtr->MemNGetDramTerm = MemNGetDramTermNb;
- NBPtr->MemNGetDynDramTerm = MemNGetDynDramTermNb;
- NBPtr->MemNGetMR0CL = MemNGetMR0CLNb;
- NBPtr->MemNGetMR0WR = MemNGetMR0WRNb;
- NBPtr->MemNGetMR2CWL = MemNGetMR2CWLNb;
- NBPtr->AllocateC6Storage = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
-
- NBPtr->IsSupported[SetSpareEn] = TRUE;
- NBPtr->IsSupported[CheckSpareEn] = TRUE;
- NBPtr->IsSupported[SetDllShutDown] = TRUE;
- NBPtr->IsSupported[CheckEccDLLPwrDnConfig] = TRUE;
- NBPtr->IsSupported[CheckMaxDramRate] = TRUE;
- NBPtr->IsSupported[CheckMemClkCSPresent] = TRUE;
- NBPtr->IsSupported[CheckMaxRdDqsDlyPtr] = TRUE;
- NBPtr->IsSupported[CheckPhyFenceTraining] = TRUE;
- NBPtr->IsSupported[CheckSendAllMRCmds] = TRUE;
- NBPtr->IsSupported[CheckFindPSOverideWithSocket] = TRUE;
- NBPtr->IsSupported[CheckODTControls] = TRUE;
- NBPtr->IsSupported[CheckDummyCLRead] = TRUE;
- NBPtr->IsSupported[CheckSlewWithoutMarginImprv] = TRUE;
- NBPtr->IsSupported[CheckDllSpeedUp] = TRUE;
- NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the default values in the MEM_DATA_STRUCT
- *
- * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
- *
- */
-VOID
-MemNInitDefaultsC32 (
- IN OUT MEM_DATA_STRUCT *MemPtr
- )
-{
- UINT8 Socket;
- UINT8 Channel;
- MEM_PARAMETER_STRUCT *RefPtr;
- ASSERT (MemPtr != NULL);
- RefPtr = MemPtr->ParameterListPtr;
-
- // Memory Map/Mgt.
- // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB
- RefPtr->BottomIo = 0xE0;
- RefPtr->UmaMode = UserOptions.CfgUmaMode;
- RefPtr->UmaSize = UserOptions.CfgUmaSize;
- RefPtr->MemHoleRemapping = TRUE;
- //
-
-
- // Dram Timing
- RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect;
- RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect;
- for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) {
- for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) {
- MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL;
- MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL;
- }
- }
-
- // Memory Clear
- RefPtr->EnableMemClr = TRUE;
-
- // TableBasedAlterations
- RefPtr->TableBasedAlterations = NULL;
-
- // Platform config table
- RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration;
-
- // Memory Restore
- RefPtr->MemRestoreCtl = FALSE;
- RefPtr->SaveMemContextCtl = FALSE;
- AmdS3ParamsInitializer (&RefPtr->MemContext);
-
- // Dram Configuration
- RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving;
- RefPtr->EnableNodeIntlv = UserOptions.CfgMemoryEnableNodeInterleaving;
- RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving;
- RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle;
- RefPtr->EnableParity = UserOptions.CfgMemoryParityEnable;
- RefPtr->EnableOnLineSpareCtl = UserOptions.CfgOnlineSpare;
-
- // Dram Power
- RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown;
-
- // ECC
- RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- *
- * This function writes training pattern
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Pattern[] - Pattern to write
- * @param[in] Address - System Address [47:16]
- * @param[in] ClCount - Number of cache lines
- *
- */
-
-VOID
-MemNWritePatternC32 (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 Address,
- IN UINT8 Pattern[],
- IN UINT16 ClCount
- )
-{
- Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
- MemUWriteCachelines (Address, Pattern, ClCount);
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- *
- * This function reads training pattern
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Buffer[] - Buffer to fill
- * @param[in] Address - System Address [47:16]
- * @param[in] ClCount - Number of cache lines
- *
- */
-
-VOID
-MemNReadPatternC32 (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Buffer[],
- IN UINT32 Address,
- IN UINT16 ClCount
- )
-{
- Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
- MemUReadCachelines (Buffer, Address, ClCount);
-}
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initiates DQS training for Server NB
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-BOOLEAN
-memNEnableTrainSequenceC32 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- BOOLEAN Retval;
- Retval = TRUE;
- if (!MemNIsIdSupportedC32 (NBPtr, &(NBPtr->MemPtr->DiesPerSystem[NBPtr->MCTPtr->NodeId].LogicalCpuid))) {
- Retval = FALSE;
- }
- return Retval;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mnc32.h b/src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mnc32.h
deleted file mode 100644
index aaf65eb..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mnc32.h
+++ /dev/null
@@ -1,196 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnc32.h
- *
- * Northbridge C32
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem)
- * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MNC32_H_
-#define _MNC32_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-#define MAX_CHANNELS_PER_SOCKET_C32 2
-#define MAX_DCTS_PER_NODE_C32 2
-#define MAX_CHANNELS_PER_DCT_C32 1
-#define MAX_NODES_SUPPORTED_C32 8
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-MemConstructNBBlockC32 (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN MEM_FEAT_BLOCK_NB *FeatPtr,
- IN MEM_SHARED_DATA *SharedPtr,
- IN UINT8 NodeID
- );
-
-VOID
-MemNInitNBDataC32 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNInitDefaultsC32 (
- IN OUT MEM_DATA_STRUCT *MemPtr
- );
-
-BOOLEAN
-MemNInitializeMctC32 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNFinalizeMctC32 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNSendMrsCmdC32 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNAutoConfigC32 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNOtherTimingC32 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNInitPhyCompC32 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNWritePatternC32 (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 Address,
- IN UINT8 Pattern[],
- IN UINT16 ClCount
- );
-
-VOID
-MemNReadPatternC32 (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Buffer[],
- IN UINT32 Address,
- IN UINT16 ClCount
- );
-
-VOID
-InitNBRegTableC32 (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT TSEFO NBRegTable[]
- );
-
-UINT8
-MemNGetSocketRelativeChannelC32 (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Dct,
- IN UINT8 Channel
- );
-
-BOOLEAN
-MemNIsIdSupportedC32 (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN CPU_LOGICAL_ID *LogicalIdPtr
- );
-
-VOID
-MemNBeforeDramInitC32 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNPlatformSpecificFormFactorInitC32 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNEnDLLShutDownC32 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-UINT32
-MemNCmnGetSetFieldC32 (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN BIT_FIELD_NAME FieldName,
- IN UINT32 Field
- );
-
-VOID
-MemNBeforePlatformSpecC32 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-memNEnableTrainSequenceC32 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-#endif /* _MNC32_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mndctc32.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mndctc32.c
deleted file mode 100644
index 8dfc9e2..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mndctc32.c
+++ /dev/null
@@ -1,365 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mndctc32.c
- *
- * Northbridge DCT support for C32
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/C32)
- * @e \$Revision: 36462 $ @e \$Date: 2010-08-20 00:49:49 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mu.h"
-#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB
-#include "mnc32.h"
-#include "merrhdl.h"
-#include "cpuFamRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-#define FILECODE PROC_MEM_NB_C32_MNDCTC32_FILECODE
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define UNUSED_CLK 4
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function programs the memory controller with configuration parameters
- *
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - An Error value lower than AGESA_ERROR may have occurred
- * @return FALSE - An Error value greater than or equal to AGESA_ERROR may have occurred
- * @return NBPtr->MCTPtr->ErrCode - Contains detailed AGESA_STATUS value
- */
-
-BOOLEAN
-MemNAutoConfigC32 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 PowerDownMode;
- UINT32 Value32;
- DIE_STRUCT *MCTPtr;
- DCT_STRUCT *DCTPtr;
- MEM_PARAMETER_STRUCT *RefPtr;
-
- RefPtr = NBPtr->RefPtr;
- MCTPtr = NBPtr->MCTPtr;
- DCTPtr = NBPtr->DCTPtr;
- //======================================================================
- // Build Dram Control Register Value (F2x78)
- //======================================================================
- //
- //It is recommended that these bits remain in the default state.
- //MemNSetBitFieldNb (NBPtr, BFRdPtrInit, 5);
-
- MemNSetBitFieldNb (NBPtr, BFEarlyArbEn, 1);
-
- //======================================================================
- // Build Dram Config Lo Register Value
- //======================================================================
- //
-
- if (MCTPtr->Status[SbParDimms]) {
- //
- // SbParDimms should be set for all DDR3 RDIMMS
- // Cannot turn off ParEn for DDR3
- //
- //@attention - add debug option for parity control
- MemNSetBitFieldNb (NBPtr, BFParEn, 1);
- }
-
- if (MCTPtr->GangedMode) {
- MemNSetBitFieldNb (NBPtr, BFWidth128, 1);
- }
-
- MemNSetBitFieldNb (NBPtr, BFX4Dimm, DCTPtr->Timings.Dimmx4Present & 0xF);
-
- if (!MCTPtr->Status[SbRegistered]) {
- MemNSetBitFieldNb (NBPtr, BFUnBuffDimm, 1);
- }
-
- if (MCTPtr->Status[SbEccDimms]) {
- MemNSetBitFieldNb (NBPtr, BFDimmEccEn, 1);
- }
-
- //======================================================================
- // Build Dram Config Hi Register Value
- //======================================================================
- //
-
- MemNSetBitFieldNb (NBPtr, BFMemClkFreq, MemNGetMemClkFreqIdNb (NBPtr, DCTPtr->Timings.Speed));
-
- if (MCTPtr->Status[SbRegistered]) {
- if ((DCTPtr->Timings.Dimmx4Present != 0) && (DCTPtr->Timings.Dimmx8Present != 0)) {
- MemNSetBitFieldNb (NBPtr, BFRDqsEn, 1);
- }
- }
-
- if (RefPtr->EnableBankSwizzle) {
- MemNSetBitFieldNb (NBPtr, BFBankSwizzleMode, 1);
- }
-
- if (DCTPtr->Timings.DimmQrPresent) {
- if (UserOptions.CfgMemoryQuadrankType == QUADRANK_UNBUFFERED) {
- MemNSetBitFieldNb (NBPtr, BFFourRankSoDimm, 1);
- } else if (UserOptions.CfgMemoryQuadrankType == QUADRANK_REGISTERED) {
- MemNSetBitFieldNb (NBPtr, BFFourRankRDimm, 1);
- }
- }
-
- MemNSetBitFieldNb (NBPtr, BFDcqBypassMax, 0xF);
- MemNSetBitFieldNb (NBPtr, BFDcqArbBypassEn, 1);
- //======================================================================
- // Build Dram Config Misc Register Value
- //======================================================================
- //
- if (MCTPtr->Status[SbRegistered]) {
- if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode)!= 0) {
- MemNSetBitFieldNb (NBPtr, BFSubMemclkRegDly, 1);
- }
- }
- //======================================================================
- // Build Dram Config Misc 2 Register Value
- //======================================================================
- //
- //
- // Ddr3FourSocketCh - Must be the same for both DCTs if either of them have > 2 Dimms
- //
- if ((GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID)) > 2) {
- MemNBrdcstSetNb (NBPtr, BFDdr3FourSocketCh, 1);
- }
- //
- // DTaxTxFifpWrDly
- //
- Value32 = MemNGetBitFieldNb (NBPtr, BFRdPtrInit);
- if ((Value32 >= 2) && (Value32 <= 5)) {
- MemNSetBitFieldNb (NBPtr, BFDataTxFifoWrDly, (6 - Value32));
- }
-
- //
- // ProgOdtEn
- //
- if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 1) {
- MemNSetBitFieldNb (NBPtr, BFProgOdtEn, 1);
- } else {
- MemNSetBitFieldNb (NBPtr, BFProgOdtEn, 0);
- }
- //
- // OdtSwizzle
- //
- if ((MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 0) && (MemNGetBitFieldNb (NBPtr, BFFourRankRDimm) == 0) && (RefPtr->EnablePowerDown)) {
- PowerDownMode = (UINT8) ((UserOptions.CfgPowerDownMode == POWER_DOWN_MODE_AUTO) ? POWER_DOWN_BY_CHANNEL : UserOptions.CfgPowerDownMode);
- IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader));
- if (PowerDownMode == 1) {
- MemNSetBitFieldNb (NBPtr, BFOdtSwizzle, 1);
- }
- }
-
-
- return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function sends an MRS command
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNSendMrsCmdC32 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MemNSwapBitsNb (NBPtr);
-
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tCS%d MR%d %04x\n",
- (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 20) & 0xF,
- (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 16) & 0xF,
- (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) & 0xFFFF));
-
- // 1.Set SendMrsCmd=1
- MemNSetBitFieldNb (NBPtr, BFSendMrsCmd, 1);
-
- // 2.Wait for SendMrsCmd=0
- MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This is a general purpose function that executes before DRAM init
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNBeforeDramInitC32 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 Dct;
- for (Dct = 0; Dct < NBPtr->DctCount; Dct ++) {
- MemNSwitchDCTNb (NBPtr, Dct);
- if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
- //Set PllLockTime and DllLockTime to default.
- MemNSetBitFieldNb (NBPtr, BFPhyPLLLockTime, 0x000007D0);
- MemNSetBitFieldNb (NBPtr, BFPhyDLLLockTime, 0x00000190);
- MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 1);
- }
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * Enable DLL Shut down
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-VOID
-MemNEnDLLShutDownC32 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 Dct;
- BOOLEAN DllShutDownEn;
-
- DllShutDownEn = TRUE;
- IDS_OPTION_HOOK (IDS_DLL_SHUT_DOWN, &DllShutDownEn, &(NBPtr->MemPtr->StdHeader));
-
- if (DllShutDownEn && NBPtr->IsSupported[SetDllShutDown]) {
- if ((NBPtr->ChannelPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_D1) != 0) {
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- MemNSwitchDCTNb (NBPtr, Dct);
- if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
- MemNSetBitFieldNb (NBPtr, BFPhyPLLLockTime, 0x0000001C);
- MemNSetBitFieldNb (NBPtr, BFPhyDLLLockTime, 0x0000013D);
- MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 0);
- }
- }
- }
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * Workaround for erratum 322 and 263
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-VOID
-MemNBeforePlatformSpecC32 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- // Errata 263
- if ((NBPtr->DCTPtr->Timings.Speed == DDR533_FREQUENCY) || (NBPtr->DCTPtr->Timings.Speed == DDR667_FREQUENCY)) {
- MemNSetBitFieldNb (NBPtr, BFErr263, 0x0800);
- } else {
- MemNSetBitFieldNb (NBPtr, BFErr263, 0);
- }
-
- // Errata 322
- // 1.Write 00000000h to F2x[1,0]9C_xD08E000
- MemNSetBitFieldNb (NBPtr, BFErr322I, 0);
- // 2.If DRAM Configuration Register[MemClkFreq] (F2x[1,0]94[2:0]) is
- // greater than or equal to 011b (DDR-800 and higher),
- // then write 00000080h to F2x[1,0]9C_xD02E001,
- // else write 00000090h to F2x[1,0]9C_xD02E001.
- MemNSetBitFieldNb (NBPtr, BFErr322II, (NBPtr->DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ? 0x80 : 0x90);
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mnflowc32.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mnflowc32.c
deleted file mode 100644
index 2785673..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mnflowc32.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnflowc32.c
- *
- * C32 initializer for MCT and DCT
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/C32)
- * @e \$Revision: 36462 $ @e \$Date: 2010-08-20 00:49:49 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mnc32.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_C32_MNFLOWC32_FILECODE
-/* features */
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledC32[MAX_FF_TYPES];
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the platform specific block
- *
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - AGESA_SUCCESS at least one dorm factor was found
- * @return FALSE - AGESA_UNSUPPORTED - Error indicating that no form factors were found
- */
-
-BOOLEAN
-MemNPlatformSpecificFormFactorInitC32 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 Dct;
- UINT8 f;
- UINT8 ErrUnSuppFFCount;
- for (Dct = 0; Dct < MAX_DCTS_PER_NODE_C32; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- if (NBPtr->ChannelPtr->ChDimmValid != 0) {
- ErrUnSuppFFCount = 0;
- for (f = 0; f < MAX_FF_TYPES; f++) {
- ASSERT (memPlatSpecFFInstalledC32[f] != NULL);
- if (memPlatSpecFFInstalledC32[f] (NBPtr->MemPtr, NBPtr->ChannelPtr, NBPtr->PsPtr) == AGESA_UNSUPPORTED) {
- ErrUnSuppFFCount++; //Count the number of AGESA_UNSUPPORTED errors
- } else {
- break;
- }
- }
- if (ErrUnSuppFFCount == MAX_FF_TYPES) {
- return FALSE; // No FF types are supported
- }
- }
- }
- return TRUE;
-}
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mnidendimmc32.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mnidendimmc32.c
deleted file mode 100644
index 84a997e..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mnidendimmc32.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnidendimmc32.c
- *
- * C32 northbridge constructor for dimm identification translator.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/C32)
- * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "mm.h"
-#include "mn.h"
-#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB
-#include "mnc32.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_C32_MNIDENDIMMC32_FILECODE
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the northbridge block for dimm identification translator
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
- * @param[in,out] NodeID - ID of current node to construct
- * @return TRUE - This is the correct constructor for the targeted node.
- * @return FALSE - This isn't the correct constructor for the targeted node.
- */
-
-BOOLEAN
-MemNIdentifyDimmConstructorC32 (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- )
-{
- //
- // Determine if this is the expected NB Type
- //
- GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
- if (!MemNIsIdSupportedC32 (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
- return FALSE;
- }
-
- NBPtr->NodeCount = MAX_NODES_SUPPORTED_C32;
- NBPtr->DctCount = MAX_DCTS_PER_NODE_C32;
- NBPtr->MemPtr = MemPtr;
- NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
- NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
- NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
- NBPtr->Ganged = FALSE;
- InitNBRegTableC32 (NBPtr, NBPtr->NBRegTable);
- NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldC32;
- NBPtr->SetBitField = MemNSetBitFieldNb;
- NBPtr->GetBitField = MemNGetBitFieldNb;
- NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelC32;
-
- return TRUE;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mnmctc32.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mnmctc32.c
deleted file mode 100644
index 7561ad6..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mnmctc32.c
+++ /dev/null
@@ -1,195 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnmctc32.c
- *
- * Northbridge C32 MCT supporting functions
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/C32)
- * @e \$Revision: 36462 $ @e \$Date: 2010-08-20 00:49:49 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mport.h"
-#include "mm.h"
-#include "mn.h"
-#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB
-#include "mnc32.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_C32_MNMCTC32_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-extern BUILD_OPT_CFG UserOptions;
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function sets final values in BUCFG and BUCFG2
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemNFinalizeMctC32 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MEM_DATA_STRUCT *MemPtr;
- S_UINT64 SMsr;
- UINT16 Speed;
- UINT32 ExtMctCfgLoRegVal;
-
- MemPtr = NBPtr->MemPtr;
- Speed = NBPtr->DCTPtr->Timings.Speed;
- MemNSetBitFieldNb (NBPtr, BFMctCfgHiReg, (!NBPtr->Ganged) ? 0x2CE00F60 : 0x2CE00F40);
-
- ExtMctCfgLoRegVal = MemNGetBitFieldNb (NBPtr, BFExtMctCfgLoReg);
- ExtMctCfgLoRegVal |= (NBPtr->Ganged) ? 0x0FC00001 : 0x0FC01001;
-
- ExtMctCfgLoRegVal &= 0x0FFFFFFF;
- if (Speed == DDR667_FREQUENCY) {
- ExtMctCfgLoRegVal |= 0x40000000;
- } else if (Speed == DDR800_FREQUENCY) {
- ExtMctCfgLoRegVal |= 0x50000000;
- } else if (Speed == DDR1066_FREQUENCY) {
- ExtMctCfgLoRegVal |= 0x60000000;
- } else if (Speed == DDR1333_FREQUENCY) {
- ExtMctCfgLoRegVal |= 0x80000000;
- } else {
- ExtMctCfgLoRegVal |= 0x90000000;
- }
- MemNSetBitFieldNb (NBPtr, BFExtMctCfgLoReg, ExtMctCfgLoRegVal);
-
- if (NBPtr->Node == BSP_DIE) {
- if (!NBPtr->ClToNbFlag) {
- LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- SMsr.lo &= ~((UINT32)1 << 15); // ClLinesToNbDis
- LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- }
-
- LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- SMsr.hi &= ~((UINT32)1 << (48 - 32)); // WbEnhWsbDis
- LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- }
-
- return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function sets initial values in BUCFG and BUCFG2
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemNInitializeMctC32 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MEM_DATA_STRUCT *MemPtr;
- S_UINT64 SMsr;
-
- MemPtr = NBPtr->MemPtr;
-
- if (NBPtr->Node == BSP_DIE) {
- LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- if (SMsr.lo & ((UINT32)1 << 15)) {
- NBPtr->ClToNbFlag = 1;
- }
- SMsr.lo |= (UINT32)1 << 15; // ClLinesToNbDis
- LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-
- LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- SMsr.hi |= (UINT32)1 << (48 - 32); // WbEnhWsbDis
- LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- }
- return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mnotc32.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mnotc32.c
deleted file mode 100644
index 164d7f4..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mnotc32.c
+++ /dev/null
@@ -1,241 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnotc32.c
- *
- * Northbridge Non-SPD timings for C32
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/C32)
- * @e \$Revision: 36462 $ @e \$Date: 2010-08-20 00:49:49 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB
-#include "mnc32.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_C32_MNOTC32_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-VOID
-STATIC
-MemNSetOtherTimingC32 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-UINT32
-STATIC
-MemNGetODTDelaysC32 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function sets the non-SPD timings
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemNOtherTimingC32 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MemNSwitchDCTNb (NBPtr, 0);
- if (NBPtr->DCTPtr->Timings.DctDimmValid > 0) {
- MemNSetOtherTimingC32 (NBPtr);
- MemNPowerDownCtlNb (NBPtr);
- MemNEnDLLShutDownC32 (NBPtr);
- }
-
- MemNSwitchDCTNb (NBPtr, 1);
- if ((NBPtr->DCTPtr->Timings.DctDimmValid > 0) && (NBPtr->MCTPtr->GangedMode == FALSE)) {
- MemNSetOtherTimingC32 (NBPtr);
- MemNPowerDownCtlNb (NBPtr);
- MemNEnDLLShutDownC32 (NBPtr);
- }
- return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function sets the non-SPD timings in PCI registers
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-STATIC
-MemNSetOtherTimingC32 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
-
- MemNSetBitFieldNb (NBPtr, BFTrdrd, MemNGetTrdrdNb (NBPtr));
- MemNSetBitFieldNb (NBPtr, BFTwrwr, MemNGetTwrwrNb (NBPtr));
- MemNSetBitFieldNb (NBPtr, BFTwrrd, MemNGetTwrrdNb (NBPtr));
- MemNSetBitFieldNb (NBPtr, BFTrwtTO, MemNGetTrwtTONb (NBPtr));
- MemNSetBitFieldNb (NBPtr, BFTrwtWB, MemNGetTrwtWBNb (NBPtr));
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function gets the ODT delays
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-UINT32
-STATIC
-MemNGetODTDelaysC32 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- INT8 Ld;
- UINT32 ODTDelays;
- //
- // On revision D processors, the BIOS must additionally configure the ODT pattern
- // and the ODT switching delays.
- //
- // Program F2x[1, 0]9C_x83 DRAM Phy ODT Assertion Control Register based on Burst length.
- // -Read the Burst Length from F2x[1, 0]84[BurstCtrl].
- // -Value of 2, BL = 4 else assume BL=8.
- // -Initialize ODTDelays based on BL value
- // -WrOdtOnDuration [14:12] = BL / 2 + 1
- // -WrOdtTrnOnDly [10:8] = 0
- // -RdOdtOnDuration [6:4] = BL / 2 + 1
- //
- ODTDelays = (MemNGetBitFieldNb (NBPtr, BFBurstCtrl) == 2) ? 0x00003030 : 0x00005050;
-
- // RdOdtTrnOnDly [3:0] < (CL-CWL) or (CL-CWL - 1)
- // See BKDG F2x[1, 0]9C_x83 DRAM Phy ODT Assertion Control Register [3:0]
- Ld = ((INT8)MemNGetBitFieldNb (NBPtr, BFTcl) + 1) - ((INT8)MemNGetBitFieldNb (NBPtr, BFTcwl) + 5);
- if (Ld < 0) {
- Ld = 0;
- }
- if (Ld > 7) {
- Ld = 7;
- }
- ODTDelays += Ld;
- return ODTDelays;
-}
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function enables power down mode
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-STATIC
-MemNPowerDownCtlC32 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MEM_PARAMETER_STRUCT *RefPtr;
- UINT8 PowerDownMode;
-
- RefPtr = NBPtr->RefPtr;
-
- // we can't enable powerdown mode when doing WL
- if (RefPtr->EnablePowerDown) {
- MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 1);
- PowerDownMode = (UINT8) UserOptions.CfgPowerDownMode;
- IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader));
- if (PowerDownMode) {
- MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1);
- }
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mnphyc32.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mnphyc32.c
deleted file mode 100644
index b05090b..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mnphyc32.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnphyc32.c
- *
- * Northbridge Phy support for C32
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/C32)
- * @e \$Revision: 36462 $ @e \$Date: 2010-08-20 00:49:49 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mu.h"
-#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB
-#include "mnc32.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_C32_MNPHYC32_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define UNUSED_CLK 4
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the DDR phy compensation logic
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNInitPhyCompC32 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- CONST UINT8 TableCompRiseSlew20x[] = {7, 3, 2, 2};
- CONST UINT8 TableCompRiseSlew15x[] = {7, 7, 3, 2};
- CONST UINT8 TableCompFallSlew20x[] = {7, 5, 3, 2};
- CONST UINT8 TableCompFallSlew15x[] = {7, 7, 5, 3};
- UINT8 i;
- UINT8 j;
- UINT8 CurrDct;
- CurrDct = NBPtr->Dct;
- // 1. BIOS disables the phy compensation register by programming F2x9C_x08[DisAutoComp]=1
- // 2. BIOS waits 5 us for the disabling of the compensation engine to complete.
- // DisAutoComp will be cleared after Dram init has completed
- //
- MemNSwitchDCTNb (NBPtr, 0);
- MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 1);
- MemUWait10ns (500, NBPtr->MemPtr);
- MemNSwitchDCTNb (NBPtr, CurrDct);
-
- // 3. For each normalized driver strength code read from
- // F2x[1, 0]9C_x00[AddrCmdDrvStren], program the
- // corresponding 3 bit predriver code in F2x9C_x0A[D3Cmp1NCal, D3Cmp1PCal].
- //
- // 4. For each normalized driver strength code read from
- // F2x[1, 0]9C_x00[DataDrvStren], program the corresponding
- // 3 bit predriver code in F2x9C_x0A[D3Cmp0NCal, D3Cmp0PCal, D3Cmp2NCal,
- // D3Cmp2PCal].
- //
- j = (UINT8) MemNGetBitFieldNb (NBPtr, BFAddrCmdDrvStren);
- i = (UINT8) MemNGetBitFieldNb (NBPtr, BFDataDrvStren);
-
- MemNSwitchDCTNb (NBPtr, 0);
- ASSERT (j <= 3);
- MemNSetBitFieldNb (NBPtr, BFD3Cmp1NCal, TableCompRiseSlew20x[j]);
- MemNSetBitFieldNb (NBPtr, BFD3Cmp1PCal, TableCompFallSlew20x[j]);
-
- if ((NBPtr->ChannelPtr->Dimms == 3) &&
- ((NBPtr->DCTPtr->Timings.Speed == DDR800_FREQUENCY) ||
- (NBPtr->DCTPtr->Timings.Speed == DDR1066_FREQUENCY))) {
- //
- // Special Case for 3 Dimms @ 800MHz or 1066MHz
- //
- MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, 1);
- MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, 1);
- MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, 1);
- MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, 1);
- } else {
- ASSERT (i <= 3);
- MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, TableCompRiseSlew15x[i]);
- MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, TableCompFallSlew15x[i]);
- MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, TableCompRiseSlew15x[i]);
- MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, TableCompFallSlew15x[i]);
- }
- MemNSwitchDCTNb (NBPtr, CurrDct);
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mnprotoc32.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mnprotoc32.c
deleted file mode 100644
index f81679b..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mnprotoc32.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnprotoc32.c
- *
- * Northbridge support functions for Errata and early samples
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/C32)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-
-#include "AGESA.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_C32_MNPROTOC32_FILECODE
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mnregc32.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mnregc32.c
deleted file mode 100644
index c4ae310..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/C32/mnregc32.c
+++ /dev/null
@@ -1,627 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnregc32.c
- *
- * Common Northbridge register related functions for C32
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/C32)
- * @e \$Revision: 38303 $ @e \$Date: 2010-09-22 00:22:47 +0800 (Wed, 22 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mnc32.h"
-#include "merrhdl.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_C32_MNREGC32_FILECODE
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/*-----------------------------------------------------------------------------*/
-/**
- * MemNIsIdSupportedC32
- * This function matches the CPU_LOGICAL_ID with certain criteria to
- * determine if it is supported by this NBBlock.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID
- *
- * @return TRUE - This node is a C32.
- * @return FALSE - This node is not a C32.
- *
- */
-BOOLEAN
-MemNIsIdSupportedC32 (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN CPU_LOGICAL_ID *LogicalIdPtr
- )
-{
- if (((LogicalIdPtr->Family & AMD_FAMILY_10_C32) != 0) && ((LogicalIdPtr->Revision & AMD_F10_C32_ALL) != 0)) {
- return TRUE;
- } else {
- return FALSE;
- }
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- * This function calculates the memory channel index relative to the
- * socket, taking the Die number, the Dct, and the channel.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Dct
- * @param[in] Channel
- *
- */
-UINT8
-MemNGetSocketRelativeChannelC32 (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Dct,
- IN UINT8 Channel
- )
-{
- return ((NBPtr->MCTPtr->DieId * MAX_DCTS_PER_NODE_C32) + Dct);
-}
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------*/
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function gets or sets a value to a bit field in a PCI register.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] FieldName - Bit Field to be programmed
- * @param[in] Field - Value to be programmed
- * @param[in] IsSet - Indicates if the function will set or get
- *
- * @return value read, if the function is used as a "get"
- */
-
-UINT32
-MemNCmnGetSetFieldC32 (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN BIT_FIELD_NAME FieldName,
- IN UINT32 Field
- )
-{
- TSEFO Address;
- PCI_ADDR PciAddr;
- UINT8 Type;
- UINT8 IsLinked;
- UINT32 Value;
- UINT32 Highbit;
- UINT32 Lowbit;
- UINT32 Mask;
-
- Value = 0;
- if ((FieldName < BFEndOfList) && (FieldName >= 0)) {
- Address = NBPtr->NBRegTable[FieldName];
- if (Address) {
- Lowbit = TSEFO_END (Address);
- Highbit = TSEFO_START (Address);
- Type = (UINT8) TSEFO_TYPE (Address);
- IsLinked = (UINT8) TSEFO_LINKED (Address);
-
- // If Fn2 and DCT1 selected, set Address to be 1xx
- if ((Type == NB_ACCESS) && ((Address & 0xF000) == 0x2000) && NBPtr->Dct) {
- if (!NBPtr->Ganged || (Address & 0xFF) == 0x98 || (Address & 0xFF) == 0x9C) {
- Address |= 0x0100;
- }
- }
-
- ASSERT ((Address & ((UINT32) 1) << 28) == 0); // Phy direct access method is not supported
-
- if ((Address >> 29) == ((DCT_PHY_ACCESS << 1) | 1)) {
- // Special DCT Phy access
- Address &= 0x0FFFFFFF;
- Lowbit = 0;
- Highbit = 16;
- IsLinked = 0;
- } else {
- // Normal DCT Phy access
- Address = TSEFO_OFFSET (Address);
- }
-
- if (Type == NB_ACCESS) {
- PciAddr.AddressValue = Address;
- PciAddr.Address.Device = NBPtr->PciAddr.Address.Device;
- PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus;
- PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment;
- Address = PciAddr.AddressValue;
- LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
- if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) &&
- (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) {
- IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Value);
- }
- } else if (Type == DCT_PHY_ACCESS) {
- MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
- MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
- Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
- IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%d9C_%x = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Value);
- } else if (Type == DCT_EXTRA) {
- MemNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address);
- MemNPollBitFieldNb (NBPtr, BFDctExtraAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
- Value = MemNGetBitFieldNb (NBPtr, BFDctExtraDataReg);
- IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%dF4_%x = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Value);
- } else {
- IDS_ERROR_TRAP;
- }
-
- if (IsSet) {
- // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
- if ((Highbit - Lowbit) != 31) {
- Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
- } else {
- Mask = (UINT32)0xFFFFFFFF;
- }
- Value &= ~(Mask << Lowbit);
- Value |= (Field & Mask) << Lowbit;
-
- if (Type == NB_ACCESS) {
- PciAddr.AddressValue = Address;
- LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
- if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) &&
- (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) {
- IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Highbit, Lowbit, Field);
- }
- } else if (Type == DCT_PHY_ACCESS) {
- MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
- Address |= DCT_ACCESS_WRITE;
- MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
- MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
- IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%d9C_%x [%d:%d] = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Highbit, Lowbit, Field);
- } else if (Type == DCT_EXTRA) {
- MemNSetBitFieldNb (NBPtr, BFDctExtraDataReg, Value);
- Address |= DCT_ACCESS_WRITE;
- MemNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address);
- MemNPollBitFieldNb (NBPtr, BFDctExtraAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
- IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%dF4_%x [%d:%d] = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Highbit, Lowbit, Field);
- } else {
- IDS_ERROR_TRAP;
- }
- if (IsLinked) {
- MemNCmnGetSetFieldC32 (NBPtr, 1, FieldName + 1, Field >> (Highbit - Lowbit + 1));
- }
- } else {
- Value = Value >> Lowbit; // Shift
- // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
- if ((Highbit - Lowbit) != 31) {
- Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
- }
- if (IsLinked) {
- Value |= MemNCmnGetSetFieldC32 (NBPtr, 0, FieldName + 1, 0) << (Highbit - Lowbit + 1);
- }
- }
- }
- } else {
- IDS_ERROR_TRAP; // Invalid bit field index
- }
- return Value;
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes bit field translation table
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] NBRegTable[] - Pointer to the bit field data structure
- *
- */
-
-VOID
-InitNBRegTableC32 (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT TSEFO NBRegTable[]
- )
-{
- UINT16 i;
- for (i = 0; i < BFEndOfList; i++) {
- NBRegTable[i] = 0;
- }
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31, 0, BFDevVendorIDReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60), 2, 0, BFNodeID);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60), 6, 4, BFNodeCnt);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x48), 31, 0, BFDramBaseReg1);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x4C), 31, 0, BFDramLimitReg1);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x50), 31, 0, BFDramBaseReg2);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x54), 31, 0, BFDramLimitReg2);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x58), 31, 0, BFDramBaseReg3);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x5C), 31, 0, BFDramLimitReg3);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x60), 31, 0, BFDramBaseReg4);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x64), 31, 0, BFDramLimitReg4);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x68), 31, 0, BFDramBaseReg5);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x6C), 31, 0, BFDramLimitReg5);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x70), 31, 0, BFDramBaseReg6);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x74), 31, 0, BFDramLimitReg6);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x78), 31, 0, BFDramBaseReg7);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x7C), 31, 0, BFDramLimitReg7);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 0, BFDramHoleAddrReg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x140), 7, 0, BFDramBaseHiReg0);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x144), 7, 0, BFDramLimitHiReg0);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x148), 7, 0, BFDramBaseHiReg1);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x14C), 7, 0, BFDramLimitHiReg1);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x150), 7, 0, BFDramBaseHiReg2);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x154), 7, 0, BFDramLimitHiReg2);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x158), 7, 0, BFDramBaseHiReg3);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x15C), 7, 0, BFDramLimitHiReg3);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x160), 7, 0, BFDramBaseHiReg4);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x164), 7, 0, BFDramLimitHiReg4);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x168), 7, 0, BFDramBaseHiReg5);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x16C), 7, 0, BFDramLimitHiReg5);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x170), 7, 0, BFDramBaseHiReg6);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x174), 7, 0, BFDramLimitHiReg6);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x178), 7, 0, BFDramBaseHiReg7);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x17C), 7, 0, BFDramLimitHiReg7);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 24, BFDramHoleBase);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 15, 7, BFDramHoleOffset);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 1, 1, BFDramMemHoistValid);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 0, 0, BFDramHoleValid);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 20, 0, BFDramBaseAddr);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 23, 21, BFDramIntlvSel);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 20, 0, BFDramLimitAddr);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 26, 21, BFDramIntlvEn);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31, 0, BFCSBaseAddr0Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31, 0, BFCSBaseAddr1Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31, 0, BFCSBaseAddr2Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31, 0, BFCSBaseAddr3Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x50), 31, 0, BFCSBaseAddr4Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x54), 31, 0, BFCSBaseAddr5Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x58), 31, 0, BFCSBaseAddr6Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x5C), 31, 0, BFCSBaseAddr7Reg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31, 0, BFCSMask0Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31, 0, BFCSMask1Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x68), 31, 0, BFCSMask2Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x6C), 31, 0, BFCSMask3Reg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 0, BFDramControlReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 0, BFDramInitRegReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31, 0, BFDramBankAddrReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31, 0, BFDramMRSReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 0, BFDramTimingLoReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 0, BFDramTimingHiReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31, 0, BFDramConfigLoReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 0, BFDramConfigHiReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 0, BFDctAddlOffsetReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31, 0, BFDctAddlDataReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 31, BFDctAccessDone);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA0), 31, 0, BFDramConfigMiscReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 31, 0, BFDramCtrlMiscReg2);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF0), 31, 0, BFDctExtraOffsetReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF4), 31, 0, BFDctExtraDataReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF0), 31, 31, BFDctExtraAccessDone);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 31, 0, BFMctCfgHiReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 31, 0, BFMctCfgLoReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 31, 0, BFExtMctCfgLoReg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x40), 31, 0, BFMcaNbCtlReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44), 22, 22, BFDramEccEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44), 2, 2, BFSyncOnUcEccEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x180), 25, 25, BFEccSymbolSize);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x48), 31, 0, BFMcaNbStatusLoReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x4C), 31, 0, BFMcaNbStatusHiReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 4, 0, BFDramScrub);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 12, 8, BFL2Scrub);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 20, 16, BFDcacheScrub);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 28, 24, BFL3Scrub);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C), 0, 0, BFScrubReDirEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C), 31, 0, BFScrubAddrLoReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x60), 31, 0, BFScrubAddrHiReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x8C), 4, 4, BFDisDatMsk);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4), 4, 0, BFNbFid);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4), 13, 13, BFMTC1eEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 25, 25, BFL3Capable);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x188), 8, 8, BFDisableL3);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 8, BFNonSPDHi);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 3, 0, BFRdPtrInit);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 9, 8, BFTwrrdHi);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 11, 10, BFTwrwrHi);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 12, BFTrdrdHi);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 16, 16, BFAltVidC3MemClkTriEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 18, 18, BFDqsRcvEnTrain);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 19, 19, BFEarlyArbEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15, 0, BFMrsAddress);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 18, 16, BFMrsBank);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 22, 20, BFMrsChipSel);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 24, 24, BFSendPchgAll);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 25, 25, BFSendAutoRefresh);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 30, 30, BFSendCtrlWord);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 7, 7, BFMrsLevel);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 12, 12, BFMrsQoff);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 1, 0, BFBurstCtrl);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 3, 2, BFDrvImpCtrl);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 9, 7, BFDramTerm_DDR3);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 11, 10, BFDramTermDyn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 13, 13, BFQoff);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 18, 18, BFASR);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 19, 19, BFSRT);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 22, 20, BFTcwl);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 23, 23, BFPchgPDModeSel);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 6, 4, BFTwrDDR3);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 3, 0, BFTcl);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 6, 4, BFTrcd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 9, 7, BFTrp);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 11, 10, BFTrtp);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 15, 12, BFTras);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 20, 16, BFTrc);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 21, 20, BFTwr);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 23, 22, BFTrrd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 24, BFMemClkDis);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 0, BFNonSPD);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 3, 0, BFTrwtWB);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 7, 4, BFTrwtTO);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 9, 8, BFTwtr);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 11, 10, BFTwrrd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 13, 12, BFTwrwr);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 14, BFTrdrd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 17, 16, BFTref);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 22, 20, BFTrfc0);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 25, 23, BFTrfc1);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 28, 26, BFTrfc2);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 29, BFTrfc3);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 0, 0, BFInitDram);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 1, 1, BFExitSelfRef);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 5, 4, BFDramTerm);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 8, 8, BFParEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 10, 10, BFBurstLength32);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 11, 11, BFWidth128);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 15, 12, BFX4Dimm);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 16, 16, BFUnBuffDimm);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 17, 17, BFEnterSelfRef);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 19, 19, BFDimmEccEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 21, 21, BFFreqChgInProg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 23, 23, BFForceAutoPchg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 27, 27, BFDisDllShutdownSR);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 2, 0, BFMemClkFreq);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 3, 3, BFMemClkFreqVal);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 8, 8, BFDdr3Mode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 9, 9, BFLegacyBiosMode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 12, 12, BFRDqsEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 15, 15, BFPowerDownEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 16, 16, BFPowerDownMode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 17, 17, BFFourRankSoDimm);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 19, 19, BFDcqArbBypassEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 18, 18, BFFourRankRDimm);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 20, 20, BFSlowAccessMode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 22, 22, BFBankSwizzleMode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 27, 24, BFDcqBypassMax);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 28, BFFourActWindow);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 8, 8, BFODTSEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 14, 12, BFCmdThrottleMode);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 2, 2, BFDdr3FourSocketCh);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 5, 5, BFSubMemclkRegDly);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 6, 6, BFOdtSwizzle);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 7, 7, BFProgOdtEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 15, 8, BFCtrlWordCS);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 18, 16, BFDataTxFifoWrDly);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 0, 0, BFDctSelHiRngEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 1, 1, BFDctSelHi);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 2, 2, BFDctSelIntLvEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 3, 3, BFMemClrInit);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 4, 4, BFDctGangEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 5, 5, BFDctDatIntLv);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 7, 6, BFDctSelIntLvAddr);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 8, 8, BFDramEnabled);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 9, 9, BFMemClrBusy);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 10, 10, BFMemCleared);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 31, 11, BFDctSelBaseAddr);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 31, 10, BFDctSelBaseOffset);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 1, 0, BFDctWrLimit);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 6, 2, BFMctWrLimit);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 11, 7, BFMctPrefReqLimit);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 12, 12, BFPrefCpuDis);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 13, 13, BFPrefIoDis);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 28, 28, BFPrefDramTrainMode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 30, 30, BFFlushWr);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 29, 29, BFFlushWrOnStpGnt);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 1, 0, BFAdapPrefMissRatio);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 3, 2, BFAdapPrefPosStep);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 5, 4, BFAdapPrefNegStep);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 10, 8, BFCohPrefPrbLmt);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xB0), 31, 0, BFOnLineSpareControl);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 7, 5, BFDdrMaxRate);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 9, 8, BFAddrCmdDrvStren);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 17, 16, BFDataDrvStren);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31, 0, BFODCControl);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31, 0, BFAddrTmgControl);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 0, 0, BFWrtLvTrEn);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 1, 1, BFWrtLvTrMode);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 3, 3, BFPhyFenceTrEn);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 5, 4, BFTrDimmSel);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11, 8, BFWrLvOdt);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 13, 13, BFDqsRcvTrEn);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 30, 30, BFDisAutoComp);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x53, 8, 0, BFWrtLvErr);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 27, 25, BFD3Cmp2PCal);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 22, 20, BFD3Cmp2NCal);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 17, 15, BFD3Cmp1PCal);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 12, 10, BFD3Cmp1NCal);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 7, 5, BFD3Cmp0PCal);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 2, 0, BFD3Cmp0NCal);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 20, 16, BFPhyFence);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 13, 12, BFCKETri);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 11, 8, BFODTTri);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 7, 0, BFChipSelTri);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x602, 31, 0, BFUSPLLCtlAll);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x603, 31, 0, BFDSPLLCtlAll);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x606, 0, 0, BFUSNibbleAlignEn);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x690, 2, 2, BFChnLinitClkEn);
-
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x180, 31, 0, BFPhyRODTCSLow);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x181, 31, 0, BFPhyRODTCSHigh);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x182, 31, 0, BFPhyWODTCSLow);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x183, 31, 0, BFPhyWODTCSHigh);
-
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x06, 3, 0, BFTrdrdSD);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x16, 3, 0, BFTwrwrSD);
-
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 31, 30, BFTSLinkSelect);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 9, 9, BFTS2BitLockEn);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 8, 8, BFTS2En);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 4, 4, BFTS1En);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 1, 1, BFTS0LinkStarEn);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 0, 0, BFTS0En);
-
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800002, 15, 0, BFLinkTrainData);
-
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800010, 17, 17, BFRstRxFifoPtrs);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800010, 16, 16, BFRxFifoPtrInit);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800010, 1, 1, BFRstTxFifoPtrs);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800010, 0, 0, BFTxFifoPtrInit);
-
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800012, 31, 24, BFLpbkCount);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800012, 21, 20, BFLpbkMap);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800012, 16, 16, BFSendLpbkMaintCmd);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800012, 15, 0, BFLpbkData);
-
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800014, 20, 16, BFMbRdPtrEn);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800014, 9, 4, BFLnkLpBkLat);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800014, 1, 1, BFLpbkRndTripLatDone);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800014, 0, 0, BFLnkLatTrainEn);
-
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800020, 1, 1, BFDsPhyReset);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800020, 0, 0, BFLinkReset);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D040F30, _NOT_USED_, _NOT_USED_, BFErr263);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F0C, _NOT_USED_, _NOT_USED_, BFErr350);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F0013, _NOT_USED_, _NOT_USED_, BFEccDLLConf);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F0830, _NOT_USED_, _NOT_USED_, BFEccDLLPwrDnConf);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F11, _NOT_USED_, _NOT_USED_, BFPhy0x0D080F11);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F10, _NOT_USED_, _NOT_USED_, BFPhy0x0D080F10);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D088F30, _NOT_USED_, _NOT_USED_, BFPhy0x0D088F30);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D08C030, _NOT_USED_, _NOT_USED_, BFPhy0x0D08C030);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D082F30, _NOT_USED_, _NOT_USED_, BFPhy0x0D082F30);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2030, _NOT_USED_, _NOT_USED_, BFPhyClkConfig0);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2130, _NOT_USED_, _NOT_USED_, BFPhyClkConfig1);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2230, _NOT_USED_, _NOT_USED_, BFPhyClkConfig2);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2330, _NOT_USED_, _NOT_USED_, BFPhyClkConfig3);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D08E000, _NOT_USED_, _NOT_USED_, BFErr322I);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D02E001, _NOT_USED_, _NOT_USED_, BFErr322II);
-
- LINK_TSEFO (NBRegTable, BFTwrrd, BFTwrrdHi);
- LINK_TSEFO (NBRegTable, BFTwrwr, BFTwrwrHi);
- LINK_TSEFO (NBRegTable, BFTrdrd, BFTrdrdHi);
-
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mnParTrainDa.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mnParTrainDa.c
deleted file mode 100644
index 143baac..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mnParTrainDa.c
+++ /dev/null
@@ -1,226 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnParTrainDa.c
- *
- * Feature which performs Memory DQS training on each node with each node training
- * its own memory through code running on a core in the associated processor.
- * This way memory can be trained in parallel by more than one processor.
- *
- * This file contains the Deerhound specific parallel training function.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Feat/HCTRN)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mnda.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuServices.h"
-#include "GeneralServices.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuApicUtilities.h"
-#include "mfParallelTraining.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_DA_MNPARTRAINDA_FILECODE
-
-/*-----------------------------------------------------------------------------
-* EXPORTED FUNCTIONS
-*
-*-----------------------------------------------------------------------------
-*/
-
-BOOLEAN
-STATIC
-MemConstructRemoteNBBlockDA (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN DIE_STRUCT *MCTPtr,
- IN MEM_FEAT_BLOCK_NB *FeatPtr
-);
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This is the training function which set up the environment for remote
- * training on the ap and launches the remote routine.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - Launch training on AP successfully.
- * @return FALSE - Fail to launch training on AP.
- */
-BOOLEAN
-MemFParallelTrainingDA (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- AMD_CONFIG_PARAMS *StdHeader;
- DIE_STRUCT *MCTPtr;
- REMOTE_TRAINING_ENV *EnvPtr;
- AP_TASK TrainingTask;
- UINT8 Socket;
- UINT8 Module;
- UINT8 APCore;
- UINT8 p;
- UINT32 LowCore;
- UINT32 HighCore;
- UINT32 BspSocket;
- UINT32 BspModule;
- UINT32 BspCore;
- AGESA_STATUS Status;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
- UINT16 MctDataSize;
- StdHeader = &(NBPtr->MemPtr->StdHeader);
- MCTPtr = NBPtr->MCTPtr;
- Socket = MCTPtr->SocketId;
- Module = MCTPtr->DieId;
-
- //
- // Allocate buffer for REMOTE_TRAINING_ENV
- //
- MctDataSize = MAX_DCTS_PER_NODE_DA * (
- sizeof (DCT_STRUCT) + (
- MAX_CHANNELS_PER_DCT_DA * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))
- )
- );
- AllocHeapParams.RequestedBufferSize = MctDataSize + sizeof (REMOTE_TRAINING_ENV);
- AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, Socket, Module, 0);
- AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
- if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
- EnvPtr = (REMOTE_TRAINING_ENV *) AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += sizeof (REMOTE_TRAINING_ENV);
-
- //
- // Setup Remote training environment
- //
- LibAmdMemCopy (&(EnvPtr->StdHeader), StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);
- LibAmdMemCopy (&(EnvPtr->DieStruct), MCTPtr, sizeof (DIE_STRUCT), StdHeader);
- for (p = 0; p < MAX_PLATFORM_TYPES; p++) {
- EnvPtr->GetPlatformCfg[p] = NBPtr->MemPtr->GetPlatformCfg[p];
- }
- EnvPtr->ErrorHandling = NBPtr->MemPtr->ErrorHandling;
- EnvPtr->NBBlockCtor = MemConstructRemoteNBBlockDA;
- EnvPtr->FeatPtr = NBPtr->FeatPtr;
- EnvPtr->HoleBase = NBPtr->RefPtr->HoleBase;
- EnvPtr->BottomIo = NBPtr->RefPtr->BottomIo;
- EnvPtr->SysLimit = NBPtr->RefPtr->SysLimit;
- EnvPtr->TableBasedAlterations = NBPtr->RefPtr->TableBasedAlterations;
- EnvPtr->PlatformMemoryConfiguration = NBPtr->RefPtr->PlatformMemoryConfiguration;
-
- LibAmdMemCopy (AllocHeapParams.BufferPtr, MCTPtr->DctData, MctDataSize, StdHeader);
-
- //
- // Get Socket, Core of the BSP
- //
- IdentifyCore (StdHeader, &BspSocket, &BspModule, &BspCore, &Status);
- EnvPtr->BspSocket = ((UINT8)BspSocket & 0x000000FF);
- EnvPtr->BspCore = ((UINT8)BspCore & 0x000000FF);
-
- //
- // Set up the remote task structure
- //
- TrainingTask.DataTransfer.DataPtr = EnvPtr;
- TrainingTask.DataTransfer.DataSizeInDwords = (UINT16) ((AllocHeapParams.RequestedBufferSize + 3) / 4);
- TrainingTask.DataTransfer.DataTransferFlags = 0;
- TrainingTask.ExeFlags = 0;
- TrainingTask.FuncAddress.PfApTaskI = (PF_AP_TASK_I)MemFParallelTraining;
-
- //
- // Get Target AP Core
- //
- GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader);
- APCore = (UINT8) (LowCore & 0x000000FF);
-
- //
- // Launch Remote Training
- //
- ApUtilRunCodeOnSocketCore (Socket, APCore, &TrainingTask, StdHeader);
-
- HeapDeallocateBuffer (AllocHeapParams.BufferHandle, StdHeader);
- return TRUE;
- } else {
- PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV, NBPtr->Node, 0, 0, 0, StdHeader);
- SetMemError (AGESA_FATAL, MCTPtr);
- ASSERT(FALSE); // Could not allocated heap space for "REMOTE_TRAINING_ENV"
- return FALSE;
- }
-}
-
-BOOLEAN
-STATIC
-MemConstructRemoteNBBlockDA (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN DIE_STRUCT *MCTPtr,
- IN MEM_FEAT_BLOCK_NB *FeatPtr
- )
-{
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
-
- NBPtr->MCTPtr = MCTPtr;
- NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue;
-
- MemNInitNBDataDA (NBPtr);
-
- FeatPtr->InitCPG (NBPtr);
- NBPtr->FeatPtr = FeatPtr;
- FeatPtr->InitHwRxEn (NBPtr);
-
- MemNSwitchDCTNb (NBPtr, 0);
-
- //----------------------------------------------------------------------------
- // Get TSC rate of the this AP
- //----------------------------------------------------------------------------
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
- FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader);
-
- return TRUE;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mnS3da.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mnS3da.c
deleted file mode 100644
index 77d4428..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mnS3da.c
+++ /dev/null
@@ -1,748 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mns3da.c
- *
- * DA memory specific function to support S3 resume
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/DA)
- * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "S3.h"
-#include "mfs3.h"
-#include "mnda.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "mnS3da.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G3_DXE)
-RDATA_GROUP (G3_DXE)
-
-#define FILECODE PROC_MEM_NB_DA_MNS3DA_FILECODE
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-UINT16
-STATIC
-MemNS3GetRegLstPtrDA (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT DESCRIPTOR_GROUP *DescriptPtr
- );
-
-AGESA_STATUS
-STATIC
-MemNS3GetDeviceRegLstDA (
- IN UINT32 RegisterLstID,
- OUT VOID **RegisterHeader
- );
-
-VOID
-STATIC
-MemNS3SetSpecialPCIRegDA (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR Address,
- IN VOID *Value,
- IN OUT VOID *ConfigPtr
- );
-
-VOID
-STATIC
-MemNS3ExitSelfRefRegDA (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-PCI_SPECIAL_CASE PciSpecialCaseFuncDA[] = {
- {MemNS3GetCSRNb, MemNS3SetCSRNb},
- {MemNS3GetCSRNb, MemNS3SetSpecialPCIRegDA},
- {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb}
-};
-
-PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorDA[] = {
- {{0, 0, 0}, FUNC_2, 0x110, 0xFFFFFFFF},
- {{0, 0, 0}, FUNC_1, 0x40, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x48, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x50, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x58, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x60, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x68, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x70, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x78, 0xFFFF3F03},
- {{0, 1, 0}, FUNC_1, 0x140, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x148, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x150, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x158, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x160, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x168, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x170, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x178, 0x000000FF},
- {{0, 0, 0}, FUNC_1, 0x44, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x4C, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x54, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x5C, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x64, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x6C, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x74, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x7C, 0xFFFF07FF},
- {{0, 1, 0}, FUNC_1, 0x144, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x14C, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x154, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x15C, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x164, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x16C, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x174, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x17C, 0x000000FF},
- {{0, 0, 0}, FUNC_1, 0xF0, 0xFF00FF83},
- {{0, 0, 0}, FUNC_1, 0x120, 0x00FFFFFF},
- {{0, 0, 0}, FUNC_1, 0x124, 0x07FFFFFF},
- {{0, 0, 0}, FUNC_2, 0x10C, 0x07F3FBF9},
- {{0, 0, 0}, FUNC_2, 0x114, 0xFFFFFC00},
- {{0, 0, 0}, FUNC_2, 0x118, 0xF773FFFF},
- {{0, 0, 0}, FUNC_2, 0x11C, 0xFFFFFFFF},
- {{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F}
-};
-
-CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefDA = {
- 0,
- (sizeof (S3PciPreSelfRefDescriptorDA) / sizeof (PCI_REG_DESCRIPTOR)),
- S3PciPreSelfRefDescriptorDA,
- NULL
-};
-
-CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorDA[] = {
- // DCT 0
- {{0, 0, 0}, FUNC_2, 0x40, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x44, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x48, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x4C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x50, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x54, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x58, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x5C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x60, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x64, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x68, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x6C, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x78, 0xFFCDBF0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x7C, 0xFFF7FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 2, 0}, FUNC_2, 0x80, 0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x84, 0x07FFEFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x88, 0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x8C, 0xFFFF7FFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x90, 0x00FFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0xA8, 0x0007FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), 0x30333333, DCT0_MASK, ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0x3FFFFFFF, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), 0x001FBFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), 0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhyClkConfig0, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhyClkConfig1, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhyClkConfig2, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhyClkConfig3, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- //errata 322
- {{2, 2, 1}, DCT0, BFErr322I, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFErr322II, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- //errata 263
- {{2, 2, 1}, DCT0, BFErr263, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- // Dll regulator disable
- {{2, 2, 1}, DCT0, BFPhy0x0D040F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhy0x0D042F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhy0x0D048F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhy0x0D04DF3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-
- // DCT 1
- {{0, 0, 0}, FUNC_2, 0x140, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x144, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x148, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x14C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x150, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x154, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x158, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x15C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x160, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x164, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x168, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x16C, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x178, 0xFFCDBF0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x17C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 2, 0}, FUNC_2, 0x180, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x184, 0x07FFEFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x188, 0xFFFFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x18C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x190, 0x00FFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x1A8, 0x0007FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), 0x30333333, DCT1_MASK, ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x001FBFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyClkConfig0, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyClkConfig1, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyClkConfig2, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyClkConfig3, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- // errata 322
- {{2, 2, 1}, DCT1, BFErr322I, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFErr322II, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- // errata 263
- {{2, 2, 1}, DCT1, BFErr263, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-
- // Dll regulator disable
- {{2, 2, 1}, DCT1, BFPhy0x0D040F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhy0x0D042F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhy0x0D048F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhy0x0D04DF3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-
- // Restore F2x[1,0]94 right before exit self refresh
- {{0, 0, 0}, FUNC_2, 0x94, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x194, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK}
-};
-
-CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefDA = {
- 0,
- (sizeof (S3CPciPreSelfDescriptorDA) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
- S3CPciPreSelfDescriptorDA,
- PciSpecialCaseFuncDA
-};
-
-CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorDA[] = {
- // DCT0
- {{2, 2, 1}, DCT0, BFEccDLLPwrDnConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFEccDLLConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10), 0x01FF01FF, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11), 0x01FF01FF, DCT0_MASK, 0x01},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12), 0x000001FF, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13), 0x01FF01FF, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14), 0x01FF01FF, DCT0_MASK, 0x04},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15), 0x000001FF, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16), 0x01FF01FF, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17), 0x01FF01FF, DCT0_MASK, 0x10},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18), 0x000001FF, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19), 0x01FF01FF, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A), 0x01FF01FF, DCT0_MASK, 0x40},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B), 0x000001FF, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20), 0x01FF01FF, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21), 0x01FF01FF, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23), 0x01FF01FF, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24), 0x01FF01FF, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26), 0x01FF01FF, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27), 0x01FF01FF, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29), 0x01FF01FF, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A), 0x01FF01FF, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01), 0x7F7F7F7F, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02), 0x7F7F7F7F, DCT0_MASK, 0x01},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03), 0x0000007F, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0x7F7F7F7F, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0x7F7F7F7F, DCT0_MASK, 0x04},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x0000007F, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0x7F7F7F7F, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0x7F7F7F7F, DCT0_MASK, 0x10},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x0000007F, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0x7F7F7F7F, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0x7F7F7F7F, DCT0_MASK, 0x40},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x0000007F, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05), 0x3F3F3F3F, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06), 0x3F3F3F3F, DCT0_MASK, 0x01},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x07), 0x0000003F, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3F3F3F3F, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3F3F3F3F, DCT0_MASK, 0x04},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x107), 0x0000003F, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3F3F3F3F, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3F3F3F3F, DCT0_MASK, 0x10},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x207), 0x0000003F, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3F3F3F3F, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3F3F3F3F, DCT0_MASK, 0x40},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x307), 0x0000003F, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0xFFFFFFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D), 0x23772377, DCT0_MASK, ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30), 0x00FF00FF, DCT0_DDR3_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31), 0x00FF00FF, DCT0_DDR3_MASK, 0x01},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32), 0x000000FF, DCT0_DDR3_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33), 0x00FF00FF, DCT0_DDR3_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34), 0x00FF00FF, DCT0_DDR3_MASK, 0x04},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35), 0x000000FF, DCT0_DDR3_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36), 0x00FF00FF, DCT0_DDR3_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37), 0x00FF00FF, DCT0_DDR3_MASK, 0x10},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38), 0x000000FF, DCT0_DDR3_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39), 0x00FF00FF, DCT0_DDR3_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B), 0x000000FF, DCT0_DDR3_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40), 0x00FF00FF, DCT0_DDR3_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41), 0x00FF00FF, DCT0_DDR3_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43), 0x00FF00FF, DCT0_DDR3_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44), 0x00FF00FF, DCT0_DDR3_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46), 0x00FF00FF, DCT0_DDR3_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47), 0x00FF00FF, DCT0_DDR3_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49), 0x00FF00FF, DCT0_DDR3_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40},
- {{2, 2, 1}, DCT0, BFPhy0x0D0F0F13, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhy0x0D0F0830, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhy0x0D07812F, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhyDLLControl, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-
- // DCT1
- {{2, 2, 1}, DCT1, BFEccDLLPwrDnConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFEccDLLConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10), 0x01FF01FF, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11), 0x01FF01FF, DCT1_MASK, 0x02},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x12), 0x000001FF, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13), 0x01FF01FF, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14), 0x01FF01FF, DCT1_MASK, 0x08},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x15), 0x000001FF, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x16), 0x01FF01FF, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x17), 0x01FF01FF, DCT1_MASK, 0x20},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x18), 0x000001FF, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x19), 0x01FF01FF, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1A), 0x01FF01FF, DCT1_MASK, 0x80},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1B), 0x000001FF, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20), 0x01FF01FF, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21), 0x01FF01FF, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23), 0x01FF01FF, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24), 0x01FF01FF, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x26), 0x01FF01FF, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x27), 0x01FF01FF, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x29), 0x01FF01FF, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x2A), 0x01FF01FF, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01), 0x7F7F7F7F, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02), 0x7F7F7F7F, DCT1_MASK, 0x02},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x03), 0x0000007F, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101), 0x7F7F7F7F, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102), 0x7F7F7F7F, DCT1_MASK, 0x08},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x103), 0x0000007F, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x201), 0x7F7F7F7F, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x202), 0x7F7F7F7F, DCT1_MASK, 0x20},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x203), 0x0000007F, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x301), 0x7F7F7F7F, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x302), 0x7F7F7F7F, DCT1_MASK, 0x80},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x303), 0x0000007F, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05), 0x3F3F3F3F, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06), 0x3F3F3F3F, DCT1_MASK, 0x02},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x07), 0x0000003F, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105), 0x3F3F3F3F, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106), 0x3F3F3F3F, DCT1_MASK, 0x08},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x107), 0x0000003F, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x205), 0x3F3F3F3F, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x206), 0x3F3F3F3F, DCT1_MASK, 0x20},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x207), 0x0000003F, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x305), 0x3F3F3F3F, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x306), 0x3F3F3F3F, DCT1_MASK, 0x80},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x307), 0x0000003F, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D), 0x23772377, DCT1_MASK, ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30), 0x00FF00FF, DCT1_DDR3_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31), 0x00FF00FF, DCT1_DDR3_MASK, 0x02},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x32), 0x000000FF, DCT1_DDR3_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33), 0x00FF00FF, DCT1_DDR3_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34), 0x00FF00FF, DCT1_DDR3_MASK, 0x08},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x35), 0x000000FF, DCT1_DDR3_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x36), 0x00FF00FF, DCT1_DDR3_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x37), 0x00FF00FF, DCT1_DDR3_MASK, 0x20},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x38), 0x000000FF, DCT1_DDR3_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x39), 0x00FF00FF, DCT1_DDR3_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3B), 0x000000FF, DCT1_DDR3_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40), 0x00FF00FF, DCT1_DDR3_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41), 0x00FF00FF, DCT1_DDR3_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43), 0x00FF00FF, DCT1_DDR3_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44), 0x00FF00FF, DCT1_DDR3_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x46), 0x00FF00FF, DCT1_DDR3_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x47), 0x00FF00FF, DCT1_DDR3_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x49), 0x00FF00FF, DCT1_DDR3_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x4A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80},
- {{2, 2, 1}, DCT1, BFPhy0x0D0F0F13, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhy0x0D0F0830, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhy0x0D07812F, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyDLLControl, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-
- // DllShutDown
- {{2, 2, 1}, DCT0, BFPhyPLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhyDLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 1, 1}, DCT0, BFDisDllShutdownSR, 0x00000001, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyPLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyDLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 1, 1}, DCT1, BFDisDllShutdownSR, 0x00000001, DCT1_MASK, ANY_DIMM_MASK},
-
- // Restore scrubber related registers after restoring training related registers
- {{0, 0, 0}, FUNC_3, 0x44, 0xFFFFFFFE, ANY_DIMM_MASK, ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_3, 0x58, 0x1F1F1F1F, ANY_DIMM_MASK, ANY_DIMM_MASK},
- {{2, 1, 1}, DCT0, BFScrubReDirEn, 0x00000001, ANY_DIMM_MASK, ANY_DIMM_MASK},
-};
-
-CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefDA = {
- 0,
- (sizeof (S3CPciPostSelfDescriptorDA) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
- S3CPciPostSelfDescriptorDA,
- PciSpecialCaseFuncDA
-};
-
-MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorDA[] = {
- {{0, 0, 0}, 0xC0010010, 0x00000000007F07FF},
- {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000},
- {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000},
- {{0, 0, 0}, 0xC001001F, 0xC047F87FFF527FFF}
-};
-
-CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefDA = {
- 0,
- (sizeof (S3MSRPreSelfRefDescriptorDA) / sizeof (MSR_REG_DESCRIPTOR)),
- S3MSRPreSelfRefDescriptorDA,
- NULL
-};
-
-VOID *MemS3RegListDA[] = {
- (VOID *)&S3PciPreSelfRefDA,
- NULL,
- (VOID *)&S3CPciPreSelfRefDA,
- (VOID *)&S3CPciPostSelfRefDA,
- (VOID *)&S3MSRPreSelfRefDA,
- NULL,
- NULL,
- NULL
-};
-
-CONST UINT16 ROMDATA SpecialCasePCIRegDA[] = {
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04)
-};
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the northbridge block for S3 resume
- *
- * @param[in,out] *S3NBPtr - Pointer to MEM_NB_BLOCK.
- * @param[in,out] *MemPtr - Pointer to MEM_DATA_STRUCT.
- * @param[in] NodeID - Node ID of the target node.
- *
- * @return BOOLEAN
- * TRUE - This is the correct constructor for the targeted node.
- * FALSE - This isn't the correct constructor for the targeted node.
- */
-BOOLEAN
-MemS3ResumeConstructNBBlockDA (
- IN OUT VOID *S3NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- )
-{
- INT32 i;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr;
-
- //
- // Determine if this is the expected NB Type
- //
- GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
- if (!MemNIsIdSupportedDA (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
- return FALSE;
- }
-
- NBPtr->MemPtr = MemPtr;
- NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
- NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
- InitNBRegTableDA (NBPtr, NBPtr->NBRegTable);
- NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
- NBPtr->Dct = 0;
- NBPtr->Channel = 0;
- NBPtr->Ganged = FALSE;
- NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA;
- NBPtr->DctCount = MAX_DCTS_PER_NODE_DA;
-
- for (i = 0; i < EnumSize; i++) {
- NBPtr->IsSupported[i] = FALSE;
- }
-
- for (i = 0; i < NumberOfHooks; i++) {
- NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) memDefTrue;
- }
-
- LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader);
-
- NBPtr->IsSupported[CheckDllSpeedUp] = TRUE;
- NBPtr->SwitchDCT = MemNSwitchDCTNb;
- NBPtr->SwitchChannel = MemNSwitchChannelNb;
- NBPtr->GetBitField = MemNGetBitFieldNb;
- NBPtr->SetBitField = MemNSetBitFieldNb;
- NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA;
- NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedDA;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = MemNS3ExitSelfRefRegDA;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskNb;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK *, DESCRIPTOR_GROUP *)) memDefRet;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeNb;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = MemNS3RestoreScrubNb;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrDA;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstDA;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = (sizeof (SpecialCasePCIRegDA) / sizeof (UINT16)) * sizeof (UINT32);
-
- MemNSwitchDCTNb (NBPtr, 0);
-
- return TRUE;
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------*/
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function returns the register list for each device for DA
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP
- * @return UINT16 - size of the device descriptor on the target node.
- */
-UINT16
-STATIC
-MemNS3GetRegLstPtrDA (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT DESCRIPTOR_GROUP *DescriptPtr
- )
-{
- UINT8 i;
- UINT16 Size;
- Size = 0;
- for (i = PRESELFREF; i <= POSTSELFREF; i ++) {
- DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i);
- DescriptPtr->PCIDevice[i].Node = NBPtr->Node;
- DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF;
- if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListDA[PCI_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) {
- DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_DA + i;
- Size += sizeof (PCI_DEVICE_DESCRIPTOR);
- }
- DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i);
- DescriptPtr->CPCIDevice[i].Node = NBPtr->Node;
- DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF;
- if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListDA[CPCI_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) {
- DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_DA + i;
- Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR);
- }
- DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i);
- DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF;
- if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListDA[MSR_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) {
- DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_DA + i;
- Size += sizeof (MSR_DEVICE_DESCRIPTOR);
- }
- DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i);
- DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF;
- if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListDA[CMSR_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) {
- DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_DA + i;
- Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR);
- }
- }
- return Size;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function return the register list according to the register ID.
- *
- * @param[in] RegisterLstID - value of the Register list ID.
- * @param[out] **RegisterHeader - pointer to the address of the register list.
- * @return none
- */
-AGESA_STATUS
-STATIC
-MemNS3GetDeviceRegLstDA (
- IN UINT32 RegisterLstID,
- OUT VOID **RegisterHeader
- )
-{
- if (RegisterLstID >= (sizeof (MemS3RegListDA) / sizeof (VOID *))) {
- ASSERT(FALSE); // RegisterListID exceeded size of Register list
- return AGESA_FATAL;
- }
- if (MemS3RegListDA[RegisterLstID] != NULL) {
- *RegisterHeader = MemS3RegListDA[RegisterLstID];
- return AGESA_SUCCESS;
- }
- ASSERT(FALSE); // Device register list error
- return AGESA_FATAL;
-}
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function stores special case register on the heap.
- *
- * @param[in] AccessWidth - Access width of the register
- * @param[in] Address - address of the CSR register in PCI_ADDR format.
- * @param[in] *Value - Pointer to the value be read.
- * @param[in, out] *ConfigPtr - Pointer to Config handle.
- * @return none
- */
-VOID
-STATIC
-MemNS3SetSpecialPCIRegDA (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR Address,
- IN VOID *Value,
- IN OUT VOID *ConfigPtr
- )
-{
- LOCATE_HEAP_PTR LocateBufferPtr;
- UINT8 i;
- UINT8 NodeID;
- UINT8 Offset;
- S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader;
-
- Offset = 0;
- LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
- if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) {
- SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr;
- // Get the node ID of the target die.
- NodeID = (UINT8) (Address.Address.Device - 24);
- for (i = 0; i < MAX_NODES_SUPPORTED_DA; i ++) {
- if (SpecialHeapHeader[i].Node == NodeID) {
- // Get the offset in the heap for the target die.
- Offset = SpecialHeapHeader[i].Offset;
- break;
- }
- }
- ASSERT (i < MAX_NODES_SUPPORTED_DA);
- // Save the value in the heap at appropriate offset based on the index
- // of the target register in the special case array.
- if (Offset != 0) {
- for (i = 0; i < (sizeof (SpecialCasePCIRegDA) / sizeof (UINT16)); i ++) {
- if (SpecialCasePCIRegDA[i] == Address.Address.Register) {
- *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)) = *(UINT32 *) Value;
- }
- }
- }
- }
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function stores special case register on the heap.
- *
- * @param[in,out] *NBPtr - Pointer to the northbridge block.
- * @param[in,out] *StdHeader - Config handle for library and services.
- * @return none
- */
-VOID
-STATIC
-MemNS3ExitSelfRefRegDA (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- LOCATE_HEAP_PTR LocateBufferPtr;
- UINT8 i;
- PCI_ADDR PciAddr;
- UINT32 Value;
- UINT8 NodeID;
- UINT8 Offset;
- S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader;
-
- Offset = 0;
- PciAddr.Address.Device = NBPtr->PciAddr.Address.Device;
- PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus;
- PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment;
- PciAddr.Address.Function = 2;
- LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
- if (HeapLocateBuffer (&LocateBufferPtr, StdHeader) == AGESA_SUCCESS) {
- SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr;
- // Get the node ID of the target die.
- NodeID = (UINT8) (PciAddr.Address.Device - 24);
- for (i = 0; i < MAX_NODES_SUPPORTED_DA; i ++) {
- if (SpecialHeapHeader[i].Node == NodeID) {
- // Get the offset in the heap for the target die.
- Offset = SpecialHeapHeader[i].Offset;
- break;
- }
- }
- ASSERT (i < MAX_NODES_SUPPORTED_DA);
- // Restore the value one by one in the sequence of the special case register array.
- if (Offset != 0) {
- for (i = 0; i < (sizeof (SpecialCasePCIRegDA) / sizeof (UINT16)); i ++) {
- PciAddr.Address.Register = SpecialCasePCIRegDA[i];
- Value = *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2));
- MemNS3SetCSRNb (AccessS3SaveWidth32, PciAddr, &Value, StdHeader);
- }
- }
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mnS3da.h b/src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mnS3da.h
deleted file mode 100644
index 59dbbda..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mnS3da.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnS3da.h
- *
- * S3 resume memory related function for DA.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/DA)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MNS3DA_H_
-#define _MNS3DA_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-/// ID for register list of DA
-typedef enum {
- PCI_LST_ESR_DA, ///< Assign 0x0000 for PCI register list for pre exit self refresh.
- PCI_LST_DA, ///< Assign 0x0001 for PCI register list for post exist self refresh.
- CPCI_LST_ESR_DA, ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh.
- CPCI_LST_DA, ///< Assign 0x0003 for conditional PCI register list for post exit self refresh.
- MSR_LST_ESR_DA, ///< Assign 0x0004 for MSR register list for pre exit self refresh.
- MSR_LST_DA, ///< Assign 0x0005 for MSR register list for post exit self refresh.
- CMSR_LST_ESR_DA, ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh.
- CMSR_LST_DA, ///< Assign 0x0007 for conditional MSR register list for post exit self refresh.
-} RegisterListIDDA;
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-#endif //_MNS3DA_H_
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mnda.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mnda.c
deleted file mode 100644
index b7fb2f3..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mnda.c
+++ /dev/null
@@ -1,490 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnda.c
- *
- * Common Northbridge functions for DA
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/DA)
- * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mnda.h"
-#include "mu.h"
-#include "S3.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "heapManager.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-#define FILECODE PROC_MEM_NB_DA_MNDA_FILECODE
-
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-#define SPLIT_CHANNEL (UINT32) 0x20000000
-#define CHANNEL_SELECT (UINT32) 0x10000000
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the northbridge block
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
- * @param[in] *FeatPtr - Pointer to the MEM_FEAT_BLOCK_NB
- * @param[in] *SharedPtr - Pointer to the MEM_SHARED_DATA
- * @param[in] NodeID - UINT8 indicating node ID of the NB object.
- *
- * @return Boolean indicating that this is the correct memory
- * controller type for the node number that was passed in.
- */
-
-BOOLEAN
-MemConstructNBBlockDA (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN MEM_FEAT_BLOCK_NB *FeatPtr,
- IN MEM_SHARED_DATA *SharedPtr,
- IN UINT8 NodeID
- )
-{
- UINT8 Dct;
- UINT8 Channel;
- UINT8 SpdSocketIndex;
- UINT8 SpdChannelIndex;
- DIE_STRUCT *MCTPtr;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
- //
- // Determine if this is the expected NB Type
- //
- GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
- if (!MemNIsIdSupportedDA (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
- return FALSE;
- }
-
- NBPtr->MemPtr = MemPtr;
- NBPtr->RefPtr = MemPtr->ParameterListPtr;
- NBPtr->SharedPtr = SharedPtr;
-
- MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
- NBPtr->MCTPtr = MCTPtr;
- NBPtr->MCTPtr->NodeId = NodeID;
- NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue;
- NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
-
- //
- // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
- //
- AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_DA * (
- sizeof (DCT_STRUCT) + (
- MAX_CHANNELS_PER_DCT_DA * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))
- )
- );
- AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0);
- AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
- if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) {
- PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader);
- SetMemError (AGESA_FATAL, MCTPtr);
- return FALSE;
- }
-
- MCTPtr->DctCount = MAX_DCTS_PER_NODE_DA;
- MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_DA * sizeof (DCT_STRUCT);
- for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
- MCTPtr->DctData[Dct].Dct = Dct;
- MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_DA;
- MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_DA * sizeof (CH_DEF_STRUCT);
- }
- NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr;
-
- //
- // Initialize Socket List
- //
- for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
- MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr[Dct] = &(MCTPtr->DctData[Dct].ChData[0]);
- MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr[Dct] = &(MCTPtr->DctData[Dct].Timings);
- MCTPtr->DctData[Dct].ChData[0].ChannelID = Dct;
- }
-
- MemNInitNBDataDA (NBPtr);
-
- FeatPtr->InitCPG (NBPtr);
- NBPtr->FeatPtr = FeatPtr;
- FeatPtr->InitHwRxEn (NBPtr);
- //
- // Calculate SPD Offsets per channel and assign pointers to the data. At this point, we calculate the Node-Dct-Channel
- // centric offsets and store the pointers to the first DIMM of each channel in the Channel Definition struct for that
- // channel. This pointer is then used later to calculate the offsets to be used for each logical dimm once the
- // dimm types(QR or not) are known. This is done in the Technology block constructor.
- //
- // Calculate the SpdSocketIndex separately from the SpdChannelIndex.
- // This will facilitate modifications due to some processors that might
- // map the DCT-CHANNEL differently.
- //
- SpdSocketIndex = GetSpdSocketIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, &MemPtr->StdHeader);
- //
- // Traverse the Dct/Channel structures
- //
- for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
- for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_DA; Channel++) {
- //
- // Calculate the number of Dimms on this channel using the
- // die/dct/channel to Socket/channel conversion.
- //
- SpdChannelIndex = GetSpdChannelIndex (NBPtr->RefPtr->PlatformMemoryConfiguration,
- NBPtr->MCTPtr->SocketId,
- MemNGetSocketRelativeChannelNb (NBPtr, Dct, Channel),
- &MemPtr->StdHeader);
- NBPtr->MCTPtr->DctData[Dct].ChData[Channel].SpdPtr = &(MemPtr->SpdDataStructure[SpdSocketIndex + SpdChannelIndex]);
- }
- }
-
- MemNSwitchDCTNb (NBPtr, 0);
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initializes member functions and variables of NB block.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNInitNBDataDA (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- INT32 i;
-
- NBPtr->DctCachePtr = NBPtr->DctCache;
- NBPtr->PsPtr = NBPtr->PSBlock;
-
- InitNBRegTableDA (NBPtr, NBPtr->NBRegTable);
- NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
- NBPtr->Dct = 0;
- NBPtr->Channel = 0;
- NBPtr->DctCount = MAX_DCTS_PER_NODE_DA;
- NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_DA;
- NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA;
- NBPtr->Ganged = FALSE;
- NBPtr->PosTrnPattern = POS_PATTERN_72B;
- NBPtr->MemCleared = FALSE;
- NBPtr->StartupSpeed = DDR800_FREQUENCY;
- NBPtr->RcvrEnDlyLimit = 0xFF;
- NBPtr->DefDctSelIntLvAddr = 3;
-
- for (i = 0; i < EnumSize; i++) {
- NBPtr->IsSupported[i] = FALSE;
- }
-
- LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader);
-
- NBPtr->SetMaxLatency = MemNSetMaxLatencyNb;
- NBPtr->getMaxLatParams = MemNGetMaxLatParamsNb;
- NBPtr->GetSysAddr = MemNGetMCTSysAddrNb;
- NBPtr->InitializeMCT = MemNInitializeMctDA;
- NBPtr->FinalizeMCT = MemNFinalizeMctDA;
- NBPtr->SendMrsCmd = MemNSendMrsCmdDA;
- NBPtr->sendZQCmd = MemNSendZQCmdNb;
- NBPtr->WritePattern = MemNWritePatternDA;
- NBPtr->ReadPattern = MemNReadPatternDA;
- NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet;
- NBPtr->CompareTestPattern = MemNCompareTestPatternNb;
- NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb;
- NBPtr->StitchMemory = MemNStitchMemoryNb;
- NBPtr->AutoConfig = memNAutoConfigDA;
- NBPtr->PlatformSpec = MemNPlatformSpecNb;
- NBPtr->InitMCT = MemNInitMCTNb;
- NBPtr->DisableDCT = MemNDisableDCTNb;
- NBPtr->StartupDCT = MemNStartupDCTNb;
- NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb;
- NBPtr->ChangeFrequency = MemNChangeFrequencyNb;
- NBPtr->RampUpFrequency = MemNRampUpFrequencyNb;
- NBPtr->ChangeNbFrequency = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefFalse;
- NBPtr->ProgramCycTimings = MemNProgramCycTimingsNb;
- NBPtr->SyncDctsReady = MemNSyncDctsReadyNb;
- NBPtr->HtMemMapInit = MemNHtMemMapInitNb;
- NBPtr->SyncAddrMapToAllNodes = MemNSyncAddrMapToAllNodesNb;
- NBPtr->CpuMemTyping = MemNCPUMemTypingNb;
- NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingNb;
- NBPtr->AfterDqsTraining = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
- NBPtr->OtherTiming = MemNOtherTimingDA;
- NBPtr->UMAMemTyping = MemNUMAMemTypingNb;
- NBPtr->TechBlockSwitch = MemNTechBlockSwitchNb;
- NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA;
- NBPtr->SetEccSymbolSize = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
- NBPtr->TrainingFlow = MemNTrainingFlowNb;
- NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb;
- MemNInitNBDataNb (NBPtr);
- NBPtr->PollBitField = MemNPollBitFieldNb;
- NBPtr->BrdcstCheck = MemNBrdcstCheckNb;
- NBPtr->BrdcstSet = MemNBrdcstSetNb;
- NBPtr->GetTrainDly = MemNGetTrainDlyNb;
- NBPtr->SetTrainDly = MemNSetTrainDlyNb;
- NBPtr->PhyFenceTraining = MemNPhyFenceTrainingNb;
- NBPtr->GetSysAddr = MemNGetMCTSysAddrNb;
- NBPtr->RankEnabled = MemNRankEnabledNb;
- NBPtr->MemPPhyFenceTrainingNb = MemNTrainPhyFenceNb;
- NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitDA;
- NBPtr->MemNBeforePlatformSpecNb = MemNBeforePlatformSpecDA;
- NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyNb;
- NBPtr->MemPNodeMemBoundaryNb = MemPNodeMemBoundaryDA;
- NBPtr->MemNInitPhyComp = MemNInitPhyCompNb;
- NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb;
- NBPtr->MemNBeforeDramInitNb = MemNBeforeDramInitDA;
- NBPtr->MemNPFenceAdjustNb = (VOID (*) (MEM_NB_BLOCK *, UINT16 *)) memDefRet;
- NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsNb;
- NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb;
- NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb;
- NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb;
- NBPtr->CSPerChannel = MemNCSPerChannelNb;
- NBPtr->CSPerDelay = MemNCSPerDelayNb;
- NBPtr->FlushPattern = MemNFlushPatternNb;
- NBPtr->MemNCapSpeedBatteryLife = MemNCapSpeedBatteryLifeDA;
- NBPtr->GetUmaSize = MemNGetUmaSizeNb;
- NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdNb;
- NBPtr->EnableSwapIntlvRgn = MemNEnableSwapIntlvRgnNb;
- NBPtr->WaitXMemClks = MemNWaitXMemClksNb;
- NBPtr->MemNGetDramTerm = MemNGetDramTermNb;
- NBPtr->MemNGetDynDramTerm = MemNGetDynDramTermNb;
- NBPtr->MemNGetMR0CL = MemNGetMR0CLNb;
- NBPtr->MemNGetMR0WR = MemNGetMR0WRNb;
- NBPtr->MemNGetMR2CWL = MemNGetMR2CWLNb;
- NBPtr->AllocateC6Storage = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
-
- NBPtr->IsSupported[SetSpareEn] = TRUE;
- NBPtr->IsSupported[CheckSpareEn] = TRUE;
- NBPtr->IsSupported[SetDllShutDown] = TRUE;
- NBPtr->IsSupported[DimmBasedOnSpeed] = TRUE;
- NBPtr->IsSupported[CheckMaxDramRate] = TRUE;
- NBPtr->IsSupported[Check1GAlign] = TRUE;
- NBPtr->IsSupported[CheckMaxRdDqsDlyPtr] = TRUE;
- NBPtr->IsSupported[CheckPhyFenceTraining] = TRUE;
- NBPtr->IsSupported[CheckGetMCTSysAddr] = TRUE;
- NBPtr->IsSupported[CheckFindPSDct] = TRUE;
- NBPtr->IsSupported[CheckDllStdBy] = TRUE;
- NBPtr->IsSupported[CheckSlewWithMarginImprv] = TRUE;
- NBPtr->IsSupported[CheckDllSpeedUp] = TRUE;
- NBPtr->IsSupported[CheckDllRegDis] = TRUE;
- NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the default values in the MEM_DATA_STRUCT
- *
- * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
- *
- */
-VOID
-MemNInitDefaultsDA (
- IN OUT MEM_DATA_STRUCT *MemPtr
- )
-{
- UINT8 Socket;
- UINT8 Channel;
- MEM_PARAMETER_STRUCT *RefPtr;
- ASSERT (MemPtr != NULL);
- RefPtr = MemPtr->ParameterListPtr;
-
- // Memory Map/Mgt.
- // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB
- RefPtr->BottomIo = 0xE0;
- RefPtr->UmaMode = UserOptions.CfgUmaMode;
- RefPtr->UmaSize = UserOptions.CfgUmaSize;
- RefPtr->MemHoleRemapping = TRUE;
-
- // Dram Timing
- RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect;
- RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect;
- for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) {
- for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) {
- MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL;
- MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL;
- }
- }
-
- // Memory Clear
- RefPtr->EnableMemClr = TRUE;
-
- // TableBasedAlterations
- RefPtr->TableBasedAlterations = NULL;
-
- // Platform config table
- RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration;
-
- // Memory Restore
- RefPtr->MemRestoreCtl = FALSE;
- RefPtr->SaveMemContextCtl = FALSE;
- AmdS3ParamsInitializer (&RefPtr->MemContext);
-
- // Dram Configuration
- RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving;
- RefPtr->EnableNodeIntlv = UserOptions.CfgMemoryEnableNodeInterleaving;
- RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving;
- RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle;
- RefPtr->EnableParity = UserOptions.CfgMemoryParityEnable;
- RefPtr->EnableOnLineSpareCtl = UserOptions.CfgOnlineSpare;
-
- // Dram Power
- RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown;
-
- // ECC
- RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- *
- * This function writes training pattern
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Pattern[] - Pattern to write
- * @param[in] Address - System Address [47:16]
- * @param[in] ClCount - Number of cache lines
- *
- */
-
-VOID
-MemNWritePatternDA (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 Address,
- IN UINT8 Pattern[],
- IN UINT16 ClCount
- )
-{
- Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
- MemUWriteCachelines (Address, Pattern, ClCount);
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- *
- * This function reads training pattern
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Buffer[] - Buffer to fill
- * @param[in] Address - System Address [47:16]
- * @param[in] ClCount - Number of cache lines
- *
- */
-
-VOID
-MemNReadPatternDA (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Buffer[],
- IN UINT32 Address,
- IN UINT16 ClCount
- )
-{
- Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
- MemUReadCachelines (Buffer, Address, ClCount);
-}
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initiates DQS training for Server NB
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-BOOLEAN
-memNEnableTrainSequenceDA (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- BOOLEAN Retval;
- Retval = TRUE;
- if (!MemNIsIdSupportedDA (NBPtr, &(NBPtr->MemPtr->DiesPerSystem[NBPtr->MCTPtr->NodeId].LogicalCpuid))) {
- Retval = FALSE;
- }
- return Retval;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mnda.h b/src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mnda.h
deleted file mode 100644
index fb33f39..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mnda.h
+++ /dev/null
@@ -1,210 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnda.h
- *
- * Northbridge DA
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem)
- * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MNDA_H_
-#define _MNDA_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-#define MAX_CHANNELS_PER_SOCKET_DA 2
-#define MAX_DCTS_PER_NODE_DA 2
-#define MAX_CHANNELS_PER_DCT_DA 1
-#define MAX_NODES_SUPPORTED_DA 8
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-MemConstructNBBlockDA (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN MEM_FEAT_BLOCK_NB *FeatPtr,
- IN MEM_SHARED_DATA *SharedPtr,
- IN UINT8 NodeID
- );
-
-VOID
-MemNInitNBDataDA (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNInitDefaultsDA (
- IN OUT MEM_DATA_STRUCT *MemPtr
- );
-
-BOOLEAN
-MemNInitializeMctDA (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNFinalizeMctDA (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNSendMrsCmdDA (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-memNAutoConfigDA (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNOtherTimingDA (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNWritePatternDA (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 Address,
- IN UINT8 Pattern[],
- IN UINT16 ClCount
- );
-
-VOID
-MemNReadPatternDA (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Buffer[],
- IN UINT32 Address,
- IN UINT16 ClCount
- );
-
-VOID
-MemPNodeMemBoundaryDA (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT UINT32 *NodeSysLimit
- );
-
-VOID
-InitNBRegTableDA (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT TSEFO NBRegTable[]
- );
-
-VOID
-MemNBeforeDramInitDA (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNBeforePlatformSpecDA (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNPlatformSpecificFormFactorInitDA (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNIsIdSupportedDA (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN CPU_LOGICAL_ID *LogicalIdPtr
- );
-
-BOOLEAN
-MemNChangeAvgValue3DA (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNChangeAvgValue8DA (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNEnDLLShutDownDA (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-UINT32
-MemNCmnGetSetFieldDA (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN BIT_FIELD_NAME FieldName,
- IN UINT32 Field
- );
-
-VOID
-MemNCapSpeedBatteryLifeDA (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-memNEnableTrainSequenceDA (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNPlatformSpecificFormFactorInitNi (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-#endif /* _MNDA_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mndctda.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mndctda.c
deleted file mode 100644
index d1e241c..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mndctda.c
+++ /dev/null
@@ -1,469 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mndctda.c
- *
- * Northbridge DA DCT supporting functions
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/DA)
- * @e \$Revision: 36619 $ @e \$Date: 2010-08-23 12:46:02 +0800 (Mon, 23 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB
-#include "mnda.h"
-#include "merrhdl.h"
-#include "cpuRegisters.h"
-#include "Filecode.h"
-#include "GeneralServices.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuRegisters.h"
-#include "mport.h"
-#include "F10PackageType.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_DA_MNDCTDA_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define UNUSED_CLK 4
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This is a general purpose function that executes before DRAM init
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNBeforeDramInitDA (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 Dct;
-
- //Setting the reset value of Phy DLL standby and shutdown registers.
- for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
- MemNSwitchDCTNb (NBPtr, Dct);
- if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
- //Set PllLockTime and DllLockTime to default.
- MemNSetBitFieldNb (NBPtr, BFPhyPLLLockTime, 0x000007D0);
- MemNSetBitFieldNb (NBPtr, BFPhyDLLLockTime, 0x00000190);
- MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 1);
-
- //Clear PHY PLL Control Register before doing fence training and reset DLL
- MemNSetBitFieldNb (NBPtr, BFPhy0x0D080F0C, 0x00002000);
- MemNSetBitFieldNb (NBPtr, BFPhyDLLControl, 0);
- MemNSetBitFieldNb (NBPtr, BFPhy0x0D080F0C, 0);
- }
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function programs the memory controller with configuration parameters
- *
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - An Error value lower than AGESA_FATAL may have occurred
- * @return FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred
- * @return NBPtr->MCTPtr->ErrCode - Contains detailed AGESA_STATUS value
- */
-
-BOOLEAN
-memNAutoConfigDA (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- DIE_STRUCT *MCTPtr;
- DCT_STRUCT *DCTPtr;
- MEM_PARAMETER_STRUCT *RefPtr;
-
- RefPtr = NBPtr->RefPtr;
- MCTPtr = NBPtr->MCTPtr;
- DCTPtr = NBPtr->DCTPtr;
- //======================================================================
- // Build Dram Control Register Value (F2x78)
- //======================================================================
- //
-
- MemNSetBitFieldNb (NBPtr, BFEarlyArbEn, 1);
-
- //======================================================================
- // Build Dram Config Lo Register Value
- //======================================================================
- //
-
- if (MCTPtr->Status[SbParDimms]) {
- //
- // SbParDimms should be set for all DDR3 RDIMMS
- // Cannot turn off ParEn for DDR3
- //
- //@attention - add debug option for parity control
- MemNSetBitFieldNb (NBPtr, BFParEn, 1);
- }
-
-
- if (MCTPtr->GangedMode) {
- MemNSetBitFieldNb (NBPtr, BFWidth128, 1);
- }
-
- MemNSetBitFieldNb (NBPtr, BFX4Dimm, DCTPtr->Timings.Dimmx4Present & 0xF);
-
- if (!MCTPtr->Status[SbRegistered]) {
- MemNSetBitFieldNb (NBPtr, BFUnBuffDimm, 1);
- }
-
- if (MCTPtr->Status[SbEccDimms]) {
- MemNSetBitFieldNb (NBPtr, BFDimmEccEn, 1);
- }
-
- //======================================================================
- // Build Dram Config Hi Register Value
- //======================================================================
- //
-
- MemNSetBitFieldNb (NBPtr, BFMemClkFreq, MemNGetMemClkFreqIdNb (NBPtr, DCTPtr->Timings.Speed));
-
- if (MCTPtr->Status[SbRegistered]) {
- if (DCTPtr->Timings.Dimmx4Present && DCTPtr->Timings.Dimmx8Present) {
- MemNSetBitFieldNb (NBPtr, BFRDqsEn, 1);
- }
- }
-
- if (RefPtr->EnableBankSwizzle) {
- MemNSetBitFieldNb (NBPtr, BFBankSwizzleMode, 1);
- }
-
- if (DCTPtr->Timings.DimmQrPresent) {
- if (UserOptions.CfgMemoryQuadrankType == QUADRANK_UNBUFFERED) {
- MemNSetBitFieldNb (NBPtr, BFFourRankSoDimm, 1);
- } else if (UserOptions.CfgMemoryQuadrankType == QUADRANK_REGISTERED) {
- MemNSetBitFieldNb (NBPtr, BFFourRankRDimm, 1);
- }
- }
-
- MemNSetBitFieldNb (NBPtr, BFDcqBypassMax, 0xF);
-
- MemNSetBitFieldNb (NBPtr, BFDcqArbBypassEn, 1);
-
- //======================================================================
- // Build Dram Config Misc Register Value
- //======================================================================
- //
- MemNSetBitFieldNb (NBPtr, BFOdtSwizzle, 1);
- // For DDR3 Registered Dimms
- if (MCTPtr->Status[SbRegistered]) {
- if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode)!= 0) {
- MemNSetBitFieldNb (NBPtr, BFSubMemclkRegDly, 1);
- }
- }
- return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function sends an MRS command
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNSendMrsCmdDA (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MemNSwapBitsNb (NBPtr);
-
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tCS%d MR%d %04x\n",
- (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 20) & 0xF,
- (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 16) & 0xF,
- (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) & 0xFFFF));
-
- // 1.Set SendMrsCmd=1
- MemNSetBitFieldNb (NBPtr, BFSendMrsCmd, 1);
-
- // 2.Wait for SendMrsCmd=0
- MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * Workaround for erratum 322 and 263
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-VOID
-MemNBeforePlatformSpecDA (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- // Errata 263
- if ((NBPtr->DCTPtr->Timings.Speed == DDR533_FREQUENCY) || (NBPtr->DCTPtr->Timings.Speed == DDR667_FREQUENCY)) {
- MemNSetBitFieldNb (NBPtr, BFErr263, 0x0800);
- } else {
- MemNSetBitFieldNb (NBPtr, BFErr263, 0);
- }
-
- // Errata 322
- // 1.Write 00000000h to F2x[1,0]9C_xD08E000
- MemNSetBitFieldNb (NBPtr, BFErr322I, 0);
- // 2.If DRAM Configuration Register[MemClkFreq] (F2x[1,0]94[2:0]) is
- // greater than or equal to 011b (DDR-800 and higher),
- // then write 00000080h to F2x[1,0]9C_xD02E001,
- // else write 00000090h to F2x[1,0]9C_xD02E001.
- MemNSetBitFieldNb (NBPtr, BFErr322II, (NBPtr->DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ? 0x80 : 0x90);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * Change Average Value of 3
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-BOOLEAN
-MemNChangeAvgValue3DA (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- if ((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_C0) != 0) {
- return TRUE;
- } else {
- return FALSE;
- }
-}
-
-/**
- *
- *
- * Change Average Value of 8
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-BOOLEAN
-MemNChangeAvgValue8DA (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- if ((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_C1) != 0) {
- return TRUE;
- } else {
- return FALSE;
- }
-}
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * Enable DLL Shut down
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-VOID
-MemNEnDLLShutDownDA (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 Dct;
- BOOLEAN DllShutDownEn;
-
- DllShutDownEn = TRUE;
- IDS_OPTION_HOOK (IDS_DLL_SHUT_DOWN, &DllShutDownEn, &(NBPtr->MemPtr->StdHeader));
-
- if (DllShutDownEn && NBPtr->IsSupported[SetDllShutDown]) {
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- MemNSwitchDCTNb (NBPtr, Dct);
- if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
- MemNSetBitFieldNb (NBPtr, BFPhyPLLLockTime, 0x0000001C);
- MemNSetBitFieldNb (NBPtr, BFPhyDLLLockTime, 0x0000013D);
- MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 0);
- }
- }
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function caps speed based on batter life check.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- */
-VOID
-MemNCapSpeedBatteryLifeDA (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- CONST UINT16 SupportedFreq[] = {
- DDR1600_FREQUENCY,
- DDR1333_FREQUENCY,
- DDR1066_FREQUENCY,
- DDR800_FREQUENCY,
- DDR667_FREQUENCY,
- DDR533_FREQUENCY,
- DDR400_FREQUENCY
- };
- UINT32 NBFreq;
- UINT8 j;
- UINT16 DdrFreq;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
- UINT32 ProcessorPackageType;
-
- FamilySpecificServices = NULL;
- DdrFreq = DDR800_FREQUENCY; // Set Default to be 400Mhz
- ProcessorPackageType = LibAmdGetPackageType (&(NBPtr->MemPtr->StdHeader));
- GetCpuServicesOfSocket (NBPtr->MCTPtr->SocketId, &FamilySpecificServices, &(NBPtr->MemPtr->StdHeader));
- if (FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, NBPtr->MemPtr->PlatFormConfig, &(NBPtr->MemPtr->StdHeader))) {
- NBFreq = (MemNGetBitFieldNb (NBPtr, BFNbFid) + 4) * 100; // Calculate the Nb P1 frequency (NbFreq / 2)
- for (j = 0; j < GET_SIZE_OF (SupportedFreq); j++) {
- if (NBFreq >= ((UINT32) 2 * SupportedFreq[j])) {
- // Pick Max MEMCLK that is less than or equal to (NCLK_P1 / 2)
- DdrFreq = SupportedFreq[j];
- break;
- }
- }
- if (NBPtr->MemPtr->PlatFormConfig->PlatformProfile.PlatformPowerPolicy == BatteryLife) {
- if (NBPtr->DCTPtr->Timings.TargetSpeed > DdrFreq) {
- NBPtr->DCTPtr->Timings.TargetSpeed = DdrFreq;
- }
- } else {
- PutEventLog (AGESA_WARNING, MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- DdrFreq = DDR800_FREQUENCY; // Set Default to be 400Mhz
- NBFreq = (MemNGetBitFieldNb (NBPtr, BFNbFid) + 4) * 200; // Calculate the Nb P0 frequency
- for (j = 0; j < GET_SIZE_OF (SupportedFreq); j++) {
- if (NBFreq >= ((UINT32) 2 * SupportedFreq[j])) {
- // Pick Max MEMCLK that is less than or equal to (NCLK_P0 / 2)
- DdrFreq = SupportedFreq[j];
- break;
- }
- }
- if (NBPtr->DCTPtr->Timings.TargetSpeed > DdrFreq) {
- NBPtr->DCTPtr->Timings.TargetSpeed = DdrFreq;
- }
- }
- if (((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_C3) != 0) && (ProcessorPackageType == PACKAGE_TYPE_S1G3_S1G4 || ProcessorPackageType == PACKAGE_TYPE_ASB2)) {
- MemNSetBitFieldNb (NBPtr, BFRdPtrInit, 4);
- MemNSetBitFieldNb (NBPtr, BFDataTxFifoWrDly, 1);
- } else {
- MemNSetBitFieldNb (NBPtr, BFRdPtrInit, 6);
- MemNSetBitFieldNb (NBPtr, BFDataTxFifoWrDly, 0);
- }
- } else {
- NBFreq = (MemNGetBitFieldNb (NBPtr, BFNbFid) + 4) * 200; // Calculate the Nb P0 frequency
- for (j = 0; j < GET_SIZE_OF (SupportedFreq); j++) {
- if (NBFreq >= ((UINT32) 2 * SupportedFreq[j])) {
- // Pick Max MEMCLK that is less than or equal to (NCLK_P0 / 2)
- DdrFreq = SupportedFreq[j];
- break;
- }
- }
- if (NBPtr->DCTPtr->Timings.TargetSpeed > DdrFreq) {
- NBPtr->DCTPtr->Timings.TargetSpeed = DdrFreq;
- }
- MemNSetBitFieldNb (NBPtr, BFRdPtrInit, 6);
- MemNSetBitFieldNb (NBPtr, BFDataTxFifoWrDly, 0);
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mnflowda.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mnflowda.c
deleted file mode 100644
index 15dbcf1..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mnflowda.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnflowda.c
- *
- * Deerhound initializer for MCT and DCT
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/DA)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mnda.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_DA_MNFLOWDA_FILECODE
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDA[MAX_FF_TYPES];
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the platform specific block
- *
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - AGESA_SUCCESS at least one dorm factor was found
- * @return FALSE - AGESA_UNSUPPORTED - Error indicating that no form factors were found
- */
-
-BOOLEAN
-MemNPlatformSpecificFormFactorInitDA (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 Dct;
- UINT8 f;
- UINT8 ErrUnSuppFFCount;
- for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- if (NBPtr->ChannelPtr->ChDimmValid != 0) {
- ErrUnSuppFFCount = 0;
- for (f = 0; f < MAX_FF_TYPES; f++) {
- ASSERT (memPlatSpecFFInstalledDA[f] != NULL);
- if (memPlatSpecFFInstalledDA[f] (NBPtr->MemPtr, NBPtr->ChannelPtr, NBPtr->PsPtr) == AGESA_UNSUPPORTED) {
- ErrUnSuppFFCount++; //Count the number of AGESA_UNSUPPORTED errors
- } else {
- break;
- }
- }
- if (ErrUnSuppFFCount == MAX_FF_TYPES) {
- return FALSE; // No FF types are supported
- }
- }
- }
- return TRUE;
-}
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mnidendimmda.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mnidendimmda.c
deleted file mode 100644
index 9d83e03..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mnidendimmda.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnidendimmda.c
- *
- * DA northbridge constructor for dimm identification translator.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/DA)
- * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "mm.h"
-#include "mn.h"
-#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB
-#include "mnda.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_NB_DA_MNIDENDIMMDA_FILECODE
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the northbridge block for dimm identification translator
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
- * @param[in,out] NodeID - ID of current node to construct
- * @return TRUE - This is the correct constructor for the targeted node.
- * @return FALSE - This isn't the correct constructor for the targeted node.
- *
- */
-
-BOOLEAN
-MemNIdentifyDimmConstructorDA (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- )
-{
- //
- // Determine if this is the expected NB Type
- //
- GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
- if (!MemNIsIdSupportedDA (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
- return FALSE;
- }
-
- NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA;
- NBPtr->DctCount = MAX_DCTS_PER_NODE_DA;
- NBPtr->MemPtr = MemPtr;
- NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
- NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
- NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
- NBPtr->Ganged = FALSE;
- InitNBRegTableDA (NBPtr, NBPtr->NBRegTable);
- NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA;
- NBPtr->SetBitField = MemNSetBitFieldNb;
- NBPtr->GetBitField = MemNGetBitFieldNb;
- NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb;
-
- return TRUE;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mnmctda.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mnmctda.c
deleted file mode 100644
index 5aecdb7..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mnmctda.c
+++ /dev/null
@@ -1,199 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnmctda.c
- *
- * Northbridge DA MCT supporting functions
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/DA)
- * @e \$Revision: 36462 $ @e \$Date: 2010-08-20 00:49:49 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mport.h"
-#include "mm.h"
-#include "mn.h"
-#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB
-#include "mnda.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_DA_MNMCTDA_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function sets final values in BUCFG and BUCFG2
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemNFinalizeMctDA (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 Dct;
- MEM_DATA_STRUCT *MemPtr;
- S_UINT64 SMsr;
-
- MemPtr = NBPtr->MemPtr;
- MemNSetBitFieldNb (NBPtr, BFAdapPrefMissRatio, 1);
- MemNSetBitFieldNb (NBPtr, BFAdapPrefPosStep, 0);
- MemNSetBitFieldNb (NBPtr, BFAdapPrefNegStep, 0);
- MemNSetBitFieldNb (NBPtr, BFCohPrefPrbLmt, 1);
- // Recommended settings for F2x11C
- MemNSetBitFieldNb (NBPtr, BFMctWrLimit, 16);
- MemNSetBitFieldNb (NBPtr, BFPrefCpuDis, 0);
- MemNSetBitFieldNb (NBPtr, BFPrefIoDis, 0);
- MemNSetBitFieldNb (NBPtr, BFFlushWrOnStpGnt, 1);
- // For power saving
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
- if (NBPtr->ChannelPtr->Dimmx4Present == 0) {
- MemNSetBitFieldNb (NBPtr, BFPhy0x0D0F0F13, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D0F0F13) | 0x80));
- }
- if (!NBPtr->MCTPtr->Status[SbEccDimms]) {
- MemNSetBitFieldNb (NBPtr, BFPhy0x0D0F0830, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D0F0830) | 0x10));
- }
- MemNSetBitFieldNb (NBPtr, BFPhy0x0D07812F, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D07812F) | 0x01));
- }
- }
-
- if (NBPtr->Node == BSP_DIE) {
- if (!NBPtr->ClToNbFlag) {
- LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- SMsr.lo &= ~((UINT32)1 << 15); // ClLinesToNbDis
- LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- }
-
- LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- SMsr.hi &= ~((UINT32)1 << (48 - 32)); // WbEnhWsbDis
- LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- }
-
- return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function sets initial values in BUCFG and BUCFG2
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemNInitializeMctDA (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MEM_DATA_STRUCT *MemPtr;
- S_UINT64 SMsr;
-
- MemPtr = NBPtr->MemPtr;
-
- if (NBPtr->Node == BSP_DIE) {
- LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- if (SMsr.lo & ((UINT32)1 << 15)) {
- NBPtr->ClToNbFlag = 1;
- }
- SMsr.lo |= (UINT32)1 << 15; // ClLinesToNbDis
- LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-
- LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- SMsr.hi |= (UINT32)1 << (48 - 32); // WbEnhWsbDis
- LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- }
- return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mnotda.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mnotda.c
deleted file mode 100644
index 22d34ce..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mnotda.c
+++ /dev/null
@@ -1,201 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnotda.c
- *
- * Northbridge Non-SPD timings for DA
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/DA)
- * @e \$Revision: 36462 $ @e \$Date: 2010-08-20 00:49:49 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB
-#include "mnda.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_DA_MNOTDA_FILECODE
-
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-VOID
-STATIC
-MemNSetOtherTimingDA (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-STATIC
-MemNPowerDownCtlDA (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function sets the non-SPD timings
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemNOtherTimingDA (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MemNSwitchDCTNb (NBPtr, 0);
- if (NBPtr->DCTPtr->Timings.DctDimmValid > 0) {
- MemNSetOtherTimingDA (NBPtr); // Set DA Timings
- MemNPowerDownCtlNb (NBPtr);
- MemNEnDLLShutDownDA (NBPtr);
- }
-
- MemNSwitchDCTNb (NBPtr, 1);
- if ((NBPtr->DCTPtr->Timings.DctDimmValid > 0) && (NBPtr->MCTPtr->GangedMode == FALSE)) {
- MemNSetOtherTimingDA (NBPtr); // Set DA Timings
- MemNPowerDownCtlNb (NBPtr);
- MemNEnDLLShutDownDA (NBPtr);
- }
- return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function sets the non-SPD timings into the PCI registers
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-STATIC
-MemNSetOtherTimingDA (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MemNSetBitFieldNb (NBPtr, BFTrdrd, MemNGetTrdrdNb (NBPtr));
- MemNSetBitFieldNb (NBPtr, BFTwrwr, MemNGetTwrwrNb (NBPtr));
- MemNSetBitFieldNb (NBPtr, BFTwrrd, MemNGetTwrrdNb (NBPtr));
- MemNSetBitFieldNb (NBPtr, BFTrwtTO, MemNGetTrwtTONb (NBPtr));
- MemNSetBitFieldNb (NBPtr, BFTrwtWB, MemNGetTrwtWBNb (NBPtr));
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function enables power down mode
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-STATIC
-MemNPowerDownCtlDA (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MEM_PARAMETER_STRUCT *RefPtr;
- UINT8 PowerDownMode;
-
- RefPtr = NBPtr->RefPtr;
-
- // we can't enable powerdown mode when doing WL
- if (RefPtr->EnablePowerDown) {
- MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 1);
- PowerDownMode = (UINT8) UserOptions.CfgPowerDownMode;
- IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader));
- if (PowerDownMode) {
- MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1);
- }
- }
-}
-
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mnprotoda.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mnprotoda.c
deleted file mode 100644
index ef042d3..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mnprotoda.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnprotoda.c
- *
- * Northbridge support functions for Errata and early samples
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/DA)
- * @e \$Revision: 36462 $ @e \$Date: 2010-08-20 00:49:49 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-
-#include "AGESA.h"
-#include "mm.h"
-#include "mn.h"
-#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB
-#include "mnda.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_DA_MNPROTODA_FILECODE
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function executes Node memory 1GB boundary alignment.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *NodeSysLimit - Pointer to the NodeSysLimit
- *
- */
-
-VOID
-MemPNodeMemBoundaryDA (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT UINT32 *NodeSysLimit
- )
-{
- if (NBPtr->GetBitField (NBPtr, BFDdr3Mode) == 0) {
- // only apply to DDR2.
- if (*NodeSysLimit > ((UINT32)1 << (30 - 16))) {
- // if (NodeSysLimit > 1GB) then set to Node limit to 1GB boundary for each node
- *NodeSysLimit += 1;
- *NodeSysLimit &= 0xFFFFC000;
- *NodeSysLimit -= 1;
- }
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mnregda.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mnregda.c
deleted file mode 100644
index 2de8daf..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/DA/mnregda.c
+++ /dev/null
@@ -1,574 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnregda.c
- *
- * Common Northbridge register related functions for DA
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/DA)
- * @e \$Revision: 38303 $ @e \$Date: 2010-09-22 00:22:47 +0800 (Wed, 22 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mnda.h"
-#include "merrhdl.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_DA_MNREGDA_FILECODE
-
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/*-----------------------------------------------------------------------------*/
-/**
- * MemNIsIdSupportedDA
- * This function matches the CPU_LOGICAL_ID with certain criteria to
- * determine if it is supported by this NBBlock.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID
- *
- * @return TRUE - This node is a RB.
- * @return FALSE - This node is not a RB.
- *
- */
-BOOLEAN
-MemNIsIdSupportedDA (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN CPU_LOGICAL_ID *LogicalIdPtr
- )
-{
-
- if (((LogicalIdPtr->Family & (AMD_FAMILY_10_BL | AMD_FAMILY_10_DA)) != 0)
- && ((LogicalIdPtr->Revision & (AMD_F10_BL_ALL | AMD_F10_DA_ALL)) != 0)) {
- return TRUE;
- } else {
- return FALSE;
- }
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------*/
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function gets or sets a value to a bit field in a PCI register.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] FieldName - Bit Field to be programmed
- * @param[in] Field - Value to be programmed
- * @param[in] IsSet - Indicates if the function will set or get
- *
- * @return value read, if the function is used as a "get"
- */
-
-UINT32
-MemNCmnGetSetFieldDA (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN BIT_FIELD_NAME FieldName,
- IN UINT32 Field
- )
-{
- TSEFO Address;
- PCI_ADDR PciAddr;
- UINT8 Type;
- UINT8 IsLinked;
- UINT32 Value;
- UINT32 Highbit;
- UINT32 Lowbit;
- UINT32 Mask;
-
- Value = 0;
- if ((FieldName < BFEndOfList) && (FieldName >= 0)) {
- Address = NBPtr->NBRegTable[FieldName];
- if (Address) {
- Lowbit = TSEFO_END (Address);
- Highbit = TSEFO_START (Address);
- Type = (UINT8) TSEFO_TYPE (Address);
- IsLinked = (UINT8) TSEFO_LINKED (Address);
-
- // If Fn2 and DCT1 selected, set Address to be 1xx
- if ((Type == NB_ACCESS) && ((Address & 0xF000) == 0x2000) && NBPtr->Dct) {
- if (!NBPtr->Ganged || (Address & 0xFF) == 0x98 || (Address & 0xFF) == 0x9C) {
- Address |= 0x0100;
- }
- }
-
- ASSERT ((Address & ((UINT32) 1) << 28) == 0); // Phy direct access method is not supported
-
- if ((Address >> 29) == ((DCT_PHY_ACCESS << 1) | 1)) {
- // Special DCT Phy access
- Address &= 0x0FFFFFFF;
- Lowbit = 0;
- Highbit = 16;
- IsLinked = 0;
- } else {
- // Normal DCT Phy access
- Address = TSEFO_OFFSET (Address);
- }
-
- if (Type == NB_ACCESS) {
- PciAddr.AddressValue = Address;
- PciAddr.Address.Device = NBPtr->PciAddr.Address.Device;
- PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus;
- PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment;
- Address = PciAddr.AddressValue;
- LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
- if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) &&
- (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) {
- IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Value);
- }
- } else if (Type == DCT_PHY_ACCESS) {
- MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
- MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
- Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
- IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%d9C_%x = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Value);
- } else {
- IDS_ERROR_TRAP;
- }
-
- if (IsSet) {
- // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
- if ((Highbit - Lowbit) != 31) {
- Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
- } else {
- Mask = (UINT32)0xFFFFFFFF;
- }
- Value &= ~(Mask << Lowbit);
- Value |= (Field & Mask) << Lowbit;
-
- if (Type == NB_ACCESS) {
- PciAddr.AddressValue = Address;
- LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
- if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) &&
- (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) {
- IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Highbit, Lowbit, Field);
- }
- } else if (Type == DCT_PHY_ACCESS) {
- MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
- Address |= DCT_ACCESS_WRITE;
- MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
- MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
- IDS_HDT_CONSOLE (MEM_SETREG, "~Fn2_%d9C_%x [%d:%d] = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Highbit, Lowbit, Field);
- } else {
- IDS_ERROR_TRAP;
- }
- if (IsLinked) {
- MemNCmnGetSetFieldDA (NBPtr, 1, FieldName + 1, Field >> (Highbit - Lowbit + 1));
- }
- } else {
- Value = Value >> Lowbit; // Shift
- // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
- if ((Highbit - Lowbit) != 31) {
- Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
- }
- if (IsLinked) {
- Value |= MemNCmnGetSetFieldDA (NBPtr, 0, FieldName + 1, 0) << (Highbit - Lowbit + 1);
- }
- }
- }
- } else {
- IDS_ERROR_TRAP; // Invalid bit field index
- }
- return Value;
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes bit field translation table
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] NBRegTable[] - Pointer to the bit field data structure
- *
- */
-
-VOID
-InitNBRegTableDA (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT TSEFO NBRegTable[]
- )
-{
- UINT16 i;
- for (i = 0; i < BFEndOfList; i++) {
- NBRegTable[i] = 0;
- }
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31, 0, BFDevVendorIDReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60), 2, 0, BFNodeID);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60), 6, 4, BFNodeCnt);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x48), 31, 0, BFDramBaseReg1);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x4C), 31, 0, BFDramLimitReg1);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x50), 31, 0, BFDramBaseReg2);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x54), 31, 0, BFDramLimitReg2);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x58), 31, 0, BFDramBaseReg3);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x5C), 31, 0, BFDramLimitReg3);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x60), 31, 0, BFDramBaseReg4);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x64), 31, 0, BFDramLimitReg4);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x68), 31, 0, BFDramBaseReg5);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x6C), 31, 0, BFDramLimitReg5);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x70), 31, 0, BFDramBaseReg6);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x74), 31, 0, BFDramLimitReg6);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x78), 31, 0, BFDramBaseReg7);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x7C), 31, 0, BFDramLimitReg7);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 0, BFDramHoleAddrReg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x140), 7, 0, BFDramBaseHiReg0);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x144), 7, 0, BFDramLimitHiReg0);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x148), 7, 0, BFDramBaseHiReg1);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x14C), 7, 0, BFDramLimitHiReg1);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x150), 7, 0, BFDramBaseHiReg2);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x154), 7, 0, BFDramLimitHiReg2);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x158), 7, 0, BFDramBaseHiReg3);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x15C), 7, 0, BFDramLimitHiReg3);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x160), 7, 0, BFDramBaseHiReg4);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x164), 7, 0, BFDramLimitHiReg4);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x168), 7, 0, BFDramBaseHiReg5);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x16C), 7, 0, BFDramLimitHiReg5);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x170), 7, 0, BFDramBaseHiReg6);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x174), 7, 0, BFDramLimitHiReg6);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x178), 7, 0, BFDramBaseHiReg7);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x17C), 7, 0, BFDramLimitHiReg7);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 24, BFDramHoleBase);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 15, 7, BFDramHoleOffset);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 1, 1, BFDramMemHoistValid);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 0, 0, BFDramHoleValid);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 20, 0, BFDramBaseAddr);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 23, 21, BFDramIntlvSel);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 20, 0, BFDramLimitAddr);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 26, 21, BFDramIntlvEn);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31, 0, BFCSBaseAddr0Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31, 0, BFCSBaseAddr1Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31, 0, BFCSBaseAddr2Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31, 0, BFCSBaseAddr3Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x50), 31, 0, BFCSBaseAddr4Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x54), 31, 0, BFCSBaseAddr5Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x58), 31, 0, BFCSBaseAddr6Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x5C), 31, 0, BFCSBaseAddr7Reg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31, 0, BFCSMask0Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31, 0, BFCSMask1Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x68), 31, 0, BFCSMask2Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x6C), 31, 0, BFCSMask3Reg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 0, BFDramControlReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 0, BFDramInitRegReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31, 0, BFDramBankAddrReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31, 0, BFDramMRSReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 0, BFDramTimingLoReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 0, BFDramTimingHiReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31, 0, BFDramConfigLoReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 0, BFDramConfigHiReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 0, BFDctAddlOffsetReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31, 0, BFDctAddlDataReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 31, BFDctAccessDone);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA0), 31, 0, BFDramConfigMiscReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 31, 0, BFDramCtrlMiscReg2);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF4), 31, 0, BFDctExtraDataReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 31, 0, BFMctCfgHiReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 31, 0, BFMctCfgLoReg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x40), 31, 0, BFMcaNbCtlReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44), 22, 22, BFDramEccEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44), 2, 2, BFSyncOnUcEccEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x180), 25, 25, BFEccSymbolSize);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x48), 31, 0, BFMcaNbStatusLoReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x4C), 31, 0, BFMcaNbStatusHiReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 4, 0, BFDramScrub);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 12, 8, BFL2Scrub);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 20, 16, BFDcacheScrub);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 28, 24, BFL3Scrub);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C), 0, 0, BFScrubReDirEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C), 31, 0, BFScrubAddrLoReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x60), 31, 0, BFScrubAddrHiReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x84), 31, 29, BFC1ClkDivisor);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x8C), 4, 4, BFDisDatMsk);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4), 4, 0, BFNbFid);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 25, 25, BFL3Capable);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x188), 8, 8, BFDisableL3);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 8, BFNonSPDHi);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 3, 0, BFRdPtrInit);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 9, 8, BFTwrrdHi);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 11, 10, BFTwrwrHi);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 12, BFTrdrdHi);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 16, 16, BFAltVidC3MemClkTriEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 18, 18, BFDqsRcvEnTrain);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 19, 19, BFEarlyArbEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15, 0, BFMrsAddress);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 18, 16, BFMrsBank);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 22, 20, BFMrsChipSel);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 24, 24, BFSendPchgAll);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 25, 25, BFSendAutoRefresh);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 30, 30, BFSendCtrlWord);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 7, 7, BFMrsLevel);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 12, 12, BFMrsQoff);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 1, 0, BFBurstCtrl);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 3, 2, BFDrvImpCtrl);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 9, 7, BFDramTerm_DDR3);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 11, 10, BFDramTermDyn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 13, 13, BFQoff);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 18, 18, BFASR);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 19, 19, BFSRT);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 22, 20, BFTcwl);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 23, 23, BFPchgPDModeSel);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 6, 4, BFTwrDDR3);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 3, 0, BFTcl);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 6, 4, BFTrcd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 9, 7, BFTrp);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 11, 10, BFTrtp);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 15, 12, BFTras);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 20, 16, BFTrc);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 21, 20, BFTwr);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 23, 22, BFTrrd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 24, BFMemClkDis);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 0, BFNonSPD);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 3, 0, BFTrwtWB);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 7, 4, BFTrwtTO);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 9, 8, BFTwtr);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 11, 10, BFTwrrd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 13, 12, BFTwrwr);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 14, BFTrdrd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 17, 16, BFTref);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 22, 20, BFTrfc0);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 25, 23, BFTrfc1);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 28, 26, BFTrfc2);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 29, BFTrfc3);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 0, 0, BFInitDram);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 1, 1, BFExitSelfRef);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 5, 4, BFDramTerm);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 8, 8, BFParEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 10, 10, BFBurstLength32);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 11, 11, BFWidth128);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 15, 12, BFX4Dimm);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 16, 16, BFUnBuffDimm);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 17, 17, BFEnterSelfRef);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 19, 19, BFDimmEccEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 21, 21, BFFreqChgInProg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 23, 23, BFForceAutoPchg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 27, 27, BFDisDllShutdownSR);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 2, 0, BFMemClkFreq);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 3, 3, BFMemClkFreqVal);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 8, 8, BFDdr3Mode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 9, 9, BFLegacyBiosMode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 12, 12, BFRDqsEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 15, 15, BFPowerDownEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 16, 16, BFPowerDownMode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 17, 17, BFFourRankSoDimm);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 19, 19, BFDcqArbBypassEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 18, 18, BFFourRankRDimm);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 20, 20, BFSlowAccessMode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 22, 22, BFBankSwizzleMode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 27, 24, BFDcqBypassMax);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 28, BFFourActWindow);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 8, 8, BFODTSEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 14, 12, BFCmdThrottleMode);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 2, 2, BFDdr3FourSocketCh);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 5, 5, BFSubMemclkRegDly);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 6, 6, BFOdtSwizzle);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 15, 8, BFCtrlWordCS);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 18, 16, BFDataTxFifoWrDly);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x10C), 0, 0, BFIntLvRgnSwapEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x10C), 9, 3, BFIntLvRgnBaseAddr);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x10C), 17, 11, BFIntLvRgnLmtAddr);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x10C), 26, 20, BFIntLvRgnSize);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 0, 0, BFDctSelHiRngEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 1, 1, BFDctSelHi);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 2, 2, BFDctSelIntLvEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 3, 3, BFMemClrInit);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 4, 4, BFDctGangEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 5, 5, BFDctDatIntLv);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 7, 6, BFDctSelIntLvAddr);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 8, 8, BFDramEnabled);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 9, 9, BFMemClrBusy);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 10, 10, BFMemCleared);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 31, 11, BFDctSelBaseAddr);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 31, 10, BFDctSelBaseOffset);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 1, 0, BFDctWrLimit);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 6, 2, BFMctWrLimit);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 11, 7, BFMctPrefReqLimit);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 12, 12, BFPrefCpuDis);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 13, 13, BFPrefIoDis);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 28, 28, BFPrefDramTrainMode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 30, 30, BFFlushWr);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 29, 29, BFFlushWrOnStpGnt);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 1, 0, BFAdapPrefMissRatio);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 3, 2, BFAdapPrefPosStep);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 5, 4, BFAdapPrefNegStep);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 10, 8, BFCohPrefPrbLmt);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xB0), 31, 0, BFOnLineSpareControl);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 7, 5, BFDdrMaxRate);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 9, 8, BFAddrCmdDrvStren);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 17, 16, BFDataDrvStren);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31, 0, BFODCControl);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31, 0, BFAddrTmgControl);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 0, 0, BFWrtLvTrEn);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 1, 1, BFWrtLvTrMode);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 3, 3, BFPhyFenceTrEn);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 5, 4, BFTrDimmSel);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11, 8, BFWrLvOdt);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 13, 13, BFDqsRcvTrEn);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 30, 30, BFDisAutoComp);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x53, 8, 0, BFWrtLvErr);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 27, 25, BFD3Cmp2PCal);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 22, 20, BFD3Cmp2NCal);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 17, 15, BFD3Cmp1PCal);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 12, 10, BFD3Cmp1NCal);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 7, 5, BFD3Cmp0PCal);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 2, 0, BFD3Cmp0NCal);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 20, 16, BFPhyFence);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 13, 12, BFCKETri);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 11, 8, BFODTTri);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 7, 0, BFChipSelTri);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D040F30, _NOT_USED_, _NOT_USED_, BFErr263);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F0C, _NOT_USED_, _NOT_USED_, BFErr350);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D08E000, _NOT_USED_, _NOT_USED_, BFErr322I);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D02E001, _NOT_USED_, _NOT_USED_, BFErr322II);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0FE006, _NOT_USED_, _NOT_USED_, BFPhyPLLLockTime);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0FE007, _NOT_USED_, _NOT_USED_, BFPhyDLLLockTime);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 31, 0, BFPhyDLLControl);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F0C, _NOT_USED_, _NOT_USED_, BFPhy0x0D080F0C);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F11, _NOT_USED_, _NOT_USED_, BFPhy0x0D080F11);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F10, _NOT_USED_, _NOT_USED_, BFPhy0x0D080F10);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D088F30, _NOT_USED_, _NOT_USED_, BFPhy0x0D088F30);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D08C030, _NOT_USED_, _NOT_USED_, BFPhy0x0D08C030);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D082F30, _NOT_USED_, _NOT_USED_, BFPhy0x0D082F30);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D040F3E, _NOT_USED_, _NOT_USED_, BFPhy0x0D040F3E);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D042F3E, _NOT_USED_, _NOT_USED_, BFPhy0x0D042F3E);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D048F3E, _NOT_USED_, _NOT_USED_, BFPhy0x0D048F3E);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D04DF3E, _NOT_USED_, _NOT_USED_, BFPhy0x0D04DF3E);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2030, _NOT_USED_, _NOT_USED_, BFPhyClkConfig0);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2130, _NOT_USED_, _NOT_USED_, BFPhyClkConfig1);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2230, _NOT_USED_, _NOT_USED_, BFPhyClkConfig2);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2330, _NOT_USED_, _NOT_USED_, BFPhyClkConfig3);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F0F13, _NOT_USED_, _NOT_USED_, BFPhy0x0D0F0F13);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F0830, _NOT_USED_, _NOT_USED_, BFPhy0x0D0F0830);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D07812F, _NOT_USED_, _NOT_USED_, BFPhy0x0D07812F);
-
- LINK_TSEFO (NBRegTable, BFTwrrd, BFTwrrdHi);
- LINK_TSEFO (NBRegTable, BFTwrwr, BFTwrwrHi);
- LINK_TSEFO (NBRegTable, BFTrdrd, BFTrdrdHi);
-
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mnParTrainDr.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mnParTrainDr.c
deleted file mode 100644
index 33ec0c7..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mnParTrainDr.c
+++ /dev/null
@@ -1,226 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnParTrainDr.c
- *
- * Feature which performs Memory DQS training on each node with each node training
- * its own memory through code running on a core in the associated processor.
- * This way memory can be trained in parallel by more than one processor.
- *
- * This file contains the Deerhound specific parallel training function.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Feat/HCTRN)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mndr.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuServices.h"
-#include "GeneralServices.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuApicUtilities.h"
-#include "mfParallelTraining.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_NB_DR_MNPARTRAINDR_FILECODE
-
-/*-----------------------------------------------------------------------------
-* EXPORTED FUNCTIONS
-*
-*-----------------------------------------------------------------------------
-*/
-
-BOOLEAN
-STATIC
-MemConstructRemoteNBBlockDR (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN DIE_STRUCT *MCTPtr,
- IN MEM_FEAT_BLOCK_NB *FeatPtr
-);
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This is the training function which set up the environment for remote
- * training on the ap and launches the remote routine.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - Launch training on AP successfully.
- * @return FALSE - Fail to launch training on AP.
- */
-BOOLEAN
-MemFParallelTrainingDr (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- AMD_CONFIG_PARAMS *StdHeader;
- DIE_STRUCT *MCTPtr;
- REMOTE_TRAINING_ENV *EnvPtr;
- AP_TASK TrainingTask;
- UINT8 Socket;
- UINT8 Module;
- UINT8 APCore;
- UINT8 p;
- UINT32 LowCore;
- UINT32 HighCore;
- UINT32 BspSocket;
- UINT32 BspModule;
- UINT32 BspCore;
- AGESA_STATUS Status;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
- UINT16 MctDataSize;
-
- StdHeader = &(NBPtr->MemPtr->StdHeader);
- MCTPtr = NBPtr->MCTPtr;
- Socket = MCTPtr->SocketId;
- Module = MCTPtr->DieId;
-
- //
- // Allocate buffer for REMOTE_TRAINING_ENV
- //
- MctDataSize = MAX_DCTS_PER_NODE_DR * (
- sizeof (DCT_STRUCT) + (
- MAX_CHANNELS_PER_DCT_DR * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))
- )
- );
- AllocHeapParams.RequestedBufferSize = MctDataSize + sizeof (REMOTE_TRAINING_ENV);
- AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, Socket, Module, 0);
- AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
- if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
- EnvPtr = (REMOTE_TRAINING_ENV *) AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += sizeof (REMOTE_TRAINING_ENV);
-
- //
- // Setup Remote training environment
- //
- LibAmdMemCopy (&(EnvPtr->StdHeader), StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);
- LibAmdMemCopy (&(EnvPtr->DieStruct), MCTPtr, sizeof (DIE_STRUCT), StdHeader);
- for (p = 0; p < MAX_PLATFORM_TYPES; p++) {
- EnvPtr->GetPlatformCfg[p] = NBPtr->MemPtr->GetPlatformCfg[p];
- }
- EnvPtr->ErrorHandling = NBPtr->MemPtr->ErrorHandling;
- EnvPtr->NBBlockCtor = MemConstructRemoteNBBlockDR;
- EnvPtr->FeatPtr = NBPtr->FeatPtr;
- EnvPtr->HoleBase = NBPtr->RefPtr->HoleBase;
- EnvPtr->BottomIo = NBPtr->RefPtr->BottomIo;
- EnvPtr->SysLimit = NBPtr->RefPtr->SysLimit;
- EnvPtr->TableBasedAlterations = NBPtr->RefPtr->TableBasedAlterations;
- EnvPtr->PlatformMemoryConfiguration = NBPtr->RefPtr->PlatformMemoryConfiguration;
-
- LibAmdMemCopy (AllocHeapParams.BufferPtr, MCTPtr->DctData, MctDataSize, StdHeader);
-
- //
- // Get Socket, Core of the BSP
- //
- IdentifyCore (StdHeader, &BspSocket, &BspModule, &BspCore, &Status);
- EnvPtr->BspSocket = ((UINT8)BspSocket & 0x000000FF);
- EnvPtr->BspCore = ((UINT8)BspCore & 0x000000FF);
-
- //
- // Set up the remote task structure
- //
- TrainingTask.DataTransfer.DataPtr = EnvPtr;
- TrainingTask.DataTransfer.DataSizeInDwords = (UINT16) (AllocHeapParams.RequestedBufferSize + 3) / 4;
- TrainingTask.DataTransfer.DataTransferFlags = 0;
- TrainingTask.ExeFlags = 0;
- TrainingTask.FuncAddress.PfApTaskI = (PF_AP_TASK_I)MemFParallelTraining;
-
- //
- // Get Target AP Core
- //
- GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader);
- APCore = (UINT8) (LowCore & 0x000000FF);
-
- //
- // Launch Remote Training
- //
- ApUtilRunCodeOnSocketCore (Socket, APCore, &TrainingTask, StdHeader);
-
- HeapDeallocateBuffer (AllocHeapParams.BufferHandle, StdHeader);
- return TRUE;
- } else {
- PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV, NBPtr->Node, 0, 0, 0, StdHeader);
- SetMemError (AGESA_FATAL, MCTPtr);
- ASSERT(FALSE); // Could not allocated heap space for "REMOTE_TRAINING_ENV"
- return FALSE;
- }
-}
-
-BOOLEAN
-STATIC
-MemConstructRemoteNBBlockDR (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN DIE_STRUCT *MCTPtr,
- IN MEM_FEAT_BLOCK_NB *FeatPtr
- )
-{
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
-
- NBPtr->MCTPtr = MCTPtr;
- NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue;
-
- MemNInitNBDataDr (NBPtr);
-
- FeatPtr->InitCPG (NBPtr);
- NBPtr->FeatPtr = FeatPtr;
- FeatPtr->InitHwRxEn (NBPtr);
- MemNSwitchDCTNb (NBPtr, 0);
-
- //----------------------------------------------------------------------------
- // Get TSC rate of the this AP
- //----------------------------------------------------------------------------
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
- FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader);
-
- return TRUE;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mnS3dr.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mnS3dr.c
deleted file mode 100644
index a9b75d9..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mnS3dr.c
+++ /dev/null
@@ -1,716 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mns3dr.c
- *
- * DR memory specific function to support S3 resume
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/DR)
- * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "S3.h"
-#include "mfs3.h"
-#include "mndr.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "mnS3dr.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G3_DXE)
-RDATA_GROUP (G3_DXE)
-
-#define FILECODE PROC_MEM_NB_DR_MNS3DR_FILECODE
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-UINT16
-STATIC
-MemNS3GetRegLstPtrDr (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT DESCRIPTOR_GROUP *DescriptPtr
- );
-
-AGESA_STATUS
-STATIC
-MemNS3GetDeviceRegLstDr (
- IN UINT32 RegisterLstID,
- OUT VOID **RegisterHeader
- );
-
-VOID
-STATIC
-MemNS3SetSpecialPCIRegDr (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR Address,
- IN VOID *Value,
- IN OUT VOID *ConfigPtr
- );
-
-VOID
-STATIC
-MemNS3ExitSelfRefRegDr (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-PCI_SPECIAL_CASE PciSpecialCaseFuncDr[] = {
- {MemNS3GetCSRNb, MemNS3SetCSRNb},
- {MemNS3GetCSRNb, MemNS3SetSpecialPCIRegDr},
- {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb}
-};
-
-PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorDr[] = {
- {{0, 0, 0}, FUNC_2, 0x110, 0xFFFFFFFF},
- {{0, 0, 0}, FUNC_1, 0x40, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x48, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x50, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x58, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x60, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x68, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x70, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x78, 0xFFFF3F03},
- {{0, 1, 0}, FUNC_1, 0x140, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x148, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x150, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x158, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x160, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x168, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x170, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x178, 0x000000FF},
- {{0, 0, 0}, FUNC_1, 0x44, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x4C, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x54, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x5C, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x64, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x6C, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x74, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x7C, 0xFFFF07FF},
- {{0, 1, 0}, FUNC_1, 0x144, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x14C, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x154, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x15C, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x164, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x16C, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x174, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x17C, 0x000000FF},
- {{0, 0, 0}, FUNC_1, 0xF0, 0xFF00FF83},
- {{0, 0, 0}, FUNC_1, 0x120, 0x00FFFFFF},
- {{0, 0, 0}, FUNC_1, 0x124, 0x07FFFFFF},
- {{0, 0, 0}, FUNC_2, 0x114, 0xFFFFFC00},
- {{0, 0, 0}, FUNC_2, 0x118, 0xF773FFFF},
- {{0, 0, 0}, FUNC_2, 0x11C, 0xFFFFFFFF},
- {{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F}
-};
-
-CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefDr = {
- 0,
- (sizeof (S3PciPreSelfRefDescriptorDr) / sizeof (PCI_REG_DESCRIPTOR)),
- S3PciPreSelfRefDescriptorDr,
- NULL
-};
-
-CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorDr[] = {
- // DCT 0
- {{0, 0, 0}, FUNC_2, 0x40, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x44, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x48, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x4C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x50, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x54, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x58, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x5C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x60, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x64, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x68, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x6C, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x78, 0xFFCDBF0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x7C, 0xFFF7FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 2, 0}, FUNC_2, 0x80, 0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x84, 0x07FFEFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x88, 0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x8C, 0xFFFF7FFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x90, 0x00FFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0xA8, 0x0007FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), 0x30333333, DCT0_MASK, ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0x3FFFFFFF, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), 0x001FBFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), 0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhyClkConfig0, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhyClkConfig1, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhyClkConfig2, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhyClkConfig3, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- // errata 322
- {{2, 2, 1}, DCT0, BFErr322I, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFErr322II, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- // errata 263
- {{2, 2, 1}, DCT0, BFErr263, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-
- // DCT 1
- {{0, 0, 0}, FUNC_2, 0x140, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x144, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x148, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x14C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x150, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x154, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x158, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x15C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x160, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x164, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x168, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x16C, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x178, 0xFFCDBF0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x17C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 2, 0}, FUNC_2, 0x180, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x184, 0x07FFEFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x188, 0xFFFFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x18C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x190, 0x00FFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x1A8, 0x0007FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), 0x30333333, DCT1_MASK, ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x001FBFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyClkConfig0, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyClkConfig1, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyClkConfig2, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyClkConfig3, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- // errata 322
- {{2, 2, 1}, DCT1, BFErr322I, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFErr322II, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- // errata 263
- {{2, 2, 1}, DCT1, BFErr263, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-
- // Restore F2x[1,0]94 right before exit self refresh
- {{0, 0, 0}, FUNC_2, 0x94, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x194, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK}
-};
-
-CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefDr = {
- 0,
- (sizeof (S3CPciPreSelfDescriptorDr) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
- S3CPciPreSelfDescriptorDr,
- PciSpecialCaseFuncDr
-};
-
-CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorDr[] = {
- // DCT0
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10), 0x01FF01FF, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11), 0x01FF01FF, DCT0_MASK, 0x01},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12), 0x000001FF, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13), 0x01FF01FF, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14), 0x01FF01FF, DCT0_MASK, 0x04},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15), 0x000001FF, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16), 0x01FF01FF, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17), 0x01FF01FF, DCT0_MASK, 0x10},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18), 0x000001FF, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19), 0x01FF01FF, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A), 0x01FF01FF, DCT0_MASK, 0x40},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B), 0x000001FF, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20), 0x01FF01FF, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21), 0x01FF01FF, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23), 0x01FF01FF, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24), 0x01FF01FF, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26), 0x01FF01FF, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27), 0x01FF01FF, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29), 0x01FF01FF, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A), 0x01FF01FF, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01), 0x7F7F7F7F, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02), 0x7F7F7F7F, DCT0_MASK, 0x01},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03), 0x0000007F, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0x7F7F7F7F, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0x7F7F7F7F, DCT0_MASK, 0x04},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x0000007F, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0x7F7F7F7F, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0x7F7F7F7F, DCT0_MASK, 0x10},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x0000007F, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0x7F7F7F7F, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0x7F7F7F7F, DCT0_MASK, 0x40},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x0000007F, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05), 0x3F3F3F3F, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06), 0x3F3F3F3F, DCT0_MASK, 0x01},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x07), 0x0000003F, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3F3F3F3F, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3F3F3F3F, DCT0_MASK, 0x04},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x107), 0x0000003F, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3F3F3F3F, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3F3F3F3F, DCT0_MASK, 0x10},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x207), 0x0000003F, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3F3F3F3F, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3F3F3F3F, DCT0_MASK, 0x40},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x307), 0x0000003F, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0xFFFFFFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D), 0x23772377, DCT0_MASK, ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30), 0x00FF00FF, DCT0_DDR3_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31), 0x00FF00FF, DCT0_DDR3_MASK, 0x01},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32), 0x000000FF, DCT0_DDR3_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33), 0x00FF00FF, DCT0_DDR3_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34), 0x00FF00FF, DCT0_DDR3_MASK, 0x04},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35), 0x000000FF, DCT0_DDR3_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36), 0x00FF00FF, DCT0_DDR3_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37), 0x00FF00FF, DCT0_DDR3_MASK, 0x10},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38), 0x000000FF, DCT0_DDR3_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39), 0x00FF00FF, DCT0_DDR3_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B), 0x000000FF, DCT0_DDR3_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40), 0x00FF00FF, DCT0_DDR3_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41), 0x00FF00FF, DCT0_DDR3_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43), 0x00FF00FF, DCT0_DDR3_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44), 0x00FF00FF, DCT0_DDR3_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46), 0x00FF00FF, DCT0_DDR3_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47), 0x00FF00FF, DCT0_DDR3_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49), 0x00FF00FF, DCT0_DDR3_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40},
-
- // DCT1
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10), 0x01FF01FF, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11), 0x01FF01FF, DCT1_MASK, 0x02},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x12), 0x000001FF, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13), 0x01FF01FF, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14), 0x01FF01FF, DCT1_MASK, 0x08},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x15), 0x000001FF, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x16), 0x01FF01FF, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x17), 0x01FF01FF, DCT1_MASK, 0x20},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x18), 0x000001FF, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x19), 0x01FF01FF, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1A), 0x01FF01FF, DCT1_MASK, 0x80},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1B), 0x000001FF, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20), 0x01FF01FF, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21), 0x01FF01FF, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23), 0x01FF01FF, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24), 0x01FF01FF, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x26), 0x01FF01FF, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x27), 0x01FF01FF, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x29), 0x01FF01FF, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x2A), 0x01FF01FF, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01), 0x7F7F7F7F, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02), 0x7F7F7F7F, DCT1_MASK, 0x02},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x03), 0x0000007F, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101), 0x7F7F7F7F, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102), 0x7F7F7F7F, DCT1_MASK, 0x08},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x103), 0x0000007F, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x201), 0x7F7F7F7F, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x202), 0x7F7F7F7F, DCT1_MASK, 0x20},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x203), 0x0000007F, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x301), 0x7F7F7F7F, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x302), 0x7F7F7F7F, DCT1_MASK, 0x80},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x303), 0x0000007F, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05), 0x3F3F3F3F, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06), 0x3F3F3F3F, DCT1_MASK, 0x02},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x07), 0x0000003F, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105), 0x3F3F3F3F, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106), 0x3F3F3F3F, DCT1_MASK, 0x08},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x107), 0x0000003F, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x205), 0x3F3F3F3F, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x206), 0x3F3F3F3F, DCT1_MASK, 0x20},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x207), 0x0000003F, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x305), 0x3F3F3F3F, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x306), 0x3F3F3F3F, DCT1_MASK, 0x80},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x307), 0x0000003F, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D), 0x23772377, DCT1_MASK, ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30), 0x00FF00FF, DCT1_DDR3_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31), 0x00FF00FF, DCT1_DDR3_MASK, 0x02},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x32), 0x000000FF, DCT1_DDR3_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33), 0x00FF00FF, DCT1_DDR3_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34), 0x00FF00FF, DCT1_DDR3_MASK, 0x08},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x35), 0x000000FF, DCT1_DDR3_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x36), 0x00FF00FF, DCT1_DDR3_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x37), 0x00FF00FF, DCT1_DDR3_MASK, 0x20},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x38), 0x000000FF, DCT1_DDR3_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x39), 0x00FF00FF, DCT1_DDR3_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3B), 0x000000FF, DCT1_DDR3_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40), 0x00FF00FF, DCT1_DDR3_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41), 0x00FF00FF, DCT1_DDR3_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43), 0x00FF00FF, DCT1_DDR3_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44), 0x00FF00FF, DCT1_DDR3_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x46), 0x00FF00FF, DCT1_DDR3_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x47), 0x00FF00FF, DCT1_DDR3_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x49), 0x00FF00FF, DCT1_DDR3_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x4A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80},
-
- // Restore scrubber related registers after restoring training related registers
- {{0, 0, 0}, FUNC_3, 0x44, 0xFFFFFFFE, ANY_DIMM_MASK, ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_3, 0x58, 0x1F1F1F1F, ANY_DIMM_MASK, ANY_DIMM_MASK},
- {{2, 1, 1}, DCT0, BFScrubReDirEn, 0x00000001, ANY_DIMM_MASK, ANY_DIMM_MASK},
-};
-
-CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefDr = {
- 0,
- (sizeof (S3CPciPostSelfDescriptorDr) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
- S3CPciPostSelfDescriptorDr,
- PciSpecialCaseFuncDr
-};
-
-MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorDr[] = {
- {{0, 0, 0}, 0xC0010010, 0x00000000007F07FF},
- {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000},
- {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000},
- {{0, 0, 0}, 0xC001001F, 0xC047F87FFF527FFF}
-};
-
-CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefDr = {
- 0,
- (sizeof (S3MSRPreSelfRefDescriptorDr) / sizeof (MSR_REG_DESCRIPTOR)),
- S3MSRPreSelfRefDescriptorDr,
- NULL
-};
-
-VOID *MemS3RegListDr[] = {
- (VOID *)&S3PciPreSelfRefDr,
- NULL,
- (VOID *)&S3CPciPreSelfRefDr,
- (VOID *)&S3CPciPostSelfRefDr,
- (VOID *)&S3MSRPreSelfRefDr,
- NULL,
- NULL,
- NULL
-};
-
-CONST UINT16 ROMDATA SpecialCasePCIRegDr[] = {
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04)
-};
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the northbridge block for S3 resume
- *
- * @param[in,out] *S3NBPtr - Pointer to MEM_NB_BLOCK.
- * @param[in,out] *MemPtr - Pointer to MEM_DATA_STRUCT.
- * @param[in] NodeID - Node ID of the target node.
- *
- * @return BOOLEAN
- * TRUE - This is the correct constructor for the targeted node.
- * FALSE - This isn't the correct constructor for the targeted node.
- */
-BOOLEAN
-MemS3ResumeConstructNBBlockDr (
- IN OUT VOID *S3NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- )
-{
- INT32 i;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr;
-
- //
- // Determine if this is the expected NB Type
- //
- GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
- if (!MemNIsIdSupportedDr (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
- return FALSE;
- }
-
- NBPtr->MemPtr = MemPtr;
- NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
- NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
- InitNBRegTableDr (NBPtr, NBPtr->NBRegTable);
- NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
- NBPtr->Dct = 0;
- NBPtr->Channel = 0;
- NBPtr->Ganged = FALSE;
- NBPtr->NodeCount = MAX_NODES_SUPPORTED_DR;
- NBPtr->DctCount = MAX_DCTS_PER_NODE_DR;
-
- for (i = 0; i < EnumSize; i++) {
- NBPtr->IsSupported[i] = FALSE;
- }
-
- for (i = 0; i < NumberOfHooks; i++) {
- NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) memDefTrue;
- }
-
- LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader);
-
- NBPtr->IsSupported[CheckDllSpeedUp] = FALSE;
- NBPtr->SwitchDCT = MemNSwitchDCTNb;
- NBPtr->SwitchChannel = MemNSwitchChannelNb;
- NBPtr->GetBitField = MemNGetBitFieldNb;
- NBPtr->SetBitField = MemNSetBitFieldNb;
- NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDr;
- NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedDr;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = MemNS3ExitSelfRefRegDr;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskNb;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK*, DESCRIPTOR_GROUP*)) memDefRet;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeNb;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = MemNS3RestoreScrubNb;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrDr;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstDr;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = (sizeof (SpecialCasePCIRegDr) / sizeof (UINT16)) * sizeof (UINT32);
-
- MemNSwitchDCTNb (NBPtr, 0);
-
- return TRUE;
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------*/
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function returns the register list for each device for DR
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP
- * @return UINT16 - size of the device descriptor on the target node.
- */
-UINT16
-STATIC
-MemNS3GetRegLstPtrDr (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT DESCRIPTOR_GROUP *DescriptPtr
- )
-{
- UINT8 i;
- UINT16 Size;
- Size = 0;
- for (i = PRESELFREF; i <= POSTSELFREF; i ++) {
- DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i);
- DescriptPtr->PCIDevice[i].Node = NBPtr->Node;
- DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF;
- if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListDr[PCI_LST_ESR_DR - PCI_LST_ESR_DR + i] != NULL) {
- DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_DR + i;
- Size += sizeof (PCI_DEVICE_DESCRIPTOR);
- }
- DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i);
- DescriptPtr->CPCIDevice[i].Node = NBPtr->Node;
- DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF;
- if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListDr[CPCI_LST_ESR_DR - PCI_LST_ESR_DR + i] != NULL) {
- DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_DR + i;
- Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR);
- }
- DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i);
- DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF;
- if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListDr[MSR_LST_ESR_DR - PCI_LST_ESR_DR + i] != NULL) {
- DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_DR + i;
- Size += sizeof (MSR_DEVICE_DESCRIPTOR);
- }
- DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i);
- DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF;
- if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListDr[CMSR_LST_ESR_DR - PCI_LST_ESR_DR + i] != NULL) {
- DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_DR + i;
- Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR);
- }
- }
- return Size;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function return the register list according to the register ID.
- *
- * @param[in] RegisterLstID - value of the Register list ID.
- * @param[out] **RegisterHeader - pointer to the address of the register list.
- * @return none
- */
-AGESA_STATUS
-STATIC
-MemNS3GetDeviceRegLstDr (
- IN UINT32 RegisterLstID,
- OUT VOID **RegisterHeader
- )
-{
- if (RegisterLstID >= (sizeof (MemS3RegListDr) / sizeof (VOID *))) {
- ASSERT(FALSE); // RegisterListID exceeded size of Register list
- return AGESA_FATAL;
- }
- if (MemS3RegListDr[RegisterLstID] != NULL) {
- *RegisterHeader = MemS3RegListDr[RegisterLstID];
- return AGESA_SUCCESS;
- }
- ASSERT(FALSE); // Device register list error
- return AGESA_FATAL;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function stores special case register on the heap.
- *
- * @param[in] AccessWidth - Access width of the register
- * @param[in] Address - address of the CSR register in PCI_ADDR format.
- * @param[in] *Value - Pointer to the value be read.
- * @param[in, out] *ConfigPtr - Pointer to Config handle.
- * @return none
- */
-VOID
-STATIC
-MemNS3SetSpecialPCIRegDr (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR Address,
- IN VOID *Value,
- IN OUT VOID *ConfigPtr
- )
-{
- LOCATE_HEAP_PTR LocateBufferPtr;
- UINT8 i;
- UINT8 NodeID;
- UINT8 Offset;
- S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader;
-
- Offset = 0;
- LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
- if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) {
- SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr;
- // Get the node ID of the target die.
- NodeID = (UINT8) (Address.Address.Device - 24);
- for (i = 0; i < MAX_NODES_SUPPORTED_DR; i ++) {
- if (SpecialHeapHeader[i].Node == NodeID) {
- // Get the offset in the heap for the target die.
- Offset = SpecialHeapHeader[i].Offset;
- break;
- }
- }
- ASSERT (i < MAX_NODES_SUPPORTED_DR);
- // Save the value in the heap at appropriate offset based on the index
- // of the target register in the special case array.
- if (Offset != 0) {
- for (i = 0; i < (sizeof (SpecialCasePCIRegDr) / sizeof (UINT16)); i ++) {
- if (SpecialCasePCIRegDr[i] == Address.Address.Register) {
- *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)) = *(UINT32 *) Value;
- }
- }
- }
- }
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function stores special case register on the heap.
- *
- * @param[in,out] *NBPtr - Pointer to the northbridge block.
- * @param[in,out] *StdHeader - Config handle for library and services.
- * @return none
- */
-VOID
-STATIC
-MemNS3ExitSelfRefRegDr (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- LOCATE_HEAP_PTR LocateBufferPtr;
- UINT8 i;
- PCI_ADDR PciAddr;
- UINT32 Value;
- UINT8 NodeID;
- UINT8 Offset;
- S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader;
-
- Offset = 0;
- PciAddr.Address.Device = NBPtr->PciAddr.Address.Device;
- PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus;
- PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment;
- PciAddr.Address.Function = 2;
- LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
- if (HeapLocateBuffer (&LocateBufferPtr, StdHeader) == AGESA_SUCCESS) {
- SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr;
- // Get the node ID of the target die.
- NodeID = (UINT8) (PciAddr.Address.Device - 24);
- for (i = 0; i < MAX_NODES_SUPPORTED_DR; i ++) {
- if (SpecialHeapHeader[i].Node == NodeID) {
- // Get the offset in the heap for the target die.
- Offset = SpecialHeapHeader[i].Offset;
- break;
- }
- }
- ASSERT (i < MAX_NODES_SUPPORTED_DR);
- // Restore the value one by one in the sequence of the special case register array.
- if (Offset != 0) {
- for (i = 0; i < (sizeof (SpecialCasePCIRegDr) / sizeof (UINT16)); i ++) {
- PciAddr.Address.Register = SpecialCasePCIRegDr[i];
- Value = *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2));
- MemNS3SetCSRNb (AccessS3SaveWidth32, PciAddr, &Value, StdHeader);
- }
- }
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mnS3dr.h b/src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mnS3dr.h
deleted file mode 100644
index 0b74ba1..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mnS3dr.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnS3dr.h
- *
- * S3 resume memory related function for DR.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/DR)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MNS3DR_H_
-#define _MNS3DR_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-/// ID for register list of DR
-typedef enum {
- PCI_LST_ESR_DR, ///< Assign 0x0000 for PCI register list for pre exit self refresh.
- PCI_LST_DR, ///< Assign 0x0001 for PCI register list for post exist self refresh.
- CPCI_LST_ESR_DR, ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh.
- CPCI_LST_DR, ///< Assign 0x0003 for conditional PCI register list for post exit self refresh.
- MSR_LST_ESR_DR, ///< Assign 0x0004 for MSR register list for pre exit self refresh.
- MSR_LST_DR, ///< Assign 0x0005 for MSR register list for post exit self refresh.
- CMSR_LST_ESR_DR, ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh.
- CMSR_LST_DR, ///< Assign 0x0007 for conditional MSR register list for post exit self refresh.
-} RegisterListIDDr;
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-#endif //_MNS3DR_H_
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mndctdr.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mndctdr.c
deleted file mode 100644
index f776b5e..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mndctdr.c
+++ /dev/null
@@ -1,515 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mndctdr.c
- *
- * Northbridge DR DCT supporting functions
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/DR)
- * @e \$Revision: 36462 $ @e \$Date: 2010-08-20 00:49:49 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "mport.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mu.h"
-#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB
-#include "mndr.h"
-#include "merrhdl.h"
-#include "OptionMemory.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_DR_MNDCTDR_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define UNUSED_CLK 4
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-VOID
-STATIC
-MemTCtlOnDimmMirrorDr (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN BOOLEAN SetFlag
- );
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function programs the memory controller with configuration parameters
- *
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - An Error value lower than AGESA_FATAL may have occurred
- * @return FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred
- * @return NBPtr->MCTPtr->ErrCode - Contains detailed AGESA_STATUS value
- */
-
-BOOLEAN
-memNAutoConfigDr (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- DIE_STRUCT *MCTPtr;
- DCT_STRUCT *DCTPtr;
- MEM_PARAMETER_STRUCT *RefPtr;
-
- RefPtr = NBPtr->RefPtr;
- MCTPtr = NBPtr->MCTPtr;
- DCTPtr = NBPtr->DCTPtr;
- //======================================================================
- // Build Dram Control Register Value (F2x78)
- //======================================================================
- //
-
- MemNSetBitFieldNb (NBPtr, BFRdPtrInit, 6);
- MemNSetBitFieldNb (NBPtr, BFDataTxFifoWrDly, 0);
-
- MemNSetBitFieldNb (NBPtr, BFEarlyArbEn, 1);
-
- //======================================================================
- // Build Dram Config Lo Register Value
- //======================================================================
- //
-
-
- if (MCTPtr->Status[SbParDimms]) {
- //
- // SbParDimms should be set for all DDR3 RDIMMS or DDR2 that support parity
- // Cannot turn off ParEn for DDR3
- //
- //@attention - add debug option for parity control
- if ((MemNGetBitFieldNb (NBPtr, BFDdr3Mode)!= 0) || (RefPtr->EnableParity)) {
- MemNSetBitFieldNb (NBPtr, BFParEn, 1);
- }
- }
-
- if (MCTPtr->GangedMode) {
- MemNSetBitFieldNb (NBPtr, BFWidth128, 1);
- }
-
- MemNSetBitFieldNb (NBPtr, BFX4Dimm, DCTPtr->Timings.Dimmx4Present & 0xF);
-
- if (!MCTPtr->Status[SbRegistered]) {
- MemNSetBitFieldNb (NBPtr, BFUnBuffDimm, 1);
- }
-
- if (MCTPtr->Status[SbEccDimms]) {
- MemNSetBitFieldNb (NBPtr, BFDimmEccEn, 1);
- }
-
- //======================================================================
- // Build Dram Config Hi Register Value
- //======================================================================
- //
-
- MemNSetBitFieldNb (NBPtr, BFMemClkFreq, MemNGetMemClkFreqIdNb (NBPtr, DCTPtr->Timings.Speed));
-
- if (MCTPtr->Status[SbRegistered]) {
- if (DCTPtr->Timings.Dimmx4Present && DCTPtr->Timings.Dimmx8Present) {
- MemNSetBitFieldNb (NBPtr, BFRDqsEn, 1);
- }
- }
-
- if (RefPtr->EnableBankSwizzle) {
- MemNSetBitFieldNb (NBPtr, BFBankSwizzleMode, 1);
- }
-
- if (DCTPtr->Timings.DimmQrPresent) {
- if (UserOptions.CfgMemoryQuadrankType == QUADRANK_UNBUFFERED) {
- MemNSetBitFieldNb (NBPtr, BFFourRankSoDimm, 1);
- } else if (UserOptions.CfgMemoryQuadrankType == QUADRANK_REGISTERED) {
- MemNSetBitFieldNb (NBPtr, BFFourRankRDimm, 1);
- }
- }
-
- MemNSetBitFieldNb (NBPtr, BFDcqBypassMax, 0xF);
-
- MemNSetBitFieldNb (NBPtr, BFDcqArbBypassEn, 1);
-
- //======================================================================
- // Build Dram Config Misc Register Value
- //======================================================================
- //
- MemNSetBitFieldNb (NBPtr, BFOdtSwizzle, 1);
- // For DDR3 Registered Dimms
- if (MCTPtr->Status[SbRegistered]) {
- if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode)!= 0) {
- MemNSetBitFieldNb (NBPtr, BFSubMemclkRegDly, 1);
- }
- }
- return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This is a general purpose function that executes before DRAM init
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNBeforeDramInitDr (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function sends an MRS command
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNSendMrsCmdDr (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- BOOLEAN ClearODM;
-
- ClearODM = FALSE;
- if ((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_C0) != 0) {
- if (MemNGetBitFieldNb (NBPtr, BFEnDramInit) == 0) {
- // For C0, if EnDramInit bit is cleared, ODM needs to be cleared before sending MRS
- MemTCtlOnDimmMirrorDr (NBPtr, FALSE);
- ClearODM = TRUE;
- }
- }
-
- MemNSwapBitsNb (NBPtr);
-
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tCS%d MR%d %04x\n",
- (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 20) & 0xF,
- (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 16) & 0xF,
- (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) & 0xFFFF));
-
- // 1.Set SendMrsCmd=1
- MemNSetBitFieldNb (NBPtr, BFSendMrsCmd, 1);
-
- // 2.Wait for SendMrsCmd=0
- MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE);
-
- if (ClearODM) {
- // Restore ODM if necessary
- MemTCtlOnDimmMirrorDr (NBPtr, TRUE);
- }
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * Workaround for erratum 322 and 263
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-VOID
-MemNBeforePlatformSpecDr (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- // Errata 263
- if ((NBPtr->DCTPtr->Timings.Speed == DDR533_FREQUENCY) || (NBPtr->DCTPtr->Timings.Speed == DDR667_FREQUENCY)) {
- MemNSetBitFieldNb (NBPtr, BFErr263, 0x0800);
- } else {
- MemNSetBitFieldNb (NBPtr, BFErr263, 0);
- }
-
- // Errata 322
- // 1.Write 00000000h to F2x[1,0]9C_xD08E000
- MemNSetBitFieldNb (NBPtr, BFErr322I, 0);
- // 2.If DRAM Configuration Register[MemClkFreq] (F2x[1,0]94[2:0]) is
- // greater than or equal to 011b (DDR-800 and higher),
- // then write 00000080h to F2x[1,0]9C_xD02E001,
- // else write 00000090h to F2x[1,0]9C_xD02E001.
- MemNSetBitFieldNb (NBPtr, BFErr322II, (NBPtr->DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ? 0x80 : 0x90);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function disables/enables F2x[1, 0][5C:40][OnDimmMirror]
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] SetFlag - Enable or disable flag - TRUE - Enable, FALSE - DISABLE
- *
- */
-
-VOID
-STATIC
-MemTCtlOnDimmMirrorDr (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN BOOLEAN SetFlag
- )
-{
- UINT8 Chipsel;
- UINT32 CSBaseAddrReg;
-
- for (Chipsel = 0; Chipsel < MAX_CS_PER_CHANNEL; Chipsel += 2) {
- CSBaseAddrReg = MemNGetBitFieldNb (NBPtr, BFCSBaseAddr1Reg + Chipsel);
- if ((CSBaseAddrReg & 1) == 1) {
- if (SetFlag && ((NBPtr->DCTPtr->Timings.DimmMirrorPresent & ((UINT8) 1 << (Chipsel >> 1))) != 0)) {
- CSBaseAddrReg |= ((UINT32) 1 << BFOnDimmMirror);
- } else {
- CSBaseAddrReg &= ~((UINT32) 1 << BFOnDimmMirror);
- }
- MemNSetBitFieldNb (NBPtr, BFCSBaseAddr1Reg + Chipsel, CSBaseAddrReg);
- }
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function adjusts Avg PRE value of Phy fence training according to specific CPU family.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *Value16 - Pointer to the value that we want to adjust
- *
- */
-
-VOID
-MemNPFenceAdjustDr (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT UINT16 *Value16
- )
-{
- if ((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_C0) != 0) {
- *Value16 += 5; //for RB C0, the Avg PRE value is subtracted by 3 only.
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function uses calculated values from DCT.Timings structure to
- * program its RB registers.
- *
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNProgramCycTimingsDr (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- CTENTRY DDR3TmgAdjTab[] = {
- // BitField, Min, Max, Bias, Ratio_x2
- {BFTcl, 4, 12, 4, 2},
- {BFTrcd, 5, 12, 5, 2},
- {BFTrp, 5, 12, 5, 2},
- {BFTrtp, 4, 7, 4, 2},
- {BFTras, 15, 30, 15, 2},
- {BFTrc, 11, 42, 11, 2},
- {BFTwrDDR3, 5, 12, 4, 2},
- {BFTrrd, 4, 7, 4, 2},
- {BFTwtr, 4, 7, 4, 2},
- {BFFourActWindow, 16, 32, 14, 1}
- };
-
- CTENTRY DDR2TmgAdjTab[] = {
- // BitField, Min, Max, Bias, Ratio_x2
- {BFTcl, 3, 7, 1, 2},
- {BFTrcd, 3, 6, 3, 2},
- {BFTrp, 3, 6, 3, 4},
- {BFTrtp, 2, 3, 2, 4},
- {BFTras, 5, 18, 3, 2},
- {BFTrc, 11, 26, 11, 2},
- {BFTwr, 3, 6, 3, 2},
- {BFTrrd, 2, 5, 2, 2},
- {BFTwtr, 5, 8, 4, 2},
- {BFFourActWindow, 8, 20, 7, 2}
- };
-
- CTENTRY *TmgAdjTab;
- DCT_STRUCT *DCTPtr;
- UINT8 *MiniMaxTmg;
- UINT8 *MiniMaxTrfc;
- UINT8 Value8;
- UINT8 j;
- UINT8 BurstMode;
- BIT_FIELD_NAME BitField;
-
- DCTPtr = NBPtr->DCTPtr;
-
- //======================================================================
- // Program DRAM Timing values
- //======================================================================
- //
- if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 1) {
- TmgAdjTab = DDR3TmgAdjTab;
- } else if (DCTPtr->Timings.Speed == DDR1066_FREQUENCY) {
- // DDR2-1066 uses DDR3 table but differs in tCL
- TmgAdjTab = DDR3TmgAdjTab;
- TmgAdjTab[0].Min = 3;
- TmgAdjTab[0].Max = 7;
- TmgAdjTab[0].Bias = 1;
- } else {
- TmgAdjTab = DDR2TmgAdjTab;
- }
-
- MiniMaxTmg = &DCTPtr->Timings.CasL;
- for (j = 0; j < GET_SIZE_OF (TmgAdjTab); j++) {
- BitField = TmgAdjTab[j].BitField;
-
- if (MiniMaxTmg[j] < TmgAdjTab[j].Min) {
- MiniMaxTmg[j] = TmgAdjTab[j].Min;
- } else if (MiniMaxTmg[j] > TmgAdjTab[j].Max) {
- MiniMaxTmg[j] = TmgAdjTab[j].Max;
- }
-
- Value8 = (UINT8) MiniMaxTmg[j];
-
- if (BitField == BFTwrDDR3) {
- Value8 = (Value8 == 10) ? 9 : (Value8 == 12) ? 10 : Value8;
- } else if (BitField == BFTrtp) {
- Value8 = (DCTPtr->Timings.Speed <= DDR1066_FREQUENCY) ? 4 : (DCTPtr->Timings.Speed == DDR1333_FREQUENCY) ? 5 : 6;
- }
-
- Value8 = Value8 - TmgAdjTab[j].Bias;
- Value8 = (Value8 * TmgAdjTab[j].Ratio_x2) >> 1;
-
- MemNSetBitFieldNb (NBPtr, BitField, Value8);
- }
-
- MiniMaxTrfc = &DCTPtr->Timings.Trfc0;
- for (j = 0; j < 4; j++) {
- MemNSetBitFieldNb (NBPtr, BFTrfc0 + j, MiniMaxTrfc[j]);
- }
-
- MemNSetBitFieldNb (NBPtr, BFTref, 2); // 7.8 us
-
- if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 1) {
- //======================================================================
- // DDR3 additional settings
- //======================================================================
-
- MemNSetBitFieldNb (NBPtr, BFTcwl, ((DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ?
- (NBPtr->GetMemClkFreqId (NBPtr, DCTPtr->Timings.Speed) - 3) : 0));
-
- MemNSetBitFieldNb (NBPtr, BFNonSPD, 0x28FF);
-
- MemNSetBitFieldNb (NBPtr, BFNonSPDHi, 0x2A);
-
- // DrvImpCtrl: drive impedance control.01b(34 ohm driver; Ron34 = Rzq/7)
- MemNSetBitFieldNb (NBPtr, BFDrvImpCtrl, 1);
-
- // burst length control
- if (NBPtr->MCTPtr->Status[Sb128bitmode]) {
- MemNSetBitFieldNb (NBPtr, BFBurstCtrl, 2);
- }
-
- // ASR=1, auto self refresh; SRT=0
- MemNSetBitFieldNb (NBPtr, BFASR, 1);
- } else {
- //======================================================================
- // DDR2 additional settings
- //======================================================================
-
- MemNSetBitFieldNb (NBPtr, BFNonSPD, 0xFF77);
-
- BurstMode = UserOptions.CfgUseBurstMode;
- IDS_OPTION_HOOK (IDS_BURST_LENGTH32, &BurstMode, &(NBPtr->MemPtr->StdHeader));
- if (BurstMode) {
- if (!NBPtr->MCTPtr->GangedMode) {
- NBPtr->SetBitField (NBPtr, BFBurstLength32, 1);
- }
- }
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mndr.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mndr.c
deleted file mode 100644
index 20925d5..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mndr.c
+++ /dev/null
@@ -1,482 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mndr.c
- *
- * Common Northbridge functions for DR
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/DR)
- * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mndr.h"
-#include "mu.h"
-#include "merrhdl.h"
-#include "S3.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "heapManager.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_DR_MNDR_FILECODE
-
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-#define SPLIT_CHANNEL (UINT32) 0x20000000
-#define CHANNEL_SELECT (UINT32) 0x10000000
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the northbridge block
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
- * @param[in] *FeatPtr - Pointer to the MEM_FEAT_BLOCK_NB
- * @param[in] *SharedPtr - Pointer to the MEM_SHARED_DATA
- * @param[in] NodeID - UINT8 indicating node ID of the NB object.
- *
- * @return Boolean indicating that this is the correct memory
- * controller type for the node number that was passed in.
- */
-
-BOOLEAN
-MemConstructNBBlockDR (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN MEM_FEAT_BLOCK_NB *FeatPtr,
- IN MEM_SHARED_DATA *SharedPtr,
- IN UINT8 NodeID
- )
-{
- UINT8 Dct;
- UINT8 Channel;
- UINT8 SpdSocketIndex;
- UINT8 SpdChannelIndex;
- DIE_STRUCT *MCTPtr;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
- //
- // Determine if this is the expected NB Type
- //
- GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
- if (!MemNIsIdSupportedDr (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
- return FALSE;
- }
-
- NBPtr->MemPtr = MemPtr;
- NBPtr->RefPtr = MemPtr->ParameterListPtr;
- NBPtr->SharedPtr = SharedPtr;
-
- MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
- NBPtr->MCTPtr = MCTPtr;
- NBPtr->MCTPtr->NodeId = NodeID;
- NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue;
- NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
-
- //
- // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
- //
- AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_DR * (
- sizeof (DCT_STRUCT) + (
- MAX_CHANNELS_PER_DCT_DR * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))
- )
- );
- AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0);
- AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
- if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) {
- PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader);
- SetMemError (AGESA_FATAL, MCTPtr);
- ASSERT(FALSE); // Could not allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
- return FALSE;
- }
-
- MCTPtr->DctCount = MAX_DCTS_PER_NODE_DR;
- MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_DR * sizeof (DCT_STRUCT);
- for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DR; Dct++) {
- MCTPtr->DctData[Dct].Dct = Dct;
- MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_DR;
- MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr;
- MCTPtr->DctData[Dct].ChData[0].Dct = Dct;
- AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_DR * sizeof (CH_DEF_STRUCT);
- }
- NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr;
-
- //
- // Initialize Socket List
- //
- for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DR; Dct++) {
- MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr[Dct] = &(MCTPtr->DctData[Dct].ChData[0]);
- MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr[Dct] = &(MCTPtr->DctData[Dct].Timings);
- MCTPtr->DctData[Dct].ChData[0].ChannelID = (MCTPtr->DieId * 2) + Dct;
- }
-
- MemNInitNBDataDr (NBPtr);
-
- FeatPtr->InitCPG (NBPtr);
- NBPtr->FeatPtr = FeatPtr;
- FeatPtr->InitHwRxEn (NBPtr);
- //
- // Calculate SPD Offsets per channel and assign pointers to the data. At this point, we calculate the Node-Dct-Channel
- // centric offsets and store the pointers to the first DIMM of each channel in the Channel Definition struct for that
- // channel. This pointer is then used later to calculate the offsets to be used for each logical dimm once the
- // dimm types(QR or not) are known. This is done in the Technology block constructor.
- //
- // Calculate the SpdSocketIndex separately from the SpdChannelIndex.
- // This will facilitate modifications due to some processors that might
- // map the DCT-CHANNEL differently.
- //
- SpdSocketIndex = GetSpdSocketIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, &MemPtr->StdHeader);
- //
- // Traverse the Dct/Channel structures
- //
- for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DR; Dct++) {
- for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_DR; Channel++) {
- //
- // Calculate the number of Dimms on this channel using the
- // die/dct/channel to Socket/channel conversion.
- //
- SpdChannelIndex = GetSpdChannelIndex (NBPtr->RefPtr->PlatformMemoryConfiguration,
- NBPtr->MCTPtr->SocketId,
- MemNGetSocketRelativeChannelNb (NBPtr, Dct, Channel),
- &MemPtr->StdHeader);
- NBPtr->MCTPtr->DctData[Dct].ChData[Channel].SpdPtr = &(MemPtr->SpdDataStructure[SpdSocketIndex + SpdChannelIndex]);
- }
- }
-
- MemNSwitchDCTNb (NBPtr, 0);
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initializes member functions and variables of NB block.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNInitNBDataDr (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- NBPtr->DctCachePtr = NBPtr->DctCache;
- NBPtr->PsPtr = NBPtr->PSBlock;
-
- InitNBRegTableDr (NBPtr, NBPtr->NBRegTable);
- NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
- NBPtr->Dct = 0;
- NBPtr->Channel = 0;
- NBPtr->DctCount = MAX_DCTS_PER_NODE_DR;
- NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_DR;
- NBPtr->Ganged = FALSE;
- NBPtr->PosTrnPattern = POS_PATTERN_72B;
- NBPtr->MemCleared = FALSE;
- NBPtr->StartupSpeed = DDR800_FREQUENCY;
- NBPtr->RcvrEnDlyLimit = 0xFF;
- NBPtr->NodeCount = MAX_NODES_SUPPORTED_DR;
- NBPtr->DefDctSelIntLvAddr = 3;
-
- LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader);
-
- NBPtr->SetMaxLatency = MemNSetMaxLatencyNb;
- NBPtr->getMaxLatParams = MemNGetMaxLatParamsNb;
- NBPtr->InitializeMCT = MemNInitializeMctDr;
- NBPtr->FinalizeMCT = MemNFinalizeMctDr;
- NBPtr->SendMrsCmd = MemNSendMrsCmdDr;
- NBPtr->sendZQCmd = MemNSendZQCmdNb;
- NBPtr->WritePattern = MemNWritePatternDr;
- NBPtr->ReadPattern = MemNReadPatternDr;
- NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet;
- NBPtr->CompareTestPattern = MemNCompareTestPatternNb;
- NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb;
- NBPtr->StitchMemory = MemNStitchMemoryNb;
- NBPtr->AutoConfig = memNAutoConfigDr;
- NBPtr->PlatformSpec = MemNPlatformSpecNb;
- NBPtr->InitMCT = MemNInitMCTNb;
- NBPtr->DisableDCT = MemNDisableDCTNb;
- NBPtr->StartupDCT = MemNStartupDCTNb;
- NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb;
- NBPtr->ChangeFrequency = MemNChangeFrequencyNb;
- NBPtr->RampUpFrequency = MemNRampUpFrequencyNb;
- NBPtr->ChangeNbFrequency = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefFalse;
- NBPtr->ProgramCycTimings = MemNProgramCycTimingsDr;
- NBPtr->SyncDctsReady = MemNSyncDctsReadyNb;
- NBPtr->HtMemMapInit = MemNHtMemMapInitNb;
- NBPtr->SyncAddrMapToAllNodes = MemNSyncAddrMapToAllNodesNb;
- NBPtr->CpuMemTyping = MemNCPUMemTypingNb;
- NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingNb;
- NBPtr->AfterDqsTraining = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
- NBPtr->OtherTiming = (BOOLEAN (*) (MEM_NB_BLOCK *)) MemMDefRet; //@attention - due to build issue with MemNOtherTimingDr
- NBPtr->UMAMemTyping = MemNUMAMemTypingNb;
- NBPtr->TechBlockSwitch = MemNTechBlockSwitchNb;
- NBPtr->SetEccSymbolSize = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
- NBPtr->TrainingFlow = MemNTrainingFlowNb;
- NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb;
- MemNInitNBDataNb (NBPtr);
- NBPtr->PollBitField = MemNPollBitFieldNb;
- NBPtr->BrdcstCheck = MemNBrdcstCheckNb;
- NBPtr->BrdcstSet = MemNBrdcstSetNb;
- NBPtr->GetTrainDly = MemNGetTrainDlyNb;
- NBPtr->SetTrainDly = MemNSetTrainDlyNb;
- NBPtr->PhyFenceTraining = MemNPhyFenceTrainingNb;
- NBPtr->GetSysAddr = MemNGetMCTSysAddrNb;
- NBPtr->RankEnabled = MemNRankEnabledNb;
- NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb;
- NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitDr;
- NBPtr->MemNBeforePlatformSpecNb = MemNBeforePlatformSpecDr;
- NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyNb;
- NBPtr->MemPPhyFenceTrainingNb = MemPPhyFenceTrainingDr;
- NBPtr->MemPNodeMemBoundaryNb = MemPNodeMemBoundaryDr;
- NBPtr->MemNInitPhyComp = MemNInitPhyCompNb;
- NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDr;
- NBPtr->MemNBeforeDramInitNb = MemNBeforeDramInitDr;
- NBPtr->MemNPFenceAdjustNb = MemNPFenceAdjustDr;
- NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsNb;
- NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb;
- NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb;
- NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb;
- NBPtr->CSPerChannel = MemNCSPerChannelNb;
- NBPtr->CSPerDelay = MemNCSPerDelayNb;
- NBPtr->FlushPattern = MemNFlushPatternNb;
- NBPtr->MemNCapSpeedBatteryLife = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
- NBPtr->GetUmaSize = MemNGetUmaSizeNb;
- NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdNb;
- NBPtr->EnableSwapIntlvRgn = (VOID (*) (MEM_NB_BLOCK *, UINT32, UINT32)) memDefRet;
- NBPtr->WaitXMemClks = MemNWaitXMemClksNb;
- NBPtr->MemNGetDramTerm = MemNGetDramTermNb;
- NBPtr->MemNGetDynDramTerm = MemNGetDynDramTermNb;
- NBPtr->MemNGetMR0CL = MemNGetMR0CLNb;
- NBPtr->MemNGetMR0WR = MemNGetMR0WRNb;
- NBPtr->MemNGetMR2CWL = MemNGetMR2CWLNb;
- NBPtr->AllocateC6Storage = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
-
- NBPtr->IsSupported[SetSpareEn] = TRUE;
- NBPtr->IsSupported[CheckSpareEn] = TRUE;
- NBPtr->IsSupported[DimmBasedOnSpeed] = TRUE;
- NBPtr->IsSupported[CheckMaxDramRate] = TRUE;
- NBPtr->IsSupported[Check1GAlign] = TRUE;
- NBPtr->IsSupported[CheckMaxRdDqsDlyPtr] = TRUE;
- NBPtr->IsSupported[CheckGetMCTSysAddr] = TRUE;
- NBPtr->IsSupported[CheckFindPSOverideWithSocket] = TRUE;
- NBPtr->IsSupported[CheckSlewWithMarginImprv] = TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the default values in the MEM_DATA_STRUCT
- *
- * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
- *
- */
-VOID
-MemNInitDefaultsDR (
- IN OUT MEM_DATA_STRUCT *MemPtr
- )
-{
- UINT8 Socket;
- UINT8 Channel;
- MEM_PARAMETER_STRUCT *RefPtr;
- ASSERT (MemPtr != NULL);
- RefPtr = MemPtr->ParameterListPtr;
-
- // Memory Map/Mgt.
- // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB
- RefPtr->BottomIo = 0xE0;
- RefPtr->UmaMode = UserOptions.CfgUmaMode;
- RefPtr->UmaSize = UserOptions.CfgUmaSize;
- RefPtr->MemHoleRemapping = TRUE;
- //
-
-
- // Dram Timing
- RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect;
- RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect;
- for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) {
- for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) {
- MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL;
- MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL;
- }
- }
-
- // Memory Clear
- RefPtr->EnableMemClr = TRUE;
-
- // TableBasedAlterations
- RefPtr->TableBasedAlterations = NULL;
-
- // Platform config table
- RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration;
-
- // Memory Restore
- RefPtr->MemRestoreCtl = FALSE;
- RefPtr->SaveMemContextCtl = FALSE;
- AmdS3ParamsInitializer (&RefPtr->MemContext);
-
- // Dram Configuration
- RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving;
- RefPtr->EnableNodeIntlv = UserOptions.CfgMemoryEnableNodeInterleaving;
- RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving;
- RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle;
- RefPtr->EnableParity = UserOptions.CfgMemoryParityEnable;
- RefPtr->EnableOnLineSpareCtl = UserOptions.CfgOnlineSpare;
-
- // Dram Power
- RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown;
-
- // ECC
- RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- *
- * This function writes training pattern
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Pattern[] - Pattern to write
- * @param[in] Address - System Address [47:16]
- * @param[in] ClCount - Number of cache lines
- *
- */
-
-VOID
-MemNWritePatternDr (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 Address,
- IN UINT8 Pattern[],
- IN UINT16 ClCount
- )
-{
- Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
- MemUWriteCachelines (Address, Pattern, ClCount);
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- *
- * This function reads training pattern
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Buffer[] - Buffer to fill
- * @param[in] Address - System Address [47:16]
- * @param[in] ClCount - Number of cache lines
- *
- */
-
-VOID
-MemNReadPatternDr (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Buffer[],
- IN UINT32 Address,
- IN UINT16 ClCount
- )
-{
- Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
- MemUReadCachelines (Buffer, Address, ClCount);
-}
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initiates DQS training for Server NB
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-BOOLEAN
-memNEnableTrainSequenceDr (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- BOOLEAN Retval;
- Retval = TRUE;
- if (!MemNIsIdSupportedDr (NBPtr, &(NBPtr->MemPtr->DiesPerSystem[NBPtr->MCTPtr->NodeId].LogicalCpuid))) {
- Retval = FALSE;
- }
- return Retval;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mndr.h b/src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mndr.h
deleted file mode 100644
index 5e837cc..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mndr.h
+++ /dev/null
@@ -1,199 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mndr.h
- *
- * Northbridge DR
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem)
- * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MNDR_H_
-#define _MNDR_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-#define MAX_CHANNELS_PER_SOCKET_DR 2
-#define MAX_DCTS_PER_NODE_DR 2
-#define MAX_CHANNELS_PER_DCT_DR 1
-#define MAX_NODES_SUPPORTED_DR 8
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-MemConstructNBBlockDR (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN MEM_FEAT_BLOCK_NB *FeatPtr,
- IN MEM_SHARED_DATA *SharedPtr,
- IN UINT8 NodeID
- );
-
-VOID
-MemNInitNBDataDr (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNInitDefaultsDR (
- IN OUT MEM_DATA_STRUCT *MemPtr
- );
-
-BOOLEAN
-MemNInitializeMctDr (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNFinalizeMctDr (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNSendMrsCmdDr (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-memNAutoConfigDr (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNOtherTimingDr (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNWritePatternDr (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 Address,
- IN UINT8 Pattern[],
- IN UINT16 ClCount
- );
-
-VOID
-MemNReadPatternDr (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Buffer[],
- IN UINT32 Address,
- IN UINT16 ClCount
- );
-
-VOID
-MemPNodeMemBoundaryDr (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT UINT32 *NodeSysLimit
- );
-
-VOID
-InitNBRegTableDr (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT TSEFO NBRegTable[]
- );
-
-BOOLEAN
-MemNIsIdSupportedDr (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN CPU_LOGICAL_ID *LogicalIdPtr
- );
-
-VOID
-MemNBeforeDramInitDr (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNBeforePlatformSpecDr (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNPlatformSpecificFormFactorInitDr (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemPPhyFenceTrainingDr (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-UINT32
-MemNCmnGetSetFieldDr (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN BIT_FIELD_NAME FieldName,
- IN UINT32 Field
- );
-
-VOID
-MemNPFenceAdjustDr (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT UINT16 *Value16
- );
-
-VOID
-MemNProgramCycTimingsDr (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-memNEnableTrainSequenceDr (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-#endif /* _MNDR_H_ */
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mnflowdr.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mnflowdr.c
deleted file mode 100644
index 8c3a9aa..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mnflowdr.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnflowdr.c
- *
- * Deerhound initializer for MCT and DCT
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Main)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mndr.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_DR_MNFLOWDR_FILECODE
-/* features */
-#include "mftds.h"
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDR[MAX_FF_TYPES];
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the platform specific block
- *
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - AGESA_SUCCESS at least one dorm factor was found
- * @return FALSE - AGESA_UNSUPPORTED - Error indicating that no form factors were found
- */
-
-BOOLEAN
-MemNPlatformSpecificFormFactorInitDr (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 Dct;
- UINT8 f;
- UINT8 ErrUnSuppFFCount;
- for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DR; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- if (NBPtr->ChannelPtr->ChDimmValid != 0) {
- ErrUnSuppFFCount = 0;
- for (f = 0; f < MAX_FF_TYPES; f++) {
- ASSERT (memPlatSpecFFInstalledDR[f] != NULL);
- if (memPlatSpecFFInstalledDR[f] (NBPtr->MemPtr, NBPtr->ChannelPtr, NBPtr->PsPtr) == AGESA_UNSUPPORTED) {
- ErrUnSuppFFCount++; //Count the number of AGESA_UNSUPPORTED errors
- } else {
- break;
- }
- }
- if (ErrUnSuppFFCount == MAX_FF_TYPES) {
- return FALSE; // No FF types are supported
- }
- }
- }
- return TRUE;
-}
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mnidendimmdr.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mnidendimmdr.c
deleted file mode 100644
index 440da5a..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mnidendimmdr.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnidendimmdr.c
- *
- * DR northbridge constructor for dimm identification translator.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/DR)
- * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "mm.h"
-#include "mn.h"
-#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB
-#include "mndr.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_NB_DR_MNIDENDIMMDR_FILECODE
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the northbridge block for dimm identification translator
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
- * @param[in,out] NodeID - ID of current node to construct
- * @return TRUE - This is the correct constructor for the targeted node.
- * @return FALSE - This isn't the correct constructor for the targeted node.
- *
- */
-
-BOOLEAN
-MemNIdentifyDimmConstructorDr (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- )
-{
- //
- // Determine if this is the expected NB Type
- //
- GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
- if (!MemNIsIdSupportedDr (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
- return FALSE;
- }
-
- NBPtr->NodeCount = MAX_NODES_SUPPORTED_DR;
- NBPtr->DctCount = MAX_DCTS_PER_NODE_DR;
- NBPtr->MemPtr = MemPtr;
- NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
- NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
- NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
- NBPtr->Ganged = FALSE;
- InitNBRegTableDr (NBPtr, NBPtr->NBRegTable);
- NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDr;
- NBPtr->SetBitField = MemNSetBitFieldNb;
- NBPtr->GetBitField = MemNGetBitFieldNb;
- NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb;
-
- return TRUE;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mnmctdr.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mnmctdr.c
deleted file mode 100644
index e42fa23..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mnmctdr.c
+++ /dev/null
@@ -1,186 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnmctdr.c
- *
- * Northbridge DR MCT supporting functions
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/DR)
- * @e \$Revision: 36462 $ @e \$Date: 2010-08-20 00:49:49 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mport.h"
-#include "mm.h"
-#include "mn.h"
-#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB
-#include "mndr.h"
-#include "mu.h"
-#include "OptionMemory.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_DR_MNMCTDR_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function sets final values in BUCFG and BUCFG2
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemNFinalizeMctDr (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MEM_DATA_STRUCT *MemPtr;
- S_UINT64 SMsr;
-
- MemPtr = NBPtr->MemPtr;
-
- MemNSetBitFieldNb (NBPtr, BFAdapPrefMissRatio, 1);
- MemNSetBitFieldNb (NBPtr, BFAdapPrefPosStep, 0);
- MemNSetBitFieldNb (NBPtr, BFAdapPrefNegStep, 0);
- MemNSetBitFieldNb (NBPtr, BFCohPrefPrbLmt, 1);
- // Recommended settings for F2x11C
- MemNSetBitFieldNb (NBPtr, BFMctWrLimit, 16);
- MemNSetBitFieldNb (NBPtr, BFPrefCpuDis, 0);
- MemNSetBitFieldNb (NBPtr, BFPrefIoDis, 0);
- MemNSetBitFieldNb (NBPtr, BFFlushWrOnStpGnt, 1);
-
- if (NBPtr->Node == BSP_DIE) {
- if (!NBPtr->ClToNbFlag) {
- LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- SMsr.lo &= ~((UINT32)1 << 15); // ClLinesToNbDis
- LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- }
-
- LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- SMsr.hi &= ~((UINT32)1 << (48 - 32)); // WbEnhWsbDis
- LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- }
-
- return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function sets initial values in BUCFG and BUCFG2
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemNInitializeMctDr (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MEM_DATA_STRUCT *MemPtr;
- S_UINT64 SMsr;
-
- MemPtr = NBPtr->MemPtr;
-
- if (NBPtr->Node == BSP_DIE) {
- LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- if (SMsr.lo & ((UINT32)1 << 15)) {
- NBPtr->ClToNbFlag = 1;
- }
- SMsr.lo |= (UINT32)1 << 15; // ClLinesToNbDis
- LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-
- LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- SMsr.hi |= (UINT32)1 << (48 - 32); // WbEnhWsbDis
- LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- }
- return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mnotdr.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mnotdr.c
deleted file mode 100644
index d8ee691..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mnotdr.c
+++ /dev/null
@@ -1,200 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnotdr.c
- *
- * Northbridge Non-SPD timings for DR
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/DR)
- * @e \$Revision: 36462 $ @e \$Date: 2010-08-20 00:49:49 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB
-#include "mndr.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_DR_MNOTDR_FILECODE
-
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-VOID
-STATIC
-MemNSetOtherTimingDR (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-STATIC
-MemNPowerDownCtlDR (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function sets the non-SPD timings
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemNOtherTimingDr (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
-
- MemNSwitchDCTNb (NBPtr, 0);
- if (NBPtr->DCTPtr->Timings.DctDimmValid > 0) {
- MemNSetOtherTimingDR (NBPtr); // Set DR Timings
- MemNPowerDownCtlNb (NBPtr);
- }
-
- MemNSwitchDCTNb (NBPtr, 1);
- if ((NBPtr->DCTPtr->Timings.DctDimmValid > 0) && (NBPtr->MCTPtr->GangedMode == FALSE)) {
- MemNSetOtherTimingDR (NBPtr); // Set DR Timings
- MemNPowerDownCtlNb (NBPtr);
- }
- return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function sets the non-SPD timings into the PCI registers
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-STATIC
-MemNSetOtherTimingDR (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MemNSetBitFieldNb (NBPtr, BFTrdrd, MemNGetTrdrdNb (NBPtr));
- MemNSetBitFieldNb (NBPtr, BFTwrwr, MemNGetTwrwrNb (NBPtr));
- MemNSetBitFieldNb (NBPtr, BFTwrrd, MemNGetTwrrdNb (NBPtr));
- MemNSetBitFieldNb (NBPtr, BFTrwtTO, MemNGetTrwtTONb (NBPtr));
- MemNSetBitFieldNb (NBPtr, BFTrwtWB, MemNGetTrwtWBNb (NBPtr));
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function enables power down mode
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-STATIC
-MemNPowerDownCtlDR (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MEM_PARAMETER_STRUCT *RefPtr;
- UINT8 PowerDownMode;
-
- RefPtr = NBPtr->RefPtr;
-
- // we can't enable powerdown mode when doing WL
- if (RefPtr->EnablePowerDown) {
- MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 1);
- PowerDownMode = (UINT8) UserOptions.CfgPowerDownMode;
- IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader));
- if (PowerDownMode) {
- MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1);
- }
- }
-}
-
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mnprotodr.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mnprotodr.c
deleted file mode 100644
index b30d604..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mnprotodr.c
+++ /dev/null
@@ -1,170 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnprotodr.c
- *
- * Northbridge support functions for Errata and early samples
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/DR)
- * @e \$Revision: 36462 $ @e \$Date: 2010-08-20 00:49:49 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-
-#include "AGESA.h"
-#include "mport.h"
-#include "mm.h"
-#include "mn.h"
-#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB
-#include "mndr.h"
-#include "cpuFamRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_DR_MNPROTODR_FILECODE
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-VOID
-STATIC
-MemNTrainFenceWHardCodeValDr (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function conditionally executes specific Phy fence training function.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemPPhyFenceTrainingDr (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- if (NBPtr->GetBitField (NBPtr, BFDdr3Mode) == 0) {
- //DDR2 specific.
- if (NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_C0) {
- MemNTrainFenceWHardCodeValDr (NBPtr);
- } else {
- MemNTrainPhyFenceNb (NBPtr);
- }
- } else {
- //DDR3 specific.
- MemNTrainPhyFenceNb (NBPtr);
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function executes hardcoded Phy fence training.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-STATIC
-MemNTrainFenceWHardCodeValDr (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 Dct;
- UINT8 CurDct;
- UINT16 Speed;
-
- CurDct = NBPtr->Dct;
- if (NBPtr->MCTPtr->NodeMemSize) {
- for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DR; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- Speed = NBPtr->DCTPtr->Timings.Speed;
- NBPtr->SetBitField (NBPtr, BFPhyFence, ((Speed == DDR800_FREQUENCY) || (Speed == DDR1066_FREQUENCY)) ? 20 : 20);
- NBPtr->SetBitField (NBPtr, BFSlowAccessMode, (NBPtr->ChannelPtr->SlowMode) ? 1 : 0);
- NBPtr->SetBitField (NBPtr, BFODCControl, NBPtr->ChannelPtr->DctOdcCtl);
- NBPtr->SetBitField (NBPtr, BFAddrTmgControl, NBPtr->ChannelPtr->DctAddrTmg);
- }
- }
-
- NBPtr->SwitchDCT (NBPtr, CurDct);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function executes Node memory 1GB boundary alignment.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *NodeSysLimit - Pointer to the NodeSysLimit
- *
- */
-
-VOID
-MemPNodeMemBoundaryDr (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT UINT32 *NodeSysLimit
- )
-{
- if (NBPtr->GetBitField (NBPtr, BFDdr3Mode) == 0) {
- // only apply to DDR2.
- if (*NodeSysLimit > ((UINT32)1 << (30 - 16))) {
- // if (NodeSysLimit > 1GB) then set to Node limit to 1GB boundary for each node
- *NodeSysLimit += 1;
- *NodeSysLimit &= 0xFFFFC000;
- *NodeSysLimit -= 1;
- }
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mnregdr.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mnregdr.c
deleted file mode 100644
index 056c317..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/DR/mnregdr.c
+++ /dev/null
@@ -1,548 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnregdr.c
- *
- * Common Northbridge register related functions for DR
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/DR)
- * @e \$Revision: 38303 $ @e \$Date: 2010-09-22 00:22:47 +0800 (Wed, 22 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mndr.h"
-#include "merrhdl.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_DR_MNREGDR_FILECODE
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------*/
-/**
- * MemNIsIdSupportedDr
- * This function matches the CPU_LOGICAL_ID with certain criteria to
- * determine if it is supported by this NBBlock.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID
- *
- * @return TRUE - This node is a RB.
- * @return FALSE - This node is not a RB.
- *
- */
-BOOLEAN
-MemNIsIdSupportedDr (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN CPU_LOGICAL_ID *LogicalIdPtr
- )
-{
-
- if (((LogicalIdPtr->Family & (AMD_FAMILY_10_RB | AMD_FAMILY_10_BL | AMD_FAMILY_10_DA)) != 0)
- && ((LogicalIdPtr->Revision & (AMD_F10_RB_ALL | AMD_F10_BL_ALL | AMD_F10_DA_ALL)) != 0)) {
- return TRUE;
- } else {
- return FALSE;
- }
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------*/
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function gets or sets a value to a bit field in a PCI register.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] FieldName - Bit Field to be programmed
- * @param[in] Field - Value to be programmed
- * @param[in] IsSet - Indicates if the function will set or get
- *
- * @return value read, if the function is used as a "get"
- */
-
-UINT32
-MemNCmnGetSetFieldDr (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN BIT_FIELD_NAME FieldName,
- IN UINT32 Field
- )
-{
- TSEFO Address;
- PCI_ADDR PciAddr;
- UINT8 Type;
- UINT8 IsLinked;
- UINT32 Value;
- UINT32 Highbit;
- UINT32 Lowbit;
- UINT32 Mask;
-
- Value = 0;
- if ((FieldName < BFEndOfList) && (FieldName >= 0)) {
- Address = NBPtr->NBRegTable[FieldName];
- if (Address) {
- Lowbit = TSEFO_END (Address);
- Highbit = TSEFO_START (Address);
- Type = (UINT8) TSEFO_TYPE (Address);
- IsLinked = (UINT8) TSEFO_LINKED (Address);
-
- // If Fn2 and DCT1 selected, set Address to be 1xx
- if ((Type == NB_ACCESS) && ((Address & 0xF000) == 0x2000) && NBPtr->Dct) {
- if (!NBPtr->Ganged || (Address & 0xFF) == 0x98 || (Address & 0xFF) == 0x9C) {
- Address |= 0x0100;
- }
- }
-
- ASSERT ((Address & ((UINT32) 1) << 28) == 0); // Phy direct access method is not supported
-
- if ((Address >> 29) == ((DCT_PHY_ACCESS << 1) | 1)) {
- // Special DCT Phy access
- Address &= 0x0FFFFFFF;
- Lowbit = 0;
- Highbit = 16;
- IsLinked = 0;
- } else {
- // Normal DCT Phy access
- Address = TSEFO_OFFSET (Address);
- }
-
- if (Type == NB_ACCESS) {
- PciAddr.AddressValue = Address;
- PciAddr.Address.Device = NBPtr->PciAddr.Address.Device;
- PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus;
- PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment;
- Address = PciAddr.AddressValue;
- LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
- if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) &&
- (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) {
- IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Value);
- }
- } else if (Type == DCT_PHY_ACCESS) {
- MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
- MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
- Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
- IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%d9C_%x = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Value);
- } else {
- IDS_ERROR_TRAP;
- }
-
- if (IsSet) {
- // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
- if ((Highbit - Lowbit) != 31) {
- Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
- } else {
- Mask = (UINT32)0xFFFFFFFF;
- }
- Value &= ~(Mask << Lowbit);
- Value |= (Field & Mask) << Lowbit;
-
- if (Type == NB_ACCESS) {
- PciAddr.AddressValue = Address;
- LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
- if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) &&
- (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) {
- IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Highbit, Lowbit, Field);
- }
- } else if (Type == DCT_PHY_ACCESS) {
- MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
- Address |= DCT_ACCESS_WRITE;
- MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
- MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
- IDS_HDT_CONSOLE (MEM_SETREG, "~Fn2_%d9C_%x [%d:%d] = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Highbit, Lowbit, Field);
- } else {
- IDS_ERROR_TRAP;
- }
- if (IsLinked) {
- MemNCmnGetSetFieldDr (NBPtr, 1, FieldName + 1, Field >> (Highbit - Lowbit + 1));
- }
- } else {
- Value = Value >> Lowbit; // Shift
- // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
- if ((Highbit - Lowbit) != 31) {
- Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
- }
- if (IsLinked) {
- Value |= MemNCmnGetSetFieldDr (NBPtr, 0, FieldName + 1, 0) << (Highbit - Lowbit + 1);
- }
- }
- }
- } else {
- IDS_ERROR_TRAP; // Invalid bit field index
- }
- return Value;
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes bit field translation table
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] NBRegTable[] - Pointer to the bit field data structure
- *
- */
-
-VOID
-InitNBRegTableDr (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT TSEFO NBRegTable[]
- )
-{
- UINT16 i;
- for (i = 0; i < BFEndOfList; i++) {
- NBRegTable[i] = 0;
- }
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31, 0, BFDevVendorIDReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60), 2, 0, BFNodeID);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60), 6, 4, BFNodeCnt);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x48), 31, 0, BFDramBaseReg1);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x4C), 31, 0, BFDramLimitReg1);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x50), 31, 0, BFDramBaseReg2);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x54), 31, 0, BFDramLimitReg2);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x58), 31, 0, BFDramBaseReg3);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x5C), 31, 0, BFDramLimitReg3);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x60), 31, 0, BFDramBaseReg4);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x64), 31, 0, BFDramLimitReg4);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x68), 31, 0, BFDramBaseReg5);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x6C), 31, 0, BFDramLimitReg5);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x70), 31, 0, BFDramBaseReg6);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x74), 31, 0, BFDramLimitReg6);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x78), 31, 0, BFDramBaseReg7);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x7C), 31, 0, BFDramLimitReg7);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 0, BFDramHoleAddrReg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x140), 7, 0, BFDramBaseHiReg0);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x144), 7, 0, BFDramLimitHiReg0);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x148), 7, 0, BFDramBaseHiReg1);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x14C), 7, 0, BFDramLimitHiReg1);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x150), 7, 0, BFDramBaseHiReg2);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x154), 7, 0, BFDramLimitHiReg2);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x158), 7, 0, BFDramBaseHiReg3);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x15C), 7, 0, BFDramLimitHiReg3);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x160), 7, 0, BFDramBaseHiReg4);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x164), 7, 0, BFDramLimitHiReg4);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x168), 7, 0, BFDramBaseHiReg5);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x16C), 7, 0, BFDramLimitHiReg5);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x170), 7, 0, BFDramBaseHiReg6);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x174), 7, 0, BFDramLimitHiReg6);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x178), 7, 0, BFDramBaseHiReg7);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x17C), 7, 0, BFDramLimitHiReg7);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 24, BFDramHoleBase);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 15, 7, BFDramHoleOffset);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 1, 1, BFDramMemHoistValid);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 0, 0, BFDramHoleValid);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 20, 0, BFDramBaseAddr);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 23, 21, BFDramIntlvSel);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 20, 0, BFDramLimitAddr);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 26, 21, BFDramIntlvEn);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31, 0, BFCSBaseAddr0Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31, 0, BFCSBaseAddr1Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31, 0, BFCSBaseAddr2Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31, 0, BFCSBaseAddr3Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x50), 31, 0, BFCSBaseAddr4Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x54), 31, 0, BFCSBaseAddr5Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x58), 31, 0, BFCSBaseAddr6Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x5C), 31, 0, BFCSBaseAddr7Reg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31, 0, BFCSMask0Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31, 0, BFCSMask1Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x68), 31, 0, BFCSMask2Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x6C), 31, 0, BFCSMask3Reg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 0, BFDramControlReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 0, BFDramInitRegReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31, 0, BFDramBankAddrReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31, 0, BFDramMRSReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 0, BFDramTimingLoReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 0, BFDramTimingHiReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31, 0, BFDramConfigLoReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 0, BFDramConfigHiReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 0, BFDctAddlOffsetReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31, 0, BFDctAddlDataReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 31, BFDctAccessDone);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA0), 31, 0, BFDramConfigMiscReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 31, 0, BFDramCtrlMiscReg2);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF4), 31, 0, BFDctExtraDataReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 31, 0, BFMctCfgHiReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 31, 0, BFMctCfgLoReg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x40), 31, 0, BFMcaNbCtlReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44), 22, 22, BFDramEccEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44), 2, 2, BFSyncOnUcEccEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x180), 25, 25, BFEccSymbolSize);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x48), 31, 0, BFMcaNbStatusLoReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x4C), 31, 0, BFMcaNbStatusHiReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 4, 0, BFDramScrub);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 12, 8, BFL2Scrub);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 20, 16, BFDcacheScrub);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 28, 24, BFL3Scrub);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C), 0, 0, BFScrubReDirEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C), 31, 0, BFScrubAddrLoReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x60), 31, 0, BFScrubAddrHiReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x84), 31, 29, BFC1ClkDivisor);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x8C), 4, 4, BFDisDatMsk);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4), 4, 0, BFNbFid);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 25, 25, BFL3Capable);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x188), 8, 8, BFDisableL3);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 8, BFNonSPDHi);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 3, 0, BFRdPtrInit);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 9, 8, BFTwrrdHi);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 11, 10, BFTwrwrHi);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 12, BFTrdrdHi);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 16, 16, BFAltVidC3MemClkTriEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 18, 18, BFDqsRcvEnTrain);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 19, 19, BFEarlyArbEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15, 0, BFMrsAddress);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 18, 16, BFMrsBank);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 22, 20, BFMrsChipSel);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 24, 24, BFSendPchgAll);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 25, 25, BFSendAutoRefresh);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 30, 30, BFSendCtrlWord);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 7, 7, BFMrsLevel);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 12, 12, BFMrsQoff);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 1, 0, BFBurstCtrl);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 3, 2, BFDrvImpCtrl);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 9, 7, BFDramTerm_DDR3);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 11, 10, BFDramTermDyn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 13, 13, BFQoff);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 18, 18, BFASR);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 19, 19, BFSRT);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 22, 20, BFTcwl);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 23, 23, BFPchgPDModeSel);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 6, 4, BFTwrDDR3);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 3, 0, BFTcl);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 6, 4, BFTrcd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 9, 7, BFTrp);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 11, 10, BFTrtp);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 15, 12, BFTras);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 20, 16, BFTrc);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 21, 20, BFTwr);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 23, 22, BFTrrd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 24, BFMemClkDis);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 0, BFNonSPD);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 3, 0, BFTrwtWB);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 7, 4, BFTrwtTO);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 9, 8, BFTwtr);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 11, 10, BFTwrrd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 13, 12, BFTwrwr);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 14, BFTrdrd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 17, 16, BFTref);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 22, 20, BFTrfc0);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 25, 23, BFTrfc1);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 28, 26, BFTrfc2);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 29, BFTrfc3);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 0, 0, BFInitDram);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 1, 1, BFExitSelfRef);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 5, 4, BFDramTerm);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 8, 8, BFParEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 10, 10, BFBurstLength32);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 11, 11, BFWidth128);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 15, 12, BFX4Dimm);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 16, 16, BFUnBuffDimm);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 17, 17, BFEnterSelfRef);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 19, 19, BFDimmEccEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 21, 21, BFFreqChgInProg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 23, 23, BFForceAutoPchg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 2, 0, BFMemClkFreq);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 3, 3, BFMemClkFreqVal);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 8, 8, BFDdr3Mode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 9, 9, BFLegacyBiosMode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 12, 12, BFRDqsEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 15, 15, BFPowerDownEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 16, 16, BFPowerDownMode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 17, 17, BFFourRankSoDimm);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 19, 19, BFDcqArbBypassEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 18, 18, BFFourRankRDimm);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 20, 20, BFSlowAccessMode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 22, 22, BFBankSwizzleMode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 27, 24, BFDcqBypassMax);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 28, BFFourActWindow);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 8, 8, BFODTSEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 14, 12, BFCmdThrottleMode);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 2, 2, BFDdr3FourSocketCh);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 5, 5, BFSubMemclkRegDly);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 6, 6, BFOdtSwizzle);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 15, 8, BFCtrlWordCS);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 18, 16, BFDataTxFifoWrDly);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 0, 0, BFDctSelHiRngEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 1, 1, BFDctSelHi);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 2, 2, BFDctSelIntLvEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 3, 3, BFMemClrInit);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 4, 4, BFDctGangEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 5, 5, BFDctDatIntLv);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 7, 6, BFDctSelIntLvAddr);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 8, 8, BFDramEnabled);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 9, 9, BFMemClrBusy);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 10, 10, BFMemCleared);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 31, 11, BFDctSelBaseAddr);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 31, 10, BFDctSelBaseOffset);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 1, 0, BFDctWrLimit);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 6, 2, BFMctWrLimit);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 11, 7, BFMctPrefReqLimit);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 12, 12, BFPrefCpuDis);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 13, 13, BFPrefIoDis);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 28, 28, BFPrefDramTrainMode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 30, 30, BFFlushWr);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 29, 29, BFFlushWrOnStpGnt);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 1, 0, BFAdapPrefMissRatio);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 3, 2, BFAdapPrefPosStep);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 5, 4, BFAdapPrefNegStep);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 10, 8, BFCohPrefPrbLmt);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xB0), 31, 0, BFOnLineSpareControl);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 7, 5, BFDdrMaxRate);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 9, 8, BFAddrCmdDrvStren);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 17, 16, BFDataDrvStren);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31, 0, BFODCControl);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31, 0, BFAddrTmgControl);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 0, 0, BFWrtLvTrEn);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 1, 1, BFWrtLvTrMode);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 3, 3, BFPhyFenceTrEn);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 5, 4, BFTrDimmSel);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11, 8, BFWrLvOdt);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 13, 13, BFDqsRcvTrEn);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 30, 30, BFDisAutoComp);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x53, 8, 0, BFWrtLvErr);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 27, 25, BFD3Cmp2PCal);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 22, 20, BFD3Cmp2NCal);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 17, 15, BFD3Cmp1PCal);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 12, 10, BFD3Cmp1NCal);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 7, 5, BFD3Cmp0PCal);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 2, 0, BFD3Cmp0NCal);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 20, 16, BFPhyFence);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 13, 12, BFCKETri);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 11, 8, BFODTTri);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 7, 0, BFChipSelTri);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D040F30, _NOT_USED_, _NOT_USED_, BFErr263);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F0C, _NOT_USED_, _NOT_USED_, BFErr350);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D08E000, _NOT_USED_, _NOT_USED_, BFErr322I);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D02E001, _NOT_USED_, _NOT_USED_, BFErr322II);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2030, _NOT_USED_, _NOT_USED_, BFPhyClkConfig0);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2130, _NOT_USED_, _NOT_USED_, BFPhyClkConfig1);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2230, _NOT_USED_, _NOT_USED_, BFPhyClkConfig2);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2330, _NOT_USED_, _NOT_USED_, BFPhyClkConfig3);
-
- LINK_TSEFO (NBRegTable, BFTwrrd, BFTwrrdHi);
- LINK_TSEFO (NBRegTable, BFTwrwr, BFTwrwrHi);
- LINK_TSEFO (NBRegTable, BFTrdrd, BFTrdrdHi);
-
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnParTrainHy.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnParTrainHy.c
deleted file mode 100644
index 651ba7c..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnParTrainHy.c
+++ /dev/null
@@ -1,224 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnParTrainHy.c
- *
- * Feature which performs Memory DQS training on each node with each node training
- * its own memory through code running on a core in the associated processor.
- * This way memory can be trained in parallel by more than one processor.
- *
- * This file contains the Hydra specific parallel training function.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Feat/HCTRN)
- * @e \$Revision: 35421 $ @e \$Date: 2010-07-22 10:42:31 +0800 (Thu, 22 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mnhy.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuServices.h"
-#include "GeneralServices.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuApicUtilities.h"
-#include "mfParallelTraining.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_NB_HY_MNPARTRAINHY_FILECODE
-/*-----------------------------------------------------------------------------
-* EXPORTED FUNCTIONS
-*
-*-----------------------------------------------------------------------------
-*/
-BOOLEAN
-STATIC
-MemConstructRemoteNBBlockHY (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN DIE_STRUCT *MCTPtr,
- IN MEM_FEAT_BLOCK_NB *FeatPtr
-);
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This is the training function which set up the environment for remote
- * training on the ap and launches the remote routine.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - Launch training on AP successfully.
- * @return FALSE - Fail to launch training on AP.
- */
-BOOLEAN
-MemFParallelTrainingHy (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- AMD_CONFIG_PARAMS *StdHeader;
- DIE_STRUCT *MCTPtr;
- REMOTE_TRAINING_ENV *EnvPtr;
- AP_TASK TrainingTask;
- UINT8 Socket;
- UINT8 Module;
- UINT8 APCore;
- UINT8 p;
- UINT32 LowCore;
- UINT32 HighCore;
- UINT32 BspSocket;
- UINT32 BspModule;
- UINT32 BspCore;
- AGESA_STATUS Status;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
- UINT16 MctDataSize;
- StdHeader = &(NBPtr->MemPtr->StdHeader);
- MCTPtr = NBPtr->MCTPtr;
- Socket = MCTPtr->SocketId;
- Module = MCTPtr->DieId;
-
- //
- // Allocate buffer for REMOTE_TRAINING_ENV
- //
- MctDataSize = MAX_DCTS_PER_NODE_HY * (
- sizeof (DCT_STRUCT) + (
- MAX_CHANNELS_PER_DCT_HY * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))
- )
- );
- AllocHeapParams.RequestedBufferSize = MctDataSize + sizeof (REMOTE_TRAINING_ENV);
- AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, Socket, Module, 0);
- AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
- if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
- EnvPtr = (REMOTE_TRAINING_ENV *) AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += sizeof (REMOTE_TRAINING_ENV);
-
- //
- // Setup Remote training environment
- //
- LibAmdMemCopy (&(EnvPtr->StdHeader), StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);
- LibAmdMemCopy (&(EnvPtr->DieStruct), MCTPtr, sizeof (DIE_STRUCT), StdHeader);
- for (p = 0; p < MAX_PLATFORM_TYPES; p++) {
- EnvPtr->GetPlatformCfg[p] = NBPtr->MemPtr->GetPlatformCfg[p];
- }
- EnvPtr->ErrorHandling = NBPtr->MemPtr->ErrorHandling;
- EnvPtr->NBBlockCtor = MemConstructRemoteNBBlockHY;
- EnvPtr->FeatPtr = NBPtr->FeatPtr;
- EnvPtr->HoleBase = NBPtr->RefPtr->HoleBase;
- EnvPtr->BottomIo = NBPtr->RefPtr->BottomIo;
- EnvPtr->UmaSize = NBPtr->RefPtr->UmaSize;
- EnvPtr->SysLimit = NBPtr->RefPtr->SysLimit;
- EnvPtr->TableBasedAlterations = NBPtr->RefPtr->TableBasedAlterations;
- EnvPtr->PlatformMemoryConfiguration = NBPtr->RefPtr->PlatformMemoryConfiguration;
-
- LibAmdMemCopy (AllocHeapParams.BufferPtr, MCTPtr->DctData, MctDataSize, StdHeader);
-
- //
- // Get Socket, Core of the BSP
- //
- IdentifyCore (StdHeader, &BspSocket, &BspModule, &BspCore, &Status);
- EnvPtr->BspSocket = ((UINT8)BspSocket & 0x000000FF);
- EnvPtr->BspCore = ((UINT8)BspCore & 0x000000FF);
-
- //
- // Set up the remote task structure
- //
- TrainingTask.DataTransfer.DataPtr = EnvPtr;
- TrainingTask.DataTransfer.DataSizeInDwords = (UINT16) (AllocHeapParams.RequestedBufferSize + 3) / 4;
- TrainingTask.DataTransfer.DataTransferFlags = 0;
- TrainingTask.ExeFlags = 0;
- TrainingTask.FuncAddress.PfApTaskI = (PF_AP_TASK_I)MemFParallelTraining;
-
- //
- // Get Target AP Core
- //
- GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader);
- APCore = (UINT8) (LowCore & 0x000000FF);
-
- //
- // Launch Remote Training
- //
- ApUtilRunCodeOnSocketCore (Socket, APCore, &TrainingTask, StdHeader);
-
- HeapDeallocateBuffer (AllocHeapParams.BufferHandle, StdHeader);
-
- return TRUE;
- } else {
- PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV, NBPtr->Node, 0, 0, 0, StdHeader);
- SetMemError (AGESA_FATAL, MCTPtr);
- ASSERT(FALSE); // Could not allocated heap space for "REMOTE_TRAINING_ENV"
- return FALSE;
- }
-}
-
-BOOLEAN
-STATIC
-MemConstructRemoteNBBlockHY (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN DIE_STRUCT *MCTPtr,
- IN MEM_FEAT_BLOCK_NB *FeatPtr
- )
-{
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
-
- NBPtr->MCTPtr = MCTPtr;
- NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue;
-
- MemNInitNBDataHy (NBPtr);
-
- FeatPtr->InitCPG (NBPtr);
- NBPtr->FeatPtr = FeatPtr;
- FeatPtr->InitHwRxEn (NBPtr);
- MemNSwitchDCTNb (NBPtr, 0);
-
- //----------------------------------------------------------------------------
- // Get TSC rate of the this AP
- //----------------------------------------------------------------------------
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
- FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader);
-
- return TRUE;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnS3hy.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnS3hy.c
deleted file mode 100644
index da2084f..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnS3hy.c
+++ /dev/null
@@ -1,740 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mns3hy.c
- *
- * HY memory specific function to support S3 resume
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/HY)
- * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "S3.h"
-#include "mfs3.h"
-#include "mnhy.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "mnS3hy.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G3_DXE)
-RDATA_GROUP (G3_DXE)
-
-#define FILECODE PROC_MEM_NB_HY_MNS3HY_FILECODE
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-UINT16
-STATIC
-MemNS3GetRegLstPtrHy (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT DESCRIPTOR_GROUP *DescriptPtr
- );
-
-AGESA_STATUS
-STATIC
-MemNS3GetDeviceRegLstHy (
- IN UINT32 RegisterLstID,
- OUT VOID **RegisterHeader
- );
-
-VOID
-STATIC
-MemNS3ExitSelfRefRegHy (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-STATIC
-MemNS3SetSpecialPCIRegHy (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR Address,
- IN VOID *Value,
- IN OUT VOID *ConfigPtr
- );
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-PCI_SPECIAL_CASE PciSpecialCaseFuncHy[] = {
- {MemNS3GetCSRNb, MemNS3SetCSRNb},
- {MemNS3GetCSRNb, MemNS3SetSpecialPCIRegHy},
- {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb}
-};
-
-PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorHy[] = {
- {{0, 0, 0}, FUNC_2, 0x110, 0xFFFFFFFF},
- {{0, 0, 0}, FUNC_1, 0x40, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x48, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x50, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x58, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x60, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x68, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x70, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x78, 0xFFFF3F03},
- {{0, 1, 0}, FUNC_1, 0x140, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x148, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x150, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x158, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x160, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x168, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x170, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x178, 0x000000FF},
- {{0, 0, 0}, FUNC_1, 0x44, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x4C, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x54, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x5C, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x64, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x6C, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x74, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x7C, 0xFFFF07FF},
- {{0, 1, 0}, FUNC_1, 0x144, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x14C, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x154, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x15C, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x164, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x16C, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x174, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x17C, 0x000000FF},
- {{0, 0, 0}, FUNC_1, 0xF0, 0xFF00FF83},
- {{0, 0, 0}, FUNC_1, 0x120, 0x00FFFFFF},
- {{0, 0, 0}, FUNC_1, 0x124, 0x07FFFFFF},
- {{0, 0, 0}, FUNC_2, 0x114, 0xFFFFFC00},
- {{0, 0, 0}, FUNC_2, 0x118, 0xF773FFFF},
- {{0, 0, 0}, FUNC_2, 0x11C, 0xFFFFFFFF},
- {{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F}
-};
-
-CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefHy = {
- 0,
- (sizeof (S3PciPreSelfRefDescriptorHy) / sizeof (PCI_REG_DESCRIPTOR)),
- S3PciPreSelfRefDescriptorHy,
- NULL
-};
-
-CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorHy[] = {
- // DCT 0
- {{0, 0, 0}, FUNC_2, 0x40, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x44, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x48, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x4C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x50, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x54, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x58, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x5C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x60, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x64, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x68, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x6C, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x78, 0xFFCDBF0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x7C, 0xFFF7FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 2, 0}, FUNC_2, 0x80, 0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x84, 0x07FFEFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x88, 0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x8C, 0xFFFF7FFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x90, 0x00FFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0xA4, 0x000F7B00, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0xA8, 0x0007FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x180), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x181), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x182), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x183), 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), 0x30333333, DCT0_MASK, ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0x3FFFFFFF, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), 0x001FBFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), 0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhyClkConfig0, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhyClkConfig1, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhyClkConfig2, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhyClkConfig3, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- //errata 322
- {{2, 2, 1}, DCT0, BFErr322I, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFErr322II, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- //errata 263
- {{2, 2, 1}, DCT0, BFErr263, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-
- // DCT 1
- {{0, 0, 0}, FUNC_2, 0x140, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x144, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x148, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x14C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x150, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x154, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x158, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x15C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x160, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x164, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x168, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x16C, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x178, 0xFFCDBF0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x17C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 2, 0}, FUNC_2, 0x180, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x184, 0x07FFEFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x188, 0xFFFFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x18C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x190, 0x00FFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x1A4, 0x000F7B00, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x1A8, 0x0007FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x180), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x181), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x182), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 1, 0x183), 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), 0x30333333, DCT1_MASK, ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x001FBFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyClkConfig0, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyClkConfig1, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyClkConfig2, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyClkConfig3, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- // errata 322
- {{2, 2, 1}, DCT1, BFErr322I, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFErr322II, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- // errata 263
- {{2, 2, 1}, DCT1, BFErr263, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-
- // Restore F2x[1,0]94 right before exit self refresh
- {{0, 0, 0}, FUNC_2, 0x94, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x194, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK}
-};
-
-CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefHy = {
- 0,
- (sizeof (S3CPciPreSelfDescriptorHy) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
- S3CPciPreSelfDescriptorHy,
- PciSpecialCaseFuncHy
-};
-
-CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorHy[] = {
- // DCT0
- {{2, 2, 1}, DCT0, BFEccDLLPwrDnConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFEccDLLConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10), 0x01FF01FF, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11), 0x01FF01FF, DCT0_MASK, 0x01},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12), 0x000001FF, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13), 0x01FF01FF, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14), 0x01FF01FF, DCT0_MASK, 0x04},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15), 0x000001FF, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16), 0x01FF01FF, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17), 0x01FF01FF, DCT0_MASK, 0x10},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18), 0x000001FF, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19), 0x01FF01FF, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A), 0x01FF01FF, DCT0_MASK, 0x40},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B), 0x000001FF, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20), 0x01FF01FF, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21), 0x01FF01FF, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23), 0x01FF01FF, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24), 0x01FF01FF, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26), 0x01FF01FF, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27), 0x01FF01FF, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29), 0x01FF01FF, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A), 0x01FF01FF, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01), 0x7F7F7F7F, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02), 0x7F7F7F7F, DCT0_MASK, 0x01},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03), 0x0000007F, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0x7F7F7F7F, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0x7F7F7F7F, DCT0_MASK, 0x04},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x0000007F, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0x7F7F7F7F, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0x7F7F7F7F, DCT0_MASK, 0x10},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x0000007F, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0x7F7F7F7F, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0x7F7F7F7F, DCT0_MASK, 0x40},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x0000007F, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05), 0x3F3F3F3F, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06), 0x3F3F3F3F, DCT0_MASK, 0x01},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x07), 0x0000003F, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3F3F3F3F, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3F3F3F3F, DCT0_MASK, 0x04},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x107), 0x0000003F, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3F3F3F3F, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3F3F3F3F, DCT0_MASK, 0x10},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x207), 0x0000003F, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3F3F3F3F, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3F3F3F3F, DCT0_MASK, 0x40},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x307), 0x0000003F, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0xFFFFFFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D), 0x23772377, DCT0_MASK, ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30), 0x00FF00FF, DCT0_DDR3_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31), 0x00FF00FF, DCT0_DDR3_MASK, 0x01},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32), 0x000000FF, DCT0_DDR3_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33), 0x00FF00FF, DCT0_DDR3_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34), 0x00FF00FF, DCT0_DDR3_MASK, 0x04},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35), 0x000000FF, DCT0_DDR3_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36), 0x00FF00FF, DCT0_DDR3_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37), 0x00FF00FF, DCT0_DDR3_MASK, 0x10},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38), 0x000000FF, DCT0_DDR3_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39), 0x00FF00FF, DCT0_DDR3_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B), 0x000000FF, DCT0_DDR3_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40), 0x00FF00FF, DCT0_DDR3_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41), 0x00FF00FF, DCT0_DDR3_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43), 0x00FF00FF, DCT0_DDR3_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44), 0x00FF00FF, DCT0_DDR3_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46), 0x00FF00FF, DCT0_DDR3_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47), 0x00FF00FF, DCT0_DDR3_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49), 0x00FF00FF, DCT0_DDR3_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40},
-
- // DCT1
- {{2, 2, 1}, DCT1, BFEccDLLPwrDnConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFEccDLLConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10), 0x01FF01FF, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11), 0x01FF01FF, DCT1_MASK, 0x02},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x12), 0x000001FF, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13), 0x01FF01FF, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14), 0x01FF01FF, DCT1_MASK, 0x08},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x15), 0x000001FF, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x16), 0x01FF01FF, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x17), 0x01FF01FF, DCT1_MASK, 0x20},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x18), 0x000001FF, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x19), 0x01FF01FF, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1A), 0x01FF01FF, DCT1_MASK, 0x80},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1B), 0x000001FF, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20), 0x01FF01FF, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21), 0x01FF01FF, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23), 0x01FF01FF, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24), 0x01FF01FF, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x26), 0x01FF01FF, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x27), 0x01FF01FF, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x29), 0x01FF01FF, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x2A), 0x01FF01FF, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01), 0x7F7F7F7F, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02), 0x7F7F7F7F, DCT1_MASK, 0x02},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x03), 0x0000007F, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101), 0x7F7F7F7F, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102), 0x7F7F7F7F, DCT1_MASK, 0x08},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x103), 0x0000007F, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x201), 0x7F7F7F7F, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x202), 0x7F7F7F7F, DCT1_MASK, 0x20},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x203), 0x0000007F, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x301), 0x7F7F7F7F, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x302), 0x7F7F7F7F, DCT1_MASK, 0x80},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x303), 0x0000007F, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05), 0x3F3F3F3F, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06), 0x3F3F3F3F, DCT1_MASK, 0x02},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x07), 0x0000003F, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105), 0x3F3F3F3F, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106), 0x3F3F3F3F, DCT1_MASK, 0x08},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x107), 0x0000003F, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x205), 0x3F3F3F3F, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x206), 0x3F3F3F3F, DCT1_MASK, 0x20},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x207), 0x0000003F, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x305), 0x3F3F3F3F, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x306), 0x3F3F3F3F, DCT1_MASK, 0x80},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x307), 0x0000003F, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D), 0x23772377, DCT1_MASK, ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30), 0x00FF00FF, DCT1_DDR3_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31), 0x00FF00FF, DCT1_DDR3_MASK, 0x02},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x32), 0x000000FF, DCT1_DDR3_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33), 0x00FF00FF, DCT1_DDR3_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34), 0x00FF00FF, DCT1_DDR3_MASK, 0x08},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x35), 0x000000FF, DCT1_DDR3_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x36), 0x00FF00FF, DCT1_DDR3_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x37), 0x00FF00FF, DCT1_DDR3_MASK, 0x20},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x38), 0x000000FF, DCT1_DDR3_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x39), 0x00FF00FF, DCT1_DDR3_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3B), 0x000000FF, DCT1_DDR3_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40), 0x00FF00FF, DCT1_DDR3_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41), 0x00FF00FF, DCT1_DDR3_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43), 0x00FF00FF, DCT1_DDR3_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44), 0x00FF00FF, DCT1_DDR3_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x46), 0x00FF00FF, DCT1_DDR3_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x47), 0x00FF00FF, DCT1_DDR3_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x49), 0x00FF00FF, DCT1_DDR3_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x4A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80},
-
- // DllShutDown
- {{2, 2, 1}, DCT0, BFPhyPLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhyDLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 1, 1}, DCT0, BFDisDllShutdownSR, 0x00000001, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyPLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyDLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 1, 1}, DCT1, BFDisDllShutdownSR, 0x00000001, DCT1_MASK, ANY_DIMM_MASK},
-
- // Restore scrubber related registers after restoring training related registers
- {{0, 0, 0}, FUNC_3, 0x180, 0x027F7BFF, ANY_DIMM_MASK, ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_3, 0x44, 0xFFFFFFFE, ANY_DIMM_MASK, ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_3, 0x58, 0x1F1F1F1F, ANY_DIMM_MASK, ANY_DIMM_MASK},
- {{2, 1, 1}, DCT0, BFScrubReDirEn, 0x00000001, ANY_DIMM_MASK, ANY_DIMM_MASK}
-};
-
-CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefHy = {
- 0,
- (sizeof (S3CPciPostSelfDescriptorHy) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
- S3CPciPostSelfDescriptorHy,
- PciSpecialCaseFuncHy
-};
-
-MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorHy[] = {
- {{0, 0, 0}, 0xC0010010, 0x00000000007F07FF},
- {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000},
- {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000},
- {{0, 0, 0}, 0xC001001F, 0xC047F87FFF527FFF}
-};
-
-CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefHy = {
- 0,
- (sizeof (S3MSRPreSelfRefDescriptorHy) / sizeof (MSR_REG_DESCRIPTOR)),
- S3MSRPreSelfRefDescriptorHy,
- NULL
-};
-
-VOID *MemS3RegListHy[] = {
- (VOID *)&S3PciPreSelfRefHy,
- NULL,
- (VOID *)&S3CPciPreSelfRefHy,
- (VOID *)&S3CPciPostSelfRefHy,
- (VOID *)&S3MSRPreSelfRefHy,
- NULL,
- NULL,
- NULL
-};
-
-CONST UINT16 ROMDATA SpecialCasePCIRegHy[] = {
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04)
-};
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the northbridge block for S3 resume
- *
- * @param[in,out] *S3NBPtr - Pointer to MEM_NB_BLOCK.
- * @param[in,out] *MemPtr - Pointer to MEM_DATA_STRUCT.
- * @param[in] NodeID - Node ID of the target node.
- *
- * @return BOOLEAN
- * TRUE - This is the correct constructor for the targeted node.
- * FALSE - This isn't the correct constructor for the targeted node.
- */
-
-BOOLEAN
-MemS3ResumeConstructNBBlockHy (
- IN OUT VOID *S3NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- )
-{
- INT32 i;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr;
- //
- // Determine if this is the expected NB Type
- //
- GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
- if (!MemNIsIdSupportedHy (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
- return FALSE;
- }
-
- NBPtr->MemPtr = MemPtr;
- NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
- NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
- InitNBRegTableHy (NBPtr, NBPtr->NBRegTable);
- NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
- NBPtr->Dct = 0;
- NBPtr->Channel = 0;
- NBPtr->Ganged = FALSE;
- NBPtr->NodeCount = MAX_NODES_SUPPORTED_HY;
- NBPtr->DctCount = MAX_DCTS_PER_NODE_HY;
-
- for (i = 0; i < EnumSize; i++) {
- NBPtr->IsSupported[i] = FALSE;
- }
-
- for (i = 0; i < NumberOfHooks; i++) {
- NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) memDefTrue;
- }
-
- LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader);
-
- NBPtr->IsSupported[CheckDllSpeedUp] = TRUE;
- NBPtr->SwitchDCT = MemNSwitchDCTNb;
- NBPtr->SwitchChannel = MemNSwitchChannelNb;
- NBPtr->GetBitField = MemNGetBitFieldNb;
- NBPtr->SetBitField = MemNSetBitFieldNb;
- NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldHy;
- NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedHy;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = MemNS3ExitSelfRefRegHy;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskNb;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK*, DESCRIPTOR_GROUP*)) memDefRet;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeNb;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = MemNS3RestoreScrubNb;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrHy;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstHy;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = (sizeof (SpecialCasePCIRegHy) / sizeof (UINT16)) * sizeof (UINT32);
-
- MemNSwitchDCTNb (NBPtr, 0);
-
- return TRUE;
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------*/
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function returns the register list for each device for HY
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP
- * @return UINT16 - size of the device descriptor on the target node.
- */
-UINT16
-STATIC
-MemNS3GetRegLstPtrHy (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT DESCRIPTOR_GROUP *DescriptPtr
- )
-{
- UINT8 i;
- UINT16 Size;
- Size = 0;
- for (i = PRESELFREF; i <= POSTSELFREF; i ++) {
- DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i);
- DescriptPtr->PCIDevice[i].Node = NBPtr->Node;
- DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF;
- if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListHy[PCI_LST_ESR_HY - PCI_LST_ESR_HY + i] != NULL) {
- DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_HY + i;
- Size += sizeof (PCI_DEVICE_DESCRIPTOR);
- }
- DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i);
- DescriptPtr->CPCIDevice[i].Node = NBPtr->Node;
- DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF;
- if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListHy[CPCI_LST_ESR_HY - PCI_LST_ESR_HY + i] != NULL) {
- DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_HY + i;
- Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR);
- }
- DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i);
- DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF;
- if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListHy[MSR_LST_ESR_HY - PCI_LST_ESR_HY + i] != NULL) {
- DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_HY + i;
- Size += sizeof (MSR_DEVICE_DESCRIPTOR);
- }
- DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i);
- DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF;
- if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListHy[CMSR_LST_ESR_HY - PCI_LST_ESR_HY + i] != NULL) {
- DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_HY + i;
- Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR);
- }
- }
- return Size;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function return the register list according to the register ID.
- *
- * @param[in] RegisterLstID - value of the Register list ID.
- * @param[out] **RegisterHeader - pointer to the address of the register list.
- * @return none
- */
-AGESA_STATUS
-STATIC
-MemNS3GetDeviceRegLstHy (
- IN UINT32 RegisterLstID,
- OUT VOID **RegisterHeader
- )
-{
- if (RegisterLstID >= (sizeof (MemS3RegListHy) / sizeof (VOID *))) {
- ASSERT(FALSE); // RegisterListID exceeded size of Register list
- return AGESA_FATAL;
- }
- if (MemS3RegListHy[RegisterLstID] != NULL) {
- *RegisterHeader = MemS3RegListHy[RegisterLstID];
- return AGESA_SUCCESS;
- }
- ASSERT(FALSE); // Device register list error
- return AGESA_FATAL;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function stores special case register on the heap.
- *
- * @param[in] AccessWidth - Access width of the register
- * @param[in] Address - address of the CSR register in PCI_ADDR format.
- * @param[in, out] *Value - Pointer to the value be read.
- * @param[in, out] *ConfigPtr - Pointer to Config handle.
- * @return none
- */
-VOID
-STATIC
-MemNS3SetSpecialPCIRegHy (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR Address,
- IN VOID *Value,
- IN OUT VOID *ConfigPtr
- )
-{
- LOCATE_HEAP_PTR LocateBufferPtr;
- UINT8 i;
- UINT8 NodeID;
- UINT8 Offset;
- S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader;
-
- Offset = 0;
- LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
- if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) {
- SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr;
- // Get the node ID of the target die.
- NodeID = (UINT8) (Address.Address.Device - 24);
- for (i = 0; i < MAX_NODES_SUPPORTED_HY; i ++) {
- if (SpecialHeapHeader[i].Node == NodeID) {
- // Get the offset in the heap for the target die.
- Offset = SpecialHeapHeader[i].Offset;
- break;
- }
- }
- ASSERT (i < MAX_NODES_SUPPORTED_HY);
- // Save the value in the heap at appropriate offset based on the index
- // of the target register in the special case array.
- if (Offset != 0) {
- for (i = 0; i < (sizeof (SpecialCasePCIRegHy) / sizeof (UINT16)); i ++) {
- if (SpecialCasePCIRegHy[i] == Address.Address.Register) {
- *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)) = *(UINT32 *) Value;
- }
- }
- }
- }
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function stores special case register on the heap.
- *
- * @param[in,out] *NBPtr - Pointer to the northbridge block.
- * @param[in,out] *StdHeader - Config handle for library and services.
- * @return none
- */
-VOID
-STATIC
-MemNS3ExitSelfRefRegHy (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- LOCATE_HEAP_PTR LocateBufferPtr;
- UINT8 i;
- PCI_ADDR PciAddr;
- UINT32 Value;
- UINT8 NodeID;
- UINT8 Offset;
- S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader;
-
- Offset = 0;
- PciAddr.Address.Device = NBPtr->PciAddr.Address.Device;
- PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus;
- PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment;
- PciAddr.Address.Function = 2;
- LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
- if (HeapLocateBuffer (&LocateBufferPtr, StdHeader) == AGESA_SUCCESS) {
- SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr;
- // Get the node ID of the target die.
- NodeID = (UINT8) (PciAddr.Address.Device - 24);
- for (i = 0; i < MAX_NODES_SUPPORTED_HY; i ++) {
- if (SpecialHeapHeader[i].Node == NodeID) {
- // Get the offset in the heap for the target die.
- Offset = SpecialHeapHeader[i].Offset;
- break;
- }
- }
- ASSERT (i < MAX_NODES_SUPPORTED_HY);
- // Restore the value one by one in the sequence of the special case register array.
- if (Offset != 0) {
- for (i = 0; i < (sizeof (SpecialCasePCIRegHy) / sizeof (UINT16)); i ++) {
- PciAddr.Address.Register = SpecialCasePCIRegHy[i];
- Value = *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2));
- MemNS3SetCSRNb (AccessS3SaveWidth32, PciAddr, &Value, StdHeader);
- }
- }
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnS3hy.h b/src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnS3hy.h
deleted file mode 100644
index 3d46433..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnS3hy.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnS3hy.h
- *
- * S3 resume memory related function for HY.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/HY)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MNS3HY_H_
-#define _MNS3HY_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-/// ID for register list of HY
-typedef enum {
- PCI_LST_ESR_HY, ///< Assign 0x0000 for PCI register list for pre exit self refresh.
- PCI_LST_HY, ///< Assign 0x0001 for PCI register list for post exist self refresh.
- CPCI_LST_ESR_HY, ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh.
- CPCI_LST_HY, ///< Assign 0x0003 for conditional PCI register list for post exit self refresh.
- MSR_LST_ESR_HY, ///< Assign 0x0004 for MSR register list for pre exit self refresh.
- MSR_LST_HY, ///< Assign 0x0005 for MSR register list for post exit self refresh.
- CMSR_LST_ESR_HY, ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh.
- CMSR_LST_HY ///< Assign 0x0007 for conditional MSR register list for post exit self refresh.
-} RegisterListIDHy;
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-#endif //_MNS3HY_H_
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mndcthy.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mndcthy.c
deleted file mode 100644
index 6048818..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mndcthy.c
+++ /dev/null
@@ -1,409 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mndctHy.c
- *
- * Northbridge DCT support for Hydra
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/HY)
- * @e \$Revision: 36462 $ @e \$Date: 2010-08-20 00:49:49 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mu.h"
-#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB
-#include "mnhy.h"
-#include "merrhdl.h"
-#include "cpuFamRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_HY_MNDCTHY_FILECODE
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define UNUSED_CLK 4
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function programs the memory controller with configuration parameters
- *
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - An Error value lower than AGESA_FATAL may have occurred
- * @return FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred
- * @return NBPtr->MCTPtr->ErrCode - Contains detailed AGESA_STATUS value
- */
-
-BOOLEAN
-MemNAutoConfigHy (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 PowerDownMode;
- UINT32 Value32;
- DIE_STRUCT *MCTPtr;
- DCT_STRUCT *DCTPtr;
- MEM_PARAMETER_STRUCT *RefPtr;
-
- RefPtr = NBPtr->RefPtr;
- MCTPtr = NBPtr->MCTPtr;
- DCTPtr = NBPtr->DCTPtr;
- //======================================================================
- // Build Dram Control Register Value (F2x78)
- //======================================================================
- //
- //It is recommended that these bits remain in the default state.
- //MemNSetBitFieldNb (NBPtr, BFRdPtrInit, 5);
-
- MemNSetBitFieldNb (NBPtr, BFEarlyArbEn, 1);
-
- //======================================================================
- // Build Dram Config Lo Register Value
- //======================================================================
- //
-
- if (MCTPtr->Status[SbParDimms]) {
- //
- // SbParDimms should be set for all DDR3 RDIMMS
- // Cannot turn off ParEn for DDR3
- //
- //@attention - add debug option for parity control
- MemNSetBitFieldNb (NBPtr, BFParEn, 1);
- }
-
-
- if (MCTPtr->GangedMode) {
- MemNSetBitFieldNb (NBPtr, BFWidth128, 1);
- }
-
- MemNSetBitFieldNb (NBPtr, BFX4Dimm, DCTPtr->Timings.Dimmx4Present & 0xF);
-
- if (!MCTPtr->Status[SbRegistered]) {
- MemNSetBitFieldNb (NBPtr, BFUnBuffDimm, 1);
- }
-
- if (MCTPtr->Status[SbEccDimms]) {
- MemNSetBitFieldNb (NBPtr, BFDimmEccEn, 1);
- }
-
- //======================================================================
- // Build Dram Config Hi Register Value
- //======================================================================
- //
-
- MemNSetBitFieldNb (NBPtr, BFMemClkFreq, MemNGetMemClkFreqIdNb (NBPtr, DCTPtr->Timings.Speed));
-
- if (MCTPtr->Status[SbRegistered]) {
- if ((DCTPtr->Timings.Dimmx4Present != 0) && (DCTPtr->Timings.Dimmx8Present != 0)) {
- MemNSetBitFieldNb (NBPtr, BFRDqsEn, 1);
- }
- }
-
- if (RefPtr->EnableBankSwizzle) {
- MemNSetBitFieldNb (NBPtr, BFBankSwizzleMode, 1);
- }
-
- if (DCTPtr->Timings.DimmQrPresent) {
- if (UserOptions.CfgMemoryQuadrankType == QUADRANK_UNBUFFERED) {
- MemNSetBitFieldNb (NBPtr, BFFourRankSoDimm, 1);
- } else if (UserOptions.CfgMemoryQuadrankType == QUADRANK_REGISTERED) {
- MemNSetBitFieldNb (NBPtr, BFFourRankRDimm, 1);
- }
- }
-
- MemNSetBitFieldNb (NBPtr, BFDcqBypassMax, 0xF);
- MemNSetBitFieldNb (NBPtr, BFDcqArbBypassEn, 1);
- //======================================================================
- // Build Dram Config Misc Register Value
- //======================================================================
- //
- if (MCTPtr->Status[SbRegistered]) {
- if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode)!= 0) {
- MemNSetBitFieldNb (NBPtr, BFSubMemclkRegDly, 1);
- }
- }
- //======================================================================
- // Build Dram Config Misc 2 Register Value
- //======================================================================
- //
- //
- // Ddr3FourSocketCh - Must be the same for both DCTs if either of them have > 2 Dimms
- //
- if ((GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration, MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID)) > 2) {
- MemNBrdcstSetNb (NBPtr, BFDdr3FourSocketCh, 1);
- }
- //
- // DTaxTxFifpWrDly
- //
- Value32 = MemNGetBitFieldNb (NBPtr, BFRdPtrInit);
- if ((Value32 >= 2) && (Value32 <= 5)) {
- MemNSetBitFieldNb (NBPtr, BFDataTxFifoWrDly, (6 - Value32));
- }
-
- //
- // ProgOdtEn
- //
- if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 1) {
- MemNSetBitFieldNb (NBPtr, BFProgOdtEn, 1);
- } else {
- MemNSetBitFieldNb (NBPtr, BFProgOdtEn, 0);
- }
- //
- // OdtSwizzle
- //
- if ((MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 0) && (MemNGetBitFieldNb (NBPtr, BFFourRankRDimm) == 0) && (RefPtr->EnablePowerDown)) {
- PowerDownMode = (UINT8) ((UserOptions.CfgPowerDownMode == POWER_DOWN_MODE_AUTO) ? POWER_DOWN_BY_CHANNEL : UserOptions.CfgPowerDownMode);
- IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader));
- if (PowerDownMode == 1) {
- MemNSetBitFieldNb (NBPtr, BFOdtSwizzle, 1);
- }
- }
-
-
- return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function sends an MRS command
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNSendMrsCmdHy (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MemNSwapBitsNb (NBPtr);
-
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tCS%d MR%d %04x\n",
- (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 20) & 0xF,
- (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 16) & 0xF,
- (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) & 0xFFFF));
-
- // 1.Set SendMrsCmd=1
- MemNSetBitFieldNb (NBPtr, BFSendMrsCmd, 1);
-
- // 2.Wait for SendMrsCmd=0
- MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function sends an MRS command to all CS of all channels
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *DummyPtr - Unused pointer
- *
- * @return TRUE
- */
-
-BOOLEAN
-MemNSendMrsCmdPerCsHy (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT VOID *DummyPtr
- )
-{
- UINT8 Dct;
- UINT8 ChipSel;
- UINT32 Dummy;
-
- if (!NBPtr->MCTPtr->Status[SbRegistered]) {
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
- IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct);
- for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) {
- if (NBPtr->GetSysAddr (NBPtr, ChipSel, &Dummy)) {
- IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", ChipSel);
- // if chip select present
- NBPtr->TechPtr->SendAllMRCmds (NBPtr->TechPtr, ChipSel);
- // NOTE: wait 512 clocks for DLL-relock
- MemUWait10ns (50000, NBPtr->MemPtr); // wait 500us
- }
- }
- }
- }
- }
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This is a general purpose function that executes before DRAM init
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNBeforeDramInitHy (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 Dct;
- for (Dct = 0; Dct < NBPtr->DctCount; Dct ++) {
- MemNSwitchDCTNb (NBPtr, Dct);
- if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
- //Set PllLockTime and DllLockTime to default.
- MemNSetBitFieldNb (NBPtr, BFPhyPLLLockTime, 0x000007D0);
- MemNSetBitFieldNb (NBPtr, BFPhyDLLLockTime, 0x00000190);
- MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 1);
- }
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * Enable DLL Shut down
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-VOID
-MemNEnDLLShutDownHy (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 Dct;
- BOOLEAN DllShutDownEn;
-
- DllShutDownEn = TRUE;
- IDS_OPTION_HOOK (IDS_DLL_SHUT_DOWN, &DllShutDownEn, &(NBPtr->MemPtr->StdHeader));
-
- if (DllShutDownEn && NBPtr->IsSupported[SetDllShutDown]) {
- if ((NBPtr->ChannelPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_D1) != 0) {
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- MemNSwitchDCTNb (NBPtr, Dct);
- if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
- MemNSetBitFieldNb (NBPtr, BFPhyPLLLockTime, 0x0000001C);
- MemNSetBitFieldNb (NBPtr, BFPhyDLLLockTime, 0x0000013D);
- MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 0);
- }
- }
- }
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * Workaround for erratum 322 and 263
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-VOID
-MemNBeforePlatformSpecHy (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- // Errata 263
- if ((NBPtr->DCTPtr->Timings.Speed == DDR533_FREQUENCY) || (NBPtr->DCTPtr->Timings.Speed == DDR667_FREQUENCY)) {
- MemNSetBitFieldNb (NBPtr, BFErr263, 0x0800);
- } else {
- MemNSetBitFieldNb (NBPtr, BFErr263, 0);
- }
-
- // Errata 322
- // 1.Write 00000000h to F2x[1,0]9C_xD08E000
- MemNSetBitFieldNb (NBPtr, BFErr322I, 0);
- // 2.If DRAM Configuration Register[MemClkFreq] (F2x[1,0]94[2:0]) is
- // greater than or equal to 011b (DDR-800 and higher),
- // then write 00000080h to F2x[1,0]9C_xD02E001,
- // else write 00000090h to F2x[1,0]9C_xD02E001.
- MemNSetBitFieldNb (NBPtr, BFErr322II, (NBPtr->DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ? 0x80 : 0x90);
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnflowhy.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnflowhy.c
deleted file mode 100644
index da281cd..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnflowhy.c
+++ /dev/null
@@ -1,135 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnflowhy.c
- *
- * Hydra initializer for MCT and DCT
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Main)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mnhy.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_HY_MNFLOWHY_FILECODE
-/* features */
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledHy[MAX_FF_TYPES];
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the platform specific block
- *
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - AGESA_SUCCESS at least one dorm factor was found
- * @return FALSE - AGESA_UNSUPPORTED - Error indicating that no form factors were found
- */
-
-BOOLEAN
-MemNPlatformSpecificFormFactorInitHy (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 Dct;
- UINT8 f;
- UINT8 ErrUnSuppFFCount;
- for (Dct = 0; Dct < MAX_DCTS_PER_NODE_HY; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- if (NBPtr->ChannelPtr->ChDimmValid != 0) {
- ErrUnSuppFFCount = 0;
- for (f = 0; f < MAX_FF_TYPES; f++) {
- ASSERT (memPlatSpecFFInstalledHy[f] != NULL);
- if (memPlatSpecFFInstalledHy[f] (NBPtr->MemPtr, NBPtr->ChannelPtr, NBPtr->PsPtr) == AGESA_UNSUPPORTED) {
- ErrUnSuppFFCount++; //Count the number of AGESA_UNSUPPORTED errors
- } else {
- break;
- }
- }
- if (ErrUnSuppFFCount == MAX_FF_TYPES) {
- return FALSE; // No FF types are supported
- }
- }
- }
- return TRUE;
-}
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnhy.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnhy.c
deleted file mode 100644
index 58a4dc9..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnhy.c
+++ /dev/null
@@ -1,487 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnhy.c
- *
- * Common Northbridge functions for Hydra
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/HY)
- * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mnhy.h"
-#include "mu.h"
-#include "S3.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "heapManager.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_HY_MNHY_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-#define SPLIT_CHANNEL (UINT32) 0x20000000
-#define CHANNEL_SELECT (UINT32) 0x10000000
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the northbridge block
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
- * @param[in] *FeatPtr - Pointer to the MEM_FEAT_BLOCK_NB
- * @param[in] *SharedPtr - Pointer to the MEM_SHARED_DATA
- * @param[in] NodeID - UINT8 indicating node ID of the NB object.
- *
- * @return Boolean indicating that this is the correct memory
- * controller type for the node number that was passed in.
- */
-
-BOOLEAN
-MemConstructNBBlockHY (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN MEM_FEAT_BLOCK_NB *FeatPtr,
- IN MEM_SHARED_DATA *SharedPtr,
- IN UINT8 NodeID
- )
-{
- UINT8 Dct;
- UINT8 Channel;
- UINT8 SpdSocketIndex;
- UINT8 SpdChannelIndex;
- DIE_STRUCT *MCTPtr;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
- //
- // Determine if this is the expected NB Type
- //
- GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
- if (!MemNIsIdSupportedHy (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
- return FALSE;
- }
-
- NBPtr->MemPtr = MemPtr;
- NBPtr->RefPtr = MemPtr->ParameterListPtr;
- NBPtr->SharedPtr = SharedPtr;
-
- MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
- NBPtr->MCTPtr = MCTPtr;
- NBPtr->MCTPtr->NodeId = NodeID;
- NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue;
- NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
-
- //
- // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
- //
- AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_HY * (
- sizeof (DCT_STRUCT) + (
- MAX_CHANNELS_PER_DCT_HY * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))
- )
- );
- AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0);
- AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
- if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) {
- PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader);
- SetMemError (AGESA_FATAL, MCTPtr);
- ASSERT(FALSE); // Could not allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
- return FALSE;
- }
-
- MCTPtr->DctCount = MAX_DCTS_PER_NODE_HY;
- MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_HY * sizeof (DCT_STRUCT);
- for (Dct = 0; Dct < MAX_DCTS_PER_NODE_HY; Dct++) {
- MCTPtr->DctData[Dct].Dct = Dct;
- MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_HY;
- MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr;
- MCTPtr->DctData[Dct].ChData[0].Dct = Dct;
- AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_HY * sizeof (CH_DEF_STRUCT);
- }
- NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr;
-
- //
- // Initialize Socket List
- //
- for (Dct = 0; Dct < MAX_DCTS_PER_NODE_HY; Dct++) {
- MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr[(MCTPtr->DieId * 2) + Dct] = &(MCTPtr->DctData[Dct].ChData[0]);
- MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr[(MCTPtr->DieId * 2) + Dct] = &(MCTPtr->DctData[Dct].Timings);
- MCTPtr->DctData[Dct].ChData[0].ChannelID = (MCTPtr->DieId * 2) + Dct;
- }
-
- MemNInitNBDataHy (NBPtr);
-
- FeatPtr->InitCPG (NBPtr);
- NBPtr->FeatPtr = FeatPtr;
- FeatPtr->InitHwRxEn (NBPtr);
- //
- // Calculate SPD Offsets per channel and assign pointers to the data. At this point, we calculate the Node-Dct-Channel
- // centric offsets and store the pointers to the first DIMM of each channel in the Channel Definition struct for that
- // channel. This pointer is then used later to calculate the offsets to be used for each logical dimm once the
- // dimm types(QR or not) are known. This is done in the Technology block constructor.
- //
- // Calculate the SpdSocketIndex separately from the SpdChannelIndex.
- // This will facilitate modifications due to some processors that might
- // map the DCT-CHANNEL differently.
- //
- SpdSocketIndex = GetSpdSocketIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, &MemPtr->StdHeader);
- //
- // Traverse the Dct/Channel structures
- //
- for (Dct = 0; Dct < MAX_DCTS_PER_NODE_HY; Dct++) {
- for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_HY; Channel++) {
- //
- // Calculate the number of Dimms on this channel using the
- // die/dct/channel to Socket/channel conversion.
- //
- SpdChannelIndex = GetSpdChannelIndex (NBPtr->RefPtr->PlatformMemoryConfiguration,
- NBPtr->MCTPtr->SocketId,
- MemNGetSocketRelativeChannelNb (NBPtr, Dct, Channel),
- &MemPtr->StdHeader);
- NBPtr->MCTPtr->DctData[Dct].ChData[Channel].SpdPtr = &(MemPtr->SpdDataStructure[SpdSocketIndex + SpdChannelIndex]);
- }
- }
-
- MemNSwitchDCTNb (NBPtr, 0);
-
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initializes member functions and variables of NB block.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNInitNBDataHy (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- NBPtr->DctCachePtr = NBPtr->DctCache;
- NBPtr->PsPtr = NBPtr->PSBlock;
-
- InitNBRegTableHy (NBPtr, NBPtr->NBRegTable);
- NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
- NBPtr->Dct = 0;
- NBPtr->Channel = 0;
- NBPtr->DctCount = MAX_DCTS_PER_NODE_HY;
- NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_HY;
- NBPtr->NodeCount = MAX_NODES_SUPPORTED_HY;
- NBPtr->Ganged = FALSE;
- NBPtr->PosTrnPattern = POS_PATTERN_256B;
- NBPtr->MemCleared = FALSE;
- NBPtr->StartupSpeed = DDR800_FREQUENCY;
- NBPtr->RcvrEnDlyLimit = 0x1FF;
- NBPtr->DefDctSelIntLvAddr = 3;
-
- LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader);
-
- NBPtr->SetMaxLatency = MemNSetMaxLatencyNb;
- NBPtr->getMaxLatParams = MemNGetMaxLatParamsNb;
- NBPtr->InitializeMCT = MemNInitializeMctHy;
- NBPtr->FinalizeMCT = MemNFinalizeMctHy;
- NBPtr->SendMrsCmd = MemNSendMrsCmdHy;
- NBPtr->sendZQCmd = MemNSendZQCmdNb;
- NBPtr->WritePattern = MemNWritePatternHy;
- NBPtr->ReadPattern = MemNReadPatternHy;
- NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK *, UINT32)) memDefRet;
- NBPtr->CompareTestPattern = MemNCompareTestPatternNb;
- NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb;
- NBPtr->StitchMemory = MemNStitchMemoryNb;
- NBPtr->AutoConfig = MemNAutoConfigHy;
- NBPtr->PlatformSpec = MemNPlatformSpecNb;
- NBPtr->InitMCT = MemNInitMCTNb;
- NBPtr->DisableDCT = MemNDisableDCTNb;
- NBPtr->StartupDCT = MemNStartupDCTNb;
- NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb;
- NBPtr->ChangeFrequency = MemNChangeFrequencyNb;
- NBPtr->RampUpFrequency = MemNRampUpFrequencyNb;
- NBPtr->ChangeNbFrequency = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefFalse;
- NBPtr->ProgramCycTimings = MemNProgramCycTimingsNb;
- NBPtr->SyncDctsReady = MemNSyncDctsReadyNb;
- NBPtr->HtMemMapInit = MemNHtMemMapInitNb;
- NBPtr->SyncAddrMapToAllNodes = MemNSyncAddrMapToAllNodesNb;
- NBPtr->CpuMemTyping = MemNCPUMemTypingNb;
- NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingNb;
- NBPtr->AfterDqsTraining = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
- NBPtr->OtherTiming = MemNOtherTimingHy;
- NBPtr->UMAMemTyping = MemNUMAMemTypingNb;
- NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelHy;
- NBPtr->TechBlockSwitch = MemNTechBlockSwitchNb;
- NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldHy;
- NBPtr->SetEccSymbolSize = MemNSetEccSymbolSizeNb;
- NBPtr->TrainingFlow = MemNTrainingFlowNb;
- MemNInitNBDataNb (NBPtr);
- NBPtr->PollBitField = MemNPollBitFieldNb;
- NBPtr->BrdcstCheck = MemNBrdcstCheckNb;
- NBPtr->BrdcstSet = MemNBrdcstSetNb;
- NBPtr->GetTrainDly = MemNGetTrainDlyNb;
- NBPtr->SetTrainDly = MemNSetTrainDlyNb;
- NBPtr->PhyFenceTraining = MemNPhyFenceTrainingNb;
- NBPtr->GetSysAddr = MemNGetMCTSysAddrNb;
- NBPtr->RankEnabled = MemNRankEnabledNb;
- NBPtr->MemNBeforeDramInitNb = MemNBeforeDramInitHy;
- NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyNb;
- NBPtr->MemPPhyFenceTrainingNb = MemNTrainPhyFenceNb;
- NBPtr->MemNInitPhyComp = MemNInitPhyCompHy;
- NBPtr->MemNBeforePlatformSpecNb = MemNBeforePlatformSpecHy;
- NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitHy;
- NBPtr->MemNPFenceAdjustNb = (VOID (*) (MEM_NB_BLOCK *, UINT16 *)) memDefRet;
- NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsNb;
- NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb;
- NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb;
- NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb;
- NBPtr->CSPerChannel = MemNCSPerChannelNb;
- NBPtr->CSPerDelay = MemNCSPerDelayNb;
- NBPtr->FlushPattern = MemNFlushPatternNb;
- NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb;
- NBPtr->MemNCapSpeedBatteryLife = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
- NBPtr->GetUmaSize = MemNGetUmaSizeNb;
- NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdNb;
- NBPtr->EnableSwapIntlvRgn = (VOID (*) (MEM_NB_BLOCK *, UINT32, UINT32)) memDefRet;
- NBPtr->WaitXMemClks = MemNWaitXMemClksNb;
- NBPtr->MemNGetDramTerm = MemNGetDramTermNb;
- NBPtr->MemNGetDynDramTerm = MemNGetDynDramTermNb;
- NBPtr->MemNGetMR0CL = MemNGetMR0CLNb;
- NBPtr->MemNGetMR0WR = MemNGetMR0WRNb;
- NBPtr->MemNGetMR2CWL = MemNGetMR2CWLNb;
- NBPtr->AllocateC6Storage = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
-
- NBPtr->IsSupported[SetSpareEn] = TRUE;
- NBPtr->IsSupported[CheckSpareEn] = TRUE;
- NBPtr->IsSupported[SetDllShutDown] = TRUE;
- NBPtr->IsSupported[CheckEccDLLPwrDnConfig] = TRUE;
- NBPtr->IsSupported[CheckMaxDramRate] = TRUE;
- NBPtr->IsSupported[CheckMemClkCSPresent] = TRUE;
- NBPtr->IsSupported[CheckMaxRdDqsDlyPtr] = TRUE;
- NBPtr->IsSupported[CheckPhyFenceTraining] = TRUE;
- NBPtr->IsSupported[CheckSendAllMRCmds] = TRUE;
- NBPtr->IsSupported[CheckFindPSOverideWithSocket] = TRUE;
- NBPtr->IsSupported[CheckODTControls] = TRUE;
- NBPtr->IsSupported[CheckDummyCLRead] = TRUE;
- NBPtr->IsSupported[CheckSlewWithoutMarginImprv] = TRUE;
- NBPtr->IsSupported[CheckDllSpeedUp] = TRUE;
- NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE;
-
- NBPtr->FamilySpecificHook[SendMrsCmdsPerCs] = MemNSendMrsCmdPerCsHy;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the default values in the MEM_DATA_STRUCT
- *
- * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
- *
- */
-VOID
-MemNInitDefaultsHY (
- IN OUT MEM_DATA_STRUCT *MemPtr
- )
-{
- UINT8 Socket;
- UINT8 Channel;
- MEM_PARAMETER_STRUCT *RefPtr;
- ASSERT (MemPtr != NULL);
- RefPtr = MemPtr->ParameterListPtr;
-
- // Memory Map/Mgt.
- // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB
- RefPtr->BottomIo = 0xE0;
- RefPtr->UmaMode = UserOptions.CfgUmaMode;
- RefPtr->UmaSize = UserOptions.CfgUmaSize;
- RefPtr->MemHoleRemapping = TRUE;
- //
-
-
- // Dram Timing
- RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect;
- RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect;
- for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) {
- for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) {
- MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL;
- MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL;
- }
- }
-
- // Memory Clear
- RefPtr->EnableMemClr = TRUE;
-
- // TableBasedAlterations
- RefPtr->TableBasedAlterations = NULL;
-
- // Platform config table
- RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration;
-
- // Memory Restore
- RefPtr->MemRestoreCtl = FALSE;
- RefPtr->SaveMemContextCtl = FALSE;
- AmdS3ParamsInitializer (&RefPtr->MemContext);
-
- // Dram Configuration
- RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving;
- RefPtr->EnableNodeIntlv = UserOptions.CfgMemoryEnableNodeInterleaving;
- RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving;
- RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle;
- RefPtr->EnableParity = UserOptions.CfgMemoryParityEnable;
- RefPtr->EnableOnLineSpareCtl = UserOptions.CfgOnlineSpare;
-
- // Dram Power
- RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown;
-
- // ECC
- RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
-}
-/*-----------------------------------------------------------------------------*/
-/**
- *
- * This function writes training pattern
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Pattern[] - Pattern to write
- * @param[in] Address - System Address [47:16]
- * @param[in] ClCount - Number of cache lines
- *
- */
-
-VOID
-MemNWritePatternHy (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 Address,
- IN UINT8 Pattern[],
- IN UINT16 ClCount
- )
-{
- Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
- MemUWriteCachelines (Address, Pattern, ClCount);
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- *
- * This function reads training pattern
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Buffer[] - Buffer to fill
- * @param[in] Address - System Address [47:16]
- * @param[in] ClCount - Number of cache lines
- *
- */
-
-VOID
-MemNReadPatternHy (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Buffer[],
- IN UINT32 Address,
- IN UINT16 ClCount
- )
-{
- Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
- MemUReadCachelines (Buffer, Address, ClCount);
-}
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initiates DQS training for Server NB
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-BOOLEAN
-memNEnableTrainSequenceHy (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- BOOLEAN Retval;
- Retval = TRUE;
- if (!MemNIsIdSupportedHy (NBPtr, &(NBPtr->MemPtr->DiesPerSystem[NBPtr->MCTPtr->NodeId].LogicalCpuid))) {
- Retval = FALSE;
- }
- return Retval;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnhy.h b/src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnhy.h
deleted file mode 100644
index bf15ab9..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnhy.h
+++ /dev/null
@@ -1,202 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnhy.h
- *
- * Northbridge Hydra
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem)
- * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MNHY_H_
-#define _MNHY_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-#define MAX_CHANNELS_PER_SOCKET_HY 4
-#define MAX_DCTS_PER_NODE_HY 2
-#define MAX_CHANNELS_PER_DCT_HY 1
-#define MAX_NODES_SUPPORTED_HY 8
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-MemConstructNBBlockHY (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN MEM_FEAT_BLOCK_NB *FeatPtr,
- IN MEM_SHARED_DATA *SharedPtr,
- IN UINT8 NodeID
- );
-
-VOID
-MemNInitNBDataHy (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNInitDefaultsHY (
- IN OUT MEM_DATA_STRUCT *MemPtr
- );
-
-BOOLEAN
-MemNInitializeMctHy (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNFinalizeMctHy (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNSendMrsCmdHy (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNAutoConfigHy (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNOtherTimingHy (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNInitPhyCompHy (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNWritePatternHy (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 Address,
- IN UINT8 Pattern[],
- IN UINT16 ClCount
- );
-
-VOID
-MemNReadPatternHy (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Buffer[],
- IN UINT32 Address,
- IN UINT16 ClCount
- );
-
-VOID
-InitNBRegTableHy (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT TSEFO NBRegTable[]
- );
-
-UINT8
-MemNGetSocketRelativeChannelHy (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Dct,
- IN UINT8 Channel
- );
-
-BOOLEAN
-MemNIsIdSupportedHy (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN CPU_LOGICAL_ID *LogicalIdPtr
- );
-
-VOID
-MemNBeforeDramInitHy (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNPlatformSpecificFormFactorInitHy (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNEnDLLShutDownHy (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-UINT32
-MemNCmnGetSetFieldHy (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN BIT_FIELD_NAME FieldName,
- IN UINT32 Field
- );
-
-VOID
-MemNBeforePlatformSpecHy (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-memNEnableTrainSequenceHy (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNSendMrsCmdPerCsHy (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT VOID *DummyPtr
- );
-
-#endif /* _MNHY_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnidendimmhy.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnidendimmhy.c
deleted file mode 100644
index 9fe91a6..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnidendimmhy.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnidendimmhy.c
- *
- * Hy northbridge constructor for dimm identification translator.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/HY)
- * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "mm.h"
-#include "mn.h"
-#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB
-#include "mnhy.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_NB_HY_MNIDENDIMMHY_FILECODE
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the northbridge block for dimm identification translator
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
- * @param[in,out] NodeID - ID of current node to construct
- * @return TRUE - This is the correct constructor for the targeted node.
- * @return FALSE - This isn't the correct constructor for the targeted node.
- */
-
-BOOLEAN
-MemNIdentifyDimmConstructorHy (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- )
-{
- //
- // Determine if this is the expected NB Type
- //
- GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
- if (!MemNIsIdSupportedHy (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
- return FALSE;
- }
-
- NBPtr->NodeCount = MAX_NODES_SUPPORTED_HY;
- NBPtr->DctCount = MAX_DCTS_PER_NODE_HY;
- NBPtr->MemPtr = MemPtr;
- NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
- NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
- NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
- NBPtr->Ganged = FALSE;
- InitNBRegTableHy (NBPtr, NBPtr->NBRegTable);
- NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldHy;
- NBPtr->GetBitField = MemNGetBitFieldNb;
- NBPtr->SetBitField = MemNSetBitFieldNb;
- NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelHy;
-
- return TRUE;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnmcthy.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnmcthy.c
deleted file mode 100644
index c58618e..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnmcthy.c
+++ /dev/null
@@ -1,195 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnmcthy.c
- *
- * Northbridge Hydra MCT supporting functions
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/HY)
- * @e \$Revision: 36462 $ @e \$Date: 2010-08-20 00:49:49 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mport.h"
-#include "mm.h"
-#include "mn.h"
-#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB
-#include "mnhy.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_HY_MNMCTHY_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-extern BUILD_OPT_CFG UserOptions;
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function sets final values in BUCFG and BUCFG2
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemNFinalizeMctHy (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MEM_DATA_STRUCT *MemPtr;
- S_UINT64 SMsr;
- UINT16 Speed;
- UINT32 ExtMctCfgLoRegVal;
-
- MemPtr = NBPtr->MemPtr;
- Speed = NBPtr->DCTPtr->Timings.Speed;
- MemNSetBitFieldNb (NBPtr, BFMctCfgHiReg, (!NBPtr->Ganged) ? 0x2CE00F60 : 0x2CE00F40);
-
- ExtMctCfgLoRegVal = MemNGetBitFieldNb (NBPtr, BFExtMctCfgLoReg);
- ExtMctCfgLoRegVal |= (NBPtr->Ganged) ? 0x0FC00001 : 0x0FC01001;
-
- ExtMctCfgLoRegVal &= 0x0FFFFFFF;
- if (Speed == DDR667_FREQUENCY) {
- ExtMctCfgLoRegVal |= 0x40000000;
- } else if (Speed == DDR800_FREQUENCY) {
- ExtMctCfgLoRegVal |= 0x50000000;
- } else if (Speed == DDR1066_FREQUENCY) {
- ExtMctCfgLoRegVal |= 0x60000000;
- } else if (Speed == DDR1333_FREQUENCY) {
- ExtMctCfgLoRegVal |= 0x80000000;
- } else {
- ExtMctCfgLoRegVal |= 0x90000000;
- }
- MemNSetBitFieldNb (NBPtr, BFExtMctCfgLoReg, ExtMctCfgLoRegVal);
-
- if (NBPtr->Node == BSP_DIE) {
- if (!NBPtr->ClToNbFlag) {
- LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- SMsr.lo &= ~((UINT32)1 << 15); // ClLinesToNbDis
- LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- }
-
- LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- SMsr.hi &= ~((UINT32)1 << (48 - 32)); // WbEnhWsbDis
- LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- }
-
- return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function sets initial values in BUCFG and BUCFG2
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemNInitializeMctHy (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MEM_DATA_STRUCT *MemPtr;
- S_UINT64 SMsr;
-
- MemPtr = NBPtr->MemPtr;
-
- if (NBPtr->Node == BSP_DIE) {
- LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- if (SMsr.lo & ((UINT32)1 << 15)) {
- NBPtr->ClToNbFlag = 1;
- }
- SMsr.lo |= (UINT32)1 << 15; // ClLinesToNbDis
- LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-
- LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- SMsr.hi |= (UINT32)1 << (48 - 32); // WbEnhWsbDis
- LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- }
- return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnothy.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnothy.c
deleted file mode 100644
index ef5cdb7..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnothy.c
+++ /dev/null
@@ -1,241 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnothy.c
- *
- * Northbridge Non-SPD timings for Hydra
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/HY)
- * @e \$Revision: 36462 $ @e \$Date: 2010-08-20 00:49:49 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB
-#include "mnhy.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_HY_MNOTHY_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-VOID
-STATIC
-MemNSetOtherTimingHY (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-UINT32
-STATIC
-MemNGetODTDelaysHy (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function sets the non-SPD timings
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemNOtherTimingHy (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MemNSwitchDCTNb (NBPtr, 0);
- if (NBPtr->DCTPtr->Timings.DctDimmValid > 0) {
- MemNSetOtherTimingHY (NBPtr);
- MemNPowerDownCtlNb (NBPtr);
- MemNEnDLLShutDownHy (NBPtr);
- }
-
- MemNSwitchDCTNb (NBPtr, 1);
- if ((NBPtr->DCTPtr->Timings.DctDimmValid > 0) && (NBPtr->MCTPtr->GangedMode == FALSE)) {
- MemNSetOtherTimingHY (NBPtr);
- MemNPowerDownCtlNb (NBPtr);
- MemNEnDLLShutDownHy (NBPtr);
- }
- return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function sets the non-SPD timings in PCI registers
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-STATIC
-MemNSetOtherTimingHY (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
-
- MemNSetBitFieldNb (NBPtr, BFTrdrd, MemNGetTrdrdNb (NBPtr));
- MemNSetBitFieldNb (NBPtr, BFTwrwr, MemNGetTwrwrNb (NBPtr));
- MemNSetBitFieldNb (NBPtr, BFTwrrd, MemNGetTwrrdNb (NBPtr));
- MemNSetBitFieldNb (NBPtr, BFTrwtTO, MemNGetTrwtTONb (NBPtr));
- MemNSetBitFieldNb (NBPtr, BFTrwtWB, MemNGetTrwtWBNb (NBPtr));
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function gets the ODT delays
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-UINT32
-STATIC
-MemNGetODTDelaysHy (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- INT8 Ld;
- UINT32 ODTDelays;
- //
- // On revision D processors, the BIOS must additionally configure the ODT pattern
- // and the ODT switching delays.
- //
- // Program F2x[1, 0]9C_x83 DRAM Phy ODT Assertion Control Register based on Burst length.
- // -Read the Burst Length from F2x[1, 0]84[BurstCtrl].
- // -Value of 2, BL = 4 else assume BL=8.
- // -Initialize ODTDelays based on BL value
- // -WrOdtOnDuration [14:12] = BL / 2 + 1
- // -WrOdtTrnOnDly [10:8] = 0
- // -RdOdtOnDuration [6:4] = BL / 2 + 1
- //
- ODTDelays = (MemNGetBitFieldNb (NBPtr, BFBurstCtrl) == 2) ? 0x00003030 : 0x00005050;
-
- // RdOdtTrnOnDly [3:0] < (CL-CWL) or (CL-CWL - 1)
- // See BKDG F2x[1, 0]9C_x83 DRAM Phy ODT Assertion Control Register [3:0]
- Ld = ((INT8)MemNGetBitFieldNb (NBPtr, BFTcl) + 1) - ((INT8)MemNGetBitFieldNb (NBPtr, BFTcwl) + 5);
- if (Ld < 0) {
- Ld = 0;
- }
- if (Ld > 7) {
- Ld = 7;
- }
- ODTDelays += Ld;
- return ODTDelays;
-}
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function enables power down mode
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-STATIC
-MemNPowerDownCtlHY (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MEM_PARAMETER_STRUCT *RefPtr;
- UINT8 PowerDownMode;
-
- RefPtr = NBPtr->RefPtr;
-
- // we can't enable powerdown mode when doing WL
- if (RefPtr->EnablePowerDown) {
- MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 1);
- PowerDownMode = (UINT8) UserOptions.CfgPowerDownMode;
- IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader));
- if (PowerDownMode) {
- MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1);
- }
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnphyhy.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnphyhy.c
deleted file mode 100644
index 9720ed8..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnphyhy.c
+++ /dev/null
@@ -1,183 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnphyHy.c
- *
- * Northbridge Phy support for Hydra
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/HY)
- * @e \$Revision: 36462 $ @e \$Date: 2010-08-20 00:49:49 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "ma.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mu.h"
-#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB
-#include "mnhy.h"
-#include "PlatformMemoryConfiguration.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_HY_MNPHYHY_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define UNUSED_CLK 4
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the DDR phy compensation logic
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNInitPhyCompHy (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- CONST UINT8 TableCompRiseSlew20x[] = {7, 3, 2, 2};
- CONST UINT8 TableCompRiseSlew15x[] = {7, 7, 3, 2};
- CONST UINT8 TableCompFallSlew20x[] = {7, 5, 3, 2};
- CONST UINT8 TableCompFallSlew15x[] = {7, 7, 5, 3};
- UINT8 i;
- UINT8 j;
- UINT8 CurrDct;
- UINT8 MaxDimmsPerChannel;
- UINT8 *DimmsPerChPtr;
-
- CurrDct = NBPtr->Dct;
-
- //
- // Get Platform Information
- //
- DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
- if (DimmsPerChPtr != NULL) {
- MaxDimmsPerChannel = *DimmsPerChPtr;
- } else {
- MaxDimmsPerChannel = 2;
- }
-
- // 1. BIOS disables the phy compensation register by programming F2x9C_x08[DisAutoComp]=1
- // 2. BIOS waits 5 us for the disabling of the compensation engine to complete.
- // DisAutoComp will be cleared after Dram init has completed
- //
- MemNSwitchDCTNb (NBPtr, 0);
- MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 1);
- MemUWait10ns (500, NBPtr->MemPtr);
- MemNSwitchDCTNb (NBPtr, CurrDct);
-
- // 3. For each normalized driver strength code read from
- // F2x[1, 0]9C_x00[AddrCmdDrvStren], program the
- // corresponding 3 bit predriver code in F2x9C_x0A[D3Cmp1NCal, D3Cmp1PCal].
- //
- // 4. For each normalized driver strength code read from
- // F2x[1, 0]9C_x00[DataDrvStren], program the corresponding
- // 3 bit predriver code in F2x9C_x0A[D3Cmp0NCal, D3Cmp0PCal, D3Cmp2NCal,
- // D3Cmp2PCal].
- //
- j = (UINT8) MemNGetBitFieldNb (NBPtr, BFAddrCmdDrvStren);
- i = (UINT8) MemNGetBitFieldNb (NBPtr, BFDataDrvStren);
-
- MemNSwitchDCTNb (NBPtr, 0);
- ASSERT (j <= 3);
- MemNSetBitFieldNb (NBPtr, BFD3Cmp1NCal, TableCompRiseSlew20x[j]);
- MemNSetBitFieldNb (NBPtr, BFD3Cmp1PCal, TableCompFallSlew20x[j]);
-
- ASSERT (i <= 3);
- MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, TableCompRiseSlew15x[i]);
- MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, TableCompFallSlew15x[i]);
- MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, TableCompRiseSlew15x[i]);
- MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, TableCompFallSlew15x[i]);
-
- //
- // Special Case for certain configs
- //
- // 3DPCH Fully populated.
- if ((MaxDimmsPerChannel == 3) && (NBPtr->ChannelPtr->Dimms == 3)) {
- MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, 3);
- MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, 5);
- MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, 3);
- MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, 5);
- }
-
- MemNSwitchDCTNb (NBPtr, CurrDct);
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnprotohy.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnprotohy.c
deleted file mode 100644
index 6ec9a1b..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnprotohy.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnprotohy.c
- *
- * Northbridge support functions for Errata and early samples
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/HY)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-
-#include "AGESA.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_HY_MNPROTOHY_FILECODE
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnreghy.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnreghy.c
deleted file mode 100644
index ff5ed1d..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/HY/mnreghy.c
+++ /dev/null
@@ -1,630 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnreghy.c
- *
- * Common Northbridge register related functions for Hydra
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/HY)
- * @e \$Revision: 38303 $ @e \$Date: 2010-09-22 00:22:47 +0800 (Wed, 22 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mnhy.h"
-#include "merrhdl.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_HY_MNREGHY_FILECODE
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/*-----------------------------------------------------------------------------*/
-/**
- * MemNIsIdSupportedHy
- * This function matches the CPU_LOGICAL_ID with certain criteria to
- * determine if it is supported by this NBBlock.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID
- *
- * @return TRUE - This node is a Hydra.
- * @return FALSE - This node is not a Hydra.
- *
- */
-BOOLEAN
-MemNIsIdSupportedHy (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN CPU_LOGICAL_ID *LogicalIdPtr
- )
-{
- if (((LogicalIdPtr->Family & AMD_FAMILY_10_HY) != 0)
- && ((LogicalIdPtr->Revision & AMD_F10_HY_ALL) != 0)) {
- return TRUE;
- } else {
- return FALSE;
- }
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- * This function calculates the memory channel index relative to the
- * socket, taking the Die number, the Dct, and the channel.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Dct
- * @param[in] Channel
- *
- */
-UINT8
-MemNGetSocketRelativeChannelHy (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Dct,
- IN UINT8 Channel
- )
-{
- return ((NBPtr->MCTPtr->DieId * MAX_DCTS_PER_NODE_HY) + Dct);
-}
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------*/
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function gets or sets a value to a bit field in a PCI register.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] FieldName - Bit Field to be programmed
- * @param[in] Field - Value to be programmed
- * @param[in] IsSet - Indicates if the function will set or get
- *
- * @return value read, if the function is used as a "get"
- */
-
-UINT32
-MemNCmnGetSetFieldHy (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN BIT_FIELD_NAME FieldName,
- IN UINT32 Field
- )
-{
- TSEFO Address;
- PCI_ADDR PciAddr;
- UINT8 Type;
- UINT8 IsLinked;
- UINT32 Value;
- UINT32 Highbit;
- UINT32 Lowbit;
- UINT32 Mask;
-
- Value = 0;
- if ((FieldName < BFEndOfList) && (FieldName >= 0)) {
- Address = NBPtr->NBRegTable[FieldName];
- if (Address) {
- Lowbit = TSEFO_END (Address);
- Highbit = TSEFO_START (Address);
- Type = (UINT8) TSEFO_TYPE (Address);
- IsLinked = (UINT8) TSEFO_LINKED (Address);
-
- // If Fn2 and DCT1 selected, set Address to be 1xx
- if ((Type == NB_ACCESS) && ((Address & 0xF000) == 0x2000) && NBPtr->Dct) {
- if (!NBPtr->Ganged || (Address & 0xFF) == 0x98 || (Address & 0xFF) == 0x9C) {
- Address |= 0x0100;
- }
- }
-
- ASSERT ((Address & ((UINT32) 1) << 28) == 0); // Phy direct access method is not supported
-
- if ((Address >> 29) == ((DCT_PHY_ACCESS << 1) | 1)) {
- // Special DCT Phy access
- Address &= 0x0FFFFFFF;
- Lowbit = 0;
- Highbit = 16;
- IsLinked = 0;
- } else {
- // Normal DCT Phy access
- Address = TSEFO_OFFSET (Address);
- }
-
- if (Type == NB_ACCESS) {
- PciAddr.AddressValue = Address;
- PciAddr.Address.Device = NBPtr->PciAddr.Address.Device;
- PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus;
- PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment;
- Address = PciAddr.AddressValue;
- LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
- if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) &&
- (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) {
- IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Value);
- }
- } else if (Type == DCT_PHY_ACCESS) {
- MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
- MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
- Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
- IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%d9C_%x = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Value);
- } else if (Type == DCT_EXTRA) {
- MemNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address);
- MemNPollBitFieldNb (NBPtr, BFDctExtraAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
- Value = MemNGetBitFieldNb (NBPtr, BFDctExtraDataReg);
- IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%dF4_%x = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Value);
- } else {
- IDS_ERROR_TRAP;
- }
-
- if (IsSet) {
- // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
- if ((Highbit - Lowbit) != 31) {
- Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
- } else {
- Mask = (UINT32)0xFFFFFFFF;
- }
- Value &= ~(Mask << Lowbit);
- Value |= (Field & Mask) << Lowbit;
-
- if (Type == NB_ACCESS) {
- PciAddr.AddressValue = Address;
- LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
- if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) &&
- (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) {
- IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Highbit, Lowbit, Field);
- }
- } else if (Type == DCT_PHY_ACCESS) {
- MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
- Address |= DCT_ACCESS_WRITE;
- MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
- MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
- IDS_HDT_CONSOLE (MEM_SETREG, "~Fn2_%d9C_%x [%d:%d] = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Highbit, Lowbit, Field);
- } else if (Type == DCT_EXTRA) {
- MemNSetBitFieldNb (NBPtr, BFDctExtraDataReg, Value);
- Address |= DCT_ACCESS_WRITE;
- MemNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address);
- MemNPollBitFieldNb (NBPtr, BFDctExtraAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
- IDS_HDT_CONSOLE (MEM_SETREG, "~Fn2_%dF4_%x [%d:%d] = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Highbit, Lowbit, Field);
- } else {
- IDS_ERROR_TRAP;
- }
- if (IsLinked) {
- MemNCmnGetSetFieldHy (NBPtr, 1, FieldName + 1, Field >> (Highbit - Lowbit + 1));
- }
- } else {
- Value = Value >> Lowbit; // Shift
- // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
- if ((Highbit - Lowbit) != 31) {
- Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
- }
- if (IsLinked) {
- Value |= MemNCmnGetSetFieldHy (NBPtr, 0, FieldName + 1, 0) << (Highbit - Lowbit + 1);
- }
- }
- }
- } else {
- IDS_ERROR_TRAP; // Invalid bit field index
- }
- return Value;
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes bit field translation table
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] NBRegTable[] - Pointer to the bit field data structure
- *
- */
-
-VOID
-InitNBRegTableHy (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT TSEFO NBRegTable[]
- )
-{
- UINT16 i;
- for (i = 0; i < BFEndOfList; i++) {
- NBRegTable[i] = 0;
- }
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31, 0, BFDevVendorIDReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60), 2, 0, BFNodeID);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60), 6, 4, BFNodeCnt);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x48), 31, 0, BFDramBaseReg1);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x4C), 31, 0, BFDramLimitReg1);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x50), 31, 0, BFDramBaseReg2);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x54), 31, 0, BFDramLimitReg2);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x58), 31, 0, BFDramBaseReg3);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x5C), 31, 0, BFDramLimitReg3);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x60), 31, 0, BFDramBaseReg4);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x64), 31, 0, BFDramLimitReg4);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x68), 31, 0, BFDramBaseReg5);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x6C), 31, 0, BFDramLimitReg5);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x70), 31, 0, BFDramBaseReg6);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x74), 31, 0, BFDramLimitReg6);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x78), 31, 0, BFDramBaseReg7);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x7C), 31, 0, BFDramLimitReg7);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 0, BFDramHoleAddrReg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x140), 7, 0, BFDramBaseHiReg0);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x144), 7, 0, BFDramLimitHiReg0);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x148), 7, 0, BFDramBaseHiReg1);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x14C), 7, 0, BFDramLimitHiReg1);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x150), 7, 0, BFDramBaseHiReg2);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x154), 7, 0, BFDramLimitHiReg2);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x158), 7, 0, BFDramBaseHiReg3);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x15C), 7, 0, BFDramLimitHiReg3);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x160), 7, 0, BFDramBaseHiReg4);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x164), 7, 0, BFDramLimitHiReg4);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x168), 7, 0, BFDramBaseHiReg5);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x16C), 7, 0, BFDramLimitHiReg5);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x170), 7, 0, BFDramBaseHiReg6);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x174), 7, 0, BFDramLimitHiReg6);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x178), 7, 0, BFDramBaseHiReg7);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x17C), 7, 0, BFDramLimitHiReg7);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 24, BFDramHoleBase);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 15, 7, BFDramHoleOffset);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 1, 1, BFDramMemHoistValid);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 0, 0, BFDramHoleValid);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 20, 0, BFDramBaseAddr);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x120), 23, 21, BFDramIntlvSel);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 20, 0, BFDramLimitAddr);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x124), 26, 21, BFDramIntlvEn);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31, 0, BFCSBaseAddr0Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31, 0, BFCSBaseAddr1Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31, 0, BFCSBaseAddr2Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31, 0, BFCSBaseAddr3Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x50), 31, 0, BFCSBaseAddr4Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x54), 31, 0, BFCSBaseAddr5Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x58), 31, 0, BFCSBaseAddr6Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x5C), 31, 0, BFCSBaseAddr7Reg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31, 0, BFCSMask0Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31, 0, BFCSMask1Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x68), 31, 0, BFCSMask2Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x6C), 31, 0, BFCSMask3Reg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 0, BFDramControlReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 0, BFDramInitRegReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31, 0, BFDramBankAddrReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31, 0, BFDramMRSReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 0, BFDramTimingLoReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 0, BFDramTimingHiReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31, 0, BFDramConfigLoReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 0, BFDramConfigHiReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 0, BFDctAddlOffsetReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31, 0, BFDctAddlDataReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 31, BFDctAccessDone);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA0), 31, 0, BFDramConfigMiscReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 31, 0, BFDramCtrlMiscReg2);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF0), 31, 0, BFDctExtraOffsetReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF4), 31, 0, BFDctExtraDataReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF0), 31, 31, BFDctExtraAccessDone);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 31, 0, BFMctCfgHiReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 31, 0, BFMctCfgLoReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 31, 0, BFExtMctCfgLoReg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x40), 31, 0, BFMcaNbCtlReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44), 22, 22, BFDramEccEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x44), 2, 2, BFSyncOnUcEccEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x180), 25, 25, BFEccSymbolSize);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x48), 31, 0, BFMcaNbStatusLoReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x4C), 31, 0, BFMcaNbStatusHiReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 4, 0, BFDramScrub);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 12, 8, BFL2Scrub);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 20, 16, BFDcacheScrub);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x58), 28, 24, BFL3Scrub);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C), 0, 0, BFScrubReDirEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x5C), 31, 0, BFScrubAddrLoReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x60), 31, 0, BFScrubAddrHiReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x8C), 4, 4, BFDisDatMsk);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4), 4, 0, BFNbFid);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4), 13, 13, BFMTC1eEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 25, 25, BFL3Capable);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x188), 8, 8, BFDisableL3);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 8, BFNonSPDHi);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 3, 0, BFRdPtrInit);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 9, 8, BFTwrrdHi);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 11, 10, BFTwrwrHi);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 12, BFTrdrdHi);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 16, 16, BFAltVidC3MemClkTriEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 18, 18, BFDqsRcvEnTrain);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 19, 19, BFEarlyArbEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15, 0, BFMrsAddress);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 18, 16, BFMrsBank);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 22, 20, BFMrsChipSel);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 24, 24, BFSendPchgAll);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 25, 25, BFSendAutoRefresh);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 30, 30, BFSendCtrlWord);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 7, 7, BFMrsLevel);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 12, 12, BFMrsQoff);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 1, 0, BFBurstCtrl);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 3, 2, BFDrvImpCtrl);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 9, 7, BFDramTerm_DDR3);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 11, 10, BFDramTermDyn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 13, 13, BFQoff);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 18, 18, BFASR);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 19, 19, BFSRT);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 22, 20, BFTcwl);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 23, 23, BFPchgPDModeSel);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 6, 4, BFTwrDDR3);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 3, 0, BFTcl);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 6, 4, BFTrcd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 9, 7, BFTrp);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 11, 10, BFTrtp);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 15, 12, BFTras);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 20, 16, BFTrc);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 21, 20, BFTwr);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 23, 22, BFTrrd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 24, BFMemClkDis);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 0, BFNonSPD);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 3, 0, BFTrwtWB);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 7, 4, BFTrwtTO);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 9, 8, BFTwtr);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 11, 10, BFTwrrd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 13, 12, BFTwrwr);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 14, BFTrdrd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 17, 16, BFTref);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 22, 20, BFTrfc0);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 25, 23, BFTrfc1);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 28, 26, BFTrfc2);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 29, BFTrfc3);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 0, 0, BFInitDram);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 1, 1, BFExitSelfRef);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 5, 4, BFDramTerm);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 8, 8, BFParEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 10, 10, BFBurstLength32);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 11, 11, BFWidth128);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 15, 12, BFX4Dimm);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 16, 16, BFUnBuffDimm);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 17, 17, BFEnterSelfRef);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 19, 19, BFDimmEccEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 23, 23, BFForceAutoPchg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 27, 27, BFDisDllShutdownSR);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 2, 0, BFMemClkFreq);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 3, 3, BFMemClkFreqVal);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 8, 8, BFDdr3Mode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 9, 9, BFLegacyBiosMode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 12, 12, BFRDqsEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 15, 15, BFPowerDownEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 16, 16, BFPowerDownMode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 17, 17, BFFourRankSoDimm);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 19, 19, BFDcqArbBypassEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 18, 18, BFFourRankRDimm);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 20, 20, BFSlowAccessMode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 21, 21, BFFreqChgInProg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 22, 22, BFBankSwizzleMode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 27, 24, BFDcqBypassMax);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 28, BFFourActWindow);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 8, 8, BFODTSEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 14, 12, BFCmdThrottleMode);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 2, 2, BFDdr3FourSocketCh);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 5, 5, BFSubMemclkRegDly);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 6, 6, BFOdtSwizzle);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 7, 7, BFProgOdtEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 15, 8, BFCtrlWordCS);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 18, 16, BFDataTxFifoWrDly);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 0, 0, BFDctSelHiRngEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 1, 1, BFDctSelHi);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 2, 2, BFDctSelIntLvEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 3, 3, BFMemClrInit);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 4, 4, BFDctGangEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 5, 5, BFDctDatIntLv);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 7, 6, BFDctSelIntLvAddr);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 8, 8, BFDramEnabled);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 9, 9, BFMemClrBusy);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 10, 10, BFMemCleared);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 31, 11, BFDctSelBaseAddr);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 31, 10, BFDctSelBaseOffset);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 1, 0, BFDctWrLimit);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 6, 2, BFMctWrLimit);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 11, 7, BFMctPrefReqLimit);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 12, 12, BFPrefCpuDis);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 13, 13, BFPrefIoDis);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 28, 28, BFPrefDramTrainMode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 30, 30, BFFlushWr);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 29, 29, BFFlushWrOnStpGnt);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 1, 0, BFAdapPrefMissRatio);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 3, 2, BFAdapPrefPosStep);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 5, 4, BFAdapPrefNegStep);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1B0), 10, 8, BFCohPrefPrbLmt);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xB0), 31, 0, BFOnLineSpareControl);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 7, 5, BFDdrMaxRate);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 9, 8, BFAddrCmdDrvStren);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 17, 16, BFDataDrvStren);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31, 0, BFODCControl);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31, 0, BFAddrTmgControl);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 0, 0, BFWrtLvTrEn);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 1, 1, BFWrtLvTrMode);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 3, 3, BFPhyFenceTrEn);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 5, 4, BFTrDimmSel);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11, 8, BFWrLvOdt);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 13, 13, BFDqsRcvTrEn);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 30, 30, BFDisAutoComp);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x53, 8, 0, BFWrtLvErr);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 27, 25, BFD3Cmp2PCal);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 22, 20, BFD3Cmp2NCal);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 17, 15, BFD3Cmp1PCal);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 12, 10, BFD3Cmp1NCal);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 7, 5, BFD3Cmp0PCal);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0A, 2, 0, BFD3Cmp0NCal);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 20, 16, BFPhyFence);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 13, 12, BFCKETri);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 11, 8, BFODTTri);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 7, 0, BFChipSelTri);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x602, 31, 0, BFUSPLLCtlAll);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x603, 31, 0, BFDSPLLCtlAll);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x606, 0, 0, BFUSNibbleAlignEn);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x690, 2, 2, BFChnLinitClkEn);
-
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x180, 31, 0, BFPhyRODTCSLow);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x181, 31, 0, BFPhyRODTCSHigh);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x182, 31, 0, BFPhyWODTCSLow);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x183, 31, 0, BFPhyWODTCSHigh);
-
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x06, 3, 0, BFTrdrdSD);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x16, 3, 0, BFTwrwrSD);
-
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 31, 30, BFTSLinkSelect);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 9, 9, BFTS2BitLockEn);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 8, 8, BFTS2En);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 4, 4, BFTS1En);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 1, 1, BFTS0LinkStarEn);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800000, 0, 0, BFTS0En);
-
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800002, 15, 0, BFLinkTrainData);
-
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800010, 17, 17, BFRstRxFifoPtrs);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800010, 16, 16, BFRxFifoPtrInit);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800010, 1, 1, BFRstTxFifoPtrs);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800010, 0, 0, BFTxFifoPtrInit);
-
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800012, 31, 24, BFLpbkCount);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800012, 21, 20, BFLpbkMap);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800012, 16, 16, BFSendLpbkMaintCmd);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800012, 15, 0, BFLpbkData);
-
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800014, 20, 16, BFMbRdPtrEn);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800014, 9, 4, BFLnkLpBkLat);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800014, 1, 1, BFLpbkRndTripLatDone);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800014, 0, 0, BFLnkLatTrainEn);
-
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800020, 1, 1, BFDsPhyReset);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x800020, 0, 0, BFLinkReset);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D040F30, _NOT_USED_, _NOT_USED_, BFErr263);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F0C, _NOT_USED_, _NOT_USED_, BFErr350);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F0013, _NOT_USED_, _NOT_USED_, BFEccDLLConf);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F0830, _NOT_USED_, _NOT_USED_, BFEccDLLPwrDnConf);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F11, _NOT_USED_, _NOT_USED_, BFPhy0x0D080F11);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D080F10, _NOT_USED_, _NOT_USED_, BFPhy0x0D080F10);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D088F30, _NOT_USED_, _NOT_USED_, BFPhy0x0D088F30);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D08C030, _NOT_USED_, _NOT_USED_, BFPhy0x0D08C030);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D082F30, _NOT_USED_, _NOT_USED_, BFPhy0x0D082F30);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2030, _NOT_USED_, _NOT_USED_, BFPhyClkConfig0);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2130, _NOT_USED_, _NOT_USED_, BFPhyClkConfig1);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2230, _NOT_USED_, _NOT_USED_, BFPhyClkConfig2);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0F2330, _NOT_USED_, _NOT_USED_, BFPhyClkConfig3);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D08E000, _NOT_USED_, _NOT_USED_, BFErr322I);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D02E001, _NOT_USED_, _NOT_USED_, BFErr322II);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0FE006, _NOT_USED_, _NOT_USED_, BFPhyPLLLockTime);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D0FE007, _NOT_USED_, _NOT_USED_, BFPhyDLLLockTime);
-
- LINK_TSEFO (NBRegTable, BFTwrrd, BFTwrrdHi);
- LINK_TSEFO (NBRegTable, BFTwrwr, BFTwrwrHi);
- LINK_TSEFO (NBRegTable, BFTrdrd, BFTrdrdHi);
-
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/NI/mnNi.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/NI/mnNi.c
deleted file mode 100644
index 4736fa8..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/NI/mnNi.c
+++ /dev/null
@@ -1,495 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnNi.c
- *
- * Common Northbridge functions for Nile
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/NI)
- * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mnda.h"
-#include "mnNi.h"
-#include "mu.h"
-#include "S3.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "heapManager.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_NI_MNNI_FILECODE
-
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-#define SPLIT_CHANNEL (UINT32) 0x20000000
-#define CHANNEL_SELECT (UINT32) 0x10000000
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the northbridge block
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
- * @param[in] *FeatPtr - Pointer to the MEM_FEAT_BLOCK_NB
- * @param[in] *SharedPtr - Pointer to the MEM_SHARED_DATA
- * @param[in] NodeID - UINT8 indicating node ID of the NB object.
- *
- * @return Boolean indicating that this is the correct memory
- * controller type for the node number that was passed in.
- */
-
-BOOLEAN
-MemConstructNBBlockNi (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN MEM_FEAT_BLOCK_NB *FeatPtr,
- IN MEM_SHARED_DATA *SharedPtr,
- IN UINT8 NodeID
- )
-{
- UINT8 Dct;
- UINT8 Channel;
- UINT8 SpdSocketIndex;
- UINT8 SpdChannelIndex;
- DIE_STRUCT *MCTPtr;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
- //
- // Determine if this is the expected NB Type
- //
- GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
- if (!MemNIsIdSupportedDA (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
- return FALSE;
- }
-
- NBPtr->MemPtr = MemPtr;
- NBPtr->RefPtr = MemPtr->ParameterListPtr;
- NBPtr->SharedPtr = SharedPtr;
-
- MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
- NBPtr->MCTPtr = MCTPtr;
- NBPtr->MCTPtr->NodeId = NodeID;
- NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue;
- NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
-
- //
- // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
- //
- AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_DA * (
- sizeof (DCT_STRUCT) + (
- MAX_CHANNELS_PER_DCT_DA * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))
- )
- );
- AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0);
- AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
- if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) {
- PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader);
- SetMemError (AGESA_FATAL, MCTPtr);
- return FALSE;
- }
-
- MCTPtr->DctCount = MAX_DCTS_PER_NODE_DA;
- MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_DA * sizeof (DCT_STRUCT);
- for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
- MCTPtr->DctData[Dct].Dct = Dct;
- MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_DA;
- MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr;
- MCTPtr->DctData[Dct].ChData[0].Dct = Dct;
- AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_DA * sizeof (CH_DEF_STRUCT);
- }
- NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr;
-
- //
- // Initialize Socket List
- //
- for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
- MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr[Dct] = &(MCTPtr->DctData[Dct].ChData[0]);
- MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr[Dct] = &(MCTPtr->DctData[Dct].Timings);
- MCTPtr->DctData[Dct].ChData[0].ChannelID = Dct;
- }
-
- MemNInitNBDataNi (NBPtr);
-
- FeatPtr->InitCPG (NBPtr);
- NBPtr->FeatPtr = FeatPtr;
- FeatPtr->InitHwRxEn (NBPtr);
-
- //
- // Calculate SPD Offsets per channel and assign pointers to the data. At this point, we calculate the Node-Dct-Channel
- // centric offsets and store the pointers to the first DIMM of each channel in the Channel Definition struct for that
- // channel. This pointer is then used later to calculate the offsets to be used for each logical dimm once the
- // dimm types(QR or not) are known. This is done in the Technology block constructor.
- //
- // Calculate the SpdSocketIndex separately from the SpdChannelIndex.
- // This will facilitate modifications due to some processors that might
- // map the DCT-CHANNEL differently.
- //
- SpdSocketIndex = GetSpdSocketIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, &MemPtr->StdHeader);
- //
- // Traverse the Dct/Channel structures
- //
- for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
- for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_DA; Channel++) {
- //
- // Calculate the number of Dimms on this channel using the
- // die/dct/channel to Socket/channel conversion.
- //
- SpdChannelIndex = GetSpdChannelIndex (NBPtr->RefPtr->PlatformMemoryConfiguration,
- NBPtr->MCTPtr->SocketId,
- MemNGetSocketRelativeChannelNb (NBPtr, Dct, Channel),
- &MemPtr->StdHeader);
- NBPtr->MCTPtr->DctData[Dct].ChData[Channel].SpdPtr = &(MemPtr->SpdDataStructure[SpdSocketIndex + SpdChannelIndex]);
- }
- }
-
- MemNSwitchDCTNb (NBPtr, 0);
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initializes member functions and variables of NB block.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNInitNBDataNi (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- INT32 i;
-
- NBPtr->DctCachePtr = NBPtr->DctCache;
- NBPtr->PsPtr = NBPtr->PSBlock;
-
- InitNBRegTableDA (NBPtr, NBPtr->NBRegTable);
- NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
- NBPtr->Dct = 0;
- NBPtr->Channel = 0;
- NBPtr->DctCount = MAX_DCTS_PER_NODE_DA;
- NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_DA;
- NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA;
- NBPtr->Ganged = FALSE;
- NBPtr->PosTrnPattern = POS_PATTERN_72B;
- NBPtr->MemCleared = FALSE;
- NBPtr->StartupSpeed = DDR800_FREQUENCY;
- NBPtr->RcvrEnDlyLimit = 0xFF;
- NBPtr->DefDctSelIntLvAddr = 3;
-
- for (i = 0; i < EnumSize; i++) {
- NBPtr->IsSupported[i] = FALSE;
- }
-
- LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader);
-
- NBPtr->SetMaxLatency = MemNSetMaxLatencyNb;
- NBPtr->getMaxLatParams = MemNGetMaxLatParamsNb;
- NBPtr->GetSysAddr = MemNGetMCTSysAddrNb;
- NBPtr->InitializeMCT = MemNInitializeMctDA;
- NBPtr->FinalizeMCT = MemNFinalizeMctDA;
- NBPtr->SendMrsCmd = MemNSendMrsCmdDA;
- NBPtr->sendZQCmd = MemNSendZQCmdNb;
- NBPtr->WritePattern = MemNWritePatternDA;
- NBPtr->ReadPattern = MemNReadPatternDA;
- NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK*, UINT32)) memDefRet;
- NBPtr->CompareTestPattern = MemNCompareTestPatternNb;
- NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb;
- NBPtr->StitchMemory = MemNStitchMemoryNb;
- NBPtr->AutoConfig = memNAutoConfigDA;
- NBPtr->PlatformSpec = MemNPlatformSpecNb;
- NBPtr->InitMCT = MemNInitMCTNb;
- NBPtr->DisableDCT = MemNDisableDCTNb;
- NBPtr->StartupDCT = MemNStartupDCTNb;
- NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb;
- NBPtr->ChangeFrequency = MemNChangeFrequencyNb;
- NBPtr->RampUpFrequency = MemNRampUpFrequencyNb;
- NBPtr->ChangeNbFrequency = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefFalse;
- NBPtr->ProgramCycTimings = MemNProgramCycTimingsNb;
- NBPtr->SyncDctsReady = MemNSyncDctsReadyNb;
- NBPtr->HtMemMapInit = MemNHtMemMapInitNb;
- NBPtr->SyncAddrMapToAllNodes = MemNSyncAddrMapToAllNodesNb;
- NBPtr->CpuMemTyping = MemNCPUMemTypingNb;
- NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingNb;
- NBPtr->AfterDqsTraining = (VOID (*) (MEM_NB_BLOCK*)) memDefRet;
- NBPtr->OtherTiming = MemNOtherTimingDA;
- NBPtr->UMAMemTyping = MemNUMAMemTypingNb;
- NBPtr->TechBlockSwitch = MemNTechBlockSwitchNb;
- NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA;
- NBPtr->SetEccSymbolSize = (VOID (*) (MEM_NB_BLOCK*)) memDefRet;
- NBPtr->TrainingFlow = MemNTrainingFlowNb;
- NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb;
- MemNInitNBDataNb (NBPtr);
- NBPtr->PollBitField = MemNPollBitFieldNb;
- NBPtr->BrdcstCheck = MemNBrdcstCheckNb;
- NBPtr->BrdcstSet = MemNBrdcstSetNb;
- NBPtr->GetTrainDly = MemNGetTrainDlyNb;
- NBPtr->SetTrainDly = MemNSetTrainDlyNb;
- NBPtr->PhyFenceTraining = MemNPhyFenceTrainingNb;
- NBPtr->GetSysAddr = MemNGetMCTSysAddrNb;
- NBPtr->RankEnabled = MemNRankEnabledNb;
- NBPtr->MemPPhyFenceTrainingNb = MemNTrainPhyFenceNb;
- NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitNi;
- NBPtr->MemNBeforePlatformSpecNb = MemNBeforePlatformSpecDA;
- NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyNb;
- NBPtr->MemPNodeMemBoundaryNb = MemPNodeMemBoundaryDA;
- NBPtr->MemNInitPhyComp = MemNInitPhyCompNb;
- NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb;
- NBPtr->MemNBeforeDramInitNb = MemNBeforeDramInitDA;
- NBPtr->MemNPFenceAdjustNb = (VOID (*) (MEM_NB_BLOCK *, UINT16 *)) memDefRet;
- NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsNb;
- NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb;
- NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb;
- NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb;
- NBPtr->CSPerChannel = MemNCSPerChannelNb;
- NBPtr->CSPerDelay = MemNCSPerDelayNb;
- NBPtr->FlushPattern = MemNFlushPatternNb;
- NBPtr->GetUmaSize = MemNGetUmaSizeNb;
- NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdNb;
- NBPtr->MemNCapSpeedBatteryLife = MemNCapSpeedBatteryLifeDA;
- NBPtr->EnableSwapIntlvRgn = MemNEnableSwapIntlvRgnNb;
- NBPtr->WaitXMemClks = MemNWaitXMemClksNb;
- NBPtr->MemNGetDramTerm = MemNGetDramTermNb;
- NBPtr->MemNGetDynDramTerm = MemNGetDynDramTermNb;
- NBPtr->MemNGetMR0CL = MemNGetMR0CLNb;
- NBPtr->MemNGetMR0WR = MemNGetMR0WRNb;
- NBPtr->MemNGetMR2CWL = MemNGetMR2CWLNb;
- NBPtr->AllocateC6Storage = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
-
- NBPtr->IsSupported[SetSpareEn] = TRUE;
- NBPtr->IsSupported[CheckSpareEn] = TRUE;
- NBPtr->IsSupported[SetDllShutDown] = TRUE;
- NBPtr->IsSupported[DimmBasedOnSpeed] = TRUE;
- NBPtr->IsSupported[CheckMaxDramRate] = TRUE;
- NBPtr->IsSupported[Check1GAlign] = TRUE;
- NBPtr->IsSupported[CheckMaxRdDqsDlyPtr] = TRUE;
- NBPtr->IsSupported[CheckPhyFenceTraining] = TRUE;
- NBPtr->IsSupported[CheckGetMCTSysAddr] = TRUE;
- NBPtr->IsSupported[CheckFindPSDct] = TRUE;
- NBPtr->IsSupported[CheckDllStdBy] = TRUE;
- NBPtr->IsSupported[CheckSlewWithMarginImprv] = TRUE;
- NBPtr->IsSupported[CheckDllSpeedUp] = TRUE;
- NBPtr->IsSupported[CheckDllRegDis] = TRUE;
- NBPtr->IsSupported[ForceEnMemHoleRemapping] = TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the default values in the MEM_DATA_STRUCT
- *
- * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
- *
- */
-VOID
-MemNInitDefaultsNi (
- IN OUT MEM_DATA_STRUCT *MemPtr
- )
-{
- UINT8 Socket;
- UINT8 Channel;
- MEM_PARAMETER_STRUCT *RefPtr;
- ASSERT (MemPtr != NULL);
- RefPtr = MemPtr->ParameterListPtr;
-
- // Memory Map/Mgt.
- // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB
- RefPtr->BottomIo = 0xE0;
- RefPtr->UmaMode = UserOptions.CfgUmaMode;
- RefPtr->UmaSize = UserOptions.CfgUmaSize;
- RefPtr->MemHoleRemapping = TRUE;
-
- // Dram Timing
- RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect;
- RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect;
- for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) {
- for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) {
- MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL;
- MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL;
- }
- }
-
- // Memory Clear
- RefPtr->EnableMemClr = TRUE;
-
- // TableBasedAlterations
- RefPtr->TableBasedAlterations = NULL;
-
- // Platform config table
- RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration;
-
- // Memory Restore
- RefPtr->MemRestoreCtl = FALSE;
- RefPtr->SaveMemContextCtl = FALSE;
- AmdS3ParamsInitializer (&RefPtr->MemContext);
-
- // Dram Configuration
- RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving;
- RefPtr->EnableNodeIntlv = UserOptions.CfgMemoryEnableNodeInterleaving;
- RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving;
- RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle;
- RefPtr->EnableParity = UserOptions.CfgMemoryParityEnable;
- RefPtr->EnableOnLineSpareCtl = UserOptions.CfgOnlineSpare;
-
- // Dram Power
- RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown;
-
- // ECC
- RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- *
- * This function writes training pattern
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Pattern[] - Pattern to write
- * @param[in] Address - System Address [47:16]
- * @param[in] ClCount - Number of cache lines
- *
- */
-
-VOID
-MemNWritePatternNi (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 Address,
- IN UINT8 Pattern[],
- IN UINT16 ClCount
- )
-{
- Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
- MemUWriteCachelines (Address, Pattern, ClCount);
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- *
- * This function reads training pattern
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Buffer[] - Buffer to fill
- * @param[in] Address - System Address [47:16]
- * @param[in] ClCount - Number of cache lines
- *
- */
-
-VOID
-MemNReadPatternNi (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Buffer[],
- IN UINT32 Address,
- IN UINT16 ClCount
- )
-{
- Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
- MemUReadCachelines (Buffer, Address, ClCount);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initiates DQS training for Server NB
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-BOOLEAN
-memNEnableTrainSequenceNi (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- BOOLEAN Retval;
- Retval = TRUE;
- if (!MemNIsIdSupportedDA (NBPtr, &(NBPtr->MemPtr->DiesPerSystem[NBPtr->MCTPtr->NodeId].LogicalCpuid))) {
- Retval = FALSE;
- }
- return Retval;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/NI/mnNi.h b/src/vendorcode/amd/agesa/Proc/Mem/NB/NI/mnNi.h
deleted file mode 100644
index 08a9da3..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/NI/mnNi.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnNi.h
- *
- * Northbridge Ni for Nile
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem)
- * @e \$Revision: 36462 $ @e \$Date: 2010-08-20 00:49:49 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MNNI_H_
-#define _MNNI_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-MemConstructNBBlockNi (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN MEM_FEAT_BLOCK_NB *FeatPtr,
- IN MEM_SHARED_DATA *SharedPtr,
- IN UINT8 NodeID
- );
-
-VOID
-MemNInitNBDataNi (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNInitDefaultsNi (
- IN OUT MEM_DATA_STRUCT *MemPtr
- );
-
-VOID
-MemNWritePatternNi (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 Address,
- IN UINT8 Pattern[],
- IN UINT16 ClCount
- );
-
-VOID
-MemNReadPatternNi (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Buffer[],
- IN UINT32 Address,
- IN UINT16 ClCount
- );
-
-BOOLEAN
-memNEnableTrainSequenceNi (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-#endif /* _MNNI_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/NI/mnS3Ni.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/NI/mnS3Ni.c
deleted file mode 100644
index c366760..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/NI/mnS3Ni.c
+++ /dev/null
@@ -1,747 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mns3Ni.c
- *
- * Ni memory specific function to support S3 resume
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/NI)
- * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "S3.h"
-#include "mfs3.h"
-#include "mnda.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "mnS3Ni.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_NI_MNS3NI_FILECODE
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-UINT16
-STATIC
-MemNS3GetRegLstPtrNi (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT DESCRIPTOR_GROUP *DescriptPtr
- );
-
-AGESA_STATUS
-STATIC
-MemNS3GetDeviceRegLstNi (
- IN UINT32 RegisterLstID,
- OUT VOID **RegisterHeader
- );
-
-VOID
-STATIC
-MemNS3SetSpecialPCIRegNi (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR Address,
- IN VOID *Value,
- IN OUT VOID *ConfigPtr
- );
-
-VOID
-STATIC
-MemNS3ExitSelfRefRegNi (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-PCI_SPECIAL_CASE PciSpecialCaseFuncNi[] = {
- {MemNS3GetCSRNb, MemNS3SetCSRNb},
- {MemNS3GetCSRNb, MemNS3SetSpecialPCIRegNi},
- {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb}
-};
-
-PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorNi[] = {
- {{0, 0, 0}, FUNC_2, 0x110, 0xFFFFFFFF},
- {{0, 0, 0}, FUNC_1, 0x40, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x48, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x50, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x58, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x60, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x68, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x70, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x78, 0xFFFF3F03},
- {{0, 1, 0}, FUNC_1, 0x140, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x148, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x150, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x158, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x160, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x168, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x170, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x178, 0x000000FF},
- {{0, 0, 0}, FUNC_1, 0x44, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x4C, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x54, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x5C, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x64, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x6C, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x74, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x7C, 0xFFFF07FF},
- {{0, 1, 0}, FUNC_1, 0x144, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x14C, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x154, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x15C, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x164, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x16C, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x174, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x17C, 0x000000FF},
- {{0, 0, 0}, FUNC_1, 0xF0, 0xFF00FF83},
- {{0, 0, 0}, FUNC_1, 0x120, 0x00FFFFFF},
- {{0, 0, 0}, FUNC_1, 0x124, 0x07FFFFFF},
- {{0, 0, 0}, FUNC_2, 0x10C, 0x07F3FBF9},
- {{0, 0, 0}, FUNC_2, 0x114, 0xFFFFFC00},
- {{0, 0, 0}, FUNC_2, 0x118, 0xF773FFFF},
- {{0, 0, 0}, FUNC_2, 0x11C, 0xFFFFFFFF},
- {{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F}
-};
-
-CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefNi = {
- 0,
- (sizeof (S3PciPreSelfRefDescriptorNi) / sizeof (PCI_REG_DESCRIPTOR)),
- S3PciPreSelfRefDescriptorNi,
- NULL
-};
-
-CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorNi[] = {
- // DCT 0
- {{0, 0, 0}, FUNC_2, 0x40, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x44, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x48, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x4C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x50, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x54, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x58, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x5C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x60, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x64, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x68, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x6C, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x78, 0xFFCDBF0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x7C, 0xFFF7FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 2, 0}, FUNC_2, 0x80, 0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x84, 0x07FFEFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x88, 0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x8C, 0xFFFF7FFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x90, 0x00FFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0xA8, 0x0007FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), 0x30333333, DCT0_MASK, ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0x3FFFFFFF, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), 0x001FBFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), 0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhyClkConfig0, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhyClkConfig1, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhyClkConfig2, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhyClkConfig3, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- //errata 322
- {{2, 2, 1}, DCT0, BFErr322I, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFErr322II, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- //errata 263
- {{2, 2, 1}, DCT0, BFErr263, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- // Dll regulator disable
- {{2, 2, 1}, DCT0, BFPhy0x0D040F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhy0x0D042F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhy0x0D048F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhy0x0D04DF3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-
- // DCT 1
- {{0, 0, 0}, FUNC_2, 0x140, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x144, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x148, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x14C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x150, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x154, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x158, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x15C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x160, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x164, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x168, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x16C, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x178, 0xFFCDBF0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x17C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 2, 0}, FUNC_2, 0x180, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x184, 0x07FFEFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x188, 0xFFFFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x18C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x190, 0x00FFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x1A8, 0x0007FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), 0x30333333, DCT1_MASK, ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x001FBFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyClkConfig0, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyClkConfig1, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyClkConfig2, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyClkConfig3, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- // errata 322
- {{2, 2, 1}, DCT1, BFErr322I, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFErr322II, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- // errata 263
- {{2, 2, 1}, DCT1, BFErr263, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- // Dll regulator disable
- {{2, 2, 1}, DCT1, BFPhy0x0D040F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhy0x0D042F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhy0x0D048F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhy0x0D04DF3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-
- // Restore F2x[1,0]94 right before exit self refresh
- {{0, 0, 0}, FUNC_2, 0x94, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x194, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK}
-};
-
-CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefNi = {
- 0,
- (sizeof (S3CPciPreSelfDescriptorNi) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
- S3CPciPreSelfDescriptorNi,
- PciSpecialCaseFuncNi
-};
-
-CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorNi[] = {
- // DCT0
- {{2, 2, 1}, DCT0, BFEccDLLPwrDnConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFEccDLLConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10), 0x01FF01FF, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11), 0x01FF01FF, DCT0_MASK, 0x01},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12), 0x000001FF, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13), 0x01FF01FF, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14), 0x01FF01FF, DCT0_MASK, 0x04},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15), 0x000001FF, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16), 0x01FF01FF, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17), 0x01FF01FF, DCT0_MASK, 0x10},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18), 0x000001FF, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19), 0x01FF01FF, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A), 0x01FF01FF, DCT0_MASK, 0x40},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B), 0x000001FF, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20), 0x01FF01FF, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21), 0x01FF01FF, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23), 0x01FF01FF, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24), 0x01FF01FF, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26), 0x01FF01FF, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27), 0x01FF01FF, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29), 0x01FF01FF, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A), 0x01FF01FF, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01), 0x7F7F7F7F, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02), 0x7F7F7F7F, DCT0_MASK, 0x01},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03), 0x0000007F, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0x7F7F7F7F, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0x7F7F7F7F, DCT0_MASK, 0x04},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x0000007F, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0x7F7F7F7F, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0x7F7F7F7F, DCT0_MASK, 0x10},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x0000007F, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0x7F7F7F7F, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0x7F7F7F7F, DCT0_MASK, 0x40},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x0000007F, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05), 0x3F3F3F3F, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06), 0x3F3F3F3F, DCT0_MASK, 0x01},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x07), 0x0000003F, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3F3F3F3F, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3F3F3F3F, DCT0_MASK, 0x04},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x107), 0x0000003F, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3F3F3F3F, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3F3F3F3F, DCT0_MASK, 0x10},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x207), 0x0000003F, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3F3F3F3F, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3F3F3F3F, DCT0_MASK, 0x40},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x307), 0x0000003F, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0xFFFFFFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D), 0x23772377, DCT0_MASK, ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30), 0x00FF00FF, DCT0_DDR3_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31), 0x00FF00FF, DCT0_DDR3_MASK, 0x01},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32), 0x000000FF, DCT0_DDR3_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33), 0x00FF00FF, DCT0_DDR3_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34), 0x00FF00FF, DCT0_DDR3_MASK, 0x04},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35), 0x000000FF, DCT0_DDR3_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36), 0x00FF00FF, DCT0_DDR3_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37), 0x00FF00FF, DCT0_DDR3_MASK, 0x10},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38), 0x000000FF, DCT0_DDR3_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39), 0x00FF00FF, DCT0_DDR3_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B), 0x000000FF, DCT0_DDR3_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40), 0x00FF00FF, DCT0_DDR3_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41), 0x00FF00FF, DCT0_DDR3_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43), 0x00FF00FF, DCT0_DDR3_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44), 0x00FF00FF, DCT0_DDR3_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46), 0x00FF00FF, DCT0_DDR3_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47), 0x00FF00FF, DCT0_DDR3_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49), 0x00FF00FF, DCT0_DDR3_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40},
- {{2, 2, 1}, DCT0, BFPhy0x0D0F0F13, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhy0x0D0F0830, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhy0x0D07812F, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhyDLLControl, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-
- // DCT1
- {{2, 2, 1}, DCT1, BFEccDLLPwrDnConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFEccDLLConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10), 0x01FF01FF, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11), 0x01FF01FF, DCT1_MASK, 0x02},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x12), 0x000001FF, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13), 0x01FF01FF, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14), 0x01FF01FF, DCT1_MASK, 0x08},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x15), 0x000001FF, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x16), 0x01FF01FF, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x17), 0x01FF01FF, DCT1_MASK, 0x20},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x18), 0x000001FF, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x19), 0x01FF01FF, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1A), 0x01FF01FF, DCT1_MASK, 0x80},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1B), 0x000001FF, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20), 0x01FF01FF, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21), 0x01FF01FF, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23), 0x01FF01FF, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24), 0x01FF01FF, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x26), 0x01FF01FF, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x27), 0x01FF01FF, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x29), 0x01FF01FF, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x2A), 0x01FF01FF, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01), 0x7F7F7F7F, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02), 0x7F7F7F7F, DCT1_MASK, 0x02},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x03), 0x0000007F, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101), 0x7F7F7F7F, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102), 0x7F7F7F7F, DCT1_MASK, 0x08},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x103), 0x0000007F, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x201), 0x7F7F7F7F, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x202), 0x7F7F7F7F, DCT1_MASK, 0x20},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x203), 0x0000007F, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x301), 0x7F7F7F7F, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x302), 0x7F7F7F7F, DCT1_MASK, 0x80},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x303), 0x0000007F, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05), 0x3F3F3F3F, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06), 0x3F3F3F3F, DCT1_MASK, 0x02},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x07), 0x0000003F, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105), 0x3F3F3F3F, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106), 0x3F3F3F3F, DCT1_MASK, 0x08},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x107), 0x0000003F, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x205), 0x3F3F3F3F, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x206), 0x3F3F3F3F, DCT1_MASK, 0x20},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x207), 0x0000003F, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x305), 0x3F3F3F3F, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x306), 0x3F3F3F3F, DCT1_MASK, 0x80},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x307), 0x0000003F, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D), 0x23772377, DCT1_MASK, ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30), 0x00FF00FF, DCT1_DDR3_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31), 0x00FF00FF, DCT1_DDR3_MASK, 0x02},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x32), 0x000000FF, DCT1_DDR3_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33), 0x00FF00FF, DCT1_DDR3_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34), 0x00FF00FF, DCT1_DDR3_MASK, 0x08},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x35), 0x000000FF, DCT1_DDR3_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x36), 0x00FF00FF, DCT1_DDR3_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x37), 0x00FF00FF, DCT1_DDR3_MASK, 0x20},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x38), 0x000000FF, DCT1_DDR3_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x39), 0x00FF00FF, DCT1_DDR3_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3B), 0x000000FF, DCT1_DDR3_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40), 0x00FF00FF, DCT1_DDR3_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41), 0x00FF00FF, DCT1_DDR3_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43), 0x00FF00FF, DCT1_DDR3_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44), 0x00FF00FF, DCT1_DDR3_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x46), 0x00FF00FF, DCT1_DDR3_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x47), 0x00FF00FF, DCT1_DDR3_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x49), 0x00FF00FF, DCT1_DDR3_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x4A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80},
- {{2, 2, 1}, DCT1, BFPhy0x0D0F0F13, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhy0x0D0F0830, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhy0x0D07812F, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyDLLControl, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-
- // DllShutDown
- {{2, 2, 1}, DCT0, BFPhyPLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhyDLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 1, 1}, DCT0, BFDisDllShutdownSR, 0x00000001, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyPLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyDLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 1, 1}, DCT1, BFDisDllShutdownSR, 0x00000001, DCT1_MASK, ANY_DIMM_MASK},
-
- // Restore scrubber related registers after restoring training related registers
- {{0, 0, 0}, FUNC_3, 0x44, 0xFFFFFFFE, ANY_DIMM_MASK, ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_3, 0x58, 0x1F1F1F1F, ANY_DIMM_MASK, ANY_DIMM_MASK},
- {{2, 1, 1}, DCT0, BFScrubReDirEn, 0x00000001, ANY_DIMM_MASK, ANY_DIMM_MASK},
-};
-
-CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefNi = {
- 0,
- (sizeof (S3CPciPostSelfDescriptorNi) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
- S3CPciPostSelfDescriptorNi,
- PciSpecialCaseFuncNi
-};
-
-MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorNi[] = {
- {{0, 0, 0}, 0xC0010010, 0x00000000007F07FF},
- {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000},
- {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000},
- {{0, 0, 0}, 0xC001001F, 0xC047F87FFF527FFF}
-};
-
-CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefNi = {
- 0,
- (sizeof (S3MSRPreSelfRefDescriptorNi) / sizeof (MSR_REG_DESCRIPTOR)),
- S3MSRPreSelfRefDescriptorNi,
- NULL
-};
-
-VOID *MemS3RegListNi[] = {
- (VOID *)&S3PciPreSelfRefNi,
- NULL,
- (VOID *)&S3CPciPreSelfRefNi,
- (VOID *)&S3CPciPostSelfRefNi,
- (VOID *)&S3MSRPreSelfRefNi,
- NULL,
- NULL,
- NULL
-};
-
-CONST UINT16 ROMDATA SpecialCasePCIRegNi[] = {
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04)
-};
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the northbridge block for S3 resume
- *
- * @param[in,out] *S3NBPtr - Pointer to MEM_NB_BLOCK.
- * @param[in,out] *MemPtr - Pointer to MEM_DATA_STRUCT.
- * @param[in] NodeID - Node ID of the target node.
- *
- * @return BOOLEAN
- * TRUE - This is the correct constructor for the targeted node.
- * FALSE - This isn't the correct constructor for the targeted node.
- */
-BOOLEAN
-MemS3ResumeConstructNBBlockNi (
- IN OUT VOID *S3NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- )
-{
- INT32 i;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr;
-
- //
- // Determine if this is the expected NB Type
- //
- GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
- if (!MemNIsIdSupportedDA (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
- return FALSE;
- }
-
- NBPtr->MemPtr = MemPtr;
- NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
- NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
- InitNBRegTableDA (NBPtr, NBPtr->NBRegTable);
- NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
- NBPtr->Dct = 0;
- NBPtr->Channel = 0;
- NBPtr->Ganged = FALSE;
- NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA;
- NBPtr->DctCount = MAX_DCTS_PER_NODE_DA;
-
- for (i = 0; i < EnumSize; i++) {
- NBPtr->IsSupported[i] = FALSE;
- }
-
- for (i = 0; i < NumberOfHooks; i++) {
- NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) memDefTrue;
- }
-
- LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader);
-
- NBPtr->IsSupported[CheckDllSpeedUp] = TRUE;
- NBPtr->SwitchDCT = MemNSwitchDCTNb;
- NBPtr->SwitchChannel = MemNSwitchChannelNb;
- NBPtr->GetBitField = MemNGetBitFieldNb;
- NBPtr->SetBitField = MemNSetBitFieldNb;
- NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA;
- NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedDA;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = MemNS3ExitSelfRefRegNi;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskNb;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK*, DESCRIPTOR_GROUP*)) memDefRet;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeNb;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = MemNS3RestoreScrubNb;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrNi;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstNi;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = (sizeof (SpecialCasePCIRegNi) / sizeof (UINT16)) * sizeof (UINT32);
-
- MemNSwitchDCTNb (NBPtr, 0);
-
- return TRUE;
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------*/
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function returns the register list for each device for Ni
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP
- * @return UINT16 - size of the device descriptor on the target node.
- */
-UINT16
-STATIC
-MemNS3GetRegLstPtrNi (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT DESCRIPTOR_GROUP *DescriptPtr
- )
-{
- UINT8 i;
- UINT16 Size;
- Size = 0;
- for (i = PRESELFREF; i <= POSTSELFREF; i ++) {
- DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i);
- DescriptPtr->PCIDevice[i].Node = NBPtr->Node;
- DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF;
- if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListNi[PCI_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) {
- DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_DA + i;
- Size += sizeof (PCI_DEVICE_DESCRIPTOR);
- }
- DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i);
- DescriptPtr->CPCIDevice[i].Node = NBPtr->Node;
- DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF;
- if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListNi[CPCI_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) {
- DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_DA + i;
- Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR);
- }
- DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i);
- DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF;
- if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListNi[MSR_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) {
- DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_DA + i;
- Size += sizeof (MSR_DEVICE_DESCRIPTOR);
- }
- DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i);
- DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF;
- if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListNi[CMSR_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) {
- DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_DA + i;
- Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR);
- }
- }
- return Size;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function return the register list according to the register ID.
- *
- * @param[in] RegisterLstID - value of the Register list ID.
- * @param[out] **RegisterHeader - pointer to the address of the register list.
- * @return none
- */
-AGESA_STATUS
-STATIC
-MemNS3GetDeviceRegLstNi (
- IN UINT32 RegisterLstID,
- OUT VOID **RegisterHeader
- )
-{
- if (RegisterLstID >= (sizeof (MemS3RegListNi) / sizeof (VOID *))) {
- ASSERT(FALSE); // RegisterListID exceeded size of Register list
- return AGESA_FATAL;
- }
- if (MemS3RegListNi[RegisterLstID] != NULL) {
- *RegisterHeader = MemS3RegListNi[RegisterLstID];
- return AGESA_SUCCESS;
- }
- ASSERT(FALSE); // Device register list error
- return AGESA_FATAL;
-}
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function stores special case register on the heap.
- *
- * @param[in] AccessWidth - Access width of the register
- * @param[in] Address - address of the CSR register in PCI_ADDR format.
- * @param[in] *Value - Pointer to the value be read.
- * @param[in, out] *ConfigPtr - Pointer to Config handle.
- * @return none
- */
-VOID
-STATIC
-MemNS3SetSpecialPCIRegNi (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR Address,
- IN VOID *Value,
- IN OUT VOID *ConfigPtr
- )
-{
- LOCATE_HEAP_PTR LocateBufferPtr;
- UINT8 i;
- UINT8 NodeID;
- UINT8 Offset;
- S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader;
-
- Offset = 0;
- LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
- if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) {
- SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr;
- // Get the node ID of the target die.
- NodeID = (UINT8) (Address.Address.Device - 24);
- for (i = 0; i < MAX_NODES_SUPPORTED_DA; i ++) {
- if (SpecialHeapHeader[i].Node == NodeID) {
- // Get the offset in the heap for the target die.
- Offset = SpecialHeapHeader[i].Offset;
- break;
- }
- }
- ASSERT (i < MAX_NODES_SUPPORTED_DA);
- // Save the value in the heap at appropriate offset based on the index
- // of the target register in the special case array.
- if (Offset != 0) {
- for (i = 0; i < (sizeof (SpecialCasePCIRegNi) / sizeof (UINT16)); i ++) {
- if (SpecialCasePCIRegNi[i] == Address.Address.Register) {
- *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)) = *(UINT32 *) Value;
- }
- }
- }
- }
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function stores special case register on the heap.
- *
- * @param[in,out] *NBPtr - Pointer to the northbridge block.
- * @param[in,out] *StdHeader - Config handle for library and services.
- * @return none
- */
-VOID
-STATIC
-MemNS3ExitSelfRefRegNi (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- LOCATE_HEAP_PTR LocateBufferPtr;
- UINT8 i;
- PCI_ADDR PciAddr;
- UINT32 Value;
- UINT8 NodeID;
- UINT8 Offset;
- S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader;
-
- Offset = 0;
- PciAddr.Address.Device = NBPtr->PciAddr.Address.Device;
- PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus;
- PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment;
- PciAddr.Address.Function = 2;
- LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
- if (HeapLocateBuffer (&LocateBufferPtr, StdHeader) == AGESA_SUCCESS) {
- SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr;
- // Get the node ID of the target die.
- NodeID = (UINT8) (PciAddr.Address.Device - 24);
- for (i = 0; i < MAX_NODES_SUPPORTED_DA; i ++) {
- if (SpecialHeapHeader[i].Node == NodeID) {
- // Get the offset in the heap for the target die.
- Offset = SpecialHeapHeader[i].Offset;
- break;
- }
- }
- ASSERT (i < MAX_NODES_SUPPORTED_DA);
- // Restore the value one by one in the sequence of the special case register array.
- if (Offset != 0) {
- for (i = 0; i < (sizeof (SpecialCasePCIRegNi) / sizeof (UINT16)); i ++) {
- PciAddr.Address.Register = SpecialCasePCIRegNi[i];
- Value = *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2));
- MemNS3SetCSRNb (AccessS3SaveWidth32, PciAddr, &Value, StdHeader);
- }
- }
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/NI/mnS3Ni.h b/src/vendorcode/amd/agesa/Proc/Mem/NB/NI/mnS3Ni.h
deleted file mode 100644
index e96f314..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/NI/mnS3Ni.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnS3Ni.h
- *
- * S3 resume memory related function for Ni.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/NI)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MNS3DA_H_
-#define _MNS3DA_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-/// ID for register list of HY
-typedef enum {
- PCI_LST_ESR_DA, ///< Assign 0x0000 for PCI register list for pre exit self refresh.
- PCI_LST_DA, ///< Assign 0x0001 for PCI register list for post exist self refresh.
- CPCI_LST_ESR_DA, ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh.
- CPCI_LST_DA, ///< Assign 0x0003 for conditional PCI register list for post exit self refresh.
- MSR_LST_ESR_DA, ///< Assign 0x0004 for MSR register list for pre exit self refresh.
- MSR_LST_DA, ///< Assign 0x0005 for MSR register list for post exit self refresh.
- CMSR_LST_ESR_DA, ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh.
- CMSR_LST_DA, ///< Assign 0x0007 for conditional MSR register list for post exit self refresh.
-} RegisterListIDDA;
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-#endif //_MNS3DA_H_
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/NI/mnflowNi.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/NI/mnflowNi.c
deleted file mode 100644
index 8deb690..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/NI/mnflowNi.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnflowNi.c
- *
- * Deerhound initializer for MCT and DCT
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/NI)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mnda.h"
-#include "mnNi.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_NI_MNFLOWNI_FILECODE
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledNi[MAX_FF_TYPES];
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the platform specific block
- *
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - AGESA_SUCCESS at least one dorm factor was found
- * @return FALSE - AGESA_UNSUPPORTED - Error indicating that no form factors were found
- */
-
-BOOLEAN
-MemNPlatformSpecificFormFactorInitNi (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 Dct;
- UINT8 f;
- UINT8 ErrUnSuppFFCount;
- for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- if (NBPtr->ChannelPtr->ChDimmValid != 0) {
- ErrUnSuppFFCount = 0;
- for (f = 0; f < MAX_FF_TYPES; f++) {
- ASSERT (memPlatSpecFFInstalledNi[f] != NULL);
- if (memPlatSpecFFInstalledNi[f] (NBPtr->MemPtr, NBPtr->ChannelPtr, NBPtr->PsPtr) == AGESA_UNSUPPORTED) {
- ErrUnSuppFFCount++; //Count the number of AGESA_UNSUPPORTED errors
- } else {
- break;
- }
- }
- if (ErrUnSuppFFCount == MAX_FF_TYPES) {
- return FALSE; // No FF types are supported
- }
- }
- }
- return TRUE;
-}
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnS3on.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnS3on.c
deleted file mode 100644
index dcbbf96..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnS3on.c
+++ /dev/null
@@ -1,576 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mns3on.c
- *
- * ON memory specific function to support S3 resume
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/ON)
- * @e \$Revision: 38639 $ @e \$Date: 2010-09-27 21:55:34 +0800 (Mon, 27 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "S3.h"
-#include "mfs3.h"
-#include "mnon.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "GeneralServices.h"
-#include "cpuCommonF14Utilities.h"
-#include "mnS3on.h"
-#include "heapManager.h"
-#include "Filecode.h"
-#define FILECODE PROC_MEM_NB_ON_MNS3ON_FILECODE
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-UINT16
-STATIC
-MemNS3GetRegLstPtrON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT DESCRIPTOR_GROUP *DescriptPtr
- );
-
-AGESA_STATUS
-STATIC
-MemNS3GetDeviceRegLstON (
- IN UINT32 RegisterLstID,
- OUT VOID **RegisterHeader
- );
-
-VOID
-STATIC
-MemNS3SetDfltPllLockTimeON (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR Address,
- IN OUT VOID *Value,
- IN OUT VOID *ConfigPtr
- );
-
-BOOLEAN
-STATIC
-MemNS3ChangeNbFrequencyWrapON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 NBPstate
- );
-
-VOID
-STATIC
-MemNS3GetConPCIMaskON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT DESCRIPTOR_GROUP *DescriptPtr
- );
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-PCI_SPECIAL_CASE PciSpecialCaseFuncON[] = {
- {MemNS3GetCSRNb, MemNS3SetCSRNb},
- {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb},
- {MemNS3DisNbPsDbgNb, MemNS3DisNbPsDbgNb},
- {MemNS3EnNbPsDbg1Nb, MemNS3EnNbPsDbg1Nb},
- { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetDfltPllLockTimeON},
- { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetDisAutoCompUnb},
- { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetDynModeChangeNb},
- {MemNS3GetBitFieldNb, MemNS3SetPreDriverCalUnb}
-};
-
-PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorON[] = {
- {{0, 2, 0}, FUNC_2, 0x110, 0x00000708},
- {{0, 0, 0}, FUNC_1, 0x40, 0x0FFF0003},
- {{0, 0, 0}, FUNC_1, 0x44, 0xFFFF0000},
- {{0, 0, 0}, FUNC_1, 0xF0, 0xFF00FF81},
- {{0, 2, 0}, FUNC_2, 0x114, 0x00000200},
- {{0, 0, 0}, FUNC_2, 0x118, 0x0F00CFFF},
- {{0, 0, 0}, FUNC_2, 0x11C, 0x61CC507C},
- {{0, 0, 0}, FUNC_2, 0x40, 0x1FF83FED},
- {{0, 0, 0}, FUNC_2, 0x44, 0x1FF83FED},
- {{0, 0, 0}, FUNC_2, 0x48, 0x1FF83FED},
- {{0, 0, 0}, FUNC_2, 0x4C, 0x1FF83FED},
- {{0, 0, 0}, FUNC_2, 0x60, 0x1FF83FE0},
- {{0, 0, 0}, FUNC_2, 0x64, 0x1FF83FE0},
- {{0, 1, 0}, FUNC_2, 0x80, 0x000000FF},
- {{0, 0, 0}, FUNC_2, 0x84, 0x00FC2FFF},
- {{0, 0, 0}, FUNC_2, 0x88, 0xFF00000F},
- {{0, 0, 0}, FUNC_2, 0x8C, 0x03F7FCFF},
- {{0, 0, 0}, FUNC_2, 0x90, 0x0EF20003},
- {{0, 1, 0}, FUNC_2, 0xA4, 0x00000007},
- {{0, 0, 0}, FUNC_2, 0xA8, 0x0078FF1F},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x06), 0x00000F8F},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x16), 0x0000000F},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x40), 0x3F1F0F0F},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x41), 0x00070707},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x83), 0x00007177},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x180), 0x0F0F0F0F},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x182), 0x0F0F0F0F},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x200), 0x00001F0F},
-
- // Phy Initialization
- {{6, 3, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0B), 0},
- // 3. Phy voltage related
- {{1, 1, 1}, DCT0, BFDataRxVioLvl, 0x00000018},
- {{1, 1, 1}, DCT0, BFClkRxVioLvl, 0x00000018},
- {{1, 2, 1}, DCT0, BFCmpVioLvl, 0x0000C000},
- {{1, 1, 1}, DCT0, BFCmdRxVioLvl, 0x00000018},
- {{1, 1, 1}, DCT0, BFAddrRxVioLvl, 0x00000018},
- // 4. Frequency Change
- {{4, 3, 1}, DCT0, BFPllLockTime, 0},
- {{0, 0, 0}, FUNC_2, 0x94, 0xFFD1CC1F},
- // NB Pstate Related Register for Pstate 0
- {{0, 0, 0}, FUNC_2, 0x78, 0xFFF63FCF},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x30), 0x00001FFF},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x31), 0x00001FFF},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x32), 0x00009F9F},
- // Access NB Pstate 1
- {{3, 3, 1}, FUNC_6, 0x98, 0},
- // NB Pstate Related Register for Pstate 1
- {{0, 0, 0}, FUNC_2, 0x78, 0xFFF63FCF},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x30), 0x00001FFF},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x31), 0x00001FFF},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x32), 0x00009F9F},
- // Disable Access to NB Pstate 1
- {{2, 3, 1}, FUNC_6, 0x98, 0},
- {{1, 1, 1}, DCT0, BFMemClkFreqVal, 0},
- {{1, 2, 1}, DCT0, BFPllLockTime, 0},
- // 5. Phy Fence
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), 0x7FFF3FFF},
- {{1, 2, 1}, DCT0, BFDataFence2, 0x00007FFF},
- {{1, 1, 1}, DCT0, BFClkFence2, 0x0000001F},
- {{1, 1, 1}, DCT0, BFCmdFence2, 0x0000001F},
- {{1, 1, 1}, DCT0, BFAddrFence2, 0x0000001F},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), 0x70777777},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), 0x003F3F3F},
- {{1, 1, 1}, DCT0, BFDQOdt03, 0x70},
- {{1, 1, 1}, DCT0, BFDQOdt47, 0x70},
- // 6. Phy Compensation Init
- {{5, 3, 1}, DCT0, BFDisablePredriverCal, 0},
- {{1, 2, 1}, DCT0, BFDataByteTxPreDriverCal2Pad1, 0},
- {{1, 2, 1}, DCT0, BFDataByteTxPreDriverCal2Pad2, 0},
- {{7, 2, 1}, DCT0, BFDataByteTxPreDriverCal, 0},
- {{1, 2, 1}, DCT0, BFCmdAddr0TxPreDriverCal2Pad1, 0},
- {{1, 2, 1}, DCT0, BFCmdAddr0TxPreDriverCal2Pad2, 0},
- {{1, 2, 1}, DCT0, BFCmdAddr1TxPreDriverCal2Pad1, 0},
- {{1, 2, 1}, DCT0, BFCmdAddr1TxPreDriverCal2Pad2, 0},
- {{1, 2, 1}, DCT0, BFAddrTxPreDriverCal2Pad1, 0},
- {{1, 2, 1}, DCT0, BFAddrTxPreDriverCal2Pad2, 0},
- {{1, 2, 1}, DCT0, BFAddrTxPreDriverCal2Pad3, 0},
- {{1, 2, 1}, DCT0, BFAddrTxPreDriverCal2Pad4, 0},
- {{7, 2, 1}, DCT0, BFCmdAddr0TxPreDriverCalPad0, 0},
- {{7, 2, 1}, DCT0, BFCmdAddr1TxPreDriverCalPad0, 0},
- {{7, 2, 1}, DCT0, BFAddrTxPreDriverCalPad0, 0},
- {{7, 2, 1}, DCT0, BFClock0TxPreDriverCalPad0, 0},
- {{7, 2, 1}, DCT0, BFClock1TxPreDriverCalPad0, 0},
-
- {{1, 2, 1}, DCT0, BFDisablePredriverCal, 0x00006000}
-};
-
-CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefON = {
- 0,
- (sizeof (S3PciPreSelfRefDescriptorON) / sizeof (PCI_REG_DESCRIPTOR)),
- S3PciPreSelfRefDescriptorON,
- PciSpecialCaseFuncON
-};
-
-CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorON[] = {
- // DCT0
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10), 0x01FF01FF, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11), 0x01FF01FF, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13), 0x01FF01FF, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14), 0x01FF01FF, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20), 0x01FF01FF, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21), 0x01FF01FF, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23), 0x01FF01FF, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24), 0x01FF01FF, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01), 0xFFFFFFFF, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02), 0xFFFFFFFF, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0xFFFFFFFF, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0xFFFFFFFF, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05), 0x3E3E3E3E, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06), 0x3E3E3E3E, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3E3E3E3E, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3E3E3E3E, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30), 0x00FF00FF, DCT0_DDR3_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31), 0x00FF00FF, DCT0_DDR3_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33), 0x00FF00FF, DCT0_DDR3_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34), 0x00FF00FF, DCT0_DDR3_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40), 0x00FF00FF, DCT0_DDR3_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41), 0x00FF00FF, DCT0_DDR3_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43), 0x00FF00FF, DCT0_DDR3_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44), 0x00FF00FF, DCT0_DDR3_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D), 0x037F037F, DCT0_MASK, ANY_DIMM_MASK},
- {{1, 1, 1}, DCT0, BFPhyClkConfig0, 0x00000010, DCT0_MASK, ANY_DIMM_MASK},
- {{1, 1, 1}, DCT0, BFPhyClkConfig1, 0x00000010, DCT0_MASK, ANY_DIMM_MASK},
- {{1, 1, 1}, DCT0, BFPhy0x0D0F0F13Bit0to7, 0x00000083, DCT0_MASK, ANY_DIMM_MASK},
- {{1, 1, 1}, DCT0, BFAddrCmdTri, 0x0000000B1, DCT0_MASK, ANY_DIMM_MASK},
- {{1, 2, 1}, DCT0, BFLowPowerDrvStrengthEn, 0x00000100, DCT0_MASK, ANY_DIMM_MASK},
- {{1, 2, 1}, DCT0, BFEnRxPadStandby, 0x000001000, DCT0_MASK, ANY_DIMM_MASK},
- {{1, 1, 1}, DCT0, BFDisDllShutdownSR, 0x00000001, DCT0_MASK, ANY_DIMM_MASK},
-
- {{0, 0, 0}, FUNC_2, 0x1C0, 0x100000, DCT0_MASK, ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_3, 0x84, 0x00060006, DCT0_MASK, ANY_DIMM_MASK},
- {{0, 2, 0}, FUNC_4, 0x12C, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_4, 0x1A8, 0x3F000000, DCT0_MASK, ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_3, 0x188, 0x00400000, DCT0_MASK, ANY_DIMM_MASK},
- {{0, 2, 0}, FUNC_6, 0x78, 0x0000FF00, DCT0_MASK, ANY_DIMM_MASK},
- // Release NB P-state force
- {{0, 0, 0}, FUNC_6, 0x90, 0x50000000, DCT0_MASK, ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x118, 0x00080000, DCT0_MASK, ANY_DIMM_MASK}
-};
-
-CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefON = {
- 0,
- (sizeof (S3CPciPostSelfDescriptorON) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
- S3CPciPostSelfDescriptorON,
- PciSpecialCaseFuncON
-};
-
-MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorON[] = {
- {{0, 0, 0}, 0xC0010010, 0x00000000007F0000},
- {{0, 0, 0}, 0xC001001A, 0x0000000FFF800000},
- {{0, 0, 0}, 0xC001001D, 0x0000000FFF800000},
- {{0, 0, 0}, 0xC001001F, 0x8480FC6A434243E0}
-};
-
-CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefON = {
- 0,
- (sizeof (S3MSRPreSelfRefDescriptorON) / sizeof (MSR_REG_DESCRIPTOR)),
- S3MSRPreSelfRefDescriptorON,
- NULL
-};
-
-VOID *MemS3RegListON[] = {
- (VOID *)&S3PciPreSelfRefON,
- NULL,
- NULL,
- (VOID *)&S3CPciPostSelfRefON,
- (VOID *)&S3MSRPreSelfRefON,
- NULL,
- NULL,
- NULL
-};
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the northbridge block for S3 resume
- *
- * @param[in,out] *S3NBPtr - Pointer to MEM_NB_BLOCK.
- * @param[in,out] *MemPtr - Pointer to MEM_DATA_STRUCT.
- * @param[in] NodeID - Node ID of the target node.
- *
- * @return BOOLEAN
- * TRUE - This is the correct constructor for the targeted node.
- * FALSE - This isn't the correct constructor for the targeted node.
- */
-BOOLEAN
-MemS3ResumeConstructNBBlockON (
- IN OUT VOID *S3NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- )
-{
- INT32 i;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr;
-
- //
- // Determine if this is the expected NB Type
- //
- GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
- if (!MemNIsIdSupportedON (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
- return FALSE;
- }
-
- NBPtr->MemPtr = MemPtr;
- NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
- NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
- MemNInitNBRegTableON (NBPtr, NBPtr->NBRegTable);
- NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
- NBPtr->Dct = 0;
- NBPtr->Channel = 0;
- NBPtr->Ganged = FALSE;
- NBPtr->NodeCount = MAX_NODES_SUPPORTED_ON;
- NBPtr->DctCount = MAX_DCTS_PER_NODE_ON;
-
- for (i = 0; i < EnumSize; i++) {
- NBPtr->IsSupported[i] = FALSE;
- }
-
- for (i = 0; i < NumberOfHooks; i++) {
- NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) memDefTrue;
- }
-
- LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader);
-
- NBPtr->SwitchDCT = (VOID (*) (MEM_NB_BLOCK*, UINT8)) memDefRet;
- NBPtr->SwitchChannel = (VOID (*) (MEM_NB_BLOCK*, UINT8)) memDefRet;
- NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldON;
- NBPtr->GetBitField = MemNGetBitFieldNb;
- NBPtr->SetBitField = MemNSetBitFieldNb;
- NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedON;
- NBPtr->ChangeNbFrequencyWrap = MemNS3ChangeNbFrequencyWrapON;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = (VOID (*) (MEM_NB_BLOCK *, AMD_CONFIG_PARAMS *)) memDefRet;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskON;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK *, DESCRIPTOR_GROUP *)) memDefRet;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeClientNb;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = (VOID (*) (MEM_NB_BLOCK *, UINT8)) memDefRet;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrON;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstON;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = 0;
-
- return TRUE;
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------*/
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function returns the conditional PCI device mask
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP
- * @return none
- */
-VOID
-STATIC
-MemNS3GetConPCIMaskON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT DESCRIPTOR_GROUP *DescriptPtr
- )
-{
- BIT_FIELD_NAME bitfield;
- UINT32 RegVal;
- UINT8 DimmMask;
-
- DimmMask = 0;
- for (bitfield = BFCSBaseAddr0Reg; bitfield <= BFCSBaseAddr3Reg; bitfield ++) {
- RegVal = MemNGetBitFieldNb (NBPtr, bitfield);
- if (RegVal & 0x1) {
- DimmMask |= (UINT8) (1 << (((bitfield - BFCSBaseAddr0Reg) >> 1) << 1));
- }
- }
-
- // Set mask before exit self refresh
- DescriptPtr->CPCIDevice[PRESELFREF].Mask1 = 1;
- // Set mask after exit self refresh
- DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 = 1;
- // Set DDR3 mask if Dimms present are DDR3
- DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= (DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 << 4);
-
- // Set dimm mask
- DescriptPtr->CPCIDevice[PRESELFREF].Mask2 = DimmMask;
- DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 = DimmMask;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function returns the register list for each device for LN
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP
- * @return UINT16 - size of the device descriptor on the target node.
- */
-UINT16
-STATIC
-MemNS3GetRegLstPtrON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT DESCRIPTOR_GROUP *DescriptPtr
- )
-{
- UINT8 i;
- UINT16 Size;
- Size = 0;
- for (i = PRESELFREF; i <= POSTSELFREF; i ++) {
- DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i);
- DescriptPtr->PCIDevice[i].Node = NBPtr->Node;
- DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF;
- if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListON[PCI_LST_ESR_ON - PCI_LST_ESR_ON + i] != NULL) {
- DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_ON + i;
- Size += sizeof (PCI_DEVICE_DESCRIPTOR);
- }
- DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i);
- DescriptPtr->CPCIDevice[i].Node = NBPtr->Node;
- DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF;
- if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListON[CPCI_LST_ESR_ON - PCI_LST_ESR_ON + i] != NULL) {
- DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_ON + i;
- Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR);
- }
- DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i);
- DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF;
- if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListON[MSR_LST_ESR_ON - PCI_LST_ESR_ON + i] != NULL) {
- DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_ON + i;
- Size += sizeof (MSR_DEVICE_DESCRIPTOR);
- }
- DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i);
- DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF;
- if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListON[CMSR_LST_ESR_ON - PCI_LST_ESR_ON + i] != NULL) {
- DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_ON + i;
- Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR);
- }
- }
- return Size;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function return the register list according to the register ID.
- *
- * @param[in] RegisterLstID - value of the Register list ID.
- * @param[out] **RegisterHeader - pointer to the address of the register list.
- * @return none
- */
-AGESA_STATUS
-STATIC
-MemNS3GetDeviceRegLstON (
- IN UINT32 RegisterLstID,
- OUT VOID **RegisterHeader
- )
-{
- if (RegisterLstID >= (sizeof (MemS3RegListON) / sizeof (VOID *))) {
- ASSERT(FALSE); // RegisterListID exceeded size of Register list
- return AGESA_FATAL;
- }
- if (MemS3RegListON[RegisterLstID] != NULL) {
- *RegisterHeader = MemS3RegListON[RegisterLstID];
- return AGESA_SUCCESS;
- }
- ASSERT(FALSE); // Device regiser list error
- return AGESA_FATAL;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function that set PllLockTime to default state.
- *
- * @param[in] AccessWidth - Access width of the register.
- * @param[in] Address - address in PCI_ADDR format.
- * @param[in, out] *Value - Pointer to the value to be written.
- * @param[in, out] *ConfigPtr - Pointer to Config handle.
- * @return none
- */
-VOID
-STATIC
-MemNS3SetDfltPllLockTimeON (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR Address,
- IN OUT VOID *Value,
- IN OUT VOID *ConfigPtr
- )
-{
- UINT16 RegValue;
-
- RegValue = 0x1838;
- MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function is a wrapper to call a CPU routine to change NB P-state and
- * update NB frequency.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] *NBPstate - NB Pstate
- *
- * @return TRUE - Succeed
- * @return FALSE - Fail
- */
-
-BOOLEAN
-STATIC
-MemNS3ChangeNbFrequencyWrapON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 NBPstate
- )
-{
- BOOLEAN Status;
- UINT32 NBFreq;
- UINT32 Speed;
-
- Speed = MemNGetBitFieldNb (NBPtr, BFMemClkFreq);
- Status = F14NbPstateInit (((Speed + 6) * 3335) / 100,
- Speed,
- NBPstate,
- &NBFreq,
- &(NBPtr->MemPtr->StdHeader));
-
- return Status;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnS3on.h b/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnS3on.h
deleted file mode 100644
index 6cb15e7..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnS3on.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnS3on.h
- *
- * S3 resume memory related function for ON.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/ON)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MNS3ON_H_
-#define _MNS3ON_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-/// ID for register list of ON
-typedef enum {
- PCI_LST_ESR_ON, ///< Assign 0x0000 for PCI register list for pre exit self refresh.
- PCI_LST_ON, ///< Assign 0x0001 for PCI register list for post exist self refresh.
- CPCI_LST_ESR_ON, ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh.
- CPCI_LST_ON, ///< Assign 0x0003 for conditional PCI register list for post exit self refresh.
- MSR_LST_ESR_ON, ///< Assign 0x0004 for MSR register list for pre exit self refresh.
- MSR_LST_ON, ///< Assign 0x0005 for MSR register list for post exit self refresh.
- CMSR_LST_ESR_ON, ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh.
- CMSR_LST_ON ///< Assign 0x0007 for conditional MSR register list for post exit self refresh.
-} RegisterListIDON;
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-#endif //_MNS3ON_H_
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mndcton.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mndcton.c
deleted file mode 100644
index c0855b8..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mndcton.c
+++ /dev/null
@@ -1,490 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mndcton.c
- *
- * Northbridge ON DCT supporting functions
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/ON)
- * @e \$Revision: 37169 $ @e \$Date: 2010-09-01 05:35:27 +0800 (Wed, 01 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mu.h"
-#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB
-#include "mnon.h"
-#include "merrhdl.h"
-#include "GeneralServices.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuCommonF14Utilities.h"
-#include "Filecode.h"
-#define FILECODE PROC_MEM_NB_ON_MNDCTON_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define UNUSED_CLK 4
-#define MAX_RD_DQS_DLY 0x1F
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function programs the memory controller with configuration parameters
- *
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - An Error value lower than AGESA_FATAL may have occurred
- * @return FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred
- * @return NBPtr->MCTPtr->ErrCode - Contains detailed AGESA_STATUS value
- */
-
-BOOLEAN
-MemNAutoConfigON (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- DIE_STRUCT *MCTPtr;
- DCT_STRUCT *DCTPtr;
- UINT8 PowerDownMode;
-
- MCTPtr = NBPtr->MCTPtr;
- DCTPtr = NBPtr->DCTPtr;
- //======================================================================
- // Build Dram Control Register Value (F2x78)
- //======================================================================
- //
-
- //======================================================================
- // Build Dram Config Lo Register Value
- //======================================================================
- //
- MemNSetBitFieldNb (NBPtr, BFEnDispAutoPrecharge, 1);
-
- MemNSetBitFieldNb (NBPtr, BFIdleCycInit, 3);
-
- //======================================================================
- // Build Dram Config Hi Register Value
- //======================================================================
- //
-
- MemNSetBitFieldNb (NBPtr, BFMemClkFreq, MemNGetMemClkFreqIdClientNb (NBPtr, DCTPtr->Timings.Speed));
-
- PowerDownMode = (UINT8) ((UserOptions.CfgPowerDownMode == POWER_DOWN_MODE_AUTO) ? POWER_DOWN_BY_CHIP_SELECT : UserOptions.CfgPowerDownMode);
- PowerDownMode = (!NBPtr->IsSupported[ChannelPDMode]) ? PowerDownMode : 0;
- IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader));
- if (PowerDownMode == 1) {
- MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1);
- }
-
- MemNSetBitFieldNb (NBPtr, BFPchgPDModeSel, 1);
-
- MemNSetBitFieldNb (NBPtr, BFDcqBypassMax, 0xE);
-
- MemNSetBitFieldNb (NBPtr, BFDctSelBankSwap, 1);
-
- //======================================================================
- // Build Dram Config Misc Register Value
- //======================================================================
- //
- // Max out Non-SPD timings
- MemNSetBitFieldNb (NBPtr, BFNonSPD, 0x18FF);
- MemNSetBitFieldNb (NBPtr, BFNonSPDHi, 0x2A);
- MemNSetBitFieldNb (NBPtr, BFTwrrdSD, 0xA);
- MemNSetBitFieldNb (NBPtr, BFTrdrdSD, 0x8);
- MemNSetBitFieldNb (NBPtr, BFTwrwrSD, 0x9);
-
- MemNSetBitFieldNb (NBPtr, BFWrOdtOnDuration, DEFAULT_WR_ODT_ON_ON);
- MemNSetBitFieldNb (NBPtr, BFRdOdtOnDuration, DEFAULT_RD_ODT_ON_ON);
- MemNSetBitFieldNb (NBPtr, BFWrOdtTrnOnDly, 0);
-
- //======================================================================
- // DRAM MRS Register, set ODT
- //======================================================================
- MemNSetBitFieldNb (NBPtr, BFBurstCtrl, 1);
-
- // DrvImpCtrl: drive impedance control.01b(34 ohm driver; Ron34 = Rzq/7)
- MemNSetBitFieldNb (NBPtr, BFDrvImpCtrl, 1);
-
- return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sends an MRS command
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNSendMrsCmdON (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MemNSetASRSRTNb (NBPtr);
- MemNSwapBitsNb (NBPtr);
-
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tCS%d MR%d %04x\n",
- (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 20) & 0xF,
- (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 16) & 0xF,
- (MemNGetBitFieldNb (NBPtr, BFDramInitRegReg) & 0xFFFF));
-
- // 1.Set SendMrsCmd=1
- MemNSetBitFieldNb (NBPtr, BFSendMrsCmd, 1);
-
- // 2.Wait for SendMrsCmd=0
- MemNPollBitFieldNb (NBPtr, BFSendMrsCmd, 0, PCI_ACCESS_TIMEOUT, FALSE);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function combines all the memory into a contiguous map.
- * Requires that Mask values for each bank be programmed first and that
- * the chip-select population indicator is correctly set.
- *
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - An Error value lower than AGESA_FATAL may have occurred
- * @return FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred
- */
-
-BOOLEAN
-MemNStitchMemoryON (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT32 NxtCSBase;
- UINT32 CurCSBase;
- UINT32 CsSize;
- UINT32 BiggestBank;
- UINT8 p;
- UINT8 q;
- UINT8 BiggestDimm;
- DIE_STRUCT *MCTPtr;
- DCT_STRUCT *DCTPtr;
- MCTPtr = NBPtr->MCTPtr;
- DCTPtr = NBPtr->DCTPtr;
-
- DCTPtr->Timings.CsEnabled = 0;
- NxtCSBase = 0;
- for (p = 0; p < MAX_CS_PER_CHANNEL_ON; p++) {
- BiggestBank = 0;
- BiggestDimm = 0;
- for (q = 0; q < MAX_CS_PER_CHANNEL_ON; q++) {
- if (((DCTPtr->Timings.CsPresent & ~DCTPtr->Timings.CsTestFail) & ((UINT16)1 << q)) != 0) {
- if ((MemNGetBitFieldNb (NBPtr, BFCSBaseAddr0Reg + q) & 7) == 0) {
- // (CSEnable|Spare==1)bank is not enabled yet
- CsSize = MemNGetBitFieldNb (NBPtr, BFCSMask0Reg + (q >> 1));
- if (CsSize != 0) {
- CsSize += ((UINT32)1 << 19);
- CsSize &= 0xFFF80000;
- }
- if (CsSize > BiggestBank) {
- BiggestBank = CsSize;
- BiggestDimm = q;
- }
- }
- }
- }
-
- if (BiggestBank != 0) {
- CurCSBase = NxtCSBase;
- CurCSBase |= ((UINT32)1 << BFCSEnable);
- NxtCSBase += BiggestBank;
- if ((BiggestDimm & 1) != 0) {
- if ((DCTPtr->Timings.DimmMirrorPresent & (1 << (BiggestDimm >> 1))) != 0) {
- CurCSBase |= ((UINT32)1 << BFOnDimmMirror);
- }
- }
- MemNSetBitFieldNb (NBPtr, BFCSBaseAddr0Reg + BiggestDimm, CurCSBase);
- DCTPtr->Timings.CsEnabled |= (1 << BiggestDimm);
- }
- if ((DCTPtr->Timings.CsTestFail & ((UINT16)1 << p)) != 0) {
- MemNSetBitFieldNb (NBPtr, (BFCSBaseAddr0Reg + p), (UINT32)1 << BFTestFail);
- }
- }
-
- if (NxtCSBase != 0) {
- DCTPtr->Timings.DctMemSize = NxtCSBase >> 8; // Scale base address from [39:8] to [47:16]
- NBPtr->MCTPtr->NodeMemSize += NBPtr->DCTPtr->Timings.DctMemSize;
- NBPtr->MCTPtr->NodeSysLimit = NBPtr->MCTPtr->NodeMemSize - 1;
- } else {
- PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_FATAL, MCTPtr);
- }
-
- return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function sets the maximum round-trip latency in the system from the processor to the DRAM
- * devices and back for Ontario.
- *
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] MaxRcvEnDly - Maximum receiver enable delay value
- *
- */
-
-VOID
-MemNSetMaxLatencyON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT16 MaxRcvEnDly
- )
-{
- UINT32 N;
- UINT32 T;
- UINT32 P;
- UINT32 Px2;
- UINT32 MemClkPeriod;
-
- AGESA_TESTPOINT (TpProcMemRcvrCalcLatency, &(NBPtr->MemPtr->StdHeader));
-
- N = 0x50; // init value for MaxRdLat used in training
-
- if (MaxRcvEnDly != 0xFFFF) {
- T = MemNTotalSyncComponentsClientNb (NBPtr);
-
- // P = P + CEIL(MAX (total delay in DqsRcvEn + RdDqsTime))
- P = ((MaxRcvEnDly + MAX_RD_DQS_DLY) + 31) / 32;
-
- // P = P + 6.5
- // T = T + 2586 ps
- Px2 = (P * 2) + 13;
- T += 2586;
-
- // N = (P/(MemClkFreq * 2) + T) * NclkFreq
- MemClkPeriod = 1000000 / NBPtr->DCTPtr->Timings.Speed;
- N = ((((Px2 * MemClkPeriod + 3) / 4) + T) * NBPtr->NBClkFreq + 999999) / 1000000;
- N += 2;
- }
-
- NBPtr->DCTPtr->Timings.MaxRdLat = (UINT16) N;
- ASSERT (N <= 0x3FF);
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\tMaxRdLat: %03x\n", N);
- MemNSetBitFieldNb (NBPtr, BFMaxLatency, N);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function retrieves the Max latency parameters
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @param[in] *MinDlyPtr - Pointer to variable to store the Minimum Delay value
- * @param[in] *MaxDlyPtr - Pointer to variable to store the Maximum Delay value
- * @param[in] *DlyBiasPtr - Pointer to variable to store Delay Bias value
- * @param[in] MaxDlyForMaxRdLat - Maximum receiver enable delay value
- *
- */
-
-VOID
-MemNGetMaxLatParamsClientON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT16 MaxDlyForMaxRdLat,
- IN OUT UINT16 *MinDlyPtr,
- IN OUT UINT16 *MaxDlyPtr,
- IN OUT UINT16 *DlyBiasPtr
- )
-{
- UINT32 P;
- UINT32 Px2;
- UINT32 T;
- UINT32 MemClkPeriod;
-
- T = MemNTotalSyncComponentsClientNb (NBPtr);
-
- // P = P + CEIL(MAX (total delay in DqsRcvEn + RdDqsTime))
- P = (MaxDlyForMaxRdLat + 31) / 32;
-
- // P = P + 6.5
- // T = T + 2586 ps
- Px2 = (P * 2) + 13;
- T += 2586;
-
- // N = (P/(MemClkFreq * 2) + T) * NclkFreq
- MemClkPeriod = 1000000 / NBPtr->DCTPtr->Timings.Speed;
-
- *MinDlyPtr = (UINT16) (((((Px2 * MemClkPeriod + 3) / 4) + T) * NBPtr->NBClkFreq + 999999) / 1000000);
-
- if (NBPtr->NbFreqChgState == 1) {
- *MinDlyPtr += 2;
- } else {
- *MinDlyPtr += 1;
- }
-
- *MaxDlyPtr = 100 + *MinDlyPtr; // 100 fixed iterations
-
- // IF ((NCLK!=MEMCLK) && (NCLK!=MEMCLK/2))
- // THEN TrainingOffset = 3
- // ELSE TrainingOffset = 2
- if ((NBPtr->NBClkFreq == NBPtr->DCTPtr->Timings.Speed) ||
- (NBPtr->NBClkFreq == (UINT32) (NBPtr->DCTPtr->Timings.Speed / 2)) ||
- (NBPtr->NBClkFreq == (UINT32) (NBPtr->DCTPtr->Timings.Speed / 2 + 1))) {
- *DlyBiasPtr = 2;
- } else {
- *DlyBiasPtr = 3;
- }
-
- // Register settings required before MaxRdLat training
- MemNSetBitFieldNb (NBPtr, BFForceCasToSlot0, 1);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function is a wrapper to call a CPU routine to change NB P-state and
- * update NB frequency.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] *NBPstate - NB Pstate
- *
- * @return TRUE - Succeed
- * @return FALSE - Fail
- */
-BOOLEAN
-MemNChangeNbFrequencyWrapON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 NBPstate
- )
-{
- BOOLEAN Status;
- UINT32 NBFreq;
- UINT32 Memclk;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
-
- if (NBPtr->NbFreqChgState == 0) {
- // While in state 0, report the new memclk to the
- // CPU module to adjust the NB P-state settings.
- Memclk = NBPtr->DCTPtr->Timings.Speed;
- } else {
- // We have already adjusted for target memclk.
- // Indicate NB P-state change only.
- Memclk = 0;
- }
-
- Status = F14NbPstateInit (Memclk,
- MemNGetMemClkFreqIdClientNb (NBPtr, NBPtr->DCTPtr->Timings.Speed),
- NBPstate,
- &NBFreq,
- &(NBPtr->MemPtr->StdHeader));
- if (Status) {
- // When NB frequency change succeeds, TSC rate may have changed.
- // We need to update TSC rate
- GetCpuServicesOfCurrentCore (&FamilySpecificServices, &NBPtr->MemPtr->StdHeader);
- FamilySpecificServices->GetTscRate (FamilySpecificServices, &NBPtr->MemPtr->TscRate, &NBPtr->MemPtr->StdHeader);
- }
- return Status;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets Dqs Odt for ON
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *OptParam - Optional parameter
- *
- * @return TRUE
- */
-
-BOOLEAN
-MemNSetDqsODTON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT VOID *OptParam
- )
-{
- if ((NBPtr->DCTPtr->Timings.Speed == DDR1333_FREQUENCY) && (NBPtr->ChannelPtr->Dimms == 1)) {
- MemNSetBitFieldNb (NBPtr, BFDQOdt03, 0x20);
- MemNSetBitFieldNb (NBPtr, BFDQOdt47, 0x20);
- }
- return TRUE;
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnflowon.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnflowon.c
deleted file mode 100644
index b7efd35..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnflowon.c
+++ /dev/null
@@ -1,168 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnflowon.c
- *
- * Llano initializer for MCT and DCT
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Main)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "Filecode.h"
-#include "GeneralServices.h"
-#define FILECODE PROC_MEM_NB_ON_MNFLOWON_FILECODE
-/* features */
-#include "mftds.h"
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledON[MAX_FF_TYPES];
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the platform specific block
- *
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - AGESA_SUCCESS at least one dorm factor was found
- * @return FALSE - AGESA_UNSUPPORTED - Error indicating that no form factors were found
- */
-
-BOOLEAN
-MemNPlatformSpecificFormFactorInitON (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 f;
-
- if (NBPtr->MCTPtr->DimmValid == 0) {
- PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &(NBPtr->MemPtr->StdHeader));
- SetMemError (AGESA_FATAL, NBPtr->MCTPtr);
- ASSERT(FALSE); // Size of memory on BSP = 0, so no DIMM found
- return FALSE; // There is no dimm present on the system.
- }
- for (f = 0; memPlatSpecFFInstalledON[f] != NULL; f++) {
- if (memPlatSpecFFInstalledON[f] (NBPtr->MemPtr, NBPtr->ChannelPtr, NBPtr->PsPtr) == AGESA_SUCCESS) {
- break;
- }
- }
- if (memPlatSpecFFInstalledON[f] == NULL) {
- return FALSE; // No FF types are supported
- }
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function selects appropriate Tech functions for the NB.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNTechBlockSwitchON (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MEM_TECH_BLOCK *TechPtr;
-
- TechPtr = NBPtr->TechPtr;
-
- // Specify Dimm-Byte training for Nb
- MemTDimmByteTrainInit (TechPtr);
-
- // Remove the following functions because they are not needed for ON
- TechPtr->SetDramMode = (BOOLEAN (*) (MEM_TECH_BLOCK *)) memDefTrue;
- TechPtr->SpdCalcWidth = (BOOLEAN (*) (MEM_TECH_BLOCK *)) memDefTrue;
- TechPtr->SetDqsEccTmgs = (BOOLEAN (*) (MEM_TECH_BLOCK *)) memDefTrue;
- TechPtr->AdjustTwrwr = (VOID (*) (MEM_TECH_BLOCK *)) memDefRet;
- TechPtr->AdjustTwrrd = (VOID (*) (MEM_TECH_BLOCK *)) memDefRet;
- TechPtr->GetLD = (INT8 (*) (MEM_TECH_BLOCK *)) memDefRet;
- TechPtr->FindMaxDlyForMaxRdLat = MemTFindMaxRcvrEnDlyRdDqsDlyByte;
- TechPtr->ResetDCTWrPtr = (VOID (*) (MEM_TECH_BLOCK *, UINT8)) memDefRet;
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnidendimmon.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnidendimmon.c
deleted file mode 100644
index 9e4060a..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnidendimmon.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnidendimmon.c
- *
- * ON northbridge constructor for dimm identification translator.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/ON)
- * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "mm.h"
-#include "mn.h"
-#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB
-#include "mnon.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-#define FILECODE PROC_MEM_NB_ON_MNIDENDIMMON_FILECODE
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the northbridge block for dimm identification translator
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
- * @param[in,out] NodeID - ID of current node to construct
- * @return TRUE - This is the correct constructor for the targeted node.
- * @return FALSE - This isn't the correct constructor for the targeted node.
- */
-
-BOOLEAN
-MemNIdentifyDimmConstructorON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- )
-{
- //
- // Determine if this is the expected NB Type
- //
- GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
- if (!MemNIsIdSupportedON (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
- return FALSE;
- }
-
- NBPtr->NodeCount = MAX_NODES_SUPPORTED_ON;
- NBPtr->DctCount = MAX_DCTS_PER_NODE_ON;
- NBPtr->MemPtr = MemPtr;
- NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
- NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
- NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
- NBPtr->Ganged = FALSE;
- MemNInitNBRegTableON (NBPtr, NBPtr->NBRegTable);
- NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldON;
- NBPtr->SetBitField = MemNSetBitFieldNb;
- NBPtr->GetBitField = MemNGetBitFieldNb;
- NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb;
-
- return TRUE;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnmcton.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnmcton.c
deleted file mode 100644
index 6a0ae76..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnmcton.c
+++ /dev/null
@@ -1,252 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnmcton.c
- *
- * Northbridge ON MCT supporting functions
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/ON)
- * @e \$Revision: 41275 $ @e \$Date: 2010-11-03 02:14:41 +0800 (Wed, 03 Nov 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mport.h"
-#include "mm.h"
-#include "mn.h"
-#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB
-#include "mnon.h"
-#include "mu.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-#define FILECODE PROC_MEM_NB_ON_MNMCTON_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-extern BUILD_OPT_CFG UserOptions;
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function create the HT memory map
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemNHtMemMapInitON (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 WeReMask;
- UINT32 BottomIo;
- UINT32 HoleOffset;
- UINT32 NodeSysBase;
- UINT32 NodeSysLimit;
- MEM_PARAMETER_STRUCT *RefPtr;
- DIE_STRUCT *MCTPtr;
-
- RefPtr = NBPtr->RefPtr;
- MCTPtr = NBPtr->MCTPtr;
- //
- // Physical addresses in this function are right adjusted by 16 bits ([47:16])
- // They are BottomIO, HoleOffset, NodeSysBase, NodeSysLimit.
- //
-
- // Enforce bottom of IO be be 128MB aligned
- BottomIo = (RefPtr->BottomIo & 0xF8) << 8;
-
- NodeSysBase = 0;
- NodeSysLimit = MCTPtr->NodeMemSize - 1;
-
- if (NodeSysLimit >= BottomIo) {
- // HW Dram Remap
- MCTPtr->Status[SbHWHole] = TRUE;
- RefPtr->GStatus[GsbHWHole] = TRUE;
- MCTPtr->NodeHoleBase = BottomIo;
- RefPtr->HoleBase = BottomIo;
-
- HoleOffset = _4GB_RJ16 - BottomIo;
- NodeSysLimit += HoleOffset;
-
- MemNSetBitFieldNb (NBPtr, BFDramHoleBase, BottomIo >> 8);
- MemNSetBitFieldNb (NBPtr, BFDramHoleOffset, HoleOffset >> 7);
- MemNSetBitFieldNb (NBPtr, BFDramHoleValid, 1);
-
- } else {
- // No Remapping. Normal Contiguous mapping
- }
- MCTPtr->NodeSysBase = NodeSysBase;
- MCTPtr->NodeSysLimit = NodeSysLimit;
- RefPtr->SysLimit = MCTPtr->NodeSysLimit;
-
- WeReMask = 3;
- // Set the Dram base and set the WE and RE flags in the base.
- MemNSetBitFieldNb (NBPtr, BFDramBaseReg0, (NodeSysBase << 8) | WeReMask);
- // Set the Dram limit
- MemNSetBitFieldNb (NBPtr, BFDramLimitReg0, ((NodeSysLimit << 8) & 0xFFFF0000));
-
- return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * Report the Uma size that is going to be allocated on Fusion.
- * Total system memory UMASize
- * >=2G 384M
- * >=1G 256M
- * <1G 64M
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return Uma size [31:0] = Addr [47:16]
- */
-UINT32
-MemNGetUmaSizeON (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT32 SysMemSize;
- UINT32 SizeOfUma;
-
- SysMemSize = NBPtr->RefPtr->SysLimit + 1;
- SysMemSize = (SysMemSize + 0x100) & 0xFFFFF000; // Ignore 16MB allocated for C6 when finding UMA size
- if (SysMemSize >= 0x8000) {
- SizeOfUma = 384 << (20 - 16);
- } else if (SysMemSize >= 0x4000) {
- SizeOfUma = 256 << (20 - 16);
- } else {
- SizeOfUma = 64 << (20 - 16);
- }
-
- return SizeOfUma;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function programs memory prefetch and priority control
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemNFinalizeMctON (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT32 MctCfgLoReg;
- UINT32 MctCfgHiReg;
-
- // To support ODTS, with assumption that Tref is set to 7.8us always in AGESA
- MemNSetBitFieldNb (NBPtr, BFDoubleTrefRateEn, 1);
-
- MctCfgLoReg = MemNGetBitFieldNb (NBPtr, BFMctCfgLoReg);
- MemNSetBitFieldNb (NBPtr, BFMctCfgLoReg, (MctCfgLoReg & 0xFFFFF000) | 0x04A4);
-
- MctCfgHiReg = MemNGetBitFieldNb (NBPtr, BFMctCfgHiReg);
- MemNSetBitFieldNb (NBPtr, BFMctCfgHiReg, (MctCfgHiReg & 0x9E33AFFF) | 0x00404000);
-
- // PchgPdTxCClkGateDis is 0 by default
- // SelCsrPllPdMode and CsrPhySrPllPdMode is 0 by default
- // SkewMemClk is 0 by default
-
- //For self-refresh
- MemNSetBitFieldNb (NBPtr, BFDramSrEn, 1);
- MemNSetBitFieldNb (NBPtr, BFDramSrHys, 5);
- if (NBPtr->IsSupported[DramSrHys]) {
- MemNSetBitFieldNb (NBPtr, BFDramSrHysEn, 1);
- }
-
- MemNSetBitFieldNb (NBPtr, BFMemTriStateEn, 1);
- MemNSetBitFieldNb (NBPtr, BFAcpiPwrStsCtrlHi, MemNGetBitFieldNb (NBPtr, BFAcpiPwrStsCtrlHi) | 0x00060006);
-
- MemNPhyPowerSavingClientNb (NBPtr);
-
- // Release NB P-state force
- MemNSetBitFieldNb (NBPtr, BFNbPsCtrlDis, 0);
- MemNSetBitFieldNb (NBPtr, BFNbPsForceReq, 0);
-
- IDS_OPTION_HOOK (IDS_PHY_DLL_STANDBY_CTRL, NBPtr, &NBPtr->MemPtr->StdHeader);
-
- return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnon.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnon.c
deleted file mode 100644
index 768d0d7..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnon.c
+++ /dev/null
@@ -1,456 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnon.c
- *
- * Common Northbridge functions for ON
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/ON)
- * @e \$Revision: 40406 $ @e \$Date: 2010-10-22 00:02:12 +0800 (Fri, 22 Oct 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mnon.h"
-#include "mu.h"
-#include "merrhdl.h"
-#include "S3.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "heapManager.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-#define FILECODE PROC_MEM_NB_ON_MNON_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-CONST MEM_FREQ_CHANGE_PARAM FreqChangeParamON = {0x1838, 2, 3, 10, 2, 9, 665, 1000};
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
-extern OPTION_MEM_FEATURE_NB* memNTrainFlowControl[];
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initializes the northbridge block
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
- * @param[in] *FeatPtr - Pointer to the MEM_FEAT_BLOCK_NB
- * @param[in] *SharedPtr - Pointer to the MEM_SHARED_DATA
- * @param[in] NodeID - UINT8 indicating node ID of the NB object.
- *
- * @retval Boolean indicating that this is the correct memory
- * controller type for the node number that was passed in.
- */
-
-BOOLEAN
-MemConstructNBBlockON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN MEM_FEAT_BLOCK_NB *FeatPtr,
- IN MEM_SHARED_DATA *SharedPtr,
- IN UINT8 NodeID
- )
-{
- INT32 i;
- DIE_STRUCT *MCTPtr;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
- //
- // Determine if this is the expected NB Type
- //
- GetLogicalIdOfSocket (MemPtr->DiesPerSystem->SocketId, &(MemPtr->DiesPerSystem->LogicalCpuid), &(MemPtr->StdHeader));
- if (!MemNIsIdSupportedON (NBPtr, &(MemPtr->DiesPerSystem->LogicalCpuid))) {
- return FALSE;
- }
-
- NBPtr->MemPtr = MemPtr;
- NBPtr->RefPtr = MemPtr->ParameterListPtr;
- NBPtr->SharedPtr = SharedPtr;
-
- MCTPtr = MemPtr->DiesPerSystem;
- NBPtr->MCTPtr = MCTPtr;
- NBPtr->MCTPtr->NodeId = 0;
- NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue;
- NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem->LogicalCpuid), &(MemPtr->StdHeader));
-
- //
- // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
- //
- AllocHeapParams.RequestedBufferSize = (sizeof (DCT_STRUCT) + sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK));
- AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0);
- AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
- if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) {
- PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader);
- SetMemError (AGESA_FATAL, MCTPtr);
- ASSERT(FALSE); // Could not allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
- return FALSE;
- }
-
- MCTPtr->Dct = 0;
- MCTPtr->DctCount = MAX_DCTS_PER_NODE_ON;
- MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += sizeof (DCT_STRUCT);
- MCTPtr->DctData->ChannelCount = 1;
- MCTPtr->DctData->ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += sizeof (CH_DEF_STRUCT);
- NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr;
-
- //
- // Initialize Socket List
- //
- *(MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr) = MCTPtr->DctData->ChData;
- *(MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr) = &(MCTPtr->DctData->Timings);
- MCTPtr->DctData->ChData->ChannelID = 0;
-
- //
- // Initialize NB block member variables
- //
-
- NBPtr->DCTPtr = NBPtr->MCTPtr->DctData;
- NBPtr->DctCachePtr = NBPtr->DctCache;
- NBPtr->PsPtr = NBPtr->PSBlock;
- NBPtr->ChannelPtr = NBPtr->DCTPtr->ChData;
-
- MemNInitNBRegTableON (NBPtr, NBPtr->NBRegTable);
- NBPtr->Node = 0;
- NBPtr->Dct = 0;
- NBPtr->Channel = 0;
- NBPtr->DctCount = MAX_DCTS_PER_NODE_ON;
- NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_ON;
- NBPtr->NodeCount = MAX_NODES_SUPPORTED_ON;
- NBPtr->Ganged = FALSE;
- NBPtr->PosTrnPattern = POS_PATTERN_256B;
- NBPtr->MemCleared = FALSE;
- NBPtr->StartupSpeed = DDR800_FREQUENCY;
- NBPtr->RcvrEnDlyLimit = 0xFF;
- NBPtr->DefDctSelIntLvAddr = 3;
- NBPtr->FreqChangeParam = (MEM_FREQ_CHANGE_PARAM *) &FreqChangeParamON;
- NBPtr->NbFreqChgState = 0;
-
- LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader);
-
- for (i = 0; i < EnumSize; i++) {
- NBPtr->IsSupported[i] = FALSE;
- }
-
- for (i = 0; i < NumberOfHooks; i++) {
- NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK*, VOID*)) memDefTrue;
- }
-
- FeatPtr->InitHwRxEn (NBPtr);
-
-
- NBPtr->SwitchDCT = (VOID (*) (MEM_NB_BLOCK*, UINT8)) memDefRet;
- NBPtr->SwitchChannel = (VOID (*) (MEM_NB_BLOCK*, UINT8)) memDefRet;
- NBPtr->GetBitField = MemNGetBitFieldNb;
- NBPtr->SetBitField = MemNSetBitFieldNb;
- NBPtr->SetMaxLatency = MemNSetMaxLatencyON;
- NBPtr->getMaxLatParams = MemNGetMaxLatParamsClientON;
- NBPtr->InitializeMCT = (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue;
- NBPtr->FinalizeMCT = MemNFinalizeMctON;
- NBPtr->SendMrsCmd = MemNSendMrsCmdON;
- NBPtr->sendZQCmd = MemNSendZQCmdNb;
- NBPtr->WritePattern = MemNWritePatternON;
- NBPtr->ReadPattern = MemNReadPatternON;
- NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK*, UINT32)) memDefRet;
-
- NBPtr->CompareTestPattern = MemNCompareTestPatternNb;
- NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb;
- NBPtr->InitMCT = MemNInitMCTNb;
- NBPtr->StitchMemory = MemNStitchMemoryON;
- NBPtr->AutoConfig = MemNAutoConfigON;
- NBPtr->PlatformSpec = MemNPlatformSpecUnb;
- NBPtr->DisableDCT = MemNDisableDCTNb;
- NBPtr->StartupDCT = MemNStartupDCTUnb;
- NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb;
- NBPtr->MemNCapSpeedBatteryLife = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
- NBPtr->ChangeFrequency = MemNChangeFrequencyUnb;
- NBPtr->RampUpFrequency = MemNRampUpFrequencyNb;
- NBPtr->ChangeNbFrequency = MemNChangeNbFrequencyNb;
- NBPtr->ProgramNbPsDependentRegs = MemNProgramNbPstateDependentRegistersClientNb;
- NBPtr->ProgramCycTimings = MemNProgramCycTimingsClientNb;
- NBPtr->SyncDctsReady = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefTrue;
- NBPtr->HtMemMapInit = MemNHtMemMapInitON;
- NBPtr->SyncAddrMapToAllNodes = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
- NBPtr->CpuMemTyping = MemNCPUMemTypingNb;
- NBPtr->UMAMemTyping = MemNUMAMemTypingNb;
- NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingON;
- NBPtr->AfterDqsTraining = MemNAfterDQSTrainingON;
- NBPtr->OtherTiming = MemNOtherTimingON;
- NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb;
- NBPtr->TechBlockSwitch = MemNTechBlockSwitchON;
- NBPtr->SetEccSymbolSize = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
- NBPtr->TrainingFlow = memNTrainFlowControl[DDR3_TRAIN_FLOW];
- NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb;
- NBPtr->PollBitField = MemNPollBitFieldNb;
- NBPtr->BrdcstCheck = MemNBrdcstCheckON;
- NBPtr->BrdcstSet = MemNSetBitFieldNb;
- NBPtr->GetTrainDly = MemNGetTrainDlyNb;
- NBPtr->SetTrainDly = MemNSetTrainDlyNb;
- NBPtr->PhyFenceTraining = MemNPhyFenceTrainingUnb;
- NBPtr->GetSysAddr = MemNGetMCTSysAddrNb;
- NBPtr->RankEnabled = MemNRankEnabledNb;
- NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldON;
- NBPtr->MemNBeforeDramInitNb = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
- NBPtr->MemNBeforePlatformSpecNb = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
- NBPtr->MemNInitPhyComp = MemNInitPhyCompClientNb;
- NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyClientNb;
- NBPtr->MemPPhyFenceTrainingNb = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
- NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitON;
- NBPtr->MemNPFenceAdjustNb = (VOID (*) (MEM_NB_BLOCK *, UINT16 *)) memDefRet;
- NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsClientNb;
- NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb;
- NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb;
- NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb;
- NBPtr->CSPerChannel = MemNCSPerChannelON;
- NBPtr->CSPerDelay = MemNCSPerDelayNb;
- NBPtr->FlushPattern = MemNFlushPatternNb;
- NBPtr->GetUmaSize = MemNGetUmaSizeON;
- NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdClientNb;
- NBPtr->EnableSwapIntlvRgn = (VOID (*) (MEM_NB_BLOCK *, UINT32, UINT32)) memDefRet;
- NBPtr->ChangeNbFrequencyWrap = MemNChangeNbFrequencyWrapON;
- NBPtr->WaitXMemClks = MemNWaitXMemClksNb;
- NBPtr->MemNGetDramTerm = MemNGetDramTermNb;
- NBPtr->MemNGetDynDramTerm = MemNGetDynDramTermNb;
- NBPtr->MemNGetMR0CL = MemNGetMR0CLNb;
- NBPtr->MemNGetMR0WR = MemNGetMR0WRNb;
- NBPtr->MemNGetMR2CWL = MemNGetMR2CWLNb;
- NBPtr->AllocateC6Storage = MemNAllocateC6StorageClientNb;
-
- NBPtr->IsSupported[SetDllShutDown] = TRUE;
- NBPtr->IsSupported[CheckPhyFenceTraining] = TRUE;
- NBPtr->IsSupported[CheckSendAllMRCmds] = TRUE;
- NBPtr->IsSupported[CheckFindPSDct] = TRUE;
- NBPtr->IsSupported[CheckODTControls] = TRUE;
- NBPtr->IsSupported[FenceTrnBeforeDramInit] = TRUE;
- NBPtr->IsSupported[WLSeedAdjust] = TRUE;
- NBPtr->IsSupported[ReverseMaxRdLatTrain] = TRUE;
- NBPtr->IsSupported[DramSrHys] = TRUE;
- NBPtr->IsSupported[CheckMaxDramRate] = TRUE;
- NBPtr->IsSupported[AdjustTwr] = TRUE;
- NBPtr->IsSupported[UnifiedNbFence] = TRUE;
- NBPtr->IsSupported[ChannelPDMode] = TRUE; // Erratum 435
-
- NBPtr->FamilySpecificHook[OverrideRcvEnSeed] = MemNOverrideRcvEnSeedON;
- NBPtr->FamilySpecificHook[BeforePhyFenceTraining] = MemNBeforePhyFenceTrainingClientNb;
- NBPtr->FamilySpecificHook[AdjustTxpdll] = MemNAdjustTxpdllClientNb;
- NBPtr->FamilySpecificHook[ForceRdDqsPhaseB] = MemNForceRdDqsPhaseBON;
- NBPtr->FamilySpecificHook[SetDqsODT] = MemNSetDqsODTON;
- NBPtr->FamilySpecificHook[ResetRxFifoPtr] = MemNResetRxFifoPtrON;
-
- FeatPtr->InitCPG (NBPtr);
- FeatPtr->InitEarlySampleSupport (NBPtr);
- NBPtr->FeatPtr = FeatPtr;
- //
- // Calculate SPD Offsets per channel and assign pointers
- // to the data.
- //
- NBPtr->MCTPtr->DctData->ChData->SpdPtr = MemPtr->SpdDataStructure;
-
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initializes the default values in the MEM_DATA_STRUCT
- *
- * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
- *
- * @retval None
- */
-VOID
-MemNInitDefaultsON (
- IN OUT MEM_DATA_STRUCT *MemPtr
- )
-{
- UINT8 Socket;
- MEM_PARAMETER_STRUCT *RefPtr;
- AGESA_TESTPOINT (TpProcMemBeforeMemDataInit, &(MemPtr->StdHeader));
- ASSERT (MemPtr != NULL);
- RefPtr = MemPtr->ParameterListPtr;
-
- // Memory Map/Mgt.
- // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB
- RefPtr->BottomIo = 0xE0;
- RefPtr->UmaMode = UserOptions.CfgUmaMode;
- RefPtr->UmaSize = UserOptions.CfgUmaSize;
- RefPtr->MemHoleRemapping = TRUE;
-
- // Dram Timing
- RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect;
- RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect;
- for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) {
- MemPtr->SocketList[Socket].ChannelPtr[0] = NULL;
- MemPtr->SocketList[Socket].TimingsPtr[0] = NULL;
- }
-
- // Memory Clear
- RefPtr->EnableMemClr = TRUE;
-
- // TableBasedAlterations
- RefPtr->TableBasedAlterations = NULL;
-
- // Platform config table
- RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration;
-
- // Memory Restore
- RefPtr->MemRestoreCtl = FALSE;
- RefPtr->SaveMemContextCtl = FALSE;
- AmdS3ParamsInitializer (&RefPtr->MemContext);
-
- // Dram Configuration
- RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving;
- RefPtr->EnableNodeIntlv = FALSE;
- RefPtr->EnableChannelIntlv = FALSE;
- RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle;
- RefPtr->EnableParity = FALSE;
- RefPtr->EnableOnLineSpareCtl = FALSE;
-
- // Dram Power
- RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown;
-
- // ECC
- RefPtr->EnableEccFeature = FALSE;
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- *
- * This function writes training pattern
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Pattern[] - Pattern to write
- * @param[in] Address - System Address [47:16]
- * @param[in] ClCount - Number of cache lines
- *
- */
-
-VOID
-MemNWritePatternON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 Address,
- IN UINT8 Pattern[],
- IN UINT16 ClCount
- )
-{
- Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
- MemUWriteCachelines (Address, Pattern, ClCount);
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- *
- * This function reads training pattern
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Buffer[] - Buffer to fill
- * @param[in] Address - System Address [47:16]
- * @param[in] ClCount - Number of cache lines
- *
- */
-
-VOID
-MemNReadPatternON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Buffer[],
- IN UINT32 Address,
- IN UINT16 ClCount
- )
-{
- Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
- MemUReadCachelines (Buffer, Address, ClCount);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initiates DQS training for Client NB
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-BOOLEAN
-memNEnableTrainSequenceON (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- BOOLEAN Retval;
- Retval = TRUE;
- if (!MemNIsIdSupportedON (NBPtr, &(NBPtr->MemPtr->DiesPerSystem[NBPtr->MCTPtr->NodeId].LogicalCpuid))) {
- Retval = FALSE;
- }
- return Retval;
-}
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnon.h b/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnon.h
deleted file mode 100644
index e5f8683..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnon.h
+++ /dev/null
@@ -1,250 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnon.h
- *
- * Ontario Northbridge block
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem)
- * @e \$Revision: 37115 $ @e \$Date: 2010-08-31 07:10:42 +0800 (Tue, 31 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MNON_H_
-#define _MNON_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-#define MAX_CHANNELS_PER_SOCKET_ON 1
-#define MAX_DCTS_PER_NODE_ON 1
-#define MAX_CHANNELS_PER_DCT_ON 1
-#define MAX_DIMMS_PER_CHANNEL_ON 2
-#define MAX_NODES_SUPPORTED_ON 1
-#define MAX_CS_PER_CHANNEL_ON 4
-
-#define DEFAULT_WR_ODT_ON_ON 6
-#define DEFAULT_RD_ODT_ON_ON 6
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-MemConstructNBBlockON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN MEM_FEAT_BLOCK_NB *FeatPtr,
- IN MEM_SHARED_DATA *SharedPtr,
- IN UINT8 NodeID
- );
-
-VOID
-MemNInitDefaultsON (
- IN OUT MEM_DATA_STRUCT *MemPtr
- );
-
-VOID
-MemNSendMrsCmdON (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNAutoConfigON (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNOtherTimingON (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-UINT8
-MemNCSPerChannelON (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNWritePatternON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 Address,
- IN UINT8 Pattern[],
- IN UINT16 ClCount
- );
-
-VOID
-MemNReadPatternON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Buffer[],
- IN UINT32 Address,
- IN UINT16 ClCount
- );
-
-VOID
-MemNInitNBRegTableON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT TSEFO NBRegTable[]
- );
-
-VOID
-MemNBeforeDQSTrainingON (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNAfterDQSTrainingON (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNPlatformSpecificFormFactorInitON (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNIsIdSupportedON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN CPU_LOGICAL_ID *LogicalIdPtr
- );
-
-UINT32
-MemNCmnGetSetFieldON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN BIT_FIELD_NAME FieldName,
- IN UINT32 Field
- );
-
-UINT32
-MemNGetUmaSizeON (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNBrdcstCheckON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN BIT_FIELD_NAME FieldName,
- IN UINT32 Field
- );
-
-VOID
-MemNTechBlockSwitchON (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNStitchMemoryON (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNHtMemMapInitON (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNSetMaxLatencyON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT16 MaxRcvEnDly
- );
-
-BOOLEAN
-MemNFinalizeMctON (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-memNEnableTrainSequenceON (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNChangeNbFrequencyWrapON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 NBPstate
- );
-
-BOOLEAN
-MemNOverrideRcvEnSeedON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT VOID *SeedPtr
- );
-
-VOID
-MemNGetMaxLatParamsClientON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT16 MaxDlyForMaxRdLat,
- IN OUT UINT16 *MinDlyPtr,
- IN OUT UINT16 *MaxDlyPtr,
- IN OUT UINT16 *DlyBiasPtr
- );
-
-BOOLEAN
-MemNForceRdDqsPhaseBON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT VOID *RdDqsDlyPtr
- );
-
-BOOLEAN
-MemNSetDqsODTON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT VOID *OptParam
- );
-
-BOOLEAN
-MemNResetRxFifoPtrON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT VOID *OptParam
- );
-#endif /* _MNON_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnoton.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnoton.c
deleted file mode 100644
index 3fe33d6..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnoton.c
+++ /dev/null
@@ -1,230 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnoton.c
- *
- * Northbridge Non-SPD timings for ON
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/ON)
- * @e \$Revision: 39158 $ @e \$Date: 2010-10-07 21:34:36 +0800 (Thu, 07 Oct 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB
-#include "mnon.h"
-#include "mu.h"
-#include "Filecode.h"
-#define FILECODE PROC_MEM_NB_ON_MNOTON_FILECODE
-
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-VOID
-STATIC
-MemNSetOtherTimingON (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-STATIC
-MemNPowerDownCtlON (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the non-SPD timings
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemNOtherTimingON (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MemNSetOtherTimingON (NBPtr);
- MemNPowerDownCtlON (NBPtr);
-
- return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the non-SPD timings into the PCI registers
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-STATIC
-MemNSetOtherTimingON (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- INT16 ROD;
- INT16 WOD;
- UINT8 LD;
- UINT8 Tcwl;
- INT16 CDDTrdrd;
- INT16 Trdrd;
- INT16 CDDTwrwr;
- INT16 Twrwr;
- INT16 CDDTwrrdSD;
- INT16 TwrrdSD;
- INT16 CDDTwrrd;
- INT16 Twrrd;
- INT16 CDDTrwtTO;
- INT16 TrwtTO;
-
- ROD = (DEFAULT_RD_ODT_ON_ON > 6) ? (DEFAULT_RD_ODT_ON_ON - 6) : 0;
- WOD = (DEFAULT_RD_ODT_ON_ON > 6) ? (DEFAULT_WR_ODT_ON_ON - 6) : 0;
-
- Tcwl = (UINT8) (NBPtr->DCTPtr->Timings.Speed / 133) + 2;
- LD = NBPtr->DCTPtr->Timings.CasL - Tcwl;
-
- // TrdrdSD = 3
- MemNSetBitFieldNb (NBPtr, BFTrdrdSD, 2 - 2 + 1);
-
- // Trdrd = CEIL(MAX(ROD + 3, CDDTrdrd/2 + (F2x[94]SlowAccessMode ? 3 : 3.5)))
- CDDTrdrd = (MemNCalcCDDNb (NBPtr, AccessRcvEnDly, AccessRcvEnDly, FALSE, TRUE) + (INT16) ((NBPtr->ChannelPtr->SlowMode ? 6 : 7) + 1)) / (INT16) 2;
- Trdrd = MAX (ROD + 3, CDDTrdrd);
- Trdrd = MIN (MAX (Trdrd, 2), 10);
- MemNSetBitFieldNb (NBPtr, BFTrdrd, (UINT8) (Trdrd - 2));
-
- // TwrwrSD = WOD + 3
- MemNSetBitFieldNb (NBPtr, BFTwrwrSD, (WOD + 3 - 1));
-
- // Twrwr = CEIL(MAX(WOD + 3, CDDTwrwr / 2 + 3.5))
- CDDTwrwr = (MemNCalcCDDNb (NBPtr, AccessWrDqsDly, AccessWrDqsDly, FALSE, TRUE) + (INT16) (7 + 1)) / (INT16) 2;
- Twrwr = MAX (WOD + 3, CDDTwrwr);
- Twrwr = MIN (MAX (Twrwr, 1), 10);
- MemNSetBitFieldNb (NBPtr, BFTwrwr, (UINT8) (Twrwr - 1));
-
- // TwrrdSD = CEIL(MAX(1, MAX(WOD, CDDTwrrdSD / 2 + 0.5) - LD + 3))
- CDDTwrrdSD = (MemNCalcCDDNb (NBPtr, AccessWrDqsDly, AccessRcvEnDly, TRUE, FALSE) + (INT16) (1 + 1)) / (INT16) 2;
- TwrrdSD = MAX (WOD, CDDTwrrdSD) - LD + 3;
- TwrrdSD = MIN (MAX (TwrrdSD, 1), 11);
- MemNSetBitFieldNb (NBPtr, BFTwrrdSD, (UINT8) (TwrrdSD - 1));
-
- // Twrrd = CEIL(MAX(1, MAX(WOD, CDDTwrrd / 2 + 0.5) - LD + 3))
- CDDTwrrd = (MemNCalcCDDNb (NBPtr, AccessWrDqsDly, AccessRcvEnDly, FALSE, TRUE) + (INT16) (1 + 1)) / (INT16) 2;
- Twrrd = MAX (WOD, CDDTwrrd) - LD + 3;
- Twrrd = MIN (MAX (Twrrd, 1), 11);
- Twrrd = MAX (Twrrd, TwrrdSD);
- MemNSetBitFieldNb (NBPtr, BFTwrrd, (UINT8) (Twrrd - 1));
-
- // TrwtTO = CEIL(MAX(ROD, CDDTrwtTO / 2 - 0.5) + LD + 3).
- CDDTrwtTO = (MemNCalcCDDNb (NBPtr, AccessRcvEnDly, AccessWrDqsDly, TRUE, TRUE) + (INT16) (1 - 1)) / (INT16) 2;
- TrwtTO = MAX (ROD, CDDTrwtTO) + LD + 3;
- TrwtTO = MIN (MAX (TrwtTO, 3), 17);
- MemNSetBitFieldNb (NBPtr, BFTrwtTO, (UINT8) (TrwtTO - 2));
-
- // TrwtWB should be set to 0xF for ON.
- MemNSetBitFieldNb (NBPtr, BFTrwtWB, 4);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function enables power down mode
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-STATIC
-MemNPowerDownCtlON (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- if (NBPtr->RefPtr->EnablePowerDown) {
- MemNSetTxpNb (NBPtr);
- MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 1);
- }
-
- if (NBPtr->RefPtr->EnableBankSwizzle) {
- MemNSetBitFieldNb (NBPtr, BFBankSwizzleMode, 1);
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnphyon.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnphyon.c
deleted file mode 100644
index e20b8cc..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnphyon.c
+++ /dev/null
@@ -1,244 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnphyon.c
- *
- * Northbridge Phy support for ON
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/ON)
- * @e \$Revision: 37401 $ @e \$Date: 2010-09-03 05:32:06 +0800 (Fri, 03 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mu.h"
-#include "merrhdl.h"
-#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB
-#include "mnon.h"
-#include "Filecode.h"
-#define FILECODE PROC_MEM_NB_ON_MNPHYON_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define MAX_CS_PER_CHANNEL_ON 4
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This is a general purpose function that executes before DRAM training
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNBeforeDQSTrainingON (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MemTBeginTraining (NBPtr->TechPtr);
-
- MemNSetBitFieldNb (NBPtr, BFDisAutoRefresh, 1);
- MemNSetBitFieldNb (NBPtr, BFZqcsInterval, 0);
- MemNSetBitFieldNb (NBPtr, BFRxMaxDurDllNoLock, 0);
- MemNSetBitFieldNb (NBPtr, BFTxMaxDurDllNoLock, 0);
- MemNSetBitFieldNb (NBPtr, BFEnRxPadStandby, 0);
- MemNSetBitFieldNb (NBPtr, BFPrefCpuDis, 1);
- MemNSetBitFieldNb (NBPtr, BFDctWrLimit, 0x1F);
- MemNSetBitFieldNb (NBPtr, BFEnCpuSerRdBehindNpIoWr, 1);
- MemNSetBitFieldNb (NBPtr, BFDbeGskMemClkAlignMode, 0);
- MemNSetBitFieldNb (NBPtr, BFMaxLatency, 0x12);
- MemNSetBitFieldNb (NBPtr, BFTraceModeEn, 0);
-
- // Enable cut through mode for NB P0
- MemNSetBitFieldNb (NBPtr, BFDisCutThroughMode, 0);
-
- MemTEndTraining (NBPtr->TechPtr);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This is a general purpose function that executes after DRAM training
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNAfterDQSTrainingON (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- if (NBPtr->DCTPtr->Timings.Speed <= DDR1066_FREQUENCY) {
- MemNSetBitFieldNb (NBPtr, BFAddrCmdTriEn, 1);
- }
- MemNSetBitFieldNb (NBPtr, BFDisAutoRefresh, 0);
- MemNSetBitFieldNb (NBPtr, BFZqcsInterval, 2);
- MemNSetBitFieldNb (NBPtr, BFEnRxPadStandby, (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) ? 0x1000 : 0);
- MemNSetBitFieldNb (NBPtr, BFPrefCpuDis, 0);
- MemNSetBitFieldNb (NBPtr, BFDctWrLimit, 0x1C);
- MemNSetBitFieldNb (NBPtr, BFDramTrainPdbDis, 1);
- MemNSetBitFieldNb (NBPtr, BFEnCpuSerRdBehindNpIoWr, 0);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function returns the number of chipselects per channel of Ontario.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return
- */
-
-UINT8
-MemNCSPerChannelON (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- return MAX_CS_PER_CHANNEL_ON;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function overrides the seed for hardware based RcvEn training of Ontario.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *SeedPtr - Pointer to the seed value.
- *
- * @return TRUE
- */
-
-BOOLEAN
-MemNOverrideRcvEnSeedON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT VOID *SeedPtr
- )
-{
- *(UINT16*) SeedPtr = 0x5B;
- return TRUE;
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function force the Rd Dqs Delay to phase B (0x20)
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *RdDqsDlyPtr - Pointer to Rd DQS delay.
- *
- * @return TRUE
- */
-
-BOOLEAN
-MemNForceRdDqsPhaseBON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT VOID *RdDqsDlyPtr
- )
-{
- if ((NBPtr->DCTPtr->Timings.Speed == DDR1333_FREQUENCY) && (*(UINT8 *) RdDqsDlyPtr < 0x20)) {
- *(UINT8 *) RdDqsDlyPtr = 0x20;
- }
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function resets RxFifo pointer during Read DQS training
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *OptParam - Optional parameter
- *
- * @return TRUE
- */
-
-BOOLEAN
-MemNResetRxFifoPtrON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT VOID *OptParam
- )
-{
- if (NBPtr->TechPtr->Direction == DQS_READ_DIR) {
- MemNSetBitFieldNb (NBPtr, BFRxPtrInitReq, 1);
- MemNPollBitFieldNb (NBPtr, BFRxPtrInitReq, 0, PCI_ACCESS_TIMEOUT, FALSE);
- }
- return TRUE;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnprotoon.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnprotoon.c
deleted file mode 100644
index d8c9c9d..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnprotoon.c
+++ /dev/null
@@ -1,165 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnprotoon.c
- *
- * Northbridge support functions for Errata and early samples
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/ON)
- * @e \$Revision: 37691 $ @e \$Date: 2010-09-10 04:28:23 +0800 (Fri, 10 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "cpuRegisters.h"
-#include "AdvancedApi.h"
-#include "Filecode.h"
-#define FILECODE PROC_MEM_NB_ON_MNPROTOON_FILECODE
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemNForceAutoCompON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT VOID *OptParam
- );
-
-BOOLEAN
-STATIC
-MemNDetectMemPllErrorON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT VOID *OptParam
- );
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initializes early sample support for Ontario
- *
- * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-VOID
-MemNInitEarlySampleSupportON (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- if ((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F14_ON_A0) != 0) {
- NBPtr->IsSupported[DramSrHys] = FALSE; // UBTS 233978
- NBPtr->NBRegTable[BFRxMaxDurDllNoLock] = 0;
- NBPtr->NBRegTable[BFTxMaxDurDllNoLock] = 0;
- NBPtr->FamilySpecificHook[ForceAutoComp] = MemNForceAutoCompON;
- }
- if ((NBPtr->MCTPtr->LogicalCpuid.Revision & (AMD_F14_ON_A0 | AMD_F14_ON_A1)) != 0) {
- NBPtr->FamilySpecificHook[DetectMemPllError] = MemNDetectMemPllErrorON;
- }
-}
-
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- *
- *
- * This function forces auto compensation to be disabled all the time for
- * ON A0
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] OptParam - Optional parameter
- *
- * @return TRUE
- * ----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemNForceAutoCompON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT VOID *OptParam
- )
-{
- MemNSetBitFieldNb (NBPtr, BFPNOdtCal, 0x2020);
- MemNSetBitFieldNb (NBPtr, BFPNDrvCal, 0x8080);
- MemNSetBitFieldNb (NBPtr, BFCalVal, 0x8000);
-
- return TRUE;
-}
-
-/*-----------------------------------------------------------------------------
- *
- *
- * This function detects MemPll divide by 3 bug
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] OptParam - Optional parameter
- *
- * @return TRUE
- * ----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemNDetectMemPllErrorON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT VOID *OptParam
- )
-{
- UINT16 Value;
-
- Value = 0xFFFF;
- if ((*(UINT8 *) OptParam) < 5) {
- LibAmdIoWrite (AccessWidth16, IDS_DEBUG_PORT, &Value, &NBPtr->MemPtr->StdHeader);
- }
- return TRUE;
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnregon.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnregon.c
deleted file mode 100644
index 3f99b2c..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/ON/mnregon.c
+++ /dev/null
@@ -1,600 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnregon.c
- *
- * Common Northbridge register related functions for ON
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/ON)
- * @e \$Revision: 39747 $ @e \$Date: 2010-10-15 02:58:08 +0800 (Fri, 15 Oct 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mnon.h"
-#include "merrhdl.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "heapManager.h"
-#include "Filecode.h"
-#define FILECODE PROC_MEM_NB_ON_MNREGON_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define PHY_DIRECT_ADDRESS_MASK 0x0D000000
-
-STATIC CONST UINT8 InstancesPerTypeON[8] = {8, 2, 1, 0, 2, 0, 1, 1};
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/*-----------------------------------------------------------------------------*/
-/**
- *
- * This function matches the CPU_LOGICAL_ID with certain criteria to
- * determine if it is supported by this NBBlock.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID
- *
- * @return TRUE - This node is a Ontario.
- * @return FALSE - This node is not a Ontario.
- */
-BOOLEAN
-MemNIsIdSupportedON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN CPU_LOGICAL_ID *LogicalIdPtr
- )
-{
- if (((LogicalIdPtr->Family & AMD_FAMILY_14_ON) != 0)
- && ((LogicalIdPtr->Revision & AMD_F14_ALL) != 0)) {
- return TRUE;
- } else {
- return FALSE;
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Check if bitfields of all enabled DCTs on a die have the expected value. Ignore
- * DCTs that are disabled.
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] FieldName - Bit Field name
- * @param[in] Field - Value to be checked
- *
- * @return TRUE - All enabled DCTs have the expected value on the bitfield.
- * @return FALSE - Not all enabled DCTs have the expected value on the bitfield.
- *
- * ----------------------------------------------------------------------------
- */
-BOOLEAN
-MemNBrdcstCheckON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN BIT_FIELD_NAME FieldName,
- IN UINT32 Field
- )
-{
- if (MemNGetBitFieldNb (NBPtr, FieldName) != Field) {
- return FALSE;
- }
- return TRUE;
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------*/
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function gets or sets a value to a bit field in a PCI register.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] FieldName - Bit Field to be programmed
- * @param[in] Field - Value to be programmed
- * @param[in] IsSet - Indicates if the function will set or get
- *
- * @return value read, if the function is used as a "get"
- */
-
-UINT32
-MemNCmnGetSetFieldON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN BIT_FIELD_NAME FieldName,
- IN UINT32 Field
- )
-{
- TSEFO Address;
- PCI_ADDR PciAddr;
- UINT8 Type;
- UINT8 IsLinked;
- UINT32 Value;
- UINT32 Highbit;
- UINT32 Lowbit;
- UINT32 Mask;
- UINT8 IsPhyDirectAccess;
- UINT8 IsWholeRegAccess;
- UINT8 NumOfInstances;
- UINT8 Instance;
-
- Value = 0;
- if ((FieldName < BFEndOfList) && (FieldName >= 0)) {
- Address = NBPtr->NBRegTable[FieldName];
- if (Address) {
- Lowbit = TSEFO_END (Address);
- Highbit = TSEFO_START (Address);
- Type = (UINT8) TSEFO_TYPE (Address);
- IsLinked = (UINT8) TSEFO_LINKED (Address);
- IsPhyDirectAccess = (UINT8) TSEFO_DIRECT_EN (Address);
- IsWholeRegAccess = (UINT8) TSEFO_WHOLE_REG_ACCESS (Address);
-
- ASSERT ((Address & ((UINT32) 1) << 29) == 0); // Old Phy direct access method is not supported
-
- Address = TSEFO_OFFSET (Address);
-
- // By default, a bit field has only one instance
- NumOfInstances = 1;
-
- if ((Type == DCT_PHY_ACCESS) && IsPhyDirectAccess) {
- Address |= PHY_DIRECT_ADDRESS_MASK;
- if (IsWholeRegAccess) {
- // In the case of whole regiter access (bit 0 to 15),
- // HW broadcast and nibble mask will be used.
- Address |= Lowbit << 16;
- Lowbit = 0;
- Highbit = 15;
- } else {
- // In the case only some bits on a register is accessed,
- // BIOS will do read-mod-write to all chiplets manually.
- // And nibble mask will be 1111b always.
- Address |= 0x000F0000;
- Field >>= Lowbit;
- if ((Address & 0x0F00) == 0x0F00) {
- // Broadcast mode
- // Find out how many instances to write to
- NumOfInstances = InstancesPerTypeON[(Address >> 13) & 0x7];
- if (!IsSet) {
- // For read, only read from instance 0 in broadcast mode
- NumOfInstances = 1;
- }
- }
- }
- }
-
- ASSERT (NumOfInstances > 0);
-
- for (Instance = 0; Instance < NumOfInstances; Instance++) {
- if (Type == NB_ACCESS) {
- PciAddr.AddressValue = Address;
- PciAddr.Address.Device = NBPtr->PciAddr.Address.Device;
- PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus;
- PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment;
- Address = PciAddr.AddressValue;
- LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
- if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) &&
- (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) {
- IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Value);
- }
- } else if (Type == DCT_PHY_ACCESS) {
- if (IsPhyDirectAccess && (NumOfInstances > 1)) {
- Address = (Address & 0x0FFFF0FF) | (((UINT32) Instance) << 8);
- }
- MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
- MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
- Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
- IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%d9C_%x = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Value);
- } else if (Type == DCT_EXTRA) {
- MemNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address);
- MemNPollBitFieldNb (NBPtr, BFDctExtraAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
- Value = MemNGetBitFieldNb (NBPtr, BFDctExtraDataReg);
- IDS_HDT_CONSOLE (MEM_GETREG, "~Fn2_%dF4_%x = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Value);
- } else {
- IDS_ERROR_TRAP;
- }
-
- if (IsSet) {
- // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
- if ((Highbit - Lowbit) != 31) {
- Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
- } else {
- Mask = (UINT32)0xFFFFFFFF;
- }
- Value &= ~(Mask << Lowbit);
- Value |= (Field & Mask) << Lowbit;
-
- if (Type == NB_ACCESS) {
- PciAddr.AddressValue = Address;
- LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
- if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) &&
- (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) {
- IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Highbit, Lowbit, Field);
- }
- } else if (Type == DCT_PHY_ACCESS) {
- MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
- Address |= DCT_ACCESS_WRITE;
- MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
- MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
- IDS_HDT_CONSOLE (MEM_SETREG, "~Fn2_%d9C_%x [%d:%d] = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Highbit, Lowbit, Field);
- } else if (Type == DCT_EXTRA) {
- MemNSetBitFieldNb (NBPtr, BFDctExtraDataReg, Value);
- Address |= DCT_ACCESS_WRITE;
- MemNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address);
- MemNPollBitFieldNb (NBPtr, BFDctExtraAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
- IDS_HDT_CONSOLE (MEM_SETREG, "~Fn2_%dF4_%x [%d:%d] = %x\n", NBPtr->Dct, Address & 0x0FFFFFFF, Highbit, Lowbit, Field);
- } else {
- IDS_ERROR_TRAP;
- }
- if (IsLinked) {
- MemNCmnGetSetFieldON (NBPtr, 1, FieldName + 1, Field >> (Highbit - Lowbit + 1));
- }
- } else {
- Value = Value >> Lowbit; // Shift
- // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
- if ((Highbit - Lowbit) != 31) {
- Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
- }
- if (IsLinked) {
- Value |= MemNCmnGetSetFieldON (NBPtr, 0, FieldName + 1, 0) << (Highbit - Lowbit + 1);
- }
- // For direct phy access, shift the bit back for compatibility reason.
- if ((Type == DCT_PHY_ACCESS) && IsPhyDirectAccess) {
- Value <<= Lowbit;
- }
- }
- }
- }
- } else {
- IDS_ERROR_TRAP; // Invalid bit field index
- }
- return Value;
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initializes bit field translation table
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] NBRegTable[] - Pointer to the bit field data structure
- *
- */
-
-VOID
-MemNInitNBRegTableON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT TSEFO NBRegTable[]
- )
-{
- UINT16 i;
- for (i = 0; i < BFEndOfList; i++) {
- NBRegTable[i] = 0;
- }
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31, 0, BFDevVendorIDReg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 31, 24, BFDramHoleBase);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 15, 7, BFDramHoleOffset);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0xF0), 0, 0, BFDramHoleValid);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31, 0, BFCSBaseAddr0Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31, 0, BFCSBaseAddr1Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31, 0, BFCSBaseAddr2Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31, 0, BFCSBaseAddr3Reg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31, 0, BFCSMask0Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31, 0, BFCSMask1Reg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 0, BFDramControlReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 0, BFDramInitRegReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31, 0, BFDramBankAddrReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31, 0, BFDramMRSReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 0, BFDramTimingLoReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 0, BFDramTimingHiReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31, 0, BFDramConfigLoReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 0, BFDramConfigHiReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 0, BFDctAddlOffsetReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 31, BFDctAccessDone);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31, 0, BFDctAddlDataReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA0), 31, 0, BFDramConfigMiscReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 31, 0, BFDramCtrlMiscReg2);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF0), 31, 0, BFDctExtraOffsetReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF0), 31, 31, BFDctExtraAccessDone);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF4), 31, 0, BFDctExtraDataReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 31, 0, BFMctCfgHiReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 31, 0, BFMctCfgLoReg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 8, BFNonSPDHi);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 3, 0, BFRdPtrInit);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 6, 6, BFRxPtrInitReq);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 9, 8, BFTwrrdHi);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 11, 10, BFTwrwrHi);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 13, 12, BFTrdrdHi);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 17, 17, BFAddrCmdTriEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 20, 20, BFForceCasToSlot0);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 21, 21, BFDisCutThroughMode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15, 0, BFMrsAddress);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 18, 16, BFMrsBank);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 22, 20, BFMrsChipSel);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 24, 24, BFSendPchgAll);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 25, 25, BFSendAutoRefresh);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 1, 0, BFBurstCtrl);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 3, 2, BFDrvImpCtrl);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 6, 4, BFTwrDDR3);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 22, 20, BFTcwl);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 23, 23, BFPchgPDModeSel);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 3, 0, BFTcl);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 24, BFMemClkDis);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 0, BFNonSPD);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 3, 0, BFTrwtWB);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 7, 4, BFTrwtTO);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 11, 10, BFTwrrd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 13, 12, BFTwrwr);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 15, 14, BFTrdrd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 17, 16, BFTref);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 22, 20, BFTrfc0);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 25, 23, BFTrfc1);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 0, 0, BFInitDram);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 1, 1, BFExitSelfRef);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 17, 17, BFEnterSelfRef);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 22, 21, BFIdleCycInit);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 25, 25, BFEnDispAutoPrecharge);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 26, 26, BFDbeSkidBufDis);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 27, 27, BFDisDllShutdownSR);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 4, 0, BFMemClkFreq);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 7, 7, BFMemClkFreqVal);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 15, 15, BFPowerDownEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 16, 16, BFPowerDownMode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 20, 20, BFSlowAccessMode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 22, 22, BFBankSwizzleMode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 27, 24, BFDcqBypassMax);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 28, BFFourActWindow);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 0, 0, BFDoubleTrefRateEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA4), 2, 1, BFThrottleEn);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 22, 21, BFDbeGskMemClkAlignMode);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xAC), 0, 0, BFMemTempHot);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xC0), 0, 0, BFTraceModeEn);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 3, 3, BFMemClrInit);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 8, 8, BFDramEnabled);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 9, 9, BFMemClrBusy);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 10, 10, BFMemCleared);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 9, 9, BFDctSelBankSwap);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x118), 19, 19, BFC6DramLock);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 12, 12, BFPrefCpuDis);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 6, 2, BFDctWrLimit);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1C0), 23, 23, BFRdTrainGo);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1C0), 22, 22, BFRdDramTrainMode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1C0), 20, 20, BFDramTrainPdbDis);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1C0), 17, 2, BFTrainLength);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1C0), 1, 1, BFWrTrainGo);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1C0), 0, 0, BFWrDramTrainMode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1C8), 31, 0, BFWrTrainAdrPtrLo);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1CC), 17, 16, BFWrTrainAdrPtrHi);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1D0), 9, 0, BFWrTrainBufAddr);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1D4), 31, 0, BFWrTrainBufDat);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1E8), 15, 8, BFTrainCmpSts2);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1E8), 7, 0, BFTrainCmpSts);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xDC), 19, 19, BFNclkFreqDone);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4), 5, 0, BFMainPllOpFreqId);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xDC), 26, 20, BFNbPs0NclkDiv);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xE8), 7, 5, BFDdrMaxRate);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x188), 22, 22, BFEnCpuSerRdBehindNpIoWr);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (6, 0x90), 6, 0, BFNbPs1NclkDiv);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (6, 0x90), 28, 28, BFNbPsForceReq);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (6, 0x90), 30, 30, BFNbPsCtrlDis);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (6, 0x98), 30, 30, BFNbPsCsrAccSel);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (6, 0x98), 31, 31, BFNbPsDbgEn);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (4, 0x12C), 11, 0, BFC6Base);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (4, 0x164), 0, 0, BFFixedErrataSkipPorFreqCap);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (4, 0x1A8), 29, 29, BFDramSrHysEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (4, 0x1A8), 28, 26, BFDramSrHys);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (4, 0x1A8), 25, 25, BFMemTriStateEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (4, 0x1A8), 24, 24, BFDramSrEn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x84), 31, 0, BFAcpiPwrStsCtrlHi);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 2, 0, BFCkeDrvStren);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 6, 4, BFCsOdtDrvStren);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 10, 8, BFAddrCmdDrvStren);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 14, 12, BFClkDrvStren);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 18, 16, BFDataDrvStren);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 22, 20, BFDqsDrvStren);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 30, 28, BFProcOdt);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31, 0, BFODCControl);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31, 0, BFAddrTmgControl);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 0, 0, BFWrtLvTrEn);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 1, 1, BFWrtLvTrMode);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 3, 3, BFPhyFenceTrEn);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 4, 4, BFTrDimmSel);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 7, 6, BFFenceTrSel);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11, 8, BFWrLvOdt);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 13, 13, BFDqsRcvTrEn);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0B, 31, 0, BFDramPhyStatusReg);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 20, 16, BFPhyFence);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 13, 12, BFCKETri);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 11, 8, BFODTTri);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 7, 0, BFChipSelTri);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 25, 24, BFRxDLLWakeupTime);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 22, 20, BFRxCPUpdPeriod);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 19, 16, BFRxMaxDurDllNoLock);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 9, 8, BFTxDLLWakeupTime);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 6, 4, BFTxCPUpdPeriod);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0D, 3, 0, BFTxMaxDurDllNoLock);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F10, 12, 12, BFEnRxPadStandby);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F13, 7, 0, BFPhy0x0D0F0F13Bit0to7);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FE003, 14, 13, BFDisablePredriverCal);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FE006, 15, 0, BFPllLockTime);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2030, 4, 4, BFPhyClkConfig0);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2130, 4, 4, BFPhyClkConfig1);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC000, 8, 8, BFLowPowerDrvStrengthEn);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F812F, 15, 0, BFAddrCmdTri);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F0F, 14, 12, BFAlwaysEnDllClks);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F31, 14, 0, BFDataFence2);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2F31, 4, 0, BFClkFence2);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8F31, 4, 0, BFCmdFence2);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC031, 4, 0, BFAddrFence2);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F02, 15, 0, BFDataByteTxPreDriverCal);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F06, 15, 0, BFDataByteTxPreDriverCal2Pad1);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F0A, 15, 0, BFDataByteTxPreDriverCal2Pad2);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8006, 15, 0, BFCmdAddr0TxPreDriverCal2Pad1);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F800A, 15, 0, BFCmdAddr0TxPreDriverCal2Pad2);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8106, 15, 0, BFCmdAddr1TxPreDriverCal2Pad1);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F810A, 15, 0, BFCmdAddr1TxPreDriverCal2Pad2);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC006, 15, 0, BFAddrTxPreDriverCal2Pad1);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC00A, 15, 0, BFAddrTxPreDriverCal2Pad2);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC00E, 15, 0, BFAddrTxPreDriverCal2Pad3);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC012, 15, 0, BFAddrTxPreDriverCal2Pad4);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8002, 15, 0, BFCmdAddr0TxPreDriverCalPad0);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8102, 15, 0, BFCmdAddr1TxPreDriverCalPad0);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC002, 15, 0, BFAddrTxPreDriverCalPad0);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2002, 15, 0, BFClock0TxPreDriverCalPad0);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2102, 15, 0, BFClock1TxPreDriverCalPad0);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F1C00, 15, 0, BFPNOdtCal);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F1D00, 15, 0, BFPNDrvCal);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D081E00, 15, 0, BFCalVal);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F1F, 4, 3, BFDataRxVioLvl);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2F1F, 4, 3, BFClkRxVioLvl);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F4009, 15, 14, BFCmpVioLvl);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8F1F, 4, 3, BFCmdRxVioLvl);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC01F, 4, 3, BFAddrRxVioLvl);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D080F0C, 15, 0, BFPhy0x0D080F0C);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F00, 6, 4, BFDQOdt03);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F08, 6, 4, BFDQOdt47);
-
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x06, 11, 8, BFTwrrdSD);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x06, 3, 0, BFTrdrdSD);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x16, 3, 0, BFTwrwrSD);
-
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x30, 12, 0, BFDbeGskFifoNumerator);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x31, 12, 0, BFDbeGskFifoDenominator);
-
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x32, 4, 0, BFDataTxFifoSchedDlySlot0);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x32, 7, 7, BFDataTxFifoSchedDlyNegSlot0);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x32, 12, 8, BFDataTxFifoSchedDlySlot1);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x32, 15, 15, BFDataTxFifoSchedDlyNegSlot1);
-
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x40, 3, 0, BFTrcd);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x40, 11, 8, BFTrp);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x40, 20, 16, BFTras);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x40, 29, 24, BFTrc);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x41, 2, 0, BFTrtp);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x41, 10, 8, BFTrrd);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x41, 18, 16, BFTwtr);
-
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x83, 2, 0, BFRdOdtTrnOnDly);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x83, 6, 4, BFRdOdtOnDuration);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x83, 8, 8, BFWrOdtTrnOnDly);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x83, 14, 12, BFWrOdtOnDuration);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x180, 31, 0, BFRdOdtPatReg);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x182, 31, 0, BFWrOdtPatReg);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x200, 3, 0, BFTxp);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x200, 12, 8, BFTxpdll);
-
- LINK_TSEFO (NBRegTable, BFTwrrd, BFTwrrdHi);
- LINK_TSEFO (NBRegTable, BFTwrwr, BFTwrwrHi);
- LINK_TSEFO (NBRegTable, BFTrdrd, BFTrdrdHi);
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/PH/mnPh.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/PH/mnPh.c
deleted file mode 100644
index 61c9449..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/PH/mnPh.c
+++ /dev/null
@@ -1,494 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnPh.c
- *
- * Common Northbridge functions for Pharaoh Hound
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/PH)
- * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mnda.h"
-#include "mnPh.h"
-#include "mu.h"
-#include "S3.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "heapManager.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_PH_MNPH_FILECODE
-
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-#define SPLIT_CHANNEL (UINT32) 0x20000000
-#define CHANNEL_SELECT (UINT32) 0x10000000
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the northbridge block
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
- * @param[in] *FeatPtr - Pointer to the MEM_FEAT_BLOCK_NB
- * @param[in] *SharedPtr - Pointer to the MEM_SHARED_DATA
- * @param[in] NodeID - UINT8 indicating node ID of the NB object.
- *
- * @return Boolean indicating that this is the correct memory
- * controller type for the node number that was passed in.
- */
-
-BOOLEAN
-MemConstructNBBlockPh (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN MEM_FEAT_BLOCK_NB *FeatPtr,
- IN MEM_SHARED_DATA *SharedPtr,
- IN UINT8 NodeID
- )
-{
- UINT8 Dct;
- UINT8 Channel;
- UINT8 SpdSocketIndex;
- UINT8 SpdChannelIndex;
- DIE_STRUCT *MCTPtr;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
- //
- // Determine if this is the expected NB Type
- //
- GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
- if (!MemNIsIdSupportedPh (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
- return FALSE;
- }
-
- NBPtr->MemPtr = MemPtr;
- NBPtr->RefPtr = MemPtr->ParameterListPtr;
- NBPtr->SharedPtr = SharedPtr;
-
- MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
- NBPtr->MCTPtr = MCTPtr;
- NBPtr->MCTPtr->NodeId = NodeID;
- NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue;
- NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
-
- //
- // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
- //
- AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_DA * (
- sizeof (DCT_STRUCT) + (
- MAX_CHANNELS_PER_DCT_DA * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))
- )
- );
- AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0);
- AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
- if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) {
- PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader);
- SetMemError (AGESA_FATAL, MCTPtr);
- return FALSE;
- }
-
- MCTPtr->DctCount = MAX_DCTS_PER_NODE_DA;
- MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_DA * sizeof (DCT_STRUCT);
- for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
- MCTPtr->DctData[Dct].Dct = Dct;
- MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_DA;
- MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr;
- MCTPtr->DctData[Dct].ChData[0].Dct = Dct;
- AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_DA * sizeof (CH_DEF_STRUCT);
- }
- NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr;
-
- //
- // Initialize Socket List
- //
- for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
- MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr[Dct] = &(MCTPtr->DctData[Dct].ChData[0]);
- MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr[Dct] = &(MCTPtr->DctData[Dct].Timings);
- MCTPtr->DctData[Dct].ChData[0].ChannelID = Dct;
- }
-
- MemNInitNBDataPh (NBPtr);
-
- FeatPtr->InitCPG (NBPtr);
- NBPtr->FeatPtr = FeatPtr;
- FeatPtr->InitHwRxEn (NBPtr);
-
- //
- // Calculate SPD Offsets per channel and assign pointers to the data. At this point, we calculate the Node-Dct-Channel
- // centric offsets and store the pointers to the first DIMM of each channel in the Channel Definition struct for that
- // channel. This pointer is then used later to calculate the offsets to be used for each logical dimm once the
- // dimm types(QR or not) are known. This is done in the Technology block constructor.
- //
- // Calculate the SpdSocketIndex separately from the SpdChannelIndex.
- // This will facilitate modifications due to some processors that might
- // map the DCT-CHANNEL differently.
- //
- SpdSocketIndex = GetSpdSocketIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, &MemPtr->StdHeader);
- //
- // Traverse the Dct/Channel structures
- //
- for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
- for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_DA; Channel++) {
- //
- // Calculate the number of Dimms on this channel using the
- // die/dct/channel to Socket/channel conversion.
- //
- SpdChannelIndex = GetSpdChannelIndex (NBPtr->RefPtr->PlatformMemoryConfiguration,
- NBPtr->MCTPtr->SocketId,
- MemNGetSocketRelativeChannelNb (NBPtr, Dct, Channel),
- &MemPtr->StdHeader);
- NBPtr->MCTPtr->DctData[Dct].ChData[Channel].SpdPtr = &(MemPtr->SpdDataStructure[SpdSocketIndex + SpdChannelIndex]);
- }
- }
-
- MemNSwitchDCTNb (NBPtr, 0);
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initializes member functions and variables of NB block.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNInitNBDataPh (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- INT32 i;
-
- NBPtr->DctCachePtr = NBPtr->DctCache;
- NBPtr->PsPtr = NBPtr->PSBlock;
-
- InitNBRegTableDA (NBPtr, NBPtr->NBRegTable);
- NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
- NBPtr->Dct = 0;
- NBPtr->Channel = 0;
- NBPtr->DctCount = MAX_DCTS_PER_NODE_DA;
- NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_DA;
- NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA;
- NBPtr->Ganged = FALSE;
- NBPtr->PosTrnPattern = POS_PATTERN_72B;
- NBPtr->MemCleared = FALSE;
- NBPtr->StartupSpeed = DDR800_FREQUENCY;
- NBPtr->RcvrEnDlyLimit = 0xFF;
- NBPtr->DefDctSelIntLvAddr = 3;
-
- for (i = 0; i < EnumSize; i++) {
- NBPtr->IsSupported[i] = FALSE;
- }
-
- LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader);
-
- NBPtr->SetMaxLatency = MemNSetMaxLatencyNb;
- NBPtr->getMaxLatParams = MemNGetMaxLatParamsNb;
- NBPtr->GetSysAddr = MemNGetMCTSysAddrNb;
- NBPtr->InitializeMCT = MemNInitializeMctDA;
- NBPtr->FinalizeMCT = MemNFinalizeMctDA;
- NBPtr->SendMrsCmd = MemNSendMrsCmdDA;
- NBPtr->sendZQCmd = MemNSendZQCmdNb;
- NBPtr->WritePattern = MemNWritePatternDA;
- NBPtr->ReadPattern = MemNReadPatternDA;
- NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK*, UINT32)) memDefRet;
- NBPtr->CompareTestPattern = MemNCompareTestPatternNb;
- NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb;
- NBPtr->StitchMemory = MemNStitchMemoryNb;
- NBPtr->AutoConfig = memNAutoConfigDA;
- NBPtr->PlatformSpec = MemNPlatformSpecNb;
- NBPtr->InitMCT = MemNInitMCTNb;
- NBPtr->DisableDCT = MemNDisableDCTNb;
- NBPtr->StartupDCT = MemNStartupDCTNb;
- NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb;
- NBPtr->ChangeFrequency = MemNChangeFrequencyNb;
- NBPtr->RampUpFrequency = MemNRampUpFrequencyNb;
- NBPtr->ChangeNbFrequency = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefFalse;
- NBPtr->ProgramCycTimings = MemNProgramCycTimingsNb;
- NBPtr->SyncDctsReady = MemNSyncDctsReadyNb;
- NBPtr->HtMemMapInit = MemNHtMemMapInitNb;
- NBPtr->SyncAddrMapToAllNodes = MemNSyncAddrMapToAllNodesNb;
- NBPtr->CpuMemTyping = MemNCPUMemTypingNb;
- NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingNb;
- NBPtr->AfterDqsTraining = (VOID (*) (MEM_NB_BLOCK*)) memDefRet;
- NBPtr->OtherTiming = MemNOtherTimingDA;
- NBPtr->UMAMemTyping = MemNUMAMemTypingNb;
- NBPtr->TechBlockSwitch = MemNTechBlockSwitchNb;
- NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA;
- NBPtr->SetEccSymbolSize = (VOID (*) (MEM_NB_BLOCK*)) memDefRet;
- NBPtr->TrainingFlow = MemNTrainingFlowNb;
- NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb;
- MemNInitNBDataNb (NBPtr);
- NBPtr->PollBitField = MemNPollBitFieldNb;
- NBPtr->BrdcstCheck = MemNBrdcstCheckNb;
- NBPtr->BrdcstSet = MemNBrdcstSetNb;
- NBPtr->GetTrainDly = MemNGetTrainDlyNb;
- NBPtr->SetTrainDly = MemNSetTrainDlyNb;
- NBPtr->PhyFenceTraining = MemNPhyFenceTrainingNb;
- NBPtr->GetSysAddr = MemNGetMCTSysAddrNb;
- NBPtr->RankEnabled = MemNRankEnabledNb;
- NBPtr->MemPPhyFenceTrainingNb = MemNTrainPhyFenceNb;
- NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitPh;
- NBPtr->MemNBeforePlatformSpecNb = MemNBeforePlatformSpecDA;
- NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyNb;
- NBPtr->MemPNodeMemBoundaryNb = MemPNodeMemBoundaryDA;
- NBPtr->MemNInitPhyComp = MemNInitPhyCompNb;
- NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb;
- NBPtr->MemNBeforeDramInitNb = MemNBeforeDramInitDA;
- NBPtr->MemNPFenceAdjustNb = (VOID (*) (MEM_NB_BLOCK *, UINT16 *)) memDefRet;
- NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsNb;
- NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb;
- NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb;
- NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb;
- NBPtr->CSPerChannel = MemNCSPerChannelNb;
- NBPtr->CSPerDelay = MemNCSPerDelayNb;
- NBPtr->FlushPattern = MemNFlushPatternNb;
- NBPtr->GetUmaSize = MemNGetUmaSizeNb;
- NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdNb;
- NBPtr->MemNCapSpeedBatteryLife = MemNCapSpeedBatteryLifeDA;
- NBPtr->EnableSwapIntlvRgn = MemNEnableSwapIntlvRgnNb;
- NBPtr->WaitXMemClks = MemNWaitXMemClksNb;
- NBPtr->MemNGetDramTerm = MemNGetDramTermNb;
- NBPtr->MemNGetDynDramTerm = MemNGetDynDramTermNb;
- NBPtr->MemNGetMR0CL = MemNGetMR0CLNb;
- NBPtr->MemNGetMR0WR = MemNGetMR0WRNb;
- NBPtr->MemNGetMR2CWL = MemNGetMR2CWLNb;
- NBPtr->AllocateC6Storage = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
-
- NBPtr->IsSupported[SetSpareEn] = TRUE;
- NBPtr->IsSupported[CheckSpareEn] = TRUE;
- NBPtr->IsSupported[SetDllShutDown] = TRUE;
- NBPtr->IsSupported[DimmBasedOnSpeed] = TRUE;
- NBPtr->IsSupported[CheckMaxDramRate] = TRUE;
- NBPtr->IsSupported[Check1GAlign] = TRUE;
- NBPtr->IsSupported[CheckMaxRdDqsDlyPtr] = TRUE;
- NBPtr->IsSupported[CheckPhyFenceTraining] = TRUE;
- NBPtr->IsSupported[CheckGetMCTSysAddr] = TRUE;
- NBPtr->IsSupported[CheckFindPSDct] = TRUE;
- NBPtr->IsSupported[CheckDllStdBy] = TRUE;
- NBPtr->IsSupported[CheckSlewWithMarginImprv] = TRUE;
- NBPtr->IsSupported[CheckDllSpeedUp] = TRUE;
- NBPtr->IsSupported[CheckDllRegDis] = TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the default values in the MEM_DATA_STRUCT
- *
- * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
- *
- */
-VOID
-MemNInitDefaultsPh (
- IN OUT MEM_DATA_STRUCT *MemPtr
- )
-{
- UINT8 Socket;
- UINT8 Channel;
- MEM_PARAMETER_STRUCT *RefPtr;
- ASSERT (MemPtr != NULL);
- RefPtr = MemPtr->ParameterListPtr;
-
- // Memory Map/Mgt.
- // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB
- RefPtr->BottomIo = 0xE0;
- RefPtr->UmaMode = UserOptions.CfgUmaMode;
- RefPtr->UmaSize = UserOptions.CfgUmaSize;
- RefPtr->MemHoleRemapping = TRUE;
-
- // Dram Timing
- RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect;
- RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect;
- for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) {
- for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) {
- MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL;
- MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL;
- }
- }
-
- // Memory Clear
- RefPtr->EnableMemClr = TRUE;
-
- // TableBasedAlterations
- RefPtr->TableBasedAlterations = NULL;
-
- // Platform config table
- RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration;
-
- // Memory Restore
- RefPtr->MemRestoreCtl = FALSE;
- RefPtr->SaveMemContextCtl = FALSE;
- AmdS3ParamsInitializer (&RefPtr->MemContext);
-
- // Dram Configuration
- RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving;
- RefPtr->EnableNodeIntlv = UserOptions.CfgMemoryEnableNodeInterleaving;
- RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving;
- RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle;
- RefPtr->EnableParity = UserOptions.CfgMemoryParityEnable;
- RefPtr->EnableOnLineSpareCtl = UserOptions.CfgOnlineSpare;
-
- // Dram Power
- RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown;
-
- // ECC
- RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- *
- * This function writes training pattern
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Pattern[] - Pattern to write
- * @param[in] Address - System Address [47:16]
- * @param[in] ClCount - Number of cache lines
- *
- */
-
-VOID
-MemNWritePatternPh (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 Address,
- IN UINT8 Pattern[],
- IN UINT16 ClCount
- )
-{
- Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
- MemUWriteCachelines (Address, Pattern, ClCount);
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- *
- * This function reads training pattern
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Buffer[] - Buffer to fill
- * @param[in] Address - System Address [47:16]
- * @param[in] ClCount - Number of cache lines
- *
- */
-
-VOID
-MemNReadPatternPh (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Buffer[],
- IN UINT32 Address,
- IN UINT16 ClCount
- )
-{
- Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
- MemUReadCachelines (Buffer, Address, ClCount);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initiates DQS training for Server NB
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-BOOLEAN
-memNEnableTrainSequencePh (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- BOOLEAN Retval;
- Retval = TRUE;
- if (!MemNIsIdSupportedPh (NBPtr, &(NBPtr->MemPtr->DiesPerSystem[NBPtr->MCTPtr->NodeId].LogicalCpuid))) {
- Retval = FALSE;
- }
- return Retval;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/PH/mnPh.h b/src/vendorcode/amd/agesa/Proc/Mem/NB/PH/mnPh.h
deleted file mode 100644
index 7253056..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/PH/mnPh.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnPh.h
- *
- * Northbridge Ph for Pharaoh Hound
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem)
- * @e \$Revision: 36462 $ @e \$Date: 2010-08-20 00:49:49 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MNPH_H_
-#define _MNPH_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-MemNIsIdSupportedPh (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN CPU_LOGICAL_ID *LogicalIdPtr
- );
-
-BOOLEAN
-MemConstructNBBlockPh (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN MEM_FEAT_BLOCK_NB *FeatPtr,
- IN MEM_SHARED_DATA *SharedPtr,
- IN UINT8 NodeID
- );
-
-VOID
-MemNInitNBDataPh (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNPlatformSpecificFormFactorInitPh (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNInitDefaultsPh (
- IN OUT MEM_DATA_STRUCT *MemPtr
- );
-
-VOID
-MemNWritePatternPh (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 Address,
- IN UINT8 Pattern[],
- IN UINT16 ClCount
- );
-
-VOID
-MemNReadPatternPh (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Buffer[],
- IN UINT32 Address,
- IN UINT16 ClCount
- );
-
-BOOLEAN
-memNEnableTrainSequencePh (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-#endif /* _MNPH_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/PH/mnS3Ph.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/PH/mnS3Ph.c
deleted file mode 100644
index e20479b..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/PH/mnS3Ph.c
+++ /dev/null
@@ -1,776 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mns3Ph.c
- *
- * Ph memory specific function to support S3 resume
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/PH)
- * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "S3.h"
-#include "mfs3.h"
-#include "mnda.h"
-#include "mnPh.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "mnS3Ph.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G3_DXE)
-RDATA_GROUP (G3_DXE)
-
-#define FILECODE PROC_MEM_NB_PH_MNS3PH_FILECODE
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-UINT16
-STATIC
-MemNS3GetRegLstPtrPh (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT DESCRIPTOR_GROUP *DescriptPtr
- );
-
-AGESA_STATUS
-STATIC
-MemNS3GetDeviceRegLstPh (
- IN UINT32 RegisterLstID,
- OUT VOID **RegisterHeader
- );
-
-VOID
-STATIC
-MemNS3SetSpecialPCIRegPh (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR Address,
- IN VOID *Value,
- IN OUT VOID *ConfigPtr
- );
-
-VOID
-STATIC
-MemNS3ExitSelfRefRegPh (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-PCI_SPECIAL_CASE PciSpecialCaseFuncPh[] = {
- {MemNS3GetCSRNb, MemNS3SetCSRNb},
- {MemNS3GetCSRNb, MemNS3SetSpecialPCIRegPh},
- {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb}
-};
-
-PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorPh[] = {
- {{0, 0, 0}, FUNC_2, 0x110, 0xFFFFFFFF},
- {{0, 0, 0}, FUNC_1, 0x40, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x48, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x50, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x58, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x60, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x68, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x70, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x78, 0xFFFF3F03},
- {{0, 1, 0}, FUNC_1, 0x140, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x148, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x150, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x158, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x160, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x168, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x170, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x178, 0x000000FF},
- {{0, 0, 0}, FUNC_1, 0x44, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x4C, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x54, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x5C, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x64, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x6C, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x74, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x7C, 0xFFFF07FF},
- {{0, 1, 0}, FUNC_1, 0x144, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x14C, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x154, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x15C, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x164, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x16C, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x174, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x17C, 0x000000FF},
- {{0, 0, 0}, FUNC_1, 0xF0, 0xFF00FF83},
- {{0, 0, 0}, FUNC_1, 0x120, 0x00FFFFFF},
- {{0, 0, 0}, FUNC_1, 0x124, 0x07FFFFFF},
- {{0, 0, 0}, FUNC_2, 0x10C, 0x07F3FBF9},
- {{0, 0, 0}, FUNC_2, 0x114, 0xFFFFFC00},
- {{0, 0, 0}, FUNC_2, 0x118, 0xF773FFFF},
- {{0, 0, 0}, FUNC_2, 0x11C, 0xFFFFFFFF},
- {{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F}
-};
-
-CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefPh = {
- 0,
- (sizeof (S3PciPreSelfRefDescriptorPh) / sizeof (PCI_REG_DESCRIPTOR)),
- S3PciPreSelfRefDescriptorPh,
- NULL
-};
-
-CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorPh[] = {
- // DCT 0
- {{0, 0, 0}, FUNC_2, 0x40, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x44, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x48, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x4C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x50, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x54, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x58, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x5C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x60, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x64, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x68, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x6C, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x78, 0xFFCDBF0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x7C, 0xFFF7FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 2, 0}, FUNC_2, 0x80, 0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x84, 0x07FFEFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x88, 0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x8C, 0xFFFF7FFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x90, 0x00FFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0xA8, 0x0007FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), 0x30333333, DCT0_MASK, ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0x3FFFFFFF, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), 0x001FBFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), 0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhyClkConfig0, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhyClkConfig1, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhyClkConfig2, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhyClkConfig3, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- //errata 322
- {{2, 2, 1}, DCT0, BFErr322I, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFErr322II, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- //errata 263
- {{2, 2, 1}, DCT0, BFErr263, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- // Dll regulator disable
- {{2, 2, 1}, DCT0, BFPhy0x0D040F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhy0x0D042F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhy0x0D048F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhy0x0D04DF3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-
- // DCT 1
- {{0, 0, 0}, FUNC_2, 0x140, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x144, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x148, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x14C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x150, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x154, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x158, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x15C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x160, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x164, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x168, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x16C, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x178, 0xFFCDBF0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x17C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 2, 0}, FUNC_2, 0x180, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x184, 0x07FFEFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x188, 0xFFFFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x18C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x190, 0x00FFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x1A8, 0x0007FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), 0x30333333, DCT1_MASK, ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x001FBFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyClkConfig0, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyClkConfig1, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyClkConfig2, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyClkConfig3, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- // errata 322
- {{2, 2, 1}, DCT1, BFErr322I, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFErr322II, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- // errata 263
- {{2, 2, 1}, DCT1, BFErr263, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- // Dll regulator disable
- {{2, 2, 1}, DCT1, BFPhy0x0D040F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhy0x0D042F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhy0x0D048F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhy0x0D04DF3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-
- // Restore F2x[1,0]94 right before exit self refresh
- {{0, 0, 0}, FUNC_2, 0x94, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x194, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK}
-};
-
-CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefPh = {
- 0,
- (sizeof (S3CPciPreSelfDescriptorPh) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
- S3CPciPreSelfDescriptorPh,
- PciSpecialCaseFuncPh
-};
-
-CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorPh[] = {
- // DCT0
- {{2, 2, 1}, DCT0, BFEccDLLPwrDnConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFEccDLLConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10), 0x01FF01FF, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11), 0x01FF01FF, DCT0_MASK, 0x01},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12), 0x000001FF, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13), 0x01FF01FF, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14), 0x01FF01FF, DCT0_MASK, 0x04},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15), 0x000001FF, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16), 0x01FF01FF, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17), 0x01FF01FF, DCT0_MASK, 0x10},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18), 0x000001FF, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19), 0x01FF01FF, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A), 0x01FF01FF, DCT0_MASK, 0x40},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B), 0x000001FF, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20), 0x01FF01FF, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21), 0x01FF01FF, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23), 0x01FF01FF, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24), 0x01FF01FF, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26), 0x01FF01FF, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27), 0x01FF01FF, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29), 0x01FF01FF, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A), 0x01FF01FF, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01), 0x7F7F7F7F, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02), 0x7F7F7F7F, DCT0_MASK, 0x01},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03), 0x0000007F, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0x7F7F7F7F, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0x7F7F7F7F, DCT0_MASK, 0x04},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x0000007F, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0x7F7F7F7F, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0x7F7F7F7F, DCT0_MASK, 0x10},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x0000007F, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0x7F7F7F7F, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0x7F7F7F7F, DCT0_MASK, 0x40},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x0000007F, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05), 0x3F3F3F3F, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06), 0x3F3F3F3F, DCT0_MASK, 0x01},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x07), 0x0000003F, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3F3F3F3F, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3F3F3F3F, DCT0_MASK, 0x04},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x107), 0x0000003F, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3F3F3F3F, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3F3F3F3F, DCT0_MASK, 0x10},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x207), 0x0000003F, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3F3F3F3F, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3F3F3F3F, DCT0_MASK, 0x40},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x307), 0x0000003F, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0xFFFFFFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D), 0x23772377, DCT0_MASK, ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30), 0x00FF00FF, DCT0_DDR3_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31), 0x00FF00FF, DCT0_DDR3_MASK, 0x01},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32), 0x000000FF, DCT0_DDR3_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33), 0x00FF00FF, DCT0_DDR3_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34), 0x00FF00FF, DCT0_DDR3_MASK, 0x04},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35), 0x000000FF, DCT0_DDR3_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36), 0x00FF00FF, DCT0_DDR3_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37), 0x00FF00FF, DCT0_DDR3_MASK, 0x10},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38), 0x000000FF, DCT0_DDR3_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39), 0x00FF00FF, DCT0_DDR3_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B), 0x000000FF, DCT0_DDR3_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40), 0x00FF00FF, DCT0_DDR3_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41), 0x00FF00FF, DCT0_DDR3_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43), 0x00FF00FF, DCT0_DDR3_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44), 0x00FF00FF, DCT0_DDR3_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46), 0x00FF00FF, DCT0_DDR3_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47), 0x00FF00FF, DCT0_DDR3_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49), 0x00FF00FF, DCT0_DDR3_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40},
- {{2, 2, 1}, DCT0, BFPhy0x0D0F0F13, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhy0x0D0F0830, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhy0x0D07812F, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhyDLLControl, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-
- // DCT1
- {{2, 2, 1}, DCT1, BFEccDLLPwrDnConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFEccDLLConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10), 0x01FF01FF, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11), 0x01FF01FF, DCT1_MASK, 0x02},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x12), 0x000001FF, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13), 0x01FF01FF, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14), 0x01FF01FF, DCT1_MASK, 0x08},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x15), 0x000001FF, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x16), 0x01FF01FF, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x17), 0x01FF01FF, DCT1_MASK, 0x20},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x18), 0x000001FF, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x19), 0x01FF01FF, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1A), 0x01FF01FF, DCT1_MASK, 0x80},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1B), 0x000001FF, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20), 0x01FF01FF, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21), 0x01FF01FF, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23), 0x01FF01FF, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24), 0x01FF01FF, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x26), 0x01FF01FF, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x27), 0x01FF01FF, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x29), 0x01FF01FF, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x2A), 0x01FF01FF, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01), 0x7F7F7F7F, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02), 0x7F7F7F7F, DCT1_MASK, 0x02},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x03), 0x0000007F, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101), 0x7F7F7F7F, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102), 0x7F7F7F7F, DCT1_MASK, 0x08},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x103), 0x0000007F, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x201), 0x7F7F7F7F, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x202), 0x7F7F7F7F, DCT1_MASK, 0x20},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x203), 0x0000007F, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x301), 0x7F7F7F7F, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x302), 0x7F7F7F7F, DCT1_MASK, 0x80},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x303), 0x0000007F, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05), 0x3F3F3F3F, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06), 0x3F3F3F3F, DCT1_MASK, 0x02},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x07), 0x0000003F, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105), 0x3F3F3F3F, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106), 0x3F3F3F3F, DCT1_MASK, 0x08},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x107), 0x0000003F, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x205), 0x3F3F3F3F, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x206), 0x3F3F3F3F, DCT1_MASK, 0x20},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x207), 0x0000003F, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x305), 0x3F3F3F3F, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x306), 0x3F3F3F3F, DCT1_MASK, 0x80},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x307), 0x0000003F, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D), 0x23772377, DCT1_MASK, ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30), 0x00FF00FF, DCT1_DDR3_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31), 0x00FF00FF, DCT1_DDR3_MASK, 0x02},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x32), 0x000000FF, DCT1_DDR3_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33), 0x00FF00FF, DCT1_DDR3_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34), 0x00FF00FF, DCT1_DDR3_MASK, 0x08},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x35), 0x000000FF, DCT1_DDR3_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x36), 0x00FF00FF, DCT1_DDR3_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x37), 0x00FF00FF, DCT1_DDR3_MASK, 0x20},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x38), 0x000000FF, DCT1_DDR3_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x39), 0x00FF00FF, DCT1_DDR3_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3B), 0x000000FF, DCT1_DDR3_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40), 0x00FF00FF, DCT1_DDR3_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41), 0x00FF00FF, DCT1_DDR3_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43), 0x00FF00FF, DCT1_DDR3_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44), 0x00FF00FF, DCT1_DDR3_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x46), 0x00FF00FF, DCT1_DDR3_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x47), 0x00FF00FF, DCT1_DDR3_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x49), 0x00FF00FF, DCT1_DDR3_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x4A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80},
- {{2, 2, 1}, DCT1, BFPhy0x0D0F0F13, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhy0x0D0F0830, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhy0x0D07812F, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyDLLControl, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-
- // DllShutDown
- {{2, 2, 1}, DCT0, BFPhyPLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhyDLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 1, 1}, DCT0, BFDisDllShutdownSR, 0x00000001, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyPLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyDLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 1, 1}, DCT1, BFDisDllShutdownSR, 0x00000001, DCT1_MASK, ANY_DIMM_MASK},
-
- // Restore scrubber related registers after restoring training related registers
- {{0, 0, 0}, FUNC_3, 0x44, 0xFFFFFFFE, ANY_DIMM_MASK, ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_3, 0x58, 0x1F1F1F1F, ANY_DIMM_MASK, ANY_DIMM_MASK},
- {{2, 1, 1}, DCT0, BFScrubReDirEn, 0x00000001, ANY_DIMM_MASK, ANY_DIMM_MASK},
-};
-
-CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefPh = {
- 0,
- (sizeof (S3CPciPostSelfDescriptorPh) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
- S3CPciPostSelfDescriptorPh,
- PciSpecialCaseFuncPh
-};
-
-MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorPh[] = {
- {{0, 0, 0}, 0xC0010010, 0x00000000007F07FF},
- {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000},
- {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000},
- {{0, 0, 0}, 0xC001001F, 0xC047F87FFF527FFF}
-};
-
-CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefPh = {
- 0,
- (sizeof (S3MSRPreSelfRefDescriptorPh) / sizeof (MSR_REG_DESCRIPTOR)),
- S3MSRPreSelfRefDescriptorPh,
- NULL
-};
-
-VOID *MemS3RegListPh[] = {
- (VOID *)&S3PciPreSelfRefPh,
- NULL,
- (VOID *)&S3CPciPreSelfRefPh,
- (VOID *)&S3CPciPostSelfRefPh,
- (VOID *)&S3MSRPreSelfRefPh,
- NULL,
- NULL,
- NULL
-};
-
-CONST UINT16 ROMDATA SpecialCasePCIRegPh[] = {
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04)
-};
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------*/
-/**
- * MemNIsIdSupportedPh
- * This function matches the CPU_LOGICAL_ID with certain criteria to
- * determine if it is supported by this NBBlock.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID
- *
- * @return TRUE - This node is a PH.
- * @return FALSE - This node is not a PH.
- *
- */
-BOOLEAN
-MemNIsIdSupportedPh (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN CPU_LOGICAL_ID *LogicalIdPtr
- )
-{
-
- if (((LogicalIdPtr->Family & AMD_FAMILY_10_PH) != 0)
- && ((LogicalIdPtr->Revision & AMD_F10_PH_ALL) != 0)) {
- return TRUE;
- } else {
- return FALSE;
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the northbridge block for S3 resume
- *
- * @param[in,out] *S3NBPtr - Pointer to MEM_NB_BLOCK.
- * @param[in,out] *MemPtr - Pointer to MEM_DATA_STRUCT.
- * @param[in] NodeID - Node ID of the target node.
- *
- * @return BOOLEAN
- * TRUE - This is the correct constructor for the targeted node.
- * FALSE - This isn't the correct constructor for the targeted node.
- */
-BOOLEAN
-MemS3ResumeConstructNBBlockPh (
- IN OUT VOID *S3NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- )
-{
- INT32 i;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr;
-
- //
- // Determine if this is the expected NB Type
- //
- GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
- if (!MemNIsIdSupportedPh (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
- return FALSE;
- }
-
- NBPtr->MemPtr = MemPtr;
- NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
- NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
- InitNBRegTableDA (NBPtr, NBPtr->NBRegTable);
- NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
- NBPtr->Dct = 0;
- NBPtr->Channel = 0;
- NBPtr->Ganged = FALSE;
- NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA;
- NBPtr->DctCount = MAX_DCTS_PER_NODE_DA;
-
- for (i = 0; i < EnumSize; i++) {
- NBPtr->IsSupported[i] = FALSE;
- }
-
- for (i = 0; i < NumberOfHooks; i++) {
- NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) memDefTrue;
- }
-
- LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader);
-
- NBPtr->IsSupported[CheckDllSpeedUp] = TRUE;
- NBPtr->SwitchDCT = MemNSwitchDCTNb;
- NBPtr->SwitchChannel = MemNSwitchChannelNb;
- NBPtr->GetBitField = MemNGetBitFieldNb;
- NBPtr->SetBitField = MemNSetBitFieldNb;
- NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA;
- NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedPh;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = MemNS3ExitSelfRefRegPh;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskNb;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK*, DESCRIPTOR_GROUP*)) memDefRet;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeNb;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = MemNS3RestoreScrubNb;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrPh;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstPh;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = (sizeof (SpecialCasePCIRegPh) / sizeof (UINT16)) * sizeof (UINT32);
-
- MemNSwitchDCTNb (NBPtr, 0);
-
- return TRUE;
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------*/
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function returns the register list for each device for Ph
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP
- * @return UINT16 - size of the device descriptor on the target node.
- */
-UINT16
-STATIC
-MemNS3GetRegLstPtrPh (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT DESCRIPTOR_GROUP *DescriptPtr
- )
-{
- UINT8 i;
- UINT16 Size;
- Size = 0;
- for (i = PRESELFREF; i <= POSTSELFREF; i ++) {
- DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i);
- DescriptPtr->PCIDevice[i].Node = NBPtr->Node;
- DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF;
- if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListPh[PCI_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) {
- DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_DA + i;
- Size += sizeof (PCI_DEVICE_DESCRIPTOR);
- }
- DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i);
- DescriptPtr->CPCIDevice[i].Node = NBPtr->Node;
- DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF;
- if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListPh[CPCI_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) {
- DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_DA + i;
- Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR);
- }
- DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i);
- DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF;
- if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListPh[MSR_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) {
- DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_DA + i;
- Size += sizeof (MSR_DEVICE_DESCRIPTOR);
- }
- DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i);
- DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF;
- if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListPh[CMSR_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) {
- DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_DA + i;
- Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR);
- }
- }
- return Size;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function return the register list according to the register ID.
- *
- * @param[in] RegisterLstID - value of the Register list ID.
- * @param[out] **RegisterHeader - pointer to the address of the register list.
- * @return none
- */
-AGESA_STATUS
-STATIC
-MemNS3GetDeviceRegLstPh (
- IN UINT32 RegisterLstID,
- OUT VOID **RegisterHeader
- )
-{
- if (RegisterLstID >= (sizeof (MemS3RegListPh) / sizeof (VOID *))) {
- ASSERT(FALSE); // RegisterListID exceeded size of Register list
- return AGESA_FATAL;
- }
- if (MemS3RegListPh[RegisterLstID] != NULL) {
- *RegisterHeader = MemS3RegListPh[RegisterLstID];
- return AGESA_SUCCESS;
- }
- ASSERT(FALSE); // Device register list error
- return AGESA_FATAL;
-}
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function stores special case register on the heap.
- *
- * @param[in] AccessWidth - Access width of the register
- * @param[in] Address - address of the CSR register in PCI_ADDR format.
- * @param[in] *Value - Pointer to the value be read.
- * @param[in, out] *ConfigPtr - Pointer to Config handle.
- * @return none
- */
-VOID
-STATIC
-MemNS3SetSpecialPCIRegPh (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR Address,
- IN VOID *Value,
- IN OUT VOID *ConfigPtr
- )
-{
- LOCATE_HEAP_PTR LocateBufferPtr;
- UINT8 i;
- UINT8 NodeID;
- UINT8 Offset;
- S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader;
-
- Offset = 0;
- LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
- if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) {
- SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr;
- // Get the node ID of the target die.
- NodeID = (UINT8) (Address.Address.Device - 24);
- for (i = 0; i < MAX_NODES_SUPPORTED_DA; i ++) {
- if (SpecialHeapHeader[i].Node == NodeID) {
- // Get the offset in the heap for the target die.
- Offset = SpecialHeapHeader[i].Offset;
- break;
- }
- }
- ASSERT (i < MAX_NODES_SUPPORTED_DA);
- // Save the value in the heap at appropriate offset based on the index
- // of the target register in the special case array.
- if (Offset != 0) {
- for (i = 0; i < (sizeof (SpecialCasePCIRegPh) / sizeof (UINT16)); i ++) {
- if (SpecialCasePCIRegPh[i] == Address.Address.Register) {
- *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)) = *(UINT32 *) Value;
- }
- }
- }
- }
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function stores special case register on the heap.
- *
- * @param[in,out] *NBPtr - Pointer to the northbridge block.
- * @param[in,out] *StdHeader - Config handle for library and services.
- * @return none
- */
-VOID
-STATIC
-MemNS3ExitSelfRefRegPh (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- LOCATE_HEAP_PTR LocateBufferPtr;
- UINT8 i;
- PCI_ADDR PciAddr;
- UINT32 Value;
- UINT8 NodeID;
- UINT8 Offset;
- S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader;
-
- Offset = 0;
- PciAddr.Address.Device = NBPtr->PciAddr.Address.Device;
- PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus;
- PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment;
- PciAddr.Address.Function = 2;
- LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
- if (HeapLocateBuffer (&LocateBufferPtr, StdHeader) == AGESA_SUCCESS) {
- SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr;
- // Get the node ID of the target die.
- NodeID = (UINT8) (PciAddr.Address.Device - 24);
- for (i = 0; i < MAX_NODES_SUPPORTED_DA; i ++) {
- if (SpecialHeapHeader[i].Node == NodeID) {
- // Get the offset in the heap for the target die.
- Offset = SpecialHeapHeader[i].Offset;
- break;
- }
- }
- ASSERT (i < MAX_NODES_SUPPORTED_DA);
- // Restore the value one by one in the sequence of the special case register array.
- if (Offset != 0) {
- for (i = 0; i < (sizeof (SpecialCasePCIRegPh) / sizeof (UINT16)); i ++) {
- PciAddr.Address.Register = SpecialCasePCIRegPh[i];
- Value = *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2));
- MemNS3SetCSRNb (AccessS3SaveWidth32, PciAddr, &Value, StdHeader);
- }
- }
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/PH/mnS3Ph.h b/src/vendorcode/amd/agesa/Proc/Mem/NB/PH/mnS3Ph.h
deleted file mode 100644
index bed2d44..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/PH/mnS3Ph.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnS3Ph.h
- *
- * S3 resume memory related function for Ph.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/PH)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MNS3PH_H_
-#define _MNS3PH_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-/// ID for register list of PH
-typedef enum {
- PCI_LST_ESR_DA, ///< Assign 0x0000 for PCI register list for pre exit self refresh.
- PCI_LST_DA, ///< Assign 0x0001 for PCI register list for post exist self refresh.
- CPCI_LST_ESR_DA, ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh.
- CPCI_LST_DA, ///< Assign 0x0003 for conditional PCI register list for post exit self refresh.
- MSR_LST_ESR_DA, ///< Assign 0x0004 for MSR register list for pre exit self refresh.
- MSR_LST_DA, ///< Assign 0x0005 for MSR register list for post exit self refresh.
- CMSR_LST_ESR_DA, ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh.
- CMSR_LST_DA, ///< Assign 0x0007 for conditional MSR register list for post exit self refresh.
-} RegisterListIDDA;
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-#endif //_MNS3PH_H_
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/PH/mnflowPh.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/PH/mnflowPh.c
deleted file mode 100644
index beac73d..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/PH/mnflowPh.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnflowPh.c
- *
- * Pharaoh Hound initializer for MCT and DCT
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/PH)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mnda.h"
-#include "mnPh.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_PH_MNFLOWPH_FILECODE
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledPh[MAX_FF_TYPES];
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the platform specific block
- *
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - AGESA_SUCCESS at least one dorm factor was found
- * @return FALSE - AGESA_UNSUPPORTED - Error indicating that no form factors were found
- */
-
-BOOLEAN
-MemNPlatformSpecificFormFactorInitPh (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 Dct;
- UINT8 f;
- UINT8 ErrUnSuppFFCount;
- for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- if (NBPtr->ChannelPtr->ChDimmValid != 0) {
- ErrUnSuppFFCount = 0;
- for (f = 0; f < MAX_FF_TYPES; f++) {
- ASSERT (memPlatSpecFFInstalledPh[f] != NULL);
- if (memPlatSpecFFInstalledPh[f] (NBPtr->MemPtr, NBPtr->ChannelPtr, NBPtr->PsPtr) == AGESA_UNSUPPORTED) {
- ErrUnSuppFFCount++; //Count the number of AGESA_UNSUPPORTED errors
- } else {
- break;
- }
- }
- if (ErrUnSuppFFCount == MAX_FF_TYPES) {
- return FALSE; // No FF types are supported
- }
- }
- }
- return TRUE;
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/PH/mnidendimmPh.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/PH/mnidendimmPh.c
deleted file mode 100644
index 3c946e9..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/PH/mnidendimmPh.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnidendimmPh.c
- *
- * PH northbridge constructor for dimm identification translator.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/PH)
- * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "mm.h"
-#include "mn.h"
-#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB
-#include "mnda.h"
-#include "mnPh.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_NB_PH_MNIDENDIMMPH_FILECODE
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the northbridge block for dimm identification translator
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
- * @param[in,out] NodeID - ID of current node to construct
- * @return TRUE - This is the correct constructor for the targeted node.
- * @return FALSE - This isn't the correct constructor for the targeted node.
- *
- */
-
-BOOLEAN
-MemNIdentifyDimmConstructorPh (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- )
-{
- //
- // Determine if this is the expected NB Type
- //
- GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
- if (!MemNIsIdSupportedPh (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
- return FALSE;
- }
-
- NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA;
- NBPtr->DctCount = MAX_DCTS_PER_NODE_DA;
- NBPtr->MemPtr = MemPtr;
- NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
- NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
- NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
- NBPtr->Ganged = FALSE;
- InitNBRegTableDA (NBPtr, NBPtr->NBRegTable);
- NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA;
- NBPtr->SetBitField = MemNSetBitFieldNb;
- NBPtr->GetBitField = MemNGetBitFieldNb;
- NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb;
-
- return TRUE;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/RB/mnRb.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/RB/mnRb.c
deleted file mode 100644
index ba3baf0..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/RB/mnRb.c
+++ /dev/null
@@ -1,494 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnRb.c
- *
- * Common Northbridge functions for Ridgeback
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/RB)
- * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mnda.h"
-#include "mnRb.h"
-#include "mu.h"
-#include "S3.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "heapManager.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_RB_MNRB_FILECODE
-
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-#define SPLIT_CHANNEL (UINT32) 0x20000000
-#define CHANNEL_SELECT (UINT32) 0x10000000
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-extern PSO_ENTRY DefaultPlatformMemoryConfiguration[];
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the northbridge block
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
- * @param[in] *FeatPtr - Pointer to the MEM_FEAT_BLOCK_NB
- * @param[in] *SharedPtr - Pointer to the MEM_SHARED_DATA
- * @param[in] NodeID - UINT8 indicating node ID of the NB object.
- *
- * @return Boolean indicating that this is the correct memory
- * controller type for the node number that was passed in.
- */
-
-BOOLEAN
-MemConstructNBBlockRb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN MEM_FEAT_BLOCK_NB *FeatPtr,
- IN MEM_SHARED_DATA *SharedPtr,
- IN UINT8 NodeID
- )
-{
- UINT8 Dct;
- UINT8 Channel;
- UINT8 SpdSocketIndex;
- UINT8 SpdChannelIndex;
- DIE_STRUCT *MCTPtr;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
- //
- // Determine if this is the expected NB Type
- //
- GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
- if (!MemNIsIdSupportedRb (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
- return FALSE;
- }
-
- NBPtr->MemPtr = MemPtr;
- NBPtr->RefPtr = MemPtr->ParameterListPtr;
- NBPtr->SharedPtr = SharedPtr;
-
- MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
- NBPtr->MCTPtr = MCTPtr;
- NBPtr->MCTPtr->NodeId = NodeID;
- NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue;
- NBPtr->VarMtrrHiMsk = GetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
-
- //
- // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
- //
- AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_DA * (
- sizeof (DCT_STRUCT) + (
- MAX_CHANNELS_PER_DCT_DA * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))
- )
- );
- AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0);
- AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
- if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) {
- PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs, NBPtr->Node, 0, 0, 0, &MemPtr->StdHeader);
- SetMemError (AGESA_FATAL, MCTPtr);
- return FALSE;
- }
-
- MCTPtr->DctCount = MAX_DCTS_PER_NODE_DA;
- MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_DA * sizeof (DCT_STRUCT);
- for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
- MCTPtr->DctData[Dct].Dct = Dct;
- MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_DA;
- MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr;
- MCTPtr->DctData[Dct].ChData[0].Dct = Dct;
- AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_DA * sizeof (CH_DEF_STRUCT);
- }
- NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr;
-
- //
- // Initialize Socket List
- //
- for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
- MemPtr->SocketList[MCTPtr->SocketId].ChannelPtr[Dct] = &(MCTPtr->DctData[Dct].ChData[0]);
- MemPtr->SocketList[MCTPtr->SocketId].TimingsPtr[Dct] = &(MCTPtr->DctData[Dct].Timings);
- MCTPtr->DctData[Dct].ChData[0].ChannelID = Dct;
- }
-
- MemNInitNBDataRb (NBPtr);
-
- FeatPtr->InitCPG (NBPtr);
- NBPtr->FeatPtr = FeatPtr;
- FeatPtr->InitHwRxEn (NBPtr);
-
- //
- // Calculate SPD Offsets per channel and assign pointers to the data. At this point, we calculate the Node-Dct-Channel
- // centric offsets and store the pointers to the first DIMM of each channel in the Channel Definition struct for that
- // channel. This pointer is then used later to calculate the offsets to be used for each logical dimm once the
- // dimm types(QR or not) are known. This is done in the Technology block constructor.
- //
- // Calculate the SpdSocketIndex separately from the SpdChannelIndex.
- // This will facilitate modifications due to some processors that might
- // map the DCT-CHANNEL differently.
- //
- SpdSocketIndex = GetSpdSocketIndex (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, &MemPtr->StdHeader);
- //
- // Traverse the Dct/Channel structures
- //
- for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
- for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_DA; Channel++) {
- //
- // Calculate the number of Dimms on this channel using the
- // die/dct/channel to Socket/channel conversion.
- //
- SpdChannelIndex = GetSpdChannelIndex (NBPtr->RefPtr->PlatformMemoryConfiguration,
- NBPtr->MCTPtr->SocketId,
- MemNGetSocketRelativeChannelNb (NBPtr, Dct, Channel),
- &MemPtr->StdHeader);
- NBPtr->MCTPtr->DctData[Dct].ChData[Channel].SpdPtr = &(MemPtr->SpdDataStructure[SpdSocketIndex + SpdChannelIndex]);
- }
- }
-
- MemNSwitchDCTNb (NBPtr, 0);
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initializes member functions and variables of NB block.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNInitNBDataRb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- INT32 i;
-
- NBPtr->DctCachePtr = NBPtr->DctCache;
- NBPtr->PsPtr = NBPtr->PSBlock;
-
- InitNBRegTableDA (NBPtr, NBPtr->NBRegTable);
- NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
- NBPtr->Dct = 0;
- NBPtr->Channel = 0;
- NBPtr->DctCount = MAX_DCTS_PER_NODE_DA;
- NBPtr->ChannelCount = MAX_CHANNELS_PER_DCT_DA;
- NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA;
- NBPtr->Ganged = FALSE;
- NBPtr->PosTrnPattern = POS_PATTERN_72B;
- NBPtr->MemCleared = FALSE;
- NBPtr->StartupSpeed = DDR800_FREQUENCY;
- NBPtr->RcvrEnDlyLimit = 0xFF;
- NBPtr->DefDctSelIntLvAddr = 3;
-
- for (i = 0; i < EnumSize; i++) {
- NBPtr->IsSupported[i] = FALSE;
- }
-
- LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader);
-
- NBPtr->SetMaxLatency = MemNSetMaxLatencyNb;
- NBPtr->getMaxLatParams = MemNGetMaxLatParamsNb;
- NBPtr->GetSysAddr = MemNGetMCTSysAddrNb;
- NBPtr->InitializeMCT = MemNInitializeMctDA;
- NBPtr->FinalizeMCT = MemNFinalizeMctDA;
- NBPtr->SendMrsCmd = MemNSendMrsCmdDA;
- NBPtr->sendZQCmd = MemNSendZQCmdNb;
- NBPtr->WritePattern = MemNWritePatternDA;
- NBPtr->ReadPattern = MemNReadPatternDA;
- NBPtr->GenHwRcvEnReads = (VOID (*) (MEM_NB_BLOCK*, UINT32)) memDefRet;
- NBPtr->CompareTestPattern = MemNCompareTestPatternNb;
- NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternNb;
- NBPtr->StitchMemory = MemNStitchMemoryNb;
- NBPtr->AutoConfig = memNAutoConfigDA;
- NBPtr->PlatformSpec = MemNPlatformSpecNb;
- NBPtr->InitMCT = MemNInitMCTNb;
- NBPtr->DisableDCT = MemNDisableDCTNb;
- NBPtr->StartupDCT = MemNStartupDCTNb;
- NBPtr->SyncTargetSpeed = MemNSyncTargetSpeedNb;
- NBPtr->ChangeFrequency = MemNChangeFrequencyNb;
- NBPtr->RampUpFrequency = MemNRampUpFrequencyNb;
- NBPtr->ChangeNbFrequency = (BOOLEAN (*) (MEM_NB_BLOCK *)) memDefFalse;
- NBPtr->ProgramCycTimings = MemNProgramCycTimingsNb;
- NBPtr->SyncDctsReady = MemNSyncDctsReadyNb;
- NBPtr->HtMemMapInit = MemNHtMemMapInitNb;
- NBPtr->SyncAddrMapToAllNodes = MemNSyncAddrMapToAllNodesNb;
- NBPtr->CpuMemTyping = MemNCPUMemTypingNb;
- NBPtr->BeforeDqsTraining = MemNBeforeDQSTrainingNb;
- NBPtr->AfterDqsTraining = (VOID (*) (MEM_NB_BLOCK*)) memDefRet;
- NBPtr->OtherTiming = MemNOtherTimingDA;
- NBPtr->UMAMemTyping = MemNUMAMemTypingNb;
- NBPtr->TechBlockSwitch = MemNTechBlockSwitchNb;
- NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA;
- NBPtr->SetEccSymbolSize = (VOID (*) (MEM_NB_BLOCK*)) memDefRet;
- NBPtr->TrainingFlow = MemNTrainingFlowNb;
- NBPtr->MinDataEyeWidth = MemNMinDataEyeWidthNb;
- MemNInitNBDataNb (NBPtr);
- NBPtr->PollBitField = MemNPollBitFieldNb;
- NBPtr->BrdcstCheck = MemNBrdcstCheckNb;
- NBPtr->BrdcstSet = MemNBrdcstSetNb;
- NBPtr->GetTrainDly = MemNGetTrainDlyNb;
- NBPtr->SetTrainDly = MemNSetTrainDlyNb;
- NBPtr->PhyFenceTraining = MemNPhyFenceTrainingNb;
- NBPtr->GetSysAddr = MemNGetMCTSysAddrNb;
- NBPtr->RankEnabled = MemNRankEnabledNb;
- NBPtr->MemPPhyFenceTrainingNb = MemNTrainPhyFenceNb;
- NBPtr->MemNPlatformSpecificFormFactorInitNb = MemNPlatformSpecificFormFactorInitRb;
- NBPtr->MemNBeforePlatformSpecNb = MemNBeforePlatformSpecDA;
- NBPtr->MemNcmnGetSetTrainDly = MemNcmnGetSetTrainDlyNb;
- NBPtr->MemPNodeMemBoundaryNb = MemPNodeMemBoundaryDA;
- NBPtr->MemNInitPhyComp = MemNInitPhyCompNb;
- NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb;
- NBPtr->MemNBeforeDramInitNb = MemNBeforeDramInitDA;
- NBPtr->MemNPFenceAdjustNb = (VOID (*) (MEM_NB_BLOCK *, UINT16 *)) memDefRet;
- NBPtr->GetTrainDlyParms = MemNGetTrainDlyParmsNb;
- NBPtr->TrainingPatternInit = MemNTrainingPatternInitNb;
- NBPtr->TrainingPatternFinalize = MemNTrainingPatternFinalizeNb;
- NBPtr->GetApproximateWriteDatDelay = MemNGetApproximateWriteDatDelayNb;
- NBPtr->CSPerChannel = MemNCSPerChannelNb;
- NBPtr->CSPerDelay = MemNCSPerDelayNb;
- NBPtr->FlushPattern = MemNFlushPatternNb;
- NBPtr->GetUmaSize = MemNGetUmaSizeNb;
- NBPtr->GetMemClkFreqId = MemNGetMemClkFreqIdNb;
- NBPtr->MemNCapSpeedBatteryLife = MemNCapSpeedBatteryLifeDA;
- NBPtr->EnableSwapIntlvRgn = MemNEnableSwapIntlvRgnNb;
- NBPtr->WaitXMemClks = MemNWaitXMemClksNb;
- NBPtr->MemNGetDramTerm = MemNGetDramTermNb;
- NBPtr->MemNGetDynDramTerm = MemNGetDynDramTermNb;
- NBPtr->MemNGetMR0CL = MemNGetMR0CLNb;
- NBPtr->MemNGetMR0WR = MemNGetMR0WRNb;
- NBPtr->MemNGetMR2CWL = MemNGetMR2CWLNb;
- NBPtr->AllocateC6Storage = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
-
- NBPtr->IsSupported[SetSpareEn] = TRUE;
- NBPtr->IsSupported[CheckSpareEn] = TRUE;
- NBPtr->IsSupported[SetDllShutDown] = TRUE;
- NBPtr->IsSupported[DimmBasedOnSpeed] = TRUE;
- NBPtr->IsSupported[CheckMaxDramRate] = TRUE;
- NBPtr->IsSupported[Check1GAlign] = TRUE;
- NBPtr->IsSupported[CheckMaxRdDqsDlyPtr] = TRUE;
- NBPtr->IsSupported[CheckPhyFenceTraining] = TRUE;
- NBPtr->IsSupported[CheckGetMCTSysAddr] = TRUE;
- NBPtr->IsSupported[CheckFindPSDct] = TRUE;
- NBPtr->IsSupported[CheckDllStdBy] = TRUE;
- NBPtr->IsSupported[CheckSlewWithMarginImprv] = TRUE;
- NBPtr->IsSupported[CheckDllSpeedUp] = TRUE;
- NBPtr->IsSupported[CheckDllRegDis] = TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the default values in the MEM_DATA_STRUCT
- *
- * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
- *
- */
-VOID
-MemNInitDefaultsRb (
- IN OUT MEM_DATA_STRUCT *MemPtr
- )
-{
- UINT8 Socket;
- UINT8 Channel;
- MEM_PARAMETER_STRUCT *RefPtr;
- ASSERT (MemPtr != NULL);
- RefPtr = MemPtr->ParameterListPtr;
-
- // Memory Map/Mgt.
- // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB
- RefPtr->BottomIo = 0xE0;
- RefPtr->UmaMode = UserOptions.CfgUmaMode;
- RefPtr->UmaSize = UserOptions.CfgUmaSize;
- RefPtr->MemHoleRemapping = TRUE;
-
- // Dram Timing
- RefPtr->UserTimingMode = UserOptions.CfgTimingModeSelect;
- RefPtr->MemClockValue = UserOptions.CfgMemoryClockSelect;
- for (Socket = 0; Socket < MAX_SOCKETS_SUPPORTED; Socket++) {
- for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) {
- MemPtr->SocketList[Socket].ChannelPtr[Channel] = NULL;
- MemPtr->SocketList[Socket].TimingsPtr[Channel] = NULL;
- }
- }
-
- // Memory Clear
- RefPtr->EnableMemClr = TRUE;
-
- // TableBasedAlterations
- RefPtr->TableBasedAlterations = NULL;
-
- // Platform config table
- RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration;
-
- // Memory Restore
- RefPtr->MemRestoreCtl = FALSE;
- RefPtr->SaveMemContextCtl = FALSE;
- AmdS3ParamsInitializer (&RefPtr->MemContext);
-
- // Dram Configuration
- RefPtr->EnableBankIntlv = UserOptions.CfgMemoryEnableBankInterleaving;
- RefPtr->EnableNodeIntlv = UserOptions.CfgMemoryEnableNodeInterleaving;
- RefPtr->EnableChannelIntlv = UserOptions.CfgMemoryChannelInterleaving;
- RefPtr->EnableBankSwizzle = UserOptions.CfgBankSwizzle;
- RefPtr->EnableParity = UserOptions.CfgMemoryParityEnable;
- RefPtr->EnableOnLineSpareCtl = UserOptions.CfgOnlineSpare;
-
- // Dram Power
- RefPtr->EnablePowerDown = UserOptions.CfgMemoryPowerDown;
-
- // ECC
- RefPtr->EnableEccFeature = UserOptions.CfgEnableEccFeature;
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- *
- * This function writes training pattern
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Pattern[] - Pattern to write
- * @param[in] Address - System Address [47:16]
- * @param[in] ClCount - Number of cache lines
- *
- */
-
-VOID
-MemNWritePatternRb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 Address,
- IN UINT8 Pattern[],
- IN UINT16 ClCount
- )
-{
- Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
- MemUWriteCachelines (Address, Pattern, ClCount);
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- *
- * This function reads training pattern
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Buffer[] - Buffer to fill
- * @param[in] Address - System Address [47:16]
- * @param[in] ClCount - Number of cache lines
- *
- */
-
-VOID
-MemNReadPatternRb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Buffer[],
- IN UINT32 Address,
- IN UINT16 ClCount
- )
-{
- Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
- MemUReadCachelines (Buffer, Address, ClCount);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initiates DQS training for Server NB
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-BOOLEAN
-memNEnableTrainSequenceRb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- BOOLEAN Retval;
- Retval = TRUE;
- if (!MemNIsIdSupportedRb (NBPtr, &(NBPtr->MemPtr->DiesPerSystem[NBPtr->MCTPtr->NodeId].LogicalCpuid))) {
- Retval = FALSE;
- }
- return Retval;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/RB/mnRb.h b/src/vendorcode/amd/agesa/Proc/Mem/NB/RB/mnRb.h
deleted file mode 100644
index bd576d1..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/RB/mnRb.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnRb.h
- *
- * Northbridge RB for RidgeBack
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/RB)
- * @e \$Revision: 36462 $ @e \$Date: 2010-08-20 00:49:49 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MNRB_H_
-#define _MNRB_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-MemNIsIdSupportedRb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN CPU_LOGICAL_ID *LogicalIdPtr
- );
-
-BOOLEAN
-MemConstructNBBlockRb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN MEM_FEAT_BLOCK_NB *FeatPtr,
- IN MEM_SHARED_DATA *SharedPtr,
- IN UINT8 NodeID
- );
-
-VOID
-MemNInitNBDataRb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNPlatformSpecificFormFactorInitRb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNInitDefaultsRb (
- IN OUT MEM_DATA_STRUCT *MemPtr
- );
-
-VOID
-MemNWritePatternRb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 Address,
- IN UINT8 Pattern[],
- IN UINT16 ClCount
- );
-
-VOID
-MemNReadPatternRb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Buffer[],
- IN UINT32 Address,
- IN UINT16 ClCount
- );
-
-BOOLEAN
-memNEnableTrainSequenceRb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-#endif /* _MNRB_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/RB/mnS3Rb.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/RB/mnS3Rb.c
deleted file mode 100644
index 755a4e3..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/RB/mnS3Rb.c
+++ /dev/null
@@ -1,776 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mns3Rb.c
- *
- * RB memory specific function to support S3 resume
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/Rb)
- * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "S3.h"
-#include "mfs3.h"
-#include "mnda.h"
-#include "mnRb.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "mnS3Rb.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G3_DXE)
-RDATA_GROUP (G3_DXE)
-
-#define FILECODE PROC_MEM_NB_RB_MNS3RB_FILECODE
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-UINT16
-STATIC
-MemNS3GetRegLstPtrRb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT DESCRIPTOR_GROUP *DescriptPtr
- );
-
-AGESA_STATUS
-STATIC
-MemNS3GetDeviceRegLstRb (
- IN UINT32 RegisterLstID,
- OUT VOID **RegisterHeader
- );
-
-VOID
-STATIC
-MemNS3SetSpecialPCIRegRb (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR Address,
- IN VOID *Value,
- IN OUT VOID *ConfigPtr
- );
-
-VOID
-STATIC
-MemNS3ExitSelfRefRegRb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-PCI_SPECIAL_CASE PciSpecialCaseFuncRb[] = {
- {MemNS3GetCSRNb, MemNS3SetCSRNb},
- {MemNS3GetCSRNb, MemNS3SetSpecialPCIRegRb},
- {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb}
-};
-
-PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorRb[] = {
- {{0, 0, 0}, FUNC_2, 0x110, 0xFFFFFFFF},
- {{0, 0, 0}, FUNC_1, 0x40, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x48, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x50, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x58, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x60, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x68, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x70, 0xFFFF3F03},
- {{0, 0, 0}, FUNC_1, 0x78, 0xFFFF3F03},
- {{0, 1, 0}, FUNC_1, 0x140, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x148, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x150, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x158, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x160, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x168, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x170, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x178, 0x000000FF},
- {{0, 0, 0}, FUNC_1, 0x44, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x4C, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x54, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x5C, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x64, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x6C, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x74, 0xFFFF07FF},
- {{0, 0, 0}, FUNC_1, 0x7C, 0xFFFF07FF},
- {{0, 1, 0}, FUNC_1, 0x144, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x14C, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x154, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x15C, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x164, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x16C, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x174, 0x000000FF},
- {{0, 1, 0}, FUNC_1, 0x17C, 0x000000FF},
- {{0, 0, 0}, FUNC_1, 0xF0, 0xFF00FF83},
- {{0, 0, 0}, FUNC_1, 0x120, 0x00FFFFFF},
- {{0, 0, 0}, FUNC_1, 0x124, 0x07FFFFFF},
- {{0, 0, 0}, FUNC_2, 0x10C, 0x07F3FBF9},
- {{0, 0, 0}, FUNC_2, 0x114, 0xFFFFFC00},
- {{0, 0, 0}, FUNC_2, 0x118, 0xF773FFFF},
- {{0, 0, 0}, FUNC_2, 0x11C, 0xFFFFFFFF},
- {{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F}
-};
-
-CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefRb = {
- 0,
- (sizeof (S3PciPreSelfRefDescriptorRb) / sizeof (PCI_REG_DESCRIPTOR)),
- S3PciPreSelfRefDescriptorRb,
- NULL
-};
-
-CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorRb[] = {
- // DCT 0
- {{0, 0, 0}, FUNC_2, 0x40, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x44, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x48, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x4C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x50, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x54, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x58, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x5C, 0x1FF83FEF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x60, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x64, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x68, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x6C, 0x1FF83FE0, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x78, 0xFFCDBF0F, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x7C, 0xFFF7FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 2, 0}, FUNC_2, 0x80, 0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x84, 0x07FFEFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x88, 0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x8C, 0xFFFF7FFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x90, 0x00FFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0xA8, 0x0007FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), 0x30333333, DCT0_MASK, ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0x3FFFFFFF, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), 0x001FBFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), 0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhyClkConfig0, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhyClkConfig1, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhyClkConfig2, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhyClkConfig3, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- //errata 322
- {{2, 2, 1}, DCT0, BFErr322I, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFErr322II, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- //errata 263
- {{2, 2, 1}, DCT0, BFErr263, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- // Dll regulator disable
- {{2, 2, 1}, DCT0, BFPhy0x0D040F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhy0x0D042F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhy0x0D048F3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhy0x0D04DF3E, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-
- // DCT 1
- {{0, 0, 0}, FUNC_2, 0x140, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x144, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x148, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x14C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x150, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x154, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x158, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x15C, 0x1FF83FEF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x160, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x164, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x168, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x16C, 0x1FF83FE0, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x178, 0xFFCDBF0F, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x17C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 2, 0}, FUNC_2, 0x180, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x184, 0x07FFEFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x188, 0xFFFFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x18C, 0xFFF7FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x190, 0x00FFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x1A8, 0x0007FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), 0x30333333, DCT1_MASK, ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x001FBFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{1, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyClkConfig0, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyClkConfig1, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyClkConfig2, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyClkConfig3, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- // errata 322
- {{2, 2, 1}, DCT1, BFErr322I, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFErr322II, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- // errata 263
- {{2, 2, 1}, DCT1, BFErr263, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- // Dll regulator disable
- {{2, 2, 1}, DCT1, BFPhy0x0D040F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhy0x0D042F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhy0x0D048F3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhy0x0D04DF3E, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-
- // Restore F2x[1,0]94 right before exit self refresh
- {{0, 0, 0}, FUNC_2, 0x94, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_2, 0x194, 0xFFFFFF07, ANY_DIMM_MASK, ANY_DIMM_MASK}
-};
-
-CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefRb = {
- 0,
- (sizeof (S3CPciPreSelfDescriptorRb) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
- S3CPciPreSelfDescriptorRb,
- PciSpecialCaseFuncRb
-};
-
-CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorRb[] = {
- // DCT0
- {{2, 2, 1}, DCT0, BFEccDLLPwrDnConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFEccDLLConf, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10), 0x01FF01FF, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11), 0x01FF01FF, DCT0_MASK, 0x01},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12), 0x000001FF, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13), 0x01FF01FF, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14), 0x01FF01FF, DCT0_MASK, 0x04},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15), 0x000001FF, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16), 0x01FF01FF, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17), 0x01FF01FF, DCT0_MASK, 0x10},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18), 0x000001FF, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19), 0x01FF01FF, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A), 0x01FF01FF, DCT0_MASK, 0x40},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B), 0x000001FF, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20), 0x01FF01FF, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21), 0x01FF01FF, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23), 0x01FF01FF, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24), 0x01FF01FF, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26), 0x01FF01FF, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27), 0x01FF01FF, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29), 0x01FF01FF, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A), 0x01FF01FF, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01), 0x7F7F7F7F, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02), 0x7F7F7F7F, DCT0_MASK, 0x01},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03), 0x0000007F, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0x7F7F7F7F, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0x7F7F7F7F, DCT0_MASK, 0x04},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x0000007F, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0x7F7F7F7F, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0x7F7F7F7F, DCT0_MASK, 0x10},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x0000007F, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0x7F7F7F7F, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0x7F7F7F7F, DCT0_MASK, 0x40},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x0000007F, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05), 0x3F3F3F3F, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06), 0x3F3F3F3F, DCT0_MASK, 0x01},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x07), 0x0000003F, DCT0_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3F3F3F3F, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3F3F3F3F, DCT0_MASK, 0x04},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x107), 0x0000003F, DCT0_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3F3F3F3F, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3F3F3F3F, DCT0_MASK, 0x10},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x207), 0x0000003F, DCT0_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3F3F3F3F, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3F3F3F3F, DCT0_MASK, 0x40},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x307), 0x0000003F, DCT0_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A), 0xFFFFFFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D), 0x23772377, DCT0_MASK, ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30), 0x00FF00FF, DCT0_DDR3_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31), 0x00FF00FF, DCT0_DDR3_MASK, 0x01},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32), 0x000000FF, DCT0_DDR3_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33), 0x00FF00FF, DCT0_DDR3_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34), 0x00FF00FF, DCT0_DDR3_MASK, 0x04},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35), 0x000000FF, DCT0_DDR3_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36), 0x00FF00FF, DCT0_DDR3_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37), 0x00FF00FF, DCT0_DDR3_MASK, 0x10},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38), 0x000000FF, DCT0_DDR3_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39), 0x00FF00FF, DCT0_DDR3_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B), 0x000000FF, DCT0_DDR3_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40), 0x00FF00FF, DCT0_DDR3_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41), 0x00FF00FF, DCT0_DDR3_MASK, 0x01},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43), 0x00FF00FF, DCT0_DDR3_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44), 0x00FF00FF, DCT0_DDR3_MASK, 0x04},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46), 0x00FF00FF, DCT0_DDR3_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47), 0x00FF00FF, DCT0_DDR3_MASK, 0x10},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49), 0x00FF00FF, DCT0_DDR3_MASK, 0x40},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A), 0x00FF00FF, DCT0_DDR3_MASK, 0x40},
- {{2, 2, 1}, DCT0, BFPhy0x0D0F0F13, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhy0x0D0F0830, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhy0x0D07812F, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhyDLLControl, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
-
- // DCT1
- {{2, 2, 1}, DCT1, BFEccDLLPwrDnConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFEccDLLConf, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10), 0x01FF01FF, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11), 0x01FF01FF, DCT1_MASK, 0x02},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x12), 0x000001FF, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13), 0x01FF01FF, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14), 0x01FF01FF, DCT1_MASK, 0x08},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x15), 0x000001FF, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x16), 0x01FF01FF, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x17), 0x01FF01FF, DCT1_MASK, 0x20},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x18), 0x000001FF, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x19), 0x01FF01FF, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1A), 0x01FF01FF, DCT1_MASK, 0x80},
- {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1B), 0x000001FF, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20), 0x01FF01FF, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21), 0x01FF01FF, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23), 0x01FF01FF, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24), 0x01FF01FF, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x26), 0x01FF01FF, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x27), 0x01FF01FF, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x29), 0x01FF01FF, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x2A), 0x01FF01FF, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01), 0x7F7F7F7F, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02), 0x7F7F7F7F, DCT1_MASK, 0x02},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x03), 0x0000007F, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101), 0x7F7F7F7F, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102), 0x7F7F7F7F, DCT1_MASK, 0x08},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x103), 0x0000007F, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x201), 0x7F7F7F7F, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x202), 0x7F7F7F7F, DCT1_MASK, 0x20},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x203), 0x0000007F, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x301), 0x7F7F7F7F, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x302), 0x7F7F7F7F, DCT1_MASK, 0x80},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x303), 0x0000007F, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05), 0x3F3F3F3F, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06), 0x3F3F3F3F, DCT1_MASK, 0x02},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x07), 0x0000003F, DCT1_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105), 0x3F3F3F3F, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106), 0x3F3F3F3F, DCT1_MASK, 0x08},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x107), 0x0000003F, DCT1_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x205), 0x3F3F3F3F, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x206), 0x3F3F3F3F, DCT1_MASK, 0x20},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x207), 0x0000003F, DCT1_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x305), 0x3F3F3F3F, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x306), 0x3F3F3F3F, DCT1_MASK, 0x80},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x307), 0x0000003F, DCT1_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D), 0x23772377, DCT1_MASK, ANY_DIMM_MASK},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30), 0x00FF00FF, DCT1_DDR3_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31), 0x00FF00FF, DCT1_DDR3_MASK, 0x02},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x32), 0x000000FF, DCT1_DDR3_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33), 0x00FF00FF, DCT1_DDR3_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34), 0x00FF00FF, DCT1_DDR3_MASK, 0x08},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x35), 0x000000FF, DCT1_DDR3_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x36), 0x00FF00FF, DCT1_DDR3_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x37), 0x00FF00FF, DCT1_DDR3_MASK, 0x20},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x38), 0x000000FF, DCT1_DDR3_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x39), 0x00FF00FF, DCT1_DDR3_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80},
- {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3B), 0x000000FF, DCT1_DDR3_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40), 0x00FF00FF, DCT1_DDR3_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41), 0x00FF00FF, DCT1_DDR3_MASK, 0x02},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43), 0x00FF00FF, DCT1_DDR3_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44), 0x00FF00FF, DCT1_DDR3_MASK, 0x08},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x46), 0x00FF00FF, DCT1_DDR3_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x47), 0x00FF00FF, DCT1_DDR3_MASK, 0x20},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x49), 0x00FF00FF, DCT1_DDR3_MASK, 0x80},
- {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x4A), 0x00FF00FF, DCT1_DDR3_MASK, 0x80},
- {{2, 2, 1}, DCT1, BFPhy0x0D0F0F13, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhy0x0D0F0830, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhy0x0D07812F, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyDLLControl, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
-
- // DllShutDown
- {{2, 2, 1}, DCT0, BFPhyPLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT0, BFPhyDLLLockTime, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 1, 1}, DCT0, BFDisDllShutdownSR, 0x00000001, DCT0_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyPLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 2, 1}, DCT1, BFPhyDLLLockTime, 0x0000FFFF, DCT1_MASK, ANY_DIMM_MASK},
- {{2, 1, 1}, DCT1, BFDisDllShutdownSR, 0x00000001, DCT1_MASK, ANY_DIMM_MASK},
-
- // Restore scrubber related registers after restoring training related registers
- {{0, 0, 0}, FUNC_3, 0x44, 0xFFFFFFFE, ANY_DIMM_MASK, ANY_DIMM_MASK},
- {{0, 0, 0}, FUNC_3, 0x58, 0x1F1F1F1F, ANY_DIMM_MASK, ANY_DIMM_MASK},
- {{2, 1, 1}, DCT0, BFScrubReDirEn, 0x00000001, ANY_DIMM_MASK, ANY_DIMM_MASK},
-};
-
-CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefRb = {
- 0,
- (sizeof (S3CPciPostSelfDescriptorRb) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
- S3CPciPostSelfDescriptorRb,
- PciSpecialCaseFuncRb
-};
-
-MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorRb[] = {
- {{0, 0, 0}, 0xC0010010, 0x00000000007F07FF},
- {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000},
- {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000},
- {{0, 0, 0}, 0xC001001F, 0xC047F87FFF527FFF}
-};
-
-CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefRb = {
- 0,
- (sizeof (S3MSRPreSelfRefDescriptorRb) / sizeof (MSR_REG_DESCRIPTOR)),
- S3MSRPreSelfRefDescriptorRb,
- NULL
-};
-
-VOID *MemS3RegListRb[] = {
- (VOID *)&S3PciPreSelfRefRb,
- NULL,
- (VOID *)&S3CPciPreSelfRefRb,
- (VOID *)&S3CPciPostSelfRefRb,
- (VOID *)&S3MSRPreSelfRefRb,
- NULL,
- NULL,
- NULL
-};
-
-CONST UINT16 ROMDATA SpecialCasePCIRegRb[] = {
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0A),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C),
- SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04)
-};
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------*/
-/**
- * MemNIsIdSupportedRb
- * This function matches the CPU_LOGICAL_ID with certain criteria to
- * determine if it is supported by this NBBlock.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID
- *
- * @return TRUE - This node is a RB.
- * @return FALSE - This node is not a RB.
- *
- */
-BOOLEAN
-MemNIsIdSupportedRb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN CPU_LOGICAL_ID *LogicalIdPtr
- )
-{
-
- if (((LogicalIdPtr->Family & AMD_FAMILY_10_RB) != 0)
- && ((LogicalIdPtr->Revision & AMD_F10_RB_ALL) != 0)) {
- return TRUE;
- } else {
- return FALSE;
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the northbridge block for S3 resume
- *
- * @param[in,out] *S3NBPtr - Pointer to MEM_NB_BLOCK.
- * @param[in,out] *MemPtr - Pointer to MEM_DATA_STRUCT.
- * @param[in] NodeID - Node ID of the target node.
- *
- * @return BOOLEAN
- * TRUE - This is the correct constructor for the targeted node.
- * FALSE - This isn't the correct constructor for the targeted node.
- */
-BOOLEAN
-MemS3ResumeConstructNBBlockRb (
- IN OUT VOID *S3NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- )
-{
- INT32 i;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr;
-
- //
- // Determine if this is the expected NB Type
- //
- GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
- if (!MemNIsIdSupportedRb (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
- return FALSE;
- }
-
- NBPtr->MemPtr = MemPtr;
- NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
- NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
- InitNBRegTableDA (NBPtr, NBPtr->NBRegTable);
- NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
- NBPtr->Dct = 0;
- NBPtr->Channel = 0;
- NBPtr->Ganged = FALSE;
- NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA;
- NBPtr->DctCount = MAX_DCTS_PER_NODE_DA;
-
- for (i = 0; i < EnumSize; i++) {
- NBPtr->IsSupported[i] = FALSE;
- }
-
- for (i = 0; i < NumberOfHooks; i++) {
- NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) memDefTrue;
- }
-
- LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader);
-
- NBPtr->IsSupported[CheckDllSpeedUp] = TRUE;
- NBPtr->SwitchDCT = MemNSwitchDCTNb;
- NBPtr->SwitchChannel = MemNSwitchChannelNb;
- NBPtr->GetBitField = MemNGetBitFieldNb;
- NBPtr->SetBitField = MemNSetBitFieldNb;
- NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA;
- NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedRb;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = MemNS3ExitSelfRefRegRb;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskNb;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK*, DESCRIPTOR_GROUP*)) memDefRet;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeNb;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = MemNS3RestoreScrubNb;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrRb;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstRb;
- ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = (sizeof (SpecialCasePCIRegRb) / sizeof (UINT16)) * sizeof (UINT32);
-
- MemNSwitchDCTNb (NBPtr, 0);
-
- return TRUE;
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------*/
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function returns the register list for each device for RB
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP
- * @return UINT16 - size of the device descriptor on the target node.
- */
-UINT16
-STATIC
-MemNS3GetRegLstPtrRb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT DESCRIPTOR_GROUP *DescriptPtr
- )
-{
- UINT8 i;
- UINT16 Size;
- Size = 0;
- for (i = PRESELFREF; i <= POSTSELFREF; i ++) {
- DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i);
- DescriptPtr->PCIDevice[i].Node = NBPtr->Node;
- DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF;
- if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListRb[PCI_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) {
- DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_DA + i;
- Size += sizeof (PCI_DEVICE_DESCRIPTOR);
- }
- DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i);
- DescriptPtr->CPCIDevice[i].Node = NBPtr->Node;
- DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF;
- if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListRb[CPCI_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) {
- DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_DA + i;
- Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR);
- }
- DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i);
- DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF;
- if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListRb[MSR_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) {
- DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_DA + i;
- Size += sizeof (MSR_DEVICE_DESCRIPTOR);
- }
- DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i);
- DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF;
- if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListRb[CMSR_LST_ESR_DA - PCI_LST_ESR_DA + i] != NULL) {
- DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_DA + i;
- Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR);
- }
- }
- return Size;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function return the register list according to the register ID.
- *
- * @param[in] RegisterLstID - value of the Register list ID.
- * @param[out] **RegisterHeader - pointer to the address of the register list.
- * @return none
- */
-AGESA_STATUS
-STATIC
-MemNS3GetDeviceRegLstRb (
- IN UINT32 RegisterLstID,
- OUT VOID **RegisterHeader
- )
-{
- if (RegisterLstID >= (sizeof (MemS3RegListRb) / sizeof (VOID *))) {
- ASSERT(FALSE); // RegisterListID exceeded size of Register list
- return AGESA_FATAL;
- }
- if (MemS3RegListRb[RegisterLstID] != NULL) {
- *RegisterHeader = MemS3RegListRb[RegisterLstID];
- return AGESA_SUCCESS;
- }
- ASSERT(FALSE); // Device register list error
- return AGESA_FATAL;
-}
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function stores special case register on the heap.
- *
- * @param[in] AccessWidth - Access width of the register
- * @param[in] Address - address of the CSR register in PCI_ADDR format.
- * @param[in] *Value - Pointer to the value be read.
- * @param[in, out] *ConfigPtr - Pointer to Config handle.
- * @return none
- */
-VOID
-STATIC
-MemNS3SetSpecialPCIRegRb (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR Address,
- IN VOID *Value,
- IN OUT VOID *ConfigPtr
- )
-{
- LOCATE_HEAP_PTR LocateBufferPtr;
- UINT8 i;
- UINT8 NodeID;
- UINT8 Offset;
- S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader;
-
- Offset = 0;
- LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
- if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) {
- SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr;
- // Get the node ID of the target die.
- NodeID = (UINT8) (Address.Address.Device - 24);
- for (i = 0; i < MAX_NODES_SUPPORTED_DA; i ++) {
- if (SpecialHeapHeader[i].Node == NodeID) {
- // Get the offset in the heap for the target die.
- Offset = SpecialHeapHeader[i].Offset;
- break;
- }
- }
- ASSERT (i < MAX_NODES_SUPPORTED_DA);
- // Save the value in the heap at appropriate offset based on the index
- // of the target register in the special case array.
- if (Offset != 0) {
- for (i = 0; i < (sizeof (SpecialCasePCIRegRb) / sizeof (UINT16)); i ++) {
- if (SpecialCasePCIRegRb[i] == Address.Address.Register) {
- *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2)) = *(UINT32 *) Value;
- }
- }
- }
- }
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function stores special case register on the heap.
- *
- * @param[in,out] *NBPtr - Pointer to the northbridge block.
- * @param[in,out] *StdHeader - Config handle for library and services.
- * @return none
- */
-VOID
-STATIC
-MemNS3ExitSelfRefRegRb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- LOCATE_HEAP_PTR LocateBufferPtr;
- UINT8 i;
- PCI_ADDR PciAddr;
- UINT32 Value;
- UINT8 NodeID;
- UINT8 Offset;
- S3_SPECIAL_CASE_HEAP_HEADER *SpecialHeapHeader;
-
- Offset = 0;
- PciAddr.Address.Device = NBPtr->PciAddr.Address.Device;
- PciAddr.Address.Bus = NBPtr->PciAddr.Address.Bus;
- PciAddr.Address.Segment = NBPtr->PciAddr.Address.Segment;
- PciAddr.Address.Function = 2;
- LocateBufferPtr.BufferHandle = AMD_MEM_S3_DATA_HANDLE;
- if (HeapLocateBuffer (&LocateBufferPtr, StdHeader) == AGESA_SUCCESS) {
- SpecialHeapHeader = (S3_SPECIAL_CASE_HEAP_HEADER *) LocateBufferPtr.BufferPtr;
- // Get the node ID of the target die.
- NodeID = (UINT8) (PciAddr.Address.Device - 24);
- for (i = 0; i < MAX_NODES_SUPPORTED_DA; i ++) {
- if (SpecialHeapHeader[i].Node == NodeID) {
- // Get the offset in the heap for the target die.
- Offset = SpecialHeapHeader[i].Offset;
- break;
- }
- }
- ASSERT (i < MAX_NODES_SUPPORTED_DA);
- // Restore the value one by one in the sequence of the special case register array.
- if (Offset != 0) {
- for (i = 0; i < (sizeof (SpecialCasePCIRegRb) / sizeof (UINT16)); i ++) {
- PciAddr.Address.Register = SpecialCasePCIRegRb[i];
- Value = *(UINT32 *) (LocateBufferPtr.BufferPtr + Offset + (i << 2));
- MemNS3SetCSRNb (AccessS3SaveWidth32, PciAddr, &Value, StdHeader);
- }
- }
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/RB/mnS3Rb.h b/src/vendorcode/amd/agesa/Proc/Mem/NB/RB/mnS3Rb.h
deleted file mode 100644
index 407c3f8..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/RB/mnS3Rb.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnS3Rb.h
- *
- * S3 resume memory related function for RB.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/RB)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MNS3RB_H_
-#define _MNS3RB_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-/// ID for register list of RB
-typedef enum {
- PCI_LST_ESR_DA, ///< Assign 0x0000 for PCI register list for pre exit self refresh.
- PCI_LST_DA, ///< Assign 0x0001 for PCI register list for post exist self refresh.
- CPCI_LST_ESR_DA, ///< Assign 0x0002 for conditional PCI register list for pre exit self refresh.
- CPCI_LST_DA, ///< Assign 0x0003 for conditional PCI register list for post exit self refresh.
- MSR_LST_ESR_DA, ///< Assign 0x0004 for MSR register list for pre exit self refresh.
- MSR_LST_DA, ///< Assign 0x0005 for MSR register list for post exit self refresh.
- CMSR_LST_ESR_DA, ///< Assign 0x0006 for conditional MSR register list for pre exit self refresh.
- CMSR_LST_DA, ///< Assign 0x0007 for conditional MSR register list for post exit self refresh.
-} RegisterListIDDA;
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-#endif //_MNS3RB_H_
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/RB/mnflowRb.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/RB/mnflowRb.c
deleted file mode 100644
index 3138c27..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/RB/mnflowRb.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnflowRb.c
- *
- * RidgeBack initializer for MCT and DCT
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/RB)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mnda.h"
-#include "mnRb.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_RB_MNFLOWRB_FILECODE
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-extern MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledRb[MAX_FF_TYPES];
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the platform specific block
- *
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - AGESA_SUCCESS at least one dorm factor was found
- * @return FALSE - AGESA_UNSUPPORTED - Error indicating that no form factors were found
- */
-
-BOOLEAN
-MemNPlatformSpecificFormFactorInitRb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 Dct;
- UINT8 f;
- UINT8 ErrUnSuppFFCount;
- for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- if (NBPtr->ChannelPtr->ChDimmValid != 0) {
- ErrUnSuppFFCount = 0;
- for (f = 0; f < MAX_FF_TYPES; f++) {
- ASSERT (memPlatSpecFFInstalledRb[f] != NULL);
- if (memPlatSpecFFInstalledRb[f] (NBPtr->MemPtr, NBPtr->ChannelPtr, NBPtr->PsPtr) == AGESA_UNSUPPORTED) {
- ErrUnSuppFFCount++; //Count the number of AGESA_UNSUPPORTED errors
- } else {
- break;
- }
- }
- if (ErrUnSuppFFCount == MAX_FF_TYPES) {
- return FALSE; // No FF types are supported
- }
- }
- }
- return TRUE;
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/RB/mnidendimmRb.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/RB/mnidendimmRb.c
deleted file mode 100644
index ce1f1c2..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/RB/mnidendimmRb.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnidendimmRb.c
- *
- * RB northbridge constructor for dimm identification translator.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/RB)
- * @e \$Revision: 36520 $ @e \$Date: 2010-08-20 14:57:36 +0800 (Fri, 20 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "mm.h"
-#include "mn.h"
-#include "OptionMemory.h" // need def for MEM_FEAT_BLOCK_NB
-#include "mnda.h"
-#include "mnRb.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuFamRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_NB_RB_MNIDENDIMMRB_FILECODE
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the northbridge block for dimm identification translator
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
- * @param[in,out] NodeID - ID of current node to construct
- * @return TRUE - This is the correct constructor for the targeted node.
- * @return FALSE - This isn't the correct constructor for the targeted node.
- *
- */
-
-BOOLEAN
-MemNIdentifyDimmConstructorRb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- )
-{
- //
- // Determine if this is the expected NB Type
- //
- GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
- if (!MemNIsIdSupportedRb (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
- return FALSE;
- }
-
- NBPtr->NodeCount = MAX_NODES_SUPPORTED_DA;
- NBPtr->DctCount = MAX_DCTS_PER_NODE_DA;
- NBPtr->MemPtr = MemPtr;
- NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]);
- NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue;
- NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24;
- NBPtr->Ganged = FALSE;
- InitNBRegTableDA (NBPtr, NBPtr->NBRegTable);
- NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldDA;
- NBPtr->SetBitField = MemNSetBitFieldNb;
- NBPtr->GetBitField = MemNGetBitFieldNb;
- NBPtr->GetSocketRelativeChannel = MemNGetSocketRelativeChannelNb;
-
- return TRUE;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/mn.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/mn.c
deleted file mode 100644
index 5624527..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/mn.c
+++ /dev/null
@@ -1,527 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mn.c
- *
- * Common Northbridge functions
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mport.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mu.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_MN_FILECODE
-
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemNDefaultFamilyHookNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT VOID *OptParam
- );
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-extern OPTION_MEM_FEATURE_NB* memNTrainFlowControl[];
-
-extern BUILD_OPT_CFG UserOptions;
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initializes member functions and variables of NB block.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNInitNBDataNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- INT32 i;
- UINT8 *BytePtr;
-
- NBPtr->DctCachePtr = NBPtr->DctCache;
- NBPtr->PsPtr = NBPtr->PSBlock;
-
- BytePtr = (UINT8 *) (NBPtr->DctCache);
- for (i = 0; i < sizeof (NBPtr->DctCache); i++) {
- *BytePtr++ = 0;
- }
-
- for (i = 0; i < EnumSize; i++) {
- NBPtr->IsSupported[i] = FALSE;
- }
-
- for (i = 0; i < NumberOfHooks; i++) {
- NBPtr->FamilySpecificHook[i] = MemNDefaultFamilyHookNb;
- }
-
- NBPtr->SwitchDCT = MemNSwitchDCTNb;
- NBPtr->SwitchChannel = MemNSwitchChannelNb;
- NBPtr->GetBitField = MemNGetBitFieldNb;
- NBPtr->SetBitField = MemNSetBitFieldNb;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * Get System address of Chipselect RJ 16 bits (Addr[47:16])
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Receiver - Chipselect to be targeted [0-7]
- * @param[out] AddrPtr - Pointer to System Address [47:16]
- *
- * @return TRUE - Address is valid
- * @return FALSE - Address is not valid
- */
-
-BOOLEAN
-MemNGetMCTSysAddrNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Receiver,
- OUT UINT32 *AddrPtr
- )
-{
- S_UINT64 SMsr;
- UINT32 CSBase;
- UINT32 HoleBase;
- UINT32 DctSelBaseAddr;
- UINT32 BottomUma;
- DIE_STRUCT *MCTPtr;
- MEM_DATA_STRUCT *MemPtr;
-
- MCTPtr = NBPtr->MCTPtr;
- MemPtr = NBPtr->MemPtr;
-
- ASSERT (Receiver < 8);
-
- CSBase = MemNGetBitFieldNb (NBPtr, BFCSBaseAddr0Reg + Receiver);
- if (CSBase & 1) {
- ASSERT ((CSBase & 0xE0) == 0); // Should not enable CS interleaving before DQS training.
-
- // Scale base address from [39:8] to [47:16]
- CSBase >>= 8;
-
- HoleBase = MCTPtr->NodeHoleBase ? MCTPtr->NodeHoleBase : 0x7FFFFFFF;
-
- if ((MemNGetBitFieldNb (NBPtr, BFDctSelHiRngEn) == 1) && (NBPtr->Dct == MemNGetBitFieldNb (NBPtr, BFDctSelHi))) {
- DctSelBaseAddr = MemNGetBitFieldNb (NBPtr, BFDctSelBaseAddr) << (27 - 16);
- if (DctSelBaseAddr > HoleBase) {
- DctSelBaseAddr -= _4GB_RJ16 - HoleBase;
- }
- CSBase += DctSelBaseAddr;
- } else {
- CSBase += MCTPtr->NodeSysBase;
- }
-
- if (CSBase >= HoleBase) {
- CSBase += _4GB_RJ16 - HoleBase;
- }
-
- CSBase += (UINT32)1 << (21 - 16); // Add 2MB offset to avoid compat area.
- if ((CSBase >= (MCT_TRNG_KEEPOUT_START >> 8)) && (CSBase <= (MCT_TRNG_KEEPOUT_END >> 8))) {
- CSBase += (((MCT_TRNG_KEEPOUT_END >> 8) - CSBase) + 0x0F) & 0xFFFFFFF0;
- }
-
- if (MCTPtr->Status[SbHWHole]) {
- if (MCTPtr->Status[SbSWNodeHole]) {
- LibAmdMsrRead (TOP_MEM, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-
- if ((CSBase >= (SMsr.lo >> 16)) && (CSBase < _4GB_RJ16)) {
- return FALSE;
- }
- }
- }
-
- BottomUma = NBPtr->RefPtr->Sub4GCacheTop >> 16;
- if (BottomUma && (CSBase >= BottomUma) && (CSBase < _4GB_RJ16)) {
- return FALSE;
- }
- *AddrPtr = CSBase;
- return TRUE;
- }
- return FALSE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function determines if a Rank is enabled.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Receiver - Receiver to check
- * @return - FALSE
- *
- */
-
-BOOLEAN
-MemNRankEnabledNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Receiver
- )
-{
- UINT32 CSBase;
- CSBase = MemNGetBitFieldNb (NBPtr, BFCSBaseAddr0Reg + Receiver);
- if (CSBase & 1) {
- return TRUE;
- } else {
- return FALSE;
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function sets the EccSymbolSize bit depending upon configurations
- * and system override.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNSetEccSymbolSizeNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT16 X4DimmsOnly;
- BOOLEAN Size;
- DIE_STRUCT *MCTPtr;
- DCT_STRUCT *DCTPtr;
-
- ASSERT (NBPtr != NULL);
-
- MCTPtr = NBPtr->MCTPtr;
- DCTPtr = NBPtr->DCTPtr;
-
- // Determine if this node has only x4 DRAM parts
- X4DimmsOnly = (UINT16) ((!(DCTPtr->Timings.Dimmx8Present | DCTPtr->Timings.Dimmx16Present)) && DCTPtr->Timings.Dimmx4Present);
- //
- // Check if EccSymbolSize BKDG value is overridden
- //
- if (UserOptions.CfgEccSymbolSize != ECCSYMBOLSIZE_USE_BKDG) {
- Size = (UserOptions.CfgEccSymbolSize == ECCSYMBOLSIZE_FORCE_X4) ? FALSE : TRUE;
- } else {
- if (X4DimmsOnly && MCTPtr->GangedMode) {
- Size = FALSE;
- } else {
- Size = TRUE;
- }
- }
- IDS_OPTION_HOOK (IDS_ECCSYMBOLSIZE, &Size, &(NBPtr->MemPtr->StdHeader));
- MemNSetBitFieldNb (NBPtr, BFEccSymbolSize, (UINT32) Size);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the training control flow
- * The DDR3 mode bit must be set prior to calling this function
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- */
-BOOLEAN
-MemNTrainingFlowNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode)!= 0) {
- memNTrainFlowControl[DDR3_TRAIN_FLOW] (NBPtr);
- } else {
- memNTrainFlowControl[DDR2_TRAIN_FLOW] (NBPtr);
- }
- return TRUE;
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- *
- * This function flushes the training pattern
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Address - System Address [47:16]
- * @param[in] ClCount - Number of cache lines
- *
- */
-
-VOID
-MemNFlushPatternNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 Address,
- IN UINT16 ClCount
- )
-{
- // Due to speculative execution during MemUReadCachelines, we must
- // flush one more cache line than we read.
- MemUProcIOClFlush (Address, ClCount + 1, NBPtr->MemPtr);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function compares test pattern with data in buffer and
- * return a pass/fail bitmap for 8 bytelanes (upper 8 bits are reserved)
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Buffer[] - Buffer data from DRAM (Measured data from DRAM) to compare
- * @param[in] Pattern[] - Pattern (Expected data in ROM/CACHE) to compare against
- * @param[in] ByteCount - Byte count
- *
- * @return PASS - Bitmap of results of comparison
- */
-
-UINT16
-MemNCompareTestPatternNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Buffer[],
- IN UINT8 Pattern[],
- IN UINT16 ByteCount
- )
-{
- UINT16 i;
- UINT16 Pass;
- UINT8 ColumnCount;
- UINT8 FailingBitMask[8];
-
- ASSERT ((ByteCount == 18 * 64) || (ByteCount == 9 * 64) || (ByteCount == 64 * 64) || (ByteCount == 32 * 64) || (ByteCount == 3 * 64));
-
- ColumnCount = NBPtr->ChannelPtr->ColumnCount;
- Pass = 0xFFFF;
- //
- // Clear Failing Bit Mask
- //
- for (i = 0; i < sizeof (FailingBitMask); i++) {
- FailingBitMask[i] = 0;
- }
-
- if (NBPtr->Ganged && (NBPtr->Dct != 0)) {
- i = 8; // DCT 1 in ganged mode
- } else {
- i = 0;
- }
-
- for (; i < ByteCount; i++) {
- if (Buffer[i] != Pattern[i]) {
- // if bytelane n fails
- Pass &= ~((UINT16)1 << (i % 8)); // clear bit n
- FailingBitMask[i % NBPtr->TechPtr->MaxByteLanes ()] |= (Buffer[i] ^ Pattern[i]);
- }
-
- if (NBPtr->Ganged && ((i & 7) == 7)) {
- i += 8; // if ganged, skip over other Channel's Data
- }
- }
- //
- // Accumulate Failing bit data
- //
- for (i = 0; i < sizeof (FailingBitMask); i++) {
- NBPtr->ChannelPtr->FailingBitMask[(ColumnCount * NBPtr->TechPtr->ChipSel) + i] &=
- FailingBitMask[i];
- }
-
- return Pass;
-}
-
-/*-----------------------------------------------------------------------------
- *
- *
- * This function compares test pattern with data in buffer and
- * return a pass/fail bitmap for 8 bytelanes (upper 8 bits are reserved)
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Buffer[] - Buffer data from DRAM (Measured data from DRAM) to compare
- * @param[in] Pattern[] - Pattern (Expected data in ROM/CACHE) to compare against
- * @param[in] ByteCount - Byte count
- *
- * @retval PASS - Bitmap of results of comparison
- * ----------------------------------------------------------------------------
- */
-UINT16
-MemNInsDlyCompareTestPatternNb (
- IN MEM_NB_BLOCK *NBPtr,
- IN UINT8 Buffer[],
- IN UINT8 Pattern[],
- IN UINT16 ByteCount
- )
-{
- UINT16 i;
- UINT16 Pass;
- UINT16 BeatOffset;
- UINT16 BeatCnt;
- UINT8 ColumnCount;
- UINT8 FailingBitMask[8];
-
- ASSERT ((ByteCount == 18 * 64) || (ByteCount == 9 * 64) || (ByteCount == 64 * 64) || (ByteCount == 32 * 64) || (ByteCount == 3 * 64));
-
- ColumnCount = NBPtr->ChannelPtr->ColumnCount;
- Pass = 0xFFFF;
- //
- // Clear Failing Bit Mask
- //
- for (i = 0; i < sizeof (FailingBitMask); i++) {
- FailingBitMask[i] = 0;
- }
-
- if (NBPtr->Ganged && (NBPtr->Dct != 0)) {
- i = 8; // DCT 1 in ganged mode
- } else {
- i = 0;
- }
-
- if (NBPtr->Ganged) {
- BeatOffset = 16;
- } else {
- BeatOffset = 8;
- }
-
- BeatCnt = 0;
- for (; i < ByteCount; i++) {
-
- if (Buffer[i] != Pattern[i + BeatOffset]) {
- // if bytelane n fails
- Pass &= ~((UINT16)1 << (i % 8)); // clear bit n
- FailingBitMask[i % NBPtr->TechPtr->MaxByteLanes ()] |= (Buffer[i] ^ Pattern[i + BeatOffset]);
- }
-
- if ((i & 7) == 7) {
- if (NBPtr->Ganged) {
- i += 8; // if ganged, skip over other Channel's Data
- }
- BeatCnt++;
- }
-
- if ((BeatCnt & 3) == 3) {
- // Skip last data beat of a 4-beat burst.
- BeatCnt++;
- i = i + BeatOffset;
- }
- }
- //
- // Accumulate Failing bit data
- //
- for (i = 0; i < sizeof (FailingBitMask); i++) {
- NBPtr->ChannelPtr->FailingBitMask[(ColumnCount * NBPtr->TechPtr->ChipSel) + i] &=
- FailingBitMask[i];
- }
-
- return Pass;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the training control flow for UNB
- * The DDR3 mode bit must be set prior to calling this function
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- */
-BOOLEAN
-MemNTrainingFlowUnb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- memNTrainFlowControl[DDR3_TRAIN_FLOW] (NBPtr);
- return TRUE;
-}
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- *
- *
- * This function is an empty function used to intialize FamilySpecificHook array
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] OptParam - Optional parameter
- *
- * @return TRUE - always
- * ----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemNDefaultFamilyHookNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT VOID *OptParam
- )
-{
- return TRUE;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/mnS3.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/mnS3.c
deleted file mode 100644
index b6ed940..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/mnS3.c
+++ /dev/null
@@ -1,929 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnS3.c
- *
- * Common Northbridge S3
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB)
- * @e \$Revision: 38639 $ @e \$Date: 2010-09-27 21:55:34 +0800 (Mon, 27 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "S3.h"
-#include "mfs3.h"
-#include "cpuFamilyTranslation.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G3_DXE)
-RDATA_GROUP (G3_DXE)
-
-#define FILECODE PROC_MEM_NB_MNS3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-VOID
-STATIC
-MemNS3GetSetBitField (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR Address,
- IN BOOLEAN IsSet,
- IN OUT VOID *Value,
- IN OUT VOID *ConfigPtr
- );
-
-BOOLEAN
-STATIC
-MemNS3GetDummyReadAddr (
- IN OUT MEM_NB_BLOCK *NBPtr,
- OUT UINT64 *TestAddr
- );
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function executes the S3 resume for a node
- *
- * @param[in,out] *S3NBPtr - Pointer to the S3_MEM_NB_BLOCK
- * @param[in] NodeID - The Node id of the target die
- *
- * @return BOOLEAN
- * TRUE - This is the correct constructor for the targeted node.
- * FALSE - This isn't the correct constructor for the targeted node.
- */
-
-BOOLEAN
-MemNS3ResumeNb (
- IN OUT S3_MEM_NB_BLOCK *S3NBPtr,
- IN UINT8 NodeID
- )
-{
- UINT8 DCT;
- BOOLEAN GangedEn;
- UINT64 TestAddr;
- MEM_NB_BLOCK *NBPtr;
- MEM_DATA_STRUCT *MemPtr;
-
- NBPtr = S3NBPtr->NBPtr;
- MemPtr = NBPtr->MemPtr;
- GangedEn = (MemNGetBitFieldNb (NBPtr, BFDctGangEn) == 1) ? TRUE : FALSE;
-
- // Errata before S3 resume sequence
-
- // Resume Sequence
- // 1. Program F2x[1,0]9C_x08[DisAutoComp]=1
- MemNSwitchDCTNb (NBPtr, 0);
- MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 1);
-
- // Program F2x[1, 0]94[MemClkFreqVal] = 1.
- // 2. Wait for F2x[1,0]94[FreqChgInPrg]=0
- for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) {
- MemNSwitchDCTNb (NBPtr, DCT);
- if ((MemNGetBitFieldNb (NBPtr, BFDisDramInterface) == 0) && !((DCT == 1) && GangedEn)) {
- MemNSetBitFieldNb (NBPtr, BFMemClkFreqVal, 1);
- while (MemNGetBitFieldNb (NBPtr, BFFreqChgInProg) != 0) {}
- }
- }
-
- // Program F2x9C_x08[DisAutoComp]=0
- MemNSwitchDCTNb (NBPtr, 0);
- MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 0);
- // BIOS must wait 750 us for the phy compensation engine
- // to reinitialize.
- MemFS3Wait10ns (75000, NBPtr->MemPtr);
-
- // 3. Restore F2x[1,0]90_x00, F2x9C_x0A, and F2x[1,0]9C_x0C
- // 4. Restore F2x[1,0]9C_x04
- // Get the register value from the heap.
- S3NBPtr->MemS3ExitSelfRefReg (NBPtr, &MemPtr->StdHeader);
-
- // Add a hook here
- AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeExitSelfRef, &MemPtr->StdHeader);
- if (AgesaHookBeforeExitSelfRefresh (0, MemPtr) == AGESA_SUCCESS) {
- }
- AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeExitSelfRef, &MemPtr->StdHeader);
-
- // 5. Set F2x[1,0]90[ExitSelfRef]
- // 6. Wait for F2x[1,0]90[ExitSelfRef]=0
- for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) {
- MemNSwitchDCTNb (NBPtr, DCT);
- if ((MemNGetBitFieldNb (NBPtr, BFDisDramInterface) == 0) && !((DCT == 1) && GangedEn)) {
- MemNSetBitFieldNb (NBPtr, BFExitSelfRef, 1);
- while (MemNGetBitFieldNb (NBPtr, BFExitSelfRef) != 0) {}
- }
- if ((MemNGetBitFieldNb (NBPtr, BFMemClkFreq) == DDR1333_FREQUENCY) && (NBPtr->IsSupported[CheckDllSpeedUp])) {
- MemNSetBitFieldNb (NBPtr, BFPhy0x0D080F11, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D080F11) | 0x2000));
- MemNSetBitFieldNb (NBPtr, BFPhy0x0D080F10, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D080F10) | 0x2000));
- MemNSetBitFieldNb (NBPtr, BFPhy0x0D088F30, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D088F30) | 0x2000));
- MemNSetBitFieldNb (NBPtr, BFPhy0x0D08C030, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D08C030) | 0x2000));
- if (DCT == 0) {
- MemNSetBitFieldNb (NBPtr, BFPhy0x0D082F30, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D082F30) | 0x2000));
- }
- // NOTE: wait 512 clocks for DLL-relock
- MemFS3Wait10ns (50000, NBPtr->MemPtr); // wait 500us
- }
- }
-
- // Errata After S3 resume sequence
- // Errata 350
- for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) {
- MemNSwitchDCTNb (NBPtr, DCT);
- if (MemNGetBitFieldNb (NBPtr, BFDisDramInterface) == 0) {
- if (!((DCT == 1) && GangedEn)) {
- if (MemNS3GetDummyReadAddr (NBPtr, &TestAddr)) {
- // Do dummy read
- Read64Mem8 (TestAddr);
- // Flush the cache line
- LibAmdCLFlush (TestAddr, 1);
- }
- }
- MemNSetBitFieldNb (NBPtr, BFErr350, 0x8000);
- MemFS3Wait10ns (60, NBPtr->MemPtr); // Wait 300ns
- MemNSetBitFieldNb (NBPtr, BFErr350, 0x0000);
- MemFS3Wait10ns (400, NBPtr->MemPtr); // Wait 2us
- }
- }
-
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function executes the S3 resume for a node on a client NB
- *
- * @param[in,out] *S3NBPtr - Pointer to the S3_MEM_NB_BLOCK
- * @param[in] NodeID - The Node id of the target die
- *
- * @return BOOLEAN
- * TRUE - This is the correct constructor for the targeted node.
- * FALSE - This isn't the correct constructor for the targeted node.
- */
-BOOLEAN
-MemNS3ResumeClientNb (
- IN OUT S3_MEM_NB_BLOCK *S3NBPtr,
- IN UINT8 NodeID
- )
-{
- UINT8 DCT;
- MEM_NB_BLOCK *NBPtr;
- MEM_DATA_STRUCT *MemPtr;
-
- NBPtr = S3NBPtr->NBPtr;
- MemPtr = NBPtr->MemPtr;
-
- // Errata before S3 resume sequence
-
- // Add a hook here
- AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeExitSelfRef, &MemPtr->StdHeader);
- if (AgesaHookBeforeExitSelfRefresh (0, MemPtr) == AGESA_SUCCESS) {
- }
- AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeExitSelfRef, &MemPtr->StdHeader);
-
- NBPtr->ChangeNbFrequencyWrap (NBPtr, 0);
- //Override the NB Pstate if needed
- IDS_OPTION_HOOK (IDS_NB_PSTATE_DIDVID, S3NBPtr->NBPtr, &MemPtr->StdHeader);
- // Set F2x[1,0]90[ExitSelfRef]
- // Wait for F2x[1,0]90[ExitSelfRef]=0
- for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) {
- MemNSwitchDCTNb (NBPtr, DCT);
- if (MemNGetBitFieldNb (NBPtr, BFDisDramInterface) == 0) {
- MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 1);
- MemNSetBitFieldNb (NBPtr, BFExitSelfRef, 1);
- while (MemNGetBitFieldNb (NBPtr, BFExitSelfRef) != 0) {}
- MemNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 0);
- }
- }
-
- // Errata After S3 resume sequence
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function returns the conditional PCI device mask
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP
- * @return none
- */
-VOID
-MemNS3GetConPCIMaskNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT DESCRIPTOR_GROUP *DescriptPtr
- )
-{
- BIT_FIELD_NAME bitfield;
- UINT32 RegVal;
- UINT8 DCT;
- UINT8 DimmMask;
- UINT8 BadDimmMask;
- UINT8 DctGangEn;
- BOOLEAN IsDDR3;
-
- IsDDR3 = FALSE;
- DimmMask = 0;
- BadDimmMask = 0;
- for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) {
- NBPtr->SwitchDCT (NBPtr, DCT);
- if (MemNGetBitFieldNb (NBPtr, BFMemClkFreqVal)) {
- if (MemNGetBitFieldNb (NBPtr, BFDdr3Mode) == 1) {
- IsDDR3 = TRUE;
- }
- for (bitfield = BFCSBaseAddr0Reg; bitfield <= BFCSBaseAddr7Reg; bitfield ++) {
- RegVal = MemNGetBitFieldNb (NBPtr, bitfield);
- if (RegVal & 0x3) {
- DimmMask |= (UINT8) (1 << ((((bitfield - BFCSBaseAddr0Reg) >> 1) << 1) + DCT));
- } else if (RegVal & 0x4) {
- BadDimmMask |= (UINT8) (1 << ((((bitfield - BFCSBaseAddr0Reg) >> 1) << 1) + DCT));
- }
- }
- }
- }
-
- NBPtr->SwitchDCT (NBPtr, 0);
- DctGangEn = (UINT8) MemNGetBitFieldNb (NBPtr, BFDctGangEn);
- // Set channel mask
- DescriptPtr->CPCIDevice[PRESELFREF].Mask1 = 0;
- DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 = 0;
- for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) {
- if (DimmMask & (0x55 << DCT)) {
- // Set mask before exit self refresh
- DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= 1 << DCT;
- // Set mask after exit self refresh
- DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= 1 << DCT;
- // Set DDR3 mask if Dimms present are DDR3
- if (IsDDR3) {
- DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= (DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 << 4);
- }
- } else if (BadDimmMask & (0x55 << DCT)) {
- // Need to save function 2 registers for bad dimm
- DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= 1 << DCT;
- }
- }
-
- // Set dimm mask
- DescriptPtr->CPCIDevice[PRESELFREF].Mask2 = DimmMask;
- DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 = DimmMask;
- if (DctGangEn) {
- // Need to set channel mask bit to 1 on DCT1 in ganged mode as some registers
- // need to be restored on both channels in ganged mode
- DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= 2;
- DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= 2;
- if (IsDDR3) {
- DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= (2 << 4);
- DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= (2 << 4);
- }
- // Before exit self refresh, do not copy dimm mask to DCT1 as registers restored
- // in that time frame don't care about individual dimm population. We want to
- // skip registers that are not needed to be restored for DCT1 in ganged mode.
- //
- // After exit self refresh, training registers will be restored and will only be
- // restored for slots which have dimms on it. So dimm mask needs to be copied to DCT1.
- //
- DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 |= DimmMask << 1;
- }
-
- // Adjust the mask if there is no dimm on the node
- if ((DescriptPtr->CPCIDevice[PRESELFREF].Mask2 == 0) &&
- (DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 == 0)) {
- DescriptPtr->CPCIDevice[PRESELFREF].Mask1 = DescriptPtr->CPCIDevice[PRESELFREF].Mask2 = NODE_WITHOUT_DIMM_MASK;
- DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 = DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 = NODE_WITHOUT_DIMM_MASK;
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function read the value of CSR register.
- *
- * @param[in] AccessWidth - Access width of the register
- * @param[in] Address - address of the CSR register in PCI_ADDR format.
- * @param[in] *Value - Pointer to the value be read.
- * @param[in, out] *ConfigPtr - Pointer to Config handle.
- * @return none
- */
-VOID
-MemNS3GetCSRNb (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR Address,
- IN VOID *Value,
- IN OUT VOID *ConfigPtr
- )
-{
- UINT32 ExtendOffset;
- UINT32 ValueRead;
- UINT8 DataPort;
-
- ValueRead = 0;
- ExtendOffset = Address.Address.Register;
- if (ExtendOffset & 0x800) {
- Address.Address.Register = 0xF0;
- DataPort = 0xF4;
- } else {
- Address.Address.Register = 0x98;
- DataPort = 0x9C;
- }
- if (ExtendOffset & 0x400) {
- Address.Address.Register |= 0x100;
- }
- ExtendOffset &= 0x3FF;
- LibAmdPciWrite (AccessS3SaveWidth32, Address, &ExtendOffset, ConfigPtr);
- while (((ValueRead >> 31) & 1) == 0) {
- LibAmdPciRead (AccessS3SaveWidth32, Address, &ValueRead, ConfigPtr);
- }
- Address.Address.Register = (Address.Address.Register & 0xF00) | DataPort;
- LibAmdPciRead (AccessWidth, Address, Value, ConfigPtr);
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function write to a CSR register
- *
- * @param[in] AccessWidth - Access width of the register
- * @param[in] Address - address of the CSR register in PCI_ADDR format.
- * @param[in, out] *Value - Pointer to the value be read.
- * @param[in, out] *ConfigPtr - Pointer to Config handle.
- * @return none
- */
-VOID
-MemNS3SetCSRNb (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR Address,
- IN OUT VOID *Value,
- IN OUT VOID *ConfigPtr
- )
-{
- UINT32 ExtendOffset;
- UINT32 ValueRead;
- UINT32 ValueWrite;
- UINT8 DataOffset;
-
- ValueRead = 0;
- ExtendOffset = Address.Address.Register;
- // Check the flag and see the type of the access
- if (ExtendOffset & 0x800) {
- Address.Address.Register = 0xF4;
- DataOffset = 0xF0;
- } else {
- Address.Address.Register = 0x9C;
- DataOffset = 0x98;
- }
- if (ExtendOffset & 0x400) {
- Address.Address.Register |= 0x100;
- }
- ExtendOffset &= 0x3FF;
- ExtendOffset |= 0x40000000;
- switch (AccessWidth) {
- case AccessS3SaveWidth8:
- ValueWrite = *(UINT8 *) Value;
- break;
- case AccessS3SaveWidth16:
- ValueWrite = *(UINT16 *) Value;
- break;
- case AccessS3SaveWidth32:
- ValueWrite = *(UINT32 *) Value;
- break;
- default:
- ASSERT (FALSE);
- }
- LibAmdPciWrite (AccessS3SaveWidth32, Address, &ValueWrite, ConfigPtr);
- Address.Address.Register = (Address.Address.Register & 0xF00) | DataOffset;
- LibAmdPciWrite (AccessS3SaveWidth32, Address, &ExtendOffset, ConfigPtr);
- while (((ValueRead >> 31) & 1) == 0) {
- LibAmdPciRead (AccessS3SaveWidth32, Address, &ValueRead, ConfigPtr);
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function reads register bitfield
- *
- * @param[in] AccessWidth - Access width of the register
- * @param[in] Address - address of the CSR register in PCI_ADDR format.
- * @param[in, out] *Value - Pointer to the value be read.
- * @param[in, out] *ConfigPtr - Pointer to Config handle.
- * @return none
- */
-VOID
-MemNS3GetBitFieldNb (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR Address,
- IN OUT VOID *Value,
- IN OUT VOID *ConfigPtr
- )
-{
- MemNS3GetSetBitField (AccessWidth, Address, FALSE, Value, ConfigPtr);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function writes register bitfield
- *
- * @param[in] AccessWidth - Access width of the register
- * @param[in] Address - address of the CSR register in PCI_ADDR format.
- * @param[in, out] *Value - Pointer to the value to be written.
- * @param[in, out] *ConfigPtr - Pointer to Config handle.
- * @return none
- */
-VOID
-MemNS3SetBitFieldNb (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR Address,
- IN OUT VOID *Value,
- IN OUT VOID *ConfigPtr
- )
-{
- MemNS3GetSetBitField (AccessWidth, Address, TRUE, Value, ConfigPtr);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function restores scrubber base register
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Node - The Node id of the target die
- *
- */
-VOID
-MemNS3RestoreScrubNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Node
- )
-{
- UINT32 ScrubAddrRJ16;
-
- ScrubAddrRJ16 = (MemNGetBitFieldNb (NBPtr, BFDramBaseReg0 + Node) & 0xFFFF0000) >> 8;
- ScrubAddrRJ16 |= MemNGetBitFieldNb (NBPtr, BFDramBaseHiReg0 + Node) << 24;
- MemNSetBitFieldNb (NBPtr, BFScrubAddrLoReg, ScrubAddrRJ16 << 16);
- MemNSetBitFieldNb (NBPtr, BFScrubAddrHiReg, ScrubAddrRJ16 >> 16);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function disable NB Pstate Debug.
- *
- * @param[in] AccessWidth - Access width of the register.
- * @param[in] Address - address in PCI_ADDR format.
- * @param[in, out] *Value - Pointer to the value to be written.
- * @param[in, out] *ConfigPtr - Pointer to Config handle.
- * @return none
- */
-VOID
-MemNS3DisNbPsDbgNb (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR Address,
- IN OUT VOID *Value,
- IN OUT VOID *ConfigPtr
- )
-{
- UINT32 RegValue;
-
- LibAmdPciRead (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr);
- // Clear NbPsDbgEn and NbPsCsrAccSel
- if ((RegValue & 0xC0000000) != 0) {
- RegValue &= 0x3FFFFFFF;
- LibAmdPciWrite (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr);
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function that enable NB Pstate debug register to allow access to NB Pstate
- * 1 registers without actually changing NB Pstate.
- *
- * @param[in] AccessWidth - Access width of the register.
- * @param[in] Address - address in PCI_ADDR format.
- * @param[in, out] *Value - Pointer to the value to be written.
- * @param[in, out] *ConfigPtr - Pointer to Config handle.
- * @return none
- */
-VOID
-MemNS3EnNbPsDbg1Nb (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR Address,
- IN OUT VOID *Value,
- IN OUT VOID *ConfigPtr
- )
-{
- UINT32 RegValue;
-
- LibAmdPciRead (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr);
- // Set NbPsDbgEn to 1 and NbPsCsrAccSel to 1
- if ((RegValue & 0xC0000000) != 0xC0000000) {
- RegValue = (*(UINT32 *)Value & 0x3FFFFFFF) | 0xC0000000;
- LibAmdPciWrite (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr);
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function sets bit 31 [DynModeChange] of F2x9C_xB
- *
- * @param[in] AccessWidth - Access width of the register.
- * @param[in] Address - address in PCI_ADDR format.
- * @param[in, out] *Value - Pointer to the value to be written.
- * @param[in, out] *ConfigPtr - Pointer to Config handle.
- * @return none
- */
-VOID
-MemNS3SetDynModeChangeNb (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR Address,
- IN OUT VOID *Value,
- IN OUT VOID *ConfigPtr
- )
-{
- UINT32 RegValue;
-
- RegValue = 0x80000000;
- IDS_SKIP_HOOK (IDS_BEFORE_S3_SPECIAL, &Address, ConfigPtr) {
- MemNS3SetCSRNb (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr);
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function does the channel disable sequence
- *
- * @param[in] AccessWidth - Access width of the register.
- * @param[in] Address - address in PCI_ADDR format.
- * @param[in, out] *Value - Pointer to the value to be written.
- * @param[in, out] *ConfigPtr - Pointer to Config handle.
- * @return none
- */
-VOID
-MemNS3DisableChannelNb (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR Address,
- IN OUT VOID *Value,
- IN OUT VOID *ConfigPtr
- )
-{
- MEM_NB_BLOCK *NBPtr;
- LOCATE_HEAP_PTR LocateBufferPtr;
- S3_MEM_NB_BLOCK *S3NBPtr;
- UINT32 RegValue;
- UINT8 Die;
-
- // See which Node should be accessed
- Die = (UINT8) (Address.Address.Device - 24);
-
- LocateBufferPtr.BufferHandle = AMD_MEM_S3_NB_HANDLE;
- if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) {
- S3NBPtr = (S3_MEM_NB_BLOCK *) LocateBufferPtr.BufferPtr;
- NBPtr = S3NBPtr[Die].NBPtr;
-
- // Function field contains the DCT number
- NBPtr->SwitchDCT (NBPtr, (UINT8) Address.Address.Function);
- RegValue = MemNGetBitFieldNb (NBPtr, BFCKETri);
- // if CKETri is 0b11, this channel is disabled
- if (RegValue == 3) {
- //Wait for 24 MEMCLKs, which is 60ns under 400MHz
- MemFS3Wait10ns (6, NBPtr->MemPtr);
- MemNSetBitFieldNb (NBPtr, BFMemClkDis, 0xFF);
- MemNSetBitFieldNb (NBPtr, BFDisDramInterface, 1);
- MemNSetBitFieldNb (NBPtr, BFDramPhyStatusReg, 0x80800000);
- }
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function disables auto compensation.
- *
- * @param[in] AccessWidth - Access width of the register.
- * @param[in] Address - address in PCI_ADDR format.
- * @param[in, out] *Value - Pointer to the value to be written.
- * @param[in, out] *ConfigPtr - Pointer to Config handle.
- * @return none
- */
-VOID
-MemNS3SetDisAutoCompUnb (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR Address,
- IN OUT VOID *Value,
- IN OUT VOID *ConfigPtr
- )
-{
- UINT16 RegValue;
-
- MemNS3GetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr);
- RegValue = 0x6000 | RegValue;
- MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function retores Pre Driver Calibration with pre driver calibration code
- * code valid bit set.
- *
- * @param[in] AccessWidth - Access width of the register.
- * @param[in] Address - address in PCI_ADDR format.
- * @param[in, out] *Value - Pointer to the value to be written.
- * @param[in, out] *ConfigPtr - Pointer to Config handle.
- * @return none
- */
-VOID
-MemNS3SetPreDriverCalUnb (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR Address,
- IN OUT VOID *Value,
- IN OUT VOID *ConfigPtr
- )
-{
- UINT16 RegValue;
-
- RegValue = 0x8000 | *(UINT16 *) Value;
- MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr);
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------*/
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function reads and writes register bitfield
- *
- * @param[in] AccessWidth - Access width of the register
- * @param[in] Address - address of the CSR register in PCI_ADDR format.
- * @param[in] IsSet - if this is a register read or write
- * @param[in, out] *Value - Pointer to the value be read or written.
- * @param[in, out] *ConfigPtr - Pointer to Config handle.
- * @return none
- */
-VOID
-STATIC
-MemNS3GetSetBitField (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR Address,
- IN BOOLEAN IsSet,
- IN OUT VOID *Value,
- IN OUT VOID *ConfigPtr
- )
-{
- BIT_FIELD_NAME BitField;
- MEM_NB_BLOCK *NBPtr;
- LOCATE_HEAP_PTR LocateBufferPtr;
- S3_MEM_NB_BLOCK *S3NBPtr;
- UINT32 RegValue;
- UINT8 Die;
-
- RegValue = 0;
- // See which Node should be accessed
- Die = (UINT8) (Address.Address.Device - 24);
-
- LocateBufferPtr.BufferHandle = AMD_MEM_S3_NB_HANDLE;
- if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) {
- S3NBPtr = (S3_MEM_NB_BLOCK *) LocateBufferPtr.BufferPtr;
- NBPtr = S3NBPtr[Die].NBPtr;
-
- // Function field contains the DCT number
- NBPtr->SwitchDCT (NBPtr, (UINT8) Address.Address.Function);
-
- // Get the bitfield name to be accessed
- // Register field contains the bitfield name
- BitField = (BIT_FIELD_NAME) Address.Address.Register;
-
- if (IsSet) {
- switch (AccessWidth) {
- case AccessS3SaveWidth8:
- RegValue = *(UINT8 *) Value;
- break;
- case AccessS3SaveWidth16:
- RegValue = *(UINT16 *) Value;
- break;
- case AccessS3SaveWidth32:
- RegValue = *(UINT32 *) Value;
- default:
- ASSERT (FALSE);
- }
- MemNSetBitFieldNb (NBPtr, BitField, RegValue);
- } else {
- RegValue = MemNGetBitFieldNb (NBPtr, BitField);
-
- switch (AccessWidth) {
- case AccessS3SaveWidth8:
- *(UINT8 *) Value = (UINT8) RegValue;
- break;
- case AccessS3SaveWidth16:
- *(UINT16 *) Value = (UINT16) RegValue;
- break;
- case AccessS3SaveWidth32:
- *(UINT32 *) Value = RegValue;
- break;
- default:
- ASSERT (FALSE);
- }
- }
- } else {
- ASSERT (FALSE);
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function gets the dummy read address for a channel of a node.
- *
- * @param[in, out] *NBPtr - Pointer to northbridge block
- * @param[out] *TestAddr - Pointer to the test address
- *
- * @retval TRUE - Dummy read address can be found
- * @retval FALSE - Dummy read address cannot be found
- *
- */
-BOOLEAN
-STATIC
-MemNS3GetDummyReadAddr (
- IN OUT MEM_NB_BLOCK *NBPtr,
- OUT UINT64 *TestAddr
- )
-{
- BOOLEAN DctSelIntlvEn;
- UINT8 DramIntlvEn;
- UINT8 DctSelIntlvAddr;
- UINT8 IntLvRgnBaseAddr;
- UINT8 IntLvRgnLmtAddr;
- UINT8 IntLvRgnSize;
- UINT32 DctSelBaseAddr;
- UINT64 TOM;
- BOOLEAN AddrFound;
-
- AddrFound = TRUE;
- // Check if Node interleaving is enabled
- DramIntlvEn = (UINT8) MemNGetBitFieldNb (NBPtr, BFDramIntlvEn);
- if (DramIntlvEn != 0) {
- // Set the address bits that identify the node
- *TestAddr = (UINT64) MemNGetBitFieldNb (NBPtr, BFDramIntlvSel) << 12;
- } else {
- *TestAddr = (UINT64) MemNGetBitFieldNb (NBPtr, BFDramBaseAddr) << 27;
- }
-
- // Check if channel interleaving is enabled
- DctSelIntlvEn = (BOOLEAN) MemNGetBitFieldNb (NBPtr, BFDctSelIntLvEn);
- DctSelBaseAddr = MemNGetBitFieldNb (NBPtr, BFDctSelBaseAddr);
- if (!DctSelIntlvEn) {
- if ((NBPtr->Dct == 1) && ((UINT8) MemNGetBitFieldNb (NBPtr, BFDctSelHi) == 1)) {
- *TestAddr = ((UINT64) DctSelBaseAddr << 27) | (*TestAddr & 0xFFFFFFF);
- }
- } else {
- DctSelIntlvAddr = (UINT8) MemNGetBitFieldNb (NBPtr, BFDctSelIntLvAddr);
- // Set the address bits that identify the channel
- if ((DctSelIntlvAddr == 0) || (DctSelIntlvAddr == 2)) {
- *TestAddr |= (UINT64) NBPtr->Dct << 6;
- } else if (DctSelIntlvAddr == 1) {
- *TestAddr |= (UINT64) NBPtr->Dct << (12 + LibAmdBitScanReverse (DramIntlvEn + 1));
- } else if (DctSelIntlvAddr == 3) {
- *TestAddr |= (UINT64) NBPtr->Dct << 9;
- }
- }
- // Adding 2M to avoid conflict
- *TestAddr += 0x200000;
-
- // If memory hoisting is disabled, the address can fall into MMIO area
- // Need to find an address out of MMIO area but belongs to the channel
- // If the whole channel is in MMIO, then do not do dummy read.
- //
- LibAmdMsrRead (TOP_MEM, &TOM, &NBPtr->MemPtr->StdHeader);
- if ((*TestAddr >= TOM) && (*TestAddr < ((UINT64) _4GB_RJ16 << 16))) {
- if ((NBPtr->Dct == 1) && ((UINT8) MemNGetBitFieldNb (NBPtr, BFDctSelHi) == 1)) {
- // This is the DCT that goes to high address range
- if (DctSelBaseAddr >= (_4GB_RJ16 >> (27 - 16))) {
- // When DctSelBaseAddr is higher than 4G, choose DctSelBaseAddr as the dummy read addr
- if (DctSelIntlvEn) {
- *TestAddr = ((UINT64) DctSelBaseAddr << 27) | (*TestAddr & 0xFFFFFFF);
- }
- } else if (MemNGetBitFieldNb (NBPtr, BFDramLimitAddr) > (UINT32) (_4GB_RJ16 >> (27 - 16))) {
- // if DctSelBase is smaller than 4G, but Dram limit is larger than 4G, then choose 4G as
- // dummy read address
- *TestAddr = ((UINT64) _4GB_RJ16 << 16) | (*TestAddr & 0xFFFFFF);
- } else {
- AddrFound = FALSE;
- }
- } else {
- // This is the DCT that only goes to low address range
- if (DctSelBaseAddr > (_4GB_RJ16 >> (27 - 16))) {
- // When DctSelBaseAddr is larger than 4G, choose 4G as the dummy read address
- // Keep the lower bits for node and channel selection
- *TestAddr = ((UINT64) _4GB_RJ16 << 16) | (*TestAddr & 0xFFFFFF);
- } else {
- AddrFound = FALSE;
- }
- }
- }
-
- // Interleaved Swap Region handling
- if ((BOOLEAN) MemNGetBitFieldNb (NBPtr, BFIntLvRgnSwapEn)) {
- IntLvRgnBaseAddr = (UINT8) MemNGetBitFieldNb (NBPtr, BFIntLvRgnBaseAddr);
- IntLvRgnLmtAddr = (UINT8) MemNGetBitFieldNb (NBPtr, BFIntLvRgnLmtAddr);
- IntLvRgnSize = (UINT8) MemNGetBitFieldNb (NBPtr, BFIntLvRgnSize);
- ASSERT (IntLvRgnSize == (IntLvRgnLmtAddr - IntLvRgnBaseAddr + 1));
- if (((*TestAddr >> 34) == 0) &&
- ((((*TestAddr >> 27) >= IntLvRgnBaseAddr) && ((*TestAddr >> 27) <= IntLvRgnLmtAddr))
- || ((*TestAddr >> 27) < IntLvRgnSize))) {
- *TestAddr ^= (UINT64) IntLvRgnBaseAddr << 27;
- }
- }
-
- return AddrFound;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/mndct.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/mndct.c
deleted file mode 100644
index 32d6f2c..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/mndct.c
+++ /dev/null
@@ -1,2651 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mndct.c
- *
- * Common Northbridge DCT support
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB)
- * @e \$Revision: 38442 $ @e \$Date: 2010-09-24 06:39:57 +0800 (Fri, 24 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mport.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mu.h"
-#include "mftds.h"
-#include "merrhdl.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_MNDCT_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define UNUSED_CLK 4
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-VOID
-STATIC
-MemNAfterStitchMemNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-UINT8
-MemNGet1KTFawTkNb (
- IN UINT8 k
- );
-
-UINT8
-MemNGet2KTFawTkNb (
- IN UINT8 k
- );
-
-VOID
-STATIC
-MemNQuarterMemClk2NClkNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT UINT16 *SubTotalPtr
- );
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function combines all the memory into a contiguous map.
- * Requires that Mask values for each bank be programmed first and that
- * the chip-select population indicator is correctly set.
- *
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - An Error value lower than AGESA_FATAL may have occurred
- * @return FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred
- */
-
-BOOLEAN
-MemNStitchMemoryNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- BOOLEAN DSpareEn;
- UINT32 NxtCSBase;
- UINT32 CurCSBase;
- UINT32 CsSize;
- UINT32 BiggestBank;
- UINT8 p;
- UINT8 q;
- UINT8 BiggestDimm;
- MEM_PARAMETER_STRUCT *RefPtr;
- DIE_STRUCT *MCTPtr;
- DCT_STRUCT *DCTPtr;
- RefPtr = NBPtr->RefPtr;
- MCTPtr = NBPtr->MCTPtr;
- DCTPtr = NBPtr->DCTPtr;
- DSpareEn = FALSE;
- if (NBPtr->IsSupported[SetSpareEn]) {
- DSpareEn = FALSE;
- if (RefPtr->GStatus[GsbEnDIMMSpareNW]) {
- DSpareEn = TRUE;
- }
- }
-
- DCTPtr->Timings.CsEnabled = 0;
- NxtCSBase = 0;
- for (p = 0; p < MAX_CS_PER_CHANNEL; p++) {
- BiggestBank = 0;
- BiggestDimm = 0;
- for (q = 0; q < MAX_CS_PER_CHANNEL; q++) {
- if (((DCTPtr->Timings.CsPresent & ~DCTPtr->Timings.CsTestFail) & ((UINT16)1 << q)) != 0) {
- if ((MemNGetBitFieldNb (NBPtr, BFCSBaseAddr0Reg + q) & 7) == 0) {
- // (CSEnable|Spare==1)bank is not enabled yet
- CsSize = MemNGetBitFieldNb (NBPtr, BFCSMask0Reg + (q >> 1));
- if (CsSize != 0) {
- CsSize += ((UINT32)1 << 19);
- CsSize &= 0xFFF80000;
- }
- if (CsSize > BiggestBank) {
- BiggestBank = CsSize;
- BiggestDimm = q;
- }
- }
- }
- }
-
- if (BiggestBank != 0) {
- CurCSBase = NxtCSBase;
- if (NBPtr->IsSupported[CheckSpareEn]) {
- if (DSpareEn) {
- CurCSBase = ((UINT32)1 << BFSpare);
- DSpareEn = FALSE;
- } else {
- CurCSBase |= ((UINT32)1 << BFCSEnable);
- NxtCSBase += BiggestBank;
- }
- } else {
- CurCSBase |= ((UINT32)1 << BFCSEnable);
- NxtCSBase += BiggestBank;
- }
- if ((BiggestDimm & 1) != 0) {
- if (!(MCTPtr->Status[SbLrdimms])) {
- // For LRDIMMS, On Dimm Mirroring is enabled after SDI
- if ((DCTPtr->Timings.DimmMirrorPresent & (1 << (BiggestDimm >> 1))) != 0) {
- CurCSBase |= ((UINT32)1 << BFOnDimmMirror);
- }
- }
- }
- MemNSetBitFieldNb (NBPtr, BFCSBaseAddr0Reg + BiggestDimm, CurCSBase);
- DCTPtr->Timings.CsEnabled |= (1 << BiggestDimm);
- }
- if ((DCTPtr->Timings.CsTestFail & ((UINT16)1 << p)) != 0) {
- IDS_HDT_CONSOLE (MEM_FLOW, "Node %d Dct %d exclude CS %d\n", NBPtr->Node, NBPtr->Dct, p);
- MemNSetBitFieldNb (NBPtr, (BFCSBaseAddr0Reg + p), (UINT32)1 << BFTestFail);
- }
- }
-
- if (NxtCSBase != 0) {
- DCTPtr->Timings.DctMemSize = NxtCSBase >> 8; // Scale base address from [39:8] to [47:16]
- MemNAfterStitchMemNb (NBPtr);
- }
-
- return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function gets platform specific config/timing values from the interface layer and
- * programs them into DCT.
- *
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - An Error value lower than AGESA_FATAL may have occurred
- * @return FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred
- */
-
-BOOLEAN
-MemNPlatformSpecNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- CONST BIT_FIELD_NAME ChipletPDRegs[] = {
- BFPhyClkConfig0,
- BFPhyClkConfig3,
- BFPhyClkConfig1,
- BFPhyClkConfig2
- };
- CONST UINT8 ChipletPDClkDisMap[][2] = {
- //F2[1, 0]x9C_x0D0F2030 -> F2x[1, 0]88[MemClkDis[1:0]]
- {0, 1},
- //F2[1, 0]x9C_x0D0F2330 -> F2x[1, 0]88[MemClkDis[7:6]]
- {6, 7},
- //F2x09C_x0D0F2130 -> F2x88[MemClkDis[5:4]]
- {4, 5},
- //F2x09C_x0D0F2230 -> F2x88[MemClkDis[3:2]]
- {2, 3},
- //F2x19C_x0D0F2130 -> F2x188[MemClkDis[5:2]]
- {2, 5},
- //F2x19C_x0D0F2230 -> F2x188[MemClkDis[4:3]]
- {3, 4}
- };
-
- UINT8 MemClkDis;
- UINT8 i;
- UINT8 MemoryAllClocks;
- UINT8 *MemClkDisMap;
- UINT16 CsPresent;
- UINT8 RegIndex;
- UINT8 Cs1;
- UINT8 Cs2;
-
- if (!MemNGetPlatformCfgNb (NBPtr)) {
- IDS_ERROR_TRAP;
- }
-
- if (!NBPtr->PsPtr->MemPDoPs (NBPtr)) {
- IDS_ERROR_TRAP;
- }
- MemNProgramPlatformSpecNb (NBPtr);
-
- MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_ODT, ALL_DIMMS);
-
- if (NBPtr->MCTPtr->GangedMode) {
- MemNSwitchDCTNb (NBPtr, 1);
- if (!MemNGetPlatformCfgNb (NBPtr)) {
- IDS_ERROR_TRAP;
- }
- MemNProgramPlatformSpecNb (NBPtr);
- MemNSwitchDCTNb (NBPtr, 0);
- }
-
- //======================================================================
- // Disable unused MemClk to save power
- //======================================================================
- //
- MemClkDis = 0;
- MemoryAllClocks = UserOptions.CfgMemoryAllClocksOn;
- IDS_OPTION_HOOK (IDS_ALL_MEMORY_CLOCK, &MemoryAllClocks, &(NBPtr->MemPtr->StdHeader));
- if (!MemoryAllClocks) {
- // Special Jedec SPD diagnostic bit - "enable all clocks"
- if (!NBPtr->MCTPtr->Status[SbDiagClks]) {
- MemClkDisMap = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MEMCLK_DIS, NBPtr->MCTPtr->SocketId, MemNGetSocketRelativeChannelNb (NBPtr, NBPtr->Dct, 0));
- if (MemClkDisMap == NULL) {
- MemClkDisMap = NBPtr->ChannelPtr->MemClkDisMap;
- }
-
- // Turn off the unused CS clocks
- CsPresent = NBPtr->DCTPtr->Timings.CsPresent;
-
- if (NBPtr->IsSupported[CheckMemClkCSPresent]) {
- if (NBPtr->ChannelPtr->RegDimmPresent != 0) {
- // All DDR3 RDIMM use only one MEMCLOCK from edge finger to the register
- // regardless of how many Ranks are on the DIMM (Single, Dual or Quad)
- CsPresent = (CsPresent | (CsPresent >> 1)) & 0x5555;
- }
- }
- for (i = 0; i < 8; i++) {
- if ((CsPresent & MemClkDisMap[i]) == 0) {
- MemClkDis |= (UINT8) (1 << i);
- }
- }
- //Chiplet power down
- for (RegIndex = 0; RegIndex < GET_SIZE_OF (ChipletPDRegs); RegIndex++) {
- if ((NBPtr->Dct == 1) && (RegIndex >= 2)) {
- Cs1 = MemClkDisMap[ChipletPDClkDisMap[RegIndex + 2][0]];
- Cs2 = MemClkDisMap[ChipletPDClkDisMap[RegIndex + 2][1]];
- } else {
- Cs1 = MemClkDisMap[ChipletPDClkDisMap[RegIndex][0]];
- Cs2 = MemClkDisMap[ChipletPDClkDisMap[RegIndex][1]];
- }
- if ((CsPresent & (UINT16) (Cs1 | Cs2)) == 0) {
- MemNSetBitFieldNb (NBPtr, ChipletPDRegs[RegIndex], (MemNGetBitFieldNb (NBPtr, ChipletPDRegs[RegIndex]) | 0x10));
- }
- }
- }
- }
- MemNSetBitFieldNb (NBPtr, BFMemClkDis, MemClkDis);
-
- AGESA_TESTPOINT (TPProcMemPhyCompensation, &(NBPtr->MemPtr->StdHeader));
- NBPtr->MemNInitPhyComp (NBPtr);
-
- MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_SLEWRATE, ALL_DIMMS);
-
- // Program DramTerm for DDR2
- if ((MemNGetBitFieldNb (NBPtr, BFDdr3Mode)) == 0) {
- MemNSetBitFieldNb (NBPtr, BFDramTerm, NBPtr->PsPtr->DramTerm);
- } else {
- // Dynamic Dynamic DramTerm for DDR3
- // Dram Term for DDR3 may vary based on chip selects
- MemNSetBitFieldNb (NBPtr, BFDramTermDyn, NBPtr->PsPtr->DynamicDramTerm);
- }
-
- MemFInitTableDrive (NBPtr, MTAfterPlatformSpec);
-
- return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function gets platform specific config/timing values from the interface layer and
- * programs them into DCT.
- *
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - An Error value lower than AGESA_FATAL may have occurred
- * @return FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred
- */
-
-BOOLEAN
-MemNPlatformSpecUnb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 MemClkDis;
- UINT8 i;
- UINT8 MemoryAllClocks;
- UINT8 *MemClkDisMap;
- UINT16 CsPresent;
-
- if (!MemNGetPlatformCfgNb (NBPtr)) {
- IDS_ERROR_TRAP;
- }
-
- if (!NBPtr->PsPtr->MemPDoPs (NBPtr)) {
- IDS_HDT_CONSOLE (MEM_FLOW, "\tDisable DCT%d due to unsupported DIMM configuration\n", NBPtr->Dct);
- NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader);
- NBPtr->DisableDCT (NBPtr);
- } else {
-
- MemNProgramPlatformSpecNb (NBPtr);
- MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_ODT, ALL_DIMMS);
-
- //======================================================================
- // Disable unused MemClk to save power
- //======================================================================
- //
- MemClkDis = 0;
- MemoryAllClocks = UserOptions.CfgMemoryAllClocksOn;
- IDS_OPTION_HOOK (IDS_ALL_MEMORY_CLOCK, &MemoryAllClocks, &(NBPtr->MemPtr->StdHeader));
- if (!MemoryAllClocks) {
- // Special Jedec SPD diagnostic bit - "enable all clocks"
- if (!NBPtr->MCTPtr->Status[SbDiagClks]) {
- MemClkDisMap = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MEMCLK_DIS, NBPtr->MCTPtr->SocketId, NBPtr->Dct);
- if (MemClkDisMap == NULL) {
- MemClkDisMap = NBPtr->ChannelPtr->MemClkDisMap;
- }
-
- // Turn off unused clocks
- CsPresent = NBPtr->DCTPtr->Timings.CsPresent;
-
- for (i = 0; i < 8; i++) {
- if ((CsPresent & MemClkDisMap[i]) == 0) {
- MemClkDis |= (UINT8) (1 << i);
- }
- }
-
- // Turn off unused chiplets
- for (i = 0; i < 3; i++) {
- if (((MemClkDis >> (i * 2)) & 0x3) == 0x3) {
- MemNSetBitFieldNb (NBPtr, BFPhyClkConfig0 + i, 0x0010);
- }
- }
- }
- }
- MemNSetBitFieldNb (NBPtr, BFMemClkDis, MemClkDis);
- MemFInitTableDrive (NBPtr, MTAfterPlatformSpec);
- }
-
- return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function disables the DCT and mem clock
- *
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNDisableDCTNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MemNSetBitFieldNb (NBPtr, BFCKETri, 0x03);
- MemNSetBitFieldNb (NBPtr, BFODTTri, 0x0F);
- MemNSetBitFieldNb (NBPtr, BFChipSelTri, 0xFF);
-
- // To maximize power savings when DisDramInterface=1b,
- // all of the MemClkDis bits should also be set.
- //
- MemNSetBitFieldNb (NBPtr, BFMemClkDis, 0xFF);
- MemNSetBitFieldNb (NBPtr, BFDisDramInterface, 1);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function disables the DCT and mem clock for client NB
- *
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNDisableDCTClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MemNSetBitFieldNb (NBPtr, BFCKETri, 0x03);
- MemNSetBitFieldNb (NBPtr, BFODTTri, 0x0F);
- MemNSetBitFieldNb (NBPtr, BFChipSelTri, 0xFF);
-
- //Wait for 24 MEMCLKs
- MemNWaitXMemClksNb (NBPtr, 24);
-
- // To maximize power savings when DisDramInterface=1b,
- // all of the MemClkDis bits should also be set.
- //
- MemNSetBitFieldNb (NBPtr, BFMemClkDis, 0xFF);
-
- MemNSetBitFieldNb (NBPtr, BFDramPhyStatusReg, 0x80800000);
-
- MemNSetBitFieldNb (NBPtr, BFDisDramInterface, 1);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the DRAM devices on all DCTs at the same time
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNStartupDCTNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- // 1. Ensure F2x[1, 0]9C_x08[DisAutoComp] = 1.
- // 2. BIOS waits 5 us for the disabling of the compensation engine to complete.
- // DisAutoComp is still being set since InitPhyComp
-
- if (NBPtr->MCTPtr->NodeMemSize != 0) {
- // Init MemClk frequency
- MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 1);
-
-
- AGESA_TESTPOINT (TpProcMemBeforeDramInit, &(NBPtr->MemPtr->StdHeader));
- NBPtr->MemNBeforeDramInitNb (NBPtr);
- IDS_HDT_CONSOLE (MEM_FLOW, "\nMemClkFreq: %d MHz\n", NBPtr->DCTPtr->Timings.Speed);
- AGESA_TESTPOINT (TpProcMemDramInit, &(NBPtr->MemPtr->StdHeader));
- NBPtr->FeatPtr->DramInit (NBPtr->TechPtr);
- }
-
- // 7. Program F2x[1, 0]9C_x08[DisAutoComp] = 0.
- // 8. BIOS must wait 750 us for the phy compensation engine
- // to reinitialize.
- // DisAutoComp will be cleared after DramEnabled turns to 1
-
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the DRAM devices on all DCTs at the same time
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNStartupDCTUnb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 Dct;
-
- if (NBPtr->MCTPtr->NodeMemSize != 0) {
- // Update NB frequency for startup DDR speed
- NBPtr->ChangeNbFrequency (NBPtr);
-
- // Program D18F2x[1,0]9C_x0000_000B = 80000000h. #109999.
- MemNBrdcstSetNb (NBPtr, BFDramPhyStatusReg, 0x80000000);
-
- // Program D18F2x[1,0]9C_x0D0F_E013[PllRegWaitTime] = 0118h. #194060.
- MemNBrdcstSetNb (NBPtr, BFPllRegWaitTime, 0x118);
-
- // Phy Voltage Level Programming
- MemNPhyVoltageLevelNb (NBPtr);
-
- // Run frequency change sequence
- MemNBrdcstSetNb (NBPtr, BFPllLockTime, NBPtr->FreqChangeParam->PllLockTimeDefault);
- MemNBrdcstSetNb (NBPtr, BFMemClkFreq, NBPtr->GetMemClkFreqId (NBPtr, NBPtr->DCTPtr->Timings.Speed));
- NBPtr->ProgramNbPsDependentRegs (NBPtr);
- MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 1);
- MemNPollBitFieldNb (NBPtr, BFFreqChgInProg, 0, PCI_ACCESS_TIMEOUT, TRUE);
- NBPtr->FamilySpecificHook[AfterMemClkFreqVal] (NBPtr, &Dct);
- MemNBrdcstSetNb (NBPtr, BFPllLockTime, 0x000F);
-
- NBPtr->FamilySpecificHook[BeforePhyFenceTraining] (NBPtr, NBPtr);
-
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- MemNSwitchDCTNb (NBPtr, Dct);
- if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
- IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct);
-
- // Phy fence programming
- AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader));
- NBPtr->PhyFenceTraining (NBPtr);
-
- // Phy compensation initialization
- AGESA_TESTPOINT (TPProcMemPhyCompensation, &(NBPtr->MemPtr->StdHeader));
- NBPtr->MemNInitPhyComp (NBPtr);
- MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_SLEWRATE, ALL_DIMMS);
- }
- }
-
- AGESA_TESTPOINT (TpProcMemBeforeDramInit, &(NBPtr->MemPtr->StdHeader));
- NBPtr->MemNBeforeDramInitNb (NBPtr);
-
- AGESA_TESTPOINT (TpProcMemDramInit, &(NBPtr->MemPtr->StdHeader));
- IDS_HDT_CONSOLE (MEM_FLOW, "\nMemClkFreq: %d MHz\n", NBPtr->DCTPtr->Timings.Speed);
- NBPtr->FeatPtr->DramInit (NBPtr->TechPtr);
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * MemNChangeFrequencyHy:
- *
- * This function change MemClk frequency to the value that is specified by DCTPtr->Timings.Speed
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNChangeFrequencyNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MEM_TECH_BLOCK *TechPtr;
- UINT8 Dct;
- UINT8 ChipSel;
- UINT32 Dummy;
-
- TechPtr = NBPtr->TechPtr;
- if (NBPtr->IsSupported[CheckDisDllShutdownSR] && !(NBPtr->IsSupported[SetDllShutDown])) {
- // #107421
- MemNBrdcstSetNb (NBPtr, BFDisDllShutdownSR, 1);
- }
-
- //Program F2x[1,0]90[EnterSelfRefresh]=1.
- //Wait until the hardware resets F2x[1,0]90[EnterSelfRefresh]=0.
- MemNBrdcstSetNb (NBPtr, BFEnterSelfRef, 1);
- MemNPollBitFieldNb (NBPtr, BFEnterSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE);
-
- //Program F2x9C_x08[DisAutoComp]=1
- MemNSwitchDCTNb (NBPtr, 0);
- MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 1);
-
- //Program F2x[1, 0]94[MemClkFreqVal] = 0.
- MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 0);
-
- //Program F2x[1, 0]94[MemClkFreq] to specify the target MEMCLK frequency.
- MemNBrdcstSetNb (NBPtr, BFMemClkFreq, NBPtr->GetMemClkFreqId (NBPtr, NBPtr->DCTPtr->Timings.Speed));
-
- IDS_OPTION_HOOK (IDS_BEFORE_MEM_FREQ_CHG, NBPtr, &(NBPtr->MemPtr->StdHeader));
- //Program F2x[1, 0]94[MemClkFreqVal] = 1.
- MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 1);
-
- //Wait until F2x[1, 0]94[FreqChgInProg]=0.
- MemNPollBitFieldNb (NBPtr, BFFreqChgInProg, 0, PCI_ACCESS_TIMEOUT, TRUE);
-
- if (NBPtr->IsSupported[CheckPhyFenceTraining]) {
- //Perform Phy Fence retraining after frequency changed
- AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader));
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- MemNSwitchDCTNb (NBPtr, Dct);
- if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
- IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct);
- AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader));
- MemNPhyFenceTrainingNb (NBPtr);
- }
- }
- }
-
- //Program F2x9C_x08[DisAutoComp]=0
- MemNSwitchDCTNb (NBPtr, 0);
- MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 0);
-
- //Program F2x[1,0]90[ExitSelfRef]=1 for both DCTs.
- //Wait until the hardware resets F2x[1, 0]90[ExitSelfRef]=0.
- MemNBrdcstSetNb (NBPtr, BFExitSelfRef, 1);
- MemNPollBitFieldNb (NBPtr, BFExitSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE);
-
- if (NBPtr->MCTPtr->Status[SbRegistered]) {
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- MemNSwitchDCTNb (NBPtr, Dct);
- if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
- TechPtr->FreqChgCtrlWrd (TechPtr);
- }
- }
- }
-
- //wait for 500 MCLKs after ExitSelfRef, 500*2.5ns=1250ns
- MemNWaitXMemClksNb (NBPtr, 500);
-
- if (NBPtr->IsSupported[CheckDisDllShutdownSR] && !(NBPtr->IsSupported[SetDllShutDown])) {
- // #107421
- MemNBrdcstSetNb (NBPtr, BFDisDllShutdownSR, 0);
- }
-
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct);
- MemNSwitchDCTNb (NBPtr, Dct);
- if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
-
- //9.Configure the DCT to send initialization MR commands:
- // BIOS must reprogram Twr, Tcwl, and Tcl based on the new MEMCLK frequency.
- // Program F2x[1, 0]7C similar to step #2 in Pass 1 above for the new Dimm values.
- TechPtr->AutoCycTiming (TechPtr);
- if (!MemNPlatformSpecNb (NBPtr)) {
- IDS_ERROR_TRAP;
- }
-
- for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) {
- if (NBPtr->IsSupported[CheckGetMCTSysAddr]) {
- if (MemNGetMCTSysAddrNb (NBPtr, ChipSel, &Dummy)) {
- // if chip select present
- TechPtr->SendAllMRCmds (TechPtr, ChipSel);
- // NOTE: wait 512 clocks for DLL-relock
- MemUWait10ns (50000, NBPtr->MemPtr); // wait 500us
- }
- }
- if (NBPtr->IsSupported[CheckSendAllMRCmds]) {
- if (MemNGetMCTSysAddrNb (NBPtr, ChipSel, &Dummy)) {
- // if chip select present
- TechPtr->SendAllMRCmds (TechPtr, ChipSel);
- }
- }
- }
- if ((NBPtr->DCTPtr->Timings.Speed == DDR1600_FREQUENCY) && (NBPtr->IsSupported[CheckDllSpeedUp])) {
- MemNSetBitFieldNb (NBPtr, BFPhy0x0D080F11, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D080F11) | 0x2000));
- MemNSetBitFieldNb (NBPtr, BFPhy0x0D080F10, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D080F10) | 0x2000));
- MemNSetBitFieldNb (NBPtr, BFPhy0x0D088F30, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D088F30) | 0x2000));
- MemNSetBitFieldNb (NBPtr, BFPhy0x0D08C030, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D08C030) | 0x2000));
- if (Dct == 0) {
- MemNSetBitFieldNb (NBPtr, BFPhy0x0D082F30, (MemNGetBitFieldNb (NBPtr, BFPhy0x0D082F30) | 0x2000));
- }
- // NOTE: wait 512 clocks for DLL-relock
- MemUWait10ns (50000, NBPtr->MemPtr); // wait 500us
- }
- }
- }
- // Re-enable phy compensation since it had been disabled during InitPhyComp
- MemNSwitchDCTNb (NBPtr, 0);
- MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 0);
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function ramp up frequency the next level if it have not reached
- * its TargetSpeed yet.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemNRampUpFrequencyNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- CONST UINT16 FreqList[] = {
- DDR400_FREQUENCY,
- DDR533_FREQUENCY,
- DDR667_FREQUENCY,
- DDR800_FREQUENCY,
- DDR1066_FREQUENCY,
- DDR1333_FREQUENCY,
- DDR1600_FREQUENCY,
- DDR1866_FREQUENCY
- };
- UINT8 Dct;
- UINT8 i;
- UINT16 NewSpeed;
- DIE_STRUCT *MCTPtr;
-
- MCTPtr = NBPtr->MCTPtr;
-
- // Do not change frequency when it is already at TargetSpeed
- if (NBPtr->DCTPtr->Timings.Speed == NBPtr->DCTPtr->Timings.TargetSpeed) {
- return TRUE;
- }
-
- // Find the next supported frequency level
- NewSpeed = NBPtr->DCTPtr->Timings.TargetSpeed;
- for (i = 0; i < (GET_SIZE_OF (FreqList) - 1); i++) {
- if (NBPtr->DCTPtr->Timings.Speed == FreqList[i]) {
- NewSpeed = FreqList[i + 1];
- break;
- }
- }
- ASSERT (i < (GET_SIZE_OF (FreqList) - 1));
- ASSERT (NewSpeed <= NBPtr->DCTPtr->Timings.TargetSpeed);
-
- // BIOS must program both DCTs to the same frequency.
- IDS_HDT_CONSOLE (MEM_FLOW, "\nMemClkFreq changed: %d MHz", NBPtr->DCTPtr->Timings.Speed);
- for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- NBPtr->DCTPtr->Timings.Speed = NewSpeed;
- }
- IDS_HDT_CONSOLE (MEM_FLOW, " -> %d MHz", NewSpeed);
-
- NBPtr->ChangeFrequency (NBPtr);
-
- return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function uses calculated values from DCT.Timings structure to
- * program its registers.
- *
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNProgramCycTimingsNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- CONST CTENTRY TmgAdjTab[] = {
- // BitField, Min, Max, Bias, Ratio_x2
- {BFTcl, 4, 12, 4, 2},
- {BFTrcd, 5, 12, 5, 2},
- {BFTrp, 5, 12, 5, 2},
- {BFTrtp, 4, 7, 4, 2},
- {BFTras, 15, 30, 15, 2},
- {BFTrc, 11, 42, 11, 2},
- {BFTwrDDR3, 5, 12, 4, 2},
- {BFTrrd, 4, 7, 4, 2},
- {BFTwtr, 4, 7, 4, 2},
- {BFFourActWindow, 16, 32, 14, 1}
- };
-
- DCT_STRUCT *DCTPtr;
- UINT8 *MiniMaxTmg;
- UINT8 *MiniMaxTrfc;
- UINT8 Value8;
- UINT8 j;
- BIT_FIELD_NAME BitField;
-
- DCTPtr = NBPtr->DCTPtr;
-
- //======================================================================
- // Program turnaround timings to their max during DRAM init and training
- //======================================================================
- //
- MemNSetBitFieldNb (NBPtr, BFNonSPD, 0x28FF);
-
- MemNSetBitFieldNb (NBPtr, BFNonSPDHi, 0x2A);
-
- //======================================================================
- // Program DRAM Timing values
- //======================================================================
- //
- MiniMaxTmg = &DCTPtr->Timings.CasL;
- for (j = 0; j < GET_SIZE_OF (TmgAdjTab); j++) {
- BitField = TmgAdjTab[j].BitField;
-
- if (MiniMaxTmg[j] < TmgAdjTab[j].Min) {
- MiniMaxTmg[j] = TmgAdjTab[j].Min;
- } else if (MiniMaxTmg[j] > TmgAdjTab[j].Max) {
- MiniMaxTmg[j] = TmgAdjTab[j].Max;
- }
-
- Value8 = (UINT8) MiniMaxTmg[j];
-
- if (BitField == BFTwrDDR3) {
- Value8 = (Value8 == 10) ? 9 : (Value8 >= 11) ? 10 : Value8;
- } else if (BitField == BFTrtp) {
- Value8 = (DCTPtr->Timings.Speed <= DDR1066_FREQUENCY) ? 4 : (DCTPtr->Timings.Speed == DDR1333_FREQUENCY) ? 5 : 6;
- }
-
- Value8 = Value8 - TmgAdjTab[j].Bias;
- Value8 = (Value8 * TmgAdjTab[j].Ratio_x2) >> 1;
-
- ASSERT ((BitField == BFTcl ) ? (Value8 <= 8) :
- (BitField == BFTrcd) ? (Value8 <= 7) :
- (BitField == BFTrp ) ? (Value8 <= 7) :
- (BitField == BFTrtp) ? (Value8 <= 3) :
- (BitField == BFTras) ? (Value8 <= 15) :
- (BitField == BFTrc ) ? (Value8 <= 31) :
- (BitField == BFTrrd) ? (Value8 <= 3) :
- (BitField == BFTwtr) ? (Value8 <= 3) :
- (BitField == BFTwrDDR3) ? ((Value8 >= 1) && (Value8 <= 6)) :
- (BitField == BFFourActWindow) ? ((Value8 >= 1) && (Value8 <= 9)) : FALSE);
- MemNSetBitFieldNb (NBPtr, BitField, Value8);
- }
-
- MiniMaxTrfc = &DCTPtr->Timings.Trfc0;
- for (j = 0; j < 4; j++) {
- ASSERT (MiniMaxTrfc[j] <= 4);
- MemNSetBitFieldNb (NBPtr, BFTrfc0 + j, MiniMaxTrfc[j]);
- }
-
- MemNSetBitFieldNb (NBPtr, BFTcwl, ((DCTPtr->Timings.Speed >= DDR800_FREQUENCY) ?
- (NBPtr->GetMemClkFreqId (NBPtr, DCTPtr->Timings.Speed) - 3) : 0));
-
- MemNSetBitFieldNb (NBPtr, BFTref, 2); // 7.8 us
-
- //======================================================================
- // DRAM MRS Register, set ODT
- //======================================================================
- //
- // DrvImpCtrl: drive impedance control.01b(34 ohm driver; Ron34 = Rzq/7)
- MemNSetBitFieldNb (NBPtr, BFDrvImpCtrl, 1);
-
- // burst length control
- if (NBPtr->MCTPtr->Status[Sb128bitmode]) {
- MemNSetBitFieldNb (NBPtr, BFBurstCtrl, 2);
- }
-
- // ASR=1, auto self refresh; SRT=0
- MemNSetBitFieldNb (NBPtr, BFASR, 1);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function uses calculated values from DCT.Timings structure to
- * program its registers.
- *
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNProgramCycTimingsClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- CONST CTENTRY TmgAdjTab[] = {
- // BitField, Min, Max, Bias, Ratio_x2
- {BFTcl, 5, 14, 4, 2},
- {BFTrcd, 5, 14, 5, 2},
- {BFTrp, 5, 14, 5, 2},
- {BFTrtp, 4, 8, 4, 2},
- {BFTras, 15, 36, 15, 2},
- {BFTrc, 20, 49, 11, 2},
- {BFTwrDDR3, 5, 16, 4, 2},
- {BFTrrd, 4, 8, 4, 2},
- {BFTwtr, 4, 8, 4, 2},
- {BFFourActWindow, 16, 40, 14, 1}
- };
-
- DCT_STRUCT *DCTPtr;
- UINT8 *MiniMaxTmg;
- UINT8 *MiniMaxTrfc;
- UINT8 Value8;
- UINT8 j;
- UINT8 Tcwl;
- UINT8 Trcd;
- INT32 TCK_ps;
- BIT_FIELD_NAME BitField;
-
- DCTPtr = NBPtr->DCTPtr;
-
- //======================================================================
- // Program DRAM Timing values
- //======================================================================
- //
- MiniMaxTmg = &DCTPtr->Timings.CasL;
- for (j = 0; j < GET_SIZE_OF (TmgAdjTab); j++) {
- BitField = TmgAdjTab[j].BitField;
-
- if (MiniMaxTmg[j] < TmgAdjTab[j].Min) {
- MiniMaxTmg[j] = TmgAdjTab[j].Min;
- } else if (MiniMaxTmg[j] > TmgAdjTab[j].Max) {
- MiniMaxTmg[j] = TmgAdjTab[j].Max;
- }
-
- Value8 = (UINT8) MiniMaxTmg[j];
-
- if (BitField == BFTwrDDR3) {
- if (NBPtr->IsSupported[AdjustTwr]) {
- Value8 ++;
- }
- Value8 = (Value8 >= 10) ? (((Value8 + 1) / 2) + 4) : Value8;
- }
-
- Value8 = Value8 - TmgAdjTab[j].Bias;
- Value8 = (Value8 * TmgAdjTab[j].Ratio_x2) >> 1;
-
- ASSERT ((BitField == BFTcl ) ? ((Value8 >= 1) && (Value8 <= 10)) :
- (BitField == BFTrcd) ? (Value8 <= 9) :
- (BitField == BFTrp ) ? (Value8 <= 9) :
- (BitField == BFTrtp) ? (Value8 <= 4) :
- (BitField == BFTras) ? (Value8 <= 21) :
- (BitField == BFTrc ) ? ((Value8 >= 9) && (Value8 <= 38)) :
- (BitField == BFTrrd) ? (Value8 <= 4) :
- (BitField == BFTwtr) ? (Value8 <= 4) :
- (BitField == BFTwrDDR3) ? (Value8 <= 7) :
- (BitField == BFFourActWindow) ? ((Value8 >= 1) && (Value8 <= 13)) : FALSE);
- MemNSetBitFieldNb (NBPtr, BitField, Value8);
- }
-
- MiniMaxTrfc = &DCTPtr->Timings.Trfc0;
- for (j = 0; j < 4; j++) {
- ASSERT (MiniMaxTrfc[j] <= 5);
- MemNSetBitFieldNb (NBPtr, BFTrfc0 + j, MiniMaxTrfc[j]);
- }
-
- Tcwl = (UINT8) (DCTPtr->Timings.Speed / 133) + 2;
- MemNSetBitFieldNb (NBPtr, BFTcwl, ((Tcwl > 5) ? (Tcwl - 5) : 0));
-
- MemNSetBitFieldNb (NBPtr, BFTref, 2); // Tref = 7.8 us
-
- // Skid buffer can only be programmed once before Dram init
- if (NBPtr->DCTPtr->Timings.Speed == DDR800_FREQUENCY) {
- TCK_ps = 1000500 / DCTPtr->Timings.TargetSpeed;
- Trcd = (UINT8) ((((1000 / 40) * (UINT32)DCTPtr->Timings.DIMMTrcd) + TCK_ps - 1) / TCK_ps);
- MemNSetBitFieldNb (NBPtr, BFDbeSkidBufDis, (Trcd > 10) ? 0 : 1);
- }
-
- MemNSetBitFieldNb (NBPtr, BFRdOdtTrnOnDly, (DCTPtr->Timings.CasL > Tcwl) ? (DCTPtr->Timings.CasL - Tcwl) : 0);
-
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function gets platform specific settings for the current channel
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - All platform types defined have initialized successfully
- * @return FALSE - At least one of the platform types gave not been initialized successfully
- */
-
-BOOLEAN
-MemNGetPlatformCfgNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 p;
-
- for (p = 0; p < MAX_PLATFORM_TYPES; p++) {
- ASSERT (NBPtr->MemPtr->GetPlatformCfg[p] != NULL);
- if (NBPtr->MemPtr->GetPlatformCfg[p] (NBPtr->MemPtr, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr) == AGESA_SUCCESS) {
- break;
- }
- }
- return (p < MAX_PLATFORM_TYPES);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function retrieves the Max latency parameters
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @param[in] *MinDlyPtr - Pointer to variable to store the Minimum Delay value
- * @param[in] *MaxDlyPtr - Pointer to variable to store the Maximum Delay value
- * @param[in] *DlyBiasPtr - Pointer to variable to store Delay Bias value
- * @param[in] MaxRcvEnDly - Maximum receiver enable delay value
- */
-
-VOID
-MemNGetMaxLatParamsNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT16 MaxRcvEnDly,
- IN OUT UINT16 *MinDlyPtr,
- IN OUT UINT16 *MaxDlyPtr,
- IN OUT UINT16 *DlyBiasPtr
- )
-{
- *MinDlyPtr = (MemNTotalSyncComponentsNb (NBPtr) + (MaxRcvEnDly >> 5)) * 2;
- MemNQuarterMemClk2NClkNb (NBPtr, MinDlyPtr);
-
- *MaxDlyPtr = 0x3FF;
-
- *DlyBiasPtr = 4;
- MemNQuarterMemClk2NClkNb (NBPtr, DlyBiasPtr); // 1 MEMCLK Margin
-
- *DlyBiasPtr += 1; // add 1 NCLK
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function sets the maximum round-trip latency in the system from the processor to the DRAM
- * devices and back.
- *
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] MaxRcvEnDly - Maximum receiver enable delay value
- *
- */
-
-VOID
-MemNSetMaxLatencyNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT16 MaxRcvEnDly
- )
-{
- UINT16 SubTotal;
-
- AGESA_TESTPOINT (TpProcMemRcvrCalcLatency, &(NBPtr->MemPtr->StdHeader));
-
- SubTotal = 0xC8; // init value for MaxRdLat used in training
-
-
- if (MaxRcvEnDly != 0xFFFF) {
- // Get all sync components BKDG steps 1-5
- SubTotal = MemNTotalSyncComponentsNb (NBPtr);
-
- // Add the maximum (worst case) delay value of DqsRcvEnGrossDelay
- // that exists across all DIMMs and byte lanes.
- //
- SubTotal += MaxRcvEnDly >> 5;
-
-
- // Add 14.5 to the sub-total. 14.5 represents part of the processor
- // specific constant delay value in the DRAM clock domain.
- //
- SubTotal <<= 1; // scale 1/2 MemClk to 1/4 MemClk
- SubTotal += 29; // add 14.5 1/2 MemClk
-
- // Convert the sub-total (in 1/2 MEMCLKs) to northbridge clocks (NCLKs)
- // as follows (assuming DDR400 and assuming that no P-state or link speed
- // changes have occurred).
- //
- MemNQuarterMemClk2NClkNb (NBPtr, &SubTotal);
-
- // Add 2 NCLKs to the sub-total. 2 represents part of the processor
- // specific constant value in the northbridge clock domain.
- //
- SubTotal += 2;
- }
-
- NBPtr->DCTPtr->Timings.MaxRdLat = SubTotal;
- // Program the F2x[1, 0]78[MaxRdLatency] register with the total delay value
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\tMaxRdLat: %03x\n", SubTotal);
- MemNSetBitFieldNb (NBPtr, BFMaxLatency, SubTotal);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function sends the ZQCL command
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNSendZQCmdNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- // 1.Program MrsAddress[10]=1
- MemNSetBitFieldNb (NBPtr, BFMrsAddress, (UINT32)1 << 10);
-
- // 2.Set SendZQCmd=1
- MemNSetBitFieldNb (NBPtr, BFSendZQCmd, 1);
-
- // 3.Wait for SendZQCmd=0
- MemNPollBitFieldNb (NBPtr, BFSendZQCmd, 0, PCI_ACCESS_TIMEOUT, FALSE);
-
- // 4.Wait 512 MEMCLKs
- MemNWaitXMemClksNb (NBPtr, 512);
-}
-
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function is used to create the DRAM map
- *
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- */
-
-VOID
-STATIC
-MemNAfterStitchMemNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- if (NBPtr->MCTPtr->GangedMode) {
- NBPtr->MCTPtr->NodeMemSize = NBPtr->DCTPtr->Timings.DctMemSize;
- NBPtr->MCTPtr->NodeSysLimit = NBPtr->MCTPtr->NodeMemSize - 1;
- NBPtr->MCTPtr->DctData[1].Timings.CsPresent = NBPtr->DCTPtr->Timings.CsPresent;
- NBPtr->MCTPtr->DctData[1].Timings.CsEnabled = NBPtr->DCTPtr->Timings.CsEnabled;
- NBPtr->MCTPtr->DctData[1].Timings.DctMemSize = NBPtr->DCTPtr->Timings.DctMemSize;
- } else {
- // In unganged mode, add DCT0 and DCT1 to NodeMemSize
- NBPtr->MCTPtr->NodeMemSize += NBPtr->DCTPtr->Timings.DctMemSize;
- NBPtr->MCTPtr->NodeSysLimit = NBPtr->MCTPtr->NodeMemSize - 1;
- }
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function Return the binary value of tfaw associated with
- * the index k
- *
- * @param[in] k value
- *
- * @return F[k], in Binary MHz.
- */
-
-UINT8
-MemNGet1KTFawTkNb (
- IN UINT8 k
- )
-{
- CONST UINT8 Tab1KTfawTK[] = {0, 8, 10, 13, 14, 19};
- ASSERT (k <= 5);
- return Tab1KTfawTK[k];
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function Return the binary value of the 2KTFaw associated with
- * the index k
- *
- * @param[in] k value
- *
- * @return 2KTFaw converted based on k.
- */
-
-UINT8
-MemNGet2KTFawTkNb (
- IN UINT8 k
- )
-{
- CONST UINT8 Tab2KTfawTK[] = {0, 10, 14, 17, 18, 24};
- ASSERT (k <= 5);
- return Tab2KTfawTK[k];
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function converts the sub-total (in 1/4 MEMCLKs) to northbridge clocks (NCLKs)
- * (assuming DDR400 and assuming that no P-state or link speed
- * changes have occurred).
- *
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *SubTotalPtr - pointer to Sub-Total
- */
-
-VOID
-STATIC
-MemNQuarterMemClk2NClkNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT UINT16 *SubTotalPtr
- )
-{
- UINT32 NBFreq;
- UINT32 MemFreq;
-
- // Multiply SubTotal by NB COF
- NBFreq = (MemNGetBitFieldNb (NBPtr, BFNbFid) + 4) * 200;
- // Divide SubTotal by 4 times current MemClk frequency
- MemFreq = NBPtr->DCTPtr->Timings.Speed * 4;
- *SubTotalPtr = (UINT16) (((NBFreq * (*SubTotalPtr)) + MemFreq - 1) / MemFreq); // round up
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function gets the total of sync components for Max Read Latency calculation
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return Total in 1/2 MEMCLKs
- */
-
-UINT16
-MemNTotalSyncComponentsNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT16 SubTotal;
-
- // Multiply the CAS Latency by two to get a number of 1/2 MEMCLKs UINTs.
- SubTotal = (UINT16) MemNGetBitFieldNb (NBPtr, BFTcl) + 1;
- if ((MemNGetBitFieldNb (NBPtr, BFDdr3Mode)) != 0) {
- SubTotal += 3;
- }
- SubTotal *= 2;
-
- // If registered DIMMs are being used then add 1 MEMCLK to the sub-total.
- if ((MemNGetBitFieldNb (NBPtr, BFUnBuffDimm)) == 0) {
- SubTotal += 2;
- }
-
- // If (F2x[1, 0]9C_x04[AddrCmdSetup] and F2x[1, 0]9C_x04[CsOdtSetup] and F2x[1, 0]9C_x04[Cke-Setup] = 0) then K = K + 1
- // If (F2x[1, 0]9C_x04[AddrCmdSetup] or F2x[1, 0]9C_x04[CsOdtSetup] or F2x[1, 0]9C_x04[CkeSetup] = 1) then K = K + 2
- if ((MemNGetBitFieldNb (NBPtr, BFAddrTmgControl) & 0x0202020) == 0) {
- SubTotal += 1;
- } else {
- SubTotal += 2;
- }
-
- // If the F2x[1, 0]78[RdPtrInit] field is 4, 5, 6 or 7 MEMCLKs,
- // then add 4, 3, 2, or 1 MEMCLKs, respectively to the sub-total.
- //
- SubTotal = SubTotal + (8 - (UINT16) MemNGetBitFieldNb (NBPtr, BFRdPtrInit));
-
- return SubTotal;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function swaps bits for OnDimmMirror support
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNSwapBitsNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 ChipSel;
- UINT32 MRSReg;
-
- ChipSel = (UINT8) MemNGetBitFieldNb (NBPtr, BFMrsChipSel);
- if ((ChipSel & 1) != 0) {
- MRSReg = MemNGetBitFieldNb (NBPtr, BFDramInitRegReg);
- if ((NBPtr->DCTPtr->Timings.DimmMirrorPresent & (1 << (ChipSel >> 1))) != 0) {
- MRSReg = (MRSReg & 0xFFFCFE07) | ((MRSReg&0x100A8) << 1) | ((MRSReg&0x20150) >> 1);
- MemNSetBitFieldNb (NBPtr, BFDramInitRegReg, MRSReg);
- }
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function swaps bits for OnDimmMirror support for Unb
- *
- * Dimm Mirroring Requires that, during MRS command cycles, the following
- * bits are swapped by software
- *
- * A3 -> A4 A7 -> A8
- * A4 -> A3 BA0 -> BA1
- * A5 -> A6 BA1 -> BA0
- * A6 -> A5
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNSwapBitsUnb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 ChipSel;
- UINT32 MRSBank;
- UINT32 MRSAddr;
-
- ChipSel = (UINT8) MemNGetBitFieldNb (NBPtr, BFMrsChipSel);
- if ((ChipSel & 1) != 0) {
- if ((NBPtr->DCTPtr->Timings.DimmMirrorPresent & (1 << (ChipSel >> 1))) != 0) {
- MRSBank = MemNGetBitFieldNb (NBPtr, BFMrsBank);
- MRSAddr = MemNGetBitFieldNb (NBPtr, BFMrsAddress);
-
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tCS%d MR%d %05x swapped to ->",
- (ChipSel & 0x7),
- (MRSBank & 0x7),
- (MRSAddr & 0x3FFFF));
- //
- // Swap Mrs Bank bits 0 with 1
- MRSBank = (MRSBank & 0x0100) | ((MRSBank & 0x01) << 1) | ((MRSBank & 0x02) >> 1);
- //
- // Swap Mrs Address bits 3 with 4, 5 with 6, and 7 with 8
- MRSAddr = (MRSAddr & 0x03FE07) | ((MRSAddr&0x000A8) << 1) | ((MRSAddr&0x00150) >> 1);
- MemNSetBitFieldNb (NBPtr, BFMrsBank, MRSBank);
- MemNSetBitFieldNb (NBPtr, BFMrsAddress, MRSAddr);
- }
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Programs Address/command timings, driver strengths, and tri-state fields.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-VOID
-MemNProgramPlatformSpecNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- CONST UINT8 PinType[3] = {PSO_CKE_TRI, PSO_ODT_TRI, PSO_CS_TRI};
- CONST UINT8 TabSize[3] = { 2, 4, 8};
- CONST BIT_FIELD_NAME BitField[3] = { BFCKETri, BFODTTri, BFChipSelTri};
- UINT8 *TabPtr;
- UINT8 i;
- UINT8 k;
- UINT8 Value;
- //===================================================================
- // Tristate unused CKE, ODT and chip select to save power
- //===================================================================
- //
- TabPtr = NULL;
- for (k = 0; k < sizeof (PinType); k++) {
- if (NBPtr->IsSupported[CheckFindPSOverideWithSocket]) {
- TabPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PinType[k], NBPtr->MCTPtr->SocketId, MemNGetSocketRelativeChannelNb (NBPtr, NBPtr->Dct, 0));
- }
- if (NBPtr->IsSupported[CheckFindPSDct]) {
- TabPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PinType[k], NBPtr->MCTPtr->SocketId, NBPtr->Dct);
- }
- if (TabPtr == NULL) {
- switch (k) {
- case 0:
- TabPtr = NBPtr->ChannelPtr->CKETriMap;
- break;
- case 1:
- TabPtr = NBPtr->ChannelPtr->ODTTriMap;
- break;
- case 2:
- TabPtr = NBPtr->ChannelPtr->ChipSelTriMap;
- break;
- default:
- IDS_ERROR_TRAP;
- }
- }
- ASSERT (TabPtr != NULL);
-
- Value = 0;
- for (i = 0; i < TabSize[k]; i++) {
- if ((NBPtr->DCTPtr->Timings.CsPresent & TabPtr[i]) == 0) {
- Value |= (UINT8) (1 << i);
- }
- }
-
- if (k == PSO_CS_TRI) {
- NBPtr->FamilySpecificHook[BeforeSetCsTri] (NBPtr, &Value);
- }
-
- ASSERT (k < GET_SIZE_OF (BitField));
- MemNSetBitFieldNb (NBPtr, BitField[k], Value);
- }
- NBPtr->MemNBeforePlatformSpecNb (NBPtr);
-
- //===================================================================
- // Program Address/Command timings and driver strength
- //===================================================================
- //
- MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_ADDRTMG, ALL_DIMMS);
- MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_ODCCONTROL, ALL_DIMMS);
-
- MemNSetBitFieldNb (NBPtr, BFSlowAccessMode, (NBPtr->ChannelPtr->SlowMode) ? 1 : 0);
- MemNSetBitFieldNb (NBPtr, BFODCControl, NBPtr->ChannelPtr->DctOdcCtl);
- MemNSetBitFieldNb (NBPtr, BFAddrTmgControl, NBPtr->ChannelPtr->DctAddrTmg);
- NBPtr->FamilySpecificHook[SetDqsODT] (NBPtr, NBPtr);
-
- if (NBPtr->IsSupported[CheckODTControls]) {
- MemNSetBitFieldNb (NBPtr, BFPhyRODTCSLow, NBPtr->ChannelPtr->PhyRODTCSLow);
- MemNSetBitFieldNb (NBPtr, BFPhyRODTCSHigh, NBPtr->ChannelPtr->PhyRODTCSHigh);
- MemNSetBitFieldNb (NBPtr, BFPhyWODTCSLow, NBPtr->ChannelPtr->PhyWODTCSLow);
- MemNSetBitFieldNb (NBPtr, BFPhyWODTCSHigh, NBPtr->ChannelPtr->PhyWODTCSHigh);
- }
-}
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function gets the Trdrd value
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return Trdrd value
- */
-
-UINT8
-MemNGetTrdrdNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- DCT_STRUCT *DCTPtr;
- INT8 Cgdd;
-
- DCTPtr = NBPtr->DCTPtr;
-
- // BIOS calculates Trdrd (in MEMCLKs) = CGDD / 2 + 3 clocks and programs F2x[1, 0]8C[Trdrd] with the
- // converted field value. BIOS rounds fractional values down.
- // The Critical Gross Delay Difference (CGDD) for Trdrd on any given byte lane is the largest F2x[1,
- // 0]9C_x[3:0][2B:10][DqsRcvEnGrossDelay] delay of any DIMM minus the F2x[1,
- // 0]9C_x[3:0][2B:10][DqsRcvEnGrossDelay] delay of any other DIMM.
-
- Cgdd = MemNGetOptimalCGDDNb (NBPtr, AccessRcvEnDly, AccessRcvEnDly);
- DCTPtr->Timings.Trdrd = (Cgdd / 2) + 3;
-
- // Transfer clk to reg definition, 2T is 00b, etc.
- DCTPtr->Timings.Trdrd -= 2;
- if (DCTPtr->Timings.Trdrd > 8) {
- DCTPtr->Timings.Trdrd = 8;
- }
-
- return DCTPtr->Timings.Trdrd;
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function gets the Twrwr value
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return Twrwr value
- */
-
-UINT8
-MemNGetTwrwrNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- DCT_STRUCT *DCTPtr;
- INT8 Cgdd;
-
- DCTPtr = NBPtr->DCTPtr;
-
- // Twrwr (in MEMCLKs) = CGDD / 2 + 3 clocks and programs F2x[1, 0]8C[Twrwr] with the
- // converted field value. BIOS rounds fractional values down.
- // On any given byte lane, the largest F2x[1, 0]9C_x[3:0][A, 7, 6, 0][2:1]:F2x[1, 0]9C_x[3:0][A, 7, 6,
- // 0]3[WrDatGrossDlyByte] delay of any DIMM minus the F2x[1, 0]9C_x[3:0][A, 7, 6, 0][2:1]:F2x[1,
- // 0]9C_x[3:0][A, 7, 6, 0]3[WrDatGrossDlyByte] delay of any other DIMM is equal to the Critical Gross
- // Delay Difference (CGDD) for Twrwr.
-
- Cgdd = MemNGetOptimalCGDDNb (NBPtr, AccessWrDatDly, AccessWrDatDly);
- DCTPtr->Timings.Twrwr = (Cgdd / 2) + 3;
- NBPtr->TechPtr->AdjustTwrwr (NBPtr->TechPtr);
-
- return DCTPtr->Timings.Twrwr;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function gets the Twrrd value. BIOS calculates Twrrd (in MEMCLKs) = CGDD / 2 - LD + 3 clocks and programs
- * F2x[1, 0]8C[Twrrd] with the converted field value. BIOS rounds fractional
- * values down.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return Value to be programmed to Twrrd field
- * pDCT->Timings.Twrrd updated
- */
-
-UINT8
-MemNGetTwrrdNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- INT8 Cgdd;
- INT8 Ld;
- INT8 Twrrd;
- DCT_STRUCT *DCTPtr;
-
- DCTPtr = NBPtr->DCTPtr;
-
- //
- // For DDR3, BIOS calculates the latency difference (Ld) as equal to read CAS latency minus write CAS
- // latency, in MEMCLKs (see F2x[1, 0]88[Tcl] and F2x[1, 0]84[Tcwl]) which can be a negative or positive
- // value.
- // For DDR2, LD is always one clock (For DDR2, Tcwl is always Tcl minus 1).
- //
- Ld = NBPtr->TechPtr->GetLD (NBPtr->TechPtr);
-
- // On any given byte lane, the largest WrDatGrossDlyByte delay of any DIMM
- // minus the DqsRcvEnGrossDelay delay of any other DIMM is
- // equal to the Critical Gross Delay Difference (CGDD) for Twrrd.
- Cgdd = MemNGetOptimalCGDDNb (NBPtr, AccessWrDatDly, AccessRcvEnDly);
- Twrrd = (Cgdd / 2) - Ld + 3;
- DCTPtr->Timings.Twrrd = (UINT8) ((Twrrd >= 0) ? Twrrd : 0);
- NBPtr->TechPtr->AdjustTwrrd (NBPtr->TechPtr);
-
- return DCTPtr->Timings.Twrrd;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function gets the TrwtTO value
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return pDCT->Timings.TrwtTO updated
- */
-
-UINT8
-MemNGetTrwtTONb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- INT8 Cgdd;
- INT8 Ld;
- INT8 TrwtTO;
- DCT_STRUCT *DCTPtr;
-
- DCTPtr = NBPtr->DCTPtr;
- //
- // For DDR3, BIOS calculates the latency difference (Ld) as equal to read CAS latency minus write CAS
- // latency, in MEMCLKs (see F2x[1, 0]88[Tcl] and F2x[1, 0]84[Tcwl]) which can be a negative or positive
- // value.
- // For DDR2, LD is always one clock (For DDR2, Tcwl is always Tcl minus 1).
- //
- Ld = NBPtr->TechPtr->GetLD (NBPtr->TechPtr);
-
- // On any byte lane, the largest DqsRcvEnGrossDelay delay of any DIMM minus
- // the WrDatGrossDlyByte delay of any other DIMM is equal to the Critical Gross
- // Delay Difference (CGDD) for TrwtTO.
- Cgdd = MemNGetOptimalCGDDNb (NBPtr, AccessRcvEnDly, AccessWrDatDly);
- TrwtTO = (Cgdd / 2) + Ld + 3;
- TrwtTO -= 2;
- DCTPtr->Timings.TrwtTO = (UINT8) ((TrwtTO > 1) ? TrwtTO : 1);
-
- return DCTPtr->Timings.TrwtTO;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function gets the TrwtWB value
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TrwtWB value
- */
-UINT8
-MemNGetTrwtWBNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- DCT_STRUCT *DCTPtr;
-
- DCTPtr = NBPtr->DCTPtr;
-
- // TrwtWB ensures read-to-write data-bus turnaround.
- // This value should be one more than the programmed TrwtTO.
- return DCTPtr->Timings.TrwtWB = DCTPtr->Timings.TrwtTO;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function converts MemClk frequency in MHz to MemClkFreq value
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Speed - MemClk frequency in MHz
- *
- * @return MemClkFreq value
- */
-UINT8
-MemNGetMemClkFreqIdNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT16 Speed
- )
-{
- return (UINT8) ((Speed < DDR800_FREQUENCY) ? ((Speed / 66) - 3) : (Speed / 133));
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function enables swapping interleaved region feature.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Base - Swap interleaved region base [47:27]
- * @param[in] Limit - Swap interleaved region limit [47:27]
- *
- */
-VOID
-MemNEnableSwapIntlvRgnNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 Base,
- IN UINT32 Limit
- )
-{
- UINT32 Size;
- UINT32 SizeOfAlign;
-
- // Swapped interleaving region must be below 16G
- if (Limit < (1 << (34 - 27))) {
- // Adjust Base and Size to meet :
- // 1. The size of the swapped region must be less than or equal to the alignment of F2x10C[IntLvRegionBase].
- // 2. Entire UMA region is swapped with interleaving region.
- Size = Limit - Base;
- SizeOfAlign = (UINT32) 1 << LibAmdBitScanForward (Base);
- while (SizeOfAlign <= Size) {
- // In case of SizeOfAlign <= Size, UmaBase -= 128MB, SizeOfIntlvrgn += 128MB.
- Base -= 1;
- Size += 1;
- SizeOfAlign = (UINT32) 1 << LibAmdBitScanForward (Base);
- }
- MemNSetBitFieldNb (NBPtr, BFIntLvRgnBaseAddr, Base);
- MemNSetBitFieldNb (NBPtr, BFIntLvRgnLmtAddr, (Limit - 1));
- MemNSetBitFieldNb (NBPtr, BFIntLvRgnSize, Size);
- MemNSetBitFieldNb (NBPtr, BFIntLvRgnSwapEn, 1);
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function converts MemClk frequency in MHz to MemClkFreq value
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Speed - MemClk frequency in MHz
- *
- * @return MemClkFreq value
- */
-UINT8
-MemNGetMemClkFreqIdClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT16 Speed
- )
-{
- return (UINT8) ((Speed > DDR400_FREQUENCY) ? ((Speed / 33) - 6) : ((Speed == DDR400_FREQUENCY) ? 2 : (Speed / 55)));
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function converts MemClk frequency in MHz to MemClkFreq value
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Speed - MemClk frequency in MHz
- *
- * @return MemClkFreq value
- */
-UINT8
-MemNGetMemClkFreqIdUnb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT16 Speed
- )
-{
- return (UINT8) ((Speed > DDR400_FREQUENCY) ? ((Speed / 33) - 6) : ((Speed == DDR400_FREQUENCY) ? 2 : (Speed / 55)));
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function converts MemClkFreq Id value to MemClk frequency in MHz
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] FreqId - FreqId from Register
- *
- * @return MemClk frequency in MHz
- */
-UINT16
-MemNGetMemClkFreqUnb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 FreqId
- )
-{
- UINT16 MemClkFreq;
- if (FreqId > 2) {
- MemClkFreq = (FreqId == 14) ? 667 : (300 + ((FreqId - 3) * 33) + (FreqId - 3) / 3);
- } else if (FreqId == 2) {
- MemClkFreq = 200;
- } else {
- MemClkFreq = 50 + (50 * FreqId);
- }
- return MemClkFreq;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function change MemClk frequency to the value that is specified by DCTPtr->Timings.Speed
- * for client NB.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNChangeFrequencyUnb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MEM_TECH_BLOCK *TechPtr;
- UINT8 Dct;
- UINT8 ChipSel;
- UINT32 Dummy;
- BOOLEAN FrequencyChangeSuccess;
-
- TechPtr = NBPtr->TechPtr;
-
- MemNBrdcstSetNb (NBPtr, BFDisDllShutdownSR, 1);
-
- //Program F2x[1,0]90[EnterSelfRefresh]=1.
- //Wait until the hardware resets F2x[1,0]90[EnterSelfRefresh]=0.
- MemNBrdcstSetNb (NBPtr, BFEnterSelfRef, 1);
- MemNPollBitFieldNb (NBPtr, BFEnterSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE);
-
- if (NBPtr->ChangeNbFrequency (NBPtr)) {
- // Reprogram Twr, Tcwl, and Tcl based on the new MEMCLK frequency.
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- MemNSwitchDCTNb (NBPtr, Dct);
- if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
- TechPtr->AutoCycTiming (TechPtr);
- if (!MemNPlatformSpecUnb (NBPtr)) {
- IDS_ERROR_TRAP;
- }
- }
- }
-
- // 1. Program PllLockTime to Family-specific value
- MemNBrdcstSetNb (NBPtr, BFPllLockTime, NBPtr->FreqChangeParam->PllLockTimeDefault);
-
- // 2. Program D18F2x[1,0]94[MemClkFreqVal] = 0.
- MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 0);
-
- // 3. Program D18F2x[1,0]94[MemClkFreq] to the desired DRAM frequency.
- MemNBrdcstSetNb (NBPtr, BFMemClkFreq, NBPtr->GetMemClkFreqId (NBPtr, NBPtr->DCTPtr->Timings.Speed));
-
- // 4. Program D18F2x[1,0]F4_x30[DbeGskFifoNumerator] and D18F2x[1,0]F4_x31[DbeGskFifoDenominator].
- // 5. Program D18F2x[1,0]F4_x32[DataTxFifoSchedDlyNegSlot1, DataTxFifoSchedDlySlot1,
- // DataTxFifoSchedDlyNegSlot0, DataTxFifoSchedDlySlot0]. See 2.10.3.2.2.1 [DCT Transmit Fifo Schedule
- // Delay Programming].
- // 6. D18F2x[1,0]78[RdPtrInit] = IF (D18F2x[1,0]94[MemClkFreq] >= 667 MHz) THEN 7 ELSE 8 ENDIF (Llano)
- // THEN 2 ELSE 3 ENDIF (Ontario)
- NBPtr->ProgramNbPsDependentRegs (NBPtr);
-
- IDS_OPTION_HOOK (IDS_BEFORE_MEM_FREQ_CHG, NBPtr, &(NBPtr->MemPtr->StdHeader));
- // 7. Program D18F2x[1,0]94[MemClkFreqVal] = 1.
- MemNBrdcstSetNb (NBPtr, BFMemClkFreqVal, 1);
- MemNPollBitFieldNb (NBPtr, BFFreqChgInProg, 0, PCI_ACCESS_TIMEOUT, TRUE);
- NBPtr->FamilySpecificHook[AfterMemClkFreqVal] (NBPtr, &Dct);
-
- // 8. IF (D18F2x[1,0]9C_x0D0F_E00A[CsrPhySrPllPdMode]==0) THEN program
- // D18F2x[1,0]9C_x0D0F_E006[PllLockTime] = 0Fh.
- // (CsrPhySrPllPdMode is kept 0 before training)
- MemNBrdcstSetNb (NBPtr, BFPllLockTime, 0x000F);
-
- FrequencyChangeSuccess = TRUE;
- } else {
- // If NB frequency cannot be updated, use the current speed as the target speed
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- MemNSwitchDCTNb (NBPtr, Dct);
- NBPtr->DCTPtr->Timings.Speed = NBPtr->TechPtr->PrevSpeed;
- NBPtr->DCTPtr->Timings.TargetSpeed = NBPtr->TechPtr->PrevSpeed;
- }
- FrequencyChangeSuccess = FALSE;
- }
-
- //Program F2x[1,0]90[ExitSelfRef]=1 for both DCTs.
- //Wait until the hardware resets F2x[1, 0]90[ExitSelfRef]=0.
- MemNBrdcstSetNb (NBPtr, BFExitSelfRef, 1);
- MemNPollBitFieldNb (NBPtr, BFExitSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE);
- MemNBrdcstSetNb (NBPtr, BFDisDllShutdownSR, 0);
-
- if (FrequencyChangeSuccess) {
- NBPtr->FamilySpecificHook[AfterMemClkFreqChg] (NBPtr, NULL);
-
- // Perform Phy Fence training and Phy comp init after frequency change
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- MemNSwitchDCTNb (NBPtr, Dct);
- if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
- IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct);
-
- // Phy fence programming
- AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader));
- NBPtr->PhyFenceTraining (NBPtr);
-
- // Phy compensation initialization
- AGESA_TESTPOINT (TPProcMemPhyCompensation, &(NBPtr->MemPtr->StdHeader));
- NBPtr->MemNInitPhyComp (NBPtr);
- MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_SLEWRATE, ALL_DIMMS);
- }
- }
-
- //======================================================================
- // Calculate and program DRAM Timings at new frequency
- //======================================================================
- //
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct);
- MemNSwitchDCTNb (NBPtr, Dct);
- if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
- for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) {
- if (MemNGetMCTSysAddrNb (NBPtr, ChipSel, &Dummy)) {
- // if chip select present
- if (!(TechPtr->TechnologySpecificHook[LrdimmSendAllMRCmds] (TechPtr, &ChipSel))) {
- TechPtr->SendAllMRCmds (TechPtr, ChipSel);
- }
- }
- }
- // Wait 512 clocks for DLL-relock
- MemNWaitXMemClksNb (NBPtr, 512);
- }
- }
- }
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function calculates and programs NB P-state dependent registers
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNProgramNbPstateDependentRegistersUnb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 RdPtrInit;
- UINT8 Dct;
-
- RdPtrInit = (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) ? 6 : 5;
- MemNBrdcstSetNb (NBPtr, BFRdPtrInit, RdPtrInit);
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\tRdPtr: %d\n", RdPtrInit);
-
- switch (RdPtrInit) {
- case 4:
- if (MemNGetBitFieldNb (NBPtr, BFNbPsSel) == 0) {
- MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 2);
- } else {
- MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 1);
- }
- break;
- case 5:
- MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 1);
- break;
- case 6:
- MemNBrdcstSetNb (NBPtr, BFDataTxFifoWrDly, 0);
- break;
- default:
- ASSERT (FALSE);
- }
-
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- MemNSwitchDCTNb (NBPtr, Dct);
- if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
- // Set ProcOdtAdv
- if (NBPtr->DCTPtr->Timings.Speed <= DDR1333_FREQUENCY) {
- MemNSetBitFieldNb (NBPtr, BFProcOdtAdv, 0);
- } else {
- MemNSetBitFieldNb (NBPtr, BFProcOdtAdv, 0x4000);
- }
- }
- }
-
- NBPtr->FamilySpecificHook[OverrideDataTxFifoWrDly] (NBPtr, NBPtr);
- IDS_OPTION_HOOK (IDS_NBPS_REG_OVERRIDE, NBPtr, &NBPtr->MemPtr->StdHeader);
-}
-
-/* -----------------------------------------------------------------------------*/
-CONST UINT8 PllDivTab[] = {0, 0, 0, 2, 3, 3, 2, 3};
-CONST UINT8 PllMultTab[] = {0, 0, 0, 16, 32, 40, 32, 56};
-
-/**
- *
- * This function calculates and programs NB P-state dependent registers
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNProgramNbPstateDependentRegistersClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 i;
- UINT8 Dct;
- UINT8 NclkFid;
- UINT16 MemClkDid;
- UINT8 PllMult;
- UINT8 NclkDiv;
- UINT8 RdPtrInitMin;
- UINT8 RdPtrInit;
- UINT32 NclkPeriod;
- UINT32 MemClkPeriod;
- INT32 PartialSum2x;
- INT32 PartialSumSlotI2x;
- INT32 RdPtrInitRmdr2x;
- INT32 TDataProp;
- UINT8 NbPstate;
- UINT8 SlowMode;
-
- NclkFid = (UINT8) (MemNGetBitFieldNb (NBPtr, BFMainPllOpFreqId) + 0x10); // NclkFid is in 100MHz
-
- MemClkDid = PllDivTab[NBPtr->DCTPtr->Timings.Speed / 133];
- NBPtr->FamilySpecificHook[OverridePllDiv] (NBPtr, &MemClkDid);
- PllMult = PllMultTab[NBPtr->DCTPtr->Timings.Speed / 133];
- NBPtr->FamilySpecificHook[OverridePllMult] (NBPtr, &PllMult);
-
- if (NBPtr->NbFreqChgState == 2) {
- MemNSetBitFieldNb (NBPtr, BFNbPsCsrAccSel, 1);
- MemNSetBitFieldNb (NBPtr, BFNbPsDbgEn, 1);
- NclkDiv = (UINT8) MemNGetBitFieldNb (NBPtr, BFNbPs1NclkDiv);
- // Divisors less than 8 are undefined. Maybe the CPU does not support NB P-states.
- if (NclkDiv < 8) {
- // Set a dummy divisor to prevent divide by zero exception below.
- NclkDiv = 8;
- }
- NbPstate = 1;
- } else {
- NclkDiv = (UINT8) MemNGetBitFieldNb (NBPtr, BFNbPs0NclkDiv);
- NbPstate = 0;
- }
- NclkPeriod = (2500 * NclkDiv) / NclkFid; // (1,000,000 * 0.25 * NclkDiv) / (NclkFid * 100MHz) = ps
- MemClkPeriod = 1000000 / NBPtr->DCTPtr->Timings.Speed;
- NBPtr->NBClkFreq = ((UINT32) NclkFid * 400) / NclkDiv;
-
- IDS_HDT_CONSOLE (MEM_FLOW, "\n\tNB P%d Freq: %dMHz\n", NbPstate, NBPtr->NBClkFreq);
- IDS_HDT_CONSOLE (MEM_FLOW, "\tMemClk Freq: %dMHz\n", NBPtr->DCTPtr->Timings.Speed);
- // D18F2x[1,0]78[RdPtrInit] = IF (D18F2x[1,0]94[MemClkFreq] >= 667 MHz) THEN 7 ELSE 8 ENDIF (Llano)
- // THEN 2 ELSE 3 ENDIF (Ontario)
- RdPtrInit = RdPtrInitMin = (NBPtr->DCTPtr->Timings.Speed >= DDR1333_FREQUENCY) ? NBPtr->FreqChangeParam->RdPtrInit667orHigher : NBPtr->FreqChangeParam->RdPtrInitLower667;
- MemNBrdcstSetNb (NBPtr, BFRdPtrInit, RdPtrInit);
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\tRdPtr: %d\n", RdPtrInit);
-
- // Program D18F2x[1,0]F4_x30[DbeGskFifoNumerator] and D18F2x[1,0]F4_x31[DbeGskFifoDenominator].
- MemNBrdcstSetNb (NBPtr, BFDbeGskFifoNumerator, NclkFid * MemClkDid * 16);
- MemNBrdcstSetNb (NBPtr, BFDbeGskFifoDenominator, PllMult * NclkDiv);
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\tDbeGskFifoNumerator: %d\n", NclkFid * MemClkDid * 16);
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\tDbeGskFifoDenominator: %d\n", PllMult * NclkDiv);
-
- // Program D18F2x[1,0]F4_x32[DataTxFifoSchedDlyNegSlot1, DataTxFifoSchedDlySlot1,
- // DataTxFifoSchedDlyNegSlot0, DataTxFifoSchedDlySlot0].
- // PartialSum = ((7 * NclkPeriod) + (1.5 * MemClkPeriod) + 520ps)*MemClkFrequency - tCWL -
- // CmdSetup - PtrSeparation - 1. (Llano)
- // PartialSum = ((5 * NclkPeriod) + MemClkPeriod) + 520ps)*MemClkFrequency - tCWL -
- // CmdSetup - PtrSeparation - 1. (Ontario)
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- MemNSwitchDCTNb (NBPtr, Dct);
- if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
- PartialSum2x = NBPtr->FreqChangeParam->NclkPeriodMul2x * NclkPeriod;
- PartialSum2x += NBPtr->FreqChangeParam->MemClkPeriodMul2x * MemClkPeriod;
- PartialSum2x += 520 * 2;
-
- // PtrSeparation = ((16 + RdPtrInitMin - D18F2x[1,0]78[RdPtrInit]) MOD 16)/2 + RdPtrInitRmdr
- // If (D18F2x[1,0]94[MemClkFreq] >= 800 MHz)
- // then RdPtrInitRmdr = (((4.5 * MemClkPeriod) - 990ps) MOD MemClkPeriod)/MemClkPeriod
- // else RdPtrInitRmdr = (((4.5 * MemClkPeriod) - 1466ps) MOD MemClkPeriod)/MemClkPeriod
- TDataProp = (NBPtr->DCTPtr->Timings.Speed >= DDR1600_FREQUENCY) ?
- NBPtr->FreqChangeParam->TDataProp800orHigher : NBPtr->FreqChangeParam->TDataPropLower800;
- RdPtrInitRmdr2x = ((NBPtr->FreqChangeParam->SyncTimeMul4x * MemClkPeriod) / 2) - 2 * (TDataProp + 520);
- RdPtrInitRmdr2x %= MemClkPeriod;
- PartialSum2x -= ((16 + RdPtrInitMin - RdPtrInit) % 16) * MemClkPeriod + RdPtrInitRmdr2x;
-
- // Convert PartialSum2x to PCLK
- PartialSum2x = (PartialSum2x + MemClkPeriod - 1) / MemClkPeriod; // round-up here
- PartialSum2x -= 2 * (MemNGetBitFieldNb (NBPtr, BFTcwl) + 5);
- if ((MemNGetBitFieldNb (NBPtr, BFAddrTmgControl) & 0x0202020) == 0) {
- PartialSum2x -= 1;
- } else {
- PartialSum2x -= 2;
- }
- PartialSum2x -= 2;
-
- // If PartialSumSlotN is positive:
- // DataTxFifoSchedDlySlotN=CEIL(PartialSumSlotN).
- // DataTxFifoSchedDlyNegSlotN=0.
- // Else if PartialSumSlotN is negative:
- // DataTxFifoSchedDlySlotN=ABS(CEIL(PartialSumSlotN*MemClkPeriod/NclkPeriod)).
- // DataTxFifoSchedDlyNegSlotN=1.
- for (i = 0; i < 2; i++) {
- PartialSumSlotI2x = PartialSum2x;
- SlowMode = (UINT8) MemNGetBitFieldNb (NBPtr, BFSlowAccessMode);
- if ((i == 0) && (SlowMode == 0)) {
- PartialSumSlotI2x += 2;
- }
- if (NBPtr->IsSupported[SchedDlySlot1Extra] && (i == 1) && (SlowMode != 0)) {
- PartialSumSlotI2x -= 2;
- }
- if (PartialSumSlotI2x > 0) {
- MemNSetBitFieldNb (NBPtr, BFDataTxFifoSchedDlyNegSlot0 + i, 0);
- MemNSetBitFieldNb (NBPtr, BFDataTxFifoSchedDlySlot0 + i, (PartialSumSlotI2x + 1) / 2);
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\tDataTxFifoSchedDlySlot%d: %d\n", i, (PartialSumSlotI2x + 1) / 2);
- } else {
- MemNSetBitFieldNb (NBPtr, BFDataTxFifoSchedDlyNegSlot0 + i, 1);
- PartialSumSlotI2x = ((-PartialSumSlotI2x) * MemClkPeriod) / (2 * NclkPeriod);
- MemNSetBitFieldNb (NBPtr, BFDataTxFifoSchedDlySlot0 + i, PartialSumSlotI2x);
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\tDataTxFifoSchedDlySlot%d: -%d\n", i, PartialSumSlotI2x);
- }
- }
-
- // Set ProcOdtAdv
- if (NBPtr->DCTPtr->Timings.Speed <= DDR1333_FREQUENCY) {
- MemNSetBitFieldNb (NBPtr, BFProcOdtAdv, 0);
- } else {
- MemNSetBitFieldNb (NBPtr, BFProcOdtAdv, 0x4000);
- }
- }
- }
-
- MemFInitTableDrive (NBPtr, MTAfterNbPstateChange);
- if (NBPtr->NbFreqChgState == 2) {
- MemNSetBitFieldNb (NBPtr, BFNbPsDbgEn, 0);
- MemNSetBitFieldNb (NBPtr, BFNbPsCsrAccSel, 0);
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function gets the total of sync components for Max Read Latency calculation
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return Total in ps
- */
-
-UINT32
-MemNTotalSyncComponentsClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT32 P;
- UINT32 T;
- UINT8 RdPtrInitMin;
- UINT8 RdPtrInit;
- UINT32 AddrTmgCtl;
- UINT8 DbeGskMemClkAlignMode;
- UINT32 MemClkPeriod;
-
- // P = P + ((16 + RdPtrInitMin - D18F2x[1,0]78[RdPtrInit]) MOD 16)
- RdPtrInitMin = (NBPtr->DCTPtr->Timings.Speed >= DDR1333_FREQUENCY) ? NBPtr->FreqChangeParam->RdPtrInit667orHigher : NBPtr->FreqChangeParam->RdPtrInitLower667;
- RdPtrInit = (UINT8) MemNGetBitFieldNb (NBPtr, BFRdPtrInit);
- P = (16 + RdPtrInitMin - RdPtrInit) % 16;
-
- // IF (AddrCmdSetup != CkeSetup) THEN P = P + 1
- AddrTmgCtl = MemNGetBitFieldNb (NBPtr, BFAddrTmgControl);
- if (((AddrTmgCtl >> 16) & 0x20) != (AddrTmgCtl & 0x20)) {
- P += 1;
- }
-
- // IF (DbeGskMemClkAlignMode==01b || (DbeGskMemClkAlignMode==00b && !(AddrCmdSetup==CsOdtSetup==CkeSetup)))
- // THEN P = P + 1
- DbeGskMemClkAlignMode = (UINT8) MemNGetBitFieldNb (NBPtr, BFDbeGskMemClkAlignMode);
- if ((DbeGskMemClkAlignMode == 1) || ((DbeGskMemClkAlignMode == 0) &&
- !((((AddrTmgCtl >> 16) & 0x20) == (AddrTmgCtl & 0x20)) && (((AddrTmgCtl >> 8) & 0x20) == (AddrTmgCtl & 0x20))))) {
- P += 1;
- }
-
- // IF (SlowAccessMode==1) THEN P = P + 2
- if (MemNGetBitFieldNb (NBPtr, BFSlowAccessMode) == 1) {
- P += 2;
- }
-
- // P = P + 2
- P += 2;
- T = 0;
-
- // If (AddrCmdSetup==0 && CsOdtSetup==0 && CkeSetup==0)
- // then P = P + 1
- // else P = P + 2
- if ((AddrTmgCtl & 0x0202020) == 0) {
- P += 1;
- } else {
- P += 2;
- }
-
- // P = P + (2 * (D18F2x[1,0]88[Tcl] clocks - 1))
- P += 2 * (NBPtr->DCTPtr->Timings.CasL - 1);
-
- // If (DisCutThroughMode==0)
- // then P = P + 3
- // else P = P + 7
- if (MemNGetBitFieldNb (NBPtr, BFDisCutThroughMode) == 0) {
- P += 3;
- } else {
- P += 7;
- }
-
- MemClkPeriod = 1000000 / NBPtr->DCTPtr->Timings.Speed;
- return (((P * MemClkPeriod + 1) / 2) + T);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function sets up phy power saving for client NB
- *
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-VOID
-MemNPhyPowerSavingClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- // 4. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]13[DllDisEarlyU] = 1b.
- // 5. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]13[DllDisEarlyL] = 1b.
- // 6. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]13[7:4] = 1010b.
- MemNSetBitFieldNb (NBPtr, BFPhy0x0D0F0F13Bit0to7, 0xA3);
- // 7. Program D18F2x[1,0]9C_x0D0F_812F[7, 5, 0] = {1b, 1b, 1b} to disable unused PAR and A[17:16] pins.
- MemNSetBitFieldNb (NBPtr, BFAddrCmdTri, MemNGetBitFieldNb (NBPtr, BFAddrCmdTri) | 0xA1);
- // 8. Program D18F2x[1,0]9C_x0D0F_C000[LowPowerDrvStrengthEn] = 1.
- if (!NBPtr->FamilySpecificHook[DisLowPwrDrvStr] (NBPtr, NULL)) {
- MemNSetBitFieldNb (NBPtr, BFLowPowerDrvStrengthEn, 0x100);
- }
- // 9. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]10[EnRxPadStandby]= IF (D18F2x[1,0]94[MemClkFreq] <=
- // 800 MHz) THEN 1 ELSE 0 ENDIF.
- MemNSetBitFieldNb (NBPtr, BFEnRxPadStandby, (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) ? 0x1000 : 0);
- // 10. Program D18F2x[1,0]9C_x0000_000D as follows:
- // TxMaxDurDllNoLock/RxMaxDurDllNoLock = 7h.
- MemNSetBitFieldNb (NBPtr, BFRxMaxDurDllNoLock, 7);
- MemNSetBitFieldNb (NBPtr, BFTxMaxDurDllNoLock, 7);
- // TxCPUpdPeriod/RxCPUpdPeriod = 011b.
- MemNSetBitFieldNb (NBPtr, BFTxCPUpdPeriod, 3);
- MemNSetBitFieldNb (NBPtr, BFRxCPUpdPeriod, 3);
- // TxDLLWakeupTime/RxDLLWakeupTime = 11b.
- MemNSetBitFieldNb (NBPtr, BFTxDLLWakeupTime, 3);
- MemNSetBitFieldNb (NBPtr, BFRxDLLWakeupTime, 3);
-
- IDS_OPTION_HOOK (IDS_PHY_DLL_STANDBY_CTRL, NBPtr, &NBPtr->MemPtr->StdHeader);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function overrides the ASR and SRT value in MRS command
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-VOID
-MemNSetASRSRTNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT32 MrsAddress;
- UINT8 Dimm;
- UINT8 *SpdBufferPtr;
-
- // Look for MR2
- if (NBPtr->GetBitField (NBPtr, BFMrsBank) == 2) {
- MrsAddress = NBPtr->GetBitField (NBPtr, BFMrsAddress);
- // Clear A6(ASR) and A7(SRT)
- MrsAddress &= (UINT32) ~0xC0;
- Dimm = (UINT8) (NBPtr->GetBitField (NBPtr, BFMrsChipSel) >> 1);
- // Make sure we access SPD of the second logical dimm of QR dimm correctly
- if ((Dimm >= 2) && ((NBPtr->ChannelPtr->DimmQrPresent & (UINT8) (1 << Dimm)) != 0)) {
- Dimm -= 2;
- }
- if (NBPtr->TechPtr->GetDimmSpdBuffer (NBPtr->TechPtr, &SpdBufferPtr, Dimm)) {
- // Bit 2 is ASR
- if (SpdBufferPtr[THERMAL_OPT] & 0x4) {
- // when ASR is 1, set SRT to 0
- MrsAddress |= 0x40;
- } else {
- // Set SRT based on bit on of thermal byte
- MrsAddress |= ((SpdBufferPtr[THERMAL_OPT] & 1) << 7);
- }
- NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
- }
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function changes NB frequency as below:
- * NBP0-DDR800 -> NBP0-DDR1066 -> ... -> NBP0-DDRTarget -> NBP1-DDRTarget -> NBP0-DDRTarget
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-BOOLEAN
-MemNChangeNbFrequencyNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- BOOLEAN Status;
-
- Status = FALSE;
-
- // State machine to change NB frequency and NB Pstate
- switch (NBPtr->NbFreqChgState) {
- case 0:
- // Starting up by not changing NB P state, but only updating NB frequency based on current MemClk frequency
- Status = NBPtr->ChangeNbFrequencyWrap (NBPtr, 0);
- if (NBPtr->DCTPtr->Timings.Speed == NBPtr->DCTPtr->Timings.TargetSpeed) {
- // When MemClk has been ramped up to its max, transition to next state, which changes NBPstate to P1
- NBPtr->NbFreqChgState = 1;
- IDS_OPTION_HOOK (IDS_NB_PSTATE_DIDVID, NBPtr, &(NBPtr->MemPtr->StdHeader));
- }
- break;
-
- case 1:
- // Clear ForceCasToSlot0 after MaxRdLatency training is completed for NB-P0
- MemNBrdcstSetNb (NBPtr, BFForceCasToSlot0, 0);
-
- // Next state would be to change NBPstate back to P0
- NBPtr->NbFreqChgState = 2;
-
- // Update NB freq dependent registers
- NBPtr->ProgramNbPsDependentRegs (NBPtr);
-
- // Change NB P-State to NBP1 for MaxRdLat training
- if (NBPtr->ChangeNbFrequencyWrap (NBPtr, 1)) {
- // Enable cut through mode for NB P1
- MemNBrdcstSetNb (NBPtr, BFDisCutThroughMode, 0);
-
- // Return TRUE to repeat MaxRdLat training
- Status = TRUE;
-
- } else {
- // If transition to NB-P1 fails, transition to exit state machine
- NBPtr->NbFreqChgState = 3;
- }
- break;
-
- case 2:
- // Clear ForceCasToSlot0 after MaxRdLatency training is completed for NB-P1
- MemNBrdcstSetNb (NBPtr, BFForceCasToSlot0, 0);
-
- // Change NB P-State back to NBP0
- Status = NBPtr->ChangeNbFrequencyWrap (NBPtr, 0);
- ASSERT (Status);
-
- // Return FALSE to get out of MaxRdLat training loop
- Status = FALSE;
-
- // Exit state machine
- NBPtr->NbFreqChgState = 3;
- break;
-
- default:
- break;
- }
-
- return Status;
-}
-
-/*-----------------------------------------------------------------------------
- *
- *
- * This function programs registers before phy fence training for CNB
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] OptParam - Optional parameter
- *
- * @return TRUE
- * ----------------------------------------------------------------------------
- */
-BOOLEAN
-MemNBeforePhyFenceTrainingClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT VOID *OptParam
- )
-{
- IDS_HDT_CONSOLE (MEM_FLOW, "\tMemClkAlign=0\n");
- MemNBrdcstSetNb (NBPtr, BFDbeGskMemClkAlignMode, 0);
-
- IDS_HDT_CONSOLE (MEM_FLOW, "\tEnDramInit = 1 for both DCTs\n");
- MemNBrdcstSetNb (NBPtr, BFEnDramInit, 1);
-
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function changes NB frequency foras below:
- * NBP0-DDR800 -> NBP0-DDR1066 -> ... -> NBP0-DDRTarget -> NBP1-DDRTarget -> NBP2-DDRTarget -> NBP3-DDRTarget -> NBP0-DDRTarget
- *
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-BOOLEAN
-MemNChangeNbFrequencyUnb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- BOOLEAN Status;
-
- Status = FALSE;
-
- // State machine to change NB frequency and NB Pstate
- switch (NBPtr->NbFreqChgState) {
- case 0:
- // Starting up by not changing NB P state, but only updating NB frequency based on current MemClk frequency
- Status = NBPtr->ChangeNbFrequencyWrap (NBPtr, 0);
- if (NBPtr->DCTPtr->Timings.Speed == NBPtr->DCTPtr->Timings.TargetSpeed) {
- // When MemClk has been ramped up to its max, transition to next state, which changes NBPstate to P1
- NBPtr->NbFreqChgState = 1;
- IDS_OPTION_HOOK (IDS_NB_PSTATE_DIDVID, NBPtr, &(NBPtr->MemPtr->StdHeader));
- }
- break;
-
- case 1:
- case 2:
- case 3:
- // Change NB P-State to NBP1 for MaxRdLat training
- if (NBPtr->ChangeNbFrequencyWrap (NBPtr, NBPtr->NbFreqChgState)) {
- NBPtr->ProgramNbPsDependentRegs (NBPtr);
-
- // Next state is to try all NBPstates
- NBPtr->NbFreqChgState++;
-
- // Return TRUE to repeat MaxRdLat training
- Status = TRUE;
- } else {
- // If transition to any NBPs fails, transition to exit state machine
- NBPtr->NbFreqChgState = 4;
- }
- break;
-
- case 4:
- // Change NB P-State back to NBP0
- Status = NBPtr->ChangeNbFrequencyWrap (NBPtr, 0);
- ASSERT (Status);
-
- // Return FALSE to get out of MaxRdLat training loop
- Status = FALSE;
-
- // Exit state machine
- NBPtr->NbFreqChgState = 5;
- break;
-
- default:
- break;
- }
-
- return Status;
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function gets "Dram Term" value from data structure
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] ChipSel - Targeted chipsel
- *
- * @return Dram Term value
- */
-UINT8
-MemNGetDramTermNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 ChipSel
- )
-{
- UINT8 DramTerm;
-
- if ((NBPtr->ChannelPtr->DimmQrPresent & ((UINT16) (1 << (ChipSel >> 1)))) != 0) {
- DramTerm = NBPtr->PsPtr->QR_DramTerm;
- } else {
- DramTerm = NBPtr->PsPtr->DramTerm;
- }
-
- return DramTerm;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function gets "Dynamic Dram Term" value from data structure
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] ChipSel - Targeted chipsel
- *
- * @return Dynamic Dram Term value
- */
-UINT8
-MemNGetDynDramTermNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 ChipSel
- )
-{
- return (NBPtr->PsPtr->DynamicDramTerm);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function returns MR0[CL] value
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return MR0[CL] value
- */
-UINT32
-MemNGetMR0CLNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 Tcl;
- UINT32 Value32;
-
- Tcl = (UINT8) MemNGetBitFieldNb (NBPtr, BFTcl);
- Value32 = (UINT32) ((Tcl < 8) ? (Tcl << 4) : (((Tcl - 8) << 4) | 4));
-
- return Value32;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function returns MR0[WR] value
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return MR0[WR] value
- */
-UINT32
-MemNGetMR0WRNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT32 Value32;
-
- Value32 = MemNGetBitFieldNb (NBPtr, BFTwrDDR3) << 9;
-
- return Value32;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function returns MR2[CWL] value
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return MR0[CWL] value
- */
-UINT32
-MemNGetMR2CWLNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT32 Value32;
-
- Value32 = MemNGetBitFieldNb (NBPtr, BFTcwl) << 3;
-
- return Value32;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function sets Txp and Txpdll
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return none
- */
-VOID
-MemNSetTxpNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- CONST UINT8 Txp[] = {0xFF, 0xFF, 3, 3, 4, 4, 5, 6, 7};
- CONST UINT8 Txpdll[] = {0xFF, 0xFF, 0xA, 0xA, 0xD, 0x10, 0x14, 0x17, 0x1A};
- UINT8 i;
- UINT8 TxpVal;
- UINT8 TxpdllVal;
- UINT16 Speed;
-
- Speed = NBPtr->DCTPtr->Timings.Speed;
- i = (UINT8) ((Speed < DDR800_FREQUENCY) ? ((Speed / 66) - 3) : (Speed / 133));
- ASSERT (i < sizeof (Txp));
- ASSERT (i < sizeof (Txpdll));
-
- TxpdllVal = Txpdll[i];
-
- if ((NBPtr->MCTPtr->Status[SbLrdimms] || NBPtr->MCTPtr->Status[SbRegistered]) &&
- ((NBPtr->DCTPtr->Timings.Speed == DDR667_FREQUENCY) || (NBPtr->DCTPtr->Timings.Speed == DDR800_FREQUENCY)) &&
- (NBPtr->RefPtr->DDR3Voltage == VOLT1_25)) {
- TxpVal = 4;
- } else {
- TxpVal = Txp[i];
- }
-
- if (TxpVal != 0xFF) {
- MemNSetBitFieldNb (NBPtr, BFTxp, TxpVal);
- }
- if (TxpdllVal != 0xFF) {
- NBPtr->FamilySpecificHook[AdjustTxpdll] (NBPtr, &TxpdllVal);
- MemNSetBitFieldNb (NBPtr, BFTxpdll, TxpdllVal);
- }
-}
-
-/*-----------------------------------------------------------------------------
- *
- *
- * This function adjust value of Txpdll to encoded value.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] OptParam - Optional parameter
- *
- * @return TRUE
- * ----------------------------------------------------------------------------
- */
-BOOLEAN
-MemNAdjustTxpdllClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT VOID *OptParam
- )
-{
- *(UINT8 *) OptParam -= 10;
- return TRUE;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/mnfeat.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/mnfeat.c
deleted file mode 100644
index 0779531..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/mnfeat.c
+++ /dev/null
@@ -1,1268 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnfeat.c
- *
- * Common Northbridge features
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB)
- * @e \$Revision: 38442 $ @e \$Date: 2010-09-24 06:39:57 +0800 (Fri, 24 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mu.h"
-#include "PlatformMemoryConfiguration.h"
-#include "merrhdl.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_MNFEAT_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define MAX_CL_CONT_READ 32
-#define MAX_CL_CONT_WRITE 32
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-VOID
-STATIC
-MemNContWritePatternNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 Address,
- IN UINT8 Pattern[],
- IN UINT16 ClCount
- );
-
-VOID
-STATIC
-MemNContReadPatternNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Buffer[],
- IN UINT32 Address,
- IN UINT16 ClCount
- );
-
-VOID
-STATIC
-MemNGenHwRcvEnReadsNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 Address
- );
-
-UINT16
-STATIC
-MemNCompareTestPatternClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Buffer[],
- IN UINT8 Pattern[],
- IN UINT16 ByteCount
- );
-
-UINT16
-STATIC
-MemNInsDlyCompareTestPatternClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Buffer[],
- IN UINT8 Pattern[],
- IN UINT16 ByteCount
- );
-
-VOID
-STATIC
-MemNContWritePatternClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 Address,
- IN UINT8 Pattern[],
- IN UINT16 ClCount
- );
-
-VOID
-STATIC
-MemNContReadPatternClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Buffer[],
- IN UINT32 Address,
- IN UINT16 ClCount
- );
-
-VOID
-STATIC
-MemNGenHwRcvEnReadsClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 Address
- );
-
-BOOLEAN
-STATIC
-MemNBeforeMemClrClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN VOID *UnUsed
- );
-
-VOID
-STATIC
-MemNGenHwRcvEnReadsUnb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 Address
- );
-
-VOID
-STATIC
-MemNRrwActivateCmd (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 ChipSelect,
- IN UINT8 Bank,
- IN UINT32 RowAddress
- );
-
-VOID
-STATIC
-MemNRrwPrechargeCmd (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 ChipSelect,
- IN UINT8 Bank
- );
-
-VOID
-STATIC
-MemNContReadPatternUnb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Buffer[],
- IN UINT32 Address,
- IN UINT16 ClCount
- );
-
-VOID
-STATIC
-MemNContWritePatternUnb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 Address,
- IN UINT8 Pattern[],
- IN UINT16 ClCount
- );
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function assigns read/write function pointers to CPG read/write modules.
- *
- * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-VOID
-MemNInitCPGNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- NBPtr->WritePattern = MemNContWritePatternNb;
- NBPtr->ReadPattern = MemNContReadPatternNb;
- NBPtr->GenHwRcvEnReads = MemNGenHwRcvEnReadsNb;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initializes member functions of HW Rx En Training.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNInitDqsTrainRcvrEnHwNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- NBPtr->MemNPrepareRcvrEnDlySeed = MemNPrepareRcvrEnDlySeedNb;
-}
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function disables member functions of Hw Rx En Training.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNDisableDqsTrainRcvrEnHwNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- NBPtr->MemNPrepareRcvrEnDlySeed = (VOID (*) (MEM_NB_BLOCK *)) memDefRet;
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function writes 9 or 18 cache lines continuously using GH CPG engine
- *
- * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Pattern - Array of bytes that will be written to DRAM
- * @param[in] Address - System Address [47:16]
- * @param[in] ClCount - Number of cache lines
- *
- */
-VOID
-STATIC
-MemNContWritePatternNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 Address,
- IN UINT8 Pattern[],
- IN UINT16 ClCount
- )
-{
- UINT16 ClDiff;
- if (ClCount > MAX_CL_CONT_WRITE) {
- ClDiff = ClCount - MAX_CL_CONT_WRITE;
- ClCount = MAX_CL_CONT_WRITE;
- } else {
- ClDiff = 0;
- }
-
- // Set F2x11C[MctWrLimit] to desired number of cachelines in the burst.
- MemNSetBitFieldNb (NBPtr, BFMctWrLimit, MAX_CL_CONT_WRITE - ClCount);
-
- // Issue the stream of writes. When F2x11C[MctWrLimit] is reached (or when F2x11C[FlushWr] is set
- // again), all the writes are written to DRAM.
- Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
- MemUWriteCachelines (Address, Pattern, ClCount);
-
- // Flush out prior writes by setting F2x11C[FlushWr].
- MemNSetBitFieldNb (NBPtr, BFFlushWr, 1);
- // Wait for F2x11C[FlushWr] to clear, indicating prior writes have been flushed.
- while (MemNGetBitFieldNb (NBPtr, BFFlushWr) != 0) {}
-
- // Set F2x11C[MctWrLimit] to 1Fh to disable write bursting.
- MemNSetBitFieldNb (NBPtr, BFMctWrLimit, 0x1F);
-
- if (ClDiff > 0) {
- MemNContWritePatternNb (NBPtr, Address + (MAX_CL_CONT_WRITE * 64), Pattern + (MAX_CL_CONT_WRITE * 64), ClDiff);
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function reads 9 or 18 cache lines continuously using GH CPG engine
- *
- * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] Buffer - Array of bytes to be filled with data read from DRAM
- * @param[in] Address - System Address [47:16]
- * @param[in] ClCount - Number of cache lines
- *
- */
-
-VOID
-STATIC
-MemNContReadPatternNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Buffer[],
- IN UINT32 Address,
- IN UINT16 ClCount
- )
-{
- BOOLEAN DisAutoRefresh;
- UINT16 ClDiff;
- if (ClCount > MAX_CL_CONT_READ) {
- ClDiff = ClCount - MAX_CL_CONT_READ;
- ClCount = MAX_CL_CONT_READ;
- } else {
- ClDiff = 0;
- }
-
- Address = MemUSetUpperFSbase (Address, NBPtr->MemPtr);
-
- // 1. BIOS ensures that the only accesses outstanding to the MCT are training reads.
- // 2. If F2x[1, 0]90[BurstLength32]=1, then BIOS ensures that the DCTs and DRAMs are configured for 64
- // byte bursts (8-beat burst length). This requires that BIOS issue MRS commands to the devices
- // to change to an 8-beat burst length and then to restore the desired burst length after training
- // is complete.
-
- if (MemNGetBitFieldNb (NBPtr, BFDisAutoRefresh) == 0) {
- DisAutoRefresh = FALSE;
- // 3. BIOS programs F2x[1, 0]90[ForceAutoPchg] = 0 and F2x[1, 0]8C[DisAutoRefresh] = 1.
- // 4. If necessary, BIOS programs F2x[1, 0]78[EarlyArbEn] = 1 at this time. See register description.
- MemNSetBitFieldNb (NBPtr, BFDisAutoRefresh, 1);
- // MemNSetBitFieldNb (NBPtr, BFForceAutoPchg, 0); // ForceAutoPchg is 0 by default.
- MemNSetBitFieldNb (NBPtr, BFZqcsInterval, 0);
- } else {
- DisAutoRefresh = TRUE;
- }
-
- MemNSetBitFieldNb (NBPtr, BFPrefCpuDis, 0);
-
- // 5. BIOS sets F2x11C[MctPrefReqLimit] to the number of training reads (Ntrain) it wishes to generate in the
- // training sequence.
- MemNSetBitFieldNb (NBPtr, BFMctPrefReqLimit, ClCount - 1);
-
- // 6. BIOS sets F2x11C[PrefDramTrainMode] bit.
- // 7. The act of setting F2x11C[PrefDramTrainMode] causes the MCT to flush out the prefetch stride predictor
- // table (removing any existing prefetch stride patterns).
- MemNSetBitFieldNb (NBPtr, BFPrefDramTrainMode, 1);
-
- // 8. BIOS issues an SFENCE (or other serializing instruction) to ensure that the prior write completes.
- // 9. For revision C and earlier processors, BIOS generates two training reads. For revision D processors BIOS
- // generates three training reads. Three are required to detect the stride with DCQ buddy enabled. These must
- // be to consecutive cache lines (i.e. 64 bytes apart) and must not cross a naturally aligned 4 Kbyte boundary.
- // 10. These reads set up a stride pattern which is detected by the prefetcher. The prefetcher then continues to
- // issue prefetches until F2x11C[MctPrefReqLimit] is reached, at which point the MCT clears
- // F2x11C[PrefDramTrainMode].
- MemUDummyCLRead (Address);
- MemUDummyCLRead (Address + 0x40);
- if (NBPtr->IsSupported[CheckDummyCLRead]) {
- MemUDummyCLRead (Address + 0x80);
- }
- // 11. BIOS issues the remaining (Ntrain - 2 for revisions C and earlier or Ntrain - 3 for revision D) reads after
- // checking that F2x11C[PrefDramTrainMode] is cleared. These reads must be to consecutive cache lines
- // (i.e., 64 bytes apart) and must not cross a naturally aligned 4KB boundary. These reads hit the prefetches
- // and read the data from the prefetch buffer.
- while (MemNGetBitFieldNb (NBPtr, BFPrefDramTrainMode) != 0) {}
- MemUReadCachelines (Buffer, Address, ClCount);
-
- // 14. BIOS restores the target values for F2x[1, 0]90[ForceAutoPchg], F2x[1, 0]8C[DisAutoRefresh] and
- // F2x[1, 0]90[BurstLength32].
- if (!DisAutoRefresh) {
- MemNSetBitFieldNb (NBPtr, BFDisAutoRefresh, 0);
- MemNSetBitFieldNb (NBPtr, BFZqcsInterval, 2);
- }
-
- if (ClDiff > 0) {
- MemNContReadPatternNb (NBPtr, Buffer + (MAX_CL_CONT_READ * 64), Address + (MAX_CL_CONT_READ * 64), ClDiff);
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function generates a continuous burst of reads during HW RcvEn training.
- *
- * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Address - System Address [47:16]
- *
- */
-VOID
-STATIC
-MemNGenHwRcvEnReadsNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 Address
- )
-{
- UINT8 TempBuffer[12 * 64];
- UINT8 BurstCount;
-
- for (BurstCount = 0; BurstCount < 10; BurstCount++) {
- NBPtr->ReadPattern (NBPtr, TempBuffer, Address, 12);
- NBPtr->FlushPattern (NBPtr, Address, 12);
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function writes cache lines continuously using TCB CPG engine
- *
- * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Pattern - Array of bytes that will be written to DRAM
- * @param[in] Address - System Address [47:16]
- * @param[in] ClCount - Number of cache lines
- *
- */
-VOID
-STATIC
-MemNContWritePatternClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 Address,
- IN UINT8 Pattern[],
- IN UINT16 ClCount
- )
-{
- UINT32 PatternHash;
- UINT32 *DwordPtr;
- UINT16 i;
- UINT16 j;
- UINT16 Multiplier;
-
- Multiplier = 1;
-
- // 1. Program D18F2x1C0[WrDramTrainMode]=1.
- MemNSetBitFieldNb (NBPtr, BFWrDramTrainMode, 1);
-
- PatternHash = ClCount << 24;
- for (i = 0; i < 3; i ++) {
- PatternHash |= (Pattern[i * ClCount * 24 + 9] << (8 * i));
- }
- if (NBPtr->CPGInit != PatternHash) {
-
- if (ClCount == 3) {
- // Double pattern length for MaxRdLat training
- Multiplier = 2;
- }
-
- // If write training buffer has not been initialized, initialize it
- // 2. Program D18F2x1C0[TrainLength] to the appropriate number of cache lines.
- MemNSetBitFieldNb (NBPtr, BFTrainLength, ClCount * Multiplier);
-
- // 3. Program D18F2x1D0[WrTrainBufAddr]=000h.
- MemNSetBitFieldNb (NBPtr, BFWrTrainBufAddr, 0);
-
- // 4. Successively write each dword of the training pattern to D18F2x1D4.
- DwordPtr = (UINT32 *) Pattern;
- for (j = 0; j < Multiplier; j++) {
- for (i = 0; i < (ClCount * 16); i++) {
- MemNSetBitFieldNb (NBPtr, BFWrTrainBufDat, DwordPtr[i]);
- }
- }
-
- NBPtr->CPGInit = PatternHash;
- }
-
- // 5. Program D18F2x1D0[WrTrainBufAddr]=000h
- MemNSetBitFieldNb (NBPtr, BFWrTrainBufAddr, 0);
-
- // 6. Program the DRAM training address
- MemNSetBitFieldNb (NBPtr, BFWrTrainAdrPtrLo, Address << (16 - 6));
- MemNSetBitFieldNb (NBPtr, BFWrTrainAdrPtrHi, (Address >> (38 - 16)) & 3);
-
- // 7. Program D18F2x1C0[WrTrainGo]=1.
- MemNSetBitFieldNb (NBPtr, BFWrTrainGo, 1);
-
- // 8. Wait for D18F2x1C0[WrTrainGo]=0.
- while (MemNGetBitFieldNb (NBPtr, BFWrTrainGo) != 0) {}
-
- // 9. Program D18F2x1C0[WrDramTrainMode]=0.
- MemNSetBitFieldNb (NBPtr, BFWrDramTrainMode, 0);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function reads cache lines continuously using TCB CPG engine
- *
- * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] Buffer - Array of bytes to be filled with data read from DRAM
- * @param[in] Address - System Address [47:16]
- * @param[in] ClCount - Number of cache lines
- *
- */
-
-VOID
-STATIC
-MemNContReadPatternClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Buffer[],
- IN UINT32 Address,
- IN UINT16 ClCount
- )
-{
- UINT16 Multiplier;
-
- Multiplier = 1;
- if (ClCount == 3) {
- // Double pattern length for MaxRdLat training
- Multiplier = 2;
- }
-
- // 1. Program D18F2x1C0[RdDramTrainMode]=1.
- MemNSetBitFieldNb (NBPtr, BFRdDramTrainMode, 1);
-
- // 2. Program D18F2x1C0[TrainLength] to the appropriate number of cache lines.
- MemNSetBitFieldNb (NBPtr, BFTrainLength, ClCount * Multiplier);
-
- // 3. Program the DRAM training address as follows:
- MemNSetBitFieldNb (NBPtr, BFWrTrainAdrPtrLo, Address << (16 - 6));
- MemNSetBitFieldNb (NBPtr, BFWrTrainAdrPtrHi, (Address >> (38 - 16)) & 3);
-
- // 4. Program D18F2x1D0[WrTrainBufAddr]=000h
- MemNSetBitFieldNb (NBPtr, BFWrTrainBufAddr, 0);
-
- // 5. Program D18F2x1C0[RdTrainGo]=1.
- MemNSetBitFieldNb (NBPtr, BFRdTrainGo, 1);
-
- // 6. Wait for D18F2x1C0[RdTrainGo]=0.
- while (MemNGetBitFieldNb (NBPtr, BFRdTrainGo) != 0) {}
-
- // 7. Read D18F2x1E8[TrainCmpSts] and D18F2x1E8[TrainCmpSts2].
- // This step will be accomplished in Compare routine.
-
- // 8. Program D18F2x1C0[RdDramTrainMode]=0.
- MemNSetBitFieldNb (NBPtr, BFRdDramTrainMode, 0);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function generates a continuous burst of reads during HW RcvEn training.
- *
- * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Address - System Address [47:16]
- *
- */
-VOID
-STATIC
-MemNGenHwRcvEnReadsClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 Address
- )
-{
- UINT8 TempBuffer[64];
- UINT8 Count;
-
- for (Count = 0; Count < 3; Count++) {
- NBPtr->ReadPattern (NBPtr, TempBuffer, Address, 64);
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function assigns read/write function pointers to CPG read/write modules.
- *
- * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-VOID
-MemNInitCPGClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- NBPtr->WritePattern = MemNContWritePatternClientNb;
- NBPtr->ReadPattern = MemNContReadPatternClientNb;
- NBPtr->GenHwRcvEnReads = MemNGenHwRcvEnReadsClientNb;
- NBPtr->FlushPattern = (VOID (*) (MEM_NB_BLOCK *, UINT32, UINT16)) memDefRet;
- NBPtr->CompareTestPattern = MemNCompareTestPatternClientNb;
- NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternClientNb;
- NBPtr->FamilySpecificHook[BeforeMemClr] = MemNBeforeMemClrClientNb;
- NBPtr->CPGInit = 0;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function compares test pattern with data in buffer and
- * return a pass/fail bitmap for 8 bytelanes (upper 8 bits are reserved)
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Buffer[] - Buffer data from DRAM (Measured data from DRAM) to compare
- * @param[in] Pattern[] - Pattern (Expected data in ROM/CACHE) to compare against
- * @param[in] ByteCount - Byte count
- *
- * @return PASS - Bitmap of results of comparison
- */
-
-UINT16
-STATIC
-MemNCompareTestPatternClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Buffer[],
- IN UINT8 Pattern[],
- IN UINT16 ByteCount
- )
-{
- return ~((UINT16) MemNGetBitFieldNb (NBPtr, BFTrainCmpSts));
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- *
- * This function compares test pattern with data in buffer and
- * return a pass/fail bitmap for 8 bytelanes (upper 8 bits are reserved)
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Buffer[] - Buffer data from DRAM (Measured data from DRAM) to compare
- * @param[in] Pattern[] - Pattern (Expected data in ROM/CACHE) to compare against
- * @param[in] ByteCount - Byte count
- *
- * @retval Bitmap of results of comparison
- */
-UINT16
-STATIC
-MemNInsDlyCompareTestPatternClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Buffer[],
- IN UINT8 Pattern[],
- IN UINT16 ByteCount
- )
-{
- return ~((UINT16) MemNGetBitFieldNb (NBPtr, BFTrainCmpSts2));
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function calculates RcvEn seed value for each rank
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-VOID
-MemNPrepareRcvrEnDlySeedNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MEM_TECH_BLOCK *TechPtr;
- CH_DEF_STRUCT *ChannelPtr;
- DIE_STRUCT *MCTPtr;
- UINT16 SeedTotal;
- UINT16 SeedFine;
- UINT16 SeedGross;
- UINT16 SeedPreGross;
- UINT16 SeedTotalPreScaling;
- UINT8 ByteLane;
- UINT16 Speed;
- UINT16 PlatEst;
- UINT8 ChipSel;
- UINT8 Pass;
- UINT16 *PlatEstSeed;
- UINT16 SeedValue[9];
- UINT16 SeedTtl[9];
- UINT16 SeedPre[9];
-
- TechPtr = NBPtr->TechPtr;
- MCTPtr = NBPtr->MCTPtr;
- ChannelPtr = TechPtr->NBPtr->ChannelPtr;
- Speed = NBPtr->DCTPtr->Timings.Speed;
- SeedTotalPreScaling = 0;
- ChipSel = TechPtr->ChipSel;
- Pass = TechPtr->Pass;
-
- for (ByteLane = 0; ByteLane < (MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) {
- TechPtr->Bytelane = ByteLane;
- if (Pass == 1) {
- // Get platform override seed
- PlatEstSeed = (UINT16 *) FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_RXEN_SEED, MCTPtr->SocketId, ChannelPtr->ChannelID);
- // For Pass1, BIOS starts with the delay value obtained from the first pass of write
- // levelization training that was done in DDR3 Training and add a delay value of 3Bh.
- PlatEst = 0x3B;
- NBPtr->FamilySpecificHook[OverrideRcvEnSeed] (NBPtr, &PlatEst);
- PlatEst = ((PlatEstSeed != NULL) ? PlatEstSeed[ByteLane] : PlatEst);
- SeedTotal = ChannelPtr->WrDqsDlys[(ChipSel >> 1) * TechPtr->DlyTableWidth () + ByteLane] + PlatEst;
- SeedValue[ByteLane] = PlatEst;
- } else {
- // For Pass2
- // SeedTotalPreScaling = (the total delay values in D18F2x[1,0]9C_x0000_00[24:10] from pass 1 of
- // DQS receiver enable training) - 20h. Subtract 1UI to get back to preamble left edge.
- if ((ChipSel & 1) == 0) {
- // Save Seed for odd CS SeedTotalPreScaling RxEn Value
- TechPtr->PrevPassRcvEnDly[ByteLane] = ChannelPtr->RcvEnDlys[(ChipSel >> 1) * TechPtr->DlyTableWidth () + ByteLane];
- }
- SeedTotalPreScaling = TechPtr->PrevPassRcvEnDly[ByteLane] - 0x20;
- // SeedTotal = SeedTotalPreScaling*target frequency/lowest supported frequency.
- SeedTotal = (UINT16) (((UINT32) SeedTotalPreScaling * Speed) / TechPtr->PrevSpeed);
- NBPtr->FamilySpecificHook[OverrideRcvEnSeedPassN] (NBPtr, &SeedTotal);
- }
- SeedTtl[ByteLane] = SeedTotal;
-
- // SeedGross = SeedTotal DIV 32.
- SeedGross = SeedTotal >> 5;
- // SeedFine = SeedTotal MOD 32.
- SeedFine = SeedTotal & 0x1F;
- // Next, determine the gross component of SeedTotal. SeedGrossPass1=SeedTotal DIV 32.
- // Then, determine the fine delay component of SeedTotal. SeedFinePass1=SeedTotal MOD 32.
- // Use SeedGrossPass1 to determine SeedPreGrossPass1:
-
- if ((SeedGross & 0x1) != 0) {
- //if SeedGross is odd
- SeedPreGross = 1;
- } else {
- //if SeedGross is even
- SeedPreGross = 2;
- }
- // (SeedGross - SeedPreGross)
- TechPtr->DiffSeedGrossSeedPreGross[ByteLane] = (SeedGross - SeedPreGross) << 5;
-
- //BIOS programs registers F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52 with SeedPreGrossPass1
- //and SeedFinePass1 from the preceding steps.
-
- NBPtr->SetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (ChipSel >> 1, ByteLane), (SeedPreGross << 5) | SeedFine);
- SeedPre[ByteLane] = (SeedPreGross << 5) | SeedFine;
-
- // 202688: Program seed value to RcvEnDly also.
- NBPtr->SetTrainDly (NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (ChipSel >> 1, ByteLane), SeedGross << 5);
- }
-
- IDS_HDT_CONSOLE_DEBUG_CODE (
- if (Pass == 1) {
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tSeedValue: ");
- for (ByteLane = 0; ByteLane < (MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) {
- IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", SeedValue[ByteLane]);
- }
- IDS_HDT_CONSOLE (MEM_FLOW, "\n");
- }
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tSeedTotal: ");
- for (ByteLane = 0; ByteLane < (MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) {
- IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", SeedTtl[ByteLane]);
- }
- IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t SeedPRE: ");
- for (ByteLane = 0; ByteLane < (MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) {
- IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", SeedPre[ByteLane]);
- }
- IDS_HDT_CONSOLE (MEM_FLOW, "\n");
- );
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Waits specified number of MEMCLKs
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] MemClkCount - Number of MEMCLKs
- *
- * ----------------------------------------------------------------------------
- */
-VOID
-MemNWaitXMemClksNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 MemClkCount
- )
-{
- MemUWait10ns ((MemClkCount * 100 + NBPtr->DCTPtr->Timings.Speed - 1) / NBPtr->DCTPtr->Timings.Speed, NBPtr->MemPtr);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Issues dummy TCB write read to zero out CL that is used for MemClr
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *UnUsed - unused
- *
- * ----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemNBeforeMemClrClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN VOID *UnUsed
- )
-{
- UINT8 Pattern[64];
- UINT8 i;
-
- for (i = 0; i < 64; i++) {
- Pattern[i] = 0;
- }
-
- MemNContWritePatternClientNb (NBPtr, 0x20, Pattern, 1);
- MemNContReadPatternClientNb (NBPtr, Pattern, 0x20, 1);
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function uses the PRBS generator in the DCT to send a DDR Activate command
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] ChipSelect - Chip select 0-7
- * @param[in] Bank - Bank Address 0-7
- * @param[in] RowAddress - Row Address [17:0]
- *
- */
-
-VOID
-STATIC
-MemNRrwActivateCmd (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 ChipSelect,
- IN UINT8 Bank,
- IN UINT32 RowAddress
- )
-{
- // Set Chip select
- MemNSetBitFieldNb (NBPtr, BFCmdChipSelect, (1 << ChipSelect));
- // Set Bank Address
- MemNSetBitFieldNb (NBPtr, BFCmdBank, Bank);
- // Set Row Address
- MemNSetBitFieldNb (NBPtr, BFCmdAddress, RowAddress);
- // Send the command
- MemNSetBitFieldNb (NBPtr, BFSendActCmd, 1);
- // Wait for command complete
- MemNPollBitFieldNb (NBPtr, BFSendActCmd, 0, PCI_ACCESS_TIMEOUT, FALSE);
- // Wait 75 MEMCLKs
- NBPtr->WaitXMemClks (NBPtr, 75);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function uses the PRBS generator in the DCT to send a DDR Precharge
- * or Precharge All command
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] ChipSelect - Chip select 0-7
- * @param[in] Bank - Bank Address 0-7, PRECHARGE_ALL_BANKS = Precharge All
- *
- *
- */
-
-VOID
-STATIC
-MemNRrwPrechargeCmd (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 ChipSelect,
- IN UINT8 Bank
- )
-{
- // Wait 25 MEMCLKs
- NBPtr->WaitXMemClks (NBPtr, 25);
- // Set Chip select
- NBPtr->SetBitField (NBPtr, BFCmdChipSelect, (1 << ChipSelect));
- if (Bank == PRECHARGE_ALL_BANKS) {
- // Set Row Address, bit 10
- NBPtr->SetBitField (NBPtr, BFCmdAddress, NBPtr->GetBitField (NBPtr, BFCmdAddress) | (1 << 10) );
- } else {
- // Clear Row Address, bit 10
- NBPtr->SetBitField (NBPtr, BFCmdAddress, NBPtr->GetBitField (NBPtr, BFCmdAddress) & (~(1 << 10)) );
- // Set Bank Address
- NBPtr->SetBitField (NBPtr, BFCmdBank, Bank);
- }
- // Send the command
- NBPtr->SetBitField (NBPtr, BFSendPchgCmd, 1);
- // Wait for command complete
- NBPtr->PollBitField (NBPtr, BFSendPchgCmd, 0, PCI_ACCESS_TIMEOUT, FALSE);
- // Wait 25 MEMCLKs
- NBPtr->WaitXMemClks (NBPtr, 25);
-}
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function generates a continuous burst of reads for HW RcvEn
- * training using the Unified Northbridge Reliable Read/Write Engine.
- *
- * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Address - Unused by this function
- *
- */
-VOID
-STATIC
-MemNGenHwRcvEnReadsUnb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 Address
- )
-{
- VOID *DummyPtr;
- DummyPtr = NULL;
- //
- // Issue Stream of Reads from the Target Rank
- //
- NBPtr->ReadPattern (NBPtr, DummyPtr, NULL, NBPtr->TechPtr->PatternLength);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function generates a continuous stream of reads from DRAM using the
- * Unified Northbridge Reliable Read/Write Engine.
- *
- * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] Buffer - Unused by this function
- * @param[in] Address - Unused by this function
- * @param[in] ClCount - Number of cache lines to read
- *
- * Assumptions:
- *
- *
- *
- */
-
-VOID
-STATIC
-MemNContReadPatternUnb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Buffer[],
- IN UINT32 Address,
- IN UINT16 ClCount
- )
-{
- MEM_TECH_BLOCK *TechPtr;
- RRW_SETTINGS *Rrw;
- UINT8 CmdTgt;
- UINT8 ChipSel;
-
- TechPtr = NBPtr->TechPtr;
- Rrw = &NBPtr->RrwSettings;
-
- ChipSel = TechPtr->ChipSel;
- CmdTgt = Rrw->CmdTgt;
- //
- // Wait for RRW Engine to be ready and turn it on
- //
- NBPtr->PollBitField (NBPtr, BFCmdSendInProg, 0, PCI_ACCESS_TIMEOUT, FALSE);
- NBPtr->SetBitField (NBPtr, BFCmdTestEnable, 1);
- //
- // Depending upon the Cmd Target, send Row Activate and set Chipselect
- // for the Row or Rows that will be used
- //
- MemNRrwActivateCmd (NBPtr, ChipSel, Rrw->TgtBankAddressA, Rrw->TgtRowAddressA);
- NBPtr->SetBitField (NBPtr, BFTgtChipSelectA, ChipSel);
- if (CmdTgt == CMD_TGT_AB) {
- MemNRrwActivateCmd (NBPtr, ChipSel, Rrw->TgtBankAddressB, Rrw->TgtRowAddressB);
- NBPtr->SetBitField (NBPtr, BFTgtChipSelectB, ChipSel);
- }
- // Set Comparison Masks
- NBPtr->SetBitField (NBPtr, BFDramDqMaskLow, Rrw->CompareMaskLow);
- NBPtr->SetBitField (NBPtr, BFDramDqMaskHigh, Rrw->CompareMaskHigh);
- //
- // If All Dimms are ECC Capable Test ECC. Otherwise, mask it off
- //
- NBPtr->SetBitField (NBPtr, BFDramEccMask, (NBPtr->MCTPtr->Status[SbEccDimms] == TRUE) ? Rrw->CompareMaskEcc : 0xFF);
- //
- // Program the PRBS Seed
- //
- NBPtr->SetBitField (NBPtr, BFDataPrbsSeed, Rrw->DataPrbsSeed);
- //
- // Set the Command Count
- //
- NBPtr->SetBitField (NBPtr, BFCmdCount, ClCount);
- //
- // Program the Bubble Count and CmdStreamLen
- //
- NBPtr->SetBitField (NBPtr, BFBubbleCnt, 0);
- NBPtr->SetBitField (NBPtr, BFBubbleCnt2, 0);
- NBPtr->SetBitField (NBPtr, BFCmdStreamLen, 1);
- //
- // Program the Starting Address
- //
- NBPtr->SetBitField (NBPtr, BFTgtBankA, Rrw->TgtBankAddressA);
- NBPtr->SetBitField (NBPtr, BFTgtAddressA, Rrw->TgtColAddressA);
- if (CmdTgt == CMD_TGT_AB) {
- NBPtr->SetBitField (NBPtr, BFTgtBankB, Rrw->TgtBankAddressB);
- NBPtr->SetBitField (NBPtr, BFTgtAddressB, Rrw->TgtColAddressB);
- }
- //
- // Reset All Errors and Disable StopOnErr
- //
- NBPtr->SetBitField (NBPtr, BFResetAllErr, 1);
- NBPtr->SetBitField (NBPtr, BFStopOnErr, 0);
- //
- // Program the CmdTarget
- //
- NBPtr->SetBitField (NBPtr, BFCmdTgt, CmdTgt);
- //
- // Set CmdType to read
- //
- NBPtr->SetBitField (NBPtr, BFCmdType, CMD_TYPE_READ);
- //
- // Start the Commands
- //
- NBPtr->SetBitField (NBPtr, BFSendCmd, 1);
- //
- // Commands have started, wait for the reads to complete then clear the command
- //
- NBPtr->PollBitField (NBPtr, BFTestStatus, 1, PCI_ACCESS_TIMEOUT, FALSE);
- NBPtr->PollBitField (NBPtr, BFCmdSendInProg, 0, PCI_ACCESS_TIMEOUT, FALSE);
- NBPtr->SetBitField (NBPtr, BFSendCmd, 0);
- //
- // Send the Precharge All Command
- //
- MemNRrwPrechargeCmd (NBPtr, ChipSel, PRECHARGE_ALL_BANKS);
- //
- // Turn Off the RRW Engine
- //
- NBPtr->SetBitField (NBPtr, BFCmdTestEnable, 0);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function generates a continuous stream of writes to DRAM using the
- * Unified Northbridge Reliable Read/Write Engine.
- *
- * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] Address - Unused by this function
- * @param[in] Pattern - Unused by this function
- * @param[in] ClCount - Number of cache lines to write
- *
- */
-
-VOID
-STATIC
-MemNContWritePatternUnb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 Address,
- IN UINT8 Pattern[],
- IN UINT16 ClCount
- )
-{
- MEM_TECH_BLOCK *TechPtr;
- RRW_SETTINGS *Rrw;
- UINT8 CmdTgt;
- UINT8 ChipSel;
-
- TechPtr = NBPtr->TechPtr;
- Rrw = &NBPtr->RrwSettings;
-
- ChipSel = TechPtr->ChipSel;
- CmdTgt = Rrw->CmdTgt;
- //
- // Wait for RRW Engine to be ready and turn it on
- //
- NBPtr->PollBitField (NBPtr, BFCmdSendInProg, 0, PCI_ACCESS_TIMEOUT, FALSE);
- NBPtr->SetBitField (NBPtr, BFCmdTestEnable, 1);
-
- //
- // Depending upon the Cmd Target, send Row Activate and set Chipselect
- // for the Row or Rows that will be used
- //
- MemNRrwActivateCmd (NBPtr, ChipSel, Rrw->TgtBankAddressA, Rrw->TgtRowAddressA);
- NBPtr->SetBitField (NBPtr, BFTgtChipSelectA, ChipSel);
- if (CmdTgt == CMD_TGT_AB) {
- MemNRrwActivateCmd (NBPtr, ChipSel, Rrw->TgtBankAddressB, Rrw->TgtRowAddressB);
- NBPtr->SetBitField (NBPtr, BFTgtChipSelectB, ChipSel);
- }
- //
- // Program the PRBS Seed
- //
- NBPtr->SetBitField (NBPtr, BFDataPrbsSeed, Rrw->DataPrbsSeed);
- //
- // Set the Command Count
- //
- NBPtr->SetBitField (NBPtr, BFCmdCount, ClCount);
- //
- // Program the Bubble Count and CmdStreamLen
- //
- NBPtr->SetBitField (NBPtr, BFBubbleCnt, 0);
- NBPtr->SetBitField (NBPtr, BFBubbleCnt2, 0);
- NBPtr->SetBitField (NBPtr, BFCmdStreamLen, 1);
- //
- // Program the Starting Address
- //
- NBPtr->SetBitField (NBPtr, BFTgtBankA, Rrw->TgtBankAddressA);
- NBPtr->SetBitField (NBPtr, BFTgtAddressA, Rrw->TgtColAddressA);
- if (CmdTgt == CMD_TGT_AB) {
- NBPtr->SetBitField (NBPtr, BFTgtBankB, Rrw->TgtBankAddressB);
- NBPtr->SetBitField (NBPtr, BFTgtAddressB, Rrw->TgtColAddressB);
- }
- //
- // Program the CmdTarget
- //
- NBPtr->SetBitField (NBPtr, BFCmdTgt, CmdTgt);
- //
- // Set CmdType to read
- //
- NBPtr->SetBitField (NBPtr, BFCmdType, CMD_TYPE_WRITE);
- //
- // Start the Commands
- //
- NBPtr->SetBitField (NBPtr, BFSendCmd, 1);
- //
- // Commands have started, wait for the writes to complete then clear the command
- //
- NBPtr->PollBitField (NBPtr, BFTestStatus, 1, PCI_ACCESS_TIMEOUT, FALSE);
- NBPtr->PollBitField (NBPtr, BFCmdSendInProg, 0, PCI_ACCESS_TIMEOUT, FALSE);
- NBPtr->SetBitField (NBPtr, BFSendCmd, 0);
- //
- // Send the Precharge All Command
- //
- MemNRrwPrechargeCmd (NBPtr, ChipSel, PRECHARGE_ALL_BANKS);
- //
- // Turn Off the RRW Engine
- //
- NBPtr->SetBitField (NBPtr, BFCmdTestEnable, 0);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function checks the Error status bits for comparison results
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Buffer[] - Not used in this implementation
- * @param[in] Pattern[] - Not used in this implementation
- * @param[in] ByteCount - Not used in this implementation
- *
- * @return PASS - Bitmap of results of comparison
- */
-
-UINT16
-STATIC
-MemNCompareTestPatternUnb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Buffer[],
- IN UINT8 Pattern[],
- IN UINT16 ByteCount
- )
-{
-
-
- UINT16 i;
- UINT16 Pass;
- UINT8 ChipSel;
- UINT8 ColumnCount;
- UINT8* FailingBitMaskPtr;
- UINT8 FailingBitMask[9];
- UINT32 NibbleErrSts;
-
- ChipSel = NBPtr->TechPtr->ChipSel;
- ColumnCount = NBPtr->ChannelPtr->ColumnCount;
- // Calculate Failing Bitmask pointer
- FailingBitMaskPtr = &(NBPtr->ChannelPtr->FailingBitMask[(ColumnCount * NBPtr->TechPtr->ChipSel)]);
-
- //
- // Get Failing bit data
- //
- *((UINT32*)FailingBitMask) = NBPtr->GetBitField (NBPtr, BFDQErrLow);
- *((UINT32*)&FailingBitMask[4]) = NBPtr->GetBitField (NBPtr, BFDQErrHigh);
- FailingBitMask[8] = (UINT8)NBPtr->GetBitField (NBPtr, BFEccErr);
-
- Pass = 0x0000;
- //
- // Get Comparison Results - Convert Nibble Masks to Byte Masks
- //
- NibbleErrSts = NBPtr->GetBitField (NBPtr, BFNibbleErrSts);
-
- for (i = 0; i < ColumnCount ; i++) {
- Pass |= ((NibbleErrSts & 0x03) > 0 ) ? (1 << i) : 0;
- NibbleErrSts >>= 2;
- FailingBitMaskPtr[i] = FailingBitMask[i];
- }
- Pass = ~Pass;
- return Pass;
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- *
- * This function checks the Error status bits for offset comparison results
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Buffer[] - Buffer data from DRAM (Measured data from DRAM) to compare
- * @param[in] Pattern[] - Pattern (Expected data in ROM/CACHE) to compare against
- * @param[in] ByteCount - Byte count
- *
- * @retval Bitmap of results of comparison
- */
-UINT16
-STATIC
-MemNInsDlyCompareTestPatternUnb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Buffer[],
- IN UINT8 Pattern[],
- IN UINT16 ByteCount
- )
-{
- UINT16 i;
- UINT16 Pass;
- UINT8 ColumnCount;
- UINT32 NibbleErr180Sts;
-
- ColumnCount = NBPtr->ChannelPtr->ColumnCount;
- Pass = 0x0000;
- //
- // Get Comparison Results - Convert Nibble Masks to Byte Masks
- //
- NibbleErr180Sts = NBPtr->GetBitField (NBPtr, BFNibbleErr180Sts);
-
- for (i = 0; i < ColumnCount ; i++) {
- Pass |= ((NibbleErr180Sts & 0x03) > 0 ) ? (1 << i) : 0;
- NibbleErr180Sts >>= 2;
- }
- Pass = ~Pass;
-
- return Pass;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function assigns read/write function pointers to CPG read/write modules.
- *
- * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-VOID
-MemNInitCPGUnb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- NBPtr->WritePattern = MemNContWritePatternUnb;
- NBPtr->ReadPattern = MemNContReadPatternUnb;
- NBPtr->GenHwRcvEnReads = MemNGenHwRcvEnReadsUnb;
- NBPtr->FlushPattern = (VOID (*) (MEM_NB_BLOCK *, UINT32, UINT16)) memDefRet;
- NBPtr->TrainingPatternInit = (AGESA_STATUS (*) (MEM_NB_BLOCK *)) memDefRetSuccess;
- NBPtr->TrainingPatternFinalize = (AGESA_STATUS (*) (MEM_NB_BLOCK *)) memDefRetSuccess;
- NBPtr->CompareTestPattern = MemNCompareTestPatternUnb;
- NBPtr->InsDlyCompareTestPattern = MemNInsDlyCompareTestPatternUnb;
- NBPtr->FamilySpecificHook[SetupHwTrainingEngine] = MemNSetupHwTrainingEngineUnb;
- NBPtr->CPGInit = 0;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/mnflow.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/mnflow.c
deleted file mode 100644
index 8e7f503..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/mnflow.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnflow.c
- *
- * Common Northbridge initializer flow for MCT and DCT
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB)
- * @e \$Revision: 37402 $ @e \$Date: 2010-09-03 05:36:02 +0800 (Fri, 03 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_MNFLOW_FILECODE
-/* features */
-#include "mftds.h"
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-STATIC
-MemNInitDCTNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-STATIC
-MemNCleanupDctRegsNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function programs the MCT with initial values
- *
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - AGESA_FATAL error did not occur (it is possible to have an Error that is not AGESA_SUCCESS)
- * @return FALSE - AGESA_FATAL error occurred
- */
-
-BOOLEAN
-MemNInitMCTNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MEM_TECH_BLOCK *TechPtr;
- UINT8 Dct;
- BOOLEAN Flag;
-
- TechPtr = NBPtr->TechPtr;
- // Switch Tech functions for Nb
- NBPtr->TechBlockSwitch (NBPtr);
- // Start Memory controller initialization sequence
- Flag = FALSE;
- if (TechPtr->DimmPresence (TechPtr)) {
- AGESA_TESTPOINT (TpProcMemPlatformSpecificInit, &(NBPtr->MemPtr->StdHeader));
- if (NBPtr->MemNPlatformSpecificFormFactorInitNb (NBPtr)) {
- AGESA_TESTPOINT (TpProcMemSpdTiming, &(NBPtr->MemPtr->StdHeader));
- if (TechPtr->SpdCalcWidth (TechPtr)) {
- AGESA_TESTPOINT (TpProcMemSpeedTclConfig, &(NBPtr->MemPtr->StdHeader));
- if (TechPtr->SpdGetTargetSpeed (TechPtr)) {
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
-
- Flag |= MemNInitDCTNb (NBPtr);
- }
-
- if (Flag && !NBPtr->IsSupported[TwoStageDramInit] && (NBPtr->MCTPtr->ErrCode != AGESA_FATAL)) {
- MemFInitTableDrive (NBPtr, MTBeforeDInit);
- AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeDramInit, &(NBPtr->MemPtr->StdHeader));
- IDS_HDT_CONSOLE (MEM_FLOW, "\nCalling out to Platform BIOS...\n");
- AgesaHookBeforeDramInit (0, NBPtr->MemPtr);
- IDS_HDT_CONSOLE (MEM_FLOW, "\nVDDIO = 1.%dV\n", (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) ? 5 :
- (NBPtr->RefPtr->DDR3Voltage == VOLT1_35) ? 35 :
- (NBPtr->RefPtr->DDR3Voltage == VOLT1_25) ? 25 : 999);
- AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeDramInit, &(NBPtr->MemPtr->StdHeader));
- IDS_OPTION_HOOK (IDS_BEFORE_DRAM_INIT, NBPtr, &(NBPtr->MemPtr->StdHeader));
- NBPtr->StartupDCT (NBPtr);
- }
- }
- }
- }
- }
- return (BOOLEAN) (NBPtr->MCTPtr->ErrCode != AGESA_FATAL);
-}
-
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function programs the DCT with initial values
- *
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - Error did not occur
- * @return FALSE - Error occurred
- */
-
-BOOLEAN
-STATIC
-MemNInitDCTNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MEM_TECH_BLOCK *TechPtr;
- TechPtr = NBPtr->TechPtr;
- TechPtr->SetDramMode (TechPtr);
-
- if (!NBPtr->MCTPtr->GangedMode || (NBPtr->MCTPtr->Dct == 0)) {
- if (NBPtr->DCTPtr->Timings.DctDimmValid == 0) {
- NBPtr->DisableDCT (NBPtr);
- } else {
- MemNCleanupDctRegsNb (NBPtr);
- if (TechPtr->AutoCycTiming (TechPtr)) {
- if (TechPtr->SpdSetBanks (TechPtr)) {
- if (NBPtr->StitchMemory (NBPtr)) {
- // if all dimms on a DCT are disabled, the DCT needs to be disabled.
- if (NBPtr->DCTPtr->Timings.CsEnabled != 0) {
- if (NBPtr->AutoConfig (NBPtr)) {
- if (NBPtr->PlatformSpec (NBPtr)) {
- return TRUE;
- }
- }
- } else {
- NBPtr->DisableDCT (NBPtr);
- }
- }
- }
- }
- }
- }
- return FALSE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function selects appropriate Tech functions for the NB.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNTechBlockSwitchNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MEM_TECH_BLOCK *TechPtr;
-
- TechPtr = NBPtr->TechPtr;
-
- // Specify Dimm-Byte training for Nb
- MemTDimmByteTrainInit (TechPtr);
-
- // Filter included for RcvrEn training.
- // note: If you'd like to drop the filter, you have to comment out these two lines together.
- TechPtr->MaxFilterDly = MAX_FILTER_DLY_DDR3;
- TechPtr->SaveRcvrEnDly = MemTSaveRcvrEnDlyByteFilter;
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- *
- * This function clears DCT registers
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-STATIC
-MemNCleanupDctRegsNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- BIT_FIELD_NAME BitField;
-
- for (BitField = BFCSBaseAddr0Reg; BitField <= BFCSBaseAddr7Reg; BitField++) {
- MemNSetBitFieldNb (NBPtr, BitField, 0);
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/mnmct.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/mnmct.c
deleted file mode 100644
index c6fe850..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/mnmct.c
+++ /dev/null
@@ -1,1184 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnmct.c
- *
- * Northbridge Common MCT supporting functions
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB)
- * @e \$Revision: 39420 $ @e \$Date: 2010-10-12 00:52:49 +0800 (Tue, 12 Oct 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mport.h"
-#include "mm.h"
-#include "mn.h"
-#include "mu.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "GeneralServices.h"
-#include "cpuFeatures.h"
-#include "merrhdl.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_MNMCT_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define _16MB_RJ16 0x0100
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemNSetMTRRrangeNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 Base,
- IN OUT UINT32 *LimitPtr,
- IN UINT32 MtrrAddr,
- IN UINT8 MtrrType
- );
-
-VOID
-STATIC
-MemNC6AdjustMSRs (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-extern BUILD_OPT_CFG UserOptions;
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Get max frequency from OEM platform definition, from
- * any user override (limiting) of max frequency, and
- * from any Si Revision Specific information. Return
- * the least of these three in DIE_STRUCT.Timings.TargetSpeed.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNSyncTargetSpeedNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- CONST UINT16 DdrMaxRateTab[] = {
- UNSUPPORTED_DDR_FREQUENCY,
- DDR1866_FREQUENCY,
- DDR1600_FREQUENCY,
- DDR1333_FREQUENCY,
- DDR1066_FREQUENCY,
- DDR800_FREQUENCY,
- DDR667_FREQUENCY,
- DDR533_FREQUENCY,
- DDR400_FREQUENCY
- };
-
- UINT8 Dct;
- UINT8 Channel;
- UINT16 MinSpeed;
- UINT16 DdrMaxRate;
- DCT_STRUCT *DCTPtr;
- USER_MEMORY_TIMING_MODE *ChnlTmgMod;
- USER_MEMORY_TIMING_MODE Mode[MAX_CHANNELS_PER_SOCKET];
- MEMORY_BUS_SPEED MemClkFreq;
- MEMORY_BUS_SPEED ProposedFreq;
-
- ASSERT (NBPtr->DctCount <= sizeof (Mode));
- MinSpeed = 16000;
- DdrMaxRate = 16000;
- if (NBPtr->IsSupported[CheckMaxDramRate]) {
- // Check maximum DRAM data rate that the processor is designed to support.
- DdrMaxRate = DdrMaxRateTab[MemNGetBitFieldNb (NBPtr, BFDdrMaxRate)];
- NBPtr->FamilySpecificHook[GetDdrMaxRate] (NBPtr, &DdrMaxRate);
- IDS_OPTION_HOOK (IDS_SKIP_FUSED_MAX_RATE, &DdrMaxRate, &NBPtr->MemPtr->StdHeader);
- }
-
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- MemNSwitchDCTNb (NBPtr, Dct);
- DCTPtr = NBPtr->DCTPtr;
-
- // Check if input user time mode is valid or not
- ASSERT ((NBPtr->RefPtr->UserTimingMode == TIMING_MODE_SPECIFIC) ||
- (NBPtr->RefPtr->UserTimingMode == TIMING_MODE_LIMITED) ||
- (NBPtr->RefPtr->UserTimingMode == TIMING_MODE_AUTO));
- Mode[Dct] = NBPtr->RefPtr->UserTimingMode;
- // Check if input clock value is valid or not
- ASSERT ((NBPtr->ChannelPtr->TechType == DDR3_TECHNOLOGY) ?
- (NBPtr->RefPtr->MemClockValue >= DDR667_FREQUENCY) :
- (NBPtr->RefPtr->MemClockValue <= DDR1066_FREQUENCY));
- MemClkFreq = NBPtr->RefPtr->MemClockValue;
- if (DCTPtr->Timings.DctDimmValid != 0) {
- Channel = MemNGetSocketRelativeChannelNb (NBPtr, Dct, 0);
- ChnlTmgMod = (USER_MEMORY_TIMING_MODE *) FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_BUS_SPEED, NBPtr->MCTPtr->SocketId, Channel);
- if (ChnlTmgMod != NULL) {
- // Check if input user timing mode is valid or not
- ASSERT ((ChnlTmgMod[0] == TIMING_MODE_SPECIFIC) || (ChnlTmgMod[0] == TIMING_MODE_LIMITED) ||
- (ChnlTmgMod[0] != TIMING_MODE_AUTO));
- if (ChnlTmgMod[0] != TIMING_MODE_AUTO) {
- Mode[Dct] = ChnlTmgMod[0];
- // Check if input clock value is valid or not
- ASSERT ((NBPtr->ChannelPtr->TechType == DDR3_TECHNOLOGY) ?
- (ChnlTmgMod[1] >= DDR667_FREQUENCY) :
- (ChnlTmgMod[1] <= DDR1066_FREQUENCY));
- MemClkFreq = ChnlTmgMod[1];
- }
- }
-
- ProposedFreq = UserOptions.CfgMemoryBusFrequencyLimit;
- if (Mode[Dct] == TIMING_MODE_LIMITED) {
- if (MemClkFreq < ProposedFreq) {
- ProposedFreq = MemClkFreq;
- }
- } else if (Mode[Dct] == TIMING_MODE_SPECIFIC) {
- ProposedFreq = MemClkFreq;
- }
-
- if (Mode[Dct] == TIMING_MODE_SPECIFIC) {
- DCTPtr->Timings.TargetSpeed = (UINT16) ProposedFreq;
- } else {
- // "limit" mode
- if (DCTPtr->Timings.TargetSpeed > ProposedFreq) {
- DCTPtr->Timings.TargetSpeed = (UINT16) ProposedFreq;
- }
- }
-
- if (DCTPtr->Timings.TargetSpeed > DdrMaxRate) {
- if (Mode[Dct] == TIMING_MODE_SPECIFIC) {
- PutEventLog (AGESA_ALERT, MEM_ALERT_USER_TMG_MODE_OVERRULED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_ALERT, NBPtr->MCTPtr);
- }
- DCTPtr->Timings.TargetSpeed = DdrMaxRate;
- }
-
- IDS_SKIP_HOOK (IDS_POR_MEM_FREQ, NBPtr, &NBPtr->MemPtr->StdHeader) {
- //
- //Call Platform POR Frequency Override
- //
- if (!MemProcessConditionalOverrides (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr, PSO_ACTION_SPEEDLIMIT, ALL_DIMMS)) {
- //
- // Get the POR frequency limit
- //
- NBPtr->PsPtr->MemPGetPORFreqLimit (NBPtr);
- }
- }
-
- if (MinSpeed > DCTPtr->Timings.TargetSpeed) {
- MinSpeed = DCTPtr->Timings.TargetSpeed;
- }
- }
- }
-
- if (MinSpeed == DDR667_FREQUENCY) {
- NBPtr->StartupSpeed = DDR667_FREQUENCY;
- }
-
- // Sync all DCTs to the same speed
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- MemNSwitchDCTNb (NBPtr, Dct);
- NBPtr->DCTPtr->Timings.TargetSpeed = MinSpeed;
- NBPtr->MemNCapSpeedBatteryLife (NBPtr);
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function waits for all DCTs to be ready
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemNSyncDctsReadyNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- if (NBPtr->MCTPtr->DimmValid) {
- MemNPollBitFieldNb (NBPtr, BFDramEnabled, 1, PCI_ACCESS_TIMEOUT, FALSE);
- // Re-enable phy compensation engine after Dram init has completed
- MemNSwitchDCTNb (NBPtr, 0);
- MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 0);
- }
- // Wait 750 us for the phy compensation engine to reinitialize.
- MemUWait10ns (75000, NBPtr->MemPtr);
-
- MemNSyncAddrMapToAllNodesNb (NBPtr);
- return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function create the HT memory map
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemNHtMemMapInitNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT32 BottomIo;
- UINT32 HoleOffset;
- UINT32 DctSelBaseAddr;
- UINT32 NodeSysBase;
- UINT32 NodeSysLimit;
- MEM_PARAMETER_STRUCT *RefPtr;
- DIE_STRUCT *MCTPtr;
-
- RefPtr = NBPtr->RefPtr;
- MCTPtr = NBPtr->MCTPtr;
- //
- // Physical addresses in this function are right adjusted by 16 bits ([47:16])
- // They are BottomIO, HoleOffset, DctSelBaseAddr, NodeSysBase, NodeSysLimit.
- //
-
- // Enforce bottom of IO be be 128MB aligned
- ASSERT ((RefPtr->BottomIo < (_4GB_RJ16 >> 8)) && (RefPtr->BottomIo != 0));
- BottomIo = (RefPtr->BottomIo & 0xF8) << 8;
-
- if (!MCTPtr->GangedMode) {
- DctSelBaseAddr = MCTPtr->DctData[0].Timings.DctMemSize;
- } else {
- DctSelBaseAddr = 0;
- }
-
- if (MCTPtr->NodeMemSize) {
- NodeSysBase = NBPtr->SharedPtr->CurrentNodeSysBase;
- NodeSysLimit = NodeSysBase + MCTPtr->NodeMemSize - 1;
- DctSelBaseAddr += NodeSysBase;
-
- if ((NBPtr->IsSupported[ForceEnMemHoleRemapping]) || (RefPtr->MemHoleRemapping)) {
- if ((NodeSysBase < BottomIo) && (NodeSysLimit >= BottomIo)) {
- // HW Dram Remap
- MCTPtr->Status[SbHWHole] = TRUE;
- RefPtr->GStatus[GsbHWHole] = TRUE;
- MCTPtr->NodeHoleBase = BottomIo;
- RefPtr->HoleBase = BottomIo;
-
- HoleOffset = _4GB_RJ16 - BottomIo;
-
- NodeSysLimit += HoleOffset;
-
- if ((DctSelBaseAddr > 0) && (DctSelBaseAddr < BottomIo)) {
- HoleOffset += DctSelBaseAddr;
- } else {
- if (DctSelBaseAddr >= BottomIo) {
- DctSelBaseAddr += HoleOffset;
- }
- HoleOffset += NodeSysBase;
- }
-
- MemNSetBitFieldNb (NBPtr, BFDramHoleBase, BottomIo >> 8);
- MemNSetBitFieldNb (NBPtr, BFDramHoleOffset, HoleOffset >> 7);
- MemNSetBitFieldNb (NBPtr, BFDramHoleValid, 1);
-
- } else if (NodeSysBase == BottomIo) {
- // SW Node Hoist
- MCTPtr->Status[SbSWNodeHole] = TRUE;
- RefPtr->GStatus[GsbSpIntRemapHole] = TRUE;
- RefPtr->GStatus[GsbSoftHole] = TRUE;
-
- RefPtr->HoleBase = NodeSysBase;
- DctSelBaseAddr = _4GB_RJ16 + (DctSelBaseAddr - NodeSysBase);
- NodeSysLimit = _4GB_RJ16 + (NodeSysLimit - NodeSysBase);
- NodeSysBase = _4GB_RJ16;
- } else {
- // No Remapping. Normal Contiguous mapping
- }
- } else {
- // No Remapping. Normal Contiguous mapping
- }
-
- if (NBPtr->IsSupported[Check1GAlign]) {
- if (UserOptions.CfgNodeMem1GBAlign) {
- NBPtr->MemPNodeMemBoundaryNb (NBPtr, (UINT32 *)&NodeSysLimit);
- }
- }
-
- MCTPtr->NodeSysBase = NodeSysBase;
- MCTPtr->NodeSysLimit = NodeSysLimit;
- RefPtr->SysLimit = NodeSysLimit;
- IDS_OPTION_HOOK (IDS_MEM_SIZE_OVERLAY, NBPtr, &NBPtr->MemPtr->StdHeader);
-
- NBPtr->SharedPtr->TopNode = NBPtr->Node;
-
- NBPtr->SharedPtr->NodeMap[NBPtr->Node].IsValid = TRUE;
- NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysBase = NodeSysBase;
- NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysLimit = NodeSysLimit & 0xFFFFFF00;
-
- MemNSetBitFieldNb (NBPtr, BFDramBaseAddr, NodeSysBase >> (27 - 16));
- MemNSetBitFieldNb (NBPtr, BFDramLimitAddr, NodeSysLimit >> (27 - 16));
-
- if ((MCTPtr->DctData[1].Timings.DctMemSize != 0) && (!NBPtr->Ganged)) {
- MemNSetBitFieldNb (NBPtr, BFDctSelBaseAddr, DctSelBaseAddr >> 11);
- MemNSetBitFieldNb (NBPtr, BFDctSelHiRngEn, 1);
- MemNSetBitFieldNb (NBPtr, BFDctSelHi, 1);
- MemNSetBitFieldNb (NBPtr, BFDctSelBaseOffset, DctSelBaseAddr >> 10);
- }
-
- NBPtr->SharedPtr->CurrentNodeSysBase = (NodeSysLimit + 1) & 0xFFFFFFF0;
- }
- return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * Program system DRAM map to this node
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNSyncAddrMapToAllNodesNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 Node;
- UINT32 NodeSysBase;
- UINT32 NodeSysLimit;
- UINT8 WeReMask;
- MEM_PARAMETER_STRUCT *RefPtr;
-
- RefPtr = NBPtr->RefPtr;
- for (Node = 0; Node < NBPtr->NodeCount; Node++) {
- NodeSysBase = NBPtr->SharedPtr->NodeMap[Node].SysBase;
- NodeSysLimit = NBPtr->SharedPtr->NodeMap[Node].SysLimit;
- if (NBPtr->SharedPtr->NodeMap[Node].IsValid) {
- WeReMask = 3;
- } else {
- WeReMask = 0;
- }
- // Set the Dram base and set the WE and RE flags in the base.
- MemNSetBitFieldNb (NBPtr, BFDramBaseReg0 + Node, (NodeSysBase << 8) | WeReMask);
- MemNSetBitFieldNb (NBPtr, BFDramBaseHiReg0 + Node, NodeSysBase >> 24);
- // Set the Dram limit and set DstNode.
- MemNSetBitFieldNb (NBPtr, BFDramLimitReg0 + Node, (NodeSysLimit << 8) | Node);
- MemNSetBitFieldNb (NBPtr, BFDramLimitHiReg0 + Node, NodeSysLimit >> 24);
-
- if (RefPtr->GStatus[GsbHWHole]) {
- MemNSetBitFieldNb (NBPtr, BFDramMemHoistValid, 1);
- MemNSetBitFieldNb (NBPtr, BFDramHoleBase, (RefPtr->HoleBase >> 8));
- }
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function enables power down mode
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNPowerDownCtlNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MEM_PARAMETER_STRUCT *RefPtr;
- UINT8 PowerDownMode;
-
- RefPtr = NBPtr->RefPtr;
-
- // we can't enable powerdown mode when doing WL
- if (RefPtr->EnablePowerDown) {
- MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 1);
- PowerDownMode = (UINT8) ((UserOptions.CfgPowerDownMode == POWER_DOWN_MODE_AUTO) ? POWER_DOWN_BY_CHANNEL : UserOptions.CfgPowerDownMode);
- IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(NBPtr->MemPtr->StdHeader));
- if (PowerDownMode) {
- MemNSetBitFieldNb (NBPtr, BFPowerDownMode, 1);
- }
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function gets the Optimal Critical Gross Delay Difference between
- * the delay parameters across all Dimms on each bytelane. Then takes the
- * largest of all the bytelanes.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] TrnDly1 - Type of first Gross Delay parameter
- * @param[in] TrnDly2 - Type of second Gross Delay parameter
- *
- * @return The largest difference between the largest and smallest
- * of the two Gross delay types within a single bytelane
- */
-INT8
-MemNGetOptimalCGDDNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN TRN_DLY_TYPE TrnDly1,
- IN TRN_DLY_TYPE TrnDly2
- )
-{
- INT8 CGDD;
- INT8 GDD;
- UINT8 Dimm1;
- UINT8 Dimm2;
- UINT8 ByteLane;
- UINT16 CsEnabled;
- BOOLEAN CGDDInit;
- BOOLEAN SameDelayType;
-
- CGDD = 0;
- CGDDInit = FALSE;
- SameDelayType = (BOOLEAN) (TrnDly1 == TrnDly2);
- CsEnabled = NBPtr->DCTPtr->Timings.CsEnabled;
-
- // If the two delay types compared are the same type, then no need to compare the same
- // pair twice. Adjustments are made in the upper bound and lower bound of the loop to
- // handle this.
- for (Dimm1 = 0; Dimm1 < (SameDelayType ? (MAX_DIMMS_PER_CHANNEL - 1) : MAX_DIMMS_PER_CHANNEL); Dimm1 ++) {
- if (CsEnabled & (UINT16) (3 << (Dimm1 << 1))) {
- for (Dimm2 = (SameDelayType ? (Dimm1 + 1) : 0); Dimm2 < MAX_DIMMS_PER_CHANNEL; Dimm2 ++) {
- if ((CsEnabled & (UINT16) (3 << (Dimm2 << 1)))) {
- for (ByteLane = 0 ; ByteLane < 8 ; ByteLane++) {
- // check each byte lane delay pair
- GDD = (UINT8) (NBPtr->GetTrainDly (NBPtr, TrnDly1, DIMM_BYTE_ACCESS (Dimm1, ByteLane)) >> 5) -
- (UINT8) (NBPtr->GetTrainDly (NBPtr, TrnDly2, DIMM_BYTE_ACCESS (Dimm2, ByteLane)) >> 5);
- // If the 2 delay types to be compared are the same, then keep the absolute difference
- if (SameDelayType && (GDD < 0)) {
- GDD = (-GDD);
- }
-
- // If CGDD is yet to be initialized, initialize it
- // Otherwise, keep the largest difference so far
- CGDD = (!CGDDInit) ? GDD : ((CGDD > GDD) ? CGDD : GDD);
- if (!CGDDInit) {
- CGDDInit = TRUE;
- }
- }
- }
- }
- }
- }
- return CGDD;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function calculates the critical delay difference (CDD)
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] TrnDlyType1 - Type of first Gross Delay parameter
- * @param[in] TrnDlyType2 - Type of second Gross Delay parameter
- * @param[in] SameDimm - CDD of same DIMMs
- * @param[in] DiffDimm - CDD of different DIMMs
- *
- * @return CDD term - in 1/2 MEMCLK
- */
-INT16
-MemNCalcCDDNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN TRN_DLY_TYPE TrnDlyType1,
- IN TRN_DLY_TYPE TrnDlyType2,
- IN BOOLEAN SameDimm,
- IN BOOLEAN DiffDimm
- )
-{
- INT16 CDD;
- INT16 CDDtemp;
- UINT16 TrnDly1;
- UINT16 TrnDly2;
- UINT8 i;
- UINT8 j;
- UINT8 ByteLane;
- UINT16 CsEnabled;
- BOOLEAN SameDlyType;
-
- SameDlyType = (BOOLEAN) (TrnDlyType1 == TrnDlyType2);
- CsEnabled = NBPtr->DCTPtr->Timings.CsEnabled;
- CDD = -32000;
- // If the two delay types compared are the same type, then no need to compare the same
- // pair twice. Adjustments are made in the upper bound and lower bound of the loop to
- // handle this.
- for (i = 0; i < (SameDlyType ? (MAX_DIMMS_PER_CHANNEL - 1) : MAX_DIMMS_PER_CHANNEL); i++) {
- if ((CsEnabled & (UINT16) (3 << (i << 1))) != 0) {
- for (j = SameDlyType ? (i + 1) : 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
- if (((CsEnabled & (UINT16) (3 << (j << 1))) != 0) && ((SameDimm && (i == j)) || (DiffDimm && (i != j)))) {
- for (ByteLane = 0; ByteLane < ((NBPtr->MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8); ByteLane++) {
- /// @todo: Gross delay mask should not be constant.
- TrnDly1 = GetTrainDlyFromHeapNb (NBPtr, TrnDlyType1, DIMM_BYTE_ACCESS (i, ByteLane)) >> 5; // Gross delay only
- TrnDly2 = GetTrainDlyFromHeapNb (NBPtr, TrnDlyType2, DIMM_BYTE_ACCESS (j, ByteLane)) >> 5; // Gross delay only
-
- CDDtemp = TrnDly1 - TrnDly2;
- // If the 2 delay types to be compared are the same, then keep the absolute difference
- if ((SameDlyType) && (CDDtemp < 0)) {
- CDDtemp = (-CDDtemp);
- }
-
- CDD = (CDD < CDDtemp) ? CDDtemp : CDD;
- }
- }
- }
- }
- }
-
- return CDD;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function gets DQS timing from data saved in heap.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] TrnDlyType - type of delay to be set
- * @param[in] Drbn - encoding of Dimm-Rank-Byte-Nibble to be accessed
- * (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding
- *
- * @return value of the target timing.
- */
-UINT16
-GetTrainDlyFromHeapNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN TRN_DLY_TYPE TrnDlyType,
- IN DRBN Drbn
- )
-{
- UINT8 Dimm;
- UINT8 Byte;
- UINT16 TrainDly;
- CH_DEF_STRUCT *ChannelPtr;
- MEM_TECH_BLOCK *TechPtr;
-
- Dimm = DRBN_DIMM (Drbn);
- Byte = DRBN_BYTE (Drbn);
- ChannelPtr = NBPtr->ChannelPtr;
- TechPtr = NBPtr->TechPtr;
-
- ASSERT (Dimm < 4);
- ASSERT (Byte <= ECC_DLY);
-
- switch (TrnDlyType) {
- case AccessRcvEnDly:
- TrainDly = ChannelPtr->RcvEnDlys[Dimm * TechPtr->DlyTableWidth () + Byte];
- break;
- case AccessWrDqsDly:
- TrainDly = ChannelPtr->WrDqsDlys[Dimm * TechPtr->DlyTableWidth () + Byte];
- break;
- case AccessWrDatDly:
- TrainDly = ChannelPtr->WrDatDlys[Dimm * TechPtr->DlyTableWidth () + Byte];
- break;
- case AccessRdDqsDly:
- TrainDly = ChannelPtr->RdDqsDlys[Dimm * TechPtr->DlyTableWidth () + Byte];
- break;
- default:
- TrainDly = 0;
- IDS_ERROR_TRAP;
- }
-
- return TrainDly;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function sets the fixed MTRRs for common legacy ranges.
- * It sets TOP_MEM and TOM2 and some variable MTRRs with WB Uncacheable type.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - An Error value lower than AGESA_FATAL may have occurred
- * @return FALSE - An Error value greater than or equal to AGESA_FATAL may have occurred
- */
-
-BOOLEAN
-MemNCPUMemTypingNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT32 Bottom32bIO;
- UINT32 Bottom40bIO;
- UINT32 Cache32bTOP;
- S_UINT64 SMsr;
-
- MEM_DATA_STRUCT *MemPtr;
- MEM_PARAMETER_STRUCT *RefPtr;
- RefPtr = NBPtr->RefPtr;
- MemPtr = NBPtr->MemPtr;
-
- //
- //======================================================================
- // Set temporary top of memory from Node structure data.
- // Adjust temp top of memory down to accommodate 32-bit IO space.
- //======================================================================
- //Bottom40bIO=top of memory, right justified 16 bits (defines dram versus IO space type)
- //Bottom32bIO=sub 4GB top of memory, right justified 16 bits (defines dram versus IO space type)
- //Cache32bTOP=sub 4GB top of WB cacheable memory, right justified 16 bits
- //
- if (RefPtr->HoleBase != 0) {
- Bottom32bIO = RefPtr->HoleBase;
- } else if (RefPtr->BottomIo != 0) {
- Bottom32bIO = (UINT32)RefPtr->BottomIo << (24 - 16);
- } else {
- Bottom32bIO = (UINT32)1 << (24 - 16);
- }
-
- Cache32bTOP = RefPtr->SysLimit + 1;
- if (Cache32bTOP < _4GB_RJ16) {
- Bottom40bIO = 0;
- if (Bottom32bIO >= Cache32bTOP) {
- Bottom32bIO = Cache32bTOP;
- }
- } else {
- Bottom40bIO = Cache32bTOP;
- }
-
- Cache32bTOP = Bottom32bIO;
-
-
- //
- //======================================================================
- // Set default values for CPU registers
- //======================================================================
- //
- LibAmdMsrRead (SYS_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- SMsr.lo |= 0x1C0000; // turn on modification enable bit and
- // mtrr enable bits
- LibAmdMsrWrite (SYS_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-
- SMsr.lo = SMsr.hi = 0x1E1E1E1E;
- LibAmdMsrWrite (0x250, (UINT64 *)&SMsr, &MemPtr->StdHeader); // 0 - 512K = WB Mem
- LibAmdMsrWrite (0x258, (UINT64 *)&SMsr, &MemPtr->StdHeader); // 512K - 640K = WB Mem
-
- //
- //======================================================================
- // Set variable MTRR values
- //======================================================================
- //
- MemNSetMTRRrangeNb (NBPtr, 0, &Cache32bTOP, 0x200, 6);
-
- RefPtr->Sub4GCacheTop = Cache32bTOP << 16;
-
- //
- //======================================================================
- // Set TOP_MEM and TOM2 CPU registers
- //======================================================================
- //
- SMsr.hi = Bottom32bIO >> (32 - 16);
- SMsr.lo = Bottom32bIO << 16;
- LibAmdMsrWrite (TOP_MEM, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-
- if (Bottom40bIO) {
- SMsr.hi = Bottom40bIO >> (32 - 16);
- SMsr.lo = Bottom40bIO << 16;
- } else {
- SMsr.hi = 0;
- SMsr.lo = 0;
- }
- LibAmdMsrWrite (TOP_MEM2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-
- LibAmdMsrRead (SYS_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- if (Bottom40bIO) {
- // Enable TOM2
- SMsr.lo |= 0x00600000;
- } else {
- // Disable TOM2
- SMsr.lo &= ~0x00600000;
- }
- SMsr.lo &= 0xFFF7FFFF; // turn off modification enable bit
- LibAmdMsrWrite (SYS_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-
- return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function runs on the BSP only, it sets the fixed MTRRs for common legacy ranges.
- * It sets TOP_MEM and TOM2 and some variable MTRRs with WB Uncacheable type.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNUMAMemTypingNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT32 Bottom32bIO;
- UINT32 Bottom32bUMA;
- UINT32 Cache32bTOP;
- UINT32 Value32;
- UINT8 BitCount;
- UINT8 i;
-
- MEM_PARAMETER_STRUCT *RefPtr;
- RefPtr = NBPtr->RefPtr;
- BitCount = 0;
- //
- //======================================================================
- // Adjust temp top of memory down to accommodate UMA memory start
- //======================================================================
- // Bottom32bIO=sub 4GB top of memory, right justified 16 bits (defines dram versus IO space type)
- // Cache32bTOP=sub 4GB top of WB cacheable memory, right justified 16 bits
- //
- Bottom32bIO = RefPtr->Sub4GCacheTop >> 16;
- Bottom32bUMA = RefPtr->UmaBase;
-
- if (Bottom32bUMA < Bottom32bIO) {
- Cache32bTOP = Bottom32bUMA;
- RefPtr->Sub4GCacheTop = Bottom32bUMA << 16;
- //
- //======================================================================
- //Set variable MTRR values
- //======================================================================
- //
- Value32 = Cache32bTOP;
- //Pre-check the bit count of bottom Uma to see if it is potentially running out of Mtrr while typing.
- while (Value32 != 0) {
- i = LibAmdBitScanForward (Value32);
- Value32 &= ~ (1 << i);
- BitCount++;
- }
-
- if (BitCount > 5) {
- NBPtr->RefPtr->GStatus[GsbMTRRshort] = TRUE;
- MemNSetMTRRUmaRegionUCNb (NBPtr, &Cache32bTOP, &Bottom32bIO);
- } else {
- MemNSetMTRRrangeNb (NBPtr, 0, &Cache32bTOP, 0x200, 6);
- }
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * Program MTRRs to describe given range as given cache type. Use MTRR pairs
- * starting with the given MTRRphys Base address, and use as many as is
- * required up to (excluding) MSR 020C, which is reserved for OS.
- *
- * "Limit" in the context of this procedure is not the numerically correct
- * limit, but rather the Last address+1, for purposes of coding efficiency
- * and readability. Size of a region is then Limit-Base.
- *
- * 1. Size of each range must be a power of two
- * 2. Each range must be naturally aligned (Base is same as size)
- *
- * There are two code paths: the ascending path and descending path (analogous
- * to bsf and bsr), where the next limit is a function of the next set bit in
- * a forward or backward sequence of bits (as a function of the Limit). We
- * start with the ascending path, to ensure that regions are naturally aligned,
- * then we switch to the descending path to maximize MTRR usage efficiency.
- * Base=0 is a special case where we start with the descending path.
- * Correct Mask for region is 2comp(Size-1)-1,
- * which is 2comp(Limit-Base-1)-1 *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Base - Base address[47:16] of specified range.
- * @param[in] *LimitPtr - Limit address[47:16] of specified range.
- * @param[in] MtrrAddr - address of var MTRR pair to start using.
- * @param[in] MtrrType - Cache type for the range.
- *
- * @return TRUE - No failure occurred
- * @return FALSE - Failure occurred because run out of variable-size MTRRs before completion.
- */
-
-BOOLEAN
-STATIC
-MemNSetMTRRrangeNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 Base,
- IN OUT UINT32 *LimitPtr,
- IN UINT32 MtrrAddr,
- IN UINT8 MtrrType
- )
-{
- S_UINT64 SMsr;
- UINT32 CurBase;
- UINT32 CurLimit;
- UINT32 CurSize;
- UINT32 CurAddr;
- UINT32 Value32;
-
- CurBase = Base;
- CurLimit = *LimitPtr;
- CurAddr = MtrrAddr;
-
- while ((CurAddr >= 0x200) && (CurAddr < 0x20A) && (CurBase < *LimitPtr)) {
- CurSize = CurLimit = (UINT32)1 << LibAmdBitScanForward (CurBase);
- CurLimit += CurBase;
- if ((CurBase == 0) || (*LimitPtr < CurLimit)) {
- CurLimit = *LimitPtr - CurBase;
- CurSize = CurLimit = (UINT32)1 << LibAmdBitScanReverse (CurLimit);
- CurLimit += CurBase;
- }
-
- // prog. MTRR with current region Base
- SMsr.lo = (CurBase << 16) | (UINT32)MtrrType;
- SMsr.hi = CurBase >> (32 - 16);
- LibAmdMsrWrite (CurAddr, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader);
-
- // prog. MTRR with current region Mask
- CurAddr++; // other half of MSR pair
- Value32 = CurSize - (UINT32)1;
- Value32 = ~Value32;
- SMsr.hi = (Value32 >> (32 - 16)) & NBPtr->VarMtrrHiMsk;
- SMsr.lo = (Value32 << 16) | ((UINT32)1 << MTRR_VALID);
- LibAmdMsrWrite (CurAddr, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader);
-
- CurBase = CurLimit;
- CurAddr++; // next MSR pair
- }
-
- if (CurLimit < *LimitPtr) {
- // Announce failure
- *LimitPtr = CurLimit;
- IDS_ERROR_TRAP;
- }
-
- while ((CurAddr >= 0x200) && (CurAddr < 0x20C)) {
- SMsr.lo = SMsr.hi = 0;
- LibAmdMsrWrite (CurAddr, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader);
- CurAddr++;
- }
-
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * Program one MTRR to describe Uma region as UC cache type if we detect running out of
- * Mtrr circumstance.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] *BasePtr - Base address[47:24] of specified range.
- * @param[in] *LimitPtr - Limit address[47:24] of specified range.
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-BOOLEAN
-MemNSetMTRRUmaRegionUCNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 *BasePtr,
- IN OUT UINT32 *LimitPtr
- )
-{
- S_UINT64 SMsr;
- UINT32 Mtrr;
- UINT32 Size;
- UINT32 Value32;
-
- Size = *LimitPtr - *BasePtr;
- // Check if Size is a power of 2
- if ((Size & (Size - 1)) != 0) {
- for (Mtrr = 0x200; Mtrr < 0x20A; Mtrr += 2) {
- LibAmdMsrRead (Mtrr + 1, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader);
- if ((SMsr.lo & ((UINT32) 1 << 11)) == 0) {
- MemNSetMTRRrangeNb (NBPtr, *BasePtr, LimitPtr, Mtrr, 0);
- break;
- }
- }
- if (Mtrr == 0x20A) {
- // Run out of MTRRs
- IDS_ERROR_TRAP;
- }
- } else {
- Mtrr = 0x20A; //Reserved pair of MTRR for UMA region.
-
- // prog. MTRR with current region Base
- SMsr.lo = *BasePtr << 16;
- SMsr.hi = *BasePtr >> (32 - 16);
- LibAmdMsrWrite (Mtrr, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader);
-
- // prog. MTRR with current region Mask
- Mtrr++; // other half of MSR pair
- Value32 = Size - (UINT32)1;
- Value32 = ~Value32;
- SMsr.hi = (Value32 >> (32 - 16)) & NBPtr->VarMtrrHiMsk;
- SMsr.lo = (Value32 << 16) | ((UINT32)1 << MTRR_VALID);
- LibAmdMsrWrite (Mtrr, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader);
- }
-
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * Report the Uma size that is going to be allocated.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return Uma size [31:0] = Addr [47:16]
- */
-UINT32
-MemNGetUmaSizeNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- return 0;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function allocates 16MB of memory for C6 storage when it is requested to be enabled
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-VOID
-MemNAllocateC6StorageClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT32 SysLimit;
-
- if (IsFeatureEnabled (C6Cstate, NBPtr->MemPtr->PlatFormConfig, &(NBPtr->MemPtr->StdHeader))) {
- SysLimit = NBPtr->RefPtr->SysLimit;
- SysLimit -= _16MB_RJ16;
-
- // Set Dram Limit
- NBPtr->MCTPtr->NodeSysLimit = SysLimit;
- NBPtr->RefPtr->SysLimit = SysLimit;
- MemNSetBitFieldNb (NBPtr, BFDramLimitReg0, ((SysLimit << 8) & 0xFFFF0000));
-
- // Set TOPMEM and MTRRs
- MemNC6AdjustMSRs (NBPtr);
-
- // Set C6Base and C6DramLock
- MemNSetBitFieldNb (NBPtr, BFC6Base, (SysLimit + 1) >> (24 - 16));
- MemNSetBitFieldNb (NBPtr, BFC6DramLock, 1);
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function allocates 16MB of memory for C6 storage when it is requested to be enabled
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-VOID
-MemNAllocateC6StorageUnb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 Node;
- UINT32 SysLimit;
- UINT32 DramLimitReg;
-
- if (NBPtr->SharedPtr->C6Enabled || IsFeatureEnabled (C6Cstate, NBPtr->MemPtr->PlatFormConfig, &(NBPtr->MemPtr->StdHeader))) {
-
- SysLimit = NBPtr->RefPtr->SysLimit;
-
- // Calculate new SysLimit
- if (!NBPtr->SharedPtr->C6Enabled) {
- if (NBPtr->SharedPtr->NodeIntlv.NodeCnt >= 2) {
- // Node Interleave is enabled, system memory available is reduced by 16MB * number of nodes
- SysLimit -= _16MB_RJ16 * NBPtr->SharedPtr->NodeIntlv.NodeCnt;
- } else {
- // Otherwise, system memory available is reduced by 16MB
- SysLimit -= _16MB_RJ16;
- }
- NBPtr->RefPtr->SysLimit = SysLimit;
- NBPtr->SharedPtr->C6Enabled = TRUE;
-
- // Set TOPMEM and MTRRs (only need to be done once for BSC)
- MemNC6AdjustMSRs (NBPtr);
- }
-
- // Set Dram Limit
- if (NBPtr->SharedPtr->NodeIntlv.NodeCnt >= 2) {
- for (Node = 0; Node < NBPtr->NodeCount; Node++) {
- DramLimitReg = MemNGetBitFieldNb (NBPtr, BFDramLimitReg0 + Node);
- if ((DramLimitReg & 0xFFFF0000) != 0) {
- MemNSetBitFieldNb (NBPtr, BFDramLimitReg0 + Node, ((SysLimit << 8) & 0xFFFF0000) | (DramLimitReg & 0xFFFF));
- MemNSetBitFieldNb (NBPtr, BFDramLimitHiReg0 + Node, SysLimit >> 24);
- }
- }
- // Node Interleave is enabled, CoreStateSaveDestNode points to its own node
- MemNSetBitFieldNb (NBPtr, BFCoreStateSaveDestNode, NBPtr->Node);
- NBPtr->MCTPtr->NodeSysLimit = SysLimit;
- } else {
- DramLimitReg = MemNGetBitFieldNb (NBPtr, BFDramLimitReg0 + NBPtr->SharedPtr->TopNode) & 0x0000FFFF;
- MemNSetBitFieldNb (NBPtr, BFDramLimitReg0 + NBPtr->SharedPtr->TopNode, ((SysLimit << 8) & 0xFFFF0000) | DramLimitReg);
- MemNSetBitFieldNb (NBPtr, BFDramLimitHiReg0 + NBPtr->SharedPtr->TopNode, SysLimit >> 24);
-
- // Node Interleave is not enabled, CoreStateSaveDestNode points to the node that contains top memory
- MemNSetBitFieldNb (NBPtr, BFCoreStateSaveDestNode, NBPtr->SharedPtr->TopNode);
-
- if (NBPtr->Node == NBPtr->SharedPtr->TopNode) {
- NBPtr->MCTPtr->NodeSysLimit = SysLimit;
- }
- }
-
- // Set CoreStateSaveDestNode and LockDramCfg
- MemNSetBitFieldNb (NBPtr, BFLockDramCfg, 1);
- MemNSetBitFieldNb (NBPtr, BFCC6SaveEn, 1);
- }
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function readjusts TOPMEM and MTRRs after allocating storage for C6
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-VOID
-STATIC
-MemNC6AdjustMSRs (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT32 SysLimit;
- UINT32 CurAddr;
- S_UINT64 SMsr;
-
- SysLimit = NBPtr->RefPtr->SysLimit + 1;
- SMsr.hi = SysLimit >> (32 - 16);
- SMsr.lo = SysLimit << 16;
- if (SysLimit < _4GB_RJ16) {
- LibAmdMsrWrite (TOP_MEM, (UINT64 *)&SMsr, &(NBPtr->MemPtr->StdHeader));
- // If there is no UMA buffer, then set top of cache and MTRR.
- // Otherwise, top of cache and MTRR will be set when UMA buffer is set up.
- if (NBPtr->RefPtr->UmaMode == UMA_NONE) {
- NBPtr->RefPtr->Sub4GCacheTop = (SysLimit << 16);
- // Find unused MTRR to set C6 region to UC
- for (CurAddr = 0x200; CurAddr < 0x20C; CurAddr += 2) {
- LibAmdMsrRead (CurAddr + 1, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader);
- if ((SMsr.lo & ((UINT32) 1 << 11)) == 0) {
- // Set region base as TOM
- SMsr.hi = SysLimit >> (32 - 16);
- SMsr.lo = SysLimit << 16;
- LibAmdMsrWrite (CurAddr, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader);
-
- // set region mask to 16MB
- SMsr.hi = NBPtr->VarMtrrHiMsk;
- SMsr.lo = 0xFF000800;
- LibAmdMsrWrite (CurAddr + 1, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader);
-
- break;
- }
- }
- }
- } else {
- LibAmdMsrWrite (TOP_MEM2, (UINT64 *)&SMsr, &(NBPtr->MemPtr->StdHeader));
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Family-specific hook to override the DdrMaxRate value for families with a
- * non-GH-compatible encoding for BFDdrMaxRate
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *DdrMaxRate - Void pointer to DdrMaxRate. Used as INT16.
- *
- * @return TRUE
- *
- */
-BOOLEAN
-MemNGetMaxDdrRateUnb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN VOID *DdrMaxRate
- )
-{
-
- * (UINT16 * ) DdrMaxRate = MemNGetMemClkFreqUnb (NBPtr, (UINT8) MemNGetBitFieldNb (NBPtr, BFDdrMaxRate));
- return TRUE;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/mnphy.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/mnphy.c
deleted file mode 100644
index bcf2f6e..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/mnphy.c
+++ /dev/null
@@ -1,1377 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnphy.c
- *
- * Common Northbridge Phy support
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB)
- * @e \$Revision: 38306 $ @e \$Date: 2010-09-22 01:51:51 +0800 (Wed, 22 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mport.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mu.h"
-#include "PlatformMemoryConfiguration.h"
-#include "heapManager.h"
-#include "merrhdl.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-#define FILECODE PROC_MEM_NB_MNPHY_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define UNUSED_CLK 4
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-/// Type of an entry for processing phy init compensation for client NB
-typedef struct {
- BIT_FIELD_NAME IndexBitField; ///< Bit field on which the value is decided
- BIT_FIELD_NAME StartTargetBitField; ///< First bit field to be modified
- BIT_FIELD_NAME EndTargetBitField; ///< Last bit field to be modified
- UINT16 ExtraValue; ///< Extra value needed to be written to bit field
- CONST UINT16 (*TxPrePN)[3][5]; ///< Pointer to slew rate table
-} PHY_COMP_INIT_CLIENTNB;
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function gets a delay value a PCI register during training
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] TrnDly - type of delay to be set
- * @param[in] DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed
- * (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding
- *
- * @return Value read
- */
-
-UINT32
-MemNGetTrainDlyNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN TRN_DLY_TYPE TrnDly,
- IN DRBN DrbnVar
- )
-{
- return NBPtr->MemNcmnGetSetTrainDly (NBPtr, 0, TrnDly, DrbnVar, 0);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function sets a delay value a PCI register during training
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] TrnDly - type of delay to be set
- * @param[in] DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed
- * (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding
- * @param[in] Field - Value to be programmed
- *
- */
-
-VOID
-MemNSetTrainDlyNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN TRN_DLY_TYPE TrnDly,
- IN DRBN DrbnVar,
- IN UINT16 Field
- )
-{
- NBPtr->MemNcmnGetSetTrainDly (NBPtr, 1, TrnDly, DrbnVar, Field);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function executes prototypical Phy fence training function.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNPhyFenceTrainingNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- NBPtr->MemPPhyFenceTrainingNb (NBPtr);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function executes prototypical Phy fence training function.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNPhyFenceTrainingUnb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 FenceThresholdTxDll;
- UINT8 FenceThresholdRxDll;
- UINT8 FenceThresholdTxPad;
- UINT16 Fence2Data;
-
- // 1. Program D18F2x[1,0]9C_x0000_0008[FenceTrSel]=10b.
- // 2. Perform phy fence training.
- // 3. Write the calculated fence value to D18F2x[1,0]9C_x0000_000C[FenceThresholdTxDll].
- MemNSetBitFieldNb (NBPtr, BFFenceTrSel, 2);
- MAKE_TSEFO (NBPtr->NBRegTable, DCT_PHY_ACCESS, 0x0C, 30, 26, BFPhyFence);
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\tFenceThresholdTxDll\n");
- MemNTrainPhyFenceNb (NBPtr);
- FenceThresholdTxDll = (UINT8) MemNGetBitFieldNb (NBPtr, BFPhyFence);
- NBPtr->FamilySpecificHook[DetectMemPllError] (NBPtr, &FenceThresholdTxDll);
-
- // 4. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]0F[AlwaysEnDllClks]=001b.
- MemNSetBitFieldNb (NBPtr, BFAlwaysEnDllClks, 0x1000);
-
- // 5. Program D18F2x[1,0]9C_x0000_0008[FenceTrSel]=01b.
- // 6. Perform phy fence training.
- // 7. Write the calculated fence value to D18F2x[1,0]9C_x0000_000C[FenceThresholdRxDll].
- MemNSetBitFieldNb (NBPtr, BFFenceTrSel, 1);
- MAKE_TSEFO (NBPtr->NBRegTable, DCT_PHY_ACCESS, 0x0C, 25, 21, BFPhyFence);
- IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tFenceThresholdRxDll\n");
- MemNTrainPhyFenceNb (NBPtr);
- FenceThresholdRxDll = (UINT8) MemNGetBitFieldNb (NBPtr, BFPhyFence);
- NBPtr->FamilySpecificHook[DetectMemPllError] (NBPtr, &FenceThresholdRxDll);
-
- // 8. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]0F[AlwaysEnDllClks]=000b.
- MemNSetBitFieldNb (NBPtr, BFAlwaysEnDllClks, 0x0000);
-
- // 9. Program D18F2x[1,0]9C_x0000_0008[FenceTrSel]=11b.
- // 10. Perform phy fence training.
- // 11. Write the calculated fence value to D18F2x[1,0]9C_x0000_000C[FenceThresholdTxPad].
- MemNSetBitFieldNb (NBPtr, BFFenceTrSel, 3);
- MAKE_TSEFO (NBPtr->NBRegTable, DCT_PHY_ACCESS, 0x0C, 20, 16, BFPhyFence);
- IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tFenceThresholdTxPad\n");
- MemNTrainPhyFenceNb (NBPtr);
- FenceThresholdTxPad = (UINT8) MemNGetBitFieldNb (NBPtr, BFPhyFence);
- NBPtr->FamilySpecificHook[DetectMemPllError] (NBPtr, &FenceThresholdTxPad);
-
- // Program Fence2 threshold for Clk, Cmd, and Addr
- if (FenceThresholdTxPad < 16) {
- MemNSetBitFieldNb (NBPtr, BFClkFence2, FenceThresholdTxPad | 0x10);
- MemNSetBitFieldNb (NBPtr, BFCmdFence2, FenceThresholdTxPad | 0x10);
- MemNSetBitFieldNb (NBPtr, BFAddrFence2, FenceThresholdTxPad | 0x10);
- } else {
- MemNSetBitFieldNb (NBPtr, BFClkFence2, 0);
- MemNSetBitFieldNb (NBPtr, BFCmdFence2, 0);
- MemNSetBitFieldNb (NBPtr, BFAddrFence2, 0);
- }
-
- // Program Fence2 threshold for data
- Fence2Data = 0;
- if (FenceThresholdTxPad < 16) {
- Fence2Data |= FenceThresholdTxPad | 0x10;
- }
- if (FenceThresholdRxDll < 16) {
- Fence2Data |= (FenceThresholdRxDll | 0x10) << 10;
- }
- if (FenceThresholdTxDll < 16) {
- Fence2Data |= (FenceThresholdTxDll | 0x10) << 5;
- }
- MemNSetBitFieldNb (NBPtr, BFDataFence2, Fence2Data);
-
- if (NBPtr->MCTPtr->Status[SbLrdimms]) {
- // 18. If motherboard routing requires CS[7:6] to adopt address timings, e.g. 3 LRDIMMs/ch with CS[7:6]
- // routed across all DIMM sockets, BIOS performs the following:
- if (FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_NO_LRDIMM_CS67_ROUTING, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID) != NULL) {
- // A. Program D18F2xA8_dct[1:0][CSTimingMux67] = 1.
- MemNSetBitFieldNb (NBPtr, BFCSTimingMux67, 1);
- // B. Program D18F2x9C_x0D0F_8021_dct[1:0]:
- // - DiffTimingEn = 1.
- // - IF (D18F2x9C_x0000_0004_dct[1:0][AddrCmdFineDelay] >=
- // D18F2x9C_x0D0F_E008_dct[1:0][FenceValue]) THEN Fence = 1 ELSE Fence = 0.
- // - Delay = D18F2x9C_x0000_0004_dct[1:0][AddrCmdFineDelay].
- //
- MemNSetBitFieldNb (NBPtr, BFDiffTimingEn, 1);
- MemNSetBitFieldNb (NBPtr, BFFence, (MemNGetBitFieldNb (NBPtr, BFAddrCmdFineDelay) >= MemNGetBitFieldNb (NBPtr, BFFenceValue)) ? 1 : 0);
- MemNSetBitFieldNb (NBPtr, BFDelay, (MemNGetBitFieldNb (NBPtr, BFAddrCmdFineDelay)));
- }
- }
-
- // 19. Reprogram F2x9C_04.
- MemNSetBitFieldNb (NBPtr, BFAddrTmgControl, MemNGetBitFieldNb (NBPtr, BFAddrTmgControl));
-
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function executes Phy fence training
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNTrainPhyFenceNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 Byte;
- UINT16 Avg;
- UINT8 PREvalue;
-
- if (MemNGetBitFieldNb (NBPtr, BFDisDramInterface)) {
- return;
- }
-
- // 1. BIOS first programs a seed value to the phase recovery
- // engine registers.
- //
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\tSeeds: ");
- for (Byte = 0; Byte < MAX_BYTELANES_PER_CHANNEL; Byte++) {
- // This includes ECC as byte 8
- MemNSetTrainDlyNb (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (0, Byte), 19);
- IDS_HDT_CONSOLE (MEM_FLOW, "%02x ", 19);
- }
-
- IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tPhyFenceTrEn = 1");
- // 2. Set F2x[1, 0]9C_x08[PhyFenceTrEn]=1.
- MemNSetBitFieldNb (NBPtr, BFPhyFenceTrEn, 1);
-
- if (!NBPtr->IsSupported[UnifiedNbFence]) {
- // 3. Wait 200 MEMCLKs.
- MemNWaitXMemClksNb (NBPtr, 200);
- } else {
- // 3. Wait 2000 MEMCLKs.
- MemNWaitXMemClksNb (NBPtr, 2000);
- }
-
- // 4. Clear F2x[1, 0]9C_x08[PhyFenceTrEn]=0.
- MemNSetBitFieldNb (NBPtr, BFPhyFenceTrEn, 0);
-
- // 5. BIOS reads the phase recovery engine registers
- // F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52.
- // 6. Calculate the average value of the fine delay and subtract 8.
- //
- Avg = 0;
- IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t PRE: ");
- for (Byte = 0; Byte < MAX_BYTELANES_PER_CHANNEL; Byte++) {
- //
- // This includes ECC as byte 8. ECC Byte lane (8) is ignored by MemNGetTrainDlyNb function where
- // ECC is not supported.
- //
- PREvalue = (UINT8) (0x1F & MemNGetTrainDlyNb (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (0, Byte)));
- Avg = Avg + ((UINT16) PREvalue);
- IDS_HDT_CONSOLE (MEM_FLOW, "%02x ", PREvalue);
- }
- Avg = ((Avg + 8) / 9); // round up
-
- Avg -= 8;
- NBPtr->MemNPFenceAdjustNb (NBPtr, &Avg);
-
- IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tFence: %02x\n", Avg);
-
- // 7. Write the value to F2x[1, 0]9C_x0C[PhyFence].
- MemNSetBitFieldNb (NBPtr, BFPhyFence, Avg);
-
- // 8. BIOS rewrites F2x[1, 0]9C_x04, DRAM Address/Command Timing Control
- // Register delays for both channels. This forces the phy to recompute
- // the fence.
- //
- MemNSetBitFieldNb (NBPtr, BFAddrTmgControl, MemNGetBitFieldNb (NBPtr, BFAddrTmgControl));
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the DDR phy compensation logic
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNInitPhyCompNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- CONST UINT8 TableCompRiseSlew20x[] = {7, 3, 2, 2};
- CONST UINT8 TableCompRiseSlew15x[] = {7, 7, 3, 2};
- CONST UINT8 TableCompFallSlew20x[] = {7, 5, 3, 2};
- CONST UINT8 TableCompFallSlew15x[] = {7, 7, 5, 3};
- UINT8 i;
- UINT8 j;
- UINT8 CurrDct;
- UINT8 CurrChannel;
- BOOLEAN MarginImprv;
- MarginImprv = FALSE;
- CurrDct = NBPtr->Dct;
- CurrChannel = NBPtr->Channel;
- if (NBPtr->IsSupported[CheckSlewWithMarginImprv]) {
- if (NBPtr->MCTPtr->GangedMode == FALSE) {
- for (i = 0; i < NBPtr->DctCount; i++) {
- MemNSwitchDCTNb (NBPtr, i);
- for (j = 0; j < NBPtr->ChannelCount; j++) {
- NBPtr->SwitchChannel (NBPtr, j);
- if ((NBPtr->ChannelPtr->Dimms == 4) && ((NBPtr->DCTPtr->Timings.Speed == DDR533_FREQUENCY) || (NBPtr->DCTPtr->Timings.Speed == DDR667_FREQUENCY))) {
- MarginImprv = TRUE;
- }
- }
- }
- MemNSwitchDCTNb (NBPtr, CurrDct);
- NBPtr->SwitchChannel (NBPtr, CurrChannel);
- }
- }
-
- // 1. BIOS disables the phy compensation register by programming F2x9C_x08[DisAutoComp]=1
- // 2. BIOS waits 5 us for the disabling of the compensation engine to complete.
- // DisAutoComp will be cleared after Dram init has completed
- //
- MemNSwitchDCTNb (NBPtr, 0);
- MemNSetBitFieldNb (NBPtr, BFDisAutoComp, 1);
- MemUWait10ns (500, NBPtr->MemPtr);
- MemNSwitchDCTNb (NBPtr, CurrDct);
-
- // 3. For each normalized driver strength code read from
- // F2x[1, 0]9C_x00[AddrCmdDrvStren], program the
- // corresponding 3 bit predriver code in F2x9C_x0A[D3Cmp1NCal, D3Cmp1PCal].
- //
- // 4. For each normalized driver strength code read from
- // F2x[1, 0]9C_x00[DataDrvStren], program the corresponding
- // 3 bit predriver code in F2x9C_x0A[D3Cmp0NCal, D3Cmp0PCal, D3Cmp2NCal,
- // D3Cmp2PCal].
- //
- j = (UINT8) MemNGetBitFieldNb (NBPtr, BFAddrCmdDrvStren);
- i = (UINT8) MemNGetBitFieldNb (NBPtr, BFDataDrvStren);
-
- MemNSwitchDCTNb (NBPtr, 0);
- MemNSetBitFieldNb (NBPtr, BFD3Cmp1NCal, TableCompRiseSlew20x[j]);
- MemNSetBitFieldNb (NBPtr, BFD3Cmp1PCal, TableCompFallSlew20x[j]);
-
- if (NBPtr->IsSupported[CheckSlewWithMarginImprv]) {
- MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, (MarginImprv) ? 0 : TableCompRiseSlew15x[i]);
- MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, (MarginImprv) ? 0 : TableCompFallSlew15x[i]);
- MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, (MarginImprv) ? 0 : TableCompRiseSlew15x[i]);
- MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, (MarginImprv) ? 0 : TableCompFallSlew15x[i]);
- }
- if (NBPtr->IsSupported[CheckSlewWithoutMarginImprv]) {
- ASSERT (i <= 3);
- MemNSetBitFieldNb (NBPtr, BFD3Cmp0NCal, TableCompRiseSlew15x[i]);
- MemNSetBitFieldNb (NBPtr, BFD3Cmp0PCal, TableCompFallSlew15x[i]);
- MemNSetBitFieldNb (NBPtr, BFD3Cmp2NCal, TableCompRiseSlew15x[i]);
- MemNSetBitFieldNb (NBPtr, BFD3Cmp2PCal, TableCompFallSlew15x[i]);
- }
- MemNSwitchDCTNb (NBPtr, CurrDct);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This is a general purpose function that executes before DRAM training
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNBeforeDQSTrainingNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 Dct;
- UINT8 ChipSel;
- UINT32 TestAddrRJ16;
- UINT32 RealAddr;
-
- MemTBeginTraining (NBPtr->TechPtr);
-
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- MemNSwitchDCTNb (NBPtr, Dct);
- if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
- for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) {
- if (MemNGetMCTSysAddrNb (NBPtr, ChipSel, &TestAddrRJ16)) {
-
- RealAddr = MemUSetUpperFSbase (TestAddrRJ16, NBPtr->MemPtr);
-
- MemUDummyCLRead (RealAddr);
-
- MemNSetBitFieldNb (NBPtr, BFErr350, 0x8000);
- MemUWait10ns (60, NBPtr->MemPtr); // Wait 300ns
- MemNSetBitFieldNb (NBPtr, BFErr350, 0x0000);
- MemUWait10ns (400, NBPtr->MemPtr); // Wait 2us
- MemUProcIOClFlush (TestAddrRJ16, 1, NBPtr->MemPtr);
- break;
- }
- }
- }
- if (NBPtr->IsSupported[CheckEccDLLPwrDnConfig]) {
- if (!NBPtr->MCTPtr->Status[SbEccDimms]) {
- MemNSetBitFieldNb (NBPtr, BFEccDLLPwrDnConf, 0x0010);
- }
- if (NBPtr->DCTPtr->Timings.Dimmx4Present == 0) {
- MemNSetBitFieldNb (NBPtr, BFEccDLLConf, 0x0080);
- }
- }
- }
-
- MemTEndTraining (NBPtr->TechPtr);
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- *
- * Returns the parameters for a requested delay value to be used in training
- * The correct Min, Max and Mask are determined based on the type of Delay,
- * and the frequency
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] TrnDly - Type of delay
- * @param[in,out] *Parms - Pointer to the TRN_DLY-PARMS struct
- *
- */
-
-VOID
-MemNGetTrainDlyParmsNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN TRN_DLY_TYPE TrnDly,
- IN OUT TRN_DLY_PARMS *Parms
- )
-{
- Parms->Min = 0;
-
- if (TrnDly == AccessWrDatDly) {
- Parms->Max = 0x1F;
- Parms->Mask = 0x01F;
- } else if (TrnDly == AccessRdDqsDly) {
- if ( (NBPtr->IsSupported[CheckMaxRdDqsDlyPtr]) && (NBPtr->DCTPtr->Timings.Speed > DDR667_FREQUENCY) ) {
- Parms->Max = 0x3E;
- Parms->Mask = 0x03E;
- } else {
- Parms->Max = 0x1F;
- Parms->Mask = 0x01F;
- }
- }
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- *
- * Returns the parameters for a requested delay value to be used in training
- * The correct Min, Max and Mask are determined based on the type of Delay,
- * and the frequency
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] TrnDly - Type of delay
- * @param[in,out] *Parms - Pointer to the TRN_DLY-PARMS struct
- *
- */
-
-VOID
-MemNGetTrainDlyParmsClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN TRN_DLY_TYPE TrnDly,
- IN OUT TRN_DLY_PARMS *Parms
- )
-{
- Parms->Min = 0;
-
- if (TrnDly == AccessWrDatDly) {
- Parms->Max = 0x1F;
- Parms->Mask = 0x01F;
- } else if (TrnDly == AccessRdDqsDly) {
- Parms->Max = 0x3E;
- Parms->Mask = 0x03E;
- }
-}
-/*-----------------------------------------------------------------------------*/
-/**
- *
- * Returns the parameters for a requested delay value to be used in training
- * The correct Min, Max and Mask are determined based on the type of Delay,
- * and the frequency
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] TrnDly - Type of delay
- * @param[in,out] *Parms - Pointer to the TRN_DLY-PARMS struct
- *
- */
-
-VOID
-MemNGetTrainDlyParmsUnb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN TRN_DLY_TYPE TrnDly,
- IN OUT TRN_DLY_PARMS *Parms
- )
-{
- Parms->Min = 0;
-
- if (TrnDly == AccessWrDatDly) {
- Parms->Max = 0x1F;
- Parms->Mask = 0x01F;
- } else if (TrnDly == AccessRdDqsDly) {
- Parms->Max = 0x1F;
- Parms->Mask = 0x01F;
- }
-}
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function gets or set DQS timing during training.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] TrnDly - type of delay to be set
- * @param[in] DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed
- * (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding
- * @param[in] Field - Value to be programmed
- * @param[in] IsSet - Indicates if the function will set or get
- *
- * @return value read, if the function is used as a "get"
- */
-
-UINT32
-MemNcmnGetSetTrainDlyNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN TRN_DLY_TYPE TrnDly,
- IN DRBN DrbnVar,
- IN UINT16 Field
- )
-{
- UINT16 Index;
- UINT16 Offset;
- UINT32 Value;
- UINT32 Address;
- UINT8 Dimm;
- UINT8 Rank;
- UINT8 Byte;
- UINT8 Nibble;
-
- Dimm = DRBN_DIMM (DrbnVar);
- Rank = DRBN_RANK (DrbnVar);
- Byte = DRBN_BYTE (DrbnVar);
- Nibble = DRBN_NBBL (DrbnVar);
-
- ASSERT (Dimm < 4);
- ASSERT (Byte <= ECC_DLY);
-
- switch (TrnDly) {
- case AccessRcvEnDly:
- Index = 0x10;
- break;
- case AccessWrDqsDly:
- Index = 0x30;
- break;
- case AccessWrDatDly:
- Index = 0x01;
- break;
- case AccessRdDqsDly:
- Index = 0x05;
- break;
- case AccessPhRecDly:
- Index = 0x50;
- break;
- default:
- Index = 0;
- IDS_ERROR_TRAP;
- }
-
- switch (TrnDly) {
- case AccessRcvEnDly:
- case AccessWrDqsDly:
- Index += (Dimm * 3);
- if (Byte & 0x04) {
- // if byte 4,5,6,7
- Index += 0x10;
- }
- if (Byte & 0x02) {
- // if byte 2,3,6,7
- Index++;
- }
- if (Byte > 7) {
- Index += 2;
- }
- Offset = 16 * (Byte % 2);
- Index |= (Rank << 8);
- Index |= (Nibble << 9);
- break;
-
- case AccessRdDqsDly:
- case AccessWrDatDly:
-
- if (NBPtr->IsSupported[DimmBasedOnSpeed]) {
- if (NBPtr->DCTPtr->Timings.Speed < DDR800_FREQUENCY) {
- // if DDR speed is below 800, use DIMM 0 delays for all DIMMs.
- Dimm = 0;
- }
- }
-
- Index += (Dimm * 0x100);
- if (Nibble) {
- if (Rank) {
- Index += 0xA0;
- } else {
- Index += 0x70;
- }
- } else if (Rank) {
- Index += 0x60;
- }
- // break is not being used here because AccessRdDqsDly and AccessWrDatDly also need
- // to run AccessPhRecDly sequence.
- case AccessPhRecDly:
- Index += (Byte / 4);
- Offset = 8 * (Byte % 4);
- break;
- default:
- Offset = 0;
- IDS_ERROR_TRAP;
- }
-
- Address = Index;
- MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
- MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
- Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
-
- if (TrnDly == AccessRdDqsDly) {
- NBPtr->FamilySpecificHook[AdjustRdDqsDlyOffset] (NBPtr, &Offset);
- }
-
- if (IsSet) {
- if (TrnDly == AccessPhRecDly) {
- Value = NBPtr->DctCachePtr->PhRecReg[Index & 0x03];
- }
-
- Value = ((UINT32)Field << Offset) | (Value & (~((UINT32) ((TrnDly == AccessRcvEnDly) ? 0x1FF : 0xFF) << Offset)));
- MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
- Address |= DCT_ACCESS_WRITE;
- MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
- MemNPollBitFieldNb (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, FALSE);
-
- if (TrnDly == AccessPhRecDly) {
- NBPtr->DctCachePtr->PhRecReg[Index & 0x03] = Value;
- }
- } else {
- Value = (Value >> Offset) & (UINT32) ((TrnDly == AccessRcvEnDly) ? 0x1FF : 0xFF);
- }
-
- return Value;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function gets or set DQS timing during training.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] IsSet - Indicates if the function will set or get
- * @param[in] TrnDly - type of delay to be set
- * @param[in] DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed
- * (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding
- * @param[in] Field - Value to be programmed
- *
- * @return value read, if the function is used as a "get"
- */
-UINT32
-MemNcmnGetSetTrainDlyClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN TRN_DLY_TYPE TrnDly,
- IN DRBN DrbnVar,
- IN UINT16 Field
- )
-{
- UINT16 Index;
- UINT16 Offset;
- UINT32 Value;
- UINT32 Address;
- UINT8 Dimm;
- UINT8 Byte;
-
- Dimm = DRBN_DIMM (DrbnVar);
- Byte = DRBN_BYTE (DrbnVar);
-
- ASSERT (Dimm < 2);
- ASSERT (Byte <= ECC_DLY);
-
- if ((Byte > 7)) {
- // Llano does not support ECC delay, so:
- if (IsSet) {
- // On write, ignore
- return 0;
- } else {
- // On read, redirect to byte 0 to correct fence averaging
- Byte = 0;
- }
- }
-
- switch (TrnDly) {
- case AccessRcvEnDly:
- Index = 0x10;
- break;
- case AccessWrDqsDly:
- Index = 0x30;
- break;
- case AccessWrDatDly:
- Index = 0x01;
- break;
- case AccessRdDqsDly:
- Index = 0x05;
- break;
- case AccessPhRecDly:
- Index = 0x50;
- break;
- default:
- Index = 0;
- IDS_ERROR_TRAP;
- }
-
- switch (TrnDly) {
- case AccessRcvEnDly:
- case AccessWrDqsDly:
- Index += (Dimm * 3);
- if (Byte & 0x04) {
- // if byte 4,5,6,7
- Index += 0x10;
- }
- if (Byte & 0x02) {
- // if byte 2,3,6,7
- Index++;
- }
- Offset = 16 * (Byte % 2);
- break;
-
- case AccessRdDqsDly:
- case AccessWrDatDly:
- Index += (Dimm * 0x100);
- // break is not being used here because AccessRdDqsDly and AccessWrDatDly also need
- // to run AccessPhRecDly sequence.
- case AccessPhRecDly:
- Index += (Byte / 4);
- Offset = 8 * (Byte % 4);
- break;
- default:
- Offset = 0;
- IDS_ERROR_TRAP;
- }
-
- Address = Index;
- MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
- Value = MemNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
-
- if (IsSet) {
- if (TrnDly == AccessPhRecDly) {
- Value = NBPtr->DctCachePtr->PhRecReg[Index & 0x03];
- }
-
- Value = ((UINT32)Field << Offset) | (Value & (~((UINT32) ((TrnDly == AccessRcvEnDly) ? 0x1FF : 0xFF) << Offset)));
- MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
- Address |= DCT_ACCESS_WRITE;
- MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
-
- if (TrnDly == AccessPhRecDly) {
- NBPtr->DctCachePtr->PhRecReg[Index & 0x03] = Value;
- }
- // Gross WrDatDly and WrDqsDly cannot be larger than 4
- ASSERT (((TrnDly == AccessWrDatDly) || (TrnDly == AccessWrDqsDly)) ? (Field < 0xA0) : TRUE);
- } else {
- Value = (Value >> Offset) & (UINT32) ((TrnDly == AccessRcvEnDly) ? 0x1FF : 0xFF);
- }
-
- return Value;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initializes the training pattern.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return AGESA_STATUS - Result
- * AGESA_SUCCESS - Training pattern is ready to use
- * AGESA_ERROR - Unable to initialize the pattern.
- */
-
-AGESA_STATUS
-MemNTrainingPatternInitNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MEM_TECH_BLOCK *TechPtr;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
- TRAIN_PATTERN TrainPattern;
- AGESA_STATUS Status;
-
- TechPtr = NBPtr->TechPtr;
- TrainPattern = 0;
- //
- // Check the training type
- //
- if (TechPtr->TrainingType == TRN_DQS_POSITION) {
- //
- // DQS Position Training
- //
- if (NBPtr->PosTrnPattern == POS_PATTERN_256B) {
- //
- // 256 Bit pattern
- //
- if (NBPtr->MCTPtr->Status[Sb128bitmode]) {
- TrainPattern = TestPatternJD256B;
- TechPtr->PatternLength = 64;
- } else {
- TrainPattern = TestPatternJD256A;
- TechPtr->PatternLength = 32;
- }
- } else {
- //
- // 72 bit pattern will be used if PosTrnPattern is not specified
- //
- if (NBPtr->MCTPtr->Status[Sb128bitmode]) {
- TrainPattern = TestPatternJD1B;
- TechPtr->PatternLength = 18;
- } else {
- TrainPattern = TestPatternJD1A;
- TechPtr->PatternLength = 9;
- }
- }
- } else if (TechPtr->TrainingType == TRN_MAX_READ_LATENCY) {
- //
- // Max Read Latency Training
- //
- TrainPattern = TestPatternML;
- TechPtr->PatternLength = (NBPtr->MCTPtr->Status[Sb128bitmode]) ? 6 : 3;
- } else {
- //
- // Error - TechPtr->Training Type must be set to one of the types handled in this function
- //
- ASSERT (FALSE);
- }
- //
- // Allocate training buffer
- //
- AllocHeapParams.RequestedBufferSize = (TechPtr->PatternLength * 64 * 2) + 16;
- AllocHeapParams.BufferHandle = AMD_MEM_TRAIN_BUFFER_HANDLE;
- AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
- Status = HeapAllocateBuffer (&AllocHeapParams, &NBPtr->MemPtr->StdHeader);
- ASSERT (Status == AGESA_SUCCESS);
- if (Status != AGESA_SUCCESS) {
- return Status;
- }
- TechPtr->PatternBufPtr = AllocHeapParams.BufferPtr;
- AlignPointerTo16Byte (&TechPtr->PatternBufPtr);
- TechPtr->TestBufPtr = TechPtr->PatternBufPtr + (TechPtr->PatternLength * 64);
-
- // Prepare training pattern
- MemUFillTrainPattern (TrainPattern, TechPtr->PatternBufPtr, TechPtr->PatternLength * 64);
-
- return Status;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function determined the settings for the Reliable Read/Write engine
- * for each specific type of training
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] *OptParam - Pointer to an Enum of TRAINING_TYPE
- *
- * @return TRUE
- */
-
-BOOLEAN
-MemNSetupHwTrainingEngineUnb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN VOID *OptParam
- )
-{
- TRAINING_TYPE TrnType;
- RRW_SETTINGS *Rrw;
-
- TrnType = *(TRAINING_TYPE*) OptParam;
- Rrw = &NBPtr->RrwSettings;
- //
- // Common Settings
- //
- Rrw->TgtBankAddressA = CPG_BANK_ADDRESS_A;
- Rrw->TgtRowAddressA = CPG_ROW_ADDRESS_A;
- Rrw->TgtColAddressA = CPG_COL_ADDRESS_A;
- Rrw->TgtBankAddressB = CPG_BANK_ADDRESS_B;
- Rrw->TgtRowAddressB = CPG_ROW_ADDRESS_B;
- Rrw->TgtColAddressB = CPG_COL_ADDRESS_B;
- Rrw->CompareMaskHigh = CPG_COMPARE_MASK_HI;
- Rrw->CompareMaskLow = CPG_COMPARE_MASK_LOW;
- Rrw->CompareMaskEcc = CPG_COMPARE_MASK_ECC;
-
- switch (TrnType) {
- case TRN_RCVR_ENABLE:
- //
- // Receiver Enable Training
- //
- NBPtr->TechPtr->PatternLength = 192;
- break;
- case TRN_MAX_READ_LATENCY:
- //
- // Max Read Latency Training
- //
- Rrw->CmdTgt = CMD_TGT_A;
- NBPtr->TechPtr->PatternLength = 32;
- Rrw->DataPrbsSeed = PRBS_SEED_32;
- break;
- case TRN_DQS_POSITION:
- //
- // Read/Write DQS Position training
- //
- Rrw->CmdTgt = CMD_TGT_AB;
- NBPtr->TechPtr->PatternLength = 256;
- Rrw->DataPrbsSeed = PRBS_SEED_256;
- break;
- default:
- ASSERT (FALSE);
- }
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function finalizes the training pattern.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Index - Index of Write Data Delay Value
- * @param[in,out] *Value - Write Data Delay Value
- * @return BOOLEAN - TRUE - Use the value returned.
- * FALSE - No more values in table.
- */
-
-BOOLEAN
-MemNGetApproximateWriteDatDelayNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Index,
- IN OUT UINT8 *Value
- )
-{
- CONST UINT8 WriteDatDelayValue[] = {0x10, 0x4, 0x8, 0xC, 0x14, 0x18, 0x1C, 0x1F};
- if (Index < GET_SIZE_OF (WriteDatDelayValue)) {
- *Value = WriteDatDelayValue[Index];
- return TRUE;
- }
- return FALSE;
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function finalizes the training pattern.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return AGESA_STATUS - Result
- * AGESA_SUCCESS - Training pattern has been finalized.
- * AGESA_ERROR - Unable to initialize the pattern.
- */
-
-AGESA_STATUS
-MemNTrainingPatternFinalizeNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- AGESA_STATUS Status;
- //
- // Deallocate training buffer
- //
- Status = HeapDeallocateBuffer (AMD_MEM_TRAIN_BUFFER_HANDLE, &NBPtr->MemPtr->StdHeader);
- ASSERT (Status == AGESA_SUCCESS);
- return Status;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function returns the number of chipselects per channel.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return
- */
-
-UINT8
-MemNCSPerChannelNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- return MAX_CS_PER_CHANNEL;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function returns the number of Chipselects controlled by each set
- * of Delay registers under current conditions.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return
- */
-
-UINT8
-MemNCSPerDelayNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- return MAX_CS_PER_DELAY;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function returns the minimum data eye width in 32nds of a UI for
- * the type of data eye(Rd/Wr) that is being trained. This value will
- * be the minimum number of consecutive delays that yield valid data.
- * Uses TechPtr->Direction to determine read or write.
- *
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return
- */
-
-UINT8
-MemNMinDataEyeWidthNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- if (NBPtr->TechPtr->Direction == DQS_READ_DIR) {
- return MIN_RD_DATAEYE_WIDTH_NB;
- } else {
- return MIN_WR_DATAEYE_WIDTH_NB;
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function programs the phy registers according to the desired phy VDDIO voltage level
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNPhyVoltageLevelNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- BIT_FIELD_NAME BitField;
- UINT16 Value;
-
- Value = (UINT16) NBPtr->RefPtr->DDR3Voltage << 3;
-
- for (BitField = BFDataRxVioLvl; BitField <= BFCmpVioLvl; BitField++) {
- if (BitField == BFCmpVioLvl) {
- Value <<= (14 - 3);
- }
- MemNBrdcstSetNb (NBPtr, BitField, Value);
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function adjusts Avg PRE value of Phy fence training according to specific CPU family.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *Value16 - Pointer to the value that we want to adjust
- *
- */
-VOID
-MemNPFenceAdjustUnb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT UINT16 *Value16
- )
-{
- *Value16 += 2; //for LN,ON,and OR, the Avg PRE value is subtracted by 6 only.
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the DDR phy compensation logic
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemNInitPhyCompClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- // Slew rate table array [x][y][z]
- // array[0]: slew rate for VDDIO 1.5V
- // array[1]: slew rate for VDDIO 1.35V
- // array[x][y]: slew rate for a certain frequency
- // array[x][y][0]: frequency mask for current entry
- CONST STATIC UINT16 TxPrePNDataDqs[2][3][5] = {
- {{ (UINT16) DDR800, 0x924, 0x924, 0x924, 0x924},
- { (UINT16) (DDR1066 + DDR1333), 0xFF6, 0xFF6, 0xFF6, 0xFF6},
- { (UINT16) (DDR1600 + DDR1866), 0xFF6, 0xFF6, 0xFF6, 0xFF6}},
- {{ (UINT16) DDR800, 0xFF6, 0xB6D, 0xB6D, 0x924},
- { (UINT16) (DDR1066 + DDR1333), 0xFF6, 0xFF6, 0xFF6, 0xFF6},
- { (UINT16) (DDR1600 + DDR1866), 0xFF6, 0xFF6, 0xFF6, 0xFF6}}
- };
- CONST STATIC UINT16 TxPrePNCmdAddr[2][3][5] = {
- {{ (UINT16) DDR800, 0x492, 0x492, 0x492, 0x492},
- { (UINT16) (DDR1066 + DDR1333), 0x6DB, 0x6DB, 0x6DB, 0x6DB},
- { (UINT16) (DDR1600 + DDR1866), 0xB6D, 0xB6D, 0xB6D, 0xB6D}},
- {{ (UINT16) DDR800, 0x492, 0x492, 0x492, 0x492},
- { (UINT16) (DDR1066 + DDR1333), 0x924, 0x6DB, 0x6DB, 0x6DB},
- { (UINT16) (DDR1600 + DDR1866), 0xB6D, 0xB6D, 0x924, 0x924}}
- };
- CONST STATIC UINT16 TxPrePNClock[2][3][5] = {
- {{ (UINT16) DDR800, 0x924, 0x924, 0x924, 0x924},
- { (UINT16) (DDR1066 + DDR1333), 0xFF6, 0xFF6, 0xFF6, 0xB6D},
- { (UINT16) (DDR1600 + DDR1866), 0xFF6, 0xFF6, 0xFF6, 0xFF6}},
- {{ (UINT16) DDR800, 0xDAD, 0xDAD, 0x924, 0x924},
- { (UINT16) (DDR1066 + DDR1333), 0xFF6, 0xFF6, 0xFF6, 0xDAD},
- { (UINT16) (DDR1600 + DDR1866), 0xFF6, 0xFF6, 0xFF6, 0xDAD}}
- };
-
- CONST PHY_COMP_INIT_CLIENTNB PhyCompInitBitField[] = {
- // 3. Program TxPreP/TxPreN for Data and DQS according toTable 14 if VDDIO is 1.5V or Table 15 if 1.35V.
- // A. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]0[A,6]={0000b, TxPreP, TxPreN}.
- // B. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]02={1000b, TxPreP, TxPreN}.
- {BFDqsDrvStren, BFDataByteTxPreDriverCal2Pad1, BFDataByteTxPreDriverCal2Pad1, 0, TxPrePNDataDqs},
- {BFDataDrvStren, BFDataByteTxPreDriverCal2Pad2, BFDataByteTxPreDriverCal2Pad2, 0, TxPrePNDataDqs},
- {BFDataDrvStren, BFDataByteTxPreDriverCal, BFDataByteTxPreDriverCal, 8, TxPrePNDataDqs},
- // 4. Program TxPreP/TxPreN for Cmd/Addr according toTable 16 if VDDIO is 1.5V or Table 17 if 1.35V.
- // A. Program D18F2x[1,0]9C_x0D0F_[C,8][1:0][12,0E,0A,06]={0000b, TxPreP, TxPreN}.
- // B. Program D18F2x[1,0]9C_x0D0F_[C,8][1:0]02={1000b, TxPreP, TxPreN}.
- {BFCsOdtDrvStren, BFCmdAddr0TxPreDriverCal2Pad1, BFCmdAddr0TxPreDriverCal2Pad2, 0, TxPrePNCmdAddr},
- {BFAddrCmdDrvStren, BFCmdAddr1TxPreDriverCal2Pad1, BFAddrTxPreDriverCal2Pad4, 0, TxPrePNCmdAddr},
- {BFCsOdtDrvStren, BFCmdAddr0TxPreDriverCalPad0, BFCmdAddr0TxPreDriverCalPad0, 8, TxPrePNCmdAddr},
- {BFCkeDrvStren, BFAddrTxPreDriverCalPad0, BFAddrTxPreDriverCalPad0, 8, TxPrePNCmdAddr},
- {BFAddrCmdDrvStren, BFCmdAddr1TxPreDriverCalPad0, BFCmdAddr1TxPreDriverCalPad0, 8, TxPrePNCmdAddr},
- // 5. Program TxPreP/TxPreN for Clock according toTable 18 if VDDIO is 1.5V or Table 19 if 1.35V.
- // A. Program D18F2x[1,0]9C_x0D0F_2[1:0]02={1000b, TxPreP, TxPreN}.
- {BFClkDrvStren, BFClock0TxPreDriverCalPad0, BFClock1TxPreDriverCalPad0, 8, TxPrePNClock}
- };
-
- BIT_FIELD_NAME CurrentBitField;
- UINT16 SpeedMask;
- CONST UINT16 (*TxPrePNArray)[5];
- UINT8 Voltage;
- UINT8 i;
- UINT8 j;
- UINT8 k;
- UINT8 Dct;
-
- Dct = NBPtr->Dct;
- NBPtr->SwitchDCT (NBPtr, 0);
- // 1. Program D18F2x[1,0]9C_x0D0F_E003[DisAutoComp, DisablePreDriverCal] = {1b, 1b}.
- MemNSetBitFieldNb (NBPtr, BFDisablePredriverCal, 0x6000);
- NBPtr->SwitchDCT (NBPtr, Dct);
-
- SpeedMask = (UINT16) 1 << (NBPtr->DCTPtr->Timings.Speed / 66);
- Voltage = (UINT8) NBPtr->RefPtr->DDR3Voltage;
-
- for (j = 0; j < GET_SIZE_OF (PhyCompInitBitField); j ++) {
- i = (UINT8) MemNGetBitFieldNb (NBPtr, PhyCompInitBitField[j].IndexBitField);
- TxPrePNArray = PhyCompInitBitField[j].TxPrePN[Voltage];
- for (k = 0; k < 3; k ++) {
- if ((TxPrePNArray[k][0] & SpeedMask) != 0) {
- for (CurrentBitField = PhyCompInitBitField[j].StartTargetBitField; CurrentBitField <= PhyCompInitBitField[j].EndTargetBitField; CurrentBitField ++) {
- MemNSetBitFieldNb (NBPtr, CurrentBitField, ((PhyCompInitBitField[j].ExtraValue << 12) | TxPrePNArray[k][i + 1]));
- }
- break;
- }
- }
- ASSERT (k < 3);
- }
-
- NBPtr->FamilySpecificHook[ForceAutoComp] (NBPtr, NBPtr);
-}
-
-/*-----------------------------------------------------------------------------
- *
- *
- * This function re-enable phy compensation.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] OptParam - Optional parameter
- *
- * @return TRUE
- * ----------------------------------------------------------------------------
- */
-BOOLEAN
-MemNReEnablePhyCompNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT VOID *OptParam
- )
-{
- UINT8 Dct;
-
- Dct = NBPtr->Dct;
-
- NBPtr->SwitchDCT (NBPtr, 0);
- // Clear DisableCal and set DisablePredriverCal
- MemNSetBitFieldNb (NBPtr, BFDisablePredriverCal, 0x2000);
- NBPtr->SwitchDCT (NBPtr, Dct);
-
- return TRUE;
-}
-
-/*-----------------------------------------------------------------------------
- *
- *
- * This function calculates the value of WrDqDqsEarly and programs it into
- * the DCT and adds it to the WrDqsGrossDelay of each byte lane on each
- * DIMM of the channel.
- *
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] OptParam - Optional parameter
- *
- * @return TRUE
- * ----------------------------------------------------------------------------
- */
-BOOLEAN
-MemNCalcWrDqDqsEarlyUnb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT VOID *OptParam
- )
-{
- MEM_TECH_BLOCK *TechPtr;
- DCT_STRUCT *DCTPtr;
- CH_DEF_STRUCT *ChannelPtr;
- UINT8 Dimm;
- UINT8 ByteLane;
- UINT8 *WrDqsDlysPtr;
- UINT8 WrDqDqsEarly;
-
- ASSERT ((NBPtr->IsSupported[WLSeedAdjust]) && (NBPtr->IsSupported[WLNegativeDelay]));
-
- TechPtr = NBPtr->TechPtr;
- ChannelPtr = NBPtr->ChannelPtr;
- DCTPtr = NBPtr->DCTPtr;
-
- ASSERT (NBPtr != NULL);
- ASSERT (ChannelPtr != NULL);
- ASSERT (DCTPtr != NULL);
- //
- // For each DIMM:
- // - The Critical Gross Delay (CGD) is the minimum GrossDly of all byte lanes and all DIMMs.
- // - If (CGD < 0) Then
- // - D18F2xA8_dct[1:0][WrDqDqsEarly] = ABS(CGD)
- // - WrDqsGrossDly = GrossDly + WrDqDqsEarly
- // - Else
- // - D18F2xA8_dct[1:0][WrDqDqsEarly] = 0.
- // - WrDqsGrossDly = GrossDly
- //
- WrDqDqsEarly = 0;
- if (TechPtr->WLCriticalDelay < 0) {
- IDS_HDT_CONSOLE(MEM_FLOW, "\t\tCalculating WrDqDqsEarly, adjusting WrDqs.\n");
- // We've saved the entire negative delay value, so take the ABS and convert to GrossDly.
- WrDqDqsEarly = (UINT8) (0x00FF &((((ABS (TechPtr->WLCriticalDelay)) + 0x1F) / 0x20)));
- //
- // Loop through All WrDqsDlys on all DIMMs
- //
- for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
- if ((DCTPtr->Timings.CsEnabled & ((UINT16)3 << (Dimm << 1))) != 0) {
- IDS_HDT_CONSOLE(MEM_FLOW, "\t\t\tDimm %x:",Dimm);
- WrDqsDlysPtr = &(ChannelPtr->WrDqsDlys[(Dimm * TechPtr->DlyTableWidth ())]);
- for (ByteLane = 0; ByteLane < TechPtr->DlyTableWidth (); ByteLane++) {
- WrDqsDlysPtr[ByteLane] += (WrDqDqsEarly << 5);
- NBPtr->SetTrainDly (NBPtr, AccessWrDqsDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), WrDqsDlysPtr[ByteLane]);
- IDS_HDT_CONSOLE(MEM_FLOW, " %02x",WrDqsDlysPtr[ByteLane]);
- }
- IDS_HDT_CONSOLE(MEM_FLOW, "\n");
- }
- }
- }
- MemNSetBitFieldNb (NBPtr, BFWrDqDqsEarly, WrDqDqsEarly);
- IDS_HDT_CONSOLE(MEM_FLOW, "\t\tWrDqDqsEarly : %02x\n",WrDqDqsEarly);
- return TRUE;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/mnreg.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/mnreg.c
deleted file mode 100644
index 8abe261..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/mnreg.c
+++ /dev/null
@@ -1,437 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnreg.c
- *
- * Common Northbridge register access functions
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB/)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "merrhdl.h"
-#include "Filecode.h"
-#include "GeneralServices.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_MNREG_FILECODE
-
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function sets the current DCT to work on.
- * Should be called before accessing a certain DCT
- * All data structures will be updated to point to the current DCT
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Dct - ID of the target DCT
- *
- */
-
-VOID
-MemNSwitchDCTNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Dct
- )
-{
- ASSERT (NBPtr->DctCount > Dct);
- //
- // Set the DctCfgSel to new DCT
- //
- NBPtr->FamilySpecificHook[DCTSelectSwitch] (NBPtr, &Dct);
- NBPtr->Dct = Dct ? 1 : 0;
- NBPtr->MCTPtr->Dct = NBPtr->Dct;
- NBPtr->DCTPtr = &(NBPtr->MCTPtr->DctData[NBPtr->Dct]);
- NBPtr->PsPtr = &(NBPtr->PSBlock[NBPtr->Dct]);
- NBPtr->DctCachePtr = &(NBPtr->DctCache[NBPtr->Dct]);
-
- MemNSwitchChannelNb (NBPtr, NBPtr->Channel);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function is used by families that use a separate DctCfgSel bit to
- * select the current DCT which will be accessed by function 2.
- * NOTE: This function must be called BEFORE the NBPtr->Dct variable is
- * updated.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] *Dct - Pointer to ID of the target DCT
- *
- */
-
-BOOLEAN
-MemNDctCfgSelectUnb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN VOID *Dct
- )
-{
- //
- // Sanity check the current DctCfgSel setting
- //
- ASSERT (NBPtr->Dct == NBPtr->GetBitField (NBPtr, BFDctCfgSel));
- //
- // Set the DctCfgSel to new DCT
- //
- NBPtr->SetBitField (NBPtr, BFDctCfgSel, *(UINT8*)Dct);
-
- return TRUE;
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function sets the current channel to work on.
- * Should be called before accessing a certain channel
- * All data structures will be updated to point to the current channel
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Channel - ID of the target channel
- *
- */
-
-VOID
-MemNSwitchChannelNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Channel
- )
-{
- NBPtr->Channel = Channel ? 1 : 0;
- NBPtr->ChannelPtr = &(NBPtr->DCTPtr->ChData[NBPtr->Channel]);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function gets a bit field from PCI register
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] FieldName - Field name
- *
- * @return Bit field value
- */
-
-UINT32
-MemNGetBitFieldNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN BIT_FIELD_NAME FieldName
- )
-{
- UINT32 Value;
-
- ASSERT (FieldName < BFEndOfList);
- Value = NBPtr->MemNCmnGetSetFieldNb (NBPtr, 0, FieldName, 0);
- return Value;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function sets a bit field from PCI register
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] FieldName - Field name
- * @param[in] Field - Value to be stored in PCT register
- *
- */
-
-VOID
-MemNSetBitFieldNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN BIT_FIELD_NAME FieldName,
- IN UINT32 Field
- )
-{
- ASSERT (FieldName < BFEndOfList);
- NBPtr->MemNCmnGetSetFieldNb (NBPtr, 1, FieldName, Field);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Check if bitfields of all enabled DCTs on a die have the expected value. Ignore
- * DCTs that are disabled.
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] FieldName - Bit Field name
- * @param[in] Field - Value to be checked
- *
- * @return TRUE - All enabled DCTs have the expected value on the bitfield.
- * @return FALSE - Not all enabled DCTs have the expected value on the bitfield.
- *
- * ----------------------------------------------------------------------------
- */
-BOOLEAN
-MemNBrdcstCheckNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN BIT_FIELD_NAME FieldName,
- IN UINT32 Field
- )
-{
- UINT8 Dct;
- UINT8 CurrentDCT;
- Dct = NBPtr->Dct;
- for (CurrentDCT = 0; CurrentDCT < NBPtr->DctCount; CurrentDCT++) {
- MemNSwitchDCTNb (NBPtr, CurrentDCT);
- if ((NBPtr->DCTPtr->Timings.DctMemSize != 0) && !((CurrentDCT == 1) && NBPtr->Ganged)) {
- if (MemNGetBitFieldNb (NBPtr, FieldName) != Field) {
- MemNSwitchDCTNb (NBPtr, Dct);
- return FALSE;
- }
- }
- }
- MemNSwitchDCTNb (NBPtr, Dct);
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Set bitfields of all enabled DCTs on a die to a value. Ignore
- * DCTs that are disabled.
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] FieldName - Bit Field name
- * @param[in] Field - Value to be set
- *
- * ----------------------------------------------------------------------------
- */
-VOID
-MemNBrdcstSetNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN BIT_FIELD_NAME FieldName,
- IN UINT32 Field
- )
-{
- UINT8 Dct;
- UINT8 CurrentDCT;
- Dct = NBPtr->Dct;
- for (CurrentDCT = 0; CurrentDCT < NBPtr->DctCount; CurrentDCT++) {
- MemNSwitchDCTNb (NBPtr, CurrentDCT);
- if ((NBPtr->DCTPtr->Timings.DctMemSize != 0) && !((CurrentDCT == 1) && NBPtr->Ganged)) {
- MemNSetBitFieldNb (NBPtr, FieldName, Field);
- }
- }
- MemNSwitchDCTNb (NBPtr, Dct);
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- * This function calculates the memory channel index relative to the
- * socket, taking the Die number, the Dct, and the channel.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Dct
- * @param[in] Channel
- *
- */
-UINT8
-MemNGetSocketRelativeChannelNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Dct,
- IN UINT8 Channel
- )
-{
- return ((NBPtr->MCTPtr->DieId *NBPtr->DctCount) + Dct);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Poll a bitfield. If the bitfield does not get set to the target value within
- * specified microseconds, it times out.
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] FieldName - Bit Field name
- * @param[in] Field - Value to be set
- * @param[in] MicroSecond - Number of microsecond to wait
- * @param[in] IfBroadCast - Need to broadcast to both DCT or not
- *
- * ----------------------------------------------------------------------------
- */
-VOID
-MemNPollBitFieldNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN BIT_FIELD_NAME FieldName,
- IN UINT32 Field,
- IN UINT32 MicroSecond,
- IN BOOLEAN IfBroadCast
- )
-{
- UINT8 ExcludeDCT;
- UINT16 ExcludeChipSelMask;
- UINT32 EventInfo;
- UINT64 InitTSC;
- UINT64 CurrentTSC;
- UINT64 TimeOut;
- AGESA_STATUS EventClass;
- MEM_DATA_STRUCT *MemPtr;
- DIE_STRUCT *MCTPtr;
- BOOLEAN TimeoutEn;
-
- MemPtr = NBPtr->MemPtr;
- MCTPtr = NBPtr->MCTPtr;
- ExcludeDCT = EXCLUDE_ALL_DCT;
- ExcludeChipSelMask = EXCLUDE_ALL_CHIPSEL;
- TimeoutEn = TRUE;
- IDS_TIMEOUT_CTL (&TimeoutEn);
-
- CurrentTSC = 0;
- LibAmdMsrRead (TSC, &InitTSC, &MemPtr->StdHeader);
- TimeOut = InitTSC + ((UINT64) MicroSecond * 1600);
-
- while ((CurrentTSC < TimeOut) || !TimeoutEn) {
- if (IfBroadCast) {
- if (NBPtr->BrdcstCheck (NBPtr, FieldName, Field)) {
- break;
- }
- } else {
- if (MemNGetBitFieldNb (NBPtr, FieldName) == Field) {
- break;
- }
- }
- LibAmdMsrRead (TSC, &CurrentTSC, &MemPtr->StdHeader);
- }
-
- if ((CurrentTSC >= TimeOut) && TimeoutEn) {
- // Default event class
- // If different event class is needed in one entry, override it.
- EventClass = AGESA_ERROR;
- switch (FieldName) {
- case BFDramEnabled:
- EventInfo = MEM_ERROR_DRAM_ENABLED_TIME_OUT;
- break;
- case BFDctAccessDone:
- EventInfo = MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT;
- ExcludeDCT = NBPtr->Dct;
- break;
- case BFSendCtrlWord:
- EventInfo = MEM_ERROR_SEND_CTRL_WORD_TIME_OUT;
- ExcludeDCT = NBPtr->Dct;
- break;
- case BFPrefDramTrainMode:
- EventInfo = MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT;
- ExcludeDCT = NBPtr->Dct;
- break;
- case BFEnterSelfRef:
- EventInfo = MEM_ERROR_ENTER_SELF_REF_TIME_OUT;
- break;
- case BFFreqChgInProg:
- EventInfo = MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT;
- ExcludeDCT = NBPtr->Dct;
- break;
- case BFExitSelfRef:
- EventInfo = MEM_ERROR_EXIT_SELF_REF_TIME_OUT;
- break;
- case BFSendMrsCmd:
- EventInfo = MEM_ERROR_SEND_MRS_CMD_TIME_OUT;
- ExcludeDCT = NBPtr->Dct;
- break;
- case BFSendZQCmd:
- EventInfo = MEM_ERROR_SEND_ZQ_CMD_TIME_OUT;
- ExcludeDCT = NBPtr->Dct;
- break;
- case BFDctExtraAccessDone:
- EventInfo = MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT;
- ExcludeDCT = NBPtr->Dct;
- break;
- case BFMemClrBusy:
- EventInfo = MEM_ERROR_MEM_CLR_BUSY_TIME_OUT;
- break;
- case BFMemCleared:
- EventInfo = MEM_ERROR_MEM_CLEARED_TIME_OUT;
- break;
- case BFFlushWr:
- EventInfo = MEM_ERROR_FLUSH_WR_TIME_OUT;
- ExcludeDCT = NBPtr->Dct;
- break;
- default:
- EventClass = 0;
- EventInfo = 0;
- IDS_ERROR_TRAP;
- }
-
- PutEventLog (EventClass, EventInfo, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &MemPtr->StdHeader);
- SetMemError (EventClass, MCTPtr);
- MemPtr->ErrorHandling (MCTPtr, ExcludeDCT, ExcludeChipSelMask, &MemPtr->StdHeader);
- }
-}
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/mntrain2.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/mntrain2.c
deleted file mode 100644
index f8b10be..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/mntrain2.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mntrain2.c
- *
- * Common Northbridge function for training flow for DDR2
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_MNTRAIN2_FILECODE
-/* features */
-#include "mftds.h"
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-extern MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR2;
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initiates DQS training
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-BOOLEAN
-MemNDQSTiming2Nb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MEM_TECH_BLOCK *TechPtr;
-
- TechPtr = NBPtr->TechPtr;
- if (TechPtr->NBPtr->MCTPtr->NodeMemSize) {
- AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader);
- AgesaHookBeforeDQSTraining (0, TechPtr->NBPtr->MemPtr);
- AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader);
- //Execute Technology specific training features
- if (memTechTrainingFeatDDR2.NonOptimizedSWDQSRecEnTrainingPart1 (TechPtr)) {
- if (memTechTrainingFeatDDR2.OptimizedSwDqsRecEnTrainingPart1 (TechPtr)) {
- MemFInitTableDrive (NBPtr, MTAfterSwRxEnTrn);
- if (memTechTrainingFeatDDR2.NonOptimizedSRdWrPosTraining (TechPtr)) {
- if (memTechTrainingFeatDDR2.OptimizedSRdWrPosTraining (TechPtr)) {
- MemFInitTableDrive (NBPtr, MTAfterDqsRwPosTrn);
- if (memTechTrainingFeatDDR2.MaxRdLatencyTraining (TechPtr)) {
- MemFInitTableDrive (NBPtr, MTAfterMaxRdLatTrn);
- }
- }
- }
- }
- }
- MemTMarkTrainFail (TechPtr);
- }
- return TRUE;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/NB/mntrain3.c b/src/vendorcode/amd/agesa/Proc/Mem/NB/mntrain3.c
deleted file mode 100644
index 3835224..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/NB/mntrain3.c
+++ /dev/null
@@ -1,236 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mntrain3.c
- *
- * Common Northbridge function for training flow for DDR3
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB)
- * @e \$Revision: 37555 $ @e \$Date: 2010-09-08 02:17:18 +0800 (Wed, 08 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_NB_MNTRAIN3_FILECODE
-/* features */
-#include "mftds.h"
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-STATIC
-MemNHwWlPart2Nb (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-extern MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[];
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initiates DQS training
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-BOOLEAN
-MemNDQSTiming3Nb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MEM_TECH_BLOCK *TechPtr;
- UINT8 i;
- BOOLEAN Retval;
- TechPtr = NBPtr->TechPtr;
- Retval = TRUE;
- if (TechPtr->NBPtr->MCTPtr->NodeMemSize) {
- //Execute Technology specific training features
- i = 0;
- while (memTrainSequenceDDR3[i].TrainingSequenceEnabled != 0) {
- if (memTrainSequenceDDR3[i].TrainingSequenceEnabled (NBPtr)) {
- NBPtr->TrainingSequenceIndex = i;
- Retval = memTrainSequenceDDR3[i].TrainingSequence (NBPtr);
- break;
- }
- i++;
- }
- }
- return Retval;
-}
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initiates DQS training for Server NB
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-BOOLEAN
-memNSequenceDDR3Nb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MEM_TECH_BLOCK *TechPtr;
- UINT8 i;
- TechPtr = NBPtr->TechPtr;
- i = NBPtr->TrainingSequenceIndex;
- if (TechPtr->NBPtr->MCTPtr->NodeMemSize != 0) {
- AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader);
- IDS_HDT_CONSOLE (MEM_FLOW, "\nCalling out to Platform BIOS...\n");
- if (AgesaHookBeforeDQSTraining (0, TechPtr->NBPtr->MemPtr) == AGESA_SUCCESS) {
- // Right now we do not have anything to do if the callout is implemented
- }
- AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader);
- //Execute Technology specific training features
- if (memTrainSequenceDDR3[i].MemTechFeatBlock->EnterHardwareTraining (TechPtr)) {
- TechPtr->TechnologySpecificHook[LrdimmBuf2DramTrain] (TechPtr, NULL);
- if (memTrainSequenceDDR3[i].MemTechFeatBlock->SwWLTraining (TechPtr)) {
- MemFInitTableDrive (NBPtr, MTAfterSwWLTrn);
- if (memTrainSequenceDDR3[i].MemTechFeatBlock->HwBasedWLTrainingPart1 (TechPtr)) {
- MemFInitTableDrive (NBPtr, MTAfterHwWLTrnP1);
- if (memTrainSequenceDDR3[i].MemTechFeatBlock->HwBasedDQSReceiverEnableTrainingPart1 (TechPtr)) {
- MemFInitTableDrive (NBPtr, MTAfterHwRxEnTrnP1);
- // If target speed is higher than start-up speed, do frequency change and second pass of WL
- if (MemNHwWlPart2Nb (TechPtr)) {
- if (memTrainSequenceDDR3[i].MemTechFeatBlock->TrainExitHwTrn (TechPtr)) {
- IDS_OPTION_HOOK (IDS_PHY_DLL_STANDBY_CTRL, NBPtr, &(NBPtr->MemPtr->StdHeader));
- if (memTrainSequenceDDR3[i].MemTechFeatBlock->NonOptimizedSWDQSRecEnTrainingPart1 (TechPtr)) {
- if (memTrainSequenceDDR3[i].MemTechFeatBlock->OptimizedSwDqsRecEnTrainingPart1 (TechPtr)) {
- MemFInitTableDrive (NBPtr, MTAfterSwRxEnTrn);
- if (memTrainSequenceDDR3[i].MemTechFeatBlock->NonOptimizedSRdWrPosTraining (TechPtr)) {
- if (memTrainSequenceDDR3[i].MemTechFeatBlock->OptimizedSRdWrPosTraining (TechPtr)) {
- MemFInitTableDrive (NBPtr, MTAfterDqsRwPosTrn);
- do {
- if (memTrainSequenceDDR3[i].MemTechFeatBlock->MaxRdLatencyTraining (TechPtr)) {
- MemFInitTableDrive (NBPtr, MTAfterMaxRdLatTrn);
- }
- } while (NBPtr->ChangeNbFrequency (NBPtr));
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- TechPtr->TechnologySpecificHook[LrdimmSyncTrainedDlys] (TechPtr, NULL);
- MemTMarkTrainFail (TechPtr);
- }
- return TRUE;
-}
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function executes HW WL at multiple speeds
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @return TRUE - No errors occurred
- * FALSE - errors occurred
- */
-
-BOOLEAN
-STATIC
-MemNHwWlPart2Nb (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- BOOLEAN retVal;
- UINT8 i;
- retVal = TRUE;
- i = TechPtr->NBPtr->TrainingSequenceIndex;
- while (TechPtr->NBPtr->DCTPtr->Timings.TargetSpeed > TechPtr->NBPtr->DCTPtr->Timings.Speed) {
- TechPtr->PrevSpeed = TechPtr->NBPtr->DCTPtr->Timings.Speed;
- if (TechPtr->NBPtr->RampUpFrequency (TechPtr->NBPtr)) {
- TechPtr->TechnologySpecificHook[LrdimmBuf2DramTrain] (TechPtr, NULL);
- if (!memTrainSequenceDDR3[i].MemTechFeatBlock->HwBasedWLTrainingPart2 (TechPtr)) {
- retVal = FALSE;
- break;
- }
- MemFInitTableDrive (TechPtr->NBPtr, MTAfterHwWLTrnP2);
- if (!memTrainSequenceDDR3[i].MemTechFeatBlock->HwBasedDQSReceiverEnableTrainingPart2 (TechPtr)) {
- retVal = FALSE;
- break;
- }
- MemFInitTableDrive (TechPtr->NBPtr, MTAfterHwRxEnTrnP2);
- } else {
- retVal = FALSE;
- break;
- }
- }
- return retVal;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ps/C32/mprc32_3.c b/src/vendorcode/amd/agesa/Proc/Mem/Ps/C32/mprc32_3.c
deleted file mode 100644
index 9113812..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ps/C32/mprc32_3.c
+++ /dev/null
@@ -1,326 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mprc32_3.c
- *
- * Platform specific settings for C32 DDR3 R-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "mport.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "mu.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-#define FILECODE PROC_MEM_PS_C32_MPRC32_3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define AMD_FAMILY_10_C32 AMD_FAMILY_10_HY
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPDoPsRC32_3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-STATIC
-MemPGetPORFreqLimitRC32_3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*
- * ODT Settings for 1 or 2 Dimms Per Channel
- *
- * Speeds Supported, # of Dimms, # of QRDimms, DramTerm, QR DramTerm, Dynamic DramTerm
- */
-STATIC CONST DRAM_TERM_ENTRY C32RDdr3DramTerm2D[] = {
- {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
- {DDR667 + DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
- {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
- {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1},
- {DDR667 + DDR800 + DDR1066 + DDR1333, ONE_DIMM, ONE_DIMM, 0, 1, 2},
- {DDR1600, ONE_DIMM, ONE_DIMM, 0, 1, 1},
- {DDR667 + DDR800, TWO_DIMM, ONE_DIMM, 5, 1, 2},
- {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, ONE_DIMM, 5, 1, 1},
- {DDR667 + DDR800, TWO_DIMM, TWO_DIMM, 0, 1, 2},
- {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, TWO_DIMM, 0, 1, 1}
-};
-/*
- * ODT Settings for 3 Dimms Per Channel
- *
- * Speeds Supported, # of Dimms, # of QRDimms, DramTerm, QR DramTerm, Dynamic DramTerm
- */
-STATIC CONST DRAM_TERM_ENTRY C32RDdr3DramTerm3D[] = {
- {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
- {DDR667 + DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
- {DDR1333 + DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 2},
- {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, THREE_DIMM, NO_DIMM, 3, 0, 2},
- {DDR667 + DDR800 + DDR1066 + DDR1333, ONE_DIMM, ONE_DIMM, 0, 1, 2},
- {DDR667 + DDR800, TWO_DIMM, ONE_DIMM, 5, 1, 2},
- {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, ONE_DIMM, 5, 1, 1},
- {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, THREE_DIMM, ONE_DIMM, 3, 1, 2}
-};
-/*
- * POR Max Frequency supported for specific Dimm configurations for 1 Dimm Per Channel
- *
- * Dimm Config, # of Dimms, Max Freq @ 1.5V, Max Freq @ 1.35V, Max Freq @ 1.25
- */
-STATIC CONST POR_SPEED_LIMIT C32RDdr3PSPorFreqLimit1D[] = {
- {SR_DIMM0 + DR_DIMM0, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0},
- {QR_DIMM0, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0}
-};
-/*
- * POR Max Frequency supported for specific Dimm configurations for 2 Dimms Per Channel
- *
- * Dimm Config, # of Dimms, Max Freq @ 1.5V, Max Freq @ 1.35V, Max Freq @ 1.25
- */
-STATIC CONST POR_SPEED_LIMIT C32RDdr3PSPorFreqLimit2D[] = {
- {SR_DIMM1 + DR_DIMM1, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0},
- {QR_DIMM1, 1, DDR1333_FREQUENCY, DDR1066_FREQUENCY, 0},
- {SR_DIMM0 + SR_DIMM1, 2, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, 2, DDR1066_FREQUENCY, DDR1066_FREQUENCY, 0},
- {QR_DIMM0 + ANY_DIMM1, 2, DDR800_FREQUENCY, DDR667_FREQUENCY, 0},
- {ANY_DIMM0 + QR_DIMM1, 2, DDR800_FREQUENCY, DDR667_FREQUENCY, 0}
-};
-/*
- * POR Max Frequency supported for specific Dimm configurations for 3 Dimms Per Channel
- *
- * Dimm Config, # of Dimms, Max Freq @ 1.5V, Max Freq @ 1.35V, Max Freq @ 1.25
- */
-STATIC CONST POR_SPEED_LIMIT C32RDdr3PSPorFreqLimit3D[] = {
- {SR_DIMM2 + DR_DIMM2, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0},
- {SR_DIMM0 + SR_DIMM2, 2, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, 2, DDR1066_FREQUENCY, DDR1066_FREQUENCY, 0},
- {QR_DIMM1, 1, DDR800_FREQUENCY, DDR800_FREQUENCY, 0},
- {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, 2, DDR800_FREQUENCY, DDR667_FREQUENCY, 0},
- {SR_DIMM0 + SR_DIMM1 + SR_DIMM2, 3, DDR1066_FREQUENCY, DDR800_FREQUENCY, 0},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, 3, DDR800_FREQUENCY, DDR800_FREQUENCY, 0},
- {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, 3, DDR667_FREQUENCY, DDR667_FREQUENCY, 0}
-
-};
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function is the constructor platform specific settings for R DIMM-DDR3 C32 DDR3
- *
- * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE
- * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT
- * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK
- *
- * @return AGESA_SUCCESS
- *
- */
-
-AGESA_STATUS
-MemPConstructPsRC32_3 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- )
-{
- ASSERT (MemPtr != 0);
- ASSERT (ChannelPtr != 0);
-
- if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_C32) == 0) {
- return AGESA_UNSUPPORTED;
- }
- if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
- return AGESA_UNSUPPORTED;
- }
- if (ChannelPtr->RegDimmPresent != ChannelPtr->ChDimmValid) {
- return AGESA_UNSUPPORTED;
- }
- PsPtr->MemPDoPs = MemPDoPsRC32_3;
- PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitRC32_3;
- return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for R-DDR3 C32 DDR3
- *
- * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
- *
- * @return TRUE - Find settings for corresponding platform and dimm population.
- * @return FALSE - Fail to find settings for corresponding platform and dimm population.
- *
- */
-
-BOOLEAN
-STATIC
-MemPDoPsRC32_3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- CONST DRAM_TERM_ENTRY *DramTermPtr;
- UINT8 MaxDimmsPerChannel;
- UINT8 *DimmsPerChPtr;
- UINT8 DramTermSize;
-
- DramTermSize = 0;
- DramTermPtr = NULL;
- DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
- if (DimmsPerChPtr != NULL) {
- MaxDimmsPerChannel = *DimmsPerChPtr;
- } else {
- MaxDimmsPerChannel = 2;
- }
-
- if ((MaxDimmsPerChannel == 1) || (MaxDimmsPerChannel == 2)) {
- DramTermSize = GET_SIZE_OF (C32RDdr3DramTerm2D);
- DramTermPtr = C32RDdr3DramTerm2D;
- } else if (MaxDimmsPerChannel == 3) {
- DramTermSize = GET_SIZE_OF (C32RDdr3DramTerm3D);
- DramTermPtr = C32RDdr3DramTerm3D;
- } else {
- IDS_ERROR_TRAP;
- }
-
- if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) {
- return FALSE;
- }
- //
- // Special Cases for certain configs not covered by the table
- //
- // SR-SR-SR 1.5v @1066 (Currently only 3DPCH config at 1066)
- if ((MaxDimmsPerChannel == 3) && (NBPtr->ChannelPtr->Dimms == 3) &&
- (NBPtr->DCTPtr->Timings.Speed == DDR1066_FREQUENCY)) {
- NBPtr->PsPtr->DramTerm = 5; //30 Ohms
- }
-
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function gets the POR speed limit for R-DDR3 C32 DDR3
- *
- * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
- *
- *
- */
-VOID
-STATIC
-MemPGetPORFreqLimitRC32_3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 *DimmsPerChPtr;
- UINT8 MaxDimmPerCH;
- UINT8 FreqLimitSize;
- UINT16 SpeedLimit;
- CONST POR_SPEED_LIMIT *FreqLimitPtr;
- DCT_STRUCT *DCTPtr;
-
- DCTPtr = NBPtr->DCTPtr;
- DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
- if (DimmsPerChPtr != NULL) {
- MaxDimmPerCH = *DimmsPerChPtr;
- } else {
- MaxDimmPerCH = 2;
- }
-
- if (MaxDimmPerCH == 4) {
- DCTPtr->Timings.DimmExclude |= DCTPtr->Timings.DctDimmValid;
- PutEventLog (AGESA_CRITICAL, MEM_ERROR_UNSUPPORTED_DIMM_CONFIG, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_CRITICAL, NBPtr->MCTPtr);
- // Change target speed to highest value so it won't affect other channels when leveling frequency across the node.
- NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY;
- return;
- } else if (MaxDimmPerCH == 3) {
- FreqLimitPtr = C32RDdr3PSPorFreqLimit3D;
- FreqLimitSize = GET_SIZE_OF (C32RDdr3PSPorFreqLimit3D);
- } else if (MaxDimmPerCH == 2) {
- FreqLimitPtr = C32RDdr3PSPorFreqLimit2D;
- FreqLimitSize = GET_SIZE_OF (C32RDdr3PSPorFreqLimit2D);
- } else {
- FreqLimitPtr = C32RDdr3PSPorFreqLimit1D;
- FreqLimitSize = GET_SIZE_OF (C32RDdr3PSPorFreqLimit1D);
- }
-
- SpeedLimit = MemPGetPorFreqLimit (NBPtr, FreqLimitSize, FreqLimitPtr);
-
- if (SpeedLimit != 0) {
- if (DCTPtr->Timings.TargetSpeed > SpeedLimit) {
- DCTPtr->Timings.TargetSpeed = SpeedLimit;
- }
- } else {
- DCTPtr->Timings.DimmExclude |= DCTPtr->Timings.DctDimmValid;
- PutEventLog (AGESA_CRITICAL, MEM_ERROR_UNSUPPORTED_DIMM_CONFIG, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_CRITICAL, NBPtr->MCTPtr);
- // Change target speed to highest value so it won't affect other channels when leveling frequency across the node.
- NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY;
- }
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ps/C32/mpuc32_3.c b/src/vendorcode/amd/agesa/Proc/Mem/Ps/C32/mpuc32_3.c
deleted file mode 100644
index 7866eed..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ps/C32/mpuc32_3.c
+++ /dev/null
@@ -1,205 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mpuc32_3.c
- *
- * Platform specific settings for C32 DDR3 U-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "mport.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "PlatformMemoryConfiguration.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_PS_C32_MPUC32_3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define AMD_FAMILY_10_C32 AMD_FAMILY_10_HY
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPDoPsUC32_3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-STATIC
-MemPGetPORFreqLimitUC32_3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-STATIC CONST DRAM_TERM_ENTRY C32UDdr3DramTerm[] = {
- {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
- {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
- {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
- {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
-};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function is the constructor for the platform specific settings for U-DDR3 C32 DDR3
- *
- * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE
- * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT
- * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK
- *
- * @return AGESA_SUCCESS
- *
- */
-
-AGESA_STATUS
-MemPConstructPsUC32_3 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- )
-{
- ASSERT (MemPtr != 0);
- ASSERT (ChannelPtr != 0);
-
- if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_C32) == 0) {
- return AGESA_UNSUPPORTED;
- }
- if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
- return AGESA_UNSUPPORTED;
- }
- if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) {
- return AGESA_UNSUPPORTED;
- }
- PsPtr->MemPDoPs = MemPDoPsUC32_3;
- PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitUC32_3;
- return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for U-DDR3 C32 DDR3
- *
- * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
- *
- * @return TRUE - Find settings for corresponding platform and dimm population.
- * @return FALSE - Fail to find settings for corresponding platform and dimm population.
- *
- */
-
-BOOLEAN
-STATIC
-MemPDoPsUC32_3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (C32UDdr3DramTerm), C32UDdr3DramTerm)) {
- return FALSE;
- }
-
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function gets the POR speed limit for SO-DDR3 C32
- *
- * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
- *
- *
- */
-VOID
-STATIC
-MemPGetPORFreqLimitUC32_3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT16 MaxSpeed;
- //
- // For 2/2 or 2/3 DPCH where one is a DR, Max Speed is 1066
- //
- if ( (NBPtr->ChannelPtr->Dimms >= 2) && ((NBPtr->ChannelPtr->DimmDrPresent & 0x07) != 0) ) {
- MaxSpeed = DDR1066_FREQUENCY;
- } else {
- //
- // Highest POR supported speed for Unbuffered dimm is 1333
- //
- MaxSpeed = DDR1333_FREQUENCY;
- }
- if (NBPtr->DCTPtr->Timings.TargetSpeed > MaxSpeed) {
- NBPtr->DCTPtr->Timings.TargetSpeed = MaxSpeed;
- } else if (NBPtr->DCTPtr->Timings.TargetSpeed == DDR667_FREQUENCY) {
- // Unbuffered DDR3 at 333MHz is not supported
- NBPtr->DCTPtr->Timings.DimmExclude |= NBPtr->DCTPtr->Timings.DctDimmValid;
- PutEventLog (AGESA_ERROR, MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_ERROR, NBPtr->MCTPtr);
- // Change target speed to highest value so it won't affect other channels when leveling frequency across the node.
- NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY;
- }
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ps/DA/mpsda2.c b/src/vendorcode/amd/agesa/Proc/Mem/Ps/DA/mpsda2.c
deleted file mode 100644
index c69a526..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ps/DA/mpsda2.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mpsda2.c
- *
- * Platform specific settings for DA DDR2 SO-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/* This file contains routine that add platform specific support S1g3 */
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "mport.h"
-#include "PlatformMemoryConfiguration.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_PS_DA_MPSDA2_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPDoPsSDA2 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-STATIC CONST DRAM_TERM_ENTRY DaSDdr2DramTerm[] = {
- {DDR533 + DDR667 + DDR800, ONE_DIMM, ANY_NUM, 2, 0, 0},
- {DDR533 + DDR667, TWO_DIMM, ANY_NUM, 1, 0, 0},
- {DDR800, TWO_DIMM, ANY_NUM, 3, 0, 0}
-};
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function is the constructor the platform specific settings for SO-DIMM DA DDR2
- *
- * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE
- * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT
- * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK
- *
- * @return AGESA_SUCCESS
- *
- */
-
-AGESA_STATUS
-MemPConstructPsSDA2 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- )
-{
- ASSERT (MemPtr != 0);
- ASSERT (ChannelPtr != 0);
-
- if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) {
- return AGESA_UNSUPPORTED;
- }
- if (ChannelPtr->TechType != DDR2_TECHNOLOGY) {
- return AGESA_UNSUPPORTED;
- }
- if (ChannelPtr->SODimmPresent != ChannelPtr->ChDimmValid) {
- return AGESA_UNSUPPORTED;
- }
-
- PsPtr->MemPDoPs = MemPDoPsSDA2;
- PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitDef;
- return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for SO-DIMM DA DDR2
- *
- * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
- *
- * @return TRUE - Find settings for corresponding platform and dimm population.
- * @return FALSE - Fail to find settings for corresponding platform and dimm population.
- *
- */
-
-BOOLEAN
-STATIC
-MemPDoPsSDA2 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (DaSDdr2DramTerm), DaSDdr2DramTerm)) {
- return FALSE;
- }
-
- return TRUE;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ps/DA/mpsda3.c b/src/vendorcode/amd/agesa/Proc/Mem/Ps/DA/mpsda3.c
deleted file mode 100644
index 981b8cd..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ps/DA/mpsda3.c
+++ /dev/null
@@ -1,257 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mpsda3.c
- *
- * Platform specific settings for DA DDR3 SO-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/* This file contains routine that add platform specific support L1 */
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "mport.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "mu.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_PS_DA_MPSDA3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPDoPsSDA3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-STATIC
-MemPGetPORFreqLimitSDA3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-STATIC CONST DRAM_TERM_ENTRY DaSDdr3DramTerm1D[] = {
- {DDR800, ONE_DIMM, NO_DIMM, 2, 0, 0},
- {DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}
-};
-
-STATIC CONST DRAM_TERM_ENTRY DaSDdr3DramTerm2D[] = {
- {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
- {DDR800, TWO_DIMM, NO_DIMM, 3, 0, 2},
- {DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
- {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
-};
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function is the constructor the platform specific settings for SO-DIMM DA DDR3
- *
- * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE
- * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT
- * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK
- *
- * @return AGESA_SUCCESS
- *
- */
-
-AGESA_STATUS
-MemPConstructPsSDA3 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- )
-{
- ASSERT (MemPtr != 0);
- ASSERT (ChannelPtr != 0);
-
- if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) {
- return AGESA_UNSUPPORTED;
- }
- if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
- return AGESA_UNSUPPORTED;
- }
- if (ChannelPtr->SODimmPresent != ChannelPtr->ChDimmValid) {
- return AGESA_UNSUPPORTED;
- }
-
- PsPtr->MemPDoPs = MemPDoPsSDA3;
- PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitSDA3;
- return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for SO-DIMM DA DDR3
- *
- * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
- *
- * @return TRUE - Find settings for corresponding platform and dimm population.
- * @return FALSE - Fail to find settings for corresponding platform and dimm population.
- *
- */
-
-BOOLEAN
-STATIC
-MemPDoPsSDA3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- CONST DRAM_TERM_ENTRY *DramTermPtr;
- UINT8 MaxDimmsPerChannel;
- UINT8 *DimmsPerChPtr;
- UINT8 DramTermSize;
-
- DramTermSize = 0;
- DramTermPtr = NULL;
- DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
- if (DimmsPerChPtr != NULL) {
- MaxDimmsPerChannel = *DimmsPerChPtr;
- } else {
- MaxDimmsPerChannel = 2;
- }
-
- if (MaxDimmsPerChannel == 1) {
- DramTermSize = GET_SIZE_OF (DaSDdr3DramTerm1D);
- DramTermPtr = DaSDdr3DramTerm1D;
- } else if (MaxDimmsPerChannel == 2) {
- DramTermSize = GET_SIZE_OF (DaSDdr3DramTerm2D);
- DramTermPtr = DaSDdr3DramTerm2D;
- } else {
- IDS_ERROR_TRAP;
- }
-
- if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) {
- return FALSE;
- }
-
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function gets the POR speed limit for SO-DDR3 DA
- *
- * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
- *
- *
- */
-VOID
-STATIC
-MemPGetPORFreqLimitSDA3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 *DimmsPerChPtr;
- UINT8 MaxDimmPerCH;
- UINT16 SpeedLimit;
-
- DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
- if (DimmsPerChPtr != NULL) {
- MaxDimmPerCH = *DimmsPerChPtr;
- } else {
- MaxDimmPerCH = 2;
- }
-
- if (MaxDimmPerCH == 1) {
- if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) {
- //
- // Highest POR supported speed for SODimm is 1333
- //
- SpeedLimit = DDR1333_FREQUENCY;
- } else {
- //
- // Max LV DDR3 Speed is 1066 for this silicon
- //
- SpeedLimit = DDR1066_FREQUENCY;
- }
- } else {
- //
- // Highest supported speed in 2DPC configuration is 1066
- //
- SpeedLimit = DDR1066_FREQUENCY;
- //
- // VOLT1_35 won't be supported while two DIMMs are populated in a channel
- //
- if ((NBPtr->RefPtr->DDR3Voltage == VOLT1_35) &&
- (NBPtr->ChannelPtr->Dimms == 2)) {
- NBPtr->RefPtr->DDR3Voltage = VOLT1_5;
- PutEventLog (AGESA_WARNING, MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_WARNING, NBPtr->MCTPtr);
- }
- }
-
- if (NBPtr->DCTPtr->Timings.TargetSpeed > SpeedLimit) {
- NBPtr->DCTPtr->Timings.TargetSpeed = SpeedLimit;
- }
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ps/DA/mpuda3.c b/src/vendorcode/amd/agesa/Proc/Mem/Ps/DA/mpuda3.c
deleted file mode 100644
index aad019a..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ps/DA/mpuda3.c
+++ /dev/null
@@ -1,210 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mpuda3.c
- *
- * Platform specific settings for DA DDR3 U-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/* This file contains routine that add platform specific support L1 */
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "mport.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "mu.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_PS_DA_MPUDA3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPDoPsUDA3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-STATIC
-MemPGetPORFreqLimitUDA3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-STATIC CONST DRAM_TERM_ENTRY DrUDdr3DramTerm[] = {
- {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
- {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
- {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
- {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
-};
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function is the constructor for the platform specific settings for U-DDR3 DA DDR3
- *
- * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE
- * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT
- * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK
- *
- * @return AGESA_SUCCESS
- *
- */
-
-AGESA_STATUS
-MemPConstructPsUDA3 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- )
-{
- ASSERT (MemPtr != 0);
- ASSERT (ChannelPtr != 0);
-
- if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) {
- return AGESA_UNSUPPORTED;
- }
- if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
- return AGESA_UNSUPPORTED;
- }
- if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) {
- return AGESA_UNSUPPORTED;
- }
-
- PsPtr->MemPDoPs = MemPDoPsUDA3;
- PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitUDA3;
- return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for U-DDR3 DA DDR3
- *
- * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
- *
- * @return TRUE - Find settings for corresponding platform and dimm population.
- * @return FALSE - Fail to find settings for corresponding platform and dimm population.
- *
- */
-
-BOOLEAN
-STATIC
-MemPDoPsUDA3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (DrUDdr3DramTerm), DrUDdr3DramTerm)) {
- return FALSE;
- }
-
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function gets the POR speed limit for U-DDR3 DA
- *
- * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
- *
- *
- */
-VOID
-STATIC
-MemPGetPORFreqLimitUDA3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT16 SpeedLimit;
-
- if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) {
- //
- // Highest POR supported speed for Unbuffered dimm is 1333
- //
- SpeedLimit = DDR1333_FREQUENCY;
- } else {
- //
- // Max LV DDR3 Speed is 1066 for this silicon
- //
- SpeedLimit = DDR1066_FREQUENCY;
- }
-
- if (NBPtr->DCTPtr->Timings.TargetSpeed > SpeedLimit) {
- NBPtr->DCTPtr->Timings.TargetSpeed = SpeedLimit;
- } else if (NBPtr->DCTPtr->Timings.TargetSpeed == DDR667_FREQUENCY) {
- // Unbuffered DDR3 at 333MHz is not supported
- NBPtr->DCTPtr->Timings.DimmExclude |= NBPtr->DCTPtr->Timings.DctDimmValid;
- PutEventLog (AGESA_ERROR, MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_ERROR, NBPtr->MCTPtr);
- // Change target speed to highest value so it won't affect other channels when leveling frequency across the node.
- NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY;
- }
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ps/DR/mprdr2.c b/src/vendorcode/amd/agesa/Proc/Mem/Ps/DR/mprdr2.c
deleted file mode 100644
index 2b59c8b..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ps/DR/mprdr2.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mprdr2.c
- *
- * Platform specific settings for DR DDR2 R-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/* This file contains routine that add platform specific support L1 */
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "mport.h"
-#include "PlatformMemoryConfiguration.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_PS_DR_MPRDR2_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPDoPsRDr2 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-STATIC CONST DRAM_TERM_ENTRY DrUDdr2DramTerm[] = {
- {DDR400 + DDR533 + DDR667, ONE_DIMM, ANY_NUM, 1, 0, 0},
- {DDR400 + DDR533, TWO_DIMM + THREE_DIMM + FOUR_DIMM, ANY_NUM, 1, 0, 0},
- {DDR667, TWO_DIMM + THREE_DIMM, ANY_NUM, 1, 0, 0},
- {DDR667, FOUR_DIMM, ANY_NUM, 3, 0, 0},
- {DDR800, ONE_DIMM, ANY_NUM, 1, 0, 0},
- {DDR800, TWO_DIMM + THREE_DIMM + FOUR_DIMM, ANY_NUM, 3, 0, 0},
- {DDR1066, ONE_DIMM, ANY_NUM, 1, 0, 0}
-};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function is the constructor platform specific settings for R DIMM-DDR2 DR DDR2
- *
- * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE
- * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT
- * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK
- *
- * @return AGESA_SUCCESS
- *
- */
-
-AGESA_STATUS
-MemPConstructPsRDr2 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- )
-{
- ASSERT (MemPtr != 0);
- ASSERT (ChannelPtr != 0);
-
-
- if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) {
- return AGESA_UNSUPPORTED;
- }
- if (ChannelPtr->TechType != DDR2_TECHNOLOGY) {
- return AGESA_UNSUPPORTED;
- }
- if (ChannelPtr->RegDimmPresent != ChannelPtr->ChDimmValid) {
- return AGESA_UNSUPPORTED;
- }
- PsPtr->MemPDoPs = MemPDoPsRDr2;
- PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitDef;
- return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for R-DDR2 DR DDR2
- *
- * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
- *
- * @return TRUE - Find settings for corresponding platform and dimm population.
- * @return FALSE - Fail to find settings for corresponding platform and dimm population.
- *
- */
-
-BOOLEAN
-STATIC
-MemPDoPsRDr2 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (DrUDdr2DramTerm), DrUDdr2DramTerm)) {
- return FALSE;
- }
-
- return TRUE;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ps/DR/mprdr3.c b/src/vendorcode/amd/agesa/Proc/Mem/Ps/DR/mprdr3.c
deleted file mode 100644
index f26f0c8..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ps/DR/mprdr3.c
+++ /dev/null
@@ -1,205 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mprdr3.c
- *
- * Platform specific settings for DR DDR3 R-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/* This file contains routine that add platform specific support L1 */
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "mport.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "mu.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_PS_DR_MPRDR3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPDoPsRDr3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-STATIC CONST DRAM_TERM_ENTRY DrRDdr3DramTerm2D[] = {
- {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
- {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
- {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
- {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1},
- {DDR800 + DDR1066 + DDR1333, ONE_DIMM, ONE_DIMM, 0, 1, 2},
- {DDR1600, ONE_DIMM, ONE_DIMM, 0, 1, 1},
- {DDR800, TWO_DIMM, ONE_DIMM, 5, 1, 2},
- {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, ONE_DIMM, 5, 1, 1},
- {DDR800, TWO_DIMM, TWO_DIMM, 0, 1, 2},
- {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, TWO_DIMM, 0, 1, 1}
-};
-
-STATIC CONST DRAM_TERM_ENTRY DrRDdr3DramTerm3D[] = {
- {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
- {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
- {DDR1333 + DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 2},
- {DDR800 + DDR1066 + DDR1333 + DDR1600, THREE_DIMM, NO_DIMM, 3, 0, 2},
- {DDR800 + DDR1066 + DDR1333, ONE_DIMM, ONE_DIMM, 0, 1, 2},
- {DDR800, TWO_DIMM, ONE_DIMM, 5, 1, 2},
- {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, ONE_DIMM, 5, 1, 1},
- {DDR800 + DDR1066 + DDR1333 + DDR1600, THREE_DIMM, ONE_DIMM, 3, 1, 2}
-};
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function is the constructor platform specific settings for R DIMM-DDR3 DR DDR3
- *
- * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE
- * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT
- * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK
- *
- * @return AGESA_SUCCESS
- *
- */
-
-AGESA_STATUS
-MemPConstructPsRDr3 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- )
-{
- ASSERT (MemPtr != 0);
- ASSERT (ChannelPtr != 0);
-
-
- if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) {
- return AGESA_UNSUPPORTED;
- }
- if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
- return AGESA_UNSUPPORTED;
- }
- if (ChannelPtr->RegDimmPresent != ChannelPtr->ChDimmValid) {
- return AGESA_UNSUPPORTED;
- }
- PsPtr->MemPDoPs = MemPDoPsRDr3;
- PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitDef;
- return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for R-DDR3 DR DDR3
- *
- * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
- *
- * @return TRUE - Find settings for corresponding platform and dimm population.
- * @return FALSE - Fail to find settings for corresponding platform and dimm population.
- *
- */
-
-BOOLEAN
-STATIC
-MemPDoPsRDr3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- CONST DRAM_TERM_ENTRY *DramTermPtr;
- UINT8 MaxDimmsPerChannel;
- UINT8 *DimmsPerChPtr;
- UINT8 DramTermSize;
-
- DramTermSize = 0;
- DramTermPtr = NULL;
- DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
- if (DimmsPerChPtr != NULL) {
- MaxDimmsPerChannel = *DimmsPerChPtr;
- } else {
- MaxDimmsPerChannel = 2;
- }
-
- if (MaxDimmsPerChannel == 2) {
- DramTermSize = GET_SIZE_OF (DrRDdr3DramTerm2D);
- DramTermPtr = DrRDdr3DramTerm2D;
- } else if (MaxDimmsPerChannel == 3) {
- DramTermSize = GET_SIZE_OF (DrRDdr3DramTerm3D);
- DramTermPtr = DrRDdr3DramTerm3D;
- } else {
- IDS_ERROR_TRAP;
- }
-
- if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) {
- return FALSE;
- }
-
- return TRUE;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ps/DR/mpsdr3.c b/src/vendorcode/amd/agesa/Proc/Mem/Ps/DR/mpsdr3.c
deleted file mode 100644
index 6de04d9..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ps/DR/mpsdr3.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mpsdr3.c
- *
- * Platform specific settings for DR DDR3 SO-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/* This file contains routine that add platform specific support L1 */
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "mport.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "mu.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_PS_DR_MPSDR3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPDoPsSDr3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-STATIC CONST DRAM_TERM_ENTRY DrSDdr3DramTerm1D[] = {
- {DDR800, ONE_DIMM, NO_DIMM, 2, 0, 0},
- {DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}
-};
-
-STATIC CONST DRAM_TERM_ENTRY DrSDdr3DramTerm2D[] = {
- {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
- {DDR800, TWO_DIMM, NO_DIMM, 3, 0, 2},
- {DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
- {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
-};
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function is the constructor the platform specific settings for SO SIMM-DDR3 DR DDR3
- *
- * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE
- * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT
- * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK
- *
- * @return AGESA_SUCCESS
- *
- */
-
-AGESA_STATUS
-MemPConstructPsSDr3 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- )
-{
- ASSERT (MemPtr != 0);
- ASSERT (ChannelPtr != 0);
-
- if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) {
- return AGESA_UNSUPPORTED;
- }
- if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
- return AGESA_UNSUPPORTED;
- }
- if (ChannelPtr->SODimmPresent != ChannelPtr->ChDimmValid) {
- return AGESA_UNSUPPORTED;
- }
- PsPtr->MemPDoPs = MemPDoPsSDr3;
- PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitDef;
- return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for S-DDR3 DR DDR3
- *
- * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
- *
- * @return TRUE - Find settings for corresponding platform and dimm population.
- * @return FALSE - Fail to find settings for corresponding platform and dimm population.
- *
- */
-
-BOOLEAN
-STATIC
-MemPDoPsSDr3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- CONST DRAM_TERM_ENTRY *DramTermPtr;
- UINT8 MaxDimmsPerChannel;
- UINT8 *DimmsPerChPtr;
- UINT8 DramTermSize;
-
- DramTermSize = 0;
- DramTermPtr = NULL;
- DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
- if (DimmsPerChPtr != NULL) {
- MaxDimmsPerChannel = *DimmsPerChPtr;
- } else {
- MaxDimmsPerChannel = 2;
- }
-
- if (MaxDimmsPerChannel == 1) {
- DramTermSize = GET_SIZE_OF (DrSDdr3DramTerm1D);
- DramTermPtr = DrSDdr3DramTerm1D;
- } else if (MaxDimmsPerChannel == 2) {
- DramTermSize = GET_SIZE_OF (DrSDdr3DramTerm2D);
- DramTermPtr = DrSDdr3DramTerm2D;
- } else {
- IDS_ERROR_TRAP;
- }
-
- if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) {
- return FALSE;
- }
-
- return TRUE;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ps/DR/mpudr2.c b/src/vendorcode/amd/agesa/Proc/Mem/Ps/DR/mpudr2.c
deleted file mode 100644
index 66fe7d1..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ps/DR/mpudr2.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mpudr2.c
- *
- * Platform specific settings for DR DDR2 U-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/* This file contains routine that add platform specific support L1 */
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "mport.h"
-#include "PlatformMemoryConfiguration.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_PS_DR_MPUDR2_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPDoPsUDr2 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-STATIC CONST DRAM_TERM_ENTRY DrUDdr2DramTerm[] = {
- {DDR400 + DDR533 + DDR667, ONE_DIMM, ANY_NUM, 1, 0, 0},
- {DDR400 + DDR533, TWO_DIMM + THREE_DIMM + FOUR_DIMM, ANY_NUM, 1, 0, 0},
- {DDR667, TWO_DIMM + THREE_DIMM, ANY_NUM, 1, 0, 0},
- {DDR667, FOUR_DIMM, ANY_NUM, 3, 0, 0},
- {DDR800, ONE_DIMM, ANY_NUM, 1, 0, 0},
- {DDR800, TWO_DIMM + THREE_DIMM + FOUR_DIMM, ANY_NUM, 3, 0, 0},
- {DDR1066, ONE_DIMM, ANY_NUM, 1, 0, 0}
-};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function is the constructor platform specific settings for U DIMM-DDR2 DR DDR2
- *
- * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE
- * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT
- * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK
- *
- * @return AGESA_SUCCESS
- *
- */
-
-AGESA_STATUS
-MemPConstructPsUDr2 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- )
-{
- ASSERT (MemPtr != 0);
- ASSERT (ChannelPtr != 0);
-
-
- if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) {
- return AGESA_UNSUPPORTED;
- }
- if (ChannelPtr->TechType != DDR2_TECHNOLOGY) {
- return AGESA_UNSUPPORTED;
- }
- if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) {
- return AGESA_UNSUPPORTED;
- }
- PsPtr->MemPDoPs = MemPDoPsUDr2;
- PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitDef;
- return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for U-DDR2 DR DDR2
- *
- * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
- *
- * @return TRUE - Find settings for corresponding platform and dimm population.
- * @return FALSE - Fail to find settings for corresponding platform and dimm population.
- *
- */
-
-BOOLEAN
-STATIC
-MemPDoPsUDr2 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (DrUDdr2DramTerm), DrUDdr2DramTerm)) {
- return FALSE;
- }
-
- return TRUE;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ps/DR/mpudr3.c b/src/vendorcode/amd/agesa/Proc/Mem/Ps/DR/mpudr3.c
deleted file mode 100644
index 1d3acbb..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ps/DR/mpudr3.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mpudr3.c
- *
- * Platform specific settings for DR DDR3 U-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/* This file contains routine that add platform specific support L1 */
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "mport.h"
-#include "PlatformMemoryConfiguration.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_PS_DR_MPUDR3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPDoPsUDr3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-STATIC CONST DRAM_TERM_ENTRY DrUDdr3DramTerm[] = {
- {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
- {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
- {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
- {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
-};
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function is the constructor for the platform specific settings for U-DDR3 DR DDR3
- *
- * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE
- * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT
- * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK
- *
- * @return AGESA_SUCCESS
- *
- */
-
-AGESA_STATUS
-MemPConstructPsUDr3 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- )
-{
- ASSERT (MemPtr != 0);
- ASSERT (ChannelPtr != 0);
-
- if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) {
- return AGESA_UNSUPPORTED;
- }
- if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
- return AGESA_UNSUPPORTED;
- }
- if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) {
- return AGESA_UNSUPPORTED;
- }
- PsPtr->MemPDoPs = MemPDoPsUDr3;
- PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitDef;
- return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for U-DDR3 DR DDR3
- *
- * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
- *
- * @return TRUE - Find settings for corresponding platform and dimm population.
- * @return FALSE - Fail to find settings for corresponding platform and dimm population.
- *
- */
-
-BOOLEAN
-STATIC
-MemPDoPsUDr3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (DrUDdr3DramTerm), DrUDdr3DramTerm)) {
- return FALSE;
- }
-
- return TRUE;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ps/HY/mprhy3.c b/src/vendorcode/amd/agesa/Proc/Mem/Ps/HY/mprhy3.c
deleted file mode 100644
index 7e4764c..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ps/HY/mprhy3.c
+++ /dev/null
@@ -1,325 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mprhy3.c
- *
- * Platform specific settings for HY DDR3 R-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/* This file contains routine that add platform specific support L1 */
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "mport.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "mu.h"
-#include "GeneralServices.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-#define FILECODE PROC_MEM_PS_HY_MPRHY3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPDoPsRHy3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-STATIC
-MemPGetPORFreqLimitRHy3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*
- * ODT Settings for 1 Dimm or 2 Dimms Per Channel
- *
- * Speeds Supported, # of Dimms, # of QRDimms, DramTerm, QR DramTerm, Dynamic DramTerm
- */
-STATIC CONST DRAM_TERM_ENTRY HyRDdr3DramTerm2D[] = {
- {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
- {DDR667 + DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
- {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
- {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1},
- {DDR667 + DDR800 + DDR1066 + DDR1333, ONE_DIMM, ONE_DIMM, 0, 1, 2},
- {DDR1600, ONE_DIMM, ONE_DIMM, 0, 1, 1},
- {DDR667 + DDR800, TWO_DIMM, ONE_DIMM, 5, 1, 2},
- {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, ONE_DIMM, 5, 1, 1},
- {DDR667 + DDR800, TWO_DIMM, TWO_DIMM, 0, 1, 2},
- {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, TWO_DIMM, 0, 1, 1}
-};
-/*
- * ODT Settings for 3 Dimms Per Channel
- *
- * Speeds Supported, # of Dimms, # of QRDimms, DramTerm, QR DramTerm, Dynamic DramTerm
- */
-STATIC CONST DRAM_TERM_ENTRY HyRDdr3DramTerm3D[] = {
- {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
- {DDR667 + DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
- {DDR1333 + DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 2},
- {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, THREE_DIMM, NO_DIMM, 3, 0, 2},
- {DDR667 + DDR800 + DDR1066 + DDR1333, ONE_DIMM, ONE_DIMM, 0, 1, 2},
- {DDR667 + DDR800, TWO_DIMM, ONE_DIMM, 5, 1, 2},
- {DDR1066 + DDR1333 + DDR1600, TWO_DIMM, ONE_DIMM, 5, 1, 1},
- {DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600, THREE_DIMM, ONE_DIMM, 3, 1, 2}
-};
-/*
- * POR Max Frequency supported for specific Dimm configurations for 1 Dimm Per Channel
- *
- * Dimm Config, # of Dimms, Max Freq @ 1.5V, Max Freq @ 1.35V, Max Freq @ 1.25
- */
-STATIC CONST POR_SPEED_LIMIT HyRDdr3PSPorFreqLimit1D[] = {
- {SR_DIMM0 + DR_DIMM0, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0},
- {QR_DIMM0, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0}
-};
-/*
- * POR Max Frequency supported for specific Dimm configurations for 2 Dimms Per Channel
- *
- * Dimm Config, # of Dimms, Max Freq @ 1.5V, Max Freq @ 1.35V, Max Freq @ 1.25
- */
-STATIC CONST POR_SPEED_LIMIT HyRDdr3PSPorFreqLimit2D[] = {
- {SR_DIMM1 + DR_DIMM1, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0},
- {QR_DIMM1, 1, DDR1333_FREQUENCY, DDR1066_FREQUENCY, 0},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, 2, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0},
- {QR_DIMM0 + ANY_DIMM1, 2, DDR1066_FREQUENCY, DDR800_FREQUENCY, 0},
- {ANY_DIMM0 + QR_DIMM1, 2, DDR1066_FREQUENCY, DDR800_FREQUENCY, 0}
-};
-/*
- * POR Max Frequency supported for specific Dimm configurations for 3 Dimms Per Channel
- *
- * Dimm Config, # of Dimms, Max Freq @ 1.5V, Max Freq @ 1.35V, Max Freq @ 1.25
- */
-STATIC CONST POR_SPEED_LIMIT HyRDdr3PSPorFreqLimit3D[] = {
- {SR_DIMM2 + DR_DIMM2, 1, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, 2, DDR1333_FREQUENCY, DDR1333_FREQUENCY, 0},
- {QR_DIMM1, 1, DDR1066_FREQUENCY, DDR1066_FREQUENCY, 0},
- {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, 2, DDR800_FREQUENCY, DDR800_FREQUENCY, 0},
- {SR_DIMM0 + SR_DIMM1 + SR_DIMM2, 3, DDR1066_FREQUENCY, DDR1066_FREQUENCY, 0},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, 3, DDR1066_FREQUENCY, DDR800_FREQUENCY, 0},
- {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, 3, DDR800_FREQUENCY, DDR667_FREQUENCY, 0}
-};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function is the constructor platform specific settings for R DIMM-DDR3 HY DDR3
- *
- * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE
- * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT
- * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK
- *
- * @return AGESA_SUCCESS
- *
- */
-
-AGESA_STATUS
-MemPConstructPsRHy3 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- )
-{
- ASSERT (MemPtr != 0);
- ASSERT (ChannelPtr != 0);
-
- if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_HY) == 0) {
- return AGESA_UNSUPPORTED;
- }
- if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
- return AGESA_UNSUPPORTED;
- }
- if (ChannelPtr->RegDimmPresent != ChannelPtr->ChDimmValid) {
- return AGESA_UNSUPPORTED;
- }
- PsPtr->MemPDoPs = MemPDoPsRHy3;
- PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitRHy3;
-
- return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for R-DDR3 HY DDR3
- *
- * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
- *
- * @return TRUE - Find settings for corresponding platform and dimm population.
- * @return FALSE - Fail to find settings for corresponding platform and dimm population.
- *
- */
-
-BOOLEAN
-STATIC
-MemPDoPsRHy3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- CONST DRAM_TERM_ENTRY *DramTermPtr;
- UINT8 MaxDimmsPerChannel;
- UINT8 *DimmsPerChPtr;
- UINT8 DramTermSize;
-
- DramTermSize = 0;
- DramTermPtr = NULL;
- DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
- if (DimmsPerChPtr != NULL) {
- MaxDimmsPerChannel = *DimmsPerChPtr;
- } else {
- MaxDimmsPerChannel = 2;
- }
-
- if ((MaxDimmsPerChannel == 1) || (MaxDimmsPerChannel == 2)) {
- DramTermSize = GET_SIZE_OF (HyRDdr3DramTerm2D);
- DramTermPtr = HyRDdr3DramTerm2D;
- } else if (MaxDimmsPerChannel == 3) {
- DramTermSize = GET_SIZE_OF (HyRDdr3DramTerm3D);
- DramTermPtr = HyRDdr3DramTerm3D;
- } else {
- IDS_ERROR_TRAP;
- }
-
- if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) {
- return FALSE;
- }
- //
- // Special Cases for certain configs not covered by the table
- //
- // 3DPCH Fully populated.
- if ((MaxDimmsPerChannel == 3) && (NBPtr->ChannelPtr->Dimms == 3)) {
- NBPtr->PsPtr->DramTerm = 5; //30 Ohms
- NBPtr->PsPtr->QR_DramTerm = 1; // 60 Ohms
- }
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function gets the POR speed limit for R-DDR3 HY
- *
- * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
- *
- *
- */
-VOID
-STATIC
-MemPGetPORFreqLimitRHy3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 *DimmsPerChPtr;
- UINT8 MaxDimmPerCH;
- UINT8 FreqLimitSize;
- UINT16 SpeedLimit;
- CONST POR_SPEED_LIMIT *FreqLimitPtr;
- DCT_STRUCT *DCTPtr;
-
- DCTPtr = NBPtr->DCTPtr;
- DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
- if (DimmsPerChPtr != NULL) {
- MaxDimmPerCH = *DimmsPerChPtr;
- } else {
- MaxDimmPerCH = 2;
- }
-
- if (MaxDimmPerCH == 4) {
- DCTPtr->Timings.DimmExclude |= DCTPtr->Timings.DctDimmValid;
- PutEventLog (AGESA_CRITICAL, MEM_ERROR_UNSUPPORTED_DIMM_CONFIG, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_CRITICAL, NBPtr->MCTPtr);
- // Change target speed to highest value so it won't affect other channels when leveling frequency across the node.
- NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY;
- return;
- } else if (MaxDimmPerCH == 3) {
- FreqLimitPtr = HyRDdr3PSPorFreqLimit3D;
- FreqLimitSize = GET_SIZE_OF (HyRDdr3PSPorFreqLimit3D);
- } else if (MaxDimmPerCH == 2) {
- FreqLimitPtr = HyRDdr3PSPorFreqLimit2D;
- FreqLimitSize = GET_SIZE_OF (HyRDdr3PSPorFreqLimit2D);
- } else {
- FreqLimitPtr = HyRDdr3PSPorFreqLimit1D;
- FreqLimitSize = GET_SIZE_OF (HyRDdr3PSPorFreqLimit1D);
- }
-
- SpeedLimit = MemPGetPorFreqLimit (NBPtr, FreqLimitSize, FreqLimitPtr);
-
- if (SpeedLimit != 0) {
- if (DCTPtr->Timings.TargetSpeed > SpeedLimit) {
- DCTPtr->Timings.TargetSpeed = SpeedLimit;
- }
- } else {
- DCTPtr->Timings.DimmExclude |= DCTPtr->Timings.DctDimmValid;
- PutEventLog (AGESA_CRITICAL, MEM_ERROR_UNSUPPORTED_DIMM_CONFIG, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_CRITICAL, NBPtr->MCTPtr);
- // Change target speed to highest value so it won't affect other channels when leveling frequency across the node.
- NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY;
- }
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ps/HY/mpshy3.c b/src/vendorcode/amd/agesa/Proc/Mem/Ps/HY/mpshy3.c
deleted file mode 100644
index 2943777..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ps/HY/mpshy3.c
+++ /dev/null
@@ -1,221 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mpshy3.c
- *
- * Platform specific settings for HY DDR3 SO-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/* This file contains routine that add platform specific support L1 */
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "mport.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "mu.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_PS_HY_MPSHY3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPDoPsSHy3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-STATIC
-MemPGetPORFreqLimitSHy3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-STATIC CONST DRAM_TERM_ENTRY HySDdr3DramTerm1D[] = {
- {DDR800, ONE_DIMM, NO_DIMM, 2, 0, 0},
- {DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}
-};
-
-STATIC CONST DRAM_TERM_ENTRY HySDdr3DramTerm2D[] = {
- {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
- {DDR800, TWO_DIMM, NO_DIMM, 3, 0, 2},
- {DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
- {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
-};
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function is the constructor the platform specific settings for SO SIMM-DDR3 HY DDR3
- *
- * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE
- * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT
- * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK
- *
- * @return AGESA_SUCCESS
- *
- */
-
-AGESA_STATUS
-MemPConstructPsSHy3 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- )
-{
- ASSERT (MemPtr != 0);
- ASSERT (ChannelPtr != 0);
-
- if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_HY) == 0) {
- return AGESA_UNSUPPORTED;
- }
- if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
- return AGESA_UNSUPPORTED;
- }
- if (ChannelPtr->SODimmPresent != ChannelPtr->ChDimmValid) {
- return AGESA_UNSUPPORTED;
- }
- PsPtr->MemPDoPs = MemPDoPsSHy3;
- PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitSHy3;
- return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for S-DDR3 HY DDR3
- *
- * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
- *
- * @return TRUE - Find settings for corresponding platform and dimm population.
- * @return FALSE - Fail to find settings for corresponding platform and dimm population.
- *
- */
-
-BOOLEAN
-STATIC
-MemPDoPsSHy3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- CONST DRAM_TERM_ENTRY *DramTermPtr;
- UINT8 MaxDimmsPerChannel;
- UINT8 *DimmsPerChPtr;
- UINT8 DramTermSize;
-
- DramTermSize = 0;
- DramTermPtr = NULL;
- DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
- if (DimmsPerChPtr != NULL) {
- MaxDimmsPerChannel = *DimmsPerChPtr;
- } else {
- MaxDimmsPerChannel = 2;
- }
-
- if (MaxDimmsPerChannel == 1) {
- DramTermSize = GET_SIZE_OF (HySDdr3DramTerm1D);
- DramTermPtr = HySDdr3DramTerm1D;
- } else if (MaxDimmsPerChannel == 2) {
- DramTermSize = GET_SIZE_OF (HySDdr3DramTerm2D);
- DramTermPtr = HySDdr3DramTerm2D;
- } else {
- IDS_ERROR_TRAP;
- }
-
- if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) {
- return FALSE;
- }
-
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function gets the POR speed limit for SO-DDR3 HY
- *
- * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
- *
- *
- */
-VOID
-STATIC
-MemPGetPORFreqLimitSHy3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT16 MaxSpeed;
- //
- // Highest POR supported speed for SODimm is 1333
- //
- MaxSpeed = DDR1333_FREQUENCY;
- if (NBPtr->DCTPtr->Timings.TargetSpeed > MaxSpeed) {
- NBPtr->DCTPtr->Timings.TargetSpeed = MaxSpeed;
- }
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ps/HY/mpuhy3.c b/src/vendorcode/amd/agesa/Proc/Mem/Ps/HY/mpuhy3.c
deleted file mode 100644
index 344b04b..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ps/HY/mpuhy3.c
+++ /dev/null
@@ -1,199 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mpuhy3.c
- *
- * Platform specific settings for HY DDR3 U-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/* This file contains routine that add platform specific support L1 */
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mport.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_PS_HY_MPUHY3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPDoPsUhy3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-STATIC
-MemPGetPORFreqLimitUHy3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-STATIC CONST DRAM_TERM_ENTRY HyUDdr3DramTerm[] = {
- {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
- {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
- {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
- {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
-};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function is the constructor for the platform specific settings for U-DDR3 HY DDR3
- *
- * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE
- * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT
- * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK
- *
- * @return AGESA_SUCCESS
- *
- */
-
-AGESA_STATUS
-MemPConstructPsUHy3 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- )
-{
- ASSERT (MemPtr != 0);
- ASSERT (ChannelPtr != 0);
-
- if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_HY) == 0) {
- return AGESA_UNSUPPORTED;
- }
- if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
- return AGESA_UNSUPPORTED;
- }
- if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) {
- return AGESA_UNSUPPORTED;
- }
- PsPtr->MemPDoPs = MemPDoPsUhy3;
- PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitUHy3;
- return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for U-DDR3 HY DDR3
- *
- * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
- *
- * @return TRUE - Find settings for corresponding platform and dimm population.
- * @return FALSE - Fail to find settings for corresponding platform and dimm population.
- *
- */
-
-BOOLEAN
-STATIC
-MemPDoPsUhy3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (HyUDdr3DramTerm), HyUDdr3DramTerm)) {
- return FALSE;
- }
-
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function gets the POR speed limit for U-DDR3 HY
- *
- * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
- *
- *
- */
-VOID
-STATIC
-MemPGetPORFreqLimitUHy3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT16 MaxSpeed;
- //
- // Highest POR supported speed for Unbuffered dimm is 1333
- //
- MaxSpeed = DDR1333_FREQUENCY;
- if (NBPtr->DCTPtr->Timings.TargetSpeed > MaxSpeed) {
- NBPtr->DCTPtr->Timings.TargetSpeed = MaxSpeed;
- } else if (NBPtr->DCTPtr->Timings.TargetSpeed == DDR667_FREQUENCY) {
- // Unbuffered DDR3 at 333MHz is not supported
- NBPtr->DCTPtr->Timings.DimmExclude |= NBPtr->DCTPtr->Timings.DctDimmValid;
- PutEventLog (AGESA_ERROR, MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_ERROR, NBPtr->MCTPtr);
- // Change target speed to highest value so it won't affect other channels when leveling frequency across the node.
- NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY;
- }
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ps/NI/mpsNi3.c b/src/vendorcode/amd/agesa/Proc/Mem/Ps/NI/mpsNi3.c
deleted file mode 100644
index c6a8e23..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ps/NI/mpsNi3.c
+++ /dev/null
@@ -1,257 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mpsNi3.c
- *
- * Platform specific settings for Ni DDR3 SO-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/* This file contains routine that add platform specific support L1 */
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "mport.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "mu.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_PS_NI_MPSNI3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPDoPsSNi3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-STATIC
-MemPGetPORFreqLimitSNi3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-STATIC CONST DRAM_TERM_ENTRY NiSDdr3DramTerm1D[] = {
- {DDR800, ONE_DIMM, NO_DIMM, 2, 0, 0},
- {DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}
-};
-
-STATIC CONST DRAM_TERM_ENTRY NiSDdr3DramTerm2D[] = {
- {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
- {DDR800, TWO_DIMM, NO_DIMM, 3, 0, 2},
- {DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
- {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
-};
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function is the constructor the platform specific settings for SO-DIMM Ni DDR3
- *
- * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE
- * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT
- * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK
- *
- * @return AGESA_SUCCESS
- *
- */
-
-AGESA_STATUS
-MemPConstructPsSNi3 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- )
-{
- ASSERT (MemPtr != 0);
- ASSERT (ChannelPtr != 0);
-
- if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) {
- return AGESA_UNSUPPORTED;
- }
- if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
- return AGESA_UNSUPPORTED;
- }
- if (ChannelPtr->SODimmPresent != ChannelPtr->ChDimmValid) {
- return AGESA_UNSUPPORTED;
- }
-
- PsPtr->MemPDoPs = MemPDoPsSNi3;
- PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitSNi3;
- return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for SO-DIMM Ni DDR3
- *
- * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
- *
- * @return TRUE - Find settings for corresponding platform and dimm population.
- * @return FALSE - Fail to find settings for corresponding platform and dimm population.
- *
- */
-
-BOOLEAN
-STATIC
-MemPDoPsSNi3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- CONST DRAM_TERM_ENTRY *DramTermPtr;
- UINT8 MaxDimmsPerChannel;
- UINT8 *DimmsPerChPtr;
- UINT8 DramTermSize;
-
- DramTermSize = 0;
- DramTermPtr = NULL;
- DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
- if (DimmsPerChPtr != NULL) {
- MaxDimmsPerChannel = *DimmsPerChPtr;
- } else {
- MaxDimmsPerChannel = 2;
- }
-
- if (MaxDimmsPerChannel == 1) {
- DramTermSize = GET_SIZE_OF (NiSDdr3DramTerm1D);
- DramTermPtr = NiSDdr3DramTerm1D;
- } else if (MaxDimmsPerChannel == 2) {
- DramTermSize = GET_SIZE_OF (NiSDdr3DramTerm2D);
- DramTermPtr = NiSDdr3DramTerm2D;
- } else {
- IDS_ERROR_TRAP;
- }
-
- if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) {
- return FALSE;
- }
-
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function gets the POR speed limit for SO-DDR3 Ni
- *
- * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
- *
- *
- */
-VOID
-STATIC
-MemPGetPORFreqLimitSNi3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 *DimmsPerChPtr;
- UINT8 MaxDimmPerCH;
- UINT16 SpeedLimit;
-
- DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
- if (DimmsPerChPtr != NULL) {
- MaxDimmPerCH = *DimmsPerChPtr;
- } else {
- MaxDimmPerCH = 2;
- }
-
- if (MaxDimmPerCH == 1) {
- if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) {
- //
- // Highest POR supported speed for SODimm is 1333
- //
- SpeedLimit = DDR1333_FREQUENCY;
- } else {
- //
- // Max LV DDR3 Speed is 1066 for this silicon
- //
- SpeedLimit = DDR1066_FREQUENCY;
- }
- } else {
- //
- // Highest supported speed in 2DPC configuration is 1066
- //
- SpeedLimit = DDR1066_FREQUENCY;
- //
- // VOLT1_35 won't be supported while two DIMMs are populated in a channel
- //
- if ((NBPtr->RefPtr->DDR3Voltage == VOLT1_35) &&
- (NBPtr->ChannelPtr->Dimms == 2)) {
- NBPtr->RefPtr->DDR3Voltage = VOLT1_5;
- PutEventLog (AGESA_WARNING, MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_WARNING, NBPtr->MCTPtr);
- }
- }
- if (NBPtr->DCTPtr->Timings.TargetSpeed > SpeedLimit) {
- NBPtr->DCTPtr->Timings.TargetSpeed = SpeedLimit;
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ps/NI/mpuNi3.c b/src/vendorcode/amd/agesa/Proc/Mem/Ps/NI/mpuNi3.c
deleted file mode 100644
index c922816..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ps/NI/mpuNi3.c
+++ /dev/null
@@ -1,235 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mpuNi3.c
- *
- * Platform specific settings for Ni DDR3 U-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/* This file contains routine that add platform specific support L1 */
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "mport.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "mu.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_PS_NI_MPUNI3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPDoPsUNi3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-STATIC
-MemPGetPORFreqLimitUNi3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-STATIC CONST DRAM_TERM_ENTRY DrUDdr3DramTerm[] = {
- {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
- {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
- {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
- {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
-};
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function is the constructor for the platform specific settings for U-DDR3 Ni DDR3
- *
- * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE
- * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT
- * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK
- *
- * @return AGESA_SUCCESS
- *
- */
-
-AGESA_STATUS
-MemPConstructPsUNi3 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- )
-{
- ASSERT (MemPtr != 0);
- ASSERT (ChannelPtr != 0);
-
- if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & (AMD_FAMILY_10_DA | AMD_FAMILY_10_BL)) == 0) {
- return AGESA_UNSUPPORTED;
- }
- if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
- return AGESA_UNSUPPORTED;
- }
- if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) {
- return AGESA_UNSUPPORTED;
- }
-
- PsPtr->MemPDoPs = MemPDoPsUNi3;
- PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitUNi3;
- return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for U-DDR3 Ni DDR3
- *
- * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
- *
- * @return TRUE - Find settings for corresponding platform and dimm population.
- * @return FALSE - Fail to find settings for corresponding platform and dimm population.
- *
- */
-
-BOOLEAN
-STATIC
-MemPDoPsUNi3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (DrUDdr3DramTerm), DrUDdr3DramTerm)) {
- return FALSE;
- }
-
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function gets the POR speed limit for U-DDR3 Ni
- *
- * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
- *
- *
- */
-VOID
-STATIC
-MemPGetPORFreqLimitUNi3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 *DimmsPerChPtr;
- UINT8 MaxDimmPerCH;
- UINT16 SpeedLimit;
-
- DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
- if (DimmsPerChPtr != NULL) {
- MaxDimmPerCH = *DimmsPerChPtr;
- } else {
- MaxDimmPerCH = 2;
- }
-
- if (MaxDimmPerCH == 1) {
- if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) {
- //
- // Highest POR supported speed for Unbuffered dimm is 1333
- //
- SpeedLimit = DDR1333_FREQUENCY;
- } else {
- //
- // Max LV DDR3 Speed is 1066 for this silicon
- //
- SpeedLimit = DDR1066_FREQUENCY;
- }
- } else {
- //
- // Highest supported speed in 2DPC configuration is 1066
- //
- SpeedLimit = DDR1066_FREQUENCY;
- //
- // VOLT1_35 won't be supported while two DIMMs are populated in a channel
- //
- if ((NBPtr->RefPtr->DDR3Voltage == VOLT1_35) &&
- (NBPtr->ChannelPtr->Dimms == 2)) {
- NBPtr->RefPtr->DDR3Voltage = VOLT1_5;
- PutEventLog (AGESA_WARNING, MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_WARNING, NBPtr->MCTPtr);
- }
- }
- if (NBPtr->DCTPtr->Timings.TargetSpeed > SpeedLimit) {
- NBPtr->DCTPtr->Timings.TargetSpeed = SpeedLimit;
- } else if (NBPtr->DCTPtr->Timings.TargetSpeed == DDR667_FREQUENCY) {
- // Unbuffered DDR3 at 333MHz is not supported
- NBPtr->DCTPtr->Timings.DimmExclude |= NBPtr->DCTPtr->Timings.DctDimmValid;
- PutEventLog (AGESA_ERROR, MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_ERROR, NBPtr->MCTPtr);
- // Change target speed to highest value so it won't affect other channels when leveling frequency across the node.
- NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY;
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ps/ON/mpson3.c b/src/vendorcode/amd/agesa/Proc/Mem/Ps/ON/mpson3.c
deleted file mode 100644
index 4aa2969..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ps/ON/mpson3.c
+++ /dev/null
@@ -1,181 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mpson3.c
- *
- * Platform specific settings for ON DDR3 SO-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps/ON)
- * @e \$Revision: 38634 $ @e \$Date: 2010-09-27 21:39:01 +0800 (Mon, 27 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "mport.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "PlatformMemoryConfiguration.h"
-#include "Filecode.h"
-#define FILECODE PROC_MEM_PS_ON_MPSON3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-STATIC CONST DRAM_TERM_ENTRY OnSoDdr3DramTerm[] = {
- {DDR800 + DDR1066, ONE_DIMM, NO_DIMM, 2, 0, 0},
- {DDR1333, ONE_DIMM, NO_DIMM, 1, 0, 0},
- {DDR800, TWO_DIMM, NO_DIMM, 3, 0, 2},
- {DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2}
-};
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPDoPsSON3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-STATIC
-MemPGetPORFreqLimitSON3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function is the constructor the platform specific settings for SO SIMM-DDR3 ON DDR3
- *
- * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE
- * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT
- * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK
- *
- * @return AGESA_SUCCESS
- *
- */
-
-AGESA_STATUS
-MemPConstructPsSON3 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- )
-{
- ASSERT (MemPtr != 0);
- ASSERT (ChannelPtr != 0);
-
- if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_14_ON) == 0) {
- return AGESA_UNSUPPORTED;
- }
- if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
- return AGESA_UNSUPPORTED;
- }
- if (ChannelPtr->SODimmPresent != ChannelPtr->ChDimmValid) {
- return AGESA_UNSUPPORTED;
- }
- PsPtr->MemPDoPs = MemPDoPsSON3;
- PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitSON3;
- return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for S-DDR3 ON DDR3
- *
- * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
- *
- * @return TRUE - Find settings for corresponding platform and dimm population.
- * @return FALSE - Fail to find settings for corresponding platform and dimm population.
- *
- */
-
-BOOLEAN
-STATIC
-MemPDoPsSON3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (OnSoDdr3DramTerm), OnSoDdr3DramTerm)) {
- return FALSE;
- }
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function gets the POR speed limit for Sodimm DDR3 of ON
- *
- * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
- *
- *
- */
-
-VOID
-STATIC
-MemPGetPORFreqLimitSON3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- if ((NBPtr->DCTPtr->Timings.TargetSpeed == DDR1333_FREQUENCY) && (MemNGetBitFieldNb (NBPtr, BFFixedErrataSkipPorFreqCap) == 0)) {
- NBPtr->DCTPtr->Timings.TargetSpeed = DDR1066_FREQUENCY;
- }
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ps/ON/mpuon3.c b/src/vendorcode/amd/agesa/Proc/Mem/Ps/ON/mpuon3.c
deleted file mode 100644
index 6e62cc0..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ps/ON/mpuon3.c
+++ /dev/null
@@ -1,182 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mpuon3.c
- *
- * Platform specific settings for ON DDR3 U-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps/ON)
- * @e \$Revision: 38634 $ @e \$Date: 2010-09-27 21:39:01 +0800 (Mon, 27 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "AdvancedApi.h"
-#include "mport.h"
-#include "PlatformMemoryConfiguration.h"
-#include "ma.h"
-#include "cpuFamRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "Filecode.h"
-#define FILECODE PROC_MEM_PS_ON_MPUON3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPDoPsUON3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-STATIC
-MemPGetPORFreqLimitUON3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-STATIC CONST DRAM_TERM_ENTRY OnUDdr3DramTerm[] = {
- {DDR800 + DDR1066, ONE_DIMM, NO_DIMM, 2, 0, 0},
- {DDR1333, ONE_DIMM, NO_DIMM, 1, 0, 0},
- {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
- {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2}
-};
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function is the constructor for the platform specific settings for U-DDR3 ON DDR3
- *
- * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE
- * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT
- * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK
- *
- * @return AGESA_SUCCESS
- *
- */
-
-AGESA_STATUS
-MemPConstructPsUON3 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- )
-{
- ASSERT (MemPtr != 0);
- ASSERT (ChannelPtr != 0);
-
- if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_14_ON) == 0) {
- return AGESA_UNSUPPORTED;
- }
- if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
- return AGESA_UNSUPPORTED;
- }
- if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) {
- return AGESA_UNSUPPORTED;
- }
- PsPtr->MemPDoPs = MemPDoPsUON3;
- PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitUON3;
- return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for U-DDR3 ON DDR3
- *
- * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
- *
- * @return TRUE - Find settings for corresponding platform and dimm population.
- * @return FALSE - Fail to find settings for corresponding platform and dimm population.
- *
- */
-
-BOOLEAN
-STATIC
-MemPDoPsUON3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (OnUDdr3DramTerm), OnUDdr3DramTerm)) {
- return FALSE;
- }
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function gets the POR speed limit for U-DDR3 of ON
- *
- * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
- *
- *
- */
-
-VOID
-STATIC
-MemPGetPORFreqLimitUON3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- if ((NBPtr->DCTPtr->Timings.TargetSpeed == DDR1333_FREQUENCY) && (MemNGetBitFieldNb (NBPtr, BFFixedErrataSkipPorFreqCap) == 0)) {
- NBPtr->DCTPtr->Timings.TargetSpeed = DDR1066_FREQUENCY;
- }
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ps/PH/mpsph3.c b/src/vendorcode/amd/agesa/Proc/Mem/Ps/PH/mpsph3.c
deleted file mode 100644
index 755abf5..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ps/PH/mpsph3.c
+++ /dev/null
@@ -1,257 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mpsPh3.c
- *
- * Platform specific settings for Ph DDR3 SO-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/* This file contains routine that add platform specific support L1 */
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "mport.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "mu.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_PS_PH_MPSPH3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPDoPsSPh3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-STATIC
-MemPGetPORFreqLimitSPh3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-STATIC CONST DRAM_TERM_ENTRY PhSDdr3DramTerm1D[] = {
- {DDR800, ONE_DIMM, NO_DIMM, 2, 0, 0},
- {DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}
-};
-
-STATIC CONST DRAM_TERM_ENTRY PhSDdr3DramTerm2D[] = {
- {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
- {DDR800, TWO_DIMM, NO_DIMM, 3, 0, 2},
- {DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
- {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
-};
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function is the constructor the platform specific settings for SO-DIMM Ph DDR3
- *
- * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE
- * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT
- * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK
- *
- * @return AGESA_SUCCESS
- *
- */
-
-AGESA_STATUS
-MemPConstructPsSPh3 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- )
-{
- ASSERT (MemPtr != 0);
- ASSERT (ChannelPtr != 0);
-
- if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_PH) == 0) {
- return AGESA_UNSUPPORTED;
- }
- if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
- return AGESA_UNSUPPORTED;
- }
- if (ChannelPtr->SODimmPresent != ChannelPtr->ChDimmValid) {
- return AGESA_UNSUPPORTED;
- }
-
- PsPtr->MemPDoPs = MemPDoPsSPh3;
- PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitSPh3;
- return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for SO-DIMM Ph DDR3
- *
- * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
- *
- * @return TRUE - Find settings for corresponding platform and dimm population.
- * @return FALSE - Fail to find settings for corresponding platform and dimm population.
- *
- */
-
-BOOLEAN
-STATIC
-MemPDoPsSPh3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- CONST DRAM_TERM_ENTRY *DramTermPtr;
- UINT8 MaxDimmsPerChannel;
- UINT8 *DimmsPerChPtr;
- UINT8 DramTermSize;
-
- DramTermSize = 0;
- DramTermPtr = NULL;
- DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
- if (DimmsPerChPtr != NULL) {
- MaxDimmsPerChannel = *DimmsPerChPtr;
- } else {
- MaxDimmsPerChannel = 2;
- }
-
- if (MaxDimmsPerChannel == 1) {
- DramTermSize = GET_SIZE_OF (PhSDdr3DramTerm1D);
- DramTermPtr = PhSDdr3DramTerm1D;
- } else if (MaxDimmsPerChannel == 2) {
- DramTermSize = GET_SIZE_OF (PhSDdr3DramTerm2D);
- DramTermPtr = PhSDdr3DramTerm2D;
- } else {
- IDS_ERROR_TRAP;
- }
-
- if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) {
- return FALSE;
- }
-
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function gets the POR speed limit for SO-DDR3 Ph
- *
- * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
- *
- *
- */
-VOID
-STATIC
-MemPGetPORFreqLimitSPh3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 *DimmsPerChPtr;
- UINT8 MaxDimmPerCH;
- UINT16 SpeedLimit;
-
- DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
- if (DimmsPerChPtr != NULL) {
- MaxDimmPerCH = *DimmsPerChPtr;
- } else {
- MaxDimmPerCH = 2;
- }
-
- if (MaxDimmPerCH == 1) {
- if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) {
- //
- // Highest POR supported speed for SODimm is 1333
- //
- SpeedLimit = DDR1333_FREQUENCY;
- } else {
- //
- // Max LV DDR3 Speed is 1066 for this silicon
- //
- SpeedLimit = DDR1066_FREQUENCY;
- }
- } else {
- //
- // Highest supported speed in 2DPC configuration is 1066
- //
- SpeedLimit = DDR1066_FREQUENCY;
- //
- // VOLT1_35 won't be supported while two DIMMs are populated in a channel
- //
- if ((NBPtr->RefPtr->DDR3Voltage == VOLT1_35) &&
- (NBPtr->ChannelPtr->Dimms == 2)) {
- NBPtr->RefPtr->DDR3Voltage = VOLT1_5;
- PutEventLog (AGESA_WARNING, MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_WARNING, NBPtr->MCTPtr);
- }
- }
- if (NBPtr->DCTPtr->Timings.TargetSpeed > SpeedLimit) {
- NBPtr->DCTPtr->Timings.TargetSpeed = SpeedLimit;
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ps/PH/mpuph3.c b/src/vendorcode/amd/agesa/Proc/Mem/Ps/PH/mpuph3.c
deleted file mode 100644
index bcbff94..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ps/PH/mpuph3.c
+++ /dev/null
@@ -1,211 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mpuPh3.c
- *
- * Platform specific settings for Ph DDR3 U-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/* This file contains routine that add platform specific support L1 */
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "mport.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "mu.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_PS_PH_MPUPH3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPDoPsUPh3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-STATIC
-MemPGetPORFreqLimitUPh3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-STATIC CONST DRAM_TERM_ENTRY DrUDdr3DramTerm[] = {
- {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
- {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
- {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
- {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
-};
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function is the constructor for the platform specific settings for U-DDR3 Ph DDR3
- *
- * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE
- * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT
- * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK
- *
- * @return AGESA_SUCCESS
- *
- */
-
-AGESA_STATUS
-MemPConstructPsUPh3 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- )
-{
- ASSERT (MemPtr != 0);
- ASSERT (ChannelPtr != 0);
-
- if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_PH) == 0) {
- return AGESA_UNSUPPORTED;
- }
- if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
- return AGESA_UNSUPPORTED;
- }
- if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) {
- return AGESA_UNSUPPORTED;
- }
-
- PsPtr->MemPDoPs = MemPDoPsUPh3;
- PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitUPh3;
- return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for U-DDR3 Ph DDR3
- *
- * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
- *
- * @return TRUE - Find settings for corresponding platform and dimm population.
- * @return FALSE - Fail to find settings for corresponding platform and dimm population.
- *
- */
-
-BOOLEAN
-STATIC
-MemPDoPsUPh3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (DrUDdr3DramTerm), DrUDdr3DramTerm)) {
- return FALSE;
- }
-
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function gets the POR speed limit for U-DDR3 Ph
- *
- * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
- *
- *
- */
-VOID
-STATIC
-MemPGetPORFreqLimitUPh3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT16 SpeedLimit;
-
- if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) {
- //
- // Highest POR supported speed for Unbuffered dimm is 1333
- //
- SpeedLimit = DDR1333_FREQUENCY;
- } else {
- //
- // Max LV DDR3 Speed is 1066 for this silicon
- //
- SpeedLimit = DDR1066_FREQUENCY;
- }
-
- if (NBPtr->DCTPtr->Timings.TargetSpeed > SpeedLimit) {
- NBPtr->DCTPtr->Timings.TargetSpeed = SpeedLimit;
- } else if (NBPtr->DCTPtr->Timings.TargetSpeed == DDR667_FREQUENCY) {
- // Unbuffered DDR3 at 333MHz is not supported
- NBPtr->DCTPtr->Timings.DimmExclude |= NBPtr->DCTPtr->Timings.DctDimmValid;
- PutEventLog (AGESA_ERROR, MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_ERROR, NBPtr->MCTPtr);
- // Change target speed to highest value so it won't affect other channels when leveling frequency across the node.
- NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY;
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ps/RB/mpsRb3.c b/src/vendorcode/amd/agesa/Proc/Mem/Ps/RB/mpsRb3.c
deleted file mode 100644
index 2e1ffdc..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ps/RB/mpsRb3.c
+++ /dev/null
@@ -1,257 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mpsRb3.c
- *
- * Platform specific settings for RB DDR3 SO-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/* This file contains routine that add platform specific support L1 */
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "mport.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "mu.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_PS_RB_MPSRB3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPDoPsSRb3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-STATIC
-MemPGetPORFreqLimitSRb3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-STATIC CONST DRAM_TERM_ENTRY RbSDdr3DramTerm1D[] = {
- {DDR800, ONE_DIMM, NO_DIMM, 2, 0, 0},
- {DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0}
-};
-
-STATIC CONST DRAM_TERM_ENTRY RbSDdr3DramTerm2D[] = {
- {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
- {DDR800, TWO_DIMM, NO_DIMM, 3, 0, 2},
- {DDR1066 + DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
- {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
-};
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function is the constructor the platform specific settings for SO-DIMM RB DDR3
- *
- * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE
- * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT
- * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK
- *
- * @return AGESA_SUCCESS
- *
- */
-
-AGESA_STATUS
-MemPConstructPsSRb3 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- )
-{
- ASSERT (MemPtr != 0);
- ASSERT (ChannelPtr != 0);
-
- if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) {
- return AGESA_UNSUPPORTED;
- }
- if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
- return AGESA_UNSUPPORTED;
- }
- if (ChannelPtr->SODimmPresent != ChannelPtr->ChDimmValid) {
- return AGESA_UNSUPPORTED;
- }
-
- PsPtr->MemPDoPs = MemPDoPsSRb3;
- PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitSRb3;
- return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for SO-DIMM RB DDR3
- *
- * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
- *
- * @return TRUE - Find settings for corresponding platform and dimm population.
- * @return FALSE - Fail to find settings for corresponding platform and dimm population.
- *
- */
-
-BOOLEAN
-STATIC
-MemPDoPsSRb3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- CONST DRAM_TERM_ENTRY *DramTermPtr;
- UINT8 MaxDimmsPerChannel;
- UINT8 *DimmsPerChPtr;
- UINT8 DramTermSize;
-
- DramTermSize = 0;
- DramTermPtr = NULL;
- DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
- if (DimmsPerChPtr != NULL) {
- MaxDimmsPerChannel = *DimmsPerChPtr;
- } else {
- MaxDimmsPerChannel = 2;
- }
-
- if (MaxDimmsPerChannel == 1) {
- DramTermSize = GET_SIZE_OF (RbSDdr3DramTerm1D);
- DramTermPtr = RbSDdr3DramTerm1D;
- } else if (MaxDimmsPerChannel == 2) {
- DramTermSize = GET_SIZE_OF (RbSDdr3DramTerm2D);
- DramTermPtr = RbSDdr3DramTerm2D;
- } else {
- IDS_ERROR_TRAP;
- }
-
- if (!MemPGetDramTerm (NBPtr, DramTermSize, DramTermPtr)) {
- return FALSE;
- }
-
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function gets the POR speed limit for SO-DDR3 RB
- *
- * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
- *
- *
- */
-VOID
-STATIC
-MemPGetPORFreqLimitSRb3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 *DimmsPerChPtr;
- UINT8 MaxDimmPerCH;
- UINT16 SpeedLimit;
-
- DimmsPerChPtr = FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MAX_DIMMS, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID);
- if (DimmsPerChPtr != NULL) {
- MaxDimmPerCH = *DimmsPerChPtr;
- } else {
- MaxDimmPerCH = 2;
- }
-
- if (MaxDimmPerCH == 1) {
- if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) {
- //
- // Highest POR supported speed for SODimm is 1333
- //
- SpeedLimit = DDR1333_FREQUENCY;
- } else {
- //
- // Max LV DDR3 Speed is 1066 for this silicon
- //
- SpeedLimit = DDR1066_FREQUENCY;
- }
- } else {
- //
- // Highest supported speed in 2DPC configuration is 1066
- //
- SpeedLimit = DDR1066_FREQUENCY;
- //
- // VOLT1_35 won't be supported while two DIMMs are populated in a channel
- //
- if ((NBPtr->RefPtr->DDR3Voltage == VOLT1_35) &&
- (NBPtr->ChannelPtr->Dimms == 2)) {
- NBPtr->RefPtr->DDR3Voltage = VOLT1_5;
- PutEventLog (AGESA_WARNING, MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_WARNING, NBPtr->MCTPtr);
- }
- }
- if (NBPtr->DCTPtr->Timings.TargetSpeed > SpeedLimit) {
- NBPtr->DCTPtr->Timings.TargetSpeed = SpeedLimit;
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ps/RB/mpuRb3.c b/src/vendorcode/amd/agesa/Proc/Mem/Ps/RB/mpuRb3.c
deleted file mode 100644
index ebe4f25..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ps/RB/mpuRb3.c
+++ /dev/null
@@ -1,211 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mpuRb3.c
- *
- * Platform specific settings for RB DDR3 U-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/* This file contains routine that add platform specific support L1 */
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "mport.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "mu.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_PS_RB_MPURB3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPDoPsURb3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-STATIC
-MemPGetPORFreqLimitURb3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-STATIC CONST DRAM_TERM_ENTRY DrUDdr3DramTerm[] = {
- {DDR800 + DDR1066 + DDR1333 + DDR1600, ONE_DIMM, NO_DIMM, 1, 0, 0},
- {DDR800 + DDR1066, TWO_DIMM, NO_DIMM, 3, 0, 2},
- {DDR1333, TWO_DIMM, NO_DIMM, 5, 0, 2},
- {DDR1600, TWO_DIMM, NO_DIMM, 5, 0, 1}
-};
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function is the constructor for the platform specific settings for U-DDR3 RB DDR3
- *
- * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE
- * @param[in,out] *ChannelPtr Pointer to CH_DEF_STRUCT
- * @param[in,out] *PsPtr Pointer to MEM_PS_BLOCK
- *
- * @return AGESA_SUCCESS
- *
- */
-
-AGESA_STATUS
-MemPConstructPsURb3 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- )
-{
- ASSERT (MemPtr != 0);
- ASSERT (ChannelPtr != 0);
-
- if ((ChannelPtr->MCTPtr->LogicalCpuid.Family & AMD_FAMILY_10_RB) == 0) {
- return AGESA_UNSUPPORTED;
- }
- if (ChannelPtr->TechType != DDR3_TECHNOLOGY) {
- return AGESA_UNSUPPORTED;
- }
- if ((ChannelPtr->RegDimmPresent != 0) || (ChannelPtr->SODimmPresent != 0)) {
- return AGESA_UNSUPPORTED;
- }
-
- PsPtr->MemPDoPs = MemPDoPsURb3;
- PsPtr->MemPGetPORFreqLimit = MemPGetPORFreqLimitURb3;
- return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for U-DDR3 RB DDR3
- *
- * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
- *
- * @return TRUE - Find settings for corresponding platform and dimm population.
- * @return FALSE - Fail to find settings for corresponding platform and dimm population.
- *
- */
-
-BOOLEAN
-STATIC
-MemPDoPsURb3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- if (!MemPGetDramTerm (NBPtr, GET_SIZE_OF (DrUDdr3DramTerm), DrUDdr3DramTerm)) {
- return FALSE;
- }
-
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function gets the POR speed limit for U-DDR3 RB
- *
- * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
- *
- *
- */
-VOID
-STATIC
-MemPGetPORFreqLimitURb3 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT16 SpeedLimit;
-
- if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) {
- //
- // Highest POR supported speed for Unbuffered dimm is 1333
- //
- SpeedLimit = DDR1333_FREQUENCY;
- } else {
- //
- // Max LV DDR3 Speed is 1066 for this silicon
- //
- SpeedLimit = DDR1066_FREQUENCY;
- }
-
- if (NBPtr->DCTPtr->Timings.TargetSpeed > SpeedLimit) {
- NBPtr->DCTPtr->Timings.TargetSpeed = SpeedLimit;
- } else if (NBPtr->DCTPtr->Timings.TargetSpeed == DDR667_FREQUENCY) {
- // Unbuffered DDR3 at 333MHz is not supported
- NBPtr->DCTPtr->Timings.DimmExclude |= NBPtr->DCTPtr->Timings.DctDimmValid;
- PutEventLog (AGESA_ERROR, MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_ERROR, NBPtr->MCTPtr);
- // Change target speed to highest value so it won't affect other channels when leveling frequency across the node.
- NBPtr->DCTPtr->Timings.TargetSpeed = UNSUPPORTED_DDR_FREQUENCY;
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ps/mp.c b/src/vendorcode/amd/agesa/Proc/Mem/Ps/mp.c
deleted file mode 100644
index 6e4e77a..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ps/mp.c
+++ /dev/null
@@ -1,510 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mp.c
- *
- * Common platform specific configuration.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "cpuRegisters.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mu.h"
-#include "ma.h"
-#include "mp.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_PS_MP_FILECODE
-
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemPPSCGen (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN MEM_PSC_TABLE_BLOCK *EntryOfTables
- );
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-extern MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[];
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is the default return function of the Platform Specific block. The function always
- * returns AGESA_UNSUPPORTED
- *
- * @param[in,out] *MemPtr Pointer to MEM_DATA_STRUCTURE
- * @param[in] *ChannelPtr Pointer to CH_DEF_STRUCT
- * @param[in] *PsPtr Pointer to MEM_PS_BLOCK
- *
- * @return AGESA_UNSUPPORTED AGESA status indicating that default is unsupported
- *
- */
-
-AGESA_STATUS
-MemPConstructPsUDef (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- )
-{
- return AGESA_UNSUPPORTED;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function will set the DramTerm and DramTermDyn in the structure of a channel.
- *
- * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
- * @param[in] ArraySize Size of the array of DramTerm
- * @param[in] *DramTermPtr Address the array of DramTerm
- *
- * @return TRUE - Find DramTerm and DramTermDyn for corresponding platform and dimm population.
- * @return FALSE - Fail to find DramTerm and DramTermDyn for corresponding platform and dimm population.
- *
- */
-BOOLEAN
-MemPGetDramTerm (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 ArraySize,
- IN CONST DRAM_TERM_ENTRY *DramTermPtr
- )
-{
- UINT8 Dimms;
- UINT8 QR_Dimms;
- UINT8 i;
- Dimms = NBPtr->ChannelPtr->Dimms;
- QR_Dimms = 0;
- for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i ++) {
- if (((NBPtr->ChannelPtr->DimmQrPresent & (UINT16) (1 << i)) != 0) && (i < 2)) {
- QR_Dimms ++;
- }
- }
-
- for (i = 0; i < ArraySize; i ++) {
- if ((DramTermPtr[i].Speed & ((UINT32) 1 << (NBPtr->DCTPtr->Timings.Speed / 66))) != 0) {
- if ((((UINT8) (1 << (Dimms - 1)) & DramTermPtr[i].Dimms) != 0) || (DramTermPtr[i].Dimms == ANY_NUM)) {
- if (((QR_Dimms == 0) && (DramTermPtr[i].QR_Dimms == NO_DIMM)) ||
- ((QR_Dimms > 0) && (((UINT8) (1 << (QR_Dimms - 1)) & DramTermPtr[i].QR_Dimms) != 0)) ||
- (DramTermPtr[i].QR_Dimms == ANY_NUM)) {
- NBPtr->PsPtr->DramTerm = DramTermPtr[i].DramTerm;
- NBPtr->PsPtr->QR_DramTerm = DramTermPtr[i].QR_DramTerm;
- NBPtr->PsPtr->DynamicDramTerm = DramTermPtr[i].DynamicDramTerm;
- break;
- }
- }
- }
- }
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function gets the highest POR supported speed.
- *
- * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
- * @param[in] FreqLimitSize Size of the array of Frequency Limit
- * @param[in] *FreqLimitPtr Address the array of Frequency Limit
- *
- * @return UINT8 - frequency limit
- *
- */
-UINT16
-MemPGetPorFreqLimit (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 FreqLimitSize,
- IN CONST POR_SPEED_LIMIT *FreqLimitPtr
- )
-{
- UINT8 i;
- UINT8 j;
- UINT8 DimmTpMatch;
- UINT16 SpeedLimit;
- UINT16 DIMMRankType;
- UINT16 _DIMMRankType;
-
- SpeedLimit = 0;
- DIMMRankType = MemAGetPsRankType (NBPtr->ChannelPtr);
- for (i = 0; i < FreqLimitSize; i++, FreqLimitPtr++) {
- if (NBPtr->ChannelPtr->Dimms != FreqLimitPtr->Dimms) {
- continue;
- }
- DimmTpMatch = 0;
- _DIMMRankType = DIMMRankType & FreqLimitPtr->DIMMRankType;
- for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j ++) {
- if ((_DIMMRankType & (UINT16) 0x0F << (j << 2)) != 0) {
- DimmTpMatch++;
- }
- }
- if (DimmTpMatch == FreqLimitPtr->Dimms) {
- if (NBPtr->RefPtr->DDR3Voltage == VOLT1_5) {
- SpeedLimit = FreqLimitPtr->SpeedLimit_1_5V;
- break;
- } else if (NBPtr->RefPtr->DDR3Voltage == VOLT1_25) {
- SpeedLimit = FreqLimitPtr->SpeedLimit_1_25V;
- break;
- } else {
- SpeedLimit = FreqLimitPtr->SpeedLimit_1_35V;
- break;
- }
- }
- }
-
- return SpeedLimit;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function is the default function for getting POR speed limit. When a
- * package does not need to cap the speed, it should use this function to initialize
- * the corresponding function pointer.
- *
- * @param[in,out] *NBPtr Pointer to MEM_NB_BLOCK
- *
- */
-VOID
-MemPGetPORFreqLimitDef (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function gets platform specific configuration such as Max Freq., Slow Mode, Dram Term,
- * and so on.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - Successfully execute platform specific configuration flow.
- * @return FALSE - Fail to execute platform specific configuration flow.
- *
- */
-BOOLEAN
-MemPPSCFlow (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 i;
-
- i = 0;
- while (memPlatSpecFlowArray[i] != NULL) {
- if ((memPlatSpecFlowArray[i])->DramTerm (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) {
- if ((memPlatSpecFlowArray[i])->ODTPattern (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) {
- if ((memPlatSpecFlowArray[i])->SAO (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) {
- if ((memPlatSpecFlowArray[i])->MR0WrCL (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) {
- if ((memPlatSpecFlowArray[i])->RC2IBT (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) {
- if ((memPlatSpecFlowArray[i])->RC10OpSpeed (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) {
- if ((memPlatSpecFlowArray[i])->LRIBT (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) {
- if ((memPlatSpecFlowArray[i])->LRNPR (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) {
- if ((memPlatSpecFlowArray[i])->LRNLR (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) {
- if (MemPPSCGen (NBPtr, (memPlatSpecFlowArray[i])->EntryOfTables)) {
- return TRUE;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- i++;
- }
- return FALSE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function constructs the rank type map of Dimm0, Dimm1, Dimm2. Also it counts the number
- * of dimm in the table.
- *
- * @param[in] Dimm0 Rank type of Dimm0
- * @param[in] Dimm1 Rank type of Dimm1
- * @param[in] Dimm2 Rank type of Dimm2
- * @param[in, out] *RankTypeInTable Pointer to RankTypeInTable variable
- *
- *
- */
-VOID
-MemPConstructRankTypeMap (
- IN UINT16 Dimm0,
- IN UINT16 Dimm1,
- IN UINT16 Dimm2,
- IN OUT UINT16 *RankTypeInTable
- )
-{
- UINT8 i;
- UINT16 RT;
- UINT8 BitShift;
-
- *RankTypeInTable = 0;
- RT = 0;
- BitShift = 0;
-
- for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) {
- switch (i) {
- case 0:
- RT = (Dimm0 == 0) ? NP : Dimm0;
- BitShift = 0;
- break;
- case 1:
- RT = (Dimm1 == 0) ? NP : Dimm1;
- BitShift = 4;
- break;
- case 2:
- RT = (Dimm2 == 0) ? NP : Dimm2;
- BitShift = 8;
- break;
- default:
- // dimm3 is not used, fills nibble3 with "NP"
- RT = NP;
- BitShift = 12;
- }
- *RankTypeInTable |= RT << BitShift;
- }
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- * MemPIsIdSupported
- * This function matches the CPU_LOGICAL_ID and PackageType with certain criteria to
- * determine if it is supported by this NB type.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] LogicalId - CPU_LOGICAL_ID
- * @param[in] PackageType - Package Type
- *
- * @return TRUE - NB type is matched !
- * @return FALSE - NB type is not matched !
- *
- */
-BOOLEAN
-MemPIsIdSupported (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN CPU_LOGICAL_ID LogicalId,
- IN UINT8 PackageType
- )
-{
- CPUID_DATA CpuId;
- UINT8 PkgType;
-
- LibAmdCpuidRead (AMD_CPUID_FMF, &CpuId, &(NBPtr->MemPtr->StdHeader));
- PkgType = (UINT8) (CpuId.EBX_Reg >> 28) & 0xF; // bit 31:28
-
- if (((NBPtr->MCTPtr->LogicalCpuid.Family & LogicalId.Family) != 0)
- && ((NBPtr->MCTPtr->LogicalCpuid.Revision & LogicalId.Revision) != 0)) {
- if ((PackageType == PT_DONT_CARE) || (PackageType == PkgType)) {
- return TRUE;
- }
- }
- return FALSE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function returns the rank type map of a channel.
- *
- * @param[in] *CurrentChannel Pointer to CH_DEF_STRUCT
- *
- * @return UINT16 - The map of rank type.
- *
- */
-UINT16
-MemPGetPsRankType (
- IN CH_DEF_STRUCT *CurrentChannel
- )
-{
- UINT8 i;
- UINT16 DIMMRankType;
-
- DIMMRankType = 0;
- for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) {
- if ((CurrentChannel->DimmQrPresent & (UINT8) 1 << i) != 0) {
- if (i < 2) {
- DIMMRankType |= (UINT16) 8 << (i << 2);
- }
- } else if ((CurrentChannel->DimmDrPresent & (UINT8) 1 << i) != 0) {
- DIMMRankType |= (UINT16) 4 << (i << 2);
- } else if ((CurrentChannel->DimmSRPresent & (UINT8) 1 << i) != 0) {
- DIMMRankType |= (UINT16) 2 << (i << 2);
- } else {
- DIMMRankType |= (UINT16) 1 << (i << 2);
- }
- }
-
- //@todo construct DIMMRankType for LRDIMM
-
- return DIMMRankType;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function performs the action for the rest of platform specific configuration such as
- * tri-state stuff
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] *EntryOfTables Pointer to MEM_PSC_TABLE_BLOCK
- *
- * @return TRUE - No error occurred.
- * @return FALSE - Error occurred.
- *
- */
-BOOLEAN
-STATIC
-MemPPSCGen (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN MEM_PSC_TABLE_BLOCK *EntryOfTables
- )
-{
- UINT8 i;
- PSCFG_TYPE PSCType;
- DIMM_TYPE DimmType;
- UINT8 MaxDimmPerCh;
- UINT8 NOD;
- CPU_LOGICAL_ID LogicalCpuid;
- UINT8 PackageType;
- CH_DEF_STRUCT *CurrentChannel;
-
- CurrentChannel = NBPtr->ChannelPtr;
-
- PackageType = 0;
- LogicalCpuid.Family = AMD_FAMILY_UNKNOWN;
- MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID);
- NOD = (UINT8) 1 << (MaxDimmPerCh - 1);
-
- if (CurrentChannel->RegDimmPresent != 0) {
- DimmType = RDIMM_TYPE;
- } else if (CurrentChannel->SODimmPresent != 0) {
- DimmType = SODIMM_TYPE;
- //@todo LRDIMM
- //} else if (CurrentChannel->LrDimmPresent) {
- // DimmType = LRDIMM_TYPE;
- } else {
- DimmType = UDIMM_TYPE;
- }
-
- for (PSCType = PSCFG_GEN_START + 1; PSCType < PSCFG_GEN_END; PSCType++) {
- i = 0;
- while (EntryOfTables->TblEntryOfGen[i] != NULL) {
- if ((EntryOfTables->TblEntryOfGen[i])->Header.PSCType == PSCType) {
- if (((EntryOfTables->TblEntryOfGen[i])->Header.DimmType & DimmType) != 0) {
- if (((EntryOfTables->TblEntryOfGen[i])->Header.NumOfDimm & NOD) != 0) {
- //
- // Determine if this is the expected NB Type
- //
- LogicalCpuid = (EntryOfTables->TblEntryOfGen[i])->Header.LogicalCpuid;
- PackageType = (EntryOfTables->TblEntryOfGen[i])->Header.PackageType;
- if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) {
- break;
- }
- }
- }
- }
- i++;
- }
-
- // Check whether no table entry is found.
- if (EntryOfTables->TblEntryOfGen[i] == NULL) {
- return FALSE;
- }
-
- // Perform the action for specific PSCType.
- if (PSCType == PSCFG_CLKDIS) {
- CurrentChannel->MemClkDisMap = (UINT8 *) (EntryOfTables->TblEntryOfGen[i])->TBLPtr;
- } else if (PSCType == PSCFG_CKETRI) {
- CurrentChannel->CKETriMap = (UINT8 *) (EntryOfTables->TblEntryOfGen[i])->TBLPtr;
- } else if (PSCType == PSCFG_ODTTRI) {
- CurrentChannel->ODTTriMap = (UINT8 *) (EntryOfTables->TblEntryOfGen[i])->TBLPtr;
- } else if (PSCType == PSCFG_CSTRI) {
- CurrentChannel->ChipSelTriMap = (UINT8 *) (EntryOfTables->TblEntryOfGen[i])->TBLPtr;
- }
- }
-
- CurrentChannel->DctEccDqsLike = 0x0403;
- CurrentChannel->DctEccDqsScale = 0x70;
-
- return TRUE;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ps/mplribt.c b/src/vendorcode/amd/agesa/Proc/Mem/Ps/mplribt.c
deleted file mode 100644
index c86ba86..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ps/mplribt.c
+++ /dev/null
@@ -1,190 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mplribt.c
- *
- * A sub-engine which extracts F0RC8, F1RC0, F1RC1 and F1RC2 value for LRDIMM configuration.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 37655 $ @e \$Date: 2010-09-09 11:15:05 +0800 (Thu, 09 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "cpuRegisters.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mu.h"
-#include "ma.h"
-#include "mp.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-#define FILECODE PROC_MEM_PS_MPLRIBT_FILECODE
-
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * A sub-function which extracts LRDIMM F0RC8, F1RC0, F1RC1 and F1RC2 value from a input
- * table and stores extracted value to a specific address.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK
- *
- * @return TRUE - Succeed in extracting the table value
- * @return FALSE - Fail to extract the table value
- *
- */
-BOOLEAN
-MemPGetLRIBT (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN MEM_PSC_TABLE_BLOCK *EntryOfTables
- )
-{
- UINT8 i;
- UINT8 MaxDimmPerCh;
- UINT8 NOD;
- UINT8 TableSize;
- UINT32 CurDDRrate;
- UINT8 DDR3Voltage;
- UINT16 RankTypeOfPopulatedDimm;
- UINT16 RankTypeInTable;
- CPU_LOGICAL_ID LogicalCpuid;
- UINT8 PackageType;
- PSCFG_L_IBT_ENTRY *TblPtr;
- CH_DEF_STRUCT *CurrentChannel;
-
- CurrentChannel = NBPtr->ChannelPtr;
-
- //@todo LRDIMM
- //if (CurrentChannel->LrDimmPresent == 0) {
- // return TRUE;
- //}
-
- TblPtr = NULL;
- TableSize = 0;
- PackageType = 0;
- LogicalCpuid.Family = AMD_FAMILY_UNKNOWN;
- MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID);
- NOD = (UINT8) 1 << (MaxDimmPerCh - 1);
-
- i = 0;
- // Obtain table pointer, table size, Logical Cpuid and PSC type according to NB type and package type.
- while (EntryOfTables->TblEntryOfLRIBT[i] != NULL) {
- if (((EntryOfTables->TblEntryOfLRIBT[i])->Header.NumOfDimm & NOD) != 0) {
- LogicalCpuid = (EntryOfTables->TblEntryOfLRIBT[i])->Header.LogicalCpuid;
- PackageType = (EntryOfTables->TblEntryOfLRIBT[i])->Header.PackageType;
- //
- // Determine if this is the expected NB Type
- //
- if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) {
- TblPtr = (PSCFG_L_IBT_ENTRY *) ((EntryOfTables->TblEntryOfLRIBT[i])->TBLPtr);
- TableSize = (EntryOfTables->TblEntryOfLRIBT[i])->TableSize;
- break;
- }
- }
- i++;
- }
-
- // Check whether no table entry is found.
- if (EntryOfTables->TblEntryOfLRIBT[i] == NULL) {
- IDS_HDT_CONSOLE (MEM_FLOW, "\nNo LRDIMM IBT table\n");
- return FALSE;
- }
-
- CurDDRrate = (UINT32) (1 << (CurrentChannel->DCTPtr->Timings.Speed / 66));
- DDR3Voltage = (UINT8) (1 << (NBPtr->RefPtr->DDR3Voltage));
- RankTypeOfPopulatedDimm = MemPGetPsRankType (CurrentChannel);
-
- for (i = 0; i < TableSize; i++) {
- MemPConstructRankTypeMap ((UINT16) TblPtr->Dimm0, (UINT16) TblPtr->Dimm1, (UINT16) TblPtr->Dimm2, &RankTypeInTable);
- if (TblPtr->DimmPerCh == MaxDimmPerCh) {
- if ((TblPtr->DDRrate & CurDDRrate) != 0) {
- if ((TblPtr->VDDIO & DDR3Voltage) != 0) {
- if ((RankTypeInTable & RankTypeOfPopulatedDimm) == RankTypeOfPopulatedDimm) {
- NBPtr->PsPtr->F0RC8 = (UINT8) TblPtr->F0RC8;
- NBPtr->PsPtr->F1RC0 = (UINT8) TblPtr->F1RC0;
- NBPtr->PsPtr->F1RC1 = (UINT8) TblPtr->F1RC1;
- NBPtr->PsPtr->F1RC2 = (UINT8) TblPtr->F1RC2;
- break;
- }
- }
- }
- }
- TblPtr++;
- }
- if (i == TableSize) {
- IDS_HDT_CONSOLE (MEM_FLOW, "\nNo LRDIMM IBT entries\n");
- return FALSE;
- }
-
- return TRUE;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ps/mplrnlr.c b/src/vendorcode/amd/agesa/Proc/Mem/Ps/mplrnlr.c
deleted file mode 100644
index b2a12b9..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ps/mplrnlr.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mplrnlr.c
- *
- * A sub-engine which extracts F0RC13[NumLogicalRanks] value for LRDIMM configuration.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mu.h"
-#include "ma.h"
-#include "mp.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-#define FILECODE PROC_MEM_PS_MPLRNLR_FILECODE
-
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * A sub-function which extracts LRDIMM F0RC13[NumLogicalRanks] value from a input
- * table and stores extracted value to a specific address.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK
- *
- * @return TRUE - Succeed in extracting the table value
- * @return FALSE - Fail to extract the table value
- *
- */
-BOOLEAN
-MemPGetLRNLR (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN MEM_PSC_TABLE_BLOCK *EntryOfTables
- )
-{
- return TRUE;
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ps/mplrnpr.c b/src/vendorcode/amd/agesa/Proc/Mem/Ps/mplrnpr.c
deleted file mode 100644
index 3bea942..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ps/mplrnpr.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mplrnpr.c
- *
- * A sub-engine which extracts F0RC13[NumPhysicalRanks] value for LRDIMM configuration.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mu.h"
-#include "ma.h"
-#include "mp.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-#define FILECODE PROC_MEM_PS_MPLRNPR_FILECODE
-
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * A sub-function which extracts LRDIMM F0RC13[NumPhysicalRanks] value from a input
- * table and stores extracted value to a specific address.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK
- *
- * @return TRUE - Succeed in extracting the table value
- * @return FALSE - Fail to extract the table value
- *
- */
-BOOLEAN
-MemPGetLRNPR (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN MEM_PSC_TABLE_BLOCK *EntryOfTables
- )
-{
- return TRUE;
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ps/mpmaxfreq.c b/src/vendorcode/amd/agesa/Proc/Mem/Ps/mpmaxfreq.c
deleted file mode 100644
index 3351364..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ps/mpmaxfreq.c
+++ /dev/null
@@ -1,250 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mpmaxfreq.c
- *
- * A sub-engine which extracts max. frequency limit value.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 37655 $ @e \$Date: 2010-09-09 11:15:05 +0800 (Thu, 09 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "cpuRegisters.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mu.h"
-#include "ma.h"
-#include "mp.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-#define FILECODE PROC_MEM_PS_MPMAXFREQ_FILECODE
-
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-typedef struct {
- UINT16 DimmPerCh:3;
- UINT16 Dimms:3;
- UINT16 SR:3;
- UINT16 DR:3;
- UINT16 QR:4;
-} CDNMaxFreq;
-
-typedef struct {
- UINT16 DimmPerCh:3;
- UINT16 Dimms:3;
- UINT16 LR:10;
-} CDNLMaxFreq;
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * A sub-function which extracts the value of max frequency supported from a input table and
- * compares it with DCTPtr->Timings.TargetSpeed
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK
- *
- * @return TRUE - Succeed in extracting the table value
- * @return FALSE - Fail to extract the table value
- *
- */
-BOOLEAN
-MemPGetMaxFreqSupported (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN MEM_PSC_TABLE_BLOCK *EntryOfTables
- )
-{
- UINT8 i;
- UINT8 MaxDimmPerCh;
- UINT8 NOD;
- UINT8 TableSize;
- PSCFG_TYPE Type;
- UINT16 CDN;
- UINT16 MaxFreqSupported;
- UINT16 *SpeedArray;
- DIMM_VOLTAGE DDR3Voltage;
- DIMM_VOLTAGE CurrentVoltage;
- DIMM_VOLTAGE VoltageHighestFreq;
- DIMM_TYPE DimmType;
- CPU_LOGICAL_ID LogicalCpuid;
- UINT8 PackageType;
- PSCFG_MAXFREQ_ENTRY *TblPtr;
- CH_DEF_STRUCT *CurrentChannel;
-
- CurrentChannel = NBPtr->ChannelPtr;
-
- Type = PSCFG_MAXFREQ;
- TblPtr = NULL;
- TableSize = 0;
- PackageType = 0;
- LogicalCpuid.Family = AMD_FAMILY_UNKNOWN;
-
- MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID);
- NOD = (UINT8) 1 << (MaxDimmPerCh - 1);
-
- if (CurrentChannel->RegDimmPresent != 0) {
- DimmType = RDIMM_TYPE;
- } else if (CurrentChannel->SODimmPresent != 0) {
- DimmType = SODIMM_TYPE;
- //@todo LRDIMM
- //} else if (CurrentChannel->LrDimmPresent) {
- // DimmType = LRDIMM_TYPE;
- } else {
- DimmType = UDIMM_TYPE;
- }
-
- i = 0;
- // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type.
- while (EntryOfTables->TblEntryOfMaxFreq[i] != NULL) {
- if (((EntryOfTables->TblEntryOfMaxFreq[i])->Header.DimmType & DimmType) != 0) {
- if (((EntryOfTables->TblEntryOfMaxFreq[i])->Header.NumOfDimm & NOD) != 0) {
- //
- // Determine if this is the expected NB Type
- //
- LogicalCpuid = (EntryOfTables->TblEntryOfMaxFreq[i])->Header.LogicalCpuid;
- PackageType = (EntryOfTables->TblEntryOfMaxFreq[i])->Header.PackageType;
- if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) {
- TblPtr = (PSCFG_MAXFREQ_ENTRY *) ((EntryOfTables->TblEntryOfMaxFreq[i])->TBLPtr);
- TableSize = (EntryOfTables->TblEntryOfMaxFreq[i])->TableSize;
- Type = (EntryOfTables->TblEntryOfMaxFreq[i])->Header.PSCType;
- break;
- }
- }
- }
- i++;
- }
-
- // Check whether no table entry is found.
- if (EntryOfTables->TblEntryOfMaxFreq[i] == NULL) {
- IDS_HDT_CONSOLE (MEM_FLOW, "\nNo MaxFreq table\n");
- return FALSE;
- }
-
- MaxFreqSupported = DDR1866_FREQUENCY;
- CDN = 0;
- DDR3Voltage = NBPtr->RefPtr->DDR3Voltage;
- VoltageHighestFreq = DDR3Voltage;
-
- // Construct the condition value
- ((CDNMaxFreq *)&CDN)->DimmPerCh = MaxDimmPerCh;
- ((CDNMaxFreq *)&CDN)->Dimms = CurrentChannel->Dimms;
- if (Type == PSCFG_MAXFREQ) {
- for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) {
- if ((CurrentChannel->DimmSRPresent & (UINT8) (1 << i)) != 0) {
- ((CDNMaxFreq *)&CDN)->SR += 1;
- }
- if ((CurrentChannel->DimmDrPresent & (UINT16) (1 << i)) != 0) {
- ((CDNMaxFreq *)&CDN)->DR += 1;
- }
- if ((CurrentChannel->DimmQrPresent & (UINT16) (1 << i)) != 0) {
- ((CDNMaxFreq *)&CDN)->QR += 1;
- }
- }
- } else {
- ((CDNLMaxFreq *)&CDN)->LR = CurrentChannel->Dimms;
- }
-
- for (i = 0; i < TableSize; i++) {
- if (CDN == ((Type == PSCFG_MAXFREQ) ? TblPtr->MAXFREQ_ENTRY.CDN :
- ((PSCFG_LR_MAXFREQ_ENTRY *)TblPtr)->LR_MAXFREQ_ENTRY.CDN)) {
- if (Type == PSCFG_MAXFREQ) {
- SpeedArray = TblPtr->MAXFREQ_ENTRY.Speed;
- } else {
- SpeedArray = ((PSCFG_LR_MAXFREQ_ENTRY *)TblPtr)->LR_MAXFREQ_ENTRY.Speed;
- }
- if (NBPtr->SharedPtr->VoltageMap != VDDIO_DETERMINED) {
- for (CurrentVoltage = VOLT1_5; CurrentVoltage <= VOLT1_25; CurrentVoltage ++) {
- if (NBPtr->SharedPtr->VoltageMap & (1 << CurrentVoltage)) {
- if (NBPtr->DCTPtr->Timings.TargetSpeed > SpeedArray[CurrentVoltage]) {
- MaxFreqSupported = SpeedArray[CurrentVoltage];
- } else {
- MaxFreqSupported = NBPtr->DCTPtr->Timings.TargetSpeed;
- }
- if (NBPtr->MaxFreqVDDIO[CurrentVoltage] > MaxFreqSupported) {
- NBPtr->MaxFreqVDDIO[CurrentVoltage] = MaxFreqSupported;
- }
- } else {
- NBPtr->MaxFreqVDDIO[CurrentVoltage] = 0;
- }
- }
- }
- MaxFreqSupported = SpeedArray[DDR3Voltage];
- break;
- }
- TblPtr++;
- }
-
- if (NBPtr->DCTPtr->Timings.TargetSpeed > MaxFreqSupported) {
- NBPtr->DCTPtr->Timings.TargetSpeed = MaxFreqSupported;
- }
- return TRUE;
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ps/mpmr0.c b/src/vendorcode/amd/agesa/Proc/Mem/Ps/mpmr0.c
deleted file mode 100644
index 5819a58..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ps/mpmr0.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mpmr0.c
- *
- * A sub-engine which extracts MR0[WR] and MR0[CL] value.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 37655 $ @e \$Date: 2010-09-09 11:15:05 +0800 (Thu, 09 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mu.h"
-#include "ma.h"
-#include "mp.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-#define FILECODE PROC_MEM_PS_MPMR0_FILECODE
-
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * A sub-function which extracts MR0[WR] or MR0[CL] value from a input table and store the
- * value to a specific address.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK
- *
- * @return TRUE - Succeed in extracting the table value
- * @return FALSE - Fail to extract the table value
- *
- */
-BOOLEAN
-MemPGetMR0WrCL (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN MEM_PSC_TABLE_BLOCK *EntryOfTables
- )
-{
-
- UINT8 i;
- UINT8 j;
- UINT8 p;
- UINT32 Value32;
- UINT8 TableSize;
- PSCFG_TYPE Type;
- CPU_LOGICAL_ID LogicalCpuid;
- UINT8 PackageType;
- PSCFG_MR0CL_ENTRY *TblPtr;
- PSC_TBL_ENTRY **ptr;
- CH_DEF_STRUCT *CurrentChannel;
-
- CurrentChannel = NBPtr->ChannelPtr;
- TblPtr = NULL;
- TableSize = 0;
-
- // Extract MR0[WR] value, then MR0[CL] value
- for (i = 0; i < 2; i++) {
- if (i == 0) {
- ptr = EntryOfTables->TblEntryOfMR0WR;
- Type = PSCFG_MR0WR;
- } else {
- ptr = EntryOfTables->TblEntryOfMR0CL;
- Type = PSCFG_MR0CL;
- }
-
- p = 0;
- // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type.
- while (ptr[p] != NULL) {
- //
- // Determine if this is the expected NB Type
- //
- LogicalCpuid = (ptr[p])->Header.LogicalCpuid;
- PackageType = (ptr[p])->Header.PackageType;
- if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) {
- TblPtr = (PSCFG_MR0CL_ENTRY *) ((ptr[p])->TBLPtr);
- TableSize = (ptr[p])->TableSize;
- break;
- }
- p++;
- }
-
- // Check whether no table entry is found.
- if (ptr[p] == NULL) {
- IDS_HDT_CONSOLE (MEM_FLOW, "\nNo MR0 table\n");
- return FALSE;
- }
-
- Value32 = (Type == PSCFG_MR0WR) ? NBPtr->GetBitField (NBPtr, BFTwrDDR3) : NBPtr->GetBitField (NBPtr, BFTcl);
- for (j = 0; j < TableSize; j++, TblPtr++) {
- if (Value32 == (UINT32) TblPtr->Timing) {
- if (Type == PSCFG_MR0WR) {
- NBPtr->PsPtr->MR0WR = (UINT8) TblPtr->Value;
- break;
- } else {
- NBPtr->PsPtr->MR0CL31 = (UINT8) TblPtr->Value;
- NBPtr->PsPtr->MR0CL0 = (UINT8) TblPtr->Value1;
- break;
- }
- }
- }
- if (j == TableSize) {
- IDS_HDT_CONSOLE (MEM_FLOW, "\nNo MR0 entries\n");
- return FALSE;
- }
- }
-
- return TRUE;
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ps/mpodtpat.c b/src/vendorcode/amd/agesa/Proc/Mem/Ps/mpodtpat.c
deleted file mode 100644
index c3c41b6..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ps/mpodtpat.c
+++ /dev/null
@@ -1,189 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mpodtpat.c
- *
- * A sub-engine which extracts ODT pattern value.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 37655 $ @e \$Date: 2010-09-09 11:15:05 +0800 (Thu, 09 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "cpuRegisters.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mu.h"
-#include "ma.h"
-#include "mp.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-#define FILECODE PROC_MEM_PS_MPODTPAT_FILECODE
-
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * A sub-function which extracts ODT Pattern value from a input table and stores extracted
- * value to a specific address.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK
- *
- * @return TRUE - Table values can be extracted per dimm population and ranks type.
- * @return FALSE - Table values cannot be extracted per dimm population and ranks type.
- *
- */
-BOOLEAN
-MemPGetODTPattern (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN MEM_PSC_TABLE_BLOCK *EntryOfTables
- )
-{
- UINT8 i;
- UINT16 RankTypeInTable;
- UINT16 RankTypeOfPopulatedDimm;
- UINT8 MaxDimmPerCh;
- UINT8 NOD;
- UINT8 TableSize;
- DIMM_TYPE DimmType;
- CPU_LOGICAL_ID LogicalCpuid;
- UINT8 PackageType;
- PSCFG_3D_ODTPAT_ENTRY *TblPtr;
- CH_DEF_STRUCT *CurrentChannel;
-
- CurrentChannel = NBPtr->ChannelPtr;
-
- TblPtr = NULL;
- TableSize = 0;
- PackageType = 0;
- LogicalCpuid.Family = AMD_FAMILY_UNKNOWN;
- MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID);
- NOD = (UINT8) 1 << (MaxDimmPerCh - 1);
-
- if (CurrentChannel->RegDimmPresent != 0) {
- DimmType = RDIMM_TYPE;
- } else if (CurrentChannel->SODimmPresent != 0) {
- DimmType = SODIMM_TYPE;
- //@todo LRDIMM
- //} else if (CurrentChannel->LrDimmPresent) {
- // DimmType = LRDIMM_TYPE;
- } else {
- DimmType = UDIMM_TYPE;
- }
-
- i = 0;
- // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type.
- while (EntryOfTables->TblEntryOfODTPattern[i] != NULL) {
- if (((EntryOfTables->TblEntryOfODTPattern[i])->Header.DimmType & DimmType) != 0) {
- if (((EntryOfTables->TblEntryOfODTPattern[i])->Header.NumOfDimm & NOD) != 0) {
- //
- // Determine if this is the expected NB Type
- //
- LogicalCpuid = (EntryOfTables->TblEntryOfODTPattern[i])->Header.LogicalCpuid;
- PackageType = (EntryOfTables->TblEntryOfODTPattern[i])->Header.PackageType;
- if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) {
- TblPtr = (PSCFG_3D_ODTPAT_ENTRY *) ((EntryOfTables->TblEntryOfODTPattern[i])->TBLPtr);
- TableSize = (EntryOfTables->TblEntryOfODTPattern[i])->TableSize;
- break;
- }
- }
- }
- i++;
- }
-
- // Check whether no table entry is found.
- if (EntryOfTables->TblEntryOfODTPattern[i] == NULL) {
- IDS_HDT_CONSOLE (MEM_FLOW, "\nNo ODT table\n");
- return FALSE;
- }
-
- RankTypeOfPopulatedDimm = MemPGetPsRankType (CurrentChannel); //@todo - LRDIMM ?
-
- for (i = 0; i < TableSize; i++) {
- MemPConstructRankTypeMap ((UINT16) TblPtr->Dimm0, (UINT16) TblPtr->Dimm1, (UINT16) TblPtr->Dimm2, &RankTypeInTable);
- if ((RankTypeInTable & RankTypeOfPopulatedDimm) == RankTypeOfPopulatedDimm) {
- CurrentChannel->PhyRODTCSHigh = TblPtr->RdODTCSHigh;
- CurrentChannel->PhyRODTCSLow = TblPtr->RdODTCSLow;
- CurrentChannel->PhyWODTCSHigh = TblPtr->WrODTCSHigh;
- CurrentChannel->PhyWODTCSLow = TblPtr->WrODTCSLow;
-
- //WL ODT
- NBPtr->FamilySpecificHook[ExtractWLODT] (NBPtr, NBPtr);
-
- return TRUE;
- }
- TblPtr++;
- }
- IDS_HDT_CONSOLE (MEM_FLOW, "\nNo ODT entries\n");
- return FALSE;
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ps/mprc10opspd.c b/src/vendorcode/amd/agesa/Proc/Mem/Ps/mprc10opspd.c
deleted file mode 100644
index 0c3ed5d..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ps/mprc10opspd.c
+++ /dev/null
@@ -1,163 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mprc10opspd.c
- *
- * A sub-engine which extracts RC10 operating speed value for RDIMM configuration.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 37655 $ @e \$Date: 2010-09-09 11:15:05 +0800 (Thu, 09 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "cpuRegisters.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mu.h"
-#include "ma.h"
-#include "mp.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-#define FILECODE PROC_MEM_PS_MPRC10OPSPD_FILECODE
-
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * A sub-function which extracts RC10 operating speed value from a input table and stores extracted
- * value to a specific address.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK
- *
- * @return TRUE - Succeed in extracting the table value
- * @return FALSE - Fail to extract the table value
- *
- */
-BOOLEAN
-MemPGetRC10OpSpd (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN MEM_PSC_TABLE_BLOCK *EntryOfTables
- )
-{
- UINT8 i;
- UINT8 TableSize;
- UINT32 CurDDRrate;
- CPU_LOGICAL_ID LogicalCpuid;
- UINT8 PackageType;
- PSCFG_OPSPD_ENTRY *TblPtr;
- CH_DEF_STRUCT *CurrentChannel;
-
- CurrentChannel = NBPtr->ChannelPtr;
-
- if (CurrentChannel->RegDimmPresent == 0) {
- return TRUE;
- }
-
- TblPtr = NULL;
- TableSize = 0;
- PackageType = 0;
- LogicalCpuid.Family = AMD_FAMILY_UNKNOWN;
-
- i = 0;
- // Obtain table pointer, table size, Logical Cpuid and PSC type according to NB type and package type.
- while (EntryOfTables->TblEntryOfRC10OpSpeed[i] != NULL) {
- LogicalCpuid = (EntryOfTables->TblEntryOfRC10OpSpeed[i])->Header.LogicalCpuid;
- PackageType = (EntryOfTables->TblEntryOfRC10OpSpeed[i])->Header.PackageType;
- //
- // Determine if this is the expected NB Type
- //
- if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) {
- TblPtr = (PSCFG_OPSPD_ENTRY *) ((EntryOfTables->TblEntryOfRC10OpSpeed[i])->TBLPtr);
- TableSize = (EntryOfTables->TblEntryOfRC10OpSpeed[i])->TableSize;
- break;
- }
- i++;
- }
-
- // Check whether no table entry is found.
- if (EntryOfTables->TblEntryOfRC10OpSpeed[i] == NULL) {
- IDS_HDT_CONSOLE (MEM_FLOW, "\nNo RC10 Op Speed table\n");
- return FALSE;
- }
-
- CurDDRrate = (UINT32) (1 << (CurrentChannel->DCTPtr->Timings.Speed / 66));
-
- for (i = 0; i < TableSize; i++) {
- if ((TblPtr->DDRrate & CurDDRrate) != 0) {
- NBPtr->PsPtr->RC10OpSpd = TblPtr->OPSPD;
- return TRUE;
- }
- TblPtr++;
- }
- IDS_HDT_CONSOLE (MEM_FLOW, "\nNo RC10 Op Speed entries\n");
- return FALSE;
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ps/mprc2ibt.c b/src/vendorcode/amd/agesa/Proc/Mem/Ps/mprc2ibt.c
deleted file mode 100644
index a1a0c81..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ps/mprc2ibt.c
+++ /dev/null
@@ -1,210 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mprc2ibt.c
- *
- * A sub-engine which extracts RC2[IBT] value for RDIMM configuration.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 37655 $ @e \$Date: 2010-09-09 11:15:05 +0800 (Thu, 09 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "cpuRegisters.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mu.h"
-#include "ma.h"
-#include "mp.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-#define FILECODE PROC_MEM_PS_MPRC2IBT_FILECODE
-
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * A sub-function which extracts RC2[IBT] value from a input table and stores extracted
- * value to a specific address.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] *EntryOfTables Pointer to MEM_PSC_TABLE_BLOCK
- *
- * @return TRUE - Table values can be extracted for all present dimms/ranks
- * @return FALSE - Table values cannot be extracted for all present dimms/ranks
- *
- */
-BOOLEAN
-MemPGetRC2IBT (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN MEM_PSC_TABLE_BLOCK *EntryOfTables
- )
-{
- UINT8 i;
- UINT8 MaxDimmPerCh;
- UINT8 NOD;
- UINT8 DimmIndex;
- UINT8 TableSize;
- UINT32 CurDDRrate;
- UINT8 DDR3Voltage;
- UINT16 RankTypeOfPopulatedDimm;
- UINT16 RankTypeInTable;
- CPU_LOGICAL_ID LogicalCpuid;
- UINT8 PackageType;
- UINT8 TgtDimmType;
- UINT8 NumOfReg;
- PSCFG_MR2IBT_ENTRY *TblPtr;
- PSCFG_MR2IBT_ENTRY *OrgTblPtr;
- CH_DEF_STRUCT *CurrentChannel;
-
- CurrentChannel = NBPtr->ChannelPtr;
-
- if (CurrentChannel->RegDimmPresent == 0) {
- return TRUE;
- }
-
- TblPtr = NULL;
- TableSize = 0;
- PackageType = 0;
- LogicalCpuid.Family = AMD_FAMILY_UNKNOWN;
- MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID);
- NOD = (UINT8) 1 << (MaxDimmPerCh - 1);
-
- i = 0;
- // Obtain table pointer, table size, Logical Cpuid and PSC type according to NB type and package type.
- while (EntryOfTables->TblEntryOfRC2IBT[i] != NULL) {
- if (((EntryOfTables->TblEntryOfRC2IBT[i])->Header.NumOfDimm & NOD) != 0) {
- LogicalCpuid = (EntryOfTables->TblEntryOfRC2IBT[i])->Header.LogicalCpuid;
- PackageType = (EntryOfTables->TblEntryOfRC2IBT[i])->Header.PackageType;
- //
- // Determine if this is the expected NB Type
- //
- if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) {
- TblPtr = (PSCFG_MR2IBT_ENTRY *) ((EntryOfTables->TblEntryOfRC2IBT[i])->TBLPtr);
- TableSize = (EntryOfTables->TblEntryOfRC2IBT[i])->TableSize;
- break;
- }
- }
- i++;
- }
-
- // Check whether no table entry is found.
- if (EntryOfTables->TblEntryOfRC2IBT[i] == NULL) {
- IDS_HDT_CONSOLE (MEM_FLOW, "\nNo RC2 IBT table\n");
- return FALSE;
- }
-
- CurDDRrate = (UINT32) (1 << (CurrentChannel->DCTPtr->Timings.Speed / 66));
- DDR3Voltage = (UINT8) (1 << (NBPtr->RefPtr->DDR3Voltage));
- RankTypeOfPopulatedDimm = MemPGetPsRankType (CurrentChannel);
-
- OrgTblPtr = TblPtr;
- for (DimmIndex = 0; DimmIndex < MAX_DIMMS_PER_CHANNEL; DimmIndex++) {
- TblPtr = OrgTblPtr;
- NumOfReg = NBPtr->PsPtr->NumOfReg[DimmIndex];
- if ((CurrentChannel->ChDimmValid& (UINT8) (1 << DimmIndex)) != 0) {
- if ((CurrentChannel->DimmQrPresent & (UINT8) (1 << DimmIndex)) != 0) {
- TgtDimmType = DIMM_QR;
- } else if ((CurrentChannel->DimmDrPresent & (UINT8) (1 << DimmIndex)) != 0) {
- TgtDimmType = DIMM_DR;
- } else {
- TgtDimmType = DIMM_SR;
- }
-
- for (i = 0; i < TableSize; i++) {
- MemPConstructRankTypeMap ((UINT16) TblPtr->Dimm0, (UINT16) TblPtr->Dimm1, (UINT16) TblPtr->Dimm2, &RankTypeInTable);
- if (TblPtr->DimmPerCh == MaxDimmPerCh) {
- if ((TblPtr->DDRrate & CurDDRrate) != 0) {
- if ((TblPtr->VDDIO & DDR3Voltage) != 0) {
- if ((RankTypeInTable & RankTypeOfPopulatedDimm) == RankTypeOfPopulatedDimm) {
- if ((TblPtr->Dimm & TgtDimmType) != 0) {
- // If TblPtr->NumOfReg == 0x0F, that means the condition will be TRUE regardless of NumRegisters in DIMM
- if ((TblPtr->NumOfReg == 0xF) || (TblPtr->NumOfReg == NumOfReg)) {
- CurrentChannel->CtrlWrd02[DimmIndex] = (UINT8) ((TblPtr->IBT & 0x1) << 2);
- CurrentChannel->CtrlWrd08[DimmIndex] = (UINT8) ((TblPtr->IBT & 0xE) >> 1);
- break;
- }
- }
- }
- }
- }
- }
- TblPtr++;
- }
- if (i == TableSize) {
- IDS_HDT_CONSOLE (MEM_FLOW, "\nNo RC2 IBT entries\n");
- return FALSE;
- }
- }
- }
-
- return TRUE;
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ps/mprtt.c b/src/vendorcode/amd/agesa/Proc/Mem/Ps/mprtt.c
deleted file mode 100644
index 5c635ad..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ps/mprtt.c
+++ /dev/null
@@ -1,229 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mprtt.c
- *
- * A sub-engine which extracts RttNom and RttWr (Dram Term and Dynamic Dram Term) value.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 37655 $ @e \$Date: 2010-09-09 11:15:05 +0800 (Thu, 09 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "cpuRegisters.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mu.h"
-#include "ma.h"
-#include "mp.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_PS_MPRTT_FILECODE
-
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define _DONT_CARE 0xFF
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * A sub-function which extracts RttNom and RttWr value from a input table and stores extracted
- * value to a specific address.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK
- *
- * @return TRUE - Table values can be extracted for all present dimms/ranks
- * @return FALSE - Table values cannot be extracted for all present dimms/ranks
- *
- */
-BOOLEAN
-MemPGetRttNomWr (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN MEM_PSC_TABLE_BLOCK *EntryOfTables
- )
-{
- UINT8 i;
- UINT8 MaxDimmPerCh;
- UINT8 NOD;
- UINT8 TableSize;
- UINT32 CurDDRrate;
- UINT8 DDR3Voltage;
- UINT16 RankTypeOfPopulatedDimm;
- UINT16 RankTypeInTable;
- DIMM_TYPE DimmType;
- CPU_LOGICAL_ID LogicalCpuid;
- UINT8 PackageType;
- UINT8 TgtDimmType;
- UINT8 TgtRank;
- UINT8 Chipsel;
- PSCFG_RTT_ENTRY *TblPtr;
- PSCFG_RTT_ENTRY *OrgTblPtr;
- CH_DEF_STRUCT *CurrentChannel;
-
- CurrentChannel = NBPtr->ChannelPtr;
-
- TblPtr = NULL;
- TableSize = 0;
- PackageType = 0;
- LogicalCpuid.Family = AMD_FAMILY_UNKNOWN;
- MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID);
- NOD = (UINT8) 1 << (MaxDimmPerCh - 1);
-
- if (CurrentChannel->RegDimmPresent != 0) {
- DimmType = RDIMM_TYPE;
- } else if (CurrentChannel->SODimmPresent != 0) {
- DimmType = SODIMM_TYPE;
- //@todo LRDIMM
- //} else if (CurrentChannel->LrDimmPresent) {
- // DimmType = LRDIMM_TYPE;
- } else {
- DimmType = UDIMM_TYPE;
- }
-
- i = 0;
- // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type.
- while (EntryOfTables->TblEntryOfDramTerm[i] != NULL) {
- if (((EntryOfTables->TblEntryOfDramTerm[i])->Header.DimmType & DimmType) != 0) {
- if (((EntryOfTables->TblEntryOfDramTerm[i])->Header.NumOfDimm & NOD) != 0) {
- //
- // Determine if this is the expected NB Type
- //
- LogicalCpuid = (EntryOfTables->TblEntryOfDramTerm[i])->Header.LogicalCpuid;
- PackageType = (EntryOfTables->TblEntryOfDramTerm[i])->Header.PackageType;
- if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) {
- TblPtr = (PSCFG_RTT_ENTRY *) ((EntryOfTables->TblEntryOfDramTerm[i])->TBLPtr);
- TableSize = (EntryOfTables->TblEntryOfDramTerm[i])->TableSize;
- break;
- }
- }
- }
- i++;
- }
-
- // Check whether no table entry is found.
- if (EntryOfTables->TblEntryOfDramTerm[i] == NULL) {
- IDS_HDT_CONSOLE (MEM_FLOW, "\nNo RTT table\n");
- return FALSE;
- }
-
- CurDDRrate = (UINT32) (1 << (CurrentChannel->DCTPtr->Timings.Speed / 66));
- DDR3Voltage = (UINT8) (1 << (NBPtr->RefPtr->DDR3Voltage));
- RankTypeOfPopulatedDimm = MemPGetPsRankType (CurrentChannel); //@todo - LRDIMM ?
-
- OrgTblPtr = TblPtr;
- for (Chipsel = 0; Chipsel < MAX_CS_PER_CHANNEL; Chipsel++) {
- TblPtr = OrgTblPtr;
- if ((NBPtr->DCTPtr->Timings.CsEnabled & (UINT16) (1 << Chipsel)) != 0) {
- if ((CurrentChannel->DimmQrPresent & (UINT8) (1 << (Chipsel >> 1))) != 0) {
- TgtDimmType = DIMM_QR;
- TgtRank = (UINT8) ((Chipsel < 4) ? 1 << (Chipsel & 1) : 4 << (Chipsel & 1));
- } else if ((CurrentChannel->DimmDrPresent & (UINT8) (1 << (Chipsel >> 1))) != 0) {
- TgtDimmType = DIMM_DR;
- TgtRank = (UINT8) 1 << (Chipsel & 1);
- } else {
- TgtDimmType = DIMM_SR;
- TgtRank = (UINT8) 1 << (Chipsel & 1);
- }
-
- if (DimmType == LRDIMM_TYPE) {
- TgtDimmType = _DONT_CARE;
- TgtRank = _DONT_CARE;
- }
-
- for (i = 0; i < TableSize; i++) {
- MemPConstructRankTypeMap ((UINT16) TblPtr->Dimm0, (UINT16) TblPtr->Dimm1, (UINT16) TblPtr->Dimm2, &RankTypeInTable);
- if (TblPtr->DimmPerCh == MaxDimmPerCh) {
- if ((TblPtr->DDRrate & CurDDRrate) != 0) {
- if ((TblPtr->VDDIO & DDR3Voltage) != 0) {
- if ((RankTypeInTable & RankTypeOfPopulatedDimm) == RankTypeOfPopulatedDimm) {
- if (((TblPtr->Dimm & TgtDimmType) != 0) || (TgtDimmType == _DONT_CARE)) {
- if (((TblPtr->Rank & TgtRank) != 0) || (TgtRank == _DONT_CARE)) {
- NBPtr->PsPtr->RttNom[Chipsel] = (UINT8) TblPtr->RttNom;
- NBPtr->PsPtr->RttWr[Chipsel] = (UINT8) TblPtr->RttWr;
- break;
- }
- }
- }
- }
- }
- }
- TblPtr++;
- }
- if ((i == TableSize) && (NBPtr->SharedPtr->VoltageMap == VDDIO_DETERMINED)) {
- IDS_HDT_CONSOLE (MEM_FLOW, "\nNo Rtt entries\n");
- return FALSE;
- }
- }
- }
- return TRUE;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Ps/mpsao.c b/src/vendorcode/amd/agesa/Proc/Mem/Ps/mpsao.c
deleted file mode 100644
index b0b2cc9..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Ps/mpsao.c
+++ /dev/null
@@ -1,200 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mpsao.c
- *
- * A sub-engine which extracts Slow access mode, Address timing and Output driver compensation value.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps)
- * @e \$Revision: 37655 $ @e \$Date: 2010-09-09 11:15:05 +0800 (Thu, 09 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "cpuRegisters.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mu.h"
-#include "ma.h"
-#include "mp.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_PS_MPSAO_FILECODE
-
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * A sub-function which extracts Slow mode, Address timing and Output driver compensation value
- * from a input table and store those value to a specific address.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK
- *
- * @return TRUE - Table values can be extracted per dimm population and ranks type.
- * @return FALSE - Table values cannot be extracted per dimm population and ranks type.
- *
- */
-BOOLEAN
-MemPGetSAO (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN MEM_PSC_TABLE_BLOCK *EntryOfTables
- )
-{
-
- UINT8 i;
- UINT8 MaxDimmPerCh;
- UINT8 NOD;
- UINT8 TableSize;
- UINT32 CurDDRrate;
- UINT8 DDR3Voltage;
- UINT16 RankTypeOfPopulatedDimm;
- UINT16 RankTypeInTable;
- DIMM_TYPE DimmType;
- CPU_LOGICAL_ID LogicalCpuid;
- UINT8 PackageType;
- PSCFG_SAO_ENTRY *TblPtr;
- CH_DEF_STRUCT *CurrentChannel;
-
- CurrentChannel = NBPtr->ChannelPtr;
-
- TblPtr = NULL;
- TableSize = 0;
- PackageType = 0;
- LogicalCpuid.Family = AMD_FAMILY_UNKNOWN;
- MaxDimmPerCh = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID);
- NOD = (UINT8) 1 << (MaxDimmPerCh - 1);
-
- if (CurrentChannel->RegDimmPresent != 0) {
- DimmType = RDIMM_TYPE;
- } else if (CurrentChannel->SODimmPresent != 0) {
- DimmType = SODIMM_TYPE;
- //@todo LRDIMM
- //} else if (CurrentChannel->LrDimmPresent) {
- // DimmType = LRDIMM_TYPE;
- } else {
- DimmType = UDIMM_TYPE;
- }
-
- i = 0;
- // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type.
- while (EntryOfTables->TblEntryOfSAO[i] != NULL) {
- if (((EntryOfTables->TblEntryOfSAO[i])->Header.DimmType & DimmType) != 0) {
- if (((EntryOfTables->TblEntryOfSAO[i])->Header.NumOfDimm & NOD) != 0) {
- //
- // Determine if this is the expected NB Type
- //
- LogicalCpuid = (EntryOfTables->TblEntryOfSAO[i])->Header.LogicalCpuid;
- PackageType = (EntryOfTables->TblEntryOfSAO[i])->Header.PackageType;
- if (MemPIsIdSupported (NBPtr, LogicalCpuid, PackageType)) {
- TblPtr = (PSCFG_SAO_ENTRY *) ((EntryOfTables->TblEntryOfSAO[i])->TBLPtr);
- TableSize = (EntryOfTables->TblEntryOfSAO[i])->TableSize;
- break;
- }
- }
- }
- i++;
- }
-
- // Check whether no table entry is found.
- if (EntryOfTables->TblEntryOfSAO[i] == NULL) {
- IDS_HDT_CONSOLE (MEM_FLOW, "\nNo SlowMode table\n");
- return FALSE;
- }
-
- CurDDRrate = (UINT32) (1 << (CurrentChannel->DCTPtr->Timings.Speed / 66));
- DDR3Voltage = (UINT8) (1 << (NBPtr->RefPtr->DDR3Voltage));
- RankTypeOfPopulatedDimm = MemPGetPsRankType (CurrentChannel); //@todo - LRDIMM ?
-
- for (i = 0; i < TableSize; i++) {
- MemPConstructRankTypeMap ((UINT16) TblPtr->Dimm0, (UINT16) TblPtr->Dimm1, (UINT16) TblPtr->Dimm2, &RankTypeInTable);
- if (TblPtr->DimmPerCh == MaxDimmPerCh) {
- if ((TblPtr->DDRrate & CurDDRrate) != 0) {
- if ((TblPtr->VDDIO & DDR3Voltage) != 0) {
- if ((RankTypeInTable & RankTypeOfPopulatedDimm) == RankTypeOfPopulatedDimm) {
- CurrentChannel->DctAddrTmg = TblPtr->AddTmgCtl;
- CurrentChannel->DctOdcCtl = TblPtr->ODC;
- CurrentChannel->SlowMode = (TblPtr->SlowMode == 1) ? TRUE : FALSE;
- return TRUE;
- }
- }
- }
- }
- TblPtr++;
- }
- IDS_HDT_CONSOLE (MEM_FLOW, "\nNo SlowMode entries\n");
- if (NBPtr->SharedPtr->VoltageMap != VDDIO_DETERMINED) {
- return TRUE;
- }
-
- return FALSE;
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR2/mt2.c b/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR2/mt2.c
deleted file mode 100644
index 9a68725..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR2/mt2.c
+++ /dev/null
@@ -1,234 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mt2.c
- *
- * Common Technology functions for DDR2
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR2)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "AdvancedApi.h"
-#include "mm.h"
-#include "mn.h"
-#include "mu.h"
-#include "mt.h"
-#include "mt2.h"
-#include "mtspd2.h"
-#include "mtot2.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-/* features */
-#include "mftds.h"
-#define FILECODE PROC_MEM_TECH_DDR2_MT2_FILECODE
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function Constructs the technology block
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-BOOLEAN
-MemConstructTechBlock2 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- TECHNOLOGY_TYPE *TechTypePtr;
- UINT8 Dct;
- UINT8 Channel;
- UINT8 i;
- DIE_STRUCT *MCTPtr;
- DCT_STRUCT *DCTPtr;
- CH_DEF_STRUCT *ChannelPtr;
- UINT8 DimmSlots;
-
- TechTypePtr = (TECHNOLOGY_TYPE *) FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MEM_TECH, NBPtr->MCTPtr->SocketId, 0);
- if (TechTypePtr != NULL) {
- // Ensure the platform override value is valid
- ASSERT ((*TechTypePtr == DDR3_TECHNOLOGY) || (*TechTypePtr == DDR2_TECHNOLOGY));
- if (*TechTypePtr != DDR2_TECHNOLOGY) {
- return FALSE;
- }
- }
-
-
- TechPtr->NBPtr = NBPtr;
- TechPtr->RefPtr = NBPtr->RefPtr;
- MCTPtr = NBPtr->MCTPtr;
-
- TechPtr->NBPtr = NBPtr;
- TechPtr->RefPtr = NBPtr->RefPtr;
-
- TechPtr->SetDramMode = MemTSetDramMode2;
- TechPtr->DimmPresence = MemTDIMMPresence2;
- TechPtr->SpdCalcWidth = MemTSPDCalcWidth2;
- TechPtr->SpdGetTargetSpeed = MemTSPDGetTargetSpeed2;
- TechPtr->AutoCycTiming = MemTAutoCycTiming2;
- TechPtr->SpdSetBanks = MemTSPDSetBanks2;
- TechPtr->SetDqsEccTmgs = MemTSetDQSEccTmgs;
- TechPtr->GetCSIntLvAddr = MemTGetCSIntLvAddr2;
- TechPtr->AdjustTwrwr = MemTAdjustTwrwr2;
- TechPtr->AdjustTwrrd = MemTAdjustTwrrd2;
- TechPtr->GetDimmSpdBuffer = MemTGetDimmSpdBuffer2;
- TechPtr->GetLD = MemTGetLD2;
- TechPtr->MaxFilterDly = 0;
-
- //
- // Map the Logical Dimms on this channel to the SPD that should be used for that logical DIMM.
- // The pointers to the DIMM SPD information is as follows (2 Dimm/Ch and 3 Dimm/Ch examples).
- //
- // DIMM Spd Buffer Current Channel DimmSpdPtr[MAX_DIMMS_PER_CHANNEL] array
- // (Number of dimms varies by platform) (Array size is determined in AGESA.H) Dimm operations loop
- // on this array only)
- // 2 DIMMS PER CHANNEL
- //
- // Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
- // Dimm 1 SR/DR DIMM <--------------DimmSpdPtr[1]
- // DimmSpdPtr[2]------->NULL
- // DimmSpdPtr[3]------->NULL
- //
- // Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
- // Dimm 1 QR DIMM <---------+----DimmSpdPtr[1]
- // | DimmSpdPtr[2]------->NULL
- // +----DimmSpdPtr[3]
- //
- // Socket N Channel N Dimm 0 QR DIMM <-----+--------DimmSpdPtr[0]
- // Dimm 1 QR DIMM <-----|---+----DimmSpdPtr[1]
- // +-- | ---DimmSpdPtr[2]
- // +----DimmSpdPtr[3]
- //
- // 3 DIMMS PER CHANNEL
- //
- // Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
- // Dimm 1 SR/DR DIMM <--------------DimmSpdPtr[1]
- // Dimm 3 SR/DR DIMM <--------------DimmSpdPtr[2]
- // DimmSpdPtr[3]------->NULL
- //
- // Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
- // Dimm 1 QR DIMM <---------+----DimmSpdPtr[1]
- // Dimm 3 SR/DR DIMM <-------- | ---DimmSpdPtr[2]
- // +----DimmSpdPtr[3]
- //
- //
-
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- DCTPtr = NBPtr->DCTPtr;
- for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) {
- NBPtr->SwitchChannel (NBPtr, Channel);
- ChannelPtr = NBPtr->ChannelPtr;
- ChannelPtr->TechType = DDR2_TECHNOLOGY;
- ChannelPtr->MCTPtr = MCTPtr;
- ChannelPtr->DCTPtr = DCTPtr;
-
- DimmSlots = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration,
- MCTPtr->SocketId,
- NBPtr->GetSocketRelativeChannel (NBPtr, Dct, Channel)
- );
- //
- // Initialize the SPD pointers for each Dimm
- //
- for (i = 0 ; i < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0])) ; i++) {
- ChannelPtr->DimmSpdPtr[i] = NULL;
- }
- for (i = 0 ; i < DimmSlots; i++) {
- ChannelPtr->DimmSpdPtr[i] = &(ChannelPtr->SpdPtr[i]);
- if ( (i + 2) < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0]))) {
- if (ChannelPtr->DimmSpdPtr[i]->DimmPresent) {
- if ((((ChannelPtr->DimmSpdPtr[i]->Data[SPD_DM_BANKS] >> 3) & 0x07) + 1) > 2) {
- ChannelPtr->DimmSpdPtr[i + 2] = &(ChannelPtr->SpdPtr[i]);
- }
- }
- }
- }
- }
- }
- return TRUE;
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR2/mt2.h b/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR2/mt2.h
deleted file mode 100644
index ded211b..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR2/mt2.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mt2.h
- *
- * Common Technology
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR2)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MT2_H_
-#define _MT2_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-MemConstructTechBlock2 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemTSetDramMode2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemTDIMMPresence2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemTSPDCalcWidth2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemTSPDGetTargetSpeed2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemTAutoCycTiming2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemTSPDSetBanks2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-VOID
-MemTGetCSIntLvAddr2 (
- IN UINT8 BankEnc,
- OUT UINT8 *LowBit,
- OUT UINT8 *HiBit
- );
-
-BOOLEAN
-MemTGetDimmSpdBuffer2 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT UINT8 **SpdBuffer,
- IN UINT8 Dimm
- );
-
-#endif /* _MT2_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR2/mtot2.c b/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR2/mtot2.c
deleted file mode 100644
index 4e6e5fb..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR2/mtot2.c
+++ /dev/null
@@ -1,164 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mtot2.c
- *
- * Technology Non-SPD Timings for DDR2
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR2)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "mm.h"
-#include "mn.h"
-#include "mu.h"
-#include "mt.h"
-#include "mtot2.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_TECH_DDR2_MTOT2_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function adjusts the Twrwr value for DDR2.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-VOID
-MemTAdjustTwrwr2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- DCT_STRUCT *DCTPtr;
-
- DCTPtr = TechPtr->NBPtr->DCTPtr;
-
- // For DDR2, 1 clock has encoded value of 0.
- // Need to transfer clk value to encoded value.
- if (DCTPtr->Timings.Twrwr >= 1) {
- DCTPtr->Timings.Twrwr -= 1;
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function adjusts the Twrrd value for DDR2.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-VOID
-MemTAdjustTwrrd2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- DCT_STRUCT *DCTPtr;
-
- DCTPtr = TechPtr->NBPtr->DCTPtr;
-
- // For DDR2, 1 clock has encoded value of 0.
- // Need to transfer clk value to encoded value.
- if (DCTPtr->Timings.Twrrd >= 1) {
- DCTPtr->Timings.Twrrd -= 1;
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function gets the LD value for DDR2
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return value of LD
- */
-
-INT8
-MemTGetLD2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- INT8 LD;
-
- // For DDR2, LD is always one clock (For DDR2, Tcwl is always Tcl minus 1).
- LD = 1;
-
- return LD;
-}
-
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR2/mtot2.h b/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR2/mtot2.h
deleted file mode 100644
index c2429ef..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR2/mtot2.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mtot2.h
- *
- * Technology Non-SPD timings for DDR2
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR2)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MTOT2_H_
-#define _MTOT2_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-VOID
-MemTAdjustTwrwr2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-VOID
-MemTAdjustTwrrd2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-INT8
-MemTGetLD2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-#endif /* _MTOT2_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR2/mtspd2.c b/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR2/mtspd2.c
deleted file mode 100644
index f9aeeed..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR2/mtspd2.c
+++ /dev/null
@@ -1,1117 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mtspd2.c
- *
- * Technology SPD supporting functions for DDR2
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR2)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mport.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mu.h"
-#include "mt2.h"
-#include "mtspd2.h"
-#include "mftds.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_TECH_DDR2_MTSPD2_FILECODE
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-UINT8
-STATIC
-MemTSPDGetTCL2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-STATIC
-MemTSysCapability2 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 k,
- IN UINT16 j
- );
-
-BOOLEAN
-STATIC
-MemTDimmSupports2 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 k,
- IN UINT8 j,
- IN UINT8 i
- );
-
-UINT8
-STATIC
-MemTGetTk2 (
- IN UINT8 k
- );
-
-UINT8
-STATIC
-MemTGetBankAddr2 (
- IN UINT8 k
- );
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the DRAM mode
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - indicates that the DRAM mode is set to DDR2
- */
-
-BOOLEAN
-MemTSetDramMode2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- TechPtr->NBPtr->SetBitField (TechPtr->NBPtr, BFLegacyBiosMode, 0);
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function determines if DIMMs are present. It checks checksum and interrogates the SPDs
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - indicates that a FATAL error has not occurred
- * @return FALSE - indicates that a FATAL error has occurred
- */
-
-BOOLEAN
-MemTDIMMPresence2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT8 *SpdBufferPtr;
- MEM_PARAMETER_STRUCT *RefPtr;
- DIE_STRUCT *MCTPtr;
- DCT_STRUCT *DCTPtr;
- CH_DEF_STRUCT *ChannelPtr;
- MEM_NB_BLOCK *NBPtr;
- UINT16 Checksum;
- UINT16 Value16;
- UINT8 Dct;
- UINT8 Channel;
- UINT8 i;
- UINT8 ByteNum;
- UINT8 Devwidth;
- UINT8 Value8;
- UINT8 MaxDimms;
- UINT8 DimmSlots;
- UINT16 DimmMask;
- BOOLEAN SPDCtrl;
-
- NBPtr = TechPtr->NBPtr;
- RefPtr = NBPtr->RefPtr;
- MCTPtr = NBPtr->MCTPtr;
-
- SPDCtrl = UserOptions.CfgIgnoreSpdChecksum;
-
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- DCTPtr = NBPtr->DCTPtr;
- for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) {
- NBPtr->SwitchChannel (NBPtr, Channel);
- ChannelPtr = NBPtr->ChannelPtr;
- ChannelPtr->DimmQrPresent = 0;
-
- // Get the maximum number of DIMMs
- DimmSlots = GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration,
- MCTPtr->SocketId,
- NBPtr->GetSocketRelativeChannel (NBPtr, Dct, Channel)
- );
- MaxDimms = MAX_DIMMS_PER_CHANNEL;
- for (i = 0; i < MaxDimms; i++) {
- // Bitmask representing dimm #i.
- DimmMask = (UINT16)1 << i;
-
- if ((ChannelPtr->DimmQrPresent & DimmMask) || (i < DimmSlots)) {
- if (MemTGetDimmSpdBuffer2 (TechPtr, &SpdBufferPtr, i)) {
- MCTPtr->DimmPresent |= DimmMask;
-
- // Start by computing checksum for this SPD
- Checksum = 0;
- for (ByteNum = 0; ByteNum < SPD_CHECKSUM; ByteNum++) {
- Checksum = Checksum + (UINT16) SpdBufferPtr[ByteNum];
- }
- // Check for valid checksum value
- AGESA_TESTPOINT (TpProcMemSPDChecking, &(NBPtr->MemPtr->StdHeader));
-
- if (SpdBufferPtr[SPD_TYPE] == JED_DDR2_SDRAM) {
- ChannelPtr->ChDimmValid |= DimmMask;
- MCTPtr->DimmValid |= DimmMask;
- } else {
- // Current socket is set up to only support DDR2 dimms.
- IDS_ERROR_TRAP;
- }
- if ((SpdBufferPtr[SPD_CHECKSUM] != (UINT8)Checksum) && !SPDCtrl) {
- //
- // if NV_SPDCHK_RESTRT is set to 0,
- // cannot ignore faulty SPD checksum
- //
- // Indicate checksum error
- ChannelPtr->DimmSpdCse |= DimmMask;
- PutEventLog (AGESA_ERROR, MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_ERROR, MCTPtr);
- }
-
- // Check module type information.
- if (SpdBufferPtr[SPD_DIMM_TYPE] & JED_REG_ADC_MSK) {
- ChannelPtr->RegDimmPresent |= DimmMask;
- MCTPtr->RegDimmPresent |= DimmMask;
- }
-
- if (SpdBufferPtr[SPD_DIMM_TYPE] & JED_SODIMM) {
- ChannelPtr->SODimmPresent |= DimmMask;
- }
-
- // Check error correction type
- if (SpdBufferPtr[SPD_EDC_TYPE] & JED_ECC) {
- MCTPtr->DimmEccPresent |= DimmMask; // Dimm has ECC
- }
- if (SpdBufferPtr[SPD_EDC_TYPE] & JED_ADRC_PAR) {
- MCTPtr->DimmParPresent |= DimmMask; // Dimm has parity
- }
-
- // Get the Dimm width data
- Devwidth = SpdBufferPtr[SPD_DEV_WIDTH] & 0xFE;
- if (Devwidth == 4) {
- ChannelPtr->Dimmx4Present |= DimmMask; // Dimm has parity
- } else if (Devwidth == 8) {
- ChannelPtr->Dimmx8Present |= DimmMask; // Dimm has parity
- } else if (Devwidth == 16) {
- ChannelPtr->Dimmx16Present |= DimmMask; // Dimm has parity
- }
-
- // Determine the page size.
- // page_size = 2^COLBITS * Devwidth/8
- //
- Value16 = (((UINT16)1 << SpdBufferPtr[SPD_COL_SZ]) * Devwidth) / 8;
- if (!(Value16 >> 11)) {
- DCTPtr->Timings.DIMM1KPage |= DimmMask;
- }
-
- // Check for 'analysis probe installed'
- if (SpdBufferPtr[SPD_ATTRIB] & JED_PROBE_MSK) {
- MCTPtr->Status[SbDiagClks] = TRUE;
- }
-
- // Determine the geometry of the DIMM module
- if (SpdBufferPtr[SPD_DM_BANKS] & SP_DPL_BIT) {
- ChannelPtr->DimmPlPresent |= DimmMask; // Dimm is planar
- }
-
- // specify the number of ranks
- Value8 = (SpdBufferPtr[SPD_DM_BANKS] & 0x07) + 1;
- if (Value8 > 2) {
- if (ChannelPtr->DimmQrPresent == 0) {
- // if any DIMMs are QR,
- // we have to make two passes through DIMMs
- //
- MaxDimms = MaxDimms << 1;
- }
-
- if (i < DimmSlots) {
- ChannelPtr->DimmQrPresent |= DimmMask;
- ChannelPtr->DimmQrPresent |= (DimmMask << 2);
- }
- Value8 = 2;
- } else if (Value8 == 2) {
- ChannelPtr->DimmDrPresent |= DimmMask; // Dual rank dimms
- }
-
- // Calculate bus loading per Channel
- if (Devwidth == 16) {
- Devwidth = 4;
- } else if (Devwidth == 4) {
- Devwidth = 16;
- }
- // double Addr bus load value for dual rank DIMMs
- if (Value8 == 2) {
- Devwidth = Devwidth << 1;
- }
-
- ChannelPtr->Ranks = ChannelPtr->Ranks + Value8;
- ChannelPtr->Loads = ChannelPtr->Loads + Devwidth;
- ChannelPtr->Dimms++;
-
- // Now examine the dimm packaging dates
- Value8 = SpdBufferPtr[SPD_MAN_DATE_YR];
- if (Value8 < M_YEAR_06) {
- ChannelPtr->DimmYr06 |= DimmMask; // Built before end of 2006
- ChannelPtr->DimmWk2406 |= DimmMask; // Built before end of week 24,2006
- } else if (Value8 == M_YEAR_06) {
- ChannelPtr->DimmYr06 |= DimmMask; // Built before end of 2006
- if (SpdBufferPtr[SPD_MAN_DATE_WK] <= M_WEEK_24) {
- ChannelPtr->DimmWk2406 |= DimmMask; // Built before end of week 24,2006
- }
- }
- } // if DIMM present
- } // Quadrank
- } // Dimm loop
-
- if (Channel == 0) {
- DCTPtr->Timings.DctDimmValid = ChannelPtr->ChDimmValid;
- DCTPtr->Timings.DimmSpdCse = ChannelPtr->DimmSpdCse;
- DCTPtr->Timings.DimmQrPresent = ChannelPtr->DimmQrPresent;
- DCTPtr->Timings.DimmDrPresent = ChannelPtr->DimmDrPresent;
- DCTPtr->Timings.Dimmx4Present = ChannelPtr->Dimmx4Present;
- DCTPtr->Timings.Dimmx8Present = ChannelPtr->Dimmx8Present;
- DCTPtr->Timings.Dimmx16Present = ChannelPtr->Dimmx16Present;
- }
- if ((Channel != 1) || (Dct != 1)) {
- MCTPtr->DimmPresent <<= 8;
- MCTPtr->DimmValid <<= 8;
- MCTPtr->RegDimmPresent <<= 8;
- MCTPtr->DimmEccPresent <<= 8;
- MCTPtr->DimmParPresent <<= 8;
- }
- } // Channel loop
- } // DCT loop
-
-
- // If we have DIMMs, some further general characteristics checking
- if (MCTPtr->DimmValid) {
- // If there are registered dimms, all the dimms must be registered
- if (MCTPtr->RegDimmPresent == MCTPtr->DimmValid) {
- // All dimms registered
- MCTPtr->Status[SbRegistered] = TRUE;
- } else if (MCTPtr->RegDimmPresent) {
- // We have an illegal DIMM mismatch
- PutEventLog (AGESA_FATAL, MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_FATAL, MCTPtr);
- }
-
- // check the ECC capability of the DIMMs
- if (MCTPtr->DimmEccPresent == MCTPtr->DimmValid) {
- MCTPtr->Status[SbEccDimms] = TRUE; // All dimms ECC capable
- }
-
- // check the parity capability of the DIMMs
- if (MCTPtr->DimmParPresent == MCTPtr->DimmValid) {
- MCTPtr->Status[SbParDimms] = TRUE; // All dimms parity capable
- }
- } else {
- }
-
- NBPtr->SwitchDCT (NBPtr, 0);
- NBPtr->SwitchChannel (NBPtr, 0);
- return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function finds the best T and CL primary timing parameter pair, per Mfg.,for the given
- * set of DIMMs, and store into DIE_STRUCT(.Speed and .Casl).
- * See "Global relationship between index values and item values" for definition of
- * CAS latency index (j) and Frequency index (k).
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - indicates that a FATAL error has not occurred
- * @return FALSE - indicates that a FATAL error has occurred
- */
-
-BOOLEAN
-MemTSPDGetTargetSpeed2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- CONST UINT16 SpeedCvt[] = {
- DDR400_FREQUENCY,
- DDR533_FREQUENCY,
- DDR667_FREQUENCY,
- DDR800_FREQUENCY,
- DDR1066_FREQUENCY
- };
- INT8 i;
- INT8 j;
- INT8 k;
- INT8 Dct;
- INT8 Channel;
- UINT8 T1min;
- UINT8 CL1min;
- BOOLEAN IsSupported;
- MEM_NB_BLOCK *NBPtr;
- DIE_STRUCT *MCTPtr;
- DCT_STRUCT *DCTPtr;
- CH_DEF_STRUCT *ChannelPtr;
-
- NBPtr = TechPtr->NBPtr;
- MCTPtr = TechPtr->NBPtr->MCTPtr;
-
- CL1min = 0xFF;
- T1min = 0xFF;
-
- // For DDR2, run SyncTargetSpeed first to get frequency limit into DCTPtr->Timings.Speed
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- NBPtr->DCTPtr->Timings.TargetSpeed = 16; // initialized with big number
- }
- NBPtr->SyncTargetSpeed (NBPtr);
-
- // Find target frequency and Tcl
- for (k = K_MAX; k >= K_MIN; k--) {
- for (j = J_MIN; j <= J_MAX; j++) {
- if (MemTSysCapability2 (TechPtr, k, j)) {
- IsSupported = TRUE;
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) {
- NBPtr->SwitchChannel (NBPtr, Channel);
- ChannelPtr = NBPtr->ChannelPtr;
- for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) {
- if (ChannelPtr->ChDimmValid & ((UINT8)1 << i)) {
- if (!MemTDimmSupports2 (TechPtr, k, j, i)) {
- IsSupported = FALSE;
- Dct = NBPtr->DctCount;
- Channel = NBPtr->ChannelCount;
- break;
- }
- }
- }
- }
- }
-
- if (IsSupported) {
- T1min = k;
- CL1min = j;
- // Kill the loops...
- k = K_MIN - 1;
- j = J_MAX + 1;
- }
- }
- }
- }
-
- if (T1min == 0xFF) {
- // Failsafe values, running in minimum mode
- PutEventLog (AGESA_FATAL, MEM_ERROR_MISMATCH_DIMM_CLOCKS, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- PutEventLog (AGESA_FATAL, MEM_ERROR_MINIMUM_MODE, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_ERROR, MCTPtr);
-
- T1min = T_DEF;
- CL1min = CL_DEF;
- }
-
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- DCTPtr = NBPtr->DCTPtr;
- DCTPtr->Timings.TargetSpeed = SpeedCvt[T1min - 1];
- }
-
- // Ensure the target speed can be applied to all channels of the current node
- NBPtr->SyncTargetSpeed (NBPtr);
-
- // Set the start-up frequency
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- DCTPtr = NBPtr->DCTPtr;
- DCTPtr->Timings.Speed = DCTPtr->Timings.TargetSpeed;
- DCTPtr->Timings.CasL = CL1min + 2; // Convert to clocks
- }
-
- return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function check the symmetry of DIMM pairs (DIMM on Channel A matching with
- * DIMM on Channel B), the overall DIMM population, and determine the width mode:
- * 64-bit, 64-bit muxed, 128-bit.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - indicates that a FATAL error has not occurred
- * @return FALSE - indicates that a FATAL error has occurred
- */
-
-BOOLEAN
-MemTSPDCalcWidth2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT8 *SpdBufferAPtr;
- UINT8 *SpdBufferBPtr;
- MEM_NB_BLOCK *NBPtr;
- DIE_STRUCT *MCTPtr;
- DCT_STRUCT *DCTPtr;
- UINT8 i;
- UINT16 DimmMask;
- UINT8 UngangMode;
-
- NBPtr = TechPtr->NBPtr;
- MCTPtr = NBPtr->MCTPtr;
- DCTPtr = NBPtr->DCTPtr;
-
- UngangMode = UserOptions.CfgMemoryModeUnganged;
- IDS_OPTION_HOOK (IDS_GANGING_MODE, &UngangMode, &(NBPtr->MemPtr->StdHeader));
-
- // Check symmetry of channel A and channel B dimms for 128-bit mode
- // capability.
- //
- AGESA_TESTPOINT (TpProcMemModeChecking, &(NBPtr->MemPtr->StdHeader));
- i = 0;
- if (MCTPtr->DctData[0].Timings.DctDimmValid == MCTPtr->DctData[1].Timings.DctDimmValid) {
- for (; i < MAX_DIMMS_PER_CHANNEL; i++) {
- DimmMask = (UINT16)1 << i;
- if (DCTPtr->Timings.DctDimmValid & DimmMask) {
- NBPtr->SwitchDCT (NBPtr, 0);
- MemTGetDimmSpdBuffer2 (TechPtr, &SpdBufferAPtr, i);
- NBPtr->SwitchDCT (NBPtr, 1);
- MemTGetDimmSpdBuffer2 (TechPtr, &SpdBufferBPtr, i);
-
- if ((SpdBufferAPtr[SPD_ROW_SZ]&0x1F) != (SpdBufferBPtr[SPD_ROW_SZ]&0x1F)) {
- break;
- }
-
- if ((SpdBufferAPtr[SPD_COL_SZ]&0x1F) != (SpdBufferBPtr[SPD_COL_SZ]&0x1F)) {
- break;
- }
-
- if (SpdBufferAPtr[SPD_BANK_SZ] != SpdBufferBPtr[SPD_BANK_SZ]) {
- break;
- }
-
- if ((SpdBufferAPtr[SPD_DEV_WIDTH]&0x7F) != (SpdBufferBPtr[SPD_DEV_WIDTH]&0x7F)) {
- break;
- }
-
- if ((SpdBufferAPtr[SPD_DM_BANKS]&0x07) != (SpdBufferBPtr[SPD_DM_BANKS]&0x07)) {
- break;
- }
- }
- }
- }
- if (i < MAX_DIMMS_PER_CHANNEL) {
- PutEventLog (AGESA_ALERT, MEM_ALERT_ORG_MISMATCH_DIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_ALERT, MCTPtr);
- } else if (!UngangMode) {
- NBPtr->Ganged = TRUE;
- MCTPtr->GangedMode = TRUE;
- MCTPtr->Status[Sb128bitmode] = TRUE;
- NBPtr->SetBitField (NBPtr, BFDctGangEn, 1);
- }
-
- return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Initialize DCT Timing registers as per DIMM SPD.
- * For primary timing (T, CL) use best case T value.
- * For secondary timing params., use most aggressive settings
- * of slowest DIMM.
- *
- * Note:
- * There are three components to determining "maximum frequency": SPD component,
- * Bus load component, and "Preset" max frequency component.
- * The SPD component is a function of the min cycle time specified by each DIMM,
- * and the interaction of cycle times from all DIMMs in conjunction with CAS
- * latency. The SPD component only applies when user timing mode is 'Auto'.
- *
- * The Bus load component is a limiting factor determined by electrical
- * characteristics on the bus as a result of varying number of device loads. The
- * Bus load component is specific to each platform but may also be a function of
- * other factors. The bus load component only applies when user timing mode is
- * ' Auto'.
- *
- * The Preset component is subdivided into three items and is the minimum of
- * the set: Silicon revision, user limit setting when user timing mode is 'Auto' and
- * memclock mode is 'Limit', OEM build specification of the maximum frequency.
- * The Preset component only applies when user timing mode is 'Auto'.
-
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - indicates that a FATAL error has not occurred
- * @return FALSE - indicates that a FATAL error has occurred
- */
-
-BOOLEAN
-MemTAutoCycTiming2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- CONST UINT8 SpdIndexes[] = {
- SPD_TRCD,
- SPD_TRP,
- SPD_TRTP,
- SPD_TRAS,
- SPD_TRC,
- SPD_TWR,
- SPD_TRRD,
- SPD_TWTR
- };
- CONST UINT8 Multiples[] = {10, 10, 10, 40, 40, 10, 10, 10};
-
- CONST UINT8 Tab1KTfawTK[] = {8, 10, 13, 14, 0, 20};
- CONST UINT8 Tab2KTfawTK[] = {10, 14, 17, 18, 0, 24};
- CONST UINT8 TabDefTrcK[] = {0x41, 0x3C, 0x3C, 0x3A, 0, 0x3A};
-
- UINT8 MiniMaxTmg[GET_SIZE_OF (SpdIndexes)];
- UINT8 MiniMaxTrfc[4];
-
- DIE_STRUCT *MCTPtr;
- DCT_STRUCT *DCTPtr;
- MEM_NB_BLOCK *NBPtr;
- UINT16 DimmMask;
- UINT16 Value16;
- UINT16 Tk40;
- UINT8 i;
- UINT8 j;
- UINT8 Value8;
- UINT8 Temp8;
- UINT8 *StatTmgPtr;
- UINT16 *StatDimmTmgPtr;
- BOOLEAN Is1066;
- UINT8 *SpdBufferPtr;
-
- NBPtr = TechPtr->NBPtr;
- MCTPtr = NBPtr->MCTPtr;
- DCTPtr = NBPtr->DCTPtr;
-
- // initialize mini-max arrays
- for (j = 0; j < GET_SIZE_OF (MiniMaxTmg); j++) {
- MiniMaxTmg[j] = 0;
- }
- for (j = 0; j < GET_SIZE_OF (MiniMaxTrfc); j++) {
- MiniMaxTrfc[j] = 0;
- }
-
- // ======================================================================
- // Get primary timing (CAS Latency and Cycle Time)
- // ======================================================================
- // Get OEM specific load variant max
- //
-
- //======================================================================
- // Gather all DIMM mini-max values for cycle timing data
- //======================================================================
- //
- DimmMask = 1;
- for (i = 0; i < (MAX_CS_PER_CHANNEL / 2); i++) {
- if (DCTPtr->Timings.DctDimmValid & DimmMask) {
- MemTGetDimmSpdBuffer2 (TechPtr, &SpdBufferPtr, i);
- for (j = 0; j < GET_SIZE_OF (SpdIndexes); j++) {
- Value8 = SpdBufferPtr[SpdIndexes[j]];
- if (SpdIndexes[j] == SPD_TRC) {
- if (Value8 == 0 || Value8 == 0xFF) {
- PutEventLog (AGESA_WARNING, MEM_WARNING_NO_SPDTRC_FOUND, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, i, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_WARNING, MCTPtr);
- Value8 = TabDefTrcK[(DCTPtr->Timings.Speed / 66) - 3];
- }
- }
- if (MiniMaxTmg[j] < Value8) {
- MiniMaxTmg[j] = Value8;
- }
- }
-
- // get Trfc0 - Trfc3 values
- Value8 = SpdBufferPtr[SPD_BANK_SZ];
- Temp8 = (Value8 << 3) | (Value8 >> 5);
- Value8 = SpdBufferPtr[SPD_DEV_WIDTH];
- ASSERT (LibAmdBitScanReverse ((UINT32)Value8) <= 4);
- Temp8 >>= 4 - LibAmdBitScanReverse ((UINT32)Value8);
- Value8 = LibAmdBitScanReverse ((UINT32)Temp8);
- if (MiniMaxTrfc[i] < Value8) {
- MiniMaxTrfc[i] = Value8;
- }
- }
- DimmMask <<= 1;
- }
-
- // ======================================================================
- // Convert DRAM CycleTiming values and store into DCT structure
- // ======================================================================
- //
- Tk40 = 40000 / DCTPtr->Timings.Speed;
- if (DCTPtr->Timings.Speed == DDR1066_FREQUENCY) {
- Is1066 = TRUE;
- } else {
- Is1066 = FALSE;
- }
- // Notes:
- // 1. All secondary time values given in SPDs are in binary with UINTs of ns.
- // 2. Some time values are scaled by four, in order to have least count of 0.25 ns
- // (more accuracy). JEDEC SPD spec. shows which ones are x1 and x4.
- // 3. Internally to this SW, cycle time, Tk, is scaled by 10 to affect a
- // least count of 0.1 ns (more accuracy).
- // 4. SPD values not scaled are multiplied by 10 and then divided by 10T to find
- // equivalent minimum number of bus clocks (a remainder causes round-up of clocks).
- // 5. SPD values that are prescaled by 4 are multiplied by 10 and then divided by 40T to find
- // equivalent minimum number of bus clocks (a remainder causes round-up of clocks).
- //
- StatDimmTmgPtr = &DCTPtr->Timings.DIMMTrcd;
- StatTmgPtr = &DCTPtr->Timings.Trcd;
- for (j = 0; j < GET_SIZE_OF (SpdIndexes); j++) {
- Value16 = (UINT16)MiniMaxTmg[j] * Multiples[j];
- StatDimmTmgPtr[j] = Value16;
-
- MiniMaxTmg[j] = (UINT8) ((Value16 + Tk40 - 1) / Tk40);
- if (SpdIndexes[j] == SPD_TRTP) {
- MiniMaxTmg[j] = (DCTPtr->Timings.Speed <= DDR533_FREQUENCY) ? 2 : 3; // based on BL of 32 bytes
- }
-
- StatTmgPtr[j] = MiniMaxTmg[j];
- }
- DCTPtr->Timings.Trfc0 = MiniMaxTrfc[0];
- DCTPtr->Timings.Trfc1 = MiniMaxTrfc[1];
- DCTPtr->Timings.Trfc2 = MiniMaxTrfc[2];
- DCTPtr->Timings.Trfc3 = MiniMaxTrfc[3];
-
- DCTPtr->Timings.CasL = MemTSPDGetTCL2 (TechPtr);
-
- if (DCTPtr->Timings.DIMM1KPage) {
- DCTPtr->Timings.Tfaw = Tab1KTfawTK[(DCTPtr->Timings.Speed / 66) - 3];
- } else {
- DCTPtr->Timings.Tfaw = Tab2KTfawTK[(DCTPtr->Timings.Speed / 66) - 3];
- }
- if (Is1066) {
- DCTPtr->Timings.Tfaw >>= 1;
- }
-
- //======================================================================
- // Program DRAM Timing values
- //======================================================================
- //
- NBPtr->ProgramCycTimings (NBPtr);
-
- MemFInitTableDrive (NBPtr, MTAfterAutoCycTiming);
-
- return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the bank addressing, program Mask values and build a chip-select population map.
- * This routine programs PCI 0:24N:2x80 config register.
- * This routine programs PCI 0:24N:2x60,64,68,6C config registers (CS Mask 0-3)
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - indicates that a FATAL error has not occurred
- * @return FALSE - indicates that a FATAL error has occurred
- */
-
-BOOLEAN
-MemTSPDSetBanks2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT8 *SpdBufferPtr;
- UINT8 i;
- UINT8 ChipSel;
- UINT8 DimmID;
- UINT8 Value8;
- UINT8 Rows;
- UINT8 Cols;
- UINT8 Ranks;
- UINT8 Banks;
- UINT32 BankAddrReg;
- UINT32 CsMask;
- UINT16 CSSpdCSE;
- UINT16 CSExclude;
- UINT16 DimmQRDR;
- DIE_STRUCT *MCTPtr;
- DCT_STRUCT *DCTPtr;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
- MCTPtr = NBPtr->MCTPtr;
- DCTPtr = NBPtr->DCTPtr;
-
- BankAddrReg = 0;
- CSSpdCSE = 0;
- CSExclude = 0;
- for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) {
- DimmID = ChipSel >> 1;
-
- DimmQRDR = (DCTPtr->Timings.DimmQrPresent) | (DCTPtr->Timings.DimmDrPresent);
- if (DCTPtr->Timings.DimmSpdCse & (UINT16) 1 << DimmID) {
- CSSpdCSE |= (UINT16) ((DimmQRDR & (UINT16) 1 << DimmID) ? 3 : 1) << ChipSel;
- }
- if ((DCTPtr->Timings.DimmExclude & ((UINT16) 1 << DimmID)) != 0) {
- CSExclude |= (UINT16) ((DimmQRDR & (UINT16) 1 << DimmID) ? 3: 1) << ChipSel;
- }
-
- if (DCTPtr->Timings.DctDimmValid & ((UINT16)1 << DimmID)) {
- MemTGetDimmSpdBuffer2 (TechPtr, &SpdBufferPtr, DimmID);
-
- // Get the basic data
- Rows = SpdBufferPtr[SPD_ROW_SZ] & 0x1F;
- Cols = SpdBufferPtr[SPD_COL_SZ] & 0x1F;
- Banks = SpdBufferPtr[SPD_L_BANKS];
- Ranks = (SpdBufferPtr[SPD_DM_BANKS] & 0x07) + 1;
-
- // Configure the bank encoding
- Value8 = (Cols - 9) << 3;
- Value8 |= (Banks == 8) ? 4 : 0;
- Value8 |= (Rows - 13);
-
- for (i = 0; i < 12; i++) {
- if (Value8 == MemTGetBankAddr2 (i)) {
- break;
- }
- }
-
- if (i < 12) {
- BankAddrReg |= ((UINT32)i << (ChipSel << 1));
-
- // Mask value=(2pow(rows+cols+banks+3)-1)>>8,
- // or 2pow(rows+cols+banks-5)-1
- //
- Value8 = Rows + Cols;
- Value8 -= (Banks == 8) ? 2:3;
- if (MCTPtr->Status[Sb128bitmode]) {
- Value8++;
- }
- CsMask = ((UINT32)1 << Value8) - 1;
- DCTPtr->Timings.CsPresent |= (UINT16)1 << ChipSel;
-
- if (Ranks >= 2) {
- DCTPtr->Timings.CsPresent |= (UINT16)1 << (ChipSel + 1);
- }
-
- // Update the DRAM CS Mask for this chipselect
- NBPtr->SetBitField (NBPtr, BFCSMask0Reg + (ChipSel >> 1), (CsMask & 0x1FF83FE0));
- }
- }
- }
- // For ranks that need to be excluded, the loading of this rank should be considered
- // in timing, so need to set CsPresent before setting CsTestFail
- if ((CSSpdCSE != 0) || (CSExclude != 0)) {
- NBPtr->MemPtr->ErrorHandling (MCTPtr, NBPtr->Dct, (CSSpdCSE | CSExclude), &NBPtr->MemPtr->StdHeader);
- }
-
- // If there are no chip selects, we have an error situation.
- if (DCTPtr->Timings.CsPresent == 0) {
- PutEventLog (AGESA_ERROR, MEM_ERROR_NO_CHIPSELECT, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_ERROR, MCTPtr);
- }
-
- NBPtr->SetBitField (NBPtr, BFDramBankAddrReg, BankAddrReg);
-
- return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function returns the low bit that will be swapped to enable CS interleaving
- *
- * @param[in] BankEnc - AddrMap Bank encoding from F2x80
- * @param[in] *LowBit - pointer to low bit
- * @param[in] *HiBit - pointer hight bit
- *
- */
-
-VOID
-MemTGetCSIntLvAddr2 (
- IN UINT8 BankEnc,
- OUT UINT8 *LowBit,
- OUT UINT8 *HiBit
- )
-{
- CONST UINT8 ArrCodesLo[] = {6, 7, 7, 8, 8, 8, 8, 8, 9, 9, 8, 9};
- CONST UINT8 ArrCodesHi[] = {19, 20, 21, 21, 21, 22, 22, 23, 23, 24, 24, 25};
- ASSERT (BankEnc < GET_SIZE_OF (ArrCodesLo));
- ASSERT (BankEnc < GET_SIZE_OF (ArrCodesHi));
- // return ArrCodes[BankEnc];
- *LowBit = ArrCodesLo[BankEnc];
- *HiBit = ArrCodesHi[BankEnc];
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function returns the CAS latency of the current frequency.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return CAS Latency
- */
-UINT8
-STATIC
-MemTSPDGetTCL2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- return TechPtr->NBPtr->DCTPtr->Timings.CasL;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Get max frequency from OEM platform definition, from
- * any user override (limiting) of max frequency, and
- * from any Si Revision Specific information. Return
- * the least of these three in DIE_STRUCT.PresetmaxFreq.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] k - Frequency index
- * @param[in] j - CAS Latency index
- *
- * @return TRUE - (k << 8) | j
- * @return FALSE - 0
- */
-
-BOOLEAN
-STATIC
-MemTSysCapability2 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 k,
- IN UINT16 j
- )
-{
- if ((k > TechPtr->NBPtr->DCTPtr->Timings.TargetSpeed) || (j > J_MAX)) {
- return FALSE;
- }
-
- return TRUE; //(k << 8) | j;
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Determine whether dimm(b,i) supports CL(j) and F(k)
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] k - Frequency index
- * @param[in] j - CAS Latency index
- * @param[in] i - DIMM number
- *
- * @return TRUE - DIMM supports
- * @return FALSE - DIMM does not support
- */
-
-BOOLEAN
-STATIC
-MemTDimmSupports2 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 k,
- IN UINT8 j,
- IN UINT8 i
- )
-{
- CONST UINT8 SpdBytesForCL[3] = { 9, 23, 25}; // SPD bytes for CL X, CL X-.5, and CL X-1
- UINT8 CLj;
- UINT8 CLi;
- UINT8 T1;
- UINT8 T2;
- UINT8 Tk;
- UINT8 *SpdBufferPtr;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
-
- MemTGetDimmSpdBuffer2 (TechPtr, &SpdBufferPtr, i);
- CLj = (UINT8) 1 << (j + 2);
- CLi = SpdBufferPtr[SPD_CAS_LAT];
-
- if (CLj & CLi) {
- // If this dimm supports the desired CAS latency...
- // Determine the SPD location of the dimm speed UINT8 appropriate
- // to the CAS latency indicated by Table_CL2_j.
- //
- T1 = LibAmdBitScanReverse ((UINT32)CLj);
- T2 = LibAmdBitScanReverse ((UINT32)CLi);
- ASSERT ((T2 - T1) < 3);
- CLi = SpdBufferPtr[SpdBytesForCL[(T2 - T1)]];
- Tk = MemTGetTk2 (k);
- if (CLi == 0) {
- PutEventLog (AGESA_FATAL, MEM_ERROR_NO_CYC_TIME, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_WARNING, NBPtr->MCTPtr);
- } else if (Tk >= CLi) {
- return TRUE;
- }
- }
- return FALSE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function returns the cycle time
- *
- * @param[in] k - CAS Latency index
- *
- * @return Tk as specified by JEDEC SPD byte 9.
- */
-
-UINT8
-STATIC
-MemTGetTk2 (
- IN UINT8 k
- )
-{
- CONST UINT8 TableTK[] = {0x00, 0x50, 0x3D, 0x30, 0x25, 0x18};
- ASSERT (k < GET_SIZE_OF (TableTK));
- return TableTK[k];
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function returns the encoded value of bank address.
- *
- * @param[in] k value
- *
- * @return RRRBCC, where CC is the number of Columns minus 9,
- * RRR is the number of Rows minus 12, and B is the number of banks
- * minus 3.
- */
-
-UINT8
-STATIC
-MemTGetBankAddr2 (
- IN UINT8 k
- )
-{
- CONST UINT8 TabBankAddr[] = {
- 0x00, 0x08, 0x09, 0x10, 0x0C, 0x0D,
- 0x11, 0x0E, 0x15, 0x16, 0x0F, 0x17
- };
- ASSERT (k < GET_SIZE_OF (TabBankAddr));
- return TabBankAddr[k];
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function returns a pointer to the SPD Buffer of a specific dimm on
- * the current channel.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in,out] **SpdBuffer - Pointer to a pointer to a UINT8 Buffer
- * @param[in] Dimm - Dimm number
- *
- *
- * @return BOOLEAN - Value of DimmPresent
- * TRUE = Dimm is present, pointer is valid
- * FALSE = Dimm is not present, pointer has not been modified.
- */
-
-BOOLEAN
-MemTGetDimmSpdBuffer2 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT UINT8 **SpdBuffer,
- IN UINT8 Dimm
- )
-{
- CH_DEF_STRUCT *ChannelPtr;
- SPD_DEF_STRUCT *SPDPtr;
- BOOLEAN DimmPresent;
-
- DimmPresent = FALSE;
- ChannelPtr = TechPtr->NBPtr->ChannelPtr;
- ASSERT (Dimm < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0])))
- SPDPtr = ChannelPtr->DimmSpdPtr[Dimm];
-
-
- if (SPDPtr != NULL) {
- DimmPresent = SPDPtr->DimmPresent;
- if (DimmPresent) {
- *SpdBuffer = SPDPtr->Data;
- }
- }
- return DimmPresent;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR2/mtspd2.h b/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR2/mtspd2.h
deleted file mode 100644
index b1cdf48..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR2/mtspd2.h
+++ /dev/null
@@ -1,184 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mtspd2.h
- *
- * Technology SPD support for DDR2
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR2)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MTSPD2_H_
-#define _MTSPD2_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*===============================================================================
- * Jedec DDR II
- *===============================================================================
- */
-#define SPD_TYPE 2 /* SPD byte read location */
-#define JED_DDR_SDRAM 7 /* Jedec defined bit field */
-#define JED_DDR2_SDRAM 8 /* Jedec defined bit field */
-
-#define SPD_DIMM_TYPE 20
-#define SPD_ATTRIB 21
-#define JED_DIF_CK_MSK 0x20 /* Differential Clock Input */
-#define JED_REG_ADC_MSK 0x11 /* Registered Address/Control */
-#define JED_PROBE_MSK 0x40 /* Analysis Probe installed */
-#define JED_SODIMM 0x04 /* SO-DIMM */
-#define SPD_DEV_ATTRIB 22
-#define SPD_EDC_TYPE 11
-#define JED_ECC 2
-#define JED_ADRC_PAR 4
-#define SPD_ROW_SZ 3
-#define SPD_COL_SZ 4
-#define SPD_L_BANKS 17 /* number of [logical] banks on each device */
-#define SPD_DM_BANKS 5 /* number of physical banks on dimm */
-#define SP_DPL_BIT 4 /* Dram package bit */
-#define SPD_BANK_SZ 31 /* capacity of physical bank */
-#define SPD_DEV_WIDTH 13
-#define SPD_CAS_LAT 18
-#define SPD_TRP 27
-#define SPD_TRRD 28
-#define SPD_TRCD 29
-#define SPD_TRAS 30
-#define SPD_TWR 36
-#define SPD_TWTR 37
-#define SPD_TRTP 38
-#define SPD_TRC 41
-#define SPD_TRFC 42
-#define SPD_CHECKSUM 63
-#define SPD_MAN_DATE_YR 93 /* Module Manufacturing Year (BCD) */
-
-#define SPD_MAN_DATE_WK 94 /* Module Manufacturing Week (BCD) */
-
-/*-----------------------------
- * Jedec DDR II related equates
- *-----------------------------
- */
-#define M_YEAR_06 0x06 /* Manufacturing Year BCD encoding of 2006 - 06d */
-#define M_WEEK_24 0x24 /* Manufacturing Week BCD encoding of June - 24d */
-
-#define J_MIN 0 /* j loop constraint. 1=CL 2.0 T */
-#define J_MAX 5 /* j loop constraint. 5=CL 7.0 T */
-#define K_MIN 1 /* k loop constraint. 1=200 MHz */
-#define K_MAX 5 /* k loop constraint. 5=533 MHz */
-#define CL_DEF 2 /* Default value for failsafe operation. 2=CL 4.0 T */
-#define T_DEF 1 /* Default value for failsafe operation. 1=5ns (cycle time) */
-
-
-#define BIAS_TCL_T 1
-#define BIAS_TRP_T 3 /* bias to convert bus clocks to bit field value */
-#define BIAS_TRRD_T 2
-#define BIAS_TRCD_T 3
-#define BIAS_TRAS_T 3
-#define BIAS_TRC_T 11
-#define BIAS_TRTP_T 1
-#define BIAS_TWR_T 3
-#define BIAS_TWTR_T 0
-#define BIAS_TFAW_T 7
-
-#define MIN_TRP_T 3 /* min programmable value in busclocks */
-#define MAX_TRP_T 6 /* max programmable value in busclocks */
-#define MIN_TRRD_T 2
-#define MAX_TRRD_T 5
-#define MIN_TRCD_T 3
-#define MAX_TRCD_T 6
-#define MIN_TRAS_T 5
-#define MAX_TRAS_T 18
-#define MIN_TRC_T 11
-#define MAX_TRC_T 26
-#define MIN_TRTP_T 2
-#define MAX_TRTP_T 4
-#define MIN_TWR_T 3
-#define MAX_TWR_T 6
-#define MIN_TWTR_T 1
-#define MAX_TWTR_T 3
-
-/* DDR2-1066 support */
-#define BIAS_TRCD_T_1066 5
-#define BIAS_TRAS_T_1066 15
-#define BIAS_TRRD_T_1066 4
-#define BIAS_TWR_T_1066 4
-#define BIAS_TRP_T_1066 5
-#define BIAS_TWTR_T_1066 4
-
-#define MIN_TRCD_T_1066 5
-#define MAX_TRCD_T_1066 12
-#define MIN_TRAS_T_1066 15
-#define MAX_TRAS_T_1066 30
-#define MIN_TRC_T_1066 11
-#define MAX_TRC_T_1066 42
-#define MIN_TRRD_T_1066 4
-#define MAX_TRRD_T_1066 7
-#define MIN_TWR_T_1066 5
-#define MAX_TWR_T_1066 8
-#define MIN_TRP_T_1066 5
-#define MAX_TRP_T_1066 12
-#define MIN_TWTR_T_1066 4
-#define MAX_TWTR_T_1066 7
-
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-
-#endif /* _MTSPD2_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mt3.c b/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mt3.c
deleted file mode 100644
index b1ab754..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mt3.c
+++ /dev/null
@@ -1,237 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mt3.c
- *
- * Common Technology functions for DDR3
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR3)
- * @e \$Revision: 36765 $ @e \$Date: 2010-08-25 23:06:36 +0800 (Wed, 25 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "mu.h"
-#include "mt.h"
-#include "mt3.h"
-#include "mtspd3.h"
-#include "mtot3.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-/* features */
-#define FILECODE PROC_MEM_TECH_DDR3_MT3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function Constructs the technology block
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-BOOLEAN
-MemConstructTechBlock3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- TECHNOLOGY_TYPE *TechTypePtr;
- UINT8 Dct;
- UINT8 Channel;
- UINT8 i;
- DIE_STRUCT *MCTPtr;
- DCT_STRUCT *DCTPtr;
- CH_DEF_STRUCT *ChannelPtr;
- UINT8 DimmSlots;
-
-
- TechTypePtr = (TECHNOLOGY_TYPE *) FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MEM_TECH, NBPtr->MCTPtr->SocketId, 0);
- if (TechTypePtr != NULL) {
- // Ensure the platform override value is valid
- ASSERT ((*TechTypePtr == DDR3_TECHNOLOGY) || (*TechTypePtr == DDR2_TECHNOLOGY));
- if (*TechTypePtr != DDR3_TECHNOLOGY) {
- return FALSE;
- }
- }
-
- TechPtr->NBPtr = NBPtr;
- TechPtr->RefPtr = NBPtr->RefPtr;
- MCTPtr = NBPtr->MCTPtr;
-
- TechPtr->SendAllMRCmds = MemTSendAllMRCmds3;
- TechPtr->FreqChgCtrlWrd = FreqChgCtrlWrd3;
- TechPtr->SetDramMode = MemTSetDramMode3;
- TechPtr->DimmPresence = MemTDIMMPresence3;
- TechPtr->SpdCalcWidth = MemTSPDCalcWidth3;
- TechPtr->SpdGetTargetSpeed = MemTSPDGetTargetSpeed3;
- TechPtr->AutoCycTiming = MemTAutoCycTiming3;
- TechPtr->SpdSetBanks = MemTSPDSetBanks3;
- TechPtr->SetDqsEccTmgs = MemTSetDQSEccTmgs;
- TechPtr->GetCSIntLvAddr = MemTGetCSIntLvAddr3;
- TechPtr->AdjustTwrwr = MemTAdjustTwrwr3;
- TechPtr->AdjustTwrrd = MemTAdjustTwrrd3;
- TechPtr->GetDimmSpdBuffer = MemTGetDimmSpdBuffer3;
- TechPtr->GetLD = MemTGetLD3;
- TechPtr->MaxFilterDly = 0;
-
- //
- // Map the Logical Dimms on this channel to the SPD that should be used for that logical DIMM.
- // The pointers to the DIMM SPD information is as follows (2 Dimm/Ch and 3 Dimm/Ch examples).
- //
- // DIMM Spd Buffer Current Channel DimmSpdPtr[MAX_DIMMS_PER_CHANNEL] array
- // (Number of dimms varies by platform) (Array size is determined in AGESA.H) Dimm operations loop
- // on this array only)
- // 2 DIMMS PER CHANNEL
- //
- // Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
- // Dimm 1 SR/DR DIMM <--------------DimmSpdPtr[1]
- // DimmSpdPtr[2]------->NULL
- // DimmSpdPtr[3]------->NULL
- //
- // Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
- // Dimm 1 QR DIMM <---------+----DimmSpdPtr[1]
- // | DimmSpdPtr[2]------->NULL
- // +----DimmSpdPtr[3]
- //
- // Socket N Channel N Dimm 0 QR DIMM <-----+--------DimmSpdPtr[0]
- // Dimm 1 QR DIMM <-----|---+----DimmSpdPtr[1]
- // +-- | ---DimmSpdPtr[2]
- // +----DimmSpdPtr[3]
- //
- // 3 DIMMS PER CHANNEL
- //
- // Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
- // Dimm 1 SR/DR DIMM <--------------DimmSpdPtr[1]
- // Dimm 3 SR/DR DIMM <--------------DimmSpdPtr[2]
- // DimmSpdPtr[3]------->NULL
- //
- // Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
- // Dimm 1 QR DIMM <---------+----DimmSpdPtr[1]
- // Dimm 3 SR/DR DIMM <-------- | ---DimmSpdPtr[2]
- // +----DimmSpdPtr[3]
- //
- //
- // FOR LRDIMMS
- //
- // This code will assign SPD pointers on the basis of Physical ranks, even though
- // an LRDIMM may only use one or two logical ranks, that determination will have to
- // be made from downstream code. An LRDIMM with greater than 2 Physical ranks will have
- // its DimmSpdPtr[] mapped as if it were a QR in the above diagrams.
-
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- DCTPtr = NBPtr->DCTPtr;
- for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) {
- NBPtr->SwitchChannel (NBPtr, Channel);
- ChannelPtr = NBPtr->ChannelPtr;
- ChannelPtr->TechType = DDR3_TECHNOLOGY;
- ChannelPtr->MCTPtr = MCTPtr;
- ChannelPtr->DCTPtr = DCTPtr;
-
- DimmSlots = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration,
- MCTPtr->SocketId,
- NBPtr->GetSocketRelativeChannel (NBPtr, Dct, Channel)
- );
- //
- // Initialize the SPD pointers for each Dimm
- //
- for (i = 0 ; i < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0])) ; i++) {
- ChannelPtr->DimmSpdPtr[i] = NULL;
- }
- for (i = 0 ; i < DimmSlots; i++) {
- ChannelPtr->DimmSpdPtr[i] = &(ChannelPtr->SpdPtr[i]);
- if ( (i + 2) < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0]))) {
- if (ChannelPtr->DimmSpdPtr[i]->DimmPresent) {
- if ((((ChannelPtr->DimmSpdPtr[i]->Data[SPD_RANKS] >> 3) & 0x07) + 1) > 2) {
- ChannelPtr->DimmSpdPtr[i + 2] = &(ChannelPtr->SpdPtr[i]);
- }
- }
- }
- }
- }
- }
- // Initialize Common technology functions
- MemTCommonTechInit (TechPtr);
-
- return TRUE;
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mt3.h b/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mt3.h
deleted file mode 100644
index 6769da0..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mt3.h
+++ /dev/null
@@ -1,136 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mt3.h
- *
- * Common Technology
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR3)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MT3_H_
-#define _MT3_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-MemConstructTechBlock3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-BOOLEAN
-MemTSetDramMode3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemTDIMMPresence3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemTSPDCalcWidth3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemTSPDGetTargetSpeed3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemTAutoCycTiming3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemTSPDSetBanks3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-VOID
-MemTGetCSIntLvAddr3 (
- IN UINT8 BankEnc,
- OUT UINT8 *LowBit,
- OUT UINT8 *HiBit
- );
-
-VOID
-MemTSendAllMRCmds3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 ChipSel
- );
-
-VOID
-FreqChgCtrlWrd3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-
-BOOLEAN
-MemTGetDimmSpdBuffer3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT UINT8 **SpdBuffer,
- IN UINT8 Dimm
- );
-#endif /* _MT3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mtlrdimm3.c b/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mtlrdimm3.c
deleted file mode 100644
index 4775def..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mtlrdimm3.c
+++ /dev/null
@@ -1,1102 +0,0 @@
-/**
- * @file
- *
- * mtlrdimm3.c
- *
- * Technology initialization and control workd support for DDR3 LRDIMMS
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR3)
- * @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "mu.h"
-#include "mt.h"
-#include "mt3.h"
-#include "mtspd3.h"
-#include "mtrci3.h"
-#include "mtsdi3.h"
-#include "mtlrdimm3.h"
-#include "merrhdl.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-#define FILECODE PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-VOID
-STATIC
-MemTSendMBCtlWord3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Fn,
- IN UINT8 Rcw,
- IN UINT8 Value
- );
-
-UINT8
-STATIC
-MemTGetSpecialMBCtlWord3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Dimm,
- IN UINT8 Fn,
- IN UINT8 Rc
- );
-
-BOOLEAN
-STATIC
-MemTLrDimmControlRegInit3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT VOID *OptParam
- );
-
-BOOLEAN
-STATIC
-MemTLrDimmFreqChgCtrlWrd3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT VOID *OptParam
- );
-
-BOOLEAN
-STATIC
-MemTWLPrepareLrdimm3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT VOID *Wl
- );
-
-BOOLEAN
-STATIC
-MemTSendAllMRCmdsLR3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT VOID *CsPtr
- );
-
-VOID
-STATIC
-MemTEMRS1Lr3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 ChipSel,
- IN UINT8 PhyRank
- );
-
-VOID
-STATIC
-MemTEMRS2Lr3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 ChipSel
- );
-
-
-BOOLEAN
-STATIC
-MemTLrdimmRankMultiplication (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT VOID *DimmID
- );
-
-BOOLEAN
-STATIC
-MemTLrdimmBuf2DramTrain3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT VOID *OptParam
- );
-
-BOOLEAN
-STATIC
-MemTLrdimmSyncTrainedDlys (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT VOID *OptParam
- );
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initializes LRDIMM functions.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-BOOLEAN
-MemTLrdimmConstructor3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- TechPtr->TechnologySpecificHook[LrdimmSendAllMRCmds] = MemTSendAllMRCmdsLR3;
- TechPtr->TechnologySpecificHook[LrdimmControlRegInit] = MemTLrDimmControlRegInit3;
- TechPtr->TechnologySpecificHook[LrdimmFreqChgCtrlWrd] = MemTLrDimmFreqChgCtrlWrd3;
- TechPtr->TechnologySpecificHook[WlTrainingPrepareLrdimm] = MemTWLPrepareLrdimm3;
- TechPtr->TechnologySpecificHook[LrdimmRankMultiplication] = MemTLrdimmRankMultiplication;
- TechPtr->TechnologySpecificHook[LrdimmBuf2DramTrain] = MemTLrdimmBuf2DramTrain3;
- TechPtr->TechnologySpecificHook[LrdimmSyncTrainedDlys] = MemTLrdimmSyncTrainedDlys;
- return TRUE;
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sends a Control word command to an LRDIMM Memory Buffer
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] Fn - control word function
- * @param[in] Rcw - control word number
- * @param[in] Value - value to send
- *
- */
-
-VOID
-STATIC
-MemTSendMBCtlWord3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Fn,
- IN UINT8 Rcw,
- IN UINT8 Value
- )
-{
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
-
- ASSERT (Rcw != RCW_FN_SELECT); // RC7 can only be used for function select
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\tF%dRC%d = %x\n", Fn, Rcw, Value);
- //
- // Select the MB Function by sending the Fn number
- // to the Function Select Control Word
- //
- MemUWait10ns (800, NBPtr->MemPtr);
- MemTSendCtlWord3 (TechPtr, RCW_FN_SELECT, Fn);
- //
- // Send the value to the control word
- //
- MemUWait10ns (800, NBPtr->MemPtr);
- MemTSendCtlWord3 (TechPtr, Rcw, Value);
-
-
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function gets the value of special RCW
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] Dimm - Physical LR DIMM number
- * @param[in] Fn - control word function
- * @param[in] Rc - control word number
- *
- * @return Special RCW value
- *
- */
-
-UINT8
-STATIC
-MemTGetSpecialMBCtlWord3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Dimm,
- IN UINT8 Fn,
- IN UINT8 Rc
- )
-{
- CONST UINT8 F0RC13PhyRankTab[] = {3, 2, 0, 1, 0};
- UINT8 PhyRanks;
- UINT8 LogRanks;
- UINT8 DramCap;
- UINT8 Value8;
- UINT8 *SpdBufferPtr;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
-
- MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, Dimm);
-
- Value8 = 0;
- switch (Fn) {
- case 0:
- switch (Rc) {
- case 8:
- // F0RC8
- Value8 = NBPtr->PsPtr->F0RC8;
- break;
- case 10:
- // F0RC10
- // 2:0 OperatingSpeed: operating speed. BIOS: Table 88.
- if (NBPtr->DCTPtr->Timings.Speed == DDR667_FREQUENCY) {
- Value8 = 0;
- } else {
- Value8 = (UINT8) (NBPtr->DCTPtr->Timings.Speed / 133) - 3;
- }
- break;
- case 11:
- // F0RC11
- // 3:2 ParityCalculation: partiy calculation. BIOS: Table.
- // 1:0 OperatingVoltage: operating voltage. BIOS: IF(VDDIO == 1.5) THEN 00b ELSEIF (VDDIO ==
- // 1.35) THEN 01b ELSE 10b ENDIF.
- DramCap = SpdBufferPtr[SPD_DENSITY] & 0xF;
- if ((NBPtr->ChannelPtr->LrDimmRankMult[Dimm] + DramCap * 2) > 8) {
- Value8 = 8;
- } else {
- Value8 = 4;
- }
- Value8 |= NBPtr->RefPtr->DDR3Voltage;
- break;
- case 13:
- // F0RC13
- // 3:2 NumLogicalRanks: partiy calculation. BIOS: Table 90.
- // 1:0 NumPhysicalRanks: operating voltage. BIOS: Table 89.
- LogRanks = NBPtr->ChannelPtr->LrDimmLogicalRanks[Dimm] >> 1;
- PhyRanks = F0RC13PhyRankTab[(SpdBufferPtr[SPD_RANKS] >> 3) & 7];
- Value8 = (LogRanks << 2) | PhyRanks;
- break;
- case 14:
- // F0RC14
- // 3 DramBusWidth: DRAM bus width. BIOS: IF (DeviceWidth==0) THEN 0 ELSE 1 ENDIF.
- // 2 MRSCommandControl: MRS command control. BIOS: IF (F0RC15[RankMultiplicationControl]
- // > 0) THEN 1 ELSE 0 ENDIF.
- // 1 RefreshPrechargeCommandControl: refresh and precharge command control. BIOS: IF
- // (F0RC15[RankMultiplicationControl] > 0) THEN D18F2xA8_dct[1:0][LrDimmEnhRefEn] ELSE 0 ENDIF.
- // 0 AddressMirror: address mirror. BIOS: RankMap. See D18F2x[5C:40]_dct[1:0][OnDimmMirror].
- if ((SpdBufferPtr[SPD_DEV_WIDTH] & 7) != 0) {
- Value8 |= 8;
- }
- if (NBPtr->ChannelPtr->LrDimmRankMult[Dimm] > 1) {
- Value8 |= 4;
- if (NBPtr->GetBitField (NBPtr, BFLrDimmEnhRefEn) == 1) {
- Value8 |= 2;
- }
- }
- if ((SpdBufferPtr[SPD_ADDRMAP] & 1) != 0) {
- Value8 |= 1;
- }
- break;
- case 15:
- // F0RC15
- // 3:0 RankMultiplicationControl: rank multiplication control. BIOS: Table 91.
- DramCap = SpdBufferPtr[SPD_DENSITY] & 0xF;
- ASSERT ((DramCap >= 2) && (DramCap <= 4)); // BKDG only lists 1Gb, 2Gb, and 4Gb
- switch (NBPtr->ChannelPtr->LrDimmRankMult[Dimm]) {
- case 1:
- Value8 = 0;
- break;
- case 2:
- Value8 = DramCap - 1;
- break;
- case 4:
- Value8 = DramCap + 3;
- break;
- default:
- ASSERT (FALSE);
- }
- break;
- default:
- ASSERT (FALSE);
- }
- break;
- case 1:
- switch (Rc) {
- case 0:
- // F1RC0
- Value8 = NBPtr->PsPtr->F1RC0;
- Value8 |= (UINT8) NBPtr->GetBitField (NBPtr, BFCSTimingMux67) << 3;
- break;
- case 1:
- // F1RC1
- Value8 = NBPtr->PsPtr->F1RC1;
- break;
- case 2:
- // F1RC2
- Value8 = NBPtr->PsPtr->F1RC2;
- break;
- case 9:
- // F1RC9
- if (NBPtr->GetBitField (NBPtr, BFLrDimmEnhRefEn) == 0) {
- Value8 = 1;
- }
- break;
- default:
- ASSERT (FALSE);
- }
- break;
- case 3:
- switch (Rc) {
- case 0:
- // F3RC0
- // 3 TDQSControl: TDQS control. BIOS: 0.
- // 2:0 RttNom: RttNom. BIOS: Table 57, Table 60
- Value8 = NBPtr->PsPtr->RttNom[Dimm << 1];
- break;
- case 1:
- // F3RC1
- // 3 Vref: Vref. BIOS: 0.
- // 2:0 RttWr: RttWr. BIOS: Table 57, Table 60.
- Value8 = NBPtr->PsPtr->RttWr[Dimm << 1];
- break;
- default:
- ASSERT (FALSE);
- }
- break;
- default:
- ASSERT (FALSE);
- }
-
- return Value8;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sends LRDIMM Control Words to all LRDIMMS
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in,out] OptParam - Optional parameter
- *
- * @return TRUE
- */
-
-BOOLEAN
-STATIC
-MemTLrDimmControlRegInit3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT VOID *OptParam
- )
-{
- CONST UINT8 RCWInitTable[] = {
- // RCW, Mask, SPD
- F0, RC0, 0x00, SPD_NONE,
- F0, RC1, 0x00, SPD_NONE,
- F0, RC2, 0x03, SPD_67,
- F0, RC10, 0x00, SPECIAL_CASE,
- F0, RC11, 0x00, SPECIAL_CASE,
-
- F1, RC8, 0x0F, SPD_69,
- F1, RC11, 0xF0, SPD_69,
- F1, RC12, 0x0F, SPD_70,
- F1, RC13, 0xF0, SPD_70,
- F1, RC14, 0x0F, SPD_71,
- F1, RC15, 0xF0, SPD_71,
-
- WAIT_6US, 0, 0, 0,
-
- F0, RC3, 0xF0, SPD_67,
- F0, RC4, 0x0F, SPD_68,
- F0, RC5, 0xF0, SPD_68,
-
- F0, RC6, 0x00, SPD_NONE,
- F0, RC8, 0x00, SPECIAL_CASE,
- F0, RC9, 0x0C, SPD_NONE,
- F0, RC13, 0x00, SPECIAL_CASE,
- F0, RC14, 0x00, SPECIAL_CASE,
- F0, RC15, 0x00, SPECIAL_CASE,
-
- F1, RC0, 0x00, SPECIAL_CASE,
- F1, RC1, 0x00, SPECIAL_CASE,
- F1, RC2, 0x00, SPECIAL_CASE,
- F1, RC3, 0x00, SPD_NONE,
- F1, RC9, 0x00, SPECIAL_CASE,
- F1, RC10, 0x00, SPD_NONE,
-
- F2, RC0, 0x00, SPD_NONE,
- F2, RC1, 0x00, SPD_NONE,
- F2, RC2, 0x0F, SPD_NONE,
- F2, RC3, 0x00, SPD_NONE,
-
- F3, RC0, 0x00, SPECIAL_CASE,
- F3, RC1, 0x00, SPECIAL_CASE,
- F3, RC2, 0x01, SPD_NONE,
- F3, RC6, 0x08, SPD_NONE
-
- // F3 RC[8,9] are programmed in MDQ RC loop
-
- // F[10:3] RC[11,10] are programmed in QxODT RC loop
-
- // F[15,14] RC[15:0] are programmed in personality RC loop
- };
-
- UINT8 Dimm;
- UINT16 i;
- UINT16 DimmMask;
- UINT8 Fn;
- UINT8 Rc;
- UINT8 Mask;
- UINT8 Spd;
- UINT8 *SpdBufferPtr;
- UINT8 FreqDiffOffset;
- UINT8 Value8;
- MEM_DATA_STRUCT *MemPtr;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
- MemPtr = NBPtr->MemPtr;
-
- if (NBPtr->MCTPtr->Status[SbLrdimms]) {
- for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
- DimmMask = (UINT16)1 << Dimm;
- if ((NBPtr->ChannelPtr->LrDimmPresent & DimmMask) != 0) {
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\tSending LRDIMM Control Words: Dimm %02x\n", Dimm);
- //
- // Select the Target Chipselects
- //
- NBPtr->SetBitField (NBPtr, BFMrsChipSel, (Dimm << 1));
- NBPtr->SetBitField (NBPtr, BFCtrlWordCS, 3 << (Dimm << 1));
-
- MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, Dimm);
- for (i = 0; i < sizeof (RCWInitTable) ; i += 4) {
- Fn = RCWInitTable[i];
- Rc = RCWInitTable[i + 1];
- Mask = RCWInitTable[i + 2];
- Spd = RCWInitTable[i + 3];
-
- if (Fn == WAIT_6US) {
- MemUWait10ns (600, MemPtr); // wait 6us for TSTAB
- } else {
- if (Spd == SPD_NONE) {
- Value8 = Mask;
- } else if (Spd == SPECIAL_CASE) {
- Value8 = MemTGetSpecialMBCtlWord3 (TechPtr, Dimm, Fn, Rc);
- } else {
- Value8 = (Mask > 0x0F) ? ((SpdBufferPtr[Spd] & Mask) >> 4) : (SpdBufferPtr[Spd] & Mask);
- }
- MemTSendMBCtlWord3 (TechPtr, Fn, Rc, Value8);
- }
- }
-
- FreqDiffOffset = (UINT8) (SPD_FREQ_DIFF_OFFSET * (((NBPtr->DCTPtr->Timings.Speed / 133) - 3) / 2));
- //
- // Send RCW to program MDQ termination and drive strength
- //
- for (Rc = 8; Rc <= 9; Rc++) {
- Value8 = SpdBufferPtr[SPD_MDQ_800_1066 + FreqDiffOffset];
- Value8 = (Rc == 9) ? (Value8 >> 4) : Value8;
- MemTSendMBCtlWord3 (TechPtr, 3, Rc, Value8 & 0x07);
- }
-
- //
- // Send RCW to program QxODT
- //
- for (Fn = 3; Fn <= 10; Fn ++) {
- for (Rc = 10; Rc <= 11; Rc++) {
- Value8 = SpdBufferPtr[SPD_QXODT_800_1066 + FreqDiffOffset + ((Fn - 3) >> 1)];
- Value8 = (Rc == 11) ? (Value8 >> 4) : (Value8 & 0x0F);
- Value8 = ((Fn & 1) == 0) ? (Value8 >> 2) : (Value8 & 0x03);
- MemTSendMBCtlWord3 (TechPtr, Fn, Rc, Value8);
- }
- }
-
- //
- // Send Personality bytes from SPD
- //
- for (Fn = 14; Fn < 16; Fn ++) {
- for (Rc = 0; Rc < 16 ; Rc++) {
- Value8 = SpdBufferPtr[SPD_PERSONALITY_BYTE + ((Fn - 14) << 3) + (Rc >> 1)];
- if ((Fn == 14) && (Rc == 0)) {
- Value8 |= 0x01; // Write global enable
- }
- if (Rc != 0x07) {
- MemTSendMBCtlWord3 (TechPtr, Fn, Rc, ((Rc & 1) != 0) ? (Value8 >> 4) : (Value8 & 0x0F));
- }
- }
- }
- }
- }
- }
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sends LRDIMM Control Words to all LRDIMMS
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in,out] OptParam - Optional parameter
- *
- * @return FALSE - The current channel does not have LRDIMM populated
- * TRUE - The current channel has LRDIMM populated
- */
-
-BOOLEAN
-STATIC
-MemTLrDimmFreqChgCtrlWrd3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT VOID *OptParam
- )
-{
- UINT8 Dct;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
-
- if (NBPtr->MCTPtr->Status[SbLrdimms]) {
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- MemNSwitchDCTNb (NBPtr, Dct);
- if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
- MemTLrDimmControlRegInit3 (TechPtr, NULL);
- }
- }
- return TRUE;
- }
- return FALSE;
-}
-
-/*-----------------------------------------------------------------------------
- *
- *
- * This function prepares LRDIMMs for WL training.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in,out] *Wl - Indicates if WL mode should be enabled
- *
- * @return TRUE - LRDIMMs present
- * ----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemTWLPrepareLrdimm3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT VOID *Wl
- )
-{
- UINT8 Dimm;
- UINT8 Value8;
- UINT16 MrsAddress;
- MEM_NB_BLOCK *NBPtr;
- NBPtr = TechPtr->NBPtr;
- MrsAddress = 0;
- if (NBPtr->MCTPtr->Status[SbLrdimms]) {
- for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
- if (*(BOOLEAN *) Wl == TRUE) {
- // Program WrLvOdt
- NBPtr->SetBitField (NBPtr, BFWrLvOdt, NBPtr->ChannelPtr->PhyWLODT[Dimm]);
- }
- if ((NBPtr->ChannelPtr->LrDimmPresent & ((UINT8) 1 << Dimm)) != 0) {
- if (Dimm == TechPtr->TargetDIMM) {
- if (*(BOOLEAN *) Wl == TRUE) {
- //
- // Select the Target Chipselects
- //
- NBPtr->SetBitField (NBPtr, BFMrsChipSel, (Dimm << 1));
- NBPtr->SetBitField (NBPtr, BFCtrlWordCS, 3 << (Dimm << 1));
-
- // Program F0RC12 to 1h
- MemTSendMBCtlWord3 (TechPtr, F0, RC12, 0x01);
- if (NBPtr->ChannelPtr->Dimms >= 2) {
- // For two or more LRDIMMs per channel program the buffer RttNom to the
- // corresponding specifed RttWr termination
- Value8 = NBPtr->MemNGetDynDramTerm (NBPtr, Dimm << 2);
- } else {
- // Program RttNom as normal
- Value8 = NBPtr->MemNGetDramTerm (NBPtr, Dimm << 2);
- }
- if ((Value8 & ((UINT8) 1 << 2)) != 0) {
- MrsAddress |= ((UINT16) 1 << 9);
- }
- if ((Value8 & ((UINT8) 1 << 1)) != 0) {
- MrsAddress |= ((UINT16) 1 << 6);
- }
- if ((Value8 & ((UINT8) 1 << 0)) != 0) {
- MrsAddress |= ((UINT16) 1 << 2);
- }
- NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
- } else {
- // Program F0RC12 to 0h
- MemTSendMBCtlWord3 (TechPtr, F0, RC12, 0x00);
- }
- }
- }
- }
- return TRUE;
- } else {
- return FALSE;
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This send all MR commands to all physical ranks of an LRDIMM
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] *CsPtr - Target Chip Select
- *
- * @return FALSE - The current channel does not have LRDIMM populated
- * TRUE - The current channel has LRDIMM populated
- */
-
-BOOLEAN
-STATIC
-MemTSendAllMRCmdsLR3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT VOID *CsPtr
- )
-{
- UINT8 *SpdBufferPtr;
- BOOLEAN Skip;
- UINT8 Rank;
- UINT8 PhyRank;
- UINT8 ChipSel;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
- ChipSel = *((UINT8 *) CsPtr);
-
- if (NBPtr->MCTPtr->Status[SbLrdimms]) {
- //
- // LRDIMM: MR0, MR2, and MR3 can be broadcasted.
- // MR1[Rtt_Nom] needs to be programmed differently per physical ranks.
- //
- // CS 0 1 2 3 4 5 6 7
- // MR[0,2,3] x x ?
- // MR1 x x x x x x x x
- //
- // ? If 3 DIMMs/ch, need to send to CS4 since it is on the 3rd physical DIMM.
- //
- Skip = TRUE;
- switch (ChipSel) {
- case 0:
- case 2:
- Skip = FALSE;
- break;
- case 4:
- if (GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration,
- NBPtr->MCTPtr->SocketId,
- NBPtr->ChannelPtr->ChannelID) == 3) {
- Skip = FALSE;
- }
- break;
- }
-
- // Select target chip select
- NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel);
-
- if (!Skip) {
- // 13.Send EMRS(2)
- MemTEMRS2Lr3 (TechPtr, ChipSel);
- NBPtr->SetBitField (NBPtr, BFMrsAddressHi, 1); // Set Address bit 13 to broadcast
- NBPtr->SendMrsCmd (NBPtr);
-
- // 14.Send EMRS(3). Ordinarily at this time, MrsAddress[2:0]=000b
- MemTEMRS33 (TechPtr);
- NBPtr->SetBitField (NBPtr, BFMrsAddressHi, 1); // Set Address bit 13 to broadcast
- NBPtr->SendMrsCmd (NBPtr);
- }
-
- // 15.Send EMRS(1). Send to each physical rank.
- MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, ChipSel >> 1);
- for (Rank = 0; Rank < NBPtr->ChannelPtr->LrDimmRankMult[ChipSel >> 1]; Rank++) {
- PhyRank = (((ChipSel >> 1) & 2) | (ChipSel & 1)) + (Rank * NBPtr->ChannelPtr->LrDimmLogicalRanks[ChipSel >> 1]);
- MemTEMRS1Lr3 (TechPtr, ChipSel, PhyRank);
- // Set Address bit 14, 15, 16, or 17 to select physical rank according to the device size
- NBPtr->SetBitField (NBPtr, BFMrsAddressHi, Rank << (SpdBufferPtr[SPD_DENSITY] & 0xF));
- NBPtr->SendMrsCmd (NBPtr);
- }
-
- if (!Skip) {
- // 16.Send MRS with MrsAddress[8]=1(reset the DLL)
- MemTMRS3 (TechPtr);
- NBPtr->SetBitField (NBPtr, BFMrsAddressHi, 1); // Set Address bit 13 to broadcast
- NBPtr->SendMrsCmd (NBPtr);
- }
-
- // If LRDIMM, return TRUE to skip sending regular MR commands.
- return TRUE;
- }
- // If not LRDIMM, send regular MR commands.
- return FALSE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function calculates the EMRS1 value for an LRDIMM
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] ChipSel - Chip select number
- * @param[in] PhyRank - Physical rank number
- */
-
-VOID
-STATIC
-MemTEMRS1Lr3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 ChipSel,
- IN UINT8 PhyRank
- )
-{
- UINT16 MrsAddress;
- UINT8 Value8;
- UINT8 *SpdBufferPtr;
- UINT8 FreqDiffOffset;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
-
- MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, ChipSel >> 1);
- FreqDiffOffset = (UINT8) (SPD_FREQ_DIFF_OFFSET * (((NBPtr->DCTPtr->Timings.Speed / 133) - 3) / 2));
-
- // BA2=0,BA1=0,BA0=1
- NBPtr->SetBitField (NBPtr, BFMrsBank, 1);
-
- MrsAddress = 0;
-
- // program MrsAddress[5,1]=output driver impedance control (DIC): 01b
- MrsAddress |= ((UINT16) 1 << 1);
-
- // program MrsAddress[5,1]=output driver impedance control (DIC):
- // DIC is read from SPD byte 77, 83, or 89 depending on DDR speed
- Value8 = SpdBufferPtr[SPD_MR1_MR2_800_1066 + FreqDiffOffset] & 3;
- if ((Value8 & ((UINT8) 1 << 1)) != 0) {
- MrsAddress |= ((UINT16) 1 << 5);
- }
- if ((Value8 & ((UINT8) 1 << 0)) != 0) {
- MrsAddress |= ((UINT16) 1 << 1);
- }
-
- // program MrsAddress[9,6,2]=nominal termination resistance of ODT (RTT):
- // RttNom is read from SPD byte 77, 83, or 89 depending on DDR speed
- if (PhyRank <= 1) {
- Value8 = (SpdBufferPtr[SPD_MR1_MR2_800_1066 + FreqDiffOffset] >> 2) & 7;
- if ((Value8 & ((UINT8) 1 << 2)) != 0) {
- MrsAddress |= ((UINT16) 1 << 9);
- }
- if ((Value8 & ((UINT8) 1 << 1)) != 0) {
- MrsAddress |= ((UINT16) 1 << 6);
- }
- if ((Value8 & ((UINT8) 1 << 0)) != 0) {
- MrsAddress |= ((UINT16) 1 << 2);
- }
- }
-
- NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function calculates the EMRS2 value for an LRDIMM
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] ChipSel - Chip select number
- */
-
-VOID
-STATIC
-MemTEMRS2Lr3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 ChipSel
- )
-{
- UINT8 RttWr;
- UINT8 *SpdBufferPtr;
- UINT8 FreqDiffOffset;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
-
- // Save default RttWr
- RttWr = NBPtr->PsPtr->RttWr[ChipSel];
-
- // Override RttWr with the value read from SPD byte 77, 83, or 89 depending on DDR speed
- MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, ChipSel >> 1);
- FreqDiffOffset = (UINT8) (SPD_FREQ_DIFF_OFFSET * (((NBPtr->DCTPtr->Timings.Speed / 133) - 3) / 2));
- NBPtr->PsPtr->RttWr[ChipSel] = SpdBufferPtr[SPD_MR1_MR2_800_1066 + FreqDiffOffset] >> 6;
-
- // Call EMRS2 calculation
- MemTEMRS23 (TechPtr);
-
- // Restore RttWr
- NBPtr->PsPtr->RttWr[ChipSel] = RttWr;
-}
-
-/*-----------------------------------------------------------------------------
- *
- *
- * This function to determine the Rank Multiplication to use for an LRDIMM
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in,out] *DimmID - Dimm ID
- *
- * @return TRUE - LRDIMM Support is installed and LRDIMMs are present
- * ----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemTLrdimmRankMultiplication (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT VOID *DimmID
- )
-{
- BOOLEAN RetVal;
- UINT8 *SpdBufferPtr;
- UINT8 Dimm;
- UINT8 NumDimmslots;
- UINT8 DramCapacity;
- UINT8 Ranks;
- UINT8 Rows;
- UINT8 RankMult;
- MEM_NB_BLOCK *NBPtr;
- CH_DEF_STRUCT *ChannelPtr;
-
- ASSERT (TechPtr != NULL);
- ASSERT (DimmID != NULL);
-
- Dimm = *(UINT8*)DimmID;
- ASSERT (Dimm < MAX_DIMMS_PER_CHANNEL);
-
- NBPtr = TechPtr->NBPtr;
- ChannelPtr = NBPtr->ChannelPtr;
- RetVal = FALSE;
- RankMult = 0;
-
- if (!MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, Dimm)) {
- ASSERT (FALSE);
- }
-
- NumDimmslots = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration,
- NBPtr->MCTPtr->SocketId,
- ChannelPtr->ChannelID);
-
- if (NBPtr->MCTPtr->Status[SbLrdimms]) {
- RetVal = TRUE;
- //
- // Determine LRDIMM Rank Multiplication
- //
- Ranks = ((SpdBufferPtr[SPD_RANKS] >> 3) & 0x07) + 1;
- if (Ranks == 5) {
- Ranks = 8;
- }
- DramCapacity = (SpdBufferPtr[SPD_DENSITY] & 0x0F);
- Rows = 12 + (SpdBufferPtr[SPD_ROW_SZ] >> 3) & 0x7;
-
- if (Ranks < 4) {
- RankMult = 1;
- } else if (Ranks == 4) {
- RankMult = (NumDimmslots < 3) ? 1 : 2;
- } else if (Ranks == 8) {
- RankMult = ((NumDimmslots < 3) && (DramCapacity < 4)) ? 2 : 4;
- }
- //
- // Save Rank Information
- //
- ChannelPtr->LrDimmRankMult[Dimm] = RankMult;
- ChannelPtr->LrDimmLogicalRanks[Dimm] = Ranks / RankMult;
- NBPtr->PsPtr->LrdimmRowAddrBits[Dimm] = Rows + (RankMult >> 1);
- //
- // Program RankDef
- //
- NBPtr->SetBitField (NBPtr, BFRankDef0 + Dimm, (RankMult == 4) ? 3 : RankMult);
- //
- // If LrdimmRowAddressBits > 16, then we must be useing some CS signals for rank
- // multiplication. If this is the case, then we want to clear the CSPresent bits
- // that correspond to those chipselects.
- // If there are 3 DIMMs per channel, then it will always be CS67, if there are
- // 2DPCH, then DIMM0 will use CS45, adn DIMM1 will use CS67.
- //
- if (NBPtr->PsPtr->LrdimmRowAddrBits[Dimm] > 16) {
- NBPtr->DCTPtr->Timings.CsPresent &= ~(0x30 << ((NumDimmslots > 2) ? 1 : Dimm) );
- }
- }
-
- return RetVal;
-
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function performs buffer to DRAM training for LRDIMMs
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in,out] OptParam - Optional parameter
- *
- * @return TRUE
- */
-
-BOOLEAN
-STATIC
-MemTLrdimmBuf2DramTrain3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT VOID *OptParam
- )
-{
- UINT8 Dct;
- UINT8 Dimm;
- UINT8 ChipSel;
- UINT16 DimmMask;
- UINT8 i;
- MEM_DATA_STRUCT *MemPtr;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
- MemPtr = NBPtr->MemPtr;
-
- if (NBPtr->MCTPtr->Status[SbLrdimms]) {
- IDS_HDT_CONSOLE (MEM_FLOW, "\nStart Buffer to DRAM training\n");
-
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct);
- NBPtr->SwitchDCT (NBPtr, Dct);
-
- //
- // ODM needs to be set after Dram Init
- //
- if (NBPtr->StartupSpeed == NBPtr->DCTPtr->Timings.Speed) {
- for (ChipSel = 1; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) {
- if ((NBPtr->DCTPtr->Timings.CsPresent & ((UINT16)1 << ChipSel)) != 0) {
- if ((NBPtr->DCTPtr->Timings.DimmMirrorPresent & (1 << (ChipSel >> 1))) != 0) {
- NBPtr->SetBitField (NBPtr, BFCSBaseAddr0Reg + ChipSel, ((NBPtr->GetBitField (NBPtr, BFCSBaseAddr0Reg + ChipSel)) | ((UINT32)1 << BFOnDimmMirror )));
- }
- }
- }
- }
-
- //
- // Buffer to DRAM training
- //
- for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
- DimmMask = (UINT16)1 << Dimm;
- if ((NBPtr->ChannelPtr->LrDimmPresent & DimmMask) != 0) {
- IDS_HDT_CONSOLE (MEM_STATUS, "\t\nDimm %d\n", Dimm);
- // Select the Target Chipselects
- NBPtr->SetBitField (NBPtr, BFMrsChipSel, (Dimm << 1));
- NBPtr->SetBitField (NBPtr, BFCtrlWordCS, 3 << (Dimm << 1));
-
- // Send F0RC12 with data = 0010b.
- MemTSendMBCtlWord3 (TechPtr, F0, RC12, 2);
-
- // Wait until D18F2xA0_dct[1:0][RcvParErr]=0 or tCAL * the number of physical ranks expires.
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\tWaiting %d ms...\n", 10 * NBPtr->ChannelPtr->LrDimmRankMult[Dimm]);
- for (i = 0; i < (NBPtr->ChannelPtr->LrdimmPhysicalRanks[Dimm] * 10); i++) {
- MemUWait10ns (1000000, MemPtr);
- }
-
- // Configure for normal operation: Send F0RC12 with data = 0000b.
- MemTSendMBCtlWord3 (TechPtr, F0, RC12, 0);
- }
- }
- }
- IDS_HDT_CONSOLE (MEM_FLOW, "\nEnd Buffer to DRAM training\n");
- }
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function copies trained delays of the first rank of a QR LRDIMM to the third rank
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in,out] OptParam - Optional parameter
- *
- * @return TRUE
- */
-
-BOOLEAN
-STATIC
-MemTLrdimmSyncTrainedDlys (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT VOID *OptParam
- )
-{
- UINT8 i;
- UINT8 Dimm;
- MEM_NB_BLOCK *NBPtr;
- CH_DEF_STRUCT *ChannelPtr;
-
- NBPtr = TechPtr->NBPtr;
- ChannelPtr = NBPtr->ChannelPtr;
-
- if (NBPtr->MCTPtr->Status[SbLrdimms]) {
- for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
- for (i = 0; i < TechPtr->DlyTableWidth (); i++) {
- if (ChannelPtr->LrDimmLogicalRanks[Dimm] > 2) {
- // If logical QR LRDIMM, copy trained delays from first rank to third rank
- NBPtr->SetTrainDly (NBPtr, AccessWrDqsDly, DIMM_BYTE_ACCESS (Dimm + 2, i),
- ChannelPtr->WrDqsDlys[Dimm * TechPtr->DlyTableWidth () + i]);
- NBPtr->SetTrainDly (NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Dimm + 2, i),
- ChannelPtr->RcvEnDlys[Dimm * TechPtr->DlyTableWidth () + i]);
- NBPtr->SetTrainDly (NBPtr, AccessRdDqsDly, DIMM_BYTE_ACCESS (Dimm + 2, i),
- ChannelPtr->RdDqsDlys[Dimm * TechPtr->DlyTableWidth () + i]);
- NBPtr->SetTrainDly (NBPtr, AccessWrDqsDly, DIMM_BYTE_ACCESS (Dimm + 2, i),
- ChannelPtr->WrDatDlys[Dimm * TechPtr->DlyTableWidth () + i]);
- }
- }
- }
- return TRUE;
- } else {
- return FALSE;
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mtlrdimm3.h b/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mtlrdimm3.h
deleted file mode 100644
index ebbec47..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mtlrdimm3.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/**
- * @file
- *
- * mtlrdimm3.h
- *
- * Definitions and declarations for DDR3 LRDIMM support
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem)
- * @e \$Revision: 27045 $ @e \$Date: 2010-02-22 17:21:31 -0600 (Mon, 22 Feb 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MTLRDIMM3_H_
-#define _MTLRDIMM3_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-#define RCW_FN_SELECT 7
-
-#define F0 0
-#define F1 1
-#define F2 2
-#define F3 3
-#define F4 4
-#define F5 5
-#define F6 6
-#define F7 7
-#define F8 8
-#define F9 9
-#define F10 10
-#define F11 11
-#define F12 12
-#define F13 13
-#define F14 14
-#define F15 15
-
-#define RC0 0
-#define RC1 1
-#define RC2 2
-#define RC3 3
-#define RC4 4
-#define RC5 5
-#define RC6 6
-#define RC7 7
-#define RC8 8
-#define RC9 9
-#define RC10 10
-#define RC11 11
-#define RC12 12
-#define RC13 13
-#define RC14 14
-#define RC15 15
-
-#define SPD_NONE 0
-#define SPD_67 67
-#define SPD_68 68
-#define SPD_69 69
-#define SPD_70 70
-#define SPD_71 71
-
-#define SPD_MDQ_800_1066 72
-#define SPD_QXODT_800_1066 73
-#define SPD_MR1_MR2_800_1066 77
-#define SPD_PERSONALITY_BYTE 150
-
-#define SPD_FREQ_DIFF_OFFSET 6
-
-#define SPECIAL_CASE 0xFF
-
-#define WAIT_6US 0xF6
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-#endif /* _MTLRDIMM3_H_ */
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mtot3.c b/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mtot3.c
deleted file mode 100644
index 2163ccf..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mtot3.c
+++ /dev/null
@@ -1,170 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mtot3.c
- *
- * Technology Non-SPD Timings for DDR3
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR3)
- * @e \$Revision: 38442 $ @e \$Date: 2010-09-24 06:39:57 +0800 (Fri, 24 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "mu.h"
-#include "mt.h"
-#include "mtot3.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_TECH_DDR3_MTOT3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function adjusts the Twrwr value for DDR3.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-VOID
-MemTAdjustTwrwr3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- DCT_STRUCT *DCTPtr;
-
- DCTPtr = TechPtr->NBPtr->DCTPtr;
-
- // For DDR3, value 0000b-0001b and >= 1011b of Twrwr is reserved.
- if (DCTPtr->Timings.Twrwr < 2) {
- DCTPtr->Timings.Twrwr = 2;
- } else if (DCTPtr->Timings.Twrwr > 10) {
- DCTPtr->Timings.Twrwr = 10;
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function adjusts the Twrrd value for DDR3.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-VOID
-MemTAdjustTwrrd3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- DCT_STRUCT *DCTPtr;
-
- DCTPtr = TechPtr->NBPtr->DCTPtr;
-
- // For DDR3, value 0000b, 0001b, and > 1010b of Twrrd is reserved.
- if (DCTPtr->Timings.Twrrd < 2) {
- DCTPtr->Timings.Twrrd = 2;
- } else if (DCTPtr->Timings.Twrrd > 10) {
- DCTPtr->Timings.Twrrd = 10;
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function gets the LD value for DDR3.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return Value of LD
- */
-
-INT8
-MemTGetLD3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- INT8 LD;
- MEM_NB_BLOCK *NBPtr;
- NBPtr = TechPtr->NBPtr;
- //
- // For DDR3, BIOS calculates the latency difference (Ld) as equal to read CAS latency minus write CAS
- // latency, in MEMCLKs (see F2x[1, 0]88[Tcl] and F2x[1, 0]84[Tcwl]) which can be a negative or positive
- // value.
- //
- LD = ((INT8) NBPtr->GetBitField (NBPtr, BFTcl) + 4) - ((INT8) NBPtr->GetBitField (NBPtr, BFTcwl) + 5);
-
- return LD;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mtot3.h b/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mtot3.h
deleted file mode 100644
index 8cdb9be..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mtot3.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mtot3.h
- *
- * Technology Non-SPD timings for DDR3
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR3)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MTOT3_H_
-#define _MTOT3_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-
-VOID
-MemTAdjustTwrwr3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-VOID
-MemTAdjustTwrrd3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-INT8
-MemTGetLD3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-#endif /* _MTOT3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mtrci3.c b/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mtrci3.c
deleted file mode 100644
index 106f501..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mtrci3.c
+++ /dev/null
@@ -1,297 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mtrci3.c
- *
- * Technology Control word initialization for DDR3
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR3)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "mu.h"
-#include "mt.h"
-#include "mtrci3.h"
-#include "merrhdl.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_TECH_DDR3_MTRCI3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sends control words
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-VOID
-MemTDramControlRegInit3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT8 ChipSel;
- UINT8 i;
- UINT8 RawCard;
- UINT8 Data;
- UINT16 CsPresent;
-
- MEM_DATA_STRUCT *MemPtr;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
- MemPtr = NBPtr->MemPtr;
- CsPresent = NBPtr->DCTPtr->Timings.CsPresent;
-
- MemUWait10ns (800, MemPtr); // wait 8us TACT must be changed to optimize to 8 MEM CLKs
-
- // Set EnDramInit to start DRAM initialization
-
- MemUWait10ns (600, MemPtr); // wait 6us for PLL LOCK
-
- for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) {
- //
- // If chip select present
- //
- if ((CsPresent & ((UINT16)3 << ChipSel)) != 0) {
- NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel);
-
- // 2. Program F2x[1, 0]A8[CtrlWordCS]=bit mask for target chip selects.
- NBPtr->SetBitField (NBPtr, BFCtrlWordCS, 3 << (ChipSel & 0xFE));
-
- RawCard = NBPtr->ChannelPtr->RefRawCard[ChipSel >> 1];
-
- for (i = 0; i <= 15; i++) {
- // wait 8us for TMRD, must be changed to optimize to 8 MEM CLKs
- MemUWait10ns (800, MemPtr);
- if ((i != 6) && (i != 7)) {
- Data = MemTGetCtlWord3 (TechPtr, i, RawCard, ChipSel);
- MemTSendCtlWord3 (TechPtr, i, Data);
- }
- }
- }
- }
- MemUWait10ns (600, MemPtr); // wait 6us for TSTAB
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function calculates the ControlRC value
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] CtrlWordNum - control Word number.
- * @param[in] RawCard - Raw Card
- * @param[in] ChipSel - Target Chip Select
- * @return Control Word value
- */
-
-UINT8
-MemTGetCtlWord3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 CtrlWordNum,
- IN UINT8 RawCard,
- IN UINT8 ChipSel
- )
-{
- UINT8 Data;
- DCT_STRUCT *DCTPtr;
- CH_DEF_STRUCT *ChannelPtr;
-
- DCTPtr = TechPtr->NBPtr->DCTPtr;
- ChannelPtr = TechPtr->NBPtr->ChannelPtr;
-
- Data = 0; //Default value for all control words is 0
- switch (CtrlWordNum) {
- case 0:
- Data = 0x02; // DA4=1
- break;
- case 1:
- if (DCTPtr->Timings.DimmSRPresent & ((UINT16) 1 << (ChipSel >> 1))) {
- Data = 0x0C; // if single rank, set DBA1 and DBA0
- }
- break;
- case 2:
- Data = ChannelPtr->CtrlWrd02[ChipSel >> 1];
- break;
- case 3:
- Data = ChannelPtr->CtrlWrd03[ChipSel >> 1];
- break;
- case 4:
- Data = ChannelPtr->CtrlWrd04[ChipSel >> 1];
- break;
- case 5:
- Data = ChannelPtr->CtrlWrd05[ChipSel >> 1];
- break;
- case 8:
- Data = ChannelPtr->CtrlWrd08[ChipSel >> 1];
- break;
- case 9:
- Data = 0x0D;
- break;
- default:;
- }
-
- return (Data & 0x0F);
-}
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sends control word command
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] CmdNum - control number.
- * @param[in] Value - value to send
- *
- */
-
-VOID
-MemTSendCtlWord3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 CmdNum,
- IN UINT8 Value
- )
-{
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
-
- // 1. Program MrsBank and MrsAddress.
- // n = [BA2, A2, A1, A0].
- // data = [BA1, BA0, A4, A3].
- // Set all other bits in MrsAddress to zero.
- //
- NBPtr->SetBitField (NBPtr, BFMrsBank, ((CmdNum & 8) >> 1) | (Value >> 2));
- NBPtr->SetBitField (NBPtr, BFMrsAddress, ((Value & 3) << 3) | (CmdNum & 7));
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tCS%d RC%02d %04x\n", (MemNGetBitFieldNb (NBPtr, BFMrsChipSel) & 7), CmdNum, Value);
-
- // 2.Set SendCtrlWord=1
- NBPtr->SetBitField (NBPtr, BFSendCtrlWord, 1);
- // 3.Wait for BFSendCtrlWord=0
- NBPtr->PollBitField (NBPtr, BFSendCtrlWord, 0, PCI_ACCESS_TIMEOUT, FALSE);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sends specific control words commands before frequency change for certain DRAM buffers.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-VOID
-FreqChgCtrlWrd3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT8 ChipSel;
- UINT16 Speed;
- UINT16 CsPresent;
-
- MEM_DATA_STRUCT *MemPtr;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
- MemPtr = NBPtr->MemPtr;
- Speed = NBPtr->DCTPtr->Timings.Speed;
- CsPresent = NBPtr->DCTPtr->Timings.CsPresent;
-
-
- for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) {
- //
- // If chip select present.
- //
- if ((CsPresent & ((UINT16)3 << ChipSel)) != 0) {
-
- NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel);
- // program F2x[1, 0]A8[CtrlWordCS]=bit mask for target chip selects.
- NBPtr->SetBitField (NBPtr, BFCtrlWordCS, 3 << (ChipSel & 0xFE));
-
- //wait 8us for TMRD, must be changed to optimize to 8 MEM CLKs
- MemUWait10ns (800, MemPtr);
- if (Speed == DDR1066_FREQUENCY) {
- MemTSendCtlWord3 (TechPtr, 0x0A, 1);
- } else if (Speed == DDR1333_FREQUENCY) {
- MemTSendCtlWord3 (TechPtr, 0x0A, 2);
- } else if (Speed == DDR1600_FREQUENCY) {
- MemTSendCtlWord3 (TechPtr, 0x0A, 3);
- }
- }
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mtrci3.h b/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mtrci3.h
deleted file mode 100644
index d5fdfee..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mtrci3.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mtrci3.h
- *
- * Technology control word init for DDR3
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR3)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MTRCI3_H_
-#define _MTRCI3_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-UINT8
-MemTGetCtlWord3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 CtrlWordNum,
- IN UINT8 RawCard,
- IN UINT8 ChipSel
- );
-
-VOID
-MemTDramControlRegInit3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-#endif /* _MTRCI3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mtsdi3.c b/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mtsdi3.c
deleted file mode 100644
index 48dc007..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mtsdi3.c
+++ /dev/null
@@ -1,493 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mtsdi3.c
- *
- * Technology Software DRAM Init for DDR3
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR3)
- * @e \$Revision: 37303 $ @e \$Date: 2010-09-02 03:43:36 +0800 (Thu, 02 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "mu.h"
-#include "mt.h"
-#include "mt3.h"
-#include "mtsdi3.h"
-#include "mtrci3.h"
-#include "merrhdl.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-#define FILECODE PROC_MEM_TECH_DDR3_MTSDI3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initiates software DRAM init for both DCTs
- * at the same time.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-BOOLEAN
-MemTDramInitSw3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT8 Dct;
- UINT8 ChipSel;
- UINT32 Dummy;
-
- MEM_DATA_STRUCT *MemPtr;
- DIE_STRUCT *MCTPtr;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
- MemPtr = NBPtr->MemPtr;
- MCTPtr = NBPtr->MCTPtr;
-
- IDS_HDT_CONSOLE (MEM_STATUS, "\nStart Dram Init\n");
- // 3.Program F2x[1,0]7C[EnDramInit]=1
- IDS_HDT_CONSOLE (MEM_FLOW, "\tEnDramInit = 1 for both DCTs\n");
- NBPtr->BrdcstSet (NBPtr, BFEnDramInit, 1);
- NBPtr->PollBitField (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, TRUE);
-
- // 4.wait 200us
- MemUWait10ns (20000, MemPtr);
-
- // 5.Program F2x[1, 0]7C[DeassertMemRstX] = 1.
- NBPtr->BrdcstSet (NBPtr, BFDeassertMemRstX, 1);
-
- // 6.wait 500us
- MemUWait10ns (50000, MemPtr);
-
- // Do Phy Fence training before sending MRS commands
- if (!NBPtr->IsSupported[FenceTrnBeforeDramInit]) {
- AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader));
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
- IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct);
- NBPtr->PhyFenceTraining (NBPtr);
- }
- }
- }
-
- // 7.NOP or deselect & take CKE high
- NBPtr->BrdcstSet (NBPtr, BFAssertCke, 1);
-
- // 8.wait 360ns
- MemUWait10ns (36, MemPtr);
-
- // The following steps are performed once for each channel with unbuffered DIMMs
- // and once for each chip select on registered DIMMs:
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
- IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct);
-
- // Enable Dram Parity if appropriate.
- NBPtr->FamilySpecificHook[EnableParityAfterMemRst] (NBPtr, NULL);
-
- // The following steps are performed with registered DIMMs only and
- // must be done for each chip select pair:
- if (MCTPtr->Status[SbRegistered]) {
- MemTDramControlRegInit3 (TechPtr);
- }
-
- // Initialize LRDIMM's register
- TechPtr->TechnologySpecificHook[LrdimmControlRegInit] (TechPtr, NULL);
-
- for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) {
- if (NBPtr->GetSysAddr (NBPtr, ChipSel, &Dummy)) {
- IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", ChipSel);
- // if chip select present
- if (!(TechPtr->TechnologySpecificHook[LrdimmSendAllMRCmds] (TechPtr, &ChipSel))) {
- MemTSendAllMRCmds3 (TechPtr, ChipSel);
- }
- // NOTE: wait 512 clocks for DLL-relock
- MemUWait10ns (50000, NBPtr->MemPtr); // wait 500us
- if (!(MCTPtr->Status[SbRegistered] || MCTPtr->Status[SbLrdimms])) {
- break;
- }
- }
- }
-
- // 17.Send two ZQCL commands (to even then odd chip select)
- NBPtr->sendZQCmd (NBPtr);
- NBPtr->sendZQCmd (NBPtr);
- }
- }
-
- // 18.Program F2x[1,0]7C[EnDramInit]=0
- NBPtr->BrdcstSet (NBPtr, BFEnDramInit, 0);
- NBPtr->PollBitField (NBPtr, BFDctAccessDone, 1, PCI_ACCESS_TIMEOUT, TRUE);
- //
- // For Unbuffered Dimms, Issue MRS for remaining CS without EnDramInit
- //
- NBPtr->FamilySpecificHook[SendMrsCmdsPerCs] (NBPtr, NBPtr);
-
- IDS_HDT_CONSOLE (MEM_FLOW, "End Dram Init\n\n");
- return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function calculates the EMRS1 value
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] Wl - Indicates if WL mode should be enabled
- * @param[in] TargetDIMM - DIMM target for WL
- */
-
-VOID
-MemTEMRS13 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN BOOLEAN Wl,
- IN UINT8 TargetDIMM
- )
-{
- UINT16 MrsAddress;
- UINT8 MaxDimmPerCH;
- UINT8 ChipSel;
- UINT8 Value8;
-
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
- MaxDimmPerCH = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration,
- NBPtr->MCTPtr->SocketId,
- NBPtr->ChannelPtr->ChannelID);
- ChipSel = (UINT8) (0x0FF & NBPtr->GetBitField (NBPtr, BFMrsChipSel));
-
- // BA2=0,BA1=0,BA0=1
- NBPtr->SetBitField (NBPtr, BFMrsBank, 1);
-
- MrsAddress = 0;
-
- // program MrsAddress[5,1]=output driver impedance control (DIC):
- // based on F2x[1,0]84[DrvImpCtrl]
- if (!(NBPtr->IsSupported[CheckDrvImpCtrl])) {
- Value8 = (UINT8)NBPtr->GetBitField (NBPtr, BFDrvImpCtrl);
- if ((Value8 & ((UINT8) 1 << 1)) != 0) {
- MrsAddress |= ((UINT16) 1 << 5);
- }
- if ((Value8 & ((UINT8) 1 << 0)) != 0) {
- MrsAddress |= ((UINT16) 1 << 1);
- }
- } else {
- MrsAddress |= ((UINT16) 1 << 1);
- }
- // program MrsAddress[9,6,2]=nominal termination resistance of ODT (RTT):
- // Different CS may have different RTT.
- //
- Value8 = NBPtr->MemNGetDramTerm (NBPtr, ChipSel);
-
- //
- // If Write Leveling this DIMM
- //
- if (Wl) {
- if ((ChipSel >> 1) == TargetDIMM) {
- // Program MrsAddress[7] = 1 for Write leveling enable
- MrsAddress |= ((UINT16) 1 << 7);
- if (ChipSel & 1) {
- // Output buffer disabled, MrsAddress[7] (Qoff = 1)
- MrsAddress |= ((UINT16) 1 << 12);
- }
- // Set Rtt_Nom = Rtt_Wr if there are 2 or more dimms
- if ((NBPtr->ChannelPtr->DimmQrPresent != 0) || (NBPtr->ChannelPtr->Dimms >= 2)) {
- Value8 = NBPtr->MemNGetDynDramTerm (NBPtr, ChipSel);
- }
- }
- }
- //
- // Turn off Rtt_Nom (DramTerm=0) for certain CS in certain configs.
- //
- // All odd CS for 4 Dimm Systems
- if (MaxDimmPerCH == 4) {
- if (ChipSel & 0x01) {
- Value8 = 0;
- }
- // CS 1 and 5 for 3 Dimm configs
- } else if (MaxDimmPerCH == 3) {
- if ((ChipSel == 1) || (ChipSel == 5)) {
- Value8 = 0;
- }
- }
- // All odd CS of any QR Dimms
- if ((NBPtr->ChannelPtr->DimmQrPresent & ((UINT8) (1 << (ChipSel >> 1)))) != 0) {
- if (ChipSel & 0x01) {
- Value8 = 0;
- }
- }
- if ((Value8 & ((UINT8) 1 << 2)) != 0) {
- MrsAddress |= ((UINT16) 1 << 9);
- }
- if ((Value8 & ((UINT8) 1 << 1)) != 0) {
- MrsAddress |= ((UINT16) 1 << 6);
- }
- if ((Value8 & ((UINT8) 1 << 0)) != 0) {
- MrsAddress |= ((UINT16) 1 << 2);
- }
-
- // program MrsAddress[12]=output disable (QOFF):
- // based on F2x[1,0]84[Qoff]
-
- if (!NBPtr->IsSupported[CheckQoff]) {
- if (NBPtr->GetBitField (NBPtr, BFQoff) != 0) {
- MrsAddress |= ((UINT16) 1 << 12);
- }
- }
-
- // program MrsAddress[11]=TDQS:
- // based on F2x[1,0]94[RDqsEn]
-
- if ((NBPtr->DCTPtr->Timings.Dimmx4Present != 0) && (NBPtr->DCTPtr->Timings.Dimmx8Present != 0)) {
- MrsAddress |= ((UINT16) 1 << 11);
- }
-
- NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function calculates the EMRS2 value
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-VOID
-MemTEMRS23 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT32 MrsAddress;
- UINT8 DramTermDyn;
- UINT8 MaxDimmPerCH;
- UINT8 ChipSel;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
-
- MaxDimmPerCH = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr->ChannelID );
- ChipSel = (UINT8) (0x0FF & NBPtr->GetBitField (NBPtr, BFMrsChipSel));
-
- // BA2=0,BA1=1,BA0=0
- NBPtr->SetBitField (NBPtr, BFMrsBank, 2);
-
- // program MrsAddress[5:3]=CAS write latency (CWL):
- MrsAddress = NBPtr->MemNGetMR2CWL (NBPtr);
-
- // program MrsAddress[6]=auto self refresh method (ASR):
- // program MrsAddress[7]=self refresh temperature range (SRT):
- MrsAddress |= 1 << 6;
- MrsAddress &= ( ~ (1 << 7));
-
- // program MrsAddress[10:9]=dynamic termination during writes (RTT_WR):
- DramTermDyn = NBPtr->MemNGetDynDramTerm (NBPtr, ChipSel);
- // Special Case for 1 DR Unbuffered Dimm in 3 Dimm/Ch
- if (!(NBPtr->MCTPtr->Status[SbRegistered])) {
- if (MaxDimmPerCH == 3) {
- if (NBPtr->ChannelPtr->Dimms == 1) {
- if ((NBPtr->ChannelPtr->DimmDrPresent & ((UINT8) (1 << (ChipSel >> 1)))) != 0) {
- DramTermDyn = 1;
- }
- }
- }
- }
- MrsAddress |= (UINT16) DramTermDyn << 9;
-
- NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function calculates the EMRS3 value
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-VOID
-MemTEMRS33 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
-
- // BA2=0,BA1=1,BA0=1
- NBPtr->SetBitField (NBPtr, BFMrsBank, 3);
-
- // program MrsAddress[1:0]=multi purpose register address location
- // (MPR Location):based on F2x[1,0]84[MprLoc]
- // program MrsAddress[2]=multi purpose register
- // (MPR):based on F2x[1,0]84[MprEn]
- NBPtr->SetBitField (NBPtr, BFMrsAddress, (NBPtr->GetBitField (NBPtr, BFDramMRSReg) >> 24) & 0x0007);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This sets MRS value
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-VOID
-MemTMRS3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT32 MrsAddress;
- MEM_NB_BLOCK *NBPtr;
- UINT32 Ppd;
-
- NBPtr = TechPtr->NBPtr;
-
- // BA2=0,BA1=0,BA0=0
- NBPtr->SetBitField (NBPtr, BFMrsBank, 0);
-
- // program MrsAddress[1:0]=burst length and control method
- // (BL):based on F2x[1,0]84[BurstCtrl]
- MrsAddress = NBPtr->GetBitField (NBPtr, BFBurstCtrl);
-
- // program MrsAddress[3]=1 (BT):interleaved
- MrsAddress |= (UINT16) 1 << 3;
-
- // program MrsAddress[6:4,2]=read CAS latency
- MrsAddress |= NBPtr->MemNGetMR0CL (NBPtr);
-
- // program MrsAddress[11:9]=write recovery for auto-precharge
- MrsAddress |= NBPtr->MemNGetMR0WR (NBPtr);
-
- // program MrsAddress[12] (PPD):based on F2x[1,0]84[PChgPDModeSel]
- Ppd = NBPtr->GetBitField (NBPtr, BFPchgPDModeSel);
- NBPtr->FamilySpecificHook[MR0_PPD] (NBPtr, &Ppd);
- IDS_OPTION_HOOK (IDS_MEM_MR0, &Ppd, &TechPtr->NBPtr->MemPtr->StdHeader);
- MrsAddress |= Ppd << 12;
-
- // program MrsAddress[8]=1 (DLL):DLL reset
- MrsAddress |= (UINT32) 1 << 8;
-
- NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This send all MR commands to a rank in sequence 2-3-1-0
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] ChipSel - Target Chip Select
- */
-
-VOID
-MemTSendAllMRCmds3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 ChipSel
- )
-{
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
-
- NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel);
-
- // 13.Send EMRS(2)
- MemTEMRS23 (TechPtr);
- NBPtr->SendMrsCmd (NBPtr);
-
- // 14.Send EMRS(3). Ordinarily at this time, MrsAddress[2:0]=000b
- MemTEMRS33 (TechPtr);
- NBPtr->SendMrsCmd (NBPtr);
-
- // 15.Send EMRS(1).
- MemTEMRS13 (TechPtr, FALSE, (ChipSel >> 1));
- NBPtr->SendMrsCmd (NBPtr);
-
- // 16.Send MRS with MrsAddress[8]=1(reset the DLL)
- MemTMRS3 (TechPtr);
- NBPtr->SendMrsCmd (NBPtr);
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mtsdi3.h b/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mtsdi3.h
deleted file mode 100644
index 5715a22..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mtsdi3.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mtsdi3.h
- *
- * Technology software DRAM init for DDR3
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR3)
- * @e \$Revision: 34985 $ @e \$Date: 2010-07-15 04:48:28 +0800 (Thu, 15 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MTSDI3_H_
-#define _MTSDI3_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-VOID
-MemTEMRS33 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-VOID
-MemTMRS3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-VOID
-MemTEMRS13 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN BOOLEAN Wl,
- IN UINT8 TargetDIMM
- );
-
-VOID
-MemTEMRS23 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-#endif /* _MTSDI3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mtspd3.c b/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mtspd3.c
deleted file mode 100644
index c2f9372..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mtspd3.c
+++ /dev/null
@@ -1,1153 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mtspd3.c
- *
- * Technology SPD supporting functions for DDR3
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR3)
- * @e \$Revision: 36054 $ @e \$Date: 2010-08-10 05:26:12 +0800 (Tue, 10 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "Ids.h"
-#include "mport.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mt3.h"
-#include "mu.h"
-#include "mtspd3.h"
-#include "mftds.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_TECH_DDR3_MTSPD3_FILECODE
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemTCRCCheck3 (
- IN OUT UINT8 *SPDPtr
- );
-
-UINT8
-STATIC
-MemTSPDGetTCL3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-STATIC
-MemTCheckBankAddr3 (
- IN UINT8 Encode,
- OUT UINT8 *Index
- );
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the DRAM mode
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - indicates that the DRAM mode is set to DDR3
- */
-
-BOOLEAN
-MemTSetDramMode3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- TechPtr->NBPtr->SetBitField (TechPtr->NBPtr, BFLegacyBiosMode, 0);
- TechPtr->NBPtr->SetBitField (TechPtr->NBPtr, BFDdr3Mode, 1);
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function determines if DIMMs are present. It checks checksum and interrogates the SPDs
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - indicates that a FATAL error has not occurred
- * @return FALSE - indicates that a FATAL error has occurred
- */
-
-BOOLEAN
-MemTDIMMPresence3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT8 Dct;
- UINT8 Channel;
- UINT8 i;
- MEM_PARAMETER_STRUCT *RefPtr;
- UINT8 *SpdBufferPtr;
- DIE_STRUCT *MCTPtr;
- DCT_STRUCT *DCTPtr;
- CH_DEF_STRUCT *ChannelPtr;
- MEM_NB_BLOCK *NBPtr;
- BOOLEAN SPDCtrl;
- UINT8 Devwidth;
- UINT8 MaxDimms;
- UINT8 Value8;
- UINT16 DimmMask;
-
- NBPtr = TechPtr->NBPtr;
- RefPtr = NBPtr->RefPtr;
- MCTPtr = NBPtr->MCTPtr;
-
- SPDCtrl = UserOptions.CfgIgnoreSpdChecksum;
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- DCTPtr = NBPtr->DCTPtr;
- for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) {
- NBPtr->SwitchChannel (NBPtr, Channel);
- ChannelPtr = NBPtr->ChannelPtr;
- ChannelPtr->DimmQrPresent = 0;
- //
- // Get the maximum number of DIMMs
- //
- MaxDimms = MAX_DIMMS_PER_CHANNEL;
- for (i = 0; i < MaxDimms; i++) {
- // Bitmask representing dimm #i.
- DimmMask = (UINT16)1 << i;
- //
- if (MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, i)) {
- MCTPtr->DimmPresent |= DimmMask;
- //
- // Check for valid checksum value
- //
- AGESA_TESTPOINT (TpProcMemSPDChecking, &(NBPtr->MemPtr->StdHeader));
- if (SpdBufferPtr[SPD_TYPE] == JED_DDR3SDRAM) {
- ChannelPtr->ChDimmValid |= DimmMask;
- MCTPtr->DimmValid |= DimmMask;
- } else {
- // Current socket is set up to only support DDR3 dimms.
- IDS_ERROR_TRAP;
- }
- if (!MemTCRCCheck3 (SpdBufferPtr) && !SPDCtrl) {
- //
- // NV_SPDCHK_RESTRT is set to 0,
- // cannot ignore faulty SPD checksum
- //
- // Indicate checksum error
- ChannelPtr->DimmSpdCse |= DimmMask;
- PutEventLog (AGESA_ERROR, MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_ERROR, MCTPtr);
- }
- //
- // Check module type information.
- //
- if (SpdBufferPtr[SPD_DIMM_TYPE] == JED_LRDIMM) {
- //
- // LRDIMMS
- //
- ChannelPtr->LrDimmPresent |= DimmMask;
- MCTPtr->LrDimmPresent |= DimmMask;
- if (!UserOptions.CfgMemoryLRDimmCapable) {
- PutEventLog (AGESA_WARNING, MEM_WARNING_UNSUPPORTED_LRDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- IDS_ERROR_TRAP;
- }
- }
- if (SpdBufferPtr[SPD_DIMM_TYPE] == JED_RDIMM || SpdBufferPtr[SPD_DIMM_TYPE] == JED_MINIRDIMM) {
- //
- // RDIMMS
- //
- ChannelPtr->RegDimmPresent |= DimmMask;
- MCTPtr->RegDimmPresent |= DimmMask;
- if (!UserOptions.CfgMemoryRDimmCapable) {
- PutEventLog (AGESA_WARNING, MEM_WARNING_UNSUPPORTED_RDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- IDS_ERROR_TRAP;
- }
- }
- if ((SpdBufferPtr[SPD_DIMM_TYPE] == JED_UDIMM) && !UserOptions.CfgMemoryUDimmCapable) {
- PutEventLog (AGESA_WARNING, MEM_WARNING_UNSUPPORTED_UDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- IDS_ERROR_TRAP;
- }
- if (SpdBufferPtr[SPD_DIMM_TYPE] == JED_SODIMM) {
- ChannelPtr->SODimmPresent |= DimmMask;
- if (!UserOptions.CfgMemorySODimmCapable) {
- PutEventLog (AGESA_WARNING, MEM_WARNING_UNSUPPORTED_SODIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- IDS_ERROR_TRAP;
- }
- }
- //
- // Check error correction type
- //
- if ((SpdBufferPtr[SPD_ECCBITS] & JED_ECC) != 0) {
- MCTPtr->DimmEccPresent |= DimmMask; // Dimm has ECC
- }
- //
- // Get the Dimm width data
- //
- Devwidth = SpdBufferPtr[SPD_DEV_WIDTH] & 0x7;
- switch (Devwidth) {
- case 0:
- ChannelPtr->Dimmx4Present |= DimmMask;
- Devwidth = 4;
- break;
- case 1:
- ChannelPtr->Dimmx8Present |= DimmMask;
- Devwidth = 8;
- break;
- case 2:
- ChannelPtr->Dimmx16Present |= DimmMask;
- Devwidth = 16;
- break;
- default:
- IDS_ERROR_TRAP;
- }
- //
- // Check for 'analysis probe installed'
- // if (SpdBufferPtr[SPD_ATTRIB] & JED_PROBE_MSK)
- //
- // Determine the geometry of the DIMM module
- // if (SpdBufferPtr[SPD_DM_BANKS] & SP_DPL_BIT)
- //
- // specify the number of ranks
- //
- Value8 = ((SpdBufferPtr[SPD_RANKS] >> 3) & 0x07) + 1;
- if (Value8 == 5) {
- // Octal Rank
- Value8 = 8;
- }
- //
- // For LRDIMMS we will assume that if there are at least 4 Physical ranks, then it Could be used
- // as a QR RDIMM with a rank Mux of x1 and therefore all four CS will be used. So an 8R LRDIMM will
- // be marked as a QR even if Rank multiplication allows it to use only 2 logical ranks.
- //
- if (ChannelPtr->LrDimmPresent |= DimmMask) {
- //
- // LRDIMM Physical Ranks
- //
- ChannelPtr->LrdimmPhysicalRanks[i] = Value8;
- }
- if (Value8 > 2) {
- if (!UserOptions.CfgMemoryQuadRankCapable) {
- PutEventLog (AGESA_WARNING, MEM_WARNING_UNSUPPORTED_QRDIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- }
- //
- // Mark this Dimm as Quad Rank
- //
- ChannelPtr->DimmQrPresent |= DimmMask;
- Value8 = 2;
- } else if (Value8 == 2) {
- ChannelPtr->DimmDrPresent |= DimmMask; // Dual rank dimms
- } else {
- ChannelPtr->DimmSRPresent |= DimmMask; // Single rank dimms
- }
- //
- // Calculate bus loading per Channel
- if (Devwidth == 16) {
- Devwidth = 4;
- } else if (Devwidth == 4) {
- Devwidth = 16;
- }
- //
- // Double Addr bus load value for dual rank DIMMs (Unless LRDIMM)
- //
- if ( ((ChannelPtr->LrDimmPresent |= DimmMask) == 0) && (Value8 == 2) ) {
- Devwidth = Devwidth << 1;
- }
- //
- ChannelPtr->Ranks = ChannelPtr->Ranks + Value8;
- ChannelPtr->Loads = ChannelPtr->Loads + Devwidth;
- if ((i < 2) || ((ChannelPtr->DimmQrPresent & DimmMask) == 0)) {
- ChannelPtr->Dimms++;
- }
- //
- // Check address mirror support for Unbuffered Dimms or LRDimms
- //
- if ((ChannelPtr->RegDimmPresent & DimmMask) == 0) {
- if ((SpdBufferPtr[SPD_ADDRMAP] & 1) != 0) {
- ChannelPtr->DimmMirrorPresent |= DimmMask;
- }
- }
- //
- // Get byte62: Reference Raw Card information
- //
- ChannelPtr->RefRawCard[i] = SpdBufferPtr[SPD_RAWCARD] & 0x1F;
- //
- // Get control word values for RC3, RC4 and RC5
- //
- ChannelPtr->CtrlWrd03[i] = SpdBufferPtr[SPD_CTLWRD03] >> 4;
- ChannelPtr->CtrlWrd04[i] = SpdBufferPtr[SPD_CTLWRD04] & 0x0F;
- ChannelPtr->CtrlWrd05[i] = SpdBufferPtr[SPD_CTLWRD05] >> 4;
- //
- // Temporarily store info. of SPD byte 63 into CtrlWrd02(s),
- // and they will be used late to calculate real RC2 and RC8 value
- //
- ChannelPtr->CtrlWrd02[i] = SpdBufferPtr[SPD_ADDRMAP] & 0x03;
- //
- // Copy the number of registers to the Ps Block to persist across frequency changes
- //
- NBPtr->PsPtr->NumOfReg[i] = SpdBufferPtr[SPD_ADDRMAP] & 0x03;
- //
- } // if DIMM present
- } // Dimm loop
-
- if (Channel == 0) {
- DCTPtr->Timings.DctDimmValid = ChannelPtr->ChDimmValid;
- DCTPtr->Timings.DimmMirrorPresent = ChannelPtr->DimmMirrorPresent;
- DCTPtr->Timings.DimmSpdCse = ChannelPtr->DimmSpdCse;
- DCTPtr->Timings.DimmQrPresent = ChannelPtr->DimmQrPresent;
- DCTPtr->Timings.DimmDrPresent = ChannelPtr->DimmDrPresent;
- DCTPtr->Timings.DimmSRPresent = ChannelPtr->DimmSRPresent;
- DCTPtr->Timings.Dimmx4Present = ChannelPtr->Dimmx4Present;
- DCTPtr->Timings.Dimmx8Present = ChannelPtr->Dimmx8Present;
- DCTPtr->Timings.Dimmx16Present = ChannelPtr->Dimmx16Present;
- }
- if ((Channel != 1) || (Dct != 1)) {
- MCTPtr->DimmPresent <<= 8;
- MCTPtr->DimmValid <<= 8;
- MCTPtr->RegDimmPresent <<= 8;
- MCTPtr->LrDimmPresent <<= 8;
- MCTPtr->DimmEccPresent <<= 8;
- MCTPtr->DimmParPresent <<= 8;
- }
- } // Channel loop
- } // DCT loop
-
- // If we have DIMMs, some further general characteristics checking
- if (MCTPtr->DimmValid != 0) {
- // If there are registered dimms, all the dimms must be registered
- if (MCTPtr->RegDimmPresent == MCTPtr->DimmValid) {
- // All dimms registered
- MCTPtr->Status[SbRegistered] = TRUE;
- MCTPtr->Status[SbParDimms] = TRUE; // All DDR3 RDIMMs are parity capable
- TechPtr->SetDqsEccTmgs = MemTSetDQSEccTmgsRDdr3; // Change the function pointer for DQS ECC timing
- } else if (MCTPtr->RegDimmPresent != 0) {
- // We have an illegal DIMM mismatch
- PutEventLog (AGESA_FATAL, MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_FATAL, MCTPtr);
- }
- // If there are LrDimms, all the dimms must be LrDimms
- if (MCTPtr->LrDimmPresent == MCTPtr->DimmValid) {
- // All dimms LRDIMMs
- MCTPtr->Status[SbLrdimms] = TRUE;
- } else if (MCTPtr->LrDimmPresent != 0) {
- // We have an illegal DIMM mismatch
- PutEventLog (AGESA_FATAL, MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_FATAL, MCTPtr);
- }
-
- // check the ECC capability of the DIMMs
- if (MCTPtr->DimmEccPresent == MCTPtr->DimmValid) {
- MCTPtr->Status[SbEccDimms] = TRUE; // All dimms ECC capable
- }
- } else {
- }
-
- NBPtr->SwitchDCT (NBPtr, 0);
- NBPtr->SwitchChannel (NBPtr, 0);
- return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function finds the maximum frequency that each channel is capable to run at.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - indicates that a FATAL error has not occurred
- * @return FALSE - indicates that a FATAL error has occurred
- */
-
-BOOLEAN
-MemTSPDGetTargetSpeed3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT8 *SpdBufferPtr;
- UINT8 Dimm;
- UINT8 Dct;
- UINT8 Channel;
- INT32 MTB_ps;
- INT32 FTB_ps;
- INT32 TCKmin_ps;
- INT32 Value32;
- MEM_NB_BLOCK *NBPtr;
- DCT_STRUCT *DCTPtr;
- CH_DEF_STRUCT *ChannelPtr;
-
- NBPtr = TechPtr->NBPtr;
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- DCTPtr = NBPtr->DCTPtr;
- TCKmin_ps = 0;
- for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) {
- NBPtr->SwitchChannel (NBPtr, Channel);
- ChannelPtr = NBPtr->ChannelPtr;
- for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
- if ((ChannelPtr->ChDimmValid & ((UINT8)1 << Dimm)) != 0) {
- MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, Dimm);
-
- // Determine tCKmin(all) which is the largest tCKmin
- // value for all modules on the memory Channel (SPD byte 12).
- //
- MTB_ps = ((INT32) SpdBufferPtr[SPD_DIVIDENT] * 1000) / SpdBufferPtr[SPD_DIVISOR];
- FTB_ps = (SpdBufferPtr[SPD_FTB] >> 4) / (SpdBufferPtr[SPD_FTB] & 0xF);
- Value32 = (MTB_ps * SpdBufferPtr[SPD_TCK]) + (FTB_ps * (INT8) SpdBufferPtr[SPD_TCK_FTB]) ;
- if (TCKmin_ps < Value32) {
- TCKmin_ps = Value32;
- }
- }
- }
- }
- if (TCKmin_ps <= 1071) {
- DCTPtr->Timings.TargetSpeed = DDR1866_FREQUENCY;
- } else if (TCKmin_ps <= 1250) {
- DCTPtr->Timings.TargetSpeed = DDR1600_FREQUENCY;
- } else if (TCKmin_ps <= 1500) {
- DCTPtr->Timings.TargetSpeed = DDR1333_FREQUENCY;
- } else if (TCKmin_ps <= 1875) {
- DCTPtr->Timings.TargetSpeed = DDR1066_FREQUENCY;
- } else if (TCKmin_ps <= 2500) {
- DCTPtr->Timings.TargetSpeed = DDR800_FREQUENCY;
- } else {
- DCTPtr->Timings.TargetSpeed = DDR667_FREQUENCY;
- }
- }
-
- // Ensure the target speed can be applied to all channels of the current node
- NBPtr->SyncTargetSpeed (NBPtr);
-
- // Set the start-up frequency
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- NBPtr->DCTPtr->Timings.Speed = TechPtr->NBPtr->StartupSpeed;
- }
- return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function check the symmetry of DIMM pairs (DIMM on Channel A matching with
- * DIMM on Channel B), the overall DIMM population, and determine the width mode:
- * 64-bit, 64-bit muxed, 128-bit.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - indicates that a FATAL error has not occurred
- * @return FALSE - indicates that a FATAL error has occurred
- */
-
-BOOLEAN
-MemTSPDCalcWidth3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT8 *SpdBufferAPtr;
- UINT8 *SpdBufferBPtr;
- MEM_NB_BLOCK *NBPtr;
- DIE_STRUCT *MCTPtr;
- DCT_STRUCT *DCTPtr;
- UINT8 i;
- UINT16 DimmMask;
- UINT8 UngangMode;
-
- NBPtr = TechPtr->NBPtr;
- MCTPtr = NBPtr->MCTPtr;
- DCTPtr = NBPtr->DCTPtr;
- UngangMode = UserOptions.CfgMemoryModeUnganged;
- // Does not support ganged mode for DDR3 dimms
- ASSERT (UngangMode);
- IDS_OPTION_HOOK (IDS_GANGING_MODE, &UngangMode, &(NBPtr->MemPtr->StdHeader));
-
- // Check symmetry of channel A and channel B dimms for 128-bit mode
- // capability.
- //
- AGESA_TESTPOINT (TpProcMemModeChecking, &(NBPtr->MemPtr->StdHeader));
- i = 0;
- if (!UngangMode) {
- if (MCTPtr->DctData[0].Timings.DctDimmValid == MCTPtr->DctData[1].Timings.DctDimmValid) {
- for (; i < MAX_DIMMS_PER_CHANNEL; i++) {
- DimmMask = (UINT16)1 << i;
- if ((DCTPtr->Timings.DctDimmValid & DimmMask) != 0) {
- NBPtr->SwitchDCT (NBPtr, 0);
- MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferAPtr, i);
- NBPtr->SwitchDCT (NBPtr, 1);
- MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferBPtr, i);
- // compare rows and columns
- if ((SpdBufferAPtr[SPD_ROW_SZ]&0x3F) != (SpdBufferBPtr[SPD_ROW_SZ]&0x3F)) {
- break;
- }
- if ((SpdBufferAPtr[SPD_DENSITY]&0x0F) != (SpdBufferBPtr[SPD_DENSITY]&0x0F)) {
- break;
- }
- // compare ranks and devwidth
- if ((SpdBufferAPtr[SPD_DEV_WIDTH]&0x7F) != (SpdBufferBPtr[SPD_DEV_WIDTH]&0x7F)) {
- break;
- }
- }
- }
- }
- if (i < MAX_DIMMS_PER_CHANNEL) {
- PutEventLog (AGESA_ALERT, MEM_ALERT_ORG_MISMATCH_DIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_ALERT, MCTPtr);
- } else {
- NBPtr->Ganged = TRUE;
- MCTPtr->GangedMode = TRUE;
- MCTPtr->Status[Sb128bitmode] = TRUE;
- NBPtr->SetBitField (NBPtr, BFDctGangEn, 1);
- }
- }
-
- return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Initialize DCT Timing registers as per DIMM SPD.
- * For primary timing (T, CL) use best case T value.
- * For secondary timing params., use most aggressive settings
- * of slowest DIMM.
- *
- * Note:
- * There are three components to determining "maximum frequency": SPD component,
- * Bus load component, and "Preset" max frequency component.
- * The SPD component is a function of the min cycle time specified by each DIMM,
- * and the interaction of cycle times from all DIMMs in conjunction with CAS
- * latency. The SPD component only applies when user timing mode is 'Auto'.
- *
- * The Bus load component is a limiting factor determined by electrical
- * characteristics on the bus as a result of varying number of device loads. The
- * Bus load component is specific to each platform but may also be a function of
- * other factors. The bus load component only applies when user timing mode is
- * ' Auto'.
- *
- * The Preset component is subdivided into three items and is the minimum of
- * the set: Silicon revision, user limit setting when user timing mode is 'Auto' and
- * memclock mode is 'Limit', OEM build specification of the maximum frequency.
- * The Preset component only applies when user timing mode is 'Auto'.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - indicates that a FATAL error has not occurred
- * @return FALSE - indicates that a FATAL error has occurred
- */
-
-BOOLEAN
-MemTAutoCycTiming3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- CONST UINT8 SpdIndexes[] = {
- SPD_TRCD,
- SPD_TRP,
- SPD_TRTP,
- SPD_TRAS,
- SPD_TRC,
- SPD_TWR,
- SPD_TRRD,
- SPD_TWTR,
- SPD_TFAW
- };
-
- CONST UINT8 SpdFTBIndexes[] = {
- SPD_TRCD_FTB,
- SPD_TRP_FTB,
- 0,
- 0,
- SPD_TRC_FTB,
- 0,
- 0,
- 0,
- 0
- };
-
- UINT8 *SpdBufferPtr;
- INT32 MiniMaxTmg[GET_SIZE_OF (SpdIndexes)];
- UINT8 MiniMaxTrfc[4];
-
- DIE_STRUCT *MCTPtr;
- DCT_STRUCT *DCTPtr;
- MEM_NB_BLOCK *NBPtr;
- UINT16 DimmMask;
- INT32 Value32;
- INT32 MTB_ps;
- INT32 FTB_ps;
- INT32 TCK_ps;
- UINT8 i;
- UINT8 j;
- UINT8 Value8;
- UINT8 *StatTmgPtr;
- UINT16 *StatDimmTmgPtr;
-
- NBPtr = TechPtr->NBPtr;
- MCTPtr = NBPtr->MCTPtr;
- DCTPtr = NBPtr->DCTPtr;
- // initialize mini-max arrays
- for (j = 0; j < GET_SIZE_OF (MiniMaxTmg); j++) {
- MiniMaxTmg[j] = 0;
- }
- for (j = 0; j < GET_SIZE_OF (MiniMaxTrfc); j++) {
- MiniMaxTrfc[j] = 0;
- }
-
- // ======================================================================
- // Get primary timing (CAS Latency and Cycle Time)
- // ======================================================================
- // Get OEM specific load variant max
- //
-
- //======================================================================
- // Gather all DIMM mini-max values for cycle timing data
- //======================================================================
- //
- DimmMask = 1;
- for (i = 0; i < (MAX_CS_PER_CHANNEL / 2); i++) {
- if ((DCTPtr->Timings.DctDimmValid & DimmMask) != 0) {
- MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, i);
- MTB_ps = ((INT32) SpdBufferPtr[SPD_DIVIDENT] * 1000) / SpdBufferPtr[SPD_DIVISOR];
- FTB_ps = (SpdBufferPtr[SPD_FTB] >> 4) / (SpdBufferPtr[SPD_FTB] & 0xF);
-
- for (j = 0; j < GET_SIZE_OF (SpdIndexes); j++) {
- Value32 = (UINT16)SpdBufferPtr[SpdIndexes[j]];
- if (SpdIndexes[j] == SPD_TRC) {
- Value32 |= ((UINT16)SpdBufferPtr[SPD_UPPER_TRC] & 0xF0) << 4;
- } else if (SpdIndexes[j] == SPD_TRAS) {
- Value32 |= ((UINT16)SpdBufferPtr[SPD_UPPER_TRAS] & 0x0F) << 8;
- } else if (SpdIndexes[j] == SPD_TFAW) {
- Value32 |= ((UINT16)SpdBufferPtr[SPD_UPPER_TFAW] & 0x0F) << 8;
- }
-
- Value32 *= MTB_ps;
- if (SpdFTBIndexes[j] != 0) {
- Value32 += (FTB_ps * (INT8) SpdBufferPtr[SpdFTBIndexes[j]]) ;
- }
- if (MiniMaxTmg[j] < Value32) {
- MiniMaxTmg[j] = Value32;
- }
- }
-
- // get Trfc0 - Trfc3 values
- Value8 = SpdBufferPtr[SPD_DENSITY] & 0x0F;
- if (MiniMaxTrfc[i] < Value8) {
- MiniMaxTrfc[i] = Value8;
- }
- }
- DimmMask <<= 1;
- }
-
- // ======================================================================
- // Convert DRAM CycleTiming values and store into DCT structure
- // ======================================================================
- //
- TCK_ps = 1000500 / DCTPtr->Timings.Speed;
-
- StatDimmTmgPtr = &DCTPtr->Timings.DIMMTrcd;
- StatTmgPtr = &DCTPtr->Timings.Trcd;
- for (j = 0; j < GET_SIZE_OF (SpdIndexes); j++) {
- Value32 = MiniMaxTmg[j];
-
- MiniMaxTmg[j] = (MiniMaxTmg[j] + TCK_ps - 1) / TCK_ps;
-
- StatDimmTmgPtr[j] = (UINT16) (Value32 / (1000 / 40));
- StatTmgPtr[j] = (UINT8) MiniMaxTmg[j];
- }
- DCTPtr->Timings.Trfc0 = MiniMaxTrfc[0];
- DCTPtr->Timings.Trfc1 = MiniMaxTrfc[1];
- DCTPtr->Timings.Trfc2 = MiniMaxTrfc[2];
- DCTPtr->Timings.Trfc3 = MiniMaxTrfc[3];
-
- DCTPtr->Timings.CasL = MemTSPDGetTCL3 (TechPtr);
-
- //======================================================================
- // Program DRAM Timing values
- //======================================================================
- //
- NBPtr->ProgramCycTimings (NBPtr);
-
- MemFInitTableDrive (NBPtr, MTAfterAutoCycTiming);
-
- return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the bank addressing, program Mask values and build a chip-select population map.
- * This routine programs PCI 0:24N:2x80 config register.
- * This routine programs PCI 0:24N:2x60,64,68,6C config registers (CS Mask 0-3)
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - indicates that a FATAL error has not occurred
- * @return FALSE - indicates that a FATAL error has occurred
- */
-
-BOOLEAN
-MemTSPDSetBanks3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT8 *SpdBufferPtr;
- UINT8 i;
- UINT8 ChipSel;
- UINT8 DimmID;
- UINT8 Value8;
- UINT8 Rows;
- UINT8 Cols;
- UINT8 Ranks;
- UINT8 Banks;
- UINT32 BankAddrReg;
- UINT32 CsMask;
- UINT16 CSSpdCSE;
- UINT16 CSExclude;
- UINT16 DimmQRDR;
- DIE_STRUCT *MCTPtr;
- DCT_STRUCT *DCTPtr;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
- MCTPtr = NBPtr->MCTPtr;
- DCTPtr = NBPtr->DCTPtr;
- BankAddrReg = 0;
- CSSpdCSE = 0;
- CSExclude = 0;
-
- for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) {
- DimmID = ChipSel >> 1;
-
- DimmQRDR = (DCTPtr->Timings.DimmQrPresent) | (DCTPtr->Timings.DimmDrPresent);
- if ((DCTPtr->Timings.DimmSpdCse & ((UINT16) 1 << DimmID)) != 0) {
- CSSpdCSE |= (UINT16) ((DimmQRDR & (UINT16) 1 << DimmID) ? 3 : 1) << ChipSel;
- }
- if ((DCTPtr->Timings.DimmExclude & ((UINT16) 1 << DimmID)) != 0) {
- CSExclude |= (UINT16) ((DimmQRDR & (UINT16) 1 << DimmID) ? 3: 1) << ChipSel;
- }
-
- if ((DCTPtr->Timings.DctDimmValid & ((UINT16)1 << DimmID)) != 0) {
- MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, DimmID);
-
- // Get the basic data
- Rows = (SpdBufferPtr[SPD_ROW_SZ] >> 3) & 0x7;
- Cols = SpdBufferPtr[SPD_COL_SZ] & 0x7;
- Banks = (SpdBufferPtr[SPD_L_BANKS] >> 4) & 0x7;
- Ranks = ((SpdBufferPtr[SPD_RANKS] >> 3) & 0x07) + 1;
- if (Ranks == 5) {
- Ranks = 8;
- }
-
- //
- // Configure the bank encoding
- // Use a 6-bit key into a lookup table.
- // Key (index) = RRRBCC, where CC is the number of Columns minus 9,
- // RRR is the number of Rows minus 12, and B is the number of banks
- // minus 3.
- //
- Value8 = Cols;
- Value8 |= (Banks == 1) ? 4 : 0;
- Value8 |= Rows << 3;
-
- if (MemTCheckBankAddr3 (Value8, &i)) {
- BankAddrReg |= ((UINT32)i << (ChipSel << 1));
-
- // Mask value=(2pow(rows+cols+banks+3)-1)>>8,
- // or 2pow(rows+cols+banks-5)-1
- //
- Value8 = (Rows + 12) + (Cols + 9) + (Banks + 3) + 3 - 8;
- if (MCTPtr->Status[Sb128bitmode]) {
- Value8++;
- }
-
- DCTPtr->Timings.CsPresent |= (UINT16)1 << ChipSel;
-
- if (Ranks >= 2) {
- DCTPtr->Timings.CsPresent |= (UINT16)1 << (ChipSel + 1);
- }
- //
- // Determine LRDIMM Rank Multiplication
- //
- if (TechPtr->TechnologySpecificHook[LrdimmRankMultiplication] (TechPtr, &DimmID)) {
- //
- // Increase the CS Size by the rank multiplication factor
- //
- Value8 += ((NBPtr->ChannelPtr->LrDimmRankMult[DimmID]) >> 1);
- }
-
- CsMask = ((UINT32)1 << Value8) - 1;
- // Update the DRAM CS Mask for this chipselect
- NBPtr->SetBitField (NBPtr, BFCSMask0Reg + (ChipSel >> 1), (CsMask & 0x1FF83FE0));
- } else {
- // Dimm is not supported, as no address mapping is found.
- DCTPtr->Timings.CsPresent |= (UINT16)1 << ChipSel;
- DCTPtr->Timings.CsTestFail |= (UINT16)1 << ChipSel;
- if (Ranks >= 2) {
- DCTPtr->Timings.CsPresent |= (UINT16)1 << (ChipSel + 1);
- DCTPtr->Timings.CsTestFail |= (UINT16)1 << (ChipSel + 1);
- }
- PutEventLog (AGESA_ERROR, MEM_ERROR_NO_ADDRESS_MAPPING, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, DimmID, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_ERROR, MCTPtr);
- }
- }
- }
- // For ranks that need to be excluded, the loading of this rank should be considered
- // in timing, so need to set CsPresent before setting CsTestFail
- if ((CSSpdCSE != 0) || (CSExclude != 0)) {
- NBPtr->MemPtr->ErrorHandling (MCTPtr, NBPtr->Dct, (CSSpdCSE | CSExclude), &NBPtr->MemPtr->StdHeader);
- }
-
- // If there are no chip selects, we have an error situation.
- if (DCTPtr->Timings.CsPresent == 0) {
- PutEventLog (AGESA_ERROR, MEM_ERROR_NO_CHIPSELECT, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_ERROR, MCTPtr);
- }
-
- NBPtr->SetBitField (NBPtr, BFDramBankAddrReg, BankAddrReg);
-
- return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function returns the low bit that will be swapped to enable CS interleaving
- *
- * @param[in] BankEnc - AddrMap Bank encoding from F2x80
- * @param[in] *LowBit - pointer to low bit
- * @param[in] *HiBit - pointer hight bit
- *
- */
-
-VOID
-MemTGetCSIntLvAddr3 (
- IN UINT8 BankEnc,
- OUT UINT8 *LowBit,
- OUT UINT8 *HiBit
- )
-{
- CONST UINT8 ArrCodesLo[] = {0, 8, 8, 0, 0, 8, 9, 8, 9, 9, 8, 9};
- CONST UINT8 ArrCodesHi[] = {0, 20, 21, 0, 0, 22, 22, 23, 23, 24, 24, 25};
- ASSERT (BankEnc < GET_SIZE_OF (ArrCodesLo));
- ASSERT (BankEnc < GET_SIZE_OF (ArrCodesHi));
- // return ArrCodes[BankEnc];
- *LowBit = ArrCodesLo[BankEnc];
- *HiBit = ArrCodesHi[BankEnc];
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function determines if the checksum is correct
- *
- * @param[in] *SPDPtr - Pointer to SPD data
- *
- * @return TRUE - CRC check passes
- * @return FALSE - CRC check fails
- */
-
-BOOLEAN
-STATIC
-MemTCRCCheck3 (
- IN OUT UINT8 *SPDPtr
- )
-{
- UINT16 Crc;
- INT16 i;
- INT16 j;
- INT16 Count;
-
- if (SPDPtr[SPD_TYPE] == JED_DDR3SDRAM) {
- Count = (SPDPtr[SPD_BYTE_USED] & 0x80) ? 117 : 126;
- Crc = 0;
- for (j = 0; j < Count; j++) {
- Crc = Crc ^ ((UINT16)SPDPtr[j] << 8);
- for (i = 0; i < 8; i++) {
- if (Crc & 0x8000) {
- Crc = (Crc << 1) ^ 0x1021;
- } else {
- Crc = (Crc << 1);
- }
- }
- }
- if (*(UINT16 *) (SPDPtr + 126) == Crc) {
- return TRUE;
- }
- }
-
- return FALSE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function returns the CAS latency of the current frequency (DCTPtr->Timings.Speed).
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return CAS Latency
- */
-
-UINT8
-STATIC
-MemTSPDGetTCL3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT8 *SpdBufferPtr;
- UINT8 CLdesired;
- UINT8 CLactual;
- UINT8 Dimm;
- UINT8 Channel;
- UINT16 CASLat;
- UINT16 Mask16;
- INT32 MTB_ps;
- INT32 FTB_ps;
- INT32 TAAmin_ps;
- INT32 TCKproposed_ps;
- INT32 Value32;
- BOOLEAN CltFail;
- MEM_NB_BLOCK *NBPtr;
- DCT_STRUCT *DCTPtr;
- CH_DEF_STRUCT *ChannelPtr;
-
- NBPtr = TechPtr->NBPtr;
- DCTPtr = NBPtr->DCTPtr;
-
- CASLat = 0xFFFF;
- TAAmin_ps = 0;
- CltFail = FALSE;
-
- for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) {
- NBPtr->SwitchChannel (NBPtr, Channel);
- ChannelPtr = NBPtr->ChannelPtr;
- for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
- if ((ChannelPtr->ChDimmValid & ((UINT8)1 << Dimm)) != 0) {
- MemTGetDimmSpdBuffer3 (TechPtr, &SpdBufferPtr, Dimm);
-
- // Step 1: Determine the common set of supported CAS Latency
- // values for all modules on the memory Channel using the CAS
- // Latencies Supported in SPD bytes 14 and 15.
- //
- CASLat &= ((UINT16)SpdBufferPtr[SPD_CASHI] << 8) | SpdBufferPtr[SPD_CASLO];
-
- // Step 2: Determine tAAmin(all) which is the largest tAAmin
- // value for all modules on the memory Channel (SPD byte 16).
- //
- MTB_ps = ((INT32) SpdBufferPtr[SPD_DIVIDENT] * 1000) / SpdBufferPtr[SPD_DIVISOR];
- FTB_ps = (SpdBufferPtr[SPD_FTB] >> 4) / (SpdBufferPtr[SPD_FTB] & 0xF);
- Value32 = (MTB_ps * SpdBufferPtr[SPD_TAA]) + (FTB_ps * (INT8) SpdBufferPtr[SPD_TAA_FTB]) ;
- if (TAAmin_ps < Value32) {
- TAAmin_ps = Value32;
- }
-
- // Step 3: Determine tCKmin(all) which is the largest tCKmin
- // value for all modules on the memory Channel (SPD byte 12).
- // * This step has been done in SPDGetTargetSpeed
- }
- }
- }
-
- TCKproposed_ps = 1000500 / DCTPtr->Timings.Speed;
-
- // Step 4: For a proposed tCK value (tCKproposed) between tCKmin(all) and tCKmax,
- // determine the desired CAS Latency. If tCKproposed is not a standard JEDEC
- // value (2.5, 1.875, 1.5, or 1.25 ns) then tCKproposed must be adjusted to the
- // next lower standard tCK value for calculating CLdesired.
- // CLdesired = ceiling ( tAAmin(all) / tCKproposed )
- // where tAAmin is defined in Byte 16. The ceiling function requires that the
- // quotient be rounded up always.
- //
- CLdesired = (UINT8) ((TAAmin_ps + TCKproposed_ps - 1) / TCKproposed_ps);
-
- // Step 5: Choose an actual CAS Latency (CLactual) that is greater than or equal
- // to CLdesired and is supported by all modules on the memory Channel as
- // determined in step 1. If no such value exists, choose a higher tCKproposed
- // value and repeat steps 4 and 5 until a solution is found.
- //
- CLactual = 4;
- for (Mask16 = 1; Mask16 < 0x8000; Mask16 <<= 1) {
- if (CASLat & Mask16) {
- if (CLdesired <= CLactual) {
- break;
- }
- }
- CLactual++;
- }
- if (Mask16 == 0x8000) {
- CltFail = TRUE;
- }
-
- // Step 6: Once the calculation of CLactual is completed, the BIOS must also
- // verify that this CAS Latency value does not exceed tAAmax, which is 20 ns
- // for all DDR3 speed grades, by multiplying CLactual times tCKproposed. If
- // not, choose a lower CL value and repeat steps 5 and 6 until a solution is found.
- //
- if ((TCKproposed_ps * CLactual) > 20000) {
- CltFail = TRUE;
- }
-
- if (!CltFail) {
- DCTPtr->Timings.CasL = CLactual;
- } else {
- // Fail to find supported Tcl, use 6 clocks since it is required for all DDR3 speed bin.
- DCTPtr->Timings.CasL = 6;
- }
-
- return DCTPtr->Timings.CasL;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function returns the encoded value of bank address.
- *
- * @param[in] Encode - RRRBCC, where CC is the number of Columns minus 9,
- * RRR is the number of Rows minus 12, and B is the number of banks
- * minus 3.
- * @param[out] *Index - index in bank address table
- * @return TRUE - encoded value is found.
- * FALSE - encoded value is not found.
- */
-
-BOOLEAN
-STATIC
-MemTCheckBankAddr3 (
- IN UINT8 Encode,
- OUT UINT8 *Index
- )
-{
- UINT8 i;
- CONST UINT8 TabBankAddr[] = {
- 0x3F, 0x01, 0x09, 0x3F, 0x3F, 0x11,
- 0x0A, 0x19, 0x12, 0x1A, 0x21, 0x22
- };
-
- for (i = 0; i < GET_SIZE_OF (TabBankAddr); i++) {
- if (Encode == TabBankAddr[i]) {
- *Index = i;
- return TRUE;
- }
- }
- return FALSE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function returns a pointer to the SPD Buffer of a specific dimm on
- * the current channel.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in,out] **SpdBuffer - Pointer to a pointer to a UINT8 Buffer
- * @param[in] Dimm - Dimm number
- *
- *
- * @return BOOLEAN - Value of DimmPresent
- * TRUE = Dimm is present, pointer is valid
- * FALSE = Dimm is not present, pointer has not been modified.
- */
-
-BOOLEAN
-MemTGetDimmSpdBuffer3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT UINT8 **SpdBuffer,
- IN UINT8 Dimm
- )
-{
- CH_DEF_STRUCT *ChannelPtr;
- SPD_DEF_STRUCT *SPDPtr;
- BOOLEAN DimmPresent;
-
- DimmPresent = FALSE;
- ChannelPtr = TechPtr->NBPtr->ChannelPtr;
- ASSERT (Dimm < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0])))
- SPDPtr = ChannelPtr->DimmSpdPtr[Dimm];
-
-
- if (SPDPtr != NULL) {
- DimmPresent = SPDPtr->DimmPresent;
- if (DimmPresent) {
- *SpdBuffer = SPDPtr->Data;
- }
- }
- return DimmPresent;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mtspd3.h
deleted file mode 100644
index 97f7683..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mtspd3.h
+++ /dev/null
@@ -1,177 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mtspd3.h
- *
- * Technology SPD support for DDR3
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR3)
- * @e \$Revision: 35415 $ @e \$Date: 2010-07-22 06:10:32 +0800 (Thu, 22 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MTSPD3_H_
-#define _MTSPD3_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*===============================================================================
- * Jedec DDR III
- *===============================================================================
- */
-#define SPD_BYTE_USED 0
-#define SPD_TYPE 2 /* SPD byte read location */
-#define JED_DDR_SDRAM 7 /* Jedec defined bit field */
-#define JED_DDR2_SDRAM 8 /* Jedec defined bit field */
-#define JED_DDR3SDRAM 0xB /* Jedec defined bit field */
-
-#define SPD_DIMM_TYPE 3
-#define SPD_ATTRIB 21
-#define JED_DIF_CK_MSK 0x20 /* Differential Clock Input */
-#define JED_RDIMM 1
-#define JED_MINIRDIMM 5
-#define JED_UDIMM 2
-#define JED_SODIMM 3
-#define JED_LRDIMM 0xB
-
-#define SPD_L_BANKS 4 /* [7:4] number of [logical] banks on each device */
-#define SPD_DENSITY 4 /* bit 3:0 */
-#define SPD_ROW_SZ 5 /* bit 5:3 */
-#define SPD_COL_SZ 5 /* bit 2:0 */
-#define SPD_RANKS 7 /* bit 5:3 */
-#define SPD_DEV_WIDTH 7 /* bit 2:0 */
-#define SPD_ECCBITS 8 /* bit 4:3 */
-#define JED_ECC 8
-#define SPD_RAWCARD 62 /* bit 2:0 */
-#define SPD_ADDRMAP 63 /* bit 0 */
-
-#define SPD_CTLWRD03 70 /* bit 7:4 */
-#define SPD_CTLWRD04 71 /* bit 3:0 */
-#define SPD_CTLWRD05 71 /* bit 7:4 */
-
-#define SPD_FTB 9
-
-#define SPD_DIVIDENT 10
-#define SPD_DIVISOR 11
-
-#define SPD_TCK 12
-#define SPD_CASLO 14
-#define SPD_CASHI 15
-#define SPD_TAA 16
-
-#define SPD_TRP 20
-#define SPD_TRRD 19
-#define SPD_TRCD 18
-#define SPD_TRAS 22
-#define SPD_TWR 17
-#define SPD_TWTR 26
-#define SPD_TRTP 27
-#define SPD_TRC 23
-#define SPD_UPPER_TRC 21 /* bit 7:4 */
-#define SPD_UPPER_TRAS 21 /* bit 3:0 */
-#define SPD_TFAW 29
-#define SPD_UPPER_TFAW 28 /* bit 3:0 */
-
-#define SPD_TCK_FTB 34
-#define SPD_TAA_FTB 35
-#define SPD_TRCD_FTB 36
-#define SPD_TRP_FTB 37
-#define SPD_TRC_FTB 38
-
-/*-----------------------------
- * Jedec DDR II related equates
- *-----------------------------
- */
-
-#define CL_DEF 4 /* Default value for failsafe operation. 4=CL 6.0 T */
-#define T_DEF 4 /* Default value for failsafe operation. 4=2.5ns (cycle time) */
-
-#define BIAS_TRTP_T 4
-#define BIAS_TRCD_T 5
-#define BIAS_TRAS_T 15
-#define BIAS_TRC_T 11
-#define BIAS_TRRD_T 4
-#define BIAS_TWR_T 4
-#define BIAS_TRP_T 5
-#define BIAS_TWTR_T 4
-#define BIAS_TFAW_T 14
-
-#define MIN_TRTP_T 4
-#define MAX_TRTP_T 7
-#define MIN_TRCD_T 5
-#define MAX_TRCD_T 12
-#define MIN_TRAS_T 15
-#define MAX_TRAS_T 30
-#define MIN_TRC_T 11
-#define MAX_TRC_T 42
-#define MIN_TRRD_T 4
-#define MAX_TRRD_T 7
-#define MIN_TWR_T 5
-#define MAX_TWR_T 12
-#define MIN_TRP_T 5
-#define MAX_TRP_T 12
-#define MIN_TWTR_T 4
-#define MAX_TWTR_T 7
-#define MIN_TFAW_T 16
-#define MAX_TFAW_T 32
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-
-#endif /* _MTSPD3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mttecc3.c b/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mttecc3.c
deleted file mode 100644
index 5f94873..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mttecc3.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mttecc3.c
- *
- * Technology ECC byte support for registered DDR3
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR3)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-#include "AGESA.h"
-#include "mm.h"
-#include "mn.h"
-#include "mu.h"
-#include "mt.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_TECH_DDR3_MTTECC3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the DQS ECC timings for registered DDR3
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemTSetDQSEccTmgsRDdr3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT8 Dct;
- UINT8 Dimm;
- UINT8 i;
- UINT8 *WrDqsDly;
- UINT16 *RcvEnDly;
- UINT8 *RdDqsDly;
- UINT8 *WrDatDly;
- UINT8 EccByte;
- INT16 TempValue;
-
- MEM_NB_BLOCK *NBPtr;
- CH_DEF_STRUCT *ChannelPtr;
-
- EccByte = TechPtr->MaxByteLanes ();
- NBPtr = TechPtr->NBPtr;
-
- if (NBPtr->MCTPtr->NodeMemSize) {
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
- ChannelPtr = NBPtr->ChannelPtr;
- for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
- if (NBPtr->DCTPtr->Timings.CsEnabled & ((UINT16)3 << (Dimm * 2))) {
- i = Dimm * TechPtr->DlyTableWidth ();
- WrDqsDly = &ChannelPtr->WrDqsDlys[i];
- RcvEnDly = &ChannelPtr->RcvEnDlys[i];
- RdDqsDly = &ChannelPtr->RdDqsDlys[i];
- WrDatDly = &ChannelPtr->WrDatDlys[i];
- // Receiver DQS Enable:
- // Receiver DQS enable for ECC bytelane = Receiver DQS enable for bytelane 3 -
- // [write DQS for bytelane 3 - write DQS for ECC]
-
- TempValue = (INT16) RcvEnDly[3] - (INT16) (WrDqsDly[3] - WrDqsDly[EccByte]);
- if (TempValue < 0) {
- TempValue = 0;
- }
- RcvEnDly[EccByte] = (UINT16) TempValue;
-
- // Read DQS:
- // Read DQS for ECC bytelane = read DQS of byte lane 3
- //
- RdDqsDly[EccByte] = RdDqsDly[3];
-
- // Write Data:
- // Write Data for ECC bytelane = Write DQS for ECC +
- // [write data for bytelane 3 - Write DQS for bytelane 3]
- TempValue = (INT16) (WrDqsDly[EccByte] + (INT8) (WrDatDly[3] - WrDqsDly[3]));
- if (TempValue < 0) {
- TempValue = 0;
- }
- WrDatDly[EccByte] = (UINT8) TempValue;
-
- NBPtr->SetTrainDly (NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Dimm, EccByte), RcvEnDly[EccByte]);
- NBPtr->SetTrainDly (NBPtr, AccessRdDqsDly, DIMM_BYTE_ACCESS (Dimm, EccByte), RdDqsDly[EccByte]);
- NBPtr->SetTrainDly (NBPtr, AccessWrDatDly, DIMM_BYTE_ACCESS (Dimm, EccByte), WrDatDly[EccByte]);
- }
- }
- }
- }
- }
- return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mttwl3.c b/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mttwl3.c
deleted file mode 100644
index 34e0927..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Tech/DDR3/mttwl3.c
+++ /dev/null
@@ -1,686 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mttwl3.c
- *
- * Technology Phy assisted write levelization for DDR3
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR3)
- * @e \$Revision: 38442 $ @e \$Date: 2010-09-24 06:39:57 +0800 (Fri, 24 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "mu.h"
-#include "mt.h"
-#include "mtsdi3.h"
-#include "merrhdl.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-#include "mtlrdimm3.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_TECH_DDR3_MTTWL3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-STATIC
-MemTWriteLevelizationHw3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Pass
- );
-
-VOID
-STATIC
-MemTWLPerDimmHw3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Dimm,
- IN UINT8 Pass
- );
-
-VOID
-STATIC
-MemTPrepareDIMMs3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 TargetDIMM,
- IN BOOLEAN Wl
- );
-
-VOID
-STATIC
-MemTProcConfig3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Dimm,
- IN UINT8 Pass
- );
-
-VOID
-STATIC
-MemTBeginWLTrain3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Dimm
- );
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function executes first pass of Phy assisted write levelization
- * for a specific node (DDR800).
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemTWriteLevelizationHw3Pass1 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- return MemTWriteLevelizationHw3 (TechPtr, 1);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function executes second pass of Phy assisted write levelization
- * for a specific node (DDR1066 and above).
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemTWriteLevelizationHw3Pass2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- // If current speed is higher than start-up speed, do second pass of WL
- if (TechPtr->NBPtr->DCTPtr->Timings.Speed > TechPtr->NBPtr->StartupSpeed) {
- return MemTWriteLevelizationHw3 (TechPtr, 2);
- }
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function prepares for Phy assisted training.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemTPreparePhyAssistedTraining (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- // Disable auto refresh by configuring F2x[1, 0]8C[DisAutoRefresh] = 1.
- TechPtr->NBPtr->BrdcstSet (TechPtr->NBPtr, BFDisAutoRefresh, 1);
- // Disable ZQ calibration short command by configuring F2x[1, 0]94[ZqcsInterval] = 00b.
- TechPtr->NBPtr->BrdcstSet (TechPtr->NBPtr, BFZqcsInterval, 0);
- return (BOOLEAN) (TechPtr->NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function revert to normal settings when exiting from Phy assisted training.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemTExitPhyAssistedTraining (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- MEM_NB_BLOCK *NBPtr;
- NBPtr = TechPtr->NBPtr;
-
- // 13.Program F2x[1, 0]8C[DisAutoRefresh] = 0.
- NBPtr->BrdcstSet (NBPtr, BFDisAutoRefresh, 0);
- // 14.Program F2x[1, 0]94[ZqcsInterval] to the proper interval for the current memory configuration.
- NBPtr->BrdcstSet (NBPtr, BFZqcsInterval, 2);
- NBPtr->FamilySpecificHook[ExitPhyAssistedTraining] (NBPtr, NBPtr);
-
- return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function executed hardware based write levelization for a specific die
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] Pass - Pass number (1 (400Mhz) or 2 (>400Mhz))
- *
- * @pre Auto refresh and ZQCL must be disabled
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-STATIC
-MemTWriteLevelizationHw3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Pass
- )
-{
- MEM_NB_BLOCK *NBPtr;
- DCT_STRUCT *DCTPtr;
- UINT8 Dct;
- UINT8 Dimm;
-
- NBPtr = TechPtr->NBPtr;
-
- IDS_HDT_CONSOLE (MEM_STATUS, "\nStart write leveling\n");
- AGESA_TESTPOINT (TpProcMemWriteLevelizationTraining, &(NBPtr->MemPtr->StdHeader));
- // Begin DQS Write timing training
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct);
- DCTPtr = NBPtr->DCTPtr;
-
- TechPtr->WLCriticalDelay = 0x00;
-
- //training for each Dimm
- for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
- if ((DCTPtr->Timings.CsEnabled & ((UINT16)3 << (Dimm << 1))) != 0) {
- if (!(NBPtr->MCTPtr->Status[SbLrdimms]) || ((NBPtr->ChannelPtr->LrDimmPresent & ((UINT8) 1 << Dimm)) != 0)) {
- IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", Dimm << 1);
- MemTWLPerDimmHw3 (TechPtr, Dimm, Pass);
- }
- }
- }
-
- NBPtr->FamilySpecificHook[CalcWrDqDqsEarly] (NBPtr, NULL);
- }
- IDS_HDT_CONSOLE (MEM_FLOW, "End write leveling\n\n");
- return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initializes per DIMM write levelization
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] Dimm - DIMM to be trained
- * @param[in] Pass - Pass number (1 (400Mhz) or 2 (>400Mhz))
- *
- */
-
-VOID
-STATIC
-MemTWLPerDimmHw3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Dimm,
- IN UINT8 Pass
- )
-{
- MEM_DATA_STRUCT *MemPtr;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
- MemPtr = NBPtr->MemPtr;
-
- ASSERT (Dimm < MAX_DIMMS_PER_CHANNEL);
-
- // 1. A. Specify the target Dimm that is to be trained by programming
- // F2x[1, 0]9C_x08[TrDimmSel].
- NBPtr->SetBitField (NBPtr, BFTrDimmSel, Dimm);
-
- TechPtr->TargetDIMM = Dimm;
- NBPtr->FamilySpecificHook[InitPerNibbleTrn] (NBPtr, NULL);
- for (TechPtr->TrnNibble = NIBBLE_0; TechPtr->TrnNibble <= (NBPtr->FamilySpecificHook[TrainWlPerNibble] (NBPtr, &Dimm)? NIBBLE_0 : NIBBLE_1); TechPtr->TrnNibble++) {
- // 2. Prepare the DIMMs for write levelization using DDR3-defined
- // MR commands.
- MemTPrepareDIMMs3 (TechPtr, Dimm, TRUE);
-
- // 3. After the DIMMs are configured, BIOS waits 40 MEMCLKs to
- // satisfy DDR3-defined internal DRAM timing.
- NBPtr->WaitXMemClks (NBPtr, 40);
-
- // 4. Configure the processor's DDR phy for write levelization training:
- MemTProcConfig3 (TechPtr, Dimm, Pass);
-
- // 5. Begin write levelization training
- MemTBeginWLTrain3 (TechPtr, Dimm);
- }
- // 7. Program the target Dimm back to normal operation
- MemTPrepareDIMMs3 (TechPtr, Dimm, FALSE);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function prepares the DIMMS for Write Levelization
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] TargetDIMM - DIMM to be trained
- * @param[in] Wl - Indicates if WL mode should be enabled
- *
- */
-
-VOID
-STATIC
-MemTPrepareDIMMs3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 TargetDIMM,
- IN BOOLEAN Wl
- )
-{
- MEM_NB_BLOCK *NBPtr;
- UINT8 ChipSel;
-
- NBPtr = TechPtr->NBPtr;
-
- AGESA_TESTPOINT (TpProcMemWlPrepDimms, &(NBPtr->MemPtr->StdHeader));
- ASSERT (TargetDIMM < MAX_DIMMS_PER_CHANNEL);
- TechPtr->TargetDIMM = TargetDIMM;
- if (!(TechPtr->TechnologySpecificHook[WlTrainingPrepareLrdimm] (TechPtr, &Wl))) {
- for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) {
- if ((NBPtr->DCTPtr->Timings.CsPresent & ((UINT16)1 << ChipSel)) != 0) {
- if (Wl) {
- // Program WrLvOdt
- NBPtr->SetBitField (NBPtr, BFWrLvOdt, NBPtr->ChannelPtr->PhyWLODT[ChipSel >> 1]);
- }
- NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel);
- // Set MR1 to F2x7C[MrsAddress], F2x7C[MrsBank]=1
- MemTEMRS13 (TechPtr, Wl, TargetDIMM);
- NBPtr->SendMrsCmd (NBPtr);
- // Set MR2 to F2x7C[MrsAddress], F2x7C[MrsBank]=1
- MemTEMRS23 (TechPtr);
- // Send command
- NBPtr->SendMrsCmd (NBPtr);
- }
- }
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function programs seed values for Write Levelization
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] Dimm - DIMM to be trained
- * @param[in] Pass - Pass for WL training (1 - 400Mhz or 2 - >400Mhz)
- *
- */
-
-VOID
-STATIC
-MemTProcConfig3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Dimm,
- IN UINT8 Pass
- )
-{
- DIE_STRUCT *MCTPtr;
- CH_DEF_STRUCT *ChannelPtr;
- MEM_NB_BLOCK *NBPtr;
- UINT16 WrDqsDly;
- // Memclk Delay incurred by register.
- UINT8 MemClkRegDly;
- UINT8 ByteLane;
- UINT8 DefaultSeed;
- UINT8 CurrentSeed;
- UINT8 *Seed;
- UINT8 RCW2;
- UINT16 Speed;
-
- NBPtr = TechPtr->NBPtr;
- MCTPtr = NBPtr->MCTPtr;
- ChannelPtr = TechPtr->NBPtr->ChannelPtr;
-
- AGESA_TESTPOINT (TpProcMemWlConfigDimms, &(NBPtr->MemPtr->StdHeader));
- RCW2 = ChannelPtr->CtrlWrd02[Dimm];
- Speed = TechPtr->NBPtr->DCTPtr->Timings.Speed;
-
- IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t Byte: 00 01 02 03 04 05 06 07 ECC\n");
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tSeeds: ");
- // Program an initialization Value to registers F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52 to set
- // the gross and fine delay for all the byte lane fields. If the target frequency is different than 400MHz,
- // BIOS must execute two training passes for each Dimm. For pass 1 at a 400MHz MEMCLK frequency,
- // use an initial total delay value.
- if (Pass == 1) {
- //
- // Get the default value of seed
- //
- if (MCTPtr->Status[SbRegistered]) {
- //
- // RDIMM
- //
- if (Speed == DDR667_FREQUENCY) {
- DefaultSeed = ((RCW2 & BIT0) == 0) ? 0x3B : 0x4B;
- } else {
- DefaultSeed = ((RCW2 & BIT0) == 0) ? 0x41 : 0x51;
- }
- } else if (ChannelPtr->SODimmPresent != 0) {
- //
- // SODIMMM
- //
- DefaultSeed = 0x12;
- } else if (MCTPtr->Status[SbLrdimms]) {
- //
- // LRDIMM
- //
- DefaultSeed = 0x0;
- } else {
- //
- // UDIMMM
- //
- DefaultSeed = 0x1A;
- }
-
- ASSERT (Speed >= DDR667_FREQUENCY);
-
- // Get platform override seed
- Seed = (UINT8 *) FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_WL_SEED, MCTPtr->SocketId, ChannelPtr->ChannelID);
-
- for (ByteLane = 0; ByteLane < TechPtr->DlyTableWidth (); ByteLane++) {
- // This includes ECC as byte 8
- CurrentSeed = ((Seed != NULL) ? Seed[ByteLane] : DefaultSeed);
- ChannelPtr->WrDqsDlys[Dimm * TechPtr->DlyTableWidth () + ByteLane] = CurrentSeed;
-
- if (NBPtr->IsSupported[WLSeedAdjust]) {
- if ((CurrentSeed & 0x20) != 0) {
- // If (SeedGross is odd) then SeedPreGross = 1
- CurrentSeed = (CurrentSeed & 0x1F) | 0x20;
- } else {
- // If (SeedGross is even) then SeedPreGross = 2
- CurrentSeed = (CurrentSeed & 0x1F) | 0x40;
- }
- }
-
- NBPtr->SetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), CurrentSeed);
- IDS_HDT_CONSOLE (MEM_FLOW, "%02x ", CurrentSeed);
- }
- } else {
- //10.Multiply the previously saved delay values in Pass 1, step #5 by (target frequency)/400 to find
- //the gross and fine delay initialization values at the target frequency. Use these values as the initial
- //seed values when executing Pass 2, step #4.
- for (ByteLane = 0; ByteLane < TechPtr->DlyTableWidth (); ByteLane++) {
- // This includes ECC as byte 8
- WrDqsDly = ChannelPtr->WrDqsDlys[Dimm * TechPtr->DlyTableWidth () + ByteLane];
- TechPtr->Bytelane = ByteLane;
- NBPtr->FamilySpecificHook[TrainWlPerNibbleSeed] (NBPtr, &WrDqsDly);
- //
- // For Registered Dimms
- //
- if (MCTPtr->Status[SbRegistered]) {
- MemClkRegDly = ((RCW2 & BIT0) == 0) ? 0x20 : 0x30;
- WrDqsDly = (UINT16) (MemClkRegDly + ((((UINT32) WrDqsDly - MemClkRegDly) * Speed) / TechPtr->PrevSpeed));
- } else {
- //
- // Unbuffered Dimms and LRDIMMs
- //
- WrDqsDly = (UINT16) (((UINT32) WrDqsDly * Speed) / TechPtr->PrevSpeed);
- }
-
- ChannelPtr->WrDqsDlys[Dimm * TechPtr->DlyTableWidth () + ByteLane] = (UINT8) WrDqsDly;
-
- if (NBPtr->IsSupported[WLSeedAdjust]) {
- if ((WrDqsDly & 0x20) != 0) {
- // If (SeedGross is odd) then SeedPreGross = 1
- WrDqsDly = (WrDqsDly & 0x1F) | 0x20;
- } else {
- // If (SeedGross is even) then SeedPreGross = 2
- WrDqsDly = (WrDqsDly & 0x1F) | 0x40;
- }
- }
- NBPtr->SetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), WrDqsDly);
- IDS_HDT_CONSOLE (MEM_FLOW, "%02x ", WrDqsDly);
- }
- }
- IDS_HDT_CONSOLE (MEM_FLOW, "\n");
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function begins WL training for a specific DIMM
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] Dimm - DIMM to be trained
- *
- */
-
-VOID
-STATIC
-MemTBeginWLTrain3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Dimm
- )
-{
- MEM_DATA_STRUCT *MemPtr;
- DIE_STRUCT *MCTPtr;
- MEM_NB_BLOCK *NBPtr;
- UINT8 ByteLane;
- UINT8 Seed;
- UINT8 Delay;
-
- NBPtr = TechPtr->NBPtr;
- MemPtr = NBPtr->MemPtr;
- MCTPtr = NBPtr->MCTPtr;
- // Assert ODT pins for write leveling
- NBPtr->SetBitField (NBPtr, BFWrLvOdtEn, 1);
-
- // Wait 10 MEMCLKs to allow for ODT signal settling.
- NBPtr->WaitXMemClks (NBPtr, 10);
-
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tWrtLvTrEn = 1\n");
- // Program F2x[1, 0]9C_x08[WrtLlTrEn]=1.
- NBPtr->SetBitField (NBPtr, BFWrtLvTrEn, 1);
-
- // Wait 200 MEMCLKs.
- NBPtr->WaitXMemClks (NBPtr, 200);
-
- // Program F2x[1, 0]9C_x08[WrtLlTrEn]=0.
- NBPtr->SetBitField (NBPtr, BFWrtLvTrEn, 0);
-
- // Read from registers F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52 to get the gross and fine Delay settings
- // for the target Dimm and save these values.
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t PRE: ");
- for (ByteLane = 0; ByteLane < (MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) {
- // This includes ECC as byte 8
- Seed = NBPtr->ChannelPtr->WrDqsDlys[(Dimm * TechPtr->DlyTableWidth ()) + ByteLane];
- Delay = (UINT8)NBPtr->GetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (Dimm, ByteLane));
- IDS_HDT_CONSOLE (MEM_FLOW, "%02x ", Delay);
-
- if (NBPtr->IsSupported[WLSeedAdjust]) {
- // Recover WrDqsGrossDly:
- // WrDqsGrossDly = SeedGross + PhRecGrossDlyByte - SeedPreGross
- if ((Seed & 0x20) != 0) {
- // If (SeedGross is odd) then SeedPreGross = 1
- Delay += (Seed & 0xE0) - 0x20;
- } else {
- // If (SeedGross is even) then SeedPreGross = 2
- if (((Seed & 0xE0) == 0) && (Delay < 0x40)) {
- // If SeedGross is 0 and PhRecGrossDlyByte is less than SeedPreGross,
- // we have a negative result and need to program the delay to 0
- if (NBPtr->IsSupported[WLNegativeDelay]) {
- //
- // Save the lowest negative delay value across all Dimms and Bytelanes
- //
- TechPtr->WLCriticalDelay = MIN (TechPtr->WLCriticalDelay, (INT16)Delay - 0x40);
- Delay -= 0x40;
- } else {
- Delay = 0;
- }
- } else {
- Delay += (Seed & 0xE0) - 0x40;
- }
- }
- } else if (((Seed >> 5) == 0) && ((Delay >> 5) == 3)) {
- IDS_OPTION_HOOK (IDS_CHECK_NEGATIVE_WL, &Delay, &(TechPtr->NBPtr->MemPtr->StdHeader));
- // If seed has gross delay of 0 and PRE has gross delay of 3,
- // then round the total delay of TxDqs to 0.
- Delay = 0;
- }
-
- if ((Delay > (Seed + 0x20)) || (Seed > (Delay + 0x20))) {
- //
- // If PRE comes back with more than Seed +/- 0x20, then this is an
- // unexpected condition. Log the condition.
- //
- PutEventLog (AGESA_ERROR, MEM_ERROR_WL_PRE_OUT_OF_RANGE, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, ((Seed << 8) + Delay), &NBPtr->MemPtr->StdHeader);
- }
-
- TechPtr->Bytelane = ByteLane;
- TechPtr->TargetDIMM = Dimm;
- NBPtr->FamilySpecificHook[TrainWlPerNibbleAdjustWLDly] (NBPtr, &Delay);
- NBPtr->SetTrainDly (NBPtr, AccessWrDqsDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), Delay);
- NBPtr->ChannelPtr->WrDqsDlys[(Dimm * TechPtr->DlyTableWidth ()) + ByteLane] = Delay;
- }
-
- IDS_HDT_CONSOLE_DEBUG_CODE (
- IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\tWrDqs: ");
- for (ByteLane = 0; ByteLane < (MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) {
- IDS_HDT_CONSOLE (MEM_FLOW, "%02x ", NBPtr->ChannelPtr->WrDqsDlys[(Dimm * TechPtr->DlyTableWidth ()) + ByteLane]);
- }
- IDS_HDT_CONSOLE (MEM_FLOW, "\n\n");
- );
-
- // Disable write leveling ODT pins
- NBPtr->SetBitField (NBPtr, BFWrLvOdtEn, 0);
-
- // Wait 10 MEMCLKs to allow for ODT signal settling.
- NBPtr->WaitXMemClks (NBPtr, 10);
-
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function programs register after Phy assisted training is finish.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemTExitPhyAssistedTrainingClient3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- MEM_NB_BLOCK *NBPtr;
- UINT8 Dct;
- UINT8 ChipSel;
- NBPtr = TechPtr->NBPtr;
-
- NBPtr->FamilySpecificHook[ReEnablePhyComp] (NBPtr, NBPtr);
- NBPtr->BrdcstSet (NBPtr, BFRxPtrInitReq, 1);
- NBPtr->PollBitField (NBPtr, BFRxPtrInitReq, 0, PCI_ACCESS_TIMEOUT, TRUE);
- NBPtr->BrdcstSet (NBPtr, BFDisDllShutdownSR, 1);
- NBPtr->BrdcstSet (NBPtr, BFEnterSelfRef, 1);
- NBPtr->PollBitField (NBPtr, BFEnterSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE);
- IDS_HDT_CONSOLE (MEM_FLOW, "\tMemClkAlign = 2\n");
- NBPtr->BrdcstSet (NBPtr, BFDbeGskMemClkAlignMode, 2);
- NBPtr->BrdcstSet (NBPtr, BFExitSelfRef, 1);
- NBPtr->PollBitField (NBPtr, BFExitSelfRef, 0, PCI_ACCESS_TIMEOUT, TRUE);
- NBPtr->BrdcstSet (NBPtr, BFDisDllShutdownSR, 0);
-
- // Calculate Max Latency for both channels to prepare for position training
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct);
- NBPtr->SwitchDCT (NBPtr, Dct);
- if (TechPtr->FindMaxDlyForMaxRdLat (TechPtr, &ChipSel)) {
- NBPtr->SetMaxLatency (NBPtr, TechPtr->MaxDlyForMaxRdLat);
- }
- }
- return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Tech/mt.c b/src/vendorcode/amd/agesa/Proc/Mem/Tech/mt.c
deleted file mode 100644
index 70fa039..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Tech/mt.c
+++ /dev/null
@@ -1,264 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mt.c
- *
- * Common Technology file
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech)
- * @e \$Revision: 36981 $ @e \$Date: 2010-08-27 23:21:43 +0800 (Fri, 27 Aug 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "mport.h"
-#include "mm.h"
-#include "mn.h"
-#include "mu.h"
-#include "mt.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_TECH_MT_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemTDefaultTechnologyHook (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT VOID *OptParam
- );
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function is the default return for non-training technology features
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- */
-BOOLEAN
-MemTFeatDef (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the TestFail bit for all CS that fail training.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- */
-VOID
-MemTMarkTrainFail (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- MEM_NB_BLOCK *NBPtr;
- UINT8 Dct;
- UINT8 ChipSel;
-
- NBPtr = TechPtr->NBPtr;
- for (Dct = 0; Dct < NBPtr->DctCount; Dct ++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- NBPtr->DCTPtr->Timings.CsEnabled &= ~NBPtr->DCTPtr->Timings.CsTrainFail;
- for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel ++) {
- if ((NBPtr->DCTPtr->Timings.CsTrainFail & ((UINT16)1 << ChipSel)) != 0) {
- NBPtr->SetBitField (NBPtr, (BFCSBaseAddr0Reg + ChipSel), (UINT32)1 << BFTestFail);
- }
- }
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the initial controller environment before training.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-VOID
-MemTBeginTraining (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- S_UINT64 SMsr;
- MEM_DATA_STRUCT *MemPtr;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
- MemPtr = NBPtr->MemPtr;
-
- LibAmdReadCpuReg (CR4_REG, &TechPtr->CR4reg);
- LibAmdWriteCpuReg (CR4_REG, TechPtr->CR4reg | ((UINT32)1 << 9)); // enable SSE2
-
- LibAmdMsrRead (HWCR, (UINT64 *) (&SMsr), &MemPtr->StdHeader); // HWCR
- TechPtr->HwcrLo = SMsr.lo;
- SMsr.lo |= 0x00020000; // turn on HWCR.wrap32dis
- SMsr.lo &= 0xFFFF7FFF; // turn off HWCR.SSEDIS
- LibAmdMsrWrite (HWCR, (UINT64 *) (&SMsr), &MemPtr->StdHeader);
-
- TechPtr->DramEcc = (UINT8) NBPtr->GetBitField (NBPtr, BFDramEccEn);
- NBPtr->SetBitField (NBPtr, BFDramEccEn, 0); // Disable ECC
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the final controller environment after training.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-VOID
-MemTEndTraining (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- S_UINT64 SMsr;
- MEM_DATA_STRUCT *MemPtr;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
- MemPtr = NBPtr->MemPtr;
-
- LibAmdWriteCpuReg (CR4_REG, TechPtr->CR4reg);
-
- LibAmdMsrRead (HWCR, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- SMsr.lo = TechPtr->HwcrLo;
- LibAmdMsrWrite (HWCR, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-
- NBPtr->SetBitField (NBPtr, BFDramEccEn, TechPtr->DramEcc);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets all the bytelanes/nibbles to the same delay value
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] Dly - Delay value to set
- *
- */
-
-VOID
-MemTSetDQSDelayAllCSR (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Dly
- )
-{
- UINT8 i;
- UINT8 MaxBytelanes;
- MaxBytelanes = (TechPtr->NBPtr->MCTPtr->Status[SbEccDimms] && TechPtr->NBPtr->IsSupported[EccByteTraining]) ? 9 : 8;
-
- for (i = 0; i < MaxBytelanes; i++) {
- TechPtr->SetDQSDelayCSR (TechPtr, i, Dly);
- }
-}
-/*-----------------------------------------------------------------------------
- *
- *
- * This function is used to intialize common technology functions
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * ----------------------------------------------------------------------------
- */
-VOID
-MemTCommonTechInit (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT8 i;
- for (i = 0; i < NumberOfTechHooks; i++) {
- TechPtr->TechnologySpecificHook[i] = MemTDefaultTechnologyHook;
- }
-}
-/*-----------------------------------------------------------------------------
- *
- *
- * This function is an empty function used to intialize TechnologySpecificHook array
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] OptParam - Optional parameter
- *
- * @return FALSE - always
- * ----------------------------------------------------------------------------
- */
-BOOLEAN
-STATIC
-MemTDefaultTechnologyHook (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT VOID *OptParam
- )
-{
- return FALSE;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Tech/mthdi.c b/src/vendorcode/amd/agesa/Proc/Mem/Tech/mthdi.c
deleted file mode 100644
index 0a95b9b..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Tech/mthdi.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mthdi.c
- *
- * Common technology hardware dram init support functions
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "mu.h"
-#include "mt.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_TECH_MTHDI_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initiates Hardware based dram initialization for both DCTs
- * at the same time.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-VOID
-MemTDramInitHw (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT8 Dct;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
-
- NBPtr->BrdcstSet (NBPtr, BFInitDram, 1);
- // Phy fence training
- AGESA_TESTPOINT (TpProcMemPhyFenceTraining, &(NBPtr->MemPtr->StdHeader));
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
- IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct);
- NBPtr->PhyFenceTraining (NBPtr);
- }
- }
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Tech/mttEdgeDetect.c b/src/vendorcode/amd/agesa/Proc/Mem/Tech/mttEdgeDetect.c
deleted file mode 100644
index f87ebb1..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Tech/mttEdgeDetect.c
+++ /dev/null
@@ -1,896 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mttEdgeDetect.c
- *
- * DQS R/W position training utilizing Data Eye Edge Detection for optimization
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech)
- * @e \$Revision: 37555 $ @e \$Date: 2010-09-08 02:17:18 +0800 (Wed, 08 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "AdvancedApi.h"
-#include "GeneralServices.h"
-#include "Ids.h"
-#include "heapManager.h"
-#include "mm.h"
-#include "mn.h"
-#include "mu.h"
-#include "mt.h"
-#include "mport.h"
-#include "mttEdgeDetect.h"
-#include "merrhdl.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_TECH_MTTEDGEDETECT_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-
-#define LAST_DELAY (-128)
-#define INC_DELAY 1
-#define DEC_DELAY 0
-
-
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/**
- * Sweep Table For Byte Training without insertion delay
- *
-*/
-DQS_POS_SWEEP_TABLE SweepTableByte[] =
-{
- // Begin End Inc/Dec Step EndResult Edge
- { 0x00, 0x1F, INC_DELAY, 4, 0xFFFF, LEFT_EDGE}, /// For Left Edge, start from 0 and Increment to 0x1F by 4 until all PASS
- { LAST_DELAY, 0x00, DEC_DELAY, -1, 0xFE00, LEFT_EDGE}, /// Then go back down to 0x00 by 1 until all FAIL
- { 0x1F, 0x00, DEC_DELAY, -4, 0xFFFF, RIGHT_EDGE}, /// For Right Edge, start from 0x1F down to 0 until all PASS.
- { LAST_DELAY, 0x1F, INC_DELAY, 1, 0xFE00, RIGHT_EDGE} /// Then go back up by 1 until all FAIL.
-};
-/**
- * Sweep Table For Byte Training with insertion delay
- *
-*/
-DQS_POS_SWEEP_TABLE InsSweepTableByte[] =
-{
- // Begin End Inc/Dec Step EndResult Edge
- { 0x00, -0x20, DEC_DELAY, -4, 0xFE00, LEFT_EDGE}, /// For Left Edge, start from 0 and Decrement to -0x20 by -4 until all FAIL
- { LAST_DELAY, 0x1F, INC_DELAY, 1, 0xFFFF, LEFT_EDGE}, /// Then go back up to 0x1F by 1 until all PASS
- { 0x1F, 0x00, DEC_DELAY, -4, 0xFFFF, RIGHT_EDGE}, /// For Right Edge, start from 0x1F down to 0 until all PASS.
- { LAST_DELAY, 0x1F, INC_DELAY, 1, 0xFE00, RIGHT_EDGE} /// Then go back up by 1 until all FAIL.
-};
-
-BOOLEAN
-STATIC
-MemTTrainDQSRdWrEdgeDetect (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-STATIC
-MemTTrainDQSEdgeDetect (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-STATIC
-MemTInitTestPatternAddress (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT SWEEP_INFO *SweepPtr
- );
-
-BOOLEAN
-STATIC
-MemTContinueSweep (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT SWEEP_INFO *SweepPtr
- );
-
-BOOLEAN
-STATIC
-MemTSetNextDelay (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT SWEEP_INFO *SweepPtr
- );
-
-UINT8
-STATIC
-MemTScaleDelayVal (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN INT8 Delay
- );
-
-VOID
-STATIC
-MemTDataEyeSave (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT SWEEP_INFO *SweepPtr,
- IN UINT8 ByteLane
- );
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function executes DQS position training for all a Memory channel using
- * the Edge Detection algorithm.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-BOOLEAN
-MemTTrainDQSEdgeDetectSw (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- MEM_NB_BLOCK *NBPtr;
- BOOLEAN Status;
-
- Status = FALSE;
- NBPtr = TechPtr->NBPtr;
- TechPtr->TrainingType = TRN_DQS_POSITION;
- //
- // Initialize the Pattern
- //
- if (AGESA_SUCCESS == NBPtr->TrainingPatternInit (NBPtr)) {
- //
- // Setup hardware training engine (if applicable)
- //
- NBPtr->FamilySpecificHook[SetupHwTrainingEngine] (NBPtr, &TechPtr->TrainingType);
- //
- // Start Edge Detection
- //
- Status |= MemTTrainDQSRdWrEdgeDetect (TechPtr);
- //
- // Finalize the Pattern
- //
- Status &= (AGESA_SUCCESS == NBPtr->TrainingPatternFinalize (NBPtr));
- }
- return Status;
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This Executes Read DQS and Write Data Position training on a chip select pair
- * using the Edge Detection algorithm.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - No Errors occurred
- * @return FALSE - Errors occurred
-
- */
-
-BOOLEAN
-STATIC
-MemTTrainDQSRdWrEdgeDetect (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- MEM_DATA_STRUCT *MemPtr;
- MEM_NB_BLOCK *NBPtr;
- UINT8 WrDqDelay;
- UINT8 Dct;
- UINT8 CSPerChannel;
- UINT8 CsPerDelay;
- UINT8 ChipSel;
- UINT8 i;
- BOOLEAN Status;
- UINT8 TimesFail;
- UINT8 TimesRetrain;
-
- NBPtr = TechPtr->NBPtr;
- MemPtr = NBPtr->MemPtr;
- TimesRetrain = DEFAULT_TRAINING_TIMES;
- IDS_OPTION_HOOK (IDS_MEM_RETRAIN_TIMES, &TimesRetrain, &MemPtr->StdHeader);
- //
- // Set environment settings before training
- //
- IDS_HDT_CONSOLE (MEM_STATUS, "\nStart Read/Write Data Eye Edge Detection.\n");
- MemTBeginTraining (TechPtr);
- //
- // Do Rd DQS /Wr Data Position training for all Dcts/Chipselects
- //
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct);
- NBPtr->SwitchDCT (NBPtr, Dct);
- //
- // Chip Select Loop
- //
- CSPerChannel = NBPtr->CSPerChannel (NBPtr);
- CsPerDelay = NBPtr->CSPerDelay (NBPtr);
- for (ChipSel = 0; ChipSel < CSPerChannel; ChipSel = ChipSel + CsPerDelay ) {
- //
- // Init Bit Error Masks
- //
- LibAmdMemFill (&NBPtr->ChannelPtr->FailingBitMask[ (ChipSel * MAX_BYTELANES_PER_CHANNEL) ],
- 0xFF,
- (MAX_BYTELANES_PER_CHANNEL * CsPerDelay),
- &MemPtr->StdHeader);
- if ((NBPtr->DCTPtr->Timings.CsEnabled & ((UINT16) 1 << ChipSel)) != 0) {
- TechPtr->ChipSel = ChipSel;
- IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", ChipSel);
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tIncrease WrDat, Train RdDqs:\n");
-
- TechPtr->DqsRdWrPosSaved = 0;
- //
- // Use a list of Approximate Write Data delay values and train Read DQS Position for
- // each until a valid Data eye is found.
- //
- Status = FALSE;
- TimesFail = 0;
- ERROR_HANDLE_RETRAIN_BEGIN (TimesFail, TimesRetrain) {
- i = 0;
- while (NBPtr->GetApproximateWriteDatDelay (NBPtr, i, &WrDqDelay)) {
- TechPtr->SmallDqsPosWindow = FALSE;
- //
- // Set Write Delay approximation
- //
- TechPtr->Direction = DQS_WRITE_DIR;
- IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\tWrite Delay: %02x", WrDqDelay);
- MemTSetDQSDelayAllCSR (TechPtr, WrDqDelay);
- //
- // Attempt Read Training
- //
- TechPtr->Direction = DQS_READ_DIR;
- if (MemTTrainDQSEdgeDetect (TechPtr)) {
- //
- // If Read DQS Training was successful, Train Write Data (DQ) Position
- //
- TechPtr->DqsRdWrPosSaved = 0;
- IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\tTrain WrDat:\n\n");
- TechPtr->Direction = DQS_WRITE_DIR;
- Status = MemTTrainDQSEdgeDetect (TechPtr);
- break;
- }
- i++;
- }
- ERROR_HANDLE_RETRAIN_END ((Status == FALSE), TimesFail)
- }
- //
- // If we went through the table, Fail.
- //
- if (Status == FALSE) {
- // On training failure, check and record whether training fails due to small window or no window
- if (TechPtr->SmallDqsPosWindow) {
- NBPtr->MCTPtr->ErrStatus[EsbSmallDqs] = TRUE;
- } else {
- NBPtr->MCTPtr->ErrStatus[EsbNoDqsPos] = TRUE;
- }
-
- SetMemError (AGESA_ERROR, NBPtr->MCTPtr);
- if (TechPtr->Direction == DQS_READ_DIR) {
- PutEventLog (AGESA_ERROR, MEM_ERROR_NO_DQS_POS_RD_WINDOW, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- } else {
- PutEventLog (AGESA_ERROR, MEM_ERROR_NO_DQS_POS_WR_WINDOW, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- }
- NBPtr->DCTPtr->Timings.CsTrainFail |= (UINT16)1 << ChipSel;
- // If the even chip select failed training always fail the odd, if present.
- if ((ChipSel & 0x01) == 0) {
- if (NBPtr->DCTPtr->Timings.CsPresent & ((UINT16)1 << (ChipSel + 1))) {
- NBPtr->DCTPtr->Timings.CsTrainFail |= (UINT16)1 << (ChipSel + 1);
- }
- }
- NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, NBPtr->DCTPtr->Timings.CsTrainFail, &NBPtr->MemPtr->StdHeader);
- }
- } else {
- //
- // Clear Bit Error Masks if these CS will not be trained.
- //
- LibAmdMemFill (&NBPtr->ChannelPtr->FailingBitMask[ (ChipSel * MAX_BYTELANES_PER_CHANNEL) ],
- 0x00,
- (MAX_BYTELANES_PER_CHANNEL * CsPerDelay),
- &NBPtr->MemPtr->StdHeader);
- }
- }
- }
- //
- // Restore environment settings after training
- //
- MemTEndTraining (TechPtr);
- IDS_HDT_CONSOLE (MEM_FLOW, "End Read/Write Data Eye Edge Detection\n\n");
- return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function executes DQS position training for both read and write, using
- * the Edge Detection Algorithm. This method searches for the beginning and end
- * of the Data Eye with out scanning every DSQ delay value. The following is a
- * detailed description of the algorithm:
- *
- * Four-Stage Data Eye Sweep
- *
- * -Search starts at Delay value of 0.
- * -Search left in steps of 4/32UI looking for all Byte lanes Passing. Left from zero rolls over to a negative value.
- * -Negative values are translated to the high end of the delay range, but using Insertion delay comparison.
- * -For each passing byte lane, freeze delay at first passing value, but set mask so next steps will not compare for byte lanes that previously passed
- * -Switch to search right in steps of 1/32UI looking for fail.
- * -For each lane, starting delay for 1/32 sweep right is first passing delay from 4/32 sweep left.
- * -For each failing byte lane, freeze delay at first failing value, but set mask so next steps will not compare for byte lanes that previously failed
- * -Search right until all byte lanes have failed
- * -For each lane, right edge used by BIOS will be first failing delay value minus 1/32
-
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - All bytelanes pass
- * @return FALSE - Some bytelanes fail
-*/
-BOOLEAN
-STATIC
-MemTTrainDQSEdgeDetect (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- MEM_NB_BLOCK *NBPtr;
- DIE_STRUCT *MCTPtr;
- DQS_POS_SWEEP_TABLE *SweepTablePtr;
- UINT8 SweepTableSize;
- SWEEP_INFO SweepData;
- BOOLEAN Status;
- UINT16 CurrentResult;
- UINT16 AlignedResult;
- UINT16 OffsetResult;
- UINT8 StageIndex;
- UINT8 CsIndex;
- UINT8 CsPerDelay;
- UINT8 i;
-
- Status = TRUE;
- //
- // Initialize Object Pointers
- //
- NBPtr = TechPtr->NBPtr;
- MCTPtr = NBPtr->MCTPtr;
- //
- /// Get Pointer to Sweep Table
- //
- if (TechPtr->Direction == DQS_READ_DIR) {
- SweepTablePtr = InsSweepTableByte;
- SweepTableSize = GET_SIZE_OF (InsSweepTableByte);
- } else {
- SweepTablePtr = SweepTableByte;
- SweepTableSize = GET_SIZE_OF (SweepTableByte);
- }
- //
- // Get number of CS to train
- //
- CsPerDelay = NBPtr->CSPerDelay (NBPtr);
- //
- /// Set up the test Pattern, exit if no Memory
- //
- if (MemTInitTestPatternAddress (TechPtr, &SweepData) == FALSE) {
- LibAmdMemFill (&NBPtr->ChannelPtr->FailingBitMask[ (TechPtr->ChipSel * MAX_BYTELANES_PER_CHANNEL) ],
- 0,
- (MAX_BYTELANES_PER_CHANNEL * CsPerDelay),
- &NBPtr->MemPtr->StdHeader);
- return FALSE;
- }
- //
- // Clear Error Flag
- //
- SweepData.Error = FALSE;
- //
- /// Process Sweep table, using entries from the table to determine Starting and Ending Delays
- /// as well as the Step size and criteria for evaluating whether the correct result is found.
- ///
- /// Delay values at this level are an abstract range of values which gets scaled to the actual value
- /// before it is written to the hardware. This allows NB specific code to handle the scaling as a
- /// function of frequency or other conditions.
- //
- for (StageIndex = 0; (StageIndex < SweepTableSize) && (SweepData.Error == FALSE); StageIndex++) {
-
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tSTAGE: %d\t", StageIndex);
- //
- /// Initialize SweepData variables
- //
- SweepData.BeginDelay = SweepTablePtr->BeginDelay;
- SweepData.EndDelay = SweepTablePtr->EndDelay;
- SweepData.Step = 0; /// Step Value will be 0 to start.
- SweepData.EndResult = SweepTablePtr->EndResult;
- if (!(MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining])) {
- SweepData.EndResult |= 0x0100;
- }
- SweepData.Edge = SweepTablePtr->MinMax;
- SweepData.InsertionDelayMsk = 0;
- SweepData.ResultFound = 0x0000;
- //
- // Set Training Delays Pointer.
- //
- if (TechPtr->Direction == DQS_READ_DIR) {
- SweepData.TrnDelays = (INT8 *) ((SweepData.Edge == RIGHT_EDGE) ? NBPtr->ChannelPtr->RdDqsMaxDlys : NBPtr->ChannelPtr->RdDqsMinDlys);
- } else {
- SweepData.TrnDelays = (INT8 *) ((SweepData.Edge == RIGHT_EDGE) ? NBPtr->ChannelPtr->WrDatMaxDlys : NBPtr->ChannelPtr->WrDatMinDlys);
- };
- //
- /// Set initial TrnDelay Values if necessary
- //
- IDS_HDT_CONSOLE (MEM_FLOW, "Sweeping %s DQS, %s from ", (TechPtr->Direction == DQS_READ_DIR) ?"Read":"Write", (SweepTablePtr->ScanDir == INC_DELAY) ? "incrementing":"decrementing");
- if (SweepData.BeginDelay != LAST_DELAY) {
- IDS_HDT_CONSOLE (MEM_FLOW, "%02x", (UINT16) MemTScaleDelayVal (TechPtr, SweepData.BeginDelay));
- for (i = 0; i < ((MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8); i++) {
- SweepData.TrnDelays[i] = SweepData.BeginDelay;
- }
- } else {
- IDS_HDT_CONSOLE (MEM_FLOW, "Current Delay");
- SweepData.Step = SweepTablePtr->Step;
- }
- IDS_HDT_CONSOLE (MEM_FLOW, " by %02x, until all bytelanes %s.\n\n", (UINT16) MemTScaleDelayVal (TechPtr, ABS (SweepTablePtr->Step)), (SweepData.EndResult == 0xFFFF)?"PASS":"FAIL");
-
- //-------------------------------------------------------------------
- // Sweep DQS Delays
- // MemTContinueSweep function returns false to break out of loop.
- // There are no other breaks out of this loop.
- //-------------------------------------------------------------------
- while (MemTContinueSweep (TechPtr, &SweepData)) {
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tByte Lane : 08 07 06 05 04 03 02 01 00\n");
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tDQS Delays : %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
- (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[8]),
- (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[7]), (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[6]),
- (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[5]), (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[4]),
- (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[3]), (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[2]),
- (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[1]), (UINT16) MemTScaleDelayVal (TechPtr, SweepData.TrnDelays[0])
- );
- //
- /// Set Step Value
- //
- SweepData.Step = SweepTablePtr->Step;
- CurrentResult = 0xFFFF;
- //
- /// Chip Select Loop: Test the Pattern for all populated CS that are controlled by the current delay registers
- //
- for (CsIndex = 0; CsIndex < CsPerDelay ; CsIndex++, TechPtr->ChipSel++) {
- ASSERT (CsIndex < MAX_CS_PER_CHANNEL);
- ASSERT (TechPtr->ChipSel < MAX_CS_PER_CHANNEL);
- if (SweepData.CsAddrValid[CsIndex] == TRUE) {
- //
- /// If this is a Write Dqs sweep, Write the pattern now.
- //
- if (TechPtr->Direction == DQS_WRITE_DIR) {
- NBPtr->WritePattern (NBPtr, SweepData.TestAddrRJ16[CsIndex], TechPtr->PatternBufPtr, TechPtr->PatternLength);
- }
- //
- /// Read the Pattern Back
- //
- NBPtr->ReadPattern (NBPtr, TechPtr->TestBufPtr, SweepData.TestAddrRJ16[CsIndex], TechPtr->PatternLength);
- //
- /// Compare the Pattern and Merge the results using InsertionDelayMsk
- //
- AlignedResult = NBPtr->CompareTestPattern (NBPtr, TechPtr->TestBufPtr, TechPtr->PatternBufPtr, TechPtr->PatternLength * 64);
- CurrentResult &= AlignedResult | SweepData.InsertionDelayMsk;
- if (SweepData.InsertionDelayMsk != 0) {
- OffsetResult = NBPtr->InsDlyCompareTestPattern (NBPtr, TechPtr->TestBufPtr, TechPtr->PatternBufPtr, TechPtr->PatternLength * 64);
- CurrentResult &= (OffsetResult | (~SweepData.InsertionDelayMsk));
- }
- //
- /// Flush the Test Pattern
- //
- NBPtr->FlushPattern (NBPtr, SweepData.TestAddrRJ16[CsIndex], TechPtr->PatternLength);
- NBPtr->FamilySpecificHook[ResetRxFifoPtr] (NBPtr, NBPtr);
- }
- } /// End Chip Select Loop
- TechPtr->ChipSel = TechPtr->ChipSel - CsIndex;
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tResult : %c %c %c %c %c %c %c %c %c \n",
- (SweepData.ResultFound & ((UINT16) 1 << (8))) ? ' ':(CurrentResult & ((UINT16) 1 << (8))) ? 'P':'.',
- (SweepData.ResultFound & ((UINT16) 1 << (7))) ? ' ':(CurrentResult & ((UINT16) 1 << (7))) ? 'P':'.',
- (SweepData.ResultFound & ((UINT16) 1 << (6))) ? ' ':(CurrentResult & ((UINT16) 1 << (6))) ? 'P':'.',
- (SweepData.ResultFound & ((UINT16) 1 << (5))) ? ' ':(CurrentResult & ((UINT16) 1 << (5))) ? 'P':'.',
- (SweepData.ResultFound & ((UINT16) 1 << (4))) ? ' ':(CurrentResult & ((UINT16) 1 << (4))) ? 'P':'.',
- (SweepData.ResultFound & ((UINT16) 1 << (3))) ? ' ':(CurrentResult & ((UINT16) 1 << (3))) ? 'P':'.',
- (SweepData.ResultFound & ((UINT16) 1 << (2))) ? ' ':(CurrentResult & ((UINT16) 1 << (2))) ? 'P':'.',
- (SweepData.ResultFound & ((UINT16) 1 << (1))) ? ' ':(CurrentResult & ((UINT16) 1 << (1))) ? 'P':'.',
- (SweepData.ResultFound & ((UINT16) 1 << (0))) ? ' ':(CurrentResult & ((UINT16) 1 << (0))) ? 'P':'.'
- );
- //
- /// Merge current result into cumulative result and make it positive.
- //
- SweepData.ResultFound |= ~(CurrentResult ^ SweepData.EndResult);
-
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t\tResultFound : %c %c %c %c %c %c %c %c %c \n\n",
- (SweepData.ResultFound & ((UINT16) 1 << (8))) ? 'Y':' ',
- (SweepData.ResultFound & ((UINT16) 1 << (7))) ? 'Y':' ',
- (SweepData.ResultFound & ((UINT16) 1 << (6))) ? 'Y':' ',
- (SweepData.ResultFound & ((UINT16) 1 << (5))) ? 'Y':' ',
- (SweepData.ResultFound & ((UINT16) 1 << (4))) ? 'Y':' ',
- (SweepData.ResultFound & ((UINT16) 1 << (3))) ? 'Y':' ',
- (SweepData.ResultFound & ((UINT16) 1 << (2))) ? 'Y':' ',
- (SweepData.ResultFound & ((UINT16) 1 << (1))) ? 'Y':' ',
- (SweepData.ResultFound & ((UINT16) 1 << (0))) ? 'Y':' '
- );
- } /// End of Delay Sweep
- //
- /// Place Final delay values at last passing delay.
- //
- if (SweepData.ResultFound == 0xFFFF) {
- if ( ABS (SweepData.Step) == 1) {
- for (i = 0; i < ((MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8) ; i++) {
- if ((SweepData.EndResult & ((UINT16) (1 << i))) == 0) {
- SweepData.TrnDelays[i] = SweepData.TrnDelays[i] - SweepData.Step;
- }
- }
- }
- }
- //
- // Update Pointer to Sweep Table
- //
- SweepTablePtr++;
- }///End of Edge Detect loop
- //
- /// If No Errors are detected, Calculate Data Eye Width and Center
- //
- if (SweepData.Error == FALSE) {
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\tData Eye Results:\n\n");
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\tByte Left Right\n");
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\tLane Edge Edge Width Center\n");
- for (i = 0; i < ((MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8) ; i++) {
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\t %0d", i);
- MemTDataEyeSave (TechPtr, &SweepData, i);
- IDS_HDT_CONSOLE (MEM_FLOW, "\n");
- if (SweepData.Error == TRUE) {
- Status = FALSE;
- }
- }
- } else {
- Status = FALSE;
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\t--DATA EYE NOT FOUND--\n\n");
- }
- return Status;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Initialize the Test Pattern Address for two chip selects and, if this
- * is a Write Data Eye, write the initial test pattern.
- *
- * Test Address is stored in the Sweep info struct. If Memory is not present
- * then return with False.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in,out] *SweepPtr - Pointer to SWEEP_INFO structure.
- *
- * @return BOOLEAN
- * TRUE - Memory is present
- * FALSE - No memory present on this Chip Select pair.
- *
-**
- */
-BOOLEAN
-STATIC
-MemTInitTestPatternAddress (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT SWEEP_INFO *SweepPtr
- )
-{
- MEM_NB_BLOCK *NBPtr;
- UINT8 ChipSel;
- UINT8 CsPerDelay;
- UINT8 CsIndex;
- BOOLEAN BanksPresent;
-
- NBPtr = TechPtr->NBPtr;
- BanksPresent = FALSE;
- CsPerDelay = NBPtr->CSPerDelay (NBPtr);
- ChipSel = TechPtr->ChipSel;
- for (CsIndex = 0; CsIndex < CsPerDelay; ChipSel++, CsIndex++, TechPtr->ChipSel++) {
- ASSERT (CsIndex < MAX_CS_PER_CHANNEL);
- ASSERT (ChipSel < MAX_CS_PER_CHANNEL);
- ASSERT (TechPtr->ChipSel < MAX_CS_PER_CHANNEL);
- //
- /// If memory is present on this cs, get the test addr
- //
- if (NBPtr->GetSysAddr (NBPtr, ChipSel, &(SweepPtr->TestAddrRJ16[CsIndex]))) {
- if (!(NBPtr->MCTPtr->Status[SbLrdimms]) || ((NBPtr->ChannelPtr->LrDimmPresent & ((UINT8) 1 << (ChipSel >> 1))) != 0)) {
- BanksPresent = TRUE;
- SweepPtr->CsAddrValid[CsIndex] = TRUE;
- //
- /// If this is a Read Dqs sweep, Write the pattern now.
- //
- if (TechPtr->Direction == DQS_READ_DIR) {
- IDS_HDT_CONSOLE (MEM_FLOW, "\tTestAddr: %x0000\n", SweepPtr->TestAddrRJ16[CsIndex]);
- NBPtr->WritePattern (NBPtr, SweepPtr->TestAddrRJ16[CsIndex], TechPtr->PatternBufPtr, TechPtr->PatternLength);
- }
- }
- } else {
- SweepPtr->CsAddrValid[CsIndex] = FALSE;
- }
- } /// End Chip Select Loop
- TechPtr->ChipSel = TechPtr->ChipSel - CsIndex;
- //
- /// return FALSE if no ChipSelects present.
- //
- return BanksPresent;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- * Test Conditions for exiting the training loop, set the next delay value,
- * and return status
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in,out] *SweepPtr - Pointer to SWEEP_INFO structure.
- *
- * @return BOOLEAN
- * TRUE - Continue to test with next delay setting
- * FALSE - Exit training loop. Either the result has been found or
- * end of delay range has been reached.
-*/
-BOOLEAN
-STATIC
-MemTContinueSweep (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT SWEEP_INFO *SweepPtr
- )
-{
- BOOLEAN Status;
- Status = FALSE;
- if (SweepPtr->ResultFound != 0xFFFF) {
- Status = MemTSetNextDelay (TechPtr, SweepPtr);
- }
- return Status;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the next delay value for each bytelane that needs to
- * be advanced. It checks the bounds of the delay to see if we are at the
- * end of the range. If we are to close to advance a whole step value, but
- * not at the boundary, then we set the delay to the boundary.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in,out] *SweepPtr - Pointer to SWEEP_INFO structure.
- *
- */
-
-BOOLEAN
-STATIC
-MemTSetNextDelay (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT SWEEP_INFO *SweepPtr
- )
-{
- DIE_STRUCT *MCTPtr;
- UINT8 i;
-
- MCTPtr = TechPtr->NBPtr->MCTPtr;
- //
- ///< Loop through bytelanes
- //
- for (i = 0; i < ((MCTPtr->Status[SbEccDimms] && TechPtr->NBPtr->IsSupported[EccByteTraining]) ? 9 : 8) ; i++) {
- //
- /// Skip Bytelanes that have already reached the desired result
- //
- if ( (SweepPtr->ResultFound & ((UINT16)1 << i)) == 0) {
- //
- /// If a bytelane has reached the end, flag an error and exit
- //
- if (SweepPtr->TrnDelays[i] == SweepPtr->EndDelay) {
- if ((SweepPtr->EndResult & ((UINT16) (1 << i))) != 0) {
- MCTPtr->ErrStatus[EsbNoDqsPos] = TRUE;
- SweepPtr->Error = TRUE;
- }
- return FALSE;
- }
- //
- /// If the Current delay value is less than a step away from EndDelay,
- //
- if ( ABS (SweepPtr->EndDelay - SweepPtr->TrnDelays[i]) < ABS (SweepPtr->Step)) {
- /// set to EndDelay.
- //
- SweepPtr->TrnDelays[i] = SweepPtr->EndDelay;
- } else {
- //
- /// Otherwise, add the step value to it
- SweepPtr->TrnDelays[i] = SweepPtr->TrnDelays[i] + SweepPtr->Step;
- }
- //
- /// Set InsertionDelayMsk bit if Delay < 0 for this bytelane
- //
- if (SweepPtr->TrnDelays[i] < 0) {
- SweepPtr->InsertionDelayMsk |= ((UINT16) 1 << i);
- } else {
- SweepPtr->InsertionDelayMsk &= ~((UINT16) 1 << i);
- }
- //
- /// Write the scaled value to the Delay Register
- //
- TechPtr->SetDQSDelayCSR (TechPtr, i, MemTScaleDelayVal (TechPtr, SweepPtr->TrnDelays[i]));
- }
- }
- return TRUE;
-}
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function accepts a delay value in 32nd of a UI and converts it to an
- * actual register value, taking into consideration NB type, rd/wr,
- * and frequency.
- *
- * Delay = (Min + (Delay * ( (Max - Min) / TRN_DELAY_MAX) )) & Mask
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] *Delay - INT8 of delay value;
- *
- * @return UINT8 of the adjusted delay value
-*/
-UINT8
-STATIC
-MemTScaleDelayVal (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN INT8 Delay
- )
-{
- MEM_NB_BLOCK *NBPtr;
- TRN_DLY_PARMS Parms;
- TRN_DLY_TYPE DelayType;
- UINT8 NewDelay;
- INT8 Factor;
- INT8 ScaledDelay;
-
- NBPtr = TechPtr->NBPtr;
- //
- // Determine Delay Type, Get Delay Parameters, and return scaled Delay value
- //
- DelayType = (TechPtr->Direction == DQS_WRITE_DIR) ? AccessWrDatDly : AccessRdDqsDly;
- NBPtr->GetTrainDlyParms (NBPtr, DelayType, &Parms);
- Factor = ((Parms.Max - Parms.Min) / TRN_DELAY_MAX);
- ScaledDelay = Delay * Factor;
- NewDelay = (Parms.Min + ScaledDelay) & Parms.Mask;
- return NewDelay;
-}
-
-
-
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function calculates the Center of the Data eye for the specified byte lane
- * and stores its DQS Delay value for reference.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in,out] *SweepPtr - Pointer to SWEEP_INFO structure.
- * @param[in] ByteLane - Bytelane number being targeted
- *
- */
-VOID
-STATIC
-MemTDataEyeSave (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT SWEEP_INFO *SweepPtr,
- IN UINT8 ByteLane
- )
-{
- MEM_NB_BLOCK *NBPtr;
- UINT8 EyeCenter;
- UINT8 DlyMin;
- UINT8 DlyMax;
- UINT8 EyeWidth;
- UINT8 Dimm;
- CH_DEF_STRUCT *ChanPtr;
-
- NBPtr = TechPtr->NBPtr;
- ChanPtr = NBPtr->ChannelPtr;
-
- ASSERT (ByteLane < ((NBPtr->MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8));
- //
- // Calculate Data Eye edges, Width, and Center in real terms.
- //
- if (TechPtr->Direction == DQS_READ_DIR) {
- DlyMin = MemTScaleDelayVal (TechPtr, ChanPtr->RdDqsMinDlys[ByteLane]);
- DlyMax = MemTScaleDelayVal (TechPtr, ChanPtr->RdDqsMaxDlys[ByteLane]);
- EyeWidth = MemTScaleDelayVal (TechPtr, (ChanPtr->RdDqsMaxDlys[ByteLane] - ChanPtr->RdDqsMinDlys[ByteLane]));
- EyeCenter = MemTScaleDelayVal (TechPtr, ((ChanPtr->RdDqsMinDlys[ByteLane] + ChanPtr->RdDqsMaxDlys[ByteLane] + 1) / 2));
- ChanPtr->RdDqsMinDlys[ByteLane] = DlyMin;
- ChanPtr->RdDqsMaxDlys[ByteLane] = DlyMax;
- NBPtr->FamilySpecificHook[ForceRdDqsPhaseB] (NBPtr, &EyeCenter);
- } else {
- DlyMin = MemTScaleDelayVal (TechPtr, ChanPtr->WrDatMinDlys[ByteLane]);
- DlyMax = MemTScaleDelayVal (TechPtr, ChanPtr->WrDatMaxDlys[ByteLane]);
- EyeWidth = MemTScaleDelayVal (TechPtr, (ChanPtr->WrDatMaxDlys[ByteLane] - ChanPtr->WrDatMinDlys[ByteLane]));
- EyeCenter = MemTScaleDelayVal (TechPtr, ((ChanPtr->WrDatMinDlys[ByteLane] + ChanPtr->WrDatMaxDlys[ByteLane] + 1) / 2));
- ChanPtr->WrDatMinDlys[ByteLane] = DlyMin;
- ChanPtr->WrDatMaxDlys[ByteLane] = DlyMax;
- }
- //
- // Flag error for small window.
- //
- if (EyeWidth < MemTScaleDelayVal (TechPtr, NBPtr->MinDataEyeWidth (NBPtr))) {
- TechPtr->SmallDqsPosWindow = TRUE;
- SweepPtr->Error = TRUE;
- }
-
- IDS_HDT_CONSOLE (MEM_FLOW, " %02x %02x %02x %02x", DlyMin, DlyMax, EyeWidth, EyeCenter);
-
- TechPtr->SetDQSDelayCSR (TechPtr, ByteLane, EyeCenter);
- TechPtr->DqsRdWrPosSaved |= (UINT8)1 << ByteLane;
- TechPtr->DqsRdWrPosSaved |= 0xFE00;
-
- Dimm = (TechPtr->ChipSel / 2) * TechPtr->DlyTableWidth () + ByteLane;
- if (TechPtr->Direction == DQS_READ_DIR) {
- ChanPtr->RdDqsDlys[Dimm] = EyeCenter;
- } else {
- ChanPtr->WrDatDlys[Dimm] = EyeCenter + ChanPtr->WrDqsDlys[Dimm];
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Tech/mttEdgeDetect.h b/src/vendorcode/amd/agesa/Proc/Mem/Tech/mttEdgeDetect.h
deleted file mode 100644
index 73bb630..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Tech/mttEdgeDetect.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mttEdgeDetect.h
- *
- * Technology Common Training Header file
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MTTEDGEDETECT_H_
-#define _MTTEDGEDETECT_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-
-#define SCAN_LEFT 0 ///< Scan Down
-#define SCAN_RIGHT 1 ///< Scan Up
-#define LEFT_EDGE 0 ///< searching for the left edge
-#define RIGHT_EDGE 1 ///< searching for the right edge
-
-#define SweepStages 4
-#define TRN_DELAY_MAX 31 ///< Max Virtual delay value for DQS Position Training
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/**
- * Sweep Table Structure. ROM based table defining parameters for DQS position
- * training delay sweep.
-*/
-typedef struct {
- INT8 BeginDelay; ///< Starting Delay Value
- INT8 EndDelay; ///< Ending Delay Value
- BOOLEAN ScanDir; ///< Scan Direction. 0 = down, 1 = up
- INT8 Step; ///< Amount to increment delay value
- UINT16 EndResult; ///< Result value to stop sweeping (to compare with failure mask)
- BOOLEAN MinMax; ///< Flag indicating lower (left edge) or higher(right edge)
-} DQS_POS_SWEEP_TABLE;
-
-/**
- * Sweep Information Struct - Used to track data through the DQS Delay Sweep
- *
-*/
-typedef struct _SWEEP_INFO {
- BOOLEAN Error; ///< Indicates an Error has been found
- UINT32 TestAddrRJ16[MAX_CS_PER_CHANNEL]; ///< System address of chipselects RJ 16 bits (Addr[47:16])
- BOOLEAN CsAddrValid[MAX_CS_PER_CHANNEL]; ///< Indicates which chipselects to test
- INT8 BeginDelay; ///< Beginning Delay value (Virtual)
- INT8 EndDelay; ///< Ending Delay value (Virtual)
- INT8 Step; ///< Amount to Inc or Dec Virtual Delay value
- BOOLEAN Edge; ///< Left or right edge (0 = LEFT, 1= RIGHT)
- UINT16 EndResult; ///< Result value that will stop a Dqs Sweep
- UINT16 InsertionDelayMsk; ///< Mask of Byte Lanes that should use ins. dly. comparison
- UINT16 LaneMsk; ///< Mask indicating byte lanes to update
- UINT16 ResultFound; ///< Mask indicating byte lanes where desired result was found on a sweep
- INT8 *TrnDelays; ///< Delay Values for each byte (Virtual). Points into the delay values
-} SWEEP_INFO; ///< stored in the CH_DEF_STRUCT.
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#endif /* _MTTEDGEDETECT_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Tech/mttdimbt.c b/src/vendorcode/amd/agesa/Proc/Mem/Tech/mttdimbt.c
deleted file mode 100644
index ced3d93..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Tech/mttdimbt.c
+++ /dev/null
@@ -1,1279 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mttdimmbt.c
- *
- * Technology Dimm Based Training
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech)
- * @e \$Revision: 38442 $ @e \$Date: 2010-09-24 06:39:57 +0800 (Fri, 24 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "mu.h"
-#include "mt.h"
-#include "GeneralServices.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_TECH_MTTDIMBT_FILECODE
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define MAX_BYTELANES 8 /* 8 byte lanes */
-#define MAX_DELAYS 9 /* 8 data bytes + 1 ECC byte */
-#define MAX_DIMMS 4 /* 4 DIMMs per channel */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-VOID
-STATIC
-MemTInitDqsPos4RcvrEnByte (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-VOID
-STATIC
-MemTSetRcvrEnDlyByte (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Receiver,
- IN UINT16 RcvEnDly
- );
-
-VOID
-STATIC
-MemTLoadRcvrEnDlyByte (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Receiver
- );
-
-BOOLEAN
-STATIC
-MemTSaveRcvrEnDlyByte (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Receiver,
- IN UINT16 RcvEnDly,
- IN UINT16 CmpResultRank0,
- IN UINT16 CmpResultRank1
- );
-
-VOID
-STATIC
-MemTResetDctWrPtrByte (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Receiver
- );
-
-UINT16
-STATIC
-MemTCompare1ClPatternByte (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Buffer[],
- IN UINT8 Pattern[]
- );
-
-VOID
-STATIC
-MemTSkipChipSelPass1Byte (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT UINT8 *ChipSelPtr
- );
-
-VOID
-STATIC
-MemTSkipChipSelPass2Byte (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT UINT8 *ChipSelPtr
- );
-
-UINT8
-STATIC
-MemTMaxByteLanesByte (VOID);
-
-UINT8
-STATIC
-MemTDlyTableWidthByte (VOID);
-
-VOID
-STATIC
-MemTSetDqsDelayCsrByte (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 ByteLane,
- IN UINT8 Dly
- );
-
-VOID
-STATIC
-MemTDqsWindowSaveByte (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 ByteLane,
- IN UINT8 DlyMin,
- IN UINT8 DlyMax
- );
-
-BOOLEAN
-STATIC
-MemTFindMaxRcvrEnDlyByte (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- OUT UINT8 *ChipSel
- );
-
-UINT16
-STATIC
-MemTCompare1ClPatternOptByte (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Buffer[],
- IN UINT8 Pattern[],
- IN UINT8 Side,
- IN UINT8 Receiver,
- IN BOOLEAN Side1En
- );
-
-VOID
-STATIC
-MemTLoadRcvrEnDlyOptByte (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Receiver
- );
-
-VOID
-STATIC
-MemTSetRcvrEnDlyOptByte (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Receiver,
- IN UINT16 RcvEnDly
- );
-
-VOID
-STATIC
-MemTLoadInitialRcvEnDlyOptByte (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Receiver
- );
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function enables byte based training if called
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-VOID
-MemTDimmByteTrainInit (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT8 Dct;
- UINT8 Channel;
- UINT8 DctCount;
- UINT8 ChannelCount;
- DIE_STRUCT *MCTPtr;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
- MCTPtr = NBPtr->MCTPtr;
-
- TechPtr->InitDQSPos4RcvrEn = MemTInitDqsPos4RcvrEnByte;
- TechPtr->SetRcvrEnDly = MemTSetRcvrEnDlyByte;
- TechPtr->LoadRcvrEnDly = MemTLoadRcvrEnDlyByte;
- TechPtr->SaveRcvrEnDly = MemTSaveRcvrEnDlyByte;
- TechPtr->SaveRcvrEnDlyFilter = MemTSaveRcvrEnDlyByteFilterOpt;
- TechPtr->ResetDCTWrPtr = MemTResetDctWrPtrByte;
- TechPtr->Compare1ClPattern = MemTCompare1ClPatternByte;
- TechPtr->SkipChipSelPass1 = MemTSkipChipSelPass1Byte;
- TechPtr->SkipChipSelPass2 = MemTSkipChipSelPass2Byte;
- TechPtr->MaxByteLanes = MemTMaxByteLanesByte;
- TechPtr->DlyTableWidth = MemTDlyTableWidthByte;
- TechPtr->SetDQSDelayCSR = MemTSetDqsDelayCsrByte;
- TechPtr->DQSWindowSave = MemTDqsWindowSaveByte;
- TechPtr->FindMaxDlyForMaxRdLat = MemTFindMaxRcvrEnDlyByte;
- TechPtr->Compare1ClPatternOpt = MemTCompare1ClPatternOptByte;
- TechPtr->LoadRcvrEnDlyOpt = MemTLoadRcvrEnDlyOptByte;
- TechPtr->SetRcvrEnDlyOpt = MemTSetRcvrEnDlyOptByte;
- TechPtr->InitializeVariablesOpt = MemTInitializeVariablesOptByte;
- TechPtr->GetMaxValueOpt = MemTGetMaxValueOptByte;
- TechPtr->SetSweepErrorOpt = MemTSetSweepErrorOptByte;
- TechPtr->CheckRcvrEnDlyLimitOpt = MemTCheckRcvrEnDlyLimitOptByte;
- TechPtr->LoadInitialRcvrEnDlyOpt = MemTLoadInitialRcvEnDlyOptByte;
- // Dynamically allocate buffers for storing trained timings.
- DctCount = MCTPtr->DctCount;
- ChannelCount = MCTPtr->DctData[0].ChannelCount;
- AllocHeapParams.RequestedBufferSize = ((DctCount * ChannelCount) *
- ((MAX_DIMMS * MAX_DELAYS * NUMBER_OF_DELAY_TABLES) +
- (MAX_DELAYS * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES)
- )
- );
- AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_TRN_DATA_HANDLE, MCTPtr->NodeId, 0, 0);
- AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
- if (HeapAllocateBuffer (&AllocHeapParams, &NBPtr->MemPtr->StdHeader) == AGESA_SUCCESS) {
- for (Dct = 0; Dct < DctCount; Dct++) {
- for (Channel = 0; Channel < ChannelCount; Channel++) {
- MCTPtr->DctData[Dct].ChData[Channel].RowCount = MAX_DIMMS;
- MCTPtr->DctData[Dct].ChData[Channel].ColumnCount = MAX_DELAYS;
-
- MCTPtr->DctData[Dct].ChData[Channel].RcvEnDlys = (UINT16 *) AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS) * 2;
- MCTPtr->DctData[Dct].ChData[Channel].WrDqsDlys = AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS);
- MCTPtr->DctData[Dct].ChData[Channel].RdDqsDlys = AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS);
- MCTPtr->DctData[Dct].ChData[Channel].WrDatDlys = AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS);
- MCTPtr->DctData[Dct].ChData[Channel].RdDqsMinDlys = AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS);
- MCTPtr->DctData[Dct].ChData[Channel].RdDqsMaxDlys = AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS);
- MCTPtr->DctData[Dct].ChData[Channel].WrDatMinDlys = AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS);
- MCTPtr->DctData[Dct].ChData[Channel].WrDatMaxDlys = AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS);
- MCTPtr->DctData[Dct].ChData[Channel].FailingBitMask = AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += (MAX_CS_PER_CHANNEL * MAX_DELAYS);
- }
- }
- } else {
- PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_FATAL, MCTPtr);
- ASSERT(FALSE); // Could not dynamically allocate buffers for storing trained timings
- }
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initializes the DQS Positions in preparation for Receiver Enable Training.
- * Write Position is no delay, Read Position is 1/2 Memclock delay
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-VOID
-STATIC
-MemTInitDqsPos4RcvrEnByte (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT8 Dimm;
- UINT8 ByteLane;
- UINT8 WrDqs;
-
- for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
- for (ByteLane = 0; ByteLane < MAX_DELAYS; ByteLane++) {
- WrDqs = TechPtr->NBPtr->ChannelPtr->WrDqsDlys[(Dimm * MAX_DELAYS) + ByteLane];
- TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessWrDatDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), WrDqs);
- TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRdDqsDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), 0x3F);
- }
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function programs DqsRcvEnDly to additional index for DQS receiver enabled training
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] Receiver - Current Chip select value
- * @param[in] RcvEnDly - receiver enable delay to be saved
- */
-
-VOID
-STATIC
-MemTSetRcvrEnDlyByte (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Receiver,
- IN UINT16 RcvEnDly
- )
-{
- UINT8 ByteLane;
-
- ASSERT (Receiver < MAX_CS_PER_CHANNEL);
- for (ByteLane = 0; ByteLane < MAX_BYTELANES; ByteLane++) {
- TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Receiver >> 1, ByteLane), RcvEnDly);
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function loads the DqsRcvEnDly from saved data and program to additional index
- * for DQS receiver enabled training
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] Receiver - Current Chip select value
- *
- */
-
-VOID
-STATIC
-MemTLoadRcvrEnDlyByte (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Receiver
- )
-{
- UINT8 i;
- UINT8 Dimm;
- UINT16 Saved;
- CH_DEF_STRUCT *ChannelPtr;
-
- ASSERT (Receiver < MAX_CS_PER_CHANNEL);
- ChannelPtr = TechPtr->NBPtr->ChannelPtr;
-
- Dimm = Receiver >> 1;
- Saved = TechPtr->DqsRcvEnSaved;
- for (i = 0; i < MAX_BYTELANES; i++) {
- if (Saved & 1) {
- TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Receiver >> 1, i),
- ChannelPtr->RcvEnDlys[Dimm * MAX_DELAYS + i]);
- }
- Saved >>= 1;
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function saves passing DqsRcvEnDly values to the stack
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] Receiver - Current Chip select value
- * @param[in] RcvEnDly - receiver enable delay to be saved
- * @param[in] CmpResultRank0 - compare result for Rank 0
- * @param[in] CmpResultRank1 - compare result for Rank 1
- *
- * @return TRUE - All bytelanes pass
- * @return FALSE - Some bytelanes fail
- */
-
-BOOLEAN
-STATIC
-MemTSaveRcvrEnDlyByte (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Receiver,
- IN UINT16 RcvEnDly,
- IN UINT16 CmpResultRank0,
- IN UINT16 CmpResultRank1
- )
-{
- UINT8 i;
- UINT8 Passed;
- UINT8 Saved;
- UINT8 Mask;
- UINT8 Dimm;
- CH_DEF_STRUCT *ChannelPtr;
-
- ASSERT (Receiver < MAX_CS_PER_CHANNEL);
- ChannelPtr = TechPtr->NBPtr->ChannelPtr;
-
- Passed = (UINT8) ((CmpResultRank0 & CmpResultRank1) & 0xFF);
-
- Saved = (UINT8) (TechPtr->DqsRcvEnSaved & Passed); //@attention - false passes filter (subject to be replaced with a better solution)
- Dimm = Receiver >> 1;
- Mask = 1;
- for (i = 0; i < MAX_BYTELANES; i++) {
- if (Passed & Mask) {
- if (!(Saved & Mask)) {
- ChannelPtr->RcvEnDlys[Dimm * MAX_DELAYS + i] = RcvEnDly + 0x20; // @attention -1 pass only
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tBL %d = %02x", i, RcvEnDly + 0x20);
- }
- Saved |= Mask;
- }
- Mask <<= 1;
- }
- TechPtr->DqsRcvEnSaved = Saved;
-
- if (Saved == 0xFF) {
- return TRUE;
- } else {
- return FALSE;
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function performs a filtering functionality and saves passing DqsRcvEnDly
- * values to the stack
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] Receiver - Current Chip select value
- * @param[in] RcvEnDly - receiver enable delay to be saved
- * @param[in] CmpResultRank0 - compare result for Rank 0
- * @param[in] CmpResultRank1 - compare result for Rank 1
- *
- * @return TRUE - All bytelanes pass
- * @return FALSE - Some bytelanes fail
- */
-
-BOOLEAN
-MemTSaveRcvrEnDlyByteFilter (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Receiver,
- IN UINT16 RcvEnDly,
- IN UINT16 CmpResultRank0,
- IN UINT16 CmpResultRank1
- )
-{
- UINT8 i;
- UINT8 Passed;
- UINT8 Saved;
- UINT8 Mask;
- UINT8 Dimm;
- UINT8 MaxFilterDly;
- CH_DEF_STRUCT *ChannelPtr;
- MEM_DCT_CACHE *DctCachePtr;
-
- ASSERT (Receiver < MAX_CS_PER_CHANNEL);
- ChannelPtr = TechPtr->NBPtr->ChannelPtr;
- DctCachePtr = TechPtr->NBPtr->DctCachePtr;
-
- MaxFilterDly = TechPtr->MaxFilterDly;
- Passed = (UINT8) ((CmpResultRank0 & CmpResultRank1) & 0xFF);
-
- Dimm = Receiver >> 1;
- Saved = (UINT8) TechPtr->DqsRcvEnSaved;
- Mask = 1;
- for (i = 0; i < MAX_BYTELANES; i++) {
- if ((Passed & Mask) != 0) {
- DctCachePtr->RcvEnDlyCounts [i] += 1;
- if ((Saved & Mask) == 0) {
- ChannelPtr->RcvEnDlys[Dimm * MAX_DELAYS + i] = RcvEnDly + 0x20;
- Saved |= Mask;
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tBL %d = %02x", i, RcvEnDly + 0x20);
- }
- } else {
- if (DctCachePtr->RcvEnDlyCounts [i] <= MaxFilterDly) {
- DctCachePtr->RcvEnDlyCounts [i] = 0;
- Saved &= ~Mask;
- }
- }
- Mask <<= 1;
- }
-
- //-----------------------
- TechPtr->DqsRcvEnSaved = (UINT16) Saved;
-
- Saved = 0;
- for (i = 0; i < MAX_BYTELANES; i++) {
- if (DctCachePtr->RcvEnDlyCounts [i] >= MaxFilterDly) {
- Saved |= (UINT8) 1 << i;
- }
- }
-
- if (Saved == 0xFF) {
- return TRUE;
- } else {
- return FALSE;
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function compares test pattern with data in buffer and return a pass/fail bitmap
- * for 8 Bytes
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] Buffer[] - Buffer data from DRAM (Measured data from DRAM) to compare
- * @param[in] Pattern[] - Pattern (Expected data in ROM/CACHE) to compare against
- *
- * @return PASS - Bit map of results of comparison
- */
-
-UINT16
-STATIC
-MemTCompare1ClPatternByte (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Buffer[],
- IN UINT8 Pattern[]
- )
-{
- UINT16 i;
- UINT16 j;
- UINT16 Pass;
- DIE_STRUCT *MCTPtr;
-
- MCTPtr = TechPtr->NBPtr->MCTPtr;
- if (MCTPtr->GangedMode && MCTPtr->Dct) {
- j = 8;
- } else {
- j = 0;
- }
-
- Pass = 0xFFFF;
- IDS_HDT_CONSOLE (MEM_FLOW, " -");
- for (i = 0; i < 8; i++) {
- if (Buffer[j] != Pattern[j]) {
- // if bytelane n fails
- Pass &= ~((UINT16)1 << (j % 8)); // clear bit n
- }
- IDS_HDT_CONSOLE (MEM_FLOW, " %c", (Buffer[j] == Pattern[j]) ? 'P' : '.');
- j++;
- }
-
- IDS_HDT_CONSOLE_DEBUG_CODE (
- IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t -");
- for (i = 0, j -= 8; i < 8; i++, j++) {
- IDS_HDT_CONSOLE (MEM_FLOW, " %02x", Buffer[j]);
- }
- IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t -");
- for (i = 0, j -= 8; i < 8; i++, j++) {
- IDS_HDT_CONSOLE (MEM_FLOW, " %02x", Pattern[j]);
- }
- IDS_HDT_CONSOLE (MEM_FLOW, "\n\n");
- );
-
- return Pass;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * The function resets the DCT input buffer write pointer.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] Receiver - Chip select
- *
- */
-
-VOID
-STATIC
-MemTResetDctWrPtrByte (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Receiver
- )
-{
- UINT8 i;
- UINT16 RcvEnDly;
-
- ASSERT (Receiver < MAX_CS_PER_CHANNEL);
- for (i = 0; i < MAX_BYTELANES; i++) {
- RcvEnDly = (UINT16) TechPtr->NBPtr->GetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Receiver / 2, i));
- TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Receiver / 2, i), RcvEnDly);
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function skips odd chip select if training at 800MT or above.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] *ChipSelPtr - Pointer to variable contains Chip select index
- *
- */
-
-VOID
-STATIC
-MemTSkipChipSelPass1Byte (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT UINT8 *ChipSelPtr
- )
-{
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
- // if the even chip select failed training, need to set CsTrainFail for odd chip select if present.
- if (NBPtr->DCTPtr->Timings.CsPresent & ((UINT16)1 << ((*ChipSelPtr) + 1))) {
- if (NBPtr->DCTPtr->Timings.CsTrainFail & ((UINT16)1 << *ChipSelPtr)) {
- NBPtr->DCTPtr->Timings.CsTrainFail |= (UINT16)1 << ((*ChipSelPtr) + 1);
- NBPtr->MemPtr->ErrorHandling (NBPtr->MCTPtr, NBPtr->Dct, NBPtr->DCTPtr->Timings.CsTrainFail, &NBPtr->MemPtr->StdHeader);
- }
- }
- (*ChipSelPtr)++;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * MemTSkipChipSelPass2Byte:
- *
- * This function skips odd chip select if training at 800MT or above.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in,out] *ChipSelPtr - Pointer to variable contains Chip select index
- *
- */
-
-VOID
-STATIC
-MemTSkipChipSelPass2Byte (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT UINT8 *ChipSelPtr
- )
-{
- if (*ChipSelPtr & 1) {
- *ChipSelPtr = MAX_CS_PER_CHANNEL; // skip all successions
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function determines the maximum number of byte lanes
- *
- * @return Max number of Bytelanes
- */
-
-UINT8
-STATIC
-MemTMaxByteLanesByte (VOID)
-{
- return MAX_BYTELANES;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function determines the width of the delay tables (eg. RcvEnDlys, WrDqsDlys,...)
- *
- * @return Delay table width in bytes
- */
-
-UINT8
-STATIC
-MemTDlyTableWidthByte (VOID)
-{
- return MAX_DELAYS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function writes the Delay value to a certain byte lane
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] ByteLane - Bytelane number being targeted
- * @param[in] Dly - Delay value
- *
- */
-
-VOID
-STATIC
-MemTSetDqsDelayCsrByte (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 ByteLane,
- IN UINT8 Dly
- )
-{
- UINT8 Reg;
- UINT8 Dimm;
-
- ASSERT (ByteLane <= MAX_BYTELANES);
-
- if (!(TechPtr->DqsRdWrPosSaved & ((UINT8)1 << ByteLane))) {
- Dimm = (TechPtr->ChipSel >> 1);
-
- if (TechPtr->Direction == DQS_WRITE_DIR) {
- Dly = Dly + ((UINT8) TechPtr->NBPtr->ChannelPtr->WrDqsDlys[(Dimm * MAX_DELAYS) + ByteLane]);
- Reg = AccessWrDatDly;
- } else {
- Reg = AccessRdDqsDly;
- }
-
- TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, Reg, DIMM_BYTE_ACCESS (Dimm, ByteLane), Dly);
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function programs the trained DQS delay for the specified byte lane
- * and stores its DQS window for reference.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] ByteLane - Bytelane number being targeted
- * @param[in] DlyMin - Minimum delay value
- * @param[in] DlyMax- Maximum delay value
- *
- */
-
-VOID
-STATIC
-MemTDqsWindowSaveByte (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 ByteLane,
- IN UINT8 DlyMin,
- IN UINT8 DlyMax
- )
-{
- UINT8 DqsDelay;
- UINT8 Dimm;
- CH_DEF_STRUCT *ChanPtr;
-
- ASSERT (ByteLane <= MAX_BYTELANES);
- ChanPtr = TechPtr->NBPtr->ChannelPtr;
-
- DqsDelay = ((DlyMin + DlyMax + 1) / 2) & 0x3F;
- MemTSetDqsDelayCsrByte (TechPtr, ByteLane, DqsDelay);
- TechPtr->DqsRdWrPosSaved |= (UINT8)1 << ByteLane;
- TechPtr->DqsRdWrPosSaved |= 0xFF00;
-
- Dimm = (TechPtr->ChipSel / 2) * MAX_DELAYS + ByteLane;
- if (TechPtr->Direction == DQS_READ_DIR) {
- ChanPtr->RdDqsDlys[Dimm] = DqsDelay;
- } else {
- ChanPtr->WrDatDlys[Dimm] = DqsDelay + ChanPtr->WrDqsDlys[Dimm];
- }
-
- if (TechPtr->Direction == DQS_READ_DIR) {
- ChanPtr->RdDqsMinDlys[ByteLane] = DlyMin;
- ChanPtr->RdDqsMaxDlys[ByteLane] = DlyMax;
- } else {
- ChanPtr->WrDatMinDlys[ByteLane] = DlyMin;
- ChanPtr->WrDatMaxDlys[ByteLane] = DlyMax;
- }
-
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function finds the DIMM that has the largest receiver enable delay.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[out] *ChipSel - Pointer to the Chip select that has the largest receiver enable delay.
- *
- * @return TRUE - A chip select can be found.
- * @return FALSE - A chip select cannot be found.
- */
-
-BOOLEAN
-STATIC
-MemTFindMaxRcvrEnDlyByte (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- OUT UINT8 *ChipSel
- )
-{
- UINT8 Dimm;
- UINT8 ByteLane;
- UINT16 RcvEnDly;
- UINT16 MaxDly;
- UINT8 MaxDlyDimm;
- BOOLEAN RetVal;
-
- MEM_NB_BLOCK *NBPtr;
- CH_DEF_STRUCT *ChannelPtr;
-
- NBPtr = TechPtr->NBPtr;
- ChannelPtr = NBPtr->ChannelPtr;
-
- RetVal = FALSE;
- MaxDly = 0;
- MaxDlyDimm = 0;
- for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
- if ((NBPtr->DCTPtr->Timings.CsTrainFail & ((UINT16) 3 << (Dimm << 1))) == 0) {
- // Only choose the dimm that does not fail training
- for (ByteLane = 0; ByteLane < ((NBPtr->MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8); ByteLane++) {
- RcvEnDly = ChannelPtr->RcvEnDlys[Dimm * MAX_DELAYS + ByteLane];
- if (RcvEnDly > MaxDly) {
- MaxDly = RcvEnDly;
- MaxDlyDimm = Dimm;
- RetVal = TRUE;
- }
- }
- }
- }
-
- if (NBPtr->MCTPtr->Status[Sb128bitmode] != 0) {
- //The RcvrEnDlys of DCT1 DIMMs should also be considered while ganging.
- NBPtr->SwitchDCT (NBPtr, 1);
- ChannelPtr = NBPtr->ChannelPtr;
- for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
- for (ByteLane = 0; ByteLane < ((NBPtr->MCTPtr->Status[SbEccDimms] && NBPtr->IsSupported[EccByteTraining]) ? 9 : 8); ByteLane++) {
- RcvEnDly = ChannelPtr->RcvEnDlys[Dimm * MAX_DELAYS + ByteLane];
- if (RcvEnDly > MaxDly) {
- MaxDly = RcvEnDly;
- MaxDlyDimm = Dimm;
- }
- }
- }
- NBPtr->SwitchDCT (NBPtr, 0);
- }
-
- TechPtr->MaxDlyForMaxRdLat = MaxDly;
- *ChipSel = (MaxDlyDimm * 2);
- return RetVal;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function finds the DIMM that has the largest receiver enable delay + Read DQS Delay.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[out] *ChipSel - Pointer to the Chip select that has the largest receiver enable delay
- * + Read DQS Delay.
- *
- * @return TRUE - A chip select can be found.
- * @return FALSE - A chip select cannot be found.
- */
-
-BOOLEAN
-MemTFindMaxRcvrEnDlyRdDqsDlyByte (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- OUT UINT8 *ChipSel
- )
-{
- UINT8 Dimm;
- UINT8 ByteLane;
- UINT16 RcvEnDly;
- UINT16 RdDqsDly;
- UINT16 TotalDly;
- UINT16 MaxDly;
- UINT8 MaxDlyDimm;
- BOOLEAN RetVal;
-
- MEM_NB_BLOCK *NBPtr;
- CH_DEF_STRUCT *ChannelPtr;
-
- NBPtr = TechPtr->NBPtr;
- ChannelPtr = NBPtr->ChannelPtr;
-
- RetVal = FALSE;
- MaxDly = 0;
- MaxDlyDimm = 0;
- for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
- if ((NBPtr->DCTPtr->Timings.CsTrainFail & ((UINT16) 3 << (Dimm << 1))) == 0) {
- // Only choose the dimm that does not fail training
- for (ByteLane = 0; ByteLane < MAX_BYTELANES; ByteLane++) {
- RcvEnDly = ChannelPtr->RcvEnDlys[Dimm * MAX_DELAYS + ByteLane];
- // Before Dqs Position Training, this value is 0. So the maximum value for
- // RdDqsDly needs to be added later when calculating the MaxRdLatency value
- // after RcvEnDly training but before DQS Position Training.
- RdDqsDly = ChannelPtr->RdDqsDlys[Dimm * MAX_DELAYS + ByteLane];
- TotalDly = RcvEnDly + (RdDqsDly >> 1);
- if (TotalDly > MaxDly) {
- MaxDly = TotalDly;
- MaxDlyDimm = Dimm;
- RetVal = TRUE;
- }
- }
- }
- }
-
- TechPtr->MaxDlyForMaxRdLat = MaxDly;
- *ChipSel = (MaxDlyDimm * 2);
- return RetVal;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function compares test pattern with data in buffer and return a pass/fail bitmap
- * for 8 Bytes for optimized receiver enable training
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] Buffer[] - Buffer data from DRAM (Measured data from DRAM) to compare
- * @param[in] Pattern[] - Pattern (Expected data in ROM/CACHE) to compare against
- * @param[in] Side - current side being targeted
- * @param[in] Receiver - Current receiver value
- * @param[in] Side1En - Indicates if the second side of the DIMM is being used
- * @return PASS - Bit map of results of comparison
- */
-
-UINT16
-STATIC
-MemTCompare1ClPatternOptByte (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Buffer[],
- IN UINT8 Pattern[],
- IN UINT8 Side,
- IN UINT8 Receiver,
- IN BOOLEAN Side1En
- )
-{
- UINT16 i;
- UINT16 j;
- UINT16 Pass;
- DIE_STRUCT *MCTPtr;
- CH_DEF_STRUCT *ChannelPtr;
-
- ASSERT (Receiver < MAX_CS_PER_CHANNEL);
- ChannelPtr = TechPtr->NBPtr->ChannelPtr;
- MCTPtr = TechPtr->NBPtr->MCTPtr;
-
- if (MCTPtr->GangedMode && MCTPtr->Dct) {
- j = 8;
- } else {
- j = 0;
- }
-
- Pass = 0xFFFF;
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tDelay[BL] -");
- for (i = 0; i < 8; i++) {
- IDS_HDT_CONSOLE (MEM_FLOW, " %02x", TechPtr->RcvrEnDlyOpt[i] & 0xFF);
- if (Buffer[j] != Pattern[j]) {
- // if bytelane n fails
- Pass &= ~((UINT16)1 << (j % 8)); // clear bit n
- TechPtr->DqsRcvEnFirstPassValOpt[i] = 0;
- TechPtr->GetFirstPassValOpt[i] = FALSE;
- TechPtr->IncBy1ForNextCountOpt[i] = FALSE;
- TechPtr->DqsRcvEnSavedOpt[i] = FALSE;
- if (TechPtr->FilterStatusOpt[i] != DONE_FILTER) {
- if (Side == ((Side1En ? 4 : 2) - 1)) {
- TechPtr->RcvrEnDlyOpt[i] += FILTER_FIRST_STAGE_COUNT;
- }
- }
- } else {
- if (TechPtr->FilterSidePassCountOpt[i] == ((Side1En ? 4 : 2) - 1)) {
- //Only apply filter if all sides have passed
- if (TechPtr->FilterStatusOpt[i] != DONE_FILTER) {
- if (TechPtr->GetFirstPassValOpt[i] == FALSE) {
- // This is the first Pass, mark the start of filter check
- TechPtr->DqsRcvEnFirstPassValOpt[i] = TechPtr->RcvrEnDlyOpt[i];
- TechPtr->GetFirstPassValOpt[i] = TRUE;
- TechPtr->IncBy1ForNextCountOpt[i] = FALSE;
- TechPtr->RcvrEnDlyOpt[i]++;
- } else {
- if ((TechPtr->RcvrEnDlyOpt[i] - TechPtr->DqsRcvEnFirstPassValOpt[i]) < FILTER_WINDOW_SIZE) {
- if (TechPtr->IncBy1ForNextCountOpt[i] == FALSE) {
- TechPtr->RcvrEnDlyOpt[i] += FILTER_SECOND_STAGE_COUNT;
- TechPtr->IncBy1ForNextCountOpt[i] = TRUE;
- } else {
- TechPtr->RcvrEnDlyOpt[i]++;
- TechPtr->IncBy1ForNextCountOpt[i] = FALSE;
- }
- } else {
- // End sweep and add offset to first pass
- TechPtr->MaxRcvrEnDlyBlOpt[i] = TechPtr->DqsRcvEnFirstPassValOpt[i];
- TechPtr->RcvrEnDlyOpt[i] = TechPtr->DqsRcvEnFirstPassValOpt[i] + FILTER_OFFSET_VALUE;
- TechPtr->FilterStatusOpt[i] = DONE_FILTER;
- TechPtr->FilterCountOpt++;
- }
- }
- } else {
- TechPtr->FilterSidePassCountOpt[i]++;
- }
- } else {
- if (TechPtr->GetFirstPassValOpt[i] == FALSE) {
- if (Side == ((Side1En ? 4 : 2) - 1)) {
- TechPtr->RcvrEnDlyOpt[i] += FILTER_FIRST_STAGE_COUNT;
- }
- }
- TechPtr->FilterSidePassCountOpt[i]++;
- }
- TechPtr->DqsRcvEnSavedOpt[i] = TRUE;
- ChannelPtr->RcvEnDlys[(Receiver >> 1) * MAX_DELAYS + i] = TechPtr->RcvrEnDlyOpt[i];
- }
- if (Side == ((Side1En ? 4 : 2) - 1)) {
- TechPtr->FilterSidePassCountOpt[i] = 0;
- }
- if (TechPtr->RcvrEnDlyOpt[i] >= TechPtr->RcvrEnDlyLimitOpt[i]) {
- TechPtr->FilterCountOpt++;
- }
-
- j++;
- }
-
- IDS_HDT_CONSOLE_DEBUG_CODE (
- IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\tPass/Fail -");
- for (i = 0, j -= 8; i < 8; i++, j++) {
- IDS_HDT_CONSOLE (MEM_FLOW, " %c", (Buffer[j] == Pattern[j]) ? 'P' : '.');
- }
- IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t Measured -");
- for (i = 0, j -= 8; i < 8; i++, j++) {
- IDS_HDT_CONSOLE (MEM_FLOW, " %02x", Buffer[j]);
- }
- IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t Expected -");
- for (i = 0, j -= 8; i < 8; i++, j++) {
- IDS_HDT_CONSOLE (MEM_FLOW, " %02x", Pattern[j]);
- }
- IDS_HDT_CONSOLE (MEM_FLOW, "\n\n");
- );
-
- return Pass;
-}
-/*-----------------------------------------------------------------------------
- *
- * This function initializes variables for optimized training.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * ----------------------------------------------------------------------------
- */
-VOID
-MemTInitializeVariablesOptByte (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT8 ByteLane;
- for (ByteLane = 0; ByteLane < MAX_BYTELANES_PER_CHANNEL; ByteLane++) {
- TechPtr->RcvrEnDlyLimitOpt[ByteLane] = FILTER_MAX_REC_EN_DLY_VALUE; // @attention - limit depends on proc type
- TechPtr->DqsRcvEnSavedOpt[ByteLane] = FALSE;
- TechPtr->RcvrEnDlyOpt[ByteLane] = FILTER_NEW_RECEIVER_START_VALUE;
- TechPtr->GetFirstPassValOpt[ByteLane] = FALSE;
- TechPtr->DqsRcvEnFirstPassValOpt[ByteLane] = 0;
- TechPtr->RevertPassValOpt[ByteLane] = FALSE;
- TechPtr->MaxRcvrEnDlyBlOpt[ByteLane] = 0;
- TechPtr->FilterStatusOpt[ByteLane] = START_FILTER;
- TechPtr->FilterCountOpt = 0;
- TechPtr->FilterSidePassCountOpt[ByteLane] = 0;
- TechPtr->IncBy1ForNextCountOpt[ByteLane] = FALSE;
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function loads the DqsRcvEnDly from saved data and program to additional index
- * for optimized DQS receiver enabled training
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] Receiver - Current Chip select value
- *
- */
-
-VOID
-STATIC
-MemTLoadRcvrEnDlyOptByte (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Receiver
- )
-{
- UINT8 i;
- UINT8 Dimm;
- CH_DEF_STRUCT *ChannelPtr;
-
- ASSERT (Receiver < MAX_CS_PER_CHANNEL);
- ChannelPtr = TechPtr->NBPtr->ChannelPtr;
-
- Dimm = Receiver >> 1;
- for (i = 0; i < 8; i++) {
- if (TechPtr->DqsRcvEnSavedOpt[i]) {
- TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Receiver >> 1, i),
- ChannelPtr->RcvEnDlys[Dimm * MAX_DELAYS + i]);
- }
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function programs DqsRcvEnDly to additional index for DQS receiver enabled training
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] Receiver - Current Chip select value
- * @param[in] RcvEnDly - receiver enable delay to be saved
- */
-
-VOID
-STATIC
-MemTSetRcvrEnDlyOptByte (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Receiver,
- IN UINT16 RcvEnDly
- )
-{
- UINT8 ByteLane;
-
- ASSERT (Receiver < MAX_CS_PER_CHANNEL);
-
- for (ByteLane = 0; ByteLane < 8; ByteLane++) {
- if (TechPtr->FilterStatusOpt[ByteLane] != DONE_FILTER) {
- TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Receiver >> 1, ByteLane), TechPtr->RcvrEnDlyOpt[ByteLane]);
- }
- }
-}
-/*-----------------------------------------------------------------------------
- *
- * This sets any Errors generated from Dly sweep
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] DCT - current DCT
- * @param[in] Receiver - current receiver
- *
- * @return FALSE - Fatal error occurs.
- * @return TRUE - No fatal error occurs.
- * ----------------------------------------------------------------------------
- */
-BOOLEAN
-MemTSetSweepErrorOptByte (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Receiver,
- IN UINT8 Dct,
- IN BOOLEAN ErrorCheck
- )
-{
- UINT8 ByteLane;
- MEM_DATA_STRUCT *MemPtr;
- DIE_STRUCT *MCTPtr;
- DCT_STRUCT *DCTPtr;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
- MemPtr = NBPtr->MemPtr;
- MCTPtr = NBPtr->MCTPtr;
- DCTPtr = NBPtr->DCTPtr;
- for (ByteLane = 0; ByteLane < MAX_BYTELANES_PER_CHANNEL; ByteLane++) {
- if (TechPtr->RcvrEnDlyOpt[ByteLane] == TechPtr->RcvrEnDlyLimitOpt[ByteLane]) {
- // no passing window
- if (ErrorCheck) {
- return FALSE;
- }
- PutEventLog (AGESA_ERROR, MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, ByteLane, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_ERROR, MCTPtr);
- }
- if (TechPtr->RcvrEnDlyOpt[ByteLane] > (TechPtr->RcvrEnDlyLimitOpt[ByteLane] - 1)) {
- // passing window too narrow, too far delayed
- if (ErrorCheck) {
- return FALSE;
- }
- PutEventLog (AGESA_ERROR, MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, ByteLane, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_ERROR, MCTPtr);
- DCTPtr->Timings.CsTrainFail |= (UINT16) (3 << Receiver) & DCTPtr->Timings.CsPresent;
- MCTPtr->ChannelTrainFail |= (UINT32)1 << Dct;
- if (!NBPtr->MemPtr->ErrorHandling (MCTPtr, NBPtr->Dct, DCTPtr->Timings.CsTrainFail, &MemPtr->StdHeader)) {
- return FALSE;
- }
- }
- }
- return TRUE;
-}
-
-/*-----------------------------------------------------------------------------
- *
- * This function determines the maximum receiver delay value
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @retval MaxRcvrValue - Maximum receiver delay value for all bytelanes
- * ----------------------------------------------------------------------------
- */
-
-UINT16
-MemTGetMaxValueOptByte (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT8 ByteLane;
- UINT16 MaxRcvrValue;
- MaxRcvrValue = 0;
- for (ByteLane = 0; ByteLane < MAX_BYTELANES_PER_CHANNEL; ByteLane++) {
- if (TechPtr->MaxRcvrEnDlyBlOpt[ByteLane] > MaxRcvrValue) {
- MaxRcvrValue = TechPtr->MaxRcvrEnDlyBlOpt[ByteLane];
- }
- }
- MaxRcvrValue += FILTER_OFFSET_VALUE;
- return MaxRcvrValue;
-}
-/*-----------------------------------------------------------------------------
- *
- * This function determines if the sweep loop should complete.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @retval TRUE - All bytelanes pass
- * FALSE - Some bytelanes fail
- * ----------------------------------------------------------------------------
- */
-
-BOOLEAN
-MemTCheckRcvrEnDlyLimitOptByte (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- if (TechPtr->FilterCountOpt >= (UINT16)MAX_CS_PER_CHANNEL) {
- return TRUE;
- } else {
- return FALSE;
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function load the result of write levelization training into RcvrEnDlyOpt,
- * using it as the initial value for Receiver DQS training.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] Receiver - Current Chip select value
- */
-VOID
-STATIC
-MemTLoadInitialRcvEnDlyOptByte (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Receiver
- )
-{
- UINT8 ByteLane;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
- for (ByteLane = 0; ByteLane < MAX_BYTELANES_PER_CHANNEL; ByteLane++) {
- TechPtr->RcvrEnDlyOpt[ByteLane] = NBPtr->ChannelPtr->WrDqsDlys[((Receiver >> 1) * TechPtr->DlyTableWidth ()) + ByteLane];
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Tech/mttecc.c b/src/vendorcode/amd/agesa/Proc/Mem/Tech/mttecc.c
deleted file mode 100644
index 01d5c29..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Tech/mttecc.c
+++ /dev/null
@@ -1,209 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mttecc.c
- *
- * Technology ECC byte support
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "mu.h"
-#include "mt.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_TECH_MTTECC_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-VOID
-STATIC
-MemTCalcDQSEccTmg (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Dimm,
- IN UINT8 Type,
- IN OUT VOID *DlyArray
- );
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the DQS ECC timings
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemTSetDQSEccTmgs (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT8 Dct;
- UINT8 Dimm;
- UINT8 i;
-
- MEM_NB_BLOCK *NBPtr;
- CH_DEF_STRUCT *ChannelPtr;
-
- NBPtr = TechPtr->NBPtr;
- if (NBPtr->MCTPtr->NodeMemSize) {
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
- ChannelPtr = NBPtr->ChannelPtr;
- for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
- if (NBPtr->DCTPtr->Timings.CsEnabled & ((UINT16)1 << (Dimm * 2))) {
- i = Dimm * TechPtr->DlyTableWidth ();
- MemTCalcDQSEccTmg (TechPtr, Dimm, AccessRcvEnDly, &ChannelPtr->RcvEnDlys[i]);
- MemTCalcDQSEccTmg (TechPtr, Dimm, AccessRdDqsDly, &ChannelPtr->RdDqsDlys[i]);
- MemTCalcDQSEccTmg (TechPtr, Dimm, AccessWrDatDly, &ChannelPtr->WrDatDlys[i]);
- }
- }
- }
- }
- }
- return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function calculates the DQS ECC timings
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] Dimm - Dimm number
- * @param[in] Type - Type of DQS timing
- * @param[in,out] *DlyArray - Pointer to the array of delays per this Dimm
- *
- */
-
-VOID
-STATIC
-MemTCalcDQSEccTmg (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Dimm,
- IN UINT8 Type,
- IN OUT VOID *DlyArray
- )
-{
- UINT8 i;
- UINT8 j;
- UINT8 Scale;
- UINT8 EccByte;
- UINT16 ByteiDly;
- UINT16 BytejDly;
- UINT16 EccDly;
- MEM_NB_BLOCK *NBPtr;
- CH_DEF_STRUCT *ChannelPtr;
-
- NBPtr = TechPtr->NBPtr;
- ChannelPtr = NBPtr->ChannelPtr;
-
- EccByte = TechPtr->MaxByteLanes ();
- i = (UINT8) (ChannelPtr->DctEccDqsLike & 0xFF);
- j = (UINT8) (ChannelPtr->DctEccDqsLike >> 8);
- Scale = ChannelPtr->DctEccDqsScale;
-
- if (Type == AccessRcvEnDly) {
- ByteiDly = ((UINT16 *) DlyArray)[i];
- BytejDly = ((UINT16 *) DlyArray)[j];
- } else {
- ByteiDly = ((UINT8 *) DlyArray)[i];
- BytejDly = ((UINT8 *) DlyArray)[j];
- }
-
- if (BytejDly > ByteiDly) {
- EccDly = ByteiDly + (UINT8) (((UINT16) (BytejDly - ByteiDly) * Scale + 0x77) / 0xFF);
- // Round up --^
- } else {
- EccDly = BytejDly + (UINT8) (((UINT16) (ByteiDly - BytejDly) * (0xFF - Scale) + 0x77) / 0xFF);
- // Round up --^
- }
-
- if (Type == AccessRcvEnDly) {
- ((UINT16 *) DlyArray)[EccByte] = EccDly;
- } else {
- ((UINT8 *) DlyArray)[EccByte] = (UINT8) EccDly;
- }
- NBPtr->SetTrainDly (NBPtr, Type, DIMM_BYTE_ACCESS (Dimm, EccByte), EccDly);
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Tech/mtthrc.c b/src/vendorcode/amd/agesa/Proc/Mem/Tech/mtthrc.c
deleted file mode 100644
index ecfa3db..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Tech/mtthrc.c
+++ /dev/null
@@ -1,306 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mtthrc.c
- *
- * Phy assisted DQS receiver enable training
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech)
- * @e \$Revision: 38442 $ @e \$Date: 2010-09-24 06:39:57 +0800 (Fri, 24 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "mu.h"
-#include "mt.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_TECH_MTTHRC_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-VOID
-STATIC
-MemTProgramRcvrEnDly (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 ChipSel,
- IN UINT8 Pass
- );
-
-BOOLEAN
-STATIC
-MemTDqsTrainRcvrEnHw (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Pass
- );
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-extern UINT16 T1minToFreq[];
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function executes first pass of Phy assisted receiver enable training
- * for current node at DDR800 and below.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @pre Auto refresh and ZQCL must be disabled
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-BOOLEAN
-MemTDqsTrainRcvrEnHwPass1 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- return MemTDqsTrainRcvrEnHw (TechPtr, 1);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function executes second pass of Phy assisted receiver enable training
- * for current node at DDR1066 and above.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @pre Auto refresh and ZQCL must be disabled
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-BOOLEAN
-MemTDqsTrainRcvrEnHwPass2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- // If current speed is higher than start-up speed, do second pass of WL
- if (TechPtr->NBPtr->DCTPtr->Timings.Speed > TechPtr->NBPtr->StartupSpeed) {
- return MemTDqsTrainRcvrEnHw (TechPtr, 2);
- }
- return TRUE;
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function executes Phy assisted receiver enable training for current node.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] Pass - Pass of the receiver training
- *
- * @pre Auto refresh and ZQCL must be disabled
- *
- */
-BOOLEAN
-STATIC
-MemTDqsTrainRcvrEnHw (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Pass
- )
-{
- MEM_NB_BLOCK *NBPtr;
- UINT32 TestAddrRJ16;
- UINT8 Dct;
- UINT8 ChipSel;
- NBPtr = TechPtr->NBPtr;
-
- TechPtr->TrainingType = TRN_RCVR_ENABLE;
-
- AGESA_TESTPOINT (TpProcMemReceiverEnableTraining , &(NBPtr->MemPtr->StdHeader));
- IDS_HDT_CONSOLE (MEM_STATUS, "\nStart HW RxEn training\n");
-
- // Set environment settings before training
- MemTBeginTraining (TechPtr);
- //
- // Setup hardware training engine (if applicable)
- //
- NBPtr->FamilySpecificHook[SetupHwTrainingEngine] (NBPtr, &TechPtr->TrainingType);
-
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct);
- NBPtr->SwitchDCT (NBPtr, Dct);
- //training for each rank
- for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) {
- if (NBPtr->GetSysAddr (NBPtr, ChipSel, &TestAddrRJ16)) {
- if (!(NBPtr->MCTPtr->Status[SbLrdimms]) || ((NBPtr->ChannelPtr->LrDimmPresent & ((UINT8) 1 << (ChipSel >> 1))) != 0)) {
- // 1.Prepare the DIMMs for training
- NBPtr->SetBitField (NBPtr, BFTrDimmSel, ChipSel >> 1);
-
- TechPtr->ChipSel = ChipSel;
- TechPtr->Pass = Pass;
- NBPtr->FamilySpecificHook[InitPerNibbleTrn] (NBPtr, NULL);
- for (TechPtr->TrnNibble = NIBBLE_0; TechPtr->TrnNibble <= (NBPtr->FamilySpecificHook[TrainRxEnPerNibble] (NBPtr, &ChipSel)? NIBBLE_0 : NIBBLE_1); TechPtr->TrnNibble++) {
- // 2.Prepare the phy for DQS receiver enable training.
- IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", ChipSel);
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\tTestAddr %x0000\n", TestAddrRJ16);
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t Byte: 00 01 02 03 04 05 06 07 ECC\n");
- NBPtr->MemNPrepareRcvrEnDlySeed (NBPtr);
-
- // 3.BIOS initiates the phy assisted receiver enable training
- NBPtr->SetBitField (NBPtr, BFDqsRcvTrEn, 1);
-
- // 4.BIOS begins sending out of back-to-back reads to create
- // a continuous stream of DQS edges on the DDR interface
- NBPtr->GenHwRcvEnReads (NBPtr, TestAddrRJ16);
-
- // 7.Program [DqsRcvTrEn]=0 to stop the DQS receive enable training.
- NBPtr->SetBitField (NBPtr, BFDqsRcvTrEn, 0);
-
- // 8.Get the gross and fine delay values.
- // 9.Calculate the corresponding final delay values
- MemTProgramRcvrEnDly (TechPtr, ChipSel, Pass);
- }
- }
- }
- }
- }
- // Restore environment settings after training
- MemTEndTraining (TechPtr);
- IDS_HDT_CONSOLE (MEM_FLOW, "End HW RxEn training\n\n");
-
- return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function calculates final RcvrEnDly for each rank
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] ChipSel - Rank to be trained
- * @param[in] Pass - Pass of the receiver training
- *
- */
-VOID
-STATIC
-MemTProgramRcvrEnDly (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 ChipSel,
- IN UINT8 Pass
- )
-{
- MEM_NB_BLOCK *NBPtr;
- CH_DEF_STRUCT *ChannelPtr;
- UINT8 ByteLane;
- UINT16 RcvEnDly;
- UINT16 CsPairRcvEnDly;
- UINT16 RankRcvEnDly[9];
- NBPtr = TechPtr->NBPtr;
- ChannelPtr = TechPtr->NBPtr->ChannelPtr;
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\t PRE: ");
- for (ByteLane = 0; ByteLane < (NBPtr->MCTPtr->Status[SbEccDimms] ? 9 : 8) ; ByteLane++) {
- RcvEnDly = (UINT8) NBPtr->GetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (ChipSel >> 1, ByteLane));
- IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", RcvEnDly);
-
- RcvEnDly = RcvEnDly + TechPtr->DiffSeedGrossSeedPreGross[ByteLane];
-
- // Add 1 UI to get to the midpoint of preamble
- RcvEnDly += 0x20;
- TechPtr->Bytelane = ByteLane;
- RankRcvEnDly[ByteLane] = RcvEnDly;
- if (NBPtr->FamilySpecificHook[TrainRxEnAdjustDlyPerNibble] (NBPtr, &RcvEnDly)) {
- if ((ChipSel & 1) == 1) {
- // For each rank pair on a dual-rank DIMM, compute the average value of the total delays saved during the
- // training of each rank and program the result in D18F2x[1,0]9C_x0000_00[24:10][DqsRcvEnGrossDelay,
- // DqsRcvEnFineDelay].
- CsPairRcvEnDly = ChannelPtr->RcvEnDlys[(ChipSel >> 1) * TechPtr->DlyTableWidth () + ByteLane];
- RcvEnDly = (CsPairRcvEnDly + RcvEnDly + 1) / 2;
- }
- }
- ChannelPtr->RcvEnDlys[(ChipSel >> 1) * TechPtr->DlyTableWidth () + ByteLane] = RcvEnDly;
- NBPtr->SetTrainDly (NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS ((ChipSel >> 1), ByteLane), RcvEnDly);
- }
-
- IDS_HDT_CONSOLE_DEBUG_CODE (
- IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t RxEn: ");
- for (ByteLane = 0; ByteLane < (NBPtr->MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) {
- IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", RankRcvEnDly[ByteLane]);
- }
- if (NBPtr->FamilySpecificHook[TrainRxEnGetAvgDlyPerNibble] (NBPtr, NULL)) {
- if ((ChipSel & 1) == 1) {
- IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t Avg: ");
- for (ByteLane = 0; ByteLane < (NBPtr->MCTPtr->Status[SbEccDimms] ? 9 : 8); ByteLane++) {
- IDS_HDT_CONSOLE (MEM_FLOW, "%03x ", ChannelPtr->RcvEnDlys[(ChipSel >> 1) * TechPtr->DlyTableWidth () + ByteLane]);
- }
- }
- }
- IDS_HDT_CONSOLE (MEM_FLOW, "\n\n");
- );
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Tech/mttml.c b/src/vendorcode/amd/agesa/Proc/Mem/Tech/mttml.c
deleted file mode 100644
index 06d583f..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Tech/mttml.c
+++ /dev/null
@@ -1,255 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mttml.c
- *
- * Technology Max Latency Training support
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech)
- * @e \$Revision: 38442 $ @e \$Date: 2010-09-24 06:39:57 +0800 (Fri, 24 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "mu.h"
-#include "mt.h"
-#include "merrhdl.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_TECH_MTTML_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function trains Max latency for all dies
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemTTrainMaxLatency (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT32 TestAddrRJ16;
- UINT8 Dct;
- UINT8 ChipSel;
- UINT8 *PatternBufPtr;
- UINT8 *TestBufferPtr;
- UINT16 CalcMaxLatDly;
- UINT16 MaxLatDly;
- UINT16 MaxLatLimit;
- UINT16 Margin;
- UINT16 CurTest;
- UINT16 _CL_;
- UINT8 TimesFail;
- UINT8 TimesRetrain;
- UINT16 i;
-
- MEM_DATA_STRUCT *MemPtr;
- DIE_STRUCT *MCTPtr;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
- MCTPtr = NBPtr->MCTPtr;
- MemPtr = NBPtr->MemPtr;
- TechPtr->TrainingType = TRN_MAX_READ_LATENCY;
- TimesRetrain = DEFAULT_TRAINING_TIMES;
- IDS_OPTION_HOOK (IDS_MEM_RETRAIN_TIMES, &TimesRetrain, &MemPtr->StdHeader);
-
- IDS_HDT_CONSOLE (MEM_STATUS, "\nStart MaxRdLat training\n");
- // Set environment settings before training
- AGESA_TESTPOINT (TpProcMemMaxRdLatencyTraining, &(MemPtr->StdHeader));
- MemTBeginTraining (TechPtr);
- //
- // Initialize the Training Pattern
- //
- if (AGESA_SUCCESS != NBPtr->TrainingPatternInit (NBPtr)) {
- return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
- }
- TechPtr->PatternLength = (MCTPtr->Status[Sb128bitmode]) ? 6 : 3;
- //
- // Setup hardware training engine (if applicable)
- //
- NBPtr->FamilySpecificHook[SetupHwTrainingEngine] (NBPtr, &TechPtr->TrainingType);
-
- MaxLatDly = 0;
- _CL_ = TechPtr->PatternLength;
- PatternBufPtr = TechPtr->PatternBufPtr;
- TestBufferPtr = TechPtr->TestBufPtr;
- //
- // Begin max latency training
- //
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- if (MCTPtr->Status[Sb128bitmode] && (Dct != 0)) {
- break;
- }
-
- IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct);
- NBPtr->SwitchDCT (NBPtr, Dct);
-
- if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
- if (TechPtr->FindMaxDlyForMaxRdLat (TechPtr, &ChipSel)) {
-
- if (NBPtr->GetSysAddr (NBPtr, ChipSel, &TestAddrRJ16)) {
- IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", ChipSel);
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tWrite to address: %04x0000\n", TestAddrRJ16);
-
- // Write the test patterns
- AGESA_TESTPOINT (TpProcMemMaxRdLatWritePattern, &(MemPtr->StdHeader));
- NBPtr->WritePattern (NBPtr, TestAddrRJ16, PatternBufPtr, _CL_);
-
- // Sweep max latency delays
- NBPtr->getMaxLatParams (NBPtr, TechPtr->MaxDlyForMaxRdLat, &CalcMaxLatDly, &MaxLatLimit, &Margin);
- AGESA_TESTPOINT (TpProcMemMaxRdLatStartSweep, &(MemPtr->StdHeader));
-
- TimesFail = 0;
- ERROR_HANDLE_RETRAIN_BEGIN (TimesFail, TimesRetrain)
- {
- MaxLatDly = CalcMaxLatDly;
- for (i = 0; i < (MaxLatLimit - CalcMaxLatDly); i++) {
- NBPtr->SetBitField (NBPtr, BFMaxLatency, MaxLatDly);
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tDly %3x", MaxLatDly);
- TechPtr->ResetDCTWrPtr (TechPtr, 6);
-
- AGESA_TESTPOINT (TpProcMemMaxRdLatReadPattern, &(MemPtr->StdHeader));
- NBPtr->ReadPattern (NBPtr, TestBufferPtr, TestAddrRJ16, _CL_);
- AGESA_TESTPOINT (TpProcMemMaxRdLatTestPattern, &(MemPtr->StdHeader));
- CurTest = NBPtr->CompareTestPattern (NBPtr, TestBufferPtr, PatternBufPtr, _CL_ * 64);
- NBPtr->FlushPattern (NBPtr, TestAddrRJ16, _CL_);
-
- if (NBPtr->IsSupported[ReverseMaxRdLatTrain]) {
- // Reverse training decrements MaxLatDly whenever the test passes
- // and uses the last passing MaxLatDly as left edge
- if (CurTest == 0xFFFF) {
- IDS_HDT_CONSOLE (MEM_FLOW, " P");
- if (MaxLatDly == 0) {
- break;
- } else {
- MaxLatDly--;
- }
- }
- } else {
- // Traditional training increments MaxLatDly until the test passes
- // and uses it as left edge
- if (CurTest == 0xFFFF) {
- IDS_HDT_CONSOLE (MEM_FLOW, " P");
- break;
- } else {
- MaxLatDly++;
- }
- }
- IDS_HDT_CONSOLE (MEM_FLOW, "\n");
- }// End of delay sweep
- ERROR_HANDLE_RETRAIN_END ((MaxLatDly >= MaxLatLimit), TimesFail)
- }
-
- AGESA_TESTPOINT (TpProcMemMaxRdLatSetDelay, &(MemPtr->StdHeader));
-
- if (MaxLatDly >= MaxLatLimit) {
- PutEventLog (AGESA_ERROR, MEM_ERROR_MAX_LAT_NO_WINDOW, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_ERROR, MCTPtr);
- NBPtr->DCTPtr->Timings.CsTrainFail |= NBPtr->DCTPtr->Timings.CsPresent;
- MCTPtr->ChannelTrainFail |= (UINT32)1 << Dct;
- if (!NBPtr->MemPtr->ErrorHandling (MCTPtr, NBPtr->Dct, EXCLUDE_ALL_CHIPSEL, &NBPtr->MemPtr->StdHeader)) {
- return FALSE;
- }
- } else {
- NBPtr->FamilySpecificHook[AddlMaxRdLatTrain] (NBPtr, &TestAddrRJ16);
-
- MaxLatDly = MaxLatDly + Margin;
- if (NBPtr->IsSupported[ReverseMaxRdLatTrain]) {
- MaxLatDly++; // Add 1 to get back to the last passing value
- }
- // Set final delays
- NBPtr->SetBitField (NBPtr, BFMaxLatency, MaxLatDly);
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\tFinal MaxRdLat: %03x\n", MaxLatDly);
- }
- }
- }
- }
- }
-
- // Restore environment settings after training
- MemTEndTraining (TechPtr);
- IDS_HDT_CONSOLE (MEM_FLOW, "End MaxRdLat training\n\n");
- //
- // Finalize the Pattern
- //
- NBPtr->TrainingPatternFinalize (NBPtr);
- return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Tech/mttoptsrc.c b/src/vendorcode/amd/agesa/Proc/Mem/Tech/mttoptsrc.c
deleted file mode 100644
index 5043657..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Tech/mttoptsrc.c
+++ /dev/null
@@ -1,427 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mttoptsrc.c
- *
- * New Technology Software based DQS receiver enable training
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech)
- * @e \$Revision: 38442 $ @e \$Date: 2010-09-24 06:39:57 +0800 (Fri, 24 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "mu.h"
-#include "mt.h"
-#include "merrhdl.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_TECH_MTTOPTSRC_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-STATIC
-MemTDqsTrainOptRcvrEnSw (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Pass
- );
-
-BOOLEAN
-MemTNewRevTrainingSupport (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- return TRUE;
-}
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function executes first pass of receiver enable training for all dies
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemTTrainOptRcvrEnSwPass1 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- return MemTDqsTrainOptRcvrEnSw (TechPtr, 1);
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function executes receiver enable training for a specific die
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] Pass - Pass of the receiver training
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-BOOLEAN
-STATIC
-MemTDqsTrainOptRcvrEnSw (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Pass
- )
-{
- _16BYTE_ALIGN UINT8 PatternBuffer[6 * 64];
- UINT8 TestBuffer[256];
- UINT8 *PatternBufPtr[6];
- UINT8 *TempPtr;
- UINT32 TestAddrRJ16[4];
- UINT32 TempAddrRJ16;
- UINT32 RealAddr;
- UINT16 CurTest[4];
- UINT8 Dct;
- UINT8 Receiver;
- UINT8 i;
- UINT8 TimesFail;
- UINT8 TimesRetrain;
- UINT16 RcvrEnDly;
- UINT16 MaxRcvrEnDly;
- UINT16 RcvrEnDlyLimit;
- UINT16 MaxDelayCha;
- BOOLEAN IsDualRank;
- BOOLEAN S0En;
- BOOLEAN S1En;
-
-
- MEM_DATA_STRUCT *MemPtr;
- DIE_STRUCT *MCTPtr;
- DCT_STRUCT *DCTPtr;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
- MemPtr = NBPtr->MemPtr;
- MCTPtr = NBPtr->MCTPtr;
- TechPtr->TrainingType = TRN_RCVR_ENABLE;
-
-
- TempAddrRJ16 = 0;
- TempPtr = NULL;
- MaxDelayCha = 0;
- TimesRetrain = DEFAULT_TRAINING_TIMES;
- IDS_OPTION_HOOK (IDS_MEM_RETRAIN_TIMES, &TimesRetrain, &MemPtr->StdHeader);
-
- IDS_HDT_CONSOLE (MEM_STATUS, "\nStart Optimized SW RxEn training\n");
- // Set environment settings before training
- MemTBeginTraining (TechPtr);
-
- PatternBufPtr[0] = PatternBufPtr[2] = PatternBuffer;
- // These two patterns used for first Test Address
- MemUFillTrainPattern (TestPattern0, PatternBufPtr[0], 64);
- // Second Cacheline used for Dummy Read is the inverse of
- // the first so that is is not mistaken for the real read
- MemUFillTrainPattern (TestPattern1, PatternBufPtr[0] + 64, 64);
- PatternBufPtr[1] = PatternBufPtr[3] = PatternBufPtr[0] + 128;
- // These two patterns used for second Test Address
- MemUFillTrainPattern (TestPattern1, PatternBufPtr[1], 64);
- // Second Cacheline used for Dummy Read is the inverse of
- // the first so that is is not mistaken for the real read
- MemUFillTrainPattern (TestPattern0, PatternBufPtr[1] + 64, 64);
-
- // Fill pattern for flush after every sweep
- PatternBufPtr[4] = PatternBufPtr[0] + 256;
- MemUFillTrainPattern (TestPattern3, PatternBufPtr[4], 64);
-
- // Fill pattern for initial dummy read
- PatternBufPtr[5] = PatternBufPtr[0] + 320;
- MemUFillTrainPattern (TestPattern4, PatternBufPtr[5], 64);
-
-
- // Begin receiver enable training
- AGESA_TESTPOINT (TpProcMemReceiverEnableTraining, &(MemPtr->StdHeader));
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct);
- NBPtr->SwitchDCT (NBPtr, Dct);
- DCTPtr = NBPtr->DCTPtr;
-
- // Set training bit
- NBPtr->SetBitField (NBPtr, BFDqsRcvEnTrain, 1);
-
- // Relax Max Latency before training
- NBPtr->SetMaxLatency (NBPtr, 0xFFFF);
-
- if (Pass == FIRST_PASS) {
- TechPtr->InitDQSPos4RcvrEn (TechPtr);
- }
-
- // there are four receiver pairs, loosely associated with chipselects.
- Receiver = DCTPtr->Timings.CsEnabled ? 0 : 8;
- for (; Receiver < 8; Receiver += 2) {
- S0En = NBPtr->GetSysAddr (NBPtr, Receiver, &TestAddrRJ16[0]);
- S1En = NBPtr->GetSysAddr (NBPtr, Receiver + 1, &TestAddrRJ16[2]);
- if (S0En) {
- TestAddrRJ16[1] = TestAddrRJ16[0] + BIGPAGE_X8_RJ16;
- }
- if (S1En) {
- TestAddrRJ16[3] = TestAddrRJ16[2] + BIGPAGE_X8_RJ16;
- }
- if (S0En && S1En) {
- IsDualRank = TRUE;
- } else {
- IsDualRank = FALSE;
- }
- if (S0En || S1En) {
- IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", Receiver);
-
- RcvrEnDlyLimit = 0x1FF; // @attention - limit depends on proc type
- TechPtr->DqsRcvEnSaved = 0;
- RcvrEnDly = RcvrEnDlyLimit;
- RealAddr = 0;
-
- TechPtr->GetFirstPassVal = FALSE;
- TechPtr->DqsRcvEnFirstPassVal = 0;
- TechPtr->RevertPassVal = FALSE;
- TechPtr->InitializeVariablesOpt (TechPtr);
-
- // Write the test patterns
- AGESA_TESTPOINT (TpProcMemRcvrWritePattern, &(MemPtr->StdHeader));
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tWrite to addresses: ");
- for (i = (S0En ? 0 : 2); i < (S1En ? 4 : 2); i++) {
- RealAddr = MemUSetUpperFSbase (TestAddrRJ16[i], MemPtr);
- // One cacheline of data to be tested and one of dummy data
- MemUWriteCachelines (RealAddr, PatternBufPtr[i], 2);
- // This is dummy data with a different pattern used for the first dummy read.
- MemUWriteCachelines (RealAddr + 128, PatternBufPtr[5], 1);
- IDS_HDT_CONSOLE (MEM_FLOW, " %04x0000 ", TestAddrRJ16[i]);
- }
- IDS_HDT_CONSOLE (MEM_FLOW, "\n");
-
- // Sweep receiver enable delays
- AGESA_TESTPOINT (TpProcMemRcvrStartSweep, &(MemPtr->StdHeader));
- TimesFail = 0;
- ERROR_HANDLE_RETRAIN_BEGIN (TimesFail, TimesRetrain)
- {
- TechPtr->LoadInitialRcvrEnDlyOpt (TechPtr, Receiver);
- while (!TechPtr->CheckRcvrEnDlyLimitOpt (TechPtr)) {
- AGESA_TESTPOINT (TpProcMemRcvrSetDelay, &(MemPtr->StdHeader));
- TechPtr->SetRcvrEnDlyOpt (TechPtr, Receiver, RcvrEnDly);
- // Read and compare the first beat of data
- for (i = (S0En ? 0 : 2); i < (S1En ? 4 : 2); i++) {
- AGESA_TESTPOINT (TpProcMemRcvrReadPattern, &(MemPtr->StdHeader));
- RealAddr = MemUSetUpperFSbase (TestAddrRJ16[i], MemPtr);
- //
- // Issue dummy cacheline reads
- //
- MemUReadCachelines (TestBuffer + 128, RealAddr + 128, 1);
- MemUReadCachelines (TestBuffer, RealAddr, 1);
- MemUProcIOClFlush (TestAddrRJ16[i], 2, MemPtr);
- //
- // Perform actual read which will be compared
- //
- MemUReadCachelines (TestBuffer + 64, RealAddr + 64, 1);
- AGESA_TESTPOINT (TpProcMemRcvrTestPattern, &(MemPtr->StdHeader));
- CurTest[i] = TechPtr->Compare1ClPatternOpt (TechPtr, TestBuffer + 64 , PatternBufPtr[i] + 64, i, Receiver, S1En);
- // Due to speculative execution during MemUReadCachelines, we must
- // flush one more cache line than we read.
- MemUProcIOClFlush (TestAddrRJ16[i], 4, MemPtr);
- TechPtr->ResetDCTWrPtr (TechPtr, Receiver);
-
- //
- // Swap the test pointers such that even and odd steps alternate.
- //
- if ((i % 2) == 0) {
- TempPtr = PatternBufPtr[i];
- PatternBufPtr[i] = PatternBufPtr[i + 1];
-
- TempAddrRJ16 = TestAddrRJ16[i];
- TestAddrRJ16[i] = TestAddrRJ16[i + 1];
- } else {
- PatternBufPtr[i] = TempPtr;
- TestAddrRJ16[i] = TempAddrRJ16;
- }
- }
- } // End of delay sweep
- ERROR_HANDLE_RETRAIN_END (!TechPtr->SetSweepErrorOpt (TechPtr, Receiver, Dct, TRUE), TimesFail)
- }
-
- if (!TechPtr->SetSweepErrorOpt (TechPtr, Receiver, Dct, FALSE)) {
- return FALSE;
- }
-
- TechPtr->LoadRcvrEnDlyOpt (TechPtr, Receiver); // set final delays
- //
- // Flush AA and 55 patterns by reading a dummy pattern to fill in FIFO
- //
- // Aquire a new FSBase, based on the last test address that we stored.
- RealAddr = MemUSetUpperFSbase (TempAddrRJ16, MemPtr);
- ASSERT (RealAddr != 0);
- MemUWriteCachelines (RealAddr, PatternBufPtr[4], 1);
- MemUWriteCachelines (RealAddr + 64, PatternBufPtr[4], 1);
- MemUReadCachelines (TestBuffer, RealAddr, 2);
- // Due to speculative execution during MemUReadCachelines, we must
- // flush one more cache line than we read.
- MemUProcIOClFlush (TempAddrRJ16, 3, MemPtr);
- }
- } // End while Receiver < 8
-
- // Clear training bit when done
- NBPtr->SetBitField (NBPtr, BFDqsRcvEnTrain, 0);
-
- // Set Max Latency for both channels
- MaxRcvrEnDly = TechPtr->GetMaxValueOpt (TechPtr);
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\tMaxRcvrEnDly: %03x\n", MaxRcvrEnDly);
- if (MCTPtr->GangedMode) {
- if (Dct == 0) {
- MaxDelayCha = MaxRcvrEnDly;
- } else if (MaxRcvrEnDly > MaxDelayCha) {
- NBPtr->SwitchDCT (NBPtr, 0);
- NBPtr->SetMaxLatency (NBPtr, MaxRcvrEnDly);
- }
- } else {
- NBPtr->SetMaxLatency (NBPtr, MaxRcvrEnDly);
- }
- TechPtr->ResetDCTWrPtr (TechPtr, 6);
- }
-
- // Restore environment settings after training
- MemTEndTraining (TechPtr);
- IDS_HDT_CONSOLE (MEM_FLOW, "End Optimized SW RxEn training\n\n");
- return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/*-----------------------------------------------------------------------------
- *
- * This function saves passing DqsRcvEnDly values to the stack
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] Receiver - Current Chip select value
- * @param[in] RcvEnDly - receiver enable delay to be saved
- * @param[in] cmpResultRank0 - compare result for Rank 0
- * @param[in] cmpResultRank0 - compare result for Rank 1
- *
- * @retval TRUE - All bytelanes pass
- * FALSE - Some bytelanes fail
- * ----------------------------------------------------------------------------
- */
-
-BOOLEAN
-MemTSaveRcvrEnDlyByteFilterOpt (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Receiver,
- IN UINT16 RcvEnDly,
- IN UINT16 CmpResultRank0,
- IN UINT16 CmpResultRank1
- )
-{
- UINT8 i;
- UINT8 Passed;
- UINT8 Dimm;
- CH_DEF_STRUCT *ChannelPtr;
-
- ASSERT (Receiver < MAX_CS_PER_CHANNEL);
- ChannelPtr = TechPtr->NBPtr->ChannelPtr;
-
- Passed = (UINT8) ((CmpResultRank0 & CmpResultRank1) & 0xFF);
-
- Dimm = Receiver >> 1;
-
- if (TechPtr->GetFirstPassVal && (RcvEnDly - TechPtr->DqsRcvEnFirstPassVal) >= 0x30) {
- for (i = 0; i < 8; i++) {
- ChannelPtr->RcvEnDlys[Dimm * TechPtr->DlyTableWidth () + i] = TechPtr->DqsRcvEnFirstPassVal + NEW_RECEIVER_FINAL_OFFSETVALUE;
- }
- TechPtr->DqsRcvEnSaved = 0xFF;
- }
-
- if (Passed == 0xFF) {
- if (!TechPtr->GetFirstPassVal) {
- TechPtr->DqsRcvEnFirstPassVal = RcvEnDly;
- TechPtr->GetFirstPassVal = TRUE;
- }
- return TRUE;
- } else {
- TechPtr->DqsRcvEnFirstPassVal = 0;
-
- // We have got first passing value, but later, we meet with glitch
- if (TechPtr->GetFirstPassVal) {
- TechPtr->DqsRcvEnFirstPassVal = 0xFF;
- TechPtr->GetFirstPassVal = FALSE;
- }
- return FALSE;
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/Tech/mttsrc.c b/src/vendorcode/amd/agesa/Proc/Mem/Tech/mttsrc.c
deleted file mode 100644
index 1686bac..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/Tech/mttsrc.c
+++ /dev/null
@@ -1,346 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mttsrc.c
- *
- * Technology Software based DQS receiver enable training
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech)
- * @e \$Revision: 38442 $ @e \$Date: 2010-09-24 06:39:57 +0800 (Fri, 24 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "mu.h"
-#include "mt.h"
-#include "GeneralServices.h"
-#include "merrhdl.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G1_PEICC)
-
-#define FILECODE PROC_MEM_TECH_MTTSRC_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-STATIC
-MemTDqsTrainRcvrEnSw (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Pass
- );
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function executes first pass of receiver enable training for all dies
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-
-BOOLEAN
-MemTTrainRcvrEnSwPass1 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- return MemTDqsTrainRcvrEnSw (TechPtr, 1);
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function executes receiver enable training for a specific die
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] Pass - Pass of the receiver training
- *
- * @return TRUE - No fatal error occurs.
- * @return FALSE - Fatal error occurs.
- */
-BOOLEAN
-STATIC
-MemTDqsTrainRcvrEnSw (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Pass
- )
-{
- _16BYTE_ALIGN UINT8 PatternBuffer[3 * 64];
- UINT8 TestBuffer[120];
- UINT8 *PatternBufPtr[4];
- UINT8 *TempPtr;
- UINT32 TestAddrRJ16[4];
- UINT32 TempAddrRJ16;
- UINT32 RealAddr;
- UINT16 CurTest[4];
- UINT8 Dct;
- UINT8 Receiver;
- UINT8 i;
- UINT8 TimesFail;
- UINT8 TimesRetrain;
- UINT16 RcvrEnDly;
- UINT16 MaxRcvrEnDly;
- UINT16 RcvrEnDlyLimit;
- UINT16 MaxDelayCha;
- BOOLEAN IsDualRank;
- BOOLEAN S0En;
- BOOLEAN S1En;
- UINT8 MaxFilterDly;
-
- MEM_DATA_STRUCT *MemPtr;
- DIE_STRUCT *MCTPtr;
- DCT_STRUCT *DCTPtr;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
- MemPtr = NBPtr->MemPtr;
- MCTPtr = NBPtr->MCTPtr;
- TechPtr->TrainingType = TRN_RCVR_ENABLE;
-
-
- TempAddrRJ16 = 0;
- TempPtr = NULL;
- MaxDelayCha = 0;
- MaxFilterDly = TechPtr->MaxFilterDly;
- RcvrEnDlyLimit = NBPtr->RcvrEnDlyLimit;
- TimesRetrain = DEFAULT_TRAINING_TIMES;
- IDS_OPTION_HOOK (IDS_MEM_RETRAIN_TIMES, &TimesRetrain, &MemPtr->StdHeader);
-
- IDS_HDT_CONSOLE (MEM_STATUS, "\nStart SW RxEn training\n");
- // Set environment settings before training
- MemTBeginTraining (TechPtr);
-
- PatternBufPtr[0] = PatternBufPtr[2] = PatternBuffer;
- MemUFillTrainPattern (TestPattern0, PatternBufPtr[0], 64);
- PatternBufPtr[1] = PatternBufPtr[3] = PatternBufPtr[0] + 128;
- MemUFillTrainPattern (TestPattern1, PatternBufPtr[1], 64);
-
- // Begin receiver enable training
- AGESA_TESTPOINT (TpProcMemReceiverEnableTraining, &(MemPtr->StdHeader));
- MaxRcvrEnDly = 0;
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct);
- NBPtr->SwitchDCT (NBPtr, Dct);
- DCTPtr = NBPtr->DCTPtr;
-
- // Set training bit
- NBPtr->SetBitField (NBPtr, BFDqsRcvEnTrain, 1);
-
- // Relax Max Latency before training
- NBPtr->SetMaxLatency (NBPtr, 0xFFFF);
-
- if (Pass == FIRST_PASS) {
- TechPtr->InitDQSPos4RcvrEn (TechPtr);
- }
-
- // there are four receiver pairs, loosely associated with chipselects.
- Receiver = DCTPtr->Timings.CsEnabled ? 0 : 8;
- for (; Receiver < 8; Receiver += 2) {
- TechPtr->DqsRcvEnSaved = 0;
- RcvrEnDly = RcvrEnDlyLimit;
- S0En = NBPtr->GetSysAddr (NBPtr, Receiver, &TestAddrRJ16[0]);
- S1En = NBPtr->GetSysAddr (NBPtr, Receiver + 1, &TestAddrRJ16[2]);
- if (S0En) {
- TestAddrRJ16[1] = TestAddrRJ16[0] + BIGPAGE_X8_RJ16;
- }
- if (S1En) {
- TestAddrRJ16[3] = TestAddrRJ16[2] + BIGPAGE_X8_RJ16;
- }
- if (S0En && S1En) {
- IsDualRank = TRUE;
- } else {
- IsDualRank = FALSE;
- }
-
- if (S0En || S1En) {
- IDS_HDT_CONSOLE (MEM_STATUS, "\t\tCS %d\n", Receiver);
-
- // Write the test patterns
- AGESA_TESTPOINT (TpProcMemRcvrWritePattern, &(MemPtr->StdHeader));
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tWrite to addresses: ");
- for (i = (S0En ? 0 : 2); i < (S1En ? 4 : 2); i++) {
- RealAddr = MemUSetUpperFSbase (TestAddrRJ16[i], MemPtr);
- MemUWriteCachelines (RealAddr, PatternBufPtr[i], 1);
- IDS_HDT_CONSOLE (MEM_FLOW, " %04x0000 ", TestAddrRJ16[i]);
- }
- IDS_HDT_CONSOLE (MEM_FLOW, "\n");
-
- // Initialize RcvrEnDly value and other DCT stored values
- // MCTPtr->DqsRcvEnPass = Pass ? 0xFF : 0;
-
- // Sweep receiver enable delays
- AGESA_TESTPOINT (TpProcMemRcvrStartSweep, &(MemPtr->StdHeader));
- TimesFail = 0;
- ERROR_HANDLE_RETRAIN_BEGIN (TimesFail, TimesRetrain)
- {
- for (RcvrEnDly = 0; RcvrEnDly < RcvrEnDlyLimit; RcvrEnDly++) {
- AGESA_TESTPOINT (TpProcMemRcvrSetDelay, &(MemPtr->StdHeader));
- TechPtr->SetRcvrEnDly (TechPtr, Receiver, RcvrEnDly);
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tDly %3x", RcvrEnDly);
-
- // Read and compare the first beat of data
- for (i = (S0En ? 0 : 2); i < (S1En ? 4 : 2); i++) {
- AGESA_TESTPOINT (TpProcMemRcvrReadPattern, &(MemPtr->StdHeader));
- RealAddr = MemUSetUpperFSbase (TestAddrRJ16[i], MemPtr);
- MemUReadCachelines (TestBuffer, RealAddr, 1);
- AGESA_TESTPOINT (TpProcMemRcvrTestPattern, &(MemPtr->StdHeader));
- CurTest[i] = TechPtr->Compare1ClPattern (TechPtr, TestBuffer, PatternBufPtr[i]);
- // Due to speculative execution during MemUReadCachelines, we must
- // flush one more cache line than we read.
- MemUProcIOClFlush (TestAddrRJ16[i], 2, MemPtr);
- TechPtr->ResetDCTWrPtr (TechPtr, Receiver);
-
- //
- // Swap the test pointers such that even and odd steps alternate.
- //
- if ((i % 2) == 0) {
- TempPtr = PatternBufPtr[i];
- PatternBufPtr[i] = PatternBufPtr[i + 1];
-
- TempAddrRJ16 = TestAddrRJ16[i];
- TestAddrRJ16[i] = TestAddrRJ16[i + 1];
- } else {
- PatternBufPtr[i] = TempPtr;
- TestAddrRJ16[i] = TempAddrRJ16;
- }
- }
-
- if (TechPtr->SaveRcvrEnDly (TechPtr, Receiver, RcvrEnDly, S0En ? (CurTest[0] & CurTest[1]) : 0xFFFF, S1En ? (CurTest[2] & CurTest[3]) : 0xFFFF)) {
- // if all bytelanes pass
- if (MaxRcvrEnDly < (RcvrEnDly - MaxFilterDly)) {
- MaxRcvrEnDly = RcvrEnDly - MaxFilterDly;
- }
- break;
- }
- } // End of delay sweep
- ERROR_HANDLE_RETRAIN_END ((RcvrEnDly > (RcvrEnDlyLimit - 1)), TimesFail)
- }
-
- if (RcvrEnDly == RcvrEnDlyLimit) {
- // no passing window
- PutEventLog (AGESA_ERROR, MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_ERROR, MCTPtr);
- }
-
- if (RcvrEnDly > (RcvrEnDlyLimit - 1)) {
- // passing window too narrow, too far delayed
- PutEventLog (AGESA_ERROR, MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_ERROR, MCTPtr);
- DCTPtr->Timings.CsTrainFail |= DCTPtr->Timings.CsPresent & (UINT16) (3 << Receiver);
- MCTPtr->ChannelTrainFail |= (UINT32)1 << Dct;
- if (!NBPtr->MemPtr->ErrorHandling (MCTPtr, NBPtr->Dct, DCTPtr->Timings.CsTrainFail, &NBPtr->MemPtr->StdHeader)) {
- return FALSE;
- }
- }
- }
-
- TechPtr->LoadRcvrEnDly (TechPtr, Receiver); // set final delays
- } // End while Receiver < 8
-
- // Clear training bit when done
- NBPtr->SetBitField (NBPtr, BFDqsRcvEnTrain, 0);
-
- // Set Max Latency for both channels
- MaxRcvrEnDly += 0x20; // @attention -
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\tMaxRcvrEnDly: %03x\n", MaxRcvrEnDly);
- if (MCTPtr->GangedMode) {
- if (Dct == 0) {
- MaxDelayCha = MaxRcvrEnDly;
- } else if (MaxRcvrEnDly > MaxDelayCha) {
- NBPtr->SwitchDCT (NBPtr, 0);
- NBPtr->SetMaxLatency (NBPtr, MaxRcvrEnDly);
- }
- } else {
- NBPtr->SetMaxLatency (NBPtr, MaxRcvrEnDly);
- }
- TechPtr->ResetDCTWrPtr (TechPtr, 6);
- }
-
- // Restore environment settings after training
- MemTEndTraining (TechPtr);
- IDS_HDT_CONSOLE (MEM_FLOW, "End SW RxEn training\n\n");
- return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/ma.h b/src/vendorcode/amd/agesa/Proc/Mem/ma.h
deleted file mode 100644
index c3c1fd7..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/ma.h
+++ /dev/null
@@ -1,318 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * ma.h
- *
- * ARDK common header file
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MA_H_
-#define _MA_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-
-#define MAX_CS_PER_CHANNEL 8 ///< Max CS per channel
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/** MARDK Structure*/
-typedef struct {
- UINT16 Speed; ///< Dram speed in MHz
- UINT8 Loads; ///< Number of Data Loads
- UINT32 AddrTmg; ///< Address Timing value
- UINT32 Odc; ///< Output Driver Compensation Value
-} PSCFG_ENTRY;
-
-/** MARDK Structure*/
-typedef struct {
- UINT16 Speed; ///< Dram speed in MHz
- UINT8 Loads; ///< Number of Data Loads
- UINT32 AddrTmg; ///< Address Timing value
- UINT32 Odc; ///< Output Driver Compensation Value
- UINT8 Dimms; ///< Number of Dimms
-} ADV_PSCFG_ENTRY;
-
-/** MARDK Structure for RDIMMs*/
-typedef struct {
- UINT16 Speed; ///< Dram speed in MHz
- UINT16 DIMMRankType; ///< Bitmap of Ranks //Bit0-3:DIMM0(1:SR, 2:DR, 4:QR, 0:No Dimm, 0xF:Any), Bit4-7:DIMM1, Bit8-11:DIMM2, Bit12-16:DIMM3
- UINT32 AddrTmg; ///< Address Timing value
- UINT16 RC2RC8; ///< RC2 and RC8 value //High byte: 1st pair value, Low byte: 2nd pair value
- UINT8 Dimms; ///< Number of Dimms
-} ADV_R_PSCFG_ENTRY;
-
-/** MARDK Structure*/
-typedef struct {
- UINT16 DIMMRankType; ///< Bitmap of Ranks //Bit0-3:DIMM0(1:SR, 2:DR, 4:QR, 0:No Dimm, 0xF:Any), Bit4-7:DIMM1, Bit8-11:DIMM2, Bit12-16:DIMM3
- UINT32 PhyRODTCSLow; ///< Fn2_9C 180
- UINT32 PhyRODTCSHigh; ///< Fn2_9C 181
- UINT32 PhyWODTCSLow; ///< Fn2_9C 182
- UINT32 PhyWODTCSHigh; ///< Fn2_9C 183
- UINT8 Dimms; ///< Number of Dimms
-} ADV_PSCFG_ODT_ENTRY;
-
-/** MARDK Structure for Write Levelization ODT*/
-typedef struct {
- UINT16 DIMMRankType; ///< Bitmap of Ranks //Bit0-3:DIMM0(1:SR, 2:DR, 4:QR, 0:No Dimm, 0xF:Any), Bit4-7:DIMM1, Bit8-11:DIMM2, Bit12-16:DIMM3
- UINT8 PhyWrLvOdt[MAX_CS_PER_CHANNEL/2]; ///< WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm
- UINT8 Dimms; ///< Number of Dimms
-} ADV_R_PSCFG_WL_ODT_ENTRY;
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-AGESA_STATUS
-MemAGetPsCfgDef (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- );
-
-AGESA_STATUS
-MemAGetPsCfgRDr2 (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- );
-
-AGESA_STATUS
-MemAGetPsCfgRDr3 (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- );
-
-AGESA_STATUS
-MemAGetPsCfgUDr3 (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- );
-
-AGESA_STATUS
-MemAGetPsCfgSDA2 (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- );
-
-AGESA_STATUS
-MemAGetPsCfgSDA3 (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- );
-
-AGESA_STATUS
-MemAGetPsCfgSNi3 (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- );
-
-AGESA_STATUS
-MemAGetPsCfgUNi3 (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- );
-
-AGESA_STATUS
-MemAGetPsCfgSRb3 (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- );
-
-AGESA_STATUS
-MemAGetPsCfgURb3 (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- );
-
-AGESA_STATUS
-MemAGetPsCfgSPh3 (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- );
-
-AGESA_STATUS
-MemAGetPsCfgUPh3 (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- );
-
-AGESA_STATUS
-MemAGetPsCfgUDA3 (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- );
-
-AGESA_STATUS
-MemAGetPsCfgRHy3 (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- );
-
-AGESA_STATUS
-MemAGetPsCfgUHy3 (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- );
-
-AGESA_STATUS
-MemAGetPsCfgRC32_3 (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- );
-
-AGESA_STATUS
-MemAGetPsCfgUC32_3 (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- );
-
-AGESA_STATUS
-MemAGetPsCfgSLN3 (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- );
-
-AGESA_STATUS
-MemAGetPsCfgULN3 (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- );
-
-AGESA_STATUS
-MemAGetPsCfgSON3 (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- );
-
-AGESA_STATUS
-MemAGetPsCfgUON3 (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- );
-
-AGESA_STATUS
-MemAGetPsCfgROr3 (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- );
-
-AGESA_STATUS
-MemAGetPsCfgUOr3 (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- );
-
-UINT16
-MemAGetPsRankType (
- IN CH_DEF_STRUCT *CurrentChannel
- );
-
-AGESA_STATUS
-MemRecNGetPsCfgDef (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- );
-
-UINT16
-MemRecNGetPsRankType (
- IN CH_DEF_STRUCT *CurrentChannel
- );
-
-AGESA_STATUS
-MemRecNGetPsCfgUDIMM3Nb (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- );
-
-AGESA_STATUS
-MemRecNGetPsCfgSODIMM3Nb (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- );
-
-AGESA_STATUS
-MemRecNGetPsCfgRDIMM3Nb (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- );
-
-#endif /* _MA_H_ */
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/memPage.h b/src/vendorcode/amd/agesa/Proc/Mem/memPage.h
deleted file mode 100644
index 1860f7a..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/memPage.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Create outline and references for Memory Component mainpage documentation.
- *
- * Design guides, maintenance guides, and general documentation, are
- * collected using this file onto the documentation mainpage.
- * This file contains doxygen comment blocks, only.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Documentation
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/**
- * @page memmain Memory Component Documentation
- *
- * Additional documentation for the Memory component consists of
- *
- * - Maintenance Guides:
- * - add here >>>
- * - Design Guides:
- * - add here >>>
- *
- */
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/merrhdl.h b/src/vendorcode/amd/agesa/Proc/Mem/merrhdl.h
deleted file mode 100644
index 4ea21e7..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/merrhdl.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mmerrhdl.h
- *
- * main error handling
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MMERRHDL_H_
-#define _MMERRHDL_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-#define EXCLUDE_ALL_DCT 0xFF
-#define EXCLUDE_ALL_CHIPSEL 0xFF
-
-/// default times of training
-#define DEFAULT_TRAINING_TIMES 1
-
-/// number of us to wait in parallel training
-#define PARALLEL_TRAINING_TIMEOUT 60000000
-
-/// number of us to wait in PCI space access
-#define PCI_ACCESS_TIMEOUT 10000000
-/// number of us to wait in special PCI space access which takes much longer than others
-#define SPECIAL_PCI_ACCESS_TIMEOUT 20000000
-
-/// Beginning of retrain handling, must be ended with the ending of the handling
-#define ERROR_HANDLE_RETRAIN_BEGIN(counter, limit) while (counter < limit)
-
-/// Ending of retrain handling
-#define ERROR_HANDLE_RETRAIN_END(condition, counter) \
-if (condition) { \
- counter ++; \
-} else { \
- break; \
-}
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-MemErrHandle (
- IN DIE_STRUCT *MCTPtr,
- IN UINT8 DCT,
- IN UINT16 ChipSelMask,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif /* _MMERRHDL_H_ */
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/mfParallelTraining.h b/src/vendorcode/amd/agesa/Proc/Mem/mfParallelTraining.h
deleted file mode 100644
index 9bb79e8..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/mfParallelTraining.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mfParallelTraining.h
- *
- * Header file for the parallel training feature
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-#ifndef _MFPARALLELTRAINING_H_
-#define _MFPARALLELTRAINING_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-typedef BOOLEAN (*REMOTE_NBBLOCK_CONSTRUCTOR) (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN DIE_STRUCT *MCTPtr,
- IN MEM_FEAT_BLOCK_NB *FeatPtr
-);
-
-///< This structure defines the environment on the AP for parallel training
-typedef struct _REMOTE_TRAINING_ENV {
- IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Config pointer of BSP
- IN OUT AGESA_STATUS (*GetPlatformCfg[MAX_PLATFORM_TYPES]) (struct _MEM_DATA_STRUCT *MemData, UINT8 SocketID, CH_DEF_STRUCT *CurrentChannel); ///< look-up platform info
- IN OUT BOOLEAN (*ErrorHandling)(struct _DIE_STRUCT *MCTPtr, UINT8 DCT, UINT16 ChipSelMask, AMD_CONFIG_PARAMS *StdHeader); ///< Error Handling
- IN REMOTE_NBBLOCK_CONSTRUCTOR NBBlockCtor; ///< NB Block constructor
- IN MEM_FEAT_BLOCK_NB *FeatPtr; ///< Feature block pointer
- IN UINT8 *TableBasedAlterations; ///< Point to an array of data bytes describing desired modifications to register settings
- IN PSO_TABLE *PlatformMemoryConfiguration; ///< Point to platform config table
- IN UINT32 HoleBase; ///< Used for Memtyping
- IN UINT32 UmaSize; ///< Used for Memtyping
- IN UINT16 BottomIo; ///< Used for Memtyping
- IN UINT32 SysLimit; ///< Used for Memtyping
- IN UINT8 BspSocket; ///< Socket number of BSP
- IN UINT8 BspCore; ///< Core number of BSP
- IN DIE_STRUCT DieStruct; ///< Remote copy of Die Struct
-} REMOTE_TRAINING_ENV;
-
-///< This structure defines Die information
-typedef struct _DIE_INFO {
- IN OUT UINT8 Socket; ///< Socket number
- IN OUT UINT8 Core; ///< Core number
- IN OUT BOOLEAN Training; ///< Training Flag, 1 = Training has been started on this core
-} DIE_INFO;
-
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-MemFParallelTraining (
- IN OUT REMOTE_TRAINING_ENV *EnvPtr,
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif /* _MFPARALLELTRAINING_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/mfStandardTraining.h b/src/vendorcode/amd/agesa/Proc/Mem/mfStandardTraining.h
deleted file mode 100644
index f54eb32..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/mfStandardTraining.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mfStandardTraining.h
- *
- * Feature implementation of standard function which performs memory training
- * from the BSP only
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-#ifndef _MFSTANDARDTRAINING_H_
-#define _MFSTANDARDTRAINING_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-MemFStandardTraining (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-#endif /* _MFSTANDARDTRAINING_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/mfmemclr.h b/src/vendorcode/amd/agesa/Proc/Mem/mfmemclr.h
deleted file mode 100644
index 4f1e729..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/mfmemclr.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mfmemclr.h
- *
- * Feature Functions For Memory Clear Operation
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MFMEMCLR_H_
-#define _MFMEMCLR_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-BOOLEAN
-MemFMctMemClr_Init (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemFMctMemClr_Sync (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-#endif /* _MFMEMCLR_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/mfs3.h b/src/vendorcode/amd/agesa/Proc/Mem/mfs3.h
deleted file mode 100644
index 14e9249..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/mfs3.h
+++ /dev/null
@@ -1,283 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mfS3.h
- *
- * S3 resume memory related functions.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Feat/S3)
- * @e \$Revision: 38639 $ @e \$Date: 2010-09-27 21:55:34 +0800 (Mon, 27 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MFS3_H_
-#define _MFS3_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-#define PRESELFREF 0
-#define POSTSELFREF 1
-#define DCT0 0
-#define DCT1 1
-#define DCT0_MASK 0x1
-#define DCT1_MASK 0x2
-#define DCT0_NBPSTATE_SUPPORT_MASK 0x4
-#define DCT1_NBPSTATE_SUPPORT_MASK 0x8
-#define DCT0_DDR3_MASK 0x10
-#define DCT1_DDR3_MASK 0x20
-#define NODE_WITHOUT_DIMM_MASK 0x80
-#define DCT0_ANY_DIMM_MASK 0x55
-#define DCT1_ANY_DIMM_MASK 0xAA
-#define ANY_DIMM_MASK 0xFF
-
-#define DCT_PHY_FLAG 0
-#define DCT_EXTRA_FLAG 1
-#define SET_S3_SPECIAL_OFFSET(AccessType, Dct, Offset) ((AccessType << 11) | (Dct << 10) | Offset)
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-/// struct for all the descriptor for pre exit self refresh and post exit self refresh
-typedef struct _DESCRIPTOR_GROUP {
- PCI_DEVICE_DESCRIPTOR PCIDevice[2]; ///< PCI device descriptor
- CONDITIONAL_PCI_DEVICE_DESCRIPTOR CPCIDevice[2]; ///< Conditional PCI device descriptor
- MSR_DEVICE_DESCRIPTOR MSRDevice[2]; ///< MSR device descriptor
- CONDITIONAL_MSR_DEVICE_DESCRIPTOR CMSRDevice[2]; ///< Conditional MSR device descriptor
-} DESCRIPTOR_GROUP;
-
-/// Northbridge block to be used in S3 resume and save.
-typedef struct _S3_MEM_NB_BLOCK {
- UINT8 MemS3SpecialCaseHeapSize; ///< Heap size for the special case register heap.
- struct _MEM_NB_BLOCK *NBPtr; ///< Pointer to the north bridge block.
- VOID (*MemS3ExitSelfRefReg) (MEM_NB_BLOCK *NBPtr, AMD_CONFIG_PARAMS *StdHeaderPtr); ///< S3 Exit self refresh register
- VOID (*MemS3GetConPCIMask) (MEM_NB_BLOCK *NBPtr, DESCRIPTOR_GROUP *DescriptPtr); ///< Get conditional mask for PCI register setting
- VOID (*MemS3GetConMSRMask) (MEM_NB_BLOCK *NBPtr, DESCRIPTOR_GROUP *DescriptPtr); ///< Get conditional mask for MSR register setting
- UINT16 (*MemS3GetRegLstPtr) (MEM_NB_BLOCK *NBPtr, DESCRIPTOR_GROUP *DescriptPtr); ///< Get register list pointer for both PCI and MSR register
- BOOLEAN (*MemS3Resume) (struct _S3_MEM_NB_BLOCK *S3NBPtr, UINT8 NodeID);///< Exit Self Refresh
- VOID (*MemS3RestoreScrub) (MEM_NB_BLOCK *NBPtr, UINT8 NodeID);///< Restore scrubber base
- AGESA_STATUS (*MemS3GetDeviceRegLst) (UINT32 ReigsterLstID, VOID **RegisterHeader); ///< Get register list for a device
-} S3_MEM_NB_BLOCK;
-
-/// Header for heap space to store the special case register.
-typedef struct _S3_SPECIAL_CASE_HEAP_HEADER {
- UINT8 Node; ///< Node ID for the the header
- UINT8 Offset; ///< Offset for the target node
-} S3_SPECIAL_CASE_HEAP_HEADER;
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-AGESA_STATUS
-AmdMemS3Resume (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-MemS3ResumeInitNB (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-MemS3Deallocate (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-MemFS3GetPciDeviceRegisterList (
- IN PCI_DEVICE_DESCRIPTOR *Device,
- OUT PCI_REGISTER_BLOCK_HEADER **RegisterHdr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-MemFS3GetCPciDeviceRegisterList (
- IN CONDITIONAL_PCI_DEVICE_DESCRIPTOR *Device,
- OUT CPCI_REGISTER_BLOCK_HEADER **RegisterHdr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-MemFS3GetMsrDeviceRegisterList (
- IN MSR_DEVICE_DESCRIPTOR *Device,
- OUT MSR_REGISTER_BLOCK_HEADER **RegisterHdr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-MemFS3GetCMsrDeviceRegisterList (
- IN CONDITIONAL_MSR_DEVICE_DESCRIPTOR *Device,
- OUT CMSR_REGISTER_BLOCK_HEADER **RegisterHdr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-MemFS3GetDeviceList (
- IN OUT DEVICE_BLOCK_HEADER **DeviceBlockHdrPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-MemFS3Wait10ns (
- IN UINT32 Count,
- IN OUT MEM_DATA_STRUCT *MemPtr
- );
-
-BOOLEAN
-MemNS3ResumeNb (
- IN OUT S3_MEM_NB_BLOCK *S3NBPtr,
- IN UINT8 NodeID
- );
-
-BOOLEAN
-MemNS3ResumeClientNb (
- IN OUT S3_MEM_NB_BLOCK *S3NBPtr,
- IN UINT8 NodeID
- );
-
-VOID
-MemNS3GetConPCIMaskNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT DESCRIPTOR_GROUP *DescriptPtr
- );
-
-VOID
-MemNS3GetCSRNb (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR Address,
- IN VOID *Value,
- IN OUT VOID *ConfigPtr
- );
-
-VOID
-MemNS3SetCSRNb (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR Address,
- IN OUT VOID *Value,
- IN OUT VOID *ConfigPtr
- );
-
-VOID
-MemNS3GetBitFieldNb (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR Address,
- IN OUT VOID *Value,
- IN OUT VOID *ConfigPtr
- );
-
-VOID
-MemNS3SetBitFieldNb (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR Address,
- IN OUT VOID *Value,
- IN OUT VOID *ConfigPtr
- );
-
-VOID
-MemNS3RestoreScrubNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Node
- );
-
-AGESA_STATUS
-MemS3InitNB (
- IN OUT S3_MEM_NB_BLOCK **S3NBPtr,
- IN OUT MEM_DATA_STRUCT **MemPtr,
- IN OUT MEM_MAIN_DATA_BLOCK *mmData,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-MemNS3DisNbPsDbgNb (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR Address,
- IN OUT VOID *Value,
- IN OUT VOID *ConfigPtr
- );
-
-VOID
-MemNS3EnNbPsDbg1Nb (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR Address,
- IN OUT VOID *Value,
- IN OUT VOID *ConfigPtr
- );
-
-VOID
-MemNS3SetDynModeChangeNb (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR Address,
- IN OUT VOID *Value,
- IN OUT VOID *ConfigPtr
- );
-
-VOID
-MemNS3DisableChannelNb (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR Address,
- IN OUT VOID *Value,
- IN OUT VOID *ConfigPtr
- );
-
-VOID
-MemNS3SetDisAutoCompUnb (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR Address,
- IN OUT VOID *Value,
- IN OUT VOID *ConfigPtr
- );
-
-VOID
-MemNS3SetPreDriverCalUnb (
- IN ACCESS_WIDTH AccessWidth,
- IN PCI_ADDR Address,
- IN OUT VOID *Value,
- IN OUT VOID *ConfigPtr
- );
-
-#endif //_MFS3_H_
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/mftds.h b/src/vendorcode/amd/agesa/Proc/Mem/mftds.h
deleted file mode 100644
index c193999..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/mftds.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mftds.h
- *
- * Memory Controller
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-#ifndef _MFTDS_H_
-#define _MFTDS_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-VOID
-MemFInitTableDrive (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 time
- );
-#endif /* _MFTDS_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/mm.h b/src/vendorcode/amd/agesa/Proc/Mem/mm.h
deleted file mode 100644
index 6497ea3..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/mm.h
+++ /dev/null
@@ -1,1003 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mm.h
- *
- * Common main functions
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem)
- * @e \$Revision: 38634 $ @e \$Date: 2010-09-27 21:39:01 +0800 (Mon, 27 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MM_H_
-#define _MM_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-#define ALLOC_SOCKET_STRUCT_HANDLE 0
-#define ALLOC_DIE_STRUCT_HANDLE 1
-#define ALLOC_DCT_STRUCT_HANDLE 2
-#define ALLOC_CHL_STRUCT_HANDLE 3
-#define ALLOC_PLATFORM_PTR_HANDLE 4
-#define ALLOC_FORM_FACTOR_HANDLE 5
-#define ALLOC_TRN_DATA_HANDLE 6
-#define ALLOC_DIMM_DATA_HANDLE 7
-#define ALLOC_PAR_TRN_HANDLE 8
-
-#define GENERATE_MEM_HANDLE(type, x, y, z) (\
- AMD_MEM_MISC_HANDLES_START + (((type) << 18) + ((x) << 12) + ((y) << 6) + (z)) \
-)
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/// Bit field names used in memory initialization
-typedef enum {
- BFDevVendorIDReg, ///< Bit field DevVendorIDReg
- BFNodeID, ///< Bit field NodeID
- BFNodeCnt, ///< Bit field NodeCnt
-
- BFDramBaseReg0, ///< Bit field DramBaseReg0
- BFDramBaseReg1, ///< Bit field DramBaseReg1
- BFDramBaseReg2, ///< Bit field DramBaseReg2
- BFDramBaseReg3, ///< Bit field DramBaseReg3
- BFDramBaseReg4, ///< Bit field DramBaseReg4
- BFDramBaseReg5, ///< Bit field DramBaseReg5
- BFDramBaseReg6, ///< Bit field DramBaseReg6
- BFDramBaseReg7, ///< Bit field DramBaseReg7
-
- BFDramLimitReg0, ///< Bit field DramLimitReg0
- BFDramLimitReg1, ///< Bit field DramLimitReg1
- BFDramLimitReg2, ///< Bit field DramLimitReg2
- BFDramLimitReg3, ///< Bit field DramLimitReg3
- BFDramLimitReg4, ///< Bit field DramLimitReg4
- BFDramLimitReg5, ///< Bit field DramLimitReg5
- BFDramLimitReg6, ///< Bit field DramLimitReg6
- BFDramLimitReg7, ///< Bit field DramLimitReg7
-
- BFDramBaseHiReg0, ///< Bit field DramBaseHiReg0
- BFDramBaseHiReg1, ///< Bit field DramBaseHiReg1
- BFDramBaseHiReg2, ///< Bit field DramBaseHiReg2
- BFDramBaseHiReg3, ///< Bit field DramBaseHiReg3
- BFDramBaseHiReg4, ///< Bit field DramBaseHiReg4
- BFDramBaseHiReg5, ///< Bit field DramBaseHiReg5
- BFDramBaseHiReg6, ///< Bit field DramBaseHiReg6
- BFDramBaseHiReg7, ///< Bit field DramBaseHiReg7
-
- BFDramLimitHiReg0, ///< Bit field DramLimitHiReg0
- BFDramLimitHiReg1, ///< Bit field DramLimitHiReg1
- BFDramLimitHiReg2, ///< Bit field DramLimitHiReg2
- BFDramLimitHiReg3, ///< Bit field DramLimitHiReg3
- BFDramLimitHiReg4, ///< Bit field DramLimitHiReg4
- BFDramLimitHiReg5, ///< Bit field DramLimitHiReg5
- BFDramLimitHiReg6, ///< Bit field DramLimitHiReg6
- BFDramLimitHiReg7, ///< Bit field DramLimitHiReg7
-
- BFDramHoleAddrReg, ///< Bit field DramHoleAddrReg
-
- BFCSBaseAddr0Reg, ///< Bit field CSBaseAddr0Reg
- BFCSBaseAddr1Reg, ///< Bit field CSBaseAddr1Reg
- BFCSBaseAddr2Reg, ///< Bit field CSBaseAddr2Reg
- BFCSBaseAddr3Reg, ///< Bit field CSBaseAddr3Reg
- BFCSBaseAddr4Reg, ///< Bit field CSBaseAddr4Reg
- BFCSBaseAddr5Reg, ///< Bit field CSBaseAddr5Reg
- BFCSBaseAddr6Reg, ///< Bit field CSBaseAddr6Reg
- BFCSBaseAddr7Reg, ///< Bit field CSBaseAddr7Reg
-
- BFCSMask0Reg, ///< Bit field CSMask0Reg
- BFCSMask1Reg, ///< Bit field CSMask1Reg
- BFCSMask2Reg, ///< Bit field CSMask2Reg
- BFCSMask3Reg, ///< Bit field CSMask3Reg
-
- BFRankDef0, ///< Bit field RankDef 0
- BFRankDef1, ///< Bit field RankDef 1
- BFRankDef2, ///< Bit field RankDef 2
- BFRankDef3, ///< Bit field RankDef 3
-
- BFDramControlReg, ///< Bit field DramControlReg
- BFDramInitRegReg, ///< Bit field DramInitRegReg
- BFDramBankAddrReg, ///< Bit field DramBankAddrReg
- BFDramMRSReg, ///< Bit field DramMRSReg
- BFDramTimingLoReg, ///< Bit field DramTimingLoReg
- BFDramTimingHiReg, ///< Bit field DramTimingHiReg
- BFDramConfigLoReg, ///< Bit field DramConfigLoReg
- BFDramConfigHiReg, ///< Bit field DramConfigHiReg
- BFDctAddlOffsetReg, ///< Bit field DctAddlOffsetReg
- BFDctAddlDataReg, ///< Bit field DctAddlDataReg
- BFDctAccessDone, ///< Bit field DctAccessDone
- BFDctAccessError, ///< Bit field DctAccessError
- BFDctExtraOffsetReg, ///< Bit field DctExtraOffsetReg
- BFDctExtraDataReg, ///< Bit field DctExtraDataReg
- BFDctExtraAccessDone, ///< Bit field DctExtraAccessDone
- BFDramConfigMiscReg, ///< Bit field DramConfigMiscReg
- BFDramCtrlMiscReg2, ///< Bit field DramCtrlMiscReg2
- BFMctCfgHiReg, ///< Bit field MctCfgHiReg
- BFMctCfgLoReg, ///< Bit field MctCfgLoReg
- BFExtMctCfgLoReg, ///< Bit field ExtMctCfgLoReg
-
- BFDramHoleBase, ///< Bit field DramHoleBase
- BFDramHoleOffset, ///< Bit field DramHoleOffset
- BFDramMemHoistValid, ///< Bit field DramMemHoistValid
- BFDramHtHoleValid, ///< Bit field BFDramHtHoleValid - Orochi
- BFDramHoleValid, ///< Bit field DramHoleValid
- BFDramBaseAddr, ///< Bit field DramBaseAddr
- BFDramIntlvSel, ///< Bit field DramIntlvSel
- BFDramLimitAddr, ///< Bit field DramLimitAddr
- BFDramIntlvEn, ///< Bit field DramIntlvEn
- BFDctCfgSel, ///< Bit field DctCfgSel
-
- BFMcaNbCtlReg, ///< Bit field McaNbCtlReg
- BFDramEccEn, ///< Bit field DramEccEn
- BFSyncOnUcEccEn, ///< Bit field SyncOnUcEccEn
- BFEccSymbolSize, ///< Bit field EccSymbolSize
- BFMcaNbStatusLoReg, ///< Bit field McaNbStatusLoReg
- BFMcaNbStatusHiReg, ///< Bit field McaNbStatusHiReg
- BFDramScrub, ///< Bit field DramScrub
- BFL2Scrub, ///< Bit field L2Scrub
- BFDcacheScrub, ///< Bit field DcacheScrub
- BFL3Scrub, ///< Bit field L3Scrub
- BFScrubReDirEn, ///< Bit field ScrubReDirEn
- BFScrubAddrLoReg, ///< Bit field ScrubAddrLoReg
- BFScrubAddrHiReg, ///< Bit field ScrubAddrHiReg
- BFC1ClkDivisor, ///< Bit field C1ClkDivisor
- BFDisDatMsk, ///< Bit field DisDatMsk
- BFNbFid, ///< Bit field NbFid
- BFMTC1eEn, ///< Bit field MTC1eEn
- BFL3Capable, ///< Bit field L3Capable
- BFDisableL3, ///< Bit field DisableL3
- BFEnhMemProtCap, ///< Bit field EnhMemProtCap
- BFNbPsForceReq, ///< Bit field NbPsForceReq
- BFNbPsCtrlDis, ///< Bit field NbPsCtrlDis
- BFNbPsCap, ///< Bit field NbPsCap
-
- BFNonSPDHi, ///< Bit field NonSPDHi
- BFRdPtrInit, ///< Bit field RdPtrInit
- BFAltVidC3MemClkTriEn, ///< Bit field AltVidC3MemClkTriEn
- BFDqsRcvEnTrain, ///< Bit field DqsRcvEnTrain
- BFEarlyArbEn, ///< Bit field EarlyArbEn
- BFMaxLatency, ///< Bit field either MaxRdLat or MaxAsyncLat
-
- BFMrsAddress, ///< Bit field MrsAddress
- BFMrsBank, ///< Bit field MrsBank
- BFMrsChipSel, ///< Bit field MrsChipSel
- BFSendPchgAll, ///< Bit field SendPchgAll
- BFSendAutoRefresh, ///< Bit field SendAutoRefresh
- BFSendMrsCmd, ///< Bit field SendMrsCmd
- BFDeassertMemRstX, ///< Bit field DeassertMemRstX
- BFAssertCke, ///< Bit field AssertCke
- BFSendZQCmd, ///< Bit field SendZQCmd
- BFSendCtrlWord, ///< Bit field SendCtrlWord
- BFEnDramInit, ///< Bit field EnDramInit
- BFMrsLevel, ///< Bit field MrsLevel
- BFMrsQoff, ///< Bit field MrsQoff
- BFMrsAddressHi, ///< Bit field MrsAddress [17:13]
-
- BFBurstCtrl, ///< Bit field BurstCtrl
- BFDrvImpCtrl, ///< Bit field DrvImpCtrl
- BFDramTerm_DDR3, ///< Bit field DramTerm_DDR3
- BFDramTermDyn, ///< Bit field DramTermDyn
- BFQoff, ///< Bit field Qoff
- BFASR, ///< Bit field ASR
- BFSRT, ///< Bit field SRT
- BFTcwl, ///< Bit field Tcwl
- BFPchgPDModeSel, ///< Bit field PchgPDModeSel
-
- BFTwrDDR3, ///< Bit field TwrDDR3
- BFTcl, ///< Bit field Tcl
- BFTrcd, ///< Bit field Trcd
- BFTrp, ///< Bit field Trp
- BFTrtp, ///< Bit field Trtp
- BFTras, ///< Bit field Tras
- BFTrc, ///< Bit field Trc
- BFTwr, ///< Bit field Twr
- BFTrrd, ///< Bit field Trrd
- BFMemClkDis, ///< Bit field MemClkDis
- BFDramTiming0, ///< Bit field BFDramTiming0
- BFDramTiming1, ///< Bit field BFDramTiming1
- BFDramTiming2, ///< Bit field BFDramTiming2
- BFDramTiming3, ///< Bit field BFDramTiming3
- BFDramNBP0, ///< Bit field BFDramNBP0
-
- BFNonSPD, ///< Bit field NonSPD
- BFTrwtWB, ///< Bit field TrwtWB
- BFTrwtTO, ///< Bit field TrwtTO
- BFTwtr, ///< Bit field Twtr
- BFTwrrd, ///< Bit field Twrrd
- BFTwrrdHi, ///< Bit field TwrrdHi
- BFTwrwr, ///< Bit field Twrwr
- BFTwrwrHi, ///< Bit field TwrwrHi
- BFTrdrdSD, ///< Bit field TrdrdSD
- BFTwrwrSD, ///< Bit field TwrwrSD
- BFTwrrdSD, ///< Bit field TwrrdSD
- BFTmod, ///< Bit field Tmod
- BFTmrd, ///< Bit field Tmrd
- BFRdOdtTrnOnDly, ///< Bit field RdOdtTrnOnDly
- BFRdOdtOnDuration, ///< Bit field RdOdtOnDuration
- BFWrOdtTrnOnDly, ///< Bit field WrOdtTrnOnDly
- BFWrOdtOnDuration, ///< Bit field WrOdtOnDuration
- BFPrtlChPDDynDly, ///< Bit field PrtlChPDDynDly
-
- BFAggrPDDelay, ///< Bit field AggrPDDelay
- BFPchgPDEnDelay, ///< Bit field PchgPDEnDelay
-
- BFTrdrd, ///< Bit field Trdrd
- BFTrdrdHi, ///< Bit field TrdrdHi
- BFTref, ///< Bit field Tref
- BFDisAutoRefresh, ///< Bit field DisAutoRefresh
- BFTrfc0, ///< Bit field Trfc0
- BFTrfc1, ///< Bit field Trfc1
- BFTrfc2, ///< Bit field Trfc2
- BFTrfc3, ///< Bit field Trfc3
-
- BFInitDram, ///< Bit field InitDram
- BFExitSelfRef, ///< Bit field ExitSelfRef
- BFDramTerm, ///< Bit field DramTerm
- BFParEn, ///< Bit field ParEn
- BFBurstLength32, ///< Bit field BurstLength32
- BFWidth128, ///< Bit field Width128
- BFX4Dimm, ///< Bit field X4Dimm
- BFDimmEccEn, ///< Bit field DimmEccEn
- BFUnBuffDimm, ///< Bit field UnBuffDimm
- BFEnterSelfRef, ///< Bit field EnterSelfRef
- BFDynPageCloseEn, ///< Bit field DynPageCloseEn
- BFIdleCycInit, ///< Bit field IdleCycInit
- BFFreqChgInProg, ///< Bit field FreqChgInProg
- BFForceAutoPchg, ///< Bit field ForceAutoPchg
- BFStagRefEn, ///< Bit field StagRefEn
- BFPendRefPaybackS3En, ///< Bit field PendRefPaybackS3En
- BFEnDispAutoPrecharge, ///< Bit field EnDispAutoPrecharge
- BFDisDllShutdownSR, ///< Bit field DisDllShutdownSR
- BFDisSscClkGateData, ///< Bit field DisSscClkGateData
- BFDisSscClkGateCmdAddr, ///< Bit field DisSscClkGateCmdAddr
- BFDisSimulRdWr, ///< Bit field DisSimulRdWr
-
- BFMemClkFreq, ///< Bit field MemClkFreq
- BFMemClkFreqVal, ///< Bit field MemClkFreqVal
- BFDdr3Mode, ///< Bit field Ddr3Mode
- BFLegacyBiosMode, ///< Bit field LegacyBiosMode
- BFZqcsInterval, ///< Bit field ZqcsInterval
- BFRDqsEn, ///< Bit field RDqsEn
- BFDisDramInterface, ///< Bit field DisDramInterface
- BFPowerDownEn, ///< Bit field PowerDownEn
- BFPowerDownMode, ///< Bit field PowerDownMode
- BFFourRankSoDimm, ///< Bit field FourRankSoDimm
- BFDcqArbBypassEn, ///< Bit field DcqArbBypassEn
- BFFourRankRDimm, ///< Bit field FourRankRDimm
- BFSlowAccessMode, ///< Bit field SlowAccessMode
- BFBankSwizzleMode, ///< Bit field BankSwizzleMode
- BFDcqBypassMax, ///< Bit field DcqBypassMax
- BFFourActWindow, ///< Bit field FourActWindow
-
- BFODTSEn, ///< Bit field ODTSEn
- BFCmdThrottleMode, ///< Bit field CmdThrottleMode
- BFBwCapEn, ///< Bit field BwCapEn
-
- BFDdr3FourSocketCh, ///< Bit field Ddr3FourSocketCh
- BFSubMemclkRegDly, ///< Bit field SubMemclkRegDly
- BFOdtSwizzle, ///< Bit field OdtSwizzle
- BFProgOdtEn, ///< Bit field ProgOdtEn
- BFCtrlWordCS, ///< Bit field CtrlWordCS
- BFRefChCmdMgtDis, ///< Bit field RefChCmdMgtDis
- BFFastSelfRefEntryDis, ///< Bit field FastSelfRefEntryDis
- BFPrtlChPDEnhEn, ///< Bit field PrtlChPDEnhEn
- BFAggrPDEn, ///< Bit field AggrPDEn
- BFDataTxFifoWrDly, ///< Bit field DataTxFifoWrDly
- BFWrDqDqsEarly, ///< Bit field WrDqDqsEarly
- BFCSMux45, ///< Bit field CSMux45
- BFCSMux67, ///< Bit field CSMux67
- BFLrDimmMrsCtrl, ///< Bit field LrDimmMrsCtrl
- BFExtendedParityEn, ///< Bit field ExtendedParityEn
- BFLrDimmEnhRefEn, ///< Bit field LrDimmEnhRefEn
- BFCSTimingMux67, ///< Bit field CSTimingMux67
-
- BFIntLvRgnSwapEn, ///< Bit field IntLvRgnSwapEn
- BFIntLvRgnBaseAddr, ///< Bit field IntLvRgnBaseAddr
- BFIntLvRgnLmtAddr, ///< Bit field IntLvRgnLmtAddr
- BFIntLvRgnSize, ///< Bit field IntLvRgnSize
-
- BFDctSelHiRngEn, ///< Bit field DctSelHiRngEn
- BFDctSelHi, ///< Bit field DctSelHi
- BFDctSelIntLvEn, ///< Bit field DctSelIntLvEn
- BFMemClrInit, ///< Bit field MemClrInit
- BFDctGangEn, ///< Bit field DctGangEn
- BFDctDatIntLv, ///< Bit field DctDatIntLv
- BFDctSelIntLvAddr, ///< Bit field DctSelIntLvAddr
- BFDctSelIntLvAddrHi, ///< Bit field DctSelIntLvAddrHi
- BFDramEnabled, ///< Bit field DramEnabled
- BFMemClrBusy, ///< Bit field MemClrBusy
- BFMemCleared, ///< Bit field MemCleared
- BFDctSelBaseAddr, ///< Bit field DctSelBaseAddr
- BFDctSelBaseOffset, ///< Bit field DctSelBaseOffset
- BFDctSelBankSwap, ///< Bit field DctSelBankSwap
-
- BFAdapPrefMissRatio, ///< Bit field AdapPrefMissRatio
- BFAdapPrefPosStep, ///< Bit field AdapPrefPosStep
- BFAdapPrefNegStep, ///< Bit field AdapPrefNegStep
- BFCohPrefPrbLmt, ///< Bit field CohPrefPrbLmt
-
- BFPrefDramTrainDone, ///< Bit field PrefDramTrainDone
- BFWrDramTrainMode, ///< Bit field WrDramTrainMode
- BFMctPrefReqLimit, ///< Bit field MctPrefReqLimit
- BFPrefDramTrainMode, ///< Bit field PrefDramTrainMode
- BFDctWrLimit, ///< Bit field DctWrLimit
- BFMctWrLimit, ///< Bit field MctWrLimit
- BFDramTrainPdbDis, ///< Bit field DramTrainPdbDis
- BFTrainLength, ///< Bit field TrainLength
- BFRdTrainGo, ///< Bit field RdTrainGo
- BFWrTrainGo, ///< Bit field WrTrainGo
- BFWrTrainAdrPtrLo, ///< Bit field WrTrainAdrPtrLo
- BFWrTrainAdrPtrHi, ///< Bit field WrTrainAdrPtrHi
- BFWrTrainBufAddr, ///< Bit field WrTrainBufAddr
- BFWrTrainBufDat, ///< Bit field WrTrainBufDat
- BFFlushWr, ///< Bit field FlushWr
- BFFlushWrOnStpGnt, ///< Bit field FlushWrOnStpGnt
- BFPrefCpuDis, ///< Bit field PrefCpuDis
- BFPrefIoDis, ///< Bit field PrefIoDis
- BFTrainCmpSts, ///< Bit field TrainCmpSts
- BFTrainCmpSts2, ///< Bit field TrainCmpSts2
- BFTraceModeEn, ///< Bit field TraceModeEn
-
- BFAddrCmdDrvStren, ///< Bit field AddrCmdDrvStren
- BFDataDrvStren, ///< Bit field DataDrvStren
- BFCkeDrvStren, ///< Bit field CkeDrvStren
- BFCsOdtDrvStren, ///< Bit field CsOdtDrvStren
- BFClkDrvStren, ///< Bit field ClkDrvStren
- BFDqsDrvStren, ///< Bit field DqsDrvStren
- BFProcOdt, ///< Bit field ProcOdt
- BFODCControl, ///< Bit field ODCControl
- BFAddrTmgControl, ///< Bit field AddrTmgControl
- BFAddrCmdFineDelay, ///< Bit field AddrCmdFineDelay
-
- BFWrtLvTrEn, ///< Bit field WrtLvTrEn
- BFWrtLvTrMode, ///< Bit field WrtLvTrMode
- BFPhyFenceTrEn, ///< Bit field PhyFenceTrEn
- BFTrDimmSel, ///< Bit field TrDimmSel
- BFTrNibbleSel, ///< Bit field TrNibbleSel
- BFFenceTrSel, ///< Bit field FenceTrSel
- BFWrLvOdt, ///< Bit field WrLvOdt
- BFWrLvOdtEn, ///< Bit field WrLvOdtEn
- BFDqsRcvTrEn, ///< Bit field DqsRcvTrEn
- BFDisAutoComp, ///< Bit field DisAutoComp
- BFDramPhaseRecCtrlByte0to3, ///< Bit field DramPhaseRecCtrlByte0to3
- BFDramPhaseRecCtrlByte4to7, ///< Bit field DramPhaseRecCtrlByte4to7
- BFDramPhaseRecCtrlEcc, ///< Bit field BFDramPhaseRecCtrlEcc
- BFWrtLvErr, ///< Bit field WrtLvErr
- BFODTAssertionCtl, ///< Bit field ODTAssertionCtl
- BFNibbleTrainModeEn, ///< Bit field NibbleTrainModeEn
- BFRankTrainModeEn, ///< Bit field RankTrainModeEn
- BFPllMult, ///< Bit field PllMult
- BFPllDiv, ///< Bit field PllDiv
- BFDramPhyCtlReg, ///< Bit field Dram Phy Control Register
-
- BFDramPhyStatusReg, ///< Bit field DramPhyStatusReg
-
- BFD3Cmp2PCal, ///< Bit field D3Cmp2PCal
- BFD3Cmp2NCal, ///< Bit field D3Cmp2NCal
- BFD3Cmp1PCal, ///< Bit field D3Cmp1PCal
- BFD3Cmp1NCal, ///< Bit field D3Cmp1NCal
- BFD3Cmp0PCal, ///< Bit field D3Cmp0PCal
- BFD3Cmp0NCal, ///< Bit field D3Cmp0NCal
-
- BFPhyFence, ///< Bit field PhyFence
- BFODTTri, ///< Bit field ODTTri
- BFCKETri, ///< Bit field CKETri
- BFChipSelTri, ///< Bit field ChipSelTri
- BFPhyRODTCSLow, ///< Bit field PhyRODTCSLow
- BFPhyRODTCSHigh, ///< Bit field PhyRODTCSHigh
- BFPhyWODTCSLow, ///< Bit field PhyWODTCSLow
- BFPhyWODTCSHigh, ///< Bit field PhyWODTCSHigh
- BFUSPLLCtlAll, ///< Bit field USPLLCtlAll
- BFDSPLLCtlAll, ///< Bit field DSPLLCtlAll
- BFUSNibbleAlignEn, ///< Bit field USNibbleAlignEn
- BFChnLinitClkEn, ///< Bit field ChnLinitClkEn
-
- BFTSLinkSelect, ///< Bit field TSLinkSelect
- BFTS2BitLockEn, ///< Bit field TS2BitLockEn
- BFTS2En, ///< Bit field TS2En
- BFTS1En, ///< Bit field TS1En
- BFTS0LinkStarEn, ///< Bit field TS0LinkStarEn
- BFTS0En, ///< Bit field TS0En
-
- BFLinkTrainData, ///< Bit field LinkTrainData
-
- BFRstRxFifoPtrs, ///< Bit field RstRxFifoPtrs
- BFRxFifoPtrInit, ///< Bit field RxFifoPtrInit
- BFRstTxFifoPtrs, ///< Bit field RstTxFifoPtrs
- BFTxFifoPtrInit, ///< Bit field TxFifoPtrInit
-
- BFLpbkCount, ///< Bit field LpbkCount
- BFLpbkMap, ///< Bit field LpbkMap
- BFSendLpbkMaintCmd, ///< Bit field SendLpbkMaintCmd
- BFLpbkData, ///< Bit field LpbkData
-
- BFMbRdPtrEn, ///< Bit field MbRdPtrEn
- BFLnkLpBkLat, ///< Bit field LnkLpBkLat
- BFLpbkRndTripLatDone, ///< Bit field LpbkRndTripLatDone
- BFLnkLatTrainEn, ///< Bit field LnkLatTrainEn
-
- BFDsPhyReset, ///< Bit field DsPhyReset
- BFLinkReset, ///< Bit field LinkReset
-
- BFPllLockTime, ///< Bit field PllLockTime
- BFPllRegWaitTime, ///< Bit field PllRegWaitTime
- BFNclkFreqDone, ///< Bit field NclkFreqDone
- BFNbPs0NclkDiv, ///< Bit field NbPs0NclkDiv
- BFNbPs1NclkDiv, ///< Bit field NbPs1NclkDiv
- BFNbPsCsrAccSel, ///< Bit field NbPsCsrAccSel
- BFNbPsDbgEn, ///< Bit field NbPsDbgEn
-
- BFOnLineSpareControl, ///< Bit field OnLineSpareControl
- BFDdrMaxRate, ///< Bit field DdrMaxRate
-
- BFNbPstateDis, ///< Bit field NbPstateDis
- BFNbPsSel, ///< Bit field NbPsSel
- BFNbPstateCtlReg, ///< Bit field NB Pstate Control register
- BFSwNbPstateLoDis, ///< Bit field SwNbPstateLoDis
- BFNbPstateLo, ///< Bit field NbPstateLo
- BFNbPstateHi, ///< Bit field NbPstateHi
- BFNbPstateMaxVal, ///< Bit field NbPstateMaxVal
- BFCurNbPstate, ///< Bit field NbCurNbPstate
-
- BFC6Base, ///< Bit field C6Base
- BFC6DramLock, ///< Bit field C6DramLock
- BFCC6SaveEn, ///< Bit field CC6SaveEn
- BFCoreStateSaveDestNode, ///< Bit field CoreStateSaveDestNode
-
- BFRxPtrInitReq, ///< Bit field RxPtrInitReq
- BFAddrCmdTriEn, ///< Bit field AddrCmdTriEn
- BFForceCasToSlot0, ///< Bit field ForceCasToSlot0
- BFDisCutThroughMode, ///< Bit field DisCutThroughMode
- BFDbeSkidBufDis, ///< Bit field DbeSkidBufDis
- BFDbeGskMemClkAlignMode, ///< Bit field DbeGskMemClkAlignMode
- BFEnCpuSerRdBehindNpIoWr, ///< Bit field EnCpuSerRdBehindNpIoWr
- BFRxDLLWakeupTime, ///< Bit field RxDllWakeupTime
- BFRxCPUpdPeriod, ///< Bit field RxCPUpdPeriod
- BFRxMaxDurDllNoLock, ///< Bit field RxMaxDurDllNoLock
- BFTxDLLWakeupTime, ///< Bit field TxDllWakeupTime
- BFTxCPUpdPeriod, ///< Bit field TxCPUpdPeriod
- BFTxMaxDurDllNoLock, ///< Bit field TxMaxDurDllNoLock
- BFEnRxPadStandby, ///< Bit field EnRxPadStandby
- BFMaxSkipErrTrain, ///< Bit field MaxSkipErrTrain
- BFSlotSel, ///< Bit field SlotSel
- BFSlot1ExtraClkEn, ///< Bit field Slot1ExtraClkEn
-
- BFMemTempHot, ///< Bit field MemTempHot
- BFDoubleTrefRateEn, ///< Bit field DoubleTrefRateEn
-
- BFAcpiPwrStsCtrlHi, ///< Bit field BFAcpiPwrStsCtrlHi
- BFDramSrHysEn, ///< Bit field BFDramSrHysEn
- BFDramSrHys, ///< Bit field BFDramSrHys
- BFMemTriStateEn, ///< Bit field BFMemTriStateEn
- BFDramSrEn, ///< Bit field BFDramSrEn
-
- BFDeassertCke, ///< Bit field BFDeassertCke
- BFFourRankRDimm0, ///< Bit field BFFourRankRDimm0
- BFFourRankRDimm1, ///< Bit field BFFourRankRDimm1
- BFTwrwrSdSc, ///< Bit field BFTwrwrSdSc
- BFTwrwrSdDc, ///< Bit field BFTwrwrSdDc
- BFTwrwrDd, ///< Bit field BFTwrwrDd
- BFTrdrdSdSc, ///< Bit field BFTrdrdSdSc
- BFTrdrdSdDc, ///< Bit field BFTrdrdSdDc
- BFTrdrdDd, ///< Bit field BFTrdrdDd
- BFTstag0, ///< Bit field BFTstag0
- BFTstag1, ///< Bit field BFTstag1
- BFTstag2, ///< Bit field BFTstag2
- BFTstag3, ///< Bit field BFTstag3
-
- BFCmdSendInProg, ///< Bit field BFCmdSendInProg
- BFSendCmd, ///< Bit field BFSendCmd
- BFTestStatus, ///< Bit field BFTestStatus
- BFCmdTgt, ///< Bit field BFCmdTgt
- BFCmdType, ///< Bit field BFCmdType
- BFStopOnErr, ///< Bit field BFStopOnErr
- BFResetAllErr, ///< Bit field BFResetAllErr
- BFCmdTestEnable, ///< Bit field BFCmdTestEnable
- BFTgtChipSelectA, ///< Bit field BFTgtChipSelectA
- BFTgtBankA, ///< Bit field BFTgtBankA
- BFTgtAddressA, ///< Bit field BFTgtAddressA
- BFTgtChipSelectB, ///< Bit field BFTgtChipSelectB
- BFTgtBankB, ///< Bit field BFTgtBankB
- BFTgtAddressB, ///< Bit field BFTgtAddressB
- BFBubbleCnt2, ///< Bit field BFBubbleCnt2
- BFBubbleCnt, ///< Bit field BFBubbleCnt
- BFCmdStreamLen, ///< Bit field BFCmdStreamLen
- BFCmdCount, ///< Bit field BFCmdCount
- BFErrDqNum, ///< Bit field BFErrDQNum
- BFErrCnt, ///< Bit field BFErrCnt
- BFNibbleErrSts, ///< Bit field BFNibbleErrSts
- BFNibbleErr180Sts, ///< Bit field BFNibbleErr180Sts
- BFDataPrbsSeed, ///< Bit field BFDataPrbsSeed
- BFDramDqMaskLow, ///< Bit field BFDramDqMaskLow
- BFDramDqMaskHigh, ///< Bit field BFDramDqMaskHigh
- BFDramEccMask, ///< Bit field BFDramEccMask
- BFSendActCmd, ///< Bit field BFSendActCmd
- BFSendPchgCmd, ///< Bit field BFSendPchgCmd
- BFCmdChipSelect, ///< Bit field BFCmdChipSelect
- BFCmdBank, ///< Bit field BFCmdBank
- BFCmdAddress, ///< Bit field BFCmdAddress
- BFErrBeatNum, ///< Bit Field BFErrBeatNum
- BFErrCmdNum, ///< Bit field BFBFErrCmdNum
- BFDQErrLow, ///< Bit field BFDQSErrLow
- BFDQErrHigh, ///< Bit field BFDQSErrHigh
- BFEccErr, ///< Bit field BFEccErr
-
- /* Bit fields for workarounds */
- BFErr263, ///< Bit field Err263
- BFErr350, ///< Bit field Err350
- BFErr322I, ///< Bit field Err322I
- BFErr322II, ///< Bit field Err322II
- BFErratum468WorkaroundNotRequired, ///< Bit field Erratum468WorkaroundNotRequired
-
- /* Bit fields for Phy */
- BFEccDLLConf, ///< Bit field EccDLLConf
- BFProcOdtAdv, ///< Bit field ProcOdtAdv
- BFEccDLLPwrDnConf, ///< Bit field EccDLLPwrDnConf
- BFPhyPLLLockTime, ///< Bit field PhyPLLLockTime
- BFPhyDLLLockTime, ///< Bit field PhyDLLLockTime
- BFSkewMemClk, ///< Bit field SkewMemClk
- BFPhyDLLControl, ///< Bit field BFPhyDLLControl
- BFPhy0x0D080F0C, ///< Bit field BFPhy0x0D080F0C
- BFPhy0x0D080F10, ///< Bit field BFPhy0x0D080F10
- BFPhy0x0D080F11, ///< Bit field BFPhy0x0D080F11
- BFPhy0x0D088F30, ///< Bit field BFPhy0x0D088F30
- BFPhy0x0D08C030, ///< Bit field BFPhy0x0D08C030
- BFPhy0x0D082F30, ///< Bit field BFPhy0x0D082F30
- BFDiffTimingEn, ///< Bit Field DiffTimingEn
- BFFence, ///< Bit Field Fence
- BFDelay, ///< Bit Field Delay
- BFFenceValue, ///< Bit Field FenceValue
-
- BFPhy0x0D040F3E, ///< Bit field BFPhy0x0D040F3E
- BFPhy0x0D042F3E, ///< Bit field BFPhy0x0D042F3E
- BFPhy0x0D048F3E, ///< Bit field BFPhy0x0D048F3E
- BFPhy0x0D04DF3E, ///< Bit field BFPhy0x0D04DF3E
-
- BFPhyClkConfig0, ///< Bit field ClkConfig0
- BFPhyClkConfig1, ///< Bit field ClkConfig1
- BFPhyClkConfig2, ///< Bit field ClkConfig2
- BFPhyClkConfig3, ///< Bit field ClkConfig3
-
- BFPhy0x0D0F0F13, ///< Bit field BFPhy0x0D0F0F13
- BFPhy0x0D0F0F13Bit0to7, ///< Bit field BFPhy0x0D0F0F13Bit0to7
- BFPhy0x0D0F0830, ///< Bit field BFPhy0x0D0F0830
- BFPhy0x0D07812F, ///< Bit field BFPhy0x0D0F8108
-
- BFDataRxVioLvl, ///< Bit field DataRxVioLvl
- BFClkRxVioLvl, ///< Bit field ClkRxVioLvl
- BFCmdRxVioLvl, ///< Bit field CmdRxVioLvl
- BFAddrRxVioLvl, ///< Bit field AddrRxVioLvl
- BFCmpVioLvl, ///< Bit field CmpVioLvl
- BFAlwaysEnDllClks, ///< Bit field AlwaysEnDllClks
- BFPhy0x0D0FE00A, ///< Bit field Phy0x0D0FE00A
- BFPllPdMode, ///< Bit fields SelCsrPllPdMode and CsrPhySrPllPdMode
-
- BFDataFence2, ///< Bit field DataFence2
- BFClkFence2, ///< Bit field ClkFence2
- BFCmdFence2, ///< Bit field CmdFence2
- BFAddrFence2, ///< Bit field AddrFence2
-
- BFAddrCmdTri, ///< Bit field BFAddrCmdTri
- BFLowPowerDrvStrengthEn, ///< Bit field BFLowPowerDrvStrengthEn
- BFLevel, ///< Bit field Level
-
- BFDbeGskFifoNumerator, ///< Bit field DbeGskFifoNumerator
- BFDbeGskFifoDenominator, ///< Bit field DbeGskFifoDenominator
- BFDataTxFifoSchedDlyNegSlot0, ///< Bit field DataTxFifoSchedDlyNegSlot0
- BFDataTxFifoSchedDlyNegSlot1, ///< Bit field DataTxFifoSchedDlyNegSlot1
- BFDataTxFifoSchedDlySlot0, ///< Bit field DataTxFifoSchedDlySlot0
- BFDataTxFifoSchedDlySlot1, ///< Bit field DataTxFifoSchedDlySlot1
-
- BFDisablePredriverCal, ///< Bit field DisablePredriverCal
- BFDataByteTxPreDriverCal, ///< Bit field DataByteTxPreDriverCal
- BFDataByteTxPreDriverCal2Pad1, ///< Bit field DataByteTxPreDriverCal2Pad1
- BFDataByteTxPreDriverCal2Pad2, ///< Bit field DataByteTxPreDriverCal2Pad2
- BFCmdAddr0TxPreDriverCal2Pad1, ///< Bit field CmdAddr0TxPreDriverCal2Pad1
- BFCmdAddr0TxPreDriverCal2Pad2, ///< Bit field CmdAddr0TxPreDriverCal2Pad2
- BFCmdAddr1TxPreDriverCal2Pad1, ///< Bit field CmdAddr1TxPreDriverCal2Pad1
- BFCmdAddr1TxPreDriverCal2Pad2, ///< Bit field CmdAddr1TxPreDriverCal2Pad2
- BFAddrTxPreDriverCal2Pad1, ///< Bit field AddrTxPreDriverCal2Pad1
- BFAddrTxPreDriverCal2Pad2, ///< Bit field AddrTxPreDriverCal2Pad2
- BFAddrTxPreDriverCal2Pad3, ///< Bit field AddrTxPreDriverCal2Pad3
- BFAddrTxPreDriverCal2Pad4, ///< Bit field AddrTxPreDriverCal2Pad4
- BFCmdAddr0TxPreDriverCalPad0, ///< Bit field CmdAddr0TxPreDriverCalPad0
- BFCmdAddr1TxPreDriverCalPad0, ///< Bit field CmdAddr1TxPreDriverCalPad0
- BFAddrTxPreDriverCalPad0, ///< Bit field AddrTxPreDriverCalPad0
- BFClock0TxPreDriverCalPad0, ///< Bit field Clock0TxPreDriverCalPad0
- BFClock1TxPreDriverCalPad0, ///< Bit field Clock1TxPreDriverCalPad0
- BFClock2TxPreDriverCalPad0, ///< Bit field Clock2TxPreDriverCalPad0
- BFPNOdtCal, ///< Bit field P/NOdtCal
- BFPNDrvCal, ///< Bit field P/NDrvCal
- BFCalVal, ///< Bit field CalVal
-
- BFTxp, ///< Bit field Txp
- BFTxpdll, ///< Bit field Txpdll
- BFL3ScrbRedirDis, ///< Bit field L3ScrbRedirDis
- BFDQOdt03, ///< Bit field DQ Odt 0-3
- BFDQOdt47, ///< Bit field DQ Odt 4-7
-
- BFFixedErrataSkipPorFreqCap, ///< Bit field FixedErrataSkipPorFreqCap
-
- // Reserved
- BFReserved01, ///< Reserved 01
- BFReserved02, ///< Reserved 02
- BFReserved03, ///< Reserved 03
- BFReserved04, ///< Reserved 04
- BFReserved05, ///< Reserved 05
- BFReserved06, ///< Reserved 06
- BFReserved07, ///< Reserved 07
- BFReserved08, ///< Reserved 08
- BFReserved09, ///< Reserved 09
- BFReserved10, ///< Reserved 10
-
- BFReserved11, ///< Reserved 11
- BFReserved12, ///< Reserved 12
- BFReserved13, ///< Reserved 13
- BFReserved14, ///< Reserved 14
- BFReserved15, ///< Reserved 15
- BFReserved16, ///< Reserved 16
- BFReserved17, ///< Reserved 17
- BFReserved18, ///< Reserved 18
- BFReserved19, ///< Reserved 19
- BFReserved20, ///< Reserved 20
-
- BFDctSelBaseAddrReg, ///< Bit field DctSelBaseAddrReg
- BFDctSelBaseOffsetReg, ///< Bit field DctSelBaseOffsetReg
-
- /* End of accessible list --- entries below this line are for private use ------------*/
- BFEndOfList, ///< End of bit field list
-
- // Only for Table Drive Support define.
- BFRcvEnDly, ///< F2x[1,0]9C_x[2B:10] Dram DQS Receiver Enable Timing Control Registers
- BFWrDatDly, ///< F2x[1, 0]9C_x[302:301, 202:201, 102:101, 02:01] DRAM Write Data Timing [High:Low] Registers
- BFRdDqsDly, ///< F2x[1, 0]9C_x[306:305, 206:205, 106:105, 06:05] DRAM Read DQS Timing Control [High:Low] Registers
- BFWrDqsDly, ///< F2x[1, 0]9C_x[4A:30] DRAM DQS Write Timing Control Registers
- BFPhRecDly, ///< F2x[1, 0]9C_x[51:50] DRAM Phase Recovery Control Register [High:Low] Registers
-
- /* Do not define any entries beyond this point */
- BFAbsLimit ///< Beyond this point is reserved for bit field manipulation
-
-} BIT_FIELD_NAME;
-
-/// Bit field aliases
-#define BFMainPllOpFreqId BFNbFid
-#define BFRdDramTrainMode BFPrefDramTrainMode
-#define BFThrottleEn BFCmdThrottleMode
-#define BFIntlvRegionEn BFIntLvRgnSwapEn
-#define BFIntlvRegionBase BFIntLvRgnBaseAddr
-#define BFIntlvRegionLimit BFIntLvRgnLmtAddr
-#define BFRdOdtPatReg BFPhyRODTCSLow
-#define BFWrOdtPatReg BFPhyWODTCSLow
-#define BFLockDramCfg BFC6DramLock
-
-/// Bit field names per DRAM CS base address register
-typedef enum {
- BFCSEnable = 0, ///< Chip select enable
- BFSpare = 1, ///< Spare rank
- BFTestFail = 2, ///< Memory test failed
- BFOnDimmMirror = 3 ///< on-DIMM mirroring enable
-} CS_BASE_BIT_FIELD;
-
-/// Flag for exclude dimm
-typedef enum {
- NORMAL, ///< Normal mode, exclude the dimm if there is new dimm failure
- TRAINING, ///< Training mode, exclude dimms that fail during training after training is done
- END_TRAINING ///< End training mode, exclude all dimms that failed during training
-} DIMM_EXCLUDE_FLAG;
-
-#define BSP_DIE 0
-#define MAX_NODES_SUPPORTED 8 ///< Maximum number of nodes in the system.
-#define MAX_CS_PER_CHANNEL 8 ///< Max CS per channel
-#define MAX_CS_PER_DELAY 2 ///< Max Chip Select Controlled by a set of delays.
-
-#define VDDIO_DETERMINED 0xFF ///< VDDIO has been determined yet. Further processing is not needed.
-
-///
-/// MEM_SHARED_DATA
-/// This structure defines the shared data area that is used by the memory
-/// code to share data between different northbridge objects. Each substructure
-/// in the data area defines how this data area is used by a different purpose.
-///
-/// There should only be one instance of this struct created for all of the memory
-/// code to use.
-///
-typedef struct _MEM_SHARED_DATA {
-
- // System memory map data
- UINT32 CurrentNodeSysBase; ///< Base[47:16] (system address) DRAM base address for current node.
- /// Memory map data for each node
- BOOLEAN AllECC; ///< ECC support on the system
- DIMM_EXCLUDE_FLAG DimmExcludeFlag; ///< Control the exclude dimm behavior
- UINT8 VoltageMap; ///< The commonly supported voltage map in the system
-
- UINT8 TopNode; ///< Node that has its memory mapped to TOPMEM/TOPMEM2
- BOOLEAN C6Enabled; ///< TRUE if C6 is enabled
-
- /// Data structure for node map
- struct {
- BOOLEAN IsValid; ///< TRUE if this node contains memory.
- UINT32 SysBase; ///< Base[47:16] (system address) DRAM base address of this node.
- UINT32 SysLimit; ///< Base[47:16] (system address) DRAM limit address of this node.
- } NodeMap[MAX_NODES_SUPPORTED];
-
- /// Data structure for node interleave feature
- struct {
- BOOLEAN IsValid; ///< TRUE if the data in this structure is valid.
- UINT8 NodeCnt; ///< Number of nodes in the system.
- UINT32 NodeMemSize; ///< Total memory of this node.
- UINT32 Dct0MemSize; ///< Total memory of this DCT 0.
- UINT8 NodeIntlvSel; ///< Index to each node.
- } NodeIntlv;
-} MEM_SHARED_DATA;
-
-///
-/// MEM_MAIN_DATA_BLOCK
-///
-typedef struct _MEM_MAIN_DATA_BLOCK {
- struct _MEM_DATA_STRUCT *MemPtr; ///< Pointer to customer shared data
- struct _MEM_NB_BLOCK *NBPtr; ///< Pointer to array of NB Blocks
- struct _MEM_TECH_BLOCK *TechPtr; ///< Pointer to array of Tech Blocks
- struct _MEM_SHARED_DATA *mmSharedPtr; ///< Pointer to shared data area.
- UINT8 DieCount; ///< Total number of Dies installed
-} MEM_MAIN_DATA_BLOCK;
-
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*
-node: Indicates the Node
-- Value ranges from 0-7, 0xF: for all nodes
-- Size - 4 Bits
-
-dct: Indicate the DRAM Controller
-- Value is 0, 1 (0xF: apply setting to all DCTs)
-- Size - 4 Bits
-
-dimm: This values specifies which DIMM register will be applied
-- The value varies from 0 to 3, 0xF: all DIMMs
-- Size - 4 Bits
-
-attr - Indicates if the value needs to be added, subtracted, overridden or Auto (not changed)
-- 0: Do not change the current value in the register
-- 1: Use the value provided in the table to override the current value in the register (the one that AGESA initially determined)
-- 2: Add the value provided in the table as an offset to the current value in the register (the one that AGESA initially determined)
-- 3: Subtract the value provided in the table as an offset to the current value in the register (the one that AGESA initially determined)
-- Size - 2 Bits
-
-time - Indicate the timing for the register which is written.
-- 0: Write register value before Dram init
-- 1: Write register value before memory training
-- 2: Write register value after memory training
-- Size - 1 Bits
-
-bytelane: bytelane number
-- This determines specifies which bytelane register will be applied
-- Bit0 =1 - set value into Bytelane0
-- Bit1 =1 - set value into Bytelane1
-- Bit2 =1 - set value into Bytelane2
-...
-...
-- 0xFFFF: all bytelane
-- Size - 16 Bits.
-
-bfIndex: Indicate the bitfield index
-- Size - 16 Bits
-
-value - Value to be used
-- This can be an offset (sub or Add) or an override value.
-- Size - DWORD
-*/
-
-// Sample code
-// NBACCESS (MTBeforeDInit, MTNodes, MTDct0, BFCSBaseAddr5Reg, MTOverride, 0x400001),
-// NBACCESS (MTBeforeTrn, MTNodes, MTDct1, BFCSBaseAddr7Reg, MTOverride, 0xFFFFFFFF),
-// DQSACCESS (MTAfterTrn, MTNodes, MTDcts, MTDIMM0, MTBL1+MTBL2, BFRcvEnDly, MTSubtract, 2),
-// DQSACCESS (MTAfterTrn, MTNodes, MTDct1, MTDIMM1, MTBLNOECC, BFRcvEnDly, MTAdd, 1),
-
-#define ENDMEMTDS 0, 0, 0, 0, 0, 0, 0xFFFFFFFF, 0
-
-#define NBACCESS(time, node, dct, bitfield, attr, value) \
-{ (time), \
- ((node) & 0x0F) | ((dct) << 4), \
- (((attr) & 0x07) << 4) | (VT_MSK_VALUE << 7) , \
- (UINT8)((bitfield) & 0x000000FF), \
- (UINT8)(((bitfield) >> 8) & 0x000000FF), \
- (UINT8)(((bitfield) >> 16) & 0x000000FF), \
- (UINT8)(((bitfield) >> 24) & 0x000000FF), \
- 0, 0, \
- (UINT8)((value) & 0x000000FF), \
- (UINT8)(((value) >> 8) & 0x000000FF), \
- (UINT8)(((value) >> 16) & 0x000000FF), \
- (UINT8)(((value) >> 24) & 0x000000FF), \
- 0, 0, 0 \
-}
-
-#define DQSACCESS(time, node, dct, dimm, bitfield, attr, b0, b1, b2, b3, b4, b5, b6, b7, b8) \
-{ (time), \
- ((node) & 0x0F) | ((dct) << 4), \
- (((dimm) & 0x0F) | ((attr) & 0x07) << 4) | (VT_ARRAY << 7) , \
- (UINT8)((bitfield) & 0x000000FF), \
- (UINT8)(((bitfield) >> 8) & 0x000000FF), \
- (UINT8)(((bitfield) >> 16) & 0x000000FF), \
- (UINT8)(((bitfield) >> 24) & 0x000000FF), \
- (b0), (b1), (b2), (b3), (b4), (b5), (b6), (b7), (b8) \
-}
-
-/// Type of modification supported by table driven support.
-typedef enum {
- MTAuto, ///< Do not change the current value in the register
- MTOverride, ///< Use the value provided in the table to override the current value in the register
- MTSubtract, ///< Subtract the value provided in the table as an offset to the current value in the register
- MTAdd ///< Add the value provided in the table as an offset to the current value in the reg
-} MTAttr;
-
-/// Time for table driven support to make modification.
-typedef enum {
- MTAfterAutoCycTiming, ///< After Auto Cycle Timing
- MTAfterPlatformSpec, ///< After Platform Specific Configuration
- MTBeforeDInit, ///< Before Dram init
- MTBeforeTrn, ///< Before memory training
- MTAfterTrn, ///< After memory training
- MTAfterSwWLTrn, ///< After SW Based WL Training
- MTAfterHwWLTrnP1, ///< After HW Based WL Training Part 1
- MTAfterHwRxEnTrnP1, ///< After HW Based Receiver Enable Training Part 1
- MTAfterHwWLTrnP2, ///< After HW Based WL Training Part 2
- MTAfterHwRxEnTrnP2, ///< After HW Based Receiver Enable Training Part 2
- MTAfterSwRxEnTrn, ///< After SW Based Receiver Enable Training
- MTAfterDqsRwPosTrn, ///< After DQS Read/Write Position Training
- MTAfterMaxRdLatTrn, ///< After Max Read Latency Training
- MTAfterNbPstateChange, ///< After programming NB Pstate dependent registers
- MTAfterInterleave, ///< After Programming Interleave registers
- MTAfterFinalizeMCT, ///< After Finalize MCT Programming
-
- MTValidTimePointLimit, ///< Mark the upper bound of the supported time points
- MTEnd = 0xFF ///< End of enum define.
-} MTTime;
-
-/// Node on which modification should be made by table driven support.
-typedef enum {
- MTNode0, ///< Node 0.
- MTNode1, ///< Node 1.
- MTNode2, ///< Node 2.
- MTNode3, ///< Node 3.
- MTNode4, ///< Node 4.
- MTNode5, ///< Node 5.
- MTNode6, ///< Node 6.
- MTNode7, ///< Node 7.
- MTNodes = 0xF ///< all nodes
-} MTNode;
-
-/// DCT on which modification should be made by table driven support.
-typedef enum {
- MTDct0, ///< DCT 0.
- MTDct1, ///< DCT 1.
- MTDcts = 0xF, ///< all dcts
-} MTDct;
-
-/// Dimm on which modification should be made by table driven support.
-typedef enum {
- MTDIMM0, ///< Dimm 0.
- MTDIMM1, ///< Dimm 1.
- MTDIMM2, ///< Dimm 2.
- MTDIMM3, ///< Dimm 3.
- MTDIMMs = 0xF, ///< all Dimms
-} MTDIMM;
-
-/// Bytelane on which modification should be made by table driven support.
-typedef enum {
- MTBL0 = 0x1, ///< set the value into Bytelane0
- MTBL1 = 0x2, ///< set the value into Bytelane1
- MTBL2 = 0x4, ///< set the value into Bytelane2
- MTBL3 = 0x8, ///< set the value into Bytelane3
- MTBL4 = 0x10, ///< set the value into Bytelane4
- MTBL5 = 0x20, ///< set the value into Bytelane5
- MTBL6 = 0x40, ///< set the value into Bytelane6
- MTBL7 = 0x80, ///< set the value into Bytelane7
- MTBL8 = 0x100, ///< set the value into ECC
- MTBLNOECC = 0xFF, ///< all Bytelanes except ECC
- MTBLs = 0xFFFF, ///< all Bytelanes
-} MTBL;
-
-/// Values used to indicate which type of training is being done.
-typedef enum {
- TRN_RCVR_ENABLE, ///< Reciever Enable Training
- TRN_DQS_POSITION, ///< Read/Write DQS Position training
- TRN_MAX_READ_LATENCY ///< Max read Latency training
-} TRAINING_TYPE;
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-AGESA_STATUS
-MemAmdFinalize (
- IN OUT MEM_DATA_STRUCT *MemPtr
- );
-
-AGESA_STATUS
-MemSocketScan (
- IN OUT MEM_MAIN_DATA_BLOCK *mmPtr
- );
-
-VOID
-SetMemError (
- IN AGESA_STATUS Errorval,
- IN OUT DIE_STRUCT *MCTPtr
- );
-
-VOID
-AmdMemInitDataStructDefRecovery (
- IN OUT MEM_DATA_STRUCT *MemPtr
- );
-
-VOID
-MemRecDefRet (VOID);
-
-BOOLEAN
-MemRecDefTrue (VOID);
-
-VOID
-SetMemRecError (
- IN AGESA_STATUS Errorval,
- IN OUT DIE_STRUCT *MCTPtr
- );
-
-AGESA_STATUS
-memDefRetSuccess (VOID);
-
-#endif /* _MM_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/mn.h b/src/vendorcode/amd/agesa/Proc/Mem/mn.h
deleted file mode 100644
index 8a06566..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/mn.h
+++ /dev/null
@@ -1,1375 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mn.h
- *
- * Common Northbridge
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem)
- * @e \$Revision: 38303 $ @e \$Date: 2010-09-22 00:22:47 +0800 (Wed, 22 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MN_H_
-#define _MN_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-#define _4GB_RJ16 ((UINT32)4 << (30 - 16))
-#define DCT_ACCESS_WRITE (UINT32) 0x40000000
-#define MTRR_VALID 11
-#define THERMAL_OPT 31
-
-#define NB_ACCESS 0
-#define DCT_PHY_ACCESS 1
-#define DCT_EXTRA 2
-
-#define DCT_PHY_DIRECT 0xF1
-
-#define VT_MSK_VALUE 0
-#define VT_ARRAY 1
-/*---------------------------------------------
- * TSEFO - Type Start End Function Offset
- *
- * 31:30 Type of access (2-bits)
- * 29:29 Special (1-bit)
- * 28:28 Phy Direct (1-bit)
- * 27:27 Whole Register Access (1-bit)
- * 26:26 Linked (1-bit)
- * 25:21 Start bit (5-bits)
- * 20:16 End bit (5-bits)
- * 15:00 Function_Offset/Index (16-bits)
- *---------------------------------------------
- */
-typedef UINT32 TSEFO;
-
-/**
- MAKE_TSEFO(TableName, a, b, c, d, BitFieldIndex):
-
- @param[in] TableName
- @param[in] BitFieldIndex
- @param[in] a Type of access.
- @param[in] b Index of register (can be in Function_Offset format).
- @param[in] c Highest bit of the bit field.
- @param[in] d Lowest bit of the bit field.
-
- @return TSEFO Access params encrypted in TSEFO format.
---*/
-#define MAKE_TSEFO(TableName, a, b, c, d, BitFieldIndex) \
-TableName[BitFieldIndex] = ( \
- (a == DCT_PHY_DIRECT) ? ( \
- (((UINT32) DCT_PHY_ACCESS) << 30) | (((UINT32) 1) << 28) | (((UINT32) b) & 0xFFFF) | (\
- ((c == 15) && (d == 0)) ? ( \
- (((UINT32) 1) << 27) | (((UINT32) b) & 0xF0000) \
- ) : ( \
- (c >= d) ? ( \
- (((UINT32) c) << 21) | (((UINT32) d) << 16) \
- ) : ( \
- (((UINT32) d) << 21) | (((UINT32) c) << 16) \
- ) \
- ) \
- ) \
- ) : ( \
- (((UINT32) a) << 30) | (((UINT32) b) & 0xFFFFFFF) | ( \
- (((UINT32) b) >> 16) ? ( \
- (((UINT32) 1) << 29) \
- ) : ( \
- (c >= d) ? ( \
- (((UINT32) c) << 21) | (((UINT32) d) << 16) \
- ) : ( \
- (((UINT32) d) << 21) | (((UINT32) c) << 16) \
- ) \
- ) \
- ) \
- ) \
-)
-
-/**
- LINK_TSEFO(TableName, LowerBitFieldIndex, HigherBitFieldIndex):
- This is one way link: any write to LowerBitFieldIndex would write to HigherBitFieldIndex,
- but NOT the other way around.
- Requirement: LowerBitFieldIndex must be declared *right* before HigherBitFieldIndex.
-
- @param[in] TableName
- @param[in] LowerBitFieldIndex
- @param[in] HigherBitFieldIndex
-
- @return TSEFO Access params encrypted in TSEFO format.
---*/
-#define LINK_TSEFO(TableName, LowerBitFieldIndex, HigherBitFieldIndex) { \
- ASSERT (LowerBitFieldIndex == (HigherBitFieldIndex - 1)) ; \
- TableName[LowerBitFieldIndex] = TableName[LowerBitFieldIndex] | (((UINT32) 1) << 26); \
-}
-
-#define TSEFO_TYPE(x) ((UINT8) (((UINT32) (x) >> 30) & 0x03))
-#define TSEFO_START(x) ((UINT8) (((UINT32) (x) >> 21) & 0x1F))
-#define TSEFO_END(x) ((UINT8) (((UINT32) (x) >> 16) & 0x1F))
-#define TSEFO_OFFSET(x) ((UINT32) (x) & 0xFFFF)
-#define TSEFO_LINKED(x) ((UINT8) (((UINT32) (x) >> 26) & 0x01))
-#define TSEFO_DIRECT_EN(x) ((UINT8) (((UINT32) (x) >> 28) & 0x01))
-#define TSEFO_WHOLE_REG_ACCESS(x) ((UINT8) (((UINT32) (x) >> 27) & 0x01))
-#define _FN(x, y) (((UINT32) (x) << 12) + (UINT32) (y))
-#define _NOT_USED_ 0
-
-/* */
-#define B0_DLY 0
-#define B1_DLY 1
-#define B2_DLY 2
-#define B3_DLY 3
-#define B4_DLY 4
-#define B5_DLY 5
-#define B6_DLY 6
-#define B7_DLY 7
-#define ECC_DLY 8
-
-#define DDR2_TRAIN_FLOW 0
-#define DDR3_TRAIN_FLOW 1
-
-//
-// Minimum Data Eye width in consecutive 32nds of a UI of
-// valid data
-//
-#define MIN_RD_DATAEYE_WIDTH_NB 4
-#define MIN_WR_DATAEYE_WIDTH_NB 4
-
-//
-// RELIABLE READ/WRITE MODE DEFINITIONS
-//
-#define PRECHARGE_ALL_BANKS 0xFF ///< Use to specify PrechargeAll Command to Precharge Cmd Function
-#define CMD_TGT_A 0x00 ///< Issue Commands to Command Target A
-#define CMD_TGT_AB 0x01 ///< Issue Commands to Command Targets A and B
-#define CMD_TYPE_READ 0x00 ///< Read Command
-#define CMD_TYPE_WRITE 0x01 ///< Write Command
-#define CMD_TYPE_WR_RD 0x02 ///< Alternating Write and Read Commands
-#define CPG_BANK_ADDRESS_A 0x0 ///< Dimm Bank address used in Reliable RD/RW mode training
-#define CPG_BANK_ADDRESS_B 0x1 ///< Dimm Bank address used in Reliable RD/RW mode training
-#define CPG_ROW_ADDRESS_A 0x0 ///< Dimm Row address used in Reliable RD/RW mode training
-#define CPG_ROW_ADDRESS_B 0x0 ///< Dimm Row address used in Reliable RD/RW mode training
-#define CPG_COL_ADDRESS_A 0x0 ///< Dimm Column address used in Reliable RD/RW mode training
-#define CPG_COL_ADDRESS_B 0x0 ///< Dimm Column address used in Reliable RD/RW mode training
-#define CPG_COMPARE_MASK_LOW 0x00000000 ///< Dram DQMask[31:0] used to mask comparison on reads. 1=ignore
-#define CPG_COMPARE_MASK_HI 0x00000000 ///< Dram DQMask[63:32] used to mask comparison on reads. 1=ignore
-#define CPG_COMPARE_MASK_ECC 0x00 ///< Dram EccMask used to mask comparison on reads. 1=ignore
-#define PRBS_SEED_32 0x062221 ///< Data PRBS Seed
-#define PRBS_SEED_64 0x066665 ///< Data PRBS Seed
-#define PRBS_SEED_128 0x026666 ///< Data PRBS Seed
-#define PRBS_SEED_256 0x044443 ///< Data PRBS Seed
-
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/// Structure for Reliable Read/Write Mode Data
-/// These are values that may need to be referenced by the low level functions
-/// during training and are initialized at the begining of a particular type of training.
-typedef struct _RRW_SETTINGS {
- UINT8 CmdTgt; ///< Value to program into CmdTgt
- UINT8 TgtBankAddressA; ///< Target A Bank address
- UINT32 TgtRowAddressA; ///< Target A Row address
- UINT32 TgtColAddressA; ///< Target A Column address
- UINT8 TgtBankAddressB; ///< Target B Bank address
- UINT32 TgtRowAddressB; ///< Target B Row address
- UINT32 TgtColAddressB; ///< Target B Column address
- UINT32 CompareMaskLow; ///< Compare Mask Bits 31:0
- UINT32 CompareMaskHigh; ///< Compare Mask Bits 63:32
- UINT8 CompareMaskEcc; ///< Compare Mask Ecc
- UINT32 DataPrbsSeed; ///< PRBS Seed value
-} RRW_SETTINGS;
-
-/// DQS training related delays
-typedef enum {
- AccessRcvEnDly, ///< Receiver enable delay
- AccessWrDatDly, ///< Write data delay
- AccessRdDqsDly, ///< Read DQS delay
- AccessWrDqsDly, ///< Write DQS delay
- AccessPhRecDly ///< Phase recovery delay
-} TRN_DLY_TYPE;
-
-/// Training patterns for position training
-typedef enum {
- POS_PATTERN_72B, ///< 72 bit pattern
- POS_PATTERN_256B, ///< 256 bit pattern
-} POS_TRN_PATTERN_TYPE;
-
-/// ODT mode
-typedef enum {
- MISSION_MODE, ///< ODT during mission mode
- WRITE_LEVELING_MODE ///< ODT during write leveling
-} ODT_MODE;
-
-/*
- * DRBN - Dimm-Rank-Byte-Nibble
- * 31:12 Reserved
- * 11:09 Dimm (3-bits)
- * 08 Rank (1-bit)
- * 07:05 Reserved
- * 04:01 Byte (4-bits)
- * 00 Nibble (1-bit)
- */
-typedef UINT32 DRBN;
-#define MAKE_DRBN(dimm, rank, byte, nibble) ((((UINT32) (dimm)) << 9) | (((UINT32) (rank)) << 8) | \
-(((UINT32) (byte)) << 1) | ((UINT32) (nibble)) )
-#define DIMM_BYTE_ACCESS(dimm, byte) ((((UINT32) (dimm)) << 9) | (((UINT32) (byte)) << 1))
-#define CS_NBBL_ACCESS(cs, nibble) ((((UINT32) (cs)) << 8) | ((UINT32) (nibble)))
-#define DRBN_DIMM(x) ((UINT8) (((UINT32) (x) >> 9) & 0x07))
-#define DRBN_RANK(x) ((UINT8) (((UINT32) (x) >> 8) & 0x01))
-#define DRBN_BYTE(x) ((UINT8) (((UINT32) (x) >> 1) & 0x0F))
-#define DRBN_NBBL(x) ((UINT8) (((UINT32) (x)) & 0x01))
-
-/* Dimm Type mask */
-#define DT_X4 0x01
-#define DT_X8 0x02
-#define DT_X16 0x04
-#define DT_SR 0x10
-#define DT_DR 0x20
-#define DT_QR 0x40
-
-#define DT_ANY_X4 0x71
-#define DT_ANY_X8 0x72
-#define DT_ANY_X16 0x74
-#define DT_ANY_SR 0x17
-#define DT_ANY_DR 0x27
-#define DT_ANY_QR 0x47
-#define DT_ANY_SR_DR (DT_ANY_SR | DT_ANY_DR)
-#define DT_ANY (DT_ANY_SR | DT_ANY_DR | DT_ANY_QR)
-
-/// Delay Scaling Info Struct - Describes number of delay increments per UI of a delay type
-///
-typedef struct _TRN_DLY_PARMS {
- UINT8 Min; ///< Minimum Value
- UINT8 Max; ///< Maximum Value
- UINT8 Mask; ///< Mask to be applied (i.e. 0xFF if adjustable by one, 0xFE if adjustable by 2, etc.)
-} TRN_DLY_PARMS;
-
-/// Structure for certain data saving needed for DCT.
-typedef struct {
- UINT8 RcvEnDlyCounts[8]; ///< DQS Receiver Enable Delay counts
- UINT32 PhRecReg[3]; ///< 3 Phase recovery control registers
-} MEM_DCT_CACHE;
-
-/// Structure for table driven support.
-typedef struct _MEM_TBL_ALIAS {
- UINT8 time; ///< Modification time.
- UINT8 node:4; ///< Node on which to make modification.
- UINT8 dct:4; ///< DCT on which to make modification.
- UINT8 dimm:4; ///< Dimm on which to make modification.
- UINT8 attr:3; ///< Attribute of modification.
- UINT8 vtype:1; ///< Flag indicating value type.
- UINT32 bfindex; ///< Bit field index that need to be modified.
- union { ///< Union is defined to easy select between single and multiple bytelane cases.
- struct { ///< Sub-struct used for one bytelane value.
- UINT16 bytelane:16; ///< Bytelane on which to make modification.
- UINT32 value; ///< Modified value.
- UINT8 reserved[3]; ///< Reserved for this purpose
- } s; ///< single value to one or multiple bytelanes
- UINT8 bytelanevalue[9]; ///< Array to specify individual bytelane values
- } data;
-} MEM_TABLE_ALIAS;
-
-/// Structure for Platform Specific Block.
-typedef struct _MEM_PS_BLOCK {
- UINT8 DramTerm; ///< Dram Term
- UINT8 QR_DramTerm; ///< Dram Term for QR
- UINT8 DynamicDramTerm; ///< Dynamic Dram Term
- UINT8 NumOfReg[MAX_DIMMS_PER_CHANNEL]; ///< Number of registers on each RDIMM (From SPD)
- UINT8 MR0WR; ///< MR0WR
- UINT8 MR0CL31; ///< MR0[CL][3:1]
- UINT8 MR0CL0; ///< MR0CL[0]
- UINT8 RttNom[8]; ///< RttNom value for maximum 8 chipsels per channel
- UINT8 RttWr[8]; ///< RttWr value for maximum 8 chipsels per channel
- UINT8 F0RC8; ///< F0RC8
- UINT8 F1RC0; ///< F1RC0
- UINT8 F1RC1; ///< F1RC1
- UINT8 F1RC2; ///< F1RC2
- UINT8 RC10OpSpd; ///< RC10[OperatingSpeed]
- UINT8 LrdimmRowAddrBits[MAX_DIMMS_PER_CHANNEL]; ///< Effective Row address bits used by LRDIMMS
- /* PUBLIC functions */
- BOOLEAN (*MemPDoPs) (struct _MEM_NB_BLOCK *NBPtr); ///< Function that gets Form factor info.
- VOID (*MemPGetPORFreqLimit) (struct _MEM_NB_BLOCK *NBPtr); ///< Function that gets the speed limit of a dimm population.
-} MEM_PS_BLOCK;
-
-/// Structure parameters needed in frequency change of client NB.
-typedef struct _MEM_FREQ_CHANGE_PARAM {
- UINT16 PllLockTimeDefault; ///< Default PllLockTime
- UINT8 RdPtrInit667orHigher; ///< RdPtrInit for frequency 667MHz and higher
- UINT8 RdPtrInitLower667; ///< RdPtrInit for frequency lower than 667MHz
- UINT8 NclkPeriodMul2x; ///< Multiplier for NclkPeriod in parial sum calculation x 2
- UINT8 MemClkPeriodMul2x; ///< Multiplier for MemClkPeriod in parial sum calculation x 2
- UINT8 SyncTimeMul4x; ///< Multiplier for SyncTime
- UINT16 TDataProp800orHigher; ///< TDataProp for frequency 800MHz or higher
- UINT16 TDataPropLower800; ///< TDataProp for frequency lower than 800MHz
-} MEM_FREQ_CHANGE_PARAM;
-
-/// List for NB items that are supported
-typedef enum {
- SetSpareEn, ///< Sets spare enable
- CheckSpareEn, ///< Spare enabled
- SetDllShutDown, ///< Sets DllShutDown
- CheckEccDLLPwrDnConfig, ///< Checks to determine if EccDLLPwrDnConf needs to be adjusted
- DimmBasedOnSpeed, ///< Checks to determine if Dimm number needs to be adjusted based on speed
- CheckMaxDramRate, ///< Checks to determine the maximum rate
- Check1GAlign, ///< Checks to determine if 1 GB alignment is supported
- DramModeBeforeDimmPres, ///< Check to determine if DRAM mode needs to be set before dimm presence
- DramModeAfterDimmPres, ///< Check to determine if DRAM mode needs to be set after dimm presence
- CheckClearOnDimmMirror, ///< Check to determine if we need to clear on DIMM mirror
- CheckDisDllShutdownSR, ///< Check to determine if DisDllShutdown needs to be set
- CheckMemClkCSPresent, ///< Check to determine if chipselect needs to be set based on disabled memclocks
- CheckChangeAvgValue, ///< Check to determine if we need to change average value
- CheckMaxRdDqsDlyPtr, ///< Check to determine change Max Rd Dqs Delay
- CheckPhyFenceTraining, ///< Check to determine if we need to Phy Fence training
- CheckGetMCTSysAddr, ///< Check to determine if we need to GetMCTSysAddr
- CheckSendAllMRCmds, ///< Check to determine if we need to SendAllMRCmds
- CheckFindPSOverideWithSocket, ///< Check to determine if we need to Find PSOveride With Socket
- CheckFindPSDct, ///< Check to determine if we need to Find PSOveride With DCT
- CheckODTControls, ///< Check to determine if we need to set ODT controls
- CheckDummyCLRead, ///< Check to determine if an extra dummy read is required
- CheckDllStdBy, ///< Check to determine if setting DLL stand by is required
- CheckSlewWithMarginImprv, ///< Check to determine if setting of Slew With MarginImprv is required
- CheckSlewWithoutMarginImprv, ///< Check to determine if setting of Slew Without MarginImprv is required
- CheckDllSpeedUp, ///< Check to determine if setting of Dll SpeedUp is required
- CheckDllRegDis, ///< Check to determine if setting of DLL Regulator Disable is required
- FenceTrnBeforeDramInit, ///< Check to determine if fence training has been done before Dram init
- WLSeedAdjust, ///< Check to determine if WL seed needs to be adjusted
- UnifiedNbFence, ///< Check to determine if Phy fence is of Unified NB
- AdjustTwr, ///< Check to determine if Twr needs to be adjusted
- ChannelPDMode, ///< Check to determine if channel power down mode is the only that is supported
- ForceEnMemHoleRemapping, ///< Check to determine if we need to force enabling memory hole remapping
- AdjustTrdrdSD, ///< Check to determine if we need to adjust TrdrdSD
- ReverseMaxRdLatTrain, ///< Check to determine if reverse (pass to fail) algorithm is supported for MaxRdLat training
- SkipErrTrain, ///< Check to determine if skip error training is supported
- DramSrHys, ///< Check to determine if DRAM SR hysteresis is supported
- PchgPDMode, ///< Check to determine if Precharge powerdown mode is supported
- EccByteTraining, ///< Check to determine if DRAM ECC Byte training
- CheckDrvImpCtrl, ///< Check to determine if we need to set DrvImpCtrl
- CheckDramTerm, ///< Check to determine if we need to set DramTerm
- CheckDramTermDyn, ///< Check to determine if we need to set DramTermDyn
- CheckQoff, ///< Check to determine if we need to set Qoff
- CheckSetSameDctODTsEn, ///< Check to defermine if we need to set "ODTsEn" the same on each DCT
- WLNegativeDelay, ///< Check to determine if the NB can tolerate a negtive WL delay value
- SchedDlySlot1Extra, ///< Check to determine if DataTxSchedDly Slot1 equation in slowMode to subtract an extra MEMCLK
- TwoStageDramInit, ///< Check to determine if we need to seperate Draminit into 2 stages. The first one processes info on all nodes. The second one does Dram Init.
-
- EnumSize ///< Size of list
-} NB_SUPPORTED;
-
-/// List for family specific functions that are supported
-typedef enum {
- BeforePhyFenceTraining, ///< Family specific tasks before Phy Fence Training
- AfterMemClkFreqVal, ///< Override PllMult and PllDiv
- OverridePllMult, ///< Override PllMult
- OverridePllDiv, ///< Override PllDiv
- BeforeMemClr, ///< Before MemClr
- SendMrsCmdsPerCs, ///< Send MRS commands per CS
- SetupHwTrainingEngine, ///< Setup Hardware training engine for specific training type
- OverrideRcvEnSeed, ///< Override seed for hardware based RcvEn training
- AddlMaxRdLatTrain, ///< Perform additional MaxRdLat training if needed
- ForceAutoComp, ///< Force Auto Comp
- DetectMemPllError, ///< Detect MemPll Divide by 3 bug
- ReEnablePhyComp, ///< Re-Enable Phy Compensation after RcvEn Training
- ExtractWLODT, ///< Extract WL ODT value thr given ODT pattern
- DCTSelectSwitch, ///< Select DCT when we switch DCT
- ScrubberErratum, ///< Erratum for setting scrubber rate
- MR0_PPD, ///< Override MR0[PPD]
- GetDdrMaxRate, ///< Interpret DdrMaxRate with Familiy-specific encoding
- ExitPhyAssistedTraining, ///< Perform family specific tasks when exiting phy assisted training
- AfterSaveRestore, ///< Action after save/restore execution
- OverrideDataTxFifoWrDly, ///< Override DataTxFifoWrDly based on training result of WrDatDly
- OverrideRcvEnSeedPassN, ///< Override seed for hardware based RcvEn training where N greater than 0
- AfterMemClkFreqChg, ///< Reprogram DIMMs' buffers after MEMCLK frequency change
- AdjustTxpdll, ///< Adjust Txpdll value to encoded register value
- CalcWrDqDqsEarly, ///< Calculate WrDqDqsEarly
- TrainWlPerNibble, ///< Train Write Leveling per nibble
- TrainWlPerNibbleAdjustWLDly, ///< Train WL per nibble and adjust the WL delay
- TrainWlPerNibbleSeed, ///< Save the seed for WL nibble based training
- TrainRxEnPerNibble, ///< Train Rx Enable Training per nibble
- TrainRxEnAdjustDlyPerNibble, ///< Train Rx Enable Training nibble and adjust the RxEn delay
- TrainRxEnGetAvgDlyPerNibble, ///< Display Rx Enable Training average nibble value for each BL
- InitPerNibbleTrn, ///< Initiates Per Nibble Training.
- BeforeSetCsTri, ///< Modify CS tri-state bit map.
- ForceRdDqsPhaseB, ///< Force RdDqsDly to phase B
- SetDqsODT, ///< Set DQS ODT
- DisLowPwrDrvStr, ///< Hook to skip setting LowPowerDriveStrengthEn
- AdjustRdDqsDlyOffset, ///< Adjust the bit offset of the RdDqsDly Bit Bitfield before writing and after reading
- ResetRxFifoPtr, ///< Reset RxFifo pointer during Read DQS training
- EnableParityAfterMemRst, ///< Enable DRAM Address Parity after memory reset.
- FinalizeVDDIO, ///< Finalize VDDIO
-
- NumberOfHooks ///< Size of list
-} FAMILY_SPECIFIC_FUNC_INDEX;
-
-///< Entry for SPD Timing
-typedef struct {
- BIT_FIELD_NAME BitField; ///< Bit field name of the timing
- UINT8 Min; ///< Minimum value for timing
- UINT8 Max; ///< Maximum value for timing
- UINT8 Bias; ///< Bias from actual value
- UINT8 Ratio_x2; ///< Actual value will be multiplied by (Ratio_x2/2)
-} CTENTRY;
-
-/// Structure for northbridge block.
-typedef struct _MEM_NB_BLOCK {
- MEM_DATA_STRUCT *MemPtr; ///< Point to MEM_DATA_STRUCT.
- MEM_PARAMETER_STRUCT *RefPtr; ///< Point to MEM_PARAMETER_STRUCT.
- DIE_STRUCT *MCTPtr; ///< point to current Node's MCT struct
- DCT_STRUCT *DCTPtr; ///< point to current Node's DCT struct
- DCT_STRUCT *AllDCTPtr; ///< point to all Node's DCT structs
- CH_DEF_STRUCT *ChannelPtr; ///< point to current channel data
- SPD_DEF_STRUCT *SPDPtr; ///< Point to SPD data for current DCT.
- struct _MEM_TECH_BLOCK *TechPtr; ///< point to technology block.
- struct _MEM_FEAT_BLOCK_NB *FeatPtr; ///< point to NB Specific feature block.
- struct _MEM_SHARED_DATA *SharedPtr; ///< Pointer to Memory scratchpad area
- SPD_DEF_STRUCT *AllNodeSPDPtr; ///< Point to SPD data for the system.
- DIE_STRUCT *AllNodeMCTPtr; ///< point to all Node's MCT structs
- UINT8 DimmToBeUsed; ///< Dimm to be used in recovery mode.
- MEM_PS_BLOCK *PsPtr; ///< point to platform specific block
- MEM_PS_BLOCK *PSBlock; ///< point to the first platform specific block on this node.
- MEM_FREQ_CHANGE_PARAM *FreqChangeParam; ///< pointer to parameter of frequency change.
-
- PCI_ADDR PciAddr; ///< PCI address for this node
- TSEFO NBRegTable[BFEndOfList]; ///< contains all bit field definitions
-
- UINT8 Node; ///< current node.
- UINT8 Dct; ///< current DCT.
- UINT8 Channel; ///< current channel.
- UINT8 DctCount; ///< number of DCTs on the current NB.
- UINT8 ChannelCount; ///< number of channels per DCT of the current NB.
- UINT8 NodeCount; ///< number of Nodes supported
- BOOLEAN Ganged; ///< mode for current MCT controller.
- POS_TRN_PATTERN_TYPE PosTrnPattern; ///< specifies the pattern that should be used for position training.
- BOOLEAN MemCleared; ///< memory clear flag.
- UINT32 CPGInit; ///< continuous pattern generation flag.
- UINT16 StartupSpeed; ///< startup speed for DDR3.
- UINT16 RcvrEnDlyLimit; ///< maximum value that RcvrEnDly field can take.
- UINT32 McaNbCtlReg; ///< reserve MCA reports.
- UINT32 VarMtrrHiMsk; ///< variable MTRR mask for upper 32 bits.
- UINT32 NBClkFreq; ///< Current NB Clock frequency
- UINT8 DefDctSelIntLvAddr; ///< Default DctSelIntLvAddr
- UINT8 TrainingSequenceIndex; ///< Index into the Training Sequence
- RRW_SETTINGS RrwSettings; ///<Settings for Reliable Read/Write mode
-
- UINT16 MaxFreqVDDIO[VOLT1_25 + 1]; ///< Max Frequency each voltage supports.
-
- MEM_DCT_CACHE DctCache[MAX_CHANNELS_PER_SOCKET]; ///< Allocate space for MCT_DCT_CACHE.
- MEM_DCT_CACHE *DctCachePtr; ///< pointer to current Node's Node struct
-
- /* Temporary storage */
- BOOLEAN ClToNbFlag; ///< is used to restore ClLinesToNbDis bit after memory
- UINT8 NbFreqChgState; ///< is used as a state index in NB frequency change state machine
- UINT32 NbPsCtlReg; ///< is used to save/restore NB Pstate control register
-
- ///< Determines if code should be executed on a give NB
- BOOLEAN IsSupported[EnumSize];
- BOOLEAN (*FamilySpecificHook[NumberOfHooks]) (struct _MEM_NB_BLOCK *NBPtr, VOID *OptParam); ///< This array of pointers point to
- ///< family specific functions.
-
- /* PUBLIC functions */
- VOID (*SwitchDCT) (struct _MEM_NB_BLOCK *NBPtr, UINT8 DCT); ///< Switch to current DCT.
- VOID (*SwitchChannel) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Channel); ///< Switch to current channel.
- VOID (*SetMaxLatency) (struct _MEM_NB_BLOCK *NBPtr, UINT16 MaxRcvEnDly); ///< Set Max Rd Latency.
- VOID (*getMaxLatParams) (struct _MEM_NB_BLOCK *NBPtr, UINT16 MaxDlyForMaxRdLat, UINT16 *MinDly, UINT16 *MaxDly, UINT16 *DlyBias); ///< retrieves the Max latency parameters.
- BOOLEAN (*GetSysAddr) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Receiver, UINT32 *Addr); ///< Get system address for training dimm.
- BOOLEAN (*RankEnabled) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Receiver); ///< Check if a rank has been enabled.
- BOOLEAN (*InitializeMCT) (struct _MEM_NB_BLOCK *NBPtr); ///< MCT initialization.
- BOOLEAN (*FinalizeMCT) (struct _MEM_NB_BLOCK *NBPtr); ///< sets final values in BUCFG and BUCFG2.
- BOOLEAN (*InitMCT) (struct _MEM_NB_BLOCK *NBPtr); ///< main entry call for memory initialization.
- VOID (*SendMrsCmd) (struct _MEM_NB_BLOCK *NBPtr); ///< send MRS command.
- VOID (*sendZQCmd) (struct _MEM_NB_BLOCK *NBPtr); ///< send ZQ command.
- VOID (*TrainingFlow) (struct _MEM_NB_BLOCK *NBPtr); ///< Set the training flow control
- VOID (*WritePattern) (struct _MEM_NB_BLOCK *NBPtr, UINT32 Address, UINT8 Pattern[], UINT16 ClCount); ///< Write training pattern.
- VOID (*ReadPattern) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Buffer[], UINT32 Address, UINT16 ClCount); ///< Read training pattern.
- VOID (*GenHwRcvEnReads) (struct _MEM_NB_BLOCK *NBPtr, UINT32 Address); ///< generates a continuous burst of reads during HW RcvEn training.
- UINT16 (*CompareTestPattern) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Buffer[], UINT8 Pattern[], UINT16 ByteCount); ///< Compare training pattern.
- UINT16 (*InsDlyCompareTestPattern) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Buffer[], UINT8 Pattern[], UINT16 ByteCount); ///< Compare training pattern using 1 beat offset to check for insertion delay
- BOOLEAN (*StitchMemory) (struct _MEM_NB_BLOCK *NBPtr); ///< combines all the memory into a contiguous map.
- VOID (*ProgramCycTimings) (struct _MEM_NB_BLOCK *NBPtr); ///< programs the memory controller with SPD timings.
- BOOLEAN (*AutoConfig) (struct _MEM_NB_BLOCK *NBPtr); ///< programs the memory controller with configuration parameters
- BOOLEAN (*PlatformSpec) (struct _MEM_NB_BLOCK *NBPtr); ///< programs platform specific parameters.
- VOID (*DisableDCT) (struct _MEM_NB_BLOCK *NBPtr); ///< disable a DCT if no dimm presents.
- VOID (*StartupDCT) (struct _MEM_NB_BLOCK *NBPtr); ///< start a DCT.
- VOID (*SyncTargetSpeed) (struct _MEM_NB_BLOCK *NBPtr); ///< Check and sync the target speed of all channels of this node.
- VOID (*ChangeFrequency) (struct _MEM_NB_BLOCK *NBPtr); ///< Frequency change sequence.
- BOOLEAN (*RampUpFrequency) (struct _MEM_NB_BLOCK *NBPtr); ///< Change frequency to the next supported level.
- BOOLEAN (*ChangeNbFrequency) (struct _MEM_NB_BLOCK *NBPtr); ///< Change NB frequency.
- VOID (*PhyFenceTraining) (struct _MEM_NB_BLOCK *NBPtr); ///< Phy fence training.
- BOOLEAN (*SyncDctsReady) (struct _MEM_NB_BLOCK *NBPtr); ///< Synchronize DCTs.
- BOOLEAN (*HtMemMapInit) (struct _MEM_NB_BLOCK *NBPtr); ///< Memory map initialization.
- VOID (*SyncAddrMapToAllNodes) (struct _MEM_NB_BLOCK *NBPtr); ///< copies the Node 0 map to all the other nodes.
- BOOLEAN (*CpuMemTyping) (struct _MEM_NB_BLOCK *NBPtr); ///< MTRR and TOM setting.
- VOID (*BeforeDqsTraining) (struct _MEM_NB_BLOCK *NBPtr); ///< processes needed before DQS training.
- VOID (*AfterDqsTraining) (struct _MEM_NB_BLOCK *NBPtr); ///< processes needed after DQS training.
- BOOLEAN (*OtherTiming) (struct _MEM_NB_BLOCK *NBPtr); ///< setting non-spd timing.
- VOID (*UMAMemTyping) (struct _MEM_NB_BLOCK *NBPtr); ///< MTRR and TOM setting needed for UMA platform.
- VOID (*Feature) (struct _MEM_NB_BLOCK *NBPtr); ///< Feature support.
- UINT8 (*GetSocketRelativeChannel) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Dct, UINT8 Channel); ///< Get channel number relative to a socket.
- VOID (*SetDramOdtRec) (struct _MEM_NB_BLOCK *NBPtr, ODT_MODE OdtMode, UINT8 ChipSelect, UINT8 TargetCS); ///< Set Dram ODT.
- UINT32 (*GetSysAddrRec) (VOID); ///< Get system address for training.
- VOID (*SwitchNodeRec) (struct _MEM_NB_BLOCK *NBPtr, UINT8 NodeID); ///< Switch to current node.
- VOID (*TechBlockSwitch) (struct _MEM_NB_BLOCK *NBPtr); ///< Selects appropriate Tech functions for the NB.
- VOID (*SetEccSymbolSize) (struct _MEM_NB_BLOCK *NBPtr); ///< Set Ecc Symbol Size.
- VOID (*GetTrainDlyParms) (struct _MEM_NB_BLOCK *NBPtr, TRN_DLY_TYPE TrnDly, TRN_DLY_PARMS *Parms); ///< Retrieve Specific Delay range info for current NB under current conditions.
- AGESA_STATUS (*TrainingPatternInit) (struct _MEM_NB_BLOCK *NBPtr); ///< Initialize the training Pattern
- AGESA_STATUS (*TrainingPatternFinalize) (struct _MEM_NB_BLOCK *NBPtr); ///< Finalize the training Pattern
- BOOLEAN (*GetApproximateWriteDatDelay) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Index, UINT8 *Value); ///< Retrieve the next WrDat Delay Approximation
- UINT8 (*CSPerChannel) (struct _MEM_NB_BLOCK *NBPtr); ///< Return number of CS per channel.
- UINT8 (*CSPerDelay) (struct _MEM_NB_BLOCK *NBPtr); ///< Return number of CS controlled per set of delay registers.
- VOID (*FlushPattern) (struct _MEM_NB_BLOCK *NBPtr, UINT32 Address, UINT16 ClCount); ///<Flush the training pattern
- UINT8 (*MinDataEyeWidth) (struct _MEM_NB_BLOCK *NBPtr); ///<Get Min Data Eye Width in 32nds of a UI
- VOID (*MemNCapSpeedBatteryLife) (struct _MEM_NB_BLOCK *NBPtr); ///< Caps speed based on battery life check.
- UINT32 (*GetUmaSize) (struct _MEM_NB_BLOCK *NBPtr); ///< Get Uma Size
- UINT8 (*GetMemClkFreqId) (struct _MEM_NB_BLOCK *NBPtr, UINT16 Speed); ///< Translate MemClk frequency in MHz to MemClkFreq value
- VOID (*EnableSwapIntlvRgn) (struct _MEM_NB_BLOCK *NBPtr, UINT32 Base, UINT32 Limit); ///< Enable swapped interleaving region
- BOOLEAN (*ChangeNbFrequencyWrap) (struct _MEM_NB_BLOCK *NBPr, UINT32 NBPstate); ///< Wrapper for NB Pstate change function
- VOID (*WaitXMemClks) (struct _MEM_NB_BLOCK *NBPr, UINT32 MemClkCount); ///< Waits a specified number of MemClks
- VOID (*ProgramNbPsDependentRegs) (struct _MEM_NB_BLOCK *NBPtr); ///< Programs NB Pstate dependent registers
- VOID (*AllocateC6Storage) (struct _MEM_NB_BLOCK *NBPtr); ///< Allocates DRAM region for Core C6
-
- /* PUBLIC Get/Set register field functions */
- UINT32 (*GetBitField) (struct _MEM_NB_BLOCK *NBPtr, BIT_FIELD_NAME FieldName); ///< Pci register bit field read.
- VOID (*SetBitField) (struct _MEM_NB_BLOCK *NBPtr, BIT_FIELD_NAME FieldName, UINT32 Value); ///< Pci register bit field write.
- BOOLEAN (*BrdcstCheck) (struct _MEM_NB_BLOCK *NBPtr, BIT_FIELD_NAME FieldName, UINT32 Value); ///< Pci register bit field broadcast read.
- VOID (*BrdcstSet) (struct _MEM_NB_BLOCK *NBPtr, BIT_FIELD_NAME FieldName, UINT32 Value); ///< Pci register bit field broadcast write.
- VOID (*PollBitField) (struct _MEM_NB_BLOCK *NBPtr, BIT_FIELD_NAME FieldName, UINT32 Field, UINT32 MicroSecond, BOOLEAN IfBroadCast); ///< Poll a Pci register bitfield.
- UINT32 (*GetTrainDly) (struct _MEM_NB_BLOCK *NBPtr, TRN_DLY_TYPE TrnDly, DRBN DrbnVar); ///< Training register bit field read.
- VOID (*SetTrainDly) (struct _MEM_NB_BLOCK *NBPtr, TRN_DLY_TYPE TrnDly, DRBN DrbnVar, UINT16 Value); ///< Training register bit field write.
- AGESA_STATUS (*InitRecovery) (struct _MEM_NB_BLOCK *NBPtr); ///< Recover mode memory init
- VOID (*MemRecNInitializeMctNb) (struct _MEM_NB_BLOCK *NBPtr); ///< Initialize MCT changes
- VOID (*MemRecNFinalizeMctNb) (struct _MEM_NB_BLOCK *NBPtr); ///< Finalize MCT changes
- VOID (*MemNInitPhyComp) (struct _MEM_NB_BLOCK *NBPtr); ///< Init Phy compensation
- VOID (*MemNBeforeDramInitNb) (struct _MEM_NB_BLOCK *NBPtr); ///< Before Dram init
- BOOLEAN (*MemNIsIdSupportedNb) (struct _MEM_NB_BLOCK *NBPtr, CPU_LOGICAL_ID *LogicalIdPtr); ///< Determines if a given CPU id is supported
- BOOLEAN (*InitNBRegTableNb) (struct _MEM_NB_BLOCK *NBPtr, TSEFO NBRegTable[]); ///< Initializes register table
- BOOLEAN (*MemNPlatformSpecificFormFactorInitNb) (struct _MEM_NB_BLOCK *NBPtr); ///< Platform specific functions
- VOID (*MemNSetOtherTimingNb) (struct _MEM_NB_BLOCK *NBPtr); ///< Set non-spd timings
- VOID (*MemNBeforePlatformSpecNb) (struct _MEM_NB_BLOCK *NBPtr); ///< Apply settings prior to platform specific settings
- UINT32 (*MemNCmnGetSetFieldNb) (struct _MEM_NB_BLOCK *NBPtr, UINT8 IsSet, BIT_FIELD_NAME FieldName, UINT32 Field); ///< Sets a register value
- UINT32 (*MemNcmnGetSetTrainDly) (struct _MEM_NB_BLOCK *NBPtr, UINT8 IsSet, TRN_DLY_TYPE TrnDly, DRBN DrbnVar, UINT16 Field); ///< Sets a training delay field
- VOID (*MemPPhyFenceTrainingNb) (struct _MEM_NB_BLOCK *NBPtr); ///< Phy Fence training
- VOID (*MemPNodeMemBoundaryNb) (struct _MEM_NB_BLOCK *NBPtr, UINT32 *NodeSysLimit); ///< Phy Fence training
- UINT32 (*MemRecNCmnGetSetFieldNb) (struct _MEM_NB_BLOCK *NBPtr, UINT8 IsSet, BIT_FIELD_NAME FieldName, UINT32 Field); ///< This functions sets bit fields in recover mode
- UINT32 (*MemRecNcmnGetSetTrainDlyNb) (struct _MEM_NB_BLOCK *NBPtr, UINT8 IsSet, TRN_DLY_TYPE TrnDly, DRBN DrbnVar, UINT16 Field); ///< This functions sets bit fields in recover mode
- VOID (*MemRecNSwitchDctNb) (struct _MEM_NB_BLOCK *NBPtr, UINT8 NodeID); ///< S3 Exit self refresh register
- VOID (*MemNPFenceAdjustNb) (struct _MEM_NB_BLOCK *NBPtr, UINT16 *Value16); ///< Adjust Avg PRE value of Phy fence training
- VOID (*MemNPrepareRcvrEnDlySeed) (struct _MEM_NB_BLOCK *NBPtr); ///< Seed valude for HW RxEn training
- UINT8 (*MemNGetDramTerm) (struct _MEM_NB_BLOCK *NBPtr, UINT8 ChipSel); ///< Dram Term value
- UINT8 (*MemNGetDynDramTerm) (struct _MEM_NB_BLOCK *NBPtr, UINT8 ChipSel); ///< Dynamic Dram Term value
- UINT32 (*MemNGetMR0CL) (struct _MEM_NB_BLOCK *NBPtr); ///< MR0[CL] value
- UINT32 (*MemNGetMR0WR) (struct _MEM_NB_BLOCK *NBPtr); ///< MR0[WR] value
- UINT32 (*MemNGetMR2CWL) (struct _MEM_NB_BLOCK *NBPtr); ///< MR2[CWL] value
-
-} MEM_NB_BLOCK;
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-VOID
-MemNInitNBDataNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNSwitchDCTNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Dct
- );
-
-VOID
-MemNSwitchChannelNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Channel
- );
-
-UINT32
-MemNGetBitFieldNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN BIT_FIELD_NAME FieldName
- );
-
-VOID
-MemNSetBitFieldNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN BIT_FIELD_NAME FieldName,
- IN UINT32 Field
- );
-
-BOOLEAN
-MemNBrdcstCheckNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN BIT_FIELD_NAME FieldName,
- IN UINT32 Field
- );
-
-VOID
-MemNBrdcstSetNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN BIT_FIELD_NAME FieldName,
- IN UINT32 Field
- );
-
-
-UINT32
-MemNGetTrainDlyNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN TRN_DLY_TYPE TrnDly,
- IN DRBN DrbnVar
- );
-
-VOID
-MemNSetTrainDlyNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN TRN_DLY_TYPE TrnDly,
- IN DRBN DrbnVar,
- IN UINT16 Field
- );
-
-BOOLEAN
-MemNRankEnabledNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Receiver
- );
-
-UINT8 MemNGetSocketRelativeChannelNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Dct,
- IN UINT8 Channel
- );
-
-VOID
-MemNPhyFenceTrainingNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNGetMCTSysAddrNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Receiver,
- OUT UINT32 *AddrPtr
- );
-
-BOOLEAN
-MemNPlatformSpecNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNStitchMemoryNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNDisableDCTNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNDisableDCTClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNStartupDCTNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNStartupDCTUnb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNChangeFrequencyNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNRampUpFrequencyNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNProgramCycTimingsNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNGetMaxLatParamsNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT16 MaxRcvEnDly,
- IN OUT UINT16 *MinDlyPtr,
- IN OUT UINT16 *MaxDlyPtr,
- IN OUT UINT16 *DlyBiasPtr
- );
-
-UINT16
-MemNTotalSyncComponentsNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNSetMaxLatencyNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT16 MaxRcvEnDly
- );
-
-VOID
-MemNSendZQCmdNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNSwapBitsNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNSwapBitsUnb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNTrainPhyFenceNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNInitPhyCompNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNGetTrainDlyParmsNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN TRN_DLY_TYPE TrnDly,
- IN OUT TRN_DLY_PARMS *Parms
- );
-
-
-VOID
-MemNGetTrainDlyParmsClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN TRN_DLY_TYPE TrnDly,
- IN OUT TRN_DLY_PARMS *Parms
- );
-
-VOID
-MemNBeforeDQSTrainingNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-UINT32
-MemNcmnGetSetTrainDlyNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN TRN_DLY_TYPE TrnDly,
- IN DRBN DrbnVar,
- IN UINT16 Field
- );
-
-UINT32
-MemNcmnGetSetTrainDlyClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN TRN_DLY_TYPE TrnDly,
- IN DRBN DrbnVar,
- IN UINT16 Field
- );
-
-VOID
-MemNSyncTargetSpeedNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNSyncDctsReadyNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNHtMemMapInitNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-UINT8
-MemNGetTrdrdNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-UINT8
-MemNGetTwrwrNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-UINT8
-MemNGetTwrrdNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-UINT8
-MemNGetTrwtTONb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-UINT8
-MemNGetTrwtWBNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNPowerDownCtlNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNCPUMemTypingNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNUMAMemTypingNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNSyncAddrMapToAllNodesNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNInitMCTNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNTechBlockSwitchNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-UINT32
-MemRecNGetBitFieldNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN BIT_FIELD_NAME FieldName
- );
-
-VOID
-MemRecNSetBitFieldNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN BIT_FIELD_NAME FieldName,
- IN UINT32 Field
- );
-
-UINT32
-MemRecNGetTrainDlyNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN TRN_DLY_TYPE TrnDly,
- IN DRBN DrbnVar
- );
-
-VOID
-MemRecNSetTrainDlyNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN TRN_DLY_TYPE TrnDly,
- IN DRBN DrbnVar,
- IN UINT16 Field
- );
-
-BOOLEAN
-MemRecNAutoConfigNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemRecNPlatformSpecNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemRecNStartupDCTNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemRecNSetMaxLatencyNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT16 MaxRcvEnDly
- );
-
-VOID
-MemRecNSetDramOdtNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN ODT_MODE OdtMode,
- IN UINT8 ChipSelect,
- IN UINT8 TargetCS
- );
-
-VOID
-MemRecNSendMrsCmdNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-
-VOID
-MemRecNSendZQCmdNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemRecNContReadPatternClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Buffer[],
- IN UINT32 Address,
- IN UINT16 ClCount
- );
-
-AGESA_STATUS
-MemRecNMemInitNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemRecNCPUMemRecTypingNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-UINT32
-MemRecNGetMCTSysAddrNb (
- VOID
- );
-
-UINT32
-MemRecGetVarMtrrHiMsk (
- IN CPU_LOGICAL_ID *LogicalIdPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-INT8
-MemNGetOptimalCGDDNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN TRN_DLY_TYPE TrnDly1,
- IN TRN_DLY_TYPE TrnDly2
- );
-
-VOID
-MemNPollBitFieldNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN BIT_FIELD_NAME FieldName,
- IN UINT32 Field,
- IN UINT32 MicroSecond,
- IN BOOLEAN IfBroadCast
- );
-
-VOID
-MemNSetEccSymbolSizeNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNDQSTiming3Nb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNDQSTiming2Nb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNTrainingFlowNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNRecTrainingFlowNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNRecTrainingFlowClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-UINT32
-MemRecNTotalSyncComponentsClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemRecNStartupDCTClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-
-VOID
-MemRecNPhyVoltageLevelNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemRecNPhyFenceTrainingNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-AGESA_STATUS
-MemNTrainingPatternInitNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNGetApproximateWriteDatDelayNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Index,
- IN OUT UINT8 *Value
- );
-
-AGESA_STATUS
-MemNTrainingPatternFinalizeNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNFlushPatternNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 Address,
- IN UINT16 ClCount
- );
-
-UINT8
-MemNCSPerChannelNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-UINT8
-MemNCSPerDelayNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-UINT8
-MemNMinDataEyeWidthNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-UINT16
-MemNCompareTestPatternNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Buffer[],
- IN UINT8 Pattern[],
- IN UINT16 ByteCount
- );
-
-UINT16
-MemNInsDlyCompareTestPatternNb (
- IN MEM_NB_BLOCK *NBPtr,
- IN UINT8 Buffer[],
- IN UINT8 Pattern[],
- IN UINT16 ByteCount
- );
-
-
-UINT32
-MemNGetUmaSizeNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNSetMTRRUmaRegionUCNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 *BasePtr,
- IN OUT UINT32 *LimitPtr
- );
-
-UINT8
-MemNGetMemClkFreqIdNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT16 Speed
- );
-
-UINT8
-MemNGetMemClkFreqIdClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT16 Speed
- );
-
-UINT8
-MemNGetMemClkFreqIdUnb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT16 Speed
- );
-
-UINT16
-MemNGetMemClkFreqUnb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 FreqId
- );
-
-BOOLEAN
-MemNGetPlatformCfgNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNPlatformSpecUnb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNProgramPlatformSpecNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNProgramCycTimingsClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-INT16
-MemNCalcCDDNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN TRN_DLY_TYPE TrnDlyType1,
- IN TRN_DLY_TYPE TrnDlyType2,
- IN BOOLEAN SameDimm,
- IN BOOLEAN DiffDimm
- );
-
-VOID
-MemNChangeFrequencyUnb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNProgramNbPstateDependentRegistersUnb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNProgramNbPstateDependentRegistersClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNAllocateC6StorageClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNAllocateC6StorageUnb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNPhyVoltageLevelNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNPhyFenceTrainingUnb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNPFenceAdjustUnb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT UINT16 *Value16
- );
-
-VOID
-MemNInitPhyCompClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-UINT32
-MemNTotalSyncComponentsClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNEnableSwapIntlvRgnNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 Base,
- IN UINT32 Limit
- );
-
-VOID
-MemNPhyPowerSavingClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNSetASRSRTNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNPrepareRcvrEnDlySeedNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNChangeNbFrequencyUnb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNChangeNbFrequencyNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemNWaitXMemClksNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT32 MemClkCount
- );
-
-BOOLEAN
-memNSequenceDDR3Nb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-UINT16
-GetTrainDlyFromHeapNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN TRN_DLY_TYPE TrnDlyType,
- IN DRBN Drbn
- );
-
-BOOLEAN
-MemNTrainingFlowUnb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNSetupHwTrainingEngineUnb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN VOID* OptParam
- );
-
-BOOLEAN
-MemNBeforePhyFenceTrainingClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT VOID *OptParam
- );
-
-BOOLEAN
-MemNReEnablePhyCompNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT VOID *OptParam
- );
-
-UINT8
-MemNGetDramTermNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 ChipSel
- );
-
-UINT8
-MemNGetDynDramTermNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 ChipSel
- );
-
-UINT32
-MemNGetMR0CLNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-UINT32
-MemNGetMR0WRNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-UINT32
-MemNGetMR2CWLNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNDctCfgSelectUnb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN VOID *Dct
- );
-
-BOOLEAN
-MemNGetMaxDdrRateUnb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN VOID *DdrMaxRate
- );
-
-BOOLEAN
-MemRecNReEnablePhyCompNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT VOID *OptParam
- );
-
-VOID
-MemNSetTxpNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemNAdjustTxpdllClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT VOID *OptParam
- );
-
-BOOLEAN
-MemNCalcWrDqDqsEarlyUnb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT VOID *OptParam
- );
-
-VOID
-MemNGetTrainDlyParmsUnb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN TRN_DLY_TYPE TrnDly,
- IN OUT TRN_DLY_PARMS *Parms
- );
-
-#endif /* _MN_H_ */
-
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/mp.h b/src/vendorcode/amd/agesa/Proc/Mem/mp.h
deleted file mode 100644
index 0bf56c7..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/mp.h
+++ /dev/null
@@ -1,569 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mp.h
- *
- * Platform Specific common header file
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem)
- * @e \$Revision: 37402 $ @e \$Date: 2010-09-03 05:36:02 +0800 (Fri, 03 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MP_H_
-#define _MP_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-/// Type of an entry for Dram Term table
-typedef struct {
- UINT32 Speed; ///< BitMap for the supported speed
- UINT8 Dimms; ///< BitMap for supported number of dimm
- UINT8 QR_Dimms; ///< BitMap for supported number of QR dimm
- UINT8 DramTerm; ///< DramTerm value
- UINT8 QR_DramTerm; ///< DramTerm value for QR
- UINT8 DynamicDramTerm; ///< Dynamic DramTerm
-} DRAM_TERM_ENTRY;
-
-/// Type of an entry for POR speed limit table
-typedef struct {
- UINT16 DIMMRankType; ///< Bitmap of Ranks
- UINT8 Dimms; ///< Number of dimm
- UINT16 SpeedLimit_1_5V; ///< POR speed limit for 1.5V
- UINT16 SpeedLimit_1_35V; ///< POR speed limit for 1.35V
- UINT16 SpeedLimit_1_25V; ///< POR speed limit for 1.25V
-} POR_SPEED_LIMIT;
-
-/// UDIMM&RDIMM Max. Frequency
-typedef union {
- struct { ///< PSCFG_MAXFREQ_ENTRY
- UINT16 DimmPerCh:3; ///< Dimm slot per chanel
- UINT16 Dimms:3; ///< Number of Dimms on a channel
- UINT16 SR:3; ///< Number of single-rank Dimm
- UINT16 DR:3; ///< Number of dual-rank Dimm
- UINT16 QR:4; ///< Number of quad-rank Dimm
- UINT16 Speed1_5V; ///< Speed limit with voltage 1.5V
- UINT16 Speed1_35V; ///< Speed limit with voltage 1.35V
- UINT16 Speed1_25V; ///< Speed limit with voltage 1.25V
- } _MAXFREQ_ENTRY;
- struct {
- UINT16 CDN; ///< Condition
- UINT16 Speed[3]; ///< Speed limit
- } MAXFREQ_ENTRY;
-} PSCFG_MAXFREQ_ENTRY;
-
-/// LRDIMM Max. Frequency
-typedef union {
- struct { ///< PSCFG_LR_MAXFREQ_ENTRY
- UINT16 DimmPerCh:3; ///< Dimm slot per chanel
- UINT16 Dimms:3; ///< Number of Dimms on a channel
- UINT16 LR:10; ///< Number of LR-DIMM
- UINT16 Speed1_5V; ///< Speed limit with voltage 1.5V
- UINT16 Speed1_35V; ///< Speed limit with voltage 1.35V
- UINT16 Speed1_25V; ///< Speed limit with voltage 1.25V
- } _LR_MAXFREQ_ENTRY;
- struct {
- UINT16 CDN;
- UINT16 Speed[3];
- } LR_MAXFREQ_ENTRY;
-} PSCFG_LR_MAXFREQ_ENTRY;
-
-/// UDIMM&RDIMM RttNom and RttWr
-typedef struct {
- UINT64 DimmPerCh:8; ///< Dimm slot per chanel
- UINT64 DDRrate:32; ///< Bitmap of DDR rate
- UINT64 VDDIO:4; ///< Bitmap of VDDIO
- UINT64 Dimm0:4; ///< Bitmap of rank type of Dimm0
- UINT64 Dimm1:4; ///< Bitmap of rank type of Dimm1
- UINT64 Dimm2:4; ///< Bitmap of rank type of Dimm2
- UINT64 Dimm:3; ///< Bitmap of rank type of Dimm
- UINT64 Rank:5; ///< Bitmap of rank
- UINT8 RttNom:3; ///< Dram term
- UINT8 RttWr:5; ///< Dynamic dram term
-} PSCFG_RTT_ENTRY;
-
-/// LRDIMM RttNom and RttWr
-typedef struct {
- UINT64 DimmPerCh:8; ///< Dimm slot per chanel
- UINT64 DDRrate:32; ///< Bitmap of DDR rate
- UINT64 VDDIO:4; ///< Bitmap of VDDIO
- UINT64 Dimm0:4; ///< Dimm0 population
- UINT64 Dimm1:4; ///< Dimm1 population
- UINT64 Dimm2:12; ///< Dimm2 population
- UINT8 RttNom:3; ///< Dram term
- UINT8 RttWr:5; ///< Dynamic dram term
-} PSCFG_LR_RTT_ENTRY;
-
-/// UDIMM&RDIMM&LRDIMM ODT pattern OF 1 DPC
-typedef struct {
- UINT16 Dimm0; ///< Bitmap of dimm0 rank type or dimm0 population of LRDIMM
- UINT32 RdODTCSHigh; ///< RdODTCSHigh
- UINT32 RdODTCSLow; ///< RdODTCSLow
- UINT32 WrODTCSHigh; ///< WrODTCSHigh
- UINT32 WrODTCSLow; ///< WrODTCSLow
-} PSCFG_1D_ODTPAT_ENTRY;
-
-/// UDIMM&RDIMM&LRDIMM ODT pattern OF 2 DPC
-typedef struct {
- UINT16 Dimm0:4; ///< Bitmap of dimm0 rank type or dimm0 population of LRDIMM
- UINT16 Dimm1:12; ///< Bitmap of dimm1 rank type or dimm1 population of LRDIMM
- UINT32 RdODTCSHigh; ///< RdODTCSHigh
- UINT32 RdODTCSLow; ///< RdODTCSLow
- UINT32 WrODTCSHigh; ///< WrODTCSHigh
- UINT32 WrODTCSLow; ///< WrODTCSLow
-} PSCFG_2D_ODTPAT_ENTRY;
-
-/// UDIMM&RDIMM&LRDIMM ODT pattern OF 3 DPC
-typedef struct {
- UINT16 Dimm0:4; ///< Bitmap of dimm0 rank type or dimm0 population of LRDIMM
- UINT16 Dimm1:4; ///< Bitmap of dimm1 rank type or dimm1 population of LRDIMM
- UINT16 Dimm2:8; ///< Bitmap of dimm2 rank type or dimm2 population of LRDIMM
- UINT32 RdODTCSHigh; ///< RdODTCSHigh
- UINT32 RdODTCSLow; ///< RdODTCSLow
- UINT32 WrODTCSHigh; ///< WrODTCSHigh
- UINT32 WrODTCSLow; ///< WrODTCSLow
-} PSCFG_3D_ODTPAT_ENTRY;
-
-/// UDIMM&RDIMM&LRDIMM SlowMode, AddrTmgCtl and ODC
-typedef struct {
- UINT64 DimmPerCh:8; ///< Dimm slot per channel
- UINT64 DDRrate:32; ///< Bitmap of DDR rate
- UINT64 VDDIO:4; ///< Bitmap of VDDIO
- UINT64 Dimm0:4; ///< Bitmap of dimm0 rank type or dimm0 population of LRDIMM
- UINT64 Dimm1:4; ///< Bitmap of dimm1 rank type or dimm1 population of LRDIMM
- UINT64 Dimm2:11; ///< Bitmap of dimm2 rank type or dimm2 population of LRDIMM
- UINT64 SlowMode:1; ///< SlowMode
- UINT32 AddTmgCtl; ///< AddTmgCtl
- UINT32 ODC; ///< ODC
-} PSCFG_SAO_ENTRY;
-
-/// UDIMM&RDIMM MR0[WR]
-typedef struct {
- UINT8 Timing; ///< Fn2_22C_dct[1:0][Twr]
- UINT8 Value; ///< MR0[WR] : bit0 - bit2 available
-} PSCFG_MR0WR_ENTRY;
-
-/// UDIMM&RDIMM MR0[CL]
-typedef struct {
- UINT8 Timing; ///< Fn2_200_dct[1:0][Tcl]
- UINT8 Value:3; ///< MR0[CL] : bit0 - bit2 CL[3:1]
- UINT8 Value1:5; ///< MR0[CL] : bit3 CL[0]
-} PSCFG_MR0CL_ENTRY;
-
-/// UDIMM&RDIMM MR2[IBT]
-typedef struct {
- UINT64 DimmPerCh:4; ///< Dimm slot per channel
- UINT64 DDRrate:32; ///< Bitmap of DDR rate
- UINT64 VDDIO:4; ///< Bitmap of VDDIO
- UINT64 Dimm0:4; ///< Bitmap of dimm0 rank type
- UINT64 Dimm1:4; ///< Bitmap of dimm1 rank type
- UINT64 Dimm2:4; ///< Bitmap of dimm2 rank type
- UINT64 Dimm:4; ///< Bitmap of rank type of Dimm
- UINT64 NumOfReg:4; ///< Number of registers
- UINT64 IBT:4; ///< MR2[IBT] value
-} PSCFG_MR2IBT_ENTRY;
-
-/// UDIMM&RDIMM&LRDIMM Operating Speed
-typedef struct {
- UINT32 DDRrate; ///< Bitmap of DDR rate
- UINT8 OPSPD; ///< RC10[OperatingSpeed]
-} PSCFG_OPSPD_ENTRY;
-
-/// LRDIMM IBT
-typedef struct {
- UINT64 DimmPerCh:4; ///< Dimm slot per channel
- UINT64 DDRrate:32; ///< Bitmap of DDR rate
- UINT64 VDDIO:4; ///< Bitmap of VDDIO
- UINT64 Dimm0:4; ///< Dimm0 population
- UINT64 Dimm1:4; ///< Dimm1 population
- UINT64 Dimm2:4; ///< Dimm2 population
- UINT64 F0RC8:3; ///< F0RC8
- UINT64 F1RC0:3; ///< F1RC0
- UINT64 F1RC1:3; ///< F1RC1
- UINT64 F1RC2:3; ///< F1RC2
-} PSCFG_L_IBT_ENTRY;
-
-/// LRDIMM F0RC13[NumPhysicalRanks]
-typedef struct {
- UINT8 NumRanks:3; ///< NumRanks
- UINT8 NumPhyRanks:5; ///< NumPhyRanks
-} PSCFG_L_NPR_ENTRY;
-
-/// LRDIMM F0RC13[NumLogicalRanks]
-typedef struct {
- UINT16 NumPhyRanks:3; ///< NumPhyRanks
- UINT16 DramCap:4; ///< DramCap
- UINT16 NumDimmSlot:9; ///< NumDimmSlot
- UINT8 NumLogRanks; ///< NumLogRanks
-} PSCFG_L_NLR_ENTRY;
-
-/// Platform specific configuration types
-typedef enum {
- PSCFG_MAXFREQ, ///< PSCFG_MAXFREQ
- PSCFG_LR_MAXFREQ, ///< PSCFG_LR_MAXFREQ
- PSCFG_RTT, ///< PSCFG_RTT
- PSCFG_LR_RTT, ///< PSCFG_LR_RTT
- PSCFG_ODT_PAT_1D, ///< PSCFG_ODT_PAT_1D
- PSCFG_ODT_PAT_2D, ///< PSCFG_ODT_PAT_2D
- PSCFG_ODT_PAT_3D, ///< PSCFG_ODT_PAT_3D
- PSCFG_LR_ODT_PAT_1D, ///< PSCFG_LR_ODT_PAT_1D
- PSCFG_LR_ODT_PAT_2D, ///< PSCFG_LR_ODT_PAT_2D
- PSCFG_LR_ODT_PAT_3D, ///< PSCFG_LR_ODT_PAT_3D
- PSCFG_SAO, ///< PSCFG_SAO
- PSCFG_LR_SAO, ///< PSCFG_LR_SAO
- PSCFG_MR0WR, ///< PSCFG_MR0WR
- PSCFG_MR0CL, ///< PSCFG_MR0CL
- PSCFG_RC2IBT, ///< PSCFG_RC2IBT
- PSCFG_RC10OPSPD, ///< PSCFG_RC10OPSPD
- PSCFG_LR_IBT, ///< PSCFG_LR_IBT
- PSCFG_LR_NPR, ///< PSCFG_LR_NPR
- PSCFG_LR_NLR, ///< PSCFG_LR_NLR
-
- // The type of general table entries could be added between
- // PSCFG_GEN_START and PSCFG_GEN_END so that the PSCGen routine
- // is able to look for the entries per the PSCType.
- PSCFG_GEN_START, ///< PSCFG_GEN_START
- PSCFG_CLKDIS, ///< PSCFG_CLKDIS
- PSCFG_CKETRI, ///< PSCFG_CKETRI
- PSCFG_ODTTRI, ///< PSCFG_ODTTRI
- PSCFG_CSTRI, ///< PSCFG_CSTRI
- PSCFG_GEN_END ///< PSCFG_GEN_END
-} PSCFG_TYPE;
-
-/// Dimm types
-typedef enum {
- UDIMM_TYPE = 0x01, ///< UDIMM_TYPE
- RDIMM_TYPE = 0x02, ///< RDIMM_TYPE
- SODIMM_TYPE = 0x04, ///< SODIMM_TYPE
- LRDIMM_TYPE = 0x08, ///< LRDIMM_TYPE
- DT_DONT_CARE = 0xFF ///< DT_DONT_CARE
-} DIMM_TYPE;
-
-/// Number of Dimm
-typedef enum {
- _1DIMM = 0x01, ///< _1DIMM
- _2DIMM = 0x02, ///< _2DIMM
- _3DIMM = 0x04, ///< _3DIMM
- _4DIMM = 0x08, ///< _4DIMM
- NOD_DONT_CARE = 0xFF ///< NOD_DONT_CARE
-} NOD_SUPPORTED;
-
-/// Table header related definitions
-typedef struct {
- PSCFG_TYPE PSCType; ///< PSC Type
- DIMM_TYPE DimmType; ///< Dimm Type
- NOD_SUPPORTED NumOfDimm; ///< Numbef of dimm
- CPU_LOGICAL_ID LogicalCpuid; ///< Logical Cpuid
- UINT8 PackageType; ///< Package Type
- TECHNOLOGY_TYPE TechType; ///< Technology type
-} PSC_TBL_HEADER;
-
-/// Table entry
-typedef struct {
- PSC_TBL_HEADER Header; ///< PSC_TBL_HEADER
- UINT8 TableSize; ///< Table size
- VOID *TBLPtr; ///< Pointer of the table
-} PSC_TBL_ENTRY;
-
-#define NOD_DONT_CARE 0xFF
-#define PT_DONT_CARE 0xFF
-#define NP 1
-#define V1_5 1
-#define V1_35 2
-#define V1_25 4
-#define VOLT_ALL (V1_5 | V1_35 | V1_25)
-#define DIMM_SR 2
-#define DIMM_DR 4
-#define DIMM_QR 8
-#define DIMM_LR 2
-#define R0 1
-#define R1 2
-#define R2 4
-#define R3 8
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-AGESA_STATUS
-MemPConstructPsUDef (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- );
-
-BOOLEAN
-MemPGetDramTerm (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 ArraySize,
- IN CONST DRAM_TERM_ENTRY *DramTermPtr
- );
-
-AGESA_STATUS
-MemPConstructPsSHy3 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- );
-
-AGESA_STATUS
-MemPConstructPsUHy3 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- );
-
-AGESA_STATUS
-MemPConstructPsRHy3 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- );
-
-AGESA_STATUS
-MemPConstructPsUC32_3 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- );
-
-AGESA_STATUS
-MemPConstructPsRC32_3 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- );
-
-
-AGESA_STATUS
-MemPConstructPsSDr3 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- );
-
-AGESA_STATUS
-MemPConstructPsUDr3 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- );
-
-AGESA_STATUS
-MemPConstructPsRDr3 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- );
-
-AGESA_STATUS
-MemPConstructPsUDA3 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- );
-
-AGESA_STATUS
-MemPConstructPsSNi3 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- );
-
-AGESA_STATUS
-MemPConstructPsUNi3 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- );
-
-AGESA_STATUS
-MemPConstructPsSRb3 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- );
-
-AGESA_STATUS
-MemPConstructPsURb3 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- );
-
-AGESA_STATUS
-MemPConstructPsSPh3 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- );
-
-AGESA_STATUS
-MemPConstructPsUPh3 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- );
-
-AGESA_STATUS
-MemPConstructPsSDA3 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- );
-
-AGESA_STATUS
-MemPConstructPsSDA2 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- );
-
-AGESA_STATUS
-MemPConstructPsSLN3 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- );
-
-AGESA_STATUS
-MemPConstructPsULN3 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- );
-
-AGESA_STATUS
-MemPConstructPsRLN3 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- );
-
-AGESA_STATUS
-MemPConstructPsSON3 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- );
-
-AGESA_STATUS
-MemPConstructPsUON3 (
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN OUT CH_DEF_STRUCT *ChannelPtr,
- IN OUT MEM_PS_BLOCK *PsPtr
- );
-
-UINT16
-MemPGetPorFreqLimit (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 FreqLimitSize,
- IN CONST POR_SPEED_LIMIT *FreqLimitPtr
- );
-
-VOID
-MemPGetPORFreqLimitDef (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemPPSCFlow (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemPConstructRankTypeMap (
- IN UINT16 Dimm0,
- IN UINT16 Dimm1,
- IN UINT16 Dimm2,
- IN OUT UINT16 *RankTypeInTable
- );
-
-BOOLEAN
-MemPIsIdSupported (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN CPU_LOGICAL_ID LogicalId,
- IN UINT8 PackageType
- );
-
-UINT16
-MemPGetPsRankType (
- IN CH_DEF_STRUCT *CurrentChannel
- );
-
-BOOLEAN
-MemPRecPSCFlow (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemPRecConstructRankTypeMap (
- IN UINT16 Dimm0,
- IN UINT16 Dimm1,
- IN UINT16 Dimm2,
- IN OUT UINT16 *RankTypeInTable
- );
-
-BOOLEAN
-MemPRecIsIdSupported (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN CPU_LOGICAL_ID LogicalId,
- IN UINT8 PackageType
- );
-
-UINT16
-MemPRecGetPsRankType (
- IN CH_DEF_STRUCT *CurrentChannel
- );
-
-#endif /* _MP_H_ */
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/mport.h b/src/vendorcode/amd/agesa/Proc/Mem/mport.h
deleted file mode 100644
index f97edc8..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/mport.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mport.h
- *
- * API's to support different OS
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MPORT_H_
-#define _MPORT_H_
-
-///< 64 bit data structure
-///< lo - Lower 32 bits
-///< hi - Upper 32 bits
-typedef struct {
- UINT32 lo; ///< Lower 32 bits
- UINT32 hi; ///< Upper 32 bits
-} S_UINT64;
-/*
- * SBDFO - Segment Bus Device Function Offset
- * 31:28 Segment (4-bits)
- * 27:20 Bus (8-bits)
- * 19:15 Device (5-bits)
- * 14:12 Function(3-bits)
- * 11:00 Offset (12-bits)
- */
-typedef UINT32 SBDFO;
-
-#define GET_SIZE_OF(x) (sizeof (x) / sizeof (x[0]))
-
-#endif /* _MPORT_H_ */
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/mt.h b/src/vendorcode/amd/agesa/Proc/Mem/mt.h
deleted file mode 100644
index ad4d112..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/mt.h
+++ /dev/null
@@ -1,435 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mt.h
- *
- * Common Technology
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem)
- * @e \$Revision: 37555 $ @e \$Date: 2010-09-08 02:17:18 +0800 (Wed, 08 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MT_H_
-#define _MT_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-#define FIRST_PASS 1
-#define SECOND_PASS 2
-#define BIGPAGE_X8_RJ16 0x80
-#define BIGPAGE_X8 0x800000
-#define DQS_FAIL 1
-#define DQS_PASS 0
-#define DQS_WRITE_DIR 1
-#define DQS_READ_DIR 0
-#define MIN_DQS_WNDW 3
-#define ST_UNSTEADY 0
-#define ST_STEADY 1
-#define ST_GROSS_SWEEP 2
-#define ST_FINE_SWEEP 3
-#define ST_FINISH 4
-#define NIBBLE_0 0
-#define NIBBLE_1 1
-
-#define MAX_BYTELANES_PER_CHANNEL (8 + 1) ///< Max Bytelanes per channel
-
-#define MAX_FILTER_DLY_DDR2 0x20
-#define MAX_FILTER_DLY_DDR3 0x28
-
-#define NEW_RECEIVER_START_VALUE 0x4
-#define NEW_RECEIVER_STEP_1 4
-#define NEW_RECEIVER_STEP_2 7
-
-#define NEW_RECEIVER_FINAL_OFFSETVALUE 5
-
-#define DBG_PRINT_STAGE 18 // "Stage"
-#define DBG_PRINT_0_TO_64 23 // "0...64"
-#define DBG_SPACES_4 21 // 4 spaces
-#define DBG_POS_NEW_LINE 11 // New Line for POS training
-#define DBG_WR_DLY 24 // "Write Delay: "
-#define DBG_B_L_R_W_M 22 // " Bytelane Left Right Width Middle"
-#define DBG_RX_EN_NEW_LINE 25 // New Line for Rx En
-#define DBG_RX_EN_STAGE1 6 // "Receiver Enable Training Stage 1:"
-#define DBG_RX_EN_STAGE2 7 // "Receiver Enable Training Stage 2:"
-#define DBG_RX_EN_STAGE3 8 // "Receiver Enable Training Stage 3:"
-#define DBG_DLY_PER_BL 9 // "Dly per BL -"
-#define DBG_A_B_DLY 10 // "ALL BLs have Dly:"
-#define DBG_RCVR_PRT_VALUE 0x0010F // PORT for RX EN training to print a value
-#define DBG_RX_POS_PRT_VALUE 0x0011F // PORT for POS training to print a value
-
-#define DONE_FILTER 0 ///< optimized receiver enable training glitch search complete
-#define START_FILTER 1 ///< optimized receiver enable training start glitch filter search
-#define FILTER_FIRST_STAGE_COUNT 4 ///< optimized receiver enable training glitch filter first stage count
-#define FILTER_SECOND_STAGE_COUNT 7 ///< optimized receiver enable training glitch second stage count
-#define FILTER_OFFSET_VALUE 0x1C ///< optimized receiver enable training glitch filter offset value int preamble
-#define FILTER_WINDOW_SIZE 0x28 ///< optimized receiver enable training glitch filter search window size
-#define FILTER_MAX_REC_EN_DLY_VALUE 0x1FF ///< optimized receiver enable glitch filter max receiver value
-#define FILTER_NEW_RECEIVER_START_VALUE 0x0 ///< optimized receiver enable glitch filter Start value
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-/// List for Technology specific functions that are supported
-typedef enum {
- WlTrainingPrepareLrdimm, ///< Technology specific tasks to prepare LRDIMMs for Training
- LrdimmControlRegInit, ///< Technology specific tasks to send control words to initialize an LRDIMM
- LrdimmFreqChgCtrlWrd, ///< Technology specific tasks to send control words to reprogram LRDIMM's register
- LrdimmSendAllMRCmds, ///< Technology specific tasks to send all MR commands
- LrdimmRankMultiplication, ///< Determine Rank Multiplication to be used
- LrdimmBuf2DramTrain, ///< Perform buffer to DRAM training for LRDIMMs
- LrdimmSyncTrainedDlys, ///< Copy trained delay of the first rank of a QR LRDIMM to the third rank
-
- NumberOfTechHooks ///< Size of list
-} TECHNOLOGY_SPECIFIC_FUNC_INDEX;
-
-/// Structure for Technology block.
-typedef struct _MEM_TECH_BLOCK {
- MEM_NB_BLOCK *NBPtr; ///< point to northbridge block.
- MEM_PARAMETER_STRUCT *RefPtr; ///< point to parameter list.
-
- /* Temporary storage */
- UINT32 HwcrLo; ///< value of HWCR.
- UINT32 CR4reg; ///< CR4 register value.
- UINT8 DramEcc; ///< value of Dram ECC bit.
- UINT8 *TestBufPtr; ///< point to buffer to store read-back data.
- UINT8 *PatternBufPtr; ///< point to pattern buffer.
- UINT16 PatternLength; ///< the length of pattern buffer in cache lines.
- UINT8 Direction; ///< direction during training.
- UINT8 ChipSel; ///< chip select number.
- UINT16 MaxDlyForMaxRdLat; ///< Largest possible value for Receiver enable delay.
- UINT16 PrevSpeed; ///< Previous MemClk frequency
- TRAINING_TYPE TrainingType; ///< Type of training currently being done
- UINT8 TargetDIMM; ///< Target DIMM to being trained
- INT16 WLCriticalDelay; ///< Minimum WL Dly of all byte lanes and all DIMMs
- UINT8 Bytelane; ///< Bytelane being trained
- UINT8 TrnNibble; ///< Nibble being trained
-
-
- UINT8 Pass; ///< current pass of training.
- UINT16 DqsRdWrPosSaved; ///< for position training byte lane saved flag
- UINT16 DqsRcvEnSaved; ///< for TrainRcvrEn UINT8 lane saved flag
- UINT16 DqsRcvEnSavedS1; ///< for TrainRcvrEn UINT8 lane saved flag
- UINT16 DqsRcvEnFirstPassVal; ///< for TrainRcvrEn UINT8 lane saved flag
- BOOLEAN GetFirstPassVal; ///< If the first passing value has been found.
- BOOLEAN RevertPassVal; ///< Flag to restart training during training process when glitch is found.
- UINT8 MaxFilterDly; ///< Maximum filter delay value for RcvrTraining.
- UINT16 RcvrEnDlyOpt[MAX_BYTELANES_PER_CHANNEL]; ///< Receiver Enable delay for optimized filter
- UINT16 MaxRcvrEnDlyBlOpt[MAX_BYTELANES_PER_CHANNEL]; ///< Max Receiver Enable delay for optimized filter
- UINT16 RcvrEnDlyLimitOpt[MAX_BYTELANES_PER_CHANNEL]; ///< Receiver Enable delay Limit for optimized filter
- UINT16 FilterStatusOpt[MAX_BYTELANES_PER_CHANNEL]; ///< Filter status to indicate if a ByteLane is "DONE", "SKIP" or "CONTINUE"
- UINT16 FilterCountOpt; ///< Filter count to indicate the total number of ByteLanes completed
- BOOLEAN DqsRcvEnSavedOpt[MAX_BYTELANES_PER_CHANNEL]; ///< for optimized TrainRcvrEn lane saved flag
- UINT16 DqsRcvEnFirstPassValOpt[MAX_BYTELANES_PER_CHANNEL]; ///< for TrainRcvrEn UINT8 lane saved flag for optimized
- BOOLEAN GetFirstPassValOpt[MAX_BYTELANES_PER_CHANNEL]; ///< If the first passing value has been found for optimized.
- BOOLEAN RevertPassValOpt[MAX_BYTELANES_PER_CHANNEL]; ///< Flag to restart training during training process when glitch is found for optimized.
- UINT8 MaxFilterDlyBlOpt[MAX_BYTELANES_PER_CHANNEL]; ///< Maximum filter delay value for RcvrTraining for optimized.
- BOOLEAN IncBy1ForNextCountOpt[MAX_BYTELANES_PER_CHANNEL]; ///< Used to determine when to increment by 1 in second stage of opt. rec. en. training
- UINT8 FilterSidePassCountOpt[MAX_BYTELANES_PER_CHANNEL]; ///< Indicates that previous side passed
- UINT16 DiffSeedGrossSeedPreGross[MAX_BYTELANES_PER_CHANNEL]; ///< Gross difference between GrossSeed and SeedPreGross for HwRxEn Training.
- UINT16 PrevPassRcvEnDly[MAX_BYTELANES_PER_CHANNEL]; ///< Receiver Enable Delay value from the previous pass
- BOOLEAN SmallDqsPosWindow; ///< Status flag to record small DQS position window event
- UINT8 WlNibbleDly[MAX_BYTELANES_PER_CHANNEL]; ///< Nibble based trainig results for Nibble 0 of Write Levelization
- UINT16 WlNibble0Seed[MAX_BYTELANES_PER_CHANNEL]; ///< Nibble based trainig seed value for Nibble 0 Write Levelization
- UINT8 RxEnNibbleDly[MAX_BYTELANES_PER_CHANNEL]; ///< Nibble based trainig results for Nibble 0 of Rx En training
-
- /* PUBLIC functions */
- VOID (*SendAllMRCmds) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 ChipSel); ///< Send MRS command.
- VOID (*FreqChgCtrlWrd) (struct _MEM_TECH_BLOCK *TechPtr); ///< Frequency change control word.
- BOOLEAN (*SetDramMode) (struct _MEM_TECH_BLOCK *TechPtr); ///< Set dram mode (DDR2 or DDR3).
- BOOLEAN (*DimmPresence) (struct _MEM_TECH_BLOCK *TechPtr); ///< determines if DIMMs present.
- BOOLEAN (*SpdCalcWidth) (struct _MEM_TECH_BLOCK *TechPtr); ///< check the symmetry of DIMM pairs.
- BOOLEAN (*SpdGetTargetSpeed) (struct _MEM_TECH_BLOCK *TechPtr); ///< get supported frequency.
- BOOLEAN (*AutoCycTiming) (struct _MEM_TECH_BLOCK *TechPtr); ///< configure timing based on spd data.
- BOOLEAN (*SpdSetBanks) (struct _MEM_TECH_BLOCK *TechPtr); ///< set bank address.
- BOOLEAN (*SetDqsEccTmgs) (struct _MEM_TECH_BLOCK *TechPtr); ///< DQS training.
- VOID (*GetCSIntLvAddr) (UINT8 BankEnc, UINT8 *LowBit, UINT8 *HiBit); ///< Get Chip select interleave address.
- VOID (*AdjustTwrwr) (struct _MEM_TECH_BLOCK *TechPtr); ///< Adjust Twrwr for certain dimm technology.
- VOID (*AdjustTwrrd) (struct _MEM_TECH_BLOCK *TechPtr); ///< Adjust Twrrd for certain dimm technology.
- INT8 (*GetLD) (struct _MEM_TECH_BLOCK *TechPtr); ///< Get LD value for certain dimm technology.
- VOID (*DramInit) (struct _MEM_TECH_BLOCK *TechPtr); ///< dram initialization.
-
- /* PRIVATE functions */
- VOID (*InitDQSPos4RcvrEn) (struct _MEM_TECH_BLOCK *TechPtr); ///< Initialize training register before training.
- VOID (*SetRcvrEnDly) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver, UINT16 RcvEnDly); ///< Set receiver enable delay register value.
- VOID (*LoadRcvrEnDly) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver); ///< Load receiver enable delay register value.
- BOOLEAN (*SaveRcvrEnDly) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver, UINT16 RcvEnDly, UINT16 cmpResultRank0, UINT16 cmpResultRank1); ///< Save receiver enable delay register value.
- BOOLEAN (*SaveRcvrEnDlyFilter) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver, UINT16 RcvEnDly, UINT16 cmpResultRank0, UINT16 cmpResultRank1); ///< saves passing DqsRcvEnDly values to the stack.
- VOID (*ResetDCTWrPtr) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver); ///< resets the DCT input buffer write pointer.
- UINT16 (*Compare1ClPattern) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Buffer[], UINT8 Pattern[]); ///< Compare training pattern of 1 cache line.
- VOID (*SkipChipSelPass1) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 *ChipSel); ///< skips odd chip select if training at 800MT or above.
- VOID (*SkipChipSelPass2) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 *ChipSel); ///< skips odd chip select if training at 800MT or above.
- UINT16 (*CompareTestPatternFilter) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Buffer[], UINT8 Pattern[], UINT16 ByteCount); ///< compare training pattern with filter.
- UINT8 (*MaxByteLanes) (VOID); ///< return maximum number of bytelanes.
- VOID (*SetDQSDelayCSR) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 ByteLane, UINT8 Dly); ///< Set CSR.
- VOID (*DQSWindowSave) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 ByteLane, UINT8 DlyMin, UINT8 DlyMax); ///< programs the trained DQS delay for the specified byte lane and stores its DQS window for reference.
- BOOLEAN (*FindMaxDlyForMaxRdLat) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 *ChipSel); ///< Find maximum receiver enable delay value.
- UINT8 (*DlyTableWidth) (VOID); ///< return the width of the delay tables (eg. RcvEnDlys, WrDqsDlys,...) in number of bytes.
- UINT16 (*Compare1ClPatternOpt) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Buffer[], UINT8 Pattern[], UINT8 Side, UINT8 Receiver, BOOLEAN Side1En); ///< Compare training pattern of 1 cache line.
- VOID (*LoadRcvrEnDlyOpt) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver); ///< Load receiver enable delay register value.
- VOID (*SetRcvrEnDlyOpt) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver, UINT16 RcvEnDly); ///< Set receiver enable delay register value.
- BOOLEAN (*CheckRcvrEnDlyLimitOpt) (struct _MEM_TECH_BLOCK *TechPtr); ///< Find limit for all bytelanes
- UINT16 (*GetMaxValueOpt) (struct _MEM_TECH_BLOCK *TechPtr); ///< Returns the max value of all bytelanes
- VOID (*InitializeVariablesOpt) (struct _MEM_TECH_BLOCK *TechPtr); ///< Initialized variables for optimized training
- BOOLEAN (*SetSweepErrorOpt)(struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver, UINT8 DCT, BOOLEAN ErrorCheck); ///< records any errors generated from optimized sweep
- VOID (*LoadInitialRcvrEnDlyOpt) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver); ///< Load the starting value for receiver DQS training.
- BOOLEAN (*GetDimmSpdBuffer) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 **SpdBuffer, UINT8 Dimm); ///< Gets pointer to spd buffer for a dimm on the current channel, if present
-
- /* Technology Specific Hooks */
- BOOLEAN (*(TechnologySpecificHook[NumberOfTechHooks])) (struct _MEM_TECH_BLOCK *TechPtr, VOID *OptParam); ///< Technology specific functions
-} MEM_TECH_BLOCK;
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-VOID
-MemTDimmByteTrainInit (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemTTrainMaxLatency (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemTSetDQSEccTmgs (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemTSetDQSEccTmgsRDdr3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemTTrainRcvrEnSwPass1 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemTTrainDQSEdgeDetectSw (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-BOOLEAN
-MemTDramInitSw3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-VOID
-MemTDramInitHw (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-BOOLEAN
-MemTFeatDef (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-BOOLEAN
-MemTSaveRcvrEnDlyByteFilter (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Receiver,
- IN UINT16 RcvEnDly,
- IN UINT16 CmpResultRank0,
- IN UINT16 CmpResultRank1
- );
-
-BOOLEAN
-MemTSaveRcvrEnDlyByteFilterOpt (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Receiver,
- IN UINT16 RcvEnDly,
- IN UINT16 CmpResultRank0,
- IN UINT16 CmpResultRank1
- );
-
-BOOLEAN
-MemTNewRevTrainingSupport (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemTTrainOptRcvrEnSwPass1 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemTWriteLevelizationHw3Pass1 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemTWriteLevelizationHw3Pass2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemTPreparePhyAssistedTraining (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemTExitPhyAssistedTraining (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemTDqsTrainRcvrEnHwPass1 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemTDqsTrainRcvrEnHwPass2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-VOID
-MemRecTSetWrDatRdDqs (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 WrDatDly
- );
-
-VOID
-MemRecTTrainDQSPosSw (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-VOID
-MemRecTTrainRcvrEnSw (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-VOID
-MemRecTTrainRcvrEnHw (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-VOID
-MemRecTBeginTraining (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-VOID
-MemRecTEndTraining (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemTSetSweepErrorOptByte (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Receiver,
- IN UINT8 Dct,
- IN BOOLEAN ErrorCheck
- );
-
-VOID
-MemTInitializeVariablesOptByte (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-UINT16
-MemTGetMaxValueOptByte (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemTCheckRcvrEnDlyLimitOptByte (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-VOID
-MemTMarkTrainFail (
- IN OUT MEM_TECH_BLOCK *TechPtr
-);
-
-VOID
-MemTBeginTraining (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-VOID
-MemTEndTraining (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-VOID
-MemTSetDQSDelayAllCSR (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Dly
- );
-
-BOOLEAN
-MemTExitPhyAssistedTrainingClient3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemTFindMaxRcvrEnDlyRdDqsDlyByte (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- OUT UINT8 *ChipSel
- );
-
-VOID
-MemTSendCtlWord3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 CmdNum,
- IN UINT8 Value
- );
-
-VOID
-MemTCommonTechInit (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemTLrdimmConstructor3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-#endif /* _MT_H_ */
diff --git a/src/vendorcode/amd/agesa/Proc/Mem/mu.h b/src/vendorcode/amd/agesa/Proc/Mem/mu.h
deleted file mode 100644
index 2a9067d..0000000
--- a/src/vendorcode/amd/agesa/Proc/Mem/mu.h
+++ /dev/null
@@ -1,238 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mu.h
- *
- * Utility support
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem)
- * @e \$Revision: 38442 $ @e \$Date: 2010-09-24 06:39:57 +0800 (Fri, 24 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MU_H_
-#define _MU_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-#ifndef PSO_ENTRY
- #define PSO_ENTRY UINT8
-#endif
-
-//
-// Maximum value macro
-//
-#define MAX(X, Y) (((X) < (Y)) ? (Y) : (X))
-//
-// Minimum Value macro
-//
-#define MIN(X, Y) (((X) < (Y)) ? (X) : (Y))
-//
-// Absolute Value Macro
-//
-#define ABS(X) (((X) < 0) ? (-(X)) : (X))
-
-
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/// Test patterns for DQS training
-typedef enum {
- TestPattern0, ///< Test pattern used in first pass of receiver enable training
- TestPattern1, ///< Test pattern used in first pass of receiver enable training
- TestPattern2, ///< Test pattern used in second pass of receiver enable training
- TestPatternJD1B, ///< 72-bit test pattern used in position training (ganged mode)
- TestPatternJD1A, ///< 72-bit test pattern used in position training
- TestPatternJD256B, ///< 256-bit test pattern used in position training (ganged mode)
- TestPatternJD256A, ///< 256-bit test pattern used in position training
- TestPatternML, ///< Test pattern used in first pass of max latency training
- TestPattern3, ///< Test pattern used in first pass of receiver enable training
- TestPattern4 ///< Test pattern used in first pass of receiver enable training
-} TRAIN_PATTERN;
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-VOID
-MemUWriteCachelines (
- IN UINT32 Address,
- IN UINT8 Pattern[],
- IN UINT16 ClCount
- );
-
-VOID
-MemUReadCachelines (
- IN UINT8 Buffer[],
- IN UINT32 Address,
- IN UINT16 ClCount
- );
-
-VOID
-MemUDummyCLRead (
- IN UINT32 Address
- );
-
-VOID
-MemUFlushPattern (
- IN UINT32 Address,
- IN UINT16 ClCount
- );
-
-
-VOID
-MemUFillTrainPattern (
- IN TRAIN_PATTERN Pattern,
- IN UINT8 Buffer[],
- IN UINT16 Size
- );
-
-UINT32
-MemUSetUpperFSbase (
- IN UINT32 Address,
- IN OUT MEM_DATA_STRUCT *MemPtr
- );
-
-VOID
-MemUSetTargetWTIO (
- IN UINT32 Address,
- IN OUT MEM_DATA_STRUCT *MemPtr
- );
-
-VOID
-MemUResetTargetWTIO (
- IN OUT MEM_DATA_STRUCT *MemPtr
- );
-
-VOID
-MemUProcIOClFlush (
- IN UINT32 Address,
- IN UINT16 ClCount,
- IN OUT MEM_DATA_STRUCT *MemPtr
- );
-
-VOID
-MemUWait10ns (
- IN UINT32 Count,
- IN OUT MEM_DATA_STRUCT *MemPtr
- );
-
-VOID
-MemUGetWrLvNblErr (
- IN OUT UINT16 *ErrBitmap,
- IN UINT32 TestAddr,
- IN UINT16 ClCount
- );
-
-VOID
-AlignPointerTo16Byte (
- IN OUT UINT8 **BufferPtrPtr
- );
-
-VOID *
-FindPSOverrideEntry (
- IN PSO_TABLE *PlatformMemoryConfiguration,
- IN PSO_ENTRY EntryType,
- IN UINT8 SocketID,
- IN UINT8 ChannelID
- );
-
-UINT8
-GetMaxDimmsPerChannel (
- IN PSO_TABLE *PlatformMemoryConfiguration,
- IN UINT8 SocketID,
- IN UINT8 ChannelID
- );
-
-UINT8
-GetMaxChannelsPerSocket (
- IN PSO_TABLE *PlatformMemoryConfiguration,
- IN UINT8 SocketID,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-UINT8
-GetMaxCSPerChannel (
- IN PSO_TABLE *PlatformMemoryConfiguration,
- IN UINT8 SocketID,
- IN UINT8 ChannelID
- );
-
-UINT8
-GetSpdSocketIndex (
- IN PSO_TABLE *PlatformMemoryConfiguration,
- IN UINT8 SocketID,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-UINT8
-GetSpdChannelIndex (
- IN PSO_TABLE *PlatformMemoryConfiguration,
- IN UINT8 SocketID,
- IN UINT8 ChannelID,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-UINT32
-GetVarMtrrHiMsk (
- IN CPU_LOGICAL_ID *LogicalIdPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-MemUMFenceInstr (
- VOID
- );
-
-#endif /* _MU_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/CPU/cpuRecovery.c b/src/vendorcode/amd/agesa/Proc/Recovery/CPU/cpuRecovery.c
deleted file mode 100644
index 67140cd..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/CPU/cpuRecovery.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU Recovery API, and related functions.
- *
- * Contains code that implements the CPU Recovery functionality
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Recovery/CPU
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "cpuRecovery.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-#include "Table.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_RECOVERY_CPU_CPURECOVERY_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Performs CPU related initialization at the recovery entry point
- *
- * This function processes the MSR and PCI register tables.
- *
- * @param[in] CpuRecoveryParams Required input parameters for recovery CPU
- * initialization.
- *
- * @retval AGESA_SUCCESS Always succeeds.
- *
- */
-AGESA_STATUS
-AmdCpuRecovery (
- IN AMD_CPU_RECOVERY_PARAMS *CpuRecoveryParams
- )
-{
- SetRegistersFromTables (&CpuRecoveryParams->PlatformConfig, &CpuRecoveryParams->StdHeader);
- LoadMicrocodePatch (&CpuRecoveryParams->StdHeader);
- return (AGESA_SUCCESS);
-}
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/CPU/cpuRecovery.h b/src/vendorcode/amd/agesa/Proc/Recovery/CPU/cpuRecovery.h
deleted file mode 100644
index 5f2d3b5..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/CPU/cpuRecovery.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU Recovery API, and related function prototypes.
- *
- * Contains code that implements the CPU Recovery functionality
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Recovery/CPU
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _CPU_RECOVERY_H_
-#define _CPU_RECOVERY_H_
-
-/*----------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *----------------------------------------------------------------------------------------
- */
-
-// These are P U B L I C functions
-AGESA_STATUS
-AmdCpuRecovery (
- IN AMD_CPU_RECOVERY_PARAMS *CpuRecoveryParams
- );
-
-#endif // _CPU_RECOVERY_H_
-
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/GNB/GfxRecovery.c b/src/vendorcode/amd/agesa/Proc/Recovery/GNB/GfxRecovery.c
deleted file mode 100644
index 8024993..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/GNB/GfxRecovery.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD GFX Recovery API, and related functions.
- *
- * Contains code that implements the GFX Recovery functionality
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Recovery/GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "GfxRecovery.h"
-#include "OptionGfxRecovery.h"
-#include "Filecode.h"
-#define FILECODE PROC_RECOVERY_GNB_GFXRECOVERY_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-extern OPTION_GFX_RECOVERY_CONFIGURATION OptionGfxRecoveryConfiguration; // global user config record
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Performs Gfx related initialization at the recovery entry point
- *
- * This function processes the MSR and PCI register tables.
- *
- * @param[in] StdHeader global state, input data
- *
- * @retval AGESA_SUCCESS Always succeeds.
- *
- */
-AGESA_STATUS
-AmdGfxRecovery (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- return ((*(OptionGfxRecoveryConfiguration.GfxRecoveryFeature)) (StdHeader));
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * This function will called if OPTION_GfxRecovery is true
- *
- * @param[in, out] StdHeader Standard Head Pointer
- *
- * @retval AGESA_STATUS
- */
-AGESA_STATUS
-GetGfxRecoveryMain (
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- //to be done
- return AGESA_SUCCESS;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/GNB/GfxRecovery.h b/src/vendorcode/amd/agesa/Proc/Recovery/GNB/GfxRecovery.h
deleted file mode 100644
index 70c9778..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/GNB/GfxRecovery.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD GFX Recovery API, and related function prototypes.
- *
- * Contains code that implements the Gfx Recovery functionality
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Recovery/GNB
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _GFX_RECOVERY_H_
-#define _GFX_RECOVERY_H_
-
-/*----------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *----------------------------------------------------------------------------------------
- */
-
-// These are P U B L I C functions
-AGESA_STATUS
-AmdGfxRecovery (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif // _GNB_RECOVERY_H_
-
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/GNB/GnbRecovery.c b/src/vendorcode/amd/agesa/Proc/Recovery/GNB/GnbRecovery.c
deleted file mode 100644
index 0c787d9..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/GNB/GnbRecovery.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD GNB Recovery API, and related functions.
- *
- * Contains code that implements the GNB Recovery functionality
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Recovery/GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "Gnb.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include GNB_MODULE_DEFINITIONS (GnbNbInitLibV1)
-#include "NbInitRecovery.h"
-#include "Filecode.h"
-#define FILECODE PROC_RECOVERY_GNB_GNBRECOVERY_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Performs Gnb Recovery related initialization at the recovery entry point
- *
- * This function processes the MSR and PCI register tables.
- *
- *
- * @param[in] StdHeader global state, input data
- *
- * @retval AGESA_SUCCESS Always succeeds.
- *
- */
-AGESA_STATUS
-AmdGnbRecovery (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- PCI_ADDR NbPciAddress;
- NbPciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0);
- NbInitOnPowerOnRecovery (NbPciAddress, StdHeader);
- GnbSetTom (NbPciAddress, StdHeader);
- return AGESA_SUCCESS;
-}
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/GNB/NbInitRecovery.c b/src/vendorcode/amd/agesa/Proc/Recovery/GNB/NbInitRecovery.c
deleted file mode 100644
index d4b831d..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/GNB/NbInitRecovery.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Various NB Recovery initialization services
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Gnb.h"
-#include GNB_MODULE_DEFINITIONS (GnbCommonLib)
-#include "GnbRegistersON.h"
-#include "Filecode.h"
-#define FILECODE PROC_RECOVERY_GNB_NBINITRECOVERY_FILECODE
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-typedef struct {
- UINT8 Reg;
- UINT32 Mask;
- UINT32 Data;
-} NB_REGISTER_RECOVERY_ENTRY;
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-
-
-CONST NB_REGISTER_RECOVERY_ENTRY NbPciInitRecoveryTable [] = {
- {
- D0F0x04_ADDRESS,
- 0xffffffff,
- 0x1 << D0F0x04_MemAccessEn_WIDTH
- }
-};
-
-CONST NB_REGISTER_RECOVERY_ENTRY NbMiscInitRecoveryTable [] = {
- {
- D0F0x64_x51_ADDRESS,
- 0xffffffff,
- 1 << D0F0x64_x51_SetPowEn_OFFSET
- }
-};
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Init NB at Power On
- *
- *
- * @param[in] NbPciAddress Gnb PCI address
- * @param[in] StdHeader Standard Configuration Header
- */
-
-
-VOID
-NbInitOnPowerOnRecovery (
- IN PCI_ADDR NbPciAddress,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINTN Index;
- // Init NBCONFIG
- for (Index = 0; Index < (sizeof (NbPciInitRecoveryTable) / sizeof (NB_REGISTER_RECOVERY_ENTRY)); Index++) {
- GnbLibPciRMW (
- NbPciAddress.AddressValue | NbPciInitRecoveryTable[Index].Reg,
- AccessWidth32,
- NbPciInitRecoveryTable[Index].Mask,
- NbPciInitRecoveryTable[Index].Data,
- StdHeader
- );
- }
-
- // Init MISCIND
- for (Index = 0; Index < (sizeof (NbMiscInitRecoveryTable) / sizeof (NB_REGISTER_RECOVERY_ENTRY)); Index++) {
- GnbLibPciIndirectRMW (
- NbPciAddress.AddressValue | D0F0x60_ADDRESS,
- NbMiscInitRecoveryTable[Index].Reg | IOC_WRITE_ENABLE,
- AccessWidth32,
- NbMiscInitRecoveryTable[Index].Mask,
- NbMiscInitRecoveryTable[Index].Data,
- StdHeader
- );
- }
- return;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/GNB/NbInitRecovery.h b/src/vendorcode/amd/agesa/Proc/Recovery/GNB/NbInitRecovery.h
deleted file mode 100644
index 651aed6..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/GNB/NbInitRecovery.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Various NB Recovery initialization services
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: GNB
- * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _NBINITRECOVERY_H_
-#define _NBINITRECOVERY_H_
-
-
-VOID
-NbInitOnPowerOnRecovery (
- IN PCI_ADDR NbPciAddress,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/HT/htInitRecovery.c b/src/vendorcode/amd/agesa/Proc/Recovery/HT/htInitRecovery.c
deleted file mode 100644
index f034b1a..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/HT/htInitRecovery.c
+++ /dev/null
@@ -1,163 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Init the Socket and Node maps for Recovery mode.
- *
- * Create the Socket and Node maps just like normal boot,
- * except that they only indicate the BSC is present.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: HyperTransport
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "Topology.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_RECOVERY_HT_HTINITRECOVERY_FILECODE
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Get new Socket and Node Maps.
- *
- * Put the Socket Die Table and the Node Table in heap with known handles.
- *
- * @param[out] SocketDieToNodeMap The Socket, Module to Node info map
- * @param[out] NodeToSocketDieMap The Node to Socket, Module map.
- * @param[in] StdHeader Header for library and services.
- */
-VOID
-STATIC
-NewNodeAndSocketTablesRecovery (
- OUT SOCKET_DIE_TO_NODE_MAP *SocketDieToNodeMap,
- OUT NODE_TO_SOCKET_DIE_MAP *NodeToSocketDieMap,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 i;
- UINT8 j;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
- // Allocate heap for the table
- AllocHeapParams.RequestedBufferSize = (((MAX_SOCKETS) * (MAX_DIES)) * sizeof (SOCKET_DIE_TO_NODE_ITEM));
- AllocHeapParams.BufferHandle = SOCKET_DIE_MAP_HANDLE;
- AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
- if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
- // HeapAllocateBuffer must set BufferPtr to valid or NULL.
- *SocketDieToNodeMap = (SOCKET_DIE_TO_NODE_MAP)AllocHeapParams.BufferPtr;
- ASSERT (SocketDieToNodeMap != NULL);
- // Initialize shared data structures
- for (i = 0; i < MAX_SOCKETS; i++) {
- for (j = 0; j < MAX_DIES; j++) {
- (**SocketDieToNodeMap)[i][j].Node = HT_LIST_TERMINAL;
- (**SocketDieToNodeMap)[i][j].LowCore = HT_LIST_TERMINAL;
- (**SocketDieToNodeMap)[i][j].HighCore = HT_LIST_TERMINAL;
- }
- }
- }
- // Allocate heap for the table
- AllocHeapParams.RequestedBufferSize = (MAX_NODES * sizeof (NODE_TO_SOCKET_DIE_ITEM));
- AllocHeapParams.BufferHandle = NODE_ID_MAP_HANDLE;
- AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
- if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
- // HeapAllocateBuffer must set BufferPtr to valid or NULL.
- *NodeToSocketDieMap = (NODE_TO_SOCKET_DIE_MAP)AllocHeapParams.BufferPtr;
- ASSERT (NodeToSocketDieMap != NULL);
- // Initialize shared data structures
- for (i = 0; i < MAX_NODES; i++) {
- (**NodeToSocketDieMap)[i].Socket = HT_LIST_TERMINAL;
- (**NodeToSocketDieMap)[i].Die = HT_LIST_TERMINAL;
- }
- }
-}
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Initialize the Node and Socket maps for an AP Core.
- *
- * In each core's local heap, create a Node to Socket map and a Socket/Module to Node map.
- * The mapping is filled in by reading the AP Mailboxes from PCI config on each node.
- *
- * @param[in] StdHeader global state, input data
- *
- * @retval AGESA_SUCCESS Always succeeds.
- */
-AGESA_STATUS
-AmdHtInitRecovery (
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- AP_MAILBOXES NodeApMailBox;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
- SOCKET_DIE_TO_NODE_MAP SocketDieToNodeMap;
- NODE_TO_SOCKET_DIE_MAP NodeToSocketDieMap;
-
- NodeApMailBox.ApMailInfo.Info = 0;
- NodeApMailBox.ApMailExtInfo.Info = 0;
-
- // Allocate heap for caching the mailboxes
- AllocHeapParams.RequestedBufferSize = sizeof (AP_MAILBOXES);
- AllocHeapParams.BufferHandle = LOCAL_AP_MAIL_BOX_CACHE_HANDLE;
- AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
- if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
- *(AP_MAILBOXES *)AllocHeapParams.BufferPtr = NodeApMailBox;
- }
-
- NewNodeAndSocketTablesRecovery (&SocketDieToNodeMap, &NodeToSocketDieMap, StdHeader);
- // HeapAllocateBuffer must set BufferPtr to valid or NULL, so the checks below are ok.
-
- // There is no option to not have socket - node maps, if they aren't allocated that is a fatal bug.
- ASSERT (SocketDieToNodeMap != NULL);
- ASSERT (NodeToSocketDieMap != NULL);
-
- (*SocketDieToNodeMap)[0][0].Node = 0;
- (*SocketDieToNodeMap)[0][0].LowCore = 0;
- (*SocketDieToNodeMap)[0][0].HighCore = 0;
-
- // We lie about being Socket 0 and Module 0 always, it isn't necessarily true.
- (*NodeToSocketDieMap)[0].Socket = (UINT8)0;
- (*NodeToSocketDieMap)[0].Die = (UINT8)0;
-
- return AGESA_SUCCESS;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/HT/htInitReset.c b/src/vendorcode/amd/agesa/Proc/Recovery/HT/htInitReset.c
deleted file mode 100644
index 9d58026..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/HT/htInitReset.c
+++ /dev/null
@@ -1,332 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Recovery HT, a Hypertransport init for Boot Blocks. For normal
- * boots, run Recovery HT first in boot block, then run full HT init
- * in the system BIOS. Recovery HT moves the devices on the chain with
- * the southbridge to their assigned device IDS, so that all their PCI
- * Config space is accessible.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Recovery HyperTransport
- * @e \$Revision: 35740 $ @e \$Date: 2010-07-30 00:04:17 +0800 (Fri, 30 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "AdvancedApi.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_RECOVERY_HT_HTINITRESET_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define MAX_NODES 1
-#define MAX_LINKS 8
-
-extern CONST AMD_HT_RESET_INTERFACE HtOptionResetDefaults;
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/**
- * Our global state data structure.
- *
- * Keep track of inputs and outputs, and keep any working state.
- */
-typedef struct {
- AMD_HT_RESET_INTERFACE *HtBlock; ///< The interface
- AGESA_STATUS Status; ///< Remember the highest severity status event
- VOID *ConfigHandle; ///< Config Pointer, opaque handle for passing to lib
-} HTR_STATE_DATA;
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/***************************************************************************
- *** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS ***
- ***************************************************************************/
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Enable Routing Tables.
- *
- * Turns routing tables on for a node zero.
- *
- * @param[in] State Our State
- */
-
-VOID
-STATIC
-HtrEnableRoutingTables (
- IN HTR_STATE_DATA *State
- )
-{
- PCI_ADDR Reg;
- UINT32 Temp;
- Temp = 0;
- Reg.AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0x6C);
- LibAmdPciWriteBits (Reg, 0, 0, &Temp, State->ConfigHandle);
-}
-
-/***************************************************************************
- *** Non-coherent init code ***
- *** Algorithms ***
- ***************************************************************************/
-/*----------------------------------------------------------------------------------------*/
-/**
- * Process the SouthBridge Link.
- *
- * Process a non-coherent link, and setting the device ID for all devices found.
- *
- * @param[in] State Our State, Inputs
- */
-VOID
-STATIC
-HtrProcessLink (
- IN HTR_STATE_DATA *State
- )
-{
- UINT32 CurrentBUID;
- UINT32 Temp;
- UINT32 UnitIDcnt;
- PCI_ADDR CurrentPtr;
- UINT8 Depth;
- BUID_SWAP_LIST *SwapPtr;
- PCI_ADDR Link1ControlRegister;
- BOOLEAN IsCaveDevice;
-
- // No PCI init to run, everything has to be on Bus zero. This makes fewer
- // northbridge dependencies.
- //
- // Assign BUIDs so that config space for all devices is visible.
- //
- if (State->HtBlock->ManualBuidSwapList != NULL) {
- // Manual non-coherent BUID assignment
- // Assign BUID's per manual override
- //
- SwapPtr = &(State->HtBlock->ManualBuidSwapList->SwapList);
- Depth = 0;
- while (SwapPtr->Swaps[Depth].FromId != 0xFF) {
- CurrentPtr.AddressValue = MAKE_SBDFO (0, 0, SwapPtr->Swaps[Depth].FromId, 0, 0);
-
- do {
- LibAmdPciFindNextCap (&CurrentPtr, State->ConfigHandle);
- ASSERT (CurrentPtr.AddressValue != ILLEGAL_SBDFO);
- LibAmdPciRead (AccessWidth32, CurrentPtr, &Temp, State->ConfigHandle);
- } while ((Temp & (UINT32)0xE00000FF) != (UINT32)0x00000008); // HyperTransport Slave Capability
-
- CurrentBUID = SwapPtr->Swaps[Depth].ToId;
- // Set the device's BUID
- LibAmdPciWriteBits (CurrentPtr, 20, 16, &CurrentBUID, State->ConfigHandle);
- Depth++;
- }
- } else {
- // Automatic non-coherent device detection
- Depth = 0;
- CurrentBUID = 1;
- for (;;) {
- CurrentPtr.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0);
-
- LibAmdPciRead (AccessWidth32, CurrentPtr, &Temp, State->ConfigHandle);
- if (Temp == (UINT32)0xFFFFFFFF) {
- // No device found at currentPtr
- break;
- }
-
- // HyperTransport Slave Capability
- do {
- LibAmdPciFindNextCap (&CurrentPtr, State->ConfigHandle);
- if (CurrentPtr.AddressValue == ILLEGAL_SBDFO) {
- // There is a device at currentPtr, but it isn't an HT device.
- return;
- }
- LibAmdPciRead (AccessWidth32, CurrentPtr, &Temp, State->ConfigHandle);
- } while ((Temp & (UINT32)0xE00000FF) != (UINT32)0x00000008); // HyperTransport Slave Capability
-
- // Get the device's Unit ID Count.
- LibAmdPciReadBits (CurrentPtr, 25, 21, &UnitIDcnt, State->ConfigHandle);
- if ((UnitIDcnt + CurrentBUID) > 24) {
- // An error handler for the case where we run out of BUID's on a chain
- State->Status = AGESA_ERROR;
- ASSERT (FALSE);
- return;
- }
- // While we are still certain we are accessing this device, remember if it is a cave device.
- // This is found by reading EOC from the Link 1 Control Register.
- Link1ControlRegister = CurrentPtr;
- Link1ControlRegister.Address.Register += 8;
- LibAmdPciReadBits (Link1ControlRegister, 6, 6, &Temp, State->ConfigHandle);
- IsCaveDevice = ((Temp == 0) ? FALSE : TRUE);
-
- // Set the device's BUID
- IDS_HDT_CONSOLE (HT_TRACE, "Device found at depth=%d.\n", Depth);
- LibAmdPciWriteBits (CurrentPtr, 20, 16, &CurrentBUID, State->ConfigHandle);
-
- CurrentPtr.Address.Device = CurrentBUID;
- // Get the device's BUID
- LibAmdPciReadBits (CurrentPtr, 20, 16, &Temp, State->ConfigHandle);
- if (Temp != CurrentBUID) {
- if ((Depth == 0) && IsCaveDevice) {
- // If the chain only consists of a single cave device, that device may have retained zero
- // for it's BUID.
- CurrentPtr.Address.Device = 0;
- LibAmdPciReadBits (CurrentPtr, 20, 16, &Temp, State->ConfigHandle);
- if (Temp == 0) {
- // Per HyperTransport specification, devices not accepting BUID reassignment hardwire BUID to zero.
- Depth++;
- // Success!
- IDS_HDT_CONSOLE (HT_TRACE, "Compliant Cave at BUID=0.\n");
- break;
- } else if (Temp == CurrentBUID) {
- // and then, there are the other kind of devices ....
- // Restore the writable BUID field (which contains the value we just wrote) to zero.
- Temp = 0;
- LibAmdPciWriteBits (CurrentPtr, 20, 16, &Temp, State->ConfigHandle);
- Depth++;
- // Success!
- IDS_HDT_CONSOLE (HT_TRACE, "Cave left at BUID=0.\n");
- break;
- }
- }
- // An error handler for this critical error
- State->Status = AGESA_ERROR;
- ASSERT (FALSE);
- return;
- }
-
- IDS_HDT_CONSOLE (HT_TRACE, "Compliant Device assigned at BUID=%d.\n", CurrentBUID);
- Depth++;
- CurrentBUID += UnitIDcnt;
- }
- // Provide information on automatic device results
- State->HtBlock->Depth = Depth;
- }
-}
-
-/***************************************************************************
- *** HT Reset Initialize ***
- ***************************************************************************/
-
-/**
- * A constructor for the HyperTransport input structure.
- *
- * Sets inputs to valid, basic level, defaults.
- *
- * @param[in] StdHeader Config handle
- * @param[in,out] AmdHtResetInterface HT Interface structure to initialize.
- *
- * @retval AGESA_SUCCESS Constructors are not allowed to fail
-*/
-AGESA_STATUS
-AmdHtResetConstructor (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface
- )
-{
- AmdHtResetInterface->ManualBuidSwapList = HtOptionResetDefaults.ManualBuidSwapList;
- return AGESA_SUCCESS;
-}
-
-
-/*----------------------------------------------------------------------------------------*/
-/**
- * Initialize HT for Reset, Boot Blocks.
- *
- * This is the top level external interface for Hypertransport Reset Initialization.
- * Create our initial internal state and initialize the non-coherent chain to the
- * southbridge. This interface must be executed by both normal and recovery boot paths.
- *
- * @param[in] StdHeader Interface structure
- * @param[in] AmdHtResetInterface our interface and inputs
- *
- * @retval AGESA_SUCCESS Successful init
- * @retval AGESA_ERROR Device Error, BUID max exceed error.
- *
- */
-AGESA_STATUS
-AmdHtInitReset (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface
- )
-{
- HTR_STATE_DATA State;
- AGESA_STATUS IgnoredStatus;
-
- State.Status = AGESA_SUCCESS;
- if (IsBsp (StdHeader, &IgnoredStatus)) {
- State.ConfigHandle = (AMD_CONFIG_PARAMS *)StdHeader;
- State.HtBlock = AmdHtResetInterface;
- HtrEnableRoutingTables (&State);
-
- HtrProcessLink (&State);
- }
- return State.Status;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/C32/mrnc32.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/C32/mrnc32.c
deleted file mode 100644
index 7176417..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/C32/mrnc32.c
+++ /dev/null
@@ -1,711 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrnc32.c
- *
- * Common Northbridge functions for C32 Recovery
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mrport.h"
-#include "cpuFamRegisters.h"
-#include "cpuRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "mm.h"
-#include "mn.h"
-#include "mrnc32.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_RECOVERY_MEM_NB_C32_MRNC32_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define MAX_DIES_PER_SOCKET 2
-#define MAX_DCTS_PER_DIE 2
-#define SPLIT_CHANNEL 0x20000000
-#define CHANNEL_SELECT 0x10000000
-#define MAX_DELAYS 9 /* 8 data bytes + 1 ECC byte */
-#define MAX_DIMMS 4 /* 4 DIMMs per channel */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-VOID
-STATIC
-MemRecNInitNBRegTableC32 (
- IN OUT TSEFO *NBRegTable
- );
-
-UINT32
-STATIC
-MemRecNCmnGetSetFieldC32 (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN BIT_FIELD_NAME FieldName,
- IN UINT32 Field
- );
-
-UINT32
-STATIC
-MemRecNcmnGetSetTrainDlyC32 (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN TRN_DLY_TYPE TrnDly,
- IN DRBN DrbnVar,
- IN UINT16 Field
- );
-
-BOOLEAN
-STATIC
-MemRecNIsIdSupportedC32 (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN CPU_LOGICAL_ID *LogicalIdPtr
- );
-
-VOID
-STATIC
-MemRecNSwitchNodeC32 (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 NodeID
- );
-
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initializes the northbridge block
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
- * @param[in] NodeID - Node ID for this NB block
- *
- * @return TRUE - This node is a C32 and this NB block has been initialized
- * @return FALSE - This node is not a C32
- */
-
-BOOLEAN
-MemRecConstructNBBlockC32 (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- )
-{
- UINT8 i;
- UINT8 Dct;
- UINT8 Channel;
- DIE_STRUCT *MCTPtr;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
- //
- // Determine if this is the expected NB Type
- //
- GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
- if (!MemRecNIsIdSupportedC32 (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
- return FALSE;
- }
-
- //
- // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
- //
- MCTPtr = &MemPtr->DiesPerSystem[NodeID];
- AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_C32 * (
- sizeof (DCT_STRUCT) + (
- MAX_CHANNELS_PER_DCT_C32 * (
- sizeof (CH_DEF_STRUCT) + (
- MAX_DIMMS * MAX_DELAYS * NUMBER_OF_DELAY_TABLES
- )
- )
- )
- );
- AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0);
- AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
- if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) {
- return FALSE;
- }
-
- MemPtr->DieCount = MAX_DIES_PER_SOCKET;
- MCTPtr->DctCount = MAX_DCTS_PER_NODE_C32;
- MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr;
- MemPtr->DiesPerSystem[NodeID + 1].DctCount = MAX_DCTS_PER_NODE_C32;
- MemPtr->DiesPerSystem[NodeID + 1].DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_C32 * sizeof (DCT_STRUCT);
- for (Dct = 0; Dct < MAX_DCTS_PER_NODE_C32; Dct++) {
- MCTPtr->DctData[Dct].Dct = Dct;
- MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_C32;
- MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr;
- MCTPtr->DctData[Dct].ChData[0].ChannelID = (MCTPtr->DieId * 2) + Dct;
- AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_C32 * sizeof (CH_DEF_STRUCT);
- for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_C32; Channel++) {
- MCTPtr->DctData[Dct].ChData[Channel].RcvEnDlys = (UINT16 *) AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS) * 2;
- MCTPtr->DctData[Dct].ChData[Channel].WrDqsDlys = AllocHeapParams.BufferPtr;
- MCTPtr->DctData[Dct].ChData[Channel].Dct = Dct;
- AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS);
- }
- }
-
- //
- // Initialize NB block's variables
- //
- NBPtr->MemPtr = MemPtr;
- NBPtr->RefPtr = MemPtr->ParameterListPtr;
- NBPtr->MCTPtr = MCTPtr;
- NBPtr->AllNodeMCTPtr = &MemPtr->DiesPerSystem[NodeID];
- NBPtr->SPDPtr = &MemPtr->SpdDataStructure[MemPtr->DiesPerSystem[NodeID].SocketId * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL];
- NBPtr->AllNodeSPDPtr = &MemPtr->SpdDataStructure[MemPtr->DiesPerSystem[NodeID].SocketId * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL];
-
- NBPtr->DctCachePtr = NBPtr->DctCache;
-
- MemRecNInitNBRegTableC32 (NBPtr->NBRegTable);
- NBPtr->Dct = 0;
- NBPtr->Channel = 0;
- NBPtr->VarMtrrHiMsk = MemRecGetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
-
- LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader);
- LibAmdMemFill (NBPtr->IsSupported, FALSE, sizeof (NBPtr->IsSupported), &NBPtr->MemPtr->StdHeader);
- for (i = 0; i < NumberOfHooks; i++) {
- NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) MemRecDefTrue;
- }
-
- NBPtr->InitRecovery = MemRecNMemInitNb;
-
- NBPtr->SwitchNodeRec = MemRecNSwitchNodeC32;
- NBPtr->SwitchDCT = MemRecNSwitchDctC32;
- NBPtr->SwitchChannel = MemRecNSwitchChannelC32;
- NBPtr->SetMaxLatency = MemRecNSetMaxLatencyNb;
- NBPtr->GetSysAddrRec = MemRecNGetMCTSysAddrNb;
- NBPtr->SendMrsCmd = MemRecNSendMrsCmdNb;
- NBPtr->sendZQCmd = MemRecNSendZQCmdNb;
- NBPtr->SetDramOdtRec = MemRecNSetDramOdtNb;
-
- NBPtr->GetBitField = MemRecNGetBitFieldNb;
- NBPtr->SetBitField = MemRecNSetBitFieldNb;
- NBPtr->GetTrainDly = MemRecNGetTrainDlyNb;
- NBPtr->SetTrainDly = MemRecNSetTrainDlyNb;
-
- NBPtr->MemRecNCmnGetSetFieldNb = MemRecNCmnGetSetFieldC32;
- NBPtr->MemRecNcmnGetSetTrainDlyNb = MemRecNcmnGetSetTrainDlyC32;
- NBPtr->MemRecNSwitchDctNb = MemRecNSwitchDctC32;
- NBPtr->TrainingFlow = MemNRecTrainingFlowNb;
- NBPtr->MemRecNInitializeMctNb = MemRecNInitializeMctC32;
- NBPtr->MemRecNFinalizeMctNb = MemRecNFinalizeMctC32;
- NBPtr->IsSupported[DramModeAfterDimmPres] = TRUE;
- MemRecNSwitchDctC32 (NBPtr, 0);
-
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function sets the current die to work on.
- * Should be called before accessing a certain die
- * All data structures will be updated to point to the current node
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] NodeID - ID of the target die
- *
- */
-
-VOID
-STATIC
-MemRecNSwitchNodeC32 (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 NodeID
- )
-{
- NBPtr->MCTPtr = &(NBPtr->AllNodeMCTPtr[NodeID]);
- NBPtr->Node = NodeID;
- NBPtr->MCTPtr->NodeId = NodeID;
- MemRecNSwitchDctC32 (NBPtr, NBPtr->Dct);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the current DCT to work on.
- * Should be called before accessing a certain DCT
- * All data structures will be updated to point to the current DCT
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Dct - ID of the target DCT
- *
- */
-
-VOID
-MemRecNSwitchDctC32 (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Dct
- )
-{
- NBPtr->Dct = Dct & 1;
- NBPtr->SPDPtr = &(NBPtr->AllNodeSPDPtr[(NBPtr->MCTPtr->NodeId * MAX_DCTS_PER_DIE + Dct) * MAX_DIMMS_PER_CHANNEL]);
- NBPtr->DCTPtr = &(NBPtr->MCTPtr->DctData[NBPtr->Dct]);
-
- MemRecNSwitchChannelC32 (NBPtr, 0);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the current channel to work on.
- * Should be called before accessing a certain channel
- * All data structures will be updated to point to the current channel
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Channel - ID of the target channel
- *
- */
-
-VOID
-MemRecNSwitchChannelC32 (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Channel
- )
-{
- NBPtr->Channel = 0;
- NBPtr->ChannelPtr = &(NBPtr->DCTPtr->ChData[0]);
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function gets or set DQS timing during training.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] TrnDly - type of delay to be set
- * @param[in] DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed
- * (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding
- * @param[in] Field - Value to be programmed
- * @param[in] IsSet - Indicates if the function will set or get
- *
- * @return value read, if the function is used as a "get"
- */
-
-UINT32
-STATIC
-MemRecNcmnGetSetTrainDlyC32 (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN TRN_DLY_TYPE TrnDly,
- IN DRBN DrbnVar,
- IN UINT16 Field
- )
-{
- UINT16 index;
- UINT16 offset;
- UINT32 value;
- UINT32 address;
- UINT8 DIMM;
- UINT8 Rank;
- UINT8 Byte;
- UINT8 Nibble;
-
- DIMM = DRBN_DIMM (DrbnVar);
- Rank = DRBN_RANK (DrbnVar);
- Byte = DRBN_BYTE (DrbnVar);
- Nibble = DRBN_NBBL (DrbnVar);
-
- switch (TrnDly) {
- case AccessRcvEnDly:
- index = 0x10;
- break;
- case AccessWrDqsDly:
- index = 0x30;
- break;
- case AccessWrDatDly:
- index = 0x01;
- break;
- case AccessRdDqsDly:
- index = 0x05;
- break;
- case AccessPhRecDly:
- index = 0x50;
- break;
- default:
- index = 0;
- IDS_ERROR_TRAP;
- }
-
- switch (TrnDly) {
- case AccessRcvEnDly:
- case AccessWrDqsDly:
- index += (DIMM * 3);
- if ((Byte & 0x04) != 0) {
- // if byte 4,5,6,7
- index += 0x10;
- }
- if ((Byte & 0x02) != 0) {
- // if byte 2,3,6,7
- index++;
- }
- if (Byte > 7) {
- index += 2;
- }
- offset = 16 * (Byte % 2);
- index |= (Rank << 8);
- index |= (Nibble << 9);
- break;
-
- case AccessRdDqsDly:
- Field &= ~ 0x0001;
- case AccessWrDatDly:
- index += (DIMM * 0x100);
- if (Nibble != 0) {
- if (Rank != 0) {
- index += 0xA0;
- } else {
- index += 0x70;
- }
- } else if (Rank != 0) {
- index += 0x60;
- }
- // break is not being used here because AccessRdDqsDly and AccessWrDatDly also need
- // to run AccessPhRecDly sequence.
- case AccessPhRecDly:
- index += (Byte / 4);
- offset = 8 * (Byte % 4);
- break;
- default:
- offset = 0;
- IDS_ERROR_TRAP;
- }
-
- address = index;
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, address);
- while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
- value = MemRecNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
-
- if (IsSet != 0) {
- if (TrnDly == AccessPhRecDly) {
- value = NBPtr->DctCachePtr->PhRecReg[index & 0x03];
- }
-
- value = ((UINT32)Field << offset) | (value & (~((UINT32)0xFF << offset)));
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlDataReg, value);
- address |= DCT_ACCESS_WRITE;
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, address);
- while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
-
- if (TrnDly == AccessPhRecDly) {
- NBPtr->DctCachePtr->PhRecReg[index & 0x03] = value;
- }
- } else {
- value = (value >> offset) & 0xFF;
- }
-
- return value;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function gets or sets a value to a bit field in a PCI register.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] FieldName - Name of Field to be set
- * @param[in] Field - Value to be programmed
- * @param[in] IsSet - Indicates if the function will set or get
- *
- * @return value read, if the function is used as a "get"
- */
-
-UINT32
-STATIC
-MemRecNCmnGetSetFieldC32 (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN BIT_FIELD_NAME FieldName,
- IN UINT32 Field
- )
-{
- SBDFO Address;
- PCI_ADDR PciAddr;
- UINT8 Type;
- UINT32 Value;
- UINT32 Highbit;
- UINT32 Lowbit;
- UINT32 Mask;
-
- Value = 0;
- if (FieldName < BFEndOfList) {
- Address = NBPtr->NBRegTable[FieldName];
- if (Address != 0) {
- Lowbit = TSEFO_END (Address);
- Highbit = TSEFO_START (Address);
- Type = TSEFO_TYPE (Address);
-
- // If Fn2 and DCT1 selected, set Address to be 1xx
- if (((Address & 0xF000) == 0x2000) && (NBPtr->Dct != 0)) {
- Address |= 0x0100;
- }
- if ((Address >> 29) == ((DCT_PHY_ACCESS << 1) | 1)) {
- // Special DCT Phy access
- Address &= 0x0FFFFFFF;
- Lowbit = 0;
- Highbit = 16;
- } else {
- // Normal DCT Phy access
- Address = TSEFO_OFFSET (Address);
- }
-
-
- if (Type == NB_ACCESS) {
- // Address |= (((UINT32) (24 + 0)) << 15);
- PciAddr.AddressValue = Address;
- // Fix for MCM
- PciAddr.Address.Device = NBPtr->MemPtr->DiesPerSystem[NBPtr->Node].PciAddr.Address.Device;
- PciAddr.Address.Bus = NBPtr->MemPtr->DiesPerSystem[NBPtr->Node].PciAddr.Address.Bus;
- PciAddr.Address.Segment = NBPtr->MemPtr->DiesPerSystem[NBPtr->Node].PciAddr.Address.Segment;
- Address = PciAddr.AddressValue;
- LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
- } else if (Type == DCT_PHY_ACCESS) {
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
- while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
-
- Value = MemRecNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
- } else {
- IDS_ERROR_TRAP;
- }
-
- if (IsSet != 0) {
- // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
- if ((Highbit - Lowbit) != 31) {
- Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
- } else {
- Mask = (UINT32)0xFFFFFFFF;
- }
- Value &= ~(Mask << Lowbit);
- Value |= (Field & Mask) << Lowbit;
-
- if (Type == NB_ACCESS) {
- PciAddr.AddressValue = Address;
- LibAmdPciWrite (AccessWidth32, PciAddr , &Value, &NBPtr->MemPtr->StdHeader);
- } else if (Type == DCT_PHY_ACCESS) {
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
- Address |= DCT_ACCESS_WRITE;
-
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
- while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
- } else {
- IDS_ERROR_TRAP;
- }
- } else {
- Value = Value >> Lowbit; // Shift
- // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
- if ((Highbit - Lowbit) != 31) {
- Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
- }
- }
- }
- } else {
- IDS_ERROR_TRAP; // Invalid bit field index
- }
- return Value;
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initializes bit field translation table
- *
-* @param[in,out] *NBRegTable - Pointer to the NB Table *
- */
-
-VOID
-STATIC
-MemRecNInitNBRegTableC32 (
- IN OUT TSEFO *NBRegTable
- )
-{
- UINT16 i;
- for (i = 0; i <= BFEndOfList; i++) {
- NBRegTable[i] = 0;
- }
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31, 0, BFDevVendorIDReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60), 2, 0, BFNodeID);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31, 0, BFCSBaseAddr0Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31, 0, BFCSBaseAddr1Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31, 0, BFCSBaseAddr2Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31, 0, BFCSBaseAddr3Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x50), 31, 0, BFCSBaseAddr4Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x54), 31, 0, BFCSBaseAddr5Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x58), 31, 0, BFCSBaseAddr6Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x5C), 31, 0, BFCSBaseAddr7Reg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31, 0, BFCSMask0Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31, 0, BFCSMask1Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x68), 31, 0, BFCSMask2Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x6C), 31, 0, BFCSMask3Reg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 0, BFDramControlReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 0, BFDramInitRegReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31, 0, BFDramBankAddrReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31, 0, BFDramMRSReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 9, 7, BFDramTerm);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 11, 10, BFDramTermDyn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 0, BFDramTimingLoReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 0, BFDramTimingHiReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31, 0, BFDramConfigLoReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 0, BFDramConfigHiReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 0, BFDctAddlOffsetReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31, 0, BFDctAddlDataReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 31, BFDctAccessDone);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4), 4, 0, BFNbFid);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 18, 18, BFDqsRcvEnTrain);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15, 0, BFMrsAddress);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 18, 16, BFMrsBank);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 22, 20, BFMrsChipSel);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 30, 30, BFSendCtrlWord);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 7, 7, BFLevel);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 12, 12, BFMrsQoff);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 0, 0, BFInitDram);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 16, 16, BFUnBuffDimm);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 8, 8, BFDdr3Mode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 9, 9, BFLegacyBiosMode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 5, 5, BFSubMemclkRegDly);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 6, 6, BFOdtSwizzle);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 15, 8, BFCtrlWordCS);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 8, 8, BFDramEnabled);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 31, 0, BFDctSelBaseAddrReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 31, 0, BFDctSelBaseOffsetReg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 31, 0, BFMctCfgHiReg);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31, 0, BFODCControl);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31, 0, BFAddrTmgControl);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 0, 0, BFWrtLvTrEn);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 1, 1, BFWrtLvTrMode);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 5, 4, BFTrDimmSel);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11, 8, BFWrLvOdt);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 30, 30, BFDisAutoComp);
-
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- * MemRecNIsIdSupportedC32
- * This function matches the CPU_LOGICAL_ID with certain criteria to
- * determine if it is supported by this NBBlock.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID
- *
- * @return TRUE - This node is a C32.
- * @return FALSE - This node is not a C32.
- *
- */
-BOOLEAN
-STATIC
-MemRecNIsIdSupportedC32 (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN CPU_LOGICAL_ID *LogicalIdPtr
- )
-{
- if ((LogicalIdPtr->Revision & AMD_F10_C32_ALL) != 0) {
- return TRUE;
- } else {
- return FALSE;
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/C32/mrnc32.h b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/C32/mrnc32.h
deleted file mode 100644
index 2d851ce..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/C32/mrnc32.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnc32.h
- *
- * Northbridge C32 Recovery
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MRNC32_H_
-#define _MRNC32_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-#define MAX_DCTS_PER_NODE_C32 2
-#define MAX_CHANNELS_PER_DCT_C32 1
-
-#define _4GB_RJ8 ((UINT32)4 << (30 - 8))
-#define MTRR_VALID 11
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-MemRecConstructNBBlockC32 (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- );
-
-VOID
-MemRecNSwitchDctC32 (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Dct
- );
-
-VOID
-MemRecNSwitchChannelC32 (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Channel
- );
-
-VOID
-MemRecNFinalizeMctC32 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemRecNInitializeMctC32 (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-#endif /* _MRNC32_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/C32/mrnmctc32.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/C32/mrnmctc32.c
deleted file mode 100644
index bc22a8c..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/C32/mrnmctc32.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrnmctc32.c
- *
- * Northbridge C32 MCT supporting functions Recovery
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mrport.h"
-#include "mm.h"
-#include "mn.h"
-#include "mrnc32.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_RECOVERY_MEM_NB_C32_MRNMCTC32_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets final values in BUCFG and BUCFG2
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemRecNFinalizeMctC32 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MEM_DATA_STRUCT *MemPtr;
- S_UINT64 SMsr;
-
- MemPtr = NBPtr->MemPtr;
-
- // Recommended settings for F2x11C
- MemRecNSetBitFieldNb (NBPtr, BFMctCfgHiReg, 0x2CE00F60);
-
- LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- if (!NBPtr->ClToNbFlag) {
- SMsr.lo &= ~((UINT32) 1 << 15); // ClLinesToNbDis
- }
- LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-
- LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- SMsr.hi &= ~((UINT32) 1 << (48 - 32)); // WbEnhWsbDis
- LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets initial values in BUCFG and BUCFG2
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemRecNInitializeMctC32 (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MEM_DATA_STRUCT *MemPtr;
- S_UINT64 SMsr;
-
- MemPtr = NBPtr->MemPtr;
-
- LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- if (SMsr.lo & ((UINT32) 1 << 15)) {
- NBPtr->ClToNbFlag = TRUE;
- }
- SMsr.lo |= (UINT32) 1 << 15; // ClLinesToNbDis
- LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-
- LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- SMsr.hi |= (UINT32) 1 << (48 - 32); // WbEnhWsbDis
- LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/C32/mrnprotoc32.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/C32/mrnprotoc32.c
deleted file mode 100644
index 8259742..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/C32/mrnprotoc32.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrnprotoc32.c
- *
- * Northbridge support functions for Errata and early samples Recovery
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-
-#include "AGESA.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_RECOVERY_MEM_NB_C32_MRNPROTOC32_FILECODE
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/DA/mrnda.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/DA/mrnda.c
deleted file mode 100644
index 8281f61..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/DA/mrnda.c
+++ /dev/null
@@ -1,651 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrnda.c
- *
- * Common Northbridge functions for Ridgeback Recovery
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "cpuRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "mrport.h"
-#include "mm.h"
-#include "mn.h"
-#include "mrnda.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_RECOVERY_MEM_NB_DA_MRNDA_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-#define SPLIT_CHANNEL 0x20000000
-#define CHANNEL_SELECT 0x10000000
-#define MAX_DELAYS 9 /* 8 data bytes + 1 ECC byte */
-#define MAX_DIMMS 4 /* 4 DIMMs per channel */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-VOID
-STATIC
-MemRecNInitNBRegTableDA (
- IN OUT TSEFO *NBRegTable
- );
-
-UINT32
-STATIC
-MemRecNCmnGetSetFieldDA (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN BIT_FIELD_NAME FieldName,
- IN UINT32 Field
- );
-
-UINT32
-STATIC
-MemRecNcmnGetSetTrainDlyDA (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN TRN_DLY_TYPE TrnDly,
- IN DRBN DrbnVar,
- IN UINT16 Field
- );
-
-BOOLEAN
-STATIC
-MemRecNIsIdSupportedDA (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN CPU_LOGICAL_ID *LogicalIdPtr
- );
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initializes the northbridge block
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
- * @param[in] NodeID - Node ID for this NB block
- *
- * @return TRUE - This node is a RB and this NB block has been initialized
- * @return FALSE - This node is not a RB
- */
-
-BOOLEAN
-MemRecConstructNBBlockDA (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- )
-{
- UINT8 i;
- UINT8 Dct;
- UINT8 Channel;
- DIE_STRUCT *MCTPtr;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
- //
- // Determine if this is the expected NB Type
- //
- GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
- if (!MemRecNIsIdSupportedDA (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
- return FALSE;
- }
-
- //
- // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
- //
- MCTPtr = &MemPtr->DiesPerSystem[NodeID];
- AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_DA * (
- sizeof (DCT_STRUCT) + (
- MAX_CHANNELS_PER_DCT_DA * (
- sizeof (CH_DEF_STRUCT) + (
- MAX_DIMMS * MAX_DELAYS * NUMBER_OF_DELAY_TABLES
- )
- )
- )
- );
- AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0);
- AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
- if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) {
- return FALSE;
- }
-
- MemPtr->DieCount = 1;
- MCTPtr->DctCount = MAX_DCTS_PER_NODE_DA;
- MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_DA * sizeof (DCT_STRUCT);
- for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
- MCTPtr->DctData[Dct].Dct = Dct;
- MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_DA;
- MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr;
- MCTPtr->DctData[Dct].ChData[0].ChannelID = Dct;
- AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_DA * sizeof (CH_DEF_STRUCT);
- for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_DA; Channel++) {
- MCTPtr->DctData[Dct].ChData[Channel].RcvEnDlys = (UINT16 *) AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS) * 2;
- MCTPtr->DctData[Dct].ChData[Channel].WrDqsDlys = AllocHeapParams.BufferPtr;
- MCTPtr->DctData[Dct].ChData[Channel].Dct = Dct;
- AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS);
- }
- }
-
- //
- // Initialize NB block's variables
- //
- NBPtr->MemPtr = MemPtr;
- NBPtr->RefPtr = MemPtr->ParameterListPtr;
- NBPtr->MCTPtr = MCTPtr;
- NBPtr->SPDPtr = &MemPtr->SpdDataStructure[MemPtr->DiesPerSystem[NodeID].SocketId * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL];
- NBPtr->AllNodeSPDPtr = &MemPtr->SpdDataStructure[MemPtr->DiesPerSystem[NodeID].SocketId * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL];
-
- NBPtr->DctCachePtr = NBPtr->DctCache;
-
- MemRecNInitNBRegTableDA (NBPtr->NBRegTable);
- NBPtr->Dct = 0;
- NBPtr->Channel = 0;
- NBPtr->VarMtrrHiMsk = MemRecGetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
-
- LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader);
- LibAmdMemFill (NBPtr->IsSupported, FALSE, sizeof (NBPtr->IsSupported), &NBPtr->MemPtr->StdHeader);
- for (i = 0; i < NumberOfHooks; i++) {
- NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) MemRecDefTrue;
- }
-
- NBPtr->InitRecovery = MemRecNMemInitNb;
-
- NBPtr->SwitchNodeRec = (VOID (*) (MEM_NB_BLOCK *, UINT8)) MemRecDefRet;
- NBPtr->SwitchDCT = MemRecNSwitchDctDA;
- NBPtr->SwitchChannel = MemRecNSwitchChannelDA;
- NBPtr->SetMaxLatency = MemRecNSetMaxLatencyNb;
- NBPtr->GetSysAddrRec = MemRecNGetMCTSysAddrNb;
- NBPtr->SendMrsCmd = MemRecNSendMrsCmdNb;
- NBPtr->sendZQCmd = MemRecNSendZQCmdNb;
- NBPtr->SetDramOdtRec = MemRecNSetDramOdtNb;
-
- NBPtr->GetBitField = MemRecNGetBitFieldNb;
- NBPtr->SetBitField = MemRecNSetBitFieldNb;
- NBPtr->GetTrainDly = MemRecNGetTrainDlyNb;
- NBPtr->SetTrainDly = MemRecNSetTrainDlyNb;
- NBPtr->MemRecNCmnGetSetFieldNb = MemRecNCmnGetSetFieldDA;
- NBPtr->MemRecNcmnGetSetTrainDlyNb = MemRecNcmnGetSetTrainDlyDA;
- NBPtr->MemRecNSwitchDctNb = MemRecNSwitchDctDA;
- NBPtr->TrainingFlow = MemNRecTrainingFlowNb;
- NBPtr->MemRecNInitializeMctNb = MemRecNInitializeMctDA;
- NBPtr->MemRecNFinalizeMctNb = MemRecNFinalizeMctDA;
- NBPtr->IsSupported[DramModeBeforeDimmPres] = TRUE;
- NBPtr->IsSupported[CheckClearOnDimmMirror] = TRUE;
- MemRecNSwitchDctDA (NBPtr, 0);
-
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the current DCT to work on.
- * Should be called before accessing a certain DCT
- * All data structures will be updated to point to the current DCT
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Dct - ID of the target DCT
- *
- */
-
-VOID
-MemRecNSwitchDctDA (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Dct
- )
-{
- NBPtr->Dct = Dct & 1;
- NBPtr->SPDPtr = &(NBPtr->AllNodeSPDPtr[Dct * MAX_DIMMS_PER_CHANNEL]);
- NBPtr->DCTPtr = &(NBPtr->MCTPtr->DctData[NBPtr->Dct]);
-
- MemRecNSwitchChannelDA (NBPtr, NBPtr->Channel);
-}
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the current channel to work on.
- * Should be called before accessing a certain channel
- * All data structures will be updated to point to the current channel
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Channel - ID of the target channel
- *
- */
-
-VOID
-MemRecNSwitchChannelDA (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Channel
- )
-{
- NBPtr->Channel = Channel & 1;
- NBPtr->ChannelPtr = &(NBPtr->DCTPtr->ChData[NBPtr->Channel]);
-}
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function gets or set DQS timing during training.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] TrnDly - type of delay to be set
- * @param[in] DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed
- * (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding
- * @param[in] Field - Value to be programmed
- * @param[in] IsSet - Indicates if the function will set or get
- *
- * @return value read, if the function is used as a "get"
- */
-
-UINT32
-STATIC
-MemRecNcmnGetSetTrainDlyDA (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN TRN_DLY_TYPE TrnDly,
- IN DRBN DrbnVar,
- IN UINT16 Field
- )
-{
- UINT16 Index;
- UINT16 Offset;
- UINT32 Value;
- UINT32 Address;
- UINT8 Dimm;
- UINT8 Byte;
-
- Dimm = DRBN_DIMM (DrbnVar);
- Byte = DRBN_BYTE (DrbnVar);
-
- ASSERT (Dimm < 4);
- ASSERT (Byte <= 8);
-
- switch (TrnDly) {
- case AccessRcvEnDly:
- Index = 0x10;
- break;
- case AccessWrDqsDly:
- Index = 0x30;
- break;
- case AccessWrDatDly:
- Index = 0x01;
- break;
- case AccessRdDqsDly:
- Index = 0x05;
- break;
- case AccessPhRecDly:
- Index = 0x50;
- break;
- default:
- Index = 0;
- IDS_ERROR_TRAP;
- }
-
- switch (TrnDly) {
- case AccessRcvEnDly:
- case AccessWrDqsDly:
- Index += (Dimm * 3);
- if (Byte & 0x04) {
- // if byte 4,5,6,7
- Index += 0x10;
- }
- if (Byte & 0x02) {
- // if byte 2,3,6,7
- Index++;
- }
- Offset = 16 * (Byte % 2);
- break;
-
- case AccessRdDqsDly:
- Field &= ~ 0x0001;
- case AccessWrDatDly:
- Index += (Dimm * 0x100);
- // break is not being used here because AccessRdDqsDly and AccessWrDatDly also need
- // to run AccessPhRecDly sequence.
- case AccessPhRecDly:
- Index += (Byte / 4);
- Offset = 8 * (Byte % 4);
- break;
- default:
- Offset = 0;
- IDS_ERROR_TRAP;
- }
-
- Address = Index;
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
- while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
- Value = MemRecNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
-
- if (IsSet) {
- if (TrnDly == AccessPhRecDly) {
- Value = NBPtr->DctCachePtr->PhRecReg[Index & 0x03];
- }
-
- Value = ((UINT32)Field << Offset) | (Value & (~((UINT32)0xFF << Offset)));
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
- Address |= DCT_ACCESS_WRITE;
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
- while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
-
- if (TrnDly == AccessPhRecDly) {
- NBPtr->DctCachePtr->PhRecReg[Index & 0x03] = Value;
- }
- } else {
- Value = (Value >> Offset) & 0xFF;
- }
-
- return Value;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function gets or sets a value to a bit field in a PCI register.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] IsSet - Indicates if the function will set or get
- * @param[in] FieldName - Name of field to be set
- * @param[in] Field - Value to be programmed
- *
- * @return value read, if the function is used as a "get"
- */
-
-UINT32
-STATIC
-MemRecNCmnGetSetFieldDA (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN BIT_FIELD_NAME FieldName,
- IN UINT32 Field
- )
-{
- SBDFO Address;
- PCI_ADDR PciAddr;
- UINT8 Type;
- UINT32 Value;
- UINT32 Highbit;
- UINT32 Lowbit;
- UINT32 Mask;
-
- Value = 0;
- if (FieldName < BFEndOfList) {
- Address = NBPtr->NBRegTable[FieldName];
- if (Address) {
- Lowbit = TSEFO_END (Address);
- Highbit = TSEFO_START (Address);
- Type = TSEFO_TYPE (Address);
-
- // If Fn2 and DCT1 selected, set Address to be 1xx
- if (((Address & 0xF000) == 0x2000) && NBPtr->Dct) {
- Address |= 0x0100;
- }
- if ((Address >> 29) == ((DCT_PHY_ACCESS << 1) | 1)) {
- // Special DCT Phy access
- Address &= 0x0FFFFFFF;
- Lowbit = 0;
- Highbit = 16;
- } else {
- // Normal DCT Phy access
- Address = TSEFO_OFFSET (Address);
- }
-
-
- if (Type == NB_ACCESS) {
- Address |= (((UINT32) (24 + 0)) << 15);
- PciAddr.AddressValue = Address;
- LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
- } else if (Type == DCT_PHY_ACCESS) {
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
- while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
-
- Value = MemRecNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
- } else {
- IDS_ERROR_TRAP;
- }
-
- if (IsSet) {
- // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
- if ((Highbit - Lowbit) != 31) {
- Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
- } else {
- Mask = (UINT32)0xFFFFFFFF;
- }
- Value &= ~(Mask << Lowbit);
- Value |= (Field & Mask) << Lowbit;
-
- if (Type == NB_ACCESS) {
- PciAddr.AddressValue = Address;
- LibAmdPciWrite (AccessWidth32, PciAddr , &Value, &NBPtr->MemPtr->StdHeader);
- } else if (Type == DCT_PHY_ACCESS) {
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
- Address |= DCT_ACCESS_WRITE;
-
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
- while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
- } else {
- IDS_ERROR_TRAP;
- }
- } else {
- Value = Value >> Lowbit; // Shift
- // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
- if ((Highbit - Lowbit) != 31) {
- Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
- }
- }
- }
- } else {
- IDS_ERROR_TRAP; // Invalid bit field index
- }
- return Value;
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initializes bit field translation table
- *
- * @param[in,out] *NBRegTable - Pointer to the NB Table *
- */
-
-VOID
-STATIC
-MemRecNInitNBRegTableDA (
- IN OUT TSEFO *NBRegTable
- )
-{
- UINT16 i;
- for (i = 0; i <= BFEndOfList; i++) {
- NBRegTable[i] = 0;
- }
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31, 0, BFDevVendorIDReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60), 2, 0, BFNodeID);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31, 0, BFCSBaseAddr0Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31, 0, BFCSBaseAddr1Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31, 0, BFCSBaseAddr2Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31, 0, BFCSBaseAddr3Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x50), 31, 0, BFCSBaseAddr4Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x54), 31, 0, BFCSBaseAddr5Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x58), 31, 0, BFCSBaseAddr6Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x5C), 31, 0, BFCSBaseAddr7Reg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31, 0, BFCSMask0Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31, 0, BFCSMask1Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x68), 31, 0, BFCSMask2Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x6C), 31, 0, BFCSMask3Reg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 0, BFDramControlReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 0, BFDramInitRegReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31, 0, BFDramBankAddrReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31, 0, BFDramMRSReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 9, 7, BFDramTerm);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 11, 10, BFDramTermDyn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 0, BFDramTimingLoReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 0, BFDramTimingHiReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31, 0, BFDramConfigLoReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 0, BFDramConfigHiReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 0, BFDctAddlOffsetReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31, 0, BFDctAddlDataReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 31, BFDctAccessDone);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4), 4, 0, BFNbFid);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 18, 18, BFDqsRcvEnTrain);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15, 0, BFMrsAddress);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 18, 16, BFMrsBank);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 22, 20, BFMrsChipSel);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 30, 30, BFSendCtrlWord);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 7, 7, BFLevel);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 12, 12, BFMrsQoff);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 0, 0, BFInitDram);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 16, 16, BFUnBuffDimm);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 8, 8, BFDdr3Mode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 9, 9, BFLegacyBiosMode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 6, 6, BFOdtSwizzle);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 15, 8, BFCtrlWordCS);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 8, 8, BFDramEnabled);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 31, 0, BFDctSelBaseAddrReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 31, 0, BFDctSelBaseOffsetReg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 6, 2, BFMctWrLimit);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 12, 12, BFPrefCpuDis);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 13, 13, BFPrefIoDis);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 29, 29, BFFlushWrOnStpGnt);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31, 0, BFODCControl);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31, 0, BFAddrTmgControl);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 0, 0, BFWrtLvTrEn);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 1, 1, BFWrtLvTrMode);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 5, 4, BFTrDimmSel);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11, 8, BFWrLvOdt);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 30, 30, BFDisAutoComp);
-
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- * MemRecNIsIdSupportedDA
- * This function matches the CPU_LOGICAL_ID with certain criteria to
- * determine if it is supported by this NBBlock.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID
- *
- */
-BOOLEAN
-STATIC
-MemRecNIsIdSupportedDA (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN CPU_LOGICAL_ID *LogicalIdPtr
- )
-{
-
- if ((LogicalIdPtr->Revision & (AMD_F10_BL_ALL | AMD_F10_DA_ALL)) != 0) {
- return TRUE;
- } else {
- return FALSE;
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/DA/mrnda.h b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/DA/mrnda.h
deleted file mode 100644
index 5652cec..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/DA/mrnda.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnda.h
- *
- * Northbridge Ridgeback Recovery
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MRNDA_H_
-#define _MRNDA_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-#define MAX_DCTS_PER_NODE_DA 2
-#define MAX_CHANNELS_PER_DCT_DA 1
-
-#define _4GB_RJ8 ((UINT32)4 << (30 - 8))
-#define MTRR_VALID 11
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-MemRecConstructNBBlockDA (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- );
-
-VOID
-MemRecNSwitchDctDA (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Dct
- );
-
-VOID
-MemRecNSwitchChannelDA (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Channel
- );
-
-VOID
-MemRecNFinalizeMctDA (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemRecNInitializeMctDA (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-#endif /* _MRNDA_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/DA/mrnmctda.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/DA/mrnmctda.c
deleted file mode 100644
index 3cb2cfd..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/DA/mrnmctda.c
+++ /dev/null
@@ -1,165 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrnmctda.c
- *
- * Northbridge DA MCT supporting functions Recovery
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mrport.h"
-#include "mm.h"
-#include "mn.h"
-#include "mrnda.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_RECOVERY_MEM_NB_DA_MRNMCTDA_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets final values in BUCFG and BUCFG2
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemRecNFinalizeMctDA (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MEM_DATA_STRUCT *MemPtr;
- S_UINT64 SMsr;
-
- MemPtr = NBPtr->MemPtr;
-
-
- // Recommended settings for F2x11C
- MemRecNSetBitFieldNb (NBPtr, BFMctWrLimit, 16);
- MemRecNSetBitFieldNb (NBPtr, BFPrefCpuDis, 0);
- MemRecNSetBitFieldNb (NBPtr, BFPrefIoDis, 0);
- MemRecNSetBitFieldNb (NBPtr, BFFlushWrOnStpGnt, 1);
-
- LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- if (!NBPtr->ClToNbFlag) {
- SMsr.lo &= ~((UINT32) 1 << 15); // ClLinesToNbDis
- }
- LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-
- LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- SMsr.hi &= ~((UINT32) 1 << (48 - 32)); // WbEnhWsbDis
- LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets initial values in BUCFG and BUCFG2
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemRecNInitializeMctDA (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MEM_DATA_STRUCT *MemPtr;
- S_UINT64 SMsr;
-
- MemPtr = NBPtr->MemPtr;
-
- LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- if (SMsr.lo & ((UINT32) 1 << 15)) {
- NBPtr->ClToNbFlag = TRUE;
- }
- SMsr.lo |= (UINT32) 1 << 15; // ClLinesToNbDis
- LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-
- LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- SMsr.hi |= (UINT32) 1 << (48 - 32); // WbEnhWsbDis
- LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/DR/mrndr.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/DR/mrndr.c
deleted file mode 100644
index e30f2b7..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/DR/mrndr.c
+++ /dev/null
@@ -1,655 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrndr.c
- *
- * Common Northbridge functions for Ridgeback Recovery
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "cpuRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "mrport.h"
-#include "mm.h"
-#include "mn.h"
-#include "mrndr.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_RECOVERY_MEM_NB_DR_MRNDR_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-#define SPLIT_CHANNEL 0x20000000
-#define CHANNEL_SELECT 0x10000000
-#define MAX_DELAYS 9 /* 8 data bytes + 1 ECC byte */
-#define MAX_DIMMS 4 /* 4 DIMMs per channel */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-VOID
-STATIC
-MemRecNInitNBRegTableDR (
- IN OUT TSEFO *NBRegTable
- );
-
-UINT32
-STATIC
-MemRecNCmnGetSetFieldDR (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN BIT_FIELD_NAME FieldName,
- IN UINT32 Field
- );
-
-UINT32
-STATIC
-MemRecNcmnGetSetTrainDlyDR (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN TRN_DLY_TYPE TrnDly,
- IN DRBN DrbnVar,
- IN UINT16 Field
- );
-
-BOOLEAN
-STATIC
-MemRecNIsIdSupportedDr (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN CPU_LOGICAL_ID *LogicalIdPtr
- );
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initializes the northbridge block
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
- * @param[in] NodeID - Node ID for this NB block
- *
- * @return TRUE - This node is a RB and this NB block has been initialized
- * @return FALSE - This node is not a RB
- */
-
-BOOLEAN
-MemRecConstructNBBlockDR (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- )
-{
- UINT8 i;
- UINT8 Dct;
- UINT8 Channel;
- DIE_STRUCT *MCTPtr;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
- //
- // Determine if this is the expected NB Type
- //
- GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
- if (!MemRecNIsIdSupportedDr (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
- return FALSE;
- }
-
- //
- // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
- //
- MCTPtr = &MemPtr->DiesPerSystem[NodeID];
- AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_DR * (
- sizeof (DCT_STRUCT) + (
- MAX_CHANNELS_PER_DCT_DR * (
- sizeof (CH_DEF_STRUCT) + (
- MAX_DIMMS * MAX_DELAYS * NUMBER_OF_DELAY_TABLES
- )
- )
- )
- );
- AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0);
- AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
- if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) {
- return FALSE;
- }
-
- MemPtr->DieCount = 1;
- MCTPtr->DctCount = MAX_DCTS_PER_NODE_DR;
- MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_DR * sizeof (DCT_STRUCT);
- for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DR; Dct++) {
- MCTPtr->DctData[Dct].Dct = Dct;
- MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_DR;
- MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr;
- MCTPtr->DctData[Dct].ChData[0].ChannelID = Dct;
- AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_DR * sizeof (CH_DEF_STRUCT);
- for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_DR; Channel++) {
- MCTPtr->DctData[Dct].ChData[Channel].RcvEnDlys = (UINT16 *) AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS) * 2;
- MCTPtr->DctData[Dct].ChData[Channel].WrDqsDlys = AllocHeapParams.BufferPtr;
- MCTPtr->DctData[Dct].ChData[Channel].Dct = Dct;
- AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS);
- }
- }
-
- //
- // Initialize NB block's variables
- //
- NBPtr->MemPtr = MemPtr;
- NBPtr->RefPtr = MemPtr->ParameterListPtr;
- NBPtr->MCTPtr = MCTPtr;
- NBPtr->SPDPtr = &MemPtr->SpdDataStructure[MemPtr->DiesPerSystem[NodeID].SocketId * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL];
- NBPtr->AllNodeSPDPtr = &MemPtr->SpdDataStructure[MemPtr->DiesPerSystem[NodeID].SocketId * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL];
-
- NBPtr->DctCachePtr = NBPtr->DctCache;
-
- MemRecNInitNBRegTableDR (NBPtr->NBRegTable);
- NBPtr->Dct = 0;
- NBPtr->Channel = 0;
- NBPtr->VarMtrrHiMsk = MemRecGetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
-
- LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader);
- LibAmdMemFill (NBPtr->IsSupported, FALSE, sizeof (NBPtr->IsSupported), &NBPtr->MemPtr->StdHeader);
- for (i = 0; i < NumberOfHooks; i++) {
- NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) MemRecDefTrue;
- }
-
- NBPtr->InitRecovery = MemRecNMemInitNb;
-
- NBPtr->SwitchNodeRec = (VOID (*) (MEM_NB_BLOCK *, UINT8)) MemRecDefRet;
- NBPtr->SwitchDCT = MemRecNSwitchDctDR;
- NBPtr->SwitchChannel = MemRecNSwitchChannelDR;
- NBPtr->SetMaxLatency = MemRecNSetMaxLatencyNb;
- NBPtr->GetSysAddrRec = MemRecNGetMCTSysAddrNb;
- NBPtr->SendMrsCmd = MemRecNSendMrsCmdNb;
- NBPtr->sendZQCmd = MemRecNSendZQCmdNb;
- NBPtr->SetDramOdtRec = MemRecNSetDramOdtNb;
-
- NBPtr->GetBitField = MemRecNGetBitFieldNb;
- NBPtr->SetBitField = MemRecNSetBitFieldNb;
- NBPtr->GetTrainDly = MemRecNGetTrainDlyNb;
- NBPtr->SetTrainDly = MemRecNSetTrainDlyNb;
- NBPtr->MemRecNCmnGetSetFieldNb = MemRecNCmnGetSetFieldDR;
- NBPtr->MemRecNcmnGetSetTrainDlyNb = MemRecNcmnGetSetTrainDlyDR;
- NBPtr->MemRecNSwitchDctNb = MemRecNSwitchDctDR;
- NBPtr->TrainingFlow = MemNRecTrainingFlowNb;
- NBPtr->MemRecNInitializeMctNb = MemRecNInitializeMctDR;
- NBPtr->MemRecNFinalizeMctNb = MemRecNFinalizeMctDR;
- NBPtr->IsSupported[DramModeBeforeDimmPres] = TRUE;
- NBPtr->IsSupported[CheckClearOnDimmMirror] = TRUE;
- MemRecNSwitchDctDR (NBPtr, 0);
-
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the current DCT to work on.
- * Should be called before accessing a certain DCT
- * All data structures will be updated to point to the current DCT
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Dct - ID of the target DCT
- *
- */
-
-VOID
-MemRecNSwitchDctDR (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Dct
- )
-{
- NBPtr->Dct = Dct & 1;
- NBPtr->SPDPtr = &(NBPtr->AllNodeSPDPtr[Dct * MAX_DIMMS_PER_CHANNEL]);
- NBPtr->DCTPtr = &(NBPtr->MCTPtr->DctData[NBPtr->Dct]);
-
- MemRecNSwitchChannelDR (NBPtr, NBPtr->Channel);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the current channel to work on.
- * Should be called before accessing a certain channel
- * All data structures will be updated to point to the current channel
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Channel - ID of the target channel
- *
- */
-
-VOID
-MemRecNSwitchChannelDR (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Channel
- )
-{
- NBPtr->Channel = Channel & 1;
- NBPtr->ChannelPtr = &(NBPtr->DCTPtr->ChData[NBPtr->Channel]);
-}
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function gets or set DQS timing during training.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] TrnDly - type of delay to be set
- * @param[in] DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed
- * (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding
- * @param[in] Field - Value to be programmed
- * @param[in] IsSet - Indicates if the function will set or get
- *
- * @return value read, if the function is used as a "get"
- */
-
-UINT32
-STATIC
-MemRecNcmnGetSetTrainDlyDR (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN TRN_DLY_TYPE TrnDly,
- IN DRBN DrbnVar,
- IN UINT16 Field
- )
-{
- UINT16 Index;
- UINT16 Offset;
- UINT32 Value;
- UINT32 Address;
- UINT8 Dimm;
- UINT8 Byte;
-
- Dimm = DRBN_DIMM (DrbnVar);
- Byte = DRBN_BYTE (DrbnVar);
-
- ASSERT (Dimm < 4);
- ASSERT (Byte <= 8);
-
- switch (TrnDly) {
- case AccessRcvEnDly:
- Index = 0x10;
- break;
- case AccessWrDqsDly:
- Index = 0x30;
- break;
- case AccessWrDatDly:
- Index = 0x01;
- break;
- case AccessRdDqsDly:
- Index = 0x05;
- break;
- case AccessPhRecDly:
- Index = 0x50;
- break;
- default:
- Index = 0;
- IDS_ERROR_TRAP;
- }
-
- switch (TrnDly) {
- case AccessRcvEnDly:
- case AccessWrDqsDly:
- Index += (Dimm * 3);
- if (Byte & 0x04) {
- // if byte 4,5,6,7
- Index += 0x10;
- }
- if (Byte & 0x02) {
- // if byte 2,3,6,7
- Index++;
- }
- Offset = 16 * (Byte % 2);
- break;
-
- case AccessRdDqsDly:
- Field &= ~ 0x0001;
- case AccessWrDatDly:
- Index += (Dimm * 0x100);
- // break is not being used here because AccessRdDqsDly and AccessWrDatDly also need
- // to run AccessPhRecDly sequence.
- case AccessPhRecDly:
- Index += (Byte / 4);
- Offset = 8 * (Byte % 4);
- break;
- default:
- Offset = 0;
- IDS_ERROR_TRAP;
- }
-
- Address = Index;
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
- while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
- Value = MemRecNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
-
- if (IsSet) {
- if (TrnDly == AccessPhRecDly) {
- Value = NBPtr->DctCachePtr->PhRecReg[Index & 0x03];
- }
-
- Value = ((UINT32)Field << Offset) | (Value & (~((UINT32)0xFF << Offset)));
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
- Address |= DCT_ACCESS_WRITE;
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
- while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
-
- if (TrnDly == AccessPhRecDly) {
- NBPtr->DctCachePtr->PhRecReg[Index & 0x03] = Value;
- }
- } else {
- Value = (Value >> Offset) & 0xFF;
- }
-
- return Value;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function gets or sets a value to a bit field in a PCI register.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] IsSet - Indicates if the function will set or get
- * @param[in] FieldName - Name of field to be set
- * @param[in] Field - Value to be programmed
- *
- * @return value read, if the function is used as a "get"
- */
-
-UINT32
-STATIC
-MemRecNCmnGetSetFieldDR (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN BIT_FIELD_NAME FieldName,
- IN UINT32 Field
- )
-{
- SBDFO Address;
- PCI_ADDR PciAddr;
- UINT8 Type;
- UINT32 Value;
- UINT32 Highbit;
- UINT32 Lowbit;
- UINT32 Mask;
-
- Value = 0;
- if (FieldName < BFEndOfList) {
- Address = NBPtr->NBRegTable[FieldName];
- if (Address) {
- Lowbit = TSEFO_END (Address);
- Highbit = TSEFO_START (Address);
- Type = TSEFO_TYPE (Address);
-
- // If Fn2 and DCT1 selected, set Address to be 1xx
- if (((Address & 0xF000) == 0x2000) && NBPtr->Dct) {
- Address |= 0x0100;
- }
- if ((Address >> 29) == ((DCT_PHY_ACCESS << 1) | 1)) {
- // Special DCT Phy access
- Address &= 0x0FFFFFFF;
- Lowbit = 0;
- Highbit = 16;
- } else {
- // Normal DCT Phy access
- Address = TSEFO_OFFSET (Address);
- }
-
-
- if (Type == NB_ACCESS) {
- Address |= (((UINT32) (24 + 0)) << 15);
- PciAddr.AddressValue = Address;
- LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
- } else if (Type == DCT_PHY_ACCESS) {
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
- while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
-
- Value = MemRecNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
- } else {
- IDS_ERROR_TRAP;
- }
-
- if (IsSet) {
- // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
- if ((Highbit - Lowbit) != 31) {
- Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
- } else {
- Mask = (UINT32)0xFFFFFFFF;
- }
- Value &= ~(Mask << Lowbit);
- Value |= (Field & Mask) << Lowbit;
-
- if (Type == NB_ACCESS) {
- PciAddr.AddressValue = Address;
- LibAmdPciWrite (AccessWidth32, PciAddr , &Value, &NBPtr->MemPtr->StdHeader);
- } else if (Type == DCT_PHY_ACCESS) {
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
- Address |= DCT_ACCESS_WRITE;
-
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
- while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
- } else {
- IDS_ERROR_TRAP;
- }
- } else {
- Value = Value >> Lowbit; // Shift
- // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
- if ((Highbit - Lowbit) != 31) {
- Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
- }
- }
- }
- } else {
- IDS_ERROR_TRAP; // Invalid bit field index
- }
- return Value;
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initializes bit field translation table
- *
- * @param[in,out] *NBRegTable - Pointer to the NB Table *
- */
-
-VOID
-STATIC
-MemRecNInitNBRegTableDR (
- IN OUT TSEFO *NBRegTable
- )
-{
- UINT16 i;
- for (i = 0; i <= BFEndOfList; i++) {
- NBRegTable[i] = 0;
- }
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31, 0, BFDevVendorIDReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60), 2, 0, BFNodeID);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31, 0, BFCSBaseAddr0Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31, 0, BFCSBaseAddr1Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31, 0, BFCSBaseAddr2Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31, 0, BFCSBaseAddr3Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x50), 31, 0, BFCSBaseAddr4Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x54), 31, 0, BFCSBaseAddr5Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x58), 31, 0, BFCSBaseAddr6Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x5C), 31, 0, BFCSBaseAddr7Reg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31, 0, BFCSMask0Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31, 0, BFCSMask1Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x68), 31, 0, BFCSMask2Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x6C), 31, 0, BFCSMask3Reg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 0, BFDramControlReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 0, BFDramInitRegReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31, 0, BFDramBankAddrReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31, 0, BFDramMRSReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 9, 7, BFDramTerm);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 11, 10, BFDramTermDyn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 0, BFDramTimingLoReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 0, BFDramTimingHiReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31, 0, BFDramConfigLoReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 0, BFDramConfigHiReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 0, BFDctAddlOffsetReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31, 0, BFDctAddlDataReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 31, BFDctAccessDone);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4), 4, 0, BFNbFid);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 18, 18, BFDqsRcvEnTrain);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15, 0, BFMrsAddress);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 18, 16, BFMrsBank);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 22, 20, BFMrsChipSel);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 30, 30, BFSendCtrlWord);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 7, 7, BFLevel);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 12, 12, BFMrsQoff);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 0, 0, BFInitDram);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 16, 16, BFUnBuffDimm);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 8, 8, BFDdr3Mode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 9, 9, BFLegacyBiosMode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 5, 5, BFSubMemclkRegDly);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 6, 6, BFOdtSwizzle);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 15, 8, BFCtrlWordCS);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 8, 8, BFDramEnabled);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 31, 0, BFDctSelBaseAddrReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 31, 0, BFDctSelBaseOffsetReg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 6, 2, BFMctWrLimit);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 12, 12, BFPrefCpuDis);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 13, 13, BFPrefIoDis);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 29, 29, BFFlushWrOnStpGnt);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31, 0, BFODCControl);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31, 0, BFAddrTmgControl);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 0, 0, BFWrtLvTrEn);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 1, 1, BFWrtLvTrMode);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 5, 4, BFTrDimmSel);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11, 8, BFWrLvOdt);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 30, 30, BFDisAutoComp);
-
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- * MemRecNIsIdSupportedDr
- * This function matches the CPU_LOGICAL_ID with certain criteria to
- * determine if it is supported by this NBBlock.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID
- *
- */
-BOOLEAN
-STATIC
-MemRecNIsIdSupportedDr (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN CPU_LOGICAL_ID *LogicalIdPtr
- )
-{
-
- if ((LogicalIdPtr->Revision & (AMD_F10_RB_ALL
- | AMD_F10_BL_ALL
- | AMD_F10_DA_ALL )) != 0) {
- return TRUE;
- } else {
- return FALSE;
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/DR/mrndr.h b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/DR/mrndr.h
deleted file mode 100644
index 2181ae5..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/DR/mrndr.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mndr.h
- *
- * Northbridge Ridgeback Recovery
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MRNDR_H_
-#define _MRNDR_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-#define MAX_DCTS_PER_NODE_DR 2
-#define MAX_CHANNELS_PER_DCT_DR 1
-
-#define _4GB_RJ8 ((UINT32)4 << (30 - 8))
-#define MTRR_VALID 11
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-MemRecConstructNBBlockDR (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- );
-
-VOID
-MemRecNSwitchDctDR (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Dct
- );
-
-VOID
-MemRecNSwitchChannelDR (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Channel
- );
-
-VOID
-MemRecNFinalizeMctDR (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemRecNInitializeMctDR (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-#endif /* _MRNDR_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/DR/mrnmctdr.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/DR/mrnmctdr.c
deleted file mode 100644
index 8ca2fae..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/DR/mrnmctdr.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrnmctdr.c
- *
- * Northbridge DR MCT supporting functions Recovery
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mrport.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mrndr.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_RECOVERY_MEM_NB_DR_MRNMCTDR_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets final values in BUCFG and BUCFG2
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemRecNFinalizeMctDR (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MEM_DATA_STRUCT *MemPtr;
- S_UINT64 SMsr;
-
- MemPtr = NBPtr->MemPtr;
-
-
- // Recommended settings for F2x11C
- MemRecNSetBitFieldNb (NBPtr, BFMctWrLimit, 16);
- MemRecNSetBitFieldNb (NBPtr, BFPrefCpuDis, 0);
- MemRecNSetBitFieldNb (NBPtr, BFPrefIoDis, 0);
- MemRecNSetBitFieldNb (NBPtr, BFFlushWrOnStpGnt, 1);
-
- LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- if (!NBPtr->ClToNbFlag) {
- SMsr.lo &= ~((UINT32) 1 << 15); // ClLinesToNbDis
- }
- LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-
- LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- SMsr.hi &= ~((UINT32) 1 << (48 - 32)); // WbEnhWsbDis
- LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets initial values in BUCFG and BUCFG2
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemRecNInitializeMctDR (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MEM_DATA_STRUCT *MemPtr;
- S_UINT64 SMsr;
-
- MemPtr = NBPtr->MemPtr;
-
- LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- if (SMsr.lo & ((UINT32) 1 << 15)) {
- NBPtr->ClToNbFlag = TRUE;
- }
- SMsr.lo |= (UINT32) 1 << 15; // ClLinesToNbDis
- LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-
- LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- SMsr.hi |= (UINT32) 1 << (48 - 32); // WbEnhWsbDis
- LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/HY/mrndcthy.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/HY/mrndcthy.c
deleted file mode 100644
index c908382..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/HY/mrndcthy.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrndctHy.c
- *
- * Northbridge DCT support for Hydra Recovery
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mru.h"
-#include "mrnhy.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_RECOVERY_MEM_NB_HY_MRNDCTHY_FILECODE
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/HY/mrnhy.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/HY/mrnhy.c
deleted file mode 100644
index 453308a..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/HY/mrnhy.c
+++ /dev/null
@@ -1,710 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrnhy.c
- *
- * Common Northbridge functions for Hydra Recovery
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mrport.h"
-#include "cpuFamRegisters.h"
-#include "cpuRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "mm.h"
-#include "mn.h"
-#include "mrnhy.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-#define FILECODE PROC_RECOVERY_MEM_NB_HY_MRNHY_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define MAX_DIES_PER_SOCKET 2
-#define MAX_DCTS_PER_DIE 2
-#define SPLIT_CHANNEL 0x20000000
-#define CHANNEL_SELECT 0x10000000
-#define MAX_DELAYS 9 /* 8 data bytes + 1 ECC byte */
-#define MAX_DIMMS 4 /* 4 DIMMs per channel */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-VOID
-STATIC
-MemRecNInitNBRegTableHy (
- IN OUT TSEFO *NBRegTable
- );
-
-UINT32
-STATIC
-MemRecNCmnGetSetFieldHy (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN BIT_FIELD_NAME FieldName,
- IN UINT32 Field
- );
-
-UINT32
-STATIC
-MemRecNcmnGetSetTrainDlyHy (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN TRN_DLY_TYPE TrnDly,
- IN DRBN DrbnVar,
- IN UINT16 Field
- );
-
-BOOLEAN
-STATIC
-MemRecNIsIdSupportedHy (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN CPU_LOGICAL_ID *LogicalIdPtr
- );
-
-VOID
-STATIC
-MemRecNSwitchNodeHy (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 NodeID
- );
-
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initializes the northbridge block
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
- * @param[in] NodeID - Node ID for this NB block
- *
- * @return TRUE - This node is a Hydra and this NB block has been initialized
- * @return FALSE - This node is not a Hydra
- */
-
-BOOLEAN
-MemRecConstructNBBlockHY (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- )
-{
- UINT8 i;
- UINT8 Dct;
- UINT8 Channel;
- DIE_STRUCT *MCTPtr;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
- //
- // Determine if this is the expected NB Type
- //
- GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
- if (!MemRecNIsIdSupportedHy (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
- return FALSE;
- }
-
- //
- // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
- //
- MCTPtr = &MemPtr->DiesPerSystem[NodeID];
- AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_HY * (
- sizeof (DCT_STRUCT) + (
- MAX_CHANNELS_PER_DCT_HY * (
- sizeof (CH_DEF_STRUCT) + (
- MAX_DIMMS * MAX_DELAYS * NUMBER_OF_DELAY_TABLES
- )
- )
- )
- );
- AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0);
- AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
- if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) {
- return FALSE;
- }
-
- MemPtr->DieCount = MAX_DIES_PER_SOCKET;
- MCTPtr->DctCount = MAX_DCTS_PER_NODE_HY;
- MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr;
- MemPtr->DiesPerSystem[NodeID + 1].DctCount = MAX_DCTS_PER_NODE_HY;
- MemPtr->DiesPerSystem[NodeID + 1].DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_HY * sizeof (DCT_STRUCT);
- for (Dct = 0; Dct < MAX_DCTS_PER_NODE_HY; Dct++) {
- MCTPtr->DctData[Dct].Dct = Dct;
- MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_HY;
- MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr;
- MCTPtr->DctData[Dct].ChData[0].ChannelID = (MCTPtr->DieId * 2) + Dct;
- AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_HY * sizeof (CH_DEF_STRUCT);
- for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_HY; Channel++) {
- MCTPtr->DctData[Dct].ChData[Channel].RcvEnDlys = (UINT16 *) AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS) * 2;
- MCTPtr->DctData[Dct].ChData[Channel].WrDqsDlys = AllocHeapParams.BufferPtr;
- MCTPtr->DctData[Dct].ChData[Channel].Dct = Dct;
- AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS);
- }
- }
-
- //
- // Initialize NB block's variables
- //
- NBPtr->MemPtr = MemPtr;
- NBPtr->RefPtr = MemPtr->ParameterListPtr;
- NBPtr->MCTPtr = MCTPtr;
- NBPtr->AllNodeMCTPtr = &MemPtr->DiesPerSystem[NodeID];
- NBPtr->SPDPtr = &MemPtr->SpdDataStructure[MemPtr->DiesPerSystem[NodeID].SocketId * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL];
- NBPtr->AllNodeSPDPtr = &MemPtr->SpdDataStructure[MemPtr->DiesPerSystem[NodeID].SocketId * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL];
-
- NBPtr->DctCachePtr = NBPtr->DctCache;
-
- MemRecNInitNBRegTableHy (NBPtr->NBRegTable);
- NBPtr->Dct = 0;
- NBPtr->Channel = 0;
- NBPtr->VarMtrrHiMsk = MemRecGetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
-
- LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader);
- LibAmdMemFill (NBPtr->IsSupported, FALSE, sizeof (NBPtr->IsSupported), &NBPtr->MemPtr->StdHeader);
- for (i = 0; i < NumberOfHooks; i++) {
- NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) MemRecDefTrue;
- }
-
- NBPtr->InitRecovery = MemRecNMemInitNb;
-
- NBPtr->SwitchNodeRec = MemRecNSwitchNodeHy;
- NBPtr->SwitchDCT = MemRecNSwitchDctHy;
- NBPtr->SwitchChannel = MemRecNSwitchChannelHy;
- NBPtr->SetMaxLatency = MemRecNSetMaxLatencyNb;
- NBPtr->GetSysAddrRec = MemRecNGetMCTSysAddrNb;
- NBPtr->SendMrsCmd = MemRecNSendMrsCmdNb;
- NBPtr->sendZQCmd = MemRecNSendZQCmdNb;
- NBPtr->SetDramOdtRec = MemRecNSetDramOdtNb;
-
- NBPtr->GetBitField = MemRecNGetBitFieldNb;
- NBPtr->SetBitField = MemRecNSetBitFieldNb;
- NBPtr->GetTrainDly = MemRecNGetTrainDlyNb;
- NBPtr->SetTrainDly = MemRecNSetTrainDlyNb;
-
- NBPtr->MemRecNCmnGetSetFieldNb = MemRecNCmnGetSetFieldHy;
- NBPtr->MemRecNcmnGetSetTrainDlyNb = MemRecNcmnGetSetTrainDlyHy;
- NBPtr->MemRecNSwitchDctNb = MemRecNSwitchDctHy;
- NBPtr->TrainingFlow = MemNRecTrainingFlowNb;
- NBPtr->MemRecNInitializeMctNb = MemRecNInitializeMctHy;
- NBPtr->MemRecNFinalizeMctNb = MemRecNFinalizeMctHy;
- NBPtr->IsSupported[DramModeAfterDimmPres] = TRUE;
- MemRecNSwitchDctHy (NBPtr, 0);
-
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function sets the current die to work on.
- * Should be called before accessing a certain die
- * All data structures will be updated to point to the current node
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] NodeID - ID of the target die
- *
- */
-
-VOID
-STATIC
-MemRecNSwitchNodeHy (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 NodeID
- )
-{
- NBPtr->MCTPtr = &(NBPtr->AllNodeMCTPtr[NodeID]);
- NBPtr->Node = NodeID;
- NBPtr->MCTPtr->NodeId = NodeID;
- MemRecNSwitchDctHy (NBPtr, NBPtr->Dct);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the current DCT to work on.
- * Should be called before accessing a certain DCT
- * All data structures will be updated to point to the current DCT
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Dct - ID of the target DCT
- *
- */
-
-VOID
-MemRecNSwitchDctHy (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Dct
- )
-{
- NBPtr->Dct = Dct & 1;
- NBPtr->SPDPtr = &(NBPtr->AllNodeSPDPtr[(NBPtr->MCTPtr->NodeId * MAX_DCTS_PER_DIE + Dct) * MAX_DIMMS_PER_CHANNEL]);
- NBPtr->DCTPtr = &(NBPtr->MCTPtr->DctData[NBPtr->Dct]);
-
- MemRecNSwitchChannelHy (NBPtr, 0);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the current channel to work on.
- * Should be called before accessing a certain channel
- * All data structures will be updated to point to the current channel
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Channel - ID of the target channel
- *
- */
-
-VOID
-MemRecNSwitchChannelHy (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Channel
- )
-{
- NBPtr->Channel = 0;
- NBPtr->ChannelPtr = &(NBPtr->DCTPtr->ChData[0]);
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function gets or set DQS timing during training.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] TrnDly - type of delay to be set
- * @param[in] DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed
- * (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding
- * @param[in] Field - Value to be programmed
- * @param[in] IsSet - Indicates if the function will set or get
- *
- * @return value read, if the function is used as a "get"
- */
-
-UINT32
-STATIC
-MemRecNcmnGetSetTrainDlyHy (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN TRN_DLY_TYPE TrnDly,
- IN DRBN DrbnVar,
- IN UINT16 Field
- )
-{
- UINT16 index;
- UINT16 offset;
- UINT32 value;
- UINT32 address;
- UINT8 DIMM;
- UINT8 Rank;
- UINT8 Byte;
- UINT8 Nibble;
-
- DIMM = DRBN_DIMM (DrbnVar);
- Rank = DRBN_RANK (DrbnVar);
- Byte = DRBN_BYTE (DrbnVar);
- Nibble = DRBN_NBBL (DrbnVar);
-
- switch (TrnDly) {
- case AccessRcvEnDly:
- index = 0x10;
- break;
- case AccessWrDqsDly:
- index = 0x30;
- break;
- case AccessWrDatDly:
- index = 0x01;
- break;
- case AccessRdDqsDly:
- index = 0x05;
- break;
- case AccessPhRecDly:
- index = 0x50;
- break;
- default:
- index = 0;
- IDS_ERROR_TRAP;
- }
-
- switch (TrnDly) {
- case AccessRcvEnDly:
- case AccessWrDqsDly:
- index += (DIMM * 3);
- if ((Byte & 0x04) != 0) {
- // if byte 4,5,6,7
- index += 0x10;
- }
- if ((Byte & 0x02) != 0) {
- // if byte 2,3,6,7
- index++;
- }
- if (Byte > 7) {
- index += 2;
- }
- offset = 16 * (Byte % 2);
- index |= (Rank << 8);
- index |= (Nibble << 9);
- break;
-
- case AccessRdDqsDly:
- Field &= ~ 0x0001;
- case AccessWrDatDly:
- index += (DIMM * 0x100);
- if (Nibble != 0) {
- if (Rank != 0) {
- index += 0xA0;
- } else {
- index += 0x70;
- }
- } else if (Rank != 0) {
- index += 0x60;
- }
- // break is not being used here because AccessRdDqsDly and AccessWrDatDly also need
- // to run AccessPhRecDly sequence.
- case AccessPhRecDly:
- index += (Byte / 4);
- offset = 8 * (Byte % 4);
- break;
- default:
- offset = 0;
- IDS_ERROR_TRAP;
- }
-
- address = index;
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, address);
- while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
- value = MemRecNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
-
- if (IsSet != 0) {
- if (TrnDly == AccessPhRecDly) {
- value = NBPtr->DctCachePtr->PhRecReg[index & 0x03];
- }
-
- value = ((UINT32)Field << offset) | (value & (~((UINT32)0xFF << offset)));
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlDataReg, value);
- address |= DCT_ACCESS_WRITE;
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, address);
- while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
-
- if (TrnDly == AccessPhRecDly) {
- NBPtr->DctCachePtr->PhRecReg[index & 0x03] = value;
- }
- } else {
- value = (value >> offset) & 0xFF;
- }
-
- return value;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function gets or sets a value to a bit field in a PCI register.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] FieldName - Name of Field to be set
- * @param[in] Field - Value to be programmed
- * @param[in] IsSet - Indicates if the function will set or get
- *
- * @return value read, if the function is used as a "get"
- */
-
-UINT32
-STATIC
-MemRecNCmnGetSetFieldHy (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN BIT_FIELD_NAME FieldName,
- IN UINT32 Field
- )
-{
- SBDFO Address;
- PCI_ADDR PciAddr;
- UINT8 Type;
- UINT32 Value;
- UINT32 Highbit;
- UINT32 Lowbit;
- UINT32 Mask;
-
- Value = 0;
- if (FieldName < BFEndOfList) {
- Address = NBPtr->NBRegTable[FieldName];
- if (Address != 0) {
- Lowbit = TSEFO_END (Address);
- Highbit = TSEFO_START (Address);
- Type = TSEFO_TYPE (Address);
-
- // If Fn2 and DCT1 selected, set Address to be 1xx
- if (((Address & 0xF000) == 0x2000) && (NBPtr->Dct != 0)) {
- Address |= 0x0100;
- }
- if ((Address >> 29) == ((DCT_PHY_ACCESS << 1) | 1)) {
- // Special DCT Phy access
- Address &= 0x0FFFFFFF;
- Lowbit = 0;
- Highbit = 16;
- } else {
- // Normal DCT Phy access
- Address = TSEFO_OFFSET (Address);
- }
-
-
- if (Type == NB_ACCESS) {
- // Address |= (((UINT32) (24 + 0)) << 15);
- PciAddr.AddressValue = Address;
- // Fix for MCM
- PciAddr.Address.Device = NBPtr->MemPtr->DiesPerSystem[NBPtr->Node].PciAddr.Address.Device;
- PciAddr.Address.Bus = NBPtr->MemPtr->DiesPerSystem[NBPtr->Node].PciAddr.Address.Bus;
- PciAddr.Address.Segment = NBPtr->MemPtr->DiesPerSystem[NBPtr->Node].PciAddr.Address.Segment;
- Address = PciAddr.AddressValue;
- LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
- } else if (Type == DCT_PHY_ACCESS) {
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
- while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
-
- Value = MemRecNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
- } else {
- IDS_ERROR_TRAP;
- }
-
- if (IsSet != 0) {
- // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
- if ((Highbit - Lowbit) != 31) {
- Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
- } else {
- Mask = (UINT32)0xFFFFFFFF;
- }
- Value &= ~(Mask << Lowbit);
- Value |= (Field & Mask) << Lowbit;
-
- if (Type == NB_ACCESS) {
- PciAddr.AddressValue = Address;
- LibAmdPciWrite (AccessWidth32, PciAddr , &Value, &NBPtr->MemPtr->StdHeader);
- } else if (Type == DCT_PHY_ACCESS) {
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
- Address |= DCT_ACCESS_WRITE;
-
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
- while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
- } else {
- IDS_ERROR_TRAP;
- }
- } else {
- Value = Value >> Lowbit; // Shift
- // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
- if ((Highbit - Lowbit) != 31) {
- Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
- }
- }
- }
- } else {
- IDS_ERROR_TRAP; // Invalid bit field index
- }
- return Value;
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initializes bit field translation table
- *
-* @param[in,out] *NBRegTable - Pointer to the NB Table *
- */
-
-VOID
-STATIC
-MemRecNInitNBRegTableHy (
- IN OUT TSEFO *NBRegTable
- )
-{
- UINT16 i;
- for (i = 0; i <= BFEndOfList; i++) {
- NBRegTable[i] = 0;
- }
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31, 0, BFDevVendorIDReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60), 2, 0, BFNodeID);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31, 0, BFCSBaseAddr0Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31, 0, BFCSBaseAddr1Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31, 0, BFCSBaseAddr2Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31, 0, BFCSBaseAddr3Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x50), 31, 0, BFCSBaseAddr4Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x54), 31, 0, BFCSBaseAddr5Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x58), 31, 0, BFCSBaseAddr6Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x5C), 31, 0, BFCSBaseAddr7Reg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31, 0, BFCSMask0Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31, 0, BFCSMask1Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x68), 31, 0, BFCSMask2Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x6C), 31, 0, BFCSMask3Reg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 0, BFDramControlReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 0, BFDramInitRegReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31, 0, BFDramBankAddrReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31, 0, BFDramMRSReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 9, 7, BFDramTerm);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 11, 10, BFDramTermDyn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 0, BFDramTimingLoReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 0, BFDramTimingHiReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31, 0, BFDramConfigLoReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 0, BFDramConfigHiReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 0, BFDctAddlOffsetReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31, 0, BFDctAddlDataReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 31, BFDctAccessDone);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4), 4, 0, BFNbFid);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 18, 18, BFDqsRcvEnTrain);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15, 0, BFMrsAddress);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 18, 16, BFMrsBank);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 22, 20, BFMrsChipSel);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 30, 30, BFSendCtrlWord);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 7, 7, BFLevel);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 12, 12, BFMrsQoff);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 0, 0, BFInitDram);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 16, 16, BFUnBuffDimm);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 8, 8, BFDdr3Mode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 9, 9, BFLegacyBiosMode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 5, 5, BFSubMemclkRegDly);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 6, 6, BFOdtSwizzle);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 15, 8, BFCtrlWordCS);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 8, 8, BFDramEnabled);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 31, 0, BFDctSelBaseAddrReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 31, 0, BFDctSelBaseOffsetReg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 31, 0, BFMctCfgHiReg);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31, 0, BFODCControl);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31, 0, BFAddrTmgControl);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 0, 0, BFWrtLvTrEn);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 1, 1, BFWrtLvTrMode);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 5, 4, BFTrDimmSel);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11, 8, BFWrLvOdt);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 30, 30, BFDisAutoComp);
-
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- * MemRecNIsIdSupportedHy
- * This function matches the CPU_LOGICAL_ID with certain criteria to
- * determine if it is supported by this NBBlock.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID
- *
- * @return TRUE - This node is a Hydra.
- * @return FALSE - This node is not a Hydra.
- *
- */
-BOOLEAN
-STATIC
-MemRecNIsIdSupportedHy (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN CPU_LOGICAL_ID *LogicalIdPtr
- )
-{
- if ((LogicalIdPtr->Revision & AMD_F10_HY_ALL) != 0) {
- return TRUE;
- } else {
- return FALSE;
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/HY/mrnhy.h b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/HY/mrnhy.h
deleted file mode 100644
index 93c3d01..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/HY/mrnhy.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnhy.h
- *
- * Northbridge Hydra Recovery
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MRNHY_H_
-#define _MRNHY_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-#define MAX_DCTS_PER_NODE_HY 2
-#define MAX_CHANNELS_PER_DCT_HY 1
-
-#define _4GB_RJ8 ((UINT32)4 << (30 - 8))
-#define MTRR_VALID 11
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-MemRecConstructNBBlockHY (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- );
-
-VOID
-MemRecNSwitchDctHy (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Dct
- );
-
-VOID
-MemRecNSwitchChannelHy (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Channel
- );
-
-VOID
-MemRecNFinalizeMctHy (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemRecNInitializeMctHy (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-#endif /* _MRNHY_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/HY/mrnmcthy.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/HY/mrnmcthy.c
deleted file mode 100644
index 60fbc9a..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/HY/mrnmcthy.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrnmctdr.c
- *
- * Northbridge DR MCT supporting functions Recovery
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mrport.h"
-#include "mm.h"
-#include "mn.h"
-#include "mrnhy.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_RECOVERY_MEM_NB_HY_MRNMCTHY_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets final values in BUCFG and BUCFG2
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemRecNFinalizeMctHy (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MEM_DATA_STRUCT *MemPtr;
- S_UINT64 SMsr;
-
- MemPtr = NBPtr->MemPtr;
-
- // Recommended settings for F2x11C
- MemRecNSetBitFieldNb (NBPtr, BFMctCfgHiReg, 0x2CE00F60);
-
- LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- if (!NBPtr->ClToNbFlag) {
- SMsr.lo &= ~((UINT32) 1 << 15); // ClLinesToNbDis
- }
- LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-
- LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- SMsr.hi &= ~((UINT32) 1 << (48 - 32)); // WbEnhWsbDis
- LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets initial values in BUCFG and BUCFG2
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemRecNInitializeMctHy (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MEM_DATA_STRUCT *MemPtr;
- S_UINT64 SMsr;
-
- MemPtr = NBPtr->MemPtr;
-
- LibAmdMsrRead (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- if (SMsr.lo & ((UINT32) 1 << 15)) {
- NBPtr->ClToNbFlag = TRUE;
- }
- SMsr.lo |= (UINT32) 1 << 15; // ClLinesToNbDis
- LibAmdMsrWrite (BU_CFG2, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-
- LibAmdMsrRead (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- SMsr.hi |= (UINT32) 1 << (48 - 32); // WbEnhWsbDis
- LibAmdMsrWrite (BU_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/HY/mrnprotohy.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/HY/mrnprotohy.c
deleted file mode 100644
index 316b25d..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/HY/mrnprotohy.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrnproto.c
- *
- * Northbridge support functions for Errata and early samples Recovery
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-
-#include "AGESA.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_RECOVERY_MEM_NB_HY_MRNPROTOHY_FILECODE
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/NI/mrnNi.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/NI/mrnNi.c
deleted file mode 100644
index 1ed06f4..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/NI/mrnNi.c
+++ /dev/null
@@ -1,651 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrnNi.c
- *
- * Common Northbridge functions for Nile Recovery
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "cpuRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "mrport.h"
-#include "mm.h"
-#include "mn.h"
-#include "mrnda.h"
-#include "mrnNi.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_RECOVERY_MEM_NB_NI_MRNNI_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-#define SPLIT_CHANNEL 0x20000000
-#define CHANNEL_SELECT 0x10000000
-#define MAX_DELAYS 9 /* 8 data bytes + 1 ECC byte */
-#define MAX_DIMMS 4 /* 4 DIMMs per channel */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-VOID
-STATIC
-MemRecNInitNBRegTableNi (
- IN OUT TSEFO *NBRegTable
- );
-
-UINT32
-STATIC
-MemRecNCmnGetSetFieldNi (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN BIT_FIELD_NAME FieldName,
- IN UINT32 Field
- );
-
-UINT32
-STATIC
-MemRecNcmnGetSetTrainDlyNi (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN TRN_DLY_TYPE TrnDly,
- IN DRBN DrbnVar,
- IN UINT16 Field
- );
-
-BOOLEAN
-STATIC
-MemRecNIsIdSupportedNi (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN CPU_LOGICAL_ID *LogicalIdPtr
- );
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initializes the northbridge block
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
- * @param[in] NodeID - Node ID for this NB block
- *
- * @return TRUE - This node is a RB and this NB block has been initialized
- * @return FALSE - This node is not a RB
- */
-
-BOOLEAN
-MemRecConstructNBBlockNi (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- )
-{
- UINT8 i;
- UINT8 Dct;
- UINT8 Channel;
- DIE_STRUCT *MCTPtr;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
- //
- // Determine if this is the expected NB Type
- //
- GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
- if (!MemRecNIsIdSupportedNi (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
- return FALSE;
- }
-
- //
- // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
- //
- MCTPtr = &MemPtr->DiesPerSystem[NodeID];
- AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_DA * (
- sizeof (DCT_STRUCT) + (
- MAX_CHANNELS_PER_DCT_DA * (
- sizeof (CH_DEF_STRUCT) + (
- MAX_DIMMS * MAX_DELAYS * NUMBER_OF_DELAY_TABLES
- )
- )
- )
- );
- AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0);
- AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
- if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) {
- return FALSE;
- }
-
- MCTPtr->DctCount = MAX_DCTS_PER_NODE_DA;
- MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_DA * sizeof (DCT_STRUCT);
- for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
- MCTPtr->DctData[Dct].Dct = Dct;
- MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_DA;
- MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr;
- MCTPtr->DctData[Dct].ChData[0].ChannelID = Dct;
- AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_DA * sizeof (CH_DEF_STRUCT);
- for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_DA; Channel++) {
- MCTPtr->DctData[Dct].ChData[Channel].RcvEnDlys = (UINT16 *) AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS) * 2;
- MCTPtr->DctData[Dct].ChData[Channel].WrDqsDlys = AllocHeapParams.BufferPtr;
- MCTPtr->DctData[Dct].ChData[Channel].Dct = Dct;
- AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS);
- }
- }
-
- //
- // Initialize NB block's variables
- //
- NBPtr->MemPtr = MemPtr;
- NBPtr->RefPtr = MemPtr->ParameterListPtr;
- NBPtr->MCTPtr = MCTPtr;
- NBPtr->SPDPtr = &MemPtr->SpdDataStructure[MemPtr->DiesPerSystem[NodeID].SocketId * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL];
- NBPtr->AllNodeSPDPtr = &MemPtr->SpdDataStructure[MemPtr->DiesPerSystem[NodeID].SocketId * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL];
-
- NBPtr->DctCachePtr = NBPtr->DctCache;
-
- MemRecNInitNBRegTableNi (NBPtr->NBRegTable);
- NBPtr->Dct = 0;
- NBPtr->Channel = 0;
- NBPtr->VarMtrrHiMsk = MemRecGetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
-
- LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader);
- LibAmdMemFill (NBPtr->IsSupported, FALSE, sizeof (NBPtr->IsSupported), &NBPtr->MemPtr->StdHeader);
- for (i = 0; i < NumberOfHooks; i++) {
- NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) MemRecDefTrue;
- }
-
- NBPtr->InitRecovery = MemRecNMemInitNb;
-
- NBPtr->SwitchNodeRec = (VOID (*) (MEM_NB_BLOCK *, UINT8)) MemRecDefRet;
- NBPtr->SwitchDCT = MemRecNSwitchDctNi;
- NBPtr->SwitchChannel = MemRecNSwitchChannelNi;
- NBPtr->SetMaxLatency = MemRecNSetMaxLatencyNb;
- NBPtr->GetSysAddrRec = MemRecNGetMCTSysAddrNb;
- NBPtr->SendMrsCmd = MemRecNSendMrsCmdNb;
- NBPtr->sendZQCmd = MemRecNSendZQCmdNb;
- NBPtr->SetDramOdtRec = MemRecNSetDramOdtNb;
-
- NBPtr->GetBitField = MemRecNGetBitFieldNb;
- NBPtr->SetBitField = MemRecNSetBitFieldNb;
- NBPtr->GetTrainDly = MemRecNGetTrainDlyNb;
- NBPtr->SetTrainDly = MemRecNSetTrainDlyNb;
- NBPtr->MemRecNCmnGetSetFieldNb = MemRecNCmnGetSetFieldNi;
- NBPtr->MemRecNcmnGetSetTrainDlyNb = MemRecNcmnGetSetTrainDlyNi;
- NBPtr->MemRecNSwitchDctNb = MemRecNSwitchDctNi;
- NBPtr->TrainingFlow = MemNRecTrainingFlowNb;
- NBPtr->MemRecNInitializeMctNb = MemRecNInitializeMctDA;
- NBPtr->MemRecNFinalizeMctNb = MemRecNFinalizeMctDA;
- NBPtr->IsSupported[DramModeBeforeDimmPres] = TRUE;
- NBPtr->IsSupported[CheckClearOnDimmMirror] = TRUE;
- MemRecNSwitchDctNi (NBPtr, 0);
-
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the current DCT to work on.
- * Should be called before accessing a certain DCT
- * All data structures will be updated to point to the current DCT
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Dct - ID of the target DCT
- *
- */
-
-VOID
-MemRecNSwitchDctNi (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Dct
- )
-{
- NBPtr->Dct = Dct & 1;
- NBPtr->SPDPtr = &(NBPtr->AllNodeSPDPtr[Dct * MAX_DIMMS_PER_CHANNEL]);
- NBPtr->DCTPtr = &(NBPtr->MCTPtr->DctData[NBPtr->Dct]);
-
- MemRecNSwitchChannelNi (NBPtr, NBPtr->Channel);
-}
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the current channel to work on.
- * Should be called before accessing a certain channel
- * All data structures will be updated to point to the current channel
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Channel - ID of the target channel
- *
- */
-
-VOID
-MemRecNSwitchChannelNi (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Channel
- )
-{
- NBPtr->Channel = Channel & 1;
- NBPtr->ChannelPtr = &(NBPtr->DCTPtr->ChData[NBPtr->Channel]);
-}
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function gets or set DQS timing during training.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] TrnDly - type of delay to be set
- * @param[in] DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed
- * (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding
- * @param[in] Field - Value to be programmed
- * @param[in] IsSet - Indicates if the function will set or get
- *
- * @return value read, if the function is used as a "get"
- */
-
-UINT32
-STATIC
-MemRecNcmnGetSetTrainDlyNi (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN TRN_DLY_TYPE TrnDly,
- IN DRBN DrbnVar,
- IN UINT16 Field
- )
-{
- UINT16 Index;
- UINT16 Offset;
- UINT32 Value;
- UINT32 Address;
- UINT8 Dimm;
- UINT8 Byte;
-
- Dimm = DRBN_DIMM (DrbnVar);
- Byte = DRBN_BYTE (DrbnVar);
-
- ASSERT (Dimm < 4);
- ASSERT (Byte <= 8);
-
- switch (TrnDly) {
- case AccessRcvEnDly:
- Index = 0x10;
- break;
- case AccessWrDqsDly:
- Index = 0x30;
- break;
- case AccessWrDatDly:
- Index = 0x01;
- break;
- case AccessRdDqsDly:
- Index = 0x05;
- break;
- case AccessPhRecDly:
- Index = 0x50;
- break;
- default:
- Index = 0;
- IDS_ERROR_TRAP;
- }
-
- switch (TrnDly) {
- case AccessRcvEnDly:
- case AccessWrDqsDly:
- Index += (Dimm * 3);
- if (Byte & 0x04) {
- // if byte 4,5,6,7
- Index += 0x10;
- }
- if (Byte & 0x02) {
- // if byte 2,3,6,7
- Index++;
- }
- Offset = 16 * (Byte % 2);
- break;
-
- case AccessRdDqsDly:
- Field &= ~ 0x0001;
- case AccessWrDatDly:
- Index += (Dimm * 0x100);
- // break is not being used here because AccessRdDqsDly and AccessWrDatDly also need
- // to run AccessPhRecDly sequence.
- case AccessPhRecDly:
- Index += (Byte / 4);
- Offset = 8 * (Byte % 4);
- break;
- default:
- Offset = 0;
- IDS_ERROR_TRAP;
- }
-
- Address = Index;
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
- while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
- Value = MemRecNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
-
- if (IsSet) {
- if (TrnDly == AccessPhRecDly) {
- Value = NBPtr->DctCachePtr->PhRecReg[Index & 0x03];
- }
-
- Value = ((UINT32)Field << Offset) | (Value & (~((UINT32)0xFF << Offset)));
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
- Address |= DCT_ACCESS_WRITE;
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
- while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
-
- if (TrnDly == AccessPhRecDly) {
- NBPtr->DctCachePtr->PhRecReg[Index & 0x03] = Value;
- }
- } else {
- Value = (Value >> Offset) & 0xFF;
- }
-
- return Value;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function gets or sets a value to a bit field in a PCI register.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] IsSet - Indicates if the function will set or get
- * @param[in] FieldName - Name of field to be set
- * @param[in] Field - Value to be programmed
- *
- * @return value read, if the function is used as a "get"
- */
-
-UINT32
-STATIC
-MemRecNCmnGetSetFieldNi (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN BIT_FIELD_NAME FieldName,
- IN UINT32 Field
- )
-{
- SBDFO Address;
- PCI_ADDR PciAddr;
- UINT8 Type;
- UINT32 Value;
- UINT32 Highbit;
- UINT32 Lowbit;
- UINT32 Mask;
-
- Value = 0;
- if (FieldName < BFEndOfList) {
- Address = NBPtr->NBRegTable[FieldName];
- if (Address) {
- Lowbit = TSEFO_END (Address);
- Highbit = TSEFO_START (Address);
- Type = TSEFO_TYPE (Address);
-
- // If Fn2 and DCT1 selected, set Address to be 1xx
- if (((Address & 0xF000) == 0x2000) && NBPtr->Dct) {
- Address |= 0x0100;
- }
- if ((Address >> 29) == ((DCT_PHY_ACCESS << 1) | 1)) {
- // Special DCT Phy access
- Address &= 0x0FFFFFFF;
- Lowbit = 0;
- Highbit = 16;
- } else {
- // Normal DCT Phy access
- Address = TSEFO_OFFSET (Address);
- }
-
-
- if (Type == NB_ACCESS) {
- Address |= (((UINT32) (24 + 0)) << 15);
- PciAddr.AddressValue = Address;
- LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
- } else if (Type == DCT_PHY_ACCESS) {
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
- while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
-
- Value = MemRecNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
- } else {
- IDS_ERROR_TRAP;
- }
-
- if (IsSet) {
- // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
- if ((Highbit - Lowbit) != 31) {
- Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
- } else {
- Mask = (UINT32)0xFFFFFFFF;
- }
- Value &= ~(Mask << Lowbit);
- Value |= (Field & Mask) << Lowbit;
-
- if (Type == NB_ACCESS) {
- PciAddr.AddressValue = Address;
- LibAmdPciWrite (AccessWidth32, PciAddr , &Value, &NBPtr->MemPtr->StdHeader);
- } else if (Type == DCT_PHY_ACCESS) {
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
- Address |= DCT_ACCESS_WRITE;
-
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
- while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
- } else {
- IDS_ERROR_TRAP;
- }
- } else {
- Value = Value >> Lowbit; // Shift
- // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
- if ((Highbit - Lowbit) != 31) {
- Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
- }
- }
- }
- } else {
- IDS_ERROR_TRAP; // Invalid bit field index
- }
- return Value;
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initializes bit field translation table
- *
- * @param[in,out] *NBRegTable - Pointer to the NB Table *
- */
-
-VOID
-STATIC
-MemRecNInitNBRegTableNi (
- IN OUT TSEFO *NBRegTable
- )
-{
- UINT16 i;
- for (i = 0; i <= BFEndOfList; i++) {
- NBRegTable[i] = 0;
- }
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31, 0, BFDevVendorIDReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60), 2, 0, BFNodeID);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31, 0, BFCSBaseAddr0Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31, 0, BFCSBaseAddr1Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31, 0, BFCSBaseAddr2Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31, 0, BFCSBaseAddr3Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x50), 31, 0, BFCSBaseAddr4Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x54), 31, 0, BFCSBaseAddr5Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x58), 31, 0, BFCSBaseAddr6Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x5C), 31, 0, BFCSBaseAddr7Reg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31, 0, BFCSMask0Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31, 0, BFCSMask1Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x68), 31, 0, BFCSMask2Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x6C), 31, 0, BFCSMask3Reg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 0, BFDramControlReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 0, BFDramInitRegReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31, 0, BFDramBankAddrReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31, 0, BFDramMRSReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 9, 7, BFDramTerm);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 11, 10, BFDramTermDyn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 0, BFDramTimingLoReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 0, BFDramTimingHiReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31, 0, BFDramConfigLoReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 0, BFDramConfigHiReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 0, BFDctAddlOffsetReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31, 0, BFDctAddlDataReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 31, BFDctAccessDone);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4), 4, 0, BFNbFid);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 18, 18, BFDqsRcvEnTrain);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15, 0, BFMrsAddress);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 18, 16, BFMrsBank);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 22, 20, BFMrsChipSel);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 30, 30, BFSendCtrlWord);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 7, 7, BFLevel);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 12, 12, BFMrsQoff);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 0, 0, BFInitDram);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 16, 16, BFUnBuffDimm);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 8, 8, BFDdr3Mode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 9, 9, BFLegacyBiosMode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 6, 6, BFOdtSwizzle);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 15, 8, BFCtrlWordCS);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 8, 8, BFDramEnabled);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 31, 0, BFDctSelBaseAddrReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 31, 0, BFDctSelBaseOffsetReg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 6, 2, BFMctWrLimit);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 12, 12, BFPrefCpuDis);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 13, 13, BFPrefIoDis);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 29, 29, BFFlushWrOnStpGnt);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31, 0, BFODCControl);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31, 0, BFAddrTmgControl);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 0, 0, BFWrtLvTrEn);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 1, 1, BFWrtLvTrMode);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 5, 4, BFTrDimmSel);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11, 8, BFWrLvOdt);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 30, 30, BFDisAutoComp);
-
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- * MemRecNIsIdSupportedNi
- * This function matches the CPU_LOGICAL_ID with certain criteria to
- * determine if it is supported by this NBBlock.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID
- *
- */
-BOOLEAN
-STATIC
-MemRecNIsIdSupportedNi (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN CPU_LOGICAL_ID *LogicalIdPtr
- )
-{
-
- if ((LogicalIdPtr->Revision & (AMD_F10_BL_ALL | AMD_F10_DA_ALL)) != 0) {
- return TRUE;
- } else {
- return FALSE;
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/NI/mrnNi.h b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/NI/mrnNi.h
deleted file mode 100644
index ddfde89..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/NI/mrnNi.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrnNi.h
- *
- * Northbridge Ni Recovery
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MRNNI_H_
-#define _MRNNI_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-#define _4GB_RJ8 ((UINT32)4 << (30 - 8))
-#define MTRR_VALID 11
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-MemRecConstructNBBlockNi (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- );
-
-VOID
-MemRecNSwitchDctNi (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Dct
- );
-
-VOID
-MemRecNSwitchChannelNi (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Channel
- );
-
-#endif /* _MRNNI_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/ON/mrndcton.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/ON/mrndcton.c
deleted file mode 100644
index e90de93..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/ON/mrndcton.c
+++ /dev/null
@@ -1,363 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrndcton.c
- *
- * Northbridge DCT support for Ontario Recovery
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "Ids.h"
-#include "amdlib.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mru.h"
-#include "mrnon.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuCommonF14Utilities.h"
-#include "Filecode.h"
-#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNDCTON_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define RECDEF_DRAM_CONTROL_REG 0x14042A03
-#define RECDEF_DRAM_MRSREG 0x000400A5
-#define RECDEF_DRAM_TIMING_LO 0x000A0092
-#define RECDEF_DRAM_TIMING_HI 0x001218FF
-#define RECDEF_CSMASK_REG 0x00003FE0
-#define RECDEF_DRAM_CONFIG_LO_REG 0x30000000
-#define RECDEF_DRAM_CONFIG_HI_REG 0x1E000000
-#define RECDEF_DRAM_BASE_REG 0x00000003
-#define RECDEF_DRAM_TIMING_0 0x0A000101
-#define RECDEF_DRAM_TIMING_1 0
-
-#define MAX_RD_DQS_DLY 0x1F
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function gets platform specific config/timing values from the interface layer and
- * programs them into DCT.
- *
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - An Error value lower than AGESA_ERROR may have occurred
- * @return FALSE - An Error value greater than or equal to AGESA_ERROR may have occurred
- */
-
-BOOLEAN
-MemRecNPlatformSpecON (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT32 AddrTmgValue;
- UINT32 DrvStrValue;
- CH_DEF_STRUCT *ChannelPtr;
-
- ChannelPtr = NBPtr->ChannelPtr;
- if (ChannelPtr->SODimmPresent != 0) {
- // SODIMM
- if (ChannelPtr->Dimms == 2) {
- AddrTmgValue = 0x00000039;
- DrvStrValue = 0x30222323;
- } else {
- AddrTmgValue = 0;
- DrvStrValue = 0x00002222;
- }
- } else {
- // UDIMM
- if (ChannelPtr->Dimms == 2) {
- AddrTmgValue = 0x00390039;
- DrvStrValue = 0x30222322;
- } else {
- AddrTmgValue = 0;
- DrvStrValue = 0x00112222;
- if (ChannelPtr->DimmDrPresent != 0) {
- AddrTmgValue = 0x003B0000;
- }
- }
- }
- MemRecNSetBitFieldNb (NBPtr, BFODCControl, DrvStrValue);
- MemRecNSetBitFieldNb (NBPtr, BFAddrTmgControl, AddrTmgValue);
-
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the maximum round-trip latency in the system from the processor to the DRAM
- * devices and back.
-
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] MaxRcvEnDly - Maximum receiver enable delay value
- *
- */
-
-VOID
-MemRecNSetMaxLatencyON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT16 MaxRcvEnDly
- )
-{
- UINT32 N;
- UINT32 T;
- UINT32 P;
- UINT32 Px2;
- UINT32 MemClkPeriod;
-
- T = MemRecNTotalSyncComponentsClientNb (NBPtr);
-
- // P = P + CEIL(MAX (total delay in DqsRcvEn + RdDqsTime))
- P = (MaxRcvEnDly + MAX_RD_DQS_DLY + 31) / 32;
-
- MemClkPeriod = 1000000 / DDR800_FREQUENCY;
-
- // P = P + 6.5
- // T = T + 2586 ps
- Px2 = (P * 2) + 13;
- T += 2586;
-
- // N = (P/(MemClkFreq * 2) + T) * NclkFreq
- N = ((((Px2 * MemClkPeriod + 3) / 4) + T) * NBPtr->NBClkFreq + 999999) / 1000000;
-
- MemRecNSetBitFieldNb (NBPtr, BFMaxLatency, N);
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Set Dram ODT for mission mode and write leveling mode.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] OdtMode - Mission mode or write leveling mode
- * @param[in] ChipSelect - Chip select number
- * @param[in] TargetCS - Chip select number that is being trained
- *
- */
-
-VOID
-MemRecNSetDramOdtON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN ODT_MODE OdtMode,
- IN UINT8 ChipSelect,
- IN UINT8 TargetCS
- )
-{
- UINT8 Dimms;
- UINT8 DramTerm;
- UINT8 DramTermDyn;
- UINT8 WrLvOdt;
- UINT8 MaxDimmsPerChannel;
-
- Dimms = NBPtr->ChannelPtr->Dimms;
-
- // Dram nominal termination
- if (Dimms == 1) {
- DramTerm = 2; // 120 Ohms
- DramTermDyn = 0; // Disabled
- } else {
- DramTerm = 3; // 40 Ohms
- DramTermDyn = 2; // 120 Ohms
- }
-
- if (OdtMode == WRITE_LEVELING_MODE) {
- if (ChipSelect == TargetCS) {
- DramTerm = DramTermDyn;
-
- MaxDimmsPerChannel = RecGetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, 0, NBPtr->ChannelPtr->ChannelID);
-
- if (MaxDimmsPerChannel == 2) {
- if (Dimms == 2) {
- WrLvOdt = 5;
- } else {
- // Dimms = 1
- if (TargetCS == 0) {
- WrLvOdt = 0xF;
- } else {
- // TargetCS = 2
- WrLvOdt = 4;
- }
- }
- } else {
- WrLvOdt = 1;
- }
- MemRecNSetBitFieldNb (NBPtr, BFWrLvOdt, WrLvOdt);
- }
- }
- MemRecNSetBitFieldNb (NBPtr, BFDramTerm, DramTerm);
- MemRecNSetBitFieldNb (NBPtr, BFDramTermDyn, DramTermDyn);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function programs the memory controller with configuration parameters
- *
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - An Error value lower than AGESA_ERROR may have occurred
- * @return FALSE - An Error value greater than or equal to AGESA_ERROR may have occurred
- */
-
-BOOLEAN
-MemRecNAutoConfigON (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 Dimm;
- UINT8 ChipSel;
- UINT32 CSBase;
- UINT32 NBClkFreq;
- DCT_STRUCT *DCTPtr;
- CH_DEF_STRUCT *ChannelPtr;
-
- DCTPtr = NBPtr->DCTPtr;
- ChannelPtr = NBPtr->ChannelPtr;
-
- // Force NB P-state to NBP0
- F14NbPstateInit (DDR800_FREQUENCY,
- 6,
- 0,
- &NBClkFreq,
- &(NBPtr->MemPtr->StdHeader));
- NBPtr->NBClkFreq = NBClkFreq;
- MemRecNSetBitFieldNb (NBPtr, BFNbPsCtrlDis, 1);
-
- //Prepare variables for future usage.
- for (Dimm = 0; Dimm < 2; Dimm++) {
- if ((ChannelPtr->ChDimmValid & (UINT8) 1 << Dimm) != 0) {
- DCTPtr->Timings.CsPresent |= (UINT16) 1 << (Dimm * 2);
- if (((ChannelPtr->DimmDrPresent & (UINT8) 1 << Dimm) == 0) && ((ChannelPtr->DimmQrPresent & (UINT8) 1 << Dimm) == 0)) {
- continue;
- } else {
- DCTPtr->Timings.CsPresent |= (UINT16) 1 << (Dimm * 2 + 1);
- }
- }
- }
-
- //Temporarily set all CS Base/Limit registers (corresponding to Dimms exist on a channel) with 256MB size for WL training.
- CSBase = 0;
- for (ChipSel = 0; ChipSel < 4; ChipSel++) {
- if (DCTPtr->Timings.CsPresent & (UINT8) 1 << ChipSel) {
-
- CSBase &= (UINT32) ~0x08; //Clear OnDimmMirror bit.
- if (((ChipSel & 1) != 0) && ((ChannelPtr->DimmMirrorPresent & (UINT8) 1 << (ChipSel >> 1)) != 0)) {
- CSBase |= (UINT32) 0x08; //Set OnDimmMirror bit.
- }
- MemRecNSetBitFieldNb (NBPtr, (BFCSBaseAddr0Reg + ChipSel), (CSBase | 0x01));
- CSBase += 0x100000;
- if ((ChipSel & 1) == 0) {
- MemRecNSetBitFieldNb (NBPtr, (BFCSMask0Reg + (ChipSel >> 1)), RECDEF_CSMASK_REG);
- }
- }
- }
- MemRecNSetBitFieldNb (NBPtr, BFDramBaseReg0, RECDEF_DRAM_BASE_REG);
- MemRecNSetBitFieldNb (NBPtr, BFDramLimitReg0, 0x70000);
- MemRecNSetBitFieldNb (NBPtr, BFDramBankAddrReg, 0x00000011);
-
- // Set timing registers
- MemRecNSetBitFieldNb (NBPtr, BFDramTiming0, RECDEF_DRAM_TIMING_0);
- MemRecNSetBitFieldNb (NBPtr, BFDramTiming1, RECDEF_DRAM_TIMING_1);
- MemRecNSetBitFieldNb (NBPtr, BFDramTimingLoReg, RECDEF_DRAM_TIMING_LO);
- MemRecNSetBitFieldNb (NBPtr, BFDramTimingHiReg, RECDEF_DRAM_TIMING_HI);
- MemRecNSetBitFieldNb (NBPtr, BFDramMRSReg, RECDEF_DRAM_MRSREG);
- MemRecNSetBitFieldNb (NBPtr, BFDramControlReg, RECDEF_DRAM_CONTROL_REG);
- // Set DRAM Config Low Register
- MemRecNSetBitFieldNb (NBPtr, BFDramConfigLoReg, RECDEF_DRAM_CONFIG_LO_REG);
-
- // Set DRAM Config High Register
- MemRecNSetBitFieldNb (NBPtr, BFDramConfigHiReg, RECDEF_DRAM_CONFIG_HI_REG);
-
- // DctWrLimit = 0x1F
- MemRecNSetBitFieldNb (NBPtr, BFDctWrLimit, 0x1F);
- // EnCpuSerRdBehindNpIoWr = 1
- MemRecNSetBitFieldNb (NBPtr, BFEnCpuSerRdBehindNpIoWr, 1);
-
- return TRUE;
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/ON/mrnmcton.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/ON/mrnmcton.c
deleted file mode 100644
index df1d5d8..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/ON/mrnmcton.c
+++ /dev/null
@@ -1,191 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrnmcton.c
- *
- * Northbridge ON MCT supporting functions Recovery
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mrport.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mrnon.h"
-#include "Filecode.h"
-#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNMCTON_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function is the Recovery memory configuration function for ON DDR3
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return AGESA_STATUS
- * - AGESA_ALERT
- * - AGESA_FATAL
- * - AGESA_SUCCESS
- * - AGESA_WARNING
- */
-
-AGESA_STATUS
-MemRecNMemInitON (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- AGESA_STATUS Status;
- MEM_TECH_BLOCK *TechPtr;
-
- TechPtr = NBPtr->TechPtr;
-
- Status = AGESA_FATAL;
- if (TechPtr->DimmPresence (TechPtr)) {
-
- if (MemRecNAutoConfigON (NBPtr)) {
-
- AGESA_TESTPOINT (TpProcMemPlatformSpecificConfig, &(NBPtr->MemPtr->StdHeader));
- if (MemRecNPlatformSpecON (NBPtr)) {
- AgesaHookBeforeDramInitRecovery (0, NBPtr->MemPtr);
- AGESA_TESTPOINT (TpProcMemStartDcts, &(NBPtr->MemPtr->StdHeader));
- MemRecNStartupDCTClientNb (NBPtr);
-
- AGESA_TESTPOINT (TpProcMemMtrrConfiguration, &(NBPtr->MemPtr->StdHeader));
- MemRecNCPUMemRecTypingNb (NBPtr);
-
- AGESA_TESTPOINT (TpProcMemDramTraining, &(NBPtr->MemPtr->StdHeader));
- NBPtr->TrainingFlow (NBPtr);
-
- Status = AGESA_SUCCESS;
- }
- }
- }
-
- return Status;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the final values for specific registers
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemRecNFinalizeMctON (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- //
- // Recommended registers setting after DRAM device initialization and training
- //
- // PrefCpuDis = 0
- MemRecNSetBitFieldNb (NBPtr, BFPrefCpuDis, 0);
- // DctWrLimit = 0x1C
- MemRecNSetBitFieldNb (NBPtr, BFDctWrLimit, 0x1C);
- // DramTrainPdbDis = 1
- MemRecNSetBitFieldNb (NBPtr, BFDramTrainPdbDis, 1);
- // EnCpuSerRdBehindNpIoWr = 0
- MemRecNSetBitFieldNb (NBPtr, BFEnCpuSerRdBehindNpIoWr, 0);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets initial values in BUCFG2
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemRecNInitializeMctON (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/ON/mrnon.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/ON/mrnon.c
deleted file mode 100644
index e8a28ed..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/ON/mrnon.c
+++ /dev/null
@@ -1,653 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrnon.c
- *
- * Common Northbridge functions for Ontario Recovery
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 38303 $ @e \$Date: 2010-09-22 00:22:47 +0800 (Wed, 22 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mrport.h"
-#include "cpuFamRegisters.h"
-#include "cpuRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "mm.h"
-#include "mn.h"
-#include "mrnon.h"
-#include "heapManager.h"
-#include "Filecode.h"
-#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-#define SPLIT_CHANNEL 0x20000000
-#define CHANNEL_SELECT 0x10000000
-#define MAX_DELAYS 9 /* 8 data bytes + 1 ECC byte */
-#define MAX_DIMMS 4 /* 4 DIMMs per channel */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-CONST MEM_FREQ_CHANGE_PARAM RecFreqChangeParamON = {0x1838, NULL, 3, 10, 2};
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-VOID
-STATIC
-MemRecNInitNBRegTableON (
- IN OUT TSEFO *NBRegTable
- );
-
-UINT32
-STATIC
-MemRecNCmnGetSetFieldON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN BIT_FIELD_NAME FieldName,
- IN UINT32 Field
- );
-
-UINT32
-STATIC
-MemRecNcmnGetSetTrainDlyON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN TRN_DLY_TYPE TrnDly,
- IN DRBN DrbnVar,
- IN UINT16 Field
- );
-
-BOOLEAN
-STATIC
-MemRecNIsIdSupportedON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN CPU_LOGICAL_ID *LogicalIdPtr
- );
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initializes the northbridge block
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
- * @param[in] NodeID - Node ID for this NB block
- *
- * @return TRUE - This node is a Llano and this NB block has been initialized
- * @return FALSE - This node is not a Llano
- */
-
-BOOLEAN
-MemRecConstructNBBlockON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- )
-{
- UINT8 i;
- DIE_STRUCT *MCTPtr;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
- //
- // Determine if this is the expected NB Type
- //
- GetLogicalIdOfSocket (MemPtr->DiesPerSystem->SocketId, &(MemPtr->DiesPerSystem->LogicalCpuid), &(MemPtr->StdHeader));
- if (!MemRecNIsIdSupportedON (NBPtr, &(MemPtr->DiesPerSystem->LogicalCpuid))) {
- return FALSE;
- }
-
- NBPtr->MemPtr = MemPtr;
- NBPtr->RefPtr = MemPtr->ParameterListPtr;
-
- MCTPtr = MemPtr->DiesPerSystem;
- NBPtr->MCTPtr = MCTPtr;
- NBPtr->MCTPtr->NodeId = 0;
- NBPtr->PciAddr.AddressValue = MCTPtr->PciAddr.AddressValue;
-
- //
- // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
- //
- AllocHeapParams.RequestedBufferSize = (sizeof (DCT_STRUCT) + sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK));
- AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0);
- AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
- if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) {
- ASSERT(FALSE); // Could not allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
- return FALSE;
- }
-
- MemPtr->DieCount = 1;
- MCTPtr->Dct = 0;
- MCTPtr->DctCount = 1;
- MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += sizeof (DCT_STRUCT);
- MCTPtr->DctData->ChannelCount = 1;
- MCTPtr->DctData->ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += sizeof (CH_DEF_STRUCT);
- NBPtr->PSBlock = (MEM_PS_BLOCK *) AllocHeapParams.BufferPtr;
-
- //
- // Initialize NB block's variables
- //
- NBPtr->DCTPtr = NBPtr->MCTPtr->DctData;
- NBPtr->DctCachePtr = NBPtr->DctCache;
- NBPtr->PsPtr = NBPtr->PSBlock;
- NBPtr->ChannelPtr = NBPtr->DCTPtr->ChData;
-
- NBPtr->DctCachePtr = NBPtr->DctCache;
-
- MemRecNInitNBRegTableON (NBPtr->NBRegTable);
- NBPtr->Dct = 0;
- NBPtr->Channel = 0;
- NBPtr->VarMtrrHiMsk = MemRecGetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
- NBPtr->FreqChangeParam = (MEM_FREQ_CHANGE_PARAM *) &RecFreqChangeParamON;
- LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader);
- LibAmdMemFill (NBPtr->IsSupported, FALSE, sizeof (NBPtr->IsSupported), &NBPtr->MemPtr->StdHeader);
- for (i = 0; i < NumberOfHooks; i++) {
- NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) MemRecDefTrue;
- }
-
- NBPtr->InitRecovery = MemRecNMemInitON;
-
- NBPtr->SwitchNodeRec = (VOID (*) (MEM_NB_BLOCK *, UINT8)) MemRecDefRet;
- NBPtr->SwitchDCT = (VOID (*) (MEM_NB_BLOCK *, UINT8)) MemRecDefRet;
- NBPtr->SwitchChannel = (VOID (*) (MEM_NB_BLOCK *, UINT8)) MemRecDefRet;
- NBPtr->SetMaxLatency = MemRecNSetMaxLatencyON;
- NBPtr->GetSysAddrRec = MemRecNGetMCTSysAddrNb;
- NBPtr->SendMrsCmd = MemRecNSendMrsCmdNb;
- NBPtr->sendZQCmd = MemRecNSendZQCmdNb;
- NBPtr->SetDramOdtRec = MemRecNSetDramOdtON;
-
- NBPtr->GetBitField = MemRecNGetBitFieldNb;
- NBPtr->SetBitField = MemRecNSetBitFieldNb;
- NBPtr->GetTrainDly = MemRecNGetTrainDlyNb;
- NBPtr->SetTrainDly = MemRecNSetTrainDlyNb;
-
- NBPtr->MemRecNCmnGetSetFieldNb = MemRecNCmnGetSetFieldON;
- NBPtr->MemRecNcmnGetSetTrainDlyNb = MemRecNcmnGetSetTrainDlyON;
- NBPtr->MemRecNSwitchDctNb = (VOID (*) (MEM_NB_BLOCK *, UINT8)) MemRecDefRet;
- NBPtr->MemRecNInitializeMctNb = MemRecNInitializeMctON;
- NBPtr->MemRecNFinalizeMctNb = MemRecNFinalizeMctON;
- NBPtr->IsSupported[DramModeAfterDimmPres] = TRUE;
- NBPtr->TrainingFlow = MemNRecTrainingFlowClientNb;
- NBPtr->ReadPattern = MemRecNContReadPatternClientNb;
-
- return TRUE;
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function gets or set DQS timing during training.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] TrnDly - type of delay to be set
- * @param[in] DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed
- * (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding
- * @param[in] Field - Value to be programmed
- * @param[in] IsSet - Indicates if the function will set or get
- *
- * @return value read, if the function is used as a "get"
- */
-
-UINT32
-STATIC
-MemRecNcmnGetSetTrainDlyON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN TRN_DLY_TYPE TrnDly,
- IN DRBN DrbnVar,
- IN UINT16 Field
- )
-{
- UINT16 Index;
- UINT16 Offset;
- UINT32 Value;
- UINT32 Address;
- UINT8 Dimm;
- UINT8 Byte;
-
- Dimm = DRBN_DIMM (DrbnVar);
- Byte = DRBN_BYTE (DrbnVar);
-
- ASSERT (Dimm < 1);
- ASSERT (Byte <= 8);
-
- switch (TrnDly) {
- case AccessRcvEnDly:
- Index = 0x10;
- break;
- case AccessWrDqsDly:
- Index = 0x30;
- break;
- case AccessWrDatDly:
- Index = 0x01;
- break;
- case AccessRdDqsDly:
- Index = 0x05;
- break;
- case AccessPhRecDly:
- Index = 0x50;
- break;
- default:
- Index = 0;
- IDS_ERROR_TRAP;
- }
-
- switch (TrnDly) {
- case AccessRcvEnDly:
- case AccessWrDqsDly:
- if ((Byte & 0x04) != 0) {
- // if byte 4,5,6,7
- Index += 0x10;
- }
- if ((Byte & 0x02) != 0) {
- // if byte 2,3,6,7
- Index++;
- }
- Offset = 16 * (Byte % 2);
- break;
-
- case AccessRdDqsDly:
- Field &= ~ 0x0001;
- case AccessWrDatDly:
- Index += (Dimm * 0x100);
- // break is not being used here because AccessRdDqsDly and AccessWrDatDly also need
- // to run AccessPhRecDly sequence.
- case AccessPhRecDly:
- Index += (Byte / 4);
- Offset = 8 * (Byte % 4);
- break;
- default:
- Offset = 0;
- IDS_ERROR_TRAP;
- }
-
- Address = Index;
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
- Value = MemRecNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
-
- if (IsSet != 0) {
- if (TrnDly == AccessPhRecDly) {
- Value = NBPtr->DctCachePtr->PhRecReg[Index & 0x03];
- }
-
- Value = ((UINT32)Field << Offset) | (Value & (~((UINT32)0xFF << Offset)));
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
- Address |= DCT_ACCESS_WRITE;
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
-
- if (TrnDly == AccessPhRecDly) {
- NBPtr->DctCachePtr->PhRecReg[Index & 0x03] = Value;
- }
- } else {
- Value = (Value >> Offset) & 0xFF;
- }
-
- return Value;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function gets or sets a value to a bit field in a PCI register.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] FieldName - Name of Field to be set * @param[in] Field - Value to be programmed
- * @param[in] IsSet - Indicates if the function will set or get
- *
- * @return value read, if the function is used as a "get"
- */
-
-UINT32
-STATIC
-MemRecNCmnGetSetFieldON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN BIT_FIELD_NAME FieldName,
- IN UINT32 Field
- )
-{
- SBDFO Address;
- PCI_ADDR PciAddr;
- UINT8 Type;
- UINT32 Value;
- UINT32 Highbit;
- UINT32 Lowbit;
- UINT32 Mask;
-
- Value = 0;
- if ((FieldName == BFDctAccessDone) || (FieldName == BFDctExtraAccessDone)) {
- Value = 1;
- } else if ((FieldName < BFEndOfList) && (FieldName >= 0)) {
- Address = NBPtr->NBRegTable[FieldName];
- if (Address != 0) {
- Lowbit = TSEFO_END (Address);
- Highbit = TSEFO_START (Address);
- Type = TSEFO_TYPE (Address);
-
- if ((Address >> 29) == ((DCT_PHY_ACCESS << 1) | 1)) {
- // Special DCT Phy access
- Address &= 0x0FFFFFFF;
- Lowbit = 0;
- Highbit = 16;
- } else {
- // Normal DCT Phy access
- Address = TSEFO_OFFSET (Address);
- }
-
-
- if (Type == NB_ACCESS) {
- Address |= (((UINT32) (24 + 0)) << 15);
- PciAddr.AddressValue = Address;
- LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
- } else if (Type == DCT_PHY_ACCESS) {
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
-
- Value = MemRecNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
- } else if (Type == DCT_EXTRA) {
- MemRecNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address);
- Value = MemRecNGetBitFieldNb (NBPtr, BFDctExtraDataReg);
- } else {
- IDS_ERROR_TRAP;
- }
-
- if (IsSet != 0) {
- // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
- if ((Highbit - Lowbit) != 31) {
- Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
- } else {
- Mask = (UINT32)0xFFFFFFFF;
- }
- Value &= ~(Mask << Lowbit);
- Value |= (Field & Mask) << Lowbit;
-
- if (Type == NB_ACCESS) {
- PciAddr.AddressValue = Address;
- LibAmdPciWrite (AccessWidth32, PciAddr , &Value, &NBPtr->MemPtr->StdHeader);
- } else if (Type == DCT_PHY_ACCESS) {
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
- Address |= DCT_ACCESS_WRITE;
-
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
- } else if (Type == DCT_EXTRA) {
- MemRecNSetBitFieldNb (NBPtr, BFDctExtraDataReg, Value);
- Address |= DCT_ACCESS_WRITE;
- MemRecNSetBitFieldNb (NBPtr, BFDctExtraOffsetReg, Address);
- } else {
- IDS_ERROR_TRAP;
- }
- } else {
- Value = Value >> Lowbit; // Shift
- // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
- if ((Highbit - Lowbit) != 31) {
- Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
- }
- }
- }
- } else {
- IDS_ERROR_TRAP; // Invalid bit field index
- }
- return Value;
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initializes bit field translation table
- *
- * @param[in,out] *NBRegTable - Pointer to the NB Table
- *
- */
-
-VOID
-STATIC
-MemRecNInitNBRegTableON (
- IN OUT TSEFO *NBRegTable
- )
-{
- UINT16 i;
- for (i = 0; i <= BFEndOfList; i++) {
- NBRegTable[i] = 0;
- }
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31, 0, BFDevVendorIDReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60), 2, 0, BFNodeID);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31, 0, BFCSBaseAddr0Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31, 0, BFCSBaseAddr1Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31, 0, BFCSBaseAddr2Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31, 0, BFCSBaseAddr3Reg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31, 0, BFCSMask0Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31, 0, BFCSMask1Reg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 0, BFDramControlReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 0, BFDramInitRegReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31, 0, BFDramBankAddrReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31, 0, BFDramMRSReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 9, 7, BFDramTerm);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 11, 10, BFDramTermDyn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 0, BFDramTimingLoReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 0, BFDramTimingHiReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31, 0, BFDramConfigLoReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 0, BFDramConfigHiReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 0, BFDctAddlOffsetReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31, 0, BFDctAddlDataReg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 18, 18, BFDqsRcvEnTrain);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15, 0, BFMrsAddress);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 18, 16, BFMrsBank);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 22, 20, BFMrsChipSel);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 30, 30, BFSendCtrlWord);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 7, 7, BFLevel);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 12, 12, BFMrsQoff);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 0, 0, BFInitDram);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 1, 1, BFExitSelfRef);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 17, 17, BFEnterSelfRef);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 27, 27, BFDisDllShutdownSR);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 4, 0, BFMemClkFreq);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 7, 7, BFMemClkFreqVal);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 8, 8, BFDdr3Mode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 9, 9, BFLegacyBiosMode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 22, 21, BFDbeGskMemClkAlignMode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF0), 31, 0, BFDctExtraOffsetReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xF4), 31, 0, BFDctExtraDataReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 8, 8, BFDramEnabled);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 31, 0, BFDctSelBaseAddrReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 31, 0, BFDctSelBaseOffsetReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 6, 2, BFDctWrLimit);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 12, 12, BFPrefCpuDis);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1C0), 17, 2, BFTrainLength);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1C0), 20, 20, BFDramTrainPdbDis);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1C0), 22, 22, BFRdDramTrainMode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1C0), 23, 23, BFRdTrainGo);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1C8), 31, 0, BFWrTrainAdrPtrLo);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x1D0), 9, 0, BFWrTrainBufAddr);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4), 5, 0, BFMainPllOpFreqId);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xDC), 26, 20, BFNbPs0NclkDiv);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0x188), 22, 22, BFEnCpuSerRdBehindNpIoWr);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (6, 0x90), 30, 30, BFNbPsCtrlDis);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 2, 0, BFCkeDrvStren);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 6, 4, BFCsOdtDrvStren);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 10, 8, BFAddrCmdDrvStren);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 14, 12, BFClkDrvStren);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 18, 16, BFDataDrvStren);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 22, 20, BFDqsDrvStren);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31, 0, BFODCControl);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31, 0, BFAddrTmgControl);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 0, 0, BFWrtLvTrEn);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 1, 1, BFWrtLvTrMode);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 3, 3, BFPhyFenceTrEn);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 4, 4, BFTrDimmSel);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 7, 6, BFFenceTrSel);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11, 8, BFWrLvOdt);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 13, 13, BFDqsRcvTrEn);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 21, 15, BFPllMult);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 27, 24, BFPllDiv);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0B, 31, 0, BFDramPhyStatusReg);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x0C, 20, 16, BFPhyFence);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FE006, 15, 0, BFPllLockTime);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FE013, 15, 0, BFPllRegWaitTime);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F1F, 4, 3, BFDataRxVioLvl);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2F1F, 4, 3, BFClkRxVioLvl);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F4009, 15, 14, BFCmpVioLvl);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8F1F, 4, 3, BFCmdRxVioLvl);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC01F, 4, 3, BFAddrRxVioLvl);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F31, 14, 0, BFDataFence2);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2F31, 4, 0, BFClkFence2);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8F31, 4, 0, BFCmdFence2);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC031, 4, 0, BFAddrFence2);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F0F, 14, 12, BFAlwaysEnDllClks);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FE003, 14, 13, BFDisablePredriverCal);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F02, 15, 0, BFDataByteTxPreDriverCal);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F06, 15, 0, BFDataByteTxPreDriverCal2Pad1);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F0F0A, 15, 0, BFDataByteTxPreDriverCal2Pad2);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8006, 15, 0, BFCmdAddr0TxPreDriverCal2Pad1);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F800A, 15, 0, BFCmdAddr0TxPreDriverCal2Pad2);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8106, 15, 0, BFCmdAddr1TxPreDriverCal2Pad1);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F810A, 15, 0, BFCmdAddr1TxPreDriverCal2Pad2);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC006, 15, 0, BFAddrTxPreDriverCal2Pad1);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC00A, 15, 0, BFAddrTxPreDriverCal2Pad2);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC00E, 15, 0, BFAddrTxPreDriverCal2Pad3);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC012, 15, 0, BFAddrTxPreDriverCal2Pad4);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8002, 15, 0, BFCmdAddr0TxPreDriverCalPad0);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F8102, 15, 0, BFCmdAddr1TxPreDriverCalPad0);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0FC002, 15, 0, BFAddrTxPreDriverCalPad0);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2002, 15, 0, BFClock0TxPreDriverCalPad0);
- MAKE_TSEFO (NBRegTable, DCT_PHY_DIRECT, 0x0D0F2102, 15, 0, BFClock1TxPreDriverCalPad0);
-
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x30, 12, 0, BFDbeGskFifoNumerator);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x31, 12, 0, BFDbeGskFifoDenominator);
-
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x32, 4, 0, BFDataTxFifoSchedDlySlot0);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x32, 7, 7, BFDataTxFifoSchedDlyNegSlot0);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x32, 12, 8, BFDataTxFifoSchedDlySlot1);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x32, 15, 15, BFDataTxFifoSchedDlyNegSlot1);
-
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x40, 31, 0, BFDramTiming0);
- MAKE_TSEFO (NBRegTable, DCT_EXTRA, 0x41, 31, 0, BFDramTiming1);
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- *
- * This function matches the CPU_LOGICAL_ID with certain criteria to
- * determine if it is supported by this NBBlock.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID
- *
- * @return TRUE - This node is a Llano.
- * @return FALSE - This node is not a Llano.
- */
-BOOLEAN
-STATIC
-MemRecNIsIdSupportedON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN CPU_LOGICAL_ID *LogicalIdPtr
- )
-{
- if ((LogicalIdPtr->Family & (AMD_FAMILY_14_ON)) != 0) {
- return TRUE;
- } else {
- return FALSE;
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/ON/mrnon.h b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/ON/mrnon.h
deleted file mode 100644
index aa56148..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/ON/mrnon.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mnon.h
- *
- * Northbridge Ontario Recovery
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MRNON_H_
-#define _MRNON_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-#define _4GB_RJ8 ((UINT32)4 << (30 - 8))
-#define MTRR_VALID 11
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-MemRecConstructNBBlockON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- );
-
-AGESA_STATUS
-MemRecNMemInitON (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemRecNFinalizeMctON (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemRecNInitializeMctON (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemRecNSetMaxLatencyON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT16 MaxRcvEnDly
- );
-
-BOOLEAN
-MemRecNPlatformSpecON (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-MemRecNSetDramOdtON (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN ODT_MODE OdtMode,
- IN UINT8 ChipSelect,
- IN UINT8 TargetCS
- );
-
-BOOLEAN
-MemRecNAutoConfigON (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-#endif /* _MRNON_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/PH/mrnPh.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/PH/mrnPh.c
deleted file mode 100644
index 0552cd5..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/PH/mrnPh.c
+++ /dev/null
@@ -1,652 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrnPh.c
- *
- * Common Northbridge functions for Pharaoh Recovery
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "cpuRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "mrport.h"
-#include "mm.h"
-#include "mn.h"
-#include "mrnda.h"
-#include "mrnPh.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_RECOVERY_MEM_NB_PH_MRNPH_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-#define SPLIT_CHANNEL 0x20000000
-#define CHANNEL_SELECT 0x10000000
-#define MAX_DELAYS 9 /* 8 data bytes + 1 ECC byte */
-#define MAX_DIMMS 4 /* 4 DIMMs per channel */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-VOID
-STATIC
-MemRecNInitNBRegTablePh (
- IN OUT TSEFO *NBRegTable
- );
-
-UINT32
-STATIC
-MemRecNCmnGetSetFieldPh (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN BIT_FIELD_NAME FieldName,
- IN UINT32 Field
- );
-
-UINT32
-STATIC
-MemRecNcmnGetSetTrainDlyPh (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN TRN_DLY_TYPE TrnDly,
- IN DRBN DrbnVar,
- IN UINT16 Field
- );
-
-BOOLEAN
-STATIC
-MemRecNIsIdSupportedPh (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN CPU_LOGICAL_ID *LogicalIdPtr
- );
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initializes the northbridge block
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
- * @param[in] NodeID - Node ID for this NB block
- *
- * @return TRUE - This node is a RB and this NB block has been initialized
- * @return FALSE - This node is not a RB
- */
-
-BOOLEAN
-MemRecConstructNBBlockPh (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- )
-{
- UINT8 i;
- UINT8 Dct;
- UINT8 Channel;
- DIE_STRUCT *MCTPtr;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
- //
- // Determine if this is the expected NB Type
- //
- GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
- if (!MemRecNIsIdSupportedPh (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
- return FALSE;
- }
-
- //
- // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
- //
- MCTPtr = &MemPtr->DiesPerSystem[NodeID];
- AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_DA * (
- sizeof (DCT_STRUCT) + (
- MAX_CHANNELS_PER_DCT_DA * (
- sizeof (CH_DEF_STRUCT) + (
- MAX_DIMMS * MAX_DELAYS * NUMBER_OF_DELAY_TABLES
- )
- )
- )
- );
- AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0);
- AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
- if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) {
- return FALSE;
- }
-
- MemPtr->DieCount = 1;
- MCTPtr->DctCount = MAX_DCTS_PER_NODE_DA;
- MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_DA * sizeof (DCT_STRUCT);
- for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
- MCTPtr->DctData[Dct].Dct = Dct;
- MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_DA;
- MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr;
- MCTPtr->DctData[Dct].ChData[0].ChannelID = Dct;
- AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_DA * sizeof (CH_DEF_STRUCT);
- for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_DA; Channel++) {
- MCTPtr->DctData[Dct].ChData[Channel].RcvEnDlys = (UINT16 *) AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS) * 2;
- MCTPtr->DctData[Dct].ChData[Channel].WrDqsDlys = AllocHeapParams.BufferPtr;
- MCTPtr->DctData[Dct].ChData[Channel].Dct = Dct;
- AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS);
- }
- }
-
- //
- // Initialize NB block's variables
- //
- NBPtr->MemPtr = MemPtr;
- NBPtr->RefPtr = MemPtr->ParameterListPtr;
- NBPtr->MCTPtr = MCTPtr;
- NBPtr->SPDPtr = &MemPtr->SpdDataStructure[MemPtr->DiesPerSystem[NodeID].SocketId * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL];
- NBPtr->AllNodeSPDPtr = &MemPtr->SpdDataStructure[MemPtr->DiesPerSystem[NodeID].SocketId * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL];
-
- NBPtr->DctCachePtr = NBPtr->DctCache;
-
- MemRecNInitNBRegTablePh (NBPtr->NBRegTable);
- NBPtr->Dct = 0;
- NBPtr->Channel = 0;
- NBPtr->VarMtrrHiMsk = MemRecGetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
-
- LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader);
- LibAmdMemFill (NBPtr->IsSupported, FALSE, sizeof (NBPtr->IsSupported), &NBPtr->MemPtr->StdHeader);
- for (i = 0; i < NumberOfHooks; i++) {
- NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) MemRecDefTrue;
- }
-
- NBPtr->InitRecovery = MemRecNMemInitNb;
-
- NBPtr->SwitchNodeRec = (VOID (*) (MEM_NB_BLOCK *, UINT8)) MemRecDefRet;
- NBPtr->SwitchDCT = MemRecNSwitchDctPh;
- NBPtr->SwitchChannel = MemRecNSwitchChannelPh;
- NBPtr->SetMaxLatency = MemRecNSetMaxLatencyNb;
- NBPtr->GetSysAddrRec = MemRecNGetMCTSysAddrNb;
- NBPtr->SendMrsCmd = MemRecNSendMrsCmdNb;
- NBPtr->sendZQCmd = MemRecNSendZQCmdNb;
- NBPtr->SetDramOdtRec = MemRecNSetDramOdtNb;
-
- NBPtr->GetBitField = MemRecNGetBitFieldNb;
- NBPtr->SetBitField = MemRecNSetBitFieldNb;
- NBPtr->GetTrainDly = MemRecNGetTrainDlyNb;
- NBPtr->SetTrainDly = MemRecNSetTrainDlyNb;
- NBPtr->MemRecNCmnGetSetFieldNb = MemRecNCmnGetSetFieldPh;
- NBPtr->MemRecNcmnGetSetTrainDlyNb = MemRecNcmnGetSetTrainDlyPh;
- NBPtr->MemRecNSwitchDctNb = MemRecNSwitchDctPh;
- NBPtr->TrainingFlow = MemNRecTrainingFlowNb;
- NBPtr->MemRecNInitializeMctNb = MemRecNInitializeMctDA;
- NBPtr->MemRecNFinalizeMctNb = MemRecNFinalizeMctDA;
- NBPtr->IsSupported[DramModeBeforeDimmPres] = TRUE;
- NBPtr->IsSupported[CheckClearOnDimmMirror] = TRUE;
- MemRecNSwitchDctPh (NBPtr, 0);
-
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the current DCT to work on.
- * Should be called before accessing a certain DCT
- * All data structures will be updated to point to the current DCT
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Dct - ID of the target DCT
- *
- */
-
-VOID
-MemRecNSwitchDctPh (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Dct
- )
-{
- NBPtr->Dct = Dct & 1;
- NBPtr->SPDPtr = &(NBPtr->AllNodeSPDPtr[Dct * MAX_DIMMS_PER_CHANNEL]);
- NBPtr->DCTPtr = &(NBPtr->MCTPtr->DctData[NBPtr->Dct]);
-
- MemRecNSwitchChannelPh (NBPtr, NBPtr->Channel);
-}
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the current channel to work on.
- * Should be called before accessing a certain channel
- * All data structures will be updated to point to the current channel
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Channel - ID of the target channel
- *
- */
-
-VOID
-MemRecNSwitchChannelPh (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Channel
- )
-{
- NBPtr->Channel = Channel & 1;
- NBPtr->ChannelPtr = &(NBPtr->DCTPtr->ChData[NBPtr->Channel]);
-}
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function gets or set DQS timing during training.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] TrnDly - type of delay to be set
- * @param[in] DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed
- * (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding
- * @param[in] Field - Value to be programmed
- * @param[in] IsSet - Indicates if the function will set or get
- *
- * @return value read, if the function is used as a "get"
- */
-
-UINT32
-STATIC
-MemRecNcmnGetSetTrainDlyPh (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN TRN_DLY_TYPE TrnDly,
- IN DRBN DrbnVar,
- IN UINT16 Field
- )
-{
- UINT16 Index;
- UINT16 Offset;
- UINT32 Value;
- UINT32 Address;
- UINT8 Dimm;
- UINT8 Byte;
-
- Dimm = DRBN_DIMM (DrbnVar);
- Byte = DRBN_BYTE (DrbnVar);
-
- ASSERT (Dimm < 4);
- ASSERT (Byte <= 8);
-
- switch (TrnDly) {
- case AccessRcvEnDly:
- Index = 0x10;
- break;
- case AccessWrDqsDly:
- Index = 0x30;
- break;
- case AccessWrDatDly:
- Index = 0x01;
- break;
- case AccessRdDqsDly:
- Index = 0x05;
- break;
- case AccessPhRecDly:
- Index = 0x50;
- break;
- default:
- Index = 0;
- IDS_ERROR_TRAP;
- }
-
- switch (TrnDly) {
- case AccessRcvEnDly:
- case AccessWrDqsDly:
- Index += (Dimm * 3);
- if (Byte & 0x04) {
- // if byte 4,5,6,7
- Index += 0x10;
- }
- if (Byte & 0x02) {
- // if byte 2,3,6,7
- Index++;
- }
- Offset = 16 * (Byte % 2);
- break;
-
- case AccessRdDqsDly:
- Field &= ~ 0x0001;
- case AccessWrDatDly:
- Index += (Dimm * 0x100);
- // break is not being used here because AccessRdDqsDly and AccessWrDatDly also need
- // to run AccessPhRecDly sequence.
- case AccessPhRecDly:
- Index += (Byte / 4);
- Offset = 8 * (Byte % 4);
- break;
- default:
- Offset = 0;
- IDS_ERROR_TRAP;
- }
-
- Address = Index;
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
- while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
- Value = MemRecNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
-
- if (IsSet) {
- if (TrnDly == AccessPhRecDly) {
- Value = NBPtr->DctCachePtr->PhRecReg[Index & 0x03];
- }
-
- Value = ((UINT32)Field << Offset) | (Value & (~((UINT32)0xFF << Offset)));
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
- Address |= DCT_ACCESS_WRITE;
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
- while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
-
- if (TrnDly == AccessPhRecDly) {
- NBPtr->DctCachePtr->PhRecReg[Index & 0x03] = Value;
- }
- } else {
- Value = (Value >> Offset) & 0xFF;
- }
-
- return Value;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function gets or sets a value to a bit field in a PCI register.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] IsSet - Indicates if the function will set or get
- * @param[in] FieldName - Name of field to be set
- * @param[in] Field - Value to be programmed
- *
- * @return value read, if the function is used as a "get"
- */
-
-UINT32
-STATIC
-MemRecNCmnGetSetFieldPh (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN BIT_FIELD_NAME FieldName,
- IN UINT32 Field
- )
-{
- SBDFO Address;
- PCI_ADDR PciAddr;
- UINT8 Type;
- UINT32 Value;
- UINT32 Highbit;
- UINT32 Lowbit;
- UINT32 Mask;
-
- Value = 0;
- if (FieldName < BFEndOfList) {
- Address = NBPtr->NBRegTable[FieldName];
- if (Address) {
- Lowbit = TSEFO_END (Address);
- Highbit = TSEFO_START (Address);
- Type = TSEFO_TYPE (Address);
-
- // If Fn2 and DCT1 selected, set Address to be 1xx
- if (((Address & 0xF000) == 0x2000) && NBPtr->Dct) {
- Address |= 0x0100;
- }
- if ((Address >> 29) == ((DCT_PHY_ACCESS << 1) | 1)) {
- // Special DCT Phy access
- Address &= 0x0FFFFFFF;
- Lowbit = 0;
- Highbit = 16;
- } else {
- // Normal DCT Phy access
- Address = TSEFO_OFFSET (Address);
- }
-
-
- if (Type == NB_ACCESS) {
- Address |= (((UINT32) (24 + 0)) << 15);
- PciAddr.AddressValue = Address;
- LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
- } else if (Type == DCT_PHY_ACCESS) {
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
- while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
-
- Value = MemRecNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
- } else {
- IDS_ERROR_TRAP;
- }
-
- if (IsSet) {
- // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
- if ((Highbit - Lowbit) != 31) {
- Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
- } else {
- Mask = (UINT32)0xFFFFFFFF;
- }
- Value &= ~(Mask << Lowbit);
- Value |= (Field & Mask) << Lowbit;
-
- if (Type == NB_ACCESS) {
- PciAddr.AddressValue = Address;
- LibAmdPciWrite (AccessWidth32, PciAddr , &Value, &NBPtr->MemPtr->StdHeader);
- } else if (Type == DCT_PHY_ACCESS) {
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
- Address |= DCT_ACCESS_WRITE;
-
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
- while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
- } else {
- IDS_ERROR_TRAP;
- }
- } else {
- Value = Value >> Lowbit; // Shift
- // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
- if ((Highbit - Lowbit) != 31) {
- Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
- }
- }
- }
- } else {
- IDS_ERROR_TRAP; // Invalid bit field index
- }
- return Value;
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initializes bit field translation table
- *
- * @param[in,out] *NBRegTable - Pointer to the NB Table *
- */
-
-VOID
-STATIC
-MemRecNInitNBRegTablePh (
- IN OUT TSEFO *NBRegTable
- )
-{
- UINT16 i;
- for (i = 0; i <= BFEndOfList; i++) {
- NBRegTable[i] = 0;
- }
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31, 0, BFDevVendorIDReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60), 2, 0, BFNodeID);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31, 0, BFCSBaseAddr0Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31, 0, BFCSBaseAddr1Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31, 0, BFCSBaseAddr2Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31, 0, BFCSBaseAddr3Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x50), 31, 0, BFCSBaseAddr4Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x54), 31, 0, BFCSBaseAddr5Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x58), 31, 0, BFCSBaseAddr6Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x5C), 31, 0, BFCSBaseAddr7Reg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31, 0, BFCSMask0Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31, 0, BFCSMask1Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x68), 31, 0, BFCSMask2Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x6C), 31, 0, BFCSMask3Reg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 0, BFDramControlReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 0, BFDramInitRegReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31, 0, BFDramBankAddrReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31, 0, BFDramMRSReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 9, 7, BFDramTerm);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 11, 10, BFDramTermDyn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 0, BFDramTimingLoReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 0, BFDramTimingHiReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31, 0, BFDramConfigLoReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 0, BFDramConfigHiReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 0, BFDctAddlOffsetReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31, 0, BFDctAddlDataReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 31, BFDctAccessDone);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4), 4, 0, BFNbFid);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 18, 18, BFDqsRcvEnTrain);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15, 0, BFMrsAddress);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 18, 16, BFMrsBank);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 22, 20, BFMrsChipSel);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 30, 30, BFSendCtrlWord);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 7, 7, BFLevel);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 12, 12, BFMrsQoff);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 0, 0, BFInitDram);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 16, 16, BFUnBuffDimm);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 8, 8, BFDdr3Mode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 9, 9, BFLegacyBiosMode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 6, 6, BFOdtSwizzle);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 15, 8, BFCtrlWordCS);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 8, 8, BFDramEnabled);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 31, 0, BFDctSelBaseAddrReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 31, 0, BFDctSelBaseOffsetReg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 6, 2, BFMctWrLimit);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 12, 12, BFPrefCpuDis);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 13, 13, BFPrefIoDis);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 29, 29, BFFlushWrOnStpGnt);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31, 0, BFODCControl);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31, 0, BFAddrTmgControl);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 0, 0, BFWrtLvTrEn);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 1, 1, BFWrtLvTrMode);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 5, 4, BFTrDimmSel);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11, 8, BFWrLvOdt);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 30, 30, BFDisAutoComp);
-
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- * MemRecNIsIdSupportedPh
- * This function matches the CPU_LOGICAL_ID with certain criteria to
- * determine if it is supported by this NBBlock.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID
- *
- */
-BOOLEAN
-STATIC
-MemRecNIsIdSupportedPh (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN CPU_LOGICAL_ID *LogicalIdPtr
- )
-{
-
- if ((LogicalIdPtr->Revision & AMD_F10_PH_ALL) != 0) {
- return TRUE;
- } else {
- return FALSE;
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/PH/mrnPh.h b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/PH/mrnPh.h
deleted file mode 100644
index 341b433..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/PH/mrnPh.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrnPh.h
- *
- * Northbridge PH Recovery
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MRNPH_H_
-#define _MRNPH_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-#define _4GB_RJ8 ((UINT32)4 << (30 - 8))
-#define MTRR_VALID 11
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-MemRecConstructNBBlockPh (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- );
-
-VOID
-MemRecNSwitchDctPh (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Dct
- );
-
-VOID
-MemRecNSwitchChannelPh (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Channel
- );
-
-#endif /* _MRNPH_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/RB/mrnRb.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/RB/mrnRb.c
deleted file mode 100644
index 627e5f7..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/RB/mrnRb.c
+++ /dev/null
@@ -1,651 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrnRb.c
- *
- * Common Northbridge functions for RidgeBack Recovery
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "cpuRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "mrport.h"
-#include "mm.h"
-#include "mn.h"
-#include "mrnda.h"
-#include "mrnRb.h"
-#include "heapManager.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_RECOVERY_MEM_NB_RB_MRNRB_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-#define SPLIT_CHANNEL 0x20000000
-#define CHANNEL_SELECT 0x10000000
-#define MAX_DELAYS 9 /* 8 data bytes + 1 ECC byte */
-#define MAX_DIMMS 4 /* 4 DIMMs per channel */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-VOID
-STATIC
-MemRecNInitNBRegTableRb (
- IN OUT TSEFO *NBRegTable
- );
-
-UINT32
-STATIC
-MemRecNCmnGetSetFieldRb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN BIT_FIELD_NAME FieldName,
- IN UINT32 Field
- );
-
-UINT32
-STATIC
-MemRecNcmnGetSetTrainDlyRb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN TRN_DLY_TYPE TrnDly,
- IN DRBN DrbnVar,
- IN UINT16 Field
- );
-
-BOOLEAN
-STATIC
-MemRecNIsIdSupportedRb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN CPU_LOGICAL_ID *LogicalIdPtr
- );
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initializes the northbridge block
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
- * @param[in] NodeID - Node ID for this NB block
- *
- * @return TRUE - This node is a RB and this NB block has been initialized
- * @return FALSE - This node is not a RB
- */
-
-BOOLEAN
-MemRecConstructNBBlockRb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- )
-{
- UINT8 i;
- UINT8 Dct;
- UINT8 Channel;
- DIE_STRUCT *MCTPtr;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
- //
- // Determine if this is the expected NB Type
- //
- GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
- if (!MemRecNIsIdSupportedRb (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) {
- return FALSE;
- }
-
- //
- // Allocate buffer for DCT_STRUCTs and CH_DEF_STRUCTs
- //
- MCTPtr = &MemPtr->DiesPerSystem[NodeID];
- AllocHeapParams.RequestedBufferSize = MAX_DCTS_PER_NODE_DA * (
- sizeof (DCT_STRUCT) + (
- MAX_CHANNELS_PER_DCT_DA * (
- sizeof (CH_DEF_STRUCT) + (
- MAX_DIMMS * MAX_DELAYS * NUMBER_OF_DELAY_TABLES
- )
- )
- )
- );
- AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DCT_STRUCT_HANDLE, NodeID, 0, 0);
- AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
- if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) {
- return FALSE;
- }
-
- MCTPtr->DctCount = MAX_DCTS_PER_NODE_DA;
- MCTPtr->DctData = (DCT_STRUCT *) AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += MAX_DCTS_PER_NODE_DA * sizeof (DCT_STRUCT);
- for (Dct = 0; Dct < MAX_DCTS_PER_NODE_DA; Dct++) {
- MCTPtr->DctData[Dct].Dct = Dct;
- MCTPtr->DctData[Dct].ChannelCount = MAX_CHANNELS_PER_DCT_DA;
- MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) AllocHeapParams.BufferPtr;
- MCTPtr->DctData[Dct].ChData[0].ChannelID = Dct;
- AllocHeapParams.BufferPtr += MAX_CHANNELS_PER_DCT_DA * sizeof (CH_DEF_STRUCT);
- for (Channel = 0; Channel < MAX_CHANNELS_PER_DCT_DA; Channel++) {
- MCTPtr->DctData[Dct].ChData[Channel].RcvEnDlys = (UINT16 *) AllocHeapParams.BufferPtr;
- AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS) * 2;
- MCTPtr->DctData[Dct].ChData[Channel].WrDqsDlys = AllocHeapParams.BufferPtr;
- MCTPtr->DctData[Dct].ChData[Channel].Dct = Dct;
- AllocHeapParams.BufferPtr += (MAX_DIMMS * MAX_DELAYS);
- }
- }
-
- //
- // Initialize NB block's variables
- //
- NBPtr->MemPtr = MemPtr;
- NBPtr->RefPtr = MemPtr->ParameterListPtr;
- NBPtr->MCTPtr = MCTPtr;
- NBPtr->SPDPtr = &MemPtr->SpdDataStructure[MemPtr->DiesPerSystem[NodeID].SocketId * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL];
- NBPtr->AllNodeSPDPtr = &MemPtr->SpdDataStructure[MemPtr->DiesPerSystem[NodeID].SocketId * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL];
-
- NBPtr->DctCachePtr = NBPtr->DctCache;
-
- MemRecNInitNBRegTableRb (NBPtr->NBRegTable);
- NBPtr->Dct = 0;
- NBPtr->Channel = 0;
- NBPtr->VarMtrrHiMsk = MemRecGetVarMtrrHiMsk (&(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader));
-
- LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &NBPtr->MemPtr->StdHeader);
- LibAmdMemFill (NBPtr->IsSupported, FALSE, sizeof (NBPtr->IsSupported), &NBPtr->MemPtr->StdHeader);
- for (i = 0; i < NumberOfHooks; i++) {
- NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) MemRecDefTrue;
- }
-
- NBPtr->InitRecovery = MemRecNMemInitNb;
-
- NBPtr->SwitchNodeRec = (VOID (*) (MEM_NB_BLOCK *, UINT8)) MemRecDefRet;
- NBPtr->SwitchDCT = MemRecNSwitchDctRb;
- NBPtr->SwitchChannel = MemRecNSwitchChannelRb;
- NBPtr->SetMaxLatency = MemRecNSetMaxLatencyNb;
- NBPtr->GetSysAddrRec = MemRecNGetMCTSysAddrNb;
- NBPtr->SendMrsCmd = MemRecNSendMrsCmdNb;
- NBPtr->sendZQCmd = MemRecNSendZQCmdNb;
- NBPtr->SetDramOdtRec = MemRecNSetDramOdtNb;
-
- NBPtr->GetBitField = MemRecNGetBitFieldNb;
- NBPtr->SetBitField = MemRecNSetBitFieldNb;
- NBPtr->GetTrainDly = MemRecNGetTrainDlyNb;
- NBPtr->SetTrainDly = MemRecNSetTrainDlyNb;
- NBPtr->MemRecNCmnGetSetFieldNb = MemRecNCmnGetSetFieldRb;
- NBPtr->MemRecNcmnGetSetTrainDlyNb = MemRecNcmnGetSetTrainDlyRb;
- NBPtr->MemRecNSwitchDctNb = MemRecNSwitchDctRb;
- NBPtr->TrainingFlow = MemNRecTrainingFlowNb;
- NBPtr->MemRecNInitializeMctNb = MemRecNInitializeMctDA;
- NBPtr->MemRecNFinalizeMctNb = MemRecNFinalizeMctDA;
- NBPtr->IsSupported[DramModeBeforeDimmPres] = TRUE;
- NBPtr->IsSupported[CheckClearOnDimmMirror] = TRUE;
- MemRecNSwitchDctRb (NBPtr, 0);
-
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the current DCT to work on.
- * Should be called before accessing a certain DCT
- * All data structures will be updated to point to the current DCT
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Dct - ID of the target DCT
- *
- */
-
-VOID
-MemRecNSwitchDctRb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Dct
- )
-{
- NBPtr->Dct = Dct & 1;
- NBPtr->SPDPtr = &(NBPtr->AllNodeSPDPtr[Dct * MAX_DIMMS_PER_CHANNEL]);
- NBPtr->DCTPtr = &(NBPtr->MCTPtr->DctData[NBPtr->Dct]);
-
- MemRecNSwitchChannelRb (NBPtr, NBPtr->Channel);
-}
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the current channel to work on.
- * Should be called before accessing a certain channel
- * All data structures will be updated to point to the current channel
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] Channel - ID of the target channel
- *
- */
-
-VOID
-MemRecNSwitchChannelRb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Channel
- )
-{
- NBPtr->Channel = Channel & 1;
- NBPtr->ChannelPtr = &(NBPtr->DCTPtr->ChData[NBPtr->Channel]);
-}
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function gets or set DQS timing during training.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] TrnDly - type of delay to be set
- * @param[in] DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed
- * (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding
- * @param[in] Field - Value to be programmed
- * @param[in] IsSet - Indicates if the function will set or get
- *
- * @return value read, if the function is used as a "get"
- */
-
-UINT32
-STATIC
-MemRecNcmnGetSetTrainDlyRb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN TRN_DLY_TYPE TrnDly,
- IN DRBN DrbnVar,
- IN UINT16 Field
- )
-{
- UINT16 Index;
- UINT16 Offset;
- UINT32 Value;
- UINT32 Address;
- UINT8 Dimm;
- UINT8 Byte;
-
- Dimm = DRBN_DIMM (DrbnVar);
- Byte = DRBN_BYTE (DrbnVar);
-
- ASSERT (Dimm < 4);
- ASSERT (Byte <= 8);
-
- switch (TrnDly) {
- case AccessRcvEnDly:
- Index = 0x10;
- break;
- case AccessWrDqsDly:
- Index = 0x30;
- break;
- case AccessWrDatDly:
- Index = 0x01;
- break;
- case AccessRdDqsDly:
- Index = 0x05;
- break;
- case AccessPhRecDly:
- Index = 0x50;
- break;
- default:
- Index = 0;
- IDS_ERROR_TRAP;
- }
-
- switch (TrnDly) {
- case AccessRcvEnDly:
- case AccessWrDqsDly:
- Index += (Dimm * 3);
- if (Byte & 0x04) {
- // if byte 4,5,6,7
- Index += 0x10;
- }
- if (Byte & 0x02) {
- // if byte 2,3,6,7
- Index++;
- }
- Offset = 16 * (Byte % 2);
- break;
-
- case AccessRdDqsDly:
- Field &= ~ 0x0001;
- case AccessWrDatDly:
- Index += (Dimm * 0x100);
- // break is not being used here because AccessRdDqsDly and AccessWrDatDly also need
- // to run AccessPhRecDly sequence.
- case AccessPhRecDly:
- Index += (Byte / 4);
- Offset = 8 * (Byte % 4);
- break;
- default:
- Offset = 0;
- IDS_ERROR_TRAP;
- }
-
- Address = Index;
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
- while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
- Value = MemRecNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
-
- if (IsSet) {
- if (TrnDly == AccessPhRecDly) {
- Value = NBPtr->DctCachePtr->PhRecReg[Index & 0x03];
- }
-
- Value = ((UINT32)Field << Offset) | (Value & (~((UINT32)0xFF << Offset)));
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
- Address |= DCT_ACCESS_WRITE;
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
- while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
-
- if (TrnDly == AccessPhRecDly) {
- NBPtr->DctCachePtr->PhRecReg[Index & 0x03] = Value;
- }
- } else {
- Value = (Value >> Offset) & 0xFF;
- }
-
- return Value;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function gets or sets a value to a bit field in a PCI register.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] IsSet - Indicates if the function will set or get
- * @param[in] FieldName - Name of field to be set
- * @param[in] Field - Value to be programmed
- *
- * @return value read, if the function is used as a "get"
- */
-
-UINT32
-STATIC
-MemRecNCmnGetSetFieldRb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 IsSet,
- IN BIT_FIELD_NAME FieldName,
- IN UINT32 Field
- )
-{
- SBDFO Address;
- PCI_ADDR PciAddr;
- UINT8 Type;
- UINT32 Value;
- UINT32 Highbit;
- UINT32 Lowbit;
- UINT32 Mask;
-
- Value = 0;
- if (FieldName < BFEndOfList) {
- Address = NBPtr->NBRegTable[FieldName];
- if (Address) {
- Lowbit = TSEFO_END (Address);
- Highbit = TSEFO_START (Address);
- Type = TSEFO_TYPE (Address);
-
- // If Fn2 and DCT1 selected, set Address to be 1xx
- if (((Address & 0xF000) == 0x2000) && NBPtr->Dct) {
- Address |= 0x0100;
- }
- if ((Address >> 29) == ((DCT_PHY_ACCESS << 1) | 1)) {
- // Special DCT Phy access
- Address &= 0x0FFFFFFF;
- Lowbit = 0;
- Highbit = 16;
- } else {
- // Normal DCT Phy access
- Address = TSEFO_OFFSET (Address);
- }
-
-
- if (Type == NB_ACCESS) {
- Address |= (((UINT32) (24 + 0)) << 15);
- PciAddr.AddressValue = Address;
- LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader);
- } else if (Type == DCT_PHY_ACCESS) {
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
- while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
-
- Value = MemRecNGetBitFieldNb (NBPtr, BFDctAddlDataReg);
- } else {
- IDS_ERROR_TRAP;
- }
-
- if (IsSet) {
- // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
- if ((Highbit - Lowbit) != 31) {
- Mask = (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
- } else {
- Mask = (UINT32)0xFFFFFFFF;
- }
- Value &= ~(Mask << Lowbit);
- Value |= (Field & Mask) << Lowbit;
-
- if (Type == NB_ACCESS) {
- PciAddr.AddressValue = Address;
- LibAmdPciWrite (AccessWidth32, PciAddr , &Value, &NBPtr->MemPtr->StdHeader);
- } else if (Type == DCT_PHY_ACCESS) {
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value);
- Address |= DCT_ACCESS_WRITE;
-
- MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address);
- while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {}
- } else {
- IDS_ERROR_TRAP;
- }
- } else {
- Value = Value >> Lowbit; // Shift
- // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
- if ((Highbit - Lowbit) != 31) {
- Value &= (((UINT32)1 << (Highbit - Lowbit + 1)) - 1);
- }
- }
- }
- } else {
- IDS_ERROR_TRAP; // Invalid bit field index
- }
- return Value;
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initializes bit field translation table
- *
- * @param[in,out] *NBRegTable - Pointer to the NB Table *
- */
-
-VOID
-STATIC
-MemRecNInitNBRegTableRb (
- IN OUT TSEFO *NBRegTable
- )
-{
- UINT16 i;
- for (i = 0; i <= BFEndOfList; i++) {
- NBRegTable[i] = 0;
- }
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x00), 31, 0, BFDevVendorIDReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (0, 0x60), 2, 0, BFNodeID);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x40), 31, 0, BFDramBaseReg0);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (1, 0x44), 31, 0, BFDramLimitReg0);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x40), 31, 0, BFCSBaseAddr0Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x44), 31, 0, BFCSBaseAddr1Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x48), 31, 0, BFCSBaseAddr2Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x4C), 31, 0, BFCSBaseAddr3Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x50), 31, 0, BFCSBaseAddr4Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x54), 31, 0, BFCSBaseAddr5Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x58), 31, 0, BFCSBaseAddr6Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x5C), 31, 0, BFCSBaseAddr7Reg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x60), 31, 0, BFCSMask0Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x64), 31, 0, BFCSMask1Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x68), 31, 0, BFCSMask2Reg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x6C), 31, 0, BFCSMask3Reg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 0, BFDramControlReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 0, BFDramInitRegReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x80), 31, 0, BFDramBankAddrReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 31, 0, BFDramMRSReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 9, 7, BFDramTerm);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x84), 11, 10, BFDramTermDyn);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x88), 31, 0, BFDramTimingLoReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 31, 0, BFDramTimingHiReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 31, 0, BFDramConfigLoReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 31, 0, BFDramConfigHiReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 0, BFDctAddlOffsetReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x9C), 31, 0, BFDctAddlDataReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x98), 31, 31, BFDctAccessDone);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (3, 0xD4), 4, 0, BFNbFid);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 18, 18, BFDqsRcvEnTrain);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x78), 31, 22, BFMaxLatency);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 15, 0, BFMrsAddress);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 18, 16, BFMrsBank);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 22, 20, BFMrsChipSel);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 26, 26, BFSendMrsCmd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 27, 27, BFDeassertMemRstX);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 28, 28, BFAssertCke);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 29, 29, BFSendZQCmd);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 30, 30, BFSendCtrlWord);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 31, 31, BFEnDramInit);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 7, 7, BFLevel);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x7C), 12, 12, BFMrsQoff);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x8C), 18, 18, BFDisAutoRefresh);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 0, 0, BFInitDram);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x90), 16, 16, BFUnBuffDimm);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 8, 8, BFDdr3Mode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 9, 9, BFLegacyBiosMode);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 11, 10, BFZqcsInterval);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x94), 14, 14, BFDisDramInterface);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 6, 6, BFOdtSwizzle);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0xA8), 15, 8, BFCtrlWordCS);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 8, 8, BFDramEnabled);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x110), 31, 0, BFDctSelBaseAddrReg);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x114), 31, 0, BFDctSelBaseOffsetReg);
-
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 6, 2, BFMctWrLimit);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 12, 12, BFPrefCpuDis);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 13, 13, BFPrefIoDis);
- MAKE_TSEFO (NBRegTable, NB_ACCESS, _FN (2, 0x11C), 29, 29, BFFlushWrOnStpGnt);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x00, 31, 0, BFODCControl);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x04, 31, 0, BFAddrTmgControl);
-
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 0, 0, BFWrtLvTrEn);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 1, 1, BFWrtLvTrMode);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 5, 4, BFTrDimmSel);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 11, 8, BFWrLvOdt);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 12, 12, BFWrLvOdtEn);
- MAKE_TSEFO (NBRegTable, DCT_PHY_ACCESS, 0x08, 30, 30, BFDisAutoComp);
-
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- * MemRecNIsIdSupportedRb
- * This function matches the CPU_LOGICAL_ID with certain criteria to
- * determine if it is supported by this NBBlock.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID
- *
- */
-BOOLEAN
-STATIC
-MemRecNIsIdSupportedRb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN CPU_LOGICAL_ID *LogicalIdPtr
- )
-{
-
- if ((LogicalIdPtr->Revision & AMD_F10_RB_ALL) != 0) {
- return TRUE;
- } else {
- return FALSE;
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/RB/mrnRb.h b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/RB/mrnRb.h
deleted file mode 100644
index 32641d3..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/RB/mrnRb.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrnRb.h
- *
- * Northbridge RB Recovery
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MRNRB_H_
-#define _MRNRB_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-#define _4GB_RJ8 ((UINT32)4 << (30 - 8))
-#define MTRR_VALID 11
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-MemRecConstructNBBlockRb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT MEM_DATA_STRUCT *MemPtr,
- IN UINT8 NodeID
- );
-
-VOID
-MemRecNSwitchDctRb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Dct
- );
-
-VOID
-MemRecNSwitchChannelRb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Channel
- );
-
-#endif /* _MRNRB_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/mrn.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/mrn.c
deleted file mode 100644
index c4baec0..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/mrn.c
+++ /dev/null
@@ -1,190 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrn.c
- *
- * Common Northbridge functions for Recovery
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem/NB)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "cpuRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "mm.h"
-#include "mn.h"
-#include "Filecode.h"
-#define FILECODE PROC_RECOVERY_MEM_NB_MRN_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-#define MAX_DCTS_PER_DIE 2
-#define SPLIT_CHANNEL 0x20000000
-#define CHANNEL_SELECT 0x10000000
-#define MAX_DELAYS 9 /* 8 data bytes + 1 ECC byte */
-#define MAX_DIMMS 4 /* 4 DIMMs per channel */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function gets a bit field from PCI register
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] FieldName - Field name
- *
- * @return Bit field value
- */
-
-UINT32
-MemRecNGetBitFieldNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN BIT_FIELD_NAME FieldName
- )
-{
- return NBPtr->MemRecNCmnGetSetFieldNb (NBPtr, 0, FieldName, 0);
-}
-
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets a bit field from PCI register
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] FieldName - Field name
- * @param[in] Field - Value to be stored in PCT register
- *
- */
-
-VOID
-MemRecNSetBitFieldNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN BIT_FIELD_NAME FieldName,
- IN UINT32 Field
- )
-{
- NBPtr->MemRecNCmnGetSetFieldNb (NBPtr, 1, FieldName, Field);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function gets a delay value a PCI register during training
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] TrnDly - type of delay to be set
- * @param[in] DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed
- * (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding
- *
- * @return Value read
- */
-
-UINT32
-MemRecNGetTrainDlyNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN TRN_DLY_TYPE TrnDly,
- IN DRBN DrbnVar
- )
-{
- return NBPtr->MemRecNcmnGetSetTrainDlyNb (NBPtr, 0, TrnDly, DrbnVar, 0);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function gets a delay value a PCI register during training
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] TrnDly - type of delay to be set
- * @param[in] DrbnVar - encoding of Dimm-Rank-Byte-Nibble to be accessed
- * (use either DIMM_BYTE_ACCESS(dimm,byte) or CS_NBBL_ACCESS(cs,nibble) to use this encoding
- * @param[in] Field - Value to be programmed
- *
- */
-
-VOID
-MemRecNSetTrainDlyNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN TRN_DLY_TYPE TrnDly,
- IN DRBN DrbnVar,
- IN UINT16 Field
- )
-{
- NBPtr->MemRecNcmnGetSetTrainDlyNb (NBPtr, 1, TrnDly, DrbnVar, Field);
-}
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/mrndct.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/mrndct.c
deleted file mode 100644
index 15ccaf3..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/mrndct.c
+++ /dev/null
@@ -1,1502 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrndct.c
- *
- * Northbridge common DCT support for Recovery
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem/NB)
- * @e \$Revision: 38303 $ @e \$Date: 2010-09-22 00:22:47 +0800 (Wed, 22 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "Ids.h"
-#include "mrport.h"
-#include "cpuFamRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mru.h"
-#include "ma.h"
-#include "Filecode.h"
-#define FILECODE PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define RECDEF_DRAM_CONTROL_REG 0x320C2A06
-#define RECDEF_DRAM_MRSREG 0x000400A4
-#define RECDEF_DRAM_TIMING_LO 0x000A0092
-#define RECDEF_DRAM_TIMING_HI 0xB6D218FF
-#define RECDEF_CSMASK_REG 0x00083FE0
-#define RECDEF_DRAM_CONFIG_LO_REG 0x00000000
-#define RECDEF_DRAM_CONFIG_HI_REG 0x1F48010B
-#define RECDEF_DRAM_BASE_REG 0x00000003
-
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-/// Type of an entry for processing phy init compensation for client NB
-typedef struct {
- BIT_FIELD_NAME IndexBitField; ///< Bit field on which the value is decided
- BIT_FIELD_NAME StartTargetBitField; ///< First bit field to be modified
- BIT_FIELD_NAME EndTargetBitField; ///< Last bit field to be modified
- UINT16 ExtraValue; ///< Extra value needed to be written to bit field
- CONST UINT16 (*TxPrePN)[4]; ///< Pointer to slew rate table
-} REC_PHY_COMP_INIT_CLIENTNB;
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-VOID
-STATIC
-MemRecTCtlOnDimmMirrorNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN BOOLEAN SetFlag
- );
-
-VOID
-STATIC
-MemRecNSwapBitsNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-STATIC
-MemRecNProgNbPstateDependentRegClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-STATIC
-MemRecNTrainPhyFenceNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-VOID
-STATIC
-MemRecNInitPhyCompClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function programs the memory controller with configuration parameters
- *
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - An Error value lower than AGESA_ERROR may have occurred
- * @return FALSE - An Error value greater than or equal to AGESA_ERROR may have occurred
- */
-
-BOOLEAN
-MemRecNAutoConfigNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 Dimm;
- UINT8 Dct;
- UINT32 RegValue;
- UINT8 ChipSel;
- UINT32 CSBase;
- DCT_STRUCT *DCTPtr;
- CH_DEF_STRUCT *ChannelPtr;
-
- Dct = NBPtr->Dct;
- DCTPtr = NBPtr->DCTPtr;
- ChannelPtr = NBPtr->ChannelPtr;
-
- //Prepare variables for future usage.
- for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
- if ((ChannelPtr->ChDimmValid & (UINT8) 1 << Dimm) != 0) {
- DCTPtr->Timings.CsPresent |= (UINT16) 1 << (Dimm * 2);
- if (((ChannelPtr->DimmDrPresent & (UINT8) 1 << Dimm) == 0) && ((ChannelPtr->DimmQrPresent & (UINT8) 1 << Dimm) == 0)) {
- continue;
- } else {
- DCTPtr->Timings.CsPresent |= (UINT16) 1 << (Dimm * 2 + 1);
- }
- }
- }
-
- Dimm = NBPtr->DimmToBeUsed;
-
- //Temporarily set all CS Base/Limit registers (corresponding to Dimms exist on a channel) with 256MB size for WL training.
- CSBase = 0;
- for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) {
- if (DCTPtr->Timings.CsPresent & (UINT8) 1 << ChipSel) {
-
- CSBase &= (UINT32) ~0x08; //Clear OnDimmMirror bit.
- if (((ChipSel & 1) != 0) && ((ChannelPtr->DimmMirrorPresent & (UINT8) 1 << (ChipSel >> 1)) != 0)) {
- CSBase |= (UINT32) 0x08; //Set OnDimmMirror bit.
- }
- MemRecNSetBitFieldNb (NBPtr, (BFCSBaseAddr0Reg + ChipSel), (CSBase | 0x01));
- CSBase += 0x100000;
- if ((ChipSel & 1) == 0) {
- MemRecNSetBitFieldNb (NBPtr, (BFCSMask0Reg + (ChipSel >> 1)), RECDEF_CSMASK_REG);
- }
- }
- }
- MemRecNSetBitFieldNb (NBPtr, BFDramBaseReg0, RECDEF_DRAM_BASE_REG);
- MemRecNSetBitFieldNb (NBPtr, BFDramLimitReg0, 0x70000);
-
- // Disable the other DCT
- NBPtr->MemRecNSwitchDctNb (NBPtr, Dct ^ 0x01);
- MemRecNSetBitFieldNb (NBPtr, BFDisDramInterface, 1);
- NBPtr->MemRecNSwitchDctNb (NBPtr, Dct);
- if (Dct != 0) {
- // If DCT 1, set DctSelBase registers
- MemRecNSetBitFieldNb (NBPtr, BFDctSelBaseAddrReg, 0x00000003);
- MemRecNSetBitFieldNb (NBPtr, BFDctSelBaseOffsetReg, 0x00000000);
- }
-
- MemRecNSetBitFieldNb (NBPtr, BFDramBankAddrReg, 0x00001111);
-
- // Set timing registers
- MemRecNSetBitFieldNb (NBPtr, BFDramTimingLoReg, RECDEF_DRAM_TIMING_LO);
- MemRecNSetBitFieldNb (NBPtr, BFDramTimingHiReg, RECDEF_DRAM_TIMING_HI);
- MemRecNSetBitFieldNb (NBPtr, BFDramMRSReg, RECDEF_DRAM_MRSREG);
- MemRecNSetBitFieldNb (NBPtr, BFDramControlReg, RECDEF_DRAM_CONTROL_REG);
-
- // Set DRAM Config Low Register
- RegValue = RECDEF_DRAM_CONFIG_LO_REG;
- // Set x4Dimm based on DIMM type
- if ((NBPtr->ChannelPtr->Dimmx4Present & ((UINT8) 1 << Dimm)) != 0) {
- RegValue |= ((UINT32) 1 << (Dimm + 12));
- }
- // If not registered, set unbuffered DIMM
- if (!(NBPtr->ChannelPtr->RegDimmPresent & ((UINT8) 1 << Dimm))) {
- RegValue |= ((UINT32) 1 << 16);
- }
- MemRecNSetBitFieldNb (NBPtr, BFDramConfigLoReg, RegValue);
-
- // Set DRAM Config High Register
- RegValue = RECDEF_DRAM_CONFIG_HI_REG;
- MemRecNSetBitFieldNb (NBPtr, BFDramConfigHiReg, RegValue);
-
- //======================================================================
- // Build Dram Config Misc Register Value
- //======================================================================
- //
- if ((NBPtr->ChannelPtr->RegDimmPresent != 0) && (NBPtr->ChannelPtr->TechType == DDR3_TECHNOLOGY)) {
- MemRecNSetBitFieldNb (NBPtr, BFSubMemclkRegDly, 1);
- }
- MemRecNSetBitFieldNb (NBPtr, BFOdtSwizzle, 1);
-
- return TRUE;
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function gets platform specific config/timing values from the interface layer and
- * programs them into DCT.
- *
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return TRUE - An Error value lower than AGESA_ERROR may have occurred
- * @return FALSE - An Error value greater than or equal to AGESA_ERROR may have occurred
- */
-
-BOOLEAN
-MemRecNPlatformSpecNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 p;
-
- p = 0;
- for (p = 0; p < MAX_PLATFORM_TYPES; p++) {
- if (NBPtr->MemPtr->GetPlatformCfg[p] (NBPtr->MemPtr, NBPtr->MCTPtr->SocketId, NBPtr->ChannelPtr) == AGESA_SUCCESS) {
- MemRecNSetBitFieldNb (NBPtr, BFODCControl, NBPtr->ChannelPtr->DctOdcCtl);
- MemRecNSetBitFieldNb (NBPtr, BFAddrTmgControl, NBPtr->ChannelPtr->DctAddrTmg);
- return TRUE;
- }
- }
- return FALSE;
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function reads MemClkFreqVal bit to see if the DIMMs are present in this node.
- * If the DIMMs are present then set the DRAM Enable bit for this node.
- *
- * Setting dram init starts up the DCT state machine, initializes the
- * dram devices with MRS commands, and kicks off any
- * HW memory clear process that the chip is capable of. The sooner
- * that dram init is set for all nodes, the faster the memory system
- * initialization can complete. Thus, the init loop is unrolled into
- * two loops so as to start the processes for non BSP nodes sooner.
- * This procedure will not wait for the process to finish. Synchronization is
- * handled elsewhere.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemRecNStartupDCTNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- // 1. Ensure F2x[1, 0]9C_x08[DisAutoComp] = 1.
- // 2. BIOS waits 5 us for the disabling of the compensation engine to complete.
- // ------- Done in InitPhyComp_Nb -------
- //
- MemRecNSetBitFieldNb (NBPtr, BFDisAutoComp, 1);
- MemRecUWait10ns (500, NBPtr->MemPtr);
-
- //MemRecNSetBitFieldNb (NBPtr, BFInitDram, 1); // HW Dram init
- AGESA_TESTPOINT (TpProcMemDramInit, &(NBPtr->MemPtr->StdHeader));
- NBPtr->TechPtr->DramInit (NBPtr->TechPtr);
-
- // 7. Program F2x[1, 0]9C_x08[DisAutoComp] = 0.
- // 8. BIOS must wait 750 us for the phy compensation engine
- // to reinitialize.
- //
- MemRecNSetBitFieldNb (NBPtr, BFDisAutoComp, 0);
- MemRecUWait10ns (75000, NBPtr->MemPtr);
-
- while (MemRecNGetBitFieldNb (NBPtr, BFDramEnabled) == 0);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initializes the DRAM devices on all DCTs at the same time
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemRecNStartupDCTClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- // Program D18F2x[1,0]9C_x0000_000B = 80000000h. #109999.
- MemRecNSetBitFieldNb (NBPtr, BFDramPhyStatusReg, 0x80000000);
-
- // Program D18F2x[1,0]9C_x0D0F_E013[PllRegWaitTime] = 0118h. #193770.
- MemRecNSetBitFieldNb (NBPtr, BFPllRegWaitTime, 0x118);
-
- // Phy Voltage Level Programming
- MemRecNPhyVoltageLevelNb (NBPtr);
-
- // Run frequency change sequence
- MemRecNSetBitFieldNb (NBPtr, BFPllLockTime, NBPtr->FreqChangeParam->PllLockTimeDefault);
- MemRecNSetBitFieldNb (NBPtr, BFMemClkFreq, 6);
- MemRecNProgNbPstateDependentRegClientNb (NBPtr);
- MemRecNSetBitFieldNb (NBPtr, BFMemClkFreqVal, 1);
- MemRecNSetBitFieldNb (NBPtr, BFPllLockTime, 0x000F);
-
- MemRecNSetBitFieldNb (NBPtr, BFDbeGskMemClkAlignMode, 0);
- MemRecNSetBitFieldNb (NBPtr, BFEnDramInit, 1);
-
- // Phy fence programming
- MemRecNPhyFenceTrainingNb (NBPtr);
-
- // Phy Compensation Initialization
- MemRecNInitPhyCompClientNb (NBPtr);
-
- // Run DramInit sequence
- AGESA_TESTPOINT (TpProcMemDramInit, &(NBPtr->MemPtr->StdHeader));
- NBPtr->TechPtr->DramInit (NBPtr->TechPtr);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the maximum round-trip latency in the system from the processor to the DRAM
- * devices and back.
-
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] MaxRcvEnDly - Maximum receiver enable delay value
- *
- */
-
-VOID
-MemRecNSetMaxLatencyNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT16 MaxRcvEnDly
- )
-{
- UINT16 SubTotal;
-
- AGESA_TESTPOINT (TpProcMemRcvrCalcLatency, &(NBPtr->MemPtr->StdHeader));
-
- // Multiply the CAS Latency by two to get a number of 1/2 MEMCLKs UINTs.
- SubTotal = 6 * 2;
-
- // If registered DIMMs are being used then add 1 MEMCLK to the sub-total.
- if (MemRecNGetBitFieldNb (NBPtr, BFUnBuffDimm) == 0) {
- SubTotal += 2;
- }
-
- // if (AddrCmdSetup || CsOdtSetup || CkeSetup) then K := K + 2;
- SubTotal += 2;
-
- // If the F2x[1, 0]78[RdPtrInit] field is 4, 5, 6 or 7 MEMCLKs,
- // then add 4, 3, 2, or 1 MEMCLKs, respectively to the sub-total.
- //
- SubTotal += 8 - 5;
-
- // Add the maximum (worst case) delay value of DqsRcvEnGrossDelay
- // that exists across all DIMMs and byte lanes.
- //
- SubTotal += MaxRcvEnDly >> 5;
-
- // Add 5.5 to the sub-total. 5.5 represents part of the processor
- // specific constant delay value in the DRAM clock domain.
- //
- SubTotal += 5; // add 5.5 1/2MemClk
-
- // Convert the sub-total (in 1/2 MEMCLKs) to northbridge clocks (NCLKs)
- // as follows (assuming DDR400 and assuming that no P-state or link speed
- // changes have occurred).
- //
- // Simplified formula:
- // SubTotal *= (Fn2xD4[NBFid]+4)/4
- //
- SubTotal = SubTotal * ((UINT16) MemRecNGetBitFieldNb (NBPtr, BFNbFid) + 4);
- SubTotal /= 4;
-
- // Add 5 NCLKs to the sub-total. 5 represents part of the processor
- // specific constant value in the northbridge clock domain.
- //
- SubTotal += 5;
-
- // Program the F2x[1, 0]78[MaxRdLatency] register with the total delay value
- MemRecNSetBitFieldNb (NBPtr, BFMaxLatency, SubTotal);
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Set Dram ODT for mission mode and write leveling mode.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] OdtMode - Mission mode or write leveling mode
- * @param[in] ChipSelect - Chip select number
- * @param[in] TargetCS - Chip select number that is being trained
- *
- */
-
-VOID
-MemRecNSetDramOdtNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN ODT_MODE OdtMode,
- IN UINT8 ChipSelect,
- IN UINT8 TargetCS
- )
-{
- UINT8 DramTerm;
- UINT8 DramTermDyn;
-
- DramTerm = NBPtr->ChannelPtr->Reserved[0];
- DramTermDyn = NBPtr->ChannelPtr->Reserved[1];
-
- if (OdtMode == WRITE_LEVELING_MODE) {
- if (ChipSelect == TargetCS) {
- DramTerm = DramTermDyn;
- MemRecNSetBitFieldNb (NBPtr, BFWrLvOdt, NBPtr->ChannelPtr->PhyWLODT[TargetCS >> 1]);
- }
- }
- MemRecNSetBitFieldNb (NBPtr, BFDramTerm, DramTerm);
- MemRecNSetBitFieldNb (NBPtr, BFDramTermDyn, DramTermDyn);
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sends an MRS command
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemRecNSendMrsCmdNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- BOOLEAN ClearODM;
- ClearODM = FALSE;
- if (NBPtr->IsSupported[CheckClearOnDimmMirror]) {
- ClearODM = FALSE;
- if ((NBPtr->MCTPtr->LogicalCpuid.Revision & AMD_F10_C0) != 0) {
- if (NBPtr->IsSupported[CheckClearOnDimmMirror]) {
- if (MemRecNGetBitFieldNb (NBPtr, BFEnDramInit) == 0) {
- // For C0, if EnDramInit bit is cleared, ODM needs to be cleared before sending MRS
- MemRecTCtlOnDimmMirrorNb (NBPtr, FALSE);
- ClearODM = TRUE;
- }
- }
- }
- }
-
- MemRecNSwapBitsNb (NBPtr);
-
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tCS%d MR%d %04x\n",
- (MemRecNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 20) & 0xF,
- (MemRecNGetBitFieldNb (NBPtr, BFDramInitRegReg) >> 16) & 0xF,
- (MemRecNGetBitFieldNb (NBPtr, BFDramInitRegReg) & 0xFFFF));
-
- // 1.Set SendMrsCmd=1
- MemRecNSetBitFieldNb (NBPtr, BFSendMrsCmd, 1);
-
- // 2.Wait for SendMrsCmd=0
- while (MemRecNGetBitFieldNb (NBPtr, BFSendMrsCmd)) {}
-
- if (NBPtr->IsSupported[CheckClearOnDimmMirror]) {
- if (ClearODM) {
- // Restore ODM if necessary
- MemRecTCtlOnDimmMirrorNb (NBPtr, TRUE);
- }
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sends the ZQCL command
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemRecNSendZQCmdNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- // 1.Program MrsAddress[10]=1
- MemRecNSetBitFieldNb (NBPtr, BFMrsAddress, (UINT32) 1 << 10);
-
- // 2.Set SendZQCmd=1
- MemRecNSetBitFieldNb (NBPtr, BFSendZQCmd, 1);
-
- // 3.Wait for SendZQCmd=0
- while (MemRecNGetBitFieldNb (NBPtr, BFSendZQCmd)) {}
-
- // 4.Wait 512 MEMCLKs
- MemRecUWait10ns (128, NBPtr->MemPtr); // 512*2.5ns=1280, wait 1280ns
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function disables/enables F2x[1, 0][5C:40][OnDimmMirror]
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] SetFlag - Enable or disable flag - TRUE - Enable, FALSE - DISABLE
- *
- */
-
-VOID
-STATIC
-MemRecTCtlOnDimmMirrorNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN BOOLEAN SetFlag
- )
-{
- UINT8 Chipsel;
- UINT32 CSBaseAddrReg;
-
- for (Chipsel = 0; Chipsel < MAX_CS_PER_CHANNEL; Chipsel += 2) {
- CSBaseAddrReg = MemRecNGetBitFieldNb (NBPtr, BFCSBaseAddr1Reg + Chipsel);
- if ((CSBaseAddrReg & 1) == 1) {
- if (SetFlag && ((NBPtr->ChannelPtr->DimmMirrorPresent & ((UINT8) 1 << (Chipsel >> 1))) != 0)) {
- CSBaseAddrReg |= ((UINT32) 1 << BFOnDimmMirror);
- } else {
- CSBaseAddrReg &= ~((UINT32) 1 << BFOnDimmMirror);
- }
- MemRecNSetBitFieldNb (NBPtr, BFCSBaseAddr1Reg + Chipsel, CSBaseAddrReg);
- }
- }
-}
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function swaps bits for OnDimmMirror support
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-STATIC
-MemRecNSwapBitsNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 ChipSel;
- UINT32 MRSReg;
-
- ChipSel = (UINT8) MemRecNGetBitFieldNb (NBPtr, BFMrsChipSel);
- if ((ChipSel & 1) != 0) {
- MRSReg = MemRecNGetBitFieldNb (NBPtr, BFDramInitRegReg);
- if ((NBPtr->ChannelPtr->DimmMirrorPresent & (UINT8) 1 << (ChipSel >> 1)) != 0) {
- MRSReg = (MRSReg & 0xFFFCFE07) | ((MRSReg&0x100A8) << 1) | ((MRSReg&0x20150) >> 1);
- MemRecNSetBitFieldNb (NBPtr, BFDramInitRegReg, MRSReg);
- }
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function gets the total of sync components for Max Read Latency calculation
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return Total in 1/2 MEMCLKs
- */
-
-UINT32
-MemRecNTotalSyncComponentsClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT32 T;
- UINT32 P;
- UINT32 AddrTmgCtl;
- UINT32 MemClkPeriod;
-
- AGESA_TESTPOINT (TpProcMemRcvrCalcLatency , &(NBPtr->MemPtr->StdHeader));
-
- // Before calculating MaxRdLatecny, program a number of registers.
- MemRecNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 1);
- MemRecNSetBitFieldNb (NBPtr, BFEnterSelfRef, 1);
- while (MemRecNGetBitFieldNb (NBPtr, BFEnterSelfRef) != 0) {}
- MemRecNSetBitFieldNb (NBPtr, BFDbeGskMemClkAlignMode, 2);
- MemRecNSetBitFieldNb (NBPtr, BFExitSelfRef, 1);
- while (MemRecNGetBitFieldNb (NBPtr, BFExitSelfRef) != 0) {}
- MemRecNSetBitFieldNb (NBPtr, BFDisDllShutdownSR, 0);
-
- // P = P + ((16 + RdPtrInitMin - D18F2x[1,0]78[RdPtrInit]) MOD 16) where RdPtrInitMin = RdPtrInit
- P = 0;
-
- AddrTmgCtl = MemRecNGetBitFieldNb (NBPtr, BFAddrTmgControl);
- if (((AddrTmgCtl >> 16) & 0x20) != (AddrTmgCtl & 0x20)) {
- P += 1;
- }
-
- // IF (DbeGskMemClkAlignMode==01b || (DbeGskMemClkAlignMode==00b && !(AddrCmdSetup==CsOdtSetup==CkeSetup)))
- // THEN P = P + 1
-
- // IF (SlowAccessMode==1) THEN P = P + 2
-
- // T = T + (0.5 * MemClkPeriod) - 786 ps
- MemClkPeriod = 1000000 / DDR800_FREQUENCY;
- T = MemClkPeriod / 2 - 768;
-
- // If (AddrCmdSetup==0 && CsOdtSetup==0 && CkeSetup==0)
- // then P = P + 1
- // else P = P + 2
- if ((AddrTmgCtl & 0x0202020) == 0) {
- P += 1;
- } else {
- P += 2;
- }
-
- // P = P + (2 * (D18F2x[1,0]88[Tcl] clocks - 1))
- P += 2 * 5; // Tcl = 6 clocks
-
- // (DisCutThroughMode = 0), so P = P + 3
- P += 3;
-
- return ((P * MemClkPeriod + 1) / 2) + T;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function programs the phy registers according to the desired phy VDDIO voltage level
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemRecNPhyVoltageLevelNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- BIT_FIELD_NAME BitField;
- UINT16 Value;
- UINT16 Mask;
-
- Mask = 0xFFE7;
- Value = (UINT16) NBPtr->RefPtr->DDR3Voltage << 3;
-
- for (BitField = BFDataRxVioLvl; BitField <= BFCmpVioLvl; BitField++) {
- if (BitField == BFCmpVioLvl) {
- Mask = 0x3FFF;
- Value <<= (14 - 3);
- }
- MemRecNSetBitFieldNb (NBPtr, BitField, ((MemRecNGetBitFieldNb (NBPtr, BitField) & Mask)) | Value);
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function executes prototypical Phy fence training function.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemRecNPhyFenceTrainingNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 FenceThresholdTxDll;
- UINT8 FenceThresholdRxDll;
- UINT8 FenceThresholdTxPad;
- UINT16 Fence2Data;
-
- // 1. Program D18F2x[1,0]9C_x0000_0008[FenceTrSel]=10b.
- // 2. Perform phy fence training. See 2.10.3.2.3.1 [Phy Fence Training].
- // 3. Write the calculated fence value to D18F2x[1,0]9C_x0000_000C[FenceThresholdTxDll].
- MemRecNSetBitFieldNb (NBPtr, BFFenceTrSel, 2);
- MAKE_TSEFO (NBPtr->NBRegTable, DCT_PHY_ACCESS, 0x0C, 30, 26, BFPhyFence);
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\tFenceThresholdTxDll\n");
- MemRecNTrainPhyFenceNb (NBPtr);
- FenceThresholdTxDll = (UINT8) MemRecNGetBitFieldNb (NBPtr, BFPhyFence);
-
- // 4. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]0F[AlwaysEnDllClks]=001b.
- MemRecNSetBitFieldNb (NBPtr, BFAlwaysEnDllClks, 0x1000);
-
- // 5. Program D18F2x[1,0]9C_x0000_0008[FenceTrSel]=01b.
- // 6. Perform phy fence training. See 2.10.3.2.3.1 [Phy Fence Training].
- // 7. Write the calculated fence value to D18F2x[1,0]9C_x0000_000C[FenceThresholdRxDll].
- MemRecNSetBitFieldNb (NBPtr, BFFenceTrSel, 1);
- MAKE_TSEFO (NBPtr->NBRegTable, DCT_PHY_ACCESS, 0x0C, 25, 21, BFPhyFence);
- IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tFenceThresholdRxDll\n");
- MemRecNTrainPhyFenceNb (NBPtr);
- FenceThresholdRxDll = (UINT8) MemRecNGetBitFieldNb (NBPtr, BFPhyFence);
-
- // 8. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]0F[AlwaysEnDllClks]=000b.
- MemRecNSetBitFieldNb (NBPtr, BFAlwaysEnDllClks, 0x0000);
-
- // 9. Program D18F2x[1,0]9C_x0000_0008[FenceTrSel]=11b.
- // 10. Perform phy fence training. See 2.10.3.2.3.1 [Phy Fence Training].
- // 11. Write the calculated fence value to D18F2x[1,0]9C_x0000_000C[FenceThresholdTxPad].
- MemRecNSetBitFieldNb (NBPtr, BFFenceTrSel, 3);
- MAKE_TSEFO (NBPtr->NBRegTable, DCT_PHY_ACCESS, 0x0C, 20, 16, BFPhyFence);
- IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tFenceThresholdTxPad\n");
- MemRecNTrainPhyFenceNb (NBPtr);
- FenceThresholdTxPad = (UINT8) MemRecNGetBitFieldNb (NBPtr, BFPhyFence);
-
- // Program Fence2 threshold for Clk, Cmd, and Addr
- if (FenceThresholdTxPad < 16) {
- MemRecNSetBitFieldNb (NBPtr, BFClkFence2, FenceThresholdTxPad | 0x10);
- MemRecNSetBitFieldNb (NBPtr, BFCmdFence2, FenceThresholdTxPad | 0x10);
- MemRecNSetBitFieldNb (NBPtr, BFAddrFence2, FenceThresholdTxPad | 0x10);
- } else {
- MemRecNSetBitFieldNb (NBPtr, BFClkFence2, 0);
- MemRecNSetBitFieldNb (NBPtr, BFCmdFence2, 0);
- MemRecNSetBitFieldNb (NBPtr, BFAddrFence2, 0);
- }
-
- // Program Fence2 threshold for data
- Fence2Data = 0;
- if (FenceThresholdTxPad < 16) {
- Fence2Data |= FenceThresholdTxPad | 0x10;
- }
- if (FenceThresholdRxDll < 16) {
- Fence2Data |= (FenceThresholdRxDll | 0x10) << 10;
- }
- if (FenceThresholdTxDll < 16) {
- Fence2Data |= (FenceThresholdTxDll | 0x10) << 5;
- }
- MemRecNSetBitFieldNb (NBPtr, BFDataFence2, Fence2Data);
-
- // Reprogram F2x9C_04.
- MemRecNSetBitFieldNb (NBPtr, BFAddrTmgControl, MemRecNGetBitFieldNb (NBPtr, BFAddrTmgControl));
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function executes Phy fence training
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-STATIC
-MemRecNTrainPhyFenceNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 Byte;
- UINT16 Avg;
- UINT8 PREvalue;
-
- if (MemRecNGetBitFieldNb (NBPtr, BFDisDramInterface)) {
- return;
- }
-
- // 1. BIOS first programs a seed value to the phase recovery
- // engine registers.
- //
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\tSeeds: ");
- for (Byte = 0; Byte < 9; Byte++) {
- // This includes ECC as byte 8
- MemRecNSetTrainDlyNb (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (0, Byte), 19);
- IDS_HDT_CONSOLE (MEM_FLOW, "%02x ", 19);
- }
-
- IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\tPhyFenceTrEn = 1");
- // 2. Set F2x[1, 0]9C_x08[PhyFenceTrEn]=1.
- MemRecNSetBitFieldNb (NBPtr, BFPhyFenceTrEn, 1);
-
- MemRecUWait10ns (5000, NBPtr->MemPtr);
-
- // 4. Clear F2x[1, 0]9C_x08[PhyFenceTrEn]=0.
- MemRecNSetBitFieldNb (NBPtr, BFPhyFenceTrEn, 0);
-
- // 5. BIOS reads the phase recovery engine registers
- // F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52.
- // 6. Calculate the average value of the fine delay and subtract 8.
- //
- Avg = 0;
- for (Byte = 0; Byte < 9; Byte++) {
- // This includes ECC as byte 8
- PREvalue = (UINT8) (0x1F & MemRecNGetTrainDlyNb (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (0, Byte)));
- Avg = Avg + ((UINT16) PREvalue);
- }
- Avg = ((Avg + 8) / 9); // round up
- Avg -= 6;
-
- // 7. Write the value to F2x[1, 0]9C_x0C[PhyFence].
- MemRecNSetBitFieldNb (NBPtr, BFPhyFence, Avg);
-
- // 8. BIOS rewrites F2x[1, 0]9C_x04, DRAM Address/Command Timing Control
- // Register delays for both channels. This forces the phy to recompute
- // the fence.
- //
- MemRecNSetBitFieldNb (NBPtr, BFAddrTmgControl, MemRecNGetBitFieldNb (NBPtr, BFAddrTmgControl));
-}
-
-/* -----------------------------------------------------------------------------*/
-CONST UINT16 RecPllDivTab[10] = {1, 2, 4, 8, 16, 128, 256, 1, 3, 6};
-
-/**
- *
- * This function calculates and programs NB P-state dependent registers
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-STATIC
-MemRecNProgNbPstateDependentRegClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 i;
- UINT8 NclkFid;
- UINT16 MemClkDid;
- UINT8 PllMult;
- UINT8 NclkDiv;
- UINT32 NclkPeriod;
- UINT32 MemClkPeriod;
- INT32 PartialSum2x;
- INT32 PartialSumSlotI2x;
-
- NclkFid = (UINT8) (MemRecNGetBitFieldNb (NBPtr, BFMainPllOpFreqId) + 0x10);
- MemClkDid = RecPllDivTab[MemRecNGetBitFieldNb (NBPtr, BFPllDiv)];
- PllMult = (UINT8) MemRecNGetBitFieldNb (NBPtr, BFPllMult);
- NclkDiv = (UINT8) MemRecNGetBitFieldNb (NBPtr, BFNbPs0NclkDiv);
-
- NclkPeriod = (2500 * NclkDiv) / NclkFid;
- MemClkPeriod = 1000000 / DDR800_FREQUENCY;
-
- // Program D18F2x[1,0]F4_x30[DbeGskFifoNumerator] and D18F2x[1,0]F4_x31[DbeGskFifoDenominator].
- MemRecNSetBitFieldNb (NBPtr, BFDbeGskFifoNumerator, NclkFid * MemClkDid * 16);
- MemRecNSetBitFieldNb (NBPtr, BFDbeGskFifoDenominator, PllMult * NclkDiv);
-
- // Program D18F2x[1,0]F4_x32[DataTxFifoSchedDlyNegSlot1, DataTxFifoSchedDlySlot1,
- // DataTxFifoSchedDlyNegSlot0, DataTxFifoSchedDlySlot0].
- // PartialSum = ((7 * NclkPeriod) + (1.5 * MemClkPeriod) + 520ps)*MemClkFrequency - tCWL -
- // CmdSetup - PtrSeparation - 1. (Llano)
- // PartialSum = ((5 * NclkPeriod) + MemClkPeriod) + 520ps)*MemClkFrequency - tCWL -
- // CmdSetup - PtrSeparation - 1. (Ontario)
- PartialSum2x = NBPtr->FreqChangeParam->NclkPeriodMul2x * NclkPeriod;
- PartialSum2x += NBPtr->FreqChangeParam->MemClkPeriodMul2x * MemClkPeriod;
- PartialSum2x += 520 * 2;
- PartialSum2x = (PartialSum2x + MemClkPeriod - 1) / MemClkPeriod; // round-up here
- PartialSum2x -= 2 * 5; //Tcwl + 5
- if ((MemRecNGetBitFieldNb (NBPtr, BFAddrTmgControl) & 0x0202020) == 0) {
- PartialSum2x -= 1;
- } else {
- PartialSum2x -= 2;
- }
- // ((16 + RdPtrInitMin - D18F2x78[RdPtrInit]) MOD 16)/2 where RdPtrInitMin = RdPtrInit
- PartialSum2x -= 0;
- PartialSum2x -= 2;
-
- // If PartialSumSlotN is positive:
- // DataTxFifoSchedDlySlotN=CEIL(PartialSumSlotN).
- // DataTxFifoSchedDlyNegSlotN=0.
- // Else if PartialSumSlotN is negative:
- // DataTxFifoSchedDlySlotN=ABS(CEIL(PartialSumSlotN*MemClkPeriod/NclkPeriod)).
- // DataTxFifoSchedDlyNegSlotN=1.
- for (i = 0; i < 2; i++) {
- PartialSumSlotI2x = PartialSum2x;
- PartialSumSlotI2x += 2;
- if (PartialSumSlotI2x > 0) {
- MemRecNSetBitFieldNb (NBPtr, BFDataTxFifoSchedDlyNegSlot0 + i, 0);
- MemRecNSetBitFieldNb (NBPtr, BFDataTxFifoSchedDlySlot0 + i, (PartialSumSlotI2x + 1) / 2);
- } else {
- MemRecNSetBitFieldNb (NBPtr, BFDataTxFifoSchedDlyNegSlot0 + i, 1);
- PartialSumSlotI2x = ((-PartialSumSlotI2x) * MemClkPeriod) / (2 * NclkPeriod);
- MemRecNSetBitFieldNb (NBPtr, BFDataTxFifoSchedDlySlot0 + i, PartialSumSlotI2x);
- }
- }
- // Program ProcOdtAdv
- MemRecNSetBitFieldNb (NBPtr, BFProcOdtAdv, 0);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function reads cache lines continuously using TCB CPG engine
- *
- * @param[in,out] NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] Buffer - Array of bytes to be filled with data read from DRAM
- * @param[in] Address - System Address [47:16]
- * @param[in] ClCount - Number of cache lines
- *
- */
-
-VOID
-MemRecNContReadPatternClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN UINT8 Buffer[],
- IN UINT32 Address,
- IN UINT16 ClCount
- )
-{
- // 1. Program D18F2x1C0[RdDramTrainMode]=1.
- MemRecNSetBitFieldNb (NBPtr, BFRdDramTrainMode, 1);
-
- // 2. Program D18F2x1C0[TrainLength] to the appropriate number of cache lines.
- MemRecNSetBitFieldNb (NBPtr, BFTrainLength, ClCount);
-
- // 3. Program the DRAM training address as follows:
- MemRecNSetBitFieldNb (NBPtr, BFWrTrainAdrPtrLo, (Address >> 6));
-
- // 4. Program D18F2x1D0[WrTrainBufAddr]=000h
- MemRecNSetBitFieldNb (NBPtr, BFWrTrainBufAddr, 0);
-
- // 5. Program D18F2x1C0[RdTrainGo]=1.
- MemRecNSetBitFieldNb (NBPtr, BFRdTrainGo, 1);
-
- // 6. Wait for D18F2x1C0[RdTrainGo]=0.
- while (MemRecNGetBitFieldNb (NBPtr, BFRdTrainGo) != 0) {}
-
- // 7. Read D18F2x1E8[TrainCmpSts] and D18F2x1E8[TrainCmpSts2].
-
- // 8. Program D18F2x1C0[RdDramTrainMode]=0.
- MemRecNSetBitFieldNb (NBPtr, BFRdDramTrainMode, 0);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for the systems with UDIMMs configuration
- *
- * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE
- * @param[in] SocketID Socket number
- * @param[in] *CurrentChannel Pointer to CH_DEF_STRUCT
- *
- * @return AGESA_SUCCESS
- * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel
- * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel
- * @return CurrentChannel->Reserved[0] Dram Term for specified channel
- * @return CurrentChannel->Reserved[1] Dynamic Dram Term for specified channel
- * @return CurrentChannel->PhyWLODT[0] WL ODT for DIMM0
- * @return CurrentChannel->PhyWLODT[1] WL ODT for DIMM1
- * @return CurrentChannel->PhyWLODT[2] WL ODT for DIMM2
- * @return CurrentChannel->PhyWLODT[3] WL ODT for DIMM3
- *
- */
-AGESA_STATUS
-MemRecNGetPsCfgUDIMM3Nb (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- )
-{
- UINT32 AddrTmgCTL;
- UINT32 DctOdcCtl;
- UINT8 Dimms;
- UINT8 MaxDimmPerCH;
- UINT8 DramTerm;
- UINT8 DramTermDyn;
-
- if ((CurrentChannel->RegDimmPresent != 0) || (CurrentChannel->SODimmPresent != 0)) {
- return AGESA_UNSUPPORTED;
- }
-
- Dimms = CurrentChannel->Dimms;
- MaxDimmPerCH = RecGetMaxDimmsPerChannel (MemData->ParameterListPtr->PlatformMemoryConfiguration, 0, CurrentChannel->ChannelID);
-
- if (MaxDimmPerCH == 1) {
- return AGESA_UNSUPPORTED;
- } else {
- DctOdcCtl = 0x20223323;
- AddrTmgCTL = 0x00390039;
- if (Dimms == 1) {
- DctOdcCtl = 0x20113222;
- AddrTmgCTL = 0x00390039;
- if (CurrentChannel->Loads == 16) {
- AddrTmgCTL = 0x003B0000;
- }
- }
- }
- CurrentChannel->DctAddrTmg = AddrTmgCTL;
- CurrentChannel->DctOdcCtl = DctOdcCtl;
-
- // ODT
- if (Dimms == 1) {
- DramTerm = 1; // 60 ohms
- DramTermDyn = 0; // Disable
- if ((MaxDimmPerCH == 3) && (CurrentChannel->DimmDrPresent != 0)) {
- DramTermDyn = 1; // 60 ohms
- }
- } else {
- DramTerm = 3; // 40 ohms
- DramTermDyn = 2; // 120 ohms
- }
- CurrentChannel->Reserved[0] = DramTerm;
- CurrentChannel->Reserved[1] = DramTermDyn;
-
- // WL ODT
- if (Dimms == 1) {
- CurrentChannel->PhyWLODT[0] = 0;
- CurrentChannel->PhyWLODT[1] = (CurrentChannel->DimmDrPresent != 0) ? 8 : 2;
- } else {
- CurrentChannel->PhyWLODT[0] = 3;
- CurrentChannel->PhyWLODT[1] = 3;
- }
- CurrentChannel->PhyWLODT[2] = 0;
- CurrentChannel->PhyWLODT[3] = 0;
-
- return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for the systems with SODIMMs configuration
- *
- * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE
- * @param[in] SocketID Socket number
- * @param[in] *CurrentChannel Pointer to CH_DEF_STRUCT
- *
- * @return AGESA_SUCCESS
- * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel
- * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel
- * @return CurrentChannel->Reserved[0] Dram Term for specified channel
- * @return CurrentChannel->Reserved[1] Dynamic Dram Term for specified channel
- * @return CurrentChannel->PhyWLODT[0] WL ODT for DIMM0
- * @return CurrentChannel->PhyWLODT[1] WL ODT for DIMM1
- * @return CurrentChannel->PhyWLODT[2] WL ODT for DIMM2
- * @return CurrentChannel->PhyWLODT[3] WL ODT for DIMM3
- *
- */
-AGESA_STATUS
-MemRecNGetPsCfgSODIMM3Nb (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- )
-{
- UINT32 AddrTmgCTL;
- UINT32 DctOdcCtl;
- UINT8 MaxDimmPerCH;
- UINT8 Dimms;
- UINT8 DramTerm;
- UINT8 DramTermDyn;
-
- if (CurrentChannel->SODimmPresent != CurrentChannel->ChDimmValid) {
- return AGESA_UNSUPPORTED;
- }
-
- Dimms = CurrentChannel->Dimms;
- MaxDimmPerCH = RecGetMaxDimmsPerChannel (MemData->ParameterListPtr->PlatformMemoryConfiguration, 0, CurrentChannel->ChannelID);
-
- if (MaxDimmPerCH == 1) {
- DctOdcCtl = 0x00113222;
- AddrTmgCTL = 0;
- } else {
- DctOdcCtl = 0x00223323;
- AddrTmgCTL = 0x00000039;
- if (Dimms == 1) {
- DctOdcCtl = 0x00113222;
- AddrTmgCTL = 0;
- }
- }
- CurrentChannel->DctAddrTmg = AddrTmgCTL;
- CurrentChannel->DctOdcCtl = DctOdcCtl;
-
- // ODT
- if (Dimms == 1) {
- DramTerm = 2; // 120 ohms
- DramTermDyn = 0; // Disable
- if (MaxDimmPerCH == 2) {
- DramTerm = 1; // 60 ohms
- }
- } else {
- DramTerm = 3; // 40 ohms
- DramTermDyn = 2; // 120 ohms
- }
- CurrentChannel->Reserved[0] = DramTerm;
- CurrentChannel->Reserved[1] = DramTermDyn;
-
- // WL ODT
- if (Dimms == 1) {
- if (MaxDimmPerCH == 1) {
- CurrentChannel->PhyWLODT[0] = (CurrentChannel->DimmDrPresent != 0) ? 4 : 1;
- CurrentChannel->PhyWLODT[1] = 0;
- } else {
- CurrentChannel->PhyWLODT[0] = 0;
- CurrentChannel->PhyWLODT[1] = (CurrentChannel->DimmDrPresent != 0) ? 8 : 2;
- }
- } else {
- CurrentChannel->PhyWLODT[0] = 3;
- CurrentChannel->PhyWLODT[1] = 3;
- }
- CurrentChannel->PhyWLODT[2] = 0;
- CurrentChannel->PhyWLODT[3] = 0;
-
- return AGESA_SUCCESS;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is function sets the platform specific settings for the systems with RDIMMs configuration
- *
- * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE
- * @param[in] SocketID Socket number
- * @param[in] *CurrentChannel Pointer to CH_DEF_STRUCT
- *
- * @return AGESA_SUCCESS
- * @return CurrentChannel->DctAddrTmg Address Command Timing Settings for specified channel
- * @return CurrentChannel->DctOdcCtl Drive Strength settings for specified channel
- * @return CurrentChannel->Reserved[0] Dram Term for specified channel
- * @return CurrentChannel->Reserved[1] Dynamic Dram Term for specified channel
- * @return CurrentChannel->PhyWLODT[0] WL ODT for DIMM0
- * @return CurrentChannel->PhyWLODT[1] WL ODT for DIMM1
- * @return CurrentChannel->PhyWLODT[2] WL ODT for DIMM2
- * @return CurrentChannel->PhyWLODT[3] WL ODT for DIMM3
- *
- */
-
-AGESA_STATUS
-MemRecNGetPsCfgRDIMM3Nb (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- )
-{
- STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY RecPSCfg2DIMMsWlODT[] = {
- {SR_DIMM0, {0x01, 0x00, 0x00, 0x00}, 1},
- {DR_DIMM0, {0x04, 0x00, 0x00, 0x00}, 1},
- {QR_DIMM0, {0x05, 0x00, 0x00, 0x00}, 1},
- {SR_DIMM1, {0x00, 0x02, 0x00, 0x00}, 1},
- {DR_DIMM1, {0x00, 0x08, 0x00, 0x00}, 1},
- {QR_DIMM1, {0x00, 0x0A, 0x00, 0x00}, 1},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1, {0x03, 0x03, 0x00, 0x00}, 2},
- {SR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2},
- {DR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2},
- {QR_DIMM0 + SR_DIMM1, {0x03, 0x07, 0x06, 0x00}, 2},
- {QR_DIMM0 + DR_DIMM1, {0x03, 0x07, 0x06, 0x00}, 2},
- {QR_DIMM0 + QR_DIMM1, {0x0B, 0x07, 0x0E, 0x0D}, 2}
- };
- STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY RecPSCfg3DIMMsWlODT[] = {
- {SR_DIMM2 + DR_DIMM2, {0x00, 0x00, 0x04, 0x00}, 1},
- {SR_DIMM0 + DR_DIMM0, {0x01, 0x02, 0x00, 0x00}, 1},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM2 + DR_DIMM2, {0x05, 0x00, 0x05, 0x00}, 2},
- {SR_DIMM0 + DR_DIMM0 + SR_DIMM1 + DR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x07, 0x07, 0x07, 0x00}, 3},
- {QR_DIMM1, {0x00, 0x0A, 0x00, 0x0A}, 1},
- {QR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x00, 0x06, 0x0E, 0x0C}, 2},
- {SR_DIMM0 + DR_DIMM0 + QR_DIMM1, {0x0B, 0x03, 0x00, 0x09}, 2},
- {SR_DIMM0 + DR_DIMM0 + QR_DIMM1 + SR_DIMM2 + DR_DIMM2, {0x0F, 0x07, 0x0F, 0x0D}, 3}
- };
- STATIC CONST ADV_R_PSCFG_WL_ODT_ENTRY RecPSCfg4DIMMsWlODT[] = {
- {ANY_DIMM3, {0x00, 0x00, 0x00, 0x08}, 1},
- {ANY_DIMM2 + ANY_DIMM3, {0x00, 0x00, 0x0C, 0x0C}, 2},
- {ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, {0x00, 0x0E, 0x0E, 0x0E}, 3},
- {ANY_DIMM0 + ANY_DIMM1 + ANY_DIMM2 + ANY_DIMM3, {0x0F, 0x0F, 0x0F, 0x0F}, 4}
- };
-
- UINT8 i;
- UINT8 j;
- UINT8 Dimms;
- UINT8 DimmQrPresent;
- UINT32 AddrTmgCTL;
- UINT32 DctOdcCtl;
- UINT8 PhyWLODT[4];
- UINT8 DramTerm;
- UINT8 DramTermDyn;
- UINT16 DIMMRankType;
- UINT16 _DIMMRankType_;
- UINT8 DimmTpMatch;
- UINT8 MaxDimmPerCH;
- UINT8 PSCfgWlODTSize;
- CONST ADV_R_PSCFG_WL_ODT_ENTRY *PSCfgWlODTPtr;
-
- if (CurrentChannel->RegDimmPresent != CurrentChannel->ChDimmValid) {
- return AGESA_UNSUPPORTED;
- }
-
- DIMMRankType = MemRecNGetPsRankType (CurrentChannel);
- MaxDimmPerCH = RecGetMaxDimmsPerChannel (MemData->ParameterListPtr->PlatformMemoryConfiguration, 0, CurrentChannel->ChannelID);
- Dimms = CurrentChannel->Dimms;
- PSCfgWlODTPtr = RecPSCfg2DIMMsWlODT;
- PSCfgWlODTSize = GET_SIZE_OF (RecPSCfg2DIMMsWlODT);
- PhyWLODT[0] = PhyWLODT[1] = PhyWLODT[2] = PhyWLODT[3] = 0xFF;
- DimmQrPresent = CurrentChannel->DimmQrPresent;
-
- if (MaxDimmPerCH == 4) {
- AddrTmgCTL = (Dimms > 2) ? 0x002F0000 : 0;
- DctOdcCtl = (Dimms == 1) ? 0x20113222 : 0x20223222;
- PSCfgWlODTPtr = RecPSCfg4DIMMsWlODT;
- PSCfgWlODTSize = GET_SIZE_OF (RecPSCfg4DIMMsWlODT);
- } else if (MaxDimmPerCH == 3) {
- AddrTmgCTL = 0;
- DctOdcCtl = 0x20223222;
- if (Dimms == 3) {
- AddrTmgCTL = 0x00380038;
- DctOdcCtl = 0x20113222;
- }
- if (Dimms == 1) {
- DctOdcCtl = 0x20113222;
- }
- PSCfgWlODTPtr = RecPSCfg3DIMMsWlODT;
- PSCfgWlODTSize = GET_SIZE_OF (RecPSCfg3DIMMsWlODT);
- } else if (MaxDimmPerCH == 2) {
- AddrTmgCTL = 0;
- DctOdcCtl = 0x20223222;
- if ((Dimms == 1) && (DimmQrPresent == 0)) {
- DctOdcCtl = 0x20113222;
- }
- } else {
- AddrTmgCTL = 0;
- DctOdcCtl = (DimmQrPresent == 0) ? 0x20113222 : 0x20223222;
- }
- CurrentChannel->DctAddrTmg = AddrTmgCTL;
- CurrentChannel->DctOdcCtl = DctOdcCtl;
-
- // ODT
- if (Dimms == 1) {
- DramTerm = 1; // 60 ohms
- DramTermDyn = 0; // Disable
- if (DimmQrPresent != 0) {
- DramTermDyn = 2; // 120 ohms
- }
- } else {
- DramTerm = 3; // 40 ohms
- DramTermDyn = 2; // 120 ohms
- if (DimmQrPresent != 0) {
- DramTerm = 1; // 60 ohms
- }
- }
- CurrentChannel->Reserved[0] = DramTerm;
- CurrentChannel->Reserved[1] = DramTermDyn;
-
- // WL ODT
- for (i = 0; i < PSCfgWlODTSize; i++, PSCfgWlODTPtr++) {
- if (Dimms != PSCfgWlODTPtr->Dimms) {
- continue;
- }
- DimmTpMatch = 0;
- _DIMMRankType_ = DIMMRankType & PSCfgWlODTPtr->DIMMRankType;
- for (j = 0; j < MAX_DIMMS_PER_CHANNEL; j++) {
- if ((_DIMMRankType_ & (UINT16) 0x0F << (j << 2)) != 0) {
- DimmTpMatch++;
- }
- }
- if (DimmTpMatch == PSCfgWlODTPtr->Dimms) {
- PhyWLODT[0] = PSCfgWlODTPtr->PhyWrLvOdt[0];
- PhyWLODT[1] = PSCfgWlODTPtr->PhyWrLvOdt[1];
- PhyWLODT[2] = PSCfgWlODTPtr->PhyWrLvOdt[2];
- PhyWLODT[3] = PSCfgWlODTPtr->PhyWrLvOdt[3];
- break;
- }
- }
- CurrentChannel->PhyWLODT[0] = PhyWLODT[0];
- CurrentChannel->PhyWLODT[1] = PhyWLODT[1];
- CurrentChannel->PhyWLODT[2] = PhyWLODT[2];
- CurrentChannel->PhyWLODT[3] = PhyWLODT[3];
-
- return AGESA_SUCCESS;
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function returns the max dimms for a given memory channel on a given
- * processor. It first searches the platform override table for the max dimms
- * value. If it is not provided, the AGESA default value is returned. The target
- * socket must be a valid present socket.
- *
- * @param[in] PlatformMemoryConfiguration - Platform config table
- * @param[in] SocketID - ID of the processor that owns the channel
- * @param[in] ChannelID - Channel to get max dimms for
- *
- *
- * @return UINT8 - Max Number of Dimms for that channel
- */
-UINT8
-RecGetMaxDimmsPerChannel (
- IN PSO_TABLE *PlatformMemoryConfiguration,
- IN UINT8 SocketID,
- IN UINT8 ChannelID
- )
-{
- UINT8 *DimmsPerChPtr;
- UINT8 MaxDimmPerCH;
-
- DimmsPerChPtr = MemRecFindPSOverrideEntry (PlatformMemoryConfiguration, PSO_MAX_DIMMS, SocketID, ChannelID);
- if (DimmsPerChPtr != NULL) {
- MaxDimmPerCH = *DimmsPerChPtr;
- } else {
- MaxDimmPerCH = 2;
- }
-
- return MaxDimmPerCH;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is the default return function of the ARDK block. The function always
- * returns AGESA_UNSUPPORTED
- *
- * @param[in,out] *MemData Pointer to MEM_DATA_STRUCTURE
- * @param[in] SocketID Socket number
- * @param[in] *CurrentChannel Pointer to CH_DEF_STRUCT
- *
- * @return AGESA_UNSUPPORTED AGESA status indicating that default is unsupported
- *
- */
-
-AGESA_STATUS
-MemRecNGetPsCfgDef (
- IN OUT MEM_DATA_STRUCT *MemData,
- IN UINT8 SocketID,
- IN OUT CH_DEF_STRUCT *CurrentChannel
- )
-{
- return AGESA_UNSUPPORTED;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function returns the rank type map of a channel.
- *
- * @param[in] *CurrentChannel Pointer to CH_DEF_STRUCT
- *
- * @return UINT16 - The map of rank type.
- *
- */
-UINT16
-MemRecNGetPsRankType (
- IN CH_DEF_STRUCT *CurrentChannel
- )
-{
- UINT8 i;
- UINT16 DIMMRankType;
-
- DIMMRankType = 0;
- for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) {
- if ((CurrentChannel->DimmQrPresent & (UINT8) 1 << i) != 0) {
- if (i < 2) {
- DIMMRankType |= (UINT16) 4 << (i << 2);
- }
- } else if ((CurrentChannel->DimmDrPresent & (UINT8) 1 << i) != 0) {
- DIMMRankType |= (UINT16) 2 << (i << 2);
- } else if ((CurrentChannel->DimmSRPresent & (UINT8) 1 << i) != 0) {
- DIMMRankType |= (UINT16) 1 << (i << 2);
- }
- }
- return DIMMRankType;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- *
- * This function initializes the DDR phy compensation logic
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-STATIC
-MemRecNInitPhyCompClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- // Slew rate table array [x]
- // array[0]: slew rate for VDDIO 1.5V
- // array[1]: slew rate for VDDIO 1.35V
- CONST STATIC UINT16 RecTxPrePNDataDqs[2][4] = {
- //{TxPreP, TxPreN}[VDDIO][Drive Strength]
- {0x924, 0x924, 0x924, 0x924},
- {0xFF6, 0xB6D, 0xB6D, 0x924}
- };
-
- CONST STATIC UINT16 RecTxPrePNCmdAddr[2][4] = {
- //{TxPreP, TxPreN}[VDDIO][Drive Strength]
- {0x492, 0x492, 0x492, 0x492},
- {0x492, 0x492, 0x492, 0x492}
- };
- CONST STATIC UINT16 RecTxPrePNClock[2][4] = {
- //{TxPreP, TxPreN}[VDDIO][Drive Strength]
- {0x924, 0x924, 0x924, 0x924},
- {0xDAD, 0xDAD, 0x924, 0x924}
- };
-
- //
- // Tables to describe the relationship between drive strength bit fields, PreDriver Calibration bit fields and also
- // the extra value that needs to be written to specific PreDriver bit fields
- //
- CONST REC_PHY_COMP_INIT_CLIENTNB RecPhyCompInitBitField[] = {
- // 3. Program TxPreP/TxPreN for Data and DQS according toTable 14 if VDDIO is 1.5V or Table 15 if 1.35V.
- // A. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]0[A,6]={0000b, TxPreP, TxPreN}.
- // B. Program D18F2x[1,0]9C_x0D0F_0[F,7:0]02={1000b, TxPreP, TxPreN}.
- {BFDqsDrvStren, BFDataByteTxPreDriverCal2Pad1, BFDataByteTxPreDriverCal2Pad1, 0, RecTxPrePNDataDqs},
- {BFDataDrvStren, BFDataByteTxPreDriverCal2Pad2, BFDataByteTxPreDriverCal2Pad2, 0, RecTxPrePNDataDqs},
- {BFDataDrvStren, BFDataByteTxPreDriverCal, BFDataByteTxPreDriverCal, 8, RecTxPrePNDataDqs},
- // 4. Program TxPreP/TxPreN for Cmd/Addr according toTable 16 if VDDIO is 1.5V or Table 17 if 1.35V.
- // A. Program D18F2x[1,0]9C_x0D0F_[C,8][1:0][12,0E,0A,06]={0000b, TxPreP, TxPreN}.
- // B. Program D18F2x[1,0]9C_x0D0F_[C,8][1:0]02={1000b, TxPreP, TxPreN}.
- {BFCsOdtDrvStren, BFCmdAddr0TxPreDriverCal2Pad1, BFCmdAddr0TxPreDriverCal2Pad2, 0, RecTxPrePNCmdAddr},
- {BFAddrCmdDrvStren, BFCmdAddr1TxPreDriverCal2Pad1, BFAddrTxPreDriverCal2Pad4, 0, RecTxPrePNCmdAddr},
- {BFCsOdtDrvStren, BFCmdAddr0TxPreDriverCalPad0, BFCmdAddr0TxPreDriverCalPad0, 8, RecTxPrePNCmdAddr},
- {BFCkeDrvStren, BFAddrTxPreDriverCalPad0, BFAddrTxPreDriverCalPad0, 8, RecTxPrePNCmdAddr},
- {BFAddrCmdDrvStren, BFCmdAddr1TxPreDriverCalPad0, BFCmdAddr1TxPreDriverCalPad0, 8, RecTxPrePNCmdAddr},
- // 5. Program TxPreP/TxPreN for Clock according toTable 18 if VDDIO is 1.5V or Table 19 if 1.35V.
- // A. Program D18F2x[1,0]9C_x0D0F_2[1:0]02={1000b, TxPreP, TxPreN}.
- {BFClkDrvStren, BFClock0TxPreDriverCalPad0, BFClock1TxPreDriverCalPad0, 8, RecTxPrePNClock}
- };
-
- BIT_FIELD_NAME CurrentBitField;
- CONST UINT16 *TxPrePNArray;
- UINT8 Voltage;
- UINT8 CurDct;
- UINT8 i;
- UINT8 j;
-
- CurDct = NBPtr->Dct;
- NBPtr->SwitchDCT (NBPtr, 0);
- // 1. Program D18F2x[1,0]9C_x0D0F_E003[DisAutoComp, DisalbePredriverCal]={1b, 1b}
- MemRecNSetBitFieldNb (NBPtr, BFDisablePredriverCal, 0x6000);
-
- NBPtr->SwitchDCT (NBPtr, CurDct);
-
- Voltage = (UINT8) NBPtr->RefPtr->DDR3Voltage;
-
- for (j = 0; j < GET_SIZE_OF (RecPhyCompInitBitField); j ++) {
- i = (UINT8) MemRecNGetBitFieldNb (NBPtr, RecPhyCompInitBitField[j].IndexBitField);
- TxPrePNArray = RecPhyCompInitBitField[j].TxPrePN[Voltage];
- for (CurrentBitField = RecPhyCompInitBitField[j].StartTargetBitField; CurrentBitField <= RecPhyCompInitBitField[j].EndTargetBitField; CurrentBitField ++) {
- MemRecNSetBitFieldNb (NBPtr, CurrentBitField, ((RecPhyCompInitBitField[j].ExtraValue << 12) | TxPrePNArray[i]));
- }
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/mrnmct.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/mrnmct.c
deleted file mode 100644
index 75156e7..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/mrnmct.c
+++ /dev/null
@@ -1,298 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrnmct.c
- *
- * Northbridge Common MCT supporting functions Recovery
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem/NB)
- * @e \$Revision: 38303 $ @e \$Date: 2010-09-22 00:22:47 +0800 (Wed, 22 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mrport.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuCacheInit.h"
-#include "Filecode.h"
-#define FILECODE PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function is the Recovery memory configuration function for Nb DDR3
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- * @return AGESA_STATUS
- * - AGESA_ALERT
- * - AGESA_FATAL
- * - AGESA_SUCCESS
- * - AGESA_WARNING
- */
-
-AGESA_STATUS
-MemRecNMemInitNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- AGESA_STATUS Status;
- MEM_TECH_BLOCK *TechPtr;
-
- TechPtr = NBPtr->TechPtr;
-
- NBPtr->MemRecNInitializeMctNb (NBPtr);
-
- if (NBPtr->IsSupported[DramModeBeforeDimmPres]) {
- TechPtr->SetDramMode (TechPtr);
- }
-
- Status = AGESA_FATAL;
- if (TechPtr->DimmPresence (TechPtr)) {
-
- if (NBPtr->IsSupported[DramModeAfterDimmPres]) {
- TechPtr->SetDramMode (TechPtr);
- }
-
- if (MemRecNAutoConfigNb (NBPtr)) {
-
- AGESA_TESTPOINT (TpProcMemPlatformSpecificConfig, &(NBPtr->MemPtr->StdHeader));
- if (MemRecNPlatformSpecNb (NBPtr)) {
- AgesaHookBeforeDramInitRecovery (0, NBPtr->MemPtr);
- AGESA_TESTPOINT (TpProcMemStartDcts, &(NBPtr->MemPtr->StdHeader));
- MemRecNStartupDCTNb (NBPtr);
-
- AGESA_TESTPOINT (TpProcMemMtrrConfiguration, &(NBPtr->MemPtr->StdHeader));
- MemRecNCPUMemRecTypingNb (NBPtr);
-
- AGESA_TESTPOINT (TpProcMemDramTraining, &(NBPtr->MemPtr->StdHeader));
- NBPtr->TrainingFlow (NBPtr);
-
- Status = AGESA_SUCCESS;
- }
- }
- }
-
- NBPtr->MemRecNFinalizeMctNb (NBPtr);
-
- return Status;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function returns a physical address of a corresponding Chip select
- *
- * @return Addr - System Address
- */
-
-UINT32
-MemRecNGetMCTSysAddrNb (
- )
-{
- UINT32 CSBase;
-
- CSBase = (UINT32) 1 << 21; // 1MB offset to avoid compat area from the base address.
- if ((CSBase >= (MCT_TRNG_KEEPOUT_START << 8)) && (CSBase <= (MCT_TRNG_KEEPOUT_END << 8))) {
- CSBase += (((MCT_TRNG_KEEPOUT_END << 8) - CSBase) + 0x0FFFFF) & 0xFFF00000;
- }
-
- return CSBase;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function runs on the BSP only, it sets the fixed MTRRs for common legacy ranges.
- * It sets TOP_MEM and TOM2 and some variable MTRRs with WB Uncacheable type.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- *
- */
-
-VOID
-MemRecNCPUMemRecTypingNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- S_UINT64 SMsr;
-
- MEM_DATA_STRUCT *MemPtr;
- MemPtr = NBPtr->MemPtr;
-
- //
- //======================================================================
- // Set default values for CPU registers
- //======================================================================
- //
-
- LibAmdMsrRead (SYS_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- SMsr.lo |= 0x1C0000; // turn on modification enable bit and
- // mtrr enable bits
- LibAmdMsrWrite (SYS_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-
- SMsr.lo = SMsr.hi = 0x1E1E1E1E;
- LibAmdMsrWrite (0x250, (UINT64 *)&SMsr, &MemPtr->StdHeader); // 0 - 512K = WB Mem
- LibAmdMsrWrite (0x258, (UINT64 *)&SMsr, &MemPtr->StdHeader); // 512K - 640K = WB Mem
-
- LibAmdMsrRead (SYS_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- SMsr.lo &= 0xFFF7FFFF; // turn off modification enable bit
- LibAmdMsrWrite (SYS_CFG, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- //
- //======================================================================
- // Set TOP_MEM and TOM2 CPU registers
- //======================================================================
- //
- SMsr.hi = 0;
- SMsr.lo = 0x08000000;
- LibAmdMsrWrite (TOP_MEM, (UINT64 *)&SMsr, &MemPtr->StdHeader); // TOP_MEM
-
- // Set FS Base address for later memory accesses
- SMsr.lo = 0;
- LibAmdMsrWrite (FS_BASE, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-
- //
- //======================================================================
- // Set variable MTRR values
- //======================================================================
- //
- SMsr.lo = 0x00000006;
- LibAmdMsrWrite (0x200, (UINT64 *)&SMsr, &MemPtr->StdHeader); // MTRRPhysBase0
-
- SMsr.hi = NBPtr->VarMtrrHiMsk;
- SMsr.lo = 0xF8000800;
- LibAmdMsrWrite (0x201, (UINT64 *)&SMsr, &MemPtr->StdHeader); // MTRRPhysMask0
-
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- *
- * This function returns the upper 32 bits mask for variable MTRR based on
- * the CPU_LOGICAL_ID.
- * @param[in] *LogicalIdPtr - Pointer to the CPU_LOGICAL_ID
- * @param[in] StdHeader - Header for library and services
- *
- * @return UINT32 - MTRR mask for upper 32 bits
- *
- */
-UINT32
-MemRecGetVarMtrrHiMsk (
- IN CPU_LOGICAL_ID *LogicalIdPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 TempNotCare;
- CPU_SPECIFIC_SERVICES *FamilySpecificServices;
- CACHE_INFO *CacheInfoPtr;
-
- GetCpuServicesFromLogicalId (LogicalIdPtr, &FamilySpecificServices, StdHeader);
- FamilySpecificServices->GetCacheInfo (FamilySpecificServices, &CacheInfoPtr, &TempNotCare, StdHeader);
- return (UINT32) (CacheInfoPtr->VariableMtrrMask >> 32);
-}
-
-/*-----------------------------------------------------------------------------
- *
- *
- * This function re-enable phy compensation.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] OptParam - Optional parameter
- *
- * @return TRUE
- * ----------------------------------------------------------------------------
- */
-BOOLEAN
-MemRecNReEnablePhyCompNb (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN OUT VOID *OptParam
- )
-{
- UINT8 Dct;
-
- Dct = NBPtr->Dct;
-
- NBPtr->SwitchDCT (NBPtr, 0);
- // Clear DisableCal and set DisablePredriverCal
- MemRecNSetBitFieldNb (NBPtr, BFDisablePredriverCal, 0x2000);
- NBPtr->SwitchDCT (NBPtr, Dct);
-
- return TRUE;
-}
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/mrntrain3.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/mrntrain3.c
deleted file mode 100644
index 7a35921..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/NB/mrntrain3.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrntrain3.c
- *
- * Common Recovery Northbridge function for training flow for DDR3
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/NB)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mrport.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mrt3.h"
-#include "Filecode.h"
-#define FILECODE PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE
-/* features */
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the training control flow
- * The DDR3 mode bit must be set prior to calling this function
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- */
-VOID
-MemNRecTrainingFlowNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MemRecTTrainDQSWriteHw3 (NBPtr->TechPtr);
-
- MemRecTTrainRcvrEnSw (NBPtr->TechPtr);
-
- MemRecTTrainDQSPosSw (NBPtr->TechPtr);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the client training control flow
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- */
-VOID
-MemNRecTrainingFlowClientNb (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- MemRecTTrainDQSWriteHw3 (NBPtr->TechPtr);
-
- MemRecTTrainRcvrEnHw (NBPtr->TechPtr);
-
- // Clear DisableCal and set DisablePredriverCal
- NBPtr->FamilySpecificHook[ReEnablePhyComp] (NBPtr, NBPtr);
-
- MemRecTTrainDQSPosSw (NBPtr->TechPtr);
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Ps/mrp.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Ps/mrp.c
deleted file mode 100644
index ab42a87..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Ps/mrp.c
+++ /dev/null
@@ -1,261 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrp.c
- *
- * Common platform specific configuration.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem/Ps)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "cpuRegisters.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mru.h"
-#include "ma.h"
-#include "mp.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_RECOVERY_MEM_PS_MRP_FILECODE
-
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-extern MEM_PSC_FLOW_BLOCK* memRecPlatSpecFlowArray[];
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function gets platform specific configuration such as Max Freq., Slow Mode, Dram Term,
- * and so on.
- *
- * @param[in] *NBPtr Pointer to MEM_NB_BLOCK
- * @return TRUE - Successfully execute platform specific configuration flow.
- * @return FALSE - Fail to execute platform specific configuration flow.
- *
- */
-BOOLEAN
-MemPRecPSCFlow (
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 i;
-
- i = 0;
- while (memRecPlatSpecFlowArray[i] != NULL) {
- if ((memRecPlatSpecFlowArray[i])->DramTerm (NBPtr, (memRecPlatSpecFlowArray[i])->EntryOfTables)) {
- if ((memRecPlatSpecFlowArray[i])->ODTPattern (NBPtr, (memRecPlatSpecFlowArray[i])->EntryOfTables)) {
- if ((memRecPlatSpecFlowArray[i])->SAO (NBPtr, (memRecPlatSpecFlowArray[i])->EntryOfTables)) {
- if ((memRecPlatSpecFlowArray[i])->MR0WrCL (NBPtr, (memRecPlatSpecFlowArray[i])->EntryOfTables)) {
- if ((memRecPlatSpecFlowArray[i])->RC2IBT (NBPtr, (memRecPlatSpecFlowArray[i])->EntryOfTables)) {
- if ((memRecPlatSpecFlowArray[i])->RC10OpSpeed (NBPtr, (memRecPlatSpecFlowArray[i])->EntryOfTables)) {
- if ((memRecPlatSpecFlowArray[i])->LRIBT (NBPtr, (memRecPlatSpecFlowArray[i])->EntryOfTables)) {
- if ((memRecPlatSpecFlowArray[i])->LRNPR (NBPtr, (memRecPlatSpecFlowArray[i])->EntryOfTables)) {
- if ((memRecPlatSpecFlowArray[i])->LRNLR (NBPtr, (memRecPlatSpecFlowArray[i])->EntryOfTables)) {
- return TRUE;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- i++;
- }
- return FALSE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function constructs the rank type map of Dimm0, Dimm1, Dimm2. Also it counts the number
- * of dimm in the table.
- *
- * @param[in] Dimm0 Rank type of Dimm0
- * @param[in] Dimm1 Rank type of Dimm1
- * @param[in] Dimm2 Rank type of Dimm2
- * @param[in, out] *RankTypeInTable Pointer to RankTypeInTable variable
- *
- *
- */
-VOID
-MemPRecConstructRankTypeMap (
- IN UINT16 Dimm0,
- IN UINT16 Dimm1,
- IN UINT16 Dimm2,
- IN OUT UINT16 *RankTypeInTable
- )
-{
- UINT8 i;
- UINT16 RT;
- UINT8 BitShift;
-
- *RankTypeInTable = 0;
- RT = 0;
- BitShift = 0;
-
- for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) {
- switch (i) {
- case 0:
- RT = (Dimm0 == 0) ? NP : Dimm0;
- BitShift = 0;
- break;
- case 1:
- RT = (Dimm1 == 0) ? NP : Dimm1;
- BitShift = 4;
- break;
- case 2:
- RT = (Dimm2 == 0) ? NP : Dimm2;
- BitShift = 8;
- break;
- default:
- // dimm3 is not used, fills nibble3 with "NP"
- RT = NP;
- BitShift = 12;
- }
- *RankTypeInTable |= RT << BitShift;
- }
-}
-
-/*-----------------------------------------------------------------------------*/
-/**
- * MemPIsIdSupported
- * This function matches the CPU_LOGICAL_ID and PackageType with certain criteria to
- * determine if it is supported by this NB type.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] LogicalId - CPU_LOGICAL_ID
- * @param[in] PackageType - Package Type
- *
- * @return TRUE - NB type is matched !
- * @return FALSE - NB type is not matched !
- *
- */
-BOOLEAN
-MemPRecIsIdSupported (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN CPU_LOGICAL_ID LogicalId,
- IN UINT8 PackageType
- )
-{
- CPUID_DATA CpuId;
- UINT8 PkgType;
-
- LibAmdCpuidRead (AMD_CPUID_FMF, &CpuId, &(NBPtr->MemPtr->StdHeader));
- PkgType = (UINT8) (CpuId.EBX_Reg >> 28) & 0xF; // bit 31:28
-
- if (((NBPtr->MCTPtr->LogicalCpuid.Family & LogicalId.Family) != 0)
- && ((NBPtr->MCTPtr->LogicalCpuid.Revision & LogicalId.Revision) != 0)) {
- if ((PackageType == PT_DONT_CARE) || (PackageType == PkgType)) {
- return TRUE;
- }
- }
- return FALSE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function returns the rank type map of a channel.
- *
- * @param[in] *CurrentChannel Pointer to CH_DEF_STRUCT
- *
- * @return UINT16 - The map of rank type.
- *
- */
-UINT16
-MemPRecGetPsRankType (
- IN CH_DEF_STRUCT *CurrentChannel
- )
-{
- UINT8 i;
- UINT16 DIMMRankType;
-
- DIMMRankType = 0;
- for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) {
- if ((CurrentChannel->DimmQrPresent & (UINT8) 1 << i) != 0) {
- if (i < 2) {
- DIMMRankType |= (UINT16) 8 << (i << 2);
- }
- } else if ((CurrentChannel->DimmDrPresent & (UINT8) 1 << i) != 0) {
- DIMMRankType |= (UINT16) 4 << (i << 2);
- } else if ((CurrentChannel->DimmSRPresent & (UINT8) 1 << i) != 0) {
- DIMMRankType |= (UINT16) 2 << (i << 2);
- } else {
- DIMMRankType |= (UINT16) 1 << (i << 2);
- }
- }
- return DIMMRankType;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Ps/mrplribt.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Ps/mrplribt.c
deleted file mode 100644
index 32a78c1..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Ps/mrplribt.c
+++ /dev/null
@@ -1,183 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrplribt.c
- *
- * A sub-engine which extracts F0RC8, F1RC0, F1RC1 and F1RC2 value for LRDIMM configuration.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem/Ps)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mru.h"
-#include "ma.h"
-#include "mp.h"
-#include "cpuFamRegisters.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-#define FILECODE PROC_RECOVERY_MEM_PS_MRPLRIBT_FILECODE
-
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * A sub-function which extracts LRDIMM F0RC8, F1RC0, F1RC1 and F1RC2 value from a input
- * table and stores extracted value to a specific address.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK
- *
- * @return TRUE - Succeed in extracting the table value
- * @return FALSE - Fail to extract the table value
- *
- */
-BOOLEAN
-MemPRecGetLRIBT (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN MEM_PSC_TABLE_BLOCK *EntryOfTables
- )
-{
- UINT8 i;
- UINT8 MaxDimmPerCh;
- UINT8 NOD;
- UINT8 TableSize;
- UINT8 DDR3Voltage;
- UINT16 RankTypeOfPopulatedDimm;
- UINT16 RankTypeInTable;
- CPU_LOGICAL_ID LogicalCpuid;
- UINT8 PackageType;
- PSCFG_L_IBT_ENTRY *TblPtr;
- CH_DEF_STRUCT *CurrentChannel;
-
- CurrentChannel = NBPtr->ChannelPtr;
-
- //@todo LRDIMM
- //if (CurrentChannel->LrDimmPresent == 0) {
- // return TRUE;
- //}
-
- TblPtr = NULL;
- TableSize = 0;
- PackageType = 0;
- LogicalCpuid.Family = AMD_FAMILY_UNKNOWN;
- MaxDimmPerCh = RecGetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID);
- NOD = (UINT8) 1 << (MaxDimmPerCh - 1);
-
- i = 0;
- // Obtain table pointer, table size, Logical Cpuid and PSC type according to NB type and package type.
- while (EntryOfTables->TblEntryOfLRIBT[i] != NULL) {
- if (((EntryOfTables->TblEntryOfLRIBT[i])->Header.NumOfDimm & NOD) != 0) {
- LogicalCpuid = (EntryOfTables->TblEntryOfLRIBT[i])->Header.LogicalCpuid;
- PackageType = (EntryOfTables->TblEntryOfLRIBT[i])->Header.PackageType;
- //
- // Determine if this is the expected NB Type
- //
- if (MemPRecIsIdSupported (NBPtr, LogicalCpuid, PackageType)) {
- TblPtr = (PSCFG_L_IBT_ENTRY *) ((EntryOfTables->TblEntryOfLRIBT[i])->TBLPtr);
- TableSize = (EntryOfTables->TblEntryOfLRIBT[i])->TableSize;
- break;
- }
- }
- i++;
- }
-
- // Check whether no table entry is found.
- if (EntryOfTables->TblEntryOfLRIBT[i] == NULL) {
- return FALSE;
- }
-
- DDR3Voltage = (UINT8) (1 << (NBPtr->RefPtr->DDR3Voltage));
- RankTypeOfPopulatedDimm = MemPRecGetPsRankType (CurrentChannel);
-
- for (i = 0; i < TableSize; i++) {
- MemPRecConstructRankTypeMap ((UINT16) TblPtr->Dimm0, (UINT16) TblPtr->Dimm1, (UINT16) TblPtr->Dimm2, &RankTypeInTable);
- if (TblPtr->DimmPerCh == MaxDimmPerCh) {
- if ((TblPtr->VDDIO & DDR3Voltage) != 0) {
- if ((RankTypeInTable & RankTypeOfPopulatedDimm) == RankTypeOfPopulatedDimm) {
- NBPtr->PsPtr->F0RC8 = (UINT8) TblPtr->F0RC8;
- NBPtr->PsPtr->F1RC0 = (UINT8) TblPtr->F1RC0;
- NBPtr->PsPtr->F1RC1 = (UINT8) TblPtr->F1RC1;
- NBPtr->PsPtr->F1RC2 = (UINT8) TblPtr->F1RC2;
- break;
- }
- }
- }
- TblPtr++;
- }
- if (i == TableSize) {
- return FALSE;
- }
-
- return TRUE;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Ps/mrplrnlr.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Ps/mrplrnlr.c
deleted file mode 100644
index 3169e21..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Ps/mrplrnlr.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrplrnlr.c
- *
- * A sub-engine which extracts F0RC13[NumLogicalRanks] value for LRDIMM configuration.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem/Ps)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mru.h"
-#include "ma.h"
-#include "mp.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-#define FILECODE PROC_RECOVERY_MEM_PS_MRPLRNLR_FILECODE
-
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * A sub-function which extracts LRDIMM F0RC13[NumLogicalRanks] value from a input
- * table and stores extracted value to a specific address.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK
- *
- * @return TRUE - Succeed in extracting the table value
- * @return FALSE - Fail to extract the table value
- *
- */
-BOOLEAN
-MemPRecGetLRNLR (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN MEM_PSC_TABLE_BLOCK *EntryOfTables
- )
-{
- return TRUE;
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Ps/mrplrnpr.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Ps/mrplrnpr.c
deleted file mode 100644
index ac934e5..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Ps/mrplrnpr.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrplrnpr.c
- *
- * A sub-engine which extracts F0RC13[NumPhysicalRanks] value for LRDIMM configuration.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem/Ps)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mru.h"
-#include "ma.h"
-#include "mp.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-#define FILECODE PROC_RECOVERY_MEM_PS_MRPLRNPR_FILECODE
-
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * A sub-function which extracts LRDIMM F0RC13[NumPhysicalRanks] value from a input
- * table and stores extracted value to a specific address.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK
- *
- * @return TRUE - Succeed in extracting the table value
- * @return FALSE - Fail to extract the table value
- *
- */
-BOOLEAN
-MemPRecGetLRNPR (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN MEM_PSC_TABLE_BLOCK *EntryOfTables
- )
-{
- return TRUE;
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Ps/mrpmr0.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Ps/mrpmr0.c
deleted file mode 100644
index da78b20..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Ps/mrpmr0.c
+++ /dev/null
@@ -1,178 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mpmr0.c
- *
- * A sub-engine which extracts MR0[WR] and MR0[CL] value.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem/Ps)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mu.h"
-#include "ma.h"
-#include "mp.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_RECOVERY_MEM_PS_MRPMR0_FILECODE
-
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * A sub-function which extracts MR0[WR] or MR0[CL] value from a input table and store the
- * value to a specific address.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK
- *
- * @return TRUE - Succeed in extracting the table value
- * @return FALSE - Fail to extract the table value
- *
- */
-BOOLEAN
-MemPRecGetMR0WrCL (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN MEM_PSC_TABLE_BLOCK *EntryOfTables
- )
-{
- UINT8 i;
- UINT8 j;
- UINT8 p;
- UINT32 Value32;
- UINT8 TableSize;
- PSCFG_TYPE Type;
- CPU_LOGICAL_ID LogicalCpuid;
- UINT8 PackageType;
- PSCFG_MR0CL_ENTRY *TblPtr;
- PSC_TBL_ENTRY **ptr;
- CH_DEF_STRUCT *CurrentChannel;
-
- CurrentChannel = NBPtr->ChannelPtr;
- TblPtr = NULL;
- TableSize = 0;
-
- // Extract MR0[WR] value, then MR0[CL] value
- for (i = 0; i < 2; i++) {
- if (i == 0) {
- ptr = EntryOfTables->TblEntryOfMR0WR;
- Type = PSCFG_MR0WR;
- } else {
- ptr = EntryOfTables->TblEntryOfMR0CL;
- Type = PSCFG_MR0CL;
- }
-
- p = 0;
- // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type.
- while (ptr[p] != NULL) {
- //
- // Determine if this is the expected NB Type
- //
- LogicalCpuid = (ptr[p])->Header.LogicalCpuid;
- PackageType = (ptr[p])->Header.PackageType;
- if (MemPRecIsIdSupported (NBPtr, LogicalCpuid, PackageType)) {
- TblPtr = (PSCFG_MR0CL_ENTRY *) ((ptr[p])->TBLPtr);
- TableSize = (ptr[p])->TableSize;
- break;
- }
- p++;
- }
-
- // Check whether no table entry is found.
- if (ptr[p] == NULL) {
- return FALSE;
- }
-
- Value32 = (Type == PSCFG_MR0WR) ? NBPtr->GetBitField (NBPtr, BFTwrDDR3) : NBPtr->GetBitField (NBPtr, BFTcl);
-
- for (j = 0; j < TableSize; j++, TblPtr++) {
- if (Value32 == (UINT32) TblPtr->Timing) {
- if (Type == PSCFG_MR0WR) {
- NBPtr->PsPtr->MR0WR = (UINT8) TblPtr->Value;
- break;
- } else {
- NBPtr->PsPtr->MR0CL31 = (UINT8) TblPtr->Value;
- NBPtr->PsPtr->MR0CL0 = (UINT8) TblPtr->Value1;
- break;
- }
- }
- }
- if (j == TableSize) {
- return FALSE;
- }
- }
-
- return TRUE;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Ps/mrpodtpat.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Ps/mrpodtpat.c
deleted file mode 100644
index 7b981d9..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Ps/mrpodtpat.c
+++ /dev/null
@@ -1,183 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrpodtpat.c
- *
- * A sub-engine which extracts ODT pattern value.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem/Ps)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "cpuRegisters.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mru.h"
-#include "ma.h"
-#include "mp.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-#define FILECODE PROC_RECOVERY_MEM_PS_MRPODTPAT_FILECODE
-
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * A sub-function which extracts ODT Pattern value from a input table and stores extracted
- * value to a specific address.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK
- *
- * @return TRUE - Table values can be extracted per dimm population and ranks type.
- * @return FALSE - Table values cannot be extracted per dimm population and ranks type.
- *
- */
-BOOLEAN
-MemPRecGetODTPattern (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN MEM_PSC_TABLE_BLOCK *EntryOfTables
- )
-{
- UINT8 i;
- UINT16 RankTypeInTable;
- UINT16 RankTypeOfPopulatedDimm;
- UINT8 MaxDimmPerCh;
- UINT8 NOD;
- UINT8 TableSize;
- DIMM_TYPE DimmType;
- CPU_LOGICAL_ID LogicalCpuid;
- UINT8 PackageType;
- PSCFG_3D_ODTPAT_ENTRY *TblPtr;
- CH_DEF_STRUCT *CurrentChannel;
-
- CurrentChannel = NBPtr->ChannelPtr;
-
- TblPtr = NULL;
- TableSize = 0;
- PackageType = 0;
- LogicalCpuid.Family = AMD_FAMILY_UNKNOWN;
- MaxDimmPerCh = RecGetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID);
- NOD = (UINT8) 1 << (MaxDimmPerCh - 1);
-
- if (CurrentChannel->RegDimmPresent != 0) {
- DimmType = RDIMM_TYPE;
- } else if (CurrentChannel->SODimmPresent != 0) {
- DimmType = SODIMM_TYPE;
- //@todo LRDIMM
- //} else if (CurrentChannel->LrDimmPresent) {
- // DimmType = LRDIMM_TYPE;
- } else {
- DimmType = UDIMM_TYPE;
- }
-
- i = 0;
- // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type.
- while (EntryOfTables->TblEntryOfODTPattern[i] != NULL) {
- if (((EntryOfTables->TblEntryOfODTPattern[i])->Header.DimmType & DimmType) != 0) {
- if (((EntryOfTables->TblEntryOfODTPattern[i])->Header.NumOfDimm & NOD) != 0) {
- //
- // Determine if this is the expected NB Type
- //
- LogicalCpuid = (EntryOfTables->TblEntryOfODTPattern[i])->Header.LogicalCpuid;
- PackageType = (EntryOfTables->TblEntryOfODTPattern[i])->Header.PackageType;
- if (MemPRecIsIdSupported (NBPtr, LogicalCpuid, PackageType)) {
- TblPtr = (PSCFG_3D_ODTPAT_ENTRY *) ((EntryOfTables->TblEntryOfODTPattern[i])->TBLPtr);
- TableSize = (EntryOfTables->TblEntryOfODTPattern[i])->TableSize;
- break;
- }
- }
- }
- i++;
- }
-
- // Check whether no table entry is found.
- if (EntryOfTables->TblEntryOfODTPattern[i] == NULL) {
- return FALSE;
- }
-
- RankTypeOfPopulatedDimm = MemPRecGetPsRankType (CurrentChannel); //@todo - LRDIMM ?
-
- for (i = 0; i < TableSize; i++) {
- MemPRecConstructRankTypeMap ((UINT16) TblPtr->Dimm0, (UINT16) TblPtr->Dimm1, (UINT16) TblPtr->Dimm2, &RankTypeInTable);
- if ((RankTypeInTable & RankTypeOfPopulatedDimm) == RankTypeOfPopulatedDimm) {
- CurrentChannel->PhyRODTCSHigh = TblPtr->RdODTCSHigh;
- CurrentChannel->PhyRODTCSLow = TblPtr->RdODTCSLow;
- CurrentChannel->PhyWODTCSHigh = TblPtr->WrODTCSHigh;
- CurrentChannel->PhyWODTCSLow = TblPtr->WrODTCSLow;
- return TRUE;
- }
- TblPtr++;
- }
- return FALSE;
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Ps/mrprc10opspd.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Ps/mrprc10opspd.c
deleted file mode 100644
index 5a2c1e0..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Ps/mrprc10opspd.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrprc10opspd.c
- *
- * A sub-engine which extracts RC10 operating speed value for RDIMM configuration.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem/Ps)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "cpuRegisters.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mru.h"
-#include "ma.h"
-#include "mp.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_RECOVERY_MEM_PS_MRPRC10OPSPD_FILECODE
-
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Ps/mrprc2ibt.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Ps/mrprc2ibt.c
deleted file mode 100644
index 99aa5c3..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Ps/mrprc2ibt.c
+++ /dev/null
@@ -1,199 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrprc2ibt.c
- *
- * A sub-engine which extracts RC2[IBT] value for RDIMM configuration.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem/Ps)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "cpuRegisters.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mru.h"
-#include "ma.h"
-#include "mp.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-#define FILECODE PROC_RECOVERY_MEM_PS_MRPRC2IBT_FILECODE
-
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * A sub-function which extracts RC2[IBT] value from a input table and stores extracted
- * value to a specific address.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK
- *
- * @return TRUE - Table values can be extracted for all present dimms/ranks
- * @return FALSE - Table values cannot be extracted for all present dimms/ranks
- *
- */
-BOOLEAN
-MemPRecGetRC2IBT (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN MEM_PSC_TABLE_BLOCK *EntryOfTables
- )
-{
- UINT8 i;
- UINT8 MaxDimmPerCh;
- UINT8 NOD;
- UINT8 DimmIndex;
- UINT8 TableSize;
- UINT8 DDR3Voltage;
- UINT16 RankTypeOfPopulatedDimm;
- UINT16 RankTypeInTable;
- CPU_LOGICAL_ID LogicalCpuid;
- UINT8 PackageType;
- UINT8 TgtDimmType;
- UINT8 NumOfReg;
- PSCFG_MR2IBT_ENTRY *TblPtr;
- PSCFG_MR2IBT_ENTRY *OrgTblPtr;
- CH_DEF_STRUCT *CurrentChannel;
-
- CurrentChannel = NBPtr->ChannelPtr;
-
- if (CurrentChannel->RegDimmPresent == 0) {
- return TRUE;
- }
-
- TblPtr = NULL;
- TableSize = 0;
- PackageType = 0;
- MaxDimmPerCh = RecGetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID);
- NOD = (UINT8) 1 << (MaxDimmPerCh - 1);
-
- i = 0;
- // Obtain table pointer, table size, Logical Cpuid and PSC type according to NB type and package type.
- while (EntryOfTables->TblEntryOfRC2IBT[i] != NULL) {
- if (((EntryOfTables->TblEntryOfRC2IBT[i])->Header.NumOfDimm & NOD) != 0) {
- LogicalCpuid = (EntryOfTables->TblEntryOfRC2IBT[i])->Header.LogicalCpuid;
- PackageType = (EntryOfTables->TblEntryOfRC2IBT[i])->Header.PackageType;
- //
- // Determine if this is the expected NB Type
- //
- if (MemPRecIsIdSupported (NBPtr, LogicalCpuid, PackageType)) {
- TblPtr = (PSCFG_MR2IBT_ENTRY *) ((EntryOfTables->TblEntryOfRC2IBT[i])->TBLPtr);
- TableSize = (EntryOfTables->TblEntryOfRC2IBT[i])->TableSize;
- break;
- }
- }
- i++;
- }
-
- // Check whether no table entry is found.
- if (EntryOfTables->TblEntryOfRC2IBT[i] == NULL) {
- return FALSE;
- }
-
- DDR3Voltage = (UINT8) (1 << (NBPtr->RefPtr->DDR3Voltage));
- RankTypeOfPopulatedDimm = MemPRecGetPsRankType (CurrentChannel);
-
- OrgTblPtr = TblPtr;
- for (DimmIndex = 0; DimmIndex < MAX_DIMMS_PER_CHANNEL; DimmIndex++) {
- TblPtr = OrgTblPtr;
- if ((CurrentChannel->ChDimmValid& (UINT8) (1 << DimmIndex)) != 0) {
- NumOfReg = CurrentChannel->CtrlWrd02[DimmIndex];
- if ((CurrentChannel->DimmQrPresent & (UINT8) (1 << DimmIndex)) != 0) {
- TgtDimmType = DIMM_QR;
- } else if ((CurrentChannel->DimmDrPresent & (UINT8) (1 << DimmIndex)) != 0) {
- TgtDimmType = DIMM_DR;
- } else {
- TgtDimmType = DIMM_SR;
- }
-
- for (i = 0; i < TableSize; i++) {
- MemPRecConstructRankTypeMap ((UINT16) TblPtr->Dimm0, (UINT16) TblPtr->Dimm1, (UINT16) TblPtr->Dimm2, &RankTypeInTable);
- if (TblPtr->DimmPerCh == MaxDimmPerCh) {
- if ((TblPtr->VDDIO & DDR3Voltage) != 0) {
- if ((RankTypeInTable & RankTypeOfPopulatedDimm) == RankTypeOfPopulatedDimm) {
- if ((TblPtr->Dimm & TgtDimmType) != 0) {
- // If TblPtr->NumOfReg == 0x0F, that means the condition will be TRUE regardless of NumRegisters in DIMM
- if ((TblPtr->NumOfReg == 0xF) || (TblPtr->NumOfReg == NumOfReg)) {
- CurrentChannel->CtrlWrd02[DimmIndex] = (UINT8) ((TblPtr->IBT & 0x1) << 2);
- CurrentChannel->CtrlWrd08[DimmIndex] = (UINT8) ((TblPtr->IBT & 0xE) >> 1);
- break;
- }
- }
- }
- }
- }
- TblPtr++;
- }
- }
- }
- return TRUE;
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Ps/mrprtt.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Ps/mrprtt.c
deleted file mode 100644
index 523f729..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Ps/mrprtt.c
+++ /dev/null
@@ -1,218 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrprtt.c
- *
- * A sub-engine which extracts RttNom and RttWr (Dram Term and Dynamic Dram Term) value.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem/Ps)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "cpuRegisters.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mru.h"
-#include "ma.h"
-#include "mp.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_RECOVERY_MEM_PS_MRPRTT_FILECODE
-
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * A sub-function which extracts RttNom and RttWr value from a input table and stores extracted
- * value to a specific address.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK
- *
- * @return TRUE - Table values can be extracted for all present dimms/ranks
- * @return FALSE - Table values cannot be extracted for all present dimms/ranks
- *
- */
-BOOLEAN
-MemPRecGetRttNomWr (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN MEM_PSC_TABLE_BLOCK *EntryOfTables
- )
-{
- UINT8 i;
- UINT8 MaxDimmPerCh;
- UINT8 NOD;
- UINT8 TableSize;
- UINT8 DDR3Voltage;
- UINT16 RankTypeOfPopulatedDimm;
- UINT16 RankTypeInTable;
- DIMM_TYPE DimmType;
- CPU_LOGICAL_ID LogicalCpuid;
- UINT8 PackageType;
- UINT8 TgtDimmType;
- UINT8 TgtRank;
- UINT8 Chipsel;
- PSCFG_RTT_ENTRY *TblPtr;
- PSCFG_RTT_ENTRY *OrgTblPtr;
- CH_DEF_STRUCT *CurrentChannel;
-
- CurrentChannel = NBPtr->ChannelPtr;
-
- TblPtr = NULL;
- TableSize = 0;
- PackageType = 0;
- LogicalCpuid.Family = AMD_FAMILY_UNKNOWN;
- MaxDimmPerCh = RecGetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID);
- NOD = (UINT8) 1 << (MaxDimmPerCh - 1);
-
- if (CurrentChannel->RegDimmPresent != 0) {
- DimmType = RDIMM_TYPE;
- } else if (CurrentChannel->SODimmPresent != 0) {
- DimmType = SODIMM_TYPE;
- //@todo LRDIMM
- //} else if (CurrentChannel->LrDimmPresent) {
- // DimmType = LRDIMM_TYPE;
- } else {
- DimmType = UDIMM_TYPE;
- }
-
- i = 0;
- // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type.
- while (EntryOfTables->TblEntryOfDramTerm[i] != NULL) {
- if (((EntryOfTables->TblEntryOfDramTerm[i])->Header.DimmType & DimmType) != 0) {
- if (((EntryOfTables->TblEntryOfDramTerm[i])->Header.NumOfDimm & NOD) != 0) {
- //
- // Determine if this is the expected NB Type
- //
- LogicalCpuid = (EntryOfTables->TblEntryOfDramTerm[i])->Header.LogicalCpuid;
- PackageType = (EntryOfTables->TblEntryOfDramTerm[i])->Header.PackageType;
- if (MemPRecIsIdSupported (NBPtr, LogicalCpuid, PackageType)) {
- TblPtr = (PSCFG_RTT_ENTRY *) ((EntryOfTables->TblEntryOfDramTerm[i])->TBLPtr);
- TableSize = (EntryOfTables->TblEntryOfDramTerm[i])->TableSize;
- break;
- }
- }
- }
- i++;
- }
-
- // Check whether no table entry is found.
- if (EntryOfTables->TblEntryOfDramTerm[i] == NULL) {
- return FALSE;
- }
-
- DDR3Voltage = (UINT8) (1 << (NBPtr->RefPtr->DDR3Voltage));
- RankTypeOfPopulatedDimm = MemPRecGetPsRankType (CurrentChannel); //@todo - LRDIMM ?
-
- OrgTblPtr = TblPtr;
- for (Chipsel = 0; Chipsel < MAX_CS_PER_CHANNEL; Chipsel++) {
- TblPtr = OrgTblPtr;
- if ((NBPtr->DCTPtr->Timings.CsEnabled & (UINT16) (1 << Chipsel)) != 0) {
- if ((CurrentChannel->DimmQrPresent & (UINT8) (1 << (Chipsel >> 1))) != 0) {
- TgtDimmType = DIMM_QR;
- TgtRank = (UINT8) ((Chipsel < 4) ? 1 << (Chipsel & 1) : 4 << (Chipsel & 1));
- } else if ((CurrentChannel->DimmDrPresent & (UINT8) (1 << (Chipsel >> 1))) != 0) {
- TgtDimmType = DIMM_DR;
- TgtRank = (UINT8) 1 << (Chipsel & 1);
- } else {
- TgtDimmType = DIMM_SR;
- TgtRank = (UINT8) 1 << (Chipsel & 1);
- }
-
- for (i = 0; i < TableSize; i++) {
- MemPRecConstructRankTypeMap ((UINT16) TblPtr->Dimm0, (UINT16) TblPtr->Dimm1, (UINT16) TblPtr->Dimm2, &RankTypeInTable);
- if (TblPtr->DimmPerCh == MaxDimmPerCh) {
- if ((TblPtr->VDDIO & DDR3Voltage) != 0) {
- if ((RankTypeInTable & RankTypeOfPopulatedDimm) == RankTypeOfPopulatedDimm) {
- if ((TblPtr->Dimm & TgtDimmType) != 0) {
- if ((TblPtr->Rank & TgtRank) != 0) {
- NBPtr->PsPtr->RttNom[Chipsel] = (UINT8) TblPtr->RttNom;
- NBPtr->PsPtr->RttWr[Chipsel] = (UINT8) TblPtr->RttWr;
- break;
- }
- }
- }
- }
- }
- TblPtr++;
- }
- if (i == TableSize) {
- return FALSE;
- }
- }
- }
-
- return TRUE;
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Ps/mrpsao.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Ps/mrpsao.c
deleted file mode 100644
index 034217b..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Ps/mrpsao.c
+++ /dev/null
@@ -1,188 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrpsao.c
- *
- * A sub-engine which extracts Slow access mode, Address timing and Output driver compensation value.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem/Ps)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "cpuRegisters.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "mru.h"
-#include "ma.h"
-#include "mp.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-#define FILECODE PROC_RECOVERY_MEM_PS_MRPSAO_FILECODE
-
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * A sub-function which extracts Slow mode, Address timing and Output driver compensation value
- * from a input table and store those value to a specific address.
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in] *EntryOfTables - Pointer to MEM_PSC_TABLE_BLOCK
- *
- * @return TRUE - Table values can be extracted per dimm population and ranks type.
- * @return FALSE - Table values cannot be extracted per dimm population and ranks type.
- *
- */
-BOOLEAN
-MemPRecGetSAO (
- IN OUT MEM_NB_BLOCK *NBPtr,
- IN MEM_PSC_TABLE_BLOCK *EntryOfTables
- )
-{
- UINT8 i;
- UINT8 MaxDimmPerCh;
- UINT8 NOD;
- UINT8 TableSize;
- UINT8 DDR3Voltage;
- UINT16 RankTypeOfPopulatedDimm;
- UINT16 RankTypeInTable;
- DIMM_TYPE DimmType;
- CPU_LOGICAL_ID LogicalCpuid;
- UINT8 PackageType;
- PSCFG_SAO_ENTRY *TblPtr;
- CH_DEF_STRUCT *CurrentChannel;
-
- CurrentChannel = NBPtr->ChannelPtr;
-
- TblPtr = NULL;
- TableSize = 0;
- PackageType = 0;
- LogicalCpuid.Family = AMD_FAMILY_UNKNOWN;
- MaxDimmPerCh = RecGetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration, NBPtr->MCTPtr->SocketId, CurrentChannel->ChannelID);
- NOD = (UINT8) 1 << (MaxDimmPerCh - 1);
-
- if (CurrentChannel->RegDimmPresent != 0) {
- DimmType = RDIMM_TYPE;
- } else if (CurrentChannel->SODimmPresent != 0) {
- DimmType = SODIMM_TYPE;
- //@todo LRDIMM
- //} else if (CurrentChannel->LrDimmPresent) {
- // DimmType = LRDIMM_TYPE;
- } else {
- DimmType = UDIMM_TYPE;
- }
-
- i = 0;
- // Obtain table pointer, table size, Logical Cpuid and PSC type according to Dimm, NB and package type.
- while (EntryOfTables->TblEntryOfSAO[i] != NULL) {
- if (((EntryOfTables->TblEntryOfSAO[i])->Header.DimmType & DimmType) != 0) {
- if (((EntryOfTables->TblEntryOfSAO[i])->Header.NumOfDimm & NOD) != 0) {
- //
- // Determine if this is the expected NB Type
- //
- LogicalCpuid = (EntryOfTables->TblEntryOfSAO[i])->Header.LogicalCpuid;
- PackageType = (EntryOfTables->TblEntryOfSAO[i])->Header.PackageType;
- if (MemPRecIsIdSupported (NBPtr, LogicalCpuid, PackageType)) {
- TblPtr = (PSCFG_SAO_ENTRY *) ((EntryOfTables->TblEntryOfSAO[i])->TBLPtr);
- TableSize = (EntryOfTables->TblEntryOfSAO[i])->TableSize;
- break;
- }
- }
- }
- i++;
- }
-
- // Check whether no table entry is found.
- if (EntryOfTables->TblEntryOfSAO[i] == NULL) {
- return FALSE;
- }
-
- DDR3Voltage = (UINT8) (1 << (NBPtr->RefPtr->DDR3Voltage));
- RankTypeOfPopulatedDimm = MemPRecGetPsRankType (CurrentChannel); //@todo - LRDIMM ?
-
- for (i = 0; i < TableSize; i++) {
- MemPRecConstructRankTypeMap ((UINT16) TblPtr->Dimm0, (UINT16) TblPtr->Dimm1, (UINT16) TblPtr->Dimm2, &RankTypeInTable);
- if (TblPtr->DimmPerCh == MaxDimmPerCh) {
- if ((TblPtr->VDDIO & DDR3Voltage) != 0) {
- if ((RankTypeInTable & RankTypeOfPopulatedDimm) == RankTypeOfPopulatedDimm) {
- CurrentChannel->DctAddrTmg = TblPtr->AddTmgCtl;
- CurrentChannel->DctOdcCtl = TblPtr->ODC;
- CurrentChannel->SlowMode = (TblPtr->SlowMode == 1) ? TRUE : FALSE;
- return TRUE;
- }
- }
- }
- TblPtr++;
- }
- return FALSE;
-}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Tech/DDR3/mrt3.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Tech/DDR3/mrt3.c
deleted file mode 100644
index 4f59351..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Tech/DDR3/mrt3.c
+++ /dev/null
@@ -1,189 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrt3.c
- *
- * Common Technology functions for DDR3 Recovery
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "mrport.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mrt3.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function Constructs the technology block
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-VOID
-MemRecConstructTechBlock3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- UINT8 Dct;
- UINT8 Channel;
- for (Dct = 0; Dct < NBPtr->MCTPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- for (Channel = 0; Channel < NBPtr->DCTPtr->ChannelCount; Channel++) {
- NBPtr->SwitchChannel (NBPtr, Channel);
- NBPtr->ChannelPtr->TechType = DDR3_TECHNOLOGY;
- }
- }
-
- TechPtr->NBPtr = NBPtr;
- TechPtr->RefPtr = NBPtr->RefPtr;
-
- TechPtr->DramInit = MemRecTDramInitSw3;
- TechPtr->SetDramMode = MemRecTSetDramMode3;
- TechPtr->DimmPresence = MemRecTDIMMPresence3;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the initial controller environment before training.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-VOID
-MemRecTBeginTraining (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- S_UINT64 SMsr;
- MEM_DATA_STRUCT *MemPtr;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
- MemPtr = NBPtr->MemPtr;
-
- LibAmdReadCpuReg (CR4_REG, &TechPtr->CR4reg);
- LibAmdWriteCpuReg (CR4_REG, TechPtr->CR4reg | ((UINT32) 1 << 9)); // enable SSE2
-
- LibAmdMsrRead (HWCR, (UINT64 *) (&SMsr), &MemPtr->StdHeader); // HWCR
- TechPtr->HwcrLo = SMsr.lo;
- SMsr.lo |= 0x00020000; // turn on HWCR.wrap32dis
- SMsr.lo &= 0xFFFF7FFF; // turn off HWCR.SSEDIS
- LibAmdMsrWrite (HWCR, (UINT64 *) (&SMsr), &MemPtr->StdHeader);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the final controller environment after training.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-VOID
-MemRecTEndTraining (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- S_UINT64 SMsr;
- MEM_DATA_STRUCT *MemPtr;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
- MemPtr = NBPtr->MemPtr;
-
- LibAmdWriteCpuReg (CR4_REG, TechPtr->CR4reg);
-
- LibAmdMsrRead (HWCR, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- SMsr.lo = TechPtr->HwcrLo;
- LibAmdMsrWrite (HWCR, (UINT64 *)&SMsr, &MemPtr->StdHeader);
-}
-
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Tech/DDR3/mrtrci3.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Tech/DDR3/mrtrci3.c
deleted file mode 100644
index 0d3e1de..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Tech/DDR3/mrtrci3.c
+++ /dev/null
@@ -1,244 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrtrci3.c
- *
- * Technology Control word initialization for DDR3 Recovery
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "OptionMemory.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "mru.h"
-#include "mt.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-UINT8
-STATIC
-MemRecTGetCtlWord3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 CtrlWordNum
- );
-
-VOID
-STATIC
-MemRecTSendCtlWord3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 CmdNum,
- IN UINT8 Value
- );
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sends control words
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return pDCT->Timings.TrwtTO updated
- */
-
-VOID
-MemRecTDramControlRegInit3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT8 RCNum;
- UINT8 Data;
-
- MEM_DATA_STRUCT *MemPtr;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
- MemPtr = NBPtr->MemPtr;
-
- // wait 8us TACT must be changed to optimize to 8 MEM CLKs
- // and wait 6us for PLL LOCK
- MemRecUWait10ns (80 + 60, MemPtr);
-
- // 2. Program F2x[1, 0]A8[CtrlWordCS]=bit mask for target chip selects.
- NBPtr->SetBitField (NBPtr, BFCtrlWordCS, 3 << (NBPtr->DimmToBeUsed << 1));
-
- for (RCNum = 0; RCNum <= 15; RCNum++) {
- // wait 8us for TMRD, must be changed to optimize to 8 MEM CLKs
- MemRecUWait10ns (80, MemPtr);
-
- if ((RCNum != 6) && (RCNum != 7)) {
- Data = MemRecTGetCtlWord3 (TechPtr, RCNum);
- MemRecTSendCtlWord3 (TechPtr, RCNum, Data);
- }
- }
-
- MemRecUWait10ns (60, MemPtr); // wait 6us for TSTAB
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function calculates the ControlRC value
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] CtrlWordNum - control Word number.
- *
- * @return Control Word value
- */
-
-UINT8
-STATIC
-MemRecTGetCtlWord3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 CtrlWordNum
- )
-{
- UINT8 Data;
-
- CH_DEF_STRUCT *ChannelPtr;
-
- ChannelPtr = TechPtr->NBPtr->ChannelPtr;
-
- Data = 0; //Default value for all control words is 0
- switch (CtrlWordNum) {
- case 0:
- Data = 0x02; // DA4=1
- break;
- case 1:
- Data = 0x0C; // if single rank, set DBA1 and DBA0
- break;
- case 3:
- Data = ChannelPtr->CtrlWrd03[TechPtr->NBPtr->DimmToBeUsed];
- break;
- case 4:
- Data = ChannelPtr->CtrlWrd04[TechPtr->NBPtr->DimmToBeUsed];
- break;
- case 5:
- Data = ChannelPtr->CtrlWrd05[TechPtr->NBPtr->DimmToBeUsed];
- break;
- case 9:
- Data = 0x0D;
- break;
- default:;
- }
-
- return (Data&0x0F);
-}
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sends control word command
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] CmdNum - control number.
- * @param[in] Value - value to send
- *
- */
-
-VOID
-STATIC
-MemRecTSendCtlWord3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 CmdNum,
- IN UINT8 Value
- )
-{
- MEM_NB_BLOCK *NBPtr;
-
- ASSERT (CmdNum < 16);
- ASSERT (Value < 16);
-
- NBPtr = TechPtr->NBPtr;
-
- // 1. Program MrsBank and MrsAddress.
- // n = [BA2, A2, A1, A0].
- // data = [BA1, BA0, A4, A3].
- // Set all other bits in MrsAddress to zero.
- //
- NBPtr->SetBitField (NBPtr, BFMrsBank, ((CmdNum&8) >> 1) | (Value >> 2));
- NBPtr->SetBitField (NBPtr, BFMrsAddress, ((Value&3) << 3) | (CmdNum&7));
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCS%d RC%02d %04x\n",
- (NBPtr->GetBitField (NBPtr, BFDramInitRegReg) >> 20) & 0xF,
- ((NBPtr->GetBitField (NBPtr, BFDramInitRegReg) >> 15) & 8) |
- (NBPtr->GetBitField (NBPtr, BFDramInitRegReg) & 7),
- ((NBPtr->GetBitField (NBPtr, BFDramInitRegReg) >> 14) & 0xC) |
- ((NBPtr->GetBitField (NBPtr, BFDramInitRegReg) >> 3) & 3));
-
- // 2.Set SendCtrlWord=1
- NBPtr->SetBitField (NBPtr, BFSendCtrlWord, 1);
- // 3.Wait for BFSendCtrlWord=0
- while (NBPtr->GetBitField (NBPtr, BFSendCtrlWord) != 0) {}
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c
deleted file mode 100644
index 92a035f..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c
+++ /dev/null
@@ -1,360 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrtsdi3.c
- *
- * Technology Software DRAM Init for DDR3 Recovery
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "OptionMemory.h"
-#include "mm.h"
-#include "mn.h"
-#include "mru.h"
-#include "mt.h"
-#include "mrt3.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initiates software DRAM init
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-VOID
-MemRecTDramInitSw3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT8 ChipSel;
- MEM_DATA_STRUCT *MemPtr;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
- MemPtr = NBPtr->MemPtr;
-
- // 3.Program F2x[1,0]7C[EnDramInit]=1
- NBPtr->SetBitField (NBPtr, BFEnDramInit, 1);
-
- // 4.wait 200us
- MemRecUWait10ns (20000, MemPtr);
-
- NBPtr->SetBitField (NBPtr, BFDeassertMemRstX, 1);
-
- // 6.wait 500us
- MemRecUWait10ns (50000, MemPtr);
-
- // 7.NOP or deselect & take CKE high
- NBPtr->SetBitField (NBPtr, BFAssertCke, 1);
-
- // 8.wait 360ns
- MemRecUWait10ns (36, MemPtr);
-
- // The following steps are performed with registered DIMMs only and
- // must be done for each chip select pair:
- //
- if (NBPtr->ChannelPtr->RegDimmPresent != 0) {
- MemRecTDramControlRegInit3 (TechPtr);
- }
-
- //
- // In recovery mode, we only need to initialize one chipsel for UDIMMs.
- //
- NBPtr->SetDramOdtRec (NBPtr, MISSION_MODE, 0, 0);
-
- for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) {
- if ((NBPtr->DCTPtr->Timings.CsPresent & (UINT16) 1 << ChipSel) != 0) {
- NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel);
- // 13.Send EMRS(2)
- MemRecTEMRS23 (TechPtr);
- NBPtr->SendMrsCmd (NBPtr);
-
- // 14.Send EMRS(3). Ordinarily at this time, MrsAddress[2:0]=000b
- MemRecTEMRS33 (TechPtr);
- NBPtr->SendMrsCmd (NBPtr);
-
- // 15.Send EMRS(1).
- MemRecTEMRS13 (TechPtr);
- NBPtr->SendMrsCmd (NBPtr);
-
- // 16.Send MRS with MrsAddress[8]=1(reset the DLL)
- MemRecTMRS3 (TechPtr);
- NBPtr->SendMrsCmd (NBPtr);
-
- //wait 500us
- MemRecUWait10ns (50000, MemPtr);
-
- if (NBPtr->ChannelPtr->RegDimmPresent == 0) {
- break;
- }
- }
- }
-
- // 17.Send two ZQCL commands (to even then odd chip select)
- NBPtr->sendZQCmd (NBPtr);
- NBPtr->sendZQCmd (NBPtr);
-
- // 18.Program F2x[1,0]7C[EnDramInit]=0
- NBPtr->SetBitField (NBPtr, BFEnDramInit, 0);
-
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function calculates the EMRS1 value
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-VOID
-MemRecTEMRS13 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT16 MrsAddress;
- UINT8 DramTerm;
-
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
-
- // BA2=0,BA1=0,BA0=1
- NBPtr->SetBitField (NBPtr, BFMrsBank, 1);
-
- MrsAddress = 0;
-
- // program MrsAddress[5,1]=output driver impedance control (DIC):
- // based on F2x[1,0]84[DrvImpCtrl], which is 2'b01
- MrsAddress |= ((UINT16) 1 << 1);
-
- // program MrsAddress[9,6,2]=nominal termination resistance of ODT (RTT):
- // based on F2x[1,0]84[DramTerm], which is 3'b001 (60 Ohms)
- if (!(NBPtr->IsSupported[CheckDramTerm])) {
- DramTerm = (UINT8) NBPtr->GetBitField (NBPtr, BFDramTerm);
- } else {
- DramTerm = NBPtr->ChannelPtr->Reserved[0];
- }
- if ((DramTerm & 1) != 0) {
- MrsAddress |= ((UINT16) 1 << 2);
- }
- if ((DramTerm & 2) != 0) {
- MrsAddress |= ((UINT16) 1 << 6);
- }
- if ((DramTerm & 4) != 0) {
- MrsAddress |= ((UINT16) 1 << 9);
- }
-
- // program MrsAddress[12]=output disable (QOFF):
- // based on F2x[1,0]84[Qoff], which is 1'b0
-
- // program MrsAddress[11]=TDQS:
- // based on F2x[1,0]94[RDqsEn], which is 1'b0
-
- NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function calculates the EMRS2 value
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-VOID
-MemRecTEMRS23 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT16 MrsAddress;
- UINT8 DramTermDyn;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
-
- // BA2=0,BA1=1,BA0=0
- NBPtr->SetBitField (NBPtr, BFMrsBank, 2);
-
- // program MrsAddress[5:3]=CAS write latency (CWL):
- // based on F2x[1,0]84[Tcwl], which is 3'b000
- //
- MrsAddress = 0;
-
- // program MrsAddress[6]=auto self refresh method (ASR):
- // based on F2x[1,0]84[ASR], which is 1'b1
- // program MrsAddress[7]=self refresh temperature range (SRT):
- // based on F2x[1,0]84[SRT], which is also 1'b0
- //
- MrsAddress |= (UINT16) 1 << 6;
-
- // program MrsAddress[10:9]=dynamic termination during writes (RTT_WR):
- // based on F2x[1,0]84[DramTermDyn]
- //
- if (!(NBPtr->IsSupported[CheckDramTermDyn])) {
- DramTermDyn = (UINT8) NBPtr->GetBitField (NBPtr, BFDramTermDyn);
- } else {
- DramTermDyn = NBPtr->ChannelPtr->Reserved[1];
- }
- MrsAddress |= (UINT16) DramTermDyn << 9;
- NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function calculates the EMRS3 value
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-VOID
-MemRecTEMRS33 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
-
- // BA2=0,BA1=1,BA0=1
- NBPtr->SetBitField (NBPtr, BFMrsBank, 3);
-
- // program MrsAddress[1:0]=multi purpose register address location
- // (MPR Location):based on F2x[1,0]84[MprLoc], which is 0
- // program MrsAddress[2]=multi purpose register
- // (MPR):based on F2x[1,0]84[MprEn], which is also 0
- //
- NBPtr->SetBitField (NBPtr, BFMrsAddress, 0);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This sets MSS value
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-VOID
-MemRecTMRS3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT16 MrsAddress;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
-
- // BA2=0,BA1=0,BA0=0
- NBPtr->SetBitField (NBPtr, BFMrsBank, 0);
-
- // program MrsAddress[1:0]=burst length and control method
- // (BL):based on F2x[1,0]84[BurstCtrl], which is 1'b0
- //
- MrsAddress = 0;
-
- // program MrsAddress[3]=1 (BT):interleaved
- MrsAddress |= (UINT16) 1 << 3;
-
- // program MrsAddress[6:4,2]=read CAS latency
- // (CL):based on F2x[1,0]88[Tcl], which is 4'b0010
- MrsAddress |= (UINT16) 2 << 4;
-
- // program MrsAddress[11:9]=write recovery for auto-precharge
- // (WR):based on F2x[1,0]84[Twr], which is 3'b010
- //
- MrsAddress |= (UINT16) 2 << 9;
-
- // program MrsAddress[12]=0 (PPD):slow exit
-
- // program MrsAddress[8]=1 (DLL):DLL reset
- MrsAddress |= (UINT16) 1 << 8; // just issue DLL reset at first time
-
- NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.c
deleted file mode 100644
index 7d20e45..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.c
+++ /dev/null
@@ -1,326 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrtspd3.c
- *
- * Technology SPD supporting functions for DDR3 Recovery
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mrtspd3.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define _UNDEF_ 0xFF
-#define MAX_DIES_PER_SOCKET 2 ///< Set to largest of any CPU
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the DRAM mode
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - indicates that the DRAM mode is set to DDR2
- */
-
-BOOLEAN
-MemRecTSetDramMode3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- TechPtr->NBPtr->SetBitField (TechPtr->NBPtr, BFLegacyBiosMode, 0);
- TechPtr->NBPtr->SetBitField (TechPtr->NBPtr, BFDdr3Mode, 1);
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function determines if DIMMs are present. It checks checksum and interrogates the SPDs
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - indicates that a FATAL error has not occurred
- * @return FALL - indicates that a FATAL error has not occurred
- */
-
-BOOLEAN
-MemRecTDIMMPresence3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT8 Node;
- UINT8 Dct;
- UINT8 Channel;
- UINT8 i;
- SPD_DEF_STRUCT *SPDPtr;
- UINT8 *SpdBufferPtr;
- DIE_STRUCT *MCTPtr;
- DCT_STRUCT *DCTPtr;
- CH_DEF_STRUCT *ChannelPtr;
- MEM_NB_BLOCK *NBPtr;
- UINT16 MaxDimms;
- UINT16 Value16;
- UINT8 Devwidth;
- UINT8 Value8;
- UINT16 DimmMask;
- UINT8 VoltageMap;
- UINT8 VDDByte;
- UINT32 V1_2XDimmMap;
- UINT32 V1_35DimmMap;
- UINT32 V1_5DimmMap;
-
- NBPtr = TechPtr->NBPtr;
- MCTPtr = NBPtr->MCTPtr;
- VoltageMap = 0xFF;
- V1_2XDimmMap = 0;
- V1_35DimmMap = 0;
- V1_5DimmMap = 0;
-
- NBPtr->DimmToBeUsed = _UNDEF_;
- for (Node = 0; Node < NBPtr->MemPtr->DieCount; Node++) {
- NBPtr->SwitchNodeRec (NBPtr, Node);
- for (Dct = 0; Dct < NBPtr->MCTPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- DCTPtr = NBPtr->DCTPtr;
- for (Channel = 0; Channel < DCTPtr->ChannelCount; Channel++) {
- NBPtr->SwitchChannel (NBPtr, Channel);
- ChannelPtr = NBPtr->ChannelPtr;
- SPDPtr = NBPtr->SPDPtr;
-
- // Get the maximum number of DIMMs
- MaxDimms = MAX_DIMMS_PER_CHANNEL;
- for (i = 0; i < MaxDimms; i++) {
- // Bitmask representing dimm #i.
- DimmMask = (UINT16) 1 << i;
-
- if (SPDPtr[i].DimmPresent) {
- SpdBufferPtr = (UINT8 *)&(SPDPtr[i].Data);
-
- MCTPtr->DimmPresent |= DimmMask;
- if (SpdBufferPtr[SPD_TYPE] == JED_DDR3SDRAM) {
- ChannelPtr->ChDimmValid |= DimmMask;
- }
-
- // Check module type information.
- if (SpdBufferPtr[SPD_DIMM_TYPE] == JED_RDIMM || SpdBufferPtr[SPD_DIMM_TYPE] == JED_MINIRDIMM) {
- ChannelPtr->RegDimmPresent |= DimmMask;
- }
-
- if (SpdBufferPtr[SPD_DIMM_TYPE] == JED_SODIMM) {
- ChannelPtr->SODimmPresent |= DimmMask;
- }
-
- // Get the Dimm width data
- Devwidth = SpdBufferPtr[SPD_DEV_WIDTH] & 0x7;
- switch (Devwidth) {
- case 0:
- ChannelPtr->Dimmx4Present |= DimmMask;
- Devwidth = 4;
- break;
- case 1:
- ChannelPtr->Dimmx8Present |= DimmMask;
- Devwidth = 8;
- break;
- case 2:
- ChannelPtr->Dimmx16Present |= DimmMask;
- Devwidth = 16;
- break;
- default:
- IDS_ERROR_TRAP;
- }
-
- // Determine the page size.
- // page_size = 2^COLBITS * Devwidth/8
- //
- Value16 = (((UINT16) 1 << (SpdBufferPtr[SPD_COL_SZ]&7)) * Devwidth) / 8;
- if ((Value16 >> 11) == 0) {
- DCTPtr->Timings.DIMM1KPage |= DimmMask;
- }
-
- // Calculate bus loading per Channel
- if (Devwidth == 16) {
- Devwidth = 4;
- } else if (Devwidth == 4) {
- Devwidth = 16;
- }
-
- // specify the number of ranks
- Value8 = ((SpdBufferPtr[SPD_RANKS] >> 3) & 0x07) + 1;
- if (Value8 > 2) {
- ChannelPtr->DimmQrPresent |= DimmMask;
- Devwidth = Devwidth << 2;
- } else if (Value8 == 2) {
- ChannelPtr->DimmDrPresent |= DimmMask; // Dual rank dimms
- Devwidth = Devwidth << 1;
- } else {
- ChannelPtr->DimmSRPresent |= DimmMask;
- }
-
- ChannelPtr->Ranks = ChannelPtr->Ranks + Value8;
- ChannelPtr->Loads = ChannelPtr->Loads + Devwidth;
- ChannelPtr->Dimms++;
-
- // Check address mirror support for Unbuffered Dimms only
- if ((ChannelPtr->RegDimmPresent & DimmMask) == 0) {
- if ((SpdBufferPtr[SPD_ADDRMAP] & 1) != 0) {
- ChannelPtr->DimmMirrorPresent |= DimmMask;
- }
- }
-
- // Get control word values for RC3, RC4 and RC5
- ChannelPtr->CtrlWrd03[i] = SpdBufferPtr[SPD_CTLWRD03] >> 4;
- ChannelPtr->CtrlWrd04[i] = SpdBufferPtr[SPD_CTLWRD04] & 0x0F;
- ChannelPtr->CtrlWrd05[i] = SpdBufferPtr[SPD_CTLWRD05] >> 4;
- //
- // Temporarily store info. of SPD byte 63 into CtrlWrd02(s),
- // and they will be used late to calculate real RC2 and RC8 value
- //
- ChannelPtr->CtrlWrd02[i] = SpdBufferPtr[SPD_ADDRMAP] & 0x03;
-
- // Get the common voltage if possible and create the individual Dimm maps per voltage
- VDDByte = SpdBufferPtr[SPD_MNVVDD];
- VDDByte ^= 1;
- VoltageMap &= VDDByte;
- //
- // Create the Dimms map
- //
- // Node: 1 0
- // Dct: 1 0 1 0
- // Dimm: 3210 3210 3210 3210
- // Dimmbitmap: xxxx xxxx xxxx xxxx
- // Ex. 0000 0001 0010 0000 (V1_2XDimmMap)
- // This indicates Node0/Dct1/Dimm1 and Node1/Dct0/Dimm0 are 1.2XV supported.
- if ((VDDByte & (UINT8) (1 << VOLT1_25)) != 0) {
- V1_2XDimmMap |= (UINT32) DimmMask << ((Node * NBPtr->MCTPtr->DctCount + Dct) * MAX_DIMMS_PER_CHANNEL);
- } else if ((VDDByte & (UINT8) (1 << VOLT1_35)) != 0) {
- V1_35DimmMap |= (UINT32) DimmMask << ((Node * NBPtr->MCTPtr->DctCount + Dct) * MAX_DIMMS_PER_CHANNEL);
- } else {
- V1_5DimmMap |= (UINT32) DimmMask << ((Node * NBPtr->MCTPtr->DctCount + Dct) * MAX_DIMMS_PER_CHANNEL);
- }
- } // if DIMM present
- } // Dimm loop
- } // Channel loop
- } // DCT loop
- }
-
- if (VoltageMap != 0xFF) {
- if (VoltageMap == 0) {
- NBPtr->RefPtr->DDR3Voltage = VOLT1_35;
- if (V1_35DimmMap != 0) {
- i = (UINT8) LibAmdBitScanForward (V1_35DimmMap);
- } else {
- i = (UINT8) LibAmdBitScanForward (V1_2XDimmMap);
- }
- } else {
- NBPtr->RefPtr->DDR3Voltage = (DIMM_VOLTAGE) LibAmdBitScanReverse (VoltageMap);
- i = (UINT8) LibAmdBitScanForward (V1_2XDimmMap | V1_35DimmMap | V1_5DimmMap);
- // In case of 1.35V Dimms and 1.5V Dimms mixture, we initialize the 1.35V Dimm.
- if ((V1_35DimmMap != 0) && (V1_5DimmMap != 0)) {
- NBPtr->RefPtr->DDR3Voltage = VOLT1_35;
- i = (UINT8) LibAmdBitScanForward (V1_35DimmMap);
- }
- }
- // Find out which Dimm we are going to initialize and which Node/Dct it belongs to
- NBPtr->DimmToBeUsed = i % MAX_DIMMS_PER_CHANNEL;
- Node = i / (NBPtr->MCTPtr->DctCount * MAX_DIMMS_PER_CHANNEL);
- Dct = (i / MAX_DIMMS_PER_CHANNEL) & (NBPtr->MCTPtr->DctCount - 1);
- NBPtr->SwitchNodeRec (NBPtr, Node);
- NBPtr->SwitchDCT (NBPtr, Dct);
- }
-
- // If we have DIMMs, some further general characteristics checking
- if (NBPtr->DimmToBeUsed == _UNDEF_) {
- // Leave with an error - no dimms on this DCT
- // LibAmdEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND, 0, NBPtr->Dct, NBPtr->Channel, 0); //@attention commented out since it is not defined in recovery code
- SetMemRecError (AGESA_FATAL, MCTPtr);
- }
-
- return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.h b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.h
deleted file mode 100644
index 1159bf9..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrtspd3.h
- *
- * Technology SPD support for DDR3 Recovery
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MTSPD3_H_
-#define _MTSPD3_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*===============================================================================
- * Jedec DDR III
- *===============================================================================
- */
-#define SPD_BYTE_USED 0
-#define SPD_TYPE 2 /* SPD byte read location */
-#define JED_DDR_SDRAM 7 /* Jedec defined bit field */
-#define JED_DDR2_SDRAM 8 /* Jedec defined bit field */
-#define JED_DDR3SDRAM 0xB /* Jedec defined bit field */
-
-#define SPD_DIMM_TYPE 3
-#define SPD_ATTRIB 21
-#define JED_DIF_CK_MSK 0x20 /* Differential Clock Input */
-#define JED_RDIMM 1
-#define JED_MINIRDIMM 5
-#define JED_UDIMM 2
-#define JED_SODIMM 3
-
-#define SPD_L_BANKS 4 /* [7:4] number of [logical] banks on each device */
-#define SPD_DENSITY 4 /* bit 3:0 */
-#define SPD_ROW_SZ 5 /* bit 5:3 */
-#define SPD_COL_SZ 5 /* bit 2:0 */
-#define SPD_MNVVDD 6
-#define SPD_RANKS 7 /* bit 5:3 */
-#define SPD_DEV_WIDTH 7 /* bit 2:0 */
-#define SPD_ECCBITS 8 /* bit 4:3 */
-#define JED_ECC 8
-#define SPD_RAWCARD 62 /* bit 2:0 */
-#define SPD_ADDRMAP 63 /* bit 0 */
-
-#define SPD_CTLWRD03 70 /* bit 7:4 */
-#define SPD_CTLWRD04 71 /* bit 3:0 */
-#define SPD_CTLWRD05 71 /* bit 7:4 */
-
-#define SPD_DIVIDENT 10
-#define SPD_DIVISOR 11
-
-#define SPD_TCK 12
-#define SPD_CASLO 14
-#define SPD_CASHI 15
-#define SPD_TAA 16
-
-#define SPD_TRP 20
-#define SPD_TRRD 19
-#define SPD_TRCD 18
-#define SPD_TRAS 22
-#define SPD_TWR 17
-#define SPD_TWTR 26
-#define SPD_TRTP 27
-#define SPD_TRC 23
-#define SPD_UPPER_TRC 21 /* bit 7:4 */
-#define SPD_UPPER_TRAS 21 /* bit 3:0 */
-#define SPD_TFAW 29
-#define SPD_UPPER_TFAW 28 /* bit 3:0 */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-
-#endif /* _MTSPD3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c
deleted file mode 100644
index 068c926..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c
+++ /dev/null
@@ -1,347 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrttwl3.c
- *
- * Technology Phy assisted write levelization for recovery DDR3
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "Ids.h"
-#include "mm.h"
-#include "mn.h"
-#include "mru.h"
-#include "mt.h"
-#include "mrt3.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define MAX_BYTELANES 8 /* Max Bytelanes per channel */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-VOID
-STATIC
-MemRecTPrepareDIMMs3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN BOOLEAN Wl
- );
-
-VOID
-STATIC
-MemRecTProcConfig3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-VOID
-STATIC
-MemRecTBeginWLTrain3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function executed hardware based write levelization for a specific die
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-VOID
-MemRecTTrainDQSWriteHw3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
-
- // Disable auto refresh by configuring F2x[1, 0]8C[DisAutoRefresh] = 1.
- NBPtr->SetBitField (NBPtr, BFDisAutoRefresh, 1);
- // Disable ZQ calibration short command by configuring F2x[1, 0]94[ZqcsInterval] = 00b.
- NBPtr->SetBitField (NBPtr, BFZqcsInterval, 0);
-
- // 1. Specify the target Dimm that is to be trained by programming
- // F2x[1, 0]9C_x08[TrDimmSel].
- NBPtr->SetBitField (NBPtr, BFTrDimmSel, NBPtr->DimmToBeUsed);
-
- // 2. Prepare the DIMMs for write levelization using DDR3-defined
- // MR commands.
- MemRecTPrepareDIMMs3 (TechPtr, TRUE);
-
- // 3. After the DIMMs are configured, BIOS waits 40 MEMCLKs to
- // satisfy DDR3-defined internal DRAM timing.
- MemRecUWait10ns (10, NBPtr->MemPtr);
-
- // 4. Configure the processor's DDR phy for write levelization training:
- MemRecTProcConfig3 (TechPtr);
-
- // 5. Begin write levelization training
- MemRecTBeginWLTrain3 (TechPtr);
-
- // 6. Configure DRAM Phy Control Register so that the phy stops driving write levelization ODT.
- // Program WrLvOdtEn=0
- NBPtr->SetBitField (NBPtr, BFWrLvOdtEn, 0);
-
- // Wait 10 MEMCLKs to allow for ODT signal settling.
- MemRecUWait10ns (3, NBPtr->MemPtr);
-
- // 7. Program the target Dimm back to normal operation
- MemRecTPrepareDIMMs3 (TechPtr, FALSE);
-
- // 13.Program F2x[1, 0]8C[DisAutoRefresh] = 0.
- NBPtr->SetBitField (NBPtr, BFDisAutoRefresh, 0);
- // 14.Program F2x[1, 0]94[ZqcsInterval] to the proper interval for the current memory configuration.
- NBPtr->SetBitField (NBPtr, BFZqcsInterval, 2);
-
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function prepares the DIMMS for Write Levelization
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] Wl - Indicates if WL mode should be enabled
- *
- */
-
-VOID
-STATIC
-MemRecTPrepareDIMMs3 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN BOOLEAN Wl
- )
-{
- UINT8 ChipSel;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
-
- AGESA_TESTPOINT (TpProcMemWlPrepDimms, &(NBPtr->MemPtr->StdHeader));
-
- for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel++) {
- // Set Dram ODT based on current mode.
- if ((NBPtr->DCTPtr->Timings.CsPresent & (UINT16) 1 << ChipSel) != 0) {
- if (Wl) {
- NBPtr->SetDramOdtRec (NBPtr, WRITE_LEVELING_MODE, ChipSel, (NBPtr->DimmToBeUsed << 1));
- } else {
- NBPtr->SetDramOdtRec (NBPtr, MISSION_MODE, 0, 0);
- }
-
- NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel);
-
- // Set MR1 to F2x7C[MrsAddress], F2x7C[MrsBank]=1
- MemRecTEMRS13 (TechPtr);
- // Program Level
- if (Wl) {
- if ((ChipSel >> 1) == NBPtr->DimmToBeUsed) {
- NBPtr->SetBitField (NBPtr, BFLevel, 1);
- if (ChipSel & 1) {
- NBPtr->SetBitField (NBPtr, BFMrsQoff, 1);
- }
- }
- }
- // Send command
- NBPtr->SendMrsCmd (NBPtr);
-
- // Set MR2 to F2x7C[MrsAddress], F2x7C[MrsBank]=1
- MemRecTEMRS23 (TechPtr);
- // Send command
- NBPtr->SendMrsCmd (NBPtr);
- }
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function configures the DIMMS for Write Levelization
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-VOID
-STATIC
-MemRecTProcConfig3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- MEM_NB_BLOCK *NBPtr;
- CH_DEF_STRUCT *ChannelPtr;
- UINT8 ByteLane;
- UINT8 *Seed;
- UINT8 DefaultSeed;
- UINT8 CurrentSeed;
- UINT8 Dimm;
-
- NBPtr = TechPtr->NBPtr;
- ChannelPtr = TechPtr->NBPtr->ChannelPtr;
-
- Dimm = NBPtr->DimmToBeUsed;
-
- // Program WrLvOdtEn=1
- NBPtr->SetBitField (NBPtr, BFWrLvOdtEn, 1);
-
- // Wait 10 MEMCLKs to allow for ODT signal settling.
- MemRecUWait10ns (3, NBPtr->MemPtr);
-
- // Program an initialization Value to registers F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52 to set
- // the gross and fine delay for all the byte lane fields. If the target frequency is different than 400MHz,
- // BIOS must execute two training passes for each Dimm. For pass 1 at a 400MHz MEMCLK frequency,
- // use an initial total delay Value of 01Fh. This represents a 1UI (UI=.5MEMCLK) delay and is determined
- // by design.
-
- // Get default seed
- if (ChannelPtr->RegDimmPresent != 0) {
- DefaultSeed = 0x41;
- } else if (ChannelPtr->SODimmPresent != 0) {
- DefaultSeed = 0x12;
- } else {
- DefaultSeed = 0x1A;
- }
-
- // Get platform override seed
- Seed = (UINT8 *) MemRecFindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_WL_SEED, NBPtr->MCTPtr->SocketId, ChannelPtr->ChannelID);
-
- for (ByteLane = 0; ByteLane < 8; ByteLane++) {
- // This includes ECC as byte 8
- CurrentSeed = ((Seed != NULL) ? Seed[ByteLane] : DefaultSeed);
- NBPtr->SetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), CurrentSeed);
- ChannelPtr->WrDqsDlys[Dimm * MAX_BYTELANES + ByteLane] = CurrentSeed;
- }
-
- // Program F2x[1, 0]9C_x08[WrtLvTrMode]=0 for phy assisted training.
-
- // Program F2x[1, 0]9C_x08[TrNibbleSel]=0
-
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function begins WL training for a specific DIMM
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-VOID
-STATIC
-MemRecTBeginWLTrain3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- MEM_NB_BLOCK *NBPtr;
- UINT8 ByteLane;
- UINT8 Seed;
- UINT8 Delay;
- UINT8 Dimm;
-
- NBPtr = TechPtr->NBPtr;
-
- Dimm = NBPtr->DimmToBeUsed;
- // Program F2x[1, 0]9C_x08[WrtLlTrEn]=1.
- NBPtr->SetBitField (NBPtr, BFWrtLvTrEn, 1);
-
- // Wait 200 MEMCLKs. If executing pass 2, wait 32 MEMCLKs.
- MemRecUWait10ns (50, NBPtr->MemPtr);
-
- // Program F2x[1, 0]9C_x08[WrtLlTrEn]=0.
- NBPtr->SetBitField (NBPtr, BFWrtLvTrEn, 0);
-
- // Read from registers F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52 to get the gross and fine Delay settings
- // for the target Dimm and save these values.
- for (ByteLane = 0; ByteLane < 8; ByteLane++) {
- // This includes ECC as byte 8
- Seed = NBPtr->ChannelPtr->WrDqsDlys[(Dimm * MAX_BYTELANES) + ByteLane];
- Delay = (UINT8)NBPtr->GetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (Dimm, ByteLane));
- if (((Seed >> 5) == 0) && ((Delay >> 5) == 3)) {
- // If seed has gross delay of 0 and PRE has gross delay of 3,
- // then round the total delay of TxDqs to 0.
- Delay = 0;
- }
- NBPtr->SetTrainDly (NBPtr, AccessWrDqsDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), Delay);
- NBPtr->ChannelPtr->WrDqsDlys[(Dimm * MAX_BYTELANES) + ByteLane] = Delay;
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Tech/mrtthrc.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Tech/mrtthrc.c
deleted file mode 100644
index 0964a53..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Tech/mrtthrc.c
+++ /dev/null
@@ -1,287 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrtthrc.c
- *
- * Phy assisted DQS receiver enable training
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "OptionMemory.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mrport.h"
-#include "mm.h"
-#include "mn.h"
-#include "mru.h"
-#include "mt.h"
-#include "PlatformMemoryConfiguration.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_RECOVERY_MEM_TECH_MRTTHRC_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define MAX_BYTELANES 8 /* Max Bytelanes per channel */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-VOID
-STATIC
-MemRecTPrepareRcvrEnDlySeed (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 ChipSel
- );
-
-UINT16
-STATIC
-MemRecTProgramRcvrEnDly (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 ChipSel
- );
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function executes Phy assisted receiver enable training for current node.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @pre Auto refresh and ZQCL must be disabled
- *
- */
-VOID
-MemRecTTrainRcvrEnHw (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT8 TempBuffer[64];
- UINT8 Count;
- UINT32 TestAddrRJ16;
- UINT8 ChipSel;
- UINT16 MaxRcvrDly;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
-
- AGESA_TESTPOINT (TpProcMemReceiverEnableTraining , &(NBPtr->MemPtr->StdHeader));
-
- // Set environment settings before training
- MemRecTBeginTraining (TechPtr);
-
- ChipSel = NBPtr->DimmToBeUsed << 1;
- TestAddrRJ16 = 1 << 21;
-
- // 1.Prepare the DIMMs for training
- NBPtr->SetBitField (NBPtr, BFTrDimmSel, ChipSel >> 1);
-
- // 2.Prepare the phy for DQS receiver enable training.
- MemRecTPrepareRcvrEnDlySeed (TechPtr, ChipSel);
-
- // 3.BIOS initiates the phy assisted receiver enable training
- NBPtr->SetBitField (NBPtr, BFDqsRcvTrEn, 1);
-
- // 4.BIOS begins sending out of back-to-back reads to create
- // a continuous stream of DQS edges on the DDR interface.
- for (Count = 0; Count < 3; Count++) {
- NBPtr->ReadPattern (NBPtr, TempBuffer, TestAddrRJ16, 64);
- }
-
- // 6.Wait 200 MEMCLKs.
- MemRecUWait10ns (200, NBPtr->MemPtr);
-
- // 7.Program [DqsRcvTrEn]=0 to stop the DQS receive enable training.
- NBPtr->SetBitField (NBPtr, BFDqsRcvTrEn, 0);
-
- // 8.Get the gross and fine delay values.
- // 9.Calculate the corresponding final delay values
- MaxRcvrDly = MemRecTProgramRcvrEnDly (TechPtr, ChipSel);
-
- // Set Max Latency for both channels
- NBPtr->SetMaxLatency (NBPtr, MaxRcvrDly);
-
- // Restore environment settings after training
- MemRecTEndTraining (TechPtr);
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function calculates RcvEn seed value for each rank
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] ChipSel - rank to be trained
- *
- */
-VOID
-STATIC
-MemRecTPrepareRcvrEnDlySeed (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 ChipSel
- )
-{
- MEM_NB_BLOCK *NBPtr;
- CH_DEF_STRUCT *ChannelPtr;
- UINT16 SeedTotal;
- UINT16 SeedFine;
- UINT16 SeedGross;
- UINT16 SeedPreGross;
- UINT16 DiffSeedGrossSeedPreGross;
- UINT8 ByteLane;
- UINT16 *PlatEstSeed;
-
- NBPtr = TechPtr->NBPtr;
- ChannelPtr = TechPtr->NBPtr->ChannelPtr;
-
- // Get platform override seed
- PlatEstSeed = (UINT16 *) MemRecFindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_RXEN_SEED, NBPtr->MCTPtr->SocketId, ChannelPtr->ChannelID);
-
- for (ByteLane = 0; ByteLane < 8; ByteLane++) {
- // For Pass1, BIOS starts with the delay value obtained from the first pass of write
- // levelization training that was done in DDR3 Training and add a delay value of 3Bh.
- SeedTotal = ChannelPtr->WrDqsDlys[((ChipSel >> 1) * MAX_BYTELANES) + ByteLane] + (PlatEstSeed != NULL) ? PlatEstSeed[ByteLane] : 0x3B;
- // SeedGross = SeedTotal DIV 32.
- SeedGross = (SeedTotal & 0x60) >> 5;
- // SeedFine = SeedTotal MOD 32.
- SeedFine = SeedTotal & 0x1F;
-
- // Next, determine the gross component of SeedTotal. SeedGrossPass1=SeedTotal DIV 32.
- // Then, determine the fine delay component of SeedTotal. SeedFinePass1=SeedTotal MOD 32.
- // Use SeedGrossPass1 to determine SeedPreGrossPass1:
-
- if ((SeedGross & 0x1) != 0) {
- //if SeedGross is odd
- SeedPreGross = 1;
- } else {
- //if SeedGross is even
- SeedPreGross = 2;
- }
-
- // (SeedGross - SeedPreGross)
- DiffSeedGrossSeedPreGross = SeedGross - SeedPreGross;
-
- ChannelPtr->RcvEnDlys[(ChipSel * MAX_BYTELANES) + ByteLane] = DiffSeedGrossSeedPreGross << 5;
-
- //BIOS programs registers F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52) with SeedPreGrossPass1
- //and SeedFinePass1 from the preceding steps.
- NBPtr->SetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (ChipSel >> 1, ByteLane), (SeedPreGross << 5) | SeedFine);
-
- // 202688: Program seed value to RcvEnDly also.
- NBPtr->SetTrainDly (NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (ChipSel >> 1, ByteLane), SeedGross << 5);
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function calculates final RcvrEnDly for each rank
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] ChipSel - Rank to be trained
- *
- * @return MaxDly - The largest delay value
- *
- */
-UINT16
-STATIC
-MemRecTProgramRcvrEnDly (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 ChipSel
- )
-{
- MEM_NB_BLOCK *NBPtr;
- CH_DEF_STRUCT *ChannelPtr;
- UINT16 DiffSeedGrossSeedPreGross;
- UINT8 ByteLane;
- UINT16 RcvEnDly;
- UINT16 MaxDly;
- NBPtr = TechPtr->NBPtr;
- ChannelPtr = TechPtr->NBPtr->ChannelPtr;
- MaxDly = 0;
- for (ByteLane = 0; ByteLane < 8; ByteLane++) {
- DiffSeedGrossSeedPreGross = (ChannelPtr->RcvEnDlys[(ChipSel * MAX_BYTELANES) + ByteLane]) & 0x1E0;
- RcvEnDly = (UINT8) NBPtr->GetTrainDly (NBPtr, AccessPhRecDly, DIMM_BYTE_ACCESS (ChipSel >> 1, ByteLane));
-
- RcvEnDly = RcvEnDly + DiffSeedGrossSeedPreGross;
-
- // Add 1 UI to get to the midpoint of preamble
- RcvEnDly += 0x20;
-
- if (RcvEnDly > MaxDly) {
- MaxDly = RcvEnDly;
- }
-
- NBPtr->SetTrainDly (NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS ((ChipSel >> 1), ByteLane), RcvEnDly);
- }
-
- return MaxDly;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Tech/mrttpos.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Tech/mrttpos.c
deleted file mode 100644
index dda47ec..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Tech/mrttpos.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mttpos.c
- *
- * Technology DQS R/W position training. Recovery
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-
-#include "AGESA.h"
-#include "amdlib.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function hard-codes DQS position delays for all bytes
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-VOID
-MemRecTTrainDQSPosSw (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- //Hard Code Settings
- MemRecTSetWrDatRdDqs (TechPtr, 0x0F);
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Tech/mrttsrc.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Tech/mrttsrc.c
deleted file mode 100644
index a9adf79..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/Tech/mrttsrc.c
+++ /dev/null
@@ -1,437 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrttsrc.c
- *
- * Technology Software based DQS receiver enable training Recovery
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 38442 $ @e \$Date: 2010-09-24 06:39:57 +0800 (Fri, 24 Sep 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "OptionMemory.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mrport.h"
-#include "mm.h"
-#include "mn.h"
-#include "mru.h"
-#include "mt.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define MAX_BYTELANES 8 /* Max Bytelanes per channel */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
-VOID
-STATIC
-MemRecTSetRcvrEnDly (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Receiver,
- IN UINT16 RcvEnDly
- );
-
-VOID
-STATIC
-MemRecTLoadRcvrEnDly (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Receiver
- );
-
-BOOLEAN
-STATIC
-MemRecTSaveRcvrEnDly (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Receiver,
- IN UINT16 RcvEnDly,
- IN UINT8 CmpResult
- );
-
-UINT8
-STATIC
-MemRecTCompare1ClPattern (
- IN UINT8 Buffer[],
- IN UINT8 Pattern[],
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function executes receiver enable training for BSP
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-VOID
-MemRecTTrainRcvrEnSw (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- _16BYTE_ALIGN UINT8 PatternBuffer[3 * 64];
- UINT8 TestBuffer[120];
- UINT8 *PatternBufPtr[2];
- UINT32 TestAddr[4];
- UINT8 TestResult;
- UINT8 Receiver;
- UINT8 i;
- UINT8 j;
- UINT16 RcvrEnDly;
-
- MEM_DATA_STRUCT *MemPtr;
- DIE_STRUCT *MCTPtr;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
- MemPtr = NBPtr->MemPtr;
- MCTPtr = NBPtr->MCTPtr;
-
- AGESA_TESTPOINT (TpProcMemReceiverEnableTraining, &(MemPtr->StdHeader));
-
- // Set environment settings before training
- MemRecTBeginTraining (TechPtr);
-
- PatternBufPtr[0] = PatternBuffer;
- MemRecUFillTrainPattern (TestPattern0, PatternBufPtr[0], 64, &(MemPtr->StdHeader));
- PatternBufPtr[1] = PatternBufPtr[0] + 128;
- MemRecUFillTrainPattern (TestPattern1, PatternBufPtr[1], 64, &(MemPtr->StdHeader));
-
- // Begin receiver enable training
- MemRecTSetWrDatRdDqs (TechPtr, 0);
-
- // there are four receiver pairs, loosely associated with chipselects.
- Receiver = NBPtr->DimmToBeUsed << 1;
- TechPtr->DqsRcvEnSaved = 0;
-
- TestAddr[0] = NBPtr->GetSysAddrRec (NBPtr);
- TestAddr[1] = TestAddr[0] + BIGPAGE_X8;
-
- IDS_HDT_CONSOLE (MEM_FLOW, "\tDct %d\n", NBPtr->Dct);
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCS %d\n", Receiver);
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tWrite to addresses: %04x0000\n", TestAddr[0]);
-
- // Sweep receiver enable delays
- AGESA_TESTPOINT (TpProcMemRcvrStartSweep, &(MemPtr->StdHeader));
- for (RcvrEnDly = 0; RcvrEnDly < 0xFF; RcvrEnDly++) {
-
- TestResult = 0xFF;
- for (i = 0; i < 2; i++) {
-
- // Set RcvrEn delay for all byte lanes
- AGESA_TESTPOINT (TpProcMemRcvrSetDelay, &(MemPtr->StdHeader));
- MemRecTSetRcvrEnDly (TechPtr, Receiver, RcvrEnDly);
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tDly %3x", RcvrEnDly);
-
- // Swap the test pointers such that even and odd steps alternate.
- j = ((RcvrEnDly & 1) != 0) ? (i ^ 1) : i;
-
- // Write, read and compare the first beat of data
- AGESA_TESTPOINT (TpProcMemRcvrWritePattern, &(MemPtr->StdHeader));
- MemRecUWrite1CL (TestAddr[j], PatternBufPtr[j]);
- AGESA_TESTPOINT (TpProcMemRcvrReadPattern, &(MemPtr->StdHeader));
- MemRecURead1CL (TestBuffer, TestAddr[j]);
- AGESA_TESTPOINT (TpProcMemRcvrTestPattern, &(MemPtr->StdHeader));
- TestResult &= MemRecTCompare1ClPattern (TestBuffer, PatternBufPtr[j], &(MemPtr->StdHeader));
- MemRecUProcIOClFlush (TestAddr[j], MemPtr);
- }
-
- if (MemRecTSaveRcvrEnDly (TechPtr, Receiver, RcvrEnDly, TestResult)) {
- // if all bytelanes pass
- break;
- }
- } // End of delay sweep
-
- if (RcvrEnDly == 0xFF) {
- // no passing window
- // LibAmdEventLog (AGESA_ERROR, MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW, 0, NBPtr->Dct, NBPtr->Channel, 0); //@attention commented out since it is not defined in recovery code
- SetMemRecError (AGESA_ERROR, MCTPtr);
- }
-
- // set final delays
- MemRecTLoadRcvrEnDly (TechPtr, Receiver);
-
- // Clear training bit when done
- NBPtr->SetBitField (NBPtr, BFDqsRcvEnTrain, 0);
-
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\tMaxRcvrEnDly: %03x\n", RcvrEnDly + 0x20);
-
- // Set Max Latency for both channels
- NBPtr->SetMaxLatency (NBPtr, RcvrEnDly + 0x20);
-
- // Restore environment settings after training
- MemRecTEndTraining (TechPtr);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * If WrDatDly is 0, this function sets the DQS Positions in preparation
- * for Receiver Enable Training. (Write Position is no delay, Read Position is 1.5 Memclock delay).
- * Otherwise it will set WrDat and RdDqs to center of data eye.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] WrDatDly - either 0 or 0x0F
- *
- */
-
-VOID
-MemRecTSetWrDatRdDqs (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 WrDatDly
- )
-{
- UINT8 ByteLane;
- UINT8 Dimm;
- UINT8 WrDqs;
- UINT8 RdDqs;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
-
- Dimm = NBPtr->DimmToBeUsed;
- for (ByteLane = 0; ByteLane < 8; ByteLane++) {
- WrDqs = NBPtr->ChannelPtr->WrDqsDlys[(Dimm * MAX_BYTELANES) + ByteLane];
- NBPtr->SetTrainDly (NBPtr, AccessWrDatDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), WrDqs + WrDatDly);
- RdDqs = (WrDatDly == 0) ? 0x2F : 0x0F;
- NBPtr->SetTrainDly (NBPtr, AccessRdDqsDly, DIMM_BYTE_ACCESS (Dimm, ByteLane), RdDqs);
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function programs DqsRcvEnDly to additional index for DQS receiver enabled training
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] Receiver - Current Chip select value
- * @param[in] RcvEnDly - receiver enable delay to be saved
- *
- */
-
-VOID
-STATIC
-MemRecTSetRcvrEnDly (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Receiver,
- IN UINT16 RcvEnDly
- )
-{
- UINT8 ByteLane;
-
- ASSERT (Receiver <= MAX_CS_PER_CHANNEL);
- for (ByteLane = 0; ByteLane < 8; ByteLane++) {
- TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Receiver >> 1, ByteLane), RcvEnDly);
- }
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function compares test pattern with data in buffer and return a pass/fail bitmap
- * for 8 Bytes
- *
- * @param[in] Buffer[] - Buffer data from DRAM (Measured data from DRAM) to compare
- * @param[in] Pattern[] - Pattern (Expected data in ROM/CACHE) to compare against
- * @param[in,out] StdHeader - The Pointer of AGESA Header.
- *
- * @return PASS - Bit map of results of comparison
- */
-
-UINT8
-STATIC
-MemRecTCompare1ClPattern (
- IN UINT8 Buffer[],
- IN UINT8 Pattern[],
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT8 i;
- UINT8 Pass;
-
- Pass = 0xFF;
- IDS_HDT_CONSOLE (MEM_FLOW, " -");
- for (i = 0; i < 8; i++) {
- if (Buffer[i] != Pattern[i]) {
- // if bytelane n fails
- Pass &= ~((UINT16) 1 << (i % 8)); // clear bit n
- }
- IDS_HDT_CONSOLE (MEM_FLOW, " %c", (Buffer[i] == Pattern[i]) ? 'P' : '.');
- }
-
- IDS_HDT_CONSOLE_DEBUG_CODE (
- IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t -");
- for (i = 0; i < 8; i++) {
- IDS_HDT_CONSOLE (MEM_FLOW, " %02x", Buffer[i]);
- }
- IDS_HDT_CONSOLE (MEM_FLOW, "\n\t\t\t -");
- for (i = 0; i < 8; i++) {
- IDS_HDT_CONSOLE (MEM_FLOW, " %02x", Pattern[i]);
- }
- IDS_HDT_CONSOLE (MEM_FLOW, "\n\n");
- );
-
- return Pass;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function saves passing DqsRcvEnDly values to the stack
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] Receiver - Current Chip select value
- * @param[in] RcvEnDly - receiver enable delay to be saved
- * @param[in] CmpResult - compare result for Rank 0
- *
- * @return TRUE - All bytelanes pass
- * @return FALSE - Some bytelanes fail
- */
-
-BOOLEAN
-STATIC
-MemRecTSaveRcvrEnDly (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Receiver,
- IN UINT16 RcvEnDly,
- IN UINT8 CmpResult
- )
-{
- UINT8 i;
- UINT8 Passed;
- UINT8 Saved;
- UINT8 Mask;
- UINT8 Dimm;
-
- ASSERT (Receiver <= MAX_CS_PER_CHANNEL);
-
- Passed = CmpResult;
- Saved = (UINT8) (TechPtr->DqsRcvEnSaved & Passed); //@todo - false passes filter (subject to be replaced with a better solution)
- Dimm = Receiver >> 1;
- Mask = 1;
- for (i = 0; i < 8; i++) {
- if ((Passed & Mask) != 0) {
- if ((Saved & Mask) == 0) {
- TechPtr->NBPtr->ChannelPtr->RcvEnDlys[Dimm * MAX_BYTELANES + i] = (UINT8) (RcvEnDly + 0x20);
- IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tBL %d = %02x", i, RcvEnDly + 0x20);
- }
- Saved |= Mask;
- }
- Mask <<= 1;
- }
- TechPtr->DqsRcvEnSaved = Saved;
-
- if (Saved == 0xFF) {
- return TRUE;
- } else {
- return FALSE;
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function loads the DqsRcvEnDly from saved data and program to additional index
- * for DQS receiver enabled training
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] Receiver - Current Chip select value
- *
- */
-
-VOID
-STATIC
-MemRecTLoadRcvrEnDly (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 Receiver
- )
-{
- UINT8 i;
- UINT8 Dimm;
- UINT16 Saved;
- CH_DEF_STRUCT *ChannelPtr;
-
- ASSERT (Receiver <= MAX_CS_PER_CHANNEL);
- ChannelPtr = TechPtr->NBPtr->ChannelPtr;
-
- Dimm = Receiver >> 1;
- Saved = TechPtr->DqsRcvEnSaved;
- for (i = 0; i < 8; i++) {
- if ((Saved & 1) != 0) {
- TechPtr->NBPtr->SetTrainDly (TechPtr->NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Receiver >> 1, i),
- ChannelPtr->RcvEnDlys[Dimm * MAX_BYTELANES + i]);
- }
- Saved >>= 1;
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/mrdef.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/mrdef.c
deleted file mode 100644
index 1d64e9e..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/mrdef.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mdef.c
- *
- * Memory Controller header file
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-#include "AGESA.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_RECOVERY_MEM_MRDEF_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This is the default return function
- */
-
-VOID
-MemRecDefRet ()
-{
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function is the default return function that returns TRUE
- *
- */
-BOOLEAN
-MemRecDefTrue ()
-{
- return TRUE;
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function programs the DCT with initial values
- *
- *
- * @param[in,out] *MCTPtr - Pointer to the DIE_STRUCT
- * @param[in] Errorval - Error value
- */
-
-VOID
-SetMemRecError (
- IN AGESA_STATUS Errorval,
- IN OUT DIE_STRUCT *MCTPtr
- )
-{
- if (MCTPtr->ErrCode < Errorval) {
- MCTPtr->ErrCode = Errorval;
- }
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/mrinit.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/mrinit.c
deleted file mode 100644
index b2970ff..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/mrinit.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrinit.c
- *
- * Initializer support functions for Recovery mode
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-#include "AGESA.h"
-#include "OptionMemory.h"
-#include "Ids.h"
-#include "mm.h"
-#include "ma.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_RECOVERY_MEM_MRINIT_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-extern PSO_TABLE DefaultPlatformMemoryConfiguration[];
-extern MEM_PLATFORM_CFG* memRecPlatformTypeInstalled[];
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function initializes the default parameter, function pointers, build options
- * and SPD data for memory configuration
- *
- * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
- *
- */
-
-VOID
-AmdMemInitDataStructDefRecovery (
- IN OUT MEM_DATA_STRUCT *MemPtr
- )
-{
- MEM_PARAMETER_STRUCT *RefPtr;
- UINT8 i;
- UINT8 p;
-
- RefPtr = MemPtr->ParameterListPtr;
-
- // Memory Map/Mgt.
- // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB
- RefPtr->BottomIo = 0xF0;
-
- RefPtr->PlatformMemoryConfiguration = DefaultPlatformMemoryConfiguration;
-
- i = 0;
- for (p = 0; p < MAX_PLATFORM_TYPES; p++) {
- if (memRecPlatformTypeInstalled[i] != NULL) {
- MemPtr->GetPlatformCfg[p] = memRecPlatformTypeInstalled[i];
- i++;
- } else {
- MemPtr->GetPlatformCfg[p] = MemRecNGetPsCfgDef;
- }
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/mrm.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/mrm.c
deleted file mode 100644
index ce9cb65..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/mrm.c
+++ /dev/null
@@ -1,288 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrm.c
- *
- * Main configuration for Recovery mode
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "amdlib.h"
-#include "GeneralServices.h"
-#include "heapManager.h"
-#include "cpuServices.h"
-#include "OptionMemoryRecovery.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_RECOVERY_MEM_MRM_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-#define MAX_DIES_PER_SOCKET 2
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-extern MEM_REC_NB_CONSTRUCTOR* MemRecNBInstalled[];
-extern MEM_REC_TECH_CONSTRUCTOR* MemRecTechInstalled[];
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-VOID
-STATIC
-MemRecSPDDataProcess (
- IN OUT MEM_DATA_STRUCT *MemPtr
- );
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function is the Recovery memory configuration function for HY DDR3
- *
- * Requirements:
- *
- * Run-Time Requirements:
- * 1. Complete Hypertransport Bus Configuration
- * 2. AmdMemInitDataStructDef must be run to set default values
- * 3. MSR bit to allow access to high PCI regs set on all nodes
- * 4. BSP in Big Real Mode
- * 5. Stack available
- * 6. MCG_CTL=-1, MC4_EN=0 for all CPUs
- * 7. MCi_STS from shutdown/warm reset recorded (if desired) prior to entry
- * 8. All var MTRRs reset to zero
- * 9. State of NB_CFG.DisDatMsk set properly on all CPUs
- *
- * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
- *
- * @return AGESA_STATUS
- * - AGESA_ALERT
- * - AGESA_FATAL
- * - AGESA_SUCCESS
- * - AGESA_WARNING
- */
-
-AGESA_STATUS
-AmdMemRecovery (
- IN OUT MEM_DATA_STRUCT *MemPtr
- )
-{
- UINT8 Socket;
- UINT8 Module;
- UINT8 i;
- AGESA_STATUS AgesaStatus;
- PCI_ADDR Address;
- MEM_NB_BLOCK NBBlock;
- MEM_TECH_BLOCK TechBlock;
- LOCATE_HEAP_PTR SocketWithMem;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
-
- //
- // Read SPD data
- //
- MemRecSPDDataProcess (MemPtr);
-
- //
- // Get the socket id from heap.
- //
- SocketWithMem.BufferHandle = AMD_REC_MEM_SOCKET_HANDLE;
- if (HeapLocateBuffer (&SocketWithMem, &MemPtr->StdHeader) == AGESA_SUCCESS) {
- Socket = *(UINT8 *) SocketWithMem.BufferPtr;
- } else {
- ASSERT(FALSE); // Socket handle not found
- return AGESA_FATAL;
- }
-
- //
- // Allocate buffer for memory init structures
- //
- AllocHeapParams.RequestedBufferSize = MAX_DIES_PER_SOCKET * sizeof (DIE_STRUCT);
- AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_DIE_STRUCT_HANDLE, 0, 0, 0);
- AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
- if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) != AGESA_SUCCESS) {
- ASSERT(FALSE); // Heap allocation failed to allocate Die struct
- return AGESA_FATAL;
- }
- MemPtr->DiesPerSystem = (DIE_STRUCT *)AllocHeapParams.BufferPtr;
-
- //
- // Discover populated CPUs
- //
- for (Module = 0; Module < MAX_DIES_PER_SOCKET; Module++) {
- if (GetPciAddress ((VOID *)MemPtr, Socket, Module, &Address, &AgesaStatus)) {
- MemPtr->DiesPerSystem[Module].SocketId = Socket;
- MemPtr->DiesPerSystem[Module].DieId = Module;
- MemPtr->DiesPerSystem[Module].PciAddr.AddressValue = Address.AddressValue;
- }
- }
-
- i = 0;
- while (MemRecNBInstalled[i] != NULL) {
- if (MemRecNBInstalled[i] (&NBBlock, MemPtr, 0) == TRUE) {
- break;
- }
- i++;
- };
- if (MemRecNBInstalled[i] == NULL) {
- ASSERT(FALSE); // No NB installed
- return AGESA_FATAL;
- }
- MemRecTechInstalled[0] (&TechBlock, &NBBlock);
- NBBlock.TechPtr = &TechBlock;
-
- return NBBlock.InitRecovery (&NBBlock);
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function fills a default SPD buffer with SPD values for all DIMMs installed in the system
- *
- * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT
- *
- */
-
-VOID
-STATIC
-MemRecSPDDataProcess (
- IN OUT MEM_DATA_STRUCT *MemPtr
- )
-{
- BOOLEAN FindSocketWithMem;
- UINT8 Channel;
- UINT8 Dimm;
- UINT8 MaxSockets;
- UINT8 *SocketWithMem;
- UINT8 Socket;
- AGESA_STATUS AgesaStatus;
- SPD_DEF_STRUCT *DimmSPDPtr;
- ALLOCATE_HEAP_PARAMS AllocHeapParams;
- AGESA_READ_SPD_PARAMS SpdParam;
- ASSERT (MemPtr != NULL);
- FindSocketWithMem = FALSE;
- //
- // Allocate heap to save socket number with memory on it.
- //
- AllocHeapParams.RequestedBufferSize = sizeof (UINT8);
- AllocHeapParams.BufferHandle = AMD_REC_MEM_SOCKET_HANDLE;
- AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
- if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) == AGESA_SUCCESS) {
- SocketWithMem = (UINT8 *) AllocHeapParams.BufferPtr;
- *SocketWithMem = 0;
-
- //
- // Allocate heap for the table
- //
- MaxSockets = (UINT8) GetPlatformNumberOfSockets ();
-
- AllocHeapParams.RequestedBufferSize = (MaxSockets * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL * sizeof (SPD_DEF_STRUCT));
- AllocHeapParams.BufferHandle = AMD_MEM_SPD_HANDLE;
- AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
- if (HeapAllocateBuffer (&AllocHeapParams, &MemPtr->StdHeader) == AGESA_SUCCESS) {
- MemPtr->SpdDataStructure = (SPD_DEF_STRUCT *) AllocHeapParams.BufferPtr;
- //
- // Initialize SpdParam Structure
- //
- LibAmdMemCopy ((VOID *)&SpdParam, (VOID *)MemPtr, (UINTN)sizeof (SpdParam.StdHeader), &MemPtr->StdHeader);
- //
- // Populate SPDDataBuffer
- //
-
- SpdParam.MemData = MemPtr;
- for (Socket = 0; Socket < MaxSockets; Socket ++) {
- SpdParam.SocketId = Socket;
- for (Channel = 0; Channel < MAX_CHANNELS_PER_SOCKET; Channel++) {
- SpdParam.MemChannelId = Channel;
- for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) {
- SpdParam.DimmId = Dimm;
- DimmSPDPtr = &(MemPtr->SpdDataStructure[(Socket * MAX_CHANNELS_PER_SOCKET + Channel) * MAX_DIMMS_PER_CHANNEL + Dimm]);
- SpdParam.Buffer = DimmSPDPtr->Data;
- AgesaStatus = AgesaReadSpdRecovery (0, &SpdParam);
- if (AgesaStatus == AGESA_SUCCESS) {
- DimmSPDPtr->DimmPresent = TRUE;
- if (!FindSocketWithMem) {
- FindSocketWithMem = TRUE;
- }
- } else {
- DimmSPDPtr->DimmPresent = FALSE;
- }
- }
- }
- if (FindSocketWithMem) {
- *SocketWithMem = Socket;
- break;
- }
- }
- }
- }
-}
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/mrport.h b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/mrport.h
deleted file mode 100644
index 41b82b5..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/mrport.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mport.h
- *
- * API's to support different OS
- *
- * A detailed description, giving important information about this file.
- * Omit the detailed description if none is needed. For other than the
- * simplest files, there should be one.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Memory
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-#ifndef _MPORT_H_
-#define _MPORT_H_
-
-///< 64 bit data structure
-///< lo - Lower 32 bits
-///< hi - Upper 32 bits
-typedef struct _S_UINT64 {
- UINT32 lo; ///< Lower 32 bits
- UINT32 hi; ///< Upper 32 bits
-} S_UINT64;
-/*
- * SBDFO - Segment Bus Device Function Offset
- * 31:28 Segment (4-bits)
- * 27:20 Bus (8-bits)
- * 19:15 Device (5-bits)
- * 14:12 Function(3-bits)
- * 11:00 Offset (12-bits)
- */
-typedef UINT32 SBDFO;
-
-//#define MAKE_SBDFO(seg,bus,dev,fun,off) ((((UINT32)(seg))<<28) | (((UINT32)(bus))<<20) | \
-// (((UINT32)(dev))<<15) | (((UINT32)(fun))<<12) | ((UINT32)(off)))
-//#define SBDFO_SEG(x) (((UINT32)(x)>>28) & 0x0F)
-//#define SBDFO_BUS(x) (((UINT32)(x)>>20) & 0xFF)
-//#define SBDFO_DEV(x) (((UINT32)(x)>>15) & 0x1F)
-//#define SBDFO_FUN(x) (((UINT32)(x)>>12) & 0x07)
-//#define SBDFO_OFF(x) (((UINT32)(x)) & 0xFFF)
-//#define ILLEGAL_SBDFO 0xFFFFFFFF
-
-
-#define GET_SIZE_OF(x) (sizeof (x) / sizeof (x[0]))
-
-#endif /* _MPORT_H_ */
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/mrt3.h b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/mrt3.h
deleted file mode 100644
index 478dc2b..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/mrt3.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mrt3.h
- *
- * Common Technology Recovery
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MRT3_H_
-#define _MRT3_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-VOID
-MemRecTTrainDQSWriteHw3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-VOID
-MemRecTDramInitSw3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemRecTSetDramMode3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemRecTDIMMPresence3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-VOID
-MemRecTEMRS13 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-VOID
-MemRecTEMRS23 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-VOID
-MemRecTEMRS33 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-VOID
-MemRecTMRS3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-VOID
-MemRecTDramControlRegInit3 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-#endif /* _MRT3_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/mru.asm b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/mru.asm
deleted file mode 100644
index 56db233..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/mru.asm
+++ /dev/null
@@ -1,187 +0,0 @@
-;*****************************************************************************
-; AMD Generic Encapsulated Software Architecture
-;
-; $Workfile:: mu.asm $ $Revision:: 237#$ $Date: 2009-12-10 07:28:37 +0800 (Thu, 10 Dec 2009) $
-; Description: Main memory controller system configuration for AGESA DDR 2
-;
-;
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-;============================================================================
-
-
- .XLIST
- .LIST
- .686p
- .MODEL FLAT
- .CODE
- ASSUME FS: NOTHING
-
-
-; Define the calling convention used for the C library modules
-;@attention - This should be in a central include file
-CALLCONV EQU NEAR C
-
-
-;===============================================================================
-;MemRecUOutPort:
-;
-; Do a 32 Bit IO Out operation using edx.
-; NOTE: This function will be obsolete in the future.
-;
-; In: Port - port number
-; Value - value to be written to port
-;
-; Out:
-;
-;All registers preserved except for "Out:"
-;===============================================================================
-MemRecUOutPort PROC CALLCONV PUBLIC Port:DWORD, Value:DWORD
- pushad
- mov edx,Port
- mov eax,Value
- out dx,al
- popad
- ret
-MemRecUOutPort ENDP
-
-
-
-;----------------------------------------------------------------------------
-; _MFENCE();
-;
-_MFENCE macro
- db 0Fh,0AEh,0F0h
- endm
-
-;----------------------------------------------------------------------------
-; _EXECFENCE();
-;
-_EXECFENCE macro
- out 0EDh,al ;prevent speculative execution of following instructions
- endm
-
-;===============================================================================
-;MemRecUWrite1CL:
-;
-; Write data from buffer to a system address
-;
-; In: Address - System address to read from
-; Pattern - pointer pattern.
-;
-; Out:
-;
-;All registers preserved except for "Out:"
-;===============================================================================
-MemRecUWrite1CL PROC CALLCONV PUBLIC Address:DWORD, Pattern:NEAR PTR DWORD
- pushad
- push ds
-
- mov eax,Address
- push ss
- pop ds
- xor edx,edx
- mov edx, DWORD PTR Pattern
- mov esi,edx
- mov edx,16
- _EXECFENCE
- mov ecx,4
- @@:
- db 66h,0Fh,6Fh,06 ;MOVDQA xmm0,[esi]
- db 64h,66h,0Fh,0E7h,00 ;MOVNTDQ fs:[eax],xmm0 (xmm0 is 128 bits)
- add eax,edx
- add esi,edx
- loop @B
-
- pop ds
- popad
- ret
-MemRecUWrite1CL ENDP
-
-;===============================================================================
-;MemRecURead1CL:
-;
-; Read one cacheline to buffer
-;
-; In: Buffer - pointer buffer.
-; : Address - System address to read from
-;
-; Out:
-;
-;All registers preserved except for "Out:"
-;===============================================================================
-MemRecURead1CL PROC CALLCONV PUBLIC Buffer:NEAR PTR DWORD, Address:DWORD
-
- pushad
-
- mov esi,Address
- xor edx,edx
- mov edx,DWORD PTR Buffer
- mov edi,edx
- mov ecx,64
- @@:
- mov al,fs:[esi]
- mov ss:[edi],al
- inc esi
- inc edi
- loop @B
-
- popad
- ret
-MemRecURead1CL ENDP
-
-
-;===============================================================================
-;MemRecUFlushPattern:
-;
-; Flush one cache line
-;
-; In: Address - System address [31:0]
-; Out:
-;
-;All registers preserved except for "Out:"
-;===============================================================================
-MemRecUFlushPattern PROC CALLCONV PUBLIC Address:DWORD
- pushad
- mov eax,Address
- _EXECFENCE
- ;clflush fs:[eax]
- db 064h ;access relative to FS BASE prefix
- db 00Fh ;opcode
- db 0AEh ;opcode
- db 038h ;eax indirect addressing
- _MFENCE
- popad
- ret
-MemRecUFlushPattern ENDP
-
-
-
- END
-
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/mru.h b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/mru.h
deleted file mode 100644
index 27ba336..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/mru.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mru.h
- *
- * Utility support Recovery
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MRU_H_
-#define _MRU_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-#ifndef PSO_ENTRY
- #define PSO_ENTRY UINT8
-#endif
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/// Test patterns for DQS training
-typedef enum {
- TestPattern0, ///< Test pattern used in first pass of receiver enable training
- TestPattern1, ///< Test pattern used in first pass of receiver enable training
- TestPattern2, ///< Test pattern used in second pass of receiver enable training
- TestPatternJD1B, ///< 72-bit test pattern used in position training (ganged mode)
- TestPatternJD1A, ///< 72-bit test pattern used in position training
- TestPatternML ///< Test pattern used in first pass of max latency training
-} TRAIN_PATTERN;
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-VOID
-MemRecUWrite1CL (
- IN UINT32 Address,
- IN UINT8 Pattern[]
- );
-
-VOID
-MemRecURead1CL (
- IN UINT8 Buffer[],
- IN UINT32 Address
- );
-
-VOID
-MemRecUFlushPattern (
- IN UINT32 Address
- );
-
-VOID
-MemRecUFillTrainPattern (
- IN TRAIN_PATTERN Pattern,
- IN UINT8 Buffer[],
- IN UINT16 Size,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-MemRecUProcIOClFlush (
- IN UINT32 Address,
- IN OUT MEM_DATA_STRUCT *MemPtr
- );
-
-VOID
-MemRecUWait10ns (
- IN UINT32 Count,
- IN OUT MEM_DATA_STRUCT *MemPtr
- );
-
-VOID *
-MemRecFindPSOverrideEntry (
- IN PSO_TABLE *PlatformMemoryConfiguration,
- IN PSO_ENTRY EntryType,
- IN UINT8 SocketID,
- IN UINT8 ChannelID
- );
-
-UINT8
-RecGetMaxDimmsPerChannel (
- IN PSO_TABLE *PlatformMemoryConfiguration,
- IN UINT8 SocketID,
- IN UINT8 ChannelID
- );
-
-#endif /* _MRU_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/mruc.c b/src/vendorcode/amd/agesa/Proc/Recovery/Mem/mruc.c
deleted file mode 100644
index 95fc64b..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/Mem/mruc.c
+++ /dev/null
@@ -1,267 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mruc.c
- *
- * Utility functions recovery
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Proc/Recovery/Mem)
- * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
- *
- **/
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-#include "AGESA.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mrport.h"
-#include "mru.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_RECOVERY_MEM_MRUC_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-VOID
-STATIC
-MemRecUResetTargetWTIO (
- IN OUT MEM_DATA_STRUCT *MemPtr
- );
-
-VOID
-STATIC
-MemRecUSetTargetWTIO (
- IN UINT32 Address,
- IN OUT MEM_DATA_STRUCT *MemPtr
- );
-
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function returns the (Index)th UINT8
- * from an indicated test Pattern.
- *
- * @param[in] Pattern - encoding of test Pattern type
- * @param[in] Buffer[] - buffer to be filled
- * @param[in] Size - Size of the bugger
- * @param[in] *StdHeader - pointer to AMD_CONFIG_PARAMS
- *
- */
-
-VOID
-MemRecUFillTrainPattern (
- IN TRAIN_PATTERN Pattern,
- IN UINT8 Buffer[],
- IN UINT16 Size,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- STATIC UINT8 PatternData[2] = {0x55, 0xAA};
-
- LibAmdMemFill (Buffer, PatternData[Pattern == TestPattern0 ? TestPattern1 : TestPattern0], Size, StdHeader);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function flushes cache lines
- *
- * @param[in] Address - System Address [39:8]
- * @param[in,out] *MemPtr - Pointer to MEM_DATA_STRUCT
- *
- */
-
-VOID
-MemRecUProcIOClFlush (
- IN UINT32 Address,
- IN OUT MEM_DATA_STRUCT *MemPtr
- )
-{
- MemRecUSetTargetWTIO (Address, MemPtr);
- MemRecUFlushPattern (Address);
- MemRecUResetTargetWTIO (MemPtr);
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function resets the target address space to Write Through IO by disabling IORRs
- */
-
-VOID
-STATIC
-MemRecUResetTargetWTIO (
- IN OUT MEM_DATA_STRUCT *MemPtr
- )
-{
- S_UINT64 Smsr;
- Smsr.hi = 0;
- Smsr.lo = 0;
- LibAmdMsrWrite (IORR0_MASK, (UINT64 *)&Smsr, &MemPtr->StdHeader);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the target range to WT IO (using an IORR overlapping
- * the already existing
- * @param[in,out] *MemPtr - pointer to MEM_DATA_STRUCTURE
- * @param[in] Address - System Address
- *
- */
-
-VOID
-STATIC
-MemRecUSetTargetWTIO (
- IN UINT32 Address,
- IN OUT MEM_DATA_STRUCT *MemPtr
- )
-{
- S_UINT64 SMsr;
-
- SMsr.lo = Address;
- SMsr.hi = 0;
- LibAmdMsrWrite (IORR0_BASE,(UINT64 *)&SMsr, &MemPtr->StdHeader); // ;IORR0 Base
- SMsr.hi = 0xFFFF;
- SMsr.lo = 0xFC000800;
- LibAmdMsrWrite (IORR0_MASK, (UINT64 *)&SMsr, &MemPtr->StdHeader); // ;64MB Mask
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Waits specified number of 10ns cycles
- * @param[in,out] MemPtr - pointer to MEM_DATA_STRUCTURE
- * @param[in] Count - Number of 10ns cycles to wait
- *
- */
-
-VOID
-MemRecUWait10ns (
- IN UINT32 Count,
- IN OUT MEM_DATA_STRUCT *MemPtr
- )
-{
- S_UINT64 SMsr;
-
- LibAmdMsrRead (TSC, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- Count += SMsr.lo;
- while (SMsr.lo < Count) {
- LibAmdMsrRead (TSC, (UINT64 *)&SMsr, &MemPtr->StdHeader);
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Find the entry of platform specific overriding table.
- *
- * @param[in] PlatformMemoryConfiguration - Platform config table
- * @param[in] EntryType - Entry type
- * @param[in] SocketID - Physical socket ID
- * @param[in] ChannelID - Physical channel ID
- *
- * @return NULL - entry could not be found.
- * @return Pointer - points to the entry's data.
- *
- * ----------------------------------------------------------------------------
- */
-VOID *
-MemRecFindPSOverrideEntry (
- IN PSO_TABLE *PlatformMemoryConfiguration,
- IN PSO_ENTRY EntryType,
- IN UINT8 SocketID,
- IN UINT8 ChannelID
- )
-{
- UINT8 *Buffer;
-
- Buffer = PlatformMemoryConfiguration;
- while (Buffer[0] != PSO_END) {
- if (Buffer[0] == EntryType) {
- if ((Buffer[2] & ((UINT8) 1 << SocketID)) != 0 ) {
- if ((Buffer[3] & ((UINT8) 1 << ChannelID)) != 0 ) {
- ASSERT ((Buffer[0] == PSO_MAX_DIMMS) ? (Buffer[4] <= MAX_DIMMS_PER_CHANNEL) : TRUE);
- ASSERT ((Buffer[0] == PSO_MAX_CHIPSELS) ? (Buffer[4] <= MAX_CS_PER_CHANNEL) : TRUE);
- ASSERT ((Buffer[0] == PSO_MAX_CHNLS) ? (Buffer[4] <= MAX_CHANNELS_PER_SOCKET) : TRUE);
- return &Buffer[4];
- }
- }
- }
- Buffer += Buffer[1] + 2;
- }
- return NULL;
-}
-
diff --git a/src/vendorcode/amd/agesa/Proc/Recovery/recoveryPage.h b/src/vendorcode/amd/agesa/Proc/Recovery/recoveryPage.h
deleted file mode 100644
index 110f248..0000000
--- a/src/vendorcode/amd/agesa/Proc/Recovery/recoveryPage.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * Create outline and references for Recovery Component mainpage documentation.
- *
- * Design guides, maintenance guides, and general documentation, are
- * collected using this file onto the documentation mainpage.
- * This file contains doxygen comment blocks, only.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Documentation
- * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
- *
- */
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-/**
- * @page recoverymain Recovery Component Documentation
- *
- * Additional documentation for the Recovery component consists of
- *
- * - Maintenance Guides:
- * - add here >>>
- * - Design Guides:
- * - add here >>>
- *
- */
diff --git a/src/vendorcode/amd/agesa/cpcar.inc b/src/vendorcode/amd/agesa/cpcar.inc
deleted file mode 100644
index b9aaa91..0000000
--- a/src/vendorcode/amd/agesa/cpcar.inc
+++ /dev/null
@@ -1,1124 +0,0 @@
-;*****************************************************************************
-; AMD Generic Encapsulated Software Architecture
-;
-; $Workfile:: cpcar.inc
-;
-; Description: CPCAR.INC - AGESA cache-as-RAM setup Include File
-;
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
-BSP_STACK_BASE_ADDR EQU 30000h ; Base address for primary cores stack
-BSP_STACK_SIZE EQU 10000h ; 64KB for BSP core
-CORE0_STACK_BASE_ADDR EQU 80000h ; Base address for primary cores stack
-CORE0_STACK_SIZE EQU 4000h ; 16KB for primary cores
-CORE1_STACK_BASE_ADDR EQU 40000h ; Base address for AP cores
-CORE1_STACK_SIZE EQU 1000h ; 4KB for each AP cores
-
-APIC_BASE_ADDRESS EQU 0000001Bh
- APIC_BSC EQU 8 ; Boot Strap Core
-
-AMD_MTRR_VARIABLE_BASE0 EQU 0200h
-AMD_MTRR_VARIABLE_BASE6 EQU 020Ch
-AMD_MTRR_FIX64k_00000 EQU 0250h
-AMD_MTRR_FIX16k_80000 EQU 0258h
-AMD_MTRR_FIX16k_A0000 EQU 0259h
-AMD_MTRR_FIX4k_C0000 EQU 0268h
-AMD_MTRR_FIX4k_C8000 EQU 0269h
-AMD_MTRR_FIX4k_D0000 EQU 026Ah
-AMD_MTRR_FIX4k_D8000 EQU 026Bh
-AMD_MTRR_FIX4k_E0000 EQU 026Ch
-AMD_MTRR_FIX4k_E8000 EQU 026Dh
-AMD_MTRR_FIX4k_F0000 EQU 026Eh
-AMD_MTRR_FIX4k_F8000 EQU 026Fh
-
-AMD_MTRR_DEFTYPE EQU 02FFh
- WB_DRAM_TYPE EQU 1Eh ; MemType - memory type
- MTRR_DEF_TYPE_EN EQU 11 ; MtrrDefTypeEn - variable and fixed MTRRs default enabled
- MTRR_DEF_TYPE_FIX_EN EQU 10 ; MtrrDefTypeEn - fixed MTRRs default enabled
-
-HWCR EQU 0C0010015h ; Hardware Configuration
- INVD_WBINVD EQU 4 ; INVD to WBINVD conversion
-
-IORR_BASE EQU 0C0010016h ; IO Range Regusters Base/Mask, 2 pairs
- ; uses 16h - 19h
-TOP_MEM EQU 0C001001Ah ; Top of Memory
-TOP_MEM2 EQU 0C001001Dh ; Top of Memory2
-
-LS_CFG EQU 0C0011020h ; Load-Store Configuration
- DIS_SS EQU 28 ; Family 10h,12h,15h:Disable Streaming Store functionality
- DIS_STREAM_ST EQU 28 ; Family 14h:DisStreamSt - Disable Streaming Store functionality
-
-IC_CFG EQU 0C0011021h ; Instruction Cache Config Register
- IC_DIS_SPEC_TLB_RLD EQU 9 ; Disable speculative TLB reloads
- DIS_IND EQU 14 ; Family 10-14h:Disable Indirect Branch Predictor
- DIS_I_CACHE EQU 14 ; Family 15h:DisICache - Disable Indirect Branch Predictor
-
-DC_CFG EQU 0C0011022h ; Data Cache Configuration
- DC_DIS_SPEC_TLB_RLD EQU 4 ; Disable speculative TLB reloads
- DIS_CLR_WBTOL2_SMC_HIT EQU 8 ; self modifying code check buffer bit
- DIS_HW_PF EQU 13 ; Hardware prefetches bit
-
-DE_CFG EQU 0C0011029h ; Decode Configuration
- CL_FLUSH_SERIALIZE EQU 23 ; Family 12h,15h: CL Flush Serialization
-
-BU_CFG2 EQU 0C001102Ah ; Family 10h: Bus Unit Configuration 2
-CU_CFG2 EQU 0C001102Ah ; Family 15h: Combined Unit Configuration 2
- F10_CL_LINES_TO_NB_DIS EQU 15 ; ClLinesToNbDis - allows WP code to be cached in L2
- IC_DIS_SPEC_TLB_WR EQU 35 ; IcDisSpecTlbWr - ITLB speculative writes
-
-CU_CFG3 EQU 0C001102Bh ; Combined Unit Configuration 3
- COMBINE_CR0_CD EQU 49 ; Combine CR0.CD for both cores of a compute unit
-
-
-CR0_PE EQU 1 ; Protection Enable
-CR0_NW EQU 29 ; Not Write-through
-CR0_CD EQU 30 ; Cache Disable
-CR0_PG EQU 31 ; Paging Enable
-
-; CPUID Functions
-
-CPUID_MODEL EQU 1
-AMD_CPUID_FMF EQU 80000001h ; Family Model Features information
-AMD_CPUID_APIC EQU 80000008h ; Long Mode and APIC info., core count
-
-NB_CFG EQU 0C001001Fh ; Northbridge Configuration Register
- INIT_APIC_ID_CPU_ID_LO EQU 54 ; InitApicIdCpuIdLo - is core# in high or low half of APIC ID?
-
-MTRR_SYS_CFG EQU 0C0010010h ; System Configuration Register
- CHX_TO_DIRTY_DIS EQU 16 ; ChxToDirtyDis Change to dirty disable
- SYS_UC_LOCK_EN EQU 17 ; SysUcLockEn System lock command enable
- MTRR_FIX_DRAM_EN EQU 18 ; MtrrFixDramEn MTRR fixed RdDram and WrDram attributes enable
- MTRR_FIX_DRAM_MOD_EN EQU 19 ; MtrrFixDramModEn MTRR fixed RdDram and WrDram modification enable
- MTRR_VAR_DRAM_EN EQU 20 ; MtrrVarDramEn MTRR variable DRAM enable
- MTRR_TOM2_EN EQU 21 ; MtrrTom2En MTRR top of memory 2 enable
-
-PERF_CONTROL3 EQU 0C0010003h ; Performance event control three
- PERF_CONTROL3_RESERVE_L EQU 00200000h ; Preserve the reserved bits
- PERF_CONTROL3_RESERVE_H EQU 0FCF0h ; Preserve the reserved bits
- CONFIG_EVENT_L EQU 0F0E2h ; All cores with level detection
- CONFIG_EVENT_H EQU 4 ; Increment count by number of event
- ; occured in clock cycle
- EVENT_ENABLE EQU 22 ; Enable the event
-PERF_COUNTER3 EQU 0C0010007h ; Performance event counter three
-
-; Local use flags, in upper most byte if ESI
-FLAG_UNKNOWN_FAMILY EQU 24 ; Signals that the family# of the installed processor is not recognized
-FLAG_STACK_REENTRY EQU 25 ; Signals that the environment has made a re-entry (2nd) call to set up the stack
-FLAG_IS_PRIMARY EQU 26 ; Signals that this core is the primary within the comoute unit
-
-; AGESA_STATUS values
-IFNDEF AGESA_SUCCESS
- AGESA_SUCCESS EQU 0
-ENDIF
-IFNDEF AGESA_WARNING
- AGESA_WARNING EQU 4
-ENDIF
-IFNDEF AGESA_FATAL
- AGESA_FATAL EQU 7
-ENDIF
-;;***************************************************************************
-;;
-;; CPU MACROS - PUBLIC
-;;
-;;***************************************************************************
-_WRMSR macro
- db 0Fh, 30h
- endm
-
-_RDMSR macro
- db 0Fh, 32h
- endm
-
-AMD_CPUID MACRO arg0
- IFB <arg0>
- mov eax, 1
- db 0Fh, 0A2h ; Execute instruction
- bswap eax
- xchg al, ah ; Ext model in al now
- rol eax, 8 ; Ext model in ah, model in al
- and ax, 0FFCFh ; Keep 23:16, 7:6, 3:0
- ELSE
- mov eax, arg0
- db 0Fh, 0A2h
- ENDIF
-ENDM
-
-
-;---------------------------------------------------
-;
-; AMD_ENABLE_STACK_FAMILY_HOOK Macro - Stackless
-;
-; Set any family specific controls needed to enable the use of
-; cache as general storage before main memory is available.
-;
-; Inputs:
-; none
-; Outputs:
-; none
-;---------------------------------------------------
-AMD_ENABLE_STACK_FAMILY_HOOK MACRO
-
- AMD_ENABLE_STACK_FAMILY_HOOK_F10
- AMD_ENABLE_STACK_FAMILY_HOOK_F12
- AMD_ENABLE_STACK_FAMILY_HOOK_F14
- AMD_ENABLE_STACK_FAMILY_HOOK_F15
-
-ENDM
-
-;----------------------------------------------
-;
-; AMD_DISABLE_STACK_FAMILY_HOOK Macro - Stackless
-;
-; Return any family specific controls to their 'standard'
-; settings for using cache with main memory.
-;
-; Inputs:
-; none
-; Outputs:
-; none
-;----------------------------------------------
-AMD_DISABLE_STACK_FAMILY_HOOK MACRO
-
- AMD_DISABLE_STACK_FAMILY_HOOK_F10
- AMD_DISABLE_STACK_FAMILY_HOOK_F12
- AMD_DISABLE_STACK_FAMILY_HOOK_F14
- AMD_DISABLE_STACK_FAMILY_HOOK_F15
-
-ENDM
-
-;---------------------------------------------------
-;
-; GET_NODE_ID_CORE_ID Macro - Stackless
-;
-; Read family specific values to determine the node and core
-; numbers for the core executing this code.
-;
-; Inputs:
-; none
-; Outputs:
-; SI[7:0] = Core# (0..N, relative to node)
-; SI[15:8]= Node# (0..N)
-; SI[23:16]= reserved
-; SI[24]= flag: 1=Family Unrecognized
-; SI[25]= flag: 1=Interface re-entry call
-; SI[26]= flag: 1=Core is primary of compute unit
-; SI[31:27]= reserved, =0
-;---------------------------------------------------
-GET_NODE_ID_CORE_ID MACRO
-
- mov si, -1
- GET_NODE_ID_CORE_ID_F10
- GET_NODE_ID_CORE_ID_F12
- GET_NODE_ID_CORE_ID_F14
- GET_NODE_ID_CORE_ID_F15
- ;
- ; Check for unrecognized Family
- ;
- .if (si == -1) ; Has family (node/core) been discovered?
- mov esi, ( (1 SHL FLAG_UNKNOWN_FAMILY)+(1 SHL FLAG_IS_PRIMARY) ) ; No, Set error code, Only let BSP continue
- mov ecx, APIC_BASE_ADDRESS ; MSR:0000_001B
- _RDMSR
- bt eax, APIC_BSC ; Is this the BSC?
- .if (!carry?)
- ; No, this is an AP
- hlt ; Kill APs
- .endif
- .endif
-ENDM
-
-
-
-
-;;***************************************************************************
-;; Family 10h MACROS
-;;***************************************************************************
-;---------------------------------------------------
-;
-; AMD_ENABLE_STACK_FAMILY_HOOK_F10 Macro - Stackless
-;
-; Set any family specific controls needed to enable the use of
-; cache as general storage before main memory is available.
-;
-; Inputs:
-; ESI - node#, core#, flags from GET_NODE_ID_CORE_ID
-; Outputs:
-; none
-;
-; Family 10h requirements (BKDG section 2.3.3):
-; * Paging disabled
-; * MSRC001_0015[INVDWBINVD]=0
-; * MSRC001_1021[DIS_IND]=1
-; * MSRC001_1021[DIS_SPEC_TLB_RLD]=1
-; * MSRC001_1022[DIS_SPEC_TLB_RLD]=1
-; * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=1
-; * MSRC001_1022[DIS_HW_PF]=1
-; * MSRC001_102A[IcDisSpecTlbWr]=1
-; * MSRC001_102A[ClLinesToNbDis]=1
-; * No INVD or WBINVD, no exceptions, page faults or interrupts
-;---------------------------------------------------
-AMD_ENABLE_STACK_FAMILY_HOOK_F10 MACRO
- local fam10_enable_stack_hook_exit
-
- AMD_CPUID CPUID_MODEL
- shr eax, 20 ; AL = cpu extended family
- cmp al, 01h ; Is this family 10h?
- jnz fam10_enable_stack_hook_exit ; Br if no
-
- mov ecx, DC_CFG ; MSR:C001_1022
- _RDMSR
- bts eax, DC_DIS_SPEC_TLB_RLD ; Turn on Disable speculative DTLB reloads bit
- bts eax, DIS_CLR_WBTOL2_SMC_HIT ; Turn on Disable the self modifying code check buffer bit
- bts eax, DIS_HW_PF ; Turn on Disable hardware prefetches bit
- _WRMSR
-
- dec cx ; MSR:C001_1021
- _RDMSR
- bts eax, IC_DIS_SPEC_TLB_RLD ; Turn on Disable speculative TLB reloads bit
- bts eax, DIS_IND ; Turn on Disable indirect branch predictor
- _WRMSR
-
- mov ecx, BU_CFG2 ; MSR C001_102A
- _RDMSR
- bts eax, F10_CL_LINES_TO_NB_DIS ; Allow BIOS ROM to be cached in the IC
- bts edx, (IC_DIS_SPEC_TLB_WR-32) ;Disable speculative writes to the ITLB
- _WRMSR
-
- mov ecx, HWCR ; MSR C001_0015
- _RDMSR
-
- bt esi, FLAG_STACK_REENTRY ; Check if stack has already been set
- .if (!carry?)
- btr eax, INVD_WBINVD ; disable INVD -> WBINVD conversion
- _WRMSR
- .endif
-
- mov eax, esi ; load core#
- .if (al == 0) ; If (BSP)
- mov ecx, PERF_COUNTER3 ; Select performance counter three
- ; to count number of CAR evictions
- xor eax, eax ; Initialize the lower part of the counter to zero
- xor edx, edx ; Initializa the upper part of the counter to zero
- _WRMSR ; Save it
- mov ecx, PERF_CONTROL3 ; Select the event control three
- _RDMSR ; Get the current setting
- and eax, PERF_CONTROL3_RESERVE_L ; Preserve the reserved bits
- or eax, CONFIG_EVENT_L ; Set the lower part of event register to
- ; select CAR Corruption occurred by any cores
- and dx, PERF_CONTROL3_RESERVE_H ; Preserve the reserved bits
- or dx, CONFIG_EVENT_H ; Set the upper part of event register
- _WRMSR ; Save it
- bts eax, EVENT_ENABLE ; Enable it
- _WRMSR ; Save it
- .endif ; endif
-
-fam10_enable_stack_hook_exit:
-ENDM
-
-;----------------------------------------------
-;
-; AMD_DISABLE_STACK_FAMILY_HOOK_F10 Macro - Stackless
-;
-; Return any family specific controls to their 'standard'
-; settings for using cache with main memory.
-;
-; Inputs:
-; ESI - [31:24] flags; [15,8]= Node#; [7,0]= core#
-; Outputs:
-; none
-;
-; Family 10h requirements:
-; * INVD or WBINVD
-; * MSRC001_0015[INVD_WBINVD]=1
-; * MSRC001_1021[DIS_IND]=0
-; * MSRC001_1021[DIS_SPEC_TLB_RLD]=0
-; * MSRC001_1022[DIS_SPEC_TLB_RLD]=0
-; * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=0
-; * MSRC001_1022[DIS_HW_PF]=0
-; * MSRC001_102A[IcDisSpecTlbWr]=0
-; * MSRC001_102A[ClLinesToNbDis]=0
-;----------------------------------------------
-AMD_DISABLE_STACK_FAMILY_HOOK_F10 MACRO
- local fam10_disable_stack_hook_exit
-
- AMD_CPUID CPUID_MODEL
- shr eax, 20 ; AL = cpu extended family
- cmp al, 01h ; Is this family 10h?
- jnz fam10_disable_stack_hook_exit ; Br if no
-
- mov ecx, DC_CFG ; MSR:C001_1022
- _RDMSR
- btr eax, DC_DIS_SPEC_TLB_RLD ; Enable speculative TLB reloads
- btr eax, DIS_CLR_WBTOL2_SMC_HIT ; Allow self modifying code check buffer
- btr eax, DIS_HW_PF ; Allow hardware prefetches
- _WRMSR
-
- dec cx ; MSR:C001_1021
- _RDMSR
- btr eax, DIS_IND ; Turn on indirect branch predictor
- btr eax, IC_DIS_SPEC_TLB_RLD ; Turn on speculative TLB reloads
- _WRMSR
-
- mov ecx, BU_CFG2 ; MSR:C001_102A
- _RDMSR
- btr eax, F10_CL_LINES_TO_NB_DIS ; Return L3 to normal mode
- btr edx, (IC_DIS_SPEC_TLB_WR-32) ;Re-enable speculative writes to the ITLB
- _WRMSR
-
- ;--------------------------------------------------------------------------
- ; Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved.
- ;--------------------------------------------------------------------------
- mov ecx, HWCR ; MSR:0000_0015
- _RDMSR
- mov bx, ax ; Save INVD -> WBINVD bit
- btr eax, INVD_WBINVD ; Disable INVD -> WBINVD conversion for the invd instruction.
- _WRMSR
- invd ; Clear the cache tag RAMs
- mov ax, bx ; Restore INVD -> WBINVD bit
- _WRMSR
-
- ;--------------------------------------------------------------------------
- ; End critical sequence in which EAX, BX, ECX, and EDX must be preserved.
- ;--------------------------------------------------------------------------
-
- mov ecx, PERF_CONTROL3 ; Select the event control three
- _RDMSR ; Retrieve the current value
- btc eax, EVENT_ENABLE ; Is event enable, complement it as well
- jnc fam10_disable_stack_hook_exit ; No
- cmp ax, CONFIG_EVENT_L ; Is the lower part of event set to capture the CAR Corruption
- jne fam10_disable_stack_hook_exit ; No
- cmp dl, CONFIG_EVENT_H ; Is the upper part of event set to capture the CAR Corruption
- jne fam10_disable_stack_hook_exit ; No
- _WRMSR ; Disable the event
-
-fam10_disable_stack_hook_exit:
-ENDM
-
-;---------------------------------------------------
-;
-; GET_NODE_ID_CORE_ID_F10 Macro - Stackless
-;
-; Read family specific values to determine the node and core
-; numbers for the core executing this code.
-;
-; Inputs:
-; none
-; Outputs:
-; SI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above)
-;---------------------------------------------------
-GET_NODE_ID_CORE_ID_F10 MACRO
-
- local node_core_f10_exit
-
- cmp si, -1 ; Has node/core already been discovered?
- jnz node_core_f10_exit ; Br if yes
-
- AMD_CPUID CPUID_MODEL
- shr eax, 20 ; AL = cpu extended family
- cmp al, 01h ; Is this family 10h?
- jnz node_core_f10_exit ; Br if no
-
- xor esi, esi ; Assume BSC, clear flags
- mov ecx, APIC_BASE_ADDRESS ; MSR:0000_001B
- _RDMSR
- bt eax, APIC_BSC ; Is this the BSC?
- .if (carry?)
- ; This is the BSP.
- ; Enable routing tables on BSP (just in case the HT init code has not yet enabled them)
- mov eax, 8000C06Ch ; PCI address for D18F0x6C Link Initialization Control Register
- mov dx, 0CF8h
- out dx, eax
- add dx, 4
- in eax, dx
- btr eax, 0 ; Set LinkInitializationControl[RouteTblDis] = 0
- out dx, eax
- .else
- ; This is an AP. Routing tables have been enabled by the HT Init process.
- ; Also, the MailBox register was set by the BSP during early init
- ; The Mailbox register content is formatted as follows:
- ; UINT32 Node:4; // The node id of Core's node.
- ; UINT32 Socket:4; // The socket of this Core's node.
- ; UINT32 Module:2; // The internal module number for Core's node.
- ; UINT32 ModuleType:2; // Single Module = 0, Multi-module = 1.
- ; UINT32 :20; // Reserved
- ;
- mov ecx, 0C0000408h ; Read the family 10h mailbox
- _RDMSR ; MC4_MISC1[63:32]
- mov si, dx ; SI = raw mailbox contents (will extract node# from this)
- shr ebx, 24 ; BL = CPUID Fn0000_0001_EBX[LocalApicId]
- mov di, bx ; DI = Initial APIC ID (will extract core# from this)
-
- AMD_CPUID AMD_CPUID_APIC ;
- shr ch, 4 ; CH = ApicIdSize, #bits in APIC ID that show core#
- inc cl ; CL = Number of enabled cores in the socket
- mov bx, cx
-
- mov ecx, NB_CFG ; MSR:C001_001F
- _RDMSR ; EDX has InitApicIdCpuIdLo bit
-
- mov cl, bh ; CL = APIC ID size
- mov al, 1 ; Convert APIC ID size to an AND mask
- shl al, cl ; AL = 2^APIC ID size
- dec al ; AL = mask for relative core number
- xor ah, ah ; AX = mask for relative core number
- bt edx, (INIT_APIC_ID_CPU_ID_LO-32) ; InitApicIdCpuIdLo == 1?
- .if (!carry?) ; Br if yes
- mov ch, 8 ; Calculate core number shift count
- sub ch, cl ; CH = core shift count
- mov cl, ch
- shr di, cl ; Right justify core number
- .endif
- and di, ax ; DI = socket-relative core number
-
- mov cx, si ; CX = raw mailbox value
- shr cx, 10 ; CL[1:0] = ModuleType or #nodes per socket (0-SCM, 1-MCM)
- and cl, 3 ; Isolate ModuleType
- xor bh, bh ; BX = Number of enabled cores in the socket
- shr bx, cl ; BX = Number of enabled cores per node
- xor dx, dx ; Clear upper word for div
- mov ax, di ; AX = socket-relative core number
- div bx ; DX = node-relative core number
- movzx eax, si ; prepare return value (clears flags)
- and ax, 000Fh ; AX = node number
- shl ax, 8 ; [15:8]=node#
- mov al, dl ; [7:0]=core# (relative to node)
- mov esi, eax ; ESI = return value
- .endif ; end: Is_AP
- bts esi, FLAG_IS_PRIMARY ; all Family 10h cores are primary
-
-node_core_f10_exit:
-ENDM
-
-
-;;***************************************************************************
-;; Family 12h MACROS
-;;***************************************************************************
-;---------------------------------------------------
-;
-; AMD_ENABLE_STACK_FAMILY_HOOK_F12 Macro - Stackless
-;
-; Set any family specific controls needed to enable the use of
-; cache as general storage before main memory is available.
-;
-; Inputs:
-; ESI - node#, core#, flags from GET_NODE_ID_CORE_ID
-; Outputs:
-; none
-;
-; Family 12h requirements (BKDG section 2.3.3):
-; The following requirements must be satisfied prior to using the cache as general storage:
-; * Paging must be disabled.
-; * MSRC001_0015[INVD_WBINVD]=0
-; * MSRC001_1020[DIS_SS]=1
-; * MSRC001_1021[DIS_SPEC_TLB_RLD]=1
-; * MSRC001_1022[DIS_SPEC_TLB_RLD]=1
-; * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=1
-; * MSRC001_1022[DIS_HW_PF]=1
-; * MSRC001_1029[ClflushSerialize]=1
-; * No INVD or WBINVD, no exceptions, page faults or interrupts
-;---------------------------------------------------
-AMD_ENABLE_STACK_FAMILY_HOOK_F12 MACRO
- local fam12_enable_stack_hook_exit
-
- AMD_CPUID CPUID_MODEL
- shr eax, 20 ; AL = cpu extended family
- cmp al, 03h ; Is this family 12h?
- jnz fam12_enable_stack_hook_exit ; Br if no
-
- mov ecx, DC_CFG ; MSR:C001_1022
- _RDMSR
- bts eax, DC_DIS_SPEC_TLB_RLD ; Disable speculative DC-TLB reloads
- bts eax, DIS_CLR_WBTOL2_SMC_HIT ; Disable self modifying code check buffer
- bts eax, DIS_HW_PF ; Disable hardware prefetches
- _WRMSR
-
- dec cx ;IC_CFG ; MSR:C001_1021
- _RDMSR
- bts eax, IC_DIS_SPEC_TLB_RLD ; Disable speculative IC-TLB reloads
- _WRMSR
-
- dec cx ;LS_CFG ; MSR:C001_1020
- _RDMSR
- bts eax, DIS_SS ; Disabled Streaming store functionality
- _WRMSR
-
- mov ecx, HWCR ; MSR C001_0015
- _RDMSR
- bt esi, FLAG_STACK_REENTRY ; Check if stack has already been set
- .if (!carry?)
- btr eax, INVD_WBINVD ; disable INVD -> WBINVD conversion
- _WRMSR
- .endif
-
- mov ecx, DE_CFG ; MSR:C001_1029
- _RDMSR
- bts eax, CL_FLUSH_SERIALIZE ; Serialize all CL Flush actions
- _WRMSR
-
-fam12_enable_stack_hook_exit:
-ENDM
-
-;----------------------------------------------
-;
-; AMD_DISABLE_STACK_FAMILY_HOOK_F12 Macro - Stackless
-;
-; Return any family specific controls to their 'standard'
-; settings for using cache with main memory.
-;
-; Inputs:
-; ESI - [31:24] flags; [15,8]= Node#; [7,0]= core#
-; Outputs:
-; none
-;
-; Family 12h requirements:
-; * INVD or WBINVD
-; * MSRC001_0015[INVD_WBINVD]=1
-; * MSRC001_1020[DIS_SS]=0
-; * MSRC001_1021[DIS_SPEC_TLB_RLD]=0
-; * MSRC001_1022[DIS_SPEC_TLB_RLD]=0
-; * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=0
-; * MSRC001_1022[DIS_HW_PF]=0
-; * MSRC001_1029[ClflushSerialize]=0
-;---------------------------------------------------
-AMD_DISABLE_STACK_FAMILY_HOOK_F12 MACRO
- local fam12_disable_stack_hook_exit
-
- AMD_CPUID CPUID_MODEL
- shr eax, 20 ; AL = cpu extended family
- cmp al, 03h ; Is this family 12h?
- jnz fam12_disable_stack_hook_exit ; Br if no
-
- mov ecx, DC_CFG ; MSR:C001_1022
- _RDMSR
- btr eax, DC_DIS_SPEC_TLB_RLD ; Turn on speculative DC-TLB reloads
- btr eax, DIS_CLR_WBTOL2_SMC_HIT ; Enable self modifying code check buffer
- btr eax, DIS_HW_PF ; Enable Hardware prefetches
- _WRMSR
-
- dec cx ;IC_CFG ; MSR:C001_1021
- _RDMSR
- btr eax, IC_DIS_SPEC_TLB_RLD ; Turn on speculative IC-TLB reloads
- _WRMSR
-
- dec cx ;LS_CFG ; MSR:C001_1020
- _RDMSR
- btr eax, DIS_SS ; Turn on Streaming store functionality
- _WRMSR
-
- mov ecx, DE_CFG ; MSR:C001_1029
- _RDMSR
- btr eax, CL_FLUSH_SERIALIZE
- _WRMSR
-
- ;--------------------------------------------------------------------------
- ; Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved.
- ;--------------------------------------------------------------------------
-
- mov ecx, HWCR ; MSR:0000_0015h
- _RDMSR
- mov bx, ax ; Save INVD -> WBINVD bit
- btr eax, INVD_WBINVD ; Disable INVD -> WBINVD conversion
- _WRMSR
- invd ; Clear the cache tag RAMs
- mov ax, bx ; Restore INVD -> WBINVD bit
- _WRMSR
-
- ;--------------------------------------------------------------------------
- ; End critical sequence in which EAX, BX, ECX, and EDX must be preserved.
- ;--------------------------------------------------------------------------
-
-fam12_disable_stack_hook_exit:
-ENDM
-
-;---------------------------------------------------
-;
-; GET_NODE_ID_CORE_ID_F12 Macro - Stackless
-;
-; Read family specific values to determine the node and core
-; numbers for the core executing this code.
-;
-; Inputs:
-; none
-; Outputs:
-; SI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above)
-;---------------------------------------------------
-GET_NODE_ID_CORE_ID_F12 MACRO
-
- local node_core_f12_exit
-
- cmp si, -1 ; Has node/core already been discovered?
- jnz node_core_f12_exit ; Br if yes
-
- AMD_CPUID CPUID_MODEL
- shr eax, 20 ; AL = cpu extended family
- cmp al, 03h ; Is this family 12h?
- jnz node_core_f12_exit ; Br if no
-
- shr ebx, 24 ; CPUID_0000_0001_EBX[31:24]: initial local APIC physical ID
- bts ebx, FLAG_IS_PRIMARY ; all family 12h cores are primary
- mov esi, ebx ; ESI = Node#=0, core number
-node_core_f12_exit:
-ENDM
-
-
-;;***************************************************************************
-;; Family 14h MACROS
-;;***************************************************************************
-;---------------------------------------------------
-;
-; AMD_ENABLE_STACK_FAMILY_HOOK_F14 Macro - Stackless
-;
-; Set any family specific controls needed to enable the use of
-; cache as general storage before main memory is available.
-;
-; Inputs:
-; ESI - node#, core#, flags from GET_NODE_ID_CORE_ID
-; Outputs:
-; none
-;
-; Family 14h requirements (BKDG section 2.3.3):
-; * Paging must be disabled.
-; * MSRC001_0015[INVD_WBINVD]=0.
-; * MSRC001_1020[DisStreamSt]=1.
-; * MSRC001_1021[DIS_SPEC_TLB_RLD]=1. Disable speculative ITLB reloads.
-; * MSRC001_1022[DIS_HW_PF]=1.
-; * No INVD or WBINVD, no exceptions, page faults or interrupts
-;---------------------------------------------------
-AMD_ENABLE_STACK_FAMILY_HOOK_F14 MACRO
- local fam14_enable_stack_hook_exit
-
- AMD_CPUID CPUID_MODEL
- shr eax, 20 ; AL = cpu extended family
- cmp al, 05h ; Is this family 14h?
- jnz fam14_enable_stack_hook_exit ; Br if no
-
- mov ecx, DC_CFG ; MSR:C001_1022
- _RDMSR
- bts eax, DIS_HW_PF ; Disable hardware prefetches
- _WRMSR
-
- dec cx ;IC_CFG ; MSR:C001_1021
- _RDMSR
- bts eax, IC_DIS_SPEC_TLB_RLD ; Disable speculative TLB reloads
- _WRMSR
-
- dec cx ;LS_CFG ; MSR:C001_1020
- _RDMSR
- bts eax, DIS_STREAM_ST ; Disabled Streaming store functionality
- _WRMSR
-
- mov ecx, HWCR ; MSR C001_0015
- _RDMSR
- bt esi, FLAG_STACK_REENTRY ; Check if stack has already been set
- .if (!carry?)
- btr eax, INVD_WBINVD ; disable INVD -> WBINVD conversion
- _WRMSR
- .endif
-
-fam14_enable_stack_hook_exit:
-ENDM
-
-;----------------------------------------------
-;
-; AMD_DISABLE_STACK_FAMILY_HOOK_F14 Macro - Stackless
-;
-; Return any family specific controls to their 'standard'
-; settings for using cache with main memory.
-;
-; Inputs:
-; ESI - [31:24] flags; [15,8]= Node#; [7,0]= core#
-; Outputs:
-; none
-;
-; Family 14h requirements:
-; * INVD or WBINVD
-; * MSRC001_0015[INVD_WBINVD]=1.
-; * MSRC001_1020[DisStreamSt]=0.
-; * MSRC001_1021[DIS_SPEC_TLB_RLD]=0.
-; * MSRC001_1022[DIS_HW_PF]=0.
-;---------------------------------------------------
-AMD_DISABLE_STACK_FAMILY_HOOK_F14 MACRO
- local fam14_disable_stack_hook_exit
-
- AMD_CPUID CPUID_MODEL
- shr eax, 20 ; AL = cpu extended family
- cmp al, 05h ; Is this family 14h?
- jnz fam14_disable_stack_hook_exit ; Br if no
-
- mov ecx, LS_CFG ; MSR:C001_1020
- _RDMSR
- btr eax, DIS_STREAM_ST ; Turn on Streaming store functionality
- _WRMSR
-
- inc cx ;IC_CFG ; MSR:C001_1021
- _RDMSR
- btr eax, IC_DIS_SPEC_TLB_RLD ; Turn on speculative DC-TLB reloads
- _WRMSR
-
- inc cx ;DC_CFG ; MSR:C001_1022
- _RDMSR
- btr eax, DIS_HW_PF ; Turn on hardware prefetches
- _WRMSR
-
- ;--------------------------------------------------------------------------
- ; Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved.
- ;--------------------------------------------------------------------------
-
- mov ecx, HWCR ; MSR:C001_0015h
- _RDMSR
- btr eax, INVD_WBINVD ; Disable INVD -> WBINVD conversion
- _WRMSR
- invd ; Clear the cache tag RAMs
- bts eax, INVD_WBINVD ; Turn on Conversion of INVD to WBINVD
- _WRMSR
-
- ;--------------------------------------------------------------------------
- ; End critical sequence in which EAX, BX, ECX, and EDX must be preserved.
- ;--------------------------------------------------------------------------
-
-fam14_disable_stack_hook_exit:
-ENDM
-
-;---------------------------------------------------
-;
-; GET_NODE_ID_CORE_ID_F14 Macro - Stackless
-;
-; Read family specific values to determine the node and core
-; numbers for the core executing this code.
-;
-; Inputs:
-; none
-; Outputs:
-; SI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above)
-;---------------------------------------------------
-GET_NODE_ID_CORE_ID_F14 MACRO
-
- local node_core_f14_exit
-
- cmp si, -1 ; Has node/core already been discovered?
- jnz node_core_f14_exit ; Br if yes
-
- AMD_CPUID CPUID_MODEL
- shr eax, 20 ; AL = cpu extended family
- cmp al, 05h ; Is this family 14h?
- jnz node_core_f14_exit ; Br if no
-
- xor esi, esi ; Node must be 0
- bts esi, FLAG_IS_PRIMARY ; all family 14h cores are primary
- mov ecx, APIC_BASE_ADDRESS ; MSR:0000_001B
- _RDMSR
- bt eax, APIC_BSC ;
- .if (!carry?) ; Is this the BSC?
- ; No, this is an AP
- inc si ; Set core to 1
- .endif ;
-node_core_f14_exit:
-ENDM
-
-
-
-;;***************************************************************************
-;; Family 15h MACROS
-;;***************************************************************************
-;---------------------------------------------------
-;
-; AMD_ENABLE_STACK_FAMILY_HOOK_F15 Macro - Stackless
-;
-; Set any family specific controls needed to enable the use of
-; cache as general storage before main memory is available.
-;
-; Inputs:
-; ESI - node#, core#, flags from GET_NODE_ID_CORE_ID
-; Outputs:
-; none
-;
-; Family 15h requirements (BKDG #42301 section 2.3.3):
-; * Paging must be disabled.
-; * MSRC001_0015[INVD_WBINVD]=0
-; * MSRC001_1020[DisSS]=1
-; * MSRC001_1021[DIS_SPEC_TLB_RLD]=1
-; * MSRC001_1022[DIS_SPEC_TLB_RLD]=1
-; * MSRC001_1022[DisHwPf]=1
-; * No INVD or WBINVD, no exceptions, page faults or interrupts
-;---------------------------------------------------
-AMD_ENABLE_STACK_FAMILY_HOOK_F15 MACRO
- local fam15_enable_stack_hook_exit
-
- AMD_CPUID CPUID_MODEL
- shr eax, 20 ; AL = cpu extended family
- cmp al, 06h ; Is this family 15h?
- jnz fam15_enable_stack_hook_exit ; Br if no
-
- bt esi, FLAG_STACK_REENTRY ; Check if stack has already been set
- .if (!carry?)
- mov ecx, HWCR ; MSR C001_0015
- _RDMSR
- btr eax, INVD_WBINVD ; disable INVD -> WBINVD conversion
- _WRMSR
- .endif
-
- mov ecx, LS_CFG ; MSR:C001_1020
- _RDMSR
- bts eax, DIS_SS ; Turn on Streaming store functionality disabled bit
- _WRMSR
-
- inc ecx ;IC_CFG ; MSR:C001_1021
- _RDMSR
- bts eax, IC_DIS_SPEC_TLB_RLD ; Turn on Disable speculative IC-TLB reloads bit
- _WRMSR
-
- inc ecx ;DC_CFG ; MSR:C001_1022
- _RDMSR
- bts eax, DC_DIS_SPEC_TLB_RLD ; Turn on Disable speculative DC-TLB reloads bit
- bts eax, DIS_HW_PF ; Turn on Disable hardware prefetches bit
- _WRMSR
-
- mov ecx, CU_CFG3 ; MSR:C001_102B
- _RDMSR
- btr edx, (COMBINE_CR0_CD - 32) ; Clear CombineCr0Cd bit
- _WRMSR
-
-fam15_enable_stack_hook_exit:
-ENDM
-
-
-;----------------------------------------------
-;
-; AMD_DISABLE_STACK_FAMILY_HOOK_F15 Macro - Stackless
-;
-; Return any family specific controls to their 'standard'
-; settings for using cache with main memory.
-;
-; Inputs:
-; ESI - [31:24] flags; [15,8]= Node#; [7,0]= core#
-; Outputs:
-; none
-;
-; Family 15h requirements:
-; * INVD or WBINVD
-; * MSRC001_0015[INVD_WBINVD]=1
-; * MSRC001_1020[DisSS]=0
-; * MSRC001_1021[DIS_SPEC_TLB_RLD]=0
-; * MSRC001_1022[DIS_SPEC_TLB_RLD]=0
-; * MSRC001_1022[DIS_HW_PF]=0
-;---------------------------------------------------
-AMD_DISABLE_STACK_FAMILY_HOOK_F15 MACRO
- local fam15_disable_stack_hook_exit
-
- AMD_CPUID CPUID_MODEL
- mov ebx, eax ; Save revision info to EBX
- shr eax, 20 ; AL = cpu extended family
- cmp al, 06h ; Is this family 15h?
- jnz fam15_disable_stack_hook_exit ; Br if no
-
- mov ecx, LS_CFG ; MSR:C001_1020
- .if (ebx != 00600F00h) ; Is this rev A0?
- _RDMSR
- btr eax, DIS_SS ; Turn on Streaming store functionality
- _WRMSR
- .endif ; End workaround for errata 495 and 496
-
- inc ecx ;IC_CFG ; MSR:C001_1021
- _RDMSR
- btr eax, IC_DIS_SPEC_TLB_RLD ; Turn on speculative TLB reloads
- _WRMSR
-
- inc ecx ;DC_CFG ; MSR:C001_1022
- _RDMSR
- btr eax, DC_DIS_SPEC_TLB_RLD ; Turn on speculative TLB reloads
- .if (ebx != 00600F00h) ; Is this rev A0?
- btr eax, DIS_HW_PF ; Turn on hardware prefetches
- .endif ; End workaround for erratum 498
- _WRMSR
-
- ;--------------------------------------------------------------------------
- ; Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved.
- ;--------------------------------------------------------------------------
-
- bt esi, FLAG_IS_PRIMARY
- .if (carry?) ; Only clear cache from primary core
- mov ecx, HWCR ; MSR:C001_0015h
- _RDMSR
- btr eax, INVD_WBINVD ; Disable INVD -> WBINVD conversion
- _WRMSR
- invd ; Clear the cache tag RAMs
- bts eax, INVD_WBINVD ; Turn on Conversion of INVD to WBINVD
- _WRMSR
- .endif ; end
-
- ;--------------------------------------------------------------------------
- ; End critical sequence in which EAX, BX, ECX, and EDX must be preserved.
- ;--------------------------------------------------------------------------
-
- mov ecx, CU_CFG3 ; MSR:C001_102B
- _RDMSR
- bts edx, (COMBINE_CR0_CD - 32) ; Set CombineCr0Cd bit
- _WRMSR
-
-fam15_disable_stack_hook_exit:
-ENDM
-
-
-;---------------------------------------------------
-;
-; GET_NODE_ID_CORE_ID_F15 Macro - Stackless
-;
-; Read family specific values to determine the node and core
-; numbers for the core executing this code.
-;
-; Inputs:
-; none
-; Outputs:
-; SI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above)
-;---------------------------------------------------
-GET_NODE_ID_CORE_ID_F15 MACRO
-
- local node_core_f15_exit
-
- cmp si, -1 ; Has node/core already been discovered?
- jnz node_core_f15_exit ; Br if yes
-
- AMD_CPUID CPUID_MODEL
- shr eax, 20 ; AL = cpu extended family
- cmp al, 06h ; Is this family 15h?
- jnz node_core_f15_exit ; Br if no
-
- xor esi, esi ; Assume BSC, clear local flags
- mov ecx, APIC_BASE_ADDRESS ; MSR:0000_001B
- _RDMSR
- bt eax, APIC_BSC ; Is this the BSC?
- .if (carry?)
- ; This is the BSP.
- ; Enable routing tables on BSP (just in case the HT init code has not yet enabled them)
- mov eax, 8000C06Ch ; PCI address for D18F0x6C Link Initialization Control Register
- mov dx, 0CF8h
- out dx, eax
- add dx, 4
- in eax, dx
- btr eax, 0 ; Set LinkInitializationControl[RouteTblDis] = 0
- out dx, eax
- .else ;
- ; This is an AP. Routing tables have been enabled by the HT Init process.
- ; Also, the MailBox register was set by the BSP during early init
- ; The Mailbox register content is formatted as follows:
- ; UINT32 Node:4; // The node id of Core's node.
- ; UINT32 Socket:4; // The socket of this Core's node.
- ; UINT32 Module:2; // The internal module number for Core's node.
- ; UINT32 ModuleType:2; // Single Module = 0, Multi-module = 1.
- ; UINT32 :20; // Reserved
- ;
- mov ecx, 0C0000408h ; Read the family 15h mailbox
- _RDMSR ; MC4_MISC1[63:32]
- mov si, dx ; SI = raw mailbox contents (will extract node# from this)
- shr ebx, 24 ; BL = CPUID Fn0000_0001_EBX[LocalApicId]
- mov di, bx ; DI = Initial APIC ID (will extract core# from this)
-
- AMD_CPUID AMD_CPUID_APIC ;
- shr ch, 4 ; CH = ApicIdSize, #bits in APIC ID that show core#
- inc cl ; CL = Number of enabled cores in the socket
- mov bx, cx
-
- mov ecx, NB_CFG
- _RDMSR ; EDX has InitApicIdCpuIdLo bit
-
- mov cl, bh ; CL = APIC ID size
- mov al, 1 ; Convert APIC ID size to an AND mask
- shl al, cl ; AL = 2^APIC ID size
- dec al ; AL = mask for relative core number
- xor ah, ah ; AX = mask for relative core number
- bt edx, (INIT_APIC_ID_CPU_ID_LO-32) ; InitApicIdCpuIdLo == 1?
- .if (!carry?) ; Br if yes
- mov ch, 8 ; Calculate core number shift count
- sub ch, cl ; CH = core shift count
- mov cl, ch ;
- shr di, cl ; Right justify core number
- .endif ;
- and di, ax ; DI = socket-relative core number
-
- mov cx, si ; CX = raw mailbox value
- shr cx, 10 ; CL[1:0] = ModuleType or #nodes per socket (0-SCM, 1-MCM)
- and cl, 3 ; Isolate ModuleType
- xor bh, bh ; BX = Number of enabled cores in the socket
- shr bx, cl ; BX = Number of enabled cores per node
- xor dx, dx ; Clear upper word for div
- mov ax, di ; AX = socket-relative core number
- div bx ; DX = node-relative core number
- movzx eax, si ; Prepare return value
- and ax, 000Fh ; AX = node number
- shl ax, 8 ; [15:8]=node#
- mov al, dl ; [7:0]=core# (relative to node)
- mov esi, eax ; ESI = node-relative core number
- .endif ; end
-
- ;
- ; determine if this core shares MTRRs
- ;
- mov eax, 8000C580h ; Compute Unit Status
- mov bx, si ; load node#(bh), core#(bl)
- shl bh, 3 ; Move node# to PCI Dev# field
- add ah, bh ; Adjust PCI adress for node number
- mov dx, 0CF8h
- out dx, eax
- add dx, 4
- in eax, dx ; [3:0]=Enabled; [19:16]=DualCore
- ;
- ; BL is MyCore# , BH is primary flag
- mov cx, 06h ; Use CH as 'first of pair' core#
- .while (cl > 0)
- bt eax, 0 ; Is pair enabled?
- .if (carry?) ;
- mov bh, 01h ; flag core as primary
- bt eax, 16 ; Is there a 2nd in the pair?
- .if (carry?) ;
- .break .if (ch == bl) ; Does 1st match MyCore#?
- inc ch
- xor bh, bh ; flag core as NOT primary
- .break .if (ch == bl) ; Does 2nd match MyCore#?
- .else ; No 2nd core
- .break .if (ch == bl) ; Does 1st match MyCore#?
- .endif
- inc ch
- .endif
- shr eax, 1
- dec cl
- .endw
- .if (cl == 0)
- ;Error - core# didn't match Compute Unit Status content
- bts esi, FLAG_UNKNOWN_FAMILY
- bts esi, FLAG_IS_PRIMARY ; Set Is_Primary for unknowns
- .endif
- .if (bh != 0) ; Check state of primary for the matched core
- bts esi, FLAG_IS_PRIMARY ; Set shared flag into return value
- .endif
- ;
-node_core_f15_exit:
-ENDM
-
-
-
diff --git a/src/vendorcode/amd/agesa/cpcarmac.inc b/src/vendorcode/amd/agesa/cpcarmac.inc
deleted file mode 100644
index b703b7f..0000000
--- a/src/vendorcode/amd/agesa/cpcarmac.inc
+++ /dev/null
@@ -1,447 +0,0 @@
-;*****************************************************************************
-; AMD Generic Encapsulated Software Architecture
-;
-; Workfile: cpcarmac.inc $Revision:: 38483 $ $Date:: 2010-09-25 02:13:03 +0800 (Sat, 25 Sep 2010) $
-;
-; Description: Code to setup and break down cache-as-stack
-;
-;*****************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*****************************************************************************
-
- .XLIST
- INCLUDE cpcar.inc
- .LIST
- .586P
- .mmx
-
-;======================================================================
-; AMD_ENABLE_STACK: Setup a stack
-;
-; In:
-; EBX = Return address (preserved)
-;
-; Out:
-; SS:ESP - Our new private stack location
-;
-; EAX = AGESA_STATUS
-;
-; ECX = Stack size in bytes
-;
-; Requirements:
-; * This routine presently is limited to a max of 64 processor cores
-; Preserved:
-; ebx ebp
-; Destroyed:
-; eax, ecx, edx, edi, esi, ds, es, ss, esp
-; mmx0, mmx1
-;
-; Description:
-; Fixed MTRR address allocation to cores:
-; The BSP gets 64K of stack, Core0 of each node gets 16K of stack, all other cores get 4K.
-; There is a max of 1 BSP, 7 core0s and 56 other cores.
-; Although each core has it's own cache storage, they share the address space. Each core must
-; be assigned a private and unique address space for its stack. To support legacy systems,
-; the stack needs to be within the legacy address space (1st 1Meg). Room must also be reserved
-; for the other legacy elements (Interrupt vectors, BIOS ROM, video buffer, etc.)
-;
-; 80000h 40000h 00000h
-; +----------+----------+----------+----------+----------+----------+----------+----------+
-; 64K | | | | | | | | | 64K ea
-; ea +----------+----------+----------+----------+----------+----------+----------+----------+
-; | MTRR 0000_0250 MTRRfix64K_00000 |
-; +----------+----------+----------+----------+----------+----------+----------+----------+
-; | 7 , 6 | 5 , 4 | 3 , 2 | 1 , 0 | 0 | | | | <-node
-; |7..1,7..1 |7..1,7..1 |7..1,7..1 |7..1,7..1 | 0 | | | | <-core
-; +----------+----------+----------+----------+----------+----------+----------+----------+
-;
-; C0000h B0000h A0000h 90000h 80000h
-; +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
-;16K | | | | | | | | | | | | | | | | |
-; ea +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
-; | MTRR 0259 MTRRfix16K_A0000 | MTRR 0258 MTRRfix16K_80000 |
-; +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
-; | > Dis|play B|uffer | < | | | | | 7 | 6 | 5 | 4 | 3 | 2 | 1 | | <-node
-; | > T| e m |p o r |a r y | B u |f f e |r A |r e a<| 0 | 0 | 0 | 0 | 0 | 0 | 0 | | <-core
-; +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
-;
-; E0000h D0000h C0000h
-; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-; 4K | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4K ea
-; ea +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-; | 026B MTRRfix4K_D8000 | 026A MTRRfix4K_D0000 | 0269 MTRRfix4K_C8000 | 0268 MTRRfix4K_C0000 |
-; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-; | | | | | | | | | | | | | | | | | >| V| I| D| E| O| |B |I |O |S | |A |r |e |a<|
-; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-;
-; 100000h F0000h E0000h
-; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-; | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4K ea
-; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-; | 026F MTRRfix4K_F8000 | 026E MTRRfix4K_F0000 | 026D MTRRfix4K_E8000 | 026C MTRRfix4K_E0000 |
-; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-; | >|MA|IN| B|IO|S |RA|NG|E | | | | | | |< | >|EX|TE|ND|ED| B|IO|S |ZO|NE| | | | | |< |
-; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
-;======================================================================
-AMD_ENABLE_STACK MACRO
- local AmdEnableStackExit
-
-; Note that SS:ESP will be default stack. Note that this stack
-; routine will not be used after memory has been initialized. Because
-; of its limited lifetime, it will not conflict with typical PCI devices.
- movd mm0, ebx ; Put return address in a safe place
- movd mm1, ebp ; Save some other user registers
-
- ; get node id and core id of current executing core
- GET_NODE_ID_CORE_ID ; Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node)
- ; Note: ESI[31:24] are used for flags: Unrecognized Family, Is_Primary core, Stack already established
-
- ; If we detected an unknown processor family, return AGESA_FATAL.
- .if (esi & (1 SHL FLAG_UNKNOWN_FAMILY))
- mov eax, AGESA_FATAL
- jmp AmdEnableStackExit
- .endif
-
- ; determine if stack is already enabled. We are using the DefType MSR for this determination.
- ; It is =0 after reset; CAR setup sets it to enable the MTRRs
- mov eax, cr0 ; Is cache enabled? (CD or NW bit set)
- CR0_MASK TEXTEQU %((1 SHL CR0_CD) OR (1 SHL CR0_NW))
- .if (!(eax & CR0_MASK))
- mov ecx, AMD_MTRR_DEFTYPE ; MSR:0000_02FF
- _RDMSR ; Are either of the default types enabled? (MTRR_DEF_TYPE_EN + MTRR_DEF_TYPE_FIX_EN)
- MSR_MASK TEXTEQU %((1 SHL MTRR_DEF_TYPE_EN)+(1 SHL MTRR_DEF_TYPE_FIX_EN))
- .if (eax & MSR_MASK)
- bts esi, FLAG_STACK_REENTRY ; indicate stack has already been initialized
- .endif
- .endif
-
- ; Set node to map the first 16MB to node 0; 0000_0000 to 00FF_FFFF as DRAM
- mov ebx, esi ; Get my Node/Core info
- xor bl, bl
- shl bh, 3 ; Isolate my node#, match alignment for PCI Dev#
- mov eax, 8000C144h ; D18F1x44:DRAM Base/Limit; N is Base, N+4 is Limit
- add ah, bh
- mov ebx, eax ; Save PCI address for Base/Limit pair
-
- mov dx, 0CF8h
- out dx, eax
- add dx, 4
- xor eax, eax ; Least Significant bit is AD24 so 0 sets mask of 00FF_FFFF (16MB)
- out dx, eax ; DRAM Limit = node0, no interleave
-
- mov eax, ebx
- sub eax, 4 ; Now point to the Base register
- mov dx, 0CF8h
- out dx, eax
- add dx, 4
- mov eax, 00000003h ; Set the read and write enable bits
- out dx, eax ; DRAM Base = 0x0000, R/W
-
- AMD_ENABLE_STACK_FAMILY_HOOK
-
- ; Init CPU MSRs for our init routines
- mov ecx, MTRR_SYS_CFG ; SYS_CFG
- _RDMSR
- bts eax, MTRR_FIX_DRAM_MOD_EN ; Turn on modification enable bit
- _WRMSR
-
- mov eax, esi
- bt eax, FLAG_STACK_REENTRY ; Is this a 2nd entry?
- .if (!carry?) ; On a re-entry, do not clear MTRRs or reset TOM; just reset the stack SS:ESP
- bt eax, FLAG_IS_PRIMARY ; Is this core the primary in a compute unit?
- .if (carry?) ; Families using shared groups do not need to clear the MTRRs since that is done at power-on reset
- ; Note: Relying on MSRs to be cleared to 0's at reset for families w/shared cores
- ; Clear all variable and Fixed MTRRs for non-shared cores
- mov ecx, AMD_MTRR_VARIABLE_BASE0
- xor eax, eax
- xor edx, edx
- .while (cl != 10h) ; Variable MTRRphysBase[n] and MTRRphysMask[n]
- _WRMSR
- inc cl
- .endw
- mov cx, AMD_MTRR_FIX64k_00000 ; MSR:0000_0250
- _WRMSR
- mov cx, AMD_MTRR_FIX16k_80000 ; MSR:0000_0258
- _WRMSR
- mov cx, AMD_MTRR_FIX16k_A0000 ; MSR:0000_0259
- _WRMSR
- mov cx, AMD_MTRR_FIX4k_C0000 ; Fixed 4Ks: MTRRfix4K_C0000 to MTRRfix4K_F8000
- .while (cl != 70h)
- _WRMSR
- inc cl
- .endw
-
- ; Set TOP_MEM (C001_001A) for non-shared cores to 16M. This will be increased at heap init.
- ; - not strictly needed since the FixedMTRRs take presedence.
- mov eax, (16 * 1024 * 1024)
- mov ecx, TOP_MEM ; MSR:C001_001A
- _WRMSR
- .endif ; End Is_Primary
- .endif ; End Stack_ReEntry
-
- ; Clear IORRs (C001_0016-19) and TOM2(C001_001D) for all cores
- xor eax, eax
- xor edx, edx
- mov ecx, IORR_BASE ; MSR:C001_0016 - 0019
- .while (cl != 1Ah)
- _WRMSR
- inc cl
- .endw
- mov ecx, TOP_MEM2 ; MSR:C001_001D
- _WRMSR
-
- ; setup MTTRs for stacks
- ; A speculative read can be generated by a speculative fetch mis-aligned in a code zone
- ; or due to a data zone being interpreted as code. When a speculative read occurs outside a
- ; controlled region (intentionally used by software), it could cause an unwanted cache eviction.
- ; To prevent speculative reads from causing an eviction, the unused cache ranges are set
- ; to UC type. Only the actively used regions (stack, heap) are reflected in the MTRRs.
- ; Note: some core stack regions will share an MTRR since the control granularity is much
- ; larger than the allocated stack zone. The allocation algorithm must account for this 'extra'
- ; space covered by the MTRR when parseling out cache space for the various uses. In some cases
- ; this could reduce the amount of EXE cache available to a core. see cpuCacheInit.c
- ;
- ; Outcome of this block is that: (Note the MTRR map at the top of the file)
- ; ebp - start address of stack block
- ; ebx - [31:16] - MTRR MSR address
- ; - [15:8] - slot# in MTRR register
- ; - [7:0] - block size in #4K blocks
- ; review: ESI[31:24]=Flags; SI[15,8]= Node#; SI[7,0]= core# (relative to node)
- ;
-
- mov ax, si ; Load node, core
- .if (al == 0) ; Is a core 0?
- .if (ah == 0) ; Is Node 0? (BSP)
- ; Is BSP, assign a 64K stack
- mov ebx, ((AMD_MTRR_FIX64k_00000 SHL 16) + (3 SHL 8) + (BSP_STACK_SIZE / 1000h))
- mov ebp, BSP_STACK_BASE_ADDR
- .else ; node 1 to 7, core0
- ; Is a Core0 of secondary node, assign 16K stacks
- mov bx, AMD_MTRR_FIX16k_80000
- shl ebx, 16 ;
- mov bh, ah ; Node# is used as slot#
- mov bl, (CORE0_STACK_SIZE / 1000h)
- mov al, ah ; Base = (Node# * Size);
- mul bl ;
- movzx eax, ax ;
- shl eax, 12 ; Expand back to full byte count (* 4K)
- add eax, CORE0_STACK_BASE_ADDR
- mov ebp, eax
- .endif
- .else ;core 1 thru core 7
- ; Is core 1-7 of any node, assign 4K stacks
- mov al, 8 ; CoreIndex = ( (Node# * 8) ...
- mul ah ;
- mov bx, si ;
- add al, bl ; ... + Core#);
-
- mov bx, AMD_MTRR_FIX64k_00000
- shl ebx, 16 ;
- mov bh, al ; Slot# = (CoreIndex / 16) + 4;
- shr bh, 4 ;
- add bh, 4 ;
- mov bl, (CORE1_STACK_SIZE / 1000h)
-
- mul bl ; Base = ( (CoreIndex * Size) ...
- movzx eax, ax ;
- shl eax, 12 ; Expand back to full byte count (* 4K)
- add eax, CORE1_STACK_BASE_ADDR ; ... + Base_Addr);
- mov ebp, eax
- .endif
-
- ; Now set the MTRR. Add this to already existing settings (don't clear any MTRR)
- mov edi, WB_DRAM_TYPE ; Load Cache type in 1st slot
- mov cl, bh ; ShiftCount = ((slot# ...
- and cl, 03h ; ... % 4) ...
- shl cl, 3 ; ... * 8);
- shl edi, cl ; Cache type is now in correct position
- ror ebx, 16 ; Get the MTRR address
- movzx ecx, bx ;
- rol ebx, 16 ; Put slot# & size back in BX
- _RDMSR ; Read-modify-write the MSR
- .if (bh < 4) ; Is value in lower or upper half of MSR?
- or eax, edi ;
- .else ;
- or edx, edi ;
- .endif ;
- _WRMSR ;
-
- ; Enable MTRR defaults as UC type
- mov ecx, AMD_MTRR_DEFTYPE ; MSR:0000_02FF
- _RDMSR ; Read-modify-write the MSR
- bts eax, MTRR_DEF_TYPE_EN ; MtrrDefTypeEn
- bts eax, MTRR_DEF_TYPE_FIX_EN ; MtrrDefTypeFixEn
- _WRMSR
-
- ; Close the modification window on the Fixed MTRRs
- mov ecx, MTRR_SYS_CFG ; MSR:0C001_0010
- _RDMSR
- bts eax, MTRR_FIX_DRAM_EN ; MtrrFixDramEn
- bts eax, MTRR_VAR_DRAM_EN ; variable MTRR enable bit
- btr eax, MTRR_FIX_DRAM_MOD_EN ; Turn off modification enable bit
- _WRMSR
-
- ; Enable caching in CR0
- mov eax, CR0 ; Enable WT/WB cache
- btr eax, CR0_PG ; Make sure paging is disabled
- btr eax, CR0_CD ; Clear CR0 NW and CD
- btr eax, CR0_NW
- mov CR0, eax
-
- ; Use the Stack Base & size to calculate SS and ESP values
- ; review:
- ; esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
- ; ebp - start address of stack block
- ; ebx - [31:16] - MTRR MSR address
- ; - [15:8] - slot# in MTRR register
- ; - [7:0] - block size in #4K blocks
- ;
- mov esp, ebp ; Initialize the stack pointer
- mov edi, esp ; Copy the stack start to edi
- movzx bx, bl
- movzx ebx, bx ; Clear upper ebx, don't need MSR addr anymore
- shl ebx, 12 ; Make size full byte count (* 4K)
- add esp, ebx ; Set the Stack Pointer as full linear address
- sub esp, 4
- ;
- ; review:
- ; esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
- ; edi - 32b start address of stack block
- ; ebx - size of stack block
- ; esp - 32b linear stack pointer
- ;
-
- ; Determine mode for SS base;
- mov ecx, CR0 ; Check for 32-bit protect mode
- bt ecx, CR0_PE ;
- .if (!carry?) ; PE=0 means real mode
- mov cx, cs ;
- .if (cx >= 0D000h) ; If CS >= D000, it's a real mode segment. PM selector would be 08-> 1000
- ; alter SS:ESP for 16b Real Mode:
- mov eax, edi ;
- shr eax, 4 ; Create a Real Mode segment for ss, ds, es
- mov ss, ax ;
- mov ds, ax ;
- mov es, ax ;
- shl eax, 4 ;
- sub edi, eax ; Adjust the clearing pointer for Seg:Offset mode
- mov esp, ebx ; Make SP an offset from SS
- sub esp, 4 ;
- .endif ; endif
- ; else
- ; Default is to use Protected 32b Mode
- .endif
- ;
- ; Clear The Stack
- ; Now that we have set the location and the MTRRs, initialize the cache by
- ; reading then writing to zero all of the stack area.
- ; review:
- ; ss - Stack base
- ; esp - stack pointer
- ; ebx - size of stack block
- ; esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
- ; edi - address of start of stack block
- ;
- shr ebx, 2 ;
- mov cx, bx ; set cx for size count of DWORDS
- ; Check our flags - Don't clear an existing stack
- .if ( !(esi & (1 SHL FLAG_STACK_REENTRY)) )
- cld
- mov esi, edi
- rep lods DWORD PTR [esi] ; Pre-load the range
- xor eax, eax
- mov cx, bx
- mov esi, edi ; Preserve base for push on stack
- rep stos DWORD PTR [edi] ; Clear the range
- mov DWORD PTR [esp], 0ABCDDCBAh ; Put marker in top stack dword
- shl ebx, 2 ; Put stack size and base
- push ebx ; in top of stack
- push esi
-
- mov ecx, ebx ; Return size of stack in bytes
- mov eax, AGESA_SUCCESS ; eax = AGESA_SUCCESS : no error return code
- .else
- movzx ecx, cx
- shl ecx, 2 ; Return size of stack, in bytes
- mov eax, esi
- shr eax, 24 ; Keep the flags as part of the error report
- or eax, 40000000h ; eax = AGESA_WARNING (Stack has already been set up)
- .endif
-AmdEnableStackExit:
- movd ebx, mm0 ; Restore return address
- movd ebp, mm1
-ENDM
-
-;======================================================================
-; AMD_DISABLE_STACK: Destroy the stack inside the cache. This routine
-; should only be executed on the BSP
-;
-; In:
-; none
-;
-; Out:
-; EAX = AGESA_SUCCESS
-;
-; Preserved:
-; ebx
-; Destroyed:
-; eax, ecx, edx, esp
-;======================================================================
-AMD_DISABLE_STACK MACRO
-
- mov esp, ebx ; Save return address
-
- ; get node/core/flags of current executing core
- GET_NODE_ID_CORE_ID ; Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node)
-
- ; Turn on modification enable bit
- mov ecx, MTRR_SYS_CFG ; MSR:C001_0010
- _RDMSR
- bts eax, MTRR_FIX_DRAM_MOD_EN ; Enable modifications
- _WRMSR
-
- ; Set lower 640K MTRRs for Write-Back memory caching
- mov ecx, AMD_MTRR_FIX64k_00000
- mov eax, 1E1E1E1Eh
- mov edx, eax
- _WRMSR ; 0 - 512K = WB Mem
- mov ecx, AMD_MTRR_FIX16k_80000
- _WRMSR ; 512K - 640K = WB Mem
-
- ; Turn off modification enable bit
- mov ecx, MTRR_SYS_CFG ; MSR:C001_0010
- _RDMSR
- btr eax, MTRR_FIX_DRAM_MOD_EN ; Disable modification
- _WRMSR
-
- AMD_DISABLE_STACK_FAMILY_HOOK ; Re-Enable 'normal' cache operations
-
- mov ebx, esp ; restore return address (ebx)
- xor eax, eax
-
-ENDM
diff --git a/src/vendorcode/amd/agesa/errno.h b/src/vendorcode/amd/agesa/errno.h
deleted file mode 100644
index 1477888..0000000
--- a/src/vendorcode/amd/agesa/errno.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-// this dummy errno.h prevents an agesa build failure when the gcc
-// cross compiler target is i386-elf. In this case, mm_malloc.h
-// includes errno.h, but the gcc cross compiler does not supply it.
-
-extern int errno;
-#define EINVAL 1
diff --git a/src/vendorcode/amd/agesa/f14/AGESA.h b/src/vendorcode/amd/agesa/f14/AGESA.h
new file mode 100644
index 0000000..0f348d6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/AGESA.h
@@ -0,0 +1,3022 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Agesa structures and definitions
+ *
+ * Contains AMD AGESA core interface
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Include
+ * @e \$Revision: 41504 $ @e \$Date: 2010-11-05 21:59:13 +0800 (Fri, 05 Nov 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+
+#ifndef _AGESA_H_
+#define _AGESA_H_
+
+#include "Porting.h"
+#include "AMD.h"
+
+//
+//
+// AGESA Types and Definitions
+//
+//
+
+// AGESA BASIC CALLOUTS
+#define AGESA_MEM_RELEASE 0x00028000
+
+// AGESA ADVANCED CALLOUTS, Processor
+#define AGESA_CHECK_UMA 0x00028100
+#define AGESA_DO_RESET 0x00028101
+#define AGESA_ALLOCATE_BUFFER 0x00028102
+#define AGESA_DEALLOCATE_BUFFER 0x00028103
+#define AGESA_LOCATE_BUFFER 0x00028104
+#define AGESA_RUNFUNC_ONAP 0x00028105
+
+// AGESA ADVANCED CALLOUTS, HyperTransport
+
+// AGESA ADVANCED CALLOUTS, Memory
+#define AGESA_READ_SPD 0x00028140
+#define AGESA_HOOKBEFORE_DRAM_INIT 0x00028141
+#define AGESA_HOOKBEFORE_DQS_TRAINING 0x00028142
+#define AGESA_READ_SPD_RECOVERY 0x00028143
+#define AGESA_HOOKBEFORE_EXIT_SELF_REF 0x00028144
+#define AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY 0x00028145
+
+// AGESA IDS CALLOUTS
+#define AGESA_GET_IDS_INIT_DATA 0x00028200
+
+// AGESA GNB CALLOUTS
+#define AGESA_GNB_PCIE_SLOT_RESET 0x00028301
+
+//------------------------------------------------------------------------
+//
+// HyperTransport Interface
+
+
+
+//-----------------------------------------------------------------------------
+// HT DEFINITIONS AND MACROS
+//
+//-----------------------------------------------------------------------------
+
+
+// Width equates for call backs
+#define HT_WIDTH_8_BITS 8 ///< Specifies 8 bit, or up to 8 bit widths.
+#define HT_WIDTH_16_BITS 16 ///< Specifies 16 bit, or up to 16 bit widths.
+#define HT_WIDTH_4_BITS 4
+#define HT_WIDTH_2_BITS 2
+#define HT_WIDTH_NO_LIMIT HT_WIDTH_16_BITS
+
+// Frequency Limit equates for call backs which take a frequency supported mask.
+#define HT_FREQUENCY_LIMIT_200M 1 ///< Specifies a limit of no more than 200 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_400M 7 ///< Specifies a limit of no more than 400 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_600M 0x1F ///< Specifies a limit of no more than 600 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_800M 0x3F ///< Specifies a limit of no more than 800 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_1000M 0x7F ///< Specifies a limit of no more than 1000 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_HT1_ONLY 0x7F ///< Specifies a limit of no more than 1000 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_1200M 0xFF ///< Specifies a limit of no more than 1200 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_1400M 0x1FF ///< Specifies a limit of no more than 1400 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_1600M 0x3FF ///< Specifies a limit of no more than 1600 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_1800M 0x7FF ///< Specifies a limit of no more than 1800 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_2000M 0xFFF ///< Specifies a limit of no more than 2000 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_2200M 0x1FFF ///< Specifies a limit of no more than 2200 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_2400M 0x3FFF ///< Specifies a limit of no more than 2400 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_2600M 0x7FFF ///< Specifies a limit of no more than 2600 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_2800M 0x27FFF ///< Specifies a limit of no more than 2800 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_3000M 0x67FFF ///< Specifies a limit of no more than 3000 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_3200M 0xE7FFF ///< Specifies a limit of no more than 3200 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_3600M 0x1E7FFF
+#define HT_FREQUENCY_LIMIT_MAX HT_FREQUENCY_LIMIT_3600M
+#define HT_FREQUENCY_NO_LIMIT 0xFFFFFFFF ///< Specifies a no limit of HT frequency.
+
+// Unit ID Clumping special values
+#define HT_CLUMPING_DISABLE 0x00000000
+#define HT_CLUMPING_NO_LIMIT 0xFFFFFFFF
+
+#define HT_LIST_TERMINAL 0xFF ///< End of list.
+#define HT_LIST_MATCH_ANY 0xFE ///< Match Any value, used for Sockets, Links, IO Chain Depth.
+#define HT_LIST_MATCH_INTERNAL_LINK 0xFD ///< Match all of the internal links.
+
+// Event Notify definitions
+
+// Event definitions.
+
+// Coherent subfunction events
+#define HT_EVENT_COH_EVENTS 0x10001000
+#define HT_EVENT_COH_NO_TOPOLOGY 0x10011000 ///< See ::HT_EVENT_DATA_COH_NO_TOPOLOGY.
+#define HT_EVENT_COH_OBSOLETE000 0x10021000 // No longer used.
+#define HT_EVENT_COH_PROCESSOR_TYPE_MIX 0x10031000 ///< See ::HT_EVENT_DATA_COH_PROCESSOR_TYPE_MIX.
+#define HT_EVENT_COH_NODE_DISCOVERED 0x10041000 ///< See ::HT_EVENT_COH_NODE_DISCOVERED.
+#define HT_EVENT_COH_MPCAP_MISMATCH 0x10051000 ///< See ::HT_EVENT_COH_MPCAP_MISMATCH.
+
+// Non-coherent subfunction events
+#define HT_EVENT_NCOH_EVENTS 0x10002000
+#define HT_EVENT_NCOH_BUID_EXCEED 0x10012000 ///< See ::HT_EVENT_DATA_NCOH_BUID_EXCEED
+#define HT_EVENT_NCOH_OBSOLETE000 0x10022000 // No longer used.
+#define HT_EVENT_NCOH_BUS_MAX_EXCEED 0x10032000 ///< See ::HT_EVENT_DATA_NCOH_BUS_MAX_EXCEED.
+#define HT_EVENT_NCOH_CFG_MAP_EXCEED 0x10042000 ///< See ::HT_EVENT_DATA_NCOH_CFG_MAP_EXCEED.
+#define HT_EVENT_NCOH_DEVICE_FAILED 0x10052000 ///< See ::HT_EVENT_DATA_NCOH_DEVICE_FAILED
+#define HT_EVENT_NCOH_AUTO_DEPTH 0x10062000 ///< See ::HT_EVENT_NCOH_AUTO_DEPTH
+
+// Optimization subfunction events
+#define HT_EVENT_OPT_EVENTS 0x10003000
+#define HT_EVENT_OPT_REQUIRED_CAP_RETRY 0x10013000 ///< See ::HT_EVENT_DATA_OPT_REQUIRED_CAP.
+#define HT_EVENT_OPT_REQUIRED_CAP_GEN3 0x10023000 ///< See ::HT_EVENT_DATA_OPT_REQUIRED_CAP.
+#define HT_EVENT_OPT_UNUSED_LINKS 0x10033000 ///< See ::HT_EVENT_DATA_OPT_UNUSED_LINKS.
+#define HT_EVENT_OPT_LINK_PAIR_EXCEED 0x10043000 ///< See ::HT_EVENT_DATA_OPT_LINK_PAIR_EXCEED.
+
+// HW Fault events
+#define HT_EVENT_HW_EVENTS 0x10004000
+#define HT_EVENT_HW_SYNCFLOOD 0x10014000 ///< See ::HT_EVENT_DATA_HW_SYNCFLOOD.
+#define HT_EVENT_HW_HTCRC 0x10024000 ///< See ::HT_EVENT_DATA_HW_HT_CRC.
+
+// The Recovery HT component uses 0x10005000 for events.
+// For consistency, we avoid that range here.
+
+#define HT_MAX_NC_BUIDS 32
+//----------------------------------------------------------------------------
+// HT TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+
+/// Specify the state redundant links are to be left in after match.
+///
+/// After matching a link for IGNORE_LINK or SKIP_REGANG, the link may be left alone,
+/// or powered off.
+
+typedef enum {
+ MATCHED, ///< The link matches the requested customization.
+ ///< When used with IGNORE_LINK,
+ ///< this will generally require other software to initialize the link.
+ ///< When used with SKIP_REGANG,
+ ///< the two unganged links will be available for distribution.
+
+ POWERED_OFF, ///< Power the link off. Support may vary based on processor model.
+ ///< Power Off is only supported for coherent links.
+ ///< Link power off may occur at a warm reset rather than immediately.
+ ///< When used with SKIP_REGANG, the paired sublink is powered off, not the matching link.
+
+ UNMATCHED, ///< The link should be processed according to normal defaults.
+ ///< Effectively, the link does not match the requested customization.
+ ///< This can be used to exclude links from a following match any.
+
+ MaxFinalLinkState ///< Not a final link state, use for limit checking.
+} FINAL_LINK_STATE;
+
+/// Swap a device from its current id to a new one.
+
+typedef struct {
+ IN UINT8 FromId; ///< The device responding to FromId,
+ IN UINT8 ToId; ///< will be moved to ToId.
+} BUID_SWAP_ITEM;
+
+
+/// Each Non-coherent chain may have a list of device swaps. After performing the swaps,
+/// the final in order list of device ids is provided. (There can be more swaps than devices.)
+/// The unused entries in both are filled with 0xFF.
+
+typedef struct {
+ IN BUID_SWAP_ITEM Swaps[HT_MAX_NC_BUIDS]; ///< The BUID Swaps to perform
+ IN UINT8 FinalIds[HT_MAX_NC_BUIDS]; ///< The ordered final BUIDs, resulting from the swaps
+} BUID_SWAP_LIST;
+
+
+/// Control Manual Initialization of Non-Coherent Chains
+///
+/// This interface is checked every time a non-coherent chain is
+/// processed. BUID assignment may be controlled explicitly on a
+/// non-coherent chain. Provide a swap list. Swaps controls the
+/// BUID assignment and FinalIds provides the device to device
+/// Linking. Device orientation can be detected automatically, or
+/// explicitly. See interface documentation for more details.
+///
+/// If a manual swap list is not supplied,
+/// automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
+/// based on each device's unit count.
+
+typedef struct {
+ // Match fields
+ IN UINT8 Socket; ///< The Socket on which this chain is located
+ IN UINT8 Link; ///< The Link on the host for this chain
+ // Override fields
+ IN BUID_SWAP_LIST SwapList; ///< The swap list
+} MANUAL_BUID_SWAP_LIST;
+
+
+/// Override options for DEVICE_CAP_OVERRIDE.
+///
+/// Specify which override actions should be performed. For Checks, 1 means to check the item
+/// and 0 means to skip the check. For the override options, 1 means to apply the override and
+/// 0 means to ignore the override.
+
+typedef struct {
+ IN UINT32 IsCheckDevVenId:1; ///< Check Match on Device/Vendor id
+ IN UINT32 IsCheckRevision:1; ///< Check Match on device Revision
+ IN UINT32 IsOverrideWidthIn:1; ///< Override Width In
+ IN UINT32 IsOverrideWidthOut:1; ///< Override Width Out
+ IN UINT32 IsOverrideFreq:1; ///< Override Frequency
+ IN UINT32 IsOverrideClumping:1; ///< Override Clumping
+ IN UINT32 IsDoCallout:1; ///< Make the optional callout
+} DEVICE_CAP_OVERRIDE_OPTIONS;
+
+/// Override capabilities of a device.
+///
+/// This interface is checked once for every Link on every IO device.
+/// Provide the width and frequency capability if needed for this device.
+/// This is used along with device capabilities, the limit interfaces, and northbridge
+/// limits to compute the default settings. The components of the device's PCI config
+/// address are provided, so its settings can be consulted if need be.
+/// The optional callout is a catch all.
+
+typedef struct {
+ // Match fields
+ IN UINT8 HostSocket; ///< The Socket on which this chain is located.
+ IN UINT8 HostLink; ///< The Link on the host for this chain.
+ IN UINT8 Depth; ///< The Depth in the I/O chain from the Host.
+ IN UINT32 DevVenId; ///< The Device's PCI Vendor + Device ID (offset 0x00).
+ IN UINT8 Revision; ///< The Device's PCI Revision field (offset 0x08).
+ IN UINT8 Link; ///< The Device's Link number (0 or 1).
+ IN DEVICE_CAP_OVERRIDE_OPTIONS Options; ///< The options for this device override.
+ // Override fields
+ IN UINT8 LinkWidthIn; ///< modify to change the Link Width In.
+ IN UINT8 LinkWidthOut; ///< modify to change the Link Width Out.
+ IN UINT32 FreqCap; ///< modify to change the Link's frequency capability.
+ IN UINT32 Clumping; ///< modify to change Unit ID clumping support.
+ IN CALLOUT_ENTRY Callout; ///< optional call for really complex cases, or NULL.
+} DEVICE_CAP_OVERRIDE;
+
+/// Callout param struct for override capabilities of a device.
+///
+/// If the optional callout is implemented this param struct is passed to it.
+
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ // Match fields
+ IN UINT8 HostSocket; ///< The Socket on which this chain is located.
+ IN UINT8 HostLink; ///< The Link on the host for this chain.
+ IN UINT8 Depth; ///< The Depth in the I/O chain from the Host.
+ IN UINT32 DevVenId; ///< The Device's PCI Vendor + Device ID (offset 0x00).
+ IN UINT8 Revision; ///< The Device's PCI Revision field (offset 0x08).
+ IN UINT8 Link; ///< The Device's Link number (0 or 1).
+ IN PCI_ADDR PciAddress; ///< The Device's PCI Address.
+ // Override fields
+ OUT UINT8 *LinkWidthIn; ///< modify to change the Link Width In.
+ OUT UINT8 *LinkWidthOut; ///< modify to change the Link Width Out.
+ OUT UINT32 *FreqCap; ///< modify to change the Link's frequency capability.
+ OUT UINT32 *Clumping; ///< modify to change Unit ID clumping support.
+} DEVICE_CAP_CALLOUT_PARAMS;
+
+/// Limits for CPU to CPU Links.
+///
+/// For each coherent connection this interface is checked once.
+/// Provide the frequency and width if needed for this Link (usually based on board
+/// restriction). This is used with CPU device capabilities and northbridge limits
+/// to compute the default settings.
+
+typedef struct {
+ // Match fields
+ IN UINT8 SocketA; ///< One Socket on which this Link is located
+ IN UINT8 LinkA; ///< The Link on this Node
+ IN UINT8 SocketB; ///< The other Socket on which this Link is located
+ IN UINT8 LinkB; ///< The Link on that Node
+ // Limit fields
+ IN UINT8 ABLinkWidthLimit; ///< modify to change the Link Width A->B
+ IN UINT8 BALinkWidthLimit; ///< modify to change the Link Width B-<A
+ IN UINT32 PcbFreqCap; ///< modify to change the Link's frequency capability
+} CPU_TO_CPU_PCB_LIMITS;
+
+/// Get limits for non-coherent Links.
+///
+/// For each non-coherent connection this interface is checked once.
+/// Provide the frequency and width if needed for this Link (usually based on board
+/// restriction). This is used with device capabilities, device overrides, and northbridge limits
+/// to compute the default settings.
+///
+typedef struct {
+ // Match fields
+ IN UINT8 HostSocket; ///< The Socket on which this Link is located
+ IN UINT8 HostLink; ///< The Link about to be initialized
+ IN UINT8 Depth; ///< The Depth in the I/O chain from the Host
+ // Limit fields
+ IN UINT8 DownstreamLinkWidthLimit; ///< modify to change the Link Width going away from processor
+ IN UINT8 UpstreamLinkWidthLimit; ///< modify to change the Link Width moving toward processor
+ IN UINT32 PcbFreqCap; ///< modify to change the Link's frequency capability
+} IO_PCB_LIMITS;
+
+/// Manually control bus number assignment.
+///
+/// This interface is checked every time a non-coherent chain is processed.
+/// If a system can not use the auto Bus numbering feature for non-coherent chain bus
+/// assignments, this interface can provide explicit control. For each chain, provide
+/// the bus number range to use.
+
+typedef struct {
+ // Match fields
+ IN UINT8 Socket; ///< The Socket on which this chain is located
+ IN UINT8 Link; ///< The Link on the host for this chain
+ // Override fields
+ IN UINT8 SecBus; ///< Secondary Bus number for this non-coherent chain
+ IN UINT8 SubBus; ///< Subordinate Bus number
+} OVERRIDE_BUS_NUMBERS;
+
+
+/// Ignore a Link.
+///
+/// This interface is checked every time a coherent Link is found and then every
+/// time a non-coherent Link from a CPU is found.
+/// Any coherent or non-coherent Link from a CPU can be ignored and not used
+/// for discovery or initialization. Useful for connection based systems.
+/// (Note: not checked for IO device to IO Device Links.)
+/// (Note: not usable for internal links (MCM processors).)
+
+typedef struct {
+ // Match fields
+ IN UINT8 Socket; ///< The Socket on which this Link is located
+ IN UINT8 Link; ///< The Link about to be initialized
+ // Customization fields
+ IN FINAL_LINK_STATE LinkState; ///< The link may be left unitialized, or powered off.
+} IGNORE_LINK;
+
+
+/// Skip reganging of subLinks.
+///
+/// This interface is checked whenever two subLinks are both connected to the same CPUs.
+/// Normally, unganged sublinks between the same two CPUs are reganged.
+/// Provide a matching structure to leave the Links unganged.
+
+typedef struct {
+ // Match fields
+ IN UINT8 SocketA; ///< One Socket on which this Link is located
+ IN UINT8 LinkA; ///< The Link on this Node
+ IN UINT8 SocketB; ///< The other Socket on which this Link is located
+ IN UINT8 LinkB; ///< The Link on that Node
+ // Customization fields
+ IN FINAL_LINK_STATE LinkState; ///< The paired sublink may be active, or powered off.
+} SKIP_REGANG;
+
+/// The System Socket layout, which sockets are physically connected.
+///
+/// The hardware method for Socket naming is preferred. Use this software method only
+/// if required.
+
+typedef struct {
+ IN UINT8 CurrentSocket; ///< The socket from which this connection originates.
+ IN UINT8 CurrentLink; ///< The Link from the source socket connects to another socket.
+ IN UINT8 TargetSocket; ///< The target socket which is connected on that link.
+} SYSTEM_PHYSICAL_SOCKET_MAP;
+
+//----------------------------------------------------------------------------
+///
+/// This is the input structure for AmdHtInitialize.
+///
+typedef struct {
+ // Basic level customization
+ IN UINT8 AutoBusStart; ///< For automatic bus number assignment, starting bus number - usually zero.
+ ///< @BldCfgItem{BLDCFG_STARTING_BUSNUM}
+ IN UINT8 AutoBusMax; ///< For automatic bus number assignment, do not assign above max.
+ ///< @BldCfgItem{BLDCFG_MAXIMUM_BUSNUM}
+ IN UINT8 AutoBusIncrement; ///< For automatic bus number assignment, each chain gets this many busses.
+ ///< @BldCfgItem{BLDCFG_ALLOCATED_BUSNUMS}
+
+ // Advanced Level Customization
+ IN MANUAL_BUID_SWAP_LIST *ManualBuidSwapList; ///< Provide Manual Swap List, if any.
+ ///< @BldCfgItem{BLDCFG_BUID_SWAP_LIST}
+ IN DEVICE_CAP_OVERRIDE *DeviceCapOverrideList; ///< Provide Device Overrides, if any.
+ ///< @BldCfgItem{BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST}
+ IN CPU_TO_CPU_PCB_LIMITS *CpuToCpuPcbLimitsList; ///< Provide CPU PCB Limits, if any.
+ ///< @BldCfgItem{BLDCFG_HTFABRIC_LIMITS_LIST}.
+ ///< @n @e Examples: See @ref FrequencyLimitExamples "Frequency Limit Examples".
+ IN IO_PCB_LIMITS *IoPcbLimitsList; ///< Provide IO PCB Limits, if any.
+ ///< @BldCfgItem{BLDCFG_HTCHAIN_LIMITS_LIST}.
+ ///< @n @e Examples: See @ref FrequencyLimitExamples "Frequency Limit Examples".
+ IN OVERRIDE_BUS_NUMBERS *OverrideBusNumbersList; ///< Provide manual Bus Number assignment, if any.
+ ///< Use either auto bus numbering or override bus
+ ///< numbers, not both.
+ ///< @BldCfgItem{BLDCFG_BUS_NUMBERS_LIST}
+
+ IN IGNORE_LINK *IgnoreLinkList; ///< Provide links to ignore, if any.
+ ///< @BldCfgItem{BLDCFG_IGNORE_LINK_LIST}
+ IN SKIP_REGANG *SkipRegangList; ///< Provide links to remain unganged, if any.
+ ///< @BldCfgItem{BLDCFG_LINK_SKIP_REGANG_LIST}
+ ///< @n @e Examples: See @ref PerfPerWattHt "Performance-per-watt Optimization".
+
+ // Expert Level Customization
+ IN UINT8 **Topolist; ///< Use this topology list in addition to the built in, if not NULL.
+ ///< @BldCfgItem{BLDCFG_ADDITIONAL_TOPOLOGIES_LIST}
+ IN SYSTEM_PHYSICAL_SOCKET_MAP *SystemPhysicalSocketMap;
+ ///< The hardware socket naming method is preferred,
+ ///< If it can't be used, this provides a software method.
+ ///< @BldCfgItem{BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP}
+} AMD_HT_INTERFACE;
+
+//-----------------------------------------------------------------------------
+//
+// HT Recovery Interface
+//
+
+
+/*-----------------------------------------------------------------------------
+ * HT Recovery DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+// BBHT subfunction events
+#define HT_EVENT_BB_EVENTS 0x10005000
+#define HT_EVENT_BB_BUID_EXCEED 0x10015000
+#define HT_EVENT_BB_DEVICE_FAILED 0x10055000
+#define HT_EVENT_BB_AUTO_DEPTH 0x10065000
+
+/*----------------------------------------------------------------------------
+ * HT Recovery TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/// The Interface structure to Recovery HT.
+
+typedef struct {
+ IN MANUAL_BUID_SWAP_LIST *ManualBuidSwapList; ///< Option to manually control SB link init
+ ///< @BldCfgItem{BLDCFG_BUID_SWAP_LIST}
+ OUT UINT32 Depth; ///< If auto init was used this is set to the depth of the chain,
+ ///< else, for manual init unmodified.
+} AMD_HT_RESET_INTERFACE;
+
+/*----------------------------------------------------------------------------
+ * CPU Feature related info
+ *----------------------------------------------------------------------------
+ */
+
+/// Build Configuration values for BLDCFG_PLATFORM_C1E_MODE
+typedef enum {
+ C1eModeDisabled = 0, ///< Disabled
+ C1eModeHardware = 1, ///< Hardware method
+ C1eModeMsgBased = 2, ///< Message-based method
+ C1eModeSoftwareDeprecated = 3, ///< Deprecated software SMI method.
+ ///< Refer to "Addendum\Examples\C1eSMMHandler.asm" for
+ ///< example host BIOS SMM Handler implementation
+ C1eModeHardwareSoftwareDeprecated = 4, ///< Hardware or deprecated software SMI method
+ MaxC1eMode = 5 ///< Not a valid value, used for verifying input
+} PLATFORM_C1E_MODES;
+
+/// Build Configuration values for BLDCFG_PLATFORM_CSTATE_MODE
+typedef enum {
+ CStateModeDisabled = 0, ///< Disabled
+ CStateModeC6 = 1, ///< C6 State
+ MaxCStateMode = 2 ///< Not a valid value, used for verifying input
+} PLATFORM_CSTATE_MODES;
+
+/// Build Configuration values for BLDCFG_PLATFORM_CPB_MODE
+typedef enum {
+ CpbModeAuto = 0, ///< Auto
+ CpbModeDisabled = 1, ///< Disabled
+ MaxCpbMode = 2 ///< Not a valid value, used for verifying input
+} PLATFORM_CPB_MODES;
+
+/*----------------------------------------------------------------------------
+ * GNB PCIe configuration info
+ *----------------------------------------------------------------------------
+ */
+
+// Event definitions
+
+
+#define GNB_EVENT_INVALID_CONFIGURATION 0x20010000 // User configuration invalid
+#define GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION 0x20010001 // Requested lane allocation for PCIe port can not be supported
+#define GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION 0x20010002 // Requested incorrect PCIe port device address
+#define GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION 0x20010003 // Incorrect parameter in DDI link configuration
+#define GNB_EVENT_INVALID_LINK_WIDTH_CONFIGURATION 0x20010004 // Invalid with for PCIe port or DDI link
+#define GNB_EVENT_INVALID_LANES_CONFIGURATION 0x20010005 // Lane double subscribe lanes
+#define GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION 0x20010006 // Requested lane allocation for DDI link(s) can not be supported
+#define GNB_EVENT_LINK_TRAINING_FAIL 0x20020000 // PCIe Link training fail
+#define GNB_EVENT_BROKEN_LANE_RECOVERY 0x20030000 // Broken lane workaround applied to recover link training
+#define GNB_EVENT_GEN2_SUPPORT_RECOVERY 0x20040000 // Scale back to GEN1 to recover link training
+
+
+#define DESCRIPTOR_TERMINATE_LIST 0x80000000ull
+
+/// PCIe port misc extended controls
+typedef struct {
+ IN UINT8 LinkComplianceMode :1; ///< Force port into compliance mode (device will not be trained, port output compliance pattern)
+ IN UINT8 LinkSafeMode :2; /**< Safe mode PCIe capability. (Parameter may limit PCIe speed requested through PCIe_PORT_DATA::LinkSpeedCapability)
+ * @li @b 0 - port can advertize muximum supported capability
+ * @li @b 1 - port limit advertized capability and speed to PCIe Gen1
+ */
+} PCIe_PORT_MISC_CONTROL;
+
+
+/// PCIe port configuration data
+typedef struct {
+ IN UINT8 PortPresent; ///< Enable PCIe port for initialization.
+ IN UINT8 ChannelType; /**< Channel type.
+ * @li @b 0 - "lowLoss",
+ * @li @b 1 - "highLoss",
+ * @li @b 2 - "mob0db",
+ * @li @b 3 - "mob3db",
+ * @li @b 4 - "extnd6db"
+ * @li @b 5 - "extnd8db"
+ */
+ IN UINT8 DeviceNumber; /**< PCI Device number for port.
+ * @li @b 0 - Native port device number
+ * @li @b N - Port device number (See available configurations @ref F12LaneConfigurations "Family 0x12", @ref F14LaneConfigurations "Family 0x14")
+ */
+ IN UINT8 FunctionNumber; ///< Reserved for future use
+ IN UINT8 LinkSpeedCapability; /**< PCIe link speed/
+ * @li @b 0 - Maximum supported by silicon
+ * @li @b 1 - Gen1
+ * @li @b 2 - Gen2
+ * @li @b 3 - Gen3
+ */
+ IN UINT8 LinkAspm; /**< ASPM control. (see AgesaPcieLinkAspm for additional option to control ASPM)
+ * @li @b 0 - Disabled
+ * @li @b 1 - L0s only
+ * @li @b 2 - L1 only
+ * @li @b 3 - L0s and L1
+ */
+ IN UINT8 LinkHotplug; /**< Hotplug control.
+ * @li @b 0 - Disabled
+ * @li @b 1 - Basic
+ * @li @b 2 - Server
+ * @li @b 3 - Enhanced
+ */
+ IN UINT8 ResetId; /**< Arbitrary number greater than 0 assigned by platform firmware for GPIO
+ * identification which control reset for given port.
+ * Each port with unique GPIO should have unique ResetId assigned.
+ * All ports use same GPIO to control reset should have same ResetId assigned.
+ * see AgesaPcieSlotResetContol.
+ */
+ IN PCIe_PORT_MISC_CONTROL MiscControls; ///< Misc extended controls
+} PCIe_PORT_DATA;
+
+/// DDI channel lane mapping
+typedef struct { ///< Structure that discribe lane mapping
+ IN UINT8 Lane0 :2; /**< Lane 0 mapping
+ * @li @b 0 - Map to lane 0
+ * @li @b 1 - Map to lane 1
+ * @li @b 2 - Map to lane 2
+ * @li @b 2 - Map to lane 3
+ */
+ IN UINT8 Lane1 :2; ///< Lane 1 mapping (see "Lane 0 mapping")
+ IN UINT8 Lane2 :2; ///< Lane 2 mapping (see "Lane 0 mapping")
+ IN UINT8 Lane3 :2; ///< Lane 3 mapping (see "Lane 0 mapping")
+} CHANNEL_MAPPING; ///< Lane mapping
+
+/// Common Channel Mapping
+typedef union {
+ IN UINT8 ChannelMappingValue; ///< Raw lane mapping
+ IN CHANNEL_MAPPING ChannelMapping; ///< Channel mapping
+} CONN_CHANNEL_MAPPING;
+
+/// DDI Configuration data
+typedef struct {
+ IN UINT8 ConnectorType; /**< Display Connector Type
+ * @li @b 0 - DP
+ * @li @b 1 - eDP
+ * @li @b 2 - Single Link DVI-D
+ * @li @b 3 - Dual Link DVI-D (see @ref F12DualLinkDviDescription "Family 0x12 Dual Link DVI connector description")
+ * @li @b 4 - HDMI
+ * @li @b 5 - Travis DP-to-VGA
+ * @li @b 6 - Travis DP-to-LVDS
+ * @li @b 7 - Hudson-2 NutMeg DP-to-VGA
+ * @li @b 8 - Single Link DVI-I
+ * @li @b 9 - Native CRT (Family 0x14)
+ * @li @b 10 - Native LVDS (Family 0x14)
+ * @li @b 11 - Auto detect LCD panel connector type. VBIOS is able to auto detect the LVDS connector type: native LVDS, eDP or Travis-LVDS
+ * The auto detection method only support panel with EDID.
+ */
+ IN UINT8 AuxIndex; /**< Indicates which AUX or DDC Line is used
+ * @li @b 0 - AUX1
+ * @li @b 1 - AUX2
+ * @li @b 2 - AUX3
+ * @li @b 3 - AUX4
+ * @li @b 4 - AUX5
+ * @li @b 5 - AUX6
+ */
+ IN UINT8 HdpIndex; /**< Indicates which HDP pin is used
+ * @li @b 0 - HDP1
+ * @li @b 1 - HDP2
+ * @li @b 2 - HDP3
+ * @li @b 3 - HDP4
+ * @li @b 4 - HDP5
+ * @li @b 5 - HDP6
+ */
+ IN CONN_CHANNEL_MAPPING Mapping[2]; /**< Set specific mapping of lanes to connector pins
+ * @li Mapping[0] define mapping for group of 4 lanes starting at PCIe_ENGINE_DATA.StartLane
+ * @li Mapping[1] define mapping for group of 4 lanes ending at PCIe_ENGINE_DATA.EndLane (only applicable for Dual DDI link)
+ * if Mapping[x] set to 0 than default mapping assumed
+ */
+} PCIe_DDI_DATA;
+
+/// Engine Configuration
+typedef struct {
+ IN UINT8 EngineType; /**< Engine type
+ * @li @b 0 - Ignore engine configuration
+ * @li @b 1 - PCIe port
+ * @li @b 2 - DDI
+ */
+ IN UINT16 StartLane; /**< Start Lane ID (in reversed configuration StartLane > EndLane)
+ * See lane description for @ref F12PcieLaneDescription "Family 0x12"
+ * @ref F14PcieLaneDescription "Family 0x14".
+ * See lane configurations for @ref F12LaneConfigurations "Family 0x12"
+ * @ref F14LaneConfigurations "Family 0x14".
+ */
+ IN UINT16 EndLane; /**< End lane ID (in reversed configuration StartLane > EndLane)
+ * See lane description for @ref F12PcieLaneDescription "Family 0x12",
+ * @ref F14PcieLaneDescription "Family 0x14".
+ * See lane configurations for @ref F12LaneConfigurations "Family 0x12"
+ * @ref F14LaneConfigurations "Family 0x14".
+ */
+
+} PCIe_ENGINE_DATA;
+
+/// PCIe port descriptor
+typedef struct {
+ IN UINT32 Flags; /**< Descriptor flags
+ * @li @b Bit31 - last descriptor in complex
+ */
+ IN PCIe_ENGINE_DATA EngineData; ///< Engine data
+ IN PCIe_PORT_DATA Port; ///< PCIe port specific configuration info
+} PCIe_PORT_DESCRIPTOR;
+
+/// DDI descriptor
+typedef struct {
+ IN UINT32 Flags; /**< Descriptor flags
+ * @li @b Bit31 - last descriptor in complex
+ */
+ IN PCIe_ENGINE_DATA EngineData; ///< Engine data
+ IN PCIe_DDI_DATA Ddi; ///< DDI port specific configuration info
+} PCIe_DDI_DESCRIPTOR;
+
+/// PCIe Complex descriptor
+typedef struct {
+ IN UINT32 Flags; /**< Descriptor flags
+ * @li @b Bit31 - last descriptor in topology
+ */
+ IN UINT32 SocketId; ///< Socket Id
+ IN PCIe_PORT_DESCRIPTOR *PciePortList; ///< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
+ IN PCIe_DDI_DESCRIPTOR *DdiLinkList; ///< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
+ IN VOID *Reserved; ///< Reserved for future use
+} PCIe_COMPLEX_DESCRIPTOR;
+
+/// Action to control PCIe slot reset
+typedef enum {
+ AssertSlotReset, ///< Assert slot reset
+ DeassertSlotReset ///< Deassert slot reset
+} PCIE_RESET_CONTROL;
+
+///Slot Reset Info
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN UINT8 ResetId; ///< Slot reset ID as specified in PCIe_PORT_DESCRIPTOR
+ IN UINT8 ResetControl; ///< Reset control as in PCIE_RESET_CONTROL
+} PCIe_SLOT_RESET_INFO;
+
+/// Engine descriptor type
+typedef enum {
+ PcieUnusedEngine = 0, ///< Unused descriptor
+ PciePortEngine = 1, ///< PCIe port
+ PcieDdiEngine = 2, ///< DDI
+ MaxPcieEngine ///< Max engine type for boundary check.
+} PCIE_ENGINE_TYPE;
+
+/// PCIe link capability/speed
+typedef enum {
+ PcieGenMaxSupported, ///< Maximum supported
+ PcieGen1 = 1, ///< Gen1
+ PcieGen2, ///< Gen2
+ MaxPcieGen ///< Max Gen for boundary check
+} PCIE_LINK_SPEED_CAP;
+
+/// PCIe PSPP Power policy
+typedef enum {
+ PsppDisabled, ///< PSPP disabled
+ PsppPerformance = 1, ///< Performance
+ PsppBalanceHigh, ///< Balance-High
+ PsppBalanceLow, ///< Balance-Low
+ PsppPowerSaving, ///< Power Saving
+ MaxPspp ///< Max Pspp for boundary check
+} PCIE_PSPP_POLICY;
+
+/// DDI display connector type
+typedef enum {
+ ConnectorTypeDP, ///< DP
+ ConnectorTypeEDP, ///< eDP
+ ConnectorTypeSingleLinkDVI, ///< Single Link DVI-D
+ ConnectorTypeDualLinkDVI, ///< Dual Link DVI-D
+ ConnectorTypeHDMI, ///< HDMI
+ ConnectorTypeTravisDpToVga, ///< Travis DP-to-VGA
+ ConnectorTypeTravisDpToLvds, ///< Travis DP-to-LVDS
+ ConnectorTypeNutmegDpToVga, ///< Hudson-2 NutMeg DP-to-VGA
+ ConnectorTypeSingleLinkDviI, ///< Single Link DVI-I
+ ConnectorTypeCrt, ///< CRT (VGA)
+ ConnectorTypeLvds, ///< LVDS
+ ConnectorTypeAutoDetect, ///< VBIOS auto detect connector type (native LVDS, eDP or Travis-LVDS)
+ MaxConnectorType ///< Not valid value, used to verify input
+} PCIE_CONNECTOR_TYPE;
+
+/// PCIe link channel type
+typedef enum {
+ ChannelTypeLowLoss, ///< Low Loss
+ ChannelTypeHighLoss, ///< High Loss
+ ChannelTypeMob0db, ///< Mobile 0dB
+ ChannelTypeMob3db, ///< Mobile 3dB
+ ChannelTypeExt6db, ///< Extended 6dB
+ ChannelTypeExt8db, ///< Extended 8dB
+ MaxChannelType ///< Not valid value, used to verify input
+} PCIE_CHANNEL_TYPE;
+
+/// PCIe link ASPM
+typedef enum {
+ AspmDisabled, ///< Disabled
+ AspmL0s, ///< PCIe L0s link state
+ AspmL1, ///< PCIe L1 link state
+ AspmL0sL1, ///< PCIe L0s & L1 link state
+ MaxAspm ///< Not valid value, used to verify input
+} PCIE_ASPM_TYPE;
+
+/// PCIe link hotplug support
+typedef enum {
+ HotplugDisabled, ///< Hotplug disable
+ HotplugBasic, ///< Basic Hotplug
+ HotplugServer, ///< Server Hotplug
+ HotplugEnhanced, ///< Enhanced
+ HotplugInboard, ///< Inboard
+ MaxHotplug ///< Not valid value, used to verify input
+} PCIE_HOTPLUG_TYPE;
+
+/// PCIe link initialization
+typedef enum {
+ PortDisabled, ///< Disable
+ PortEnabled ///< Enable
+} PCIE_PORT_ENABLE;
+
+/// DDI Aux channel
+typedef enum {
+ Aux1, ///< Aux1
+ Aux2, ///< Aux2
+ Aux3, ///< Aux3
+ Aux4, ///< Aux4
+ Aux5, ///< Aux5
+ Aux6, ///< Aux6
+ MaxAux ///< Not valid value, used to verify input
+} PCIE_AUX_TYPE;
+
+/// DDI Hdp Index
+typedef enum {
+ Hdp1, ///< Hdp1
+ Hdp2, ///< Hdp2
+ Hdp3, ///< Hdp3
+ Hdp4, ///< Hdp4
+ Hdp5, ///< Hdp5
+ Hdp6, ///< Hdp6
+ MaxHdp ///< Not valid value, used to verify input
+} PCIE_HDP_TYPE;
+
+// Macro for statically initialization of various structures
+#define PCIE_ENGINE_DATA_INITIALIZER(mType, mStartLane, mEndLane) {mType, mStartLane, mEndLane}
+#define PCIE_PORT_DATA_INITIALIZER(mPortPresent, mChannelType, mDevAddress, mHotplug, mMaxLinkSpeed, mMaxLinkCap, mAspm, mResetId) \
+{mPortPresent, mChannelType, mDevAddress, 0, mMaxLinkSpeed, mAspm, mHotplug, mResetId, {0, mMaxLinkCap} }
+#define PCIE_DDI_DATA_INITIALIZER(mConnectorType, mAuxIndex, mHpdIndex ) \
+{mConnectorType, mAuxIndex, mHpdIndex, {0, 0}}
+#define PCIE_DDI_DATA_INITIALIZER_V1(mConnectorType, mAuxIndex, mHpdIndex, mMapping0, mMapping1) \
+{mConnectorType, mAuxIndex, mHpdIndex, {mMapping0, mMapping1}}
+
+
+/*----------------------------------------------------------------------------
+ * GNB configuration info
+ *----------------------------------------------------------------------------
+ */
+/// Configuration settings for GNB.
+typedef struct {
+ IN UINT8 Gnb3dStereoPinIndex; ///< 3D Stereo Pin ID.
+ ///< @li 0 = Stereo 3D is disabled (default).
+ ///< @li 1 = Use processor pin HPD1.
+ ///< @li 2 = Use processor pin HPD2
+ ///< @li 3 = Use processor pin HPD3
+ ///< @li 4 = Use processor pin HPD4
+ ///< @li 5 = Use processor pin HPD5
+ ///< @li 6 = Use processor pin HPD6
+ ///< @BldCfgItem{BLDCFG_STEREO_3D_PINOUT}
+ IN UINT16 LvdsSpreadSpectrum; ///< Spread spectrum value in 0.01 %
+ ///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM}
+ IN UINT16 LvdsSpreadSpectrumRate; ///< Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz
+ ///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE}
+} GNB_ENV_CONFIGURATION;
+
+/// GNB configuration info
+typedef struct {
+ IN PCIe_COMPLEX_DESCRIPTOR *PcieComplexList; /**< Pointer to array of structures describe PCIe topology on each processor package or NULL.
+ * Last element of array must ne terminated with DESCRIPTOR_TERMINATE_LIST
+ * Example of topology definition for single socket system:
+ * @code
+ * PCIe_PORT_DESCRIPTOR PortList [] = {
+ * // Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...)
+ * {
+ * 0, //Descriptor flags
+ * PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15),
+ * PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+ * },
+ * // Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...)
+ * {
+ * 0, //Descriptor flags
+ * PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 19),
+ * PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+ * },
+ * // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
+ * {
+ * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
+ * PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
+ * PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+ * }
+ * };
+ * PCIe_PORT_DESCRIPTOR DdiList [] = {
+ * // Initialize Ddi descriptor (DDI interface Lanes 24:27, Display Port Connector, ...)
+ * {
+ * 0, //Descriptor flags
+ * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27),
+ * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1, 0)
+ * },
+ * // Initialize Ddi descriptor (DDI interface Lanes 28:31, HDMI, ...)
+ * {
+ * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
+ * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31),
+ * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2, 0)
+ * }
+ * };
+ * PCIe_COMPLEX_DESCRIPTOR PlatformTopology = {
+ * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate complexes list
+ * 0, //Socket ID
+ * &PortList[0],
+ * &DdiList[0],
+ * }
+ * @endcode
+ */
+ IN UINT8 PsppPolicy; /**< PSPP (PCIe Speed Power Policy)
+ * @li @b 0 - Disabled
+ * @li @b 1 - Performance
+ * @li @b 2 - Balance-High
+ * @li @b 3 - Balance-Low
+ * @li @b 4 - Power Saving
+ */
+
+} GNB_CONFIGURATION;
+//
+// MEMORY-SPECIFIC DATA STRUCTURES
+//
+//
+//
+//
+// AGESA MAXIMIUM VALUES
+//
+// These Max values are used to define array sizes and associated loop
+// counts in the code. They reflect the maximum values that AGESA
+// currently supports and does not necessarily reflect the hardware
+// capabilities of configuration.
+//
+
+#define MAX_SOCKETS_SUPPORTED 8 ///< Max number of sockets in system
+#define MAX_CHANNELS_PER_SOCKET 4 ///< Max Channels per sockets
+#define MAX_DIMMS_PER_CHANNEL 4 ///< Max DIMMs on a memory channel (independent of platform)
+#define NUMBER_OF_DELAY_TABLES 9 ///< Number of tables defined in CH_DEF_STRUCT.
+ ///< Eg: UINT16 *RcvEnDlys;
+ ///< UINT8 *WrDqsDlys;
+ ///< UINT8 *RdDqsDlys;
+ ///< UINT8 *WrDatDlys;
+ ///< UINT8 *RdDqsMinDlys;
+ ///< UINT8 *RdDqsMaxDlys;
+ ///< UINT8 *WrDatMinDlys;
+ ///< UINT8 *WrDatMaxDlys;
+#define NUMBER_OF_FAILURE_MASK_TABLES 1 ///< Number of failure mask tables
+
+#define MAX_PLATFORM_TYPES 16 ///< Platform types per system
+
+#define MCT_TRNG_KEEPOUT_START 0x00004000 ///< base [39:8]
+#define MCT_TRNG_KEEPOUT_END 0x00007FFF ///< base [39:8]
+
+#define UMA_ATTRIBUTE_INTERLEAVE 0x80000000 ///< Uma Region is interleaved
+#define UMA_ATTRIBUTE_ON_DCT0 0x40000000 ///< UMA resides on memory that belongs to DCT0
+#define UMA_ATTRIBUTE_ON_DCT1 0x20000000 ///< UMA resides on memory that belongs to DCT1
+
+typedef UINT8 PSO_TABLE; ///< Platform Configuration Table
+
+// AGESA DEFINITIONS
+//
+// Many of these are derived from the platform and hardware specific definitions
+
+/// EccSymbolSize override value
+#define ECCSYMBOLSIZE_USE_BKDG 0 ///< Use BKDG Recommended Value
+#define ECCSYMBOLSIZE_FORCE_X4 4 ///< Force to x4
+#define ECCSYMBOLSIZE_FORCE_X8 8 ///< Force to x8
+/// CPU Package Type
+#define PT_L1 0 ///< L1 Package type
+#define PT_M2 1 ///< AM Package type
+#define PT_S1 2 ///< S1 Package type
+
+/// Structures use to pass system Logical CPU-ID
+typedef struct {
+ IN OUT UINT64 Family; ///< Indicates logical ID Family
+ IN OUT UINT64 Revision; ///< Indicates logical ID Family
+} CPU_LOGICAL_ID;
+
+/// Build Configuration values for BLDCFG_AMD_PLATFORM_TYPE
+typedef enum {
+ AMD_PLATFORM_SERVER = 0x8000, ///< Server
+ AMD_PLATFORM_DESKTOP = 0x10000, ///< Desktop
+ AMD_PLATFORM_MOBILE = 0x20000, ///< Mobile
+} AMD_PLATFORM_TYPE;
+
+/// Dram technology type
+typedef enum {
+ DDR2_TECHNOLOGY, ///< DDR2 technology
+ DDR3_TECHNOLOGY ///< DDR3 technology
+} TECHNOLOGY_TYPE;
+
+/// Build Configuration values for BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT & BLDCFG_MEMORY_CLOCK_SELECT
+typedef enum {
+ DDR400_FREQUENCY = 200, ///< DDR 400
+ DDR533_FREQUENCY = 266, ///< DDR 533
+ DDR667_FREQUENCY = 333, ///< DDR 667
+ DDR800_FREQUENCY = 400, ///< DDR 800
+ DDR1066_FREQUENCY = 533, ///< DDR 1066
+ DDR1333_FREQUENCY = 667, ///< DDR 1333
+ DDR1600_FREQUENCY = 800, ///< DDR 1600
+ DDR1866_FREQUENCY = 933, ///< DDR 1866
+ UNSUPPORTED_DDR_FREQUENCY ///< Highest limit of DDR frequency
+} MEMORY_BUS_SPEED;
+
+/// Build Configuration values for BLDCFG_MEMORY_QUADRANK_TYPE
+typedef enum {
+ QUADRANK_REGISTERED, ///< Quadrank registered DIMM
+ QUADRANK_UNBUFFERED ///< Quadrank unbuffered DIMM
+} QUANDRANK_TYPE;
+
+/// Build Configuration values for BLDCFG_TIMING_MODE_SELECT
+typedef enum {
+ TIMING_MODE_AUTO, ///< Use best rate possible
+ TIMING_MODE_LIMITED, ///< Set user top limit
+ TIMING_MODE_SPECIFIC ///< Set user specified speed
+} USER_MEMORY_TIMING_MODE;
+
+/// Build Configuration values for BLDCFG_POWER_DOWN_MODE
+typedef enum {
+ POWER_DOWN_BY_CHANNEL, ///< Channel power down mode
+ POWER_DOWN_BY_CHIP_SELECT, ///< Chip select power down mode
+ POWER_DOWN_MODE_AUTO ///< AGESA to select power down mode
+} POWER_DOWN_MODE;
+
+/// Low voltage support
+typedef enum {
+ VOLT1_5, ///< 1.5 Volt
+ VOLT1_35, ///< 1.35 Volt
+ VOLT1_25, ///< 1.25 Volt
+ VOLT_UNSUPPORTED = 0xFF ///< No common voltage found
+} DIMM_VOLTAGE;
+
+/// UMA Mode
+typedef enum {
+ UMA_NONE = 0, ///< UMA None
+ UMA_SPECIFIED = 1, ///< UMA Specified
+ UMA_AUTO = 2 ///< UMA Auto
+} UMA_MODE;
+
+/// Build Configuration values for BLDCFG_UMA_ALIGNMENT
+typedef enum {
+ NO_UMA_ALIGNED = 0x00FFFFFF, ///< NO UMA aligned
+ UMA_128MB_ALIGNED = 0x00FFF800, ///< UMA 128MB aligned
+ UMA_256MB_ALIGNED = 0x00FFF000, ///< UMA 256MB aligned
+ UMA_512MB_ALIGNED = 0x00FFE000, ///< UMA 512MB aligned
+} UMA_ALIGNMENT;
+
+///
+/// Global MCT Configuration Status Word (GStatus)
+///
+typedef enum {
+ GsbMTRRshort, ///< Ran out of MTRRs while mapping memory
+ GsbAllECCDimms, ///< All banks of all Nodes are ECC capable
+ GsbDramECCDis, ///< Dram ECC requested but not enabled.
+ GsbSoftHole, ///< A Node Base gap was created
+ GsbHWHole, ///< A HW dram remap was created
+ GsbNodeIntlv, ///< Node Memory interleaving was enabled
+ GsbSpIntRemapHole, ///< Special condition for Node Interleave and HW remapping
+ GsbEnDIMMSpareNW, ///< Indicates that DIMM Spare can be used without a warm reset
+
+ GsbEOL ///< End of list
+} GLOBAL_STATUS_FIELD;
+
+///
+/// Local Error Status (DIE_STRUCT.ErrStatus[31:0])
+///
+typedef enum {
+ EsbNoDimms, ///< No DIMMs
+ EsbSpdChkSum, ///< SPD Checksum fail
+ EsbDimmMismatchM, ///< dimm module type(buffer) mismatch
+ EsbDimmMismatchT, ///< dimm CL/T mismatch
+ EsbDimmMismatchO, ///< dimm organization mismatch (128-bit)
+ EsbNoTrcTrfc, ///< SPD missing Trc or Trfc info
+ EsbNoCycTime, ///< SPD missing byte 23 or 25
+ EsbBkIntDis, ///< Bank interleave requested but not enabled
+ EsbDramECCDis, ///< Dram ECC requested but not enabled
+ EsbSpareDis, ///< Online spare requested but not enabled
+ EsbMinimumMode, ///< Running in Minimum Mode
+ EsbNoRcvrEn, ///< No DQS Receiver Enable pass window found
+ EsbSmallRcvr, ///< DQS Rcvr En pass window too small (far right of dynamic range)
+ EsbNoDqsPos, ///< No DQS-DQ passing positions
+ EsbSmallDqs, ///< DQS-DQ passing window too small
+ EsbDCBKScrubDis, ///< DCache scrub requested but not enabled
+
+ EsbEMPNotSupported, ///< Processor is not capable for EMP.
+ EsbEMPConflict, ///< EMP requested but cannot be enabled since
+ ///< channel interleaving, bank interleaving, or bank swizzle is enabled.
+ EsbEMPDis, ///< EMP requested but cannot be enabled since
+ ///< memory size of each DCT is not a power of two.
+
+ EsbEOL ///< End of list
+} ERROR_STATUS_FIELD;
+
+///
+/// Local Configuration Status (DIE_STRUCT.Status[31:0])
+///
+typedef enum {
+ SbRegistered, ///< All DIMMs are Registered
+ SbEccDimms, ///< All banks ECC capable
+ SbParDimms, ///< All banks Addr/CMD Parity capable
+ SbDiagClks, ///< Jedec ALL slots clock enable diag mode
+ Sb128bitmode, ///< DCT in 128-bit mode operation
+ Sb64MuxedMode, ///< DCT in 64-bit mux'ed mode.
+ Sb2TMode, ///< 2T CMD timing mode is enabled.
+ SbSWNodeHole, ///< Remapping of Node Base on this Node to create a gap.
+ SbHWHole, ///< Memory Hole created on this Node using HW remapping.
+ SbOver400Mhz, ///< DCT freq greater than or equal to 400MHz flag
+ SbDQSPosPass2, ///< Used for TrainDQSPos DIMM0/1, when freq greater than or equal to 400MHz
+ SbDQSRcvLimit, ///< Used for DQSRcvEnTrain to know we have reached the upper bound.
+ SbExtConfig, ///< Indicate the default setting for extended PCI configuration support
+ SbLrdimms, ///< All DIMMs are LRDIMMs
+
+ SbEOL ///< End of list
+} LOCAL_STATUS_FIELD;
+
+
+///< CPU MSR Register definitions ------------------------------------------
+#define SYS_CFG 0xC0010010
+#define TOP_MEM 0xC001001A
+#define TOP_MEM2 0xC001001D
+#define HWCR 0xC0010015
+#define NB_CFG 0xC001001F
+
+#define FS_BASE 0xC0000100
+#define IORR0_BASE 0xC0010016
+#define IORR0_MASK 0xC0010017
+#define BU_CFG 0xC0011023
+#define BU_CFG2 0xC001102A
+#define COFVID_STAT 0xC0010071
+#define TSC 0x10
+
+//-----------------------------------------------------------------------------
+///
+/// SPD Data for each DIMM.
+///
+typedef struct _SPD_DEF_STRUCT {
+ IN BOOLEAN DimmPresent; ///< Indicates that the DIMM is present and Data is valid
+ IN UINT8 Data[256]; ///< Buffer for 256 Bytes of SPD data from DIMM
+} SPD_DEF_STRUCT;
+
+///
+/// Channel Definition Structure.
+/// This data structure defines entries that are specific to the channel initialization
+///
+typedef struct _CH_DEF_STRUCT {
+ OUT UINT8 ChannelID; ///< Physical channel ID of a socket(0 = CH A, 1 = CH B, 2 = CH C, 3 = CH D)
+ OUT TECHNOLOGY_TYPE TechType; ///< Technology type of this channel
+ OUT UINT8 ChDimmPresent; ///< For each bit n 0..7, 1 = DIMM n is present.
+ ///< DIMM# Select Signal
+ ///< 0 MA0_CS_L[0, 1]
+ ///< 1 MB0_CS_L[0, 1]
+ ///< 2 MA1_CS_L[0, 1]
+ ///< 3 MB1_CS_L[0, 1]
+ ///< 4 MA2_CS_L[0, 1]
+ ///< 5 MB2_CS_L[0, 1]
+ ///< 6 MA3_CS_L[0, 1]
+ ///< 7 MB3_CS_L[0, 1]
+
+ OUT struct _DCT_STRUCT *DCTPtr; ///< Pointer to the DCT data of this channel.
+ OUT struct _DIE_STRUCT *MCTPtr; ///< Pointer to the node data of this channel.
+ OUT SPD_DEF_STRUCT *SpdPtr; ///< Pointer to the SPD data for this channel. (Setup by NB Constructor)
+ OUT SPD_DEF_STRUCT *DimmSpdPtr[MAX_DIMMS_PER_CHANNEL]; ///< Array of pointers to
+ ///< SPD Data for each Dimm. (Setup by Tech Block Constructor)
+ OUT UINT8 ChDimmValid; ///< For each bit n 0..3, 1 = DIMM n is valid and is/will be configured where 4..7 are reserved.
+ ///<
+ OUT UINT8 RegDimmPresent; ///< For each bit n 0..3, 1 = DIMM n is a registered DIMM where 4..7 are reserved.
+ OUT UINT8 LrDimmPresent; ///< For each bit n 0..3, 1 = DIMM n is Load Reduced DIMM where 4..7 are reserved.
+ OUT UINT8 SODimmPresent; ///< For each bit n 0..3, 1 = DIMM n is a SO-DIMM, where 4..7 are reserved.
+ OUT UINT8 Loads; ///< Number of devices loading bus
+ OUT UINT8 Dimms; ///< Number of DIMMs loading Channel
+ OUT UINT8 Ranks; ///< Number of ranks loading Channel DATA
+ OUT BOOLEAN SlowMode; ///< 1T or 2T CMD mode (slow access mode)
+ ///< FALSE = 1T
+ ///< TRUE = 2T
+ ///< The following pointers will be pointed to dynamically allocated buffers.
+ ///< Each buffer is two dimensional (RowCount x ColumnCount) and is lay-outed as in below.
+ ///< Example: If DIMM and Byte based training, then
+ ///< XX is a value in Hex
+ ///< BYTE 0, BYTE 1, BYTE 2, BYTE 3, BYTE 4, BYTE 5, BYTE 6, BYTE 7, ECC BYTE
+ ///< Row1 - Logical DIMM0 XX XX XX XX XX XX XX XX XX
+ ///< Row2 - Logical DIMM1 XX XX XX XX XX XX XX XX XX
+ OUT UINT16 *RcvEnDlys; ///< DQS Receiver Enable Delays
+ OUT UINT8 *WrDqsDlys; ///< Write DQS delays (only valid for DDR3)
+ OUT UINT8 *RdDqsDlys; ///< Read Dqs delays
+ OUT UINT8 *WrDatDlys; ///< Write Data delays
+ OUT UINT8 *RdDqsMinDlys; ///< Minimum Window for Read DQS
+ OUT UINT8 *RdDqsMaxDlys; ///< Maximum Window for Read DQS
+ OUT UINT8 *WrDatMinDlys; ///< Minimum Window for Write data
+ OUT UINT8 *WrDatMaxDlys; ///< Maximum Window for Write data
+ OUT UINT8 RowCount; ///< Number of rows of the allocated buffer.
+ OUT UINT8 ColumnCount; ///< Number of columns of the allocated buffer.
+ OUT UINT8 *FailingBitMask; ///< Table of masks to Track Failing bits
+ OUT UINT32 DctOdcCtl; ///< Output Driver Strength (see BKDG FN2:Offset 9Ch, index 00h)
+ OUT UINT32 DctAddrTmg; ///< Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h)
+ OUT UINT32 PhyRODTCSLow; ///< Phy Read ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 180h)
+ OUT UINT32 PhyRODTCSHigh; ///< Phy Read ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 181h)
+ OUT UINT32 PhyWODTCSLow; ///< Phy Write ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 182h)
+ OUT UINT32 PhyWODTCSHigh; ///< Phy Write ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 183)
+ OUT UINT8 PhyWLODT[4]; ///< Write Levelization ODT Pattern for Dimm 0-3 (see BKDG FN2:Offset 9Ch, index 0x8[11:8])
+ OUT UINT16 DctEccDqsLike; ///< DCT DQS ECC UINT8 like...
+ OUT UINT8 DctEccDqsScale; ///< DCT DQS ECC UINT8 scale
+ OUT UINT16 PtrPatternBufA; ///< Ptr on stack to aligned DQS testing pattern
+ OUT UINT16 PtrPatternBufB; ///< Ptr on stack to aligned DQS testing pattern
+ OUT UINT8 ByteLane; ///< Current UINT8 Lane (0..7)
+ OUT UINT8 Direction; ///< Current DQS-DQ training write direction (0=read, 1=write)
+ OUT UINT8 Pattern; ///< Current pattern
+ OUT UINT8 DqsDelay; ///< Current DQS delay value
+ OUT UINT16 HostBiosSrvc1; ///< UINT16 sized general purpose field for use by host BIOS. Scratch space.
+ OUT UINT32 HostBiosSrvc2; ///< UINT32 sized general purpose field for use by host BIOS. Scratch space.
+ OUT UINT16 DctMaxRdLat; ///< Max Read Latency (ns) for the DCT
+ OUT UINT8 DIMMValidCh; ///< DIMM# in CH
+ OUT UINT8 MaxCh; ///< Max number of CH in system
+ OUT UINT8 Dct; ///< Dct pointer
+ OUT UINT8 WrDatGrossH; ///< Write Data Gross delay high value
+ OUT UINT8 DqsRcvEnGrossL; ///< DQS Receive Enable Gross Delay low
+
+ OUT UINT8 TrwtWB; ///< Non-SPD timing value for TrwtWB
+ OUT UINT8 CurrRcvrDctADelay; ///< for keep current RcvrEnDly
+ OUT UINT16 T1000; ///< get the T1000 figure (cycle time (ns) * 1K)
+ OUT UINT8 DqsRcvEnPass; ///< for TrainRcvrEn UINT8 lane pass flag
+ OUT UINT8 DqsRcvEnSaved; ///< for TrainRcvrEn UINT8 lane saved flag
+ OUT UINT8 SeedPass1Remainder; ///< for Phy assisted DQS receiver enable training
+
+ OUT UINT8 ClToNbFlag; ///< is used to restore ClLinesToNbDis bit after memory
+ OUT UINT32 NodeSysBase; ///< for channel interleave usage
+ OUT UINT8 RefRawCard[MAX_DIMMS_PER_CHANNEL]; ///< Array of rawcards detected
+ OUT UINT8 CtrlWrd02[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 2 values per DIMM
+ OUT UINT8 CtrlWrd03[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 3 values per DIMM
+ OUT UINT8 CtrlWrd04[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 4 values per DIMM
+ OUT UINT8 CtrlWrd05[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 5 values per DIMM
+ OUT UINT8 CtrlWrd08[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 8 values per DIMM
+
+ OUT UINT16 CsPresentDCT; ///< For each bit n 0..7, 1 = Chip-select n is present
+ OUT UINT8 DimmMirrorPresent; ///< For each bit n 0..3, 1 = DIMM n is OnDimmMirror capable where 4..7 are reserved.
+ OUT UINT8 DimmSpdCse; ///< For each bit n 0..3, 1 = DIMM n SPD checksum error where 4..7 are reserved.
+ OUT UINT8 DimmExclude; ///< For each bit n 0..3, 1 = DIMM n gets excluded where 4..7 are reserved.
+ OUT UINT8 DimmYr06; ///< Bitmap indicating which Dimms have a manufacturer's year code <= 2006
+ OUT UINT8 DimmWk2406; ///< Bitmap indicating which Dimms have a manufacturer's week code <= 24 of 2006 (June)
+ OUT UINT8 DimmPlPresent; ///< Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.
+ OUT UINT8 DimmQrPresent; ///< QuadRank DIMM present?
+ OUT UINT8 DimmDrPresent; ///< Bitmap indicating that Dual Rank Dimms are present
+ OUT UINT8 DimmSRPresent; ///< Bitmap indicating that Single Rank Dimms are present
+ OUT UINT8 Dimmx4Present; ///< For each bit n 0..3, 1 = DIMM n contains x4 data devices. where 4..7 are reserved.
+ OUT UINT8 Dimmx8Present; ///< For each bit n 0..3, 1 = DIMM n contains x8 data devices. where 4..7 are reserved.
+ OUT UINT8 Dimmx16Present; ///< For each bit n 0..3, 1 = DIMM n contains x16 data devices. where 4..7 are reserved.
+ OUT UINT8 LrdimmPhysicalRanks[MAX_DIMMS_PER_CHANNEL];///< Number of Physical Ranks for LRDIMMs
+ OUT UINT8 LrDimmLogicalRanks[MAX_DIMMS_PER_CHANNEL];///< Number of LRDIMM Logical ranks in this configuration
+ OUT UINT8 LrDimmRankMult[MAX_DIMMS_PER_CHANNEL];///< Rank Multipication factor per dimm.
+
+ OUT UINT8 *MemClkDisMap; ///< This pointer will be set to point to an array that describes
+ ///< the routing of M[B,A]_CLK pins to the DIMMs' ranks. AGESA will
+ ///< base on this array to disable unused MemClk to save power.
+ ///<
+ ///< The array must have 8 entries. Each entry, which associates with
+ ///< one MemClkDis bit, is a bitmap of 8 CS that that MemClk is routed to.
+ ///< Example:
+ ///< BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package
+ ///< is like below:
+ ///< Bit AM3/S1g3 pin name
+ ///< 0 M[B,A]_CLK_H/L[0]
+ ///< 1 M[B,A]_CLK_H/L[1]
+ ///< 2 M[B,A]_CLK_H/L[2]
+ ///< 3 M[B,A]_CLK_H/L[3]
+ ///< 4 M[B,A]_CLK_H/L[4]
+ ///< 5 M[B,A]_CLK_H/L[5]
+ ///< 6 M[B,A]_CLK_H/L[6]
+ ///< 7 M[B,A]_CLK_H/L[7]
+ ///< And platform has the following routing:
+ ///< CS0 M[B,A]_CLK_H/L[4]
+ ///< CS1 M[B,A]_CLK_H/L[2]
+ ///< CS2 M[B,A]_CLK_H/L[3]
+ ///< CS3 M[B,A]_CLK_H/L[5]
+ ///< Then MemClkDisMap should be pointed to the following array:
+ ///< CLK_2 CLK_3 CLK_4 CLK_5
+ ///< 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00
+ ///< Each entry of the array is the bitmask of 8 chip selects.
+
+ OUT UINT8 *CKETriMap; ///< This pointer will be set to point to an array that describes
+ ///< the routing of CKE pins to the DIMMs' ranks.
+ ///< The array must have 2 entries. Each entry, which associates with
+ ///< one CKE pin, is a bitmap of 8 CS that that CKE is routed to.
+ ///< AGESA will base on this array to disable unused CKE pins to save power.
+
+ OUT UINT8 *ODTTriMap; ///< This pointer will be set to point to an array that describes
+ ///< the routing of ODT pins to the DIMMs' ranks.
+ ///< The array must have 4 entries. Each entry, which associates with
+ ///< one ODT pin, is a bitmap of 8 CS that that ODT is routed to.
+ ///< AGESA will base on this array to disable unused ODT pins to save power.
+
+ OUT UINT8 *ChipSelTriMap; ///< This pointer will be set to point to an array that describes
+ ///< the routing of chip select pins to the DIMMs' ranks.
+ ///< The array must have 8 entries. Each entry is a bitmap of 8 CS.
+ ///< AGESA will base on this array to disable unused Chip select pins to save power.
+
+ OUT BOOLEAN ExtendTmp; ///< If extended temperature is supported on all dimms on a channel.
+
+ OUT UINT8 Reserved[100]; ///< Reserved
+} CH_DEF_STRUCT;
+
+///
+/// DCT Channel Timing Parameters.
+/// This data structure sets timings that are specific to the channel.
+///
+typedef struct _CH_TIMING_STRUCT {
+ OUT UINT16 DctDimmValid; ///< For each bit n 0..3, 1=DIMM n is valid and is/will be configured where 4..7 are reserved.
+ OUT UINT16 DimmMirrorPresent; ///< For each bit n 0..3, 1=DIMM n is OnDimmMirror capable where 4..7 are reserved.
+ OUT UINT16 DimmSpdCse; ///< For each bit n 0..3, 1=DIMM n SPD checksum error where 4..7 are reserved.
+ OUT UINT16 DimmExclude; ///< For each bit n 0..3, 1 = DIMM n gets excluded where 4..7 are reserved.
+ OUT UINT16 CsPresent; ///< For each bit n 0..7, 1=Chip-select n is present
+ OUT UINT16 CsEnabled; ///< For each bit n 0..7, 1=Chip-select n is enabled
+ OUT UINT16 CsTestFail; ///< For each bit n 0..7, 1=Chip-select n is present but disabled
+ OUT UINT16 CsTrainFail; ///< Bitmap showing which chipselects failed training
+ OUT UINT16 DIMM1KPage; ///< For each bit n 0..3, 1=DIMM n contains 1K page devices. where 4..7 are reserved
+ OUT UINT16 DimmQrPresent; ///< QuadRank DIMM present?
+ OUT UINT16 DimmDrPresent; ///< Bitmap indicating that Dual Rank Dimms are present , where 4..7 are reserved
+ OUT UINT8 DimmSRPresent; ///< Bitmap indicating that Single Rank Dimms are present, where 4..7 are reserved
+ OUT UINT16 Dimmx4Present; ///< For each bit n 0..3, 1=DIMM n contains x4 data devices. where 4..7 are reserved
+ OUT UINT16 Dimmx8Present; ///< For each bit n 0..3, 1=DIMM n contains x8 data devices. where 4..7 are reserved
+ OUT UINT16 Dimmx16Present; ///< For each bit n 0..3, 1=DIMM n contains x16 data devices. where 4..7 are reserved
+
+ OUT UINT16 DIMMTrcd; ///< Minimax Trcd*40 (ns) of DIMMs
+ OUT UINT16 DIMMTrp; ///< Minimax Trp*40 (ns) of DIMMs
+ OUT UINT16 DIMMTrtp; ///< Minimax Trtp*40 (ns) of DIMMs
+ OUT UINT16 DIMMTras; ///< Minimax Tras*40 (ns) of DIMMs
+ OUT UINT16 DIMMTrc; ///< Minimax Trc*40 (ns) of DIMMs
+ OUT UINT16 DIMMTwr; ///< Minimax Twr*40 (ns) of DIMMs
+ OUT UINT16 DIMMTrrd; ///< Minimax Trrd*40 (ns) of DIMMs
+ OUT UINT16 DIMMTwtr; ///< Minimax Twtr*40 (ns) of DIMMs
+ OUT UINT16 DIMMTfaw; ///< Minimax Tfaw*40 (ns) of DIMMs
+ OUT UINT16 TargetSpeed; ///< Target DRAM bus speed in MHz
+ OUT UINT16 Speed; ///< DRAM bus speed in MHz
+ ///< 400 (MHz)
+ ///< 533 (MHz)
+ ///< 667 (MHz)
+ ///< 800 (MHz)
+ ///< and so on...
+ OUT UINT8 CasL; ///< CAS latency DCT setting (busclocks)
+ OUT UINT8 Trcd; ///< DCT Trcd (busclocks)
+ OUT UINT8 Trp; ///< DCT Trp (busclocks)
+ OUT UINT8 Trtp; ///< DCT Trtp (busclocks)
+ OUT UINT8 Tras; ///< DCT Tras (busclocks)
+ OUT UINT8 Trc; ///< DCT Trc (busclocks)
+ OUT UINT8 Twr; ///< DCT Twr (busclocks)
+ OUT UINT8 Trrd; ///< DCT Trrd (busclocks)
+ OUT UINT8 Twtr; ///< DCT Twtr (busclocks)
+ OUT UINT8 Tfaw; ///< DCT Tfaw (busclocks)
+ OUT UINT8 Trfc0; ///< DCT Logical DIMM0 Trfc
+ ///< 0 = 75ns (for 256Mb devs)
+ ///< 1 = 105ns (for 512Mb devs)
+ ///< 2 = 127.5ns (for 1Gb devs)
+ ///< 3 = 195ns (for 2Gb devs)
+ ///< 4 = 327.5ns (for 4Gb devs)
+ OUT UINT8 Trfc1; ///< DCT Logical DIMM1 Trfc (see Trfc0 for format)
+ OUT UINT8 Trfc2; ///< DCT Logical DIMM2 Trfc (see Trfc0 for format)
+ OUT UINT8 Trfc3; ///< DCT Logical DIMM3 Trfc (see Trfc0 for format)
+ OUT UINT32 DctMemSize; ///< Base[47:16], total DRAM size controlled by this DCT.
+ ///<
+ OUT BOOLEAN SlowMode; ///< 1T or 2T CMD mode (slow access mode)
+ ///< FALSE = 1T
+ ///< TRUE = 2T
+ OUT UINT8 TrwtTO; ///< DCT TrwtTO (busclocks)
+ OUT UINT8 Twrrd; ///< DCT Twrrd (busclocks)
+ OUT UINT8 Twrwr; ///< DCT Twrwr (busclocks)
+ OUT UINT8 Trdrd; ///< DCT Trdrd (busclocks)
+ OUT UINT8 TrwtWB; ///< DCT TrwtWB (busclocks)
+ OUT UINT8 TrdrdSD; ///< DCT TrdrdSD (busclocks)
+ OUT UINT8 TwrwrSD; ///< DCT TwrwrSD (busclocks)
+ OUT UINT8 TwrrdSD; ///< DCT TwrrdSD (busclocks)
+ OUT UINT16 MaxRdLat; ///< Max Read Latency
+ OUT UINT8 WrDatGrossH; ///< Temporary variables must be removed
+ OUT UINT8 DqsRcvEnGrossL; ///< Temporary variables must be removed
+} CH_TIMING_STRUCT;
+
+///
+/// Data for each DCT.
+/// This data structure defines data used to configure each DRAM controller.
+///
+typedef struct _DCT_STRUCT {
+ OUT UINT8 Dct; ///< Current Dct
+ OUT CH_TIMING_STRUCT Timings; ///< Channel Timing structure
+ OUT CH_DEF_STRUCT *ChData; ///< Pointed to a dynamically allocated array of Channel structures
+ OUT UINT8 ChannelCount; ///< Number of channel per this DCT
+} DCT_STRUCT;
+
+
+///
+/// Data Structure defining each Die.
+/// This data structure contains information that is used to configure each Die.
+///
+typedef struct _DIE_STRUCT {
+
+ /// Advanced:
+
+ OUT UINT8 NodeId; ///< Node ID of current controller
+ OUT UINT8 SocketId; ///< Socket ID of this Die
+ OUT UINT8 DieId; ///< ID of this die relative to the socket
+ OUT PCI_ADDR PciAddr; ///< Pci bus and device number of this controller.
+ OUT AGESA_STATUS ErrCode; ///< Current error condition of Node
+ ///< 0x0 = AGESA_SUCCESS
+ ///< 0x1 = AGESA_UNSUPPORTED
+ ///< 0x2 = AGESA_BOUNDS_CHK
+ ///< 0x3 = AGESA_ALERT
+ ///< 0x4 = AGESA_WARNING
+ ///< 0x5 = AGESA_ERROR
+ ///< 0x6 = AGESA_CRITICAL
+ ///< 0x7 = AGESA_FATAL
+ ///<
+ OUT BOOLEAN ErrStatus[EsbEOL]; ///< Error Status bit Field
+ ///<
+ OUT BOOLEAN Status[SbEOL]; ///< Status bit Field
+ ///<
+ OUT UINT32 NodeMemSize; ///< Base[47:16], total DRAM size controlled by both DCT0 and DCT1 of this Node.
+ ///<
+ OUT UINT32 NodeSysBase; ///< Base[47:16] (system address) DRAM base address of this Node.
+ ///<
+ OUT UINT32 NodeHoleBase; ///< If not zero, Base[47:16] (system address) of dram hole for HW remapping. Dram hole exists on this Node
+ ///<
+ OUT UINT32 NodeSysLimit; ///< Base[47:16] (system address) DRAM limit address of this Node.
+ ///<
+ OUT UINT32 DimmPresent; ///< For each bit n 0..7, 1 = DIMM n is present.
+ ///< DIMM# Select Signal
+ ///< 0 MA0_CS_L[0, 1]
+ ///< 1 MB0_CS_L[0, 1]
+ ///< 2 MA1_CS_L[0, 1]
+ ///< 3 MB1_CS_L[0, 1]
+ ///< 4 MA2_CS_L[0, 1]
+ ///< 5 MB2_CS_L[0, 1]
+ ///< 6 MA3_CS_L[0, 1]
+ ///< 7 MB3_CS_L[0, 1]
+ ///<
+ OUT UINT32 DimmValid; ///< For each bit n 0..7, 1 = DIMM n is valid and is / will be configured
+ OUT UINT32 RegDimmPresent; ///< For each bit n 0..7, 1 = DIMM n is registered DIMM
+ OUT UINT32 LrDimmPresent; ///< For each bit n 0..7, 1 = DIMM n is Load Reduced DIMM
+ OUT UINT32 DimmEccPresent; ///< For each bit n 0..7, 1 = DIMM n is ECC capable.
+ OUT UINT32 DimmParPresent; ///< For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable.
+ ///<
+ OUT UINT16 DimmTrainFail; ///< Bitmap showing which dimms failed training
+ OUT UINT16 ChannelTrainFail; ///< Bitmap showing the channel information about failed Chip Selects
+ ///< 0 in any bit field indicates Channel 0
+ ///< 1 in any bit field indicates Channel 1
+ OUT UINT8 Dct; ///< Need to be removed
+ ///< DCT pointer
+ OUT BOOLEAN GangedMode; ///< Ganged mode
+ ///< 0 = disabled
+ ///< 1 = enabled
+ OUT CPU_LOGICAL_ID LogicalCpuid; ///< The logical CPUID of the node
+ ///<
+ OUT UINT16 HostBiosSrvc1; ///< UINT16 sized general purpose field for use by host BIOS. Scratch space.
+ ///<
+ OUT UINT32 HostBiosSrvc2; ///< UINT32 sized general purpose field for use by host BIOS. Scratch space.
+ ///<
+ OUT UINT8 MLoad; ///< Need to be removed
+ ///< Number of devices loading MAA bus
+ ///<
+ OUT UINT8 MaxAsyncLat; ///< Legacy wrapper
+ ///<
+ OUT UINT8 ChbD3Rcvrdly; ///< Legacy wrapper
+ ///<
+ OUT UINT16 ChaMaxRdLat; ///< Max Read Latency (ns) for DCT 0
+ ///<
+ OUT UINT8 ChbD3BcRcvrdly; ///< CHB DIMM 3 Check UINT8 Receiver Enable Delay
+
+ OUT DCT_STRUCT *DctData; ///< Pointed to a dynamically allocated array of DCT_STRUCTs
+ OUT UINT8 DctCount; ///< Number of DCTs per this Die
+ OUT UINT8 Reserved[16]; ///< Reserved
+} DIE_STRUCT;
+
+/**********************************************************************
+ * S3 Support structure
+ **********************************************************************/
+/// AmdInitResume, AmdS3LateRestore, and AmdS3Save param structure
+typedef struct {
+ OUT UINT32 Signature; ///< "ASTR" for AMD Suspend-To-RAM
+ OUT UINT16 Version; ///< S3 Params version number
+ IN OUT UINT32 Flags; ///< Indicates operation
+ IN OUT VOID *NvStorage; ///< Pointer to memory critical save state data
+ IN OUT UINT32 NvStorageSize; ///< Size in bytes of the NvStorage region
+ IN OUT VOID *VolatileStorage; ///< Pointer to remaining AMD save state data
+ IN OUT UINT32 VolatileStorageSize; ///< Size in bytes of the VolatileStorage region
+} AMD_S3_PARAMS;
+
+///===============================================================================
+/// MEM_PARAMETER_STRUCT
+/// This data structure is used to pass wrapper parameters to the memory configuration code
+///
+typedef struct _MEM_PARAMETER_STRUCT {
+
+ // Basic (Return parameters)
+ // (This section contains the outbound parameters from the memory init code)
+
+ OUT BOOLEAN GStatus[GsbEOL]; ///< Global Status bitfield.
+ ///<
+ OUT UINT32 HoleBase; ///< If not zero Base[47:16] (system address) of sub 4GB dram hole for HW remapping.
+ ///<
+ OUT UINT32 Sub4GCacheTop; ///< If not zero, the 32-bit top of cacheable memory.
+ ///<
+ OUT UINT32 SysLimit; ///< Limit[47:16] (system address).
+ ///<
+
+ OUT DIMM_VOLTAGE DDR3Voltage; ///< Find support voltage and send back to platform BIOS.
+ ///< 0 = 1.5v
+ ///< 1 = 1.35v
+ ///< 2 = 1.2v
+ ///< 0xFF = Mixed 1.5V and 1.2V in the system. 1.5V dimms get excluded
+ ///< from the system.
+ ///<
+
+ OUT struct _MEM_DATA_STRUCT *MemData; ///< Access to global memory init data.
+
+ // Advanced (Optional parameters)
+ // Optional (all defaults values will be initialized by the
+ // 'AmdMemInitDataStructDef' based on AMD defaults. It is up
+ // to the IBV/OEM to change the defaults after initialization
+ // but prior to the main entry to the memory code):
+
+ // Memory Map/Mgt.
+
+ IN UINT16 BottomIo; ///< Bottom of 32-bit IO space (8-bits).
+ ///< NV_BOTTOM_IO[7:0]=Addr[31:24]
+ ///<
+ IN BOOLEAN MemHoleRemapping; ///< Memory Hole Remapping (1-bit).
+ ///< FALSE = disable
+ ///< TRUE = enable
+
+
+ // Dram Timing
+
+ IN USER_MEMORY_TIMING_MODE UserTimingMode; ///< User Memclock Mode.
+ ///< @BldCfgItem{BLDCFG_TIMING_MODE_SELECT}
+
+ IN MEMORY_BUS_SPEED MemClockValue; ///< Memory Clock Value.
+ ///< @BldCfgItem{BLDCFG_MEMORY_CLOCK_SELECT}
+
+
+ // Dram Configuration
+
+ IN BOOLEAN EnableBankIntlv; ///< Dram Bank (chip-select) Interleaving (1-bit).
+ ///< - FALSE =disable (default)
+ ///< - TRUE = enable
+ ///<
+ ///< @BldCfgItem{BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING}
+
+ IN BOOLEAN EnableNodeIntlv; ///< Node Memory Interleaving (1-bit).
+ ///< - FALSE = disable (default)
+ ///< - TRUE = enable
+ ///<
+ ///< @BldCfgItem{BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING}
+
+ IN BOOLEAN EnableChannelIntlv; ///< Channel Interleaving (1-bit).
+ ///< - FALSE = disable (default)
+ ///< - TRUE = enable
+ ///<
+ ///< @BldCfgItem{BLDCFG_MEMORY_CHANNEL_INTERLEAVING}
+ // ECC
+
+ IN BOOLEAN EnableEccFeature; ///< enable ECC error to go into MCE.
+ ///< - FALSE = disable (default)
+ ///< - TRUE = enable
+ ///<
+ ///< @BldCfgItem{BLDCFG_ENABLE_ECC_FEATURE}
+ // Dram Power
+
+ IN BOOLEAN EnablePowerDown; ///< CKE based power down mode (1-bit).
+ ///< - FALSE =disable (default)
+ ///< - TRUE =enable
+ ///<
+ ///< @BldCfgItem{BLDCFG_MEMORY_POWER_DOWN}
+
+ // Online Spare
+
+ IN BOOLEAN EnableOnLineSpareCtl; ///< Chip Select Spare Control bit 0.
+ ///< - FALSE = disable Spare (default)
+ ///< - TRUE = enable Spare
+ ///<
+ ///< @BldCfgItem{BLDCFG_ONLINE_SPARE}
+
+ IN UINT8 *TableBasedAlterations; ///< Desired modifications to register settings.
+
+ IN PSO_TABLE *PlatformMemoryConfiguration;
+ ///< A table that contains platform specific settings.
+ ///< For example, MemClk routing, the number of DIMM slots per channel, ....
+ ///< AGESA initializes this pointer with DefaultPlatformMemoryConfiguration that
+ ///< contains default conservative settings. Platform BIOS can either tweak
+ ///< DefaultPlatformMemoryConfiguration or reassign this pointer to its own table.
+ ///<
+ IN BOOLEAN EnableParity; ///< Parity control.
+ ///< - TRUE = enable
+ ///< - FALSE = disable (default)
+ ///<
+ ///< @BldCfgItem{BLDCFG_MEMORY_PARITY_ENABLE}
+
+ IN BOOLEAN EnableBankSwizzle; ///< BankSwizzle control.
+ ///< - FALSE = disable
+ ///< - TRUE = enable (default)
+ ///<
+ ///< @BldCfgItem{BLDCFG_BANK_SWIZZLE}
+
+ ///<
+
+ IN BOOLEAN EnableMemClr; ///< Memory Clear functionality control.
+ ///< - FALSE = disable
+ ///< - TRUE = enable (default)
+ ///<
+
+ // Uma Configuration
+
+ IN UMA_MODE UmaMode; ///< Uma Mode
+ ///< 0 = None
+ ///< 1 = Specified
+ ///< 2 = Auto
+ IN OUT UINT32 UmaSize; ///< The size of shared graphics dram (16-bits)
+ ///< NV_UMA_Size[31:0]=Addr[47:16]
+ ///<
+ OUT UINT32 UmaBase; ///< The allocated Uma base address (32-bits)
+ ///< NV_UMA_Base[31:0]=Addr[47:16]
+ ///<
+
+ /// Memory Restore Feature
+
+ IN BOOLEAN MemRestoreCtl; ///< Memory context restore control
+ ///< FALSE = perform memory init as normal (AMD default)
+ ///< TRUE = restore memory context and skip training. This requires
+ ///< MemContext is valid before AmdInitPost
+ ///<
+ IN BOOLEAN SaveMemContextCtl; ///< Control switch to save memory context at the end of MemAuto
+ ///< TRUE = AGESA will setup MemContext block before exit AmdInitPost
+ ///< FALSE = AGESA will not setup MemContext block. Platform is
+ ///< expected to call S3Save later in POST if it wants to
+ ///< use memory context restore feature.
+ ///<
+ IN OUT AMD_S3_PARAMS MemContext; ///< Memory context block describes the data that platform needs to
+ ///< save and restore for memory context restore feature to work.
+ ///< It uses the subset of S3Save block to save/restore. Hence platform
+ ///< may save only S3 block and uses it for both S3 resume and
+ ///< memory context restore.
+ ///< - If MemRestoreCtl is TRUE, platform needs to pass in MemContext
+ ///< before AmdInitPost.
+ ///< - If SaveMemContextCtl is TRUE, platform needs to save MemContext
+ ///< right after AmdInitPost.
+ ///<
+} MEM_PARAMETER_STRUCT;
+
+
+///
+/// Function definition.
+/// This data structure passes function pointers to the memory configuration code.
+/// The wrapper can use this structure with customized versions.
+///
+typedef struct _MEM_FUNCTION_STRUCT {
+
+ // PUBLIC required Internal functions
+
+ IN OUT BOOLEAN (*amdMemGetPsCfgU) ( VOID *pMemData); ///< Proc for Unbuffered DIMMs, platform specific
+ IN OUT BOOLEAN (*amdMemGetPsCfgR) (VOID *pMemData); ///< Proc for Registered DIMMs, platform specific
+
+ // PUBLIC optional functions
+
+ IN OUT VOID (*amdMemEccInit) (VOID *pMemData); ///< NB proc for ECC feature
+ IN OUT VOID (*amdMemChipSelectInterleaveInit) (VOID *pMemData); ///< NB proc for CS interleave feature
+ IN OUT VOID (*amdMemDctInterleavingInit) (VOID *pMemData); ///< NB proc for Channel interleave feature
+ IN OUT VOID (*amdMemMctInterleavingInit) (VOID *pMemData); ///< NB proc for Node interleave feature
+ IN OUT VOID (*amdMemParallelTraining) (VOID *pMemData); ///< NB proc for parallel training feature
+ IN OUT VOID (*amdMemEarlySampleSupport) (VOID *pMemData); ///< NB code for early sample support feature
+ IN OUT VOID (*amdMemMultiPartInitSupport) (VOID *pMemData); ///< NB code for 'multi-part'
+ IN OUT VOID (*amdMemOnlineSpareSupport) (VOID *pMemData); ///< NB code for On-Line Spare feature
+ IN OUT VOID (*amdMemUDimmInit) (VOID *pMemData); ///< NB code for UDIMMs
+ IN OUT VOID (*amdMemRDimmInit) (VOID *pMemData); ///< NB code for RDIMMs
+ IN OUT VOID (*amdMemLrDimmInit) (VOID *pMemData); ///< NB code for LRDIMMs
+
+ IN OUT UINT32 Reserved[100]; ///< Reserved for later function definition
+} MEM_FUNCTION_STRUCT;
+
+///
+/// Socket Structure
+///
+///
+typedef struct _MEM_SOCKET_STRUCT {
+ OUT VOID *ChannelPtr[MAX_CHANNELS_PER_SOCKET]; ///< Pointers to each channels training data
+
+ OUT VOID *TimingsPtr[MAX_CHANNELS_PER_SOCKET]; ///< Pointers to each channels timing data
+} MEM_SOCKET_STRUCT;
+
+///
+/// Contains all data relevant to Memory Initialization.
+///
+typedef struct _MEM_DATA_STRUCT {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+
+ IN MEM_PARAMETER_STRUCT *ParameterListPtr; ///< List of input Parameters
+
+ OUT MEM_FUNCTION_STRUCT FunctionList; ///< List of function Pointers
+
+ IN OUT AGESA_STATUS (*GetPlatformCfg[MAX_PLATFORM_TYPES]) (struct _MEM_DATA_STRUCT *MemData, UINT8 SocketID, CH_DEF_STRUCT *CurrentChannel); ///< look-up platform info
+
+ IN OUT BOOLEAN (*ErrorHandling)(struct _DIE_STRUCT *MCTPtr, UINT8 DCT, UINT16 ChipSelMask, AMD_CONFIG_PARAMS *StdHeader); ///< Error Handling
+
+
+ OUT MEM_SOCKET_STRUCT SocketList[MAX_SOCKETS_SUPPORTED]; ///< Socket list for memory code.
+ ///< SocketList is a shortcut for IBVs to retrieve training
+ ///< and timing data for each channel indexed by socket/channel,
+ ///< eliminating their need to parse die/dct/channel etc.
+ ///< It contains pointers to the populated data structures for
+ ///< each channel and skips the channel structures that are
+ ///< unpopulated. In the case of channels sharing the same DCT,
+ ///< the pTimings pointers will point to the same DCT Timing data.
+
+ OUT DIE_STRUCT *DiesPerSystem; ///< Pointed to an array of DIE_STRUCTs
+ OUT UINT8 DieCount; ///< Number of MCTs in the system.
+
+ IN SPD_DEF_STRUCT *SpdDataStructure; ///< Pointer to SPD Data structure
+
+ IN OUT struct _PLATFORM_CONFIGURATION *PlatFormConfig; ///< Platform profile/build option config structure
+
+ IN OUT BOOLEAN IsFlowControlSupported; ///< Indicates if flow control is supported
+
+ OUT UINT32 TscRate; ///< The rate at which the TSC increments in megahertz.
+
+} MEM_DATA_STRUCT;
+
+///
+/// Uma Structure
+///
+///
+typedef struct _UMA_INFO {
+ OUT UINT64 UmaBase; ///< UmaBase[63:0] = Addr[63:0]
+ OUT UINT32 UmaSize; ///< UmaSize[31:0] = Addr[31:0]
+ OUT UINT32 UmaAttributes; ///< Indicate the attribute of Uma
+ OUT UINT8 UmaMode; ///< Indicate the mode of Uma
+ OUT UINT16 MemClock; ///< Indicate memory running speed in MHz
+ OUT UINT8 Reserved[3]; ///< Reserved for future usage
+} UMA_INFO;
+
+// AGESA MEMORY ERRORS
+
+// AGESA_ALERT Memory Errors
+#define MEM_ALERT_USER_TMG_MODE_OVERRULED 0x04010000 ///< TIMING_MODE_SPECIFIC is requested but
+ ///< cannot be applied to current configurations.
+#define MEM_ALERT_ORG_MISMATCH_DIMM 0x04010100 ///< DIMM organization miss-match
+#define MEM_ALERT_BK_INT_DIS 0x04010200 ///< Bank interleaving disable for internal issue
+
+// AGESA_ERROR Memory Errors
+#define MEM_ERROR_NO_DQS_POS_RD_WINDOW 0x04010300 ///< No DQS Position window for RD DQS
+#define MEM_ERROR_SMALL_DQS_POS_RD_WINDOW 0x04020300 ///< Small DQS Position window for RD DQS
+#define MEM_ERROR_NO_DQS_POS_WR_WINDOW 0x04030300 ///< No DQS Position window for WR DQS
+#define MEM_ERROR_SMALL_DQS_POS_WR_WINDOW 0x04040300 ///< Small DQS Position window for WR DQS
+#define MEM_ERROR_ECC_DIS 0x04010400 ///< ECC has been disabled as a result of an internal issue
+#define MEM_ERROR_DIMM_SPARING_NOT_ENABLED 0x04010500 ///< DIMM sparing has not been enabled for an internal issues
+#define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE 0x04050300 ///< Receive Enable value is too large
+#define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW 0x04060300 ///< There is no DQS receiver enable window
+#define MEM_ERROR_DRAM_ENABLED_TIME_OUT 0x04010600 ///< Time out when polling DramEnabled bit
+#define MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT 0x04010700 ///< Time out when polling DctAccessDone bit
+#define MEM_ERROR_SEND_CTRL_WORD_TIME_OUT 0x04010800 ///< Time out when polling SendCtrlWord bit
+#define MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT 0x04010900 ///< Time out when polling PrefDramTrainMode bit
+#define MEM_ERROR_ENTER_SELF_REF_TIME_OUT 0x04010A00 ///< Time out when polling EnterSelfRef bit
+#define MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT 0x04010B00 ///< Time out when polling FreqChgInProg bit
+#define MEM_ERROR_EXIT_SELF_REF_TIME_OUT 0x04020A00 ///< Time out when polling ExitSelfRef bit
+#define MEM_ERROR_SEND_MRS_CMD_TIME_OUT 0x04010C00 ///< Time out when polling SendMrsCmd bit
+#define MEM_ERROR_SEND_ZQ_CMD_TIME_OUT 0x04010D00 ///< Time out when polling SendZQCmd bit
+#define MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT 0x04010E00 ///< Time out when polling DctExtraAccessDone bit
+#define MEM_ERROR_MEM_CLR_BUSY_TIME_OUT 0x04010F00 ///< Time out when polling MemClrBusy bit
+#define MEM_ERROR_MEM_CLEARED_TIME_OUT 0x04020F00 ///< Time out when polling MemCleared bit
+#define MEM_ERROR_FLUSH_WR_TIME_OUT 0x04011000 ///< Time out when polling FlushWr bit
+#define MEM_ERROR_MAX_LAT_NO_WINDOW 0x04070300 ///< Fail to find pass during Max Rd Latency training
+#define MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL 0x04080300 ///< Fail to launch training code on an AP
+#define MEM_ERROR_PARALLEL_TRAINING_TIME_OUT 0x04090300 ///< Fail to finish parallel training
+#define MEM_ERROR_NO_ADDRESS_MAPPING 0x04011100 ///< No address mapping found for a dimm
+#define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT 0x040A0300 ///< There is no DQS receiver enable window and the value is equal to the largest value
+#define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE 0x040B0300 ///< Receive Enable value is too large and is 1 less than limit
+#define MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR 0x04011200 ///< SPD Checksum error for NV_SPDCHK_RESTRT
+#define MEM_ERROR_NO_CHIPSELECT 0x04011300 ///< No chipselects found
+#define MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM 0x04011500 ///< Unbuffered dimm is not supported at 333MHz
+#define MEM_ERROR_WL_PRE_OUT_OF_RANGE 0x040C0300 ///< Returned PRE value during write levelizzation was out of range
+
+// AGESA_WARNING Memory Errors
+#define MEM_WARNING_UNSUPPORTED_QRDIMM 0x04011600 ///< QR DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_UDIMM 0x04021600 ///< U DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_SODIMM 0x04031600 ///< SO-DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_X4DIMM 0x04041600 ///< x4 DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_RDIMM 0x04051600 ///< R DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_LRDIMM 0x04061600 ///< LR DIMMs detected but not supported
+#define MEM_WARNING_EMP_NOT_SUPPORTED 0x04011700 ///< Processor is not capable for EMP
+#define MEM_WARNING_EMP_CONFLICT 0x04021700 ///< EMP cannot be enabled if channel interleaving,
+#define MEM_WARNING_EMP_NOT_ENABLED 0x04031700 ///< Memory size is not power of two.
+#define MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED 0x04011800 ///< Performance has been enabled, but battery life is preferred.
+ ///< bank interleaving, or bank swizzle is enabled.
+#define MEM_WARNING_NO_SPDTRC_FOUND 0x04011900 ///< No Trc timing value found in SPD of a dimm.
+#define MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED 0x04012000 ///< Node Interleaveing Requested, but could not be enabled
+#define MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED 0x04012100 ///< Channel Interleaveing Requested, but could not be enabled
+#define MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED 0x04012200 ///< Bank Interleaveing Requested, but could not be enabled
+#define MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED 0x04012300 ///< Voltage 1.35 determined, but could not be supported
+
+// AGESA_FATAL Memory Errors
+#define MEM_ERROR_MINIMUM_MODE 0x04011A00 ///< Running in minimum mode
+#define MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM 0x04011B00 ///< DIMM modules are miss-matched
+#define MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM 0x04011C00 ///< No DIMMs have been found
+#define MEM_ERROR_MISMATCH_DIMM_CLOCKS 0x04011D00 ///< DIMM clocks miss-matched
+#define MEM_ERROR_NO_CYC_TIME 0x04011E00 ///< No cycle time found
+#define MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS 0x04011F00 ///< Heap allocation error with dynamic storing of trained timings
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs 0x04021F00 ///< Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV 0x04031F00 ///< Heap allocation error with REMOTE_TRAINING_ENV
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_SPD 0x04041F00 ///< Heap allocation error for SPD data
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA 0x04051F00 ///< Heap allocation error for RECEIVED_DATA during parallel training
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS 0x04061F00 ///< Heap allocation error for S3 "SPECIAL_CASE_REGISTER"
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA 0x04071F00 ///< Heap allocation error for Training Data
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK 0x04081F00 ///< Heap allocation error for DIMM Identify "MEM_NB_BLOCK
+#define MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM 0x04022300 ///< No Constructor for DIMM Identify
+
+// AGESA_CRITICAL Memory Errors
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3 0x04091F00 ///< Heap allocation error for DMI table for DDR3
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2 0x040A1F00 ///< Heap allocation error for DMI table for DDR2
+#define MEM_ERROR_UNSUPPORTED_DIMM_CONFIG 0x04011400 ///< Dimm population is not supported
+
+
+
+/*----------------------------------------------------------------------------
+ *
+ * END OF MEMORY-SPECIFIC DATA STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+
+/*----------------------------------------------------------------------------
+ *
+ * CPU RELATED DEFINITIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+// CPU Event definitions.
+
+// Defines used to filter CPU events based on functional blocks
+#define CPU_EVENT_PM_EVENT_MASK 0xFF00FF00
+#define CPU_EVENT_PM_EVENT_CLASS 0x08000400
+
+//================================================================
+// CPU General events
+// Heap allocation (AppFunction = 01h)
+#define CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT 0x08000100
+#define CPU_ERROR_HEAP_IS_ALREADY_INITIALIZED 0x08010100
+#define CPU_ERROR_HEAP_IS_FULL 0x08020100
+#define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED 0x08030100
+#define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT 0x08040100
+// BrandId (AppFunction = 02h)
+#define CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE 0x08000200
+// Micro code patch (AppFunction = 03h)
+#define CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED 0x08000300
+// Power management (AppFunction = 04h)
+#define CPU_EVENT_PM_PSTATE_OVERCURRENT 0x08000400
+#define CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT 0x08010400
+#define CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE 0x08020400
+#define CPU_ERROR_PM_NB_PSTATE_MISMATCH 0x08030400
+// BIST (AppFunction = 05h)
+#define CPU_EVENT_BIST_ERROR 0x08000500
+
+//=================================================================
+// CPU Feature events
+// Execution cache (AppFunction = 21h)
+// AGESA_CACHE_SIZE_REDUCED 2101
+// AGESA_CACHE_REGIONS_ACROSS_1MB 2102
+// AGESA_CACHE_REGIONS_ACROSS_4GB 2103
+// AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY 2104
+// AGESA_CACHE_START_ADDRESS_LESS_D0000 2105
+// AGESA_THREE_CACHE_REGIONS_ABOVE_1MB 2106
+// AGESA_DEALLOCATE_CACHE_REGIONS 2107
+#define CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR 0x08002100
+// Core Leveling (AppFunction = 22h)
+#define CPU_WARNING_ADJUSTED_LEVELING_MODE 0x08002200
+// HT Assist (AppFunction = 23h)
+#define CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG 0x08002300
+
+// CPU Build Configuration structures and definitions
+
+/// Build Configuration structure for BLDCFG_AP_MTRR_SETTINGS
+typedef struct {
+ IN UINT32 MsrAddr; ///< Fixed-Sized MTRR address
+ IN UINT64 MsrData; ///< MTRR Settings
+} AP_MTRR_SETTINGS;
+
+#define AMD_AP_MTRR_FIX64k_00000 0x00000250
+#define AMD_AP_MTRR_FIX16k_80000 0x00000258
+#define AMD_AP_MTRR_FIX16k_A0000 0x00000259
+#define AMD_AP_MTRR_FIX4k_C0000 0x00000268
+#define AMD_AP_MTRR_FIX4k_C8000 0x00000269
+#define AMD_AP_MTRR_FIX4k_D0000 0x0000026A
+#define AMD_AP_MTRR_FIX4k_D8000 0x0000026B
+#define AMD_AP_MTRR_FIX4k_E0000 0x0000026C
+#define AMD_AP_MTRR_FIX4k_E8000 0x0000026D
+#define AMD_AP_MTRR_FIX4k_F0000 0x0000026E
+#define AMD_AP_MTRR_FIX4k_F8000 0x0000026F
+#define CPU_LIST_TERMINAL 0xFFFFFFFF
+
+/************************************************************************
+ *
+ * AGESA interface Call-Out function parameter structures
+ *
+ ***********************************************************************/
+
+/// Parameters structure for interface call-out AgesaAllocateBuffer
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN OUT UINT32 BufferLength; ///< Size of buffer to allocate
+ IN UINT32 BufferHandle; ///< Identifier or name for the buffer
+ OUT VOID *BufferPointer; ///< location of the created buffer
+} AGESA_BUFFER_PARAMS;
+
+/// Parameters structure for interface call-out AgesaRunCodeOnAp
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN UINT32 FunctionNumber; ///< Index of the procedure to execute
+ IN VOID *RelatedDataBlock; ///< Location of data structure the procedure will use
+ IN UINT32 RelatedBlockLength; ///< Size of the related data block
+} AP_EXE_PARAMS;
+
+/// Parameters structure for the interface call-out AgesaReadSpd & AgesaReadSpdRecovery
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN UINT8 SocketId; ///< Address of SPD - socket ID
+ IN UINT8 MemChannelId; ///< Address of SPD - memory channel ID
+ IN UINT8 DimmId; ///< Address of SPD - DIMM ID
+ IN OUT UINT8 *Buffer; ///< Location where to place the SPD content
+ IN OUT MEM_DATA_STRUCT *MemData; ///< Location of the MemData structure, for reference
+} AGESA_READ_SPD_PARAMS;
+
+/// Buffer Handles
+typedef enum {
+ AMD_DMI_INFO_BUFFER_HANDLE = 0x000D000, ///< Assign 0x000D000 buffer handle to DMI function
+ AMD_PSTATE_DATA_BUFFER_HANDLE, ///< Assign 0x000D001 buffer handle to Pstate data
+ AMD_PSTATE_ACPI_BUFFER_HANDLE, ///< Assign 0x000D002 buffer handle to Pstate table
+ AMD_BRAND_ID_BUFFER_HANDLE, ///< Assign 0x000D003 buffer handle to Brand ID
+ AMD_ACPI_SLIT_BUFFER_HANDLE, ///< Assign 0x000D004 buffer handle to SLIT function
+ AMD_SRAT_INFO_BUFFER_HANDLE, ///< Assign 0x000D005 buffer handle to SRAT function
+ AMD_WHEA_BUFFER_HANDLE, ///< Assign 0x000D006 buffer handle to WHEA function
+ AMD_S3_INFO_BUFFER_HANDLE, ///< Assign 0x000D007 buffer handle to S3 function
+ AMD_S3_NB_INFO_BUFFER_HANDLE, ///< Assign 0x000D008 buffer handle to S3 NB device info
+ AMD_ACPI_ALIB_BUFFER_HANDLE ///< Assign 0x000D009 buffer handle to ALIB SSDT table
+} AMD_BUFFER_HANDLE;
+/************************************************************************
+ *
+ * AGESA interface Call-Out function prototypes
+ *
+ ***********************************************************************/
+
+VOID
+AgesaDoReset (
+ IN UINTN ResetType,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+AgesaAllocateBuffer (
+ IN UINTN FcnData,
+ IN OUT AGESA_BUFFER_PARAMS *AllocParams
+ );
+
+AGESA_STATUS
+AgesaDeallocateBuffer (
+ IN UINTN FcnData,
+ IN OUT AGESA_BUFFER_PARAMS *DeallocParams
+ );
+
+AGESA_STATUS
+AgesaLocateBuffer (
+ IN UINTN FcnData,
+ IN OUT AGESA_BUFFER_PARAMS *LocateParams
+ );
+
+AGESA_STATUS
+AgesaReadSpd (
+ IN UINTN FcnData,
+ IN OUT AGESA_READ_SPD_PARAMS *ReadSpd
+ );
+
+AGESA_STATUS
+AgesaReadSpdRecovery (
+ IN UINTN FcnData,
+ IN OUT AGESA_READ_SPD_PARAMS *ReadSpd
+ );
+
+AGESA_STATUS
+AgesaHookBeforeDramInitRecovery (
+ IN UINTN FcnData,
+ IN OUT MEM_DATA_STRUCT *MemData
+ );
+
+AGESA_STATUS
+AgesaRunFcnOnAp (
+ IN UINTN ApicIdOfCore,
+ IN AP_EXE_PARAMS *LaunchApParams
+ );
+
+AGESA_STATUS
+AgesaHookBeforeDramInit (
+ IN UINTN FcnData,
+ IN OUT MEM_DATA_STRUCT *MemData
+ );
+
+AGESA_STATUS
+AgesaHookBeforeDQSTraining (
+ IN UINTN FcnData,
+ IN OUT MEM_DATA_STRUCT *MemData
+ );
+
+AGESA_STATUS
+AgesaHookBeforeExitSelfRefresh (
+ IN UINTN FcnData,
+ IN OUT MEM_DATA_STRUCT *MemData
+ );
+
+AGESA_STATUS
+AgesaPcieSlotResetControl (
+ IN UINTN FcnData,
+ IN PCIe_SLOT_RESET_INFO *ResetInfo
+ );
+
+/************************************************************************
+ *
+ * AGESA interface structure definition and function prototypes
+ *
+ ***********************************************************************/
+
+/**********************************************************************
+ * Platform Configuration: The parameters in boot branch function
+ **********************************************************************/
+
+/// The possible platform control flow settings.
+typedef enum {
+ Nfcm, ///< Normal Flow Control Mode.
+ UmaDr, ///< UMA using Display Refresh flow control.
+ UmaIfcm, ///< UMA using Isochronous Flow Control.
+ Ifcm, ///< Isochronous Flow Control Mode (other than for UMA).
+ Iommu, ///< An IOMMU is in use in the system.
+ MaxControlFlow ///< Not a control flow mode, use for limit checking.
+} PLATFORM_CONTROL_FLOW;
+
+/// Platform Deemphasis Levels.
+///
+/// The deemphasis level is set for the receiver, based on link characterization. The DCV level is
+/// set based on the level of the far transmitter.
+typedef enum {
+ DeemphasisLevelNone, ///< No Deemphasis.
+ DeemphasisLevelMinus3, ///< Minus 3 db deemphasis.
+ DeemphasisLevelMinus6, ///< Minus 6 db deemphasis.
+ DeemphasisLevelMinus8, ///< Minus 8 db deemphasis.
+ DeemphasisLevelMinus11, ///< Minus 11 db deemphasis.
+ DeemphasisLevelMinus11pre8, ///< Minus 11, Minus 8 precursor db deemphasis.
+ DcvLevelNone = 16, ///< No DCV Deemphasis.
+ DcvLevelMinus2, ///< Minus 2 db DCV deemphasis.
+ DcvLevelMinus3, ///< Minus 3 db DCV deemphasis.
+ DcvLevelMinus5, ///< Minus 5 db DCV deemphasis.
+ DcvLevelMinus6, ///< Minus 6 db DCV deemphasis.
+ DcvLevelMinus7, ///< Minus 7 db DCV deemphasis.
+ DcvLevelMinus8, ///< Minus 8 db DCV deemphasis.
+ DcvLevelMinus9, ///< Minus 9 db DCV deemphasis.
+ DcvLevelMinus11, ///< Minus 11 db DCV deemphasis.
+ MaxPlatformDeemphasisLevel ///< Not a deemphasis level, use for limit checking.
+} PLATFORM_DEEMPHASIS_LEVEL;
+
+/// Provide Deemphasis Levels for HT Links.
+///
+/// For each CPU to CPU or CPU to IO device HT link, the list of Deemphasis Levels will
+/// be checked for a match. The item matches for a Socket, Link if the link frequency is
+/// is in the inclusive range HighFreq:LoFreq.
+/// AGESA does not set deemphasis in IO devices, only in processors.
+
+typedef struct {
+ // Match fields
+ IN UINT8 Socket; ///< One Socket on which this Link is located
+ IN UINT8 Link; ///< The Link on this Processor.
+ IN UINT8 LoFreq; ///< If the link is set to this frequency or greater, apply these levels, and
+ IN UINT8 HighFreq; ///< If the link is set to this frequency or less, apply these levels.
+ // Value fields
+ IN PLATFORM_DEEMPHASIS_LEVEL ReceiverDeemphasis; ///< The deemphasis level for this link
+ IN PLATFORM_DEEMPHASIS_LEVEL DcvDeemphasis; ///< The DCV, or far transmitter deemphasis level.
+} CPU_HT_DEEMPHASIS_LEVEL;
+
+/// The possible platform power policy settings.
+typedef enum {
+ Performance, ///< Optimize for performance.
+ BatteryLife, ///< Optimize for battery life.
+ MaxPowerPolicy ///< Not a power policy mode, use for limit checking.
+} PLATFORM_POWER_POLICY;
+
+/// Platform performance settings for optimized settings.
+/// Several configuration settings for the processor depend upon other parts and
+/// general designer choices for the system. The determination of these data points
+/// is not standard for all platforms, so the host environment needs to provide these
+/// to specify how the system is to be configured.
+typedef struct {
+ IN PLATFORM_CONTROL_FLOW PlatformControlFlowMode; ///< The platform's control flow mode for optimum platform performance.
+ ///< @BldCfgItem{BLDCFG_PLATFORM_CONTROL_FLOW_MODE}
+ IN BOOLEAN UseHtAssist; ///< HyperTransport link traffic optimization.
+ ///< @BldCfgItem{BLDCFG_USE_HT_ASSIST}
+ IN BOOLEAN UseAtmMode; ///< HyperTransport link traffic optimization.
+ ///< @BldCfgItem{BLDCFG_USE_ATM_MODE}
+ IN BOOLEAN Use32ByteRefresh; ///< Display Refresh traffic generates 32 byte requests.
+ ///< @BldCfgItem{BLDCFG_USE_32_BYTE_REFRESH}
+ IN BOOLEAN UseVariableMctIsocPriority; ///< The Memory controller will be set to Variable Isoc Priority.
+ ///< @BldCfgItem{BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY}
+ IN PLATFORM_POWER_POLICY PlatformPowerPolicy; ///< The platform's desired power policy
+ ///< @BldCfgItem{BLDCFG_PLATFORM_POWER_POLICY_MODE}
+} PERFORMANCE_PROFILE;
+
+/// Platform settings that describe the voltage regulator modules of the system.
+/// Many power management settings are dependent upon the characteristics of the
+/// on-board voltage regulator module (VRM). The host environment needs to provide
+/// these to specify how the system is to be configured.
+typedef struct {
+ IN UINT32 CurrentLimit; ///< Vrm Current Limit.
+ ///< @BldCfgItem{BLDCFG_VRM_CURRENT_LIMIT}
+ ///< @BldCfgItem{BLDCFG_VRM_NB_CURRENT_LIMIT}
+ IN UINT32 LowPowerThreshold; ///< Vrm Low Power Threshold.
+ ///< @BldCfgItem{BLDCFG_VRM_LOW_POWER_THRESHOLD}
+ ///< @BldCfgItem{BLDCFG_VRM_NB_LOW_POWER_THRESHOLD}
+ IN UINT32 SlewRate; ///< Vrm Slew Rate.
+ ///< @BldCfgItem{BLDCFG_VRM_SLEW_RATE}
+ ///< @BldCfgItem{BLDCFG_VRM_NB_SLEW_RATE}
+ IN UINT32 AdditionalDelay; ///< Vrm Additional Delay.
+ ///< @BldCfgItem{BLDCFG_VRM_ADDITIONAL_DELAY}
+ ///< @BldCfgItem{BLDCFG_VRM_NB_ADDITIONAL_DELAY}
+ IN BOOLEAN HiSpeedEnable; ///< Select high speed VRM.
+ ///< @BldCfgItem{BLDCFG_VRM_HIGH_SPEED_ENABLE}
+ ///< @BldCfgItem{BLDCFG_VRM_NB_HIGH_SPEED_ENABLE}
+ IN UINT32 InrushCurrentLimit; ///< Vrm Inrush Current Limit.
+ ///< @BldCfgItem{BLDCFG_VRM_INRUSH_CURRENT_LIMIT}
+ ///< @BldCfgItem{BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT}
+} PLATFORM_VRM_CONFIGURATION;
+
+/// The VRM types to characterize.
+typedef enum {
+ CoreVrm, ///< VDD plane.
+ NbVrm, ///< VDDNB plane.
+ MaxVrmType ///< Not a valid VRM type, use for limit checking.
+} PLATFORM_VRM_TYPE;
+
+
+/// Build Option/Configuration Boolean Structure.
+typedef struct {
+ IN AMD_CODE_HEADER VersionString; ///< AMD embedded code version string
+
+ //Build Option Area
+ IN BOOLEAN OptionUDimms; ///< @ref BLDOPT_REMOVE_UDIMMS_SUPPORT "BLDOPT_REMOVE_UDIMMS_SUPPORT"
+ IN BOOLEAN OptionRDimms; ///< @ref BLDOPT_REMOVE_RDIMMS_SUPPORT "BLDOPT_REMOVE_RDIMMS_SUPPORT"
+ IN BOOLEAN OptionLrDimms; ///< @ref BLDOPT_REMOVE_LRDIMMS_SUPPORT "BLDOPT_REMOVE_LRDIMMS_SUPPORT"
+ IN BOOLEAN OptionEcc; ///< @ref BLDOPT_REMOVE_ECC_SUPPORT "BLDOPT_REMOVE_ECC_SUPPORT"
+ IN BOOLEAN OptionBankInterleave; ///< @ref BLDOPT_REMOVE_BANK_INTERLEAVE "BLDOPT_REMOVE_BANK_INTERLEAVE"
+ IN BOOLEAN OptionDctInterleave; ///< @ref BLDOPT_REMOVE_DCT_INTERLEAVE "BLDOPT_REMOVE_DCT_INTERLEAVE"
+ IN BOOLEAN OptionNodeInterleave; ///< @ref BLDOPT_REMOVE_NODE_INTERLEAVE "BLDOPT_REMOVE_NODE_INTERLEAVE"
+ IN BOOLEAN OptionParallelTraining; ///< @ref BLDOPT_REMOVE_PARALLEL_TRAINING "BLDOPT_REMOVE_PARALLEL_TRAINING"
+ IN BOOLEAN OptionOnlineSpare; ///< @ref BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT "BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT"
+ IN BOOLEAN OptionMemRestore; ///< @ref BLDOPT_REMOVE_MEM_RESTORE_SUPPORT "BLDOPT_REMOVE_MEM_RESTORE_SUPPORT"
+ IN BOOLEAN OptionMultisocket; ///< @ref BLDOPT_REMOVE_MULTISOCKET_SUPPORT "BLDOPT_REMOVE_MULTISOCKET_SUPPORT"
+ IN BOOLEAN OptionAcpiPstates; ///< @ref BLDOPT_REMOVE_ACPI_PSTATES "BLDOPT_REMOVE_ACPI_PSTATES"
+ IN BOOLEAN OptionSrat; ///< @ref BLDOPT_REMOVE_SRAT "BLDOPT_REMOVE_SRAT"
+ IN BOOLEAN OptionSlit; ///< @ref BLDOPT_REMOVE_SLIT "BLDOPT_REMOVE_SLIT"
+ IN BOOLEAN OptionWhea; ///< @ref BLDOPT_REMOVE_WHEA "BLDOPT_REMOVE_WHEA"
+ IN BOOLEAN OptionDmi; ///< @ref BLDOPT_REMOVE_DMI "BLDOPT_REMOVE_DMI"
+ IN BOOLEAN OptionEarlySamples; ///< @ref BLDOPT_REMOVE_EARLY_SAMPLES "BLDOPT_REMOVE_EARLY_SAMPLES"
+ IN BOOLEAN OptionAddrToCsTranslator; ///< ADDR_TO_CS_TRANSLATOR
+
+ //Build Configuration Area
+ IN UINT64 CfgPciMmioAddress; ///< Pci Mmio Base Address to use for PCI Config accesses.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCI_MMIO_BASE}
+ IN UINT32 CfgPciMmioSize; ///< Pci Mmio region Size.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCI_MMIO_SIZE}
+ IN PLATFORM_VRM_CONFIGURATION CfgPlatVrmCfg[MaxVrmType]; ///< Several configuration settings for the voltage regulator modules.
+ IN UINT32 CfgPlatNumIoApics; ///< The number of IO APICS for the platform.
+ IN UINT32 CfgMemInitPstate; ///< Memory Init Pstate.
+ IN PLATFORM_C1E_MODES CfgPlatformC1eMode; ///< Select the C1e Mode that will used.
+ IN UINT32 CfgPlatformC1eOpData; ///< An IO port or additional C1e setup data, depends on C1e mode.
+ IN UINT32 CfgPlatformC1eOpData1; ///< An IO port or additional C1e setup data, depends on C1e mode.
+ IN UINT32 CfgPlatformC1eOpData2; ///< An IO port or additional C1e setup data, depends on C1e mode.
+ IN PLATFORM_CSTATE_MODES CfgPlatformCStateMode; ///< Select the C-State Mode that will used.
+ IN UINT32 CfgPlatformCStateOpData; ///< An IO port or additional C-State setup data, depends on C-State mode.
+ IN UINT16 CfgPlatformCStateIoBaseAddress; ///< Specifies I/O ports that can be used to allow CPU to enter CStates
+ IN PLATFORM_CPB_MODES CfgPlatformCpbMode; ///< Enable or disable core performance boost
+ IN UINT32 CfgCoreLevelingMode; ///< Apply any downcoring or core count leveling as specified.
+ IN PERFORMANCE_PROFILE CfgPerformanceProfile; ///< The platform's control flow mode and platform performance settings.
+ IN CPU_HT_DEEMPHASIS_LEVEL *CfgPlatformDeemphasisList; ///< Deemphasis levels for the platform's HT links.
+
+ IN UINT32 CfgAmdPlatformType; ///< Designate the platform as a Server, Desktop, or Mobile.
+ IN UINT32 CfgAmdPstateCapValue; ///< Amd pstate ceiling enabling deck
+
+ IN MEMORY_BUS_SPEED CfgMemoryBusFrequencyLimit; ///< Memory Bus Frequency Limit.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT}
+ IN BOOLEAN CfgMemoryModeUnganged; ///< Memory Mode Unganged.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_MODE_UNGANGED}
+ IN BOOLEAN CfgMemoryQuadRankCapable; ///< Memory Quad Rank Capable.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_QUAD_RANK_CAPABLE}
+ IN QUANDRANK_TYPE CfgMemoryQuadrankType; ///< Memory Quadrank Type.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_QUADRANK_TYPE}
+ IN BOOLEAN CfgMemoryRDimmCapable; ///< Memory RDIMM Capable.
+ IN BOOLEAN CfgMemoryLRDimmCapable; ///< Memory LRDIMM Capable.
+ IN BOOLEAN CfgMemoryUDimmCapable; ///< Memory UDIMM Capable.
+ IN BOOLEAN CfgMemorySODimmCapable; ///< Memory SODimm Capable.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_SODIMM_CAPABLE}
+ IN BOOLEAN CfgMemoryEnableBankInterleaving; ///< Memory Enable Bank Interleaving.
+ IN BOOLEAN CfgMemoryEnableNodeInterleaving; ///< Memory Enable Node Interleaving.
+ IN BOOLEAN CfgMemoryChannelInterleaving; ///< Memory Channel Interleaving.
+ IN BOOLEAN CfgMemoryPowerDown; ///< Memory Power Down.
+ IN POWER_DOWN_MODE CfgPowerDownMode; ///< Power Down Mode.
+ IN BOOLEAN CfgOnlineSpare; ///< Online Spare.
+ IN BOOLEAN CfgMemoryParityEnable; ///< Memory Parity Enable.
+ IN BOOLEAN CfgBankSwizzle; ///< Bank Swizzle.
+ IN USER_MEMORY_TIMING_MODE CfgTimingModeSelect; ///< Timing Mode Select.
+ IN MEMORY_BUS_SPEED CfgMemoryClockSelect; ///< Memory Clock Select.
+ IN BOOLEAN CfgDqsTrainingControl; ///< Dqs Training Control.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_DQS_TRAINING_CONTROL}
+ IN BOOLEAN CfgIgnoreSpdChecksum; ///< Ignore Spd Checksum.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGNORE_SPD_CHECKSUM}
+ IN BOOLEAN CfgUseBurstMode; ///< Use Burst Mode.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_USE_BURST_MODE}
+ IN BOOLEAN CfgMemoryAllClocksOn; ///< Memory All Clocks On.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_ALL_CLOCKS_ON}
+ IN BOOLEAN CfgEnableEccFeature; ///< Enable ECC Feature.
+ IN BOOLEAN CfgEccRedirection; ///< ECC Redirection.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_REDIRECTION}
+ IN UINT16 CfgScrubDramRate; ///< Scrub Dram Rate.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DRAM_RATE}
+ IN UINT16 CfgScrubL2Rate; ///< Scrub L2Rate.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L2_RATE}
+ IN UINT16 CfgScrubL3Rate; ///< Scrub L3Rate.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L3_RATE}
+ IN UINT16 CfgScrubIcRate; ///< Scrub Ic Rate.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_IC_RATE}
+ IN UINT16 CfgScrubDcRate; ///< Scrub Dc Rate.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DC_RATE}
+ IN BOOLEAN CfgEccSyncFlood; ///< ECC Sync Flood.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYNC_FLOOD}
+ IN UINT16 CfgEccSymbolSize; ///< ECC Symbol Size.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYMBOL_SIZE}
+ IN UINT64 CfgHeapDramAddress; ///< Heap contents will be temporarily stored in this address during the transition.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_HEAP_DRAM_ADDRESS}
+ IN BOOLEAN CfgNodeMem1GBAlign; ///< Node Mem 1GB boundary Alignment
+ IN BOOLEAN CfgS3LateRestore; ///< S3 Late Restore
+ IN BOOLEAN CfgAcpiPstateIndependent; ///< PSD method dependent/Independent
+ IN AP_MTRR_SETTINGS *CfgApMtrrSettingsList; ///< The AP's MTRR settings before final halt
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_AP_MTRR_SETTINGS_LIST}
+ IN UMA_MODE CfgUmaMode; ///< Uma Mode
+ IN UINT32 CfgUmaSize; ///< Uma Size [31:0]=Addr[47:16]
+ IN BOOLEAN CfgUmaAbove4G; ///< Uma Above 4G Support
+ IN UMA_ALIGNMENT CfgUmaAlignment; ///< Uma alignment
+ IN BOOLEAN CfgProcessorScopeInSb; ///< ACPI Processor Object in \\_SB scope
+ IN CHAR8 CfgProcessorScopeName0; ///< OEM specific 1st character of processor scope name.
+ IN CHAR8 CfgProcessorScopeName1; ///< OEM specific 2nd character of processor scope name.
+ IN UINT8 CfgGnbHdAudio; ///< GNB HD Audio
+ IN UINT8 CfgAbmSupport; ///< Abm Support
+ IN UINT8 CfgDynamicRefreshRate; ///< DRR Dynamic Refresh Rate
+ IN UINT16 CfgLcdBackLightControl; ///< LCD Backlight Control
+ IN UINT8 CfgGnb3dStereoPinIndex; ///< 3D Stereo Pin ID.
+ IN UINT32 CfgTempPcieMmioBaseAddress; ///< Temp pcie MMIO base Address
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_TEMP_PCIE_MMIO_BASE_ADDRESS}
+ IN UINT32 CfgGnbIGPUSSID; ///< Gnb internal GPU SSID
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGPU_SUBSYSTEM_ID}
+ IN UINT32 CfgGnbHDAudioSSID; ///< Gnb HD Audio SSID
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID}
+ IN UINT32 CfgGnbPcieSSID; ///< Gnb PCIe SSID
+ ///< Build-time customizable only - @BldCfgItem{BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID}
+ IN UINT16 CfgLvdsSpreadSpectrum; ///< Lvds Spread Spectrum
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM}
+ IN UINT16 CfgLvdsSpreadSpectrumRate; ///< Lvds Spread Spectrum Rate
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE}
+ IN BOOLEAN Reserved; ///< reserved...
+} BUILD_OPT_CFG;
+
+/// A structure containing platform specific operational characteristics. This
+/// structure is initially populated by the initializer with a copy of the same
+/// structure that was created at build time using the build configuration controls.
+typedef struct _PLATFORM_CONFIGURATION {
+ IN PERFORMANCE_PROFILE PlatformProfile; ///< Several configuration settings for the processor.
+ IN CPU_HT_DEEMPHASIS_LEVEL *PlatformDeemphasisList; ///< Deemphasis levels for the platform's HT links.
+ ///< @BldCfgItem{BLDCFG_PLATFORM_DEEMPHASIS_LIST}.
+ ///< @n @e Examples: See @ref DeemphasisExamples "Deemphasis List Examples".
+ IN UINT8 CoreLevelingMode; ///< Indicates how to balance the number of cores per processor.
+ ///< @BldCfgItem{BLDCFG_CORE_LEVELING_MODE}
+ IN PLATFORM_C1E_MODES C1eMode; ///< Specifies the method of C1e enablement - Disabled, HW, or message based.
+ ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_MODE}
+ IN UINT32 C1ePlatformData; ///< If C1eMode is HW, specifies the P_LVL3 I/O port of the platform.
+ ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA}
+ IN UINT32 C1ePlatformData1; ///< If C1eMode is SW, specifies the address of chipset's SMI command port.
+ ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA1}
+ IN UINT32 C1ePlatformData2; ///< If C1eMode is SW, specifies the unique number used by the SMI handler to identify SMI source.
+ ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA2}
+ IN PLATFORM_CSTATE_MODES CStateMode; ///< Specifies the method of C-State enablement - Disabled, or C6.
+ ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_MODE}
+ IN UINT32 CStatePlatformData; ///< This element specifies some pertinent data needed for the operation of the Cstate feature
+ ///< If CStateMode is CStateModeC6, this item is reserved
+ ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_OPDATA}
+ IN UINT16 CStateIoBaseAddress; ///< This item specifies a free block of 8 consecutive bytes of I/O ports that
+ ///< can be used to allow the CPU to enter Cstates.
+ ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS}
+ IN PLATFORM_CPB_MODES CpbMode; ///< Specifies the method of core performance boost enablement - Disabled, or Auto.
+ ///< @BldCfgItem{BLDCFG_PLATFORM_CPB_MODE}
+ IN BOOLEAN UserOptionDmi; ///< When set to TRUE, the DMI data table is generated.
+ IN BOOLEAN UserOptionPState; ///< When set to TRUE, the PState data tables are generated.
+ IN BOOLEAN UserOptionSrat; ///< When set to TRUE, the SRAT data table is generated.
+ IN BOOLEAN UserOptionSlit; ///< When set to TRUE, the SLIT data table is generated.
+ IN BOOLEAN UserOptionWhea; ///< When set to TRUE, the WHEA data table is generated.
+ IN UINT32 PowerCeiling; ///< P-State Ceiling Enabling Deck - Max power milli-watts.
+ IN BOOLEAN ForcePstateIndependent; ///< P-State _PSD independence or dependence.
+ ///< @BldCfgItem{BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT}
+ IN UINT32 NumberOfIoApics; ///< Number of I/O APICs in the system
+ ///< @BldCfgItem{BLDCFG_PLATFORM_NUM_IO_APICS}
+ IN PLATFORM_VRM_CONFIGURATION VrmProperties[MaxVrmType]; ///< Several configuration settings for the voltage regulator modules.
+ IN BOOLEAN ProcessorScopeInSb; ///< ACPI Processor Object in \\_SB scope
+ ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_IN_SB}
+ IN CHAR8 ProcessorScopeName0; ///< OEM specific 1st character of processor scope name.
+ ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_NAME0}
+ IN CHAR8 ProcessorScopeName1; ///< OEM specific 2nd character of processor scope name.
+ ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_NAME1}
+ IN UINT8 GnbHdAudio; ///< Control GFX HD Audio controller(Used for HDMI and DP display output),
+ ///< essentially it enables function 1 of graphics device.
+ ///< @li 0 = HD Audio disable
+ ///< @li 1 = HD Audio enable
+ ///< @BldCfgItem{BLDCFG_CFG_GNB_HD_AUDIO}
+ IN UINT8 AbmSupport; ///< Automatic adjust LVDS/eDP Back light level support.It is
+ ///< characteristic specific to display panel which used by platform design.
+ ///< @li 0 = ABM support disabled
+ ///< @li 1 = ABM support enabled
+ ///< @BldCfgItem{BLDCFG_CFG_ABM_SUPPORT}
+ IN UINT8 DynamicRefreshRate; ///< Adjust refresh rate on LVDS/eDP.
+ ///< @BldCfgItem{BLDCFG_CFG_DYNAMIC_REFRESH_RATE}
+ IN UINT16 LcdBackLightControl; ///< The PWM frequency to LCD backlight control.
+ ///< If equal to 0 backlight not controlled by iGPU
+ ///< @BldCfgItem{BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL}
+} PLATFORM_CONFIGURATION;
+
+
+/**********************************************************************
+ * Structures for: AmdInitLate
+ **********************************************************************/
+#define PROC_VERSION_LENGTH 48
+#define MAX_DIMMS_PER_SOCKET 16
+
+/* Interface Parameter Structures */
+/// DMI Type4 - Processor ID
+typedef struct {
+ OUT UINT32 ProcIdLsd; ///< Lower half of 64b ID
+ OUT UINT32 ProcIdMsd; ///< Upper half of 64b ID
+} TYPE4_PROC_ID;
+
+/// DMI Type 4 - Processor information
+typedef struct {
+ OUT UINT8 T4ProcType; ///< CPU Type
+ OUT UINT8 T4ProcFamily; ///< Family 1
+ OUT TYPE4_PROC_ID T4ProcId; ///< Id
+ OUT UINT8 T4Voltage; ///< Voltage
+ OUT UINT16 T4ExternalClock; ///< External clock
+ OUT UINT16 T4MaxSpeed; ///< Max speed
+ OUT UINT16 T4CurrentSpeed; ///< Current speed
+ OUT UINT8 T4Status; ///< Status
+ OUT UINT8 T4ProcUpgrade; ///< Up grade
+ OUT UINT8 T4CoreCount; ///< Core count
+ OUT UINT8 T4CoreEnabled; ///< Core Enable
+ OUT UINT8 T4ThreadCount; ///< Thread count
+ OUT UINT16 T4ProcCharacteristics; ///< Characteristics
+ OUT UINT16 T4ProcFamily2; ///< Family 2
+ OUT CHAR8 T4ProcVersion[PROC_VERSION_LENGTH]; ///< Cpu version
+} TYPE4_DMI_INFO;
+
+/// DMI Type 7 - Cache information
+typedef struct _TYPE7_DMI_INFO {
+ OUT UINT16 T7CacheCfg; ///< Cache cfg
+ OUT UINT16 T7MaxCacheSize; ///< Max size
+ OUT UINT16 T7InstallSize; ///< Install size
+ OUT UINT16 T7SupportedSramType; ///< Supported Sram Type
+ OUT UINT16 T7CurrentSramType; ///< Current type
+ OUT UINT8 T7CacheSpeed; ///< Speed
+ OUT UINT8 T7ErrorCorrectionType; ///< ECC type
+ OUT UINT8 T7SystemCacheType; ///< Cache type
+ OUT UINT8 T7Associativity; ///< Associativity
+} TYPE7_DMI_INFO;
+
+/// DMI Type 16 offset 04h - Location
+typedef enum {
+ OtherLocation = 0x01, ///< Assign 01 to Other
+ UnknownLocation, ///< Assign 02 to Unknown
+ SystemboardOrMotherboard, ///< Assign 03 to systemboard or motherboard
+ IsaAddonCard, ///< Assign 04 to ISA add-on card
+ EisaAddonCard, ///< Assign 05 to EISA add-on card
+ PciAddonCard, ///< Assign 06 to PCI add-on card
+ McaAddonCard, ///< Assign 07 to MCA add-on card
+ PcmciaAddonCard, ///< Assign 08 to PCMCIA add-on card
+ ProprietaryAddonCard, ///< Assign 09 to proprietary add-on card
+ NuBus, ///< Assign 0A to NuBus
+ Pc98C20AddonCard, ///< Assign 0A0 to PC-98/C20 add-on card
+ Pc98C24AddonCard, ///< Assign 0A1 to PC-98/C24 add-on card
+ Pc98EAddoncard, ///< Assign 0A2 to PC-98/E add-on card
+ Pc98LocalBusAddonCard ///< Assign 0A3 to PC-98/Local bus add-on card
+} DMI_T16_LOCATION;
+
+/// DMI Type 16 offset 05h - Memory Error Correction
+typedef enum {
+ OtherUse = 0x01, ///< Assign 01 to Other
+ UnknownUse, ///< Assign 02 to Unknown
+ SystemMemory, ///< Assign 03 to system memory
+ VideoMemory, ///< Assign 04 to video memory
+ FlashMemory, ///< Assign 05 to flash memory
+ NonvolatileRam, ///< Assign 06 to non-volatile RAM
+ CacheMemory ///< Assign 07 to cache memory
+} DMI_T16_USE;
+
+/// DMI Type 16 offset 07h - Maximum Capacity
+typedef enum {
+ Dmi16OtherErrCorrection = 0x01, ///< Assign 01 to Other
+ Dmi16UnknownErrCorrection, ///< Assign 02 to Unknown
+ Dmi16NoneErrCorrection, ///< Assign 03 to None
+ Dmi16Parity, ///< Assign 04 to parity
+ Dmi16SingleBitEcc, ///< Assign 05 to Single-bit ECC
+ Dmi16MultiBitEcc, ///< Assign 06 to Multi-bit ECC
+ Dmi16Crc ///< Assign 07 to CRC
+} DMI_T16_ERROR_CORRECTION;
+
+/// DMI Type 16 - Physical Memory Array
+typedef struct {
+ OUT DMI_T16_LOCATION Location; ///< The physical location of the Memory Array,
+ ///< whether on the system board or an add-in board.
+ OUT DMI_T16_USE Use; ///< Identifies the function for which the array
+ ///< is used.
+ OUT DMI_T16_ERROR_CORRECTION MemoryErrorCorrection; ///< The primary hardware error correction or
+ ///< detection method supported by this memory array.
+ OUT UINT32 MaximumCapacity; ///< The maximum memory capacity, in kilobytes,
+ ///< for the array.
+ OUT UINT16 NumberOfMemoryDevices; ///< The number of slots or sockets available
+ ///< for memory devices in this array.
+} TYPE16_DMI_INFO;
+
+/// DMI Type 17 offset 0Eh - Form Factor
+typedef enum {
+ OtherFormFactor = 0x01, ///< Assign 01 to Other
+ UnknowFormFactor, ///< Assign 02 to Unknown
+ SimmFormFactor, ///< Assign 03 to SIMM
+ SipFormFactor, ///< Assign 04 to SIP
+ ChipFormFactor, ///< Assign 05 to Chip
+ DipFormFactor, ///< Assign 06 to DIP
+ ZipFormFactor, ///< Assign 07 to ZIP
+ ProprietaryCardFormFactor, ///< Assign 08 to Proprietary Card
+ DimmFormFactorFormFactor, ///< Assign 09 to DIMM
+ TsopFormFactor, ///< Assign 10 to TSOP
+ RowOfChipsFormFactor, ///< Assign 11 to Row of chips
+ RimmFormFactor, ///< Assign 12 to RIMM
+ SodimmFormFactor, ///< Assign 13 to SODIMM
+ SrimmFormFactor, ///< Assign 14 to SRIMM
+ FbDimmFormFactor ///< Assign 15 to FB-DIMM
+} DMI_T17_FORM_FACTOR;
+
+/// DMI Type 17 offset 12h - Memory Type
+typedef enum {
+ OtherMemType = 0x01, ///< Assign 01 to Other
+ UnknownMemType, ///< Assign 02 to Unknown
+ DramMemType, ///< Assign 03 to DRAM
+ EdramMemType, ///< Assign 04 to EDRAM
+ VramMemType, ///< Assign 05 to VRAM
+ SramMemType, ///< Assign 06 to SRAM
+ RamMemType, ///< Assign 07 to RAM
+ RomMemType, ///< Assign 08 to ROM
+ FlashMemType, ///< Assign 09 to Flash
+ EepromMemType, ///< Assign 10 to EEPROM
+ FepromMemType, ///< Assign 11 to FEPROM
+ EpromMemType, ///< Assign 12 to EPROM
+ CdramMemType, ///< Assign 13 to CDRAM
+ ThreeDramMemType, ///< Assign 14 to 3DRAM
+ SdramMemType, ///< Assign 15 to SDRAM
+ SgramMemType, ///< Assign 16 to SGRAM
+ RdramMemType, ///< Assign 17 to RDRAM
+ DdrMemType, ///< Assign 18 to DDR
+ Ddr2MemType, ///< Assign 19 to DDR2
+ Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM
+ Ddr3MemType = 0x18, ///< Assign 24 to DDR3
+ Fbd2MemType ///< Assign 25 to FBD2
+} DMI_T17_MEMORY_TYPE;
+
+/// DMI Type 17 offset 13h - Type Detail
+typedef struct {
+ OUT UINT16 Reserved1:1; ///< Reserved
+ OUT UINT16 Other:1; ///< Other
+ OUT UINT16 Unknown:1; ///< Unknown
+ OUT UINT16 FastPaged:1; ///< Fast-Paged
+ OUT UINT16 StaticColumn:1; ///< Static column
+ OUT UINT16 PseudoStatic:1; ///< Pseudo-static
+ OUT UINT16 Rambus:1; ///< RAMBUS
+ OUT UINT16 Synchronous:1; ///< Synchronous
+ OUT UINT16 Cmos:1; ///< CMOS
+ OUT UINT16 Edo:1; ///< EDO
+ OUT UINT16 WindowDram:1; ///< Window DRAM
+ OUT UINT16 CacheDram:1; ///< Cache Dram
+ OUT UINT16 NonVolatile:1; ///< Non-volatile
+ OUT UINT16 Reserved2:3; ///< Reserved
+} DMI_T17_TYPE_DETAIL;
+
+/// DMI Type 17 - Memory Device
+typedef struct {
+ OUT UINT16 TotalWidth; ///< Total Width, in bits, of this memory device, including any check or error-correction bits.
+ OUT UINT16 DataWidth; ///< Data Width, in bits, of this memory device.
+ OUT UINT16 MemorySize; ///< The size of the memory device.
+ OUT DMI_T17_FORM_FACTOR FormFactor; ///< The implementation form factor for this memory device.
+ OUT UINT8 DeviceSet; ///< Identifies when the Memory Device is one of a set of
+ ///< Memory Devices that must be populated with all devices of
+ ///< the same type and size, and the set to which this device belongs.
+ OUT CHAR8 DeviceLocator[8]; ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
+ OUT CHAR8 BankLocator[10]; ///< The string number of the string that identifies the physically labeled bank where the memory device is located.
+ OUT DMI_T17_MEMORY_TYPE MemoryType; ///< The type of memory used in this device.
+ OUT DMI_T17_TYPE_DETAIL TypeDetail; ///< Additional detail on the memory device type
+ OUT UINT16 Speed; ///< Identifies the speed of the device, in megahertz (MHz).
+ OUT UINT64 ManufacturerIdCode; ///< Manufacturer ID code.
+ OUT CHAR8 SerialNumber[9]; ///< Serial Number.
+ OUT CHAR8 PartNumber[19]; ///< Part Number.
+ OUT UINT8 Attributes; ///< Bits 7-4: Reserved, Bits 3-0: rank.
+ OUT UINT32 ExtSize; ///< Extended Size.
+ OUT UINT16 ConfigSpeed; ///< Configured memory clock speed
+} TYPE17_DMI_INFO;
+
+/// Memory DMI Type 17 and 20 - for memory use
+typedef struct {
+ OUT UINT16 TotalWidth; ///< Total Width, in bits, of this memory device, including any check or error-correction bits.
+ OUT UINT16 DataWidth; ///< Data Width, in bits, of this memory device.
+ OUT UINT16 MemorySize; ///< The size of the memory device.
+ OUT DMI_T17_FORM_FACTOR FormFactor; ///< The implementation form factor for this memory device.
+ OUT UINT8 DeviceLocator; ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
+ OUT UINT8 BankLocator; ///< The string number of the string that identifies the physically labeled bank where the memory device is located.
+ OUT UINT16 Speed; ///< Identifies the speed of the device, in megahertz (MHz).
+ OUT UINT64 ManufacturerIdCode; ///< Manufacturer ID code.
+ OUT UINT8 SerialNumber[4]; ///< Serial Number.
+ OUT UINT8 PartNumber[18]; ///< Part Number.
+ OUT UINT8 Attributes; ///< Bits 7-4: Reserved, Bits 3-0: rank.
+ OUT UINT32 ExtSize; ///< Extended Size.
+ OUT UINT8 Socket:3; ///< Socket ID
+ OUT UINT8 Channel:2; ///< Channel ID
+ OUT UINT8 Dimm:2; ///< DIMM ID
+ OUT UINT8 DimmPresent:1; ///< Dimm Present
+ OUT UINT32 StartingAddr; ///< The physical address, in kilobytes, of a range
+ ///< of memory mapped to the referenced Memory Device.
+ OUT UINT32 EndingAddr; ///< The handle, or instance number, associated with
+ ///< the Memory Device structure to which this address
+ ///< range is mapped.
+ OUT UINT16 ConfigSpeed; ///< Configured memory clock speed
+} MEM_DMI_INFO;
+
+/// DMI Type 19 - Memory Array Mapped Address
+typedef struct {
+ OUT UINT32 StartingAddr; ///< The physical address, in kilobytes,
+ ///< of a range of memory mapped to the
+ ///< specified physical memory array.
+ OUT UINT32 EndingAddr; ///< The physical ending address of the
+ ///< last kilobyte of a range of addresses
+ ///< mapped to the specified physical memory array.
+ OUT UINT16 MemoryArrayHandle; ///< The handle, or instance number, associated
+ ///< with the physical memory array to which this
+ ///< address range is mapped.
+ OUT UINT8 PartitionWidth; ///< Identifies the number of memory devices that
+ ///< form a single row of memory for the address
+ ///< partition defined by this structure.
+} TYPE19_DMI_INFO;
+
+///DMI Type 20 - Memory Device Mapped Address
+typedef struct {
+ OUT UINT32 StartingAddr; ///< The physical address, in kilobytes, of a range
+ ///< of memory mapped to the referenced Memory Device.
+ OUT UINT32 EndingAddr; ///< The handle, or instance number, associated with
+ ///< the Memory Device structure to which this address
+ ///< range is mapped.
+ OUT UINT16 MemoryDeviceHandle; ///< The handle, or instance number, associated with
+ ///< the Memory Device structure to which this address
+ ///< range is mapped.
+ OUT UINT16 MemoryArrayMappedAddressHandle; ///< The handle, or instance number, associated
+ ///< with the Memory Array Mapped Address structure to
+ ///< which this device address range is mapped.
+ OUT UINT8 PartitionRowPosition; ///< Identifies the position of the referenced Memory
+ ///< Device in a row of the address partition.
+ OUT UINT8 InterleavePosition; ///< The position of the referenced Memory Device in
+ ///< an interleave.
+ OUT UINT8 InterleavedDataDepth; ///< The maximum number of consecutive rows from the
+ ///< referenced Memory Device that are accessed in a
+ ///< single interleaved transfer.
+} TYPE20_DMI_INFO;
+
+/// Collection of pointers to the DMI records
+typedef struct {
+ OUT TYPE4_DMI_INFO T4[MAX_SOCKETS_SUPPORTED]; ///< Type 4 struc
+ OUT TYPE7_DMI_INFO T7L1[MAX_SOCKETS_SUPPORTED]; ///< Type 7 struc 1
+ OUT TYPE7_DMI_INFO T7L2[MAX_SOCKETS_SUPPORTED]; ///< Type 7 struc 2
+ OUT TYPE7_DMI_INFO T7L3[MAX_SOCKETS_SUPPORTED]; ///< Type 7 struc 3
+ OUT TYPE16_DMI_INFO T16; ///< Type 16 struc
+ OUT TYPE17_DMI_INFO T17[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 17 struc
+ OUT TYPE19_DMI_INFO T19; ///< Type 19 struc
+ OUT TYPE20_DMI_INFO T20[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 20 struc
+} DMI_INFO;
+
+/**********************************************************************
+ * Interface call: AllocateExecutionCache
+ **********************************************************************/
+#define MAX_CACHE_REGIONS 3
+
+/// AllocateExecutionCache sub param structure for cached memory region
+typedef struct {
+ IN OUT UINT32 ExeCacheStartAddr; ///< Start address
+ IN OUT UINT32 ExeCacheSize; ///< Size
+} EXECUTION_CACHE_REGION;
+
+/**********************************************************************
+ * Interface call: AmdGetAvailableExeCacheSize
+ **********************************************************************/
+/// Get available Cache remain
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ OUT UINT32 AvailableExeCacheSize; ///< Remain size
+} AMD_GET_EXE_SIZE_PARAMS;
+
+AGESA_STATUS
+AmdGetAvailableExeCacheSize (
+ IN OUT AMD_GET_EXE_SIZE_PARAMS *AmdGetExeSizeParams
+ );
+
+/// Selection type for core leveling
+typedef enum {
+ CORE_LEVEL_LOWEST, ///< Level to lowest common denominator
+ CORE_LEVEL_TWO, ///< Level to 2 cores
+ CORE_LEVEL_POWER_OF_TWO, ///< Level to 1,2,4 or 8
+ CORE_LEVEL_NONE, ///< Do no leveling
+ CORE_LEVEL_COMPUTE_UNIT, ///< Level cores to one core per compute unit
+ CORE_LEVEL_ONE, ///< Level to 1 core
+ CORE_LEVEL_THREE, ///< Level to 3 cores
+ CORE_LEVEL_FOUR, ///< Level to 4 cores
+ CORE_LEVEL_FIVE, ///< Level to 5 cores
+ CORE_LEVEL_SIX, ///< Level to 6 cores
+ CORE_LEVEL_SEVEN, ///< Level to 7 cores
+ CORE_LEVEL_EIGHT, ///< Level to 8 cores
+ CORE_LEVEL_NINE, ///< Level to 9 cores
+ CORE_LEVEL_TEN, ///< Level to 10 cores
+ CORE_LEVEL_ELEVEN, ///< Level to 11 cores
+ CORE_LEVEL_TWELVE, ///< Level to 12 cores
+ CORE_LEVEL_THIRTEEN, ///< Level to 13 cores
+ CORE_LEVEL_FOURTEEN, ///< Level to 14 cores
+ CORE_LEVEL_FIFTEEN, ///< Level to 15 cores
+ CoreLevelModeMax ///< Used for bounds checking
+} CORE_LEVELING_TYPE;
+
+
+
+
+
+/************************************************************************
+ *
+ * AGESA Basic Level interface structure definition and function prototypes
+ *
+ ***********************************************************************/
+
+/**********************************************************************
+ * Interface call: AmdCreateStruct
+ **********************************************************************/
+AGESA_STATUS
+AmdCreateStruct (
+ IN OUT AMD_INTERFACE_PARAMS *InterfaceParams
+ );
+
+/**********************************************************************
+ * Interface call: AmdReleaseStruct
+ **********************************************************************/
+AGESA_STATUS
+AmdReleaseStruct (
+ IN OUT AMD_INTERFACE_PARAMS *InterfaceParams
+ );
+
+/**********************************************************************
+ * Interface call: AmdInitReset
+ **********************************************************************/
+/// AmdInitReset param structure
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN EXECUTION_CACHE_REGION CacheRegion[3]; ///< The cached memory region
+ IN AMD_HT_RESET_INTERFACE HtConfig; ///< The interface for Ht Recovery
+} AMD_RESET_PARAMS;
+
+AGESA_STATUS
+AmdInitReset (
+ IN OUT AMD_RESET_PARAMS *ResetParams
+ );
+
+
+/**********************************************************************
+ * Interface call: AmdInitEarly
+ **********************************************************************/
+/// InitEarly param structure
+///
+/// Provide defaults or customizations to each service performed in AmdInitEarly.
+///
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN EXECUTION_CACHE_REGION CacheRegion[3]; ///< Execution Map Interface
+ IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
+ IN AMD_HT_INTERFACE HtConfig; ///< HyperTransport Interface
+ IN GNB_CONFIGURATION GnbConfig; ///< GNB configuration
+} AMD_EARLY_PARAMS;
+
+AGESA_STATUS
+AmdInitEarly (
+ IN OUT AMD_EARLY_PARAMS *EarlyParams
+ );
+
+
+/**********************************************************************
+ * Interface call: AmdInitPost
+ **********************************************************************/
+/// AmdInitPost param structure
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
+ IN MEM_PARAMETER_STRUCT MemConfig; ///< Memory post param
+} AMD_POST_PARAMS;
+
+AGESA_STATUS
+AmdInitPost (
+ IN OUT AMD_POST_PARAMS *PostParams ///< Amd Cpu init param
+ );
+
+
+/**********************************************************************
+ * Interface call: AmdInitEnv
+ **********************************************************************/
+/// AmdInitEnv param structure
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
+ IN GNB_ENV_CONFIGURATION GnbEnvConfiguration; ///< platform operational characteristics.
+} AMD_ENV_PARAMS;
+
+AGESA_STATUS
+AmdInitEnv (
+ IN OUT AMD_ENV_PARAMS *EnvParams
+ );
+
+
+/**********************************************************************
+ * Interface call: AmdInitMid
+ **********************************************************************/
+/// AmdInitMid param structure
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
+} AMD_MID_PARAMS;
+
+AGESA_STATUS
+AmdInitMid (
+ IN OUT AMD_MID_PARAMS *MidParams
+ );
+
+
+/**********************************************************************
+ * Interface call: AmdInitLate
+ **********************************************************************/
+/// AmdInitLate param structure
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
+ OUT DMI_INFO *DmiTable; ///< DMI Interface
+ OUT VOID *AcpiPState; ///< Acpi Pstate SSDT Table
+ OUT VOID *AcpiSrat; ///< SRAT Table
+ OUT VOID *AcpiSlit; ///< SLIT Table
+ OUT VOID *AcpiWheaMce; ///< WHEA MCE Table
+ OUT VOID *AcpiWheaCmc; ///< WHEA CMC Table
+ OUT VOID *AcpiAlib; ///< ACPI SSDT table with ALIB implementation
+} AMD_LATE_PARAMS;
+
+AGESA_STATUS
+AmdInitLate (
+ IN OUT AMD_LATE_PARAMS *LateParams
+ );
+
+/**********************************************************************
+ * Interface call: AmdInitRecovery
+ **********************************************************************/
+/// CPU Recovery Parameters
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
+} AMD_CPU_RECOVERY_PARAMS;
+
+/// AmdInitRecovery param structure
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN MEM_PARAMETER_STRUCT MemConfig; ///< Memory post param
+ IN EXECUTION_CACHE_REGION CacheRegion[3]; ///< The cached memory region. And the max cache region is 3
+ IN AMD_CPU_RECOVERY_PARAMS CpuRecoveryParams; ///< Params for CPU related recovery init.
+} AMD_RECOVERY_PARAMS;
+
+AGESA_STATUS
+AmdInitRecovery (
+ IN OUT AMD_RECOVERY_PARAMS *RecoveryParams
+ );
+
+/**********************************************************************
+ * Interface call: AmdInitResume
+ **********************************************************************/
+/// AmdInitResume param structure
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN PLATFORM_CONFIGURATION PlatformConfig; ///< Platform operational characteristics
+ IN AMD_S3_PARAMS S3DataBlock; ///< Save state data
+} AMD_RESUME_PARAMS;
+
+AGESA_STATUS
+AmdInitResume (
+ IN AMD_RESUME_PARAMS *ResumeParams
+ );
+
+
+/**********************************************************************
+ * Interface call: AmdS3LateRestore
+ **********************************************************************/
+/// AmdS3LateRestore param structure
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
+ IN AMD_S3_PARAMS S3DataBlock; ///< Save state data
+} AMD_S3LATE_PARAMS;
+
+AGESA_STATUS
+AmdS3LateRestore (
+ IN OUT AMD_S3LATE_PARAMS *S3LateParams
+ );
+
+
+/**********************************************************************
+ * Interface call: AmdS3Save
+ **********************************************************************/
+/// AmdS3Save param structure
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
+ OUT AMD_S3_PARAMS S3DataBlock; ///< Standard header
+} AMD_S3SAVE_PARAMS;
+
+AGESA_STATUS
+AmdS3Save (
+ IN OUT AMD_S3SAVE_PARAMS *AmdS3SaveParams
+ );
+
+
+/**********************************************************************
+ * Interface call: AmdLateRunApTask
+ **********************************************************************/
+/**
+ * Entry point for AP tasking.
+ */
+AGESA_STATUS
+AmdLateRunApTask (
+ IN AP_EXE_PARAMS *AmdApExeParams
+);
+
+//
+// General Services API
+//
+
+/**********************************************************************
+ * Interface service call: AmdGetApicId
+ **********************************************************************/
+/// Request the APIC ID of a particular core.
+
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN UINT8 Socket; ///< The Core's Socket.
+ IN UINT8 Core; ///< The Core id.
+ OUT BOOLEAN IsPresent; ///< The Core is present, and ApicAddress is valid.
+ OUT UINT8 ApicAddress; ///< The Core's APIC ID.
+} AMD_APIC_PARAMS;
+
+/**
+ * Get a specified Core's APIC ID.
+ */
+AGESA_STATUS
+AmdGetApicId (
+ IN OUT AMD_APIC_PARAMS *AmdParamApic
+);
+
+/**********************************************************************
+ * Interface service call: AmdGetPciAddress
+ **********************************************************************/
+/// Request the PCI Address of a Processor Module (that is, its Northbridge)
+
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN UINT8 Socket; ///< The Processor's socket
+ IN UINT8 Module; ///< The Module in that Processor
+ OUT BOOLEAN IsPresent; ///< The Core is present, and PciAddress is valid.
+ OUT PCI_ADDR PciAddress; ///< The Processor's PCI Config Space address (Function 0, Register 0)
+} AMD_GET_PCI_PARAMS;
+
+/**
+ * Get Processor Module's PCI Config Space address.
+ */
+AGESA_STATUS
+AmdGetPciAddress (
+ IN OUT AMD_GET_PCI_PARAMS *AmdParamGetPci
+);
+
+/**********************************************************************
+ * Interface service call: AmdIdentifyCore
+ **********************************************************************/
+/// Request the identity (Socket, Module, Core) of the current Processor Core
+
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ OUT UINT8 Socket; ///< The current Core's Socket
+ OUT UINT8 Module; ///< The current Core's Processor Module
+ OUT UINT8 Core; ///< The current Core's core id.
+} AMD_IDENTIFY_PARAMS;
+
+/**
+ * "Who am I" for the current running core.
+ */
+AGESA_STATUS
+AmdIdentifyCore (
+ IN OUT AMD_IDENTIFY_PARAMS *AmdParamIdentify
+);
+
+/**********************************************************************
+ * Interface service call: AmdReadEventLog
+ **********************************************************************/
+/// An Event Log Entry.
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ OUT UINT32 EventClass; ///< The severity of this event, matches AGESA_STATUS.
+ OUT UINT32 EventInfo; ///< The unique event identifier, zero means "no event".
+ OUT UINT32 DataParam1; ///< Data specific to the Event.
+ OUT UINT32 DataParam2; ///< Data specific to the Event.
+ OUT UINT32 DataParam3; ///< Data specific to the Event.
+ OUT UINT32 DataParam4; ///< Data specific to the Event.
+} EVENT_PARAMS;
+
+/**
+ * Read an Event from the Event Log.
+ */
+AGESA_STATUS
+AmdReadEventLog (
+ IN EVENT_PARAMS *Event
+);
+
+/**********************************************************************
+ * Interface service call: AmdIdentifyDimm
+ **********************************************************************/
+/// Request the identity of dimm from system address
+
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN UINT64 MemoryAddress; ///< System Address that needs to be translated to dimm identification.
+ OUT UINT8 SocketId; ///< The socket on which the targeted address locates.
+ OUT UINT8 MemChannelId; ///< The channel on which the targeted address locates.
+ OUT UINT8 DimmId; ///< The dimm on which the targeted address locates.
+} AMD_IDENTIFY_DIMM;
+
+/**
+ * Get the dimm identification for the address.
+ */
+AGESA_STATUS
+AmdIdentifyDimm (
+ IN OUT AMD_IDENTIFY_DIMM *AmdDimmIdentify
+);
+
+/// Data structure for the Mapping Item between Unified ID for IDS Setup Option
+/// and the option value.
+///
+typedef struct {
+ IN UINT16 IdsNvId; ///< Unified ID for IDS Setup Option.
+ OUT UINT16 IdsNvValue; ///< The value of IDS Setup Option.
+} IDS_NV_ITEM;
+
+/// Data Structure for IDS CallOut Function
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN IDS_NV_ITEM *IdsNvPtr; ///< Memory Pointer of IDS NV Table
+ IN OUT UINTN Reserved; ///< reserved
+} IDS_CALLOUT_STRUCT;
+
+AGESA_STATUS
+AmdIdsRunApTaskLate (
+ IN AP_EXE_PARAMS *AmdApExeParams
+ );
+
+
+#define AGESA_IDS_DFT_VAL 0xFFFF ///< Default value of every uninitlized NV item, the action for it will be ignored
+#define AGESA_IDS_NV_END 0xFFFF ///< Flag specify end of option structure
+/// WARNING: Don't change the comment below, it used as signature for script
+/// AGESA IDS NV ID Definitions
+typedef enum {
+ AGESA_IDS_EXT_ID_START = 0x0000,///< 0x0000 specify the start of external NV id
+
+ AGESA_IDS_NV_UCODE, ///< 0x0001 Enable or disable microcode patching
+
+ AGESA_IDS_NV_TARGET_PSTATE, ///< 0x0002 Set the P-state required to be activated
+ AGESA_IDS_NV_POSTPSTATE, ///< 0x0003 Set the P-state required to be activated through POST
+
+ AGESA_IDS_NV_BANK_INTERLEAVE, ///< 0x0004 Enable or disable Bank Interleave
+ AGESA_IDS_NV_CHANNEL_INTERLEAVE, ///< 0x0005 Enable or disable Channel Interleave
+ AGESA_IDS_NV_NODE_INTERLEAVE, ///< 0x0006 Enable or disable Node Interleave
+ AGESA_IDS_NV_MEMHOLE, ///< 0x0007 Enables or disable memory hole
+
+ AGESA_IDS_NV_SCRUB_REDIRECTION, ///< 0x0008 Enable or disable a write to dram with corrected data
+ AGESA_IDS_NV_DRAM_SCRUB, ///< 0x0009 Set the rate of background scrubbing for DRAM
+ AGESA_IDS_NV_DCACHE_SCRUB, ///< 0x000A Set the rate of background scrubbing for the DCache.
+ AGESA_IDS_NV_L2_SCRUB, ///< 0x000B Set the rate of background scrubbing for the L2 cache
+ AGESA_IDS_NV_L3_SCRUB, ///< 0x000C Set the rate of background scrubbing for the L3 cache
+ AGESA_IDS_NV_ICACHE_SCRUB, ///< 0x000D Set the rate of background scrubbing for the Icache
+ AGESA_IDS_NV_SYNC_ON_ECC_ERROR, ///< 0x000E Enable or disable the sync flood on un-correctable ECC error
+ AGESA_IDS_NV_ECC_SYMBOL_SIZE, ///< 0x000F Set ECC symbol size
+
+ AGESA_IDS_NV_ALL_MEMCLKS, ///< 0x0010 Enable or disable all memory clocks enable
+ AGESA_IDS_NV_DCT_GANGING_MODE, ///< 0x0011 Set the Ganged mode
+ AGESA_IDS_NV_DRAM_BURST_LENGTH32, ///< 0x0012 Set the DRAM Burst Length 32
+ AGESA_IDS_NV_MEMORY_POWER_DOWN, ///< 0x0013 Enable or disable Memory power down mode
+ AGESA_IDS_NV_MEMORY_POWER_DOWN_MODE, ///< 0x0014 Set the Memory power down mode
+ AGESA_IDS_NV_DLL_SHUT_DOWN, ///< 0x0015 Enable or disable DLLShutdown
+ AGESA_IDS_NV_ONLINE_SPARE, ///< 0x0016 Enable or disable the Dram controller to designate a DIMM bank as a spare for logical swap
+
+ AGESA_IDS_NV_HT_ASSIST, ///< 0x0017 Enable or Disable HT Assist
+ AGESA_IDS_NV_ATMMODE, ///< 0x0018 Enable or Disable ATM mode
+
+ AGESA_IDS_NV_HDTOUT, ///< 0x0019 Enable or disable HDTOUT feature
+
+ AGESA_IDS_NV_HTLINKSOCKET, ///< 0x001A HT Link Socket
+ AGESA_IDS_NV_HTLINKPORT, ///< 0x001B HT Link Port
+ AGESA_IDS_NV_HTLINKFREQ, ///< 0x001C HT Link Frequency
+ AGESA_IDS_NV_HTLINKWIDTHIN, ///< 0x001D HT Link In Width
+ AGESA_IDS_NV_HTLINKWIDTHOUT, ///< 0x001E HT Link Out Width
+
+ AGESA_IDS_NV_GNBHDAUDIOEN, ///< 0x001F Enable or disable GNB HD Audio
+
+ AGESA_IDS_NV_CPB_EN, ///< 0x0020 Core Performance Boost
+
+ AGESA_IDS_NV_HTC_EN, ///< 0x0021 HTC Enable
+ AGESA_IDS_NV_HTC_OVERRIDE, ///< 0x0022 HTC Override
+ AGESA_IDS_NV_HTC_PSTATE_LIMIT, ///< 0x0023 HTC P-state limit select
+ AGESA_IDS_NV_HTC_TEMP_HYS, ///< 0x0024 HTC Temperature Hysteresis
+ AGESA_IDS_NV_HTC_ACT_TEMP, ///< 0x0025 HTC Activation Temp
+
+ AGESA_IDS_NV_POWER_POLICY, ///< 0x0026 Select Platform Power Policy
+ AGESA_IDS_EXT_ID_END, ///< 0x0027 specify the end of external NV ID
+} IDS_EX_NV_ID;
+
+
+#define IDS_NUM_EXT_NV_ITEM (AGESA_IDS_EXT_ID_END - AGESA_IDS_EXT_ID_START + 1)
+
+#endif // _AGESA_H_
diff --git a/src/vendorcode/amd/agesa/f14/AMD.h b/src/vendorcode/amd/agesa/f14/AMD.h
new file mode 100644
index 0000000..f788da8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/AMD.h
@@ -0,0 +1,482 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Agesa structures and definitions
+ *
+ * Contains AMD AGESA core interface
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Include
+ * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+
+#ifndef _AMD_H_
+#define _AMD_H_
+
+#define AGESA_REVISION "Arch2008"
+#define AGESA_ID "AGESA"
+
+#define Int16FromChar(a,b) ((a) << 0 | (b) << 8)
+#define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)
+//
+//
+// AGESA Types and Definitions
+//
+//
+#define LAST_ENTRY 0xFFFFFFFF
+#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D')
+#define IOCF8 0xCF8
+#define IOCFC 0xCFC
+
+/// The return status for all AGESA public services.
+///
+/// Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
+/// will have log entries with more detail.
+///
+typedef enum {
+ AGESA_SUCCESS = 0, ///< The service completed normally. Info may be logged.
+ AGESA_UNSUPPORTED, ///< The dispatcher or create struct had an unimplemented function requested.
+ ///< Not logged.
+ AGESA_BOUNDS_CHK, ///< A dynamic parameter was out of range and the service was not provided.
+ ///< Example, memory address not installed, heap buffer handle not found.
+ ///< Not Logged.
+ // AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
+ AGESA_ALERT, ///< An observed condition, but no loss of function.
+ ///< See log. Example, HT CRC.
+ AGESA_WARNING, ///< Possible or minor loss of function. See Log.
+ AGESA_ERROR, ///< Significant loss of function, boot may be possible. See Log.
+ AGESA_CRITICAL, ///< Continue boot only to notify user. See Log.
+ AGESA_FATAL, ///< Halt booting. See Log, however Fatal errors pertaining to heap problems
+ ///< may not be able to reliably produce log events.
+ AgesaStatusMax ///< Not a status, for limit checking.
+} AGESA_STATUS;
+
+/// For checking whether a status is at or above the mandatory log level.
+#define AGESA_STATUS_LOG_LEVEL AGESA_ALERT
+
+/**
+ * Callout method to the host environment.
+ *
+ * Callout using a dispatch with appropriate thunk layer, which is determined by the host environment.
+ *
+ * @param[in] Function The specific callout function being invoked.
+ * @param[in] FcnData Function specific data item.
+ * @param[in,out] ConfigPtr Reference to Callout params.
+ */
+typedef AGESA_STATUS (*CALLOUT_ENTRY) (
+ IN UINT32 Function,
+ IN UINTN FcnData,
+ IN OUT VOID *ConfigPtr
+ );
+
+typedef AGESA_STATUS (*IMAGE_ENTRY) (VOID *ConfigPtr);
+typedef AGESA_STATUS (*MODULE_ENTRY) (VOID *ConfigPtr);
+
+///This allocation type is used by the AmdCreateStruct entry point
+typedef enum {
+ PreMemHeap = 0, ///< Create heap in cache.
+ PostMemDram, ///< Create heap in memory.
+ ByHost ///< Create heap by Host.
+} ALLOCATION_METHOD;
+
+/// These width descriptors are used by the library function, and others, to specify the data size
+typedef enum ACCESS_WIDTH {
+ AccessWidth8 = 1, ///< Access width is 8 bits.
+ AccessWidth16, ///< Access width is 16 bits.
+ AccessWidth32, ///< Access width is 32 bits.
+ AccessWidth64, ///< Access width is 64 bits.
+
+ AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data.
+ AccessS3SaveWidth16, ///< Save 16 bits data.
+ AccessS3SaveWidth32, ///< Save 32 bits data.
+ AccessS3SaveWidth64, ///< Save 64 bits data.
+} ACCESS_WIDTH;
+
+/// AGESA struct name
+typedef enum {
+ // AGESA BASIC FUNCTIONS
+ AMD_INIT_RECOVERY = 0x00020000, ///< AmdInitRecovery entry point handle
+ AMD_CREATE_STRUCT, ///< AmdCreateStruct handle
+ AMD_INIT_EARLY, ///< AmdInitEarly entry point handle
+ AMD_INIT_ENV, ///< AmdInitEnv entry point handle
+ AMD_INIT_LATE, ///< AmdInitLate entry point handle
+ AMD_INIT_MID, ///< AmdInitMid entry point handle
+ AMD_INIT_POST, ///< AmdInitPost entry point handle
+ AMD_INIT_RESET, ///< AmdInitReset entry point handle
+ AMD_INIT_RESUME, ///< AmdInitResume entry point handle
+ AMD_RELEASE_STRUCT, ///< AmdReleaseStruct handle
+ AMD_S3LATE_RESTORE, ///< AmdS3LateRestore entry point handle
+ AMD_S3_SAVE, ///< AmdS3Save entry point handle
+ AMD_GET_APIC_ID, ///< AmdGetApicId entry point handle
+ AMD_GET_PCI_ADDRESS, ///< AmdGetPciAddress entry point handle
+ AMD_IDENTIFY_CORE, ///< AmdIdentifyCore general service handle
+ AMD_READ_EVENT_LOG, ///< AmdReadEventLog general service handle
+ AMD_GET_EXECACHE_SIZE, ///< AmdGetAvailableExeCacheSize general service handle
+ AMD_LATE_RUN_AP_TASK, ///< AmdLateRunApTask entry point handle
+ AMD_IDENTIFY_DIMMS ///< AmdIdentifyDimm general service handle
+} AGESA_STRUCT_NAME;
+
+ /* ResetType constant values */
+#define WARM_RESET_WHENEVER 1
+#define COLD_RESET_WHENEVER 2
+#define WARM_RESET_IMMEDIATELY 3
+#define COLD_RESET_IMMEDIATELY 4
+
+
+// AGESA Structures
+
+/// The standard header for all AGESA services.
+/// For internal AGESA naming conventions, see @ref amdconfigparamname .
+typedef struct {
+ IN UINT32 ImageBasePtr; ///< The AGESA Image base address.
+ IN UINT32 Func; ///< The service desired
+ IN UINT32 AltImageBasePtr; ///< Alternate Image location
+ IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA
+ IN UINT8 HeapStatus; ///< For heap status from boot time slide.
+ IN UINT64 HeapBasePtr; ///< Location of the heap
+ IN OUT UINT8 Reserved[7]; ///< This space is reserved for future use.
+} AMD_CONFIG_PARAMS;
+
+
+/// Create Struct Interface.
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN AGESA_STRUCT_NAME AgesaFunctionName; ///< The service to init
+ IN ALLOCATION_METHOD AllocationMethod; ///< How to handle buffer allocation
+ IN OUT UINT32 NewStructSize; ///< The size of the allocated data, in for ByHost, else out only.
+ IN OUT VOID *NewStructPtr; ///< The struct for the service.
+ ///< The struct to init for ByHost allocation,
+ ///< the initialized struct on return.
+} AMD_INTERFACE_PARAMS;
+
+#define FUNC_0 0 // bit-placed for PCI address creation
+#define FUNC_1 1
+#define FUNC_2 2
+#define FUNC_3 3
+#define FUNC_4 4
+#define FUNC_5 5
+#define FUNC_6 6
+#define FUNC_7 7
+
+/// AGESA Binary module header structure
+typedef struct {
+ IN UINT32 Signature; ///< Binary Signature
+ IN CHAR8 CreatorID[8]; ///< 8 characters ID
+ IN CHAR8 Version[12]; ///< 12 characters version
+ IN UINT32 ModuleInfoOffset; ///< Offset of module
+ IN UINT32 EntryPointAddress; ///< Entry address
+ IN UINT32 ImageBase; ///< Image base
+ IN UINT32 RelocTableOffset; ///< Relocate Table offset
+ IN UINT32 ImageSize; ///< Size
+ IN UINT16 Checksum; ///< Checksum
+ IN UINT8 ImageType; ///< Type
+ IN UINT8 V_Reserved; ///< Reserved
+} AMD_IMAGE_HEADER;
+/// AGESA Binary module header structure
+typedef struct _AMD_MODULE_HEADER {
+ IN UINT32 ModuleHeaderSignature; ///< Module signature
+ IN CHAR8 ModuleIdentifier[8]; ///< 8 characters ID
+ IN CHAR8 ModuleVersion[12]; ///< 12 characters version
+ IN VOID *ModuleDispatcher; ///< A pointer point to dispatcher
+ IN struct _AMD_MODULE_HEADER *NextBlock; ///< Next module header link
+} AMD_MODULE_HEADER;
+
+// AMD_CODE_HEADER Signatures.
+#define AGESA_CODE_SIGNATURE {'!', '!', 'A', 'G', 'E', 'S', 'A', ' '}
+#define CIMXNB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'}
+#define CIMXSB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'}
+
+/// AGESA_CODE_SIGNATURE
+typedef struct {
+ IN CHAR8 Signature[8]; ///< code header Signature
+ IN CHAR8 ComponentName[8]; ///< 8 character name of the code module
+ IN CHAR8 Version[12]; ///< 12 character version string
+ IN CHAR8 TerminatorNull; ///< null terminated string
+ IN CHAR8 VerReserved[7]; ///< reserved space
+} AMD_CODE_HEADER;
+
+/// Extended PCI address format
+typedef struct {
+ IN OUT UINT32 Register:12; ///< Register offset
+ IN OUT UINT32 Function:3; ///< Function number
+ IN OUT UINT32 Device:5; ///< Device number
+ IN OUT UINT32 Bus:8; ///< Bus number
+ IN OUT UINT32 Segment:4; ///< Segment
+} EXT_PCI_ADDR;
+
+/// Union type for PCI address
+typedef union _PCI_ADDR {
+ IN UINT32 AddressValue; ///< Formal address
+ IN EXT_PCI_ADDR Address; ///< Extended address
+} PCI_ADDR;
+
+// SBDFO - Segment Bus Device Function Offset
+// 31:28 Segment (4-bits)
+// 27:20 Bus (8-bits)
+// 19:15 Device (5-bits)
+// 14:12 Function(3-bits)
+// 11:00 Offset (12-bits)
+
+#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \
+ (((UINT32)(Dev)) << 15) | (((UINT32)(Fun)) << 12) | ((UINT32)(Off)))
+#define ILLEGAL_SBDFO 0xFFFFFFFF
+
+/// CPUID data received registers format
+typedef struct {
+ OUT UINT32 EAX_Reg; ///< CPUID instruction result in EAX
+ OUT UINT32 EBX_Reg; ///< CPUID instruction result in EBX
+ OUT UINT32 ECX_Reg; ///< CPUID instruction result in ECX
+ OUT UINT32 EDX_Reg; ///< CPUID instruction result in EDX
+} CPUID_DATA;
+
+/// HT frequency for external callbacks
+typedef enum {
+ HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks
+ HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks
+ HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks
+ HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks
+ HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks
+ HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks
+ HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks
+ HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks
+ HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks
+ HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks
+ HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks
+ HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks
+ HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks
+ HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks
+ HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks
+ HT_FREQUENCY_3200M = 19, ///< HT speed 3200 for external callbacks
+ HT_FREQUENCY_MAX ///< Limit check.
+} HT_FREQUENCIES;
+// The minimum HT3 frequency
+#define HT3_FREQUENCY_MIN HT_FREQUENCY_1200M
+
+#ifndef BIT0
+ #define BIT0 0x0000000000000001ull
+#endif
+#ifndef BIT1
+ #define BIT1 0x0000000000000002ull
+#endif
+#ifndef BIT2
+ #define BIT2 0x0000000000000004ull
+#endif
+#ifndef BIT3
+ #define BIT3 0x0000000000000008ull
+#endif
+#ifndef BIT4
+ #define BIT4 0x0000000000000010ull
+#endif
+#ifndef BIT5
+ #define BIT5 0x0000000000000020ull
+#endif
+#ifndef BIT6
+ #define BIT6 0x0000000000000040ull
+#endif
+#ifndef BIT7
+ #define BIT7 0x0000000000000080ull
+#endif
+#ifndef BIT8
+ #define BIT8 0x0000000000000100ull
+#endif
+#ifndef BIT9
+ #define BIT9 0x0000000000000200ull
+#endif
+#ifndef BIT10
+ #define BIT10 0x0000000000000400ull
+#endif
+#ifndef BIT11
+ #define BIT11 0x0000000000000800ull
+#endif
+#ifndef BIT12
+ #define BIT12 0x0000000000001000ull
+#endif
+#ifndef BIT13
+ #define BIT13 0x0000000000002000ull
+#endif
+#ifndef BIT14
+ #define BIT14 0x0000000000004000ull
+#endif
+#ifndef BIT15
+ #define BIT15 0x0000000000008000ull
+#endif
+#ifndef BIT16
+ #define BIT16 0x0000000000010000ull
+#endif
+#ifndef BIT17
+ #define BIT17 0x0000000000020000ull
+#endif
+#ifndef BIT18
+ #define BIT18 0x0000000000040000ull
+#endif
+#ifndef BIT19
+ #define BIT19 0x0000000000080000ull
+#endif
+#ifndef BIT20
+ #define BIT20 0x0000000000100000ull
+#endif
+#ifndef BIT21
+ #define BIT21 0x0000000000200000ull
+#endif
+#ifndef BIT22
+ #define BIT22 0x0000000000400000ull
+#endif
+#ifndef BIT23
+ #define BIT23 0x0000000000800000ull
+#endif
+#ifndef BIT24
+ #define BIT24 0x0000000001000000ull
+#endif
+#ifndef BIT25
+ #define BIT25 0x0000000002000000ull
+#endif
+#ifndef BIT26
+ #define BIT26 0x0000000004000000ull
+#endif
+#ifndef BIT27
+ #define BIT27 0x0000000008000000ull
+#endif
+#ifndef BIT28
+ #define BIT28 0x0000000010000000ull
+#endif
+#ifndef BIT29
+ #define BIT29 0x0000000020000000ull
+#endif
+#ifndef BIT30
+ #define BIT30 0x0000000040000000ull
+#endif
+#ifndef BIT31
+ #define BIT31 0x0000000080000000ull
+#endif
+#ifndef BIT32
+ #define BIT32 0x0000000100000000ull
+#endif
+#ifndef BIT33
+ #define BIT33 0x0000000200000000ull
+#endif
+#ifndef BIT34
+ #define BIT34 0x0000000400000000ull
+#endif
+#ifndef BIT35
+ #define BIT35 0x0000000800000000ull
+#endif
+#ifndef BIT36
+ #define BIT36 0x0000001000000000ull
+#endif
+#ifndef BIT37
+ #define BIT37 0x0000002000000000ull
+#endif
+#ifndef BIT38
+ #define BIT38 0x0000004000000000ull
+#endif
+#ifndef BIT39
+ #define BIT39 0x0000008000000000ull
+#endif
+#ifndef BIT40
+ #define BIT40 0x0000010000000000ull
+#endif
+#ifndef BIT41
+ #define BIT41 0x0000020000000000ull
+#endif
+#ifndef BIT42
+ #define BIT42 0x0000040000000000ull
+#endif
+#ifndef BIT43
+ #define BIT43 0x0000080000000000ull
+#endif
+#ifndef BIT44
+ #define BIT44 0x0000100000000000ull
+#endif
+#ifndef BIT45
+ #define BIT45 0x0000200000000000ull
+#endif
+#ifndef BIT46
+ #define BIT46 0x0000400000000000ull
+#endif
+#ifndef BIT47
+ #define BIT47 0x0000800000000000ull
+#endif
+#ifndef BIT48
+ #define BIT48 0x0001000000000000ull
+#endif
+#ifndef BIT49
+ #define BIT49 0x0002000000000000ull
+#endif
+#ifndef BIT50
+ #define BIT50 0x0004000000000000ull
+#endif
+#ifndef BIT51
+ #define BIT51 0x0008000000000000ull
+#endif
+#ifndef BIT52
+ #define BIT52 0x0010000000000000ull
+#endif
+#ifndef BIT53
+ #define BIT53 0x0020000000000000ull
+#endif
+#ifndef BIT54
+ #define BIT54 0x0040000000000000ull
+#endif
+#ifndef BIT55
+ #define BIT55 0x0080000000000000ull
+#endif
+#ifndef BIT56
+ #define BIT56 0x0100000000000000ull
+#endif
+#ifndef BIT57
+ #define BIT57 0x0200000000000000ull
+#endif
+#ifndef BIT58
+ #define BIT58 0x0400000000000000ull
+#endif
+#ifndef BIT59
+ #define BIT59 0x0800000000000000ull
+#endif
+#ifndef BIT60
+ #define BIT60 0x1000000000000000ull
+#endif
+#ifndef BIT61
+ #define BIT61 0x2000000000000000ull
+#endif
+#ifndef BIT62
+ #define BIT62 0x4000000000000000ull
+#endif
+#ifndef BIT63
+ #define BIT63 0x8000000000000000ull
+#endif
+
+#endif // _AMD_H_
diff --git a/src/vendorcode/amd/agesa/f14/Dispatcher.h b/src/vendorcode/amd/agesa/f14/Dispatcher.h
new file mode 100644
index 0000000..fd6aaa8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Dispatcher.h
@@ -0,0 +1,54 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Pushhigh Interface
+ *
+ * Contains interface to Pushhigh entry
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Legacy
+ * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _DISPATCHER_H_
+#define _DISPATCHER_H_
+
+// AGESA function prototypes
+AGESA_STATUS CALLCONV AmdAgesaDispatcher ( IN OUT VOID *ConfigPtr );
+AGESA_STATUS CALLCONV AmdAgesaCallout ( IN UINT32 Func, IN UINT32 Data, IN OUT VOID *ConfigPtr );
+
+#endif // _DISPATCHER_H_
diff --git a/src/vendorcode/amd/agesa/f14/Include/AdvancedApi.h b/src/vendorcode/amd/agesa/f14/Include/AdvancedApi.h
new file mode 100644
index 0000000..573650a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Include/AdvancedApi.h
@@ -0,0 +1,168 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Advanced API Interface for HT, Memory and CPU
+ *
+ * Contains additional declarations need to use HT, Memory and CPU Advanced interface, such as
+ * would be required by the basic interface implementations.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Include
+ * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+
+#ifndef _ADVANCED_API_H_
+#define _ADVANCED_API_H_
+
+/*----------------------------------------------------------------------------
+ * HT FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * A constructor for the HyperTransport input structure.
+ *
+ * Sets inputs to valid, basic level, defaults.
+ *
+ * @param[in] StdHeader Opaque handle to standard config header
+ * @param[in] AmdHtInterface HT Interface structure to initialize.
+ *
+ * @retval AGESA_SUCCESS Constructors are not allowed to fail
+*/
+AGESA_STATUS
+AmdHtInterfaceConstructor (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN AMD_HT_INTERFACE *AmdHtInterface
+ );
+
+/**
+ * The top level external interface for Hypertransport Initialization.
+ *
+ * Create our initial internal state, initialize the coherent fabric,
+ * initialize the non-coherent chains, and perform any required fabric tuning or
+ * optimization.
+ *
+ * @param[in] StdHeader Opaque handle to standard config header
+ * @param[in] PlatformConfiguration The platform configuration options.
+ * @param[in] AmdHtInterface HT Interface structure.
+ *
+ * @retval AGESA_SUCCESS Only information events logged.
+ * @retval AGESA_ALERT Sync Flood or CRC error logged.
+ * @retval AGESA_WARNING Example: expected capability not found
+ * @retval AGESA_ERROR logged events indicating some devices may not be available
+ * @retval AGESA_FATAL Mixed Family or MP capability mismatch
+ *
+ */
+AGESA_STATUS
+AmdHtInitialize (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN PLATFORM_CONFIGURATION *PlatformConfiguration,
+ IN AMD_HT_INTERFACE *AmdHtInterface
+ );
+
+/*----------------------------------------------------------------------------
+ * HT Recovery FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * A constructor for the HyperTransport input structure.
+ *
+ */
+AGESA_STATUS
+AmdHtResetConstructor (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface
+ );
+
+/**
+ * Initialize HT at Reset for both Normal and Recovery.
+ *
+ */
+AGESA_STATUS
+AmdHtInitReset (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface
+ );
+
+/**
+ * Initialize the Node and Socket maps for an AP Core.
+ *
+ */
+AGESA_STATUS
+AmdHtInitRecovery (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+///----------------------------------------------------------------------------
+/// MEMORY FUNCTIONS PROTOTYPE
+///
+///----------------------------------------------------------------------------
+
+AGESA_STATUS
+AmdMemRecovery (
+ IN OUT MEM_DATA_STRUCT *MemPtr
+ );
+
+AGESA_STATUS
+AmdMemAuto (
+ IN OUT MEM_DATA_STRUCT *MemPtr
+ );
+
+VOID
+AmdMemInitDataStructDef (
+ IN OUT MEM_DATA_STRUCT *MemPtr,
+ IN OUT PLATFORM_CONFIGURATION *PlatFormConfig
+ );
+
+VOID
+memDefRet (
+ VOID
+ );
+
+BOOLEAN
+memDefTrue (
+ VOID
+ );
+
+BOOLEAN
+memDefFalse (
+ VOID
+ );
+#endif // _ADVANCED_API_H_
diff --git a/src/vendorcode/amd/agesa/f14/Include/BrazosInstall.h b/src/vendorcode/amd/agesa/f14/Include/BrazosInstall.h
new file mode 100644
index 0000000..6753965
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Include/BrazosInstall.h
@@ -0,0 +1,102 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build options for a Brazos platform solution
+ *
+ * This file generates the defaults tables for the "Brazos" platform solution
+ * set of processors. The documented build options are imported from a user
+ * controlled file for processing.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Core
+ * @e \$Revision: 40817 $ @e \$Date: 2010-10-28 03:28:12 +0800 (Thu, 28 Oct 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "AdvancedApi.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "cpuFeatures.h"
+#include "Table.h"
+#include "CommonReturns.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "GnbInterface.h"
+
+/*****************************************************************************
+ * Define the RELEASE VERSION string
+ *
+ * The Release Version string should identify the next planned release.
+ * When a branch is made in preparation for a release, the release manager
+ * should change/confirm that the branch version of this file contains the
+ * string matching the desired version for the release. The trunk version of
+ * the file should always contain a trailing 'X'. This will make sure that a
+ * development build from trunk will not be confused for a released version.
+ * The release manager will need to remove the trailing 'X' and update the
+ * version string as appropriate for the release. The trunk copy of this file
+ * should also be updated/incremented for the next expected version, + trailing 'X'
+ ****************************************************************************/
+ // This is the delivery package title, "BrazosPI"
+ // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING {'O', 'n', 't', 'a', 'r', 'o', 'P', 'I'}
+
+ // This is the release version number of the AGESA component
+ // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING {'V', '1', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
+
+
+// The Brazos solution is defined to be family 0x14 in the FT1 socket.
+#define INSTALL_FT1_SOCKET_SUPPORT TRUE
+#define INSTALL_FAMILY_14_SUPPORT TRUE
+
+
+// The following definitions specify the default values for various parameters in which there are
+// no clearly defined defaults to be used in the common file. The values below are based on product
+// and BKDG content, please consult the AGESA Memory team for consultation.
+#define DFLT_SCRUB_DRAM_RATE (0)
+#define DFLT_SCRUB_L2_RATE (0)
+#define DFLT_SCRUB_L3_RATE (0)
+#define DFLT_SCRUB_IC_RATE (0)
+#define DFLT_SCRUB_DC_RATE (0)
+#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
+#define DFLT_VRM_SLEW_RATE (5000)
+
+
+// Instantiate all solution relevant data.
+#include "PlatformInstall.h"
+
diff --git a/src/vendorcode/amd/agesa/f14/Include/CommonReturns.h b/src/vendorcode/amd/agesa/f14/Include/CommonReturns.h
new file mode 100644
index 0000000..9912edc
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Include/CommonReturns.h
@@ -0,0 +1,125 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Common Return routines.
+ *
+ * Routines which do nothing, returning a result (preferably some version of zero) which
+ * is consistent with "do nothing" or "default". Useful for function pointer tables.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Common
+ * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _COMMON_RETURNS_H_
+#define _COMMON_RETURNS_H_
+
+
+/**
+* Return True
+*
+* @retval True Default case, no special action
+*/
+BOOLEAN
+CommonReturnTrue (void);
+
+/**
+* Return False.
+*
+* @retval FALSE Default case, no special action
+*/
+BOOLEAN
+CommonReturnFalse (void);
+
+/**
+ * Return (UINT8)zero.
+ *
+ *
+ * @retval zero None, or only case zero.
+ */
+UINT8
+CommonReturnZero8 (void);
+
+/**
+ * Return (UINT32)zero.
+ *
+ *
+ * @retval zero None, or only case zero.
+ */
+UINT32
+CommonReturnZero32 (void);
+
+/**
+ * Return (UINT64)zero.
+ *
+ *
+ * @retval zero None, or only case zero.
+ */
+UINT64
+CommonReturnZero64 (void);
+
+/**
+ * Return NULL
+ *
+ * @retval NULL pointer to nothing
+ */
+VOID *
+CommonReturnNULL (void);
+
+/**
+* Return AGESA_SUCCESS.
+*
+* @retval AGESA_SUCCESS Success.
+*/
+AGESA_STATUS
+CommonReturnAgesaSuccess (void);
+
+/**
+ * Do Nothing.
+ *
+ */
+VOID
+CommonVoid (void);
+
+/**
+ * ASSERT if this routine is called.
+ *
+ */
+VOID
+CommonAssert (void);
+
+#endif // _COMMON_RETURNS_H_
diff --git a/src/vendorcode/amd/agesa/f14/Include/DanNiInstall.h b/src/vendorcode/amd/agesa/f14/Include/DanNiInstall.h
new file mode 100644
index 0000000..c56f90c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Include/DanNiInstall.h
@@ -0,0 +1,117 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build options for a Danube + Nile platform solution
+ *
+ * This file generates the defaults tables for the "DanNi" platform solution
+ * set of processors. The documented build options are imported from a user
+ * controlled file for processing.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Core
+ * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "AdvancedApi.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "cpuFeatures.h"
+#include "Table.h"
+#include "CommonReturns.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "GnbInterfaceStub.h"
+
+/*****************************************************************************
+ * Define the RELEASE VERSION string
+ *
+ * The Release Version string should identify the next planned release.
+ * When a branch is made in preparation for a release, the release manager
+ * should change/confirm that the branch version of this file contains the
+ * string matching the desired version for the release. The trunk version of
+ * the file should always contain a trailing 'X'. This will make sure that a
+ * development build from trunk will not be confused for a released version.
+ * The release manager will need to remove the trailing 'X' and update the
+ * version string as appropriate for the release. The trunk copy of this file
+ * should also be updated/incremented for the next expected version, + trailing 'X'
+ ****************************************************************************/
+ // This is the delivery package title, "DanNiPI "
+ // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING {'D', 'a', 'n', 'N', 'i', 'P', 'I', ' '}
+
+ // This is the release version number of the AGESA component
+ // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '5', '.', '0', 'X', ' ', ' ', ' '}
+
+
+// The DanNi solution is defined to be family 0x10 in the S1g4 and ASB2 sockets.
+#define INSTALL_S1G4_SOCKET_SUPPORT TRUE
+#define INSTALL_ASB2_SOCKET_SUPPORT TRUE
+#define INSTALL_FAMILY_10_SUPPORT TRUE
+
+#ifdef BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT
+ #if BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT == TRUE
+ #undef INSTALL_S1G4_SOCKET_SUPPORT
+ #define INSTALL_S1G4_SOCKET_SUPPORT FALSE
+ #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT
+ #if BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT == TRUE
+ #undef INSTALL_ASB2_SOCKET_SUPPORT
+ #define INSTALL_ASB2_SOCKET_SUPPORT FALSE
+ #endif
+#endif
+
+
+// The following definitions specify the default values for various parameters in which there are
+// no clearly defined defaults to be used in the common file. The values below are based on product
+// and BKDG content, please consult the AGESA Memory team for consultation.
+#define DFLT_SCRUB_DRAM_RATE (0)
+#define DFLT_SCRUB_L2_RATE (0x10)
+#define DFLT_SCRUB_L3_RATE (0x10)
+#define DFLT_SCRUB_IC_RATE (0)
+#define DFLT_SCRUB_DC_RATE (0x12)
+#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
+#define DFLT_VRM_SLEW_RATE (5000)
+
+
+// Instantiate all solution relevant data.
+#include "PlatformInstall.h"
+
diff --git a/src/vendorcode/amd/agesa/f14/Include/DanubeInstall.h b/src/vendorcode/amd/agesa/f14/Include/DanubeInstall.h
new file mode 100644
index 0000000..f2c91c4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Include/DanubeInstall.h
@@ -0,0 +1,102 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build options for a Danube platform solution
+ *
+ * This file generates the defaults tables for the "Danube" platform solution
+ * set of processors. The documented build options are imported from a user
+ * controlled file for processing.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Core
+ * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "AdvancedApi.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "cpuFeatures.h"
+#include "Table.h"
+#include "CommonReturns.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "GnbInterfaceStub.h"
+
+/*****************************************************************************
+ * Define the RELEASE VERSION string
+ *
+ * The Release Version string should identify the next planned release.
+ * When a branch is made in preparation for a release, the release manager
+ * should change/confirm that the branch version of this file contains the
+ * string matching the desired version for the release. The trunk version of
+ * the file should always contain a trailing 'X'. This will make sure that a
+ * development build from trunk will not be confused for a released version.
+ * The release manager will need to remove the trailing 'X' and update the
+ * version string as appropriate for the release. The trunk copy of this file
+ * should also be updated/incremented for the next expected version, + trailing 'X'
+ ****************************************************************************/
+ // This is the delivery package title, "DanNiPI "
+ // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING {'D', 'a', 'n', 'N', 'i', 'P', 'I', ' '}
+
+ // This is the release version number of the AGESA component
+ // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '5', '.', '0', 'X', ' ', ' ', ' '}
+
+
+// The Danube solution is defined to be family 0x10 in the S1g4 socket.
+#define INSTALL_S1G4_SOCKET_SUPPORT TRUE
+#define INSTALL_FAMILY_10_SUPPORT TRUE
+
+
+// The following definitions specify the default values for various parameters in which there are
+// no clearly defined defaults to be used in the common file. The values below are based on product
+// and BKDG content, please consult the AGESA Memory team for consultation.
+#define DFLT_SCRUB_DRAM_RATE (0)
+#define DFLT_SCRUB_L2_RATE (0x10)
+#define DFLT_SCRUB_L3_RATE (0)
+#define DFLT_SCRUB_IC_RATE (0)
+#define DFLT_SCRUB_DC_RATE (0x12)
+#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
+#define DFLT_VRM_SLEW_RATE (5000)
+
+
+// Instantiate all solution relevant data.
+#include "PlatformInstall.h"
+
diff --git a/src/vendorcode/amd/agesa/f14/Include/DevTestInstall.h b/src/vendorcode/amd/agesa/f14/Include/DevTestInstall.h
new file mode 100644
index 0000000..9874551
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Include/DevTestInstall.h
@@ -0,0 +1,111 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build options for a DevTest platform solution
+ *
+ * This file generates the defaults tables for the "DevTest" platform solution
+ * set of processors. The documented build options are imported from a user
+ * controlled file for processing.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Core
+ * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "AdvancedApi.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "cpuFeatures.h"
+#include "Table.h"
+#include "CommonReturns.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "GnbInterfaceStub.h"
+
+/*****************************************************************************
+ * Define the RELEASE VERSION string
+ *
+ * The Release Version string should identify the next planned release.
+ * When a branch is made in preparation for a release, the release manager
+ * should change/confirm that the branch version of this file contains the
+ * string matching the desired version for the release. The trunk version of
+ * the file should always contain a trailing 'X'. This will make sure that a
+ * development build from trunk will not be confused for a released version.
+ * The release manager will need to remove the trailing 'X' and update the
+ * version string as appropriate for the release. The trunk copy of this file
+ * should also be updated/incremented for the next expected version, + trailing 'X'
+ ****************************************************************************/
+ // This is the delivery package title, "DevTest "
+ // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING {'D', 'e', 'v', 'T', 'e', 's', 't', ' '}
+
+ // This is the release version number of the AGESA component
+ // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING {'V', '0', '.', '1', '.', '2', '.', '3', 'X', ' ', ' ', ' '}
+
+
+// The DevTest solution is defined to be everything that AGESA supports.
+#define INSTALL_C32_SOCKET_SUPPORT TRUE
+#define INSTALL_G34_SOCKET_SUPPORT TRUE
+#define INSTALL_S1G4_SOCKET_SUPPORT TRUE
+#define INSTALL_ASB2_SOCKET_SUPPORT TRUE
+#define INSTALL_FS1_SOCKET_SUPPORT TRUE
+#define INSTALL_FM1_SOCKET_SUPPORT TRUE
+#define INSTALL_FT1_SOCKET_SUPPORT TRUE
+#define INSTALL_AM3_SOCKET_SUPPORT TRUE
+#define INSTALL_FAMILY_10_SUPPORT TRUE
+#define INSTALL_FAMILY_12_SUPPORT TRUE
+#define INSTALL_FAMILY_14_SUPPORT TRUE
+#define INSTALL_FAMILY_15_SUPPORT TRUE
+
+// The following definitions specify the default values for various parameters in which there are
+// no clearly defined defaults to be used in the common file. The values below are based on product
+// and BKDG content, please consult the AGESA Memory team for consultation.
+#define DFLT_SCRUB_DRAM_RATE (0xFF)
+#define DFLT_SCRUB_L2_RATE (0x10)
+#define DFLT_SCRUB_L3_RATE (0x10)
+#define DFLT_SCRUB_IC_RATE (0)
+#define DFLT_SCRUB_DC_RATE (0x12)
+#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
+#define DFLT_VRM_SLEW_RATE (2500)
+
+
+// Instantiate all solution relevant data.
+#include "PlatformInstall.h"
+
diff --git a/src/vendorcode/amd/agesa/f14/Include/DragonInstall.h b/src/vendorcode/amd/agesa/f14/Include/DragonInstall.h
new file mode 100644
index 0000000..ee45b72
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Include/DragonInstall.h
@@ -0,0 +1,102 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build options for a Dragon platform solution
+ *
+ * This file generates the defaults tables for the "Dragon" platform solution
+ * set of processors. The documented build options are imported from a user
+ * controlled file for processing.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Core
+ * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "AdvancedApi.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "cpuFeatures.h"
+#include "Table.h"
+#include "CommonReturns.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "GnbInterfaceStub.h"
+
+/*****************************************************************************
+ * Define the RELEASE VERSION string
+ *
+ * The Release Version string should identify the next planned release.
+ * When a branch is made in preparation for a release, the release manager
+ * should change/confirm that the branch version of this file contains the
+ * string matching the desired version for the release. The trunk version of
+ * the file should always contain a trailing 'X'. This will make sure that a
+ * development build from trunk will not be confused for a released version.
+ * The release manager will need to remove the trailing 'X' and update the
+ * version string as appropriate for the release. The trunk copy of this file
+ * should also be updated/incremented for the next expected version, + trailing 'X'
+ ****************************************************************************/
+ // This is the delivery package title, "DragonPI"
+ // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING {'D', 'r', 'a', 'g', 'o', 'n', 'P', 'I'}
+
+ // This is the release version number of the AGESA component
+ // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING {'V', '0', '.', '1', '.', '2', '.', '3', 'X', ' ', ' ', ' '}
+
+
+// The Danube solution is defined to be family 0x10 in the AM3 socket.
+#define INSTALL_AM3_SOCKET_SUPPORT TRUE
+#define INSTALL_FAMILY_10_SUPPORT TRUE
+
+
+// The following definitions specify the default values for various parameters in which there are
+// no clearly defined defaults to be used in the common file. The values below are based on product
+// and BKDG content, please consult the AGESA Memory team for consultation.
+#define DFLT_SCRUB_DRAM_RATE (0)
+#define DFLT_SCRUB_L2_RATE (0)
+#define DFLT_SCRUB_L3_RATE (0)
+#define DFLT_SCRUB_IC_RATE (0)
+#define DFLT_SCRUB_DC_RATE (0)
+#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
+#define DFLT_VRM_SLEW_RATE (2500)
+
+
+// Instantiate all solution relevant data.
+#include "PlatformInstall.h"
+
diff --git a/src/vendorcode/amd/agesa/f14/Include/Filecode.h b/src/vendorcode/amd/agesa/f14/Include/Filecode.h
new file mode 100644
index 0000000..9ba1b29
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Include/Filecode.h
@@ -0,0 +1,849 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Collectively assign unique filecodes for assert and debug to each source file.
+ *
+ * Publish values for decorated filenames, which can be used for
+ * ASSERT and debug support using a preprocessor define like:
+ * @n <tt> \#define FILECODE MY_C_FILENAME_FILECODE </tt> @n
+ * This file serves as a reference for debugging to associate the code and filename.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Include
+ * @e \$Revision: 40742 $ @e \$Date: 2010-10-27 04:04:08 +0800 (Wed, 27 Oct 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _FILECODE_H_
+#define _FILECODE_H_
+
+#define UNASSIGNED_FILE_FILECODE (0xFFFF)
+
+/// For debug use in any Platform's options C file.
+/// Can be reused for platforms and image builds, since only one options file can be built.
+#define PLATFORM_SPECIFIC_OPTIONS_FILECODE (0xBBBB)
+
+
+#define PROC_GNB_COMMON_GNBLIBFEATURES_FILECODE (0xA001)
+#define PROC_GNB_GFX_FAMILY_0X12_F12GFXSERVICES_FILECODE (0xA002)
+#define PROC_GNB_GFX_FAMILY_0X14_F14GFXSERVICES_FILECODE (0xA003)
+#define PROC_GNB_GFX_GFXCONFIGDATA_FILECODE (0xA004)
+#define PROC_GNB_GFX_GFXDEBUGBAR_FILECODE (0xA005)
+#define PROC_GNB_GFX_GFXGMCINIT_FILECODE (0xA006)
+#define PROC_GNB_GFX_GFXINITATENVPOST_FILECODE (0xA010)
+#define PROC_GNB_GFX_GFXINITATMIDPOST_FILECODE (0xA011)
+#define PROC_GNB_GFX_GFXINITATPOST_FILECODE (0xA012)
+#define PROC_GNB_GFX_GFXINTEGRATEDINFOTABLEINIT_FILECODE (0xA013)
+#define PROC_GNB_GFX_GFXLIB_FILECODE (0xA014)
+#define PROC_GNB_GFX_GFXREGISTERACC_FILECODE (0xA015)
+#define PROC_GNB_GFX_GFXSTRAPSINIT_FILECODE (0xA016)
+#define PROC_GNB_GNBINITATEARLY_FILECODE (0xA017)
+#define PROC_GNB_GNBINITATENV_FILECODE (0xA020)
+#define PROC_GNB_GNBINITATLATE_FILECODE (0xA021)
+#define PROC_GNB_GNBINITATMID_FILECODE (0xA022)
+#define PROC_GNB_GNBINITATPOST_FILECODE (0xA023)
+#define PROC_GNB_GNBINITATRESET_FILECODE (0xA024)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIB_FILECODE (0xA025)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBCPUACC_FILECODE (0xA026)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBHEAP_FILECODE (0xA027)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBIOACC_FILECODE (0xA028)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBMEMACC_FILECODE (0xA029)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCI_FILECODE (0xA02A)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCIACC_FILECODE (0xA030)
+#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXCARDINFO_FILECODE (0xA031)
+#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXENUMCONNECTORS_FILECODE (0xA032)
+#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXPOWERPLAYTABLE_FILECODE (0xA033)
+#define PROC_GNB_MODULES_GNBNBINITLIBV1_GNBNBINITLIBV1_FILECODE (0xA034)
+#define PROC_GNB_MODULES_GNBPCIEALIBV1_PCIEALIB_FILECODE (0xA035)
+#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGDATA_FILECODE (0xA036)
+#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGLIB_FILECODE (0xA037)
+#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIEINPUTPARSER_FILECODE (0xA038)
+#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIEMAPTOPOLOGY_FILECODE (0xA039)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPM_FILECODE (0xA03A)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMBLACKLIST_FILECODE (0xA03B)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMEXITLATENCY_FILECODE (0xA03C)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPHYSERVICES_FILECODE (0xA03D)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPIFSERVICES_FILECODE (0xA03E)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTREGACC_FILECODE (0xA03F)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTSERVICES_FILECODE (0xA041)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPOWERMGMT_FILECODE (0xA043)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIESBLINK_FILECODE (0xA044)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIESILICONSERVICES_FILECODE (0xA045)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETIMER_FILECODE (0xA046)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETOPOLOGYSERVICES_FILECODE (0xA047)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEUTILITYLIB_FILECODE (0xA048)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEWRAPPERREGACC_FILECODE (0xA049)
+#define PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIETRAINING_FILECODE (0xA04A)
+#define PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIEWORKAROUNDS_FILECODE (0xA04B)
+#define PROC_GNB_NB_FAMILY_0X12_F12NBPOWERGATE_FILECODE (0xA04C)
+#define PROC_GNB_NB_FAMILY_0X12_F12NBSERVICES_FILECODE (0xA04D)
+#define PROC_GNB_NB_FAMILY_0X12_F12NBSMU_FILECODE (0xA04E)
+#define PROC_GNB_NB_FAMILY_0X14_F14NBLCLKNCLKRATIO_FILECODE (0xA04F)
+#define PROC_GNB_NB_FAMILY_0X14_F14NBPOWERGATE_FILECODE (0xA050)
+#define PROC_GNB_NB_FAMILY_0X14_F14NBSERVICES_FILECODE (0xA051)
+#define PROC_GNB_NB_FAMILY_0X14_F14NBSMU_FILECODE (0xA052)
+#define PROC_GNB_NB_FEATURE_NBFUSETABLE_FILECODE (0xA053)
+#define PROC_GNB_NB_FEATURE_NBLCLKDPM_FILECODE (0xA054)
+#define PROC_GNB_NB_FAMILY_0X12_F12NBLCLKDPM_FILECODE (0xA055)
+#define PROC_GNB_NB_FAMILY_0X14_F14NBLCLKDPM_FILECODE (0xA056)
+#define PROC_GNB_NB_NBCONFIGDATA_FILECODE (0xA060)
+#define PROC_GNB_NB_NBINIT_FILECODE (0xA061)
+#define PROC_GNB_NB_NBINITATEARLY_FILECODE (0xA062)
+#define PROC_GNB_NB_NBINITATENV_FILECODE (0xA063)
+#define PROC_GNB_NB_NBINITATLATEPOST_FILECODE (0xA070)
+#define PROC_GNB_NB_NBINITATPOST_FILECODE (0xA071)
+#define PROC_GNB_NB_NBINITATRESET_FILECODE (0xA072)
+#define PROC_GNB_NB_NBPOWERMGMT_FILECODE (0xA073)
+#define PROC_GNB_NB_NBSMULIB_FILECODE (0xA074)
+#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIEALIB_FILECODE (0xA075)
+#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXCONFIG_FILECODE (0xA076)
+#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXSERVICES_FILECODE (0xA077)
+#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIEPHYSERVICES_FILECODE (0xA078)
+#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIEPIFSERVICES_FILECODE (0xA079)
+#define PROC_GNB_PCIE_FAMILY_0X12_F12PCIEWRAPPERSERVICES_FILECODE (0xA07A)
+#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIEALIB_FILECODE (0xA07D)
+#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIECOMPLEXCONFIG_FILECODE (0xA07E)
+#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIECOMPLEXSERVICES_FILECODE (0xA07F)
+#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIEPHYSERVICES_FILECODE (0xA080)
+#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIEPIFSERVICES_FILECODE (0xA081)
+#define PROC_GNB_PCIE_FAMILY_0X14_F14PCIEWRAPPERSERVICES_FILECODE (0xA082)
+#define PROC_GNB_PCIE_FEATURE_PCIEPOWERGATE_FILECODE (0xA083)
+#define PROC_GNB_PCIE_PCIEINIT_FILECODE (0xA084)
+#define PROC_GNB_PCIE_PCIEINITATEARLYPOST_FILECODE (0xA085)
+#define PROC_GNB_PCIE_PCIEINITATENV_FILECODE (0xA086)
+#define PROC_GNB_PCIE_PCIEINITATLATEPOST_FILECODE (0xA087)
+#define PROC_GNB_PCIE_PCIEINITATPOST_FILECODE (0xA088)
+#define PROC_GNB_PCIE_PCIELATEINIT_FILECODE (0xA089)
+#define PROC_GNB_PCIE_PCIEMISCLIB_FILECODE (0xA08A)
+#define PROC_GNB_PCIE_PCIEPORTINIT_FILECODE (0xA08B)
+#define PROC_GNB_PCIE_PCIEPORTLATEINIT_FILECODE (0xA08C)
+#define PROC_GNB_MODULES_GNBCABLESAFE_GNBCABLESAFE_FILECODE (0xA08D)
+#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGENV_FILECODE (0xA08E)
+#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGPOST_FILECODE (0xA08F)
+
+#define PROC_RECOVERY_GNB_GNBRECOVERY_FILECODE (0xAE01)
+#define PROC_RECOVERY_GNB_NBINITRECOVERY_FILECODE (0xAE02)
+
+// FCH
+#define PROC_COMMON_AMDFCH_FILECODE (0xB000)
+#define PROC_FCH_AZALIA_AZALIA_FILECODE (0xB001)
+#define PROC_FCH_AZALIA_AZALIARESET_FILECODE (0xB002)
+#define PROC_FCH_COMMON_ACPILIB_FILECODE (0xB010)
+#define PROC_FCH_COMMON_AMDSBLIB_FILECODE (0xB011)
+#define PROC_FCH_COMMON_FCHCOMMON_FILECODE (0xB012)
+#define PROC_FCH_COMMON_FCHCOMMONSMM_FILECODE (0xB013)
+#define PROC_FCH_COMMON_MEMLIB_FILECODE (0xB014)
+#define PROC_FCH_COMMON_PCILIB_FILECODE (0xB015)
+#define PROC_FCH_COMMON_SBPELIB_FILECODE (0xB016)
+#define PROC_FCH_GEC_FAMILY_HUDSON2_GEC_FILECODE (0xB020)
+#define PROC_FCH_GEC_FAMILY_HUDSON2_GECRESET_FILECODE (0xB021)
+#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HWACPI_FILECODE (0xB030)
+#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HWACPIRESET_FILECODE (0xB031)
+#define PROC_FCH_HWM_FAMILY_HUDSON2_HWM_FILECODE (0xB032)
+#define PROC_FCH_HWM_FAMILY_HUDSON2_HWMRESET_FILECODE (0xB033)
+#define PROC_FCH_IDE_IDE_FILECODE (0xB040)
+#define PROC_FCH_IMC_FAMILY_HUDSON2_IMC_FILECODE (0xB050)
+#define PROC_FCH_IMC_FAMILY_HUDSON2_IMCLIB_FILECODE (0xB051)
+#define PROC_FCH_IMC_FAMILY_HUDSON2_IMCRESET_FILECODE (0xB052)
+#define PROC_FCH_IMC_FAMILY_HUDSON2_SBEC_FILECODE (0xB053)
+#define PROC_FCH_IMC_FAMILY_HUDSON2_SBECRESET_FILECODE (0xB054)
+#define PROC_FCH_INTERFACE_INITRESETDEF_FILECODE (0xB060)
+#define PROC_FCH_INTERFACE_INITENVDEF_FILECODE (0xB061)
+#define PROC_FCH_INTERFACE_FCHINITRESET_FILECODE (0xB062)
+#define PROC_FCH_INTERFACE_FCHINITENV_FILECODE (0xB063)
+#define PROC_FCH_INTERFACE_FCHINITLATE_FILECODE (0xB064)
+#define PROC_FCH_INTERFACE_FCHINITMID_FILECODE (0xB065)
+#define PROC_FCH_INTERFACE_FCHINITS3_FILECODE (0xB066)
+#define PROC_FCH_INTERFACE_FCHTASKLAUNCHER_FILECODE (0xB067)
+#define PROC_FCH_IR_IR_FILECODE (0xB070)
+#define PROC_FCH_PCIB_PCIB_FILECODE (0xB080)
+#define PROC_FCH_PCIB_PCIBRESET_FILECODE (0xB081)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_AB_FILECODE (0xB090)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_ABRESET_FILECODE (0xB091)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_GPP_FILECODE (0xB092)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_GPPHP_FILECODE (0xB093)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_GPPLIB_FILECODE (0xB094)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_GPPRESET_FILECODE (0xB095)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_PCIE_FILECODE (0xB096)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_PCIERESET_FILECODE (0xB097)
+#define PROC_FCH_SATA_FAMILY_HUDSON2_AHCI_FILECODE (0xB0A0)
+#define PROC_FCH_SATA_FAMILY_HUDSON2_AHCILIB_FILECODE (0xB0A1)
+#define PROC_FCH_SATA_FAMILY_HUDSON2_IDE2AHCI_FILECODE (0xB0A2)
+#define PROC_FCH_SATA_FAMILY_HUDSON2_IDE2AHCILIB_FILECODE (0xB0A3)
+#define PROC_FCH_SATA_FAMILY_HUDSON2_RAID_FILECODE (0xB0A4)
+#define PROC_FCH_SATA_FAMILY_HUDSON2_RAIDLIB_FILECODE (0xB0A5)
+#define PROC_FCH_SATA_FAMILY_HUDSON2_SATA_FILECODE (0xB0A6)
+#define PROC_FCH_SATA_FAMILY_HUDSON2_SATAIDE_FILECODE (0xB0A7)
+#define PROC_FCH_SATA_FAMILY_HUDSON2_SATAIDELIB_FILECODE (0xB0A8)
+#define PROC_FCH_SATA_FAMILY_HUDSON2_SATALIB_FILECODE (0xB0A9)
+#define PROC_FCH_SATA_FAMILY_HUDSON2_SATARESET_FILECODE (0xB0AA)
+#define PROC_FCH_SBUSB_FAMILY_HUDSON2_EHCI_FILECODE (0xB0B0)
+#define PROC_FCH_SBUSB_FAMILY_HUDSON2_EHCIRESET_FILECODE (0xB0B1)
+#define PROC_FCH_SBUSB_FAMILY_HUDSON2_OHCI_FILECODE (0xB0B2)
+#define PROC_FCH_SBUSB_FAMILY_HUDSON2_OHCIRESET_FILECODE (0xB0B3)
+#define PROC_FCH_SBUSB_FAMILY_HUDSON2_USB_FILECODE (0xB0B4)
+#define PROC_FCH_SBUSB_FAMILY_HUDSON2_USBRESET_FILECODE (0xB0B5)
+#define PROC_FCH_SBUSB_FAMILY_HUDSON2_XHCI_FILECODE (0xB0B6)
+#define PROC_FCH_SBUSB_FAMILY_HUDSON2_XHCIRESET_FILECODE (0xB0B7)
+#define PROC_FCH_SD_SD_FILECODE (0xB0C0)
+#define PROC_FCH_SPI_LPC_FILECODE (0xB0D0)
+#define PROC_FCH_SPI_LPCRESET_FILECODE (0xB0D1)
+#define PROC_FCH_SPI_SPI_FILECODE (0xB0D2)
+#define PROC_FCH_SPI_SPIRESET_FILECODE (0xB0D3)
+
+#define UEFI_DXE_AMDSBDXE_AMDSBDXE_FILECODE (0xB200)
+#define UEFI_DXE_AMDSBWHEA_AMDSBWHEA_FILECODE (0xB210)
+#define UEFI_DXE_AMDSBWHEA_BERTTABLE_FILECODE (0xB211)
+#define UEFI_DXE_AMDSBWHEA_EINJTABLE_FILECODE (0xB212)
+#define UEFI_DXE_AMDSBWHEA_ERSTTABLE_FILECODE (0xB213)
+#define UEFI_DXE_AMDSBWHEA_HESTTABLE_FILECODE (0xB214)
+#define UEFI_DXE_CF9RESET_CF9RESET_FILECODE (0xB220)
+#define UEFI_DXE_CF9RESET_IA32_IA32CF9RESET_FILECODE (0xB221)
+#define UEFI_DXE_CF9RESET_X64_X64CF9RESET_FILECODE (0xB222)
+#define UEFI_DXE_LEGACYINTERRUPT_LEGACYINTERRUPT_FILECODE (0xB230)
+#define UEFI_DXE_SMMCONTROL_SMMCONTROL_FILECODE (0xB240)
+#define UEFI_LIBRARY_DECCAN_FCHSMMLIB_FCHDXECOMMON_FILECODE (0xB250)
+#define UEFI_LIBRARY_DECCAN_FCHSMMLIB_FCHSMMLIB_FILECODE (0xB251)
+#define UEFI_LIBRARY_DECCAN_FCHDXELIB_FCHDXELIB_FILECODE (0xB252)
+#define UEFI_PEI_AMDSBPEI_AMDSBPEI_FILECODE (0xB260)
+#define UEFI_PEI_AMDSBPEI_SBRESET_FILECODE (0xB261)
+#define UEFI_PEI_AMDSBPEI_SBSTALL_FILECODE (0xB262)
+#define UEFI_PEI_SMBUS_SMBUS_FILECODE (0xB270)
+#define UEFI_SMM_AMDSBSMM_AMDSBSMM_FILECODE (0xB280)
+#define UEFI_SMM_AMDSBSMM_GECSMI_FILECODE (0xB281)
+#define UEFI_SMM_AMDSBSMM_GPESMI_FILECODE (0xB282)
+#define UEFI_SMM_AMDSBSMM_IOTRAPSMI_FILECODE (0xB283)
+#define UEFI_SMM_AMDSBSMM_MISCSMI_FILECODE (0xB284)
+#define UEFI_SMM_AMDSBSMM_PERIODICTIMERSMI_FILECODE (0xB285)
+#define UEFI_SMM_AMDSBSMM_POWERBUTTONSMI_FILECODE (0xB286)
+#define UEFI_SMM_AMDSBSMM_SWSMI_FILECODE (0xB287)
+#define UEFI_SMM_AMDSBSMM_SXSMI_FILECODE (0xB288)
+#define UEFI_DXE_SMBUS_SMBUSLIGHT_FILECODE (0xB2A0)
+#define UEFI_SMM_AMDSBSMMDISPATCHER_AMDSBSMMDISPATCHER_FILECODE (0xB290)
+#define UEFI_SMM_AMDSBSMMGECROMDISPATCHER_AMDSBSMMGECROMDISPATCHER_FILECODE (0xB291)
+#define UEFI_SMM_AMDSBSMMGPEDISPATCHER_AMDSBSMMGPEDISPATCHER_FILECODE (0xB292)
+#define UEFI_SMM_AMDSBSMMIOTRAPDISPATCHER_AMDSBSMMIOTRAPDISPATCHER_FILECODE (0xB293)
+#define UEFI_SMM_AMDSBSMMMISCDISPATCHER_AMDSBSMMMISCDISPATCHER_FILECODE (0xB294)
+#define UEFI_SMM_AMDSBSMMPERIODICALDISPATCHER_AMDSBSMMPERIODICALDISPATCHER_FILECODE (0xB295)
+#define UEFI_SMM_AMDSBSMMPWRBTNDISPATCHER_AMDSBSMMPWRBTNDISPATCHER_FILECODE (0xB296)
+#define UEFI_SMM_AMDSBSMMSWDISPATCHER_AMDSBSMMSWDISPATCHER_FILECODE (0xB297)
+#define UEFI_SMM_AMDSBSMMSXDISPATCHER_AMDSBSMMSXDISPATCHER_FILECODE (0xB298)
+#define UEFI_SMM_AMDSBSMMUSBDISPATCHER_AMDSBSMMUSBDISPATCHER_FILECODE (0xB299)
+
+#define LIB_AMDLIB_FILECODE (0xC001)
+
+#define LEGACY_PROC_AGESACALLOUTS_FILECODE (0xC010)
+#define LEGACY_PROC_HOBTRANSFER_FILECODE (0xC011)
+#define LEGACY_PROC_DISPATCHER_FILECODE (0xC012)
+
+#define UEFI_DXE_AMDAGESADXEDRIVER_AMDAGESADXEDRIVER_FILECODE (0xC120)
+
+#define UEFI_PEI_AMDINITPOSTPEIM_AMDINITPOSTPEIM_FILECODE (0xC140)
+#define UEFI_PEI_AMDPROCESSORINITPEIM_AMDPROCESSORINITPEIM_FILECODE (0xC141)
+#define UEFI_PEI_AMDRESETMANAGER_AMDRESETMANAGER_FILECODE (0xC142)
+#define UEFI_PROC_HOBTRANSFERUEFI_FILECODE (0xC162)
+
+#define PROC_COMMON_AMDINITEARLY_FILECODE (0xC020)
+#define PROC_COMMON_AMDINITENV_FILECODE (0xC021)
+#define PROC_COMMON_AMDINITLATE_FILECODE (0xC022)
+#define PROC_COMMON_AMDINITMID_FILECODE (0xC023)
+#define PROC_COMMON_AMDINITPOST_FILECODE (0xC024)
+#define PROC_COMMON_AMDINITRECOVERY_FILECODE (0xC025)
+#define PROC_COMMON_AMDINITRESET_FILECODE (0xC026)
+#define PROC_COMMON_AMDINITRESUME_FILECODE (0xC027)
+#define PROC_COMMON_AMDS3LATERESTORE_FILECODE (0xC028)
+#define PROC_COMMON_AMDS3SAVE_FILECODE (0xC029)
+#define PROC_COMMON_AMDLATERUNAPTASK_FILECODE (0xC02A)
+
+#define PROC_COMMON_COMMONRETURNS_FILECODE (0xC0C0)
+#define PROC_COMMON_CREATESTRUCT_FILECODE (0xC0D0)
+#define PROC_COMMON_COMMONINITS_FILECODE (0xC0F0)
+#define PROC_COMMON_S3RESTORESTATE_FILECODE (0xC0F8)
+#define PROC_COMMON_S3SAVESTATE_FILECODE (0xC0F9)
+
+#define PROC_CPU_CPUAPICUTILITIES_FILECODE (0xC401)
+#define PROC_CPU_CPUBRANDID_FILECODE (0xC402)
+#define PROC_CPU_TABLE_FILECODE (0xC403)
+#define PROC_CPU_CPUEARLYINIT_FILECODE (0xC405)
+#define PROC_CPU_CPUEVENTLOG_FILECODE (0xC406)
+#define PROC_CPU_CPUFAMILYTRANSLATION_FILECODE (0xC407)
+#define PROC_CPU_CPUGENERALSERVICES_FILECODE (0xC408)
+#define PROC_CPU_CPUINITEARLYTABLE_FILECODE (0xC409)
+#define PROC_CPU_CPULATEINIT_FILECODE (0xC40A)
+#define PROC_CPU_CPUMICROCODEPATCH_FILECODE (0xC40B)
+#define PROC_CPU_CPUWARMRESET_FILECODE (0xC40C)
+#define PROC_CPU_HEAPMANAGER_FILECODE (0xC40D)
+#define PROC_CPU_CPUBIST_FILECODE (0xC40E)
+
+#define PROC_CPU_CPUPOSTINIT_FILECODE (0xC420)
+#define PROC_CPU_CPUPOWERMGMT_FILECODE (0xC430)
+#define PROC_CPU_CPUPOWERMGMTMULTISOCKET_FILECODE (0xC431)
+#define PROC_CPU_CPUPOWERMGMTSINGLESOCKET_FILECODE (0xC432)
+#define PROC_CPU_S3_FILECODE (0xC460)
+
+// Family 10h
+#define PROC_CPU_FAMILY_0X10_CPUCOMMONF10UTILITIES_FILECODE (0xC801)
+#define PROC_CPU_FAMILY_0X10_CPUF10BRANDID_FILECODE (0xC802)
+#define PROC_CPU_FAMILY_0X10_CPUF10CACHEDEFAULTS_FILECODE (0xC803)
+#define PROC_CPU_FAMILY_0X10_CPUF10CACHEFLUSHONHALT_FILECODE (0xC804)
+#define PROC_CPU_FAMILY_0X10_CPUF10DMI_FILECODE (0xC805)
+#define PROC_CPU_FAMILY_0X10_CPUF10EARLYINIT_FILECODE (0xC806)
+#define PROC_CPU_FAMILY_0X10_CPUF10FEATURELEVELING_FILECODE (0xC807)
+#define PROC_CPU_FAMILY_0X10_CPUF10HTPHYTABLES_FILECODE (0xC808)
+#define PROC_CPU_FAMILY_0X10_CPUF10MSRTABLES_FILECODE (0xC809)
+#define PROC_CPU_FAMILY_0X10_CPUF10PCITABLES_FILECODE (0xC80A)
+#define PROC_CPU_FAMILY_0X10_CPUF10POWERCHECK_FILECODE (0xC80B)
+#define PROC_CPU_FAMILY_0X10_CPUF10POWERMGMTSYSTEMTABLES_FILECODE (0xC80C)
+#define PROC_CPU_FAMILY_0X10_CPUF10POWERPLANE_FILECODE (0xC80D)
+#define PROC_CPU_FAMILY_0X10_CPUF10SOFTWARETHERMAL_FILECODE (0xC80E)
+#define PROC_CPU_FAMILY_0X10_CPUF10UTILITIES_FILECODE (0xC80F)
+#define PROC_CPU_FAMILY_0X10_CPUF10WHEAINITDATATABLES_FILECODE (0xC810)
+#define PROC_CPU_FAMILY_0X10_CPUF10PSTATE_FILECODE (0xC811)
+#define PROC_CPU_FAMILY_0X10_CPUF10CPB_FILECODE (0xC812)
+#define PROC_CPU_FAMILY_0X10_CPUF10WORKAROUNDSTABLE_FILECODE (0xC813)
+#define PROC_CPU_FAMILY_0X10_F10PMNBCOFVIDINIT_FILECODE (0xC820)
+#define PROC_CPU_FAMILY_0X10_F10SINGLELINKPCITABLES_FILECODE (0xC821)
+#define PROC_CPU_FAMILY_0X10_F10MULTILINKPCITABLES_FILECODE (0xC822)
+#define PROC_CPU_FAMILY_0X10_F10PMNBPSTATEINIT_FILECODE (0xC823)
+#define PROC_CPU_FAMILY_0X10_F10PMASYMBOOSTINIT_FILECODE (0xC824)
+#define PROC_CPU_FAMILY_0X10_F10INITEARLYTABLE_FILECODE (0xC825)
+#define PROC_CPU_FAMILY_0X10_F10PMDUALPLANEONLYSUPPORT_FILECODE (0xC826)
+#define PROC_CPU_FAMILY_0X10_F10IOCSTATE_FILECODE (0xC827)
+#define PROC_CPU_FAMILY_0X10_REVC_F10REVCUTILITIES_FILECODE (0xC830)
+#define PROC_CPU_FAMILY_0X10_REVC_F10REVCHWC1E_FILECODE (0xC831)
+#define PROC_CPU_FAMILY_0X10_REVC_F10REVCSWC1E_FILECODE (0xC832)
+#define PROC_CPU_FAMILY_0X10_REVC_F10REVCPCITABLES_FILECODE (0xC833)
+#define PROC_CPU_FAMILY_0X10_REVC_F10REVCMSRTABLES_FILECODE (0xC834)
+#define PROC_CPU_FAMILY_0X10_REVC_F10REVCHTPHYTABLES_FILECODE (0xC835)
+#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLHTPHYTABLES_FILECODE (0xC836)
+#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLLOGICALIDTABLES_FILECODE (0xC837)
+#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMICROCODEPATCHTABLES_FILECODE (0xC838)
+#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMSRTABLES_FILECODE (0xC839)
+#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLEQUIVALENCETABLE_FILECODE (0xC83A)
+#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLPCITABLES_FILECODE (0xC83B)
+#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLCACHEFLUSHONHALT_FILECODE (0xC83C)
+#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAHTPHYTABLES_FILECODE (0xC83D)
+#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DALOGICALIDTABLES_FILECODE (0xC83E)
+#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMICROCODEPATCHTABLES_FILECODE (0xC83F)
+#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMSRTABLES_FILECODE (0xC840)
+#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAEQUIVALENCETABLE_FILECODE (0xC841)
+#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAPCITABLES_FILECODE (0xC842)
+#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DACACHEFLUSHONHALT_FILECODE (0xC843)
+#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBHTPHYTABLES_FILECODE (0xC844)
+#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBLOGICALIDTABLES_FILECODE (0xC845)
+#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMICROCODEPATCHTABLES_FILECODE (0xC846)
+#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMSRTABLES_FILECODE (0xC847)
+#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBEQUIVALENCETABLE_FILECODE (0xC848)
+#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBPCITABLES_FILECODE (0xC849)
+#define PROC_CPU_FAMILY_0X10_REVD_F10REVDUTILITIES_FILECODE (0xC850)
+#define PROC_CPU_FAMILY_0X10_REVD_F10REVDMSGBASEDC1E_FILECODE (0xC851)
+#define PROC_CPU_FAMILY_0X10_REVD_F10REVDHTASSIST_FILECODE (0xC852)
+#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYHTPHYTABLES_FILECODE (0xC853)
+#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYINITEARLYTABLE_FILECODE (0xC854)
+#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYLOGICALIDTABLES_FILECODE (0xC855)
+#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMICROCODEPATCHTABLES_FILECODE (0xC856)
+#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMSRTABLES_FILECODE (0xC857)
+#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYEQUIVALENCETABLE_FILECODE (0xC858)
+#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYPCITABLES_FILECODE (0xC859)
+#define PROC_CPU_FAMILY_0X10_REVE_F10REVEUTILITIES_FILECODE (0xC860)
+#define PROC_CPU_FAMILY_0X10_REVE_F10REVEMSRTABLES_FILECODE (0xC861)
+#define PROC_CPU_FAMILY_0X10_REVE_F10REVEPCITABLES_FILECODE (0xC862)
+#define PROC_CPU_FAMILY_0X10_REVE_F10REVEHTPHYTABLES_FILECODE (0xC863)
+#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHEQUIVALENCETABLE_FILECODE (0xC864)
+#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHHTPHYTABLES_FILECODE (0xC865)
+#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHLOGICALIDTABLES_FILECODE (0xC866)
+#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHMICROCODEPATCHTABLES_FILECODE (0xC867)
+
+// Family 12h
+#define PROC_CPU_FAMILY_0X12_CPUCOMMONF12UTILITIES_FILECODE (0xC901)
+#define PROC_CPU_FAMILY_0X12_CPUF12BRANDID_FILECODE (0xC902)
+#define PROC_CPU_FAMILY_0X12_CPUF12CACHEDEFAULTS_FILECODE (0xC903)
+#define PROC_CPU_FAMILY_0X12_CPUF12DMI_FILECODE (0xC904)
+#define PROC_CPU_FAMILY_0X12_CPUF12MSRTABLES_FILECODE (0xC905)
+#define PROC_CPU_FAMILY_0X12_CPUF12EARLYNBPSTATEINIT_FILECODE (0xC906)
+#define PROC_CPU_FAMILY_0X12_CPUF12PCITABLES_FILECODE (0xC907)
+#define PROC_CPU_FAMILY_0X12_CPUF12POWERCHECK_FILECODE (0xC908)
+#define PROC_CPU_FAMILY_0X12_CPUF12POWERMGMTSYSTEMTABLES_FILECODE (0xC909)
+#define PROC_CPU_FAMILY_0X12_CPUF12POWERPLANE_FILECODE (0xC90A)
+#define PROC_CPU_FAMILY_0X12_CPUF12SOFTWARETHERMAL_FILECODE (0xC90B)
+#define PROC_CPU_FAMILY_0X12_CPUF12UTILITIES_FILECODE (0xC90C)
+#define PROC_CPU_FAMILY_0X12_CPUF12WHEAINITDATATABLES_FILECODE (0xC90D)
+#define PROC_CPU_FAMILY_0X12_CPUF12PSTATE_FILECODE (0xC90E)
+#define PROC_CPU_FAMILY_0X12_F12C6STATE_FILECODE (0xC90F)
+#define PROC_CPU_FAMILY_0X12_F12CPB_FILECODE (0xC910)
+#define PROC_CPU_FAMILY_0X12_F12IOCSTATE_FILECODE (0xC911)
+#define PROC_CPU_FAMILY_0X12_LN_F12LNLOGICALIDTABLES_FILECODE (0xC921)
+#define PROC_CPU_FAMILY_0X12_LN_F12LNMICROCODEPATCHTABLES_FILECODE (0xC922)
+#define PROC_CPU_FAMILY_0X12_LN_F12LNEQUIVALENCETABLE_FILECODE (0xC923)
+#define PROC_CPU_FAMILY_0X12_CPUF12PERCOREPCITABLES_FILECODE (0xC924)
+#define PROC_CPU_FAMILY_0X12_LN_F12LNEARLYSAMPLES_FILECODE (0xC925)
+
+// Family 14h
+#define PROC_CPU_FAMILY_0X14_CPUCOMMONF14UTILITIES_FILECODE (0xCA01)
+#define PROC_CPU_FAMILY_0X14_CPUF14BRANDID_FILECODE (0xCA02)
+#define PROC_CPU_FAMILY_0X14_CPUF14CACHEDEFAULTS_FILECODE (0xCA03)
+#define PROC_CPU_FAMILY_0X14_CPUF14DMI_FILECODE (0xCA04)
+#define PROC_CPU_FAMILY_0X14_CPUF14MSRTABLES_FILECODE (0xCA05)
+#define PROC_CPU_FAMILY_0X14_CPUF14PCITABLES_FILECODE (0xCA06)
+#define PROC_CPU_FAMILY_0X14_CPUF14POWERCHECK_FILECODE (0xCA07)
+#define PROC_CPU_FAMILY_0X14_CPUF14POWERMGMTSYSTEMTABLES_FILECODE (0xCA08)
+#define PROC_CPU_FAMILY_0X14_CPUF14POWERPLANE_FILECODE (0xCA09)
+#define PROC_CPU_FAMILY_0X14_CPUF14SOFTWARETHERMAL_FILECODE (0xCA0A)
+#define PROC_CPU_FAMILY_0X14_CPUF14UTILITIES_FILECODE (0xCA0B)
+#define PROC_CPU_FAMILY_0X14_CPUF14WHEAINITDATATABLES_FILECODE (0xCA0C)
+#define PROC_CPU_FAMILY_0X14_CPUF14PSTATE_FILECODE (0xCA0D)
+#define PROC_CPU_FAMILY_0X14_F14C6STATE_FILECODE (0xCA0E)
+#define PROC_CPU_FAMILY_0X14_F14IOCSTATE_FILECODE (0xCA0F)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONLOGICALIDTABLES_FILECODE (0xCA21)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONMICROCODEPATCHTABLES_FILECODE (0xCA22)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONEQUIVALENCETABLE_FILECODE (0xCA23)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONINITEARLYTABLE_FILECODE (0xCA24)
+#define PROC_CPU_FAMILY_0X14_CPUF14PERCOREPCITABLES_FILECODE (0xCA25)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONEARLYSAMPLES_FILECODE (0xCA26)
+
+// Family 15h
+#define PROC_CPU_FAMILY_0X15_CPUCOMMONF15UTILITIES_FILECODE (0xCB01)
+#define PROC_CPU_FAMILY_0X15_CPUF15BRANDID_FILECODE (0xCB02)
+#define PROC_CPU_FAMILY_0X15_CPUF15CACHEDEFAULTS_FILECODE (0xCB03)
+#define PROC_CPU_FAMILY_0X15_CPUF15CACHEFLUSHONHALT_FILECODE (0xCB04)
+#define PROC_CPU_FAMILY_0X15_CPUF15COREAFTERRESET_FILECODE (0xCB05)
+#define PROC_CPU_FAMILY_0X15_CPUF15DMI_FILECODE (0xCB06)
+#define PROC_CPU_FAMILY_0X15_CPUF15FEATURELEVELING_FILECODE (0xCB07)
+#define PROC_CPU_FAMILY_0X15_CPUF15HTPHYTABLES_FILECODE (0xCB08)
+#define PROC_CPU_FAMILY_0X15_CPUF15MSRTABLES_FILECODE (0xCB09)
+#define PROC_CPU_FAMILY_0X15_CPUF15NBAFTERRESET_FILECODE (0xCB0A)
+#define PROC_CPU_FAMILY_0X15_CPUF15PCITABLES_FILECODE (0xCB0B)
+#define PROC_CPU_FAMILY_0X15_CPUF15POWERCHECK_FILECODE (0xCB0C)
+#define PROC_CPU_FAMILY_0X15_CPUF15POWERMGMTSYSTEMTABLES_FILECODE (0xCB0D)
+#define PROC_CPU_FAMILY_0X15_CPUF15POWERPLANE_FILECODE (0xCB0E)
+#define PROC_CPU_FAMILY_0X15_CPUF15SOFTWARETHERMAL_FILECODE (0xCB0F)
+#define PROC_CPU_FAMILY_0X15_CPUF15UTILITIES_FILECODE (0xCB10)
+#define PROC_CPU_FAMILY_0X15_CPUF15WHEAINITDATATABLES_FILECODE (0xCB11)
+#define PROC_CPU_FAMILY_0X15_CPUF15PSTATE_FILECODE (0xCB12)
+#define PROC_CPU_FAMILY_0X15_F15PMNBCOFVIDINIT_FILECODE (0xCB13)
+#define PROC_CPU_FAMILY_0X15_F15SINGLELINKPCITABLES_FILECODE (0xCB14)
+#define PROC_CPU_FAMILY_0X15_F15MULTILINKPCITABLES_FILECODE (0xCB15)
+#define PROC_CPU_FAMILY_0X15_F15C6STATE_FILECODE (0xCB16)
+#define PROC_CPU_FAMILY_0X15_F15CPB_FILECODE (0xCB17)
+#define PROC_CPU_FAMILY_0X15_F15INITEARLYTABLE_FILECODE (0xCB18)
+#define PROC_CPU_FAMILY_0X15_F15LOWPWRPSTATE_FILECODE (0xCB19)
+#define PROC_CPU_FAMILY_0X15_CPUF15WORKAROUNDSTABLE_FILECODE (0xCB1A)
+#define PROC_CPU_FAMILY_0X15_F15IOCSTATE_FILECODE (0xCB1B)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORHTASSIST_FILECODE (0xCB30)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORMSGBASEDC1E_FILECODE (0xCB31)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORLOGICALIDTABLES_FILECODE (0xCB32)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORMICROCODEPATCHTABLES_FILECODE (0xCB33)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORMSRTABLES_FILECODE (0xCB34)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORSHAREDMSRTABLE_FILECODE (0xCB35)
+#define PROC_CPU_FAMILY_0X15_OR_F15OREQUIVALENCETABLE_FILECODE (0xCB36)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORPCITABLES_FILECODE (0xCB37)
+
+
+
+#define PROC_CPU_FEATURE_CPUCACHEFLUSHONHALT_FILECODE (0xDC01)
+#define PROC_CPU_FEATURE_CPUCACHEINIT_FILECODE (0xDC02)
+#define PROC_CPU_FEATURE_CPUDMI_FILECODE (0xDC10)
+#define PROC_CPU_FEATURE_CPUFEATURELEVELING_FILECODE (0xDC20)
+#define PROC_CPU_FEATURE_CPUHTASSIST_FILECODE (0xDC30)
+#define PROC_CPU_FEATURE_CPUPSTATEGATHER_FILECODE (0xDC41)
+#define PROC_CPU_FEATURE_CPUPSTATELEVELING_FILECODE (0xDC42)
+#define PROC_CPU_FEATURE_CPUPSTATETABLES_FILECODE (0xDC43)
+#define PROC_CPU_FEATURE_CPUSLIT_FILECODE (0xDC50)
+#define PROC_CPU_FEATURE_CPUSRAT_FILECODE (0xDC60)
+#define PROC_CPU_FEATURE_CPUWHEA_FILECODE (0xDC70)
+#define PROC_CPU_FEATURE_CPUHWC1E_FILECODE (0xDC80)
+#define PROC_CPU_FEATURE_CPUSWC1E_FILECODE (0xDC81)
+#define PROC_CPU_FEATURE_CPUC6STATE_FILECODE (0xDC82)
+#define PROC_CPU_FEATURE_CPUCPB_FILECODE (0xDC83)
+#define PROC_CPU_FEATURE_CPULOWPWRPSTATE_FILECODE (0xDC84)
+#define PROC_CPU_FEATURE_CPUIOCSTATE_FILECODE (0xDC85)
+#define PROC_CPU_FEATURE_CPUFEATURES_FILECODE (0xDC90)
+#define PROC_CPU_FEATURE_CPUMSGBASEDC1E_FILECODE (0xDCA0)
+#define PROC_CPU_FEATURE_CPUCORELEVELING_FILECODE (0xDCB0)
+#define PROC_CPU_FEATURE_PRESERVEMAILBOX_FILECODE (0xDCC0)
+
+#define PROC_RECOVERY_CPU_CPURECOVERY_FILECODE (0xDE01)
+
+#define PROC_HT_FEATURES_HTFEATSETS_FILECODE (0xE001)
+#define PROC_HT_FEATURES_HTFEATDYNAMICDISCOVERY_FILECODE (0xE002)
+#define PROC_HT_FEATURES_HTFEATGANGING_FILECODE (0xE003)
+#define PROC_HT_FEATURES_HTFEATNONCOHERENT_FILECODE (0xE004)
+#define PROC_HT_FEATURES_HTFEATOPTIMIZATION_FILECODE (0xE005)
+#define PROC_HT_FEATURES_HTFEATROUTING_FILECODE (0xE006)
+#define PROC_HT_FEATURES_HTFEATSUBLINKS_FILECODE (0xE007)
+#define PROC_HT_FEATURES_HTFEATTRAFFICDISTRIBUTION_FILECODE (0xE008)
+#define PROC_HT_FEATURES_HTIDS_FILECODE (0xE009)
+#define PROC_HT_HTFEAT_FILECODE (0xE021)
+#define PROC_HT_HTINTERFACE_FILECODE (0xE022)
+#define PROC_HT_HTINTERFACECOHERENT_FILECODE (0xE023)
+#define PROC_HT_HTINTERFACEGENERAL_FILECODE (0xE024)
+#define PROC_HT_HTINTERFACENONCOHERENT_FILECODE (0xE025)
+#define PROC_HT_HTMAIN_FILECODE (0xE026)
+#define PROC_HT_HTNOTIFY_FILECODE (0xE027)
+#define PROC_HT_HTGRAPH_HTGRAPH_FILECODE (0xE028)
+#define PROC_HT_HTNB_FILECODE (0xE081)
+#define PROC_HT_NBCOMMON_HTNBCOHERENT_FILECODE (0xE082)
+#define PROC_HT_NBCOMMON_HTNBNONCOHERENT_FILECODE (0xE083)
+#define PROC_HT_NBCOMMON_HTNBOPTIMIZATION_FILECODE (0xE084)
+#define PROC_HT_NBCOMMON_HTNBUTILITIES_FILECODE (0xE085)
+#define PROC_HT_FAM10_HTNBFAM10_FILECODE (0xE0C1)
+#define PROC_HT_FAM10_HTNBCOHERENTFAM10_FILECODE (0xE0C2)
+#define PROC_HT_FAM10_HTNBNONCOHERENTFAM10_FILECODE (0xE0C3)
+#define PROC_HT_FAM10_HTNBOPTIMIZATIONFAM10_FILECODE (0xE0C4)
+#define PROC_HT_FAM10_HTNBSYSTEMFAM10_FILECODE (0xE0C5)
+#define PROC_HT_FAM10_HTNBUTILITIESFAM10_FILECODE (0xE0C6)
+#define PROC_HT_FAM12_HTNBFAM12_FILECODE (0xE101)
+#define PROC_HT_FAM12_HTNBUTILITIESFAM12_FILECODE (0xE102)
+#define PROC_HT_FAM14_HTNBFAM14_FILECODE (0xE141)
+#define PROC_HT_FAM14_HTNBUTILITIESFAM14_FILECODE (0xE142)
+#define PROC_HT_FAM15_HTNBFAM15_FILECODE (0xE181)
+#define PROC_HT_FAM15_HTNBCOHERENTFAM15_FILECODE (0xE182)
+#define PROC_HT_FAM15_HTNBNONCOHERENTFAM15_FILECODE (0xE183)
+#define PROC_HT_FAM15_HTNBOPTIMIZATIONFAM15_FILECODE (0xE184)
+#define PROC_HT_FAM15_HTNBSYSTEMFAM15_FILECODE (0xE185)
+#define PROC_HT_FAM15_HTNBUTILITIESFAM15_FILECODE (0xE186)
+
+#define PROC_RECOVERY_HT_HTINITRECOVERY_FILECODE (0xE302)
+#define PROC_RECOVERY_HT_HTINITRESET_FILECODE (0xE301)
+
+#define PROC_IDS_CONTROL_IDSCTRL_FILECODE (0xE801)
+#define PROC_IDS_CONTROL_IDSLIB_FILECODE (0xE802)
+#define PROC_IDS_DEBUG_IDSDEBUG_FILECODE (0xE803)
+#define PROC_IDS_PERF_IDSPERF_FILECODE (0xE804)
+#define PROC_IDS_FAMILY_0X10_IDSF10ALLSERVICE_FILECODE (0xE805)
+#define PROC_IDS_FAMILY_0X10_BL_IDSF10BLSERVICE_FILECODE (0xE806)
+#define PROC_IDS_FAMILY_0X10_DA_IDSF10DASERVICE_FILECODE (0xE807)
+#define PROC_IDS_FAMILY_0X10_HY_IDSF10HYSERVICE_FILECODE (0xE808)
+#define PROC_IDS_FAMILY_0X10_RB_IDSF10RBSERVICE_FILECODE (0xE809)
+#define PROC_IDS_FAMILY_0X12_IDSF12ALLSERVICE_FILECODE (0xE80A)
+#define PROC_IDS_FAMILY_0X14_IDSF14ALLSERVICE_FILECODE (0xE80B)
+#define PROC_IDS_FAMILY_0X15_IDSF15ALLSERVICE_FILECODE (0xE80C)
+
+#define PROC_IDS_DEBUG_IDSIDTTABLE_FILECODE (0xE80D)
+#define PROC_IDS_CONTROL_IDSNVTOCMOS_FILECODE (0xE80E)
+
+///0xE820 ~ 0xE840 is reserved for ids extend module
+
+#define PROC_MEM_ARDK_MA_FILECODE (0xF001)
+#define PROC_MEM_ARDK_DR_MARDR2_FILECODE (0xF002)
+#define PROC_MEM_ARDK_DR_MARDR3_FILECODE (0xF003)
+#define PROC_MEM_ARDK_HY_MARHY3_FILECODE (0xF004)
+#define PROC_MEM_ARDK_LN_MASLN3_FILECODE (0xF005)
+#define PROC_MEM_ARDK_DR_MAUDR3_FILECODE (0xF006)
+#define PROC_MEM_ARDK_HY_MAUHY3_FILECODE (0xF007)
+#define PROC_MEM_ARDK_LN_MAULN3_FILECODE (0xF008)
+#define PROC_MEM_ARDK_DA_MAUDA3_FILECODE (0xF009)
+#define PROC_MEM_ARDK_DA_MASDA2_FILECODE (0xF00A)
+#define PROC_MEM_ARDK_DA_MASDA3_FILECODE (0xF00B)
+#define PROC_MEM_ARDK_NI_MASNI3_FILECODE (0xF00C)
+#define PROC_MEM_ARDK_C32_MARC32_3_FILECODE (0xF00D)
+#define PROC_MEM_ARDK_C32_MAUC32_3_FILECODE (0xF00E)
+#define PROC_MEM_ARDK_NI_MAUNI3_FILECODE (0xF00F)
+#define PROC_MEM_ARDK_ON_MASON3_FILECODE (0xF010)
+#define PROC_MEM_ARDK_ON_MAUON3_FILECODE (0xF011)
+#define PROC_MEM_ARDK_PH_MASPH3_FILECODE (0xF012)
+#define PROC_MEM_ARDK_PH_MAUPH3_FILECODE (0xF013)
+#define PROC_MEM_ARDK_OR_MAROR3_FILECODE (0xF014)
+#define PROC_MEM_ARDK_OR_MAUOR3_FILECODE (0xF017)
+#define PROC_MEM_ARDK_RB_MASRB3_FILECODE (0xF018)
+#define PROC_MEM_ARDK_RB_MAURB3_FILECODE (0xF019)
+
+#define PROC_MEM_FEAT_CHINTLV_MFCHI_FILECODE (0xF081)
+#define PROC_MEM_FEAT_CSINTLV_MFCSI_FILECODE (0xF082)
+#define PROC_MEM_FEAT_ECC_MFECC_FILECODE (0xF083)
+#define PROC_MEM_FEAT_ECC_MFEMP_FILECODE (0xF085)
+#define PROC_MEM_FEAT_EXCLUDIMM_MFDIMMEXCLUD_FILECODE (0xF086)
+#define PROC_MEM_FEAT_IDENDIMM_MFIDENDIMM_FILECODE (0xF088)
+#define PROC_MEM_FEAT_INTLVRN_MFINTLVRN_FILECODE (0xF089)
+#define PROC_MEM_FEAT_LVDDR3_MFLVDDR3_FILECODE (0xF08A)
+#define PROC_MEM_FEAT_MEMCLR_MFMEMCLR_FILECODE (0xF08B)
+#define PROC_MEM_FEAT_NDINTLV_MFNDI_FILECODE (0xF08C)
+#define PROC_MEM_FEAT_ODTHERMAL_MFODTHERMAL_FILECODE (0xF08D)
+#define PROC_MEM_FEAT_OLSPARE_MFSPR_FILECODE (0xF08E)
+#define PROC_MEM_FEAT_PARTRN_MFPARALLELTRAINING_FILECODE (0xF08F)
+#define PROC_MEM_FEAT_PARTRN_MFSTANDARDTRAINING_FILECODE (0xF091)
+#define PROC_MEM_FEAT_S3_MFS3_FILECODE (0xF092)
+#define PROC_MEM_FEAT_TABLE_MFTDS_FILECODE (0xF093)
+
+#define PROC_MEM_MAIN_MDEF_FILECODE (0xF101)
+#define PROC_MEM_MAIN_MINIT_FILECODE (0xF102)
+#define PROC_MEM_MAIN_MM_FILECODE (0xF103)
+#define PROC_MEM_FEAT_DMI_MFDMI_FILECODE (0xF104)
+#define PROC_MEM_MAIN_MMECC_FILECODE (0xF105)
+#define PROC_MEM_MAIN_MMEXCLUDEDIMM_FILECODE (0xF106)
+#define PROC_MEM_MAIN_DR_MMFLOWDR_FILECODE (0xF107)
+#define PROC_MEM_MAIN_HY_MMFLOWHY_FILECODE (0xF108)
+#define PROC_MEM_MAIN_LN_MMFLOWLN_FILECODE (0xF109)
+#define PROC_MEM_MAIN_ON_MMFLOWON_FILECODE (0xF10A)
+#define PROC_MEM_MAIN_MMNODEINTERLEAVE_FILECODE (0xF10B)
+#define PROC_MEM_MAIN_MMONLINESPARE_FILECODE (0xF10C)
+#define PROC_MEM_MAIN_MMPARALLELTRAINING_FILECODE (0xF10D)
+#define PROC_MEM_MAIN_MMSTANDARDTRAINING_FILECODE (0xF10E)
+#define PROC_MEM_MAIN_MUC_FILECODE (0xF10F)
+#define PROC_MEM_MAIN_MMMEMCLR_FILECODE (0xF110)
+#define PROC_MEM_MAIN_DA_MMFLOWDA_FILECODE (0xF111)
+#define PROC_MEM_MAIN_MMFLOW_FILECODE (0xF112)
+#define PROC_MEM_MAIN_MERRHDL_FILECODE (0xF113)
+#define PROC_MEM_MAIN_C32_MMFLOWC32_FILECODE (0xF114)
+#define PROC_MEM_MAIN_MMLVDDR3_FILECODE (0xF115)
+#define PROC_MEM_MAIN_MMUMAALLOC_FILECODE (0xF116)
+#define PROC_MEM_MAIN_MMMEMRESTORE_FILECODE (0xF117)
+#define PROC_MEM_MAIN_MMCONDITIONALPSO_FILECODE (0xF118)
+#define PROC_MEM_MAIN_OR_MMFLOWOR_FILECODE (0xF119)
+#define PROC_MEM_MAIN_RB_MMFLOWRB_FILECODE (0xF11A)
+#define PROC_MEM_MAIN_PH_MMFLOWPH_FILECODE (0xF11B)
+
+#define PROC_MEM_NB_DR_MNDR_FILECODE (0XF213)
+#define PROC_MEM_NB_DR_MNFLOWDR_FILECODE (0XF214)
+#define PROC_MEM_NB_DR_MNIDENDIMMDR_FILECODE (0XF216)
+#define PROC_MEM_NB_DR_MNMCTDR_FILECODE (0XF217)
+#define PROC_MEM_NB_DR_MNDCTDR_FILECODE (0XF218)
+#define PROC_MEM_NB_DR_MNOTDR_FILECODE (0XF219)
+#define PROC_MEM_NB_DR_MNPARTRAINDR_FILECODE (0XF21A)
+#define PROC_MEM_NB_DR_MNPROTODR_FILECODE (0XF21C)
+#define PROC_MEM_NB_DR_MNS3DR_FILECODE (0XF21D)
+#define PROC_MEM_NB_DR_MNREGDR_FILECODE (0XF21E)
+#define PROC_MEM_NB_RB_MNRB_FILECODE (0XF220)
+#define PROC_MEM_NB_RB_MNFLOWRB_FILECODE (0XF221)
+#define PROC_MEM_NB_RB_MNS3RB_FILECODE (0XF222)
+#define PROC_MEM_NB_RB_MNIDENDIMMRB_FILECODE (0XF223)
+#define PROC_MEM_NB_HY_MNFLOWHY_FILECODE (0XF233)
+#define PROC_MEM_NB_HY_MNHY_FILECODE (0XF235)
+#define PROC_MEM_NB_HY_MNIDENDIMMHY_FILECODE (0XF236)
+#define PROC_MEM_NB_HY_MNMCTHY_FILECODE (0XF237)
+#define PROC_MEM_NB_HY_MNDCTHY_FILECODE (0XF238)
+#define PROC_MEM_NB_HY_MNOTHY_FILECODE (0XF239)
+#define PROC_MEM_NB_HY_MNPARTRAINHY_FILECODE (0XF23A)
+#define PROC_MEM_NB_HY_MNPHYHY_FILECODE (0XF23B)
+#define PROC_MEM_NB_HY_MNPROTOHY_FILECODE (0XF23C)
+#define PROC_MEM_NB_HY_MNS3HY_FILECODE (0XF23D)
+#define PROC_MEM_NB_HY_MNREGHY_FILECODE (0XF23E)
+#define PROC_MEM_NB_ON_MNON_FILECODE (0xF240)
+#define PROC_MEM_NB_ON_MNREGON_FILECODE (0xF241)
+#define PROC_MEM_NB_ON_MNDCTON_FILECODE (0xF242)
+#define PROC_MEM_NB_ON_MNIDENDIMMON_FILECODE (0xF244)
+#define PROC_MEM_NB_ON_MNMCTON_FILECODE (0xF245)
+#define PROC_MEM_NB_ON_MNOTON_FILECODE (0xF246)
+#define PROC_MEM_NB_ON_MNPHYON_FILECODE (0xF247)
+#define PROC_MEM_NB_ON_MNS3ON_FILECODE (0xF248)
+#define PROC_MEM_NB_ON_MNFLOWON_FILECODE (0xF249)
+#define PROC_MEM_NB_ON_MNPROTOON_FILECODE (0xF24A)
+#define PROC_MEM_NB_LN_MNDCTLN_FILECODE (0XF252)
+#define PROC_MEM_NB_LN_MNFLOWLN_FILECODE (0XF253)
+#define PROC_MEM_NB_LN_MNIDENDIMMLN_FILECODE (0XF254)
+#define PROC_MEM_NB_LN_MNMCTLN_FILECODE (0XF255)
+#define PROC_MEM_NB_LN_MNOTLN_FILECODE (0XF256)
+#define PROC_MEM_NB_LN_MNPHYLN_FILECODE (0XF257)
+#define PROC_MEM_NB_LN_MNPROTOLN_FILECODE (0XF258)
+#define PROC_MEM_NB_LN_MNLN_FILECODE (0XF259)
+#define PROC_MEM_NB_LN_MNS3LN_FILECODE (0XF25A)
+#define PROC_MEM_NB_LN_MNREGLN_FILECODE (0XF25B)
+#define PROC_MEM_NB_DA_MNDA_FILECODE (0XF260)
+#define PROC_MEM_NB_DA_MNFLOWDA_FILECODE (0XF261)
+#define PROC_MEM_NB_DA_MNIDENDIMMDA_FILECODE (0XF263)
+#define PROC_MEM_NB_DA_MNMCTDA_FILECODE (0XF264)
+#define PROC_MEM_NB_DA_MNDCTDA_FILECODE (0XF265)
+#define PROC_MEM_NB_DA_MNOTDA_FILECODE (0XF266)
+#define PROC_MEM_NB_DA_MNPARTRAINDA_FILECODE (0XF267)
+#define PROC_MEM_NB_DA_MNPROTODA_FILECODE (0XF269)
+#define PROC_MEM_NB_DA_MNS3DA_FILECODE (0XF26A)
+#define PROC_MEM_NB_DA_MNREGDA_FILECODE (0XF26B)
+#define PROC_MEM_NB_C32_MNC32_FILECODE (0XF26C)
+#define PROC_MEM_NB_C32_MNDCTC32_FILECODE (0XF26D)
+#define PROC_MEM_NB_C32_MNFLOWC32_FILECODE (0XF26E)
+#define PROC_MEM_NB_C32_MNIDENDIMMC32_FILECODE (0XF26F)
+#define PROC_MEM_NB_C32_MNMCTC32_FILECODE (0XF270)
+#define PROC_MEM_NB_C32_MNOTC32_FILECODE (0XF271)
+#define PROC_MEM_NB_C32_MNPARTRAINC32_FILECODE (0XF272)
+#define PROC_MEM_NB_C32_MNPHYC32_FILECODE (0XF273)
+#define PROC_MEM_NB_C32_MNPROTOC32_FILECODE (0XF274)
+#define PROC_MEM_NB_C32_MNS3C32_FILECODE (0XF275)
+#define PROC_MEM_NB_C32_MNREGC32_FILECODE (0XF277)
+#define PROC_MEM_NB_MN_FILECODE (0XF27C)
+#define PROC_MEM_NB_MNDCT_FILECODE (0XF27D)
+#define PROC_MEM_NB_MNPHY_FILECODE (0XF27E)
+#define PROC_MEM_NB_MNMCT_FILECODE (0XF27F)
+#define PROC_MEM_NB_MNS3_FILECODE (0XF280)
+#define PROC_MEM_NB_MNFLOW_FILECODE (0XF281)
+#define PROC_MEM_NB_MNFEAT_FILECODE (0XF282)
+#define PROC_MEM_NB_MNTRAIN2_FILECODE (0XF283)
+#define PROC_MEM_NB_MNTRAIN3_FILECODE (0XF284)
+#define PROC_MEM_NB_MNREG_FILECODE (0XF285)
+#define PROC_MEM_NB_NI_MNNI_FILECODE (0XF286)
+#define PROC_MEM_NB_NI_MNS3NI_FILECODE (0XF287)
+#define PROC_MEM_NB_NI_MNFLOWNI_FILECODE (0XF288)
+#define PROC_MEM_NB_PH_MNFLOWPH_FILECODE (0XF289)
+#define PROC_MEM_NB_PH_MNPH_FILECODE (0XF28A)
+#define PROC_MEM_NB_PH_MNS3PH_FILECODE (0XF28B)
+#define PROC_MEM_NB_PH_MNIDENDIMMPH_FILECODE (0XF28C)
+#define PROC_MEM_NB_OR_MNFLOWOR_FILECODE (0XF290)
+#define PROC_MEM_NB_OR_MNOR_FILECODE (0XF291)
+#define PROC_MEM_NB_OR_MNIDENDIMMOR_FILECODE (0XF292)
+#define PROC_MEM_NB_OR_MNMCTOR_FILECODE (0XF293)
+#define PROC_MEM_NB_OR_MNDCTOR_FILECODE (0XF294)
+#define PROC_MEM_NB_OR_MNOTOR_FILECODE (0XF295)
+#define PROC_MEM_NB_OR_MNPARTRAINOR_FILECODE (0XF296)
+#define PROC_MEM_NB_OR_MNPHYOR_FILECODE (0XF297)
+#define PROC_MEM_NB_OR_MNPROTOOR_FILECODE (0XF298)
+#define PROC_MEM_NB_OR_MNS3OR_FILECODE (0XF299)
+#define PROC_MEM_NB_OR_MNREGOR_FILECODE (0XF29A)
+
+#define PROC_MEM_PS_MP_FILECODE (0XF401)
+#define PROC_MEM_PS_DR_MPRDR3_FILECODE (0XF402)
+#define PROC_MEM_PS_HY_MPRHY3_FILECODE (0XF403)
+#define PROC_MEM_PS_LN_MPRLN3_FILECODE (0XF404)
+#define PROC_MEM_PS_DR_MPSDR3_FILECODE (0XF405)
+#define PROC_MEM_PS_HY_MPSHY3_FILECODE (0XF406)
+#define PROC_MEM_PS_LN_MPSLN3_FILECODE (0XF407)
+#define PROC_MEM_PS_DR_MPUDR3_FILECODE (0XF408)
+#define PROC_MEM_PS_HY_MPUHY3_FILECODE (0XF409)
+#define PROC_MEM_PS_LN_MPULN3_FILECODE (0XF40A)
+#define PROC_MEM_PS_DA_MPUDA3_FILECODE (0XF40B)
+#define PROC_MEM_PS_DA_MPSDA2_FILECODE (0XF40C)
+#define PROC_MEM_PS_DA_MPSDA3_FILECODE (0XF40D)
+#define PROC_MEM_PS_DR_MPRDR2_FILECODE (0XF40E)
+#define PROC_MEM_PS_DR_MPUDR2_FILECODE (0XF40F)
+#define PROC_MEM_PS_C32_MPRC32_3_FILECODE (0XF410)
+#define PROC_MEM_PS_C32_MPUC32_3_FILECODE (0XF411)
+#define PROC_MEM_PS_NI_MPSNI3_FILECODE (0XF412)
+#define PROC_MEM_PS_NI_MPUNI3_FILECODE (0XF413)
+#define PROC_MEM_PS_ON_MPSON3_FILECODE (0XF414)
+#define PROC_MEM_PS_ON_MPUON3_FILECODE (0XF415)
+#define PROC_MEM_PS_PH_MPSPH3_FILECODE (0XF416)
+#define PROC_MEM_PS_PH_MPUPH3_FILECODE (0XF417)
+#define PROC_MEM_PS_RB_MPSRB3_FILECODE (0XF418)
+#define PROC_MEM_PS_RB_MPURB3_FILECODE (0XF419)
+#define PROC_MEM_PS_OR_AM3_MPUORA3_FILECODE (0XF41A)
+#define PROC_MEM_PS_OR_AM3_MPSORA3_FILECODE (0XF41B)
+#define PROC_MEM_PS_OR_C32_MPRORC3_FILECODE (0XF41C)
+#define PROC_MEM_PS_OR_C32_MPUORC3_FILECODE (0XF41D)
+#define PROC_MEM_PS_OR_C32_MPLORC3_FILECODE (0XF41E)
+#define PROC_MEM_PS_OR_G34_MPRORG3_FILECODE (0XF41F)
+#define PROC_MEM_PS_OR_G34_MPUORG3_FILECODE (0XF420)
+#define PROC_MEM_PS_OR_G34_MPLORG3_FILECODE (0XF421)
+#define PROC_MEM_PS_MPRTT_FILECODE (0XF422)
+#define PROC_MEM_PS_MPMAXFREQ_FILECODE (0XF423)
+#define PROC_MEM_PS_MPODTPAT_FILECODE (0XF424)
+#define PROC_MEM_PS_MPSAO_FILECODE (0XF425)
+#define PROC_MEM_PS_MPMR0_FILECODE (0XF426)
+#define PROC_MEM_PS_MPRC2IBT_FILECODE (0XF427)
+#define PROC_MEM_PS_MPRC10OPSPD_FILECODE (0XF428)
+#define PROC_MEM_PS_MPLRIBT_FILECODE (0XF429)
+#define PROC_MEM_PS_MPLRNPR_FILECODE (0XF42A)
+#define PROC_MEM_PS_MPLRNLR_FILECODE (0XF42B)
+#define PROC_MEM_PS_OR_MPOR3_FILECODE (0XF42C)
+
+#define PROC_MEM_TECH_MT_FILECODE (0XF501)
+#define PROC_MEM_TECH_MTHDI_FILECODE (0XF502)
+#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0XF504)
+#define PROC_MEM_TECH_MTTECC_FILECODE (0XF505)
+#define PROC_MEM_TECH_MTTHRC_FILECODE (0XF506)
+#define PROC_MEM_TECH_MTTML_FILECODE (0XF507)
+#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0XF509)
+#define PROC_MEM_TECH_MTTSRC_FILECODE (0XF50B)
+#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0XF50C)
+#define PROC_MEM_TECH_DDR2_MT2_FILECODE (0XF541)
+#define PROC_MEM_TECH_DDR2_MTOT2_FILECODE (0XF543)
+#define PROC_MEM_TECH_DDR2_MTSPD2_FILECODE (0XF544)
+#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0XF581)
+#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0XF583)
+#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0XF584)
+#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0XF585)
+#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0XF586)
+#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0XF587)
+#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0XF588)
+#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0XF589)
+
+#define PROC_RECOVERY_MEM_MRDEF_FILECODE (0XF801)
+#define PROC_RECOVERY_MEM_MRINIT_FILECODE (0XF802)
+#define PROC_RECOVERY_MEM_MRM_FILECODE (0XF803)
+#define PROC_RECOVERY_MEM_MRUC_FILECODE (0XF804)
+#define PROC_RECOVERY_MEM_NB_DR_MRNDR_FILECODE (0XF812)
+#define PROC_RECOVERY_MEM_NB_DR_MRNMCTDR_FILECODE (0XF813)
+#define PROC_RECOVERY_MEM_NB_HY_MRNDCTHY_FILECODE (0XF821)
+#define PROC_RECOVERY_MEM_NB_HY_MRNHY_FILECODE (0XF822)
+#define PROC_RECOVERY_MEM_NB_HY_MRNMCTHY_FILECODE (0XF823)
+#define PROC_RECOVERY_MEM_NB_HY_MRNPROTOHY_FILECODE (0XF825)
+#define PROC_RECOVERY_MEM_NB_LN_MRNDCTLN_FILECODE (0XF831)
+#define PROC_RECOVERY_MEM_NB_LN_MRNMCTLN_FILECODE (0XF832)
+#define PROC_RECOVERY_MEM_NB_LN_MRNLN_FILECODE (0XF833)
+#define PROC_RECOVERY_MEM_NB_DA_MRNDA_FILECODE (0XF842)
+#define PROC_RECOVERY_MEM_NB_DA_MRNMCTDA_FILECODE (0XF843)
+#define PROC_RECOVERY_MEM_NB_NI_MRNNI_FILECODE (0XF845)
+#define PROC_RECOVERY_MEM_NB_C32_MRNC32_FILECODE (0XF851)
+#define PROC_RECOVERY_MEM_NB_C32_MRNMCTC32_FILECODE (0XF852)
+#define PROC_RECOVERY_MEM_NB_C32_MRNPROTOC32_FILECODE (0XF853)
+#define PROC_RECOVERY_MEM_NB_ON_MRNDCTON_FILECODE (0xF861)
+#define PROC_RECOVERY_MEM_NB_ON_MRNMCTON_FILECODE (0xF862)
+#define PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE (0xF863)
+#define PROC_RECOVERY_MEM_NB_PH_MRNPH_FILECODE (0xF871)
+#define PROC_RECOVERY_MEM_NB_RB_MRNRB_FILECODE (0xF881)
+#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE (0XF8C1)
+#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE (0XF8C2)
+#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE (0XF8C3)
+#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE (0XF8C4)
+#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE (0XF8C5)
+#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE (0XF8C6)
+#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE (0XF8C7)
+#define PROC_RECOVERY_MEM_NB_MRN_FILECODE (0XF8C8)
+#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE (0XF8C9)
+#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE (0XF8CA)
+#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE (0XF8CB)
+#define PROC_RECOVERY_MEM_TECH_MRTTHRC_FILECODE (0XF8CC)
+#define PROC_RECOVERY_MEM_NB_OR_MRNDCTOR_FILECODE (0XF8CD)
+#define PROC_RECOVERY_MEM_NB_OR_MRNOR_FILECODE (0XF8CE)
+#define PROC_RECOVERY_MEM_NB_OR_MRNMCTOR_FILECODE (0XF8CF)
+#define PROC_RECOVERY_MEM_NB_OR_MRNPROTOOR_FILECODE (0XF8D0)
+#define PROC_RECOVERY_MEM_PS_MRP_FILECODE (0XF8E0)
+#define PROC_RECOVERY_MEM_PS_MRPRTT_FILECODE (0XF8E1)
+#define PROC_RECOVERY_MEM_PS_MRPODTPAT_FILECODE (0XF8E2)
+#define PROC_RECOVERY_MEM_PS_MRPSAO_FILECODE (0XF8E3)
+#define PROC_RECOVERY_MEM_PS_MRPMR0_FILECODE (0XF8E4)
+#define PROC_RECOVERY_MEM_PS_MRPRC2IBT_FILECODE (0XF8E5)
+#define PROC_RECOVERY_MEM_PS_MRPRC10OPSPD_FILECODE (0XF8E6)
+#define PROC_RECOVERY_MEM_PS_MRPLRIBT_FILECODE (0XF8E7)
+#define PROC_RECOVERY_MEM_PS_MRPLRNPR_FILECODE (0XF8E8)
+#define PROC_RECOVERY_MEM_PS_MRPLRNLR_FILECODE (0XF8E9)
+#define PROC_RECOVERY_MEM_PS_OR_MRPOR3_FILECODE (0XF8EA)
+#define PROC_RECOVERY_MEM_PS_OR_AM3_MRPSORA3_FILECODE (0XF8EB)
+#define PROC_RECOVERY_MEM_PS_OR_AM3_MRPUORA3_FILECODE (0XF8EC)
+#define PROC_RECOVERY_MEM_PS_OR_C32_MRPUORC3_FILECODE (0XF8ED)
+#define PROC_RECOVERY_MEM_PS_OR_C32_MRPRORC3_FILECODE (0XF8EE)
+#define PROC_RECOVERY_MEM_PS_OR_C32_MRPLORC3_FILECODE (0XF8EF)
+#define PROC_RECOVERY_MEM_PS_OR_G34_MRPUORG3_FILECODE (0XF8F0)
+#define PROC_RECOVERY_MEM_PS_OR_G34_MRPRORG3_FILECODE (0XF8F1)
+#define PROC_RECOVERY_MEM_PS_OR_G34_MRPLORG3_FILECODE (0XF8F2)
+
+#endif // _FILECODE_H_
diff --git a/src/vendorcode/amd/agesa/f14/Include/GeneralServices.h b/src/vendorcode/amd/agesa/f14/Include/GeneralServices.h
new file mode 100644
index 0000000..14ba10e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Include/GeneralServices.h
@@ -0,0 +1,203 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * General Services
+ *
+ * Provides Services similar to the external General Services API, except
+ * suited to use within AGESA components. Socket, Core and PCI identification.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Common
+ * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _GENERAL_SERVICES_H_
+#define _GENERAL_SERVICES_H_
+
+/*----------------------------------------------------------------------------------------
+ * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+#define NUMBER_OF_EVENT_DATA_PARAMS 4
+
+/**
+ * AMD Device id for MMIO check.
+ */
+#define AMD_DEV_VEN_ID 0x1022
+#define AMD_DEV_VEN_ID_ADDRESS 0
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S, S T R U C T U R E S, E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+/**
+ * An AGESA Event Log entry.
+ */
+typedef struct {
+ AGESA_STATUS EventClass; ///< The severity of the event, its associated AGESA_STATUS.
+ UINT32 EventInfo; ///< Uniquely identifies the event.
+ UINT32 DataParam1; ///< Event specific additional data
+ UINT32 DataParam2; ///< Event specific additional data
+ UINT32 DataParam3; ///< Event specific additional data
+ UINT32 DataParam4; ///< Event specific additional data
+} AGESA_EVENT;
+
+/*----------------------------------------------------------------------------------------
+ * F U N C T I O N P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+/**
+ * Get a specified Core's APIC ID.
+ *
+ * @param[in] StdHeader Header for library and services.
+ * @param[in] Socket The Core's Socket.
+ * @param[in] Core The Core id.
+ * @param[out] ApicAddress The Core's APIC ID.
+ * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
+ *
+ * @retval TRUE The core is present, APIC Id valid
+ * @retval FALSE The core is not present, APIC Id not valid.
+ */
+BOOLEAN
+GetApicId (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN UINT32 Socket,
+ IN UINT32 Core,
+ OUT UINT8 *ApicAddress,
+ OUT AGESA_STATUS *AgesaStatus
+);
+
+/**
+ * Get Processor Module's PCI Config Space address.
+ *
+ * @param[in] StdHeader Header for library and services.
+ * @param[in] Socket The Core's Socket.
+ * @param[in] Module The Module in that Processor
+ * @param[out] PciAddress The Processor's PCI Config Space address (Function 0, Register 0)
+ * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
+ *
+ * @retval TRUE The core is present, PCI Address valid
+ * @retval FALSE The core is not present, PCI Address not valid.
+ */
+BOOLEAN
+GetPciAddress (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN UINT32 Socket,
+ IN UINT32 Module,
+ OUT PCI_ADDR *PciAddress,
+ OUT AGESA_STATUS *AgesaStatus
+);
+
+/**
+ * "Who am I" for the current running core.
+ *
+ * @param[in] StdHeader Header for library and services.
+ * @param[out] Socket The current Core's Socket
+ * @param[out] Module The current Core's Processor Module
+ * @param[out] Core The current Core's core id.
+ * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
+ *
+ */
+VOID
+IdentifyCore (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ OUT UINT32 *Socket,
+ OUT UINT32 *Module,
+ OUT UINT32 *Core,
+ OUT AGESA_STATUS *AgesaStatus
+);
+
+/**
+ * A boolean function determine executed CPU is BSP core.
+ */
+BOOLEAN
+IsBsp (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader,
+ OUT AGESA_STATUS *AgesaStatus
+ );
+
+/**
+ * This function logs AGESA events into the event log.
+ */
+VOID
+PutEventLog (
+ IN AGESA_STATUS EventClass,
+ IN UINT32 EventInfo,
+ IN UINT32 DataParam1,
+ IN UINT32 DataParam2,
+ IN UINT32 DataParam3,
+ IN UINT32 DataParam4,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+/**
+ * This function gets event logs from the circular buffer.
+ */
+AGESA_STATUS
+GetEventLog (
+ OUT AGESA_EVENT *EventRecord,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+/**
+ * This function gets event logs from the circular buffer without flushing the entry.
+ */
+BOOLEAN
+PeekEventLog (
+ OUT AGESA_EVENT *EventRecord,
+ IN UINT16 Index,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * This routine programs the registers necessary to get the PCI MMIO mechanism
+ * up and functioning.
+ */
+VOID
+InitializePciMmio (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+#endif // _GENERAL_SERVICES_H_
diff --git a/src/vendorcode/amd/agesa/f14/Include/GnbInterface.h b/src/vendorcode/amd/agesa/f14/Include/GnbInterface.h
new file mode 100644
index 0000000..761cf3a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Include/GnbInterface.h
@@ -0,0 +1,96 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB API definition.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 37658 $ @e \$Date: 2010-09-09 15:25:38 +0800 (Thu, 09 Sep 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _GNBINTERFACE_H_
+#define _GNBINTERFACE_H_
+
+AGESA_STATUS
+GnbInitAtReset (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+GnbInitAtEarly (
+ IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr
+ );
+
+AGESA_STATUS
+GnbInitAtPost (
+ IN OUT AMD_POST_PARAMS *PostParamsPtr
+ );
+
+VOID
+GnbInitDataStructAtEnvDef (
+ IN OUT GNB_ENV_CONFIGURATION *GnbEnvConfigPtr,
+ IN AMD_ENV_PARAMS *EnvParamsPtr
+ );
+
+AGESA_STATUS
+GnbInitAtEnv (
+ IN AMD_ENV_PARAMS *EnvParamsPtr
+ );
+
+AGESA_STATUS
+GnbInitAtMid (
+ IN OUT AMD_MID_PARAMS *MidParamsPtr
+ );
+
+AGESA_STATUS
+GnbInitAtLate (
+ IN OUT AMD_LATE_PARAMS *LateParamsPtr
+ );
+
+AGESA_STATUS
+GnbInitAtPostAfterDram (
+ IN OUT AMD_POST_PARAMS *PostParamsPtr
+ );
+
+AGESA_STATUS
+AmdGnbRecovery (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f14/Include/GnbInterfaceStub.h b/src/vendorcode/amd/agesa/f14/Include/GnbInterfaceStub.h
new file mode 100644
index 0000000..0b3ff08
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Include/GnbInterfaceStub.h
@@ -0,0 +1,232 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ *
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 37658 $ @e \$Date: 2010-09-09 15:25:38 +0800 (Thu, 09 Sep 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+/*----------------------------------------------------------------------------------------
+ * M O D U L E S U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S A N D S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ * P R O T O T Y P E S O F L O C A L F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Reset Stub
+ *
+ *
+ *
+ * @param[in] StdHeader Standard configuration header
+ * @retval AGESA_STATUS Always succeeds
+ */
+
+AGESA_STATUS
+GnbInitAtReset (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+
+ return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Early Stub
+ *
+ *
+ *
+ * @param[in,out] EarlyParamsPtr Pointer to early configuration params.
+ * @retval AGESA_STATUS Always succeeds
+ */
+
+AGESA_STATUS
+GnbInitAtEarly (
+ IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr
+ )
+{
+ return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Default constructor of GNB configuration at Env
+ *
+ *
+ *
+ * @param[in] GnbEnvConfigPtr Pointer to gnb env configuration params.
+ * @param[in] EnvParamsPtr Pointer to env configuration params.
+ */
+VOID
+GnbInitDataStructAtEnvDef (
+ IN OUT GNB_ENV_CONFIGURATION *GnbEnvConfigPtr,
+ IN AMD_ENV_PARAMS *EnvParamsPtr
+ )
+{
+
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Env
+ *
+ *
+ *
+ * @param[in] EnvParamsPtr Pointer to env configuration params.
+* @retval AGESA_STATUS Always succeeds
+ */
+
+AGESA_STATUS
+GnbInitAtEnv (
+ IN AMD_ENV_PARAMS *EnvParamsPtr
+ )
+{
+
+ return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Post
+ *
+ *
+ *
+ * @param[in,out] PostParamsPtr Pointer to Post configuration params.
+ * @retval AGESA_STATUS Always succeeds
+ */
+
+AGESA_STATUS
+GnbInitAtPost (
+ IN OUT AMD_POST_PARAMS *PostParamsPtr
+ )
+{
+
+ return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Mid post
+ *
+ *
+ *
+ * @param[in,out] MidParamsPtr Pointer to mid configuration params.
+ * @retval AGESA_STATUS Always succeeds
+ */
+
+AGESA_STATUS
+GnbInitAtMid (
+ IN OUT AMD_MID_PARAMS *MidParamsPtr
+ )
+{
+
+ return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Late post
+ *
+ *
+ *
+ * @param[in,out] LateParamsPtr Pointer to late configuration params.
+ * @retval AGESA_STATUS Always succeeds
+ */
+
+AGESA_STATUS
+GnbInitAtLate (
+ IN OUT AMD_LATE_PARAMS *LateParamsPtr
+ )
+{
+
+ return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * AmdGnbRecovery
+ *
+ *
+ *
+ * @param[in] StdHeader Standard configuration header
+ * @retval AGESA_STATUS Always succeeds
+ */
+AGESA_STATUS
+AmdGnbRecovery (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Post after DRAM init
+ *
+ *
+ *
+ * @param[in] PostParamsPtr Pointer to post configuration parameters
+ * @retval Initialization status.
+ */
+
+AGESA_STATUS
+GnbInitAtPostAfterDram (
+ IN OUT AMD_POST_PARAMS *PostParamsPtr
+ )
+{
+ return AGESA_SUCCESS;
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f14/Include/Ids.h b/src/vendorcode/amd/agesa/f14/Include/Ids.h
new file mode 100644
index 0000000..cbd0b13
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Include/Ids.h
@@ -0,0 +1,927 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD IDS Routines
+ *
+ * Contains AMD AGESA Integrated Debug Macros
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: IDS
+ * @e \$Revision: 38634 $ @e \$Date: 2010-09-27 21:39:01 +0800 (Mon, 27 Sep 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+ /* Macros to aid debugging */
+ /* These definitions expand to zero (0) bytes of code when disabled */
+
+#ifndef _IDS_H_
+#define _IDS_H_
+
+#undef FALSE
+#undef TRUE
+#define FALSE 0
+#define TRUE 1
+// Proto type for optionsids.h
+typedef UINT32 IDS_STATUS; ///< Status of IDS function.
+#define IDS_SUCCESS ((IDS_STATUS) 0x00000000) ///< IDS Function is Successful.
+#define IDS_UNSUPPORTED ((IDS_STATUS) 0xFFFFFFFF) ///< IDS Function is not existed.
+
+#define IDS_STRINGIZE(a) #a ///< for define stringize macro
+/**
+ * IDS Option Hook Points
+ *
+ * These are the values to indicate hook point in AGESA for IDS Options.
+ *
+ */
+typedef enum { //vv- for debug reference only
+ IDS_INIT_EARLY_BEFORE, ///< 00 Option Hook Point before AGESA function AMD_INIT_EARLY.
+ ///< IDS Object is initialized.
+ ///< Override CPU Core Leveling Mode.
+ ///< Set P-State in Post
+ IDS_INIT_EARLY_AFTER, ///< 01 Option Hook Point after AGESA function AMD_INIT_EARLY.
+ IDS_INIT_LATE_BEFORE, ///< 02 Option Hook Point before AGESA function AMD_INIT_LATE.
+ ///< It will be used to control the following tables.
+ ///< ACPI P-State Table (_PSS, XPSS, _PCT, _PSD, _PPC)
+ ///< ACPI SRAT Table
+ ///< ACPI SLIT Table
+ ///< ACPI WHEA Table
+ ///< DMI Table
+ IDS_INIT_LATE_AFTER, ///< 03 Option Hook Point after AGESA function AMD_INIT_LATE.
+ IDS_INIT_MID_BEFORE, ///< 04 Option Hook Point before AGESA function AMD_INIT_MID.
+ IDS_INIT_MID_AFTER, ///< 05 Option Hook Point after AGESA function AMD_INIT_MID.
+ IDS_INIT_POST_BEFORE, ///< 06 Option Hook Point before AGESA function AMD_INIT_POST.
+ ///< Control Interleaving and DRAM memory hole
+ ///< Override the setting of ECC Control
+ ///< Override the setting of Online Spare Rank
+ IDS_INIT_POST_AFTER, ///< 07 Option Hook Point after AGESA function AMD_INIT_POST.
+ IDS_INIT_RESET_BEFORE, ///< 08 Option Hook Point before AGESA function AMD_INIT_RESET.
+ IDS_INIT_RESET_AFTER, ///< 09 Option Hook Point after AGESA function AMD_INIT_RESET.
+ IDS_INIT_POST_MID, ///< 0a Option Hook Point after AGESA function AMD_INIT_POST.
+ IDS_BEFORE_S3_SAVE, ///< 0b override any settings before S3 save.
+ IDS_BEFORE_S3_RESTORE, ///< 0c override any settings before S3 restore
+ IDS_AFTER_S3_SAVE, ///< 0d Override any settings after S3 save
+ IDS_AFTER_S3_RESTORE, ///< 0e Override any settings after S3 restore
+ IDS_BEFORE_DQS_TRAINING, ///< 0f override any settings before DQS training
+ IDS_BEFORE_DRAM_INIT, ///< 10 override any settings before Dram initialization
+ IDS_BEFORE_MEM_FREQ_CHG, ///< 11 override settings before MemClk frequency change
+ IDS_BEFORE_WARM_RESET , ///< 12 Override PCI or MSR Registers Before Warm Reset
+ IDS_BEFORE_MEM_INIT, ///< 13 Override PCI or MSR Registers Before Memory Init
+ IDS_BEFORE_PCI_INIT, ///< 14 Override PCI or MSR Registers Before PCI Init
+ IDS_BEFORE_OS, ///< 15 Override PCI or MSR Registers Before booting to OS
+ IDS_UCODE, ///< 16 Enable or Disable microcode patching
+ IDS_BEFORE_AP_EARLY_HALT, ///< 17 Option Hook Point before AP early halt
+
+ IDS_PLATFORM_RSVD1 = 0x38, ///< from 0x38 to 0x3f will reserved for platform used
+ IDS_PLATFORM_RSVD2 = 0x39, ///< from 0x38 to 0x3f will reserved for platform used
+ IDS_PLATFORM_RSVD3 = 0x3a, ///< from 0x38 to 0x3f will reserved for platform used
+ IDS_PLATFORM_RSVD4 = 0x3b, ///< from 0x38 to 0x3f will reserved for platform used
+ IDS_PLATFORM_RSVD5 = 0x3c, ///< from 0x38 to 0x3f will reserved for platform used
+ IDS_PLATFORM_RSVD6 = 0x3d, ///< from 0x38 to 0x3f will reserved for platform used
+ IDS_PLATFORM_RSVD7 = 0x3e, ///< from 0x38 to 0x3f will reserved for platform used
+ IDS_PLATFORM_RSVD8 = 0x3f, ///< from 0x38 to 0x3f will reserved for platform used
+
+ // All the above timing point is used by BVM, their value should never be changed
+ IDS_HT_CONTROL, ///< 40 Override the setting of HT Link Control
+ IDS_HT_TRISTATE, ///< 41 Enable or Disable HT Tri-state during an LDTSTP#
+ IDS_INIT_DRAM_TABLE, ///< 42 Generate override table for Dram Timing
+ ///< Dram Controller, Drive Strength and DQS Timing
+ IDS_GET_DRAM_TABLE, ///< 43 Generate override table for Dram Timing
+ IDS_GANGING_MODE, ///< 44 override Memory Mode Unganged
+ IDS_POWERDOWN_MODE, ///< 45 override Power Down Mode
+ IDS_BURST_LENGTH32, ///< 46 override Burst Length32
+ IDS_ALL_MEMORY_CLOCK, ///< 47 override All Memory Clks Enable
+ IDS_ECC, ///< 48 override ECC parameter
+ IDS_ECCSYMBOLSIZE, ///< 49 override ECC symbol size
+ IDS_CPU_Early_Override, ///< 4a override CPU early parameter
+ IDS_CACHE_FLUSH_HLT, ///< 4b override Cache Flush Hlt
+ IDS_CHANNEL_INTERLEAVE, ///< 4c override Channel Interleave
+ IDS_MEM_ERROR_RECOVERY, ///< 4d override memory error recovery
+ IDS_MEM_RETRAIN_TIMES, ///< 4e override memory retrain times
+ IDS_MEM_SIZE_OVERLAY, ///< 4f Override the syslimit
+ IDS_HT_ASSIST, ///< 50 Override Probe Filter
+ IDS_CHECK_NEGATIVE_WL, ///< 51 Check for negative write leveling result
+ IDS_DLL_SHUT_DOWN, ///< 52 Check for Dll Shut Down
+ IDS_POR_MEM_FREQ, ///< 53 Entry to enable/disable MemClk frequency enforcement
+ IDS_PHY_DLL_STANDBY_CTRL, ///< 54 Enable/Disable Phy DLL standby feature
+ IDS_PLATFORMCFG_OVERRIDE, ///< 55 Hook for Override PlatformConfig structure
+ IDS_LOADCARD_ERROR_RECOVERY, ///< 56 Special error handling for load card support
+ IDS_MEM_IGNORE_ERROR, ///< 57 Ignore error and do not do fatal exit in memory
+ IDS_GNB_SMU_SERVICE_CONFIG, ///< 58 Config GNB SMU service
+ IDS_GNB_ORBDYNAMIC_WAKE, ///< 59 config GNB dynamic wake
+ IDS_GNB_PLATFORMCFG_OVERRIDE, ///< 5a override ids gnb platform config
+ IDS_GNB_LCLK_DPM_EN, ///< 5b override GNB LCLK DPM configuration
+ IDS_GNB_LCLK_DEEP_SLEEP, ///< 5c override GNB LCLK DPM deep sleep
+ IDS_GNB_CLOCK_GATING, ///< 5d Override GNB Clock gating config
+ IDS_NB_PSTATE_DIDVID, ///< 5e Override NB P-state settings
+ IDS_CPB_CTRL, ///< 5f Config the Core peformance boost feature
+ IDS_HTC_CTRL, ///< 60 Hook for Hardware Thermal Control
+ IDS_CC6_WORKAROUND, ///< 61 Hook for skip CC6 work around
+ IDS_MEM_MR0, ///< 62 Hook for override Memory Mr0 register
+ IDS_REG_TABLE, ///< 63 Hook for add IDS register table to the loop
+ IDS_NBBUFFERALLOCATIONATEARLY, ///< 64 Hook for override North bridge bufer allocation
+ IDS_BEFORE_S3_SPECIAL, ///< 65 Hook to bypass S3 special functions
+ IDS_SET_PCI_REGISTER_ENTRY, ///< 66 Hook to SetRegisterForPciEntry
+ IDS_ERRATUM463_WORKAROUND, ///< 67 Hook to Erratum 463 workaround
+ IDS_BEFORE_MEMCLR, ///< 68 Hook before set Memclr bit
+ IDS_OVERRIDE_IO_CSTATE, ///< 69 Hook for override io C-state setting
+ IDS_NBPSDIS_OVERRIDE, ///< 6a Hook for override NB pstate disable setting
+ IDS_NBPS_REG_OVERRIDE, ///< 6b Hook for override Memory NBps reg
+ IDS_LOW_POWER_PSTATE, ///< 6c Hook for disalbe Low power_Pstates feature
+ IDS_CST_CREATE, ///< 6d Hook for create _CST
+ IDS_CST_SIZE, ///< 6e Hook for get _CST size
+ IDS_ENFORCE_VDDIO, ///< 6f Hook to override VDDIO
+ IDS_SKIP_PERFORMANCE_OPT, ///< 70 Hook to skip performance optimization
+ IDS_INIT_MEM_REG_TABLE, ///< 71 Hook for init memory register table
+ IDS_SKIP_FUSED_MAX_RATE ///< 72 Hook to skip fused max rate cap
+} AGESA_IDS_OPTION;
+
+#include "OptionsIds.h"
+#include "Filecode.h"
+
+/* Initialize IDS controls */
+#ifndef IDSOPT_IDS_ENABLED
+ #define IDSOPT_IDS_ENABLED FALSE
+#endif
+
+#ifndef IDSOPT_CONTROL_ENABLED
+ #define IDSOPT_CONTROL_ENABLED FALSE
+#endif
+
+#ifndef IDSOPT_TRACING_ENABLED
+ #define IDSOPT_TRACING_ENABLED FALSE
+#endif
+
+#ifndef IDSOPT_TRACE_USER_OPTIONS
+ #define IDSOPT_TRACE_USER_OPTIONS TRUE
+#endif
+
+#ifndef IDSOPT_PERF_ANALYSIS
+ #define IDSOPT_PERF_ANALYSIS FALSE
+#endif
+
+#ifndef IDSOPT_HEAP_CHECKING
+ #define IDSOPT_HEAP_CHECKING FALSE
+#endif
+
+#ifndef IDSOPT_ASSERT_ENABLED
+ #define IDSOPT_ASSERT_ENABLED FALSE
+#endif
+
+#ifndef IDSOPT_ERROR_TRAP_ENABLED
+ #define IDSOPT_ERROR_TRAP_ENABLED FALSE
+#endif
+
+#ifndef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+ #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE
+#endif
+
+#ifndef IDSOPT_DEBUG_CODE_ENABLED
+ #define IDSOPT_DEBUG_CODE_ENABLED FALSE
+#endif
+
+#ifndef IDSOPT_C_OPTIMIZATION_DISABLED
+ #define IDSOPT_C_OPTIMIZATION_DISABLED FALSE
+#endif
+
+#if IDSOPT_IDS_ENABLED == FALSE
+ #undef IDSOPT_CONTROL_ENABLED
+ #undef IDSOPT_TRACING_ENABLED
+ #undef IDSOPT_PERF_ANALYSIS
+ #undef IDSOPT_HEAP_CHECKING
+ #undef IDSOPT_ASSERT_ENABLED
+ #undef IDSOPT_ERROR_TRAP_ENABLED
+ #undef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+ #undef IDSOPT_DEBUG_CODE_ENABLED
+ #undef IDSOPT_TRACE_USER_OPTIONS
+
+ #define IDSOPT_CONTROL_ENABLED FALSE
+ #define IDSOPT_TRACING_ENABLED FALSE
+ #define IDSOPT_PERF_ANALYSIS FALSE
+ #define IDSOPT_HEAP_CHECKING FALSE
+ #define IDSOPT_ASSERT_ENABLED FALSE
+ #define IDSOPT_ERROR_TRAP_ENABLED FALSE
+ #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE
+ #define IDSOPT_DEBUG_CODE_ENABLED FALSE
+ #define IDSOPT_TRACE_USER_OPTIONS FALSE
+#endif
+
+/**
+ * Make a Progress Report to the User.
+ *
+ * This Macro is always enabled. The default action is to write the TestPoint value
+ * to an I/O port. The I/O port is 8 bits in size and the default address is 0x80.
+ * IBVs can change AGESA's default port by defining IDS_DEBUG_PORT to desired port
+ * in OptionsIds.h in their build tip.
+ *
+ * @param[in] TestPoint The value for display indicating progress
+ * @param[in,out] StdHeader Pointer of AMD_CONFIG_PARAMS
+ *
+ **/
+
+#define AGESA_TESTPOINT(TestPoint, StdHeader)
+
+#ifndef IDS_DEBUG_PORT
+ #define IDS_DEBUG_PORT 0x80
+#endif
+
+/**
+ * @def STOP_HERE
+ * (macro) - Causes program to halt. This is @b only for use during active debugging .
+ *
+ * Causes the program to halt and display the file number of the source of the
+ * halt (displayed in decimal).
+ *
+ **/
+#if IDSOPT_IDS_ENABLED == TRUE
+ #ifdef STOP_CODE
+ #undef STOP_CODE
+ #endif
+ #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \
+ ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
+ (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
+ #define STOP_HERE
+#else
+ #define STOP_HERE
+#endif
+
+/**
+ * @def ASSERT
+ * Test an assertion that the given statement is True.
+ *
+ * The statement is evaluated to a boolean value. If the statement is True,
+ * then no action is taken (no error). If the statement is False, a error stop
+ * is generated to halt the program. Used for testing for fatal errors that
+ * must be resolved before production. This is used to do parameter checks,
+ * bounds checking, range checks and 'sanity' checks.
+ *
+ * @param[in] conditional Assert that evaluating this conditional results in TRUE.
+ *
+ **/
+#ifndef ASSERT
+ #if IDSOPT_ASSERT_ENABLED == TRUE
+ #ifdef STOP_CODE
+ #undef STOP_CODE
+ #endif
+ #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \
+ ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
+ (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
+
+ #define ASSERT(conditional)
+ #else
+ #define ASSERT(conditional)
+ #endif
+#endif
+
+#if IDSOPT_CAR_CORRUPTION_CHECK_ENABLED == TRUE
+ #undef IDSOPT_ERROR_TRAP_ENABLED
+ #define IDSOPT_ERROR_TRAP_ENABLED TRUE
+ #define IDS_CAR_CORRUPTION_CHECK(StdHeader)
+#else
+ #define IDS_CAR_CORRUPTION_CHECK(StdHeader)
+#endif
+/**
+ * @def DEBUG_CODE
+ * Make the code active when IDSOPT_DEBUG_CODE_ENABLED enable
+ *
+ */
+#ifndef DEBUG_CODE
+ #if IDSOPT_DEBUG_CODE_ENABLED == TRUE
+ #define DEBUG_CODE(Code)
+ #else
+ #define DEBUG_CODE(Code)
+ #endif
+#endif
+
+/**
+ * @def IDS_ERROR_TRAP
+ * Trap AGESA Error events with stop code display.
+ *
+ * Works similarly to use of "ASSERT (FALSE);"
+ *
+ */
+#if IDSOPT_ERROR_TRAP_ENABLED == TRUE
+ #ifdef STOP_CODE
+ #undef STOP_CODE
+ #endif
+ #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \
+ ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
+ (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
+
+ #define IDS_ERROR_TRAP
+#else
+ #define IDS_ERROR_TRAP
+#endif
+
+///give the extended Macro default value
+#ifndef __IDS_EXTENDED__
+ #define IDS_EXTENDED_HOOK(idsoption, dataptr, idsnvptr, stdheader) IDS_SUCCESS
+ #define IDS_INITIAL_F10_PM_STEP
+ #define IDS_INITIAL_F12_PM_STEP
+ #define IDS_INITIAL_F14_PM_STEP
+ #define IDS_INITIAL_F15_PM_STEP
+ #define IDS_EXTENDED_GET_DATA_EARLY(data, StdHeader)
+ #define IDS_EXTENDED_GET_DATA_LATE(data, StdHeader)
+ #define IDS_EXTENDED_HEAP_SIZE 0
+ #define IDS_EXT_INCLUDE_F10(file)
+ #define IDS_EXT_INCLUDE_F12(file)
+ #define IDS_EXT_INCLUDE_F14(file)
+ #define IDS_EXT_INCLUDE_F15(file)
+ #define IDS_EXT_INCLUDE(file)
+#endif
+
+#ifndef IDS_NUM_NV_ITEM
+ #define IDS_NUM_NV_ITEM (IDS_NUM_EXT_NV_ITEM)
+#endif
+
+#if IDSOPT_CONTROL_ENABLED == TRUE
+ #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader)
+
+ #define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader)
+#else
+ #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader)
+
+ #define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader)
+#endif
+
+/**
+ * Macro to add a *skip* hook for IDS options
+ *
+ * The default minimal action is to do nothing and there is no any code to increase.
+ * For debug environments, IDS dispatcher function will be called to perform
+ * the detailed action and to skip AGESA code if necessary.
+ *
+ * @param[in] IdsOption IDS Option ID for this hook point
+ * @param[in, out] DataPtr Data Pointer to override
+ * @param[in, out] StdHeader Pointer of AMD_CONFIG_PARAMS
+ *
+ *
+ **/
+
+#if IDSOPT_CONTROL_ENABLED == TRUE
+ #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader)
+#else
+ #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader)
+#endif
+
+/**
+ * Macro to add a heap manager routine
+ *
+ * when memory is allocated the heap manager actually allocates two extra dwords of data,
+ * one dword buffer before the actual memory, and one dword afterwards.
+ * a complete heap walk and check to be performed at any time.
+ * it would ASSERT if the heap is corrupt
+ *
+ * @param[in] StdHeader Pointer of AMD_CONFIG_PARAMS
+ *
+ *
+ **/
+
+// Heap debug feature
+#define SENTINEL_BEFORE_VALUE 0x64616548 // "Head"
+#define SENTINEL_AFTER_VALUE 0x6C696154 // "Tail"
+#if IDSOPT_IDS_ENABLED == TRUE
+ #if IDSOPT_HEAP_CHECKING == TRUE
+ #define SIZE_OF_SENTINEL 0
+ #define NUM_OF_SENTINEL 0
+ #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte)
+ #define SET_SENTINEL_AFTER(NodePtr)
+ #define Heap_Check(stdheader)
+ #else
+ #define SIZE_OF_SENTINEL 0
+ #define NUM_OF_SENTINEL 0
+ #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte)
+ #define SET_SENTINEL_AFTER(NodePtr)
+ #define Heap_Check(stdheader)
+ #endif
+#else
+ #define SIZE_OF_SENTINEL 0
+ #define NUM_OF_SENTINEL 0
+ #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte)
+ #define SET_SENTINEL_AFTER(NodePtr)
+ #define Heap_Check(stdheader)
+#endif
+
+
+ //Note a is from 0 to 63
+#define DEBUG_PRINT_SHIFT(a) ((UINT64)1 << a)
+//If you change the Bitmap definition below, please change the Hash in ParseFilter of hdtout2008.pl accordingly
+//Memory Masks
+#define MEM_SETREG DEBUG_PRINT_SHIFT (0)
+#define MEM_GETREG DEBUG_PRINT_SHIFT (1)
+#define MEM_FLOW DEBUG_PRINT_SHIFT (2)
+#define MEM_STATUS DEBUG_PRINT_SHIFT (3)
+#define MEMORY_TRACE_RSV1 DEBUG_PRINT_SHIFT (4)
+#define MEMORY_TRACE_RSV2 DEBUG_PRINT_SHIFT (5)
+#define MEMORY_TRACE_RSV3 DEBUG_PRINT_SHIFT (6)
+#define MEMORY_TRACE_RSV4 DEBUG_PRINT_SHIFT (7)
+#define MEMORY_TRACE_RSV5 DEBUG_PRINT_SHIFT (8)
+#define MEMORY_TRACE_RSV6 DEBUG_PRINT_SHIFT (9)
+
+
+
+//CPU Masks
+#define CPU_TRACE DEBUG_PRINT_SHIFT (10)
+#define CPU_TRACE_RSV1 DEBUG_PRINT_SHIFT (11)
+#define CPU_TRACE_RSV2 DEBUG_PRINT_SHIFT (12)
+#define CPU_TRACE_RSV3 DEBUG_PRINT_SHIFT (13)
+#define CPU_TRACE_RSV4 DEBUG_PRINT_SHIFT (14)
+#define CPU_TRACE_RSV5 DEBUG_PRINT_SHIFT (15)
+#define CPU_TRACE_RSV6 DEBUG_PRINT_SHIFT (16)
+#define CPU_TRACE_RSV7 DEBUG_PRINT_SHIFT (17)
+#define CPU_TRACE_RSV8 DEBUG_PRINT_SHIFT (18)
+#define CPU_TRACE_RSV9 DEBUG_PRINT_SHIFT (19)
+
+//GNB Masks
+#define GNB_TRACE DEBUG_PRINT_SHIFT (20)
+#define PCIE_MISC DEBUG_PRINT_SHIFT (21)
+#define PCIE_PORTREG_TRACE DEBUG_PRINT_SHIFT (22)
+#define PCIE_HOSTREG_TRACE DEBUG_PRINT_SHIFT (23)
+#define GNB_TRACE_RSV2 DEBUG_PRINT_SHIFT (24)
+#define NB_MISC DEBUG_PRINT_SHIFT (25)
+#define GNB_TRACE_RSV3 DEBUG_PRINT_SHIFT (26)
+#define GFX_MISC DEBUG_PRINT_SHIFT (27)
+#define NB_SMUREG_TRACE DEBUG_PRINT_SHIFT (28)
+#define GNB_TRACE_RSV1 DEBUG_PRINT_SHIFT (29)
+
+//HT Masks
+#define HT_TRACE DEBUG_PRINT_SHIFT (30)
+#define HT_TRACE_RSV1 DEBUG_PRINT_SHIFT (31)
+#define HT_TRACE_RSV2 DEBUG_PRINT_SHIFT (32)
+#define HT_TRACE_RSV3 DEBUG_PRINT_SHIFT (33)
+#define HT_TRACE_RSV4 DEBUG_PRINT_SHIFT (34)
+#define HT_TRACE_RSV5 DEBUG_PRINT_SHIFT (35)
+#define HT_TRACE_RSV6 DEBUG_PRINT_SHIFT (36)
+#define HT_TRACE_RSV7 DEBUG_PRINT_SHIFT (37)
+#define HT_TRACE_RSV8 DEBUG_PRINT_SHIFT (38)
+#define HT_TRACE_RSV9 DEBUG_PRINT_SHIFT (39)
+
+//FCH Masks
+#define FCH_TRACE DEBUG_PRINT_SHIFT (40)
+#define FCH_TRACE_RSV1 DEBUG_PRINT_SHIFT (41)
+#define FCH_TRACE_RSV2 DEBUG_PRINT_SHIFT (42)
+#define FCH_TRACE_RSV3 DEBUG_PRINT_SHIFT (43)
+#define FCH_TRACE_RSV4 DEBUG_PRINT_SHIFT (44)
+#define FCH_TRACE_RSV5 DEBUG_PRINT_SHIFT (45)
+#define FCH_TRACE_RSV6 DEBUG_PRINT_SHIFT (46)
+#define FCH_TRACE_RSV7 DEBUG_PRINT_SHIFT (47)
+#define FCH_TRACE_RSV8 DEBUG_PRINT_SHIFT (48)
+#define FCH_TRACE_RSV9 DEBUG_PRINT_SHIFT (49)
+
+//Other Masks
+#define MAIN_FLOW DEBUG_PRINT_SHIFT (50)
+#define EVENT_LOG DEBUG_PRINT_SHIFT (51)
+#define PERFORMANCE_ANALYSE DEBUG_PRINT_SHIFT (52)
+
+//Ids Masks
+#define IDS_TRACE DEBUG_PRINT_SHIFT (53)
+#define IDS_REG DEBUG_PRINT_SHIFT (54)
+#define IDS_TRACE_RSV2 DEBUG_PRINT_SHIFT (55)
+#define IDS_TRACE_RSV3 DEBUG_PRINT_SHIFT (56)
+
+//S3
+#define S3_TRACE DEBUG_PRINT_SHIFT (57)
+
+
+//Reserved
+#define TRACE_RSV1 DEBUG_PRINT_SHIFT (58)
+#define TRACE_RSV2 DEBUG_PRINT_SHIFT (59)
+#define TRACE_RSV3 DEBUG_PRINT_SHIFT (60)
+#define TRACE_RSV4 DEBUG_PRINT_SHIFT (61)
+#define TRACE_RSV5 DEBUG_PRINT_SHIFT (62)
+#define TRACE_RSV6 DEBUG_PRINT_SHIFT (63)
+
+#define GNB_TRACE_DEFAULT 0
+
+#define GNB_TRACE_REG 0
+
+#define GNB_TRACE_ALL 0
+
+#define CPU_TRACE_ALL 0
+
+#define MEMORY_TRACE_ALL 0
+
+#define HT_TRACE_ALL 0
+
+#define FCH_TRACE_ALL 0
+
+#define IDS_TRACE_ALL 0
+
+#define OTHER_TRACE_ALL 0
+
+#define TRACE_MASK_ALL (0ull)
+#ifndef IDS_DEBUG_PRINT_MASK
+ #define IDS_DEBUG_PRINT_MASK 0
+#endif
+
+
+/**
+ * Macro to add HDT OUT
+ *
+ * The default minimal action is to do nothing and there is no any code to increase.
+ * For debug environments, the debug information can be displayed in HDT or other
+ * devices.
+ *
+ **/
+#if IDSOPT_IDS_ENABLED == TRUE
+ #if IDSOPT_TRACING_ENABLED == TRUE
+ #define IDS_HDT_CONSOLE_INIT(x)
+ #define IDS_HDT_CONSOLE_EXIT(x)
+ #define IDS_HDT_CONSOLE_S3_EXIT(x)
+ #define IDS_HDT_CONSOLE_S3_AP_EXIT(x)
+
+ #if IDSOPT_C_OPTIMIZATION_DISABLED == TRUE
+ #ifdef __GNUC__
+ #define IDS_HDT_CONSOLE(f, s, ...)
+ #else
+ #define IDS_HDT_CONSOLE(f, s, ...)
+ #endif
+ #else
+ #pragma warning(disable: 4127)
+ #ifdef __GNUC__
+ #define IDS_HDT_CONSOLE(f, s, ...)
+ #else
+ #define IDS_HDT_CONSOLE(f, s, ...)
+ #endif
+ #endif
+
+ #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x)
+ #define IDS_HDT_CONSOLE_ASSERT(x)
+ #define IDS_FUNCLIST_ADDR NULL
+ #define IDS_FUNCLIST_EXTERN()
+ #define IDS_TIMEOUT_CTL(t)
+ #define IDS_HDT_CONSOLE_DEBUG_CODE(Code)
+ #define CONSOLE(s, ...)
+ #else
+ #define IDS_HDT_CONSOLE_INIT(x)
+ #define IDS_HDT_CONSOLE_EXIT(x)
+ #define IDS_HDT_CONSOLE_S3_EXIT(x)
+ #define IDS_HDT_CONSOLE_S3_AP_EXIT(x)
+ #define IDS_HDT_CONSOLE(f, s, ...)
+ #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x)
+ #define IDS_HDT_CONSOLE_ASSERT(x)
+ #define IDS_FUNCLIST_ADDR NULL
+ #define IDS_FUNCLIST_EXTERN()
+ #define IDS_TIMEOUT_CTL(t)
+ #define IDS_HDT_CONSOLE_DEBUG_CODE(Code)
+ #define CONSOLE(s, ...)
+ #endif
+#else
+ #define IDS_HDT_CONSOLE_INIT(x)
+ #define IDS_HDT_CONSOLE_EXIT(x)
+ #define IDS_HDT_CONSOLE_S3_EXIT(x)
+ #define IDS_HDT_CONSOLE_S3_AP_EXIT(x)
+ #define IDS_HDT_CONSOLE(f, s, ...)
+ #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x)
+ #define IDS_HDT_CONSOLE_ASSERT(x)
+ #define IDS_FUNCLIST_ADDR NULL
+ #define IDS_FUNCLIST_EXTERN()
+ #define IDS_TIMEOUT_CTL(t)
+ #define IDS_HDT_CONSOLE_DEBUG_CODE(Code)
+ #define CONSOLE(s, ...)
+#endif
+
+#define IDS_TRACE_SHOW_BLD_OPT_CFG IDSOPT_TRACE_USER_OPTIONS
+
+#if IDSOPT_PERF_ANALYSIS == TRUE
+ #define IDS_PERF_TIMESTAMP(StdHeader, TestPoint)
+ #define IDS_PERF_ANALYSE(StdHeader)
+ #define IDS_PERF_TIME_MEASURE(StdHeader)
+#else
+ #define IDS_PERF_TIMESTAMP(StdHeader, TestPoint)
+ #define IDS_PERF_ANALYSE(StdHeader)
+ #define IDS_PERF_TIME_MEASURE(StdHeader)
+#endif
+
+///For IDS feat use
+#define IDS_FAMILY_ALL 0x0ull
+#define IDS_BSP_ONLY TRUE
+#define IDS_ALL_CORES FALSE
+
+#define IDS_LATE_RUN_AP_TASK_ID PROC_IDS_CONTROL_IDSLIB_FILECODE
+
+#define IDS_CALLOUT_INIT 0x00 ///< The function data of IDS callout function of initialization.
+
+#define IDS_CALLOUT_GNB_PPFUSE_OVERRIDE 0x00 ///< The function data of IDS callout function of GNB pp fuse table.
+#define IDS_CALLOUT_GNB_INTEGRATED_TABLE_CONFIG 0x00 ///< The function data of IDS callout function of GNB integrated table.
+#define IDS_CALLOUT_GNB_NB_POWERGATE_CONFIG 0x00 ///< The function data of IDS callout function of GNB NB power gate config.
+#define IDS_CALLOUT_GNB_PCIE_POWERGATE_CONFIG 0x00 ///< The function data of IDS callout function of GNB PCIE power gateconfig.
+#define IDS_CALLOUT_GNB_PCIE_PLATFORM_CONFIG 0x00 ///< The function data of IDS callout function of GNB pcie platform config.
+#define IDS_CALLOUT_GNB_PCIE_PHY_CONFIG 0x00 ///< The function data of IDS callout function of GNB pcie PHY config.
+#define IDS_CALLOUT_GNB_GMM_REGISTER_OVERRIDE 0x00 ///< The function data of IDS callout function of GNB GMM register override
+
+/// Function entry for HDT script to call
+typedef struct _SCRIPT_FUNCTION {
+ UINT32 FuncAddr; ///< Function address in ROM
+ CHAR8 FuncName[40]; ///< Function name
+} SCRIPT_FUNCTION;
+
+/// Data Structure for Mem ECC parameter override
+typedef struct {
+ IN BOOLEAN CfgEccRedirection; ///< ECC Redirection
+ IN UINT16 CfgScrubDramRate; ///< Scrub Dram Rate
+ IN UINT16 CfgScrubL2Rate; ///< Scrub L2Rate
+ IN UINT16 CfgScrubL3Rate; ///< Scrub L3Rate
+ IN UINT16 CfgScrubIcRate; ///< Scrub Ic Rate
+ IN UINT16 CfgScrubDcRate; ///< Scrub Dc Rate
+ IN BOOLEAN CfgEccSyncFlood; ///< ECC Sync Flood
+} ECC_OVERRIDE_STRUCT;
+
+
+
+
+/**
+ * AGESA Test Points
+ *
+ * These are the values displayed to the user to indicate progress through boot.
+ * These can be used in a debug environment to stop the debugger at a specific
+ * test point:
+ * For SimNow!, this command
+ * bi 81 w vb 49
+ * will stop the debugger on one of the TracePoints (49 is the TP value in this example).
+ *
+ */
+typedef enum {
+ StartProcessorTestPoints, ///< 00 Entry used for range testing for @b Processor related TPs
+
+ // Memory test points
+ TpProcMemBeforeMemDataInit, ///< 01 .. Memory structure initialization (Public interface)
+ TpProcMemBeforeSpdProcessing, ///< 02 .. SPD Data processing (Public interface)
+ TpProcMemAmdMemAuto, ///< 03 .. Memory configuration (Public interface)
+ TpProcMemDramInit, ///< 04 .. DRAM initialization
+ TpProcMemSPDChecking, ///< 05 ..
+ TpProcMemModeChecking, ///< 06 ..
+ TpProcMemSpeedTclConfig, ///< 07 .. Speed and TCL configuration
+ TpProcMemSpdTiming, ///< 08 ..
+ TpProcMemDramMapping, ///< 09 ..
+ TpProcMemPlatformSpecificConfig, ///< 0A ..
+ TPProcMemPhyCompensation, ///< 0B ..
+ TpProcMemStartDcts, ///< 0C ..
+ TpProcMemBeforeDramInit, ///< 0D .. (Public interface)
+ TpProcMemPhyFenceTraining, ///< 0E ..
+ TpProcMemSynchronizeDcts, ///< 0F ..
+ TpProcMemSystemMemoryMapping, ///< 10 ..
+ TpProcMemMtrrConfiguration, ///< 11 ..
+ TpProcMemDramTraining, ///< 12 ..
+ TpProcMemBeforeAnyTraining, ///< 13 .. (Public interface)
+ TpProcMemWriteLevelizationTraining, ///< 14 ..
+ TpProcMemWlFirstPass, ///< 15 .. Below 800Mhz first pass start
+ TpProcMemWlSecondPass, ///< 16 .. Above 800Mhz second pass start
+ TpProcMemWlDimmConfig, ///< 17 .. Target DIMM configured
+ TpProcMemWlPrepDimms, ///< 18 .. Prepare DIMMS for WL
+ TpProcMemWlConfigDimms, ///< 19 .. Configure DIMMS for WL
+ TpProcMemReceiverEnableTraining, ///< 1A ..
+ TpProcMemRcvrStartSweep, ///< 1B .. Start sweep loop
+ TpProcMemRcvrSetDelay, ///< 1C .. Set receiver Delay
+ TpProcMemRcvrWritePattern, ///< 1D .. Write test pattern
+ TpProcMemRcvrReadPattern, ///< 1E .. Read test pattern
+ TpProcMemRcvrTestPattern, ///< 1F .. Compare test pattern
+ TpProcMemRcvrCalcLatency, ///< 20 .. Calculate MaxRdLatency per channel
+ TpProcMemReceiveDqsTraining, ///< 21 ..
+ TpProcMemRcvDqsSetDelay, ///< 22 .. Set Write Data delay
+ TpProcMemRcvDqsWritePattern, ///< 23 .. Write test pattern
+ TpProcMemRcvDqsStartSweep, ///< 24 .. Start read sweep
+ TpProcMemRcvDqsSetRcvDelay, ///< 25 .. Set Receive DQS delay
+ TpProcMemRcvDqsReadPattern, ///< 26 .. Read Test pattern
+ TpProcMemRcvDqsTstPattern, ///< 27 .. Compare Test pattern
+ TpProcMemRcvDqsResults, ///< 28 .. Update results
+ TpProcMemRcvDqsFindWindow, ///< 29 .. Start Find passing window
+ TpProcMemTransmitDqsTraining, ///< 2A ..
+ TpProcMemTxDqStartSweep, ///< 2B .. Start write sweep
+ TpProcMemTxDqSetDelay, ///< 2C .. Set Transmit DQ delay
+ TpProcMemTxDqWritePattern, ///< 2D .. Write test pattern
+ TpProcMemTxDqReadPattern, ///< 2E .. Read Test pattern
+ TpProcMemTxDqTestPattern, ///< 2F .. Compare Test pattern
+ TpProcMemTxDqResults, ///< 30 .. Update results
+ TpProcMemTxDqFindWindow, ///< 31 .. Start Find passing window
+ TpProcMemMaxRdLatencyTraining, ///< 32 ..
+ TpProcMemMaxRdLatStartSweep, ///< 33 .. Start sweep
+ TpProcMemMaxRdLatSetDelay, ///< 34 .. Set delay
+ TpProcMemMaxRdLatWritePattern, ///< 35 .. Write test pattern
+ TpProcMemMaxRdLatReadPattern, ///< 36 .. Read Test pattern
+ TpProcMemMaxRdLatTestPattern, ///< 37 .. Compare Test pattern
+ TpProcMemOnlineSpareInit, ///< 38 .. Online Spare init
+ TpProcMemBankInterleaveInit, ///< 39 .. Bank Interleave Init
+ TpProcMemNodeInterleaveInit, ///< 3A .. Node Interleave Init
+ TpProcMemChannelInterleaveInit, ///< 3B .. Channel Interleave Init
+ TpProcMemEccInitialization, ///< 3C .. ECC initialization
+ TpProcMemPlatformSpecificInit, ///< 3D .. Platform Specific Init
+ TpProcMemBeforeAgesaReadSpd, ///< 3E .. Before callout for "AgesaReadSpd"
+ TpProcMemAfterAgesaReadSpd, ///< 3F .. After callout for "AgesaReadSpd"
+ TpProcMemBeforeAgesaHookBeforeDramInit, ///< 40 .. Before optional callout "AgesaHookBeforeDramInit"
+ TpProcMemAfterAgesaHookBeforeDramInit, ///< 41 .. After optional callout "AgesaHookBeforeDramInit"
+ TpProcMemBeforeAgesaHookBeforeDQSTraining, ///< 42 .. Before optional callout "AgesaHookBeforeDQSTraining"
+ TpProcMemAfterAgesaHookBeforeDQSTraining, ///< 43 .. After optional callout "AgesaHookBeforeDQSTraining"
+ TpProcMemBeforeAgesaHookBeforeExitSelfRef, ///< 44 .. Before optional callout "AgesaHookBeforeDramInit"
+ TpProcMemAfterAgesaHookBeforeExitSelfRef, ///< 45 .. After optional callout "AgesaHookBeforeDramInit"
+ TpProcMemAfterMemDataInit, ///< 46 .. After MemDataInit
+ TpProcMemInitializeMCT, ///< 47 .. Before InitializeMCT
+ TpProcMemLvDdr3, ///< 48 .. Before LV DDR3
+ TpProcMemInitMCT, ///< 49 .. Before InitMCT
+ TpProcMemOtherTiming, ///< 4A.. Before OtherTiming
+ TpProcMemUMAMemTyping, ///< 4B .. Before UMAMemTyping
+ TpProcMemSetDqsEccTmgs, ///< 4C .. Before SetDqsEccTmgs
+ TpProcMemMemClr, ///< 4D .. Before MemClr
+ TpProcMemOnDimmThermal, ///< 4E .. Before On DIMM Thermal
+ TpProcMemDmi, ///< 4F .. Before DMI
+ TpProcMemEnd, ///< 50 .. End of memory code
+
+ // CPU test points
+ TpProcCpuEntryDmi, ///< 51 .. Entry point CreateDmiRecords
+ TpProcCpuEntryPstate, ///< 52 .. Entry point GenerateSsdt
+ TpProcCpuEntryPstateLeveling, ///< 53 .. Entry point PStateLeveling
+ TpProcCpuEntryPstateGather, ///< 54 .. Entry point PStateGatherData
+ TpProcCpuEntryWhea, ///< 55 .. Entry point CreateAcpiWhea
+ TpProcCpuEntrySrat, ///< 56 .. Entry point CreateAcpiSrat
+ TpProcCpuEntrySlit, ///< 57 .. Entry point CreateAcpiSlit
+ TpProcCpuProcessRegisterTables, ///< 58 .. Register table processing
+ TpProcCpuSetBrandID, ///< 59 .. Set brand ID
+ TpProcCpuLocalApicInit, ///< 5A .. Initialize local APIC
+ TpProcCpuLoadUcode, ///< 5B .. Load microcode patch
+ TpProcCpuBeforePMFeatureInit, ///< 5C .. BeforePM feature dispatch point
+ TpProcCpuPowerMgmtInit, ///< 5D .. Power Management table processing
+ TpProcCpuEarlyFeatureInit, ///< 5E .. Early feature dispatch point
+ TpProcCpuCoreLeveling, ///< 5F .. Core Leveling
+ TpProcCpuApMtrrSync, ///< 60 .. AP MTRR sync up
+ TpProcCpuPostFeatureInit, ///< 61 .. POST feature dispatch point
+ TpProcCpuFeatureLeveling, ///< 62 .. CPU Feature Leveling
+ TpProcCpuBeforeAllocateWheaBuffer, ///< 63 .. Before the WHEA init code calls out to allocate a buffer
+ TpProcCpuAfterAllocateWheaBuffer, ///< 64 .. After the WHEA init code calls out to allocate a buffer
+ TpProcCpuBeforeAllocateSratBuffer, ///< 65 .. Before the SRAT init code calls out to allocate a buffer
+ TpProcCpuAfterAllocateSratBuffer, ///< 66 .. After the SRAT init code calls out to allocate a buffer
+ TpProcCpuBeforeLocateSsdtBuffer, ///< 67 .. Before the P-state init code calls out to locate a buffer
+ TpProcCpuAfterLocateSsdtBuffer, ///< 68 .. After the P-state init code calls out to locate a buffer
+ TpProcCpuBeforeAllocateSsdtBuffer, ///< 69 .. Before the P-state init code calls out to allocate a buffer
+ TpProcCpuAfterAllocateSsdtBuffer, ///< 6A .. After the P-state init code calls out to allocate a buffer
+
+ // HT test points
+ TpProcHtEntry = 0x71, ///< 71 .. Coherent Discovery begin (Public interface)
+ TpProcHtTopology, ///< 72 .. Topology match, routing, begin
+ TpProcHtManualNc, ///< 73 .. Manual Non-coherent Init begin
+ TpProcHtAutoNc, ///< 74 .. Automatic Non-coherent init begin
+ TpProcHtOptGather, ///< 75 .. Optimization: Gather begin
+ TpProcHtOptRegang, ///< 76 .. Optimization: Regang begin
+ TpProcHtOptLinks, ///< 77 .. Optimization: Link Begin
+ TpProcHtOptSubLinks, ///< 78 .. Optimization: Sublinks begin
+ TpProcHtOptFinish, ///< 79 .. Optimization: Set begin
+ TpProcHtTrafficDist, ///< 7A .. Traffic Distribution begin
+ TpProcHtTuning, ///< 7B .. Misc Tuning Begin
+ TpProcHtDone, ///< 7C .. HT Init complete
+ TpProcHtApMapEntry, ///< 7D .. AP HT: Init Maps begin
+ TpProcHtApMapDone, ///< 7E .. AP HT: Complete
+
+ StartNbTestPoints = 0x90, ///< 90 Entry used for range testing for @b NorthBridge related TPs
+ TpNbxxx, ///< 91 .
+ EndNbTestPoints, ///< 92 End of TP range for NB
+
+ StartSbTestPoints = 0xB0, ///< B0 Entry used for range testing for @b SouthBridge related TPs
+ TpSbxxx, ///< B1 .
+ EndSbTestPoints, ///< B2 End of TP range for SB
+
+ // Interface test points
+ TpIfAmdInitResetEntry = 0xC0, ///< C0 .. Entry to AmdInitReset
+ TpIfAmdInitResetExit, ///< C1 .. Exiting from AmdInitReset
+ TpIfAmdInitRecoveryEntry, ///< C2 .. Entry to AmdInitRecovery
+ TpIfAmdInitRecoveryExit, ///< C3 .. Exiting from AmdInitRecovery
+ TpIfAmdInitEarlyEntry, ///< C4 .. Entry to AmdInitEarly
+ TpIfAmdInitEarlyExit, ///< C5 .. Exiting from AmdInitEarly
+ TpIfAmdInitPostEntry, ///< C6 .. Entry to AmdInitPost
+ TpIfAmdInitPostExit, ///< C7 .. Exiting from AmdInitPost
+ TpIfAmdInitEnvEntry, ///< C8 .. Entry to AmdInitEnv
+ TpIfAmdInitEnvExit, ///< C9 .. Exiting from AmdInitEnv
+ TpIfAmdInitMidEntry, ///< CA .. Entry to AmdInitMid
+ TpIfAmdInitMidExit, ///< CB .. Exiting from AmdInitMid
+ TpIfAmdInitLateEntry, ///< CC .. Entry to AmdInitLate
+ TpIfAmdInitLateExit, ///< CD .. Exiting from AmdInitLate
+ TpIfAmdS3SaveEntry, ///< CE .. Entry to AmdS3Save
+ TpIfAmdS3SaveExit, ///< CF .. Exiting from AmdS3Save
+ TpIfAmdInitResumeEntry, ///< D0 .. Entry to AmdInitResume
+ TpIfAmdInitResumeExit, ///< D1 .. Exiting from AmdInitResume
+ TpIfAmdS3LateRestoreEntry, ///< D2 .. Entry to AmdS3LateRestore
+ TpIfAmdS3LateRestoreExit, ///< D3 .. Exiting from AmdS3LateRestore
+ TpIfAmdLateRunApTaskEntry, ///< D4 .. Entry to AmdS3LateRestore
+ TpIfAmdLateRunApTaskExit, ///< D5 .. Exiting from AmdS3LateRestore
+ TpIfAmdReadEventLogEntry, ///< D6 .. Entry to AmdReadEventLog
+ TpIfAmdReadEventLogExit, ///< D7 .. Exiting from AmdReadEventLog
+ TpIfAmdGetApicIdEntry, ///< D8 .. Entry to AmdGetApicId
+ TpIfAmdGetApicIdExit, ///< D9 .. Exiting from AmdGetApicId
+ TpIfAmdGetPciAddressEntry, ///< DA .. Entry to AmdGetPciAddress
+ TpIfAmdGetPciAddressExit, ///< DB .. Exiting from AmdGetPciAddress
+ TpIfAmdIdentifyCoreEntry, ///< DC .. Entry to AmdIdentifyCore
+ TpIfAmdIdentifyCoreExit, ///< DD .. Exiting from AmdIdentifyCore
+ TpIfBeforeRunApFromIds, ///< DE .. After IDS calls out to run code on an AP
+ TpIfAfterRunApFromIds, ///< DF .. After IDS calls out to run code on an AP
+ TpIfBeforeGetIdsData, ///< E0 .. Before IDS calls out to get IDS data
+ TpIfAfterGetIdsData, ///< E1 .. After IDS calls out to get IDS data
+ TpIfBeforeAllocateHeapBuffer, ///< E2 .. Before the heap manager calls out to allocate a buffer
+ TpIfAfterAllocateHeapBuffer, ///< E3 .. After the heap manager calls out to allocate a buffer
+ TpIfBeforeDeallocateHeapBuffer, ///< E4 .. Before the heap manager calls out to deallocate a buffer
+ TpIfAfterDeallocateHeapBuffer, ///< E5 .. After the heap manager calls out to deallocate a buffer
+ TpIfBeforeLocateHeapBuffer, ///< E6 .. Before the heap manager calls out to locate a buffer
+ TpIfAfterLocateHeapBuffer, ///< E7 .. After the heap manager calls out to locate a buffer
+ TpIfBeforeRunApFromAllAps, ///< E8 .. Before the BSP calls out to run code on an AP
+ TpIfAfterRunApFromAllAps, ///< E9 .. After the BSP calls out to run code on an AP
+ TpIfBeforeRunApFromAllCore0s, ///< EA .. Before the BSP calls out to run code on an AP
+ TpIfAfterRunApFromAllCore0s, ///< EB .. After the BSP calls out to run code on an AP
+ TpIfBeforeAllocateS3SaveBuffer, ///< EC .. Before the S3 save code calls out to allocate a buffer
+ TpIfAfterAllocateS3SaveBuffer, ///< ED .. After the S3 save code calls out to allocate a buffer
+ TpIfBeforeAllocateMemoryS3SaveBuffer, ///< EE .. Before the memory S3 save code calls out to allocate a buffer
+ TpIfAfterAllocateMemoryS3SaveBuffer, ///< EF .. After the memory S3 save code calls out to allocate a buffer
+ TpIfBeforeLocateS3PciBuffer, ///< F0 .. Before the memory code calls out to locate a buffer
+ TpIfAfterLocateS3PciBuffer, ///< F1 .. After the memory code calls out to locate a buffer
+ TpIfBeforeLocateS3CPciBuffer, ///< F2 .. Before the memory code calls out to locate a buffer
+ TpIfAfterLocateS3CPciBuffer, ///< F3 .. After the memory code calls out to locate a buffer
+ TpIfBeforeLocateS3MsrBuffer, ///< F4 .. Before the memory code calls out to locate a buffer
+ TpIfAfterLocateS3MsrBuffer, ///< F5 .. After the memory code calls out to locate a buffer
+ TpIfBeforeLocateS3CMsrBuffer, ///< F6 .. Before the memory code calls out to locate a buffer
+ TpIfAfterLocateS3CMsrBuffer, ///< F7 .. After the memory code calls out to locate a buffer
+ TpPerfUnit, ///< F8 .. The Unit of performance measure.
+ EndAgesaTps = 0xFF, ///< Last defined AGESA TP
+} AGESA_TP;
+
+///Ids Feat description
+typedef enum {
+ IDS_FEAT_UCODE_UPDATE = 0x0000, ///< Feat for Ucode Update
+ IDS_FEAT_TARGET_PSTATE, ///< Feat for Target Pstate
+ IDS_FEAT_POSTPSTATE, ///< Feat for Post Pstate
+ IDS_FEAT_ECC_CTRL, ///< Feat for Ecc Control
+ IDS_FEAT_ECC_SYMBOL_SIZE, ///< Feat for Ecc symbol size
+ IDS_FEAT_DCT_ALLMEMCLK, ///< Feat for all memory clock
+ IDS_FEAT_DCT_GANGMODE, ///< Feat for Dct gang mode
+ IDS_FEAT_DCT_BURSTLENGTH, ///< Feat for dct burst length
+ IDS_FEAT_DCT_POWERDOWN, ///< Feat for dct power down
+ IDS_FEAT_DCT_DLLSHUTDOWN, ///< Feat for dct dll shut down
+ IDS_FEAT_PROBE_FILTER, ///< Feat for probe filter
+ IDS_FEAT_HDTOUT, ///< Feat for hdt out
+ IDS_FEAT_HT_SETTING, ///< Feat for Ht setting
+ IDS_FEAT_GNB_PLATFORMCFG, ///< Feat for override GNB platform config
+ IDS_FEAT_CPB_CTRL, ///< Feat for Config the Core peformance boost feature
+ IDS_FEAT_HTC_CTRL, ///< Feat for Hardware Thermal Control
+ IDS_FEAT_MEMORY_MAPPING, ///< Feat for Memory Mapping
+ IDS_FEAT_POWER_POLICY, ///< Feat for Power Policy
+ IDS_FEAT_END = 0xFF ///< End of Common feat
+} IDS_FEAT;
+
+typedef IDS_STATUS IDS_COMMON_FUNC (
+ IN OUT VOID *DataPtr,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader,
+ IN IDS_NV_ITEM *IdsNvPtr
+ );
+
+typedef IDS_COMMON_FUNC *PIDS_COMMON_FUNC;
+
+/// Data Structure of IDS Feature block
+typedef struct _IDS_FEAT_STRUCT {
+ IDS_FEAT IdsFeat; ///< Ids Feat ID
+ BOOLEAN IsBsp; ///< swith for Bsp check
+ AGESA_IDS_OPTION IdsOption; ///< IDS option
+ UINT64 CpuFamily; ///<
+ PIDS_COMMON_FUNC pf_idsoption; ///<pointer to function
+} IDS_FEAT_STRUCT;
+
+
+/// Data Structure of IDS option
+typedef struct _IDS_OPTION_STRUCT {
+ AGESA_IDS_OPTION idsoption; ///< IDS option
+ PIDS_COMMON_FUNC pf_idsoption; ///<pointer to function
+} IDS_OPTION_STRUCT;
+
+/// Data Structure of IDS option table
+typedef struct _IDS_OPTION_STRUCT_TBL {
+ UINT8 version; ///<Version of IDS option table
+ UINT16 size; ///<Size of IDS option table
+ CONST IDS_OPTION_STRUCT *pIdsOptionStruct; ///<pointer to array of structure
+} IDS_OPTION_STRUCT_TBL;
+
+#endif // _IDS_H_
diff --git a/src/vendorcode/amd/agesa/f14/Include/IdsHt.h b/src/vendorcode/amd/agesa/f14/Include/IdsHt.h
new file mode 100644
index 0000000..02be40b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Include/IdsHt.h
@@ -0,0 +1,126 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD IDS HyperTransport Definitions
+ *
+ * Contains AMD AGESA Integrated Debug HT related items.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: IDS
+ * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _IDS_HT_H_
+#define _IDS_HT_H_
+
+// Frequency equates for call backs which take an actual frequency setting
+#define HT_FREQUENCY_200M 0
+#define HT_FREQUENCY_400M 2
+#define HT_FREQUENCY_600M 4
+#define HT_FREQUENCY_800M 5
+#define HT_FREQUENCY_1000M 6
+#define HT_FREQUENCY_1200M 7
+#define HT_FREQUENCY_1400M 8
+#define HT_FREQUENCY_1600M 9
+#define HT_FREQUENCY_1800M 10
+#define HT_FREQUENCY_2000M 11
+#define HT_FREQUENCY_2200M 12
+#define HT_FREQUENCY_2400M 13
+#define HT_FREQUENCY_2600M 14
+#define HT_FREQUENCY_2800M 17
+#define HT_FREQUENCY_3000M 18
+#define HT_FREQUENCY_3200M 19
+#define HT_FREQUENCY_3600M 20
+
+/**
+ * HT IDS: HT Link Port Override params.
+ *
+ * Provide an absolute override of HT Link Port settings. No checking is done that
+ * the settings obey limits or capabilities, this responsibility rests with the user.
+ *
+ * Rules for values of structure items:
+ * - Socket
+ * - HT_LIST_TERMINAL == end of port override list, rest of item is not accessed
+ * - HT_LIST_MATCH_ANY == Match Any Socket
+ * - 0 .. 7 == The matching socket
+ * - Link
+ * - HT_LIST_MATCH_ANY == Match Any package link (that is not the internal links)
+ * - HT_LIST_MATCH_INTERNAL_LINK == Match the internal links
+ * - 0 .. 7 == The matching package link. 0 .. 3 are the ganged links or sublink 0's, 4 .. 7 are the sublink1's.
+ * - Frequency
+ * - HT_LIST_TERMINAL == Do not override the frequency, AUTO setting
+ * - HT_FREQUENCY_200M .. HT_FREQUENCY_3600M = The frequency value to use
+ * - Widthin
+ * - HT_LIST_TERMINAL == Do not override the width, AUTO setting
+ * - 2, 4, 8, 16, 32 == The width value to use
+ * - Widthout
+ * - HT_LIST_TERMINAL == Do not override the width, AUTO setting
+ * - 2, 4, 8, 16, 32 == The width value to use
+ */
+typedef struct {
+ // Match Fields
+ UINT8 Socket; ///< The Socket which this port is on.
+ UINT8 Link; ///< The port for this package link on that socket.
+ // Override fields
+ UINT8 Frequency; ///< Absolutely override the port's frequency.
+ UINT8 WidthIn; ///< Absolutely override the port's width.
+ UINT8 WidthOut; ///< Absolutely override the port's width.
+} HTIDS_PORT_OVERRIDE;
+
+/**
+ * A list of port overrides to search.
+ */
+typedef HTIDS_PORT_OVERRIDE *HTIDS_PORT_OVERRIDE_LIST;
+VOID
+HtIdsGetPortOverride (
+ IN BOOLEAN IsSourcePort,
+ IN OUT PORT_DESCRIPTOR *Port0,
+ IN OUT PORT_DESCRIPTOR *Port1,
+ IN OUT HTIDS_PORT_OVERRIDE_LIST *PortOverrideList,
+ IN STATE_DATA *State
+ );
+
+typedef
+VOID
+F_HtIdsGetPortOverride (
+ IN BOOLEAN IsSourcePort,
+ IN OUT PORT_DESCRIPTOR *Port0,
+ IN OUT PORT_DESCRIPTOR *Port1,
+ IN OUT HTIDS_PORT_OVERRIDE_LIST *PortOverrideList,
+ IN STATE_DATA *State
+ );
+typedef F_HtIdsGetPortOverride* PF_HtIdsGetPortOverride;
+#endif // _IDS_HT_H
diff --git a/src/vendorcode/amd/agesa/f14/Include/LynxInstall.h b/src/vendorcode/amd/agesa/f14/Include/LynxInstall.h
new file mode 100644
index 0000000..02338f9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Include/LynxInstall.h
@@ -0,0 +1,102 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build options for a Lynx platform solution
+ *
+ * This file generates the defaults tables for the "Lynx" platform solution
+ * set of processors. The documented build options are imported from a user
+ * controlled file for processing.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Core
+ * @e \$Revision: 37651 $ @e \$Date: 2010-09-09 07:05:06 +0800 (Thu, 09 Sep 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "AdvancedApi.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "cpuFeatures.h"
+#include "Table.h"
+#include "CommonReturns.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "GnbInterface.h"
+
+/*****************************************************************************
+ * Define the RELEASE VERSION string
+ *
+ * The Release Version string should identify the next planned release.
+ * When a branch is made in preparation for a release, the release manager
+ * should change/confirm that the branch version of this file contains the
+ * string matching the desired version for the release. The trunk version of
+ * the file should always contain a trailing 'X'. This will make sure that a
+ * development build from trunk will not be confused for a released version.
+ * The release manager will need to remove the trailing 'X' and update the
+ * version string as appropriate for the release. The trunk copy of this file
+ * should also be updated/incremented for the next expected version, + trailing 'X'
+ ****************************************************************************/
+ // This is the delivery package title, "LlanoPI "
+ // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING {'L', 'l', 'a', 'n', 'o', 'P', 'I', ' '}
+
+ // This is the release version number of the AGESA component
+ // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '6', '.', '0', 'X', ' ', ' ', ' '}
+
+
+// The Lynx solution is defined to be family 0x12 in the FM1 socket.
+#define INSTALL_FM1_SOCKET_SUPPORT TRUE
+#define INSTALL_FAMILY_12_SUPPORT TRUE
+
+
+// The following definitions specify the default values for various parameters in which there are
+// no clearly defined defaults to be used in the common file. The values below are based on product
+// and BKDG content, please consult the AGESA Memory team for consultation.
+#define DFLT_SCRUB_DRAM_RATE (0)
+#define DFLT_SCRUB_L2_RATE (0)
+#define DFLT_SCRUB_L3_RATE (0)
+#define DFLT_SCRUB_IC_RATE (0)
+#define DFLT_SCRUB_DC_RATE (0)
+#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
+#define DFLT_VRM_SLEW_RATE (5000)
+
+
+// Instantiate all solution relevant data.
+#include "PlatformInstall.h"
+
diff --git a/src/vendorcode/amd/agesa/f14/Include/MaranelloInstall.h b/src/vendorcode/amd/agesa/f14/Include/MaranelloInstall.h
new file mode 100644
index 0000000..881f32b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Include/MaranelloInstall.h
@@ -0,0 +1,118 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build options for a Maranello platform solution
+ *
+ * This file generates the defaults tables for the "Maranello" platform solution
+ * set of processors. The documented build options are imported from a user
+ * controlled file for processing.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Core
+ * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "AdvancedApi.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "cpuFeatures.h"
+#include "Table.h"
+#include "CommonReturns.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "GnbInterfaceStub.h"
+
+/*****************************************************************************
+ * Define the RELEASE VERSION string
+ *
+ * The Release Version string should identify the next planned release.
+ * When a branch is made in preparation for a release, the release manager
+ * should change/confirm that the branch version of this file contains the
+ * string matching the desired version for the release. The trunk version of
+ * the file should always contain a trailing 'X'. This will make sure that a
+ * development build from trunk will not be confused for a released version.
+ * The release manager will need to remove the trailing 'X' and update the
+ * version string as appropriate for the release. The trunk copy of this file
+ * should also be updated/incremented for the next expected version, + trailing 'X'
+ ****************************************************************************/
+ // This is the delivery package title, "MarG34PI"
+ // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING {'O', 'r', 'o', 'c', 'h', 'i', 'P', 'I'}
+
+ // This is the release version number of the AGESA component
+ // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '6', '.', '0', 'X', ' ', ' ', ' '}
+
+
+
+// The Maranello solution is defined to be families 0x10 and 0x15 in the G34 socket.
+#define INSTALL_G34_SOCKET_SUPPORT TRUE
+#define INSTALL_FAMILY_10_SUPPORT TRUE
+#define INSTALL_FAMILY_15_SUPPORT TRUE
+
+#ifdef BLDOPT_REMOVE_FAMILY_10_SUPPORT
+ #if BLDOPT_REMOVE_FAMILY_10_SUPPORT == TRUE
+ #undef INSTALL_FAMILY_10_SUPPORT
+ #define INSTALL_FAMILY_10_SUPPORT FALSE
+ #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_FAMILY_15_SUPPORT
+ #if BLDOPT_REMOVE_FAMILY_15_SUPPORT == TRUE
+ #undef INSTALL_FAMILY_15_SUPPORT
+ #define INSTALL_FAMILY_15_SUPPORT FALSE
+ #endif
+#endif
+
+
+// The following definitions specify the default values for various parameters in which there are
+// no clearly defined defaults to be used in the common file. The values below are based on product
+// and BKDG content, please consult the AGESA Memory team for consultation.
+#define DFLT_SCRUB_DRAM_RATE (0xFF)
+#define DFLT_SCRUB_L2_RATE (0x10)
+#define DFLT_SCRUB_L3_RATE (0x10)
+#define DFLT_SCRUB_IC_RATE (0)
+#define DFLT_SCRUB_DC_RATE (0x12)
+#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
+#define DFLT_VRM_SLEW_RATE (2500)
+
+
+// Instantiate all solution relevant data.
+#include "PlatformInstall.h"
+
diff --git a/src/vendorcode/amd/agesa/f14/Include/NileInstall.h b/src/vendorcode/amd/agesa/f14/Include/NileInstall.h
new file mode 100644
index 0000000..dac582e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Include/NileInstall.h
@@ -0,0 +1,102 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build options for a Nile platform solution
+ *
+ * This file generates the defaults tables for the "Nile" platform solution
+ * set of processors. The documented build options are imported from a user
+ * controlled file for processing.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Core
+ * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "AdvancedApi.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "cpuFeatures.h"
+#include "Table.h"
+#include "CommonReturns.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "GnbInterfaceStub.h"
+
+/*****************************************************************************
+ * Define the RELEASE VERSION string
+ *
+ * The Release Version string should identify the next planned release.
+ * When a branch is made in preparation for a release, the release manager
+ * should change/confirm that the branch version of this file contains the
+ * string matching the desired version for the release. The trunk version of
+ * the file should always contain a trailing 'X'. This will make sure that a
+ * development build from trunk will not be confused for a released version.
+ * The release manager will need to remove the trailing 'X' and update the
+ * version string as appropriate for the release. The trunk copy of this file
+ * should also be updated/incremented for the next expected version, + trailing 'X'
+ ****************************************************************************/
+ // This is the delivery package title, "DanNiPI "
+ // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING {'D', 'a', 'n', 'N', 'i', 'P', 'I', ' '}
+
+ // This is the release version number of the AGESA component
+ // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '5', '.', '0', 'X', ' ', ' ', ' '}
+
+
+// The Nile solution is defined to be family 0x10 in the ASB2 socket.
+#define INSTALL_ASB2_SOCKET_SUPPORT TRUE
+#define INSTALL_FAMILY_10_SUPPORT TRUE
+
+
+// The following definitions specify the default values for various parameters in which there are
+// no clearly defined defaults to be used in the common file. The values below are based on product
+// and BKDG content, please consult the AGESA Memory team for consultation.
+#define DFLT_SCRUB_DRAM_RATE (0)
+#define DFLT_SCRUB_L2_RATE (0)
+#define DFLT_SCRUB_L3_RATE (0)
+#define DFLT_SCRUB_IC_RATE (0)
+#define DFLT_SCRUB_DC_RATE (0)
+#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
+#define DFLT_VRM_SLEW_RATE (5000)
+
+
+// Instantiate all solution relevant data.
+#include "PlatformInstall.h"
+
diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionC6Install.h b/src/vendorcode/amd/agesa/f14/Include/OptionC6Install.h
new file mode 100644
index 0000000..a7cc69f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Include/OptionC6Install.h
@@ -0,0 +1,151 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: C6 C-state
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Options
+ * @e \$Revision: 37456 $ @e \$Date: 2010-09-04 04:17:05 +0800 (Sat, 04 Sep 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _OPTION_C6_STATE_INSTALL_H_
+#define _OPTION_C6_STATE_INSTALL_H_
+
+#include "cpuC6State.h"
+
+/* This option is designed to be included into the platform solution install
+ * file. The platform solution install file will define the options status.
+ * Check to validate the definition
+ */
+#define OPTION_C6_STATE_FEAT
+#define F12_C6_STATE_SUPPORT
+#define F14_C6_STATE_SUPPORT
+#define F15_C6_STATE_SUPPORT
+
+#if OPTION_C6_STATE == TRUE
+ #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
+ #ifdef OPTION_FAMILY12H
+ #if OPTION_FAMILY12H == TRUE
+ #if OPTION_FAMILY12H_LN == TRUE
+ extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
+ #undef OPTION_C6_STATE_FEAT
+ #define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
+ extern CONST C6_FAMILY_SERVICES ROMDATA F12C6Support;
+ #undef F12_C6_STATE_SUPPORT
+ #define F12_C6_STATE_SUPPORT {AMD_FAMILY_12_LN, &F12C6Support},
+
+ #if OPTION_EARLY_SAMPLES == TRUE
+ extern F_F12_ES_C6_INIT F12C6A0Workaround;
+
+ CONST F12_ES_C6_SUPPORT ROMDATA F12EarlySampleC6Support =
+ {
+ F12C6A0Workaround
+ };
+ #else
+ CONST F12_ES_C6_SUPPORT ROMDATA F12EarlySampleC6Support =
+ {
+ (PF_F12_ES_C6_INIT) CommonVoid
+ };
+ #endif
+
+ #endif
+ #endif
+ #endif
+
+ #ifdef OPTION_FAMILY14H
+ #if OPTION_FAMILY14H == TRUE
+ #if OPTION_FAMILY14H_ON == TRUE
+ extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
+ #undef OPTION_C6_STATE_FEAT
+ #define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
+ extern CONST C6_FAMILY_SERVICES ROMDATA F14C6Support;
+ #undef F14_C6_STATE_SUPPORT
+ #define F14_C6_STATE_SUPPORT {AMD_FAMILY_14_ON, &F14C6Support},
+
+ #if OPTION_EARLY_SAMPLES == TRUE
+ extern F_F14_ES_IS_C6_SUPPORTED F14IsC6DisabledEarlySample;
+ extern F_F14_ES_C6_INIT F14C6A0Workaround;
+
+ CONST F14_ES_C6_SUPPORT ROMDATA F14EarlySampleC6Support =
+ {
+ F14IsC6DisabledEarlySample,
+ F14C6A0Workaround
+ };
+ #else
+ CONST F14_ES_C6_SUPPORT ROMDATA F14EarlySampleC6Support =
+ {
+ (PF_F14_ES_IS_C6_SUPPORTED) CommonVoid,
+ (PF_F14_ES_C6_INIT) CommonVoid
+ };
+ #endif
+
+ #endif
+ #endif
+ #endif
+
+ #ifdef OPTION_FAMILY15H
+ #if OPTION_FAMILY15H == TRUE
+ #if OPTION_FAMILY15H_OR == TRUE
+ extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
+ #undef OPTION_C6_STATE_FEAT
+ #define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
+ extern CONST C6_FAMILY_SERVICES ROMDATA F15C6Support;
+ #undef F15_C6_STATE_SUPPORT
+ #define F15_C6_STATE_SUPPORT {AMD_FAMILY_15_OR, &F15C6Support},
+ #endif
+ #endif
+ #endif
+ #endif
+#endif
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA C6FamilyServiceArray[] =
+{
+ F12_C6_STATE_SUPPORT
+ F14_C6_STATE_SUPPORT
+ F15_C6_STATE_SUPPORT
+ {0, NULL}
+};
+
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA C6FamilyServiceTable =
+{
+ (sizeof (C6FamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+ &C6FamilyServiceArray[0]
+};
+
+#endif // _OPTION_C6_STATE_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionCpbInstall.h b/src/vendorcode/amd/agesa/f14/Include/OptionCpbInstall.h
new file mode 100644
index 0000000..45f8498
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Include/OptionCpbInstall.h
@@ -0,0 +1,122 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: Core Performance Boost
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Options
+ * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _OPTION_CPB_INSTALL_H_
+#define _OPTION_CPB_INSTALL_H_
+
+#include "cpuCpb.h"
+
+/* This option is designed to be included into the platform solution install
+ * file. The platform solution install file will define the options status.
+ * Check to validate the definition
+ */
+#define OPTION_CPB_FEAT
+#define F10_CPB_SUPPORT
+#define F12_CPB_SUPPORT
+#define F15_CPB_SUPPORT
+
+#if OPTION_CPB == TRUE
+ #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
+ // Family 10h
+ #ifdef OPTION_FAMILY10H
+ #if OPTION_FAMILY10H == TRUE
+ #if OPTION_FAMILY10H_PH == TRUE
+ extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
+ #undef OPTION_CPB_FEAT
+ #define OPTION_CPB_FEAT &CpuFeatureCpb,
+ extern CONST CPB_FAMILY_SERVICES ROMDATA F10CpbSupport;
+ #undef F10_CPB_SUPPORT
+ #define F10_CPB_SUPPORT {AMD_FAMILY_10_PH, &F10CpbSupport},
+ #endif
+ #endif
+ #endif
+
+ // Family 12h
+ #ifdef OPTION_FAMILY12H
+ #if OPTION_FAMILY12H == TRUE
+ #if OPTION_FAMILY12H_LN == TRUE
+ extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
+ #undef OPTION_CPB_FEAT
+ #define OPTION_CPB_FEAT &CpuFeatureCpb,
+ extern CONST CPB_FAMILY_SERVICES ROMDATA F12CpbSupport;
+ #undef F12_CPB_SUPPORT
+ #define F12_CPB_SUPPORT {AMD_FAMILY_12_LN, &F12CpbSupport},
+ #endif
+ #endif
+ #endif
+
+ // Family 15h
+ #ifdef OPTION_FAMILY15H
+ #if OPTION_FAMILY15H == TRUE
+ #if OPTION_FAMILY15H_OR == TRUE
+ extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
+ #undef OPTION_CPB_FEAT
+ #define OPTION_CPB_FEAT &CpuFeatureCpb,
+ extern CONST CPB_FAMILY_SERVICES ROMDATA F15CpbSupport;
+ #undef F15_CPB_SUPPORT
+ #define F15_CPB_SUPPORT {AMD_FAMILY_15_OR, &F15CpbSupport},
+ #endif
+ #endif
+ #endif
+
+ #endif
+#endif
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpbFamilyServiceArray[] =
+{
+ F10_CPB_SUPPORT
+ F12_CPB_SUPPORT
+ F15_CPB_SUPPORT
+ {0, NULL}
+};
+
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CpbFamilyServiceTable =
+{
+ (sizeof (CpbFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+ &CpbFamilyServiceArray[0]
+};
+
+#endif // _OPTION_CPB_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionCpuCacheFlushOnHaltInstall.h b/src/vendorcode/amd/agesa/f14/Include/OptionCpuCacheFlushOnHaltInstall.h
new file mode 100644
index 0000000..87aea08
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Include/OptionCpuCacheFlushOnHaltInstall.h
@@ -0,0 +1,120 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: CPU Cache Flush On Halt
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Options
+ * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
+#define _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
+
+#include "cpuPostInit.h"
+
+/* This option is designed to be included into the platform solution install
+ * file. The platform solution install file will define the options status.
+ * Check to validate the definition
+ */
+#define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
+#define F10_BL_CPU_CFOH_SUPPORT
+#define F10_DA_CPU_CFOH_SUPPORT
+#define F10_CPU_CFOH_SUPPORT
+#define F15_OR_CPU_CFOH_SUPPORT
+
+#if OPTION_CPU_CFOH == TRUE
+ #if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
+ #ifdef OPTION_FAMILY10H
+ #if OPTION_FAMILY10H == TRUE
+ extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt;
+ #undef OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
+ #define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT &CpuFeatureCacheFlushOnHalt,
+
+ #if OPTION_FAMILY10H_BL == TRUE
+ extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10BlCacheFlushOnHalt;
+ #undef F10_BL_CPU_CFOH_SUPPORT
+ #define F10_BL_CPU_CFOH_SUPPORT {AMD_FAMILY_10_BL, &F10BlCacheFlushOnHalt},
+ #endif
+
+ #if OPTION_FAMILY10H_DA == TRUE
+ extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10DaCacheFlushOnHalt;
+ #undef F10_DA_CPU_CFOH_SUPPORT
+ #define F10_DA_CPU_CFOH_SUPPORT {AMD_FAMILY_10_DA, &F10DaCacheFlushOnHalt},
+ #endif
+
+ #if (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_HY == TRUE) || (OPTION_FAMILY10H_PH == TRUE)
+ extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10CacheFlushOnHalt;
+ #undef F10_CPU_CFOH_SUPPORT
+ #define F10_CPU_CFOH_SUPPORT {AMD_FAMILY_10_RB | AMD_FAMILY_10_HY | AMD_FAMILY_10_PH, &F10CacheFlushOnHalt},
+ #endif
+ #endif
+ #endif
+
+ #ifdef OPTION_FAMILY15H
+ #if OPTION_FAMILY15H == TRUE
+ extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt;
+ #undef OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
+ #define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT &CpuFeatureCacheFlushOnHalt,
+
+ #if OPTION_FAMILY15H_OR == TRUE
+ extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F15CacheFlushOnHalt;
+ #undef F15_OR_CPU_CFOH_SUPPORT
+ #define F15_OR_CPU_CFOH_SUPPORT {AMD_FAMILY_15_OR, &F15CacheFlushOnHalt},
+ #endif
+ #endif
+ #endif
+ #endif
+#endif
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CacheFlushOnHaltFamilyServiceArray[] =
+{
+ F10_BL_CPU_CFOH_SUPPORT
+ F10_DA_CPU_CFOH_SUPPORT
+ F10_CPU_CFOH_SUPPORT
+ F15_OR_CPU_CFOH_SUPPORT
+ {0, NULL}
+};
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CacheFlushOnHaltFamilyServiceTable =
+{
+ (sizeof (CacheFlushOnHaltFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+ &CacheFlushOnHaltFamilyServiceArray[0]
+};
+
+#endif // _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionCpuCoreLevelingInstall.h b/src/vendorcode/amd/agesa/f14/Include/OptionCpuCoreLevelingInstall.h
new file mode 100644
index 0000000..b49bef1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Include/OptionCpuCoreLevelingInstall.h
@@ -0,0 +1,115 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: CPU Core Leveling
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Options
+ * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _OPTION_CPU_CORELEVELING_INSTALL_H_
+#define _OPTION_CPU_CORELEVELING_INSTALL_H_
+
+
+/* This option is designed to be included into the platform solution install
+ * file. The platform solution install file will define the options status.
+ * Check to validate the definition
+ */
+#define OPTION_CPU_CORE_LEVELING_FEAT
+#define F10_REVE_CPU_CORELEVELING_SUPPORT
+#define F10_REVD_CPU_CORELEVELING_SUPPORT
+#define F10_REVC_CPU_CORELEVELING_SUPPORT
+#define F15_CPU_CORELEVELING_SUPPORT
+
+#if OPTION_CPU_CORELEVLING == TRUE
+ #if (AGESA_ENTRY_INIT_EARLY == TRUE)
+ // Family 10h
+ #if OPTION_FAMILY10H == TRUE
+ extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling;
+ #undef OPTION_CPU_CORE_LEVELING_FEAT
+ #define OPTION_CPU_CORE_LEVELING_FEAT &CpuFeatureCoreLeveling,
+ #if OPTION_FAMILY10H == TRUE
+ #if OPTION_FAMILY10H_HY == TRUE
+ extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevDCoreLeveling;
+ #undef F10_REVD_CPU_CORELEVELING_SUPPORT
+ #define F10_REVD_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_HY, &F10RevDCoreLeveling},
+ #endif
+
+ #if (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE)
+ extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevCCoreLeveling;
+ #undef F10_REVC_CPU_CORELEVELING_SUPPORT
+ #define F10_REVC_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_RB | AMD_FAMILY_10_BL | AMD_FAMILY_10_DA, &F10RevCCoreLeveling},
+ #endif
+
+ #if (OPTION_FAMILY10H_PH == TRUE)
+ extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevECoreLeveling;
+ #undef F10_REVE_CPU_CORELEVELING_SUPPORT
+ #define F10_REVE_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_PH, &F10RevECoreLeveling},
+ #endif
+ #endif
+ #endif
+ // Family 15h
+ #if OPTION_FAMILY15H == TRUE
+ extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling;
+ #undef OPTION_CPU_CORE_LEVELING_FEAT
+ #define OPTION_CPU_CORE_LEVELING_FEAT &CpuFeatureCoreLeveling,
+
+ extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F15CoreLeveling;
+ #undef F15_CPU_CORELEVELING_SUPPORT
+ #define F15_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_15, &F15CoreLeveling},
+ #endif
+ #endif
+#endif
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CoreLevelingFamilyServiceArray[] =
+{
+ F10_REVE_CPU_CORELEVELING_SUPPORT
+ F10_REVD_CPU_CORELEVELING_SUPPORT
+ F10_REVC_CPU_CORELEVELING_SUPPORT
+ F15_CPU_CORELEVELING_SUPPORT
+ {0, NULL}
+};
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CoreLevelingFamilyServiceTable =
+{
+ (sizeof (CoreLevelingFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+ &CoreLevelingFamilyServiceArray[0]
+};
+
+#endif // _OPTION_CPU_CORELEVELING_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionCpuFamiliesInstall.h b/src/vendorcode/amd/agesa/f14/Include/OptionCpuFamiliesInstall.h
new file mode 100644
index 0000000..44c1796
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Include/OptionCpuFamiliesInstall.h
@@ -0,0 +1,406 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of all appropriate CPU family specific support.
+ *
+ * This file generates the defaults tables for all family specific
+ * combinations.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Core
+ * @e \$Revision: 37640 $ @e \$Date: 2010-09-08 23:01:59 +0800 (Wed, 08 Sep 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+/* Default all CPU Specific Service members to off. They
+ will be enabled as needed by cross referencing families
+ with entry points in the family / model install files. */
+#define GET_PSTATE_POWER FALSE
+#define GET_PSTATE_FREQ FALSE
+#define DISABLE_PSTATE FALSE
+#define TRANSITION_PSTATE FALSE
+#define PROC_IDD_MAX FALSE
+#define GET_TSC_RATE FALSE
+#define PSTATE_TRANSITION_LATENCY FALSE
+#define GET_PSTATE_REGISTER_INFO FALSE
+#define GET_PSTATE_MAX_STATE FALSE
+#define SET_PSTATE_LEVELING_REG FALSE
+#define GET_NB_FREQ FALSE
+#define IS_NBCOF_INIT_NEEDED FALSE
+#define AP_INITIAL_LAUNCH FALSE
+#define GET_AP_MAILBOX_FROM_HW FALSE
+#define SET_AP_CORE_NUMBER FALSE
+#define GET_AP_CORE_NUMBER FALSE
+#define TRANSFER_AP_CORE_NUMBER FALSE
+#define ID_POSITION_INITIAL_APICID FALSE
+#define SAVE_FEATURES FALSE
+#define WRITE_FEATURES FALSE
+#define SET_DOWN_CORE_REG FALSE
+#define SET_WARM_RESET_FLAG FALSE
+#define GET_WARM_RESET_FLAG FALSE
+#define USES_REGISTER_TABLES FALSE
+#define BASE_FAMILY_PCI FALSE
+#define MODEL_SPECIFIC_PCI FALSE
+#define BASE_FAMILY_MSR FALSE
+#define MODEL_SPECIFIC_MSR FALSE
+#define BRAND_STRING1 FALSE
+#define BRAND_STRING2 FALSE
+#define BASE_FAMILY_HT_PCI FALSE
+#define MODEL_SPECIFIC_HT_PCI FALSE
+#define BASE_FAMILY_WORKAROUNDS FALSE
+#define GET_PATCHES FALSE
+#define GET_PATCHES_EQUIVALENCE_TABLE FALSE
+#define GET_CACHE_INFO FALSE
+#define GET_SYSTEM_PM_TABLE FALSE
+#define GET_WHEA_INIT FALSE
+#define GET_CFOH_REG FALSE
+#define GET_PLATFORM_TYPE_SPECIFIC_INFO FALSE
+#define IS_NB_PSTATE_ENABLED FALSE
+
+/*
+ * Pull in family specific services based on entry point
+ */
+#if AGESA_ENTRY_INIT_RESET == TRUE
+ #undef ID_POSITION_INITIAL_APICID
+ #define ID_POSITION_INITIAL_APICID TRUE
+ #undef GET_AP_MAILBOX_FROM_HW
+ #define GET_AP_MAILBOX_FROM_HW TRUE
+ #undef SET_WARM_RESET_FLAG
+ #define SET_WARM_RESET_FLAG TRUE
+ #undef GET_WARM_RESET_FLAG
+ #define GET_WARM_RESET_FLAG TRUE
+ #undef GET_CACHE_INFO
+ #define GET_CACHE_INFO TRUE
+ #undef GET_AP_CORE_NUMBER
+ #define GET_AP_CORE_NUMBER TRUE
+ #undef TRANSFER_AP_CORE_NUMBER
+ #define TRANSFER_AP_CORE_NUMBER TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_RECOVERY == TRUE
+ #undef ID_POSITION_INITIAL_APICID
+ #define ID_POSITION_INITIAL_APICID TRUE
+ #undef USES_REGISTER_TABLES
+ #define USES_REGISTER_TABLES TRUE
+ #undef BASE_FAMILY_PCI
+ #define BASE_FAMILY_PCI TRUE
+ #undef MODEL_SPECIFIC_PCI
+ #define MODEL_SPECIFIC_PCI TRUE
+ #undef BASE_FAMILY_MSR
+ #define BASE_FAMILY_MSR TRUE
+ #undef MODEL_SPECIFIC_MSR
+ #define MODEL_SPECIFIC_MSR TRUE
+ #undef GET_CACHE_INFO
+ #define GET_CACHE_INFO TRUE
+ #undef GET_PLATFORM_TYPE_SPECIFIC_INFO
+ #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
+ #undef IS_NB_PSTATE_ENABLED
+ #define IS_NB_PSTATE_ENABLED TRUE
+ #undef GET_PATCHES
+ #define GET_PATCHES TRUE
+ #undef GET_PATCHES_EQUIVALENCE_TABLE
+ #define GET_PATCHES_EQUIVALENCE_TABLE TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_EARLY == TRUE
+ #undef TRANSITION_PSTATE
+ #define TRANSITION_PSTATE TRUE
+ #undef DISABLE_PSTATE
+ #define DISABLE_PSTATE TRUE
+ #undef PROC_IDD_MAX
+ #define PROC_IDD_MAX TRUE
+ #undef GET_TSC_RATE
+ #define GET_TSC_RATE TRUE
+ #undef GET_NB_FREQ
+ #define GET_NB_FREQ TRUE
+ #undef IS_NBCOF_INIT_NEEDED
+ #define IS_NBCOF_INIT_NEEDED TRUE
+ #undef AP_INITIAL_LAUNCH
+ #define AP_INITIAL_LAUNCH TRUE
+ #undef GET_AP_MAILBOX_FROM_HW
+ #define GET_AP_MAILBOX_FROM_HW TRUE
+ #undef SET_AP_CORE_NUMBER
+ #define SET_AP_CORE_NUMBER TRUE
+ #undef GET_AP_CORE_NUMBER
+ #define GET_AP_CORE_NUMBER TRUE
+ #undef TRANSFER_AP_CORE_NUMBER
+ #define TRANSFER_AP_CORE_NUMBER TRUE
+ #undef ID_POSITION_INITIAL_APICID
+ #define ID_POSITION_INITIAL_APICID TRUE
+ #undef SET_DOWN_CORE_REG
+ #define SET_DOWN_CORE_REG TRUE
+ #undef SET_WARM_RESET_FLAG
+ #define SET_WARM_RESET_FLAG TRUE
+ #undef GET_WARM_RESET_FLAG
+ #define GET_WARM_RESET_FLAG TRUE
+ #undef USES_REGISTER_TABLES
+ #define USES_REGISTER_TABLES TRUE
+ #undef BASE_FAMILY_PCI
+ #define BASE_FAMILY_PCI TRUE
+ #undef MODEL_SPECIFIC_PCI
+ #define MODEL_SPECIFIC_PCI TRUE
+ #undef BASE_FAMILY_MSR
+ #define BASE_FAMILY_MSR TRUE
+ #undef MODEL_SPECIFIC_MSR
+ #define MODEL_SPECIFIC_MSR TRUE
+ #undef BRAND_STRING1
+ #define BRAND_STRING1 TRUE
+ #undef BRAND_STRING2
+ #define BRAND_STRING2 TRUE
+ #undef BASE_FAMILY_HT_PCI
+ #define BASE_FAMILY_HT_PCI TRUE
+ #undef MODEL_SPECIFIC_HT_PCI
+ #define MODEL_SPECIFIC_HT_PCI TRUE
+ #undef BASE_FAMILY_WORKAROUNDS
+ #define BASE_FAMILY_WORKAROUNDS TRUE
+ #undef GET_PATCHES
+ #define GET_PATCHES TRUE
+ #undef GET_PATCHES_EQUIVALENCE_TABLE
+ #define GET_PATCHES_EQUIVALENCE_TABLE TRUE
+ #undef GET_SYSTEM_PM_TABLE
+ #define GET_SYSTEM_PM_TABLE TRUE
+ #undef GET_CACHE_INFO
+ #define GET_CACHE_INFO TRUE
+ #undef GET_PLATFORM_TYPE_SPECIFIC_INFO
+ #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
+ #undef IS_NB_PSTATE_ENABLED
+ #define IS_NB_PSTATE_ENABLED TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_POST == TRUE
+ #undef ID_POSITION_INITIAL_APICID
+ #define ID_POSITION_INITIAL_APICID TRUE
+ #undef GET_PSTATE_POWER
+ #define GET_PSTATE_POWER TRUE
+ #undef GET_PSTATE_FREQ
+ #define GET_PSTATE_FREQ TRUE
+ #undef TRANSITION_PSTATE
+ #define TRANSITION_PSTATE TRUE
+ #undef PROC_IDD_MAX
+ #define PROC_IDD_MAX TRUE
+ #undef GET_AP_CORE_NUMBER
+ #define GET_AP_CORE_NUMBER TRUE
+ #undef GET_PSTATE_REGISTER_INFO
+ #define GET_PSTATE_REGISTER_INFO TRUE
+ #undef GET_PSTATE_MAX_STATE
+ #define GET_PSTATE_MAX_STATE TRUE
+ #undef SET_PSTATE_LEVELING_REG
+ #define SET_PSTATE_LEVELING_REG TRUE
+ #undef SET_WARM_RESET_FLAG
+ #define SET_WARM_RESET_FLAG TRUE
+ #undef GET_WARM_RESET_FLAG
+ #define GET_WARM_RESET_FLAG TRUE
+ #undef SAVE_FEATURES
+ #define SAVE_FEATURES TRUE
+ #undef WRITE_FEATURES
+ #define WRITE_FEATURES TRUE
+ #undef GET_CFOH_REG
+ #define GET_CFOH_REG TRUE
+ #undef IS_NB_PSTATE_ENABLED
+ #define IS_NB_PSTATE_ENABLED TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_ENV == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_MID == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_LATE == TRUE
+ #undef GET_AP_CORE_NUMBER
+ #define GET_AP_CORE_NUMBER TRUE
+ #undef GET_PSTATE_FREQ
+ #define GET_PSTATE_FREQ TRUE
+ #undef TRANSITION_PSTATE
+ #define TRANSITION_PSTATE TRUE
+ #undef PSTATE_TRANSITION_LATENCY
+ #define PSTATE_TRANSITION_LATENCY TRUE
+ #undef GET_WHEA_INIT
+ #define GET_WHEA_INIT TRUE
+ #undef GET_PLATFORM_TYPE_SPECIFIC_INFO
+ #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
+ #undef GET_TSC_RATE
+ #define GET_TSC_RATE TRUE
+ #undef BRAND_STRING1
+ #define BRAND_STRING1 TRUE
+ #undef BRAND_STRING2
+ #define BRAND_STRING2 TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_S3SAVE == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_RESUME == TRUE
+ #undef GET_CFOH_REG
+ #define GET_CFOH_REG TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
+ #undef ID_POSITION_INITIAL_APICID
+ #define ID_POSITION_INITIAL_APICID TRUE
+#endif
+
+/*
+ * Initialize PCI MMIO mask to 0
+ */
+#define FAMILY_MMIO_BASE_MASK (0ull)
+
+
+/*
+ * Initialize all families to disabled
+ */
+#define OPT_F10_TABLE
+#define OPT_F12_TABLE
+#define OPT_F14_TABLE
+#define OPT_F15_TABLE
+
+#define OPT_F10_ID_TABLE
+#define OPT_F12_ID_TABLE
+#define OPT_F14_ID_TABLE
+#define OPT_F15_ID_TABLE
+
+
+/*
+ * Install family specific support
+ */
+#if (OPTION_FAMILY10H == TRUE)
+ #include "OptionFamily10hInstall.h"
+#endif
+
+#if (OPTION_FAMILY12H == TRUE)
+ #include "OptionFamily12hInstall.h"
+#endif
+
+#if (OPTION_FAMILY14H == TRUE)
+ #include "OptionFamily14hInstall.h"
+#endif
+
+#if (OPTION_FAMILY15H == TRUE)
+ #include "OptionFamily15hInstall.h"
+#endif
+
+
+/*
+ * Process PCI MMIO mask
+ */
+
+// If size is 0, but base is not, break the build.
+#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE == 0)
+ #error BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
+#endif
+
+// If base is 0, but size is not, break the build.
+#if (CFG_PCI_MMIO_BASE == 0) && (CFG_PCI_MMIO_SIZE != 0)
+ #error BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
+#endif
+
+#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE != 0)
+ // Both are non-zero, begin further processing.
+
+ // Heap runs from 4MB to 8MB. Disallow any addresses below 8MB.
+ #if (CFG_PCI_MMIO_BASE < 0x800000)
+ #error BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
+ #endif
+
+ // Break the build if the address is too high for the enabled families.
+ #if ((CFG_PCI_MMIO_BASE & FAMILY_MMIO_BASE_MASK) != 0)
+ #error BLDCFG: Invalid PCI MMIO base address for the installed CPU families
+ #endif
+
+ // If the size parameter is not valid, break the build.
+ #if (CFG_PCI_MMIO_SIZE != 1) && (CFG_PCI_MMIO_SIZE != 2) && (CFG_PCI_MMIO_SIZE != 4) && (CFG_PCI_MMIO_SIZE != 8) && (CFG_PCI_MMIO_SIZE != 16)
+ #if (CFG_PCI_MMIO_SIZE != 32) && (CFG_PCI_MMIO_SIZE != 64) && (CFG_PCI_MMIO_SIZE != 128) && (CFG_PCI_MMIO_SIZE != 256)
+ #error BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
+ #endif
+ #endif
+
+ #define PCI_MMIO_ALIGNMENT ((0x100000 * CFG_PCI_MMIO_SIZE) - 1)
+ // If the base is not aligned according to size, break the build.
+ #if ((CFG_PCI_MMIO_BASE & PCI_MMIO_ALIGNMENT) != 0)
+ #error BLDCFG: Invalid PCI MMIO base -- must be properly aligned according to MMIO size
+ #endif
+ #undef PCI_MMIO_ALIGNMENT
+#endif
+
+/*
+ * Process sockets / modules
+ */
+#ifndef ADVCFG_PLATFORM_SOCKETS
+ #error BLDOPT Set Family supported sockets.
+#endif
+#ifndef ADVCFG_PLATFORM_MODULES
+ #error BLDOPT Set Family supported modules.
+#endif
+
+CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration =
+{
+ ADVCFG_PLATFORM_SOCKETS,
+ ADVCFG_PLATFORM_MODULES
+};
+
+/*
+ * Instantiate global data needed for processor identification
+ */
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpuSupportedFamiliesArray[] =
+{
+ OPT_F10_TABLE
+ OPT_F12_TABLE
+ OPT_F14_TABLE
+ OPT_F15_TABLE
+};
+
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CpuSupportedFamiliesTable =
+{
+ (sizeof (CpuSupportedFamiliesArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+ &CpuSupportedFamiliesArray[0]
+};
+
+
+CONST CPU_LOGICAL_ID_FAMILY_XLAT ROMDATA CpuSupportedFamilyIdArray[] =
+{
+ OPT_F10_ID_TABLE
+ OPT_F12_ID_TABLE
+ OPT_F14_ID_TABLE
+ OPT_F15_ID_TABLE
+};
+
+CONST CPU_FAMILY_ID_XLAT_TABLE ROMDATA CpuSupportedFamilyIdTable =
+{
+ (sizeof (CpuSupportedFamilyIdArray) / sizeof (CPU_LOGICAL_ID_FAMILY_XLAT)),
+ CpuSupportedFamilyIdArray
+};
diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionCpuFeaturesInstall.h b/src/vendorcode/amd/agesa/f14/Include/OptionCpuFeaturesInstall.h
new file mode 100644
index 0000000..63cd55e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Include/OptionCpuFeaturesInstall.h
@@ -0,0 +1,78 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of multiple CPU features.
+ *
+ * Aggregates enabled CPU features into a list for the dispatcher to process.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Options
+ * @e \$Revision: 37157 $ @e \$Date: 2010-09-01 03:24:07 +0800 (Wed, 01 Sep 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _OPTION_CPU_FEATURES_INSTALL_H_
+#define _OPTION_CPU_FEATURES_INSTALL_H_
+
+#include "OptionHwC1eInstall.h"
+#include "OptionMsgBasedC1eInstall.h"
+#include "OptionSwC1eInstall.h"
+#include "OptionHtAssistInstall.h"
+#include "OptionCpuCoreLevelingInstall.h"
+#include "OptionIoCstateInstall.h"
+#include "OptionC6Install.h"
+#include "OptionCpbInstall.h"
+#include "OptionCpuCacheFlushOnHaltInstall.h"
+#include "OptionLowPwrPstateInstall.h"
+#include "OptionPreserveMailboxInstall.h"
+
+CONST CPU_FEATURE_DESCRIPTOR* ROMDATA SupportedCpuFeatureList[] =
+{
+ OPTION_HW_C1E_FEAT
+ OPTION_MSG_BASED_C1E_FEAT
+ OPTION_SW_C1E_FEAT
+ OPTION_HT_ASSIST_FEAT
+ OPTION_CPU_CORE_LEVELING_FEAT
+ OPTION_IO_CSTATE_FEAT
+ OPTION_C6_STATE_FEAT
+ OPTION_CPB_FEAT
+ OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
+ OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT // this function should be run before creating ACPI objects and after Pstate initialization
+ OPTION_PRESERVE_MAILBOX_FEAT
+ NULL
+};
+
+
+#endif // _OPTION_CPU_FEATURES_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionDmi.h b/src/vendorcode/amd/agesa/f14/Include/OptionDmi.h
new file mode 100644
index 0000000..216e871
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Include/OptionDmi.h
@@ -0,0 +1,92 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD DMI option API.
+ *
+ * Contains structures and values used to control the DMI option code.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: OPTION
+ * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _OPTION_DMI_H_
+#define _OPTION_DMI_H_
+
+/*----------------------------------------------------------------------------------------
+ * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S, S T R U C T U R E S, E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+typedef AGESA_STATUS OPTION_DMI_FEATURE (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader,
+ IN OUT DMI_INFO **DmiPtr
+ );
+
+typedef AGESA_STATUS OPTION_DMI_RELEASE_BUFFER (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+#define DMI_STRUCT_VERSION 0x01
+
+/// DMI option configuration. Determine the item of structure when compiling.
+typedef struct {
+ UINT16 OptDmiVersion; ///< Dmi version.
+ OPTION_DMI_FEATURE *DmiFeature; ///< Feature main routine, otherwise dummy.
+ OPTION_DMI_RELEASE_BUFFER *DmiReleaseBuffer; ///< Release buffer
+ UINT16 NumEntries; ///< Number of entry.
+ VOID *((*FamilyList)[]); ///< Family service.
+} OPTION_DMI_CONFIGURATION;
+
+/*----------------------------------------------------------------------------------------
+ * F U N C T I O N P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+
+#endif // _OPTION_DMI_H_
diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionDmiInstall.h b/src/vendorcode/amd/agesa/f14/Include/OptionDmiInstall.h
new file mode 100644
index 0000000..87f27e7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Include/OptionDmiInstall.h
@@ -0,0 +1,194 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: DMI
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Options
+ * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _OPTION_DMI_INSTALL_H_
+#define _OPTION_DMI_INSTALL_H_
+
+#include "cpuLateInit.h"
+
+/* This option is designed to be included into the platform solution install
+ * file. The platform solution install file will define the options status.
+ * Check to validate the definition
+ */
+#if AGESA_ENTRY_INIT_LATE == TRUE
+ #ifndef OPTION_DMI
+ #error BLDOPT: Option not defined: "OPTION_DMI"
+ #endif
+ #if OPTION_DMI == TRUE
+ OPTION_DMI_FEATURE GetDmiInfoMain;
+ OPTION_DMI_RELEASE_BUFFER ReleaseDmiBuffer;
+ #define USER_DMI_OPTION &GetDmiInfoMain
+ #define USER_DMI_RELEASE_BUFFER &ReleaseDmiBuffer
+
+ // This additional check keeps AP launch routines from being unnecessarily included
+ // in single socket systems.
+ #if OPTION_MULTISOCKET == TRUE
+ #undef AGESA_ENTRY_LATE_RUN_AP_TASK
+ #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE
+ #define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info},
+ #else
+ #define CPU_DMI_AP_GET_TYPE4_TYPE7
+ #endif
+
+ // Family 10
+ #ifdef OPTION_FAMILY10H
+ #if OPTION_FAMILY10H == TRUE
+ extern PROC_FAMILY_TABLE ProcFamily10DmiTable;
+ #define FAM10_DMI_SUPPORT FAM10_ENABLED,
+ #define FAM10_DMI_TABLE &ProcFamily10DmiTable,
+ #else
+ #define FAM10_DMI_SUPPORT
+ #define FAM10_DMI_TABLE
+ #endif
+ #else
+ #define FAM10_DMI_SUPPORT
+ #define FAM10_DMI_TABLE
+ #endif
+
+ // Family 12
+ #ifdef OPTION_FAMILY12H
+ #if OPTION_FAMILY12H == TRUE
+ extern PROC_FAMILY_TABLE ProcFamily12DmiTable;
+ #define FAM12_DMI_SUPPORT FAM12_ENABLED,
+ #define FAM12_DMI_TABLE &ProcFamily12DmiTable,
+ #else
+ #define FAM12_DMI_SUPPORT
+ #define FAM12_DMI_TABLE
+ #endif
+ #else
+ #define FAM12_DMI_SUPPORT
+ #define FAM12_DMI_TABLE
+ #endif
+
+ // Family 14
+ #ifdef OPTION_FAMILY14H
+ #if OPTION_FAMILY14H == TRUE
+ extern PROC_FAMILY_TABLE ProcFamily14DmiTable;
+ #define FAM14_DMI_SUPPORT FAM14_ENABLED,
+ #define FAM14_DMI_TABLE &ProcFamily14DmiTable,
+ #else
+ #define FAM14_DMI_SUPPORT
+ #define FAM14_DMI_TABLE
+ #endif
+ #else
+ #define FAM14_DMI_SUPPORT
+ #define FAM14_DMI_TABLE
+ #endif
+
+ // Family 15
+ #ifdef OPTION_FAMILY15H
+ #if OPTION_FAMILY15H == TRUE
+ extern PROC_FAMILY_TABLE ProcFamily15DmiTable;
+ #define FAM15_DMI_SUPPORT FAM15_ENABLED,
+ #define FAM15_DMI_TABLE &ProcFamily15DmiTable,
+ #else
+ #define FAM15_DMI_SUPPORT
+ #define FAM15_DMI_TABLE
+ #endif
+ #else
+ #define FAM15_DMI_SUPPORT
+ #define FAM15_DMI_TABLE
+ #endif
+
+ #else
+ OPTION_DMI_FEATURE GetDmiInfoStub;
+ OPTION_DMI_RELEASE_BUFFER ReleaseDmiBufferStub;
+ #define USER_DMI_OPTION GetDmiInfoStub
+ #define USER_DMI_RELEASE_BUFFER ReleaseDmiBufferStub
+ #define FAM10_DMI_SUPPORT
+ #define FAM10_DMI_TABLE
+ #define FAM12_DMI_SUPPORT
+ #define FAM12_DMI_TABLE
+ #define FAM14_DMI_SUPPORT
+ #define FAM14_DMI_TABLE
+ #define FAM15_DMI_SUPPORT
+ #define FAM15_DMI_TABLE
+ #define CPU_DMI_AP_GET_TYPE4_TYPE7
+ #endif
+#else
+ OPTION_DMI_FEATURE GetDmiInfoStub;
+ OPTION_DMI_RELEASE_BUFFER ReleaseDmiBufferStub;
+ #define USER_DMI_OPTION GetDmiInfoStub
+ #define USER_DMI_RELEASE_BUFFER ReleaseDmiBufferStub
+ #define FAM10_DMI_SUPPORT
+ #define FAM10_DMI_TABLE
+ #define FAM12_DMI_SUPPORT
+ #define FAM12_DMI_TABLE
+ #define FAM14_DMI_SUPPORT
+ #define FAM14_DMI_TABLE
+ #define FAM15_DMI_SUPPORT
+ #define FAM15_DMI_TABLE
+ #define CPU_DMI_AP_GET_TYPE4_TYPE7
+#endif
+
+/// DMI supported families enum
+typedef enum {
+ FAM10_DMI_SUPPORT ///< Conditionally define F10 support
+ FAM12_DMI_SUPPORT ///< Conditionally define F12 support
+ FAM14_DMI_SUPPORT ///< Conditionally define F14 support
+ FAM15_DMI_SUPPORT ///< Conditionally define F15 support
+ NUM_DMI_FAMILIES ///< Number of installed families
+} AGESA_DMI_SUPPORTED_FAM;
+
+/* Declare the Family List. An array of pointers to tables that each describe a family */
+CONST PROC_FAMILY_TABLE ROMDATA *ProcTables[] = {
+ FAM10_DMI_TABLE
+ FAM12_DMI_TABLE
+ FAM14_DMI_TABLE
+ FAM15_DMI_TABLE
+ NULL
+};
+
+/* Declare the instance of the DMI option configuration structure */
+CONST OPTION_DMI_CONFIGURATION ROMDATA OptionDmiConfiguration = {
+ DMI_STRUCT_VERSION,
+ USER_DMI_OPTION,
+ USER_DMI_RELEASE_BUFFER,
+ NUM_DMI_FAMILIES,
+ (VOID *((*)[])) &ProcTables // Compiler says array size must match struct decl
+};
+
+#endif // _OPTION_DMI_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionFamily10hInstall.h b/src/vendorcode/amd/agesa/f14/Include/OptionFamily10hInstall.h
new file mode 100644
index 0000000..4b4347f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Include/OptionFamily10hInstall.h
@@ -0,0 +1,1996 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of family 10h support
+ *
+ * This file generates the defaults tables for family 10h processors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Core
+ * @e \$Revision: 37150 $ @e \$Date: 2010-08-31 23:53:37 +0800 (Tue, 31 Aug 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _OPTION_FAMILY_10H_INSTALL_H_
+#define _OPTION_FAMILY_10H_INSTALL_H_
+
+/*
+ * Common Family 10h routines
+ */
+extern F_CPU_DISABLE_PSTATE F10DisablePstate;
+extern F_CPU_TRANSITION_PSTATE F10TransitionPstate;
+extern F_CPU_GET_TSC_RATE F10GetTscRate;
+extern F_CPU_GET_NB_FREQ F10GetCurrentNbFrequency;
+extern F_CPU_AP_INITIAL_LAUNCH F10LaunchApCore;
+extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F10GetApMailboxFromHardware;
+extern F_CPU_SET_AP_CORE_NUMBER F10SetApCoreNumber;
+extern F_CPU_GET_AP_CORE_NUMBER F10GetApCoreNumber;
+extern F_CPU_TRANSFER_AP_CORE_NUMBER F10TransferApCoreNumber;
+extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F10CpuAmdCoreIdPositionInInitialApicId;
+extern F_CPU_SAVE_FEATURES F10SaveFeatures;
+extern F_CPU_WRITE_FEATURES F10WriteFeatures;
+extern F_CPU_SET_WARM_RESET_FLAG F10SetAgesaWarmResetFlag;
+extern F_CPU_GET_WARM_RESET_FLAG F10GetAgesaWarmResetFlag;
+extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10BrandIdString1;
+extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10BrandIdString2;
+extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10CacheInfo;
+extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10SysPmTable;
+extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10WheaInitData;
+extern F_CPU_SET_CFOH_REG SetF10CacheFlushOnHaltRegister;
+extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetEmptyArray;
+extern F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO F10GetPlatformTypeSpecificInfo;
+extern F_NEXT_LINK_HAS_HTFPY_FEATS F10NextLinkHasHtPhyFeats;
+extern F_SET_HT_PHY_REGISTER F10SetHtPhyRegister;
+extern F_GET_NEXT_HT_LINK_FEATURES F10GetNextHtLinkFeatures;
+extern CONST REGISTER_TABLE ROMDATA F10PciRegisterTable;
+extern CONST REGISTER_TABLE ROMDATA F10MsrRegisterTable;
+extern CONST REGISTER_TABLE ROMDATA F10HtPhyRegisterTable;
+extern CONST REGISTER_TABLE ROMDATA F10MultiLinkPciRegisterTable;
+extern CONST REGISTER_TABLE ROMDATA F10SingleLinkPciRegisterTable;
+extern CONST REGISTER_TABLE ROMDATA F10WorkaroundsTable;
+extern F_GET_EARLY_INIT_TABLE GetF10EarlyInitOnCoreTable;
+
+
+/*
+ * Install family 10h model 5 support
+ */
+#ifdef OPTION_FAMILY10H_BL
+ #if OPTION_FAMILY10H_BL == TRUE
+ extern CONST REGISTER_TABLE ROMDATA F10RevCPciRegisterTable;
+ extern CONST REGISTER_TABLE ROMDATA F10RevCMsrRegisterTable;
+ extern CONST REGISTER_TABLE ROMDATA F10RevCHtPhyRegisterTable;
+ extern CONST REGISTER_TABLE ROMDATA F10BlPciRegisterTable;
+ extern CONST REGISTER_TABLE ROMDATA F10BlMsrRegisterTable;
+ extern CONST REGISTER_TABLE ROMDATA F10BlHtPhyRegisterTable;
+ extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10BlMicroCodePatchesStruct;
+ extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10BlMicrocodeEquivalenceTable;
+ extern F_CPU_GET_IDD_MAX F10CommonRevCGetProcIddMax;
+ extern F_CPU_GET_NB_PSTATE_INFO F10CommonRevCGetNbPstateInfo;
+ extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevCGetNbCofVidUpdate;
+ extern F_IS_NB_PSTATE_ENABLED F10CommonRevCIsNbPstateEnabled;
+ extern F_CPU_NUMBER_OF_BRANDSTRING_CORES F10CommonRevCGetNumberOfCoresForBrandstring;
+
+ #if USES_REGISTER_TABLES == TRUE
+ CONST REGISTER_TABLE ROMDATA *F10BlRegisterTables[] =
+ {
+ #if BASE_FAMILY_PCI == TRUE
+ &F10PciRegisterTable,
+ #endif
+ #if MODEL_SPECIFIC_PCI == TRUE
+ &F10SingleLinkPciRegisterTable,
+ #endif
+ #if MODEL_SPECIFIC_PCI == TRUE
+ &F10RevCPciRegisterTable,
+ #endif
+ #if MODEL_SPECIFIC_PCI == TRUE
+ &F10BlPciRegisterTable,
+ #endif
+ #if BASE_FAMILY_MSR == TRUE
+ &F10MsrRegisterTable,
+ #endif
+ #if MODEL_SPECIFIC_MSR == TRUE
+ &F10RevCMsrRegisterTable,
+ #endif
+ #if MODEL_SPECIFIC_MSR == TRUE
+ &F10BlMsrRegisterTable,
+ #endif
+ #if MODEL_SPECIFIC_HT_PCI == TRUE
+ &F10HtPhyRegisterTable,
+ #endif
+ #if MODEL_SPECIFIC_HT_PCI == TRUE
+ &F10RevCHtPhyRegisterTable,
+ #endif
+ #if MODEL_SPECIFIC_HT_PCI == TRUE
+ &F10BlHtPhyRegisterTable,
+ #endif
+ #if BASE_FAMILY_WORKAROUNDS == TRUE
+ &F10WorkaroundsTable,
+ #endif
+ // the end.
+ NULL
+ };
+ #endif
+
+ #if USES_REGISTER_TABLES == TRUE
+ CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10BlTableEntryTypeDescriptors[] =
+ {
+ {MsrRegister, SetRegisterForMsrEntry},
+ {PciRegister, SetRegisterForPciEntry},
+ {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
+ {HtPhyRegister, SetRegisterForHtPhyEntry},
+ {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
+ {DeemphasisRegister, SetRegisterForDeemphasisEntry},
+ {ProfileFixup, SetRegisterForPerformanceProfileEntry},
+ {HtHostPciRegister, SetRegisterForHtHostEntry},
+ {HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid},
+ {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
+ {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
+ {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
+ {HtPhyProfileRegister, SetRegisterForHtPhyProfileEntry},
+ // End
+ {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
+ };
+ #endif
+
+ CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10BlServices =
+ {
+ 0,
+ #if DISABLE_PSTATE == TRUE
+ F10DisablePstate,
+ #else
+ (PF_CPU_DISABLE_PSTATE) CommonAssert,
+ #endif
+ #if TRANSITION_PSTATE == TRUE
+ F10TransitionPstate,
+ #else
+ (PF_CPU_TRANSITION_PSTATE) CommonAssert,
+ #endif
+ #if PROC_IDD_MAX == TRUE
+ F10CommonRevCGetProcIddMax,
+ #else
+ (PF_CPU_GET_IDD_MAX) CommonAssert,
+ #endif
+ #if GET_TSC_RATE == TRUE
+ F10GetTscRate,
+ #else
+ (PF_CPU_GET_TSC_RATE) CommonAssert,
+ #endif
+ #if GET_NB_FREQ == TRUE
+ F10GetCurrentNbFrequency,
+ #else
+ (PF_CPU_GET_NB_FREQ) CommonAssert,
+ #endif
+ #if GET_NB_FREQ == TRUE
+ F10CommonRevCGetNbPstateInfo,
+ #else
+ (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
+ #endif
+ #if IS_NBCOF_INIT_NEEDED == TRUE
+ F10CommonRevCGetNbCofVidUpdate,
+ #else
+ (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
+ #endif
+ #if AP_INITIAL_LAUNCH == TRUE
+ F10LaunchApCore,
+ #else
+ (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
+ #endif
+ #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
+ F10CommonRevCGetNumberOfCoresForBrandstring,
+ #else
+ (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
+ #endif
+ #if GET_AP_MAILBOX_FROM_HW == TRUE
+ F10GetApMailboxFromHardware,
+ #else
+ (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
+ #endif
+ #if SET_AP_CORE_NUMBER == TRUE
+ F10SetApCoreNumber,
+ #else
+ (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
+ #endif
+ #if GET_AP_CORE_NUMBER == TRUE
+ F10GetApCoreNumber,
+ #else
+ (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
+ #endif
+ #if TRANSFER_AP_CORE_NUMBER == TRUE
+ F10TransferApCoreNumber,
+ #else
+ (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
+ #endif
+ #if ID_POSITION_INITIAL_APICID == TRUE
+ F10CpuAmdCoreIdPositionInInitialApicId,
+ #else
+ (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
+ #endif
+ #if SAVE_FEATURES == TRUE
+ F10SaveFeatures,
+ #else
+ (PF_CPU_SAVE_FEATURES) CommonAssert,
+ #endif
+ #if WRITE_FEATURES == TRUE
+ F10WriteFeatures,
+ #else
+ (PF_CPU_WRITE_FEATURES) CommonAssert,
+ #endif
+ #if SET_WARM_RESET_FLAG == TRUE
+ F10SetAgesaWarmResetFlag,
+ #else
+ (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
+ #endif
+ #if GET_WARM_RESET_FLAG == TRUE
+ F10GetAgesaWarmResetFlag,
+ #else
+ (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
+ #endif
+ #if BRAND_STRING1 == TRUE
+ GetF10BrandIdString1,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if BRAND_STRING2 == TRUE
+ GetF10BrandIdString2,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_PATCHES == TRUE
+ GetF10BlMicroCodePatchesStruct,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
+ GetF10BlMicrocodeEquivalenceTable,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_CACHE_INFO == TRUE
+ GetF10CacheInfo,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_SYSTEM_PM_TABLE == TRUE
+ GetF10SysPmTable,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_WHEA_INIT == TRUE
+ GetF10WheaInitData,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
+ F10GetPlatformTypeSpecificInfo,
+ #else
+ (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
+ #endif
+ #if IS_NB_PSTATE_ENABLED == TRUE
+ F10CommonRevCIsNbPstateEnabled,
+ #else
+ (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
+ #endif
+ #if (BASE_FAMILY_HT_PCI == TRUE)
+ F10NextLinkHasHtPhyFeats,
+ #else
+ (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
+ #endif
+ #if (BASE_FAMILY_HT_PCI == TRUE)
+ F10SetHtPhyRegister,
+ #else
+ (PF_SET_HT_PHY_REGISTER) CommonAssert,
+ #endif
+ #if BASE_FAMILY_PCI == TRUE
+ F10GetNextHtLinkFeatures,
+ #else
+ (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
+ #endif
+ #if USES_REGISTER_TABLES == TRUE
+ (REGISTER_TABLE **) F10BlRegisterTables,
+ #else
+ NULL,
+ #endif
+ #if USES_REGISTER_TABLES == TRUE
+ (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10BlTableEntryTypeDescriptors,
+ #else
+ NULL,
+ #endif
+ NULL,
+ NULL,
+ InitCacheDisabled,
+ #if AGESA_ENTRY_INIT_EARLY == TRUE
+ GetF10EarlyInitOnCoreTable
+ #else
+ (PF_GET_EARLY_INIT_TABLE) CommonVoid
+ #endif
+ };
+
+ #define BL_SOCKETS 1
+ #define BL_MODULES 1
+ #define BL_RECOVERY_SOCKETS 1
+ #define BL_RECOVERY_MODULES 1
+ extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10BlLogicalIdAndRev;
+ #define OPT_F10_BL_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10BlLogicalIdAndRev,
+ #ifndef ADVCFG_PLATFORM_SOCKETS
+ #define ADVCFG_PLATFORM_SOCKETS BL_SOCKETS
+ #else
+ #if ADVCFG_PLATFORM_SOCKETS < BL_SOCKETS
+ #undef ADVCFG_PLATFORM_SOCKETS
+ #define ADVCFG_PLATFORM_SOCKETS BL_SOCKETS
+ #endif
+ #endif
+ #ifndef ADVCFG_PLATFORM_MODULES
+ #define ADVCFG_PLATFORM_MODULES BL_MODULES
+ #else
+ #if ADVCFG_PLATFORM_MODULES < BL_MODULES
+ #undef ADVCFG_PLATFORM_MODULES
+ #define ADVCFG_PLATFORM_MODULES BL_MODULES
+ #endif
+ #endif
+
+ #if GET_PATCHES == TRUE
+ #define F10_BL_UCODE_C6
+ #define F10_BL_UCODE_C8
+
+ // If a patch is required for recovery mode to function properly, add a
+ // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
+ #if AGESA_ENTRY_INIT_EARLY == TRUE
+ #if OPTION_AM3_SOCKET_SUPPORT == TRUE
+ extern CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c6;
+ #undef F10_BL_UCODE_C6
+ #define F10_BL_UCODE_C6 &CpuF10MicrocodePatch010000c6,
+ #endif
+ #if (OPTION_S1G4_SOCKET_SUPPORT == TRUE) || (OPTION_AM3_SOCKET_SUPPORT == TRUE) || (OPTION_ASB2_SOCKET_SUPPORT == TRUE)
+ extern CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c8;
+ #undef F10_BL_UCODE_C8
+ #define F10_BL_UCODE_C8 &CpuF10MicrocodePatch010000c8,
+ #endif
+ #endif
+
+ CONST MICROCODE_PATCHES ROMDATA *CpuF10BlMicroCodePatchArray[] =
+ {
+ F10_BL_UCODE_C6
+ F10_BL_UCODE_C8
+ NULL
+ };
+
+ CONST UINT8 ROMDATA CpuF10BlNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF10BlMicroCodePatchArray) / sizeof (CpuF10BlMicroCodePatchArray[0])) - 1);
+ #endif
+
+ #define OPT_F10_BL_CPU {AMD_FAMILY_10_BL, &cpuF10BlServices},
+ #else
+ #define OPT_F10_BL_CPU
+ #define OPT_F10_BL_ID
+ #endif
+#else
+ #define OPT_F10_BL_CPU
+ #define OPT_F10_BL_ID
+#endif
+
+/*
+ * Install family 10h model 6 support
+ */
+#ifdef OPTION_FAMILY10H_DA
+ #if OPTION_FAMILY10H_DA == TRUE
+ extern CONST REGISTER_TABLE ROMDATA F10RevCPciRegisterTable;
+ extern CONST REGISTER_TABLE ROMDATA F10RevCMsrRegisterTable;
+ extern CONST REGISTER_TABLE ROMDATA F10RevCHtPhyRegisterTable;
+ extern CONST REGISTER_TABLE ROMDATA F10DaPciRegisterTable;
+ extern CONST REGISTER_TABLE ROMDATA F10DaMsrRegisterTable;
+ extern CONST REGISTER_TABLE ROMDATA F10DaHtPhyRegisterTable;
+ extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10DaMicroCodePatchesStruct;
+ extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10DaMicrocodeEquivalenceTable;
+ extern F_CPU_GET_IDD_MAX F10CommonRevCGetProcIddMax;
+ extern F_CPU_GET_NB_PSTATE_INFO F10CommonRevCGetNbPstateInfo;
+ extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevCGetNbCofVidUpdate;
+ extern F_CPU_SET_CFOH_REG SetF10DaCacheFlushOnHaltRegister;
+ extern F_IS_NB_PSTATE_ENABLED F10CommonRevCIsNbPstateEnabled;
+ extern F_CPU_NUMBER_OF_BRANDSTRING_CORES F10CommonRevCGetNumberOfCoresForBrandstring;
+
+ #if USES_REGISTER_TABLES == TRUE
+ CONST REGISTER_TABLE ROMDATA *F10DaRegisterTables[] =
+ {
+ #if BASE_FAMILY_PCI == TRUE
+ &F10PciRegisterTable,
+ #endif
+ #if MODEL_SPECIFIC_PCI == TRUE
+ &F10SingleLinkPciRegisterTable,
+ #endif
+ #if MODEL_SPECIFIC_PCI == TRUE
+ &F10RevCPciRegisterTable,
+ #endif
+ #if MODEL_SPECIFIC_PCI == TRUE
+ &F10DaPciRegisterTable,
+ #endif
+ #if BASE_FAMILY_MSR == TRUE
+ &F10MsrRegisterTable,
+ #endif
+ #if MODEL_SPECIFIC_MSR == TRUE
+ &F10RevCMsrRegisterTable,
+ #endif
+ #if MODEL_SPECIFIC_MSR == TRUE
+ &F10DaMsrRegisterTable,
+ #endif
+ #if MODEL_SPECIFIC_HT_PCI == TRUE
+ &F10HtPhyRegisterTable,
+ #endif
+ #if MODEL_SPECIFIC_HT_PCI == TRUE
+ &F10RevCHtPhyRegisterTable,
+ #endif
+ #if MODEL_SPECIFIC_HT_PCI == TRUE
+ &F10DaHtPhyRegisterTable,
+ #endif
+ #if BASE_FAMILY_WORKAROUNDS == TRUE
+ &F10WorkaroundsTable,
+ #endif
+ // the end.
+ NULL
+ };
+ #endif
+
+ #if USES_REGISTER_TABLES == TRUE
+ CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10DaTableEntryTypeDescriptors[] =
+ {
+ {MsrRegister, SetRegisterForMsrEntry},
+ {PciRegister, SetRegisterForPciEntry},
+ {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
+ {HtPhyRegister, SetRegisterForHtPhyEntry},
+ {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
+ {DeemphasisRegister, SetRegisterForDeemphasisEntry},
+ {ProfileFixup, SetRegisterForPerformanceProfileEntry},
+ {HtHostPciRegister, SetRegisterForHtHostEntry},
+ {HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid},
+ {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
+ {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
+ {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
+ {HtPhyProfileRegister, SetRegisterForHtPhyProfileEntry},
+ // End
+ {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
+ };
+ #endif
+
+ CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10DaServices =
+ {
+ 0,
+ #if DISABLE_PSTATE == TRUE
+ F10DisablePstate,
+ #else
+ (PF_CPU_DISABLE_PSTATE) CommonAssert,
+ #endif
+ #if TRANSITION_PSTATE == TRUE
+ F10TransitionPstate,
+ #else
+ (PF_CPU_TRANSITION_PSTATE) CommonAssert,
+ #endif
+ #if PROC_IDD_MAX == TRUE
+ F10CommonRevCGetProcIddMax,
+ #else
+ (PF_CPU_GET_IDD_MAX) CommonAssert,
+ #endif
+ #if GET_TSC_RATE == TRUE
+ F10GetTscRate,
+ #else
+ (PF_CPU_GET_TSC_RATE) CommonAssert,
+ #endif
+ #if GET_NB_FREQ == TRUE
+ F10GetCurrentNbFrequency,
+ #else
+ (PF_CPU_GET_NB_FREQ) CommonAssert,
+ #endif
+ #if GET_NB_FREQ == TRUE
+ F10CommonRevCGetNbPstateInfo,
+ #else
+ (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
+ #endif
+ #if IS_NBCOF_INIT_NEEDED == TRUE
+ F10CommonRevCGetNbCofVidUpdate,
+ #else
+ (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
+ #endif
+ #if AP_INITIAL_LAUNCH == TRUE
+ F10LaunchApCore,
+ #else
+ (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
+ #endif
+ #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
+ F10CommonRevCGetNumberOfCoresForBrandstring,
+ #else
+ (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
+ #endif
+ #if GET_AP_MAILBOX_FROM_HW == TRUE
+ F10GetApMailboxFromHardware,
+ #else
+ (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
+ #endif
+ #if SET_AP_CORE_NUMBER == TRUE
+ F10SetApCoreNumber,
+ #else
+ (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
+ #endif
+ #if GET_AP_CORE_NUMBER == TRUE
+ F10GetApCoreNumber,
+ #else
+ (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
+ #endif
+ #if TRANSFER_AP_CORE_NUMBER == TRUE
+ F10TransferApCoreNumber,
+ #else
+ (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
+ #endif
+ #if ID_POSITION_INITIAL_APICID == TRUE
+ F10CpuAmdCoreIdPositionInInitialApicId,
+ #else
+ (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
+ #endif
+ #if SAVE_FEATURES == TRUE
+ F10SaveFeatures,
+ #else
+ (PF_CPU_SAVE_FEATURES) CommonAssert,
+ #endif
+ #if WRITE_FEATURES == TRUE
+ F10WriteFeatures,
+ #else
+ (PF_CPU_WRITE_FEATURES) CommonAssert,
+ #endif
+ #if SET_WARM_RESET_FLAG == TRUE
+ F10SetAgesaWarmResetFlag,
+ #else
+ (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
+ #endif
+ #if GET_WARM_RESET_FLAG == TRUE
+ F10GetAgesaWarmResetFlag,
+ #else
+ (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
+ #endif
+ #if BRAND_STRING1 == TRUE
+ GetF10BrandIdString1,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if BRAND_STRING2 == TRUE
+ GetF10BrandIdString2,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_PATCHES == TRUE
+ GetF10DaMicroCodePatchesStruct,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
+ GetF10DaMicrocodeEquivalenceTable,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_CACHE_INFO == TRUE
+ GetF10CacheInfo,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_SYSTEM_PM_TABLE == TRUE
+ GetF10SysPmTable,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_WHEA_INIT == TRUE
+ GetF10WheaInitData,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
+ F10GetPlatformTypeSpecificInfo,
+ #else
+ (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
+ #endif
+ #if IS_NB_PSTATE_ENABLED == TRUE
+ F10CommonRevCIsNbPstateEnabled,
+ #else
+ (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
+ #endif
+ #if (BASE_FAMILY_HT_PCI == TRUE)
+ F10NextLinkHasHtPhyFeats,
+ #else
+ (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
+ #endif
+ #if (BASE_FAMILY_HT_PCI == TRUE)
+ F10SetHtPhyRegister,
+ #else
+ (PF_SET_HT_PHY_REGISTER) CommonAssert,
+ #endif
+ #if BASE_FAMILY_PCI == TRUE
+ F10GetNextHtLinkFeatures,
+ #else
+ (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
+ #endif
+ #if USES_REGISTER_TABLES == TRUE
+ (REGISTER_TABLE **) F10DaRegisterTables,
+ #else
+ NULL,
+ #endif
+ #if USES_REGISTER_TABLES == TRUE
+ (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10DaTableEntryTypeDescriptors,
+ #else
+ NULL,
+ #endif
+ NULL,
+ NULL,
+ InitCacheDisabled,
+ #if AGESA_ENTRY_INIT_EARLY == TRUE
+ GetF10EarlyInitOnCoreTable
+ #else
+ (PF_GET_EARLY_INIT_TABLE) CommonVoid
+ #endif
+ };
+
+ #define DA_SOCKETS 1
+ #define DA_MODULES 1
+ #define DA_RECOVERY_SOCKETS 1
+ #define DA_RECOVERY_MODULES 1
+ extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10DaLogicalIdAndRev;
+ #define OPT_F10_DA_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10DaLogicalIdAndRev,
+ #ifndef ADVCFG_PLATFORM_SOCKETS
+ #define ADVCFG_PLATFORM_SOCKETS DA_SOCKETS
+ #else
+ #if ADVCFG_PLATFORM_SOCKETS < DA_SOCKETS
+ #undef ADVCFG_PLATFORM_SOCKETS
+ #define ADVCFG_PLATFORM_SOCKETS DA_SOCKETS
+ #endif
+ #endif
+ #ifndef ADVCFG_PLATFORM_MODULES
+ #define ADVCFG_PLATFORM_MODULES DA_MODULES
+ #else
+ #if ADVCFG_PLATFORM_MODULES < DA_MODULES
+ #undef ADVCFG_PLATFORM_MODULES
+ #define ADVCFG_PLATFORM_MODULES DA_MODULES
+ #endif
+ #endif
+
+ #if GET_PATCHES == TRUE
+ #define F10_DA_UCODE_C7
+ #define F10_DA_UCODE_C8
+
+ // If a patch is required for recovery mode to function properly, add a
+ // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
+ #if AGESA_ENTRY_INIT_EARLY == TRUE
+ #if (OPTION_S1G3_SOCKET_SUPPORT == TRUE) || (OPTION_AM3_SOCKET_SUPPORT == TRUE)
+ extern CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c7;
+ #undef F10_DA_UCODE_C7
+ #define F10_DA_UCODE_C7 &CpuF10MicrocodePatch010000c7,
+ #endif
+ #if (OPTION_S1G4_SOCKET_SUPPORT == TRUE) || (OPTION_AM3_SOCKET_SUPPORT == TRUE) || (OPTION_ASB2_SOCKET_SUPPORT == TRUE)
+ extern CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c8;
+ #undef F10_DA_UCODE_C8
+ #define F10_DA_UCODE_C8 &CpuF10MicrocodePatch010000c8,
+ #endif
+ #endif
+
+ CONST MICROCODE_PATCHES ROMDATA *CpuF10DaMicroCodePatchArray[] =
+ {
+ F10_DA_UCODE_C7
+ F10_DA_UCODE_C8
+ NULL
+ };
+
+ CONST UINT8 ROMDATA CpuF10DaNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF10DaMicroCodePatchArray) / sizeof (CpuF10DaMicroCodePatchArray[0])) - 1);
+ #endif
+
+ #define OPT_F10_DA_CPU {AMD_FAMILY_10_DA, &cpuF10DaServices},
+ #else
+ #define OPT_F10_DA_CPU
+ #define OPT_F10_DA_ID
+ #endif
+#else
+ #define OPT_F10_DA_CPU
+ #define OPT_F10_DA_ID
+#endif
+
+/*
+ * Install family 10h models 8 & 9 support
+ */
+#ifdef OPTION_FAMILY10H_HY
+ #if OPTION_FAMILY10H_HY == TRUE
+ extern CONST REGISTER_TABLE ROMDATA F10HyPciRegisterTable;
+ extern CONST REGISTER_TABLE ROMDATA F10HyMsrRegisterTable;
+ extern CONST REGISTER_TABLE ROMDATA F10HyHtPhyRegisterTable;
+ extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10HyMicroCodePatchesStruct;
+ extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10HyMicrocodeEquivalenceTable;
+ extern F_CPU_GET_IDD_MAX F10CommonRevDGetProcIddMax;
+ extern F_CPU_GET_NB_PSTATE_INFO F10CommonRevDGetNbPstateInfo;
+ extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevDGetNbCofVidUpdate;
+ extern CONST PACKAGE_HTLINK_MAP_ITEM ROMDATA HtFam10RevDPackageLinkMap[];
+ extern F_CPU_NUMBER_OF_BRANDSTRING_CORES F10CommonRevDGetNumberOfCoresForBrandstring;
+ extern F_GET_EARLY_INIT_TABLE GetF10HyEarlyInitOnCoreTable;
+
+ #if USES_REGISTER_TABLES == TRUE
+ CONST REGISTER_TABLE ROMDATA *F10HyRegisterTables[] =
+ {
+ #if BASE_FAMILY_PCI == TRUE
+ &F10PciRegisterTable,
+ #endif
+ #if MODEL_SPECIFIC_PCI == TRUE
+ &F10MultiLinkPciRegisterTable,
+ #endif
+ #if MODEL_SPECIFIC_PCI == TRUE
+ &F10HyPciRegisterTable,
+ #endif
+ #if BASE_FAMILY_MSR == TRUE
+ &F10MsrRegisterTable,
+ #endif
+ #if MODEL_SPECIFIC_MSR == TRUE
+ &F10HyMsrRegisterTable,
+ #endif
+ #if MODEL_SPECIFIC_HT_PCI == TRUE
+ &F10HtPhyRegisterTable,
+ #endif
+ #if MODEL_SPECIFIC_HT_PCI == TRUE
+ &F10HyHtPhyRegisterTable,
+ #endif
+ #if BASE_FAMILY_WORKAROUNDS == TRUE
+ &F10WorkaroundsTable,
+ #endif
+ // the end.
+ NULL
+ };
+ #endif
+
+ #if USES_REGISTER_TABLES == TRUE
+ CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10HyTableEntryTypeDescriptors[] =
+ {
+ {MsrRegister, SetRegisterForMsrEntry},
+ {PciRegister, SetRegisterForPciEntry},
+ {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
+ {HtPhyRegister, SetRegisterForHtPhyEntry},
+ {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
+ {DeemphasisRegister, SetRegisterForDeemphasisEntry},
+ {HtPhyFreqRegister, SetRegisterForHtPhyFreqEntry},
+ {ProfileFixup, SetRegisterForPerformanceProfileEntry},
+ {HtHostPciRegister, SetRegisterForHtHostEntry},
+ {HtTokenPciRegister, SetRegisterForHtLinkTokenEntry},
+ {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
+ {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
+ {TokenPciRegister, SetRegisterForTokenPciEntry},
+ {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
+ {HtLinkPciRegister, SetRegisterForHtLinkPciEntry},
+ // End
+ {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
+ };
+ #endif
+
+ CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10HyServices =
+ {
+ 0,
+ #if DISABLE_PSTATE == TRUE
+ F10DisablePstate,
+ #else
+ (PF_CPU_DISABLE_PSTATE) CommonAssert,
+ #endif
+ #if TRANSITION_PSTATE == TRUE
+ F10TransitionPstate,
+ #else
+ (PF_CPU_TRANSITION_PSTATE) CommonAssert,
+ #endif
+ #if PROC_IDD_MAX == TRUE
+ F10CommonRevDGetProcIddMax,
+ #else
+ (PF_CPU_GET_IDD_MAX) CommonAssert,
+ #endif
+ #if GET_TSC_RATE == TRUE
+ F10GetTscRate,
+ #else
+ (PF_CPU_GET_TSC_RATE) CommonAssert,
+ #endif
+ #if GET_NB_FREQ == TRUE
+ F10GetCurrentNbFrequency,
+ #else
+ (PF_CPU_GET_NB_FREQ) CommonAssert,
+ #endif
+ #if GET_NB_FREQ == TRUE
+ F10CommonRevDGetNbPstateInfo,
+ #else
+ (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
+ #endif
+ #if IS_NBCOF_INIT_NEEDED == TRUE
+ F10CommonRevDGetNbCofVidUpdate,
+ #else
+ (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
+ #endif
+ #if AP_INITIAL_LAUNCH == TRUE
+ F10LaunchApCore,
+ #else
+ (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
+ #endif
+ #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
+ F10CommonRevDGetNumberOfCoresForBrandstring,
+ #else
+ (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
+ #endif
+ #if GET_AP_MAILBOX_FROM_HW == TRUE
+ F10GetApMailboxFromHardware,
+ #else
+ (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
+ #endif
+ #if SET_AP_CORE_NUMBER == TRUE
+ F10SetApCoreNumber,
+ #else
+ (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
+ #endif
+ #if GET_AP_CORE_NUMBER == TRUE
+ F10GetApCoreNumber,
+ #else
+ (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
+ #endif
+ #if TRANSFER_AP_CORE_NUMBER == TRUE
+ F10TransferApCoreNumber,
+ #else
+ (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
+ #endif
+ #if ID_POSITION_INITIAL_APICID == TRUE
+ F10CpuAmdCoreIdPositionInInitialApicId,
+ #else
+ (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
+ #endif
+ #if SAVE_FEATURES == TRUE
+ F10SaveFeatures,
+ #else
+ (PF_CPU_SAVE_FEATURES) CommonAssert,
+ #endif
+ #if WRITE_FEATURES == TRUE
+ F10WriteFeatures,
+ #else
+ (PF_CPU_WRITE_FEATURES) CommonAssert,
+ #endif
+ #if SET_WARM_RESET_FLAG == TRUE
+ F10SetAgesaWarmResetFlag,
+ #else
+ (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
+ #endif
+ #if GET_WARM_RESET_FLAG == TRUE
+ F10GetAgesaWarmResetFlag,
+ #else
+ (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
+ #endif
+ #if BRAND_STRING1 == TRUE
+ GetF10BrandIdString1,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if BRAND_STRING2 == TRUE
+ GetF10BrandIdString2,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_PATCHES == TRUE
+ GetF10HyMicroCodePatchesStruct,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
+ GetF10HyMicrocodeEquivalenceTable,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_CACHE_INFO == TRUE
+ GetF10CacheInfo,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_SYSTEM_PM_TABLE == TRUE
+ GetF10SysPmTable,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_WHEA_INIT == TRUE
+ GetF10WheaInitData,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
+ F10GetPlatformTypeSpecificInfo,
+ #else
+ (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
+ #endif
+ #if IS_NB_PSTATE_ENABLED == TRUE
+ (PF_IS_NB_PSTATE_ENABLED) CommonReturnFalse,
+ #else
+ (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
+ #endif
+ #if (BASE_FAMILY_HT_PCI == TRUE)
+ F10NextLinkHasHtPhyFeats,
+ #else
+ (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
+ #endif
+ #if (BASE_FAMILY_HT_PCI == TRUE)
+ F10SetHtPhyRegister,
+ #else
+ (PF_SET_HT_PHY_REGISTER) CommonAssert,
+ #endif
+ #if BASE_FAMILY_PCI == TRUE
+ F10GetNextHtLinkFeatures,
+ #else
+ (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
+ #endif
+ #if USES_REGISTER_TABLES == TRUE
+ (REGISTER_TABLE **) F10HyRegisterTables,
+ #else
+ NULL,
+ #endif
+ #if USES_REGISTER_TABLES == TRUE
+ (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10HyTableEntryTypeDescriptors,
+ #else
+ NULL,
+ #endif
+ #if MODEL_SPECIFIC_HT_PCI == TRUE
+ (PACKAGE_HTLINK_MAP) &HtFam10RevDPackageLinkMap,
+ #else
+ NULL,
+ #endif
+ NULL,
+ InitCacheDisabled,
+ #if AGESA_ENTRY_INIT_EARLY == TRUE
+ #if OPTION_C32_SOCKET_SUPPORT == TRUE
+ GetF10HyEarlyInitOnCoreTable
+ #else
+ GetF10EarlyInitOnCoreTable
+ #endif
+ #else
+ (PF_GET_EARLY_INIT_TABLE) CommonVoid
+ #endif
+ };
+
+ #define HY_SOCKETS 8
+ #if (OPTION_G34_SOCKET_SUPPORT == TRUE)
+ #define HY_MODULES 2
+ #else
+ #define HY_MODULES 1
+ #endif
+ #define HY_RECOVERY_SOCKETS 1
+ #define HY_RECOVERY_MODULES 1
+ extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10HyLogicalIdAndRev;
+ #define OPT_F10_HY_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10HyLogicalIdAndRev,
+ #ifndef ADVCFG_PLATFORM_SOCKETS
+ #define ADVCFG_PLATFORM_SOCKETS HY_SOCKETS
+ #else
+ #if ADVCFG_PLATFORM_SOCKETS < HY_SOCKETS
+ #undef ADVCFG_PLATFORM_SOCKETS
+ #define ADVCFG_PLATFORM_SOCKETS HY_SOCKETS
+ #endif
+ #endif
+ #ifndef ADVCFG_PLATFORM_MODULES
+ #define ADVCFG_PLATFORM_MODULES HY_MODULES
+ #else
+ #if ADVCFG_PLATFORM_MODULES < HY_MODULES
+ #undef ADVCFG_PLATFORM_MODULES
+ #define ADVCFG_PLATFORM_MODULES HY_MODULES
+ #endif
+ #endif
+
+ #if GET_PATCHES == TRUE
+ #define F10_HY_UCODE_C4
+ #define F10_HY_UCODE_C5
+
+ // If a patch is required for recovery mode to function properly, add a
+ // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
+ #if AGESA_ENTRY_INIT_EARLY == TRUE
+ #if OPTION_C32_SOCKET_SUPPORT == TRUE
+ extern CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c5;
+ #undef F10_HY_UCODE_C5
+ #define F10_HY_UCODE_C5 &CpuF10MicrocodePatch010000c5,
+ #endif
+ #if (OPTION_C32_SOCKET_SUPPORT == TRUE) || (OPTION_G34_SOCKET_SUPPORT == TRUE)
+ extern CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c4;
+ #undef F10_HY_UCODE_C4
+ #define F10_HY_UCODE_C4 &CpuF10MicrocodePatch010000c4,
+ #endif
+ #endif
+
+ CONST MICROCODE_PATCHES ROMDATA *CpuF10HyMicroCodePatchArray[] =
+ {
+ F10_HY_UCODE_C4
+ F10_HY_UCODE_C5
+ NULL
+ };
+
+ CONST UINT8 ROMDATA CpuF10HyNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF10HyMicroCodePatchArray) / sizeof (CpuF10HyMicroCodePatchArray[0])) - 1);
+ #endif
+
+ #define OPT_F10_HY_CPU {AMD_FAMILY_10_HY, &cpuF10HyServices},
+ #else
+ #define OPT_F10_HY_CPU
+ #define OPT_F10_HY_ID
+ #endif
+#else
+ #define OPT_F10_HY_CPU
+ #define OPT_F10_HY_ID
+#endif
+
+/*
+ * Install family 10h model 10 support
+ */
+#ifdef OPTION_FAMILY10H_PH
+ #if OPTION_FAMILY10H_PH == TRUE
+ extern CONST REGISTER_TABLE ROMDATA F10RevEPciRegisterTable;
+ extern CONST REGISTER_TABLE ROMDATA F10RevEMsrRegisterTable;
+ extern CONST REGISTER_TABLE ROMDATA F10RevEHtPhyRegisterTable;
+ extern CONST REGISTER_TABLE ROMDATA F10PhPciRegisterTable;
+ extern CONST REGISTER_TABLE ROMDATA F10PhMsrRegisterTable;
+ extern CONST REGISTER_TABLE ROMDATA F10PhHtPhyRegisterTable;
+ extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10PhMicroCodePatchesStruct;
+ extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10PhMicrocodeEquivalenceTable;
+ extern F_CPU_GET_IDD_MAX F10CommonRevEGetProcIddMax;
+ extern F_CPU_GET_NB_PSTATE_INFO F10CommonRevEGetNbPstateInfo;
+ extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevEGetNbCofVidUpdate;
+ extern F_CPU_NUMBER_OF_BRANDSTRING_CORES F10CommonRevEGetNumberOfCoresForBrandstring;
+
+ #if USES_REGISTER_TABLES == TRUE
+ CONST REGISTER_TABLE ROMDATA *F10PhRegisterTables[] =
+ {
+ #if BASE_FAMILY_PCI == TRUE
+ &F10PciRegisterTable,
+ #endif
+ #if MODEL_SPECIFIC_PCI == TRUE
+ &F10SingleLinkPciRegisterTable,
+ #endif
+ #if MODEL_SPECIFIC_PCI == TRUE
+ &F10RevEPciRegisterTable,
+ #endif
+ #if BASE_FAMILY_MSR == TRUE
+ &F10MsrRegisterTable,
+ #endif
+ #if MODEL_SPECIFIC_MSR == TRUE
+ &F10RevEMsrRegisterTable,
+ #endif
+ #if MODEL_SPECIFIC_HT_PCI == TRUE
+ &F10HtPhyRegisterTable,
+ #endif
+ #if MODEL_SPECIFIC_HT_PCI == TRUE
+ &F10RevEHtPhyRegisterTable,
+ #endif
+ #if MODEL_SPECIFIC_HT_PCI == TRUE
+ &F10PhHtPhyRegisterTable,
+ #endif
+ #if BASE_FAMILY_WORKAROUNDS == TRUE
+ &F10WorkaroundsTable,
+ #endif
+ // the end.
+ NULL
+ };
+ #endif
+
+ #if USES_REGISTER_TABLES == TRUE
+ CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10PhTableEntryTypeDescriptors[] =
+ {
+ {MsrRegister, SetRegisterForMsrEntry},
+ {PciRegister, SetRegisterForPciEntry},
+ {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
+ {HtPhyRegister, SetRegisterForHtPhyEntry},
+ {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
+ {DeemphasisRegister, SetRegisterForDeemphasisEntry},
+ {ProfileFixup, SetRegisterForPerformanceProfileEntry},
+ {HtHostPciRegister, SetRegisterForHtHostEntry},
+ {HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid},
+ {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
+ {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
+ {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
+ {HtPhyProfileRegister, SetRegisterForHtPhyProfileEntry},
+ // End
+ {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
+ };
+ #endif
+
+ CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10PhServices =
+ {
+ 0,
+ #if DISABLE_PSTATE == TRUE
+ F10DisablePstate,
+ #else
+ (PF_CPU_DISABLE_PSTATE) CommonAssert,
+ #endif
+ #if TRANSITION_PSTATE == TRUE
+ F10TransitionPstate,
+ #else
+ (PF_CPU_TRANSITION_PSTATE) CommonAssert,
+ #endif
+ #if PROC_IDD_MAX == TRUE
+ F10CommonRevEGetProcIddMax,
+ #else
+ (PF_CPU_GET_IDD_MAX) CommonAssert,
+ #endif
+ #if GET_TSC_RATE == TRUE
+ F10GetTscRate,
+ #else
+ (PF_CPU_GET_TSC_RATE) CommonAssert,
+ #endif
+ #if GET_NB_FREQ == TRUE
+ F10GetCurrentNbFrequency,
+ #else
+ (PF_CPU_GET_NB_FREQ) CommonAssert,
+ #endif
+ #if GET_NB_FREQ == TRUE
+ F10CommonRevEGetNbPstateInfo,
+ #else
+ (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
+ #endif
+ #if IS_NBCOF_INIT_NEEDED == TRUE
+ F10CommonRevEGetNbCofVidUpdate,
+ #else
+ (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
+ #endif
+ #if AP_INITIAL_LAUNCH == TRUE
+ F10LaunchApCore,
+ #else
+ (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
+ #endif
+ #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
+ F10CommonRevEGetNumberOfCoresForBrandstring,
+ #else
+ (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
+ #endif
+ #if GET_AP_MAILBOX_FROM_HW == TRUE
+ F10GetApMailboxFromHardware,
+ #else
+ (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
+ #endif
+ #if SET_AP_CORE_NUMBER == TRUE
+ F10SetApCoreNumber,
+ #else
+ (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
+ #endif
+ #if GET_AP_CORE_NUMBER == TRUE
+ F10GetApCoreNumber,
+ #else
+ (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
+ #endif
+ #if TRANSFER_AP_CORE_NUMBER == TRUE
+ F10TransferApCoreNumber,
+ #else
+ (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
+ #endif
+ #if ID_POSITION_INITIAL_APICID == TRUE
+ F10CpuAmdCoreIdPositionInInitialApicId,
+ #else
+ (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
+ #endif
+ #if SAVE_FEATURES == TRUE
+ F10SaveFeatures,
+ #else
+ (PF_CPU_SAVE_FEATURES) CommonAssert,
+ #endif
+ #if WRITE_FEATURES == TRUE
+ F10WriteFeatures,
+ #else
+ (PF_CPU_WRITE_FEATURES) CommonAssert,
+ #endif
+ #if SET_WARM_RESET_FLAG == TRUE
+ F10SetAgesaWarmResetFlag,
+ #else
+ (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
+ #endif
+ #if GET_WARM_RESET_FLAG == TRUE
+ F10GetAgesaWarmResetFlag,
+ #else
+ (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
+ #endif
+ #if BRAND_STRING1 == TRUE
+ GetF10BrandIdString1,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if BRAND_STRING2 == TRUE
+ GetF10BrandIdString2,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_PATCHES == TRUE
+ GetF10PhMicroCodePatchesStruct,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
+ GetF10PhMicrocodeEquivalenceTable,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_CACHE_INFO == TRUE
+ GetF10CacheInfo,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_SYSTEM_PM_TABLE == TRUE
+ GetF10SysPmTable,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_WHEA_INIT == TRUE
+ GetF10WheaInitData,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
+ F10GetPlatformTypeSpecificInfo,
+ #else
+ (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
+ #endif
+ #if IS_NB_PSTATE_ENABLED == TRUE
+ (PF_IS_NB_PSTATE_ENABLED) CommonReturnFalse,
+ #else
+ (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
+ #endif
+ #if (BASE_FAMILY_HT_PCI == TRUE)
+ F10NextLinkHasHtPhyFeats,
+ #else
+ (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
+ #endif
+ #if (BASE_FAMILY_HT_PCI == TRUE)
+ F10SetHtPhyRegister,
+ #else
+ (PF_SET_HT_PHY_REGISTER) CommonAssert,
+ #endif
+ #if BASE_FAMILY_PCI == TRUE
+ F10GetNextHtLinkFeatures,
+ #else
+ (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
+ #endif
+ #if USES_REGISTER_TABLES == TRUE
+ (REGISTER_TABLE **) F10PhRegisterTables,
+ #else
+ NULL,
+ #endif
+ #if USES_REGISTER_TABLES == TRUE
+ (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10PhTableEntryTypeDescriptors,
+ #else
+ NULL,
+ #endif
+ NULL,
+ NULL,
+ InitCacheDisabled,
+ #if AGESA_ENTRY_INIT_EARLY == TRUE
+ GetF10EarlyInitOnCoreTable
+ #else
+ (PF_GET_EARLY_INIT_TABLE) CommonVoid
+ #endif
+ };
+
+ #define PH_SOCKETS 1
+ #define PH_MODULES 1
+ #define PH_RECOVERY_SOCKETS 1
+ #define PH_RECOVERY_MODULES 1
+ extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10PhLogicalIdAndRev;
+ #define OPT_F10_PH_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10PhLogicalIdAndRev,
+ #ifndef ADVCFG_PLATFORM_SOCKETS
+ #define ADVCFG_PLATFORM_SOCKETS PH_SOCKETS
+ #else
+ #if ADVCFG_PLATFORM_SOCKETS < PH_SOCKETS
+ #undef ADVCFG_PLATFORM_SOCKETS
+ #define ADVCFG_PLATFORM_SOCKETS PH_SOCKETS
+ #endif
+ #endif
+ #ifndef ADVCFG_PLATFORM_MODULES
+ #define ADVCFG_PLATFORM_MODULES PH_MODULES
+ #else
+ #if ADVCFG_PLATFORM_MODULES < PH_MODULES
+ #undef ADVCFG_PLATFORM_MODULES
+ #define ADVCFG_PLATFORM_MODULES PH_MODULES
+ #endif
+ #endif
+
+ #if GET_PATCHES == TRUE
+ #define F10_PH_UCODE_BF
+
+ // If a patch is required for recovery mode to function properly, add a
+ // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
+ #if AGESA_ENTRY_INIT_EARLY == TRUE
+ #if OPTION_AM3_SOCKET_SUPPORT == TRUE
+ extern CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000bf;
+ #undef F10_PH_UCODE_BF
+ #define F10_PH_UCODE_BF &CpuF10MicrocodePatch010000bf,
+ #endif
+ #endif
+
+ CONST MICROCODE_PATCHES ROMDATA *CpuF10PhMicroCodePatchArray[] =
+ {
+ F10_PH_UCODE_BF
+ NULL
+ };
+
+ CONST UINT8 ROMDATA CpuF10PhNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF10PhMicroCodePatchArray) / sizeof (CpuF10PhMicroCodePatchArray[0])) - 1);
+ #endif
+
+ #define OPT_F10_PH_CPU {AMD_FAMILY_10_PH, &cpuF10PhServices},
+ #else
+ #define OPT_F10_PH_CPU
+ #define OPT_F10_PH_ID
+ #endif
+#else
+ #define OPT_F10_PH_CPU
+ #define OPT_F10_PH_ID
+#endif
+
+
+/*
+ * Install family 10h model 4 support
+ */
+#ifdef OPTION_FAMILY10H_RB
+ #if OPTION_FAMILY10H_RB == TRUE
+ extern CONST REGISTER_TABLE ROMDATA F10RevCPciRegisterTable;
+ extern CONST REGISTER_TABLE ROMDATA F10RevCMsrRegisterTable;
+ extern CONST REGISTER_TABLE ROMDATA F10RevCHtPhyRegisterTable;
+ extern CONST REGISTER_TABLE ROMDATA F10RbPciRegisterTable;
+ extern CONST REGISTER_TABLE ROMDATA F10RbMsrRegisterTable;
+ extern CONST REGISTER_TABLE ROMDATA F10RbHtPhyRegisterTable;
+ extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10RbMicroCodePatchesStruct;
+ extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10RbMicrocodeEquivalenceTable;
+ extern F_CPU_GET_IDD_MAX F10CommonRevCGetProcIddMax;
+ extern F_CPU_GET_NB_PSTATE_INFO F10CommonRevCGetNbPstateInfo;
+ extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevCGetNbCofVidUpdate;
+ extern F_IS_NB_PSTATE_ENABLED F10CommonRevCIsNbPstateEnabled;
+ extern F_CPU_NUMBER_OF_BRANDSTRING_CORES F10CommonRevCGetNumberOfCoresForBrandstring;
+
+ #if USES_REGISTER_TABLES == TRUE
+ CONST REGISTER_TABLE ROMDATA *F10RbRegisterTables[] =
+ {
+ #if BASE_FAMILY_PCI == TRUE
+ &F10PciRegisterTable,
+ #endif
+ #if MODEL_SPECIFIC_PCI == TRUE
+ &F10MultiLinkPciRegisterTable,
+ &F10SingleLinkPciRegisterTable,
+ #endif
+ #if MODEL_SPECIFIC_PCI == TRUE
+ &F10RevCPciRegisterTable,
+ #endif
+ #if MODEL_SPECIFIC_PCI == TRUE
+ &F10RbPciRegisterTable,
+ #endif
+ #if BASE_FAMILY_MSR == TRUE
+ &F10MsrRegisterTable,
+ #endif
+ #if MODEL_SPECIFIC_MSR == TRUE
+ &F10RevCMsrRegisterTable,
+ #endif
+ #if MODEL_SPECIFIC_MSR == TRUE
+ &F10RbMsrRegisterTable,
+ #endif
+ #if MODEL_SPECIFIC_HT_PCI == TRUE
+ &F10HtPhyRegisterTable,
+ #endif
+ #if MODEL_SPECIFIC_HT_PCI == TRUE
+ &F10RevCHtPhyRegisterTable,
+ #endif
+ #if MODEL_SPECIFIC_HT_PCI == TRUE
+ &F10RbHtPhyRegisterTable,
+ #endif
+ #if BASE_FAMILY_WORKAROUNDS == TRUE
+ &F10WorkaroundsTable,
+ #endif
+ // the end.
+ NULL
+ };
+ #endif
+
+ #if USES_REGISTER_TABLES == TRUE
+ CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10RbTableEntryTypeDescriptors[] =
+ {
+ {MsrRegister, SetRegisterForMsrEntry},
+ {PciRegister, SetRegisterForPciEntry},
+ {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
+ {HtPhyRegister, SetRegisterForHtPhyEntry},
+ {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
+ {DeemphasisRegister, SetRegisterForDeemphasisEntry},
+ {ProfileFixup, SetRegisterForPerformanceProfileEntry},
+ {HtHostPciRegister, SetRegisterForHtHostEntry},
+ {HtTokenPciRegister, SetRegisterForHtLinkTokenEntry},
+ {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
+ {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
+ {TokenPciRegister, SetRegisterForTokenPciEntry},
+ {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
+ {HtPhyProfileRegister, SetRegisterForHtPhyProfileEntry},
+ // End
+ {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
+ };
+ #endif
+
+ CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10RbServices =
+ {
+ 0,
+ #if DISABLE_PSTATE == TRUE
+ F10DisablePstate,
+ #else
+ (PF_CPU_DISABLE_PSTATE) CommonAssert,
+ #endif
+ #if TRANSITION_PSTATE == TRUE
+ F10TransitionPstate,
+ #else
+ (PF_CPU_TRANSITION_PSTATE) CommonAssert,
+ #endif
+ #if PROC_IDD_MAX == TRUE
+ F10CommonRevCGetProcIddMax,
+ #else
+ (PF_CPU_GET_IDD_MAX) CommonAssert,
+ #endif
+ #if GET_TSC_RATE == TRUE
+ F10GetTscRate,
+ #else
+ (PF_CPU_GET_TSC_RATE) CommonAssert,
+ #endif
+ #if GET_NB_FREQ == TRUE
+ F10GetCurrentNbFrequency,
+ #else
+ (PF_CPU_GET_NB_FREQ) CommonAssert,
+ #endif
+ #if GET_NB_FREQ == TRUE
+ F10CommonRevCGetNbPstateInfo,
+ #else
+ (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
+ #endif
+ #if IS_NBCOF_INIT_NEEDED == TRUE
+ F10CommonRevCGetNbCofVidUpdate,
+ #else
+ (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
+ #endif
+ #if AP_INITIAL_LAUNCH == TRUE
+ F10LaunchApCore,
+ #else
+ (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
+ #endif
+ #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
+ F10CommonRevCGetNumberOfCoresForBrandstring,
+ #else
+ (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
+ #endif
+ #if GET_AP_MAILBOX_FROM_HW == TRUE
+ F10GetApMailboxFromHardware,
+ #else
+ (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
+ #endif
+ #if SET_AP_CORE_NUMBER == TRUE
+ F10SetApCoreNumber,
+ #else
+ (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
+ #endif
+ #if GET_AP_CORE_NUMBER == TRUE
+ F10GetApCoreNumber,
+ #else
+ (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
+ #endif
+ #if TRANSFER_AP_CORE_NUMBER == TRUE
+ F10TransferApCoreNumber,
+ #else
+ (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
+ #endif
+ #if ID_POSITION_INITIAL_APICID == TRUE
+ F10CpuAmdCoreIdPositionInInitialApicId,
+ #else
+ (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
+ #endif
+ #if SAVE_FEATURES == TRUE
+ F10SaveFeatures,
+ #else
+ (PF_CPU_SAVE_FEATURES) CommonAssert,
+ #endif
+ #if WRITE_FEATURES == TRUE
+ F10WriteFeatures,
+ #else
+ (PF_CPU_WRITE_FEATURES) CommonAssert,
+ #endif
+ #if SET_WARM_RESET_FLAG == TRUE
+ F10SetAgesaWarmResetFlag,
+ #else
+ (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
+ #endif
+ #if GET_WARM_RESET_FLAG == TRUE
+ F10GetAgesaWarmResetFlag,
+ #else
+ (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
+ #endif
+ #if BRAND_STRING1 == TRUE
+ GetF10BrandIdString1,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if BRAND_STRING2 == TRUE
+ GetF10BrandIdString2,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_PATCHES == TRUE
+ GetF10RbMicroCodePatchesStruct,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
+ GetF10RbMicrocodeEquivalenceTable,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_CACHE_INFO == TRUE
+ GetF10CacheInfo,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_SYSTEM_PM_TABLE == TRUE
+ GetF10SysPmTable,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_WHEA_INIT == TRUE
+ GetF10WheaInitData,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
+ F10GetPlatformTypeSpecificInfo,
+ #else
+ (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
+ #endif
+ #if IS_NB_PSTATE_ENABLED == TRUE
+ F10CommonRevCIsNbPstateEnabled,
+ #else
+ (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
+ #endif
+ #if (BASE_FAMILY_HT_PCI == TRUE)
+ F10NextLinkHasHtPhyFeats,
+ #else
+ (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
+ #endif
+ #if (BASE_FAMILY_HT_PCI == TRUE)
+ F10SetHtPhyRegister,
+ #else
+ (PF_SET_HT_PHY_REGISTER) CommonAssert,
+ #endif
+ #if BASE_FAMILY_PCI == TRUE
+ F10GetNextHtLinkFeatures,
+ #else
+ (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
+ #endif
+ #if USES_REGISTER_TABLES == TRUE
+ (REGISTER_TABLE **) F10RbRegisterTables,
+ #else
+ NULL,
+ #endif
+ #if USES_REGISTER_TABLES == TRUE
+ (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10RbTableEntryTypeDescriptors,
+ #else
+ NULL,
+ #endif
+ NULL,
+ NULL,
+ InitCacheDisabled,
+ #if AGESA_ENTRY_INIT_EARLY == TRUE
+ GetF10EarlyInitOnCoreTable
+ #else
+ (PF_GET_EARLY_INIT_TABLE) CommonVoid
+ #endif
+ };
+
+ #define RB_SOCKETS 8
+ #define RB_MODULES 1
+ #define RB_RECOVERY_SOCKETS 1
+ #define RB_RECOVERY_MODULES 1
+ extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10RbLogicalIdAndRev;
+ #define OPT_F10_RB_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10RbLogicalIdAndRev,
+ #ifndef ADVCFG_PLATFORM_SOCKETS
+ #define ADVCFG_PLATFORM_SOCKETS RB_SOCKETS
+ #else
+ #if ADVCFG_PLATFORM_SOCKETS < RB_SOCKETS
+ #undef ADVCFG_PLATFORM_SOCKETS
+ #define ADVCFG_PLATFORM_SOCKETS RB_SOCKETS
+ #endif
+ #endif
+ #ifndef ADVCFG_PLATFORM_MODULES
+ #define ADVCFG_PLATFORM_MODULES RB_MODULES
+ #else
+ #if ADVCFG_PLATFORM_MODULES < RB_MODULES
+ #undef ADVCFG_PLATFORM_MODULES
+ #define ADVCFG_PLATFORM_MODULES RB_MODULES
+ #endif
+ #endif
+
+ #if GET_PATCHES == TRUE
+ #define F10_RB_UCODE_85
+ #define F10_RB_UCODE_C6
+ #define F10_RB_UCODE_C8
+
+ // If a patch is required for recovery mode to function properly, add a
+ // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
+ #if AGESA_ENTRY_INIT_EARLY == TRUE
+ #if OPTION_AM3_SOCKET_SUPPORT == TRUE
+ extern CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch01000085;
+ extern CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c6;
+ extern CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c8;
+ #undef F10_RB_UCODE_85
+ #define F10_RB_UCODE_85 &CpuF10MicrocodePatch01000085,
+ #undef F10_RB_UCODE_C6
+ #define F10_RB_UCODE_C6 &CpuF10MicrocodePatch010000c6,
+ #undef F10_RB_UCODE_C8
+ #define F10_RB_UCODE_C8 &CpuF10MicrocodePatch010000c8,
+ #endif
+ #endif
+
+ CONST MICROCODE_PATCHES ROMDATA *CpuF10RbMicroCodePatchArray[] =
+ {
+ F10_RB_UCODE_85
+ F10_RB_UCODE_C6
+ F10_RB_UCODE_C8
+ NULL
+ };
+
+ CONST UINT8 ROMDATA CpuF10RbNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF10RbMicroCodePatchArray) / sizeof (CpuF10RbMicroCodePatchArray[0])) - 1);
+ #endif
+
+ #define OPT_F10_RB_CPU {AMD_FAMILY_10_RB, &cpuF10RbServices},
+ #else
+ #define OPT_F10_RB_CPU
+ #define OPT_F10_RB_ID
+ #endif
+#else
+ #define OPT_F10_RB_CPU
+ #define OPT_F10_RB_ID
+#endif
+
+
+/*
+ * Install unknown family 10h support
+ */
+
+#if USES_REGISTER_TABLES == TRUE
+ CONST REGISTER_TABLE ROMDATA *F10UnknownRegisterTables[] =
+ {
+ #if BASE_FAMILY_PCI == TRUE
+ &F10PciRegisterTable,
+ #endif
+ #if BASE_FAMILY_MSR == TRUE
+ &F10MsrRegisterTable,
+ #endif
+ #if BASE_FAMILY_HT_PCI == TRUE
+ &F10HtPhyRegisterTable,
+ #endif
+ #if OPTION_MULTISOCKET == TRUE
+ #if MODEL_SPECIFIC_PCI == TRUE
+ &F10MultiLinkPciRegisterTable,
+ #endif
+ #endif
+ #if OPTION_MULTISOCKET == FALSE
+ #if MODEL_SPECIFIC_PCI == TRUE
+ &F10SingleLinkPciRegisterTable,
+ #endif
+ #endif
+ #if BASE_FAMILY_WORKAROUNDS == TRUE
+ &F10WorkaroundsTable,
+ #endif
+ // the end.
+ NULL
+ };
+#endif
+
+#if USES_REGISTER_TABLES == TRUE
+ CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10UnknownTableEntryTypeDescriptors[] =
+ {
+ {MsrRegister, SetRegisterForMsrEntry},
+ {PciRegister, SetRegisterForPciEntry},
+ {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
+ {HtPhyRegister, SetRegisterForHtPhyEntry},
+ {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
+ {DeemphasisRegister, SetRegisterForDeemphasisEntry},
+ {ProfileFixup, SetRegisterForPerformanceProfileEntry},
+ {HtHostPciRegister, SetRegisterForHtHostEntry},
+ {HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid},
+ {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
+ {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
+ {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
+ // End
+ {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
+ };
+#endif
+
+
+CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10UnknownServices =
+{
+ 0,
+ #if DISABLE_PSTATE == TRUE
+ F10DisablePstate,
+ #else
+ (PF_CPU_DISABLE_PSTATE) CommonAssert,
+ #endif
+ #if TRANSITION_PSTATE == TRUE
+ F10TransitionPstate,
+ #else
+ (PF_CPU_TRANSITION_PSTATE) CommonAssert,
+ #endif
+ #if PROC_IDD_MAX == TRUE
+ (PF_CPU_GET_IDD_MAX) CommonReturnFalse,
+ #else
+ (PF_CPU_GET_IDD_MAX) CommonAssert,
+ #endif
+ #if GET_TSC_RATE == TRUE
+ F10GetTscRate,
+ #else
+ (PF_CPU_GET_TSC_RATE) CommonAssert,
+ #endif
+ #if GET_NB_FREQ == TRUE
+ F10GetCurrentNbFrequency,
+ #else
+ (PF_CPU_GET_NB_FREQ) CommonAssert,
+ #endif
+ #if GET_NB_FREQ == TRUE
+ (PF_CPU_GET_NB_PSTATE_INFO) CommonReturnFalse,
+ #else
+ (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
+ #endif
+ #if IS_NBCOF_INIT_NEEDED == TRUE
+ (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonReturnFalse,
+ #else
+ (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
+ #endif
+ #if AP_INITIAL_LAUNCH == TRUE
+ F10LaunchApCore,
+ #else
+ (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
+ #endif
+ #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
+ (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonReturnZero8,
+ #else
+ (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
+ #endif
+ #if GET_AP_MAILBOX_FROM_HW == TRUE
+ F10GetApMailboxFromHardware,
+ #else
+ (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
+ #endif
+ #if SET_AP_CORE_NUMBER == TRUE
+ F10SetApCoreNumber,
+ #else
+ (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
+ #endif
+ #if GET_AP_CORE_NUMBER == TRUE
+ F10GetApCoreNumber,
+ #else
+ (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
+ #endif
+ #if TRANSFER_AP_CORE_NUMBER == TRUE
+ F10TransferApCoreNumber,
+ #else
+ (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
+ #endif
+ #if ID_POSITION_INITIAL_APICID == TRUE
+ F10CpuAmdCoreIdPositionInInitialApicId,
+ #else
+ (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
+ #endif
+ #if SAVE_FEATURES == TRUE
+ F10SaveFeatures,
+ #else
+ (PF_CPU_SAVE_FEATURES) CommonAssert,
+ #endif
+ #if WRITE_FEATURES == TRUE
+ F10WriteFeatures,
+ #else
+ (PF_CPU_WRITE_FEATURES) CommonAssert,
+ #endif
+ #if SET_WARM_RESET_FLAG == TRUE
+ F10SetAgesaWarmResetFlag,
+ #else
+ (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
+ #endif
+ #if GET_WARM_RESET_FLAG == TRUE
+ F10GetAgesaWarmResetFlag,
+ #else
+ (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
+ #endif
+ #if BRAND_STRING1 == TRUE
+ GetF10BrandIdString1,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if BRAND_STRING2 == TRUE
+ GetF10BrandIdString2,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_PATCHES == TRUE
+ GetEmptyArray,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
+ GetEmptyArray,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_CACHE_INFO == TRUE
+ GetF10CacheInfo,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_SYSTEM_PM_TABLE == TRUE
+ GetF10SysPmTable,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_WHEA_INIT == TRUE
+ GetF10WheaInitData,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
+ F10GetPlatformTypeSpecificInfo,
+ #else
+ (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
+ #endif
+ #if IS_NB_PSTATE_ENABLED == TRUE
+ (PF_IS_NB_PSTATE_ENABLED) CommonReturnFalse,
+ #else
+ (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
+ #endif
+ #if (BASE_FAMILY_HT_PCI == TRUE)
+ F10NextLinkHasHtPhyFeats,
+ #else
+ (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
+ #endif
+ #if (BASE_FAMILY_HT_PCI == TRUE)
+ F10SetHtPhyRegister,
+ #else
+ (PF_SET_HT_PHY_REGISTER) CommonVoid,
+ #endif
+ #if BASE_FAMILY_PCI == TRUE
+ F10GetNextHtLinkFeatures,
+ #else
+ (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
+ #endif
+ #if USES_REGISTER_TABLES == TRUE
+ (REGISTER_TABLE **) F10UnknownRegisterTables,
+ #else
+ NULL,
+ #endif
+ #if USES_REGISTER_TABLES == TRUE
+ (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10UnknownTableEntryTypeDescriptors,
+ #else
+ NULL,
+ #endif
+ NULL,
+ NULL,
+ InitCacheDisabled,
+ #if AGESA_ENTRY_INIT_EARLY == TRUE
+ GetF10EarlyInitOnCoreTable
+ #else
+ (PF_GET_EARLY_INIT_TABLE) CommonVoid
+ #endif
+};
+
+// Family 10h maximum base address is 48 bits. Limit BLDCFG to 48 bits, if appropriate.
+#if (FAMILY_MMIO_BASE_MASK < 0xFFFF000000000000ull)
+ #undef FAMILY_MMIO_BASE_MASK
+ #define FAMILY_MMIO_BASE_MASK (0xFFFF000000000000ull)
+#endif
+
+#undef OPT_F10_ID_TABLE
+#define OPT_F10_ID_TABLE {0x10, {AMD_FAMILY_10, AMD_F10_UNKNOWN}, F10LogicalIdTable, (sizeof (F10LogicalIdTable) / sizeof (F10LogicalIdTable[0]))},
+#define OPT_F10_UNKNOWN_CPU {AMD_FAMILY_10, &cpuF10UnknownServices},
+
+#undef OPT_F10_TABLE
+#define OPT_F10_TABLE OPT_F10_BL_CPU OPT_F10_DA_CPU OPT_F10_HY_CPU OPT_F10_PH_CPU OPT_F10_RB_CPU OPT_F10_UNKNOWN_CPU
+
+#if OPTION_G34_SOCKET_SUPPORT == TRUE
+ extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayG34;
+ extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayG34;
+ #define F10_G34_BRANDSTRING1 &F10BrandIdString1ArrayG34,
+ #define F10_G34_BRANDSTRING2 &F10BrandIdString2ArrayG34,
+#else
+ #define F10_G34_BRANDSTRING1
+ #define F10_G34_BRANDSTRING2
+#endif
+#if OPTION_C32_SOCKET_SUPPORT == TRUE
+ extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayC32;
+ extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayC32;
+ #define F10_C32_BRANDSTRING1 &F10BrandIdString1ArrayC32,
+ #define F10_C32_BRANDSTRING2 &F10BrandIdString2ArrayC32,
+#else
+ #define F10_C32_BRANDSTRING1
+ #define F10_C32_BRANDSTRING2
+#endif
+#if OPTION_S1G3_SOCKET_SUPPORT == TRUE
+ extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayS1g3;
+ extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayS1g3;
+ #define F10_S1G3_BRANDSTRING1 &F10BrandIdString1ArrayS1g3,
+ #define F10_S1G3_BRANDSTRING2 &F10BrandIdString2ArrayS1g3,
+#else
+ #define F10_S1G3_BRANDSTRING1
+ #define F10_S1G3_BRANDSTRING2
+#endif
+#if OPTION_S1G4_SOCKET_SUPPORT == TRUE
+ extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayS1g4;
+ extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayS1g4;
+ #define F10_S1G4_BRANDSTRING1 &F10BrandIdString1ArrayS1g4,
+ #define F10_S1G4_BRANDSTRING2 &F10BrandIdString2ArrayS1g4,
+#else
+ #define F10_S1G4_BRANDSTRING1
+ #define F10_S1G4_BRANDSTRING2
+#endif
+#if OPTION_ASB2_SOCKET_SUPPORT == TRUE
+ extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayAsb2;
+ extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayAsb2;
+ #define F10_ASB2_BRANDSTRING1 &F10BrandIdString1ArrayAsb2,
+ #define F10_ASB2_BRANDSTRING2 &F10BrandIdString2ArrayAsb2,
+#else
+ #define F10_ASB2_BRANDSTRING1
+ #define F10_ASB2_BRANDSTRING2
+#endif
+#if OPTION_AM3_SOCKET_SUPPORT == TRUE
+ extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayAm3;
+ extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayAm3;
+ #define F10_AM3_BRANDSTRING1 &F10BrandIdString1ArrayAm3,
+ #define F10_AM3_BRANDSTRING2 &F10BrandIdString2ArrayAm3,
+#else
+ #define F10_AM3_BRANDSTRING1
+ #define F10_AM3_BRANDSTRING2
+#endif
+
+#if BRAND_STRING1 == TRUE
+ CONST CPU_BRAND_TABLE ROMDATA *F10BrandIdString1Tables[] =
+ {
+ F10_G34_BRANDSTRING1
+ F10_C32_BRANDSTRING1
+ F10_S1G3_BRANDSTRING1
+ F10_S1G4_BRANDSTRING1
+ F10_ASB2_BRANDSTRING1
+ F10_AM3_BRANDSTRING1
+ };
+
+ CONST UINT8 F10BrandIdString1TableCount = (sizeof (F10BrandIdString1Tables) / sizeof (F10BrandIdString1Tables[0]));
+#endif
+
+#if BRAND_STRING2 == TRUE
+ CONST CPU_BRAND_TABLE ROMDATA *F10BrandIdString2Tables[] =
+ {
+ F10_G34_BRANDSTRING2
+ F10_C32_BRANDSTRING2
+ F10_S1G3_BRANDSTRING2
+ F10_S1G4_BRANDSTRING2
+ F10_ASB2_BRANDSTRING2
+ F10_AM3_BRANDSTRING2
+ };
+
+ CONST UINT8 F10BrandIdString2TableCount = (sizeof (F10BrandIdString2Tables) / sizeof (F10BrandIdString2Tables[0]));
+#endif
+
+CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY ROMDATA F10LogicalIdTable[] =
+{
+ OPT_F10_BL_ID
+ OPT_F10_DA_ID
+ OPT_F10_HY_ID
+ OPT_F10_PH_ID
+ OPT_F10_RB_ID
+};
+
+#endif // _OPTION_FAMILY_10H_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionFamily12hEarlySample.h b/src/vendorcode/amd/agesa/f14/Include/OptionFamily12hEarlySample.h
new file mode 100644
index 0000000..e475a18
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Include/OptionFamily12hEarlySample.h
@@ -0,0 +1,138 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Family 12h 'early sample' support
+ *
+ * This file defines the required structures for family 12h pre-production processors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Core
+ * @e \$Revision: 37456 $ @e \$Date: 2010-09-04 04:17:05 +0800 (Sat, 04 Sep 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _OPTION_FAMILY_12H_EARLY_SAMPLE_H_
+#define _OPTION_FAMILY_12H_EARLY_SAMPLE_H_
+
+
+/*---------------------------------------------------------------------------------------
+ * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ * T Y P E D E F S, S T R U C T U R E S, E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+/**
+ * Return the appropriate values of certain NB P-state related registers.
+ *
+ * @param[in,out] FCRxFE00_6000 The value of FCRxFE006000.
+ * @param[in,out] FCRxFE00_6002 The value of FCRxFE006002.
+ * @param[in,out] FCRxFE00_7006 The value of FCRxFE007006.
+ * @param[in,out] FCRxFE00_7009 The value of FCRxFE007009.
+ * @param[in] MainPll The main PLL frequency.
+ * @param[in] StdHeader Handle of Header for calling lib functions and services.
+ *
+ */
+typedef VOID F_F12_ES_NB_PSTATE_INIT (
+ IN OUT VOID *FCRxFE00_6000,
+ IN OUT VOID *FCRxFE00_6002,
+ IN OUT VOID *FCRxFE00_7006,
+ IN OUT VOID *FCRxFE00_7009,
+ IN UINT32 MainPll,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+/// Reference to a Method.
+typedef F_F12_ES_NB_PSTATE_INIT *PF_F12_ES_NB_PSTATE_INIT;
+
+/**
+ * Return the appropriate value of a certain NB P-state related register.
+ *
+ * @param[in,out] FCRxFE00_6000 The value of FCRxFE006000.
+ * @param[in] StdHeader Handle of Header for calling lib functions and services.
+ *
+ */
+typedef VOID F_F12_ES_POWER_PLANE_INIT (
+ IN OUT VOID *FCRxFE00_6000,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+/// Reference to a Method.
+typedef F_F12_ES_POWER_PLANE_INIT *PF_F12_ES_POWER_PLANE_INIT;
+
+/**
+ * Implements an early sample workaround required for C6
+ *
+ * @param[in] StdHeader Handle of Header for calling lib functions and services.
+ *
+ */
+typedef VOID F_F12_ES_C6_INIT (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+/// Reference to a Method.
+typedef F_F12_ES_C6_INIT *PF_F12_ES_C6_INIT;
+
+
+/// Hook points in the core functionality necessary for
+/// providing support for pre-production CPUs.
+typedef struct {
+ PF_F12_ES_POWER_PLANE_INIT F12PowerPlaneInitHook; ///< Allows for override of a certain processor register value during power plane init
+ PF_F12_ES_NB_PSTATE_INIT F12NbPstateInitHook; ///< Allows for override of certain processor register values for proper NB P-state init
+} F12_ES_CORE_SUPPORT;
+
+/// Hook points in the C6 feature necessary for
+/// providing support for pre-production CPUs.
+typedef struct {
+ PF_F12_ES_C6_INIT F12InitializeC6; ///< Hook for erratum 453 workaround
+} F12_ES_C6_SUPPORT;
+
+
+/*---------------------------------------------------------------------------------------
+ * F U N C T I O N P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+
+
+#endif // _OPTION_FAMILY_12H_EARLY_SAMPLE_H_
diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionFamily12hInstall.h b/src/vendorcode/amd/agesa/f14/Include/OptionFamily12hInstall.h
new file mode 100644
index 0000000..63e8b27
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Include/OptionFamily12hInstall.h
@@ -0,0 +1,665 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of family 12h support
+ *
+ * This file generates the defaults tables for family 12h processors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Core
+ * @e \$Revision: 37456 $ @e \$Date: 2010-09-04 04:17:05 +0800 (Sat, 04 Sep 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _OPTION_FAMILY_12H_INSTALL_H_
+#define _OPTION_FAMILY_12H_INSTALL_H_
+
+
+#include "OptionFamily12hEarlySample.h"
+
+/*
+ * Common Family 12h routines
+ */
+extern F_CPU_DISABLE_PSTATE F12DisablePstate;
+extern F_CPU_TRANSITION_PSTATE F12TransitionPstate;
+extern F_CPU_GET_TSC_RATE F12GetTscRate;
+extern F_CPU_GET_NB_FREQ F12GetCurrentNbFrequency;
+extern F_CPU_GET_NB_PSTATE_INFO F12GetNbPstateInfo;
+extern F_CPU_IS_NBCOF_INIT_NEEDED F12GetNbCofVidUpdate;
+extern F_CPU_AP_INITIAL_LAUNCH F12LaunchApCore;
+extern F_CPU_GET_IDD_MAX F12GetProcIddMax;
+extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F12GetApMailboxFromHardware;
+extern F_CPU_GET_AP_CORE_NUMBER F12GetApCoreNumber;
+extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F12CpuAmdCoreIdPositionInInitialApicId;
+extern F_CPU_SET_DOWN_CORE_REGISTER F12SetDownCoreRegister;
+extern F_CPU_SET_WARM_RESET_FLAG F12SetAgesaWarmResetFlag;
+extern F_CPU_GET_WARM_RESET_FLAG F12GetAgesaWarmResetFlag;
+extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12BrandIdString1;
+extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12BrandIdString2;
+extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12CacheInfo;
+extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12SysPmTable;
+extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12WheaInitData;
+extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetEmptyArray;
+extern F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO F12GetPlatformTypeSpecificInfo;
+extern CONST REGISTER_TABLE ROMDATA F12PciRegisterTable;
+extern CONST REGISTER_TABLE ROMDATA F12PerCorePciRegisterTable;
+extern CONST REGISTER_TABLE ROMDATA F12MsrRegisterTable;
+extern F_CPU_NUMBER_OF_BRANDSTRING_CORES F12GetNumberOfCoresForBrandstring;
+extern F_GET_EARLY_INIT_TABLE GetCommonEarlyInitOnCoreTable;
+extern F_IS_NB_PSTATE_ENABLED F12IsNbPstateEnabled;
+#if OPTION_EARLY_SAMPLES == TRUE
+ extern CONST REGISTER_TABLE ROMDATA F12EarlySampleMsrRegisterTable;
+#endif
+
+/*
+ * Install family 12h model 0 support
+ */
+
+#ifdef OPTION_FAMILY12H_LN
+ #if OPTION_FAMILY12H_LN == TRUE
+ extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12LnMicroCodePatchesStruct;
+ extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12LnMicrocodeEquivalenceTable;
+
+ #if USES_REGISTER_TABLES == TRUE
+ CONST REGISTER_TABLE ROMDATA *F12LnRegisterTables[] =
+ {
+ #if BASE_FAMILY_PCI == TRUE
+ &F12PciRegisterTable,
+ #endif
+ #if BASE_FAMILY_PCI == TRUE
+ &F12PerCorePciRegisterTable,
+ #endif
+ #if BASE_FAMILY_MSR == TRUE
+ &F12MsrRegisterTable,
+ #if OPTION_EARLY_SAMPLES == TRUE
+ &F12EarlySampleMsrRegisterTable,
+ #endif
+ #endif
+ // the end.
+ NULL
+ };
+ #endif
+
+ #if USES_REGISTER_TABLES == TRUE
+ CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F12LnTableEntryTypeDescriptors[] =
+ {
+ {MsrRegister, SetRegisterForMsrEntry},
+ {PciRegister, SetRegisterForPciEntry},
+ {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
+ {ProfileFixup, (PF_DO_TABLE_ENTRY)CommonVoid},
+ // End
+ {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
+ };
+ #endif
+
+ CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF12LnServices =
+ {
+ 0,
+ #if DISABLE_PSTATE == TRUE
+ F12DisablePstate,
+ #else
+ (PF_CPU_DISABLE_PSTATE) CommonAssert,
+ #endif
+ #if TRANSITION_PSTATE == TRUE
+ F12TransitionPstate,
+ #else
+ (PF_CPU_TRANSITION_PSTATE) CommonAssert,
+ #endif
+ #if PROC_IDD_MAX == TRUE
+ F12GetProcIddMax,
+ #else
+ (PF_CPU_GET_IDD_MAX) CommonAssert,
+ #endif
+ #if GET_TSC_RATE == TRUE
+ F12GetTscRate,
+ #else
+ (PF_CPU_GET_TSC_RATE) CommonAssert,
+ #endif
+ #if GET_NB_FREQ == TRUE
+ F12GetCurrentNbFrequency,
+ #else
+ (PF_CPU_GET_NB_FREQ) CommonAssert,
+ #endif
+ #if GET_NB_FREQ == TRUE
+ F12GetNbPstateInfo,
+ #else
+ (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
+ #endif
+ #if IS_NBCOF_INIT_NEEDED == TRUE
+ F12GetNbCofVidUpdate,
+ #else
+ (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
+ #endif
+ #if AP_INITIAL_LAUNCH == TRUE
+ F12LaunchApCore,
+ #else
+ (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
+ #endif
+ #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
+ F12GetNumberOfCoresForBrandstring,
+ #else
+ (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
+ #endif
+ #if GET_AP_MAILBOX_FROM_HW == TRUE
+ F12GetApMailboxFromHardware,
+ #else
+ (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
+ #endif
+ #if SET_AP_CORE_NUMBER == TRUE
+ (PF_CPU_SET_AP_CORE_NUMBER) CommonVoid,
+ #else
+ (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
+ #endif
+ #if GET_AP_CORE_NUMBER == TRUE
+ F12GetApCoreNumber,
+ #else
+ (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
+ #endif
+ #if TRANSFER_AP_CORE_NUMBER == TRUE
+ (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid,
+ #else
+ (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
+ #endif
+ #if ID_POSITION_INITIAL_APICID == TRUE
+ F12CpuAmdCoreIdPositionInInitialApicId,
+ #else
+ (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
+ #endif
+ #if SAVE_FEATURES == TRUE
+ (PF_CPU_SAVE_FEATURES) CommonVoid,
+ #else
+ (PF_CPU_SAVE_FEATURES) CommonAssert,
+ #endif
+ #if WRITE_FEATURES == TRUE
+ (PF_CPU_WRITE_FEATURES) CommonVoid,
+ #else
+ (PF_CPU_WRITE_FEATURES) CommonAssert,
+ #endif
+ #if SET_WARM_RESET_FLAG == TRUE
+ F12SetAgesaWarmResetFlag,
+ #else
+ (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
+ #endif
+ #if GET_WARM_RESET_FLAG == TRUE
+ F12GetAgesaWarmResetFlag,
+ #else
+ (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
+ #endif
+ #if BRAND_STRING1 == TRUE
+ GetF12BrandIdString1,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if BRAND_STRING2 == TRUE
+ GetF12BrandIdString2,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_PATCHES == TRUE
+ GetF12LnMicroCodePatchesStruct,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
+ GetF12LnMicrocodeEquivalenceTable,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_CACHE_INFO == TRUE
+ GetF12CacheInfo,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_SYSTEM_PM_TABLE == TRUE
+ GetF12SysPmTable,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_WHEA_INIT == TRUE
+ GetF12WheaInitData,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
+ F12GetPlatformTypeSpecificInfo,
+ #else
+ (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
+ #endif
+ #if IS_NB_PSTATE_ENABLED == TRUE
+ F12IsNbPstateEnabled,
+ #else
+ (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
+ #endif
+ #if (BASE_FAMILY_HT_PCI == TRUE)
+ (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
+ #else
+ (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
+ #endif
+ #if (BASE_FAMILY_HT_PCI == TRUE)
+ (PF_SET_HT_PHY_REGISTER) CommonVoid,
+ #else
+ (PF_SET_HT_PHY_REGISTER) CommonAssert,
+ #endif
+ #if BASE_FAMILY_PCI == TRUE
+ (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
+ #else
+ (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
+ #endif
+ #if USES_REGISTER_TABLES == TRUE
+ (REGISTER_TABLE **) F12LnRegisterTables,
+ #else
+ NULL,
+ #endif
+ #if USES_REGISTER_TABLES == TRUE
+ (TABLE_ENTRY_TYPE_DESCRIPTOR *) F12LnTableEntryTypeDescriptors,
+ #else
+ NULL,
+ #endif
+ #if MODEL_SPECIFIC_HT_PCI == TRUE
+ NULL,
+ #else
+ NULL,
+ #endif
+ NULL,
+ InitCacheDisabled,
+ #if AGESA_ENTRY_INIT_EARLY == TRUE
+ GetCommonEarlyInitOnCoreTable
+ #else
+ (PF_GET_EARLY_INIT_TABLE) CommonVoid
+ #endif
+ };
+
+ #define LN_SOCKETS 1
+ #define LN_MODULES 1
+ #define LN_RECOVERY_SOCKETS 1
+ #define LN_RECOVERY_MODULES 1
+ extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF12LnLogicalIdAndRev;
+ #define OPT_F12_LN_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF12LnLogicalIdAndRev,
+ #ifndef ADVCFG_PLATFORM_SOCKETS
+ #define ADVCFG_PLATFORM_SOCKETS LN_SOCKETS
+ #else
+ #if ADVCFG_PLATFORM_SOCKETS < LN_SOCKETS
+ #undef ADVCFG_PLATFORM_SOCKETS
+ #define ADVCFG_PLATFORM_SOCKETS LN_SOCKETS
+ #endif
+ #endif
+ #ifndef ADVCFG_PLATFORM_MODULES
+ #define ADVCFG_PLATFORM_MODULES LN_MODULES
+ #else
+ #if ADVCFG_PLATFORM_MODULES < LN_MODULES
+ #undef ADVCFG_PLATFORM_MODULES
+ #define ADVCFG_PLATFORM_MODULES LN_MODULES
+ #endif
+ #endif
+
+ #if GET_PATCHES == TRUE
+ #define F12_LN_UCODE_02
+
+ // If a patch is required for recovery mode to function properly, add a
+ // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
+ #if AGESA_ENTRY_INIT_EARLY == TRUE
+ #if OPTION_EARLY_SAMPLES == TRUE
+ extern CONST MICROCODE_PATCHES ROMDATA CpuF12MicrocodePatch03000002;
+ #undef F12_LN_UCODE_02
+ #define F12_LN_UCODE_02 &CpuF12MicrocodePatch03000002,
+ #endif
+ #endif
+
+ CONST MICROCODE_PATCHES ROMDATA *CpuF12LnMicroCodePatchArray[] =
+ {
+ F12_LN_UCODE_02
+ NULL
+ };
+
+ CONST UINT8 ROMDATA CpuF12LnNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF12LnMicroCodePatchArray) / sizeof (CpuF12LnMicroCodePatchArray[0])) - 1);
+ #endif
+
+ #if OPTION_EARLY_SAMPLES == TRUE
+ extern F_F12_ES_NB_PSTATE_INIT F12NbPstateInitEarlySampleHook;
+ extern F_F12_ES_POWER_PLANE_INIT F12PowerPlaneInitEarlySampleHook;
+
+ CONST F12_ES_CORE_SUPPORT ROMDATA F12EarlySampleCoreSupport =
+ {
+ #if AGESA_ENTRY_INIT_EARLY == TRUE
+ F12PowerPlaneInitEarlySampleHook,
+ #else
+ (PF_F12_ES_POWER_PLANE_INIT) CommonAssert,
+ #endif
+ #if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_RECOVERY == TRUE)
+ F12NbPstateInitEarlySampleHook
+ #else
+ (PF_F12_ES_NB_PSTATE_INIT) CommonAssert
+ #endif
+ };
+ #else
+ CONST F12_ES_CORE_SUPPORT ROMDATA F12EarlySampleCoreSupport =
+ {
+ #if AGESA_ENTRY_INIT_EARLY == TRUE
+ (PF_F12_ES_POWER_PLANE_INIT) CommonVoid,
+ #else
+ (PF_F12_ES_POWER_PLANE_INIT) CommonAssert,
+ #endif
+ #if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_RECOVERY == TRUE)
+ (PF_F12_ES_NB_PSTATE_INIT) CommonVoid
+ #else
+ (PF_F12_ES_NB_PSTATE_INIT) CommonAssert
+ #endif
+ };
+ #endif
+
+ #define OPT_F12_LN_CPU {AMD_FAMILY_12_LN, &cpuF12LnServices},
+ #else // OPTION_FAMILY12H_LN == TRUE
+ #define OPT_F12_LN_CPU
+ #define OPT_F12_LN_ID
+ #endif // OPTION_FAMILY12H_LN == TRUE
+#else // defined (OPTION_FAMILY12H_LN)
+ #define OPT_F12_LN_CPU
+ #define OPT_F12_LN_ID
+#endif // defined (OPTION_FAMILY12H_LN)
+
+
+/*
+ * Install unknown family 12h support
+ */
+
+#if USES_REGISTER_TABLES == TRUE
+ CONST REGISTER_TABLE ROMDATA *F12UnknownRegisterTables[] =
+ {
+ #if BASE_FAMILY_PCI == TRUE
+ &F12PciRegisterTable,
+ #endif
+ #if BASE_FAMILY_PCI == TRUE
+ &F12PerCorePciRegisterTable,
+ #endif
+ #if BASE_FAMILY_MSR == TRUE
+ &F12MsrRegisterTable,
+ #endif
+ // the end.
+ NULL
+ };
+#endif
+
+#if USES_REGISTER_TABLES == TRUE
+ CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F12UnknownTableEntryTypeDescriptors[] =
+ {
+ {MsrRegister, SetRegisterForMsrEntry},
+ {PciRegister, SetRegisterForPciEntry},
+ {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
+ {ProfileFixup, (PF_DO_TABLE_ENTRY)CommonVoid},
+ // End
+ {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
+ };
+#endif
+
+CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF12UnknownServices =
+{
+ 0,
+ #if DISABLE_PSTATE == TRUE
+ F12DisablePstate,
+ #else
+ (PF_CPU_DISABLE_PSTATE) CommonAssert,
+ #endif
+ #if TRANSITION_PSTATE == TRUE
+ F12TransitionPstate,
+ #else
+ (PF_CPU_TRANSITION_PSTATE) CommonAssert,
+ #endif
+ #if PROC_IDD_MAX == TRUE
+ F12GetProcIddMax,
+ #else
+ (PF_CPU_GET_IDD_MAX) CommonAssert,
+ #endif
+ #if GET_TSC_RATE == TRUE
+ F12GetTscRate,
+ #else
+ (PF_CPU_GET_TSC_RATE) CommonAssert,
+ #endif
+ #if GET_NB_FREQ == TRUE
+ F12GetCurrentNbFrequency,
+ #else
+ (PF_CPU_GET_NB_FREQ) CommonAssert,
+ #endif
+ #if GET_NB_FREQ == TRUE
+ F12GetNbPstateInfo,
+ #else
+ (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
+ #endif
+ #if IS_NBCOF_INIT_NEEDED == TRUE
+ F12GetNbCofVidUpdate,
+ #else
+ (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
+ #endif
+ #if AP_INITIAL_LAUNCH == TRUE
+ F12LaunchApCore,
+ #else
+ (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
+ #endif
+ #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
+ F12GetNumberOfCoresForBrandstring,
+ #else
+ (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
+ #endif
+ #if GET_AP_MAILBOX_FROM_HW == TRUE
+ F12GetApMailboxFromHardware,
+ #else
+ (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
+ #endif
+ #if SET_AP_CORE_NUMBER == TRUE
+ (PF_CPU_SET_AP_CORE_NUMBER) CommonVoid,
+ #else
+ (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
+ #endif
+ #if GET_AP_CORE_NUMBER == TRUE
+ F12GetApCoreNumber,
+ #else
+ (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
+ #endif
+ #if TRANSFER_AP_CORE_NUMBER == TRUE
+ (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid,
+ #else
+ (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
+ #endif
+ #if ID_POSITION_INITIAL_APICID == TRUE
+ F12CpuAmdCoreIdPositionInInitialApicId,
+ #else
+ (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
+ #endif
+ #if SAVE_FEATURES == TRUE
+ (PF_CPU_SAVE_FEATURES) CommonVoid,
+ #else
+ (PF_CPU_SAVE_FEATURES) CommonAssert,
+ #endif
+ #if WRITE_FEATURES == TRUE
+ (PF_CPU_WRITE_FEATURES) CommonVoid,
+ #else
+ (PF_CPU_WRITE_FEATURES) CommonAssert,
+ #endif
+ #if SET_WARM_RESET_FLAG == TRUE
+ F12SetAgesaWarmResetFlag,
+ #else
+ (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
+ #endif
+ #if GET_WARM_RESET_FLAG == TRUE
+ F12GetAgesaWarmResetFlag,
+ #else
+ (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
+ #endif
+ #if BRAND_STRING1 == TRUE
+ GetF12BrandIdString1,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if BRAND_STRING2 == TRUE
+ GetF12BrandIdString2,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_PATCHES == TRUE
+ GetEmptyArray,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
+ GetEmptyArray,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_CACHE_INFO == TRUE
+ GetF12CacheInfo,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_SYSTEM_PM_TABLE == TRUE
+ GetF12SysPmTable,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_WHEA_INIT == TRUE
+ GetF12WheaInitData,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
+ F12GetPlatformTypeSpecificInfo,
+ #else
+ (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
+ #endif
+ #if IS_NB_PSTATE_ENABLED == TRUE
+ F12IsNbPstateEnabled,
+ #else
+ (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
+ #endif
+ #if (BASE_FAMILY_HT_PCI == TRUE)
+ (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
+ #else
+ (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonAssert,
+ #endif
+ #if (BASE_FAMILY_HT_PCI == TRUE)
+ (PF_SET_HT_PHY_REGISTER) CommonVoid,
+ #else
+ (PF_SET_HT_PHY_REGISTER) CommonAssert,
+ #endif
+ #if BASE_FAMILY_PCI == TRUE
+ (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
+ #else
+ (PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert,
+ #endif
+ #if USES_REGISTER_TABLES == TRUE
+ (REGISTER_TABLE **) F12UnknownRegisterTables,
+ #else
+ NULL,
+ #endif
+ #if USES_REGISTER_TABLES == TRUE
+ (TABLE_ENTRY_TYPE_DESCRIPTOR *) F12UnknownTableEntryTypeDescriptors,
+ #else
+ NULL,
+ #endif
+ #if MODEL_SPECIFIC_HT_PCI == TRUE
+ NULL,
+ #else
+ NULL,
+ #endif
+ NULL,
+ InitCacheDisabled,
+ #if AGESA_ENTRY_INIT_EARLY == TRUE
+ GetCommonEarlyInitOnCoreTable
+ #else
+ (PF_GET_EARLY_INIT_TABLE) CommonVoid
+ #endif
+};
+
+ // Family 12h maximum base address is 40 bits. Limit BLDCFG to 40 bits, if appropriate.
+#if (FAMILY_MMIO_BASE_MASK < 0xFFFFFF0000000000ull)
+ #undef FAMILY_MMIO_BASE_MASK
+ #define FAMILY_MMIO_BASE_MASK (0xFFFFFF0000000000ull)
+#endif
+
+#undef OPT_F12_ID_TABLE
+#define OPT_F12_ID_TABLE {0x12, {AMD_FAMILY_12, AMD_F12_UNKNOWN}, F12LogicalIdTable, (sizeof (F12LogicalIdTable) / sizeof (F12LogicalIdTable[0]))},
+#define OPT_F12_UNKNOWN_CPU {AMD_FAMILY_12, &cpuF12UnknownServices},
+
+#undef OPT_F12_TABLE
+#define OPT_F12_TABLE OPT_F12_LN_CPU OPT_F12_UNKNOWN_CPU
+
+#if OPTION_FS1_SOCKET_SUPPORT == TRUE
+ #define F12_FS1_BRANDSTRING1 NULL,
+ #define F12_FS1_BRANDSTRING2 NULL,
+#else
+ #define F12_FS1_BRANDSTRING1
+ #define F12_FS1_BRANDSTRING2
+#endif
+#if OPTION_FM1_SOCKET_SUPPORT == TRUE
+ #define F12_FM1_BRANDSTRING1 NULL,
+ #define F12_FM1_BRANDSTRING2 NULL,
+#else
+ #define F12_FM1_BRANDSTRING1
+ #define F12_FM1_BRANDSTRING2
+#endif
+#if OPTION_FP1_SOCKET_SUPPORT == TRUE
+ #define F12_FP1_BRANDSTRING1 NULL,
+ #define F12_FP1_BRANDSTRING2 NULL,
+#else
+ #define F12_FP1_BRANDSTRING1
+ #define F12_FP1_BRANDSTRING2
+#endif
+
+#if BRAND_STRING1 == TRUE
+ CONST CPU_BRAND_TABLE ROMDATA *F12BrandIdString1Tables[] =
+ {
+ F12_FS1_BRANDSTRING1
+ F12_FM1_BRANDSTRING1
+ F12_FP1_BRANDSTRING1
+ };
+
+ CONST UINT8 F12BrandIdString1TableCount = (sizeof (F12BrandIdString1Tables) / sizeof (F12BrandIdString1Tables[0]));
+#endif
+
+#if BRAND_STRING2 == TRUE
+ CONST CPU_BRAND_TABLE ROMDATA *F12BrandIdString2Tables[] =
+ {
+ F12_FS1_BRANDSTRING2
+ F12_FM1_BRANDSTRING2
+ F12_FP1_BRANDSTRING2
+ };
+
+ CONST UINT8 F12BrandIdString2TableCount = (sizeof (F12BrandIdString2Tables) / sizeof (F12BrandIdString2Tables[0]));
+#endif
+
+CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY ROMDATA F12LogicalIdTable[] =
+{
+ OPT_F12_LN_ID
+};
+
+#endif // _OPTION_FAMILY_12H_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionFamily14hEarlySample.h b/src/vendorcode/amd/agesa/f14/Include/OptionFamily14hEarlySample.h
new file mode 100644
index 0000000..ef042bd
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Include/OptionFamily14hEarlySample.h
@@ -0,0 +1,170 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Family 14h 'early sample' support
+ *
+ * This file defines the required structures for family 14h pre-production processors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Core
+ * @e \$Revision: 37018 $ @e \$Date: 2010-08-28 05:46:16 +0800 (Sat, 28 Aug 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _OPTION_FAMILY_14H_EARLY_SAMPLE_H_
+#define _OPTION_FAMILY_14H_EARLY_SAMPLE_H_
+
+
+/*---------------------------------------------------------------------------------------
+ * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ * T Y P E D E F S, S T R U C T U R E S, E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+/**
+ * Return the correct early init table pointer.
+ *
+ * @param[in,out] Table The early init table pointer.
+ * @param[in] StdHeader Handle of Header for calling lib functions and services.
+ *
+ */
+typedef VOID F_F14_ES_GET_EARLY_INIT_TABLE (
+ IN OUT CONST VOID **Table,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+/// Reference to a Method.
+typedef F_F14_ES_GET_EARLY_INIT_TABLE *PF_F14_ES_GET_EARLY_INIT_TABLE;
+
+/**
+ * Return the appropriate values of certain NB P-state related registers.
+ *
+ * @param[in,out] FCRxFE00_6000 The value of FCRxFE006000.
+ * @param[in,out] FCRxFE00_6002 The value of FCRxFE006002.
+ * @param[in,out] FCRxFE00_7006 The value of FCRxFE007006.
+ * @param[in,out] FCRxFE00_7009 The value of FCRxFE007009.
+ * @param[in] MainPll The main PLL frequency.
+ * @param[in] StdHeader Handle of Header for calling lib functions and services.
+ *
+ */
+typedef VOID F_F14_ES_NB_PSTATE_INIT (
+ IN OUT VOID *FCRxFE00_6000,
+ IN OUT VOID *FCRxFE00_6002,
+ IN OUT VOID *FCRxFE00_7006,
+ IN OUT VOID *FCRxFE00_7009,
+ IN UINT32 MainPll,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+/// Reference to a Method.
+typedef F_F14_ES_NB_PSTATE_INIT *PF_F14_ES_NB_PSTATE_INIT;
+
+/**
+ * Return the appropriate value of a certain NB P-state related register.
+ *
+ * @param[in,out] FCRxFE00_6000 The value of FCRxFE006000.
+ * @param[in] StdHeader Handle of Header for calling lib functions and services.
+ *
+ */
+typedef VOID F_F14_ES_POWER_PLANE_INIT (
+ IN OUT VOID *FCRxFE00_6000,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+/// Reference to a Method.
+typedef F_F14_ES_POWER_PLANE_INIT *PF_F14_ES_POWER_PLANE_INIT;
+
+/**
+ * Returns whether or not the processor should enable the C6 feature.
+ *
+ * @param[in,out] IsEnabled Whether or not to enable C6
+ * @param[in] StdHeader Handle of Header for calling lib functions and services.
+ *
+ */
+typedef VOID F_F14_ES_IS_C6_SUPPORTED (
+ IN OUT BOOLEAN *IsEnabled,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+/// Reference to a Method.
+typedef F_F14_ES_IS_C6_SUPPORTED *PF_F14_ES_IS_C6_SUPPORTED;
+
+/**
+ * Implements an early sample workaround required for C6
+ *
+ * @param[in] StdHeader Handle of Header for calling lib functions and services.
+ *
+ */
+typedef VOID F_F14_ES_C6_INIT (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+/// Reference to a Method.
+typedef F_F14_ES_C6_INIT *PF_F14_ES_C6_INIT;
+
+
+/// Hook points in the core functionality necessary for
+/// providing support for pre-production CPUs.
+typedef struct {
+ PF_F14_ES_GET_EARLY_INIT_TABLE F14GetEarlyInitTableHook; ///< Early init table pointer override
+ PF_F14_ES_POWER_PLANE_INIT F14PowerPlaneInitHook; ///< Allows for override of a certain processor register value during power plane init
+ PF_F14_ES_NB_PSTATE_INIT F14NbPstateInitHook; ///< Allows for override of certain processor register values for proper NB P-state init
+} F14_ES_CORE_SUPPORT;
+
+/// Hook points in the C6 feature necessary for
+/// providing support for pre-production CPUs.
+typedef struct {
+ PF_F14_ES_IS_C6_SUPPORTED F14IsC6SupportedHook; ///< C6 enablement override
+ PF_F14_ES_C6_INIT F14InitializeC6; ///< Hook for erratum 453 workaround
+} F14_ES_C6_SUPPORT;
+
+
+/*---------------------------------------------------------------------------------------
+ * F U N C T I O N P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+
+
+#endif // _OPTION_FAMILY_14H_EARLY_SAMPLE_H_
diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionFamily14hInstall.h b/src/vendorcode/amd/agesa/f14/Include/OptionFamily14hInstall.h
new file mode 100644
index 0000000..38a287d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Include/OptionFamily14hInstall.h
@@ -0,0 +1,661 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of family 14h support
+ *
+ * This file generates the default tables for family 14h processors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Core
+ * @e \$Revision: 37854 $ @e \$Date: 2010-09-14 06:35:39 +0800 (Tue, 14 Sep 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _OPTION_FAMILY_14H_INSTALL_H_
+#define _OPTION_FAMILY_14H_INSTALL_H_
+
+
+#include "OptionFamily14hEarlySample.h"
+
+/*
+ * Common Family 14h routines
+ */
+extern F_CPU_DISABLE_PSTATE F14DisablePstate;
+extern F_CPU_TRANSITION_PSTATE F14TransitionPstate;
+extern F_CPU_GET_TSC_RATE F14GetTscRate;
+extern F_CPU_GET_NB_FREQ F14GetCurrentNbFrequency;
+extern F_CPU_GET_NB_PSTATE_INFO F14GetNbPstateInfo;
+extern F_CPU_IS_NBCOF_INIT_NEEDED F14GetNbCofVidUpdate;
+extern F_CPU_AP_INITIAL_LAUNCH F14LaunchApCore;
+extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F14GetApMailboxFromHardware;
+extern F_CPU_GET_AP_CORE_NUMBER F14GetApCoreNumber;
+extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F14CpuAmdCoreIdPositionInInitialApicId;
+extern F_CPU_SET_WARM_RESET_FLAG F14SetAgesaWarmResetFlag;
+extern F_CPU_GET_WARM_RESET_FLAG F14GetAgesaWarmResetFlag;
+extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14BrandIdString1;
+extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14BrandIdString2;
+extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14CacheInfo;
+extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14SysPmTable;
+extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14WheaInitData;
+extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetEmptyArray;
+extern F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO F14GetPlatformTypeSpecificInfo;
+extern F_CPU_GET_IDD_MAX F14GetProcIddMax;
+extern CONST REGISTER_TABLE ROMDATA F14PciRegisterTable;
+extern CONST REGISTER_TABLE ROMDATA F14PerCorePciRegisterTable;
+extern CONST REGISTER_TABLE ROMDATA F14MsrRegisterTable;
+extern F_CPU_NUMBER_OF_BRANDSTRING_CORES F14GetNumberOfCoresForBrandstring;
+extern F_GET_EARLY_INIT_TABLE GetF14OnEarlyInitOnCoreTable;
+extern F_IS_NB_PSTATE_ENABLED F14IsNbPstateEnabled;
+#if OPTION_EARLY_SAMPLES == TRUE
+ extern CONST REGISTER_TABLE ROMDATA F14EarlySampleMsrRegisterTable;
+#endif
+
+
+/*
+ * Install family 14h model 0 support
+ */
+#ifdef OPTION_FAMILY14H_ON
+ #if OPTION_FAMILY14H_ON == TRUE
+ extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14OnMicroCodePatchesStruct;
+ extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14OnMicrocodeEquivalenceTable;
+
+ #if USES_REGISTER_TABLES == TRUE
+ CONST REGISTER_TABLE ROMDATA *F14OnRegisterTables[] =
+ {
+ #if BASE_FAMILY_PCI == TRUE
+ &F14PciRegisterTable,
+ #endif
+ #if BASE_FAMILY_PCI == TRUE
+ &F14PerCorePciRegisterTable,
+ #endif
+ #if BASE_FAMILY_MSR == TRUE
+ &F14MsrRegisterTable,
+ #if OPTION_EARLY_SAMPLES == TRUE
+ &F14EarlySampleMsrRegisterTable,
+ #endif
+ #endif
+ // the end.
+ NULL
+ };
+ #endif
+
+ #if USES_REGISTER_TABLES == TRUE
+ CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F14OnTableEntryTypeDescriptors[] =
+ {
+ {MsrRegister, SetRegisterForMsrEntry},
+ {PciRegister, SetRegisterForPciEntry},
+ {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
+ // End
+ {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
+ };
+ #endif
+
+ CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF14OnServices =
+ {
+ 0,
+ #if DISABLE_PSTATE == TRUE
+ F14DisablePstate,
+ #else
+ (PF_CPU_DISABLE_PSTATE) CommonAssert,
+ #endif
+ #if TRANSITION_PSTATE == TRUE
+ F14TransitionPstate,
+ #else
+ (PF_CPU_TRANSITION_PSTATE) CommonAssert,
+ #endif
+ #if PROC_IDD_MAX == TRUE
+ F14GetProcIddMax,
+ #else
+ (PF_CPU_GET_IDD_MAX) CommonAssert,
+ #endif
+ #if GET_TSC_RATE == TRUE
+ F14GetTscRate,
+ #else
+ (PF_CPU_GET_TSC_RATE) CommonAssert,
+ #endif
+ #if GET_NB_FREQ == TRUE
+ F14GetCurrentNbFrequency,
+ #else
+ (PF_CPU_GET_NB_FREQ) CommonAssert,
+ #endif
+ #if GET_NB_FREQ == TRUE
+ F14GetNbPstateInfo,
+ #else
+ (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
+ #endif
+ #if IS_NBCOF_INIT_NEEDED == TRUE
+ F14GetNbCofVidUpdate,
+ #else
+ (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
+ #endif
+ #if AP_INITIAL_LAUNCH == TRUE
+ F14LaunchApCore,
+ #else
+ (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
+ #endif
+ #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
+ F14GetNumberOfCoresForBrandstring,
+ #else
+ (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
+ #endif
+ #if GET_AP_MAILBOX_FROM_HW == TRUE
+ F14GetApMailboxFromHardware,
+ #else
+ (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
+ #endif
+ #if SET_AP_CORE_NUMBER == TRUE
+ (PF_CPU_SET_AP_CORE_NUMBER) CommonVoid,
+ #else
+ (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
+ #endif
+ #if GET_AP_CORE_NUMBER == TRUE
+ F14GetApCoreNumber,
+ #else
+ (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
+ #endif
+ #if TRANSFER_AP_CORE_NUMBER == TRUE
+ (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid,
+ #else
+ (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
+ #endif
+ #if ID_POSITION_INITIAL_APICID == TRUE
+ F14CpuAmdCoreIdPositionInInitialApicId,
+ #else
+ (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
+ #endif
+ #if SAVE_FEATURES == TRUE
+ (PF_CPU_SAVE_FEATURES) CommonVoid,
+ #else
+ (PF_CPU_SAVE_FEATURES) CommonAssert,
+ #endif
+ #if WRITE_FEATURES == TRUE
+ (PF_CPU_WRITE_FEATURES) CommonVoid,
+ #else
+ (PF_CPU_WRITE_FEATURES) CommonAssert,
+ #endif
+ #if SET_WARM_RESET_FLAG == TRUE
+ F14SetAgesaWarmResetFlag,
+ #else
+ (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
+ #endif
+ #if GET_WARM_RESET_FLAG == TRUE
+ F14GetAgesaWarmResetFlag,
+ #else
+ (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
+ #endif
+ #if BRAND_STRING1 == TRUE
+ GetF14BrandIdString1,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if BRAND_STRING2 == TRUE
+ GetF14BrandIdString2,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_PATCHES == TRUE
+ GetF14OnMicroCodePatchesStruct,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
+ GetF14OnMicrocodeEquivalenceTable,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_CACHE_INFO == TRUE
+ GetF14CacheInfo,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_SYSTEM_PM_TABLE == TRUE
+ GetF14SysPmTable,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_WHEA_INIT == TRUE
+ GetF14WheaInitData,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
+ F14GetPlatformTypeSpecificInfo,
+ #else
+ (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
+ #endif
+ #if IS_NB_PSTATE_ENABLED == TRUE
+ F14IsNbPstateEnabled,
+ #else
+ (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
+ #endif
+ #if (BASE_FAMILY_HT_PCI == TRUE)
+ (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
+ #else
+ (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
+ #endif
+ #if (BASE_FAMILY_HT_PCI == TRUE)
+ (PF_SET_HT_PHY_REGISTER) CommonVoid,
+ #else
+ (PF_SET_HT_PHY_REGISTER) CommonAssert,
+ #endif
+ #if BASE_FAMILY_PCI == TRUE
+ (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
+ #else
+ (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
+ #endif
+ #if USES_REGISTER_TABLES == TRUE
+ (REGISTER_TABLE **) F14OnRegisterTables,
+ #else
+ NULL,
+ #endif
+ #if USES_REGISTER_TABLES == TRUE
+ (TABLE_ENTRY_TYPE_DESCRIPTOR *) F14OnTableEntryTypeDescriptors,
+ #else
+ NULL,
+ #endif
+ #if MODEL_SPECIFIC_HT_PCI == TRUE
+ NULL,
+ #else
+ NULL,
+ #endif
+ NULL,
+ InitCacheDisabled,
+ #if AGESA_ENTRY_INIT_EARLY == TRUE
+ GetF14OnEarlyInitOnCoreTable
+ #else
+ (PF_GET_EARLY_INIT_TABLE) CommonVoid
+ #endif
+ };
+
+ #define ON_SOCKETS 1
+ #define ON_MODULES 1
+ #define ON_RECOVERY_SOCKETS 1
+ #define ON_RECOVERY_MODULES 1
+ extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF14OnLogicalIdAndRev;
+ #define OPT_F14_ON_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF14OnLogicalIdAndRev,
+ #ifndef ADVCFG_PLATFORM_SOCKETS
+ #define ADVCFG_PLATFORM_SOCKETS ON_SOCKETS
+ #else
+ #if ADVCFG_PLATFORM_SOCKETS < ON_SOCKETS
+ #undef ADVCFG_PLATFORM_SOCKETS
+ #define ADVCFG_PLATFORM_SOCKETS ON_SOCKETS
+ #endif
+ #endif
+ #ifndef ADVCFG_PLATFORM_MODULES
+ #define ADVCFG_PLATFORM_MODULES ON_MODULES
+ #else
+ #if ADVCFG_PLATFORM_MODULES < ON_MODULES
+ #undef ADVCFG_PLATFORM_MODULES
+ #define ADVCFG_PLATFORM_MODULES ON_MODULES
+ #endif
+ #endif
+
+ #if GET_PATCHES == TRUE
+ #define F14_ON_UCODE_0B
+ #define F14_ON_UCODE_1A
+ #define F14_ON_UCODE_25
+
+ // If a patch is required for recovery mode to function properly, add a
+ // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
+ #if AGESA_ENTRY_INIT_EARLY == TRUE
+ #if OPTION_EARLY_SAMPLES == TRUE
+ extern CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch0500000B;
+ #undef F14_ON_UCODE_0B
+ #define F14_ON_UCODE_0B &CpuF14MicrocodePatch0500000B,
+
+ extern CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch0500001A;
+ #undef F14_ON_UCODE_1A
+ #define F14_ON_UCODE_1A &CpuF14MicrocodePatch0500001A,
+ #endif
+ extern CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch05000025;
+ #undef F14_ON_UCODE_25
+ #define F14_ON_UCODE_25 &CpuF14MicrocodePatch05000025,
+ #endif
+
+ CONST MICROCODE_PATCHES ROMDATA *CpuF14OnMicroCodePatchArray[] =
+ {
+ F14_ON_UCODE_0B
+ F14_ON_UCODE_1A
+ F14_ON_UCODE_25
+ NULL
+ };
+
+ CONST UINT8 ROMDATA CpuF14OnNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF14OnMicroCodePatchArray) / sizeof (CpuF14OnMicroCodePatchArray[0])) - 1);
+ #endif
+
+ #if OPTION_EARLY_SAMPLES == TRUE
+ extern F_F14_ES_GET_EARLY_INIT_TABLE GetF14OnEarlySampleEarlyInitTable;
+ extern F_F14_ES_NB_PSTATE_INIT F14NbPstateInitEarlySampleHook;
+ extern F_F14_ES_POWER_PLANE_INIT F14PowerPlaneInitEarlySampleHook;
+
+ CONST F14_ES_CORE_SUPPORT ROMDATA F14EarlySampleCoreSupport =
+ {
+ #if AGESA_ENTRY_INIT_EARLY == TRUE
+ GetF14OnEarlySampleEarlyInitTable,
+ F14PowerPlaneInitEarlySampleHook,
+ #else
+ (PF_F14_ES_GET_EARLY_INIT_TABLE) CommonAssert,
+ (PF_F14_ES_POWER_PLANE_INIT) CommonAssert,
+ #endif
+ #if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_RECOVERY == TRUE)
+ F14NbPstateInitEarlySampleHook
+ #else
+ (PF_F14_ES_NB_PSTATE_INIT) CommonAssert
+ #endif
+ };
+ #else
+ CONST F14_ES_CORE_SUPPORT ROMDATA F14EarlySampleCoreSupport =
+ {
+ #if AGESA_ENTRY_INIT_EARLY == TRUE
+ (PF_F14_ES_GET_EARLY_INIT_TABLE) CommonVoid,
+ (PF_F14_ES_POWER_PLANE_INIT) CommonVoid,
+ #else
+ (PF_F14_ES_GET_EARLY_INIT_TABLE) CommonAssert,
+ (PF_F14_ES_POWER_PLANE_INIT) CommonAssert,
+ #endif
+ #if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_RECOVERY == TRUE)
+ (PF_F14_ES_NB_PSTATE_INIT) CommonVoid
+ #else
+ (PF_F14_ES_NB_PSTATE_INIT) CommonAssert
+ #endif
+ };
+ #endif
+
+ #define OPT_F14_ON_CPU {AMD_FAMILY_14_ON, &cpuF14OnServices},
+ #else // OPTION_FAMILY14H_ON == TRUE
+ #define OPT_F14_ON_CPU
+ #define OPT_F14_ON_ID
+ #endif // OPTION_FAMILY14H_ON == TRUE
+#else // defined (OPTION_FAMILY14H_ON)
+ #define OPT_F14_ON_CPU
+ #define OPT_F14_ON_ID
+#endif // defined (OPTION_FAMILY14H_ON)
+
+/*
+ * Install unknown family 14h support
+ */
+
+#if USES_REGISTER_TABLES == TRUE
+ CONST REGISTER_TABLE ROMDATA *F14UnknownRegisterTables[] =
+ {
+ #if BASE_FAMILY_PCI == TRUE
+ &F14PciRegisterTable,
+ #endif
+ #if BASE_FAMILY_PCI == TRUE
+ &F14PerCorePciRegisterTable,
+ #endif
+ #if BASE_FAMILY_MSR == TRUE
+ &F14MsrRegisterTable,
+ #endif
+ // the end.
+ NULL
+ };
+#endif
+
+#if USES_REGISTER_TABLES == TRUE
+ CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F14UnknownTableEntryTypeDescriptors[] =
+ {
+ {MsrRegister, SetRegisterForMsrEntry},
+ {PciRegister, SetRegisterForPciEntry},
+ {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
+ // End
+ {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
+ };
+#endif
+
+CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF14UnknownServices =
+{
+ 0,
+ #if DISABLE_PSTATE == TRUE
+ F14DisablePstate,
+ #else
+ (PF_CPU_DISABLE_PSTATE) CommonAssert,
+ #endif
+ #if TRANSITION_PSTATE == TRUE
+ F14TransitionPstate,
+ #else
+ (PF_CPU_TRANSITION_PSTATE) CommonAssert,
+ #endif
+ #if PROC_IDD_MAX == TRUE
+ (PF_CPU_GET_IDD_MAX) F14GetProcIddMax,
+ #else
+ (PF_CPU_GET_IDD_MAX) CommonAssert,
+ #endif
+ #if GET_TSC_RATE == TRUE
+ F14GetTscRate,
+ #else
+ (PF_CPU_GET_TSC_RATE) CommonAssert,
+ #endif
+ #if GET_NB_FREQ == TRUE
+ F14GetCurrentNbFrequency,
+ #else
+ (PF_CPU_GET_NB_FREQ) CommonAssert,
+ #endif
+ #if GET_NB_FREQ == TRUE
+ F14GetNbPstateInfo,
+ #else
+ (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
+ #endif
+ #if IS_NBCOF_INIT_NEEDED == TRUE
+ F14GetNbCofVidUpdate,
+ #else
+ (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
+ #endif
+ #if AP_INITIAL_LAUNCH == TRUE
+ F14LaunchApCore,
+ #else
+ (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
+ #endif
+ #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
+ F14GetNumberOfCoresForBrandstring,
+ #else
+ (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
+ #endif
+ #if GET_AP_MAILBOX_FROM_HW == TRUE
+ F14GetApMailboxFromHardware,
+ #else
+ (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
+ #endif
+ #if SET_AP_CORE_NUMBER == TRUE
+ (PF_CPU_SET_AP_CORE_NUMBER) CommonVoid,
+ #else
+ (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
+ #endif
+ #if GET_AP_CORE_NUMBER == TRUE
+ F14GetApCoreNumber,
+ #else
+ (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
+ #endif
+ #if TRANSFER_AP_CORE_NUMBER == TRUE
+ (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid,
+ #else
+ (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
+ #endif
+ #if ID_POSITION_INITIAL_APICID == TRUE
+ F14CpuAmdCoreIdPositionInInitialApicId,
+ #else
+ (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
+ #endif
+ #if SAVE_FEATURES == TRUE
+ (PF_CPU_SAVE_FEATURES) CommonVoid,
+ #else
+ (PF_CPU_SAVE_FEATURES) CommonAssert,
+ #endif
+ #if WRITE_FEATURES == TRUE
+ (PF_CPU_WRITE_FEATURES) CommonVoid,
+ #else
+ (PF_CPU_WRITE_FEATURES) CommonAssert,
+ #endif
+ #if SET_WARM_RESET_FLAG == TRUE
+ F14SetAgesaWarmResetFlag,
+ #else
+ (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
+ #endif
+ #if GET_WARM_RESET_FLAG == TRUE
+ F14GetAgesaWarmResetFlag,
+ #else
+ (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
+ #endif
+ #if BRAND_STRING1 == TRUE
+ GetF14BrandIdString1,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if BRAND_STRING2 == TRUE
+ GetF14BrandIdString2,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_PATCHES == TRUE
+ GetEmptyArray,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
+ GetEmptyArray,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_CACHE_INFO == TRUE
+ GetF14CacheInfo,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_SYSTEM_PM_TABLE == TRUE
+ GetF14SysPmTable,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_WHEA_INIT == TRUE
+ GetF14WheaInitData,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
+ F14GetPlatformTypeSpecificInfo,
+ #else
+ (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
+ #endif
+ #if IS_NB_PSTATE_ENABLED == TRUE
+ F14IsNbPstateEnabled,
+ #else
+ (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
+ #endif
+ #if (BASE_FAMILY_HT_PCI == TRUE)
+ (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
+ #else
+ (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonVoid,
+ #endif
+ #if (BASE_FAMILY_HT_PCI == TRUE)
+ (PF_SET_HT_PHY_REGISTER) CommonVoid,
+ #else
+ (PF_SET_HT_PHY_REGISTER) CommonVoid,
+ #endif
+ #if BASE_FAMILY_PCI == TRUE
+ (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
+ #else
+ (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
+ #endif
+ #if USES_REGISTER_TABLES == TRUE
+ (REGISTER_TABLE **) F14UnknownRegisterTables,
+ #else
+ NULL,
+ #endif
+ #if USES_REGISTER_TABLES == TRUE
+ (TABLE_ENTRY_TYPE_DESCRIPTOR *) F14UnknownTableEntryTypeDescriptors,
+ #else
+ NULL,
+ #endif
+ #if MODEL_SPECIFIC_HT_PCI == TRUE
+ NULL,
+ #else
+ NULL,
+ #endif
+ NULL,
+ InitCacheDisabled,
+ #if AGESA_ENTRY_INIT_EARLY == TRUE
+ GetF14OnEarlyInitOnCoreTable
+ #else
+ (PF_GET_EARLY_INIT_TABLE) CommonVoid
+ #endif
+};
+
+ // Family 14h maximum base address is 40 bits. Limit BLDCFG to 40 bits, if appropriate.
+#if (FAMILY_MMIO_BASE_MASK < 0xFFFFFF0000000000ull)
+ #undef FAMILY_MMIO_BASE_MASK
+ #define FAMILY_MMIO_BASE_MASK (0xFFFFFF0000000000ull)
+#endif
+
+#undef OPT_F14_ID_TABLE
+#define OPT_F14_ID_TABLE {0x14, {AMD_FAMILY_14, AMD_F14_UNKNOWN}, F14LogicalIdTable, (sizeof (F14LogicalIdTable) / sizeof (F14LogicalIdTable[0]))},
+#define OPT_F14_UNKNOWN_CPU {AMD_FAMILY_14, &cpuF14UnknownServices},
+
+#undef OPT_F14_TABLE
+#define OPT_F14_TABLE OPT_F14_ON_CPU OPT_F14_UNKNOWN_CPU
+
+#if OPTION_FT1_SOCKET_SUPPORT == TRUE
+ extern CONST CPU_BRAND_TABLE ROMDATA F14OnBrandIdString1ArrayFt1;
+ extern CONST CPU_BRAND_TABLE ROMDATA F14OnBrandIdString2ArrayFt1;
+ #define F14_FT1_BRANDSTRING1 &F14OnBrandIdString1ArrayFt1,
+ #define F14_FT1_BRANDSTRING2 &F14OnBrandIdString2ArrayFt1,
+#else
+ #define F14_FT1_BRANDSTRING1
+ #define F14_FT1_BRANDSTRING2
+#endif
+
+#if BRAND_STRING1 == TRUE
+ CONST CPU_BRAND_TABLE ROMDATA *F14BrandIdString1Tables[] =
+ {
+ F14_FT1_BRANDSTRING1
+ };
+
+ CONST UINT8 F14BrandIdString1TableCount = (sizeof (F14BrandIdString1Tables) / sizeof (F14BrandIdString1Tables[0]));
+#endif
+
+#if BRAND_STRING2 == TRUE
+ CONST CPU_BRAND_TABLE ROMDATA *F14BrandIdString2Tables[] =
+ {
+ F14_FT1_BRANDSTRING2
+ };
+
+ CONST UINT8 F14BrandIdString2TableCount = (sizeof (F14BrandIdString2Tables) / sizeof (F14BrandIdString2Tables[0]));
+#endif
+
+CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY ROMDATA F14LogicalIdTable[] =
+{
+ OPT_F14_ON_ID
+};
+
+#endif // _OPTION_FAMILY_14H_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionFamily15hInstall.h b/src/vendorcode/amd/agesa/f14/Include/OptionFamily15hInstall.h
new file mode 100644
index 0000000..b05bfe3
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Include/OptionFamily15hInstall.h
@@ -0,0 +1,717 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of family 15h support
+ *
+ * This file generates the defaults tables for family 15h processors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Core
+ * @e \$Revision: 37150 $ @e \$Date: 2010-08-31 23:53:37 +0800 (Tue, 31 Aug 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _OPTION_FAMILY_15H_INSTALL_H_
+#define _OPTION_FAMILY_15H_INSTALL_H_
+
+/*
+ * Pull in family specific services based on entry point
+ */
+
+/*
+ * Common Family 15h routines
+ */
+extern F_GET_EARLY_INIT_TABLE GetF15EarlyInitOnCoreTable;
+extern F_IS_NB_PSTATE_ENABLED F15IsNbPstateEnabled;
+
+/*
+ * Install family 15h model 0 support
+ */
+#ifdef OPTION_FAMILY15H_OR
+ #if OPTION_FAMILY15H_OR == TRUE
+ extern F_CPU_GET_IDD_MAX F15GetProcIddMax;
+ extern F_CPU_GET_NB_PSTATE_INFO F15GetNbPstateInfo;
+ extern F_CPU_IS_NBCOF_INIT_NEEDED F15CommonGetNbCofVidUpdate;
+ extern F_CPU_DISABLE_PSTATE F15DisablePstate;
+ extern F_CPU_TRANSITION_PSTATE F15TransitionPstate;
+ extern F_CPU_GET_TSC_RATE F15GetTscRate;
+ extern F_CPU_GET_NB_FREQ F15GetCurrentNbFrequency;
+ extern F_CPU_AP_INITIAL_LAUNCH F15LaunchApCore;
+ extern F_CPU_NUMBER_OF_BRANDSTRING_CORES F15CommonGetNumberOfCoresForBrandstring;
+ extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F15GetApMailboxFromHardware;
+ extern F_CPU_SET_AP_CORE_NUMBER F15SetApCoreNumber;
+ extern F_CPU_GET_AP_CORE_NUMBER F15GetApCoreNumber;
+ extern F_CPU_TRANSFER_AP_CORE_NUMBER F15TransferApCoreNumber;
+ extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F15CpuAmdCoreIdPositionInInitialApicId;
+ extern F_CPU_SAVE_FEATURES F15SaveFeatures;
+ extern F_CPU_WRITE_FEATURES F15WriteFeatures;
+ extern F_CPU_SET_WARM_RESET_FLAG F15SetAgesaWarmResetFlag;
+ extern F_CPU_GET_WARM_RESET_FLAG F15GetAgesaWarmResetFlag;
+ extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15CacheInfo;
+ extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15SysPmTable;
+ extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15WheaInitData;
+ extern F_CPU_SET_CFOH_REG SetF15CacheFlushOnHaltRegister;
+ extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetEmptyArray;
+ extern F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO F15GetPlatformTypeSpecificInfo;
+ extern F_NEXT_LINK_HAS_HTFPY_FEATS F15NextLinkHasHtPhyFeats;
+ extern F_SET_HT_PHY_REGISTER F15SetHtPhyRegister;
+ extern F_GET_NEXT_HT_LINK_FEATURES F15GetNextHtLinkFeatures;
+ extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15OrMicroCodePatchesStruct;
+ extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15OrMicrocodeEquivalenceTable;
+ extern CONST REGISTER_TABLE ROMDATA F15OrPciRegisterTable;
+ extern CONST REGISTER_TABLE ROMDATA F15OrMsrRegisterTable;
+ extern CONST REGISTER_TABLE ROMDATA F15OrSharedMsrRegisterTable;
+ extern CONST REGISTER_TABLE ROMDATA F15OrHtPhyRegisterTable;
+ extern CONST REGISTER_TABLE ROMDATA F15PciRegisterTable;
+ extern CONST REGISTER_TABLE ROMDATA F15MsrRegisterTable;
+ extern CONST REGISTER_TABLE ROMDATA F15HtPhyRegisterTable;
+ extern CONST REGISTER_TABLE ROMDATA F15MultiLinkPciRegisterTable;
+ extern CONST REGISTER_TABLE ROMDATA F15SingleLinkPciRegisterTable;
+ extern CONST REGISTER_TABLE ROMDATA F15WorkaroundsTable;
+ extern CONST PACKAGE_HTLINK_MAP_ITEM ROMDATA HtFam15PackageLinkMap[];
+
+ /**
+ * Core Pair and core pair primary determination table.
+ *
+ * The two fields from the core pair hardware register can be used to determine whether
+ * even number cores are primary or all cores are primary. It can be extended if it is
+ * decided to have other configs as well. The other logically possible value sets are BitMapMapping,
+ * but they are currently not supported by the processor.
+ */
+ CONST CORE_PAIR_MAP ROMDATA HtFam15CorePairMapping[] =
+ {
+ {1, 1, EvenCoresMapping}, ///< 1 Compute Unit with 2 cores
+ {3, 3, EvenCoresMapping}, ///< 2 Compute Units both with 2 Cores
+ {7, 7, EvenCoresMapping}, ///< 3 Compute Units all with 2 Cores
+ {0xF, 0xF, EvenCoresMapping}, ///< 4 Compute Units all with 2 Cores
+ {1, 0, AllCoresMapping}, ///< 1 Compute Unit with 1 core
+ {3, 0, AllCoresMapping}, ///< 2 Compute Units both with 1 Core
+ {7, 0, AllCoresMapping}, ///< 3 Compute Units all with 1 Core
+ {0xF, 0, AllCoresMapping}, ///< 4 Compute Units all with 1 Core
+ {HT_LIST_TERMINAL, HT_LIST_TERMINAL, MaxComputeUnitMapping} ///< End
+ };
+
+
+ #if USES_REGISTER_TABLES == TRUE
+ CONST REGISTER_TABLE ROMDATA *F15OrRegisterTables[] =
+ {
+ #if BASE_FAMILY_PCI == TRUE
+ &F15PciRegisterTable,
+ #endif
+ #if MODEL_SPECIFIC_PCI == TRUE
+ &F15MultiLinkPciRegisterTable,
+ #endif
+ #if MODEL_SPECIFIC_PCI == TRUE
+ &F15OrPciRegisterTable,
+ #endif
+ #if BASE_FAMILY_MSR == TRUE
+ &F15MsrRegisterTable,
+ #endif
+ #if MODEL_SPECIFIC_MSR == TRUE
+ &F15OrMsrRegisterTable,
+ #endif
+ #if MODEL_SPECIFIC_MSR == TRUE
+ &F15OrSharedMsrRegisterTable,
+ #endif
+ #if MODEL_SPECIFIC_HT_PCI == TRUE
+ &F15HtPhyRegisterTable,
+ #endif
+ #if MODEL_SPECIFIC_HT_PCI == TRUE
+ &F15OrHtPhyRegisterTable,
+ #endif
+ #if BASE_FAMILY_WORKAROUNDS == TRUE
+ &F15WorkaroundsTable,
+ #endif
+ // the end.
+ NULL
+ };
+ #endif
+
+ #if USES_REGISTER_TABLES == TRUE
+ CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F15OrTableEntryTypeDescriptors[] =
+ {
+ {MsrRegister, SetRegisterForMsrEntry},
+ {PciRegister, SetRegisterForPciEntry},
+ {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
+ {HtPhyRegister, SetRegisterForHtPhyEntry},
+ {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
+ {DeemphasisRegister, SetRegisterForDeemphasisEntry},
+ {HtPhyFreqRegister, SetRegisterForHtPhyFreqEntry},
+ {ProfileFixup, SetRegisterForPerformanceProfileEntry},
+ {HtHostPciRegister, SetRegisterForHtHostEntry},
+ {HtHostPerfPciRegister, SetRegisterForHtHostPerfEntry},
+ {HtTokenPciRegister, SetRegisterForHtLinkTokenEntry},
+ {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
+ {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
+ {CompUnitCountsPciRegister, SetRegisterForComputeUnitCountsEntry},
+ {TokenPciRegister, SetRegisterForTokenPciEntry},
+ {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
+ {HtLinkPciRegister, SetRegisterForHtLinkPciEntry},
+ // End
+ {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
+ };
+ #endif
+
+ CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF15OrServices =
+ {
+ 0,
+ #if DISABLE_PSTATE == TRUE
+ F15DisablePstate,
+ #else
+ (PF_CPU_DISABLE_PSTATE) CommonAssert,
+ #endif
+ #if TRANSITION_PSTATE == TRUE
+ F15TransitionPstate,
+ #else
+ (PF_CPU_TRANSITION_PSTATE) CommonAssert,
+ #endif
+ #if PROC_IDD_MAX == TRUE
+ F15GetProcIddMax,
+ #else
+ (PF_CPU_GET_IDD_MAX) CommonAssert,
+ #endif
+ #if GET_TSC_RATE == TRUE
+ F15GetTscRate,
+ #else
+ (PF_CPU_GET_TSC_RATE) CommonAssert,
+ #endif
+ #if GET_NB_FREQ == TRUE
+ F15GetCurrentNbFrequency,
+ #else
+ (PF_CPU_GET_NB_FREQ) CommonAssert,
+ #endif
+ #if GET_NB_FREQ == TRUE
+ F15GetNbPstateInfo,
+ #else
+ (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
+ #endif
+ #if IS_NBCOF_INIT_NEEDED == TRUE
+ F15CommonGetNbCofVidUpdate,
+ #else
+ (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
+ #endif
+ #if AP_INITIAL_LAUNCH == TRUE
+ F15LaunchApCore,
+ #else
+ (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
+ #endif
+ #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
+ F15CommonGetNumberOfCoresForBrandstring,
+ #else
+ (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
+ #endif
+ #if GET_AP_MAILBOX_FROM_HW == TRUE
+ F15GetApMailboxFromHardware,
+ #else
+ (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
+ #endif
+ #if SET_AP_CORE_NUMBER == TRUE
+ F15SetApCoreNumber,
+ #else
+ (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
+ #endif
+ #if GET_AP_CORE_NUMBER == TRUE
+ F15GetApCoreNumber,
+ #else
+ (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
+ #endif
+ #if TRANSFER_AP_CORE_NUMBER == TRUE
+ F15TransferApCoreNumber,
+ #else
+ (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
+ #endif
+ #if ID_POSITION_INITIAL_APICID == TRUE
+ F15CpuAmdCoreIdPositionInInitialApicId,
+ #else
+ (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
+ #endif
+ #if SAVE_FEATURES == TRUE
+ // F15SaveFeatures,
+ (PF_CPU_SAVE_FEATURES) CommonVoid,
+ #else
+ (PF_CPU_SAVE_FEATURES) CommonAssert,
+ #endif
+ #if WRITE_FEATURES == TRUE
+ // F15WriteFeatures,
+ (PF_CPU_WRITE_FEATURES) CommonVoid,
+ #else
+ (PF_CPU_WRITE_FEATURES) CommonAssert,
+ #endif
+ #if SET_WARM_RESET_FLAG == TRUE
+ F15SetAgesaWarmResetFlag,
+ #else
+ (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
+ #endif
+ #if GET_WARM_RESET_FLAG == TRUE
+ F15GetAgesaWarmResetFlag,
+ #else
+ (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
+ #endif
+ #if BRAND_STRING1 == TRUE
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if BRAND_STRING2 == TRUE
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_PATCHES == TRUE
+ GetF15OrMicroCodePatchesStruct,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
+ GetF15OrMicrocodeEquivalenceTable,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_CACHE_INFO == TRUE
+ GetF15CacheInfo,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_SYSTEM_PM_TABLE == TRUE
+ GetF15SysPmTable,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_WHEA_INIT == TRUE
+ GetF15WheaInitData,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
+ F15GetPlatformTypeSpecificInfo,
+ #else
+ (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
+ #endif
+ #if IS_NB_PSTATE_ENABLED == TRUE
+ F15IsNbPstateEnabled,
+ #else
+ (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
+ #endif
+ #if (BASE_FAMILY_HT_PCI == TRUE)
+ F15NextLinkHasHtPhyFeats,
+ #else
+ (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
+ #endif
+ #if (BASE_FAMILY_HT_PCI == TRUE)
+ F15SetHtPhyRegister,
+ #else
+ (PF_SET_HT_PHY_REGISTER) CommonAssert,
+ #endif
+ #if BASE_FAMILY_PCI == TRUE
+ F15GetNextHtLinkFeatures,
+ #else
+ (PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert,
+ #endif
+ #if USES_REGISTER_TABLES == TRUE
+ (REGISTER_TABLE **) F15OrRegisterTables,
+ #else
+ NULL,
+ #endif
+ #if USES_REGISTER_TABLES == TRUE
+ (TABLE_ENTRY_TYPE_DESCRIPTOR *) F15OrTableEntryTypeDescriptors,
+ #else
+ NULL,
+ #endif
+ #if MODEL_SPECIFIC_HT_PCI == TRUE
+ (PACKAGE_HTLINK_MAP) &HtFam15PackageLinkMap,
+ #else
+ NULL,
+ #endif
+ (CORE_PAIR_MAP *) &HtFam15CorePairMapping,
+ InitCacheEnabled,
+ #if AGESA_ENTRY_INIT_EARLY == TRUE
+ GetF15EarlyInitOnCoreTable
+ #else
+ (PF_GET_EARLY_INIT_TABLE) CommonVoid
+ #endif
+ };
+
+ #define OR_SOCKETS 8
+ #define OR_MODULES 2
+ #define OR_RECOVERY_SOCKETS 1
+ #define OR_RECOVERY_MODULES 1
+ extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF15OrLogicalIdAndRev;
+ #define OPT_F15_OR_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF15OrLogicalIdAndRev,
+ #ifndef ADVCFG_PLATFORM_SOCKETS
+ #define ADVCFG_PLATFORM_SOCKETS OR_SOCKETS
+ #else
+ #if ADVCFG_PLATFORM_SOCKETS < OR_SOCKETS
+ #undef ADVCFG_PLATFORM_SOCKETS
+ #define ADVCFG_PLATFORM_SOCKETS OR_SOCKETS
+ #endif
+ #endif
+ #ifndef ADVCFG_PLATFORM_MODULES
+ #define ADVCFG_PLATFORM_MODULES OR_MODULES
+ #else
+ #if ADVCFG_PLATFORM_MODULES < OR_MODULES
+ #undef ADVCFG_PLATFORM_MODULES
+ #define ADVCFG_PLATFORM_MODULES OR_MODULES
+ #endif
+ #endif
+
+ #if GET_PATCHES == TRUE
+ #define F15_OR_UCODE_09
+
+ #if AGESA_ENTRY_INIT_EARLY == TRUE
+ #if OPTION_EARLY_SAMPLES == TRUE
+ extern CONST MICROCODE_PATCHES_4K ROMDATA CpuF15OrMicrocodePatch06000009;
+ #undef F15_OR_UCODE_09
+ #define F15_OR_UCODE_09 &CpuF15OrMicrocodePatch06000009,
+ #endif
+ #endif
+
+ CONST MICROCODE_PATCHES_4K ROMDATA *CpuF15OrMicroCodePatchArray[] =
+ {
+ F15_OR_UCODE_09
+ NULL
+ };
+
+ CONST UINT8 ROMDATA CpuF15OrNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF15OrMicroCodePatchArray) / sizeof (CpuF15OrMicroCodePatchArray[0])) - 1);
+ #endif
+
+ #define OPT_F15_OR_CPU {AMD_FAMILY_15_OR, &cpuF15OrServices},
+
+ #else // OPTION_FAMILY15H_OR == TRUE
+ #define OPT_F15_OR_CPU
+ #define OPT_F15_OR_ID
+ #endif // OPTION_FAMILY15H_OR == TRUE
+#else // defined (OPTION_FAMILY15H_OR)
+ #define OPT_F15_OR_CPU
+ #define OPT_F15_OR_ID
+#endif // defined (OPTION_FAMILY15H_OR)
+
+/*
+ * Install unknown family 15h support
+ */
+
+
+#if USES_REGISTER_TABLES == TRUE
+ CONST REGISTER_TABLE ROMDATA *F15UnknownRegisterTables[] =
+ {
+ #if BASE_FAMILY_PCI == TRUE
+ &F15PciRegisterTable,
+ #endif
+ #if BASE_FAMILY_MSR == TRUE
+ &F15MsrRegisterTable,
+ #endif
+ #if BASE_FAMILY_HT_PCI == TRUE
+ &F15HtPhyRegisterTable,
+ #endif
+ #if OPTION_MULTISOCKET == TRUE
+ #if MODEL_SPECIFIC_PCI == TRUE
+ &F15MultiLinkPciRegisterTable,
+ #endif
+ #endif
+ #if OPTION_MULTISOCKET == FALSE
+ #if MODEL_SPECIFIC_PCI == TRUE
+ &F15SingleLinkPciRegisterTable,
+ #endif
+ #endif
+ #if BASE_FAMILY_WORKAROUNDS == TRUE
+ &F15WorkaroundsTable,
+ #endif
+ // the end.
+ NULL
+ };
+#endif
+
+#if USES_REGISTER_TABLES == TRUE
+ CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F15UnknownTableEntryTypeDescriptors[] =
+ {
+ {MsrRegister, SetRegisterForMsrEntry},
+ {PciRegister, SetRegisterForPciEntry},
+ {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
+ {HtPhyRegister, SetRegisterForHtPhyEntry},
+ {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
+ {DeemphasisRegister, SetRegisterForDeemphasisEntry},
+ {ProfileFixup, SetRegisterForPerformanceProfileEntry},
+ {HtHostPciRegister, SetRegisterForHtHostEntry},
+ {HtHostPerfPciRegister, SetRegisterForHtHostPerfEntry},
+ {HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid},
+ {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
+ {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
+ {CompUnitCountsPciRegister, SetRegisterForComputeUnitCountsEntry},
+ {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
+ // End
+ {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
+ };
+#endif
+
+
+CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF15UnknownServices =
+{
+ 0,
+ #if DISABLE_PSTATE == TRUE
+ F15DisablePstate,
+ #else
+ (PF_CPU_DISABLE_PSTATE) CommonAssert,
+ #endif
+ #if TRANSITION_PSTATE == TRUE
+ F15TransitionPstate,
+ #else
+ (PF_CPU_TRANSITION_PSTATE) CommonAssert,
+ #endif
+ #if PROC_IDD_MAX == TRUE
+ (PF_CPU_GET_IDD_MAX) CommonReturnFalse,
+ #else
+ (PF_CPU_GET_IDD_MAX) CommonAssert,
+ #endif
+ #if GET_TSC_RATE == TRUE
+ F15GetTscRate,
+ #else
+ (PF_CPU_GET_TSC_RATE) CommonAssert,
+ #endif
+ #if GET_NB_FREQ == TRUE
+ F15GetCurrentNbFrequency,
+ #else
+ (PF_CPU_GET_NB_FREQ) CommonAssert,
+ #endif
+ #if GET_NB_FREQ == TRUE
+ F15GetNbPstateInfo,
+ #else
+ (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
+ #endif
+ #if IS_NBCOF_INIT_NEEDED == TRUE
+ (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonReturnFalse,
+ #else
+ (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
+ #endif
+ #if AP_INITIAL_LAUNCH == TRUE
+ F15LaunchApCore,
+ #else
+ (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
+ #endif
+ #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
+ (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonVoid,
+ #else
+ (PF_CPU_NUMBER_OF_BRANDSTRING_CORES) CommonAssert,
+ #endif
+ #if GET_AP_MAILBOX_FROM_HW == TRUE
+ F15GetApMailboxFromHardware,
+ #else
+ (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
+ #endif
+ #if SET_AP_CORE_NUMBER == TRUE
+ F15SetApCoreNumber,
+ #else
+ (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
+ #endif
+ #if GET_AP_CORE_NUMBER == TRUE
+ F15GetApCoreNumber,
+ #else
+ (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
+ #endif
+ #if TRANSFER_AP_CORE_NUMBER == TRUE
+ F15TransferApCoreNumber,
+ #else
+ (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
+ #endif
+ #if ID_POSITION_INITIAL_APICID == TRUE
+ F15CpuAmdCoreIdPositionInInitialApicId,
+ #else
+ (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
+ #endif
+ #if SAVE_FEATURES == TRUE
+ // F15SaveFeatures,
+ (PF_CPU_SAVE_FEATURES) CommonVoid,
+ #else
+ (PF_CPU_SAVE_FEATURES) CommonAssert,
+ #endif
+ #if WRITE_FEATURES == TRUE
+ // F15WriteFeatures,
+ (PF_CPU_WRITE_FEATURES) CommonVoid,
+ #else
+ (PF_CPU_WRITE_FEATURES) CommonAssert,
+ #endif
+ #if SET_WARM_RESET_FLAG == TRUE
+ F15SetAgesaWarmResetFlag,
+ #else
+ (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
+ #endif
+ #if GET_WARM_RESET_FLAG == TRUE
+ F15GetAgesaWarmResetFlag,
+ #else
+ (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
+ #endif
+ #if BRAND_STRING1 == TRUE
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if BRAND_STRING2 == TRUE
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_PATCHES == TRUE
+ GetEmptyArray,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
+ GetEmptyArray,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_CACHE_INFO == TRUE
+ GetF15CacheInfo,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_SYSTEM_PM_TABLE == TRUE
+ GetF15SysPmTable,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_WHEA_INIT == TRUE
+ GetF15WheaInitData,
+ #else
+ (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+ #endif
+ #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
+ F15GetPlatformTypeSpecificInfo,
+ #else
+ (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
+ #endif
+ #if IS_NB_PSTATE_ENABLED == TRUE
+ F15IsNbPstateEnabled,
+ #else
+ (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
+ #endif
+ #if (BASE_FAMILY_HT_PCI == TRUE)
+ F15NextLinkHasHtPhyFeats,
+ #else
+ (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
+ #endif
+ #if (BASE_FAMILY_HT_PCI == TRUE)
+ F15SetHtPhyRegister,
+ #else
+ (PF_SET_HT_PHY_REGISTER) CommonVoid,
+ #endif
+ #if BASE_FAMILY_PCI == TRUE
+ F15GetNextHtLinkFeatures,
+ #else
+ (PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert,
+ #endif
+ #if USES_REGISTER_TABLES == TRUE
+ (REGISTER_TABLE **) F15UnknownRegisterTables,
+ #else
+ NULL,
+ #endif
+ #if USES_REGISTER_TABLES == TRUE
+ (TABLE_ENTRY_TYPE_DESCRIPTOR *) F15UnknownTableEntryTypeDescriptors,
+ #else
+ NULL,
+ #endif
+ NULL,
+ NULL,
+ InitCacheEnabled,
+ #if AGESA_ENTRY_INIT_EARLY == TRUE
+ GetF15EarlyInitOnCoreTable
+ #else
+ (PF_GET_EARLY_INIT_TABLE) CommonVoid
+ #endif
+};
+
+// Family 15h maximum base address is 48 bits. Limit BLDCFG to 48 bits, if appropriate.
+#if (FAMILY_MMIO_BASE_MASK < 0xFFFF000000000000ull)
+ #undef FAMILY_MMIO_BASE_MASK
+ #define FAMILY_MMIO_BASE_MASK (0xFFFF000000000000ull)
+#endif
+
+
+#undef OPT_F15_ID_TABLE
+#define OPT_F15_ID_TABLE {0x15, {AMD_FAMILY_15, AMD_F15_UNKNOWN}, F15LogicalIdTable, (sizeof (F15LogicalIdTable) / sizeof (F15LogicalIdTable[0]))},
+#define OPT_F15_UNKNOWN_CPU {AMD_FAMILY_15, &cpuF15UnknownServices},
+
+#undef OPT_F15_TABLE
+#define OPT_F15_TABLE OPT_F15_OR_CPU OPT_F15_UNKNOWN_CPU
+
+
+#if OPTION_G34_SOCKET_SUPPORT == TRUE
+ #define F15_G34_BRANDSTRING1 NULL,
+ #define F15_G34_BRANDSTRING2 NULL,
+#else
+ #define F15_G34_BRANDSTRING1
+ #define F15_G34_BRANDSTRING2
+#endif
+#if OPTION_C32_SOCKET_SUPPORT == TRUE
+ #define F15_C32_BRANDSTRING1 NULL,
+ #define F15_C32_BRANDSTRING2 NULL,
+#else
+ #define F15_C32_BRANDSTRING1
+ #define F15_C32_BRANDSTRING2
+#endif
+#if OPTION_AM3_SOCKET_SUPPORT == TRUE
+ #define F15_AM3_BRANDSTRING1 NULL,
+ #define F15_AM3_BRANDSTRING2 NULL,
+#else
+ #define F15_AM3_BRANDSTRING1
+ #define F15_AM3_BRANDSTRING2
+#endif
+
+#if BRAND_STRING1 == TRUE
+ CONST CPU_BRAND_TABLE ROMDATA *F15BrandIdString1Tables[] =
+ {
+ F15_G34_BRANDSTRING1
+ F15_C32_BRANDSTRING1
+ F15_AM3_BRANDSTRING1
+ };
+
+ CONST UINT8 F15BrandIdString1TableCount = (sizeof (F15BrandIdString1Tables) / sizeof (F15BrandIdString1Tables[0]));
+#endif
+
+#if BRAND_STRING2 == TRUE
+ CONST CPU_BRAND_TABLE ROMDATA *F15BrandIdString2Tables[] =
+ {
+ F15_G34_BRANDSTRING2
+ F15_C32_BRANDSTRING2
+ F15_AM3_BRANDSTRING2
+ };
+
+ CONST UINT8 F15BrandIdString2TableCount = (sizeof (F15BrandIdString2Tables) / sizeof (F15BrandIdString2Tables[0]));
+#endif
+
+CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY ROMDATA F15LogicalIdTable[] =
+{
+ OPT_F15_OR_ID
+};
+
+#endif // _OPTION_FAMILY_15H_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionGfxRecovery.h b/src/vendorcode/amd/agesa/f14/Include/OptionGfxRecovery.h
new file mode 100644
index 0000000..e7d921e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Include/OptionGfxRecovery.h
@@ -0,0 +1,84 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD GFX Recovery option API.
+ *
+ * Contains structures and values used to control the GfxRecovery option code.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: OPTION
+ * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _OPTION_GFX_RECOVERY_H_
+#define _OPTION_GFX_RECOVERY_H_
+
+/*----------------------------------------------------------------------------------------
+ * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S, S T R U C T U R E S, E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+typedef AGESA_STATUS OPTION_GFX_RECOVERY_FEATURE (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+#define GFX_RECOVERY_STRUCT_VERSION 0x01
+
+/// The Option Configuration of GFX Recovery
+typedef struct {
+ UINT16 OptGfxRecoveryVersion; ///< The version number of GFX Recovery
+ OPTION_GFX_RECOVERY_FEATURE *GfxRecoveryFeature; ///< The Option Feature of GFX Recovery
+} OPTION_GFX_RECOVERY_CONFIGURATION;
+
+/*----------------------------------------------------------------------------------------
+ * F U N C T I O N P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+
+#endif // _OPTION_GFX_RECOVERY_H_
diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionGfxRecoveryInstall.h b/src/vendorcode/amd/agesa/f14/Include/OptionGfxRecoveryInstall.h
new file mode 100644
index 0000000..d271cd0
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Include/OptionGfxRecoveryInstall.h
@@ -0,0 +1,56 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: GfxRecovery
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Options
+ * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _OPTION_GFX_RECOVERY_INSTALL_H_
+#define _OPTION_GFX_RECOVERY_INSTALL_H_
+
+/* This option is designed to be included into the platform solution install
+ * file. The platform solution install file will define the options status.
+ * Check to validate the definition
+ */
+
+
+#endif // _OPTION_GFX_RECOVERY_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionGnb.h b/src/vendorcode/amd/agesa/f14/Include/OptionGnb.h
new file mode 100644
index 0000000..5f3fbd6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Include/OptionGnb.h
@@ -0,0 +1,92 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD ALIB option API.
+ *
+ * Contains structures and values used to control the ALIB option code.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: OPTION
+ * @e \$Revision: 40151 $ @e \$Date: 2010-10-20 06:38:17 +0800 (Wed, 20 Oct 2010) $
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _OPTION_GNB_H_
+#define _OPTION_GNB_H_
+
+/*----------------------------------------------------------------------------------------
+ * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S, S T R U C T U R E S, E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+typedef AGESA_STATUS OPTION_GNB_FEATURE (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+/// The Option Configuration of ALIB
+typedef struct {
+ UINT64 Type; ///< Type
+ OPTION_GNB_FEATURE *GnbFeature; ///< The GNB Feature
+} OPTION_GNB_CONFIGURATION;
+
+/// The Build time options configuration
+typedef struct {
+ BOOLEAN IgfxModeAsPcieEp; ///< Itegrated Gfx mode Pcie EP or Legacy
+ BOOLEAN LclkDeepSleepEn; ///< Default for LCLK deep sleep
+ BOOLEAN LclkDpmEn; ///< Default for LCLK DPM
+ BOOLEAN GmcPowerGateStutterOnly; ///< Force GMC power gate to stutter only
+ BOOLEAN SmuSclkClockGatingEnable;///< Control SMU SCLK gating
+ BOOLEAN PcieAspmBlackListEnable; ///< Control Pcie Aspm Black List
+} GNB_BUILD_OPTIONS;
+
+/*----------------------------------------------------------------------------------------
+ * F U N C T I O N P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+#endif // _OPTION_GNB_H_
diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionGnbInstall.h b/src/vendorcode/amd/agesa/f14/Include/OptionGnbInstall.h
new file mode 100644
index 0000000..d8acee7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Include/OptionGnbInstall.h
@@ -0,0 +1,449 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: GNB
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Options
+ * @e \$Revision: 40151 $ @e \$Date: 2010-10-20 06:38:17 +0800 (Wed, 20 Oct 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _OPTION_GNB_INSTALL_H_
+#define _OPTION_GNB_INSTALL_H_
+
+#include "S3SaveState.h"
+/* This option is designed to be included into the platform solution install
+ * file. The platform solution install file will define the options status.
+ * Check to validate the definition
+ */
+
+#define GNB_TYPE_LN OPTION_FAMILY12H
+#define GNB_TYPE_ON OPTION_FAMILY14H
+#define GNB_TYPE_KR FALSE
+#define GNB_TYPE_TN FALSE
+
+#ifndef CFG_IGFX_AS_PCIE_EP
+ #define CFG_IGFX_AS_PCIE_EP TRUE
+#endif
+
+#ifndef CFG_LCLK_DEEP_SLEEP_EN
+ #if (GNB_TYPE_ON == TRUE)
+ #define CFG_LCLK_DEEP_SLEEP_EN TRUE
+ #else
+ #define CFG_LCLK_DEEP_SLEEP_EN FALSE
+ #endif
+#endif
+
+#ifndef CFG_LCLK_DPM_EN
+ #if (GNB_TYPE_ON == TRUE)
+ #define CFG_LCLK_DPM_EN TRUE
+ #else
+ #define CFG_LCLK_DPM_EN FALSE
+ #endif
+#endif
+
+#ifndef CFG_GMC_POWER_GATE_STUTTER_ONLY
+ #define CFG_GMC_POWER_GATE_STUTTER_ONLY FALSE
+#endif
+
+#ifndef CFG_SMU_SCLK_CLOCK_GATING_ENABLE
+ #if (GNB_TYPE_ON == TRUE)
+ #define CFG_SMU_SCLK_CLOCK_GATING_ENABLE TRUE
+ #else
+ #define CFG_SMU_SCLK_CLOCK_GATING_ENABLE FALSE
+ #endif
+#endif
+
+#ifndef CFG_PCIE_ASPM_BLACK_LIST_ENABLE
+ #define CFG_PCIE_ASPM_BLACK_LIST_ENABLE TRUE
+#endif
+
+GNB_BUILD_OPTIONS GnbBuildOptions = {
+ CFG_IGFX_AS_PCIE_EP,
+ CFG_LCLK_DEEP_SLEEP_EN,
+ CFG_LCLK_DPM_EN,
+ CFG_GMC_POWER_GATE_STUTTER_ONLY,
+ CFG_SMU_SCLK_CLOCK_GATING_ENABLE,
+ CFG_PCIE_ASPM_BLACK_LIST_ENABLE
+};
+
+
+
+#if (AGESA_ENTRY_INIT_EARLY == TRUE)
+//---------------------------------------------------------------------------------------------------
+ #ifndef OPTION_NB_EARLY_INIT
+ #define OPTION_NB_EARLY_INIT TRUE
+ #endif
+ #if (OPTION_NB_EARLY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
+ OPTION_GNB_FEATURE NbInitAtEarly;
+ #define OPTION_NBINITATEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtEarly},
+ #else
+ #define OPTION_NBINITATEARLY_ENTRY
+ #endif
+//---------------------------------------------------------------------------------------------------
+// SMU init
+ #ifndef OPTION_SMU
+ #define OPTION_SMU TRUE
+ #endif
+ #if (OPTION_SMU == TRUE) && (GNB_TYPE_LN == TRUE)
+ OPTION_GNB_FEATURE F12NbSmuInitFeature;
+ #define OPTION_F12NBSMUINITFEATURE_ENTRY {AMD_FAMILY_LN, F12NbSmuInitFeature},
+ #else
+ #define OPTION_F12NBSMUINITFEATURE_ENTRY
+ #endif
+ #if (OPTION_SMU == TRUE) && (GNB_TYPE_ON == TRUE)
+ OPTION_GNB_FEATURE F14NbSmuInitFeature;
+ #define OPTION_F14NBSMUINITFEATURE_ENTRY {AMD_FAMILY_ON, F14NbSmuInitFeature},
+ #else
+ #define OPTION_F14NBSMUINITFEATURE_ENTRY
+ #endif
+ #if (OPTION_SMU == TRUE) && (GNB_TYPE_KR == TRUE)
+ OPTION_GNB_FEATURE KRNbSmuInitFeature;
+ #define OPTION_KRNBSMUINITFEATURE_ENTRY {AMD_FAMILY_KR, KRNbSmuInitFeature},
+ #else
+ #define OPTION_KRNBSMUINITFEATURE_ENTRY
+ #endif
+//---------------------------------------------------------------------------------------------------
+ #ifndef OPTION_PCIE_CONFIG_INIT
+ #define OPTION_PCIE_CONFIG_INIT TRUE
+ #endif
+ #if (OPTION_PCIE_CONFIG_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
+ OPTION_GNB_FEATURE PcieConfigurationInit;
+ #define OPTION_PCIECONFIGURATIONINIT_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieConfigurationInit},
+ #else
+ #define OPTION_PCIECONFIGURATIONINIT_ENTRY
+ #endif
+//---------------------------------------------------------------------------------------------------
+ #ifndef OPTION_PCIE_EARLY_INIT
+ #define OPTION_PCIE_EARLY_INIT TRUE
+ #endif
+ #if (OPTION_PCIE_EARLY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
+ OPTION_GNB_FEATURE PcieInitAtEarly;
+ #define OPTION_PCIEINITATEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtEarly},
+ #else
+ #define OPTION_PCIEINITATEARLY_ENTRY
+ #endif
+//---------------------------------------------------------------------------------------------------
+ OPTION_GNB_CONFIGURATION GnbEarlyFeatureTable[] = {
+ OPTION_NBINITATEARLY_ENTRY
+ OPTION_F12NBSMUINITFEATURE_ENTRY
+ OPTION_F14NBSMUINITFEATURE_ENTRY
+ OPTION_KRNBSMUINITFEATURE_ENTRY
+ OPTION_PCIECONFIGURATIONINIT_ENTRY
+ OPTION_PCIEINITATEARLY_ENTRY
+ {0, NULL}
+ };
+
+#endif
+
+#if (AGESA_ENTRY_INIT_POST == TRUE)
+//---------------------------------------------------------------------------------------------------
+ #ifndef OPTION_GFX_CONFIG_POST_INIT
+ #define OPTION_GFX_CONFIG_POST_INIT TRUE
+ #endif
+ #if (OPTION_GFX_CONFIG_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
+ OPTION_GNB_FEATURE GfxConfigPostInterface;
+ #define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxConfigPostInterface},
+ #else
+ #define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY
+ #endif
+//---------------------------------------------------------------------------------------------------
+ #ifndef OPTION_GFX_POST_INIT
+ #define OPTION_GFX_POST_INIT TRUE
+ #endif
+ #if (OPTION_GFX_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
+ OPTION_GNB_FEATURE GfxInitAtPost;
+ #define OPTION_GFXINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtPost},
+ #else
+ #define OPTION_GFXINITATPOST_ENTRY
+ #endif
+//---------------------------------------------------------------------------------------------------
+ #ifndef OPTION_NB_POST_INIT
+ #define OPTION_NB_POST_INIT TRUE
+ #endif
+ #if (OPTION_NB_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
+ OPTION_GNB_FEATURE NbInitAtPost;
+ #define OPTION_NBINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtPost},
+ #else
+ #define OPTION_NBINITATPOST_ENTRY
+ #endif
+//---------------------------------------------------------------------------------------------------
+ #ifndef OPTION_PCIE_POST_INIT
+ #define OPTION_PCIE_POST_INIT TRUE
+ #endif
+ #if (OPTION_PCIE_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
+ OPTION_GNB_FEATURE PcieInitAtPost;
+ #define OPTION_PCIEINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtPost},
+ #else
+ #define OPTION_PCIEINITATPOST_ENTRY
+ #endif
+//---------------------------------------------------------------------------------------------------
+ OPTION_GNB_CONFIGURATION GnbPostFeatureTable[] = {
+ OPTION_GFXCONFIGPOSTINTERFACE_ENTRY
+ OPTION_GFXINITATPOST_ENTRY
+ {0, NULL}
+ };
+
+ OPTION_GNB_CONFIGURATION GnbPostAfterDramFeatureTable[] = {
+ OPTION_NBINITATPOST_ENTRY
+ OPTION_PCIEINITATPOST_ENTRY
+ {0, NULL}
+ };
+#endif
+
+#if (AGESA_ENTRY_INIT_ENV == TRUE)
+//---------------------------------------------------------------------------------------------------
+ #ifndef OPTION_FUSE_TABLE_INIT
+ #define OPTION_FUSE_TABLE_INIT TRUE
+ #endif
+ #if (OPTION_FUSE_TABLE_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
+ OPTION_GNB_FEATURE NbFuseTableFeature;
+ #define OPTION_NBFUSETABLEFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbFuseTableFeature},
+ #else
+ #define OPTION_NBFUSETABLEFEATURE_ENTRY
+ #endif
+//---------------------------------------------------------------------------------------------------
+ #ifndef OPTION_NB_ENV_INIT
+ #define OPTION_NB_ENV_INIT TRUE
+ #endif
+ #if (OPTION_NB_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
+ OPTION_GNB_FEATURE NbInitAtEnv;
+ #define OPTION_NBINITATENVT_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtEnv},
+ #else
+ #define OPTION_NBINITATENVT_ENTRY
+ #endif
+//---------------------------------------------------------------------------------------------------
+ #ifndef OPTION_GFX_CONFIG_ENV_INIT
+ #define OPTION_GFX_CONFIG_ENV_INIT TRUE
+ #endif
+ #if (OPTION_GFX_CONFIG_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
+ OPTION_GNB_FEATURE GfxConfigEnvInterface;
+ #define OPTION_GFXCONFIGENVINTERFACE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxConfigEnvInterface},
+ #else
+ #define OPTION_GFXCONFIGENVINTERFACE_ENTRY
+ #endif
+
+//---------------------------------------------------------------------------------------------------
+ #ifndef OPTION_GFX_ENV_INIT
+ #define OPTION_GFX_ENV_INIT TRUE
+ #endif
+ #if (OPTION_GFX_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
+ OPTION_GNB_FEATURE GfxInitAtEnvPost;
+ #define OPTION_GFXINITATENVPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtEnvPost},
+ #else
+ #define OPTION_GFXINITATENVPOST_ENTRY
+ #endif
+//---------------------------------------------------------------------------------------------------
+ #ifndef OPTION_POWER_GATE
+ #define OPTION_POWER_GATE TRUE
+ #endif
+ #if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_LN == TRUE)
+ OPTION_GNB_FEATURE F12NbPowerGateFeature;
+ #define OPTION_F12NBPOWERGATEFEATURE_ENTRY {AMD_FAMILY_LN, F12NbPowerGateFeature},
+ #else
+ #define OPTION_F12NBPOWERGATEFEATURE_ENTRY
+ #endif
+ #if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_ON == TRUE)
+ OPTION_GNB_FEATURE F14NbPowerGateFeature;
+ #define OPTION_F14NBPOWERGATEFEATURE_ENTRY {AMD_FAMILY_ON, F14NbPowerGateFeature},
+ #else
+ #define OPTION_F14NBPOWERGATEFEATURE_ENTRY
+ #endif
+ #if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_KR == TRUE)
+ OPTION_GNB_FEATURE KRNbPowerGateFeature;
+ #define OPTION_KRNBPOWERGATEFEATURE_ENTRY {AMD_FAMILY_KR, KRNbPowerGateFeature},
+ #else
+ #define OPTION_KRNBPOWERGATEFEATURE_ENTRY
+ #endif
+//---------------------------------------------------------------------------------------------------
+ #ifndef OPTION_PCIE_ENV_INIT
+ #define OPTION_PCIE_ENV_INIT TRUE
+ #endif
+ #if (OPTION_PCIE_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
+ OPTION_GNB_FEATURE PcieInitAtEnv;
+ #define OPTION_PCIEINITATENV_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtEnv},
+ #else
+ #define OPTION_PCIEINITATENV_ENTRY
+ #endif
+//---------------------------------------------------------------------------------------------------
+
+ OPTION_GNB_CONFIGURATION GnbEnvFeatureTable[] = {
+ OPTION_NBFUSETABLEFEATURE_ENTRY
+ OPTION_NBINITATENVT_ENTRY
+ OPTION_PCIEINITATENV_ENTRY
+ OPTION_GFXCONFIGENVINTERFACE_ENTRY
+ OPTION_GFXINITATENVPOST_ENTRY
+ OPTION_F12NBPOWERGATEFEATURE_ENTRY
+ OPTION_F14NBPOWERGATEFEATURE_ENTRY
+ OPTION_KRNBPOWERGATEFEATURE_ENTRY
+ {0, NULL}
+ };
+#endif
+
+#if (AGESA_ENTRY_INIT_MID == TRUE)
+//---------------------------------------------------------------------------------------------------
+ #ifndef OPTOIN_GNB_CABLESAFE
+ #define OPTOIN_GNB_CABLESAFE TRUE
+ #endif
+ #if (OPTOIN_GNB_CABLESAFE == TRUE) && (GNB_TYPE_LN == TRUE)
+ OPTION_GNB_FEATURE GnbCableSafeEntry;
+ #define OPTION_GNBCABLESAFEENTRY_ENTRY {AMD_FAMILY_LN, GnbCableSafeEntry},
+ #else
+ #define OPTION_GNBCABLESAFEENTRY_ENTRY
+ #endif
+//---------------------------------------------------------------------------------------------------
+ #ifndef OPTOIN_NB_LCLK_NCLK_RATIO
+ #define OPTOIN_NB_LCLK_NCLK_RATIO TRUE
+ #endif
+ #if (OPTOIN_NB_LCLK_NCLK_RATIO == TRUE) && (GNB_TYPE_ON == TRUE)
+ OPTION_GNB_FEATURE F14NbLclkNclkRatioFeature;
+ #define OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY {AMD_FAMILY_ON, F14NbLclkNclkRatioFeature},
+ #else
+ #define OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY
+ #endif
+ #if (OPTOIN_NB_LCLK_NCLK_RATIO == TRUE) && (GNB_TYPE_KR == TRUE)
+ OPTION_GNB_FEATURE KRNbLclkNclkRatioFeature;
+ #define OPTION_KRNBLCLKNCLKRATIOFEATURE_ENTRY {AMD_FAMILY_KR, KRNbLclkNclkRatioFeature},
+ #else
+ #define OPTION_KRNBLCLKNCLKRATIOFEATURE_ENTRY
+ #endif
+//---------------------------------------------------------------------------------------------------
+ #ifndef OPTION_NB_LCLK_DPM_INIT
+ #define OPTION_NB_LCLK_DPM_INIT TRUE
+ #endif
+ #if (OPTION_NB_LCLK_DPM_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
+ OPTION_GNB_FEATURE NbLclkDpmFeature;
+ #define OPTION_NBLCLKDPMFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbLclkDpmFeature},
+ #else
+ #define OPTION_NBLCLKDPMFEATURE_ENTRY
+ #endif
+//---------------------------------------------------------------------------------------------------
+ #ifndef OPTION_PCIE_POWER_GATE
+ #define OPTION_PCIE_POWER_GATE TRUE
+ #endif
+ #if (OPTION_PCIE_POWER_GATE == TRUE) && (GNB_TYPE_LN == TRUE)
+ OPTION_GNB_FEATURE PciePowerGateFeature;
+ #define OPTION_PCIEPOWERGATEFEATURE_ENTRY {AMD_FAMILY_LN, PciePowerGateFeature},
+ #else
+ #define OPTION_PCIEPOWERGATEFEATURE_ENTRY
+ #endif
+//---------------------------------------------------------------------------------------------------
+ #ifndef OPTION_GFX_MID_INIT
+ #define OPTION_GFX_MID_INIT TRUE
+ #endif
+ #if (OPTION_GFX_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
+ OPTION_GNB_FEATURE GfxInitAtMidPost;
+ #define OPTION_GFXINITATMIDPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtMidPost},
+ #else
+ #define OPTION_GFXINITATMIDPOST_ENTRY
+ #endif
+//---------------------------------------------------------------------------------------------------
+ #ifndef OPTION_GFX_INTEGRATED_TABLE_INIT
+ #define OPTION_GFX_INTEGRATED_TABLE_INIT TRUE
+ #endif
+ #if (OPTION_GFX_INTEGRATED_TABLE_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
+ OPTION_GNB_FEATURE GfxIntegratedInfoTableEntry;
+ #define OPTION_GFXINTEGRATEDINFOTABLE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxIntegratedInfoTableEntry},
+ #else
+ #define OPTION_GFXINTEGRATEDINFOTABLE_ENTRY
+ #endif
+//---------------------------------------------------------------------------------------------------
+ #ifndef OPTION_PCIe_MID_INIT
+ #define OPTION_PCIe_MID_INIT TRUE
+ #endif
+ #if (OPTION_PCIe_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
+ OPTION_GNB_FEATURE PcieInitAtMid;
+ #define OPTION_PCIEINITATMID_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtMid},
+ #else
+ #define OPTION_PCIEINITATMID_ENTRY
+ #endif
+//---------------------------------------------------------------------------------------------------
+ #ifndef OPTION_NB_MID_INIT
+ #define OPTION_NB_MID_INIT TRUE
+ #endif
+ #if (OPTION_NB_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
+ OPTION_GNB_FEATURE NbInitAtLatePost;
+ #define OPTION_NBINITATLATEPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtLatePost},
+ #else
+ #define OPTION_NBINITATLATEPOST_ENTRY
+ #endif
+//---------------------------------------------------------------------------------------------------
+ OPTION_GNB_CONFIGURATION GnbMidFeatureTable[] = {
+ OPTION_GFXINITATMIDPOST_ENTRY
+ OPTION_GFXINTEGRATEDINFOTABLE_ENTRY
+ OPTION_GNBCABLESAFEENTRY_ENTRY
+ OPTION_PCIEINITATMID_ENTRY
+ OPTION_NBINITATLATEPOST_ENTRY
+ OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY
+ OPTION_KRNBLCLKNCLKRATIOFEATURE_ENTRY
+ OPTION_NBLCLKDPMFEATURE_ENTRY
+ OPTION_PCIEPOWERGATEFEATURE_ENTRY
+ {0, NULL}
+ };
+#endif
+
+#if (AGESA_ENTRY_INIT_LATE == TRUE)
+//---------------------------------------------------------------------------------------------------
+ #ifndef OPTION_ALIB
+ #define OPTION_ALIB FALSE
+ #endif
+ #if (OPTION_ALIB == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
+ OPTION_GNB_FEATURE PcieAlibFeature;
+ #define OPTION_PCIEALIBFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieAlibFeature},
+ #else
+ #define OPTION_PCIEALIBFEATURE_ENTRY
+ #endif
+//---------------------------------------------------------------------------------------------------
+ OPTION_GNB_CONFIGURATION GnbLateFeatureTable[] = {
+ OPTION_PCIEALIBFEATURE_ENTRY
+ {0, NULL}
+ };
+#endif
+
+#if (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE )
+ S3_DISPATCH_FUNCTION NbSmuServiceRequestS3Script;
+ S3_DISPATCH_FUNCTION PcieLateRestoreS3Script;
+ S3_DISPATCH_FUNCTION NbSmuIndirectWriteS3Script;
+ #define GNB_S3_DISPATCH_FUNCTION_TABLE \
+ {S3DispatchGnbSmuIndirectWrite, NbSmuIndirectWriteS3Script}, \
+ {S3DispatchGnbSmuServiceRequest, NbSmuServiceRequestS3Script}, \
+ {S3DispatchGnbPcieLateRestore, PcieLateRestoreS3Script},
+#endif
+
+#endif // _OPTION_GNB_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionHtAssistInstall.h b/src/vendorcode/amd/agesa/f14/Include/OptionHtAssistInstall.h
new file mode 100644
index 0000000..171e9ea
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Include/OptionHtAssistInstall.h
@@ -0,0 +1,109 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: HT Assist
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Options
+ * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _OPTION_HT_ASSIST_INSTALL_H_
+#define _OPTION_HT_ASSIST_INSTALL_H_
+
+#include "cpuHtAssist.h"
+
+/* This option is designed to be included into the platform solution install
+ * file. The platform solution install file will define the options status.
+ * Check to validate the definition
+ */
+#define OPTION_HT_ASSIST_FEAT
+#define F10_HT_ASSIST_SUPPORT
+#define F15_HT_ASSIST_SUPPORT
+#define HT_ASSIST_AP_DISABLE_CACHE
+#define HT_ASSIST_AP_ENABLE_CACHE
+
+#if (OPTION_HT_ASSIST == TRUE || OPTION_ATM_MODE == TRUE)
+ #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)
+ #ifdef OPTION_FAMILY10H
+ #if OPTION_FAMILY10H == TRUE
+ #if OPTION_FAMILY10H_HY == TRUE
+ extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHtAssist;
+ #undef OPTION_HT_ASSIST_FEAT
+ #define OPTION_HT_ASSIST_FEAT &CpuFeatureHtAssist,
+ extern CONST HT_ASSIST_FAMILY_SERVICES ROMDATA F10HtAssist;
+ #undef F10_HT_ASSIST_SUPPORT
+ #define F10_HT_ASSIST_SUPPORT {AMD_FAMILY_10_HY, &F10HtAssist},
+ #endif
+ #endif
+ #endif
+
+ #ifdef OPTION_FAMILY15H
+ #if OPTION_FAMILY15H == TRUE
+ extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHtAssist;
+ #undef OPTION_HT_ASSIST_FEAT
+ #define OPTION_HT_ASSIST_FEAT &CpuFeatureHtAssist,
+ extern CONST HT_ASSIST_FAMILY_SERVICES ROMDATA F15HtAssist;
+ #undef F15_HT_ASSIST_SUPPORT
+ #define F15_HT_ASSIST_SUPPORT {AMD_FAMILY_15, &F15HtAssist},
+ #endif
+ #endif
+
+ CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA HtAssistFamilyServiceArray[] =
+ {
+ F10_HT_ASSIST_SUPPORT
+ F15_HT_ASSIST_SUPPORT
+ {0, NULL}
+ };
+ CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA HtAssistFamilyServiceTable =
+ {
+ (sizeof (HtAssistFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+ &HtAssistFamilyServiceArray[0]
+ };
+
+ #undef AGESA_ENTRY_LATE_RUN_AP_TASK
+ #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE
+ #undef HT_ASSIST_AP_DISABLE_CACHE
+ #define HT_ASSIST_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches},
+ #undef HT_ASSIST_AP_ENABLE_CACHE
+ #define HT_ASSIST_AP_ENABLE_CACHE {AP_LATE_TASK_ENABLE_CACHE, (IMAGE_ENTRY) EnableAllCaches},
+ #endif
+#endif
+
+#endif // _OPTION_HT_ASSIST_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionHtInstall.h b/src/vendorcode/amd/agesa/f14/Include/OptionHtInstall.h
new file mode 100644
index 0000000..637f069
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Include/OptionHtInstall.h
@@ -0,0 +1,301 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: Ht
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Options
+ * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _OPTION_HT_INSTALL_H_
+#define _OPTION_HT_INSTALL_H_
+
+#include "Topology.h"
+#include "htFeat.h"
+#include "htInterface.h"
+#include "htNb.h"
+#include "htTopologies.h"
+/*
+ * Advanced Option only, hardware socket naming is the preferred method.
+ */
+#ifdef BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP
+ #define CFG_SYSTEM_PHYSICAL_SOCKET_MAP (BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP)
+#else
+ #define CFG_SYSTEM_PHYSICAL_SOCKET_MAP (NULL)
+#endif
+
+/*
+ * OPTION_IS_RECOVERY_HT is true if Basic API is being used.
+ */
+#ifndef OPTION_IS_RECOVERY_HT
+ #define OPTION_IS_RECOVERY_HT TRUE
+#endif
+
+/* This option is designed to be included into the platform solution install
+ * file. The platform solution install file will define the options status.
+ * Check to validate the definition.
+ */
+
+#ifndef OPTION_MULTISOCKET
+ #error BLDOPT: Option not defined: "OPTION_MULTISOCKET"
+#endif
+
+/*
+ * Based on user level options, set Ht internal options.
+ * For now, Family 10h support will assume single module. For multi module,
+ * this will have to be changed to not set non-coherent only.
+ */
+#define OPTION_HT_NON_COHERENT_ONLY FALSE
+
+#if ((OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE) || (OPTION_FAMILY16H == TRUE))
+/* Fusion Families do not need a non-coherent only option. */
+#else
+ // Process Family 10h and 15h by socket, applying the MultiSocket option where it is allowable.
+ #if OPTION_G34_SOCKET_SUPPORT == FALSE
+ // Hydra has coherent support, other Family 10h should follow MultiSocket support.
+ #if OPTION_MULTISOCKET == FALSE
+ #undef OPTION_HT_NON_COHERENT_ONLY
+ #define OPTION_HT_NON_COHERENT_ONLY TRUE
+ #endif
+ #endif
+#endif
+
+/*
+ * Macros will generate the correct item reference based on options
+ */
+#if AGESA_ENTRY_INIT_EARLY == TRUE
+ // Select the interface and features
+ #if ((OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE) || (OPTION_FAMILY16H == TRUE))
+ #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
+ #define INTERNAL_HT_OPTION_FEATURES &HtFeaturesNone
+ #define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceMapsOnly
+ #else
+ // Family 10h and 15h
+ #if OPTION_HT_NON_COHERENT_ONLY == FALSE
+ #define INTERNAL_HT_OPTION_FEATURES &HtFeaturesDefault
+ #define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceDefault
+ #else
+ #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
+ #define INTERNAL_HT_OPTION_FEATURES &HtFeaturesNonCoherentOnly
+ #define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceNonCoherentOnly
+ #endif
+ #endif
+ // Select Northbridge components
+ #if OPTION_FAMILY10H == TRUE
+ #if OPTION_HT_NON_COHERENT_ONLY == TRUE
+ #define INTERNAL_HT_OPTION_FAM10_NB &HtFam10NbNonCoherentOnly, &HtFam10RevDNbNonCoherentOnly,
+ #else
+ #define INTERNAL_HT_OPTION_FAM10_NB &HtFam10NbDefault, &HtFam10RevDNbDefault,
+ #endif
+ #else
+ #define INTERNAL_HT_OPTION_FAM10_NB
+ #endif
+ #if OPTION_FAMILY12H == TRUE
+ #define INTERNAL_HT_OPTION_FAM12_NB &HtFam12Nb,
+ #else
+ #define INTERNAL_HT_OPTION_FAM12_NB
+ #endif
+ #if OPTION_FAMILY14H == TRUE
+ #define INTERNAL_HT_OPTION_FAM14_NB &HtFam14Nb,
+ #else
+ #define INTERNAL_HT_OPTION_FAM14_NB
+ #endif
+ #if OPTION_FAMILY15H == TRUE
+ #if OPTION_HT_NON_COHERENT_ONLY == TRUE
+ #define INTERNAL_HT_OPTION_FAM15_NB &HtFam15NbNonCoherentOnly,
+ #else
+ #define INTERNAL_HT_OPTION_FAM15_NB &HtFam15NbDefault,
+ #endif
+ #else
+ #define INTERNAL_HT_OPTION_FAM15_NB
+ #endif
+
+ #define INTERNAL_ONLY_NB_LIST_ITEM INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS,
+ #ifndef INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS
+ #undef INTERNAL_ONLY_NB_LIST_ITEM
+ #define INTERNAL_ONLY_NB_LIST_ITEM
+ #endif
+
+ /* Install the correct set of northbridge implementations. Each item provides its own comma, the last item
+ * is ok to have a comma because the final item (NULL) is added below.
+ */
+ #define INTERNAL_HT_OPTION_SUPPORTED_NBS \
+ INTERNAL_ONLY_NB_LIST_ITEM \
+ INTERNAL_HT_OPTION_FAM10_NB \
+ INTERNAL_HT_OPTION_FAM15_NB \
+ INTERNAL_HT_OPTION_FAM12_NB \
+ INTERNAL_HT_OPTION_FAM14_NB
+
+#else
+ // Not Init Early
+ #define INTERNAL_HT_OPTION_FEATURES NULL
+ #define INTERNAL_HT_OPTION_INTERFACE NULL
+ #define INTERNAL_HT_OPTION_SUPPORTED_NBS NULL
+ #define HT_OPTIONS_PLATFORM NULL
+ #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
+#endif
+
+#ifdef AGESA_ENTRY_INIT_EARLY
+ #if AGESA_ENTRY_INIT_EARLY == TRUE
+
+ extern HT_FEATURES HtFeaturesDefault;
+ extern HT_FEATURES HtFeaturesNonCoherentOnly;
+ extern HT_FEATURES HtFeaturesNone;
+ extern HT_INTERFACE HtInterfaceDefault;
+ extern HT_INTERFACE HtInterfaceNonCoherentOnly;
+ extern HT_INTERFACE HtInterfaceMapsOnly;
+ extern HT_INTERFACE HtInterfaceNone;
+ extern NORTHBRIDGE HtFam10NbDefault;
+ extern NORTHBRIDGE HtFam10RevDNbDefault;
+ extern NORTHBRIDGE HtFam10NbNonCoherentOnly;
+ extern NORTHBRIDGE HtFam10RevDNbNonCoherentOnly;
+ extern NORTHBRIDGE HtFam12Nb;
+ extern NORTHBRIDGE HtFam14Nb;
+ extern NORTHBRIDGE HtFam10NbNone;
+ extern NORTHBRIDGE HtFam15NbDefault;
+ extern NORTHBRIDGE HtFam15NbNonCoherentOnly;
+
+ CONST VOID * CONST ROMDATA HtInstalledFamilyNorthbridgeList[] = {
+ INTERNAL_HT_OPTION_SUPPORTED_NBS
+ NULL
+ };
+
+ STATIC CONST AMD_HT_INTERFACE ROMDATA HtOptionsPlatform =
+ {
+ CFG_STARTING_BUSNUM, CFG_MAXIMUM_BUSNUM, CFG_ALLOCATED_BUSNUM,
+ (MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST,
+ (DEVICE_CAP_OVERRIDE *)CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST,
+ (CPU_TO_CPU_PCB_LIMITS *)CFG_HTFABRIC_LIMITS_LIST,
+ (IO_PCB_LIMITS *)CFG_HTCHAIN_LIMITS_LIST,
+ (OVERRIDE_BUS_NUMBERS *)CFG_BUS_NUMBERS_LIST,
+ (IGNORE_LINK *)CFG_IGNORE_LINK_LIST,
+ (SKIP_REGANG *)CFG_LINK_SKIP_REGANG_LIST,
+ (UINT8 **)CFG_ADDITIONAL_TOPOLOGIES_LIST,
+ (SYSTEM_PHYSICAL_SOCKET_MAP *)CFG_SYSTEM_PHYSICAL_SOCKET_MAP
+ };
+ #ifndef HT_OPTIONS_PLATFORM
+ #define HT_OPTIONS_PLATFORM &HtOptionsPlatform
+ #endif
+
+ /**
+ * A list of all the supported topologies.
+ *
+ */
+ #ifndef INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES
+ CONST UINT8 *CONST ROMDATA AmdTopolist[] =
+ {
+ amdHtTopologySingleNode,
+ amdHtTopologyDualNode,
+ amdHtTopologyThreeLine,
+ amdHtTopologyTriangle,
+ amdHtTopologyFourLine,
+ amdHtTopologyFourStar,
+ amdHtTopologyFourDegenerate,
+ amdHtTopologyFourSquare,
+ amdHtTopologyFourKite,
+ amdHtTopologyFourFully,
+ amdHtTopologyFiveFully,
+ amdHtTopologyFiveTwistedLadder,
+ amdHtTopologySixFully,
+ amdHtTopologySixDoubloonLower,
+ amdHtTopologySixDoubloonUpper,
+ amdHtTopologySixTwistedLadder,
+ amdHtTopologySevenFully,
+ amdHtTopologySevenTwistedLadder,
+ amdHtTopologyEightFully,
+ amdHtTopologyEightDoubloon,
+ amdHtTopologyEightTwistedLadder,
+ amdHtTopologyEightStraightLadder,
+ amdHtTopologySixTwinTriangles,
+ amdHtTopologyEightTwinFullyFourWays,
+ NULL
+ };
+ #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES AmdTopolist
+ #endif
+
+ /**
+ * Declare the instance of the Ht option configuration structure
+ */
+ CONST OPTION_HT_CONFIGURATION ROMDATA OptionHtConfiguration = {
+ OPTION_IS_RECOVERY_HT,
+ CFG_SET_HTCRC_SYNC_FLOOD,
+ CFG_USE_UNIT_ID_CLUMPING,
+ HT_OPTIONS_PLATFORM,
+ INTERNAL_HT_OPTION_INTERFACE,
+ INTERNAL_HT_OPTION_FEATURES,
+ &HtInstalledFamilyNorthbridgeList,
+ INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES
+ };
+
+ #endif
+#endif
+
+#ifndef OPTION_HT_INIIT_RESET_ENTRY
+
+ #define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset
+
+ #if (OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE)
+ #undef OPTION_HT_INIIT_RESET_ENTRY
+ #define OPTION_HT_INIIT_RESET_ENTRY NULL
+ #endif
+
+ #if ((OPTION_FAMILY10H == TRUE) || (OPTION_FAMILY15H == TRUE))
+ #undef OPTION_HT_INIIT_RESET_ENTRY
+ #define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset
+ #endif
+
+#endif
+
+#ifdef AGESA_ENTRY_INIT_RESET
+ #if AGESA_ENTRY_INIT_RESET == TRUE
+
+ CONST AMD_HT_RESET_INTERFACE ROMDATA HtOptionResetDefaults = {
+ (MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST,
+ 0 // Unused by options
+ };
+
+ CONST OPTION_HT_INIT_RESET ROMDATA HtOptionInitReset = {
+ OPTION_HT_INIIT_RESET_ENTRY
+ };
+ #endif
+
+#endif
+
+#endif // _OPTION_HT_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionHwC1eInstall.h b/src/vendorcode/amd/agesa/f14/Include/OptionHwC1eInstall.h
new file mode 100644
index 0000000..745914f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Include/OptionHwC1eInstall.h
@@ -0,0 +1,83 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: HW C1e
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Options
+ * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+#ifndef _OPTION_HW_C1E_INSTALL_H_
+#define _OPTION_HW_C1E_INSTALL_H_
+
+#include "cpuHwC1e.h"
+
+/* This option is designed to be included into the platform solution install
+ * file. The platform solution install file will define the options status.
+ * Check to validate the definition
+ */
+#define OPTION_HW_C1E_FEAT
+#define F10_HW_C1E_SUPPORT
+#if AGESA_ENTRY_INIT_EARLY == TRUE
+ #ifdef OPTION_FAMILY10H
+ #if OPTION_FAMILY10H == TRUE
+ #if (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE) || (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_PH == TRUE)
+ extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHwC1e;
+ #undef OPTION_HW_C1E_FEAT
+ #define OPTION_HW_C1E_FEAT &CpuFeatureHwC1e,
+ extern CONST HW_C1E_FAMILY_SERVICES ROMDATA F10HwC1e;
+ #undef F10_HW_C1E_SUPPORT
+ #define F10_HW_C1E_SUPPORT {(AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_RB | AMD_FAMILY_10_PH), &F10HwC1e},
+ #endif
+ #endif
+ #endif
+ CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA HwC1eFamilyServiceArray[] =
+ {
+ F10_HW_C1E_SUPPORT
+ {0, NULL}
+ };
+ CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA HwC1eFamilyServiceTable =
+ {
+ (sizeof (HwC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+ &HwC1eFamilyServiceArray[0]
+ };
+#endif
+
+#endif // _OPTION_HW_C1E_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionIdsInstall.h b/src/vendorcode/amd/agesa/f14/Include/OptionIdsInstall.h
new file mode 100644
index 0000000..11de68e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f14/Include/OptionIdsInstall.h
@@ -0,0 +1,417 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * IDS Option Install File
+ *
+ * This file generates the defaults tables for family 10h model 5 processors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Core
+ * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+#ifndef _OPTION_IDS_INSTALL_H_
+#define _OPTION_IDS_INSTALL_H_
+#include "Ids.h"
+#include "IdsHt.h"
+#include "IdsLib.h"
+#ifdef __IDS_EXTENDED__
+ #include OPTION_IDS_EXT_INSTALL_FILE
+#endif
+
+#define IDS_LATE_RUN_AP_TASK
+
+#define M_HTIDS_PORT_OVERRIDE_HOOK (PF_HtIdsGetPortOverride)CommonVoid
+#if (IDSOPT_IDS_ENABLED == TRUE)
+ #if (IDSOPT_CONTROL_ENABLED == TRUE)
+ // Check for all families which include HT Features.
+ #if (OPTION_FAMILY10H == TRUE) && (AGESA_ENTRY_INIT_POST == TRUE)
+ #undef M_HTIDS_PORT_OVERRIDE_HOOK
+ #define M_HTIDS_PORT_OVERRIDE_HOOK HtIdsGetPortOverride
+ #endif
+ #endif
+#endif // OPTION_IDS_LEVEL
+CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride = M_HTIDS_PORT_OVERRIDE_HOOK;
+
+#if (IDSOPT_IDS_ENABLED == TRUE)
+ #if (AGESA_ENTRY_INIT_LATE == TRUE)
+ #undef IDS_LATE_RUN_AP_TASK
+ #define IDS_LATE_RUN_AP_TASK
+ #endif
+#endif // OPTION_IDS_LEVEL
+
+#if (IDSOPT_TRACING_ENABLED == TRUE)
+ #if (AGESA_ENTRY_INIT_POST == TRUE)
+ #include <mu.h>
+ CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
+ { (UINT32) (UINT64) MemUWriteCachelines, "WriteCl(PhyAddrLo,BufferAddr,ClCnt)"},
+ { (UINT32) (UINT64) MemUReadCachelines, "ReadCl(BufferAddr,PhyAddrLo,ClCnt)"},
+ { (UINT32) (UINT64) MemUFlushPattern, "FlushCl(PhyAddrLo,ClCnt)"}
+ };
+ #elif (AGESA_ENTRY_INIT_RECOVERY == TRUE)
+ #include <mru.h>
+ CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
+ { (UINT32) (UINT64) MemRecUWrite1CL, "Write1Cl(PhyAddrLo,BufferAddr)"},
+ { (UINT32) (UINT64) MemRecURead1CL, "Read1Cl(BufferAddr,PhyAddrLo)"},
+ { (UINT32) (UINT64) MemRecUFlushPattern, "Flush1Cl(PhyAddrLo)"}
+ };
+ #else
+ CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
+ { (UINT32) (UINT64) CommonReturnFalse, "DefRet()"},
+ { (UINT32) (UINT64) CommonReturnFalse, "DefRet()"},
+ { (UINT32) (UINT64) CommonReturnFalse, "DefRet()"