[coreboot] [PATCH] Set up MTRR for coreboot_ram
Peter Stuge
peter at stuge.se
Tue May 3 02:50:14 CEST 2011
Stefan Reinauer wrote:
> And in addition you need to set up MTRRs correctly by doing something
> like this: (sorry, wrong CPU type but the code should be fairly similar)
>
> Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
Acked-by: Peter Stuge <peter at stuge.se>
> --- src/cpu/intel/model_106cx/cache_as_ram.inc
> +++ src/cpu/intel/model_106cx/cache_as_ram.inc
> @@ -195,13 +195,27 @@ clear_mtrrs:
>
> post_code(0x38)
>
> - /* Enable Write Back and Speculative Reads for the first 1MB. */
> + /* Enable Write Back and Speculative Reads for the first MB
> + * and coreboot_ram.
> + */
> movl $MTRRphysBase_MSR(0), %ecx
> movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax
> xorl %edx, %edx
> wrmsr
> movl $MTRRphysMask_MSR(0), %ecx
> - movl $(~(1024 * 1024 - 1) | (1 << 11)), %eax
> + movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax
> + xorl %edx, %edx
> + wrmsr
> +
> + /* Enable Caching and speculative Reads for the
> + * complete ROM now that we actually have RAM.
> + */
> + movl $MTRRphysBase_MSR(1), %ecx
> + movl $(0xffc00000 | MTRR_TYPE_WRPROT), %eax
> + xorl %edx, %edx
> + wrmsr
> + movl $MTRRphysMask_MSR(1), %ecx
> + movl $(~(4*1024*1024 - 1) | MTRRphysMaskValid), %eax
> xorl %edx, %edx
> wrmsr
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