[coreboot] [commit] r6585 - trunk/src/mainboard/amd/persimmon
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svn at coreboot.org
Sun May 15 23:56:04 CEST 2011
Author: mjones
Date: Sun May 15 23:56:03 2011
New Revision: 6585
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6585
Log:
Enable SPI cacheline prefetch early to reduce boot time.
Signed-off-by: Scott Duplichan <scott at notabs.org>
Acked-by: Marc Jones <marcj303 at gmail.com>
Modified:
trunk/src/mainboard/amd/persimmon/romstage.c
Modified: trunk/src/mainboard/amd/persimmon/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/persimmon/romstage.c Sun May 15 23:54:04 2011 (r6584)
+++ trunk/src/mainboard/amd/persimmon/romstage.c Sun May 15 23:56:03 2011 (r6585)
@@ -50,6 +50,21 @@
// all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
__writemsr (0xc0010062, 0);
+ if (boot_cpu())
+ {
+ u8 reg8;
+ // SB800: program AcpiMmioEn to enable MMIO access to MiscCntrl register
+ outb(0x24, 0xCD6);
+ reg8 = inb(0xCD7);
+ reg8 |= 1;
+ reg8 &= ~(1 << 1);
+ outb(reg8, 0xCD7);
+
+ // program SB800 MiscCntrl
+ *(volatile u32 *)(0xFED80000+0xE00+0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
+ *(volatile u32 *)(0xFED80000+0xE00+0x40) |= 1 << 1; /* 48Mhz */
+ }
+
// early enable of PrefetchEnSPIFromHost
if (boot_cpu())
{
@@ -78,17 +93,6 @@
f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
}
- //reg8 = pmio_read(0x24);
- outb(0x24, 0xCD6);
- reg8 = inb(0xCD7);
- reg8 |= 1;
- reg8 &= ~(1 << 1);
- //pmio_write(0x24, reg8);
- outb(0x24, 0xCD6);
- outb(reg8, 0xCD7);
-
- *(volatile u32 *)(0xFED80000+0xE00+0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
- *(volatile u32 *)(0xFED80000+0xE00+0x40) |= 1 << 1; /* 48Mhz */
/* Halt if there was a built in self test failure */
post_code(0x34);
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