[coreboot] [commit] r6591 - trunk/src/mainboard/amd/persimmon
Peter Stuge
peter at stuge.se
Mon May 16 01:52:07 CEST 2011
repository service wrote:
> Log:
> Enable rom cache early to reduce boot time.
> +++ trunk/src/mainboard/amd/persimmon/romstage.c Mon May 16 00:06:09 2011 (r6591)
> @@ -47,6 +47,11 @@
> u32 val;
> u8 reg8;
>
> + // all cores: allow caching of flash chip code and data
> + // (there are no cache-as-ram reliability concerns with family 14h)
> + __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
> + __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
Is this something that we should have in component code rather than
mainboard code?
And when would it be suitable to *not* allow caching, if ever? I'm
thinking if this should be an option anywhere, or not.
//Peter
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