[coreboot] [patch] ck804 mmconf

[Scott Duplichan]

Stefan Reinauer wrote:

]>> Why would the resource allocator have to worry about posted vs
]>> non-posted PCI transactions?
]> How else will the northbridge be told to make the region non-posted?
]Why would it have to? Not sure I understand your concern. Your patch 
]does not address that issue at all.

This subject came up recently:
http://www.coreboot.org/pipermail/coreboot/2010-October/061288.html

AMD processors have 8 mmio base/limit register pairs. Each pair
defines an address range as posted mmio or as non-posted mmio.
Somehow posted and non-posted ranges have to be allocated so
that they can be consolidated into a total of 8 or fewer ranges.
Then the mmio base/limit registers can be programmed to cover
the ranges.

Thanks,
ScottD