[coreboot] Trouble with cbfstool when attempting dualboot

Kyösti Mälkki kyosti.malkki at gmail.com
Tue Nov 1 14:02:30 CET 2011


On Mon, 2011-10-31 at 15:20 +0100, Patrick Georgi wrote: 
> Am Montag, 31. Oktober 2011 07:32:50 schrieb Kyösti Mälkki:
> > If my new normal/romstage is built with GCC for Cache-As-Ram, the same
> > alignment does not apply and on boot it halts before any serial output.
> Does it "halt" or is it just _very_ slow (several minutes until the 
> first life sign on serial)? The latter would indicate wrong MTRR setup, 
> while the former is a more fundamental problem.
> 

It isn't only slow. I did experience the slow version with bad MTRR
setup when I did the big->tiny bootblock switch and MTRR setup missed
one ~.

My Cache-As-Ram boot enters intel/car/cache_as_ram.inc but never reaches
LogicalAP_SIPINotdone in it. I found a note in this file saying LAPIC ID
logic works only for processors with two threads, so does a dual Xeon
P4/HT setup require re-writing this logic? The car.inc was earlier used
for Tyan s2735 that is also dual-Xeon board with same socket.


I happen to have normal/romstage that does not cross CONFIG_XIP_ROM_SIZE
boundary. I think it is a bug in cbfstool that normal/romstage placement
is unaligned, since early_mtrr_init does not cover cases where
normal/romstage crosses said boundary. One would witness the very slow
boot effect then, too.

Updated image with normal/romstage compiled with ROMCC: 

coreboot.rom: 512 kB, bootblocksize 978, romsize 524288, offset 0x0
Alignment: 64 bytes

Name                           Offset     Type         Size
fallback/romstage              0x0        stage        43801
fallback/coreboot_ram          0xab80     stage        163868
fallback/payload               0x32c00    payload      33141
(empty)                        0x3adc0    null         20888
normal/romstage                0x3ff80    stage        43789  
normal/coreboot_ram            0x4ab00    stage        163868
normal/payload                 0x72b80    payload      33141
(empty)                        0x7ad40    null         20134


Updated image with normal/romstage compiled with GCC:

coreboot.rom: 512 kB, bootblocksize 978, romsize 524288, offset 0x0
Alignment: 64 bytes

Name                           Offset     Type         Size
fallback/romstage              0x0        stage        43801
fallback/coreboot_ram          0xab80     stage        163868
fallback/payload               0x32c00    payload      33141
normal/romstage                0x3adc0    stage        15121
normal/coreboot_ram            0x3e900    stage        163868
normal/payload                 0x66980    payload      33141
(empty)                        0x6eb40    null         69798




KM 





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