[coreboot] Patch set updated for coreboot: f3b36f4 support for setting the Memory DQ Drive Strength register in amdk8 raminit
Florian Zumbiehl
gerrit at coreboot.org
Fri Nov 4 23:12:46 CET 2011
Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/382
-gerrit
commit f3b36f4d36c5be1c7f7f7e29ba5ceaa1df055a6c
Author: Florian Zumbiehl <florz at florz.de>
Date: Tue Nov 1 20:19:03 2011 +0100
support for setting the Memory DQ Drive Strength register in amdk8 raminit
make sure DRAM drive strength is not reduced
Change-Id: Ic68c10b75bd0217540fb1f55dded1f9d7f5e8aea
Signed-off-by: Florian Zumbiehl <florz at florz.de>
---
src/northbridge/amd/amdk8/pre_f.h | 6 ++++++
src/northbridge/amd/amdk8/raminit.c | 12 ++++++++++++
2 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/src/northbridge/amd/amdk8/pre_f.h b/src/northbridge/amd/amdk8/pre_f.h
index dae2d97..0d5f6fa 100644
--- a/src/northbridge/amd/amdk8/pre_f.h
+++ b/src/northbridge/amd/amdk8/pre_f.h
@@ -157,6 +157,12 @@
#define DCH_RDPREAMBLE_BASE ((2<<1)+0) /* 2.0 ns */
#define DCH_RDPREAMBLE_MIN ((2<<1)+0) /* 2.0 ns */
#define DCH_RDPREAMBLE_MAX ((9<<1)+1) /* 9.5 ns */
+#define DCH_DQ_DRV_STRENGTH_SHIFT 13
+#define DCH_DQ_DRV_STRENGTH_MASK 3
+#define DCH_DQ_DRV_STRENGTH_0 0
+#define DCH_DQ_DRV_STRENGTH_15 1
+#define DCH_DQ_DRV_STRENGTH_30 2
+#define DCH_DQ_DRV_STRENGTH_50 3
#define DCH_IDLE_LIMIT_SHIFT 16
#define DCH_IDLE_LIMIT_MASK 0x7
#define DCH_IDLE_LIMIT_0 0
diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c
index 02c764d..e09075f 100644
--- a/src/northbridge/amd/amdk8/raminit.c
+++ b/src/northbridge/amd/amdk8/raminit.c
@@ -2201,6 +2201,18 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
printk(BIOS_DEBUG, "No memory for this cpu\n");
return;
}
+
+ if (!is_cpu_pre_e0()) {
+ uint32_t dch;
+
+ // see also erratum 114, essentially: never ever
+ // set to anything but 0
+ dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
+ dch &= ~(DCH_DQ_DRV_STRENGTH_MASK << DCH_DQ_DRV_STRENGTH_SHIFT);
+ dch |= DCH_DQ_DRV_STRENGTH_0 << DCH_DQ_DRV_STRENGTH_SHIFT;
+ pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
+ }
+
dimm_mask = spd_enable_2channels(ctrl, dimm_mask);
if (dimm_mask < 0)
goto hw_spd_err;
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