[coreboot] Patch set updated for coreboot: 897a07d Refactor src/southbridge/intel/i82801ex/
Idwer Vollering (vidwer@gmail.com)
gerrit at coreboot.org
Tue Nov 8 03:23:31 CET 2011
Idwer Vollering (vidwer at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/415
-gerrit
commit 897a07d55541bec5336b67789cfc155c31053d41
Author: Idwer Vollering <vidwer at gmail.com>
Date: Mon Nov 7 17:48:33 2011 +0100
Refactor src/southbridge/intel/i82801ex/
Change-Id: I8be22f0292e322562b117f1e8bf493ed25eb4bec
Signed-off-by: Idwer Vollering <vidwer at gmail.com>
---
src/southbridge/intel/i82801ex/chip.h | 1 -
src/southbridge/intel/i82801ex/early_smbus.c | 32 ++++++++------
src/southbridge/intel/i82801ex/ehci.c | 8 ++-
src/southbridge/intel/i82801ex/i82801ex.c | 12 +++---
src/southbridge/intel/i82801ex/i82801ex.h | 26 +++++++++---
src/southbridge/intel/i82801ex/ide.c | 15 +++----
src/southbridge/intel/i82801ex/lpc.c | 59 +++++++++++++-------------
src/southbridge/intel/i82801ex/pci.c | 20 +++++----
src/southbridge/intel/i82801ex/sata.c | 35 +++++++++-------
src/southbridge/intel/i82801ex/smbus.c | 3 +-
src/southbridge/intel/i82801ex/smbus.h | 6 ++-
src/southbridge/intel/i82801ex/uhci.c | 1 -
src/southbridge/intel/i82801ex/watchdog.c | 10 +++--
src/superio/winbond/w83627thg/early_serial.c | 11 +++++
src/superio/winbond/w83627thg/w83627thg.h | 2 +
15 files changed, 141 insertions(+), 100 deletions(-)
diff --git a/src/southbridge/intel/i82801ex/chip.h b/src/southbridge/intel/i82801ex/chip.h
index f04fc3f..544b6f7 100644
--- a/src/southbridge/intel/i82801ex/chip.h
+++ b/src/southbridge/intel/i82801ex/chip.h
@@ -33,4 +33,3 @@ struct southbridge_intel_i82801ex_config
extern struct chip_operations southbridge_intel_i82801ex_ops;
#endif /* I82801EX_CHIP_H */
-
diff --git a/src/southbridge/intel/i82801ex/early_smbus.c b/src/southbridge/intel/i82801ex/early_smbus.c
index cdf1f62..b9c3849 100644
--- a/src/southbridge/intel/i82801ex/early_smbus.c
+++ b/src/southbridge/intel/i82801ex/early_smbus.c
@@ -1,21 +1,25 @@
+#include "i82801ex.h"
#include "smbus.h"
-#define SMBUS_IO_BASE 0x0f00
-
static void enable_smbus(void)
{
device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
print_spew("SMBus controller enabled\n");
- pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
- print_debug_hex32(pci_read_config32(dev, 0x20));
+ /* bit 0 is read only and hardwired to 1 */
+ pci_write_config32(dev, SMB_BASE, SMBUS_IO_BASE);
+ print_debug("SMB_BASE = 0x");
+ /* don't show bit 0 */
+ print_debug_hex32(pci_read_config32(dev, SMB_BASE) & 0xfffffffe);
+ print_debug("\n");
+
/* Set smbus enable */
- pci_write_config8(dev, 0x40, 1);
+ pci_write_config8(dev, HOSTC, 1);
/* Set smbus iospace enable */
- pci_write_config8(dev, 0x4, 1);
+ pci_write_config8(dev, PCICMD, 1);
/* SMBALERT_DIS */
- pci_write_config8(dev, 0x11, 4);
+ pci_write_config8(dev, SLV_CMD, 4);
/* Disable interrupt generation */
outb(0, SMBUS_IO_BASE + SMBHSTCTL);
@@ -81,7 +85,7 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
/* setup transaction */
/* Obtain ownership */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
- for(stat=0;(stat&0x40)==0;) {
+ for (stat = 0; (stat & 0x40) == 0;) {
stat = inb(SMBUS_IO_BASE + SMBHSTSTAT);
}
/* clear the done bit */
@@ -99,13 +103,13 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
outb(length & 0xFF, SMBUS_IO_BASE + SMBHSTDAT0);
/* try sending out the first byte of data here */
- byte=(data1>>(0))&0x0ff;
- outb(byte,SMBUS_IO_BASE + SMBBLKDAT);
+ byte = (data1 >> (0) ) & 0x0ff;
+ outb(byte, SMBUS_IO_BASE + SMBBLKDAT);
/* issue a block write command */
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x5 << 2) | 0x40,
SMBUS_IO_BASE + SMBHSTCTL);
- for(i=0;i<length;i++) {
+ for(i = 0; i < length; i++) {
/* poll for transaction completion */
if (smbus_wait_until_blk_done(SMBUS_IO_BASE) < 0) {
@@ -113,10 +117,10 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
}
/* load the next byte */
- if(i>3)
- byte=(data2>>(i%4))&0x0ff;
+ if(i > 3)
+ byte= (data2 >> (i % 4)) & 0x0ff;
else
- byte=(data1>>(i))&0x0ff;
+ byte=(data1 >> (i)) & 0x0ff;
outb(byte,SMBUS_IO_BASE + SMBBLKDAT);
/* clear the done bit */
diff --git a/src/southbridge/intel/i82801ex/ehci.c b/src/southbridge/intel/i82801ex/ehci.c
index 8ae921d..4117c4e 100644
--- a/src/southbridge/intel/i82801ex/ehci.c
+++ b/src/southbridge/intel/i82801ex/ehci.c
@@ -5,6 +5,8 @@
#include <device/pci_ops.h>
#include "i82801ex.h"
+#define ACCESS_CNTL 0x80
+
static void ehci_init(struct device *dev)
{
uint32_t cmd;
@@ -20,14 +22,14 @@ static void ehci_init(struct device *dev)
static void ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
uint8_t access_cntl;
- access_cntl = pci_read_config8(dev, 0x80);
+ access_cntl = pci_read_config8(dev, ACCESS_CNTL);
/* Enable writes to protected registers */
- pci_write_config8(dev, 0x80, access_cntl | 1);
+ pci_write_config8(dev, ACCESS_CNTL, access_cntl | 1);
/* Write the subsystem vendor and device id */
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
/* Restore protection */
- pci_write_config8(dev, 0x80, access_cntl);
+ pci_write_config8(dev, ACCESS_CNTL, access_cntl);
}
static struct pci_operations lops_pci = {
diff --git a/src/southbridge/intel/i82801ex/i82801ex.c b/src/southbridge/intel/i82801ex/i82801ex.c
index fc41645..a30e887 100644
--- a/src/southbridge/intel/i82801ex/i82801ex.c
+++ b/src/southbridge/intel/i82801ex/i82801ex.c
@@ -12,13 +12,13 @@ void i82801ex_enable(device_t dev)
/* See if we are behind the i82801ex pci bridge */
lpc_dev = dev_find_slot(dev->bus->secondary, PCI_DEVFN(0x1f, 0));
- if((dev->path.pci.devfn &0xf8)== 0xf8) {
+ if((dev->path.pci.devfn & 0xf8) == 0xf8) {
index = dev->path.pci.devfn & 7;
}
- else if((dev->path.pci.devfn &0xf8)== 0xe8) {
- index = (dev->path.pci.devfn & 7) +8;
+ else if((dev->path.pci.devfn & 0xf8) == 0xe8) {
+ index = (dev->path.pci.devfn & 7) + 8;
}
- if ((!lpc_dev) || (index >= 16) || ((1<<index)&0x3091)) {
+ if ((!lpc_dev) || (index >= 16) || ((1 << index) & 0x3091)) {
return;
}
if ((lpc_dev->vendor != PCI_VENDOR_ID_INTEL) ||
@@ -31,13 +31,13 @@ void i82801ex_enable(device_t dev)
}
}
- reg = reg_old = pci_read_config16(lpc_dev, 0xf2);
+ reg = reg_old = pci_read_config16(lpc_dev, FUNC_DIS);
reg &= ~(1 << index);
if (!dev->enabled) {
reg |= (1 << index);
}
if (reg != reg_old) {
- pci_write_config16(lpc_dev, 0xf2, reg);
+ pci_write_config16(lpc_dev, FUNC_DIS, reg);
}
}
diff --git a/src/southbridge/intel/i82801ex/i82801ex.h b/src/southbridge/intel/i82801ex/i82801ex.h
index 67fecdd..137b346 100644
--- a/src/southbridge/intel/i82801ex/i82801ex.h
+++ b/src/southbridge/intel/i82801ex/i82801ex.h
@@ -5,11 +5,25 @@
extern void i82801ex_enable(device_t dev);
-#define PCI_DMA_CFG 0x90
-#define SERIRQ_CNTL 0x64
-#define GEN_CNTL 0xd0
-#define GEN_STS 0xd4
-#define RTC_CONF 0xd8
-#define GEN_PMCON_3 0xa4
+#define PCICMD 0x4
+
+#define ACPI_CNTL 0x44
+#define SERIRQ_CNTL 0x64
+#define PCI_DMA_CFG 0x90
+#define GEN_PMCON_3 0xa4
+#define SATA_RD_CFG 0xae
+#define GEN_CNTL 0xd0
+#define GEN_STA 0xd4
+#define RTC_CONF 0xd8
+#define GPIO_CNTL 0x5c
+#define LPC_EN 0xe6
+#define FUNC_DIS 0xf2
+
+/* IDE, SATA */
+#define IDE_TIMP 0x40
+#define IDE_TIMS 0x42
+#define SDMA_CNT 0x48
+#define SDMA_TIM 0x4a
+#define IDE_CONFIG 0x54
#endif /* I82801EX_H */
diff --git a/src/southbridge/intel/i82801ex/ide.c b/src/southbridge/intel/i82801ex/ide.c
index bbab6f1..b67ae7a 100644
--- a/src/southbridge/intel/i82801ex/ide.c
+++ b/src/southbridge/intel/i82801ex/ide.c
@@ -7,18 +7,18 @@
static void ide_init(struct device *dev)
{
- /* Enable IDE devices and timmings */
- pci_write_config16(dev, 0x40, 0x0a307); // IDE0
- pci_write_config16(dev, 0x42, 0x0a307); // IDE1
- pci_write_config8(dev, 0x48, 0x05);
- pci_write_config16(dev, 0x4a, 0x0101);
- pci_write_config16(dev, 0x54, 0x5055);
+ /* Enable IDE devices and timings */
+ pci_write_config16(dev, IDE_TIMP, 0x0a307);
+ pci_write_config16(dev, IDE_TIMS, 0x0a307);
+ pci_write_config8(dev, SDMA_CNT, 0x05);
+ pci_write_config16(dev, SDMA_TIM, 0x0101);
+ pci_write_config16(dev, IDE_CONFIG, 0x5055);
printk(BIOS_DEBUG, "IDE Enabled\n");
}
static void i82801ex_ide_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
- /* This value is also visible in uchi[0-2] and smbus functions */
+ /* This value is also visible in uhci[0-2] and smbus functions */
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
@@ -40,4 +40,3 @@ static const struct pci_driver ide_driver __pci_driver = {
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_82801ER_IDE,
};
-
diff --git a/src/southbridge/intel/i82801ex/lpc.c b/src/southbridge/intel/i82801ex/lpc.c
index 998360c..d57517f 100644
--- a/src/southbridge/intel/i82801ex/lpc.c
+++ b/src/southbridge/intel/i82801ex/lpc.c
@@ -12,33 +12,32 @@
#include <arch/ioapic.h>
#include "i82801ex.h"
-#define ACPI_BAR 0x40
-#define GPIO_BAR 0x58
+#define ACPI_BAR 0x40
+#define GPIO_BAR 0x58
+#define PIRQ_ABCD_OUT 0x60
+#define PIRQ_EFGH_OUT 0x68
-#define NMI_OFF 0
-#define MAINBOARD_POWER_OFF 0
-#define MAINBOARD_POWER_ON 1
+#define NMI_OFF 0
+#define MAINBOARD_POWER_OFF 0
+#define MAINBOARD_POWER_ON 1
#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
#endif
-#define SERIRQ_CNTL 0x64
static void i82801ex_enable_serial_irqs(device_t dev)
{
/* set packet length and toggle silent mode bit */
- pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0 << 0));
- pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(0 << 6)|((21 - 17) << 2)|(0 << 0));
+ pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
+ pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
}
-#define PCI_DMA_CFG 0x90
static void i82801ex_pci_dma_cfg(device_t dev)
{
/* Set PCI DMA CFG to lpc I/F DMA */
pci_write_config16(dev, PCI_DMA_CFG, 0xfcff);
}
-#define LPC_EN 0xe6
static void i82801ex_enable_lpc(device_t dev)
{
/* lpc i/f enable */
@@ -169,10 +168,10 @@ static void i82801ex_pirq_init(device_t dev)
config = dev->chip_info;
if(config->pirq_a_d) {
- pci_write_config32(dev, 0x60, config->pirq_a_d);
+ pci_write_config32(dev, PIRQ_ABCD_OUT, config->pirq_a_d);
}
if(config->pirq_e_h) {
- pci_write_config32(dev, 0x68, config->pirq_e_h);
+ pci_write_config32(dev, PIRQ_EFGH_OUT, config->pirq_e_h);
}
}
@@ -230,25 +229,25 @@ static void enable_hpet(struct device *dev)
*/
dword &= ~(3 << 15); /* clear it */
- dword |= (code<<15);
+ dword |= (code << 15);
pci_write_config32(dev, GEN_CNTL, dword);
- printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address | (code <<12) );
+ printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address | (code << 12) );
}
static void lpc_init(struct device *dev)
{
uint8_t byte;
uint32_t value;
- int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+ int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
/* IO APIC initialization */
- value = pci_read_config32(dev, 0xd0);
- value |= (1 << 8)|(1<<7)|(1<<1);
- pci_write_config32(dev, 0xd0, value);
- value = pci_read_config32(dev, 0xd4);
- value |= (1<<1);
- pci_write_config32(dev, 0xd4, value);
+ value = pci_read_config32(dev, GEN_CNTL);
+ value |= (1 << 8) | (1 << 7) | (1 << 1);
+ pci_write_config32(dev, GEN_CNTL, value);
+ value = pci_read_config32(dev, GEN_STA);
+ value |= (1 << 1);
+ pci_write_config32(dev, GEN_STA, value);
setup_ioapic(IO_APIC_ADDR, 0); // Don't rename IO APIC ID.
i82801ex_enable_serial_irqs(dev);
@@ -258,16 +257,16 @@ static void lpc_init(struct device *dev)
i82801ex_enable_lpc(dev);
/* Clear SATA to non raid */
- pci_write_config8(dev, 0xae, 0x00);
+ pci_write_config8(dev, SATA_RD_CFG, 0x00);
get_option(&pwr_on, "power_on_after_fail");
- byte = pci_read_config8(dev, 0xa4);
+ byte = pci_read_config8(dev, GEN_PMCON_3);
byte &= 0xfe;
if (!pwr_on) {
byte |= 1;
}
- pci_write_config8(dev, 0xa4, byte);
- printk(BIOS_INFO, "set power %s after power fail\n", pwr_on?"on":"off");
+ pci_write_config8(dev, GEN_PMCON_3, byte);
+ printk(BIOS_INFO, "set power %s after power fail\n", pwr_on ? "on" : "off");
/* Set up the PIRQ */
i82801ex_pirq_init(dev);
@@ -282,7 +281,7 @@ static void lpc_init(struct device *dev)
isa_dma_init();
/* Disable IDE (needed when sata is enabled) */
- pci_write_config8(dev, 0xf2, 0x60);
+ pci_write_config8(dev, FUNC_DIS, 0x60);
enable_hpet(dev);
}
@@ -327,14 +326,14 @@ static void i82801ex_lpc_enable_resources(device_t dev)
pci_dev_enable_resources(dev);
/* Enable the ACPI bar */
- acpi_cntl = pci_read_config8(dev, 0x44);
+ acpi_cntl = pci_read_config8(dev, ACPI_CNTL);
acpi_cntl |= (1 << 4);
- pci_write_config8(dev, 0x44, acpi_cntl);
+ pci_write_config8(dev, ACPI_CNTL, acpi_cntl);
/* Enable the GPIO bar */
- gpio_cntl = pci_read_config8(dev, 0x5c);
+ gpio_cntl = pci_read_config8(dev, GPIO_CNTL);
gpio_cntl |= (1 << 4);
- pci_write_config8(dev, 0x5c, gpio_cntl);
+ pci_write_config8(dev, GPIO_CNTL, gpio_cntl);
}
static struct pci_operations lops_pci = {
diff --git a/src/southbridge/intel/i82801ex/pci.c b/src/southbridge/intel/i82801ex/pci.c
index 80c6e49..4c8254e 100644
--- a/src/southbridge/intel/i82801ex/pci.c
+++ b/src/southbridge/intel/i82801ex/pci.c
@@ -5,27 +5,30 @@
#include <device/pci_ops.h>
#include "i82801ex.h"
+#define PCISTS 0x6
+#define SECSTS 0x1e
+
static void pci_init(struct device *dev)
{
uint16_t word;
/* Clear system errors */
- word = pci_read_config16(dev, 0x06);
+ word = pci_read_config16(dev, PCISTS);
word |= 0xf900; /* Clear possible errors */
- pci_write_config16(dev, 0x06, word);
+ pci_write_config16(dev, PCISTS, word);
#if 0
/* System error enable */
uint32_t dword;
- dword = pci_read_config32(dev, 0x04);
- dword |= (1<<8); /* SERR# Enable */
- dword |= (1<<6); /* Parity Error Response */
- pci_write_config32(dev, 0x04, dword);
+ dword = pci_read_config32(dev, PCICMD);
+ dword |= (1 << 8); /* SERR# Enable */
+ dword |= (1 << 6); /* Parity Error Response */
+ pci_write_config32(dev, PCICMD, dword);
#endif
- word = pci_read_config16(dev, 0x1e);
+ word = pci_read_config16(dev, SECSTS);
word |= 0xf800; /* Clear possible errors */
- pci_write_config16(dev, 0x1e, word);
+ pci_write_config16(dev, SECSTS, word);
}
static struct device_operations pci_ops = {
@@ -42,4 +45,3 @@ static const struct pci_driver pci_driver __pci_driver = {
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_82801ER_PCI,
};
-
diff --git a/src/southbridge/intel/i82801ex/sata.c b/src/southbridge/intel/i82801ex/sata.c
index 9b340e9..0ac709f 100644
--- a/src/southbridge/intel/i82801ex/sata.c
+++ b/src/southbridge/intel/i82801ex/sata.c
@@ -5,35 +5,41 @@
#include <device/pci_ops.h>
#include "i82801ex.h"
+#define SATA_PI 0x9
+#define SATA_MAP 0x90
+#define SATA_PCS 0x92
+#define SATA_SRI 0xa0
+#define SATA_SRD 0xa4
+
static void sata_init(struct device *dev)
{
printk(BIOS_DEBUG, "SATA init\n");
/* SATA configuration */
- pci_write_config8(dev, 0x04, 0x07);
- pci_write_config8(dev, 0x09, 0x8f);
+ pci_write_config8(dev, PCICMD, 0x07);
+ pci_write_config8(dev, SATA_PI, 0x8f);
- /* Set timmings */
- pci_write_config16(dev, 0x40, 0x0a307);
- pci_write_config16(dev, 0x42, 0x0a307);
+ /* Set timings */
+ pci_write_config16(dev, IDE_TIMP, 0x0a307);
+ pci_write_config16(dev, IDE_TIMS, 0x0a307);
/* Sync DMA */
- pci_write_config16(dev, 0x48, 0x000f);
- pci_write_config16(dev, 0x4a, 0x1111);
+ pci_write_config16(dev, SDMA_CNT, 0x000f);
+ pci_write_config16(dev, SDMA_TIM, 0x1111);
/* 66 mhz */
- pci_write_config16(dev, 0x54, 0xf00f);
+ pci_write_config16(dev, IDE_CONFIG, 0xf00f);
/* Combine ide - sata configuration */
- pci_write_config8(dev, 0x90, 0x0);
+ pci_write_config8(dev, SATA_MAP, 0x0);
/* port 0 & 1 enable */
- pci_write_config8(dev, 0x92, 0x33);
+ pci_write_config8(dev, SATA_PCS, 0x33);
/* initialize SATA */
- pci_write_config16(dev, 0xa0, 0x0018);
- pci_write_config32(dev, 0xa4, 0x00000264);
- pci_write_config16(dev, 0xa0, 0x0040);
- pci_write_config32(dev, 0xa4, 0x00220043);
+ pci_write_config16(dev, SATA_SRI, 0x0018);
+ pci_write_config32(dev, SATA_SRD, 0x00000264);
+ pci_write_config16(dev, SATA_SRI, 0x0040);
+ pci_write_config32(dev, SATA_SRD, 0x00220043);
}
@@ -57,4 +63,3 @@ static const struct pci_driver sata_driver_nr __pci_driver = {
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_82801EB_SATA,
};
-
diff --git a/src/southbridge/intel/i82801ex/smbus.c b/src/southbridge/intel/i82801ex/smbus.c
index 6bb4899..eb2794c 100644
--- a/src/southbridge/intel/i82801ex/smbus.c
+++ b/src/southbridge/intel/i82801ex/smbus.c
@@ -16,7 +16,7 @@ static int lsmbus_read_byte(device_t dev, u8 address)
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
- res = find_resource(pbus->dev, 0x20);
+ res = find_resource(pbus->dev, SMB_BASE);
return do_smbus_read_byte(res->base, device, address);
}
@@ -46,4 +46,3 @@ static const struct pci_driver smbus_driver __pci_driver = {
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_82801ER_SMB,
};
-
diff --git a/src/southbridge/intel/i82801ex/smbus.h b/src/southbridge/intel/i82801ex/smbus.h
index f330c0a..a9167d2 100644
--- a/src/southbridge/intel/i82801ex/smbus.h
+++ b/src/southbridge/intel/i82801ex/smbus.h
@@ -1,5 +1,10 @@
#include <device/smbus_def.h>
+#define SMBUS_IO_BASE 0xf00
+#define SMB_BASE 0x20
+#define SLV_CMD 0x11
+#define HOSTC 0x40
+
#define SMBHSTSTAT 0x0
#define SMBHSTCTL 0x2
#define SMBHSTCMD 0x3
@@ -102,4 +107,3 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned
}
return byte;
}
-
diff --git a/src/southbridge/intel/i82801ex/uhci.c b/src/southbridge/intel/i82801ex/uhci.c
index 56536b7..c9cf82e 100644
--- a/src/southbridge/intel/i82801ex/uhci.c
+++ b/src/southbridge/intel/i82801ex/uhci.c
@@ -53,4 +53,3 @@ static const struct pci_driver usb3_driver __pci_driver = {
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_82801ER_USB3,
};
-
diff --git a/src/southbridge/intel/i82801ex/watchdog.c b/src/southbridge/intel/i82801ex/watchdog.c
index 26f6644..3f02f61 100644
--- a/src/southbridge/intel/i82801ex/watchdog.c
+++ b/src/southbridge/intel/i82801ex/watchdog.c
@@ -3,6 +3,9 @@
#include <arch/io.h>
#include <device/device.h>
#include <device/pci.h>
+#include "i82801ex.h"
+
+#define PMBASE 0x40
void watchdog_off(void)
{
@@ -12,11 +15,11 @@ void watchdog_off(void)
/* turn off the ICH5 watchdog */
dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
/* Enable I/O space */
- value = pci_read_config16(dev, 0x04);
+ value = pci_read_config16(dev, PCICMD);
value |= (1 << 10);
- pci_write_config16(dev, 0x04, value);
+ pci_write_config16(dev, PCICMD, value);
/* Get TCO base */
- base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60;
+ base = (pci_read_config32(dev, PMBASE) & 0x0fffe) + 0x60;
/* Disable the watchdog timer */
value = inw(base + 0x08);
value |= 1 << 11;
@@ -26,4 +29,3 @@ void watchdog_off(void)
outw(0x0002, base + 0x06);
printk(BIOS_DEBUG, "Watchdog ICH5 disabled\n");
}
-
diff --git a/src/superio/winbond/w83627thg/early_serial.c b/src/superio/winbond/w83627thg/early_serial.c
index 559e982..b80e514 100644
--- a/src/superio/winbond/w83627thg/early_serial.c
+++ b/src/superio/winbond/w83627thg/early_serial.c
@@ -45,3 +45,14 @@ static void inline w83627thg_enable_serial(device_t dev, u16 iobase)
pnp_set_enable(dev, 1);
pnp_exit_ext_func_mode(dev);
}
+
+#ifndef __ROMCC__
+void w83627thg_set_clksel_48(device_t dev) {
+ u8 reg8;
+ pnp_enter_ext_func_mode(dev);
+ reg8 = pnp_read_config(dev, 0x24);
+ reg8 |= (1 << 6); /* Set CLKSEL (clock input on pin 1) to 48MHz. */
+ pnp_write_config(dev, 0x24, reg8);
+ pnp_exit_ext_func_mode(dev);
+}
+#endif
diff --git a/src/superio/winbond/w83627thg/w83627thg.h b/src/superio/winbond/w83627thg/w83627thg.h
index 73be544..99ff565 100644
--- a/src/superio/winbond/w83627thg/w83627thg.h
+++ b/src/superio/winbond/w83627thg/w83627thg.h
@@ -34,4 +34,6 @@
#define W83627THG_ACPI 10
#define W83627THG_HWM 11 /* Hardware monitor */
+void w83627thg_set_clksel_48(device_t dev);
+
#endif
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