[coreboot] New patch to review for coreboot: 0b141d5 move function from header file to .c file

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/429

-gerrit

commit 0b141d5dc0d97bbbedd514d19255d7eba096c645
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Tue Nov 8 09:58:29 2011 -0800

    move function from header file to .c file
    
    http://review.coreboot.org/#change,378 introduced a function in k8x8xx.h
    move this function to ctrl.c and add a prototype to the header file instead.
    
    Change-Id: I0919ffb2030c53669b95f58b649d4a160f660923
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/southbridge/via/k8t890/ctrl.c   |   13 +++++++++++++
 src/southbridge/via/k8t890/k8x8xx.h |   16 ++--------------
 2 files changed, 15 insertions(+), 14 deletions(-)

diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c
index d68e03e..5fa6686 100644
--- a/src/southbridge/via/k8t890/ctrl.c
+++ b/src/southbridge/via/k8t890/ctrl.c
@@ -25,6 +25,19 @@
 #include <console/console.h>
 #include "k8x8xx.h"
 
+void k8x8xx_vt8237_mirrored_regs_fill(struct k8x8xx_vt8237_mirrored_regs *regs)
+	msr_t msr;
+
+	regs->rom_shadow_ctrl_pg_c = 0xff;
+	regs->rom_shadow_ctrl_pg_d = 0xff;
+	regs->rom_shadow_ctrl_pg_e_memhole_smi_decoding = 0xff;
+	regs->rom_shadow_ctrl_pg_f_memhole = 0x30;
+	regs->smm_apic_decoding = 0x19;
+	msr = rdmsr(TOP_MEM);
+	regs->shadow_mem_ctrl = msr.lo >> 24;
+	regs->low_top_address = msr.lo >> 16;
+}
+
 /* We support here K8M890/K8T890 and VT8237R PCI1/Vlink which setup is not in separate
  * PCI device 0:11.7, but it is mapped to PCI 0:0.7 (0x70-0x7c for PCI1)
  */
diff --git a/src/southbridge/via/k8t890/k8x8xx.h b/src/southbridge/via/k8t890/k8x8xx.h
index c61c984..908940a 100644
--- a/src/southbridge/via/k8t890/k8x8xx.h
+++ b/src/southbridge/via/k8t890/k8x8xx.h
@@ -28,6 +28,7 @@
 #endif
 #include "k8t890.h"
 
+#ifndef __PRE_RAM__
 struct k8x8xx_vt8237_mirrored_regs {
 	u16 low_top_address;
 	u8 rom_shadow_ctrl_pg_c,
@@ -38,20 +39,7 @@ struct k8x8xx_vt8237_mirrored_regs {
 		shadow_mem_ctrl;
 };
 
-static inline void k8x8xx_vt8237_mirrored_regs_fill(struct k8x8xx_vt8237_mirrored_regs *regs){
-	msr_t msr;
-
-	regs->rom_shadow_ctrl_pg_c = 0xff;
-	regs->rom_shadow_ctrl_pg_d = 0xff;
-	regs->rom_shadow_ctrl_pg_e_memhole_smi_decoding = 0xff;
-	regs->rom_shadow_ctrl_pg_f_memhole = 0x30;
-	regs->smm_apic_decoding = 0x19;
-	msr = rdmsr(TOP_MEM);
-	regs->shadow_mem_ctrl = msr.lo >> 24;
-	regs->low_top_address = msr.lo >> 16;
-}
-
-#ifndef __PRE_RAM__
+void k8x8xx_vt8237_mirrored_regs_fill(struct k8x8xx_vt8237_mirrored_regs *regs);
 void k8x8xx_vt8237r_cfg(struct device *, struct device *);
 #endif