[coreboot] New patch to review for coreboot: 8b99e13 Fix compilation of AMD GX2 northbridge code with gcc 4.6
Stefan Reinauer (stefan.reinauer@coreboot.org)
gerrit at coreboot.org
Fri Oct 14 02:27:59 CEST 2011
Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/267
-gerrit
commit 8b99e131dab9680feb84d4a1e126b58ea12aa8d0
Author: Stefan Reinauer <reinauer at google.com>
Date: Thu Oct 13 17:26:10 2011 -0700
Fix compilation of AMD GX2 northbridge code with gcc 4.6
Change-Id: I71d96b7cd36dd99a3590ec311c11f67f13012e68
Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
src/northbridge/amd/gx2/northbridgeinit.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c
index fd8d3f9..e4aaa8b 100644
--- a/src/northbridge/amd/gx2/northbridgeinit.c
+++ b/src/northbridge/amd/gx2/northbridgeinit.c
@@ -485,7 +485,7 @@ performance:
static void GeodeLinkPriority(void)
{
- msr_t msr;
+ msr_t msr = { 0, 0 };
struct msrinit *prio = GeodeLinkPriorityTable;
int i;
@@ -526,7 +526,7 @@ static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo)
/* ok this is whacky bit translation time. */
int bit;
uint8_t shadowByte;
- msr_t msr;
+ msr_t msr = { 0, 0 };
shadowByte = (uint8_t) (shadowLo >> 16);
/* load up D000 settings in edx. */
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