[coreboot] New patch to review for coreboot: cfb1039 Remove ROMCC, re-define CACHE_AS_RAM
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Mon Oct 24 11:43:56 CEST 2011
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/332
-gerrit
commit cfb10391c1d65b358fd425a6a1a7231d55c7b039
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Sun Oct 23 20:27:50 2011 +0300
Remove ROMCC, re-define CACHE_AS_RAM
In mainboard Kconfig's
rename NO_TINY_BOOTBLOCK to NO_CACHE_AS_RAM
rename MAYBE_TINY_BOOTBLOCK to MAYBE_CACHE_AS_RAM
remove ROMCC
In cpu Kconfig's
remove CACHE_AS_RAM
New definition at arch-level Kconfig is:
CACHE_AS_RAM = 1
if (NO_CACHE_AS_RAM) // from mainboard
CACHE_AS_RAM = 0
else if (MAYBE_CACHE_AS_RAM) // from mainboard
CACHE_AS_RAM = [ menuconfig expert option ]
Currently unconverted boards will go through cycle:
NO_C-A-R -> MAYBE_C-A-R -> (empty).
Conditionally include cpu's cache_as_ram.inc for PGA604.
This allows converting one of these mainboards to Cache-As-Ram,
while others remain in their functional NO_CACHE_AS_RAM state.
If you require positive feedback for conversions to CAR, before
accepting them in the master, you could not merge the first one
until the last one with same socket is confirmed.
Change-Id: I32cf1d2de5ffdfe9bb0b448676b1607aaabbffab
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/arch/x86/Kconfig | 31 +++++++-----------------
src/arch/x86/Makefile.inc | 11 ++++++--
src/cpu/Kconfig | 4 ---
src/cpu/amd/car/cache_as_ram.inc | 2 +-
src/cpu/amd/model_gx2/Kconfig | 1 -
src/cpu/amd/model_gx2/syspreinit.c | 2 +-
src/cpu/amd/model_lx/Kconfig | 1 -
src/cpu/amd/model_lx/syspreinit.c | 2 +-
src/cpu/amd/socket_754/Kconfig | 1 -
src/cpu/amd/socket_939/Kconfig | 1 -
src/cpu/amd/socket_940/Kconfig | 1 -
src/cpu/amd/socket_AM2/Kconfig | 1 -
src/cpu/amd/socket_AM2r2/Kconfig | 1 -
src/cpu/amd/socket_AM3/Kconfig | 1 -
src/cpu/amd/socket_ASB2/Kconfig | 1 -
src/cpu/amd/socket_C32/Kconfig | 1 -
src/cpu/amd/socket_F/Kconfig | 1 -
src/cpu/amd/socket_F_1207/Kconfig | 1 -
src/cpu/amd/socket_S1G1/Kconfig | 1 -
src/cpu/intel/car/cache_as_ram.inc | 2 +-
src/cpu/intel/model_106cx/cache_as_ram.inc | 2 +-
src/cpu/intel/model_6ex/cache_as_ram.inc | 2 +-
src/cpu/intel/model_6fx/cache_as_ram.inc | 2 +-
src/cpu/intel/slot_1/Kconfig | 1 -
src/cpu/intel/socket_441/Kconfig | 1 -
src/cpu/intel/socket_FC_PGA370/Kconfig | 2 -
src/cpu/intel/socket_PGA370/Kconfig | 1 -
src/cpu/intel/socket_mFCBGA479/Kconfig | 1 -
src/cpu/intel/socket_mFCPGA478/Kconfig | 1 -
src/cpu/intel/socket_mPGA479M/Kconfig | 1 -
src/cpu/intel/socket_mPGA604/Kconfig | 1 -
src/cpu/intel/socket_mPGA604/Makefile.inc | 2 +-
src/cpu/via/car/cache_as_ram.inc | 2 +-
src/cpu/via/model_c7/Kconfig | 1 -
src/cpu/x86/mtrr/earlymtrr.c | 2 +-
src/include/assert.h | 2 +-
src/include/cpu/x86/bist.h | 2 +-
src/include/cpu/x86/mtrr.h | 2 +-
src/lib/Makefile.inc | 2 +-
src/lib/generic_sdram.c | 2 +-
src/lib/ramtest.c | 24 +++++++++---------
src/mainboard/aaeon/pfm-540i_revb/Kconfig | 2 +-
src/mainboard/advantech/pcm-5820/Kconfig | 3 +-
src/mainboard/amd/db800/Kconfig | 2 +-
src/mainboard/amd/norwich/Kconfig | 2 +-
src/mainboard/amd/rumba/Kconfig | 2 +-
src/mainboard/artecgroup/dbe61/Kconfig | 2 +-
src/mainboard/asi/mb_5blgp/Kconfig | 3 +-
src/mainboard/asi/mb_5blmp/Kconfig | 3 +-
src/mainboard/asus/a8v-e_deluxe/Kconfig | 2 +-
src/mainboard/asus/a8v-e_se/Kconfig | 2 +-
src/mainboard/asus/mew-am/Kconfig | 2 +-
src/mainboard/asus/mew-vm/Kconfig | 2 +-
src/mainboard/axus/tc320/Kconfig | 3 +-
src/mainboard/bcom/winnet100/Kconfig | 3 +-
src/mainboard/bcom/winnetp680/Kconfig | 2 +-
src/mainboard/dell/s1850/Kconfig | 3 +-
src/mainboard/digitallogic/msm586seg/Kconfig | 3 +-
src/mainboard/digitallogic/msm800sev/Kconfig | 2 +-
src/mainboard/eaglelion/5bcm/Kconfig | 3 +-
src/mainboard/ecs/p6iwp-fe/Kconfig | 2 +-
src/mainboard/emulation/qemu-x86/Kconfig | 1 -
src/mainboard/hp/e_vectra_p2706t/Kconfig | 2 +-
src/mainboard/iei/juki-511p/Kconfig | 3 +-
src/mainboard/iei/nova4899r/Kconfig | 3 +-
src/mainboard/iei/pcisa-lx-800-r10/Kconfig | 2 +-
src/mainboard/intel/d810e2cb/Kconfig | 1 -
src/mainboard/intel/eagleheights/Kconfig | 2 +-
src/mainboard/intel/jarrell/Kconfig | 3 +-
src/mainboard/intel/mtarvon/Kconfig | 2 +-
src/mainboard/intel/truxton/Kconfig | 3 +-
src/mainboard/intel/xe7501devkit/Kconfig | 3 +-
src/mainboard/jetway/j7f24/Kconfig | 2 +-
src/mainboard/lenovo/x60/Kconfig | 2 +-
src/mainboard/lippert/frontrunner/Kconfig | 2 +-
src/mainboard/lippert/hurricane-lx/Kconfig | 2 +-
src/mainboard/lippert/literunner-lx/Kconfig | 2 +-
src/mainboard/lippert/roadrunner-lx/Kconfig | 2 +-
src/mainboard/lippert/spacerunner-lx/Kconfig | 2 +-
src/mainboard/mitac/6513wu/Kconfig | 2 +-
src/mainboard/msi/ms6178/Kconfig | 2 +-
src/mainboard/nec/powermate2000/Kconfig | 2 +-
src/mainboard/pcengines/alix1c/Kconfig | 2 +-
src/mainboard/pcengines/alix2d/Kconfig | 2 +-
src/mainboard/roda/rk886ex/Kconfig | 2 +-
src/mainboard/supermicro/x6dai_g/Kconfig | 3 +-
src/mainboard/supermicro/x6dhe_g/Kconfig | 3 +-
src/mainboard/supermicro/x6dhe_g2/Kconfig | 3 +-
src/mainboard/supermicro/x6dhr_ig/Kconfig | 3 +-
src/mainboard/supermicro/x6dhr_ig2/Kconfig | 3 +-
src/mainboard/technologic/ts5300/Kconfig | 3 +-
src/mainboard/televideo/tc7020/Kconfig | 3 +-
src/mainboard/traverse/geos/Kconfig | 2 +-
src/mainboard/tyan/s2735/Kconfig | 2 +-
src/mainboard/via/epia-cn/Kconfig | 2 +-
src/mainboard/via/epia-m/Kconfig | 3 +-
src/mainboard/via/epia-m700/Kconfig | 2 +-
src/mainboard/via/epia-n/Kconfig | 3 +-
src/mainboard/via/epia/Kconfig | 3 +-
src/mainboard/via/pc2500e/Kconfig | 2 +-
src/mainboard/winent/pl6064/Kconfig | 2 +-
src/mainboard/wyse/s50/Kconfig | 2 +-
src/northbridge/intel/e7501/debug.c | 32 +++++++++++++-------------
src/northbridge/intel/i3100/raminit.c | 2 +-
src/southbridge/intel/i82801cx/early_smbus.c | 1 -
105 files changed, 120 insertions(+), 181 deletions(-)
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index 3544bef..01c98d3 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -30,11 +30,11 @@ config MAX_REBOOT_CNT
int
default 3
-config NO_TINY_BOOTBLOCK
+config NO_CACHE_AS_RAM
bool
default n
-config MAYBE_TINY_BOOTBLOCK
+config MAYBE_CACHE_AS_RAM
bool
default n
@@ -42,31 +42,23 @@ config CACHE_AS_RAM_OVERRIDE
bool "Enable Cache-As-Ram (experimental)"
default n
depends on EXPERT
- depends on MAYBE_TINY_BOOTBLOCK
+ depends on MAYBE_CACHE_AS_RAM
help
Your mainboard has been converted to use Cache-As-Ram, but
we have not yet received any confirmation that it actually
works for this setup.
Beware: This may leave your system non-bootable!
-config TINY_BOOTBLOCK
+config CACHE_AS_RAM
bool
default y if CACHE_AS_RAM_OVERRIDE
- default n if NO_TINY_BOOTBLOCK
- default n if MAYBE_TINY_BOOTBLOCK
- default y
-
-# Really a synonym for TINY_BOOTBLOCK now
-config USE_CACHE_AS_RAM
- bool
- default y if CACHE_AS_RAM_OVERRIDE
- default n if NO_TINY_BOOTBLOCK
- default n if MAYBE_TINY_BOOTBLOCK
+ default n if NO_CACHE_AS_RAM
+ default n if MAYBE_CACHE_AS_RAM
default y
config BIG_BOOTBLOCK
bool
- default n if TINY_BOOTBLOCK
+ default n if CACHE_AS_RAM
default y
# We had to rename the choice options under arch/ because otherwise
@@ -75,7 +67,7 @@ config BIG_BOOTBLOCK
choice
prompt "Bootblock behaviour"
default X86_BOOTBLOCK_SIMPLE
- depends on TINY_BOOTBLOCK
+ depends on CACHE_AS_RAM
config X86_BOOTBLOCK_SIMPLE
bool "Always load fallback"
@@ -93,18 +85,13 @@ config BOOTBLOCK_SOURCE
config UPDATE_IMAGE
bool "Update existing coreboot.rom image"
default n
- depends on TINY_BOOTBLOCK
+ depends on CACHE_AS_RAM
help
If this option is enabled, no new coreboot.rom file
is created. Instead it is expected that there already
is a suitable file for further processing.
The bootblock will not be modified.
-config ROMCC
- bool
- default n if USE_CACHE_AS_RAM
- default y
-
config PC80_SYSTEM
bool
default y
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 7e71518..9659ace 100755
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -198,7 +198,12 @@ ifeq ($(CONFIG_SSE),y)
crt0s += $(src)/cpu/x86/sse_enable.inc
endif
+
+# When some mainboards with a specific socket have been converted
+# to cache-as-ram, but others haven't, cache_as_ram.inc is
+# included only conditionally
crt0s += $(cpu_incs)
+crt0s += $(cpu_incs-y)
ifeq ($(CONFIG_LLSHELL),y)
crt0s += $(src)/arch/x86/llshell/llshell.inc
@@ -218,11 +223,11 @@ crt0s += $(chipset_bootblock_inc)
ldscripts += $(chipset_bootblock_lds)
endif
-ifeq ($(CONFIG_ROMCC),y)
+ifeq ($(CONFIG_CACHE_AS_RAM),n)
crt0s += $(src)/arch/x86/init/crt0_romcc_epilogue.inc
endif
-ifeq ($(CONFIG_ROMCC),y)
+ifeq ($(CONFIG_CACHE_AS_RAM),n)
ROMCCFLAGS ?= -mcpu=p2 -O2
$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h
@@ -278,7 +283,7 @@ ifeq ($(CONFIG_HAVE_BUS_CONFIG),y)
ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/get_bus_conf.c
endif
-ifeq ($(CONFIG_TINY_BOOTBLOCK),y)
+ifeq ($(CONFIG_BIG_BOOTBLOCK),n)
include $(src)/arch/x86/Makefile.bootblock.inc
else
include $(src)/arch/x86/Makefile.bigbootblock.inc
diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig
index 6e65186..3edc10b 100644
--- a/src/cpu/Kconfig
+++ b/src/cpu/Kconfig
@@ -5,10 +5,6 @@ source src/cpu/intel/Kconfig
source src/cpu/via/Kconfig
source src/cpu/x86/Kconfig
-config CACHE_AS_RAM
- bool
- default !ROMCC
-
config DCACHE_RAM_BASE
hex
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index 4899296..0f3f464 100644
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -281,7 +281,7 @@ clear_fixed_var_mtrr_out:
#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
-#if CONFIG_TINY_BOOTBLOCK
+#if CONFIG_CACHE_AS_RAM
#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
#else
#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
diff --git a/src/cpu/amd/model_gx2/Kconfig b/src/cpu/amd/model_gx2/Kconfig
index 4515a71..deeffbb 100644
--- a/src/cpu/amd/model_gx2/Kconfig
+++ b/src/cpu/amd/model_gx2/Kconfig
@@ -24,7 +24,6 @@ if CPU_AMD_GX2
config CPU_SPECIFIC_OPTIONS
def_bool y
- select CACHE_AS_RAM
config DCACHE_RAM_BASE
hex
diff --git a/src/cpu/amd/model_gx2/syspreinit.c b/src/cpu/amd/model_gx2/syspreinit.c
index 4a6a837..8140348 100644
--- a/src/cpu/amd/model_gx2/syspreinit.c
+++ b/src/cpu/amd/model_gx2/syspreinit.c
@@ -13,7 +13,7 @@ static void StartTimer1(void)
void SystemPreInit(void)
{
/* they want a jump ... */
-#if !CONFIG_USE_CACHE_AS_RAM
+#if !CONFIG_CACHE_AS_RAM
__asm__ __volatile__("jmp .+2\ninvd\njmp .+2\n");
#endif
StartTimer1();
diff --git a/src/cpu/amd/model_lx/Kconfig b/src/cpu/amd/model_lx/Kconfig
index 742ef69..b2bf944 100644
--- a/src/cpu/amd/model_lx/Kconfig
+++ b/src/cpu/amd/model_lx/Kconfig
@@ -5,7 +5,6 @@ if CPU_AMD_LX
config CPU_SPECIFIC_OPTIONS
def_bool y
- select CACHE_AS_RAM
config DCACHE_RAM_BASE
hex
diff --git a/src/cpu/amd/model_lx/syspreinit.c b/src/cpu/amd/model_lx/syspreinit.c
index fcedfe2..35c54fb 100644
--- a/src/cpu/amd/model_lx/syspreinit.c
+++ b/src/cpu/amd/model_lx/syspreinit.c
@@ -39,7 +39,7 @@ void SystemPreInit(void)
{
/* they want a jump ... */
-#if !CONFIG_USE_CACHE_AS_RAM
+#if !CONFIG_CACHE_AS_RAM
__asm__ __volatile__("jmp .+2\ninvd\njmp .+2\n");
#endif
StartTimer1();
diff --git a/src/cpu/amd/socket_754/Kconfig b/src/cpu/amd/socket_754/Kconfig
index 7a353a3..4166754 100644
--- a/src/cpu/amd/socket_754/Kconfig
+++ b/src/cpu/amd/socket_754/Kconfig
@@ -6,7 +6,6 @@ if CPU_AMD_SOCKET_754
config SOCKET_SPECIFIC_OPTIONS
def_bool y
select CPU_AMD_MODEL_FXX
- select CACHE_AS_RAM
config CPU_ADDR_BITS
int
diff --git a/src/cpu/amd/socket_939/Kconfig b/src/cpu/amd/socket_939/Kconfig
index 4546297..ff36a84 100644
--- a/src/cpu/amd/socket_939/Kconfig
+++ b/src/cpu/amd/socket_939/Kconfig
@@ -1,5 +1,4 @@
config CPU_AMD_SOCKET_939
bool
select CPU_AMD_MODEL_FXX
- select CACHE_AS_RAM
diff --git a/src/cpu/amd/socket_940/Kconfig b/src/cpu/amd/socket_940/Kconfig
index 1dbf652..603aa03 100644
--- a/src/cpu/amd/socket_940/Kconfig
+++ b/src/cpu/amd/socket_940/Kconfig
@@ -7,7 +7,6 @@ config SOCKET_SPECIFIC_OPTIONS
def_bool y
select K8_HT_FREQ_1G_SUPPORT
select CPU_AMD_MODEL_FXX
- select CACHE_AS_RAM
config CPU_ADDR_BITS
int
diff --git a/src/cpu/amd/socket_AM2/Kconfig b/src/cpu/amd/socket_AM2/Kconfig
index 6849154..3663061 100644
--- a/src/cpu/amd/socket_AM2/Kconfig
+++ b/src/cpu/amd/socket_AM2/Kconfig
@@ -4,7 +4,6 @@ config CPU_AMD_SOCKET_AM2
# Opteron K8 1G HT support
select K8_HT_FREQ_1G_SUPPORT
select CPU_AMD_MODEL_FXX
- select CACHE_AS_RAM
config CPU_SOCKET_TYPE
hex
diff --git a/src/cpu/amd/socket_AM2r2/Kconfig b/src/cpu/amd/socket_AM2r2/Kconfig
index c7cff14..9435a55 100644
--- a/src/cpu/amd/socket_AM2r2/Kconfig
+++ b/src/cpu/amd/socket_AM2r2/Kconfig
@@ -3,7 +3,6 @@ config CPU_AMD_SOCKET_AM2R2
select CPU_AMD_MODEL_10XXX
select HT3_SUPPORT
select PCI_IO_CFG_EXT
- select CACHE_AS_RAM
config CPU_SOCKET_TYPE
hex
diff --git a/src/cpu/amd/socket_AM3/Kconfig b/src/cpu/amd/socket_AM3/Kconfig
index c718ead..2979cbe 100644
--- a/src/cpu/amd/socket_AM3/Kconfig
+++ b/src/cpu/amd/socket_AM3/Kconfig
@@ -3,7 +3,6 @@ config CPU_AMD_SOCKET_AM3
select CPU_AMD_MODEL_10XXX
select HT3_SUPPORT
select PCI_IO_CFG_EXT
- select CACHE_AS_RAM
config CPU_SOCKET_TYPE
hex
diff --git a/src/cpu/amd/socket_ASB2/Kconfig b/src/cpu/amd/socket_ASB2/Kconfig
index 964a59f..7b8857f 100644
--- a/src/cpu/amd/socket_ASB2/Kconfig
+++ b/src/cpu/amd/socket_ASB2/Kconfig
@@ -3,7 +3,6 @@ config CPU_AMD_SOCKET_ASB2
select CPU_AMD_MODEL_10XXX
select HT3_SUPPORT
select PCI_IO_CFG_EXT
- select CACHE_AS_RAM
config CPU_SOCKET_TYPE
hex
diff --git a/src/cpu/amd/socket_C32/Kconfig b/src/cpu/amd/socket_C32/Kconfig
index 7ffa374..70578c2 100644
--- a/src/cpu/amd/socket_C32/Kconfig
+++ b/src/cpu/amd/socket_C32/Kconfig
@@ -3,7 +3,6 @@ config CPU_AMD_SOCKET_C32
select CPU_AMD_MODEL_10XXX
select HT3_SUPPORT
select PCI_IO_CFG_EXT
- select CACHE_AS_RAM
config CPU_SOCKET_TYPE
hex
diff --git a/src/cpu/amd/socket_F/Kconfig b/src/cpu/amd/socket_F/Kconfig
index 8514369..f32e690 100644
--- a/src/cpu/amd/socket_F/Kconfig
+++ b/src/cpu/amd/socket_F/Kconfig
@@ -3,7 +3,6 @@ config CPU_AMD_SOCKET_F
select K8_REV_F_SUPPORT
select K8_HT_FREQ_1G_SUPPORT
select CPU_AMD_MODEL_FXX
- select CACHE_AS_RAM
config CPU_SOCKET_TYPE
hex
diff --git a/src/cpu/amd/socket_F_1207/Kconfig b/src/cpu/amd/socket_F_1207/Kconfig
index 224059a..959fea5 100644
--- a/src/cpu/amd/socket_F_1207/Kconfig
+++ b/src/cpu/amd/socket_F_1207/Kconfig
@@ -2,7 +2,6 @@ config CPU_AMD_SOCKET_F_1207
bool
select CPU_AMD_MODEL_10XXX
select PCI_IO_CFG_EXT
- select CACHE_AS_RAM
config CPU_SOCKET_TYPE
hex
diff --git a/src/cpu/amd/socket_S1G1/Kconfig b/src/cpu/amd/socket_S1G1/Kconfig
index 284c181..b96613c 100644
--- a/src/cpu/amd/socket_S1G1/Kconfig
+++ b/src/cpu/amd/socket_S1G1/Kconfig
@@ -8,7 +8,6 @@ config SOCKET_SPECIFIC_OPTIONS
select K8_REV_F_SUPPORT
select K8_HT_FREQ_1G_SUPPORT
select CPU_AMD_MODEL_FXX
- select CACHE_AS_RAM
config CPU_SOCKET_TYPE
hex
diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc
index 2310d7d..de98719 100644
--- a/src/cpu/intel/car/cache_as_ram.inc
+++ b/src/cpu/intel/car/cache_as_ram.inc
@@ -231,7 +231,7 @@ clear_fixed_var_mtrr_out:
#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
-#if CONFIG_TINY_BOOTBLOCK
+#if CONFIG_CACHE_AS_RAM
#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
#else
#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc
index da14db2..bbb4856 100644
--- a/src/cpu/intel/model_106cx/cache_as_ram.inc
+++ b/src/cpu/intel/model_106cx/cache_as_ram.inc
@@ -102,7 +102,7 @@ clear_mtrrs:
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
-#if CONFIG_TINY_BOOTBLOCK
+#if CONFIG_CACHE_AS_RAM
#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
#else
#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index 02de5ab..5dac9ca 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -102,7 +102,7 @@ clear_mtrrs:
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
-#if CONFIG_TINY_BOOTBLOCK
+#if CONFIG_CACHE_AS_RAM
#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
#else
#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc
index 2f13d35..8930df2 100644
--- a/src/cpu/intel/model_6fx/cache_as_ram.inc
+++ b/src/cpu/intel/model_6fx/cache_as_ram.inc
@@ -109,7 +109,7 @@ clear_mtrrs:
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
-#if CONFIG_TINY_BOOTBLOCK
+#if CONFIG_CACHE_AS_RAM
#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
#else
#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig
index 45c94ac..ce43525 100644
--- a/src/cpu/intel/slot_1/Kconfig
+++ b/src/cpu/intel/slot_1/Kconfig
@@ -19,7 +19,6 @@
config CPU_INTEL_SLOT_1
bool
- select CACHE_AS_RAM
config DCACHE_RAM_SIZE
hex
diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig
index f73c8a9..2269190 100644
--- a/src/cpu/intel/socket_441/Kconfig
+++ b/src/cpu/intel/socket_441/Kconfig
@@ -8,7 +8,6 @@ config SOCKET_SPECIFIC_OPTIONS # dummy
select CPU_INTEL_MODEL_106CX
select MMX
select SSE
- select CACHE_AS_RAM
config DCACHE_RAM_BASE
hex
diff --git a/src/cpu/intel/socket_FC_PGA370/Kconfig b/src/cpu/intel/socket_FC_PGA370/Kconfig
index 88541a8..a97d9c3 100644
--- a/src/cpu/intel/socket_FC_PGA370/Kconfig
+++ b/src/cpu/intel/socket_FC_PGA370/Kconfig
@@ -23,8 +23,6 @@ config CPU_INTEL_SOCKET_FC_PGA370
select CPU_INTEL_MODEL_68X
select MMX
select SSE
- select CACHE_AS_RAM
- select TINY_BOOTBLOCK
config DCACHE_RAM_SIZE
hex
diff --git a/src/cpu/intel/socket_PGA370/Kconfig b/src/cpu/intel/socket_PGA370/Kconfig
index adfb5f3..6993e62 100644
--- a/src/cpu/intel/socket_PGA370/Kconfig
+++ b/src/cpu/intel/socket_PGA370/Kconfig
@@ -21,7 +21,6 @@ config CPU_INTEL_SOCKET_PGA370
bool
select MMX
select UDELAY_TSC
- select CACHE_AS_RAM
if CPU_INTEL_SOCKET_PGA370
diff --git a/src/cpu/intel/socket_mFCBGA479/Kconfig b/src/cpu/intel/socket_mFCBGA479/Kconfig
index d2ceabe..5576623 100644
--- a/src/cpu/intel/socket_mFCBGA479/Kconfig
+++ b/src/cpu/intel/socket_mFCBGA479/Kconfig
@@ -3,4 +3,3 @@ config CPU_INTEL_SOCKET_MFCBGA479
select CPU_INTEL_MODEL_6BX
select MMX
select SSE
- select CACHE_AS_RAM
diff --git a/src/cpu/intel/socket_mFCPGA478/Kconfig b/src/cpu/intel/socket_mFCPGA478/Kconfig
index 3f39303..566d482 100644
--- a/src/cpu/intel/socket_mFCPGA478/Kconfig
+++ b/src/cpu/intel/socket_mFCPGA478/Kconfig
@@ -9,7 +9,6 @@ config SOCKET_SPECIFIC_OPTIONS # dummy
select CPU_INTEL_CORE2
select MMX
select SSE
- select CACHE_AS_RAM
config DCACHE_RAM_BASE
hex
diff --git a/src/cpu/intel/socket_mPGA479M/Kconfig b/src/cpu/intel/socket_mPGA479M/Kconfig
index 4be39b5..8598eaf 100644
--- a/src/cpu/intel/socket_mPGA479M/Kconfig
+++ b/src/cpu/intel/socket_mPGA479M/Kconfig
@@ -6,4 +6,3 @@ config CPU_INTEL_SOCKET_MPGA479M
select CPU_INTEL_MODEL_F2X
select MMX
select SSE
- select CACHE_AS_RAM
diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig
index 61e8637..2fc27cf 100644
--- a/src/cpu/intel/socket_mPGA604/Kconfig
+++ b/src/cpu/intel/socket_mPGA604/Kconfig
@@ -6,7 +6,6 @@ config CPU_INTEL_SOCKET_MPGA604
select MMX
select SSE
select UDELAY_TSC
- select CACHE_AS_RAM
# mPGA604 are usually Intel Netburst CPUs which should have SSE2
# but the ramtest.c code on the Dell S1850 seems to choke on
diff --git a/src/cpu/intel/socket_mPGA604/Makefile.inc b/src/cpu/intel/socket_mPGA604/Makefile.inc
index ad88892..80ae79f 100644
--- a/src/cpu/intel/socket_mPGA604/Makefile.inc
+++ b/src/cpu/intel/socket_mPGA604/Makefile.inc
@@ -10,5 +10,5 @@ subdirs-y += ../../x86/smm
subdirs-y += ../microcode
subdirs-y += ../hyperthreading
-cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc
+cpu_incs-$(CONFIG_CACHE_AS_RAM) += $(src)/cpu/intel/car/cache_as_ram.inc
diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc
index 20b3220..23bd78d 100644
--- a/src/cpu/via/car/cache_as_ram.inc
+++ b/src/cpu/via/car/cache_as_ram.inc
@@ -110,7 +110,7 @@ clear_fixed_var_mtrr_out:
movl $(~(CacheSize - 1) | MTRRphysMaskValid), %eax
wrmsr
-#if CONFIG_TINY_BOOTBLOCK
+#if CONFIG_CACHE_AS_RAM
#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
#else
#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
diff --git a/src/cpu/via/model_c7/Kconfig b/src/cpu/via/model_c7/Kconfig
index 8e6f0e8..25aa43a 100644
--- a/src/cpu/via/model_c7/Kconfig
+++ b/src/cpu/via/model_c7/Kconfig
@@ -8,7 +8,6 @@ config CPU_SPECFIC_OPTIONS
select UDELAY_TSC
select MMX
select SSE2
- select CACHE_AS_RAM
config DCACHE_RAM_BASE
hex
diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c
index 85cbfb5..dcfcccd 100644
--- a/src/cpu/x86/mtrr/earlymtrr.c
+++ b/src/cpu/x86/mtrr/earlymtrr.c
@@ -20,7 +20,7 @@ static void set_var_mtrr(
wrmsr(MTRRphysMask_MSR(reg), maskm);
}
-#if !defined(CONFIG_USE_CACHE_AS_RAM) || (CONFIG_USE_CACHE_AS_RAM == 0)
+#if !defined(CONFIG_CACHE_AS_RAM) || (CONFIG_CACHE_AS_RAM == 0)
static void cache_lbmem(int type)
{
/* Enable caching for 0 - 1MB using variable mtrr */
diff --git a/src/include/assert.h b/src/include/assert.h
index 98cdfea..346e769 100644
--- a/src/include/assert.h
+++ b/src/include/assert.h
@@ -20,7 +20,7 @@
#ifndef __ASSERT_H__
#define __ASSERT_H__
-#if defined(__PRE_RAM__) && !CONFIG_USE_CACHE_AS_RAM
+#if defined(__PRE_RAM__) && !CONFIG_CACHE_AS_RAM
/* ROMCC versions */
#define ASSERT(x) { \
diff --git a/src/include/cpu/x86/bist.h b/src/include/cpu/x86/bist.h
index b4f2d2d..d1646bf 100644
--- a/src/include/cpu/x86/bist.h
+++ b/src/include/cpu/x86/bist.h
@@ -4,7 +4,7 @@
static void report_bist_failure(u32 bist)
{
if (bist != 0) {
-#if CONFIG_USE_CACHE_AS_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_EMERG, "BIST failed: %08x", bist);
#else
print_emerg("BIST failed: ");
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 44a2223..5413366 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -69,7 +69,7 @@ void x86_setup_fixed_mtrrs(void);
#if !defined (__ASSEMBLER__)
#if defined(CONFIG_XIP_ROM_SIZE)
-# if CONFIG_TINY_BOOTBLOCK
+# if CONFIG_CACHE_AS_RAM
extern unsigned long AUTO_XIP_ROM_BASE;
# define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
# else
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 667cf8f..b207ffe 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -6,7 +6,7 @@ romstage-y += memcmp.c
romstage-y += cbfs.c
romstage-y += lzma.c
#romstage-y += lzmadecode.c
-romstage-$(CONFIG_USE_CACHE_AS_RAM) += ramtest.c
+romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c
romstage-$(CONFIG_HAVE_ACPI_RESUME) += cbmem.c
romstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
diff --git a/src/lib/generic_sdram.c b/src/lib/generic_sdram.c
index 7e2ff8b..efb61db 100644
--- a/src/lib/generic_sdram.c
+++ b/src/lib/generic_sdram.c
@@ -2,7 +2,7 @@
static inline void print_debug_sdram_8(const char *strval, uint32_t val)
{
-#if CONFIG_USE_CACHE_AS_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "%s%02x\n", strval, val);
#else
print_debug(strval); print_debug_hex8(val); print_debug("\n");
diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c
index 9323f76..3f4657f 100644
--- a/src/lib/ramtest.c
+++ b/src/lib/ramtest.c
@@ -53,7 +53,7 @@ static void ram_fill(unsigned long start, unsigned long stop)
/*
* Fill.
*/
-#if CONFIG_USE_CACHE_AS_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "DRAM fill: 0x%08lx-0x%08lx\n", start, stop);
#else
print_debug("DRAM fill: ");
@@ -65,7 +65,7 @@ static void ram_fill(unsigned long start, unsigned long stop)
for(addr = start; addr < stop ; addr += 4) {
/* Display address being filled */
if (!(addr & 0xfffff)) {
-#if CONFIG_USE_CACHE_AS_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "%08lx \r", addr);
#else
print_debug_hex32(addr);
@@ -75,7 +75,7 @@ static void ram_fill(unsigned long start, unsigned long stop)
write_phys(addr, (u32)addr);
};
/* Display final address */
-#if CONFIG_USE_CACHE_AS_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "%08lx\nDRAM filled\n", addr);
#else
print_debug_hex32(addr);
@@ -90,7 +90,7 @@ static void ram_verify(unsigned long start, unsigned long stop)
/*
* Verify.
*/
-#if CONFIG_USE_CACHE_AS_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "DRAM verify: 0x%08lx-0x%08lx\n", start, stop);
#else
print_debug("DRAM verify: ");
@@ -103,7 +103,7 @@ static void ram_verify(unsigned long start, unsigned long stop)
unsigned long value;
/* Display address being tested */
if (!(addr & 0xfffff)) {
-#if CONFIG_USE_CACHE_AS_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "%08lx \r", addr);
#else
print_debug_hex32(addr);
@@ -113,7 +113,7 @@ static void ram_verify(unsigned long start, unsigned long stop)
value = read_phys(addr);
if (value != addr) {
/* Display address with error */
-#if CONFIG_USE_CACHE_AS_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_ERR, "Fail: @0x%08lx Read value=0x%08lx\n", addr, value);
#else
print_err("Fail: @0x");
@@ -124,7 +124,7 @@ static void ram_verify(unsigned long start, unsigned long stop)
#endif
i++;
if(i>256) {
-#if CONFIG_USE_CACHE_AS_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "Aborting.\n");
#else
print_debug("Aborting.\n");
@@ -134,14 +134,14 @@ static void ram_verify(unsigned long start, unsigned long stop)
}
}
/* Display final address */
-#if CONFIG_USE_CACHE_AS_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "%08lx", addr);
#else
print_debug_hex32(addr);
#endif
if (i) {
-#if CONFIG_USE_CACHE_AS_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "\nDRAM did _NOT_ verify!\n");
#else
print_debug("\nDRAM did _NOT_ verify!\n");
@@ -149,7 +149,7 @@ static void ram_verify(unsigned long start, unsigned long stop)
die("DRAM ERROR");
}
else {
-#if CONFIG_USE_CACHE_AS_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "\nDRAM range verified.\n");
#else
print_debug("\nDRAM range verified.\n");
@@ -165,7 +165,7 @@ void ram_check(unsigned long start, unsigned long stop)
* test than a "Is my DRAM faulty?" test. Not all bits
* are tested. -Tyson
*/
-#if CONFIG_USE_CACHE_AS_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "Testing DRAM : %08lx - %08lx\n", start, stop);
#else
print_debug("Testing DRAM : ");
@@ -178,7 +178,7 @@ void ram_check(unsigned long start, unsigned long stop)
/* Make sure we don't read before we wrote */
phys_memory_barrier();
ram_verify(start, stop);
-#if CONFIG_USE_CACHE_AS_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "Done.\n");
#else
print_debug("Done.\n");
diff --git a/src/mainboard/aaeon/pfm-540i_revb/Kconfig b/src/mainboard/aaeon/pfm-540i_revb/Kconfig
index 5e042f3..b3b4d59 100644
--- a/src/mainboard/aaeon/pfm-540i_revb/Kconfig
+++ b/src/mainboard/aaeon/pfm-540i_revb/Kconfig
@@ -3,7 +3,7 @@ if BOARD_AAEON_PFM_540I_REVB
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select MAYBE_TINY_BOOTBLOCK
+ select MAYBE_CACHE_AS_RAM
select CPU_AMD_LX
select NORTHBRIDGE_AMD_LX
select SOUTHBRIDGE_AMD_CS5536
diff --git a/src/mainboard/advantech/pcm-5820/Kconfig b/src/mainboard/advantech/pcm-5820/Kconfig
index 4d15053..330109a 100644
--- a/src/mainboard/advantech/pcm-5820/Kconfig
+++ b/src/mainboard/advantech/pcm-5820/Kconfig
@@ -21,12 +21,11 @@ if BOARD_ADVANTECH_PCM_5820
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select NO_TINY_BOOTBLOCK
+ select NO_CACHE_AS_RAM
select CPU_AMD_GX1
select NORTHBRIDGE_AMD_GX1
select SOUTHBRIDGE_AMD_CS5530
select SUPERIO_WINBOND_W83977F
- select ROMCC
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC
diff --git a/src/mainboard/amd/db800/Kconfig b/src/mainboard/amd/db800/Kconfig
index fbd9cbb..ad97fab 100644
--- a/src/mainboard/amd/db800/Kconfig
+++ b/src/mainboard/amd/db800/Kconfig
@@ -3,7 +3,7 @@ if BOARD_AMD_DB800
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select MAYBE_TINY_BOOTBLOCK
+ select MAYBE_CACHE_AS_RAM
select CPU_AMD_LX
select NORTHBRIDGE_AMD_LX
select SOUTHBRIDGE_AMD_CS5536
diff --git a/src/mainboard/amd/norwich/Kconfig b/src/mainboard/amd/norwich/Kconfig
index 182d9da..87fe29b 100644
--- a/src/mainboard/amd/norwich/Kconfig
+++ b/src/mainboard/amd/norwich/Kconfig
@@ -3,7 +3,7 @@ if BOARD_AMD_NORWICH
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select MAYBE_TINY_BOOTBLOCK
+ select MAYBE_CACHE_AS_RAM
select CPU_AMD_LX
select NORTHBRIDGE_AMD_LX
select SOUTHBRIDGE_AMD_CS5536
diff --git a/src/mainboard/amd/rumba/Kconfig b/src/mainboard/amd/rumba/Kconfig
index d4d025b..283e823 100644
--- a/src/mainboard/amd/rumba/Kconfig
+++ b/src/mainboard/amd/rumba/Kconfig
@@ -21,7 +21,7 @@ if BOARD_AMD_RUMBA
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select MAYBE_TINY_BOOTBLOCK
+ select MAYBE_CACHE_AS_RAM
select CPU_AMD_GX2
select NORTHBRIDGE_AMD_GX2
select SOUTHBRIDGE_AMD_CS5536
diff --git a/src/mainboard/artecgroup/dbe61/Kconfig b/src/mainboard/artecgroup/dbe61/Kconfig
index 3a9acb6..40676d0 100644
--- a/src/mainboard/artecgroup/dbe61/Kconfig
+++ b/src/mainboard/artecgroup/dbe61/Kconfig
@@ -3,7 +3,7 @@ if BOARD_ARTECGROUP_DBE61
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select MAYBE_TINY_BOOTBLOCK
+ select MAYBE_CACHE_AS_RAM
select CPU_AMD_LX
select NORTHBRIDGE_AMD_LX
select SOUTHBRIDGE_AMD_CS5536
diff --git a/src/mainboard/asi/mb_5blgp/Kconfig b/src/mainboard/asi/mb_5blgp/Kconfig
index c1a07df..fb3b08d 100644
--- a/src/mainboard/asi/mb_5blgp/Kconfig
+++ b/src/mainboard/asi/mb_5blgp/Kconfig
@@ -21,12 +21,11 @@ if BOARD_ASI_MB_5BLGP
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select NO_TINY_BOOTBLOCK
+ select NO_CACHE_AS_RAM
select CPU_AMD_GX1
select NORTHBRIDGE_AMD_GX1
select SOUTHBRIDGE_AMD_CS5530
select SUPERIO_NSC_PC87351
- select ROMCC
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC
diff --git a/src/mainboard/asi/mb_5blmp/Kconfig b/src/mainboard/asi/mb_5blmp/Kconfig
index a5e0086..020adf4 100644
--- a/src/mainboard/asi/mb_5blmp/Kconfig
+++ b/src/mainboard/asi/mb_5blmp/Kconfig
@@ -21,12 +21,11 @@ if BOARD_ASI_MB_5BLMP
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select NO_TINY_BOOTBLOCK
+ select NO_CACHE_AS_RAM
select CPU_AMD_GX1
select NORTHBRIDGE_AMD_GX1
select SOUTHBRIDGE_AMD_CS5530
select SUPERIO_NSC_PC87351
- select ROMCC
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC
diff --git a/src/mainboard/asus/a8v-e_deluxe/Kconfig b/src/mainboard/asus/a8v-e_deluxe/Kconfig
index c3c0e91..379f036 100644
--- a/src/mainboard/asus/a8v-e_deluxe/Kconfig
+++ b/src/mainboard/asus/a8v-e_deluxe/Kconfig
@@ -3,7 +3,7 @@ if BOARD_ASUS_A8V_E_DELUXE
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select MAYBE_TINY_BOOTBLOCK
+ select MAYBE_CACHE_AS_RAM
select CPU_AMD_SOCKET_939
select K8_HT_FREQ_1G_SUPPORT
select NORTHBRIDGE_AMD_AMDK8
diff --git a/src/mainboard/asus/a8v-e_se/Kconfig b/src/mainboard/asus/a8v-e_se/Kconfig
index da42165..d81cee4 100644
--- a/src/mainboard/asus/a8v-e_se/Kconfig
+++ b/src/mainboard/asus/a8v-e_se/Kconfig
@@ -3,7 +3,7 @@ if BOARD_ASUS_A8V_E_SE
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select MAYBE_TINY_BOOTBLOCK
+ select MAYBE_CACHE_AS_RAM
select CPU_AMD_SOCKET_939
select K8_HT_FREQ_1G_SUPPORT
select NORTHBRIDGE_AMD_AMDK8
diff --git a/src/mainboard/asus/mew-am/Kconfig b/src/mainboard/asus/mew-am/Kconfig
index 1064313..a6ab36c 100644
--- a/src/mainboard/asus/mew-am/Kconfig
+++ b/src/mainboard/asus/mew-am/Kconfig
@@ -21,7 +21,7 @@ if BOARD_ASUS_MEW_AM
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select MAYBE_TINY_BOOTBLOCK
+ select MAYBE_CACHE_AS_RAM
select CPU_INTEL_SOCKET_PGA370
select NORTHBRIDGE_INTEL_I82810
select SOUTHBRIDGE_INTEL_I82801AX
diff --git a/src/mainboard/asus/mew-vm/Kconfig b/src/mainboard/asus/mew-vm/Kconfig
index 98dab9d..58916e0 100644
--- a/src/mainboard/asus/mew-vm/Kconfig
+++ b/src/mainboard/asus/mew-vm/Kconfig
@@ -21,7 +21,7 @@ if BOARD_ASUS_MEW_VM
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select MAYBE_TINY_BOOTBLOCK
+ select MAYBE_CACHE_AS_RAM
select CPU_INTEL_SOCKET_PGA370
select NORTHBRIDGE_INTEL_I82810
select SOUTHBRIDGE_INTEL_I82801AX
diff --git a/src/mainboard/axus/tc320/Kconfig b/src/mainboard/axus/tc320/Kconfig
index e9cba2d..710a342 100644
--- a/src/mainboard/axus/tc320/Kconfig
+++ b/src/mainboard/axus/tc320/Kconfig
@@ -21,12 +21,11 @@ if BOARD_AXUS_TC320
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select NO_TINY_BOOTBLOCK
+ select NO_CACHE_AS_RAM
select CPU_AMD_GX1
select NORTHBRIDGE_AMD_GX1
select SOUTHBRIDGE_AMD_CS5530
select SUPERIO_NSC_PC97317
- select ROMCC
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC
diff --git a/src/mainboard/bcom/winnet100/Kconfig b/src/mainboard/bcom/winnet100/Kconfig
index 9309518..a7cba28 100644
--- a/src/mainboard/bcom/winnet100/Kconfig
+++ b/src/mainboard/bcom/winnet100/Kconfig
@@ -21,12 +21,11 @@ if BOARD_BCOM_WINNET100
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select NO_TINY_BOOTBLOCK
+ select NO_CACHE_AS_RAM
select CPU_AMD_GX1
select NORTHBRIDGE_AMD_GX1
select SOUTHBRIDGE_AMD_CS5530
select SUPERIO_NSC_PC97317
- select ROMCC
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC
diff --git a/src/mainboard/bcom/winnetp680/Kconfig b/src/mainboard/bcom/winnetp680/Kconfig
index a8bb2bb..010b63d 100644
--- a/src/mainboard/bcom/winnetp680/Kconfig
+++ b/src/mainboard/bcom/winnetp680/Kconfig
@@ -3,7 +3,7 @@ if BOARD_BCOM_WINNETP680
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select MAYBE_TINY_BOOTBLOCK
+ select MAYBE_CACHE_AS_RAM
select CPU_VIA_C7
select NORTHBRIDGE_VIA_CN700
select SOUTHBRIDGE_VIA_VT8237R
diff --git a/src/mainboard/dell/s1850/Kconfig b/src/mainboard/dell/s1850/Kconfig
index 39ef51d..120af25 100644
--- a/src/mainboard/dell/s1850/Kconfig
+++ b/src/mainboard/dell/s1850/Kconfig
@@ -3,13 +3,12 @@ if BOARD_DELL_S1850
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select NO_TINY_BOOTBLOCK
+ select NO_CACHE_AS_RAM
select CPU_INTEL_SOCKET_MPGA604
select NORTHBRIDGE_INTEL_E7520
select SOUTHBRIDGE_INTEL_I82801EX
select SOUTHBRIDGE_INTEL_PXHD
select SUPERIO_NSC_PC8374
- select ROMCC
select HAVE_HARD_RESET
select HAVE_OPTION_TABLE
select BOARD_HAS_HARD_RESET
diff --git a/src/mainboard/digitallogic/msm586seg/Kconfig b/src/mainboard/digitallogic/msm586seg/Kconfig
index 5312309..5d2bec4 100644
--- a/src/mainboard/digitallogic/msm586seg/Kconfig
+++ b/src/mainboard/digitallogic/msm586seg/Kconfig
@@ -3,12 +3,11 @@ if BOARD_DIGITALLOGIC_MSM586SEG
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select NO_TINY_BOOTBLOCK
+ select NO_CACHE_AS_RAM
select CPU_AMD_SC520
select HAVE_PIRQ_TABLE
select HAVE_OPTION_TABLE
select BOARD_ROMSIZE_KB_512
- select ROMCC
config MAINBOARD_DIR
string
diff --git a/src/mainboard/digitallogic/msm800sev/Kconfig b/src/mainboard/digitallogic/msm800sev/Kconfig
index 1cebd1b..df5bc34 100644
--- a/src/mainboard/digitallogic/msm800sev/Kconfig
+++ b/src/mainboard/digitallogic/msm800sev/Kconfig
@@ -3,7 +3,7 @@ if BOARD_DIGITALLOGIC_MSM800SEV
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select MAYBE_TINY_BOOTBLOCK
+ select MAYBE_CACHE_AS_RAM
select CPU_AMD_LX
select NORTHBRIDGE_AMD_LX
select SOUTHBRIDGE_AMD_CS5536
diff --git a/src/mainboard/eaglelion/5bcm/Kconfig b/src/mainboard/eaglelion/5bcm/Kconfig
index 77f7a93..ce7b005 100644
--- a/src/mainboard/eaglelion/5bcm/Kconfig
+++ b/src/mainboard/eaglelion/5bcm/Kconfig
@@ -21,12 +21,11 @@ if BOARD_EAGLELION_5BCM
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select NO_TINY_BOOTBLOCK
+ select NO_CACHE_AS_RAM
select CPU_AMD_GX1
select NORTHBRIDGE_AMD_GX1
select SOUTHBRIDGE_AMD_CS5530
select SUPERIO_NSC_PC97317
- select ROMCC
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC
diff --git a/src/mainboard/ecs/p6iwp-fe/Kconfig b/src/mainboard/ecs/p6iwp-fe/Kconfig
index 25efbc6..b377168 100644
--- a/src/mainboard/ecs/p6iwp-fe/Kconfig
+++ b/src/mainboard/ecs/p6iwp-fe/Kconfig
@@ -22,7 +22,7 @@ if BOARD_ECS_P6IWP_FE
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select MAYBE_TINY_BOOTBLOCK
+ select MAYBE_CACHE_AS_RAM
select CPU_INTEL_SOCKET_PGA370
select NORTHBRIDGE_INTEL_I82810
select SOUTHBRIDGE_INTEL_I82801AX
diff --git a/src/mainboard/emulation/qemu-x86/Kconfig b/src/mainboard/emulation/qemu-x86/Kconfig
index db1a027..b9598b0 100644
--- a/src/mainboard/emulation/qemu-x86/Kconfig
+++ b/src/mainboard/emulation/qemu-x86/Kconfig
@@ -4,7 +4,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
select SOUTHBRIDGE_INTEL_I82371EB
- select ROMCC
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_256
diff --git a/src/mainboard/hp/e_vectra_p2706t/Kconfig b/src/mainboard/hp/e_vectra_p2706t/Kconfig
index 74117a3..606a9fd 100644
--- a/src/mainboard/hp/e_vectra_p2706t/Kconfig
+++ b/src/mainboard/hp/e_vectra_p2706t/Kconfig
@@ -25,7 +25,7 @@ if BOARD_HP_E_VECTRA_P2706T
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select MAYBE_TINY_BOOTBLOCK
+ select MAYBE_CACHE_AS_RAM
select CPU_INTEL_SOCKET_PGA370
select NORTHBRIDGE_INTEL_I82810
select SOUTHBRIDGE_INTEL_I82801AX
diff --git a/src/mainboard/iei/juki-511p/Kconfig b/src/mainboard/iei/juki-511p/Kconfig
index 2efa6ce..7ef1e4f 100644
--- a/src/mainboard/iei/juki-511p/Kconfig
+++ b/src/mainboard/iei/juki-511p/Kconfig
@@ -21,12 +21,11 @@ if BOARD_IEI_JUKI_511P
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select NO_TINY_BOOTBLOCK
+ select NO_CACHE_AS_RAM
select CPU_AMD_GX1
select NORTHBRIDGE_AMD_GX1
select SOUTHBRIDGE_AMD_CS5530
select SUPERIO_WINBOND_W83977F
- select ROMCC
select PIRQ_ROUTE
select HAVE_PIRQ_TABLE
select HAVE_OPTION_TABLE
diff --git a/src/mainboard/iei/nova4899r/Kconfig b/src/mainboard/iei/nova4899r/Kconfig
index 09bbb92..1cbebe7 100644
--- a/src/mainboard/iei/nova4899r/Kconfig
+++ b/src/mainboard/iei/nova4899r/Kconfig
@@ -21,12 +21,11 @@ if BOARD_IEI_NOVA_4899R
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select NO_TINY_BOOTBLOCK
+ select NO_CACHE_AS_RAM
select CPU_AMD_GX1
select NORTHBRIDGE_AMD_GX1
select SOUTHBRIDGE_AMD_CS5530
select SUPERIO_WINBOND_W83977TF
- select ROMCC
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select HAVE_OPTION_TABLE
diff --git a/src/mainboard/iei/pcisa-lx-800-r10/Kconfig b/src/mainboard/iei/pcisa-lx-800-r10/Kconfig
index 38cdb92..d20a1dc 100644
--- a/src/mainboard/iei/pcisa-lx-800-r10/Kconfig
+++ b/src/mainboard/iei/pcisa-lx-800-r10/Kconfig
@@ -3,7 +3,7 @@ if BOARD_IEI_PCISA_LX_800_R10
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select MAYBE_TINY_BOOTBLOCK
+ select MAYBE_CACHE_AS_RAM
select CPU_AMD_LX
select NORTHBRIDGE_AMD_LX
select SOUTHBRIDGE_AMD_CS5536
diff --git a/src/mainboard/intel/d810e2cb/Kconfig b/src/mainboard/intel/d810e2cb/Kconfig
index f5b6da7..8c6c76b 100644
--- a/src/mainboard/intel/d810e2cb/Kconfig
+++ b/src/mainboard/intel/d810e2cb/Kconfig
@@ -21,7 +21,6 @@ if BOARD_INTEL_D810E2CB
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select MAYBE_TINY_BOOTBLOCK
select CPU_INTEL_SOCKET_FC_PGA370
select NORTHBRIDGE_INTEL_I82810
select SOUTHBRIDGE_INTEL_I82801BX
diff --git a/src/mainboard/intel/eagleheights/Kconfig b/src/mainboard/intel/eagleheights/Kconfig
index 8ef4e99..eecd0ac 100644
--- a/src/mainboard/intel/eagleheights/Kconfig
+++ b/src/mainboard/intel/eagleheights/Kconfig
@@ -3,7 +3,7 @@ if BOARD_INTEL_EAGLEHEIGHTS
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select NO_TINY_BOOTBLOCK
+ select NO_CACHE_AS_RAM
select CPU_INTEL_SOCKET_BGA956
select NORTHBRIDGE_INTEL_I3100
select SOUTHBRIDGE_INTEL_I3100
diff --git a/src/mainboard/intel/jarrell/Kconfig b/src/mainboard/intel/jarrell/Kconfig
index e297e3b..6a5b608 100644
--- a/src/mainboard/intel/jarrell/Kconfig
+++ b/src/mainboard/intel/jarrell/Kconfig
@@ -3,13 +3,12 @@ if BOARD_INTEL_JARRELL
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select NO_TINY_BOOTBLOCK
+ select NO_CACHE_AS_RAM
select CPU_INTEL_SOCKET_MPGA604
select NORTHBRIDGE_INTEL_E7520
select SOUTHBRIDGE_INTEL_PXHD
select SOUTHBRIDGE_INTEL_I82801EX
select SUPERIO_NSC_PC87427
- select ROMCC
select HAVE_HARD_RESET
select BOARD_HAS_HARD_RESET
select HAVE_OPTION_TABLE
diff --git a/src/mainboard/intel/mtarvon/Kconfig b/src/mainboard/intel/mtarvon/Kconfig
index 7ec8b92..4e520b2 100644
--- a/src/mainboard/intel/mtarvon/Kconfig
+++ b/src/mainboard/intel/mtarvon/Kconfig
@@ -3,7 +3,7 @@ if BOARD_INTEL_MTARVON
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select MAYBE_TINY_BOOTBLOCK
+ select MAYBE_CACHE_AS_RAM
select CPU_INTEL_SOCKET_MPGA479M
select NORTHBRIDGE_INTEL_I3100
select SOUTHBRIDGE_INTEL_I3100
diff --git a/src/mainboard/intel/truxton/Kconfig b/src/mainboard/intel/truxton/Kconfig
index 130c642..372d9df 100644
--- a/src/mainboard/intel/truxton/Kconfig
+++ b/src/mainboard/intel/truxton/Kconfig
@@ -3,13 +3,12 @@ if BOARD_INTEL_TRUXTON
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select NO_TINY_BOOTBLOCK
+ select NO_CACHE_AS_RAM
select CPU_INTEL_EP80579
select NORTHBRIDGE_INTEL_I3100
select SOUTHBRIDGE_INTEL_I3100
select SUPERIO_INTEL_I3100
select SUPERIO_SMSC_SMSCSUPERIO
- select ROMCC
select HAVE_HARD_RESET
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
diff --git a/src/mainboard/intel/xe7501devkit/Kconfig b/src/mainboard/intel/xe7501devkit/Kconfig
index e001250..5c4f540 100644
--- a/src/mainboard/intel/xe7501devkit/Kconfig
+++ b/src/mainboard/intel/xe7501devkit/Kconfig
@@ -3,13 +3,12 @@ if BOARD_INTEL_XE7501DEVKIT
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select NO_TINY_BOOTBLOCK
+ select NO_CACHE_AS_RAM
select CPU_INTEL_SOCKET_MPGA604
select NORTHBRIDGE_INTEL_E7501
select SOUTHBRIDGE_INTEL_I82870
select SOUTHBRIDGE_INTEL_I82801CX
select SUPERIO_SMSC_LPC47B272
- select ROMCC
select HAVE_HARD_RESET
select BOARD_HAS_HARD_RESET
select HAVE_PIRQ_TABLE
diff --git a/src/mainboard/jetway/j7f24/Kconfig b/src/mainboard/jetway/j7f24/Kconfig
index 35cdeb6..69f300b 100644
--- a/src/mainboard/jetway/j7f24/Kconfig
+++ b/src/mainboard/jetway/j7f24/Kconfig
@@ -4,7 +4,7 @@ if BOARD_JETWAY_J7F24
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select MAYBE_TINY_BOOTBLOCK
+ select MAYBE_CACHE_AS_RAM
select CPU_VIA_C7
select NORTHBRIDGE_VIA_CN700
select SOUTHBRIDGE_VIA_VT8237R
diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig
index 291d084..b02fcca 100644
--- a/src/mainboard/lenovo/x60/Kconfig
+++ b/src/mainboard/lenovo/x60/Kconfig
@@ -3,7 +3,7 @@ if BOARD_LENOVO_X60
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select NO_TINY_BOOTBLOCK
+ select NO_CACHE_AS_RAM
select CPU_INTEL_SOCKET_MFCPGA478
select NORTHBRIDGE_INTEL_I945GM
select SOUTHBRIDGE_INTEL_I82801GX
diff --git a/src/mainboard/lippert/frontrunner/Kconfig b/src/mainboard/lippert/frontrunner/Kconfig
index bae2e75..27c8b60 100644
--- a/src/mainboard/lippert/frontrunner/Kconfig
+++ b/src/mainboard/lippert/frontrunner/Kconfig
@@ -3,7 +3,7 @@ if BOARD_LIPPERT_FRONTRUNNER
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select MAYBE_TINY_BOOTBLOCK
+ select MAYBE_CACHE_AS_RAM
select CPU_AMD_GX2
select NORTHBRIDGE_AMD_GX2
select SOUTHBRIDGE_AMD_CS5535
diff --git a/src/mainboard/lippert/hurricane-lx/Kconfig b/src/mainboard/lippert/hurricane-lx/Kconfig
index b32c338..cac1186 100644
--- a/src/mainboard/lippert/hurricane-lx/Kconfig
+++ b/src/mainboard/lippert/hurricane-lx/Kconfig
@@ -3,7 +3,7 @@ if BOARD_LIPPERT_HURRICANE_LX
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select MAYBE_TINY_BOOTBLOCK
+ select MAYBE_CACHE_AS_RAM
select CPU_AMD_LX
select NORTHBRIDGE_AMD_LX
select SOUTHBRIDGE_AMD_CS5536
diff --git a/src/mainboard/lippert/literunner-lx/Kconfig b/src/mainboard/lippert/literunner-lx/Kconfig
index 6afba94..4218a7f 100644
--- a/src/mainboard/lippert/literunner-lx/Kconfig
+++ b/src/mainboard/lippert/literunner-lx/Kconfig
@@ -3,7 +3,7 @@ if BOARD_LIPPERT_LITERUNNER_LX
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select MAYBE_TINY_BOOTBLOCK
+ select MAYBE_CACHE_AS_RAM
select CPU_AMD_LX
select NORTHBRIDGE_AMD_LX
select SOUTHBRIDGE_AMD_CS5536
diff --git a/src/mainboard/lippert/roadrunner-lx/Kconfig b/src/mainboard/lippert/roadrunner-lx/Kconfig
index cbf3ea0..3a0a689 100644
--- a/src/mainboard/lippert/roadrunner-lx/Kconfig
+++ b/src/mainboard/lippert/roadrunner-lx/Kconfig
@@ -3,7 +3,7 @@ if BOARD_LIPPERT_ROADRUNNER_LX
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select MAYBE_TINY_BOOTBLOCK
+ select MAYBE_CACHE_AS_RAM
select CPU_AMD_LX
select NORTHBRIDGE_AMD_LX
select SOUTHBRIDGE_AMD_CS5536
diff --git a/src/mainboard/lippert/spacerunner-lx/Kconfig b/src/mainboard/lippert/spacerunner-lx/Kconfig
index 7781f06..e99f47d 100644
--- a/src/mainboard/lippert/spacerunner-lx/Kconfig
+++ b/src/mainboard/lippert/spacerunner-lx/Kconfig
@@ -3,7 +3,7 @@ if BOARD_LIPPERT_SPACERUNNER_LX
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select MAYBE_TINY_BOOTBLOCK
+ select MAYBE_CACHE_AS_RAM
select CPU_AMD_LX
select NORTHBRIDGE_AMD_LX
select SOUTHBRIDGE_AMD_CS5536
diff --git a/src/mainboard/mitac/6513wu/Kconfig b/src/mainboard/mitac/6513wu/Kconfig
index 773b3c0..a1fa602 100644
--- a/src/mainboard/mitac/6513wu/Kconfig
+++ b/src/mainboard/mitac/6513wu/Kconfig
@@ -21,7 +21,7 @@ if BOARD_MITAC_6513WU
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select MAYBE_TINY_BOOTBLOCK
+ select MAYBE_CACHE_AS_RAM
select CPU_INTEL_SOCKET_PGA370
select NORTHBRIDGE_INTEL_I82810
select SOUTHBRIDGE_INTEL_I82801AX
diff --git a/src/mainboard/msi/ms6178/Kconfig b/src/mainboard/msi/ms6178/Kconfig
index 7746341..e5696ae 100644
--- a/src/mainboard/msi/ms6178/Kconfig
+++ b/src/mainboard/msi/ms6178/Kconfig
@@ -21,7 +21,7 @@ if BOARD_MSI_MS_6178
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select MAYBE_TINY_BOOTBLOCK
+ select MAYBE_CACHE_AS_RAM
select CPU_INTEL_SOCKET_PGA370
select NORTHBRIDGE_INTEL_I82810
select SOUTHBRIDGE_INTEL_I82801AX
diff --git a/src/mainboard/nec/powermate2000/Kconfig b/src/mainboard/nec/powermate2000/Kconfig
index 3f3aab4..244b543 100644
--- a/src/mainboard/nec/powermate2000/Kconfig
+++ b/src/mainboard/nec/powermate2000/Kconfig
@@ -21,7 +21,7 @@ if BOARD_NEC_POWERMATE_2000
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select MAYBE_TINY_BOOTBLOCK
+ select MAYBE_CACHE_AS_RAM
select CPU_INTEL_SOCKET_PGA370
select NORTHBRIDGE_INTEL_I82810
select SOUTHBRIDGE_INTEL_I82801AX
diff --git a/src/mainboard/pcengines/alix1c/Kconfig b/src/mainboard/pcengines/alix1c/Kconfig
index da620c0..b0758fa 100644
--- a/src/mainboard/pcengines/alix1c/Kconfig
+++ b/src/mainboard/pcengines/alix1c/Kconfig
@@ -3,7 +3,7 @@ if BOARD_PCENGINES_ALIX1C
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select MAYBE_TINY_BOOTBLOCK
+ select MAYBE_CACHE_AS_RAM
select CPU_AMD_LX
select NORTHBRIDGE_AMD_LX
select SOUTHBRIDGE_AMD_CS5536
diff --git a/src/mainboard/pcengines/alix2d/Kconfig b/src/mainboard/pcengines/alix2d/Kconfig
index 8c1a8e2..4cc8c94 100644
--- a/src/mainboard/pcengines/alix2d/Kconfig
+++ b/src/mainboard/pcengines/alix2d/Kconfig
@@ -3,7 +3,7 @@ if BOARD_PCENGINES_ALIX2D
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select MAYBE_TINY_BOOTBLOCK
+ select MAYBE_CACHE_AS_RAM
select CPU_AMD_LX
select NORTHBRIDGE_AMD_LX
select SOUTHBRIDGE_AMD_CS5536
diff --git a/src/mainboard/roda/rk886ex/Kconfig b/src/mainboard/roda/rk886ex/Kconfig
index 8ab7b32..cf1d8ed 100644
--- a/src/mainboard/roda/rk886ex/Kconfig
+++ b/src/mainboard/roda/rk886ex/Kconfig
@@ -3,7 +3,7 @@ if BOARD_RODA_RK886EX
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select NO_TINY_BOOTBLOCK
+ select NO_CACHE_AS_RAM
select CPU_INTEL_SOCKET_MFCPGA478
select NORTHBRIDGE_INTEL_I945GM
select SOUTHBRIDGE_INTEL_I82801GX
diff --git a/src/mainboard/supermicro/x6dai_g/Kconfig b/src/mainboard/supermicro/x6dai_g/Kconfig
index d0921b6..6fedc2b 100644
--- a/src/mainboard/supermicro/x6dai_g/Kconfig
+++ b/src/mainboard/supermicro/x6dai_g/Kconfig
@@ -3,12 +3,11 @@ if BOARD_SUPERMICRO_X6DAI_G
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select NO_TINY_BOOTBLOCK
+ select NO_CACHE_AS_RAM
select CPU_INTEL_SOCKET_MPGA604
select NORTHBRIDGE_INTEL_E7525
select SOUTHBRIDGE_INTEL_ESB6300
select SUPERIO_WINBOND_W83627HF
- select ROMCC
select HAVE_HARD_RESET
select BOARD_HAS_HARD_RESET
select HAVE_OPTION_TABLE
diff --git a/src/mainboard/supermicro/x6dhe_g/Kconfig b/src/mainboard/supermicro/x6dhe_g/Kconfig
index 64bc746..10f3e8f 100644
--- a/src/mainboard/supermicro/x6dhe_g/Kconfig
+++ b/src/mainboard/supermicro/x6dhe_g/Kconfig
@@ -3,13 +3,12 @@ if BOARD_SUPERMICRO_X6DHE_G
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select NO_TINY_BOOTBLOCK
+ select NO_CACHE_AS_RAM
select CPU_INTEL_SOCKET_MPGA604
select NORTHBRIDGE_INTEL_E7520
select SOUTHBRIDGE_INTEL_ESB6300
select SOUTHBRIDGE_INTEL_PXHD
select SUPERIO_WINBOND_W83627HF
- select ROMCC
select HAVE_HARD_RESET
select BOARD_HAS_HARD_RESET
select HAVE_OPTION_TABLE
diff --git a/src/mainboard/supermicro/x6dhe_g2/Kconfig b/src/mainboard/supermicro/x6dhe_g2/Kconfig
index 8295fbd..e0f7a86 100644
--- a/src/mainboard/supermicro/x6dhe_g2/Kconfig
+++ b/src/mainboard/supermicro/x6dhe_g2/Kconfig
@@ -3,13 +3,12 @@ if BOARD_SUPERMICRO_X6DHE_G2
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select NO_TINY_BOOTBLOCK
+ select NO_CACHE_AS_RAM
select CPU_INTEL_SOCKET_MPGA604
select NORTHBRIDGE_INTEL_E7520
select SOUTHBRIDGE_INTEL_I82801EX
select SOUTHBRIDGE_INTEL_PXHD
select SUPERIO_NSC_PC87427
- select ROMCC
select HAVE_HARD_RESET
select BOARD_HAS_HARD_RESET
select HAVE_OPTION_TABLE
diff --git a/src/mainboard/supermicro/x6dhr_ig/Kconfig b/src/mainboard/supermicro/x6dhr_ig/Kconfig
index 6e080ba..8e5608c 100644
--- a/src/mainboard/supermicro/x6dhr_ig/Kconfig
+++ b/src/mainboard/supermicro/x6dhr_ig/Kconfig
@@ -3,13 +3,12 @@ if BOARD_SUPERMICRO_X6DHR_IG
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select NO_TINY_BOOTBLOCK
+ select NO_CACHE_AS_RAM
select CPU_INTEL_SOCKET_MPGA604
select NORTHBRIDGE_INTEL_E7520
select SOUTHBRIDGE_INTEL_I82801EX
select SOUTHBRIDGE_INTEL_PXHD
select SUPERIO_WINBOND_W83627HF
- select ROMCC
select HAVE_HARD_RESET
select BOARD_HAS_HARD_RESET
select HAVE_OPTION_TABLE
diff --git a/src/mainboard/supermicro/x6dhr_ig2/Kconfig b/src/mainboard/supermicro/x6dhr_ig2/Kconfig
index 9713169..790bf37 100644
--- a/src/mainboard/supermicro/x6dhr_ig2/Kconfig
+++ b/src/mainboard/supermicro/x6dhr_ig2/Kconfig
@@ -3,13 +3,12 @@ if BOARD_SUPERMICRO_X6DHR_IG2
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select NO_TINY_BOOTBLOCK
+ select NO_CACHE_AS_RAM
select CPU_INTEL_SOCKET_MPGA604
select NORTHBRIDGE_INTEL_E7520
select SOUTHBRIDGE_INTEL_I82801EX
select SOUTHBRIDGE_INTEL_PXHD
select SUPERIO_WINBOND_W83627HF
- select ROMCC
select HAVE_HARD_RESET
select BOARD_HAS_HARD_RESET
select HAVE_OPTION_TABLE
diff --git a/src/mainboard/technologic/ts5300/Kconfig b/src/mainboard/technologic/ts5300/Kconfig
index 6352ca4..ab10061 100644
--- a/src/mainboard/technologic/ts5300/Kconfig
+++ b/src/mainboard/technologic/ts5300/Kconfig
@@ -3,9 +3,8 @@ if BOARD_TECHNOLOGIC_TS5300
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select NO_TINY_BOOTBLOCK
+ select NO_CACHE_AS_RAM
select CPU_AMD_SC520
- select ROMCC
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_1024
diff --git a/src/mainboard/televideo/tc7020/Kconfig b/src/mainboard/televideo/tc7020/Kconfig
index a3e5260..6f78018 100644
--- a/src/mainboard/televideo/tc7020/Kconfig
+++ b/src/mainboard/televideo/tc7020/Kconfig
@@ -21,12 +21,11 @@ if BOARD_TELEVIDEO_TC7020
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select NO_TINY_BOOTBLOCK
+ select NO_CACHE_AS_RAM
select CPU_AMD_GX1
select NORTHBRIDGE_AMD_GX1
select SOUTHBRIDGE_AMD_CS5530
select SUPERIO_NSC_PC97317
- select ROMCC
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC
diff --git a/src/mainboard/traverse/geos/Kconfig b/src/mainboard/traverse/geos/Kconfig
index 6a5e0b9..3210ec6 100644
--- a/src/mainboard/traverse/geos/Kconfig
+++ b/src/mainboard/traverse/geos/Kconfig
@@ -3,7 +3,7 @@ if BOARD_TRAVERSE_GEOS
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select MAYBE_TINY_BOOTBLOCK
+ select MAYBE_CACHE_AS_RAM
select CPU_AMD_LX
select NORTHBRIDGE_AMD_LX
select SOUTHBRIDGE_AMD_CS5536
diff --git a/src/mainboard/tyan/s2735/Kconfig b/src/mainboard/tyan/s2735/Kconfig
index 36739f3..a076bd6 100644
--- a/src/mainboard/tyan/s2735/Kconfig
+++ b/src/mainboard/tyan/s2735/Kconfig
@@ -3,7 +3,7 @@ if BOARD_TYAN_S2735
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select NO_TINY_BOOTBLOCK
+ select NO_CACHE_AS_RAM
select CPU_INTEL_SOCKET_MPGA604
select NORTHBRIDGE_INTEL_E7501
select SOUTHBRIDGE_INTEL_I82870
diff --git a/src/mainboard/via/epia-cn/Kconfig b/src/mainboard/via/epia-cn/Kconfig
index c14dda6..b16040d 100644
--- a/src/mainboard/via/epia-cn/Kconfig
+++ b/src/mainboard/via/epia-cn/Kconfig
@@ -3,7 +3,7 @@ if BOARD_VIA_EPIA_CN
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select MAYBE_TINY_BOOTBLOCK
+ select MAYBE_CACHE_AS_RAM
select CPU_VIA_C7
select NORTHBRIDGE_VIA_CN700
select SOUTHBRIDGE_VIA_VT8237R
diff --git a/src/mainboard/via/epia-m/Kconfig b/src/mainboard/via/epia-m/Kconfig
index f23600b..947fee7 100644
--- a/src/mainboard/via/epia-m/Kconfig
+++ b/src/mainboard/via/epia-m/Kconfig
@@ -3,7 +3,7 @@ if BOARD_VIA_EPIA_M
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select NO_TINY_BOOTBLOCK
+ select NO_CACHE_AS_RAM
select CPU_VIA_C3
select NORTHBRIDGE_VIA_VT8623
select SOUTHBRIDGE_VIA_VT8235
@@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_256
- select ROMCC
config MAINBOARD_DIR
string
diff --git a/src/mainboard/via/epia-m700/Kconfig b/src/mainboard/via/epia-m700/Kconfig
index 38f045f..56c6e12 100644
--- a/src/mainboard/via/epia-m700/Kconfig
+++ b/src/mainboard/via/epia-m700/Kconfig
@@ -3,7 +3,7 @@ if BOARD_VIA_EPIA_M700
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select MAYBE_TINY_BOOTBLOCK
+ select MAYBE_CACHE_AS_RAM
select CPU_VIA_C7
select NORTHBRIDGE_VIA_VX800
select SUPERIO_WINBOND_W83697HF
diff --git a/src/mainboard/via/epia-n/Kconfig b/src/mainboard/via/epia-n/Kconfig
index b6a54b0..ca669b3 100644
--- a/src/mainboard/via/epia-n/Kconfig
+++ b/src/mainboard/via/epia-n/Kconfig
@@ -3,7 +3,7 @@ if BOARD_VIA_EPIA_N
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select NO_TINY_BOOTBLOCK
+ select NO_CACHE_AS_RAM
select CPU_VIA_C3
select NORTHBRIDGE_VIA_CN400
select SOUTHBRIDGE_VIA_VT8237R
@@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select EPIA_VT8237R_INIT
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_512
- select ROMCC
config MAINBOARD_DIR
string
diff --git a/src/mainboard/via/epia/Kconfig b/src/mainboard/via/epia/Kconfig
index daa2b4f..2ec8457 100644
--- a/src/mainboard/via/epia/Kconfig
+++ b/src/mainboard/via/epia/Kconfig
@@ -3,7 +3,7 @@ if BOARD_VIA_EPIA
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select NO_TINY_BOOTBLOCK
+ select NO_CACHE_AS_RAM
select CPU_VIA_C3
select NORTHBRIDGE_VIA_VT8601
select SOUTHBRIDGE_VIA_VT8231
@@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_256
- select ROMCC
config MAINBOARD_DIR
string
diff --git a/src/mainboard/via/pc2500e/Kconfig b/src/mainboard/via/pc2500e/Kconfig
index e25cdb9..5c92942 100644
--- a/src/mainboard/via/pc2500e/Kconfig
+++ b/src/mainboard/via/pc2500e/Kconfig
@@ -3,7 +3,7 @@ if BOARD_VIA_PC2500E
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select MAYBE_TINY_BOOTBLOCK
+ select MAYBE_CACHE_AS_RAM
select CPU_VIA_C7
select NORTHBRIDGE_VIA_CN700
select SOUTHBRIDGE_VIA_VT8237R
diff --git a/src/mainboard/winent/pl6064/Kconfig b/src/mainboard/winent/pl6064/Kconfig
index 8c722da..1d1c04a 100644
--- a/src/mainboard/winent/pl6064/Kconfig
+++ b/src/mainboard/winent/pl6064/Kconfig
@@ -3,7 +3,7 @@ if BOARD_WINENT_PL6064
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select MAYBE_TINY_BOOTBLOCK
+ select MAYBE_CACHE_AS_RAM
select CPU_AMD_LX
select NORTHBRIDGE_AMD_LX
select SOUTHBRIDGE_AMD_CS5536
diff --git a/src/mainboard/wyse/s50/Kconfig b/src/mainboard/wyse/s50/Kconfig
index 6df776d..0700ff7 100644
--- a/src/mainboard/wyse/s50/Kconfig
+++ b/src/mainboard/wyse/s50/Kconfig
@@ -21,7 +21,7 @@ if BOARD_WYSE_S50
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select MAYBE_TINY_BOOTBLOCK
+ select MAYBE_CACHE_AS_RAM
select CPU_AMD_GX2
select NORTHBRIDGE_AMD_GX2
select SOUTHBRIDGE_AMD_CS5536
diff --git a/src/northbridge/intel/e7501/debug.c b/src/northbridge/intel/e7501/debug.c
index 45c1edd..f19de0c 100644
--- a/src/northbridge/intel/e7501/debug.c
+++ b/src/northbridge/intel/e7501/debug.c
@@ -39,7 +39,7 @@ static void dump_pci_device(unsigned dev)
for(i = 0; i < 256; i++) {
unsigned char val;
if ((i & 0x0f) == 0) {
-#if CONFIG_USE_CACHE_AS_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "\n%02x:",i);
#else
print_debug("\n");
@@ -48,7 +48,7 @@ static void dump_pci_device(unsigned dev)
#endif
}
val = pci_read_config8(dev, i);
-#if CONFIG_USE_CACHE_AS_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, " %02x", val);
#else
print_debug_char(' ');
@@ -101,7 +101,7 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl)
device = ctrl->channel0[i];
if (device) {
int j;
-#if CONFIG_USE_CACHE_AS_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device);
#else
print_debug("dimm: ");
@@ -113,7 +113,7 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl)
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
-#if CONFIG_USE_CACHE_AS_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "\n%02x: ", j);
#else
print_debug("\n");
@@ -126,7 +126,7 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl)
break;
}
byte = status & 0xff;
-#if CONFIG_USE_CACHE_AS_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "%02x ", byte);
#else
print_debug_hex8(byte);
@@ -138,7 +138,7 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl)
device = ctrl->channel1[i];
if (device) {
int j;
-#if CONFIG_USE_CACHE_AS_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device);
#else
print_debug("dimm: ");
@@ -150,7 +150,7 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl)
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
-#if CONFIG_USE_CACHE_AS_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "\n%02x: ", j);
#else
print_debug("\n");
@@ -163,7 +163,7 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl)
break;
}
byte = status & 0xff;
-#if CONFIG_USE_CACHE_AS_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "%02x ", byte);
#else
print_debug_hex8(byte);
@@ -181,7 +181,7 @@ static inline void dump_smbus_registers(void)
for(device = 1; device < 0x80; device++) {
int j;
if( smbus_read_byte(device, 0) < 0 ) continue;
-#if CONFIG_USE_CACHE_AS_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "smbus: %02x", device);
#else
print_debug("smbus: ");
@@ -195,7 +195,7 @@ static inline void dump_smbus_registers(void)
break;
}
if ((j & 0xf) == 0) {
-#if CONFIG_USE_CACHE_AS_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "\n%02x: ",j);
#else
print_debug("\n");
@@ -204,7 +204,7 @@ static inline void dump_smbus_registers(void)
#endif
}
byte = status & 0xff;
-#if CONFIG_USE_CACHE_AS_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "%02x ", byte);
#else
print_debug_hex8(byte);
@@ -219,7 +219,7 @@ static inline void dump_io_resources(unsigned port)
{
int i;
-#if CONFIG_USE_CACHE_AS_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "%04x:\n", port);
#else
print_debug_hex16(port);
@@ -228,7 +228,7 @@ static inline void dump_io_resources(unsigned port)
for(i=0;i<256;i++) {
uint8_t val;
if ((i & 0x0f) == 0) {
-#if CONFIG_USE_CACHE_AS_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "%02x:", i);
#else
print_debug_hex8(i);
@@ -236,7 +236,7 @@ static inline void dump_io_resources(unsigned port)
#endif
}
val = inb(port);
-#if CONFIG_USE_CACHE_AS_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, " %02x",val);
#else
print_debug_char(' ');
@@ -255,7 +255,7 @@ static inline void dump_mem(unsigned start, unsigned end)
print_debug("dump_mem:");
for(i=start;i<end;i++) {
if((i & 0xf)==0) {
-#if CONFIG_USE_CACHE_AS_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, "\n%08x:", i);
#else
print_debug("\n");
@@ -263,7 +263,7 @@ static inline void dump_mem(unsigned start, unsigned end)
print_debug(":");
#endif
}
-#if CONFIG_USE_CACHE_AS_RAM
+#if CONFIG_CACHE_AS_RAM
printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
#else
print_debug(" ");
diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c
index a417336..ced3de1 100644
--- a/src/northbridge/intel/i3100/raminit.c
+++ b/src/northbridge/intel/i3100/raminit.c
@@ -1197,7 +1197,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
pci_write_config16(ctrl->f0, MCHSCRB, data16);
/* The memory is now setup, use it */
-#if CONFIG_USE_CACHE_AS_RAM == 0
+#if CONFIG_CACHE_AS_RAM == 0
cache_lbmem(MTRR_TYPE_WRBACK);
#endif
}
diff --git a/src/southbridge/intel/i82801cx/early_smbus.c b/src/southbridge/intel/i82801cx/early_smbus.c
index b62db80..2e31507 100644
--- a/src/southbridge/intel/i82801cx/early_smbus.c
+++ b/src/southbridge/intel/i82801cx/early_smbus.c
@@ -85,7 +85,6 @@ static int smbus_wait_until_done(void)
static int smbus_read_byte(unsigned device, unsigned address)
{
- unsigned char global_control_register;
unsigned char global_status_register;
unsigned char byte;
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