[coreboot] New patch to review for coreboot: b7ff170 inteltool: Add Intel i63xx I/O Controller Hub
Sven Schnelle (svens@stackframe.org)
gerrit at coreboot.org
Sun Oct 30 13:23:57 CET 2011
Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/356
-gerrit
commit b7ff170a978d5a7d03c5a8c1ef344921b54dad7a
Author: Sven Schnelle <svens at stackframe.org>
Date: Sun Oct 30 13:30:36 2011 +0100
inteltool: Add Intel i63xx I/O Controller Hub
Change-Id: Iaea7e4d1b206d43661ecb61d2ae517723fb8d008
Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
util/inteltool/gpio.c | 25 +++++++++++++++++++++
util/inteltool/inteltool.c | 1 +
util/inteltool/inteltool.h | 2 +-
util/inteltool/powermgt.c | 52 ++++++++++++++++++++++++++++++++++++++++++++
util/inteltool/rootcmplx.c | 1 +
5 files changed, 80 insertions(+), 1 deletions(-)
diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c
index 6b56ec4..1d48a68 100644
--- a/util/inteltool/gpio.c
+++ b/util/inteltool/gpio.c
@@ -203,6 +203,24 @@ static const io_register_t ich10_gpio_registers[] = {
{ 0x7c, 4, "RESERVED" },
};
+static const io_register_t i631x_gpio_registers[] = {
+ { 0x00, 4, "GPIO_USE_SEL" },
+ { 0x04, 4, "GP_IO_SEL" },
+ { 0x08, 4, "RESERVED" },
+ { 0x0c, 4, "GP_LVL" },
+ { 0x10, 4, "RESERVED" },
+ { 0x14, 4, "RESERVED" },
+ { 0x18, 4, "GPO_BLINK" },
+ { 0x1c, 4, "RESERVED" },
+ { 0x20, 4, "RESERVED" },
+ { 0x24, 4, "RESERVED" },
+ { 0x28, 4, "RESERVED" },
+ { 0x2c, 4, "GPI_INV" },
+ { 0x30, 4, "GPIO_USE_SEL2" },
+ { 0x34, 4, "GP_IO_SEL2" },
+ { 0x38, 4, "GP_LVL2" },
+};
+
int print_gpios(struct pci_dev *sb)
{
int i, size;
@@ -269,6 +287,13 @@ int print_gpios(struct pci_dev *sb)
gpio_registers = ich0_gpio_registers;
size = ARRAY_SIZE(ich0_gpio_registers);
break;
+
+ case PCI_DEVICE_ID_INTEL_I63XX:
+ gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
+ gpio_registers = i631x_gpio_registers;
+ size = ARRAY_SIZE(i631x_gpio_registers);
+ break;
+
case PCI_DEVICE_ID_INTEL_82371XX:
printf("This southbridge has GPIOs in the PM unit.\n");
return 1;
diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c
index 6fab118..488d9f5 100644
--- a/util/inteltool/inteltool.c
+++ b/util/inteltool/inteltool.c
@@ -82,6 +82,7 @@ static const struct {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "82371AB/EB/MB" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X44, "82X38/X48" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_32X0, "3200/3210" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I63XX, "Intel 63xx I/O Controller Hub" },
};
#ifndef __DARWIN__
diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h
index bddd17c..1bfb3d1 100644
--- a/util/inteltool/inteltool.h
+++ b/util/inteltool/inteltool.h
@@ -84,7 +84,7 @@
#define PCI_DEVICE_ID_INTEL_X58 0x3405
#define PCI_DEVICE_ID_INTEL_SCH_POULSBO 0x8100
#define PCI_DEVICE_ID_INTEL_ATOM_DXXX 0xa000
-
+#define PCI_DEVICE_ID_INTEL_I63XX 0x2670
/* untested, but almost identical to D-series */
#define PCI_DEVICE_ID_INTEL_ATOM_NXXX 0xa010
diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c
index a2ac32e..4974738 100644
--- a/util/inteltool/powermgt.c
+++ b/util/inteltool/powermgt.c
@@ -550,6 +550,51 @@ static const io_register_t i82371xx_pm_registers[] = {
{ 0x37, 1, "GPOREG 3" },
};
+static const io_register_t i63xx_pm_registers[] = {
+ { 0x00, 2, "PM1_STS" },
+ { 0x02, 2, "PM1_EN" },
+ { 0x04, 4, "PM1_CNT" },
+ { 0x08, 4, "PM1_TMR" },
+ { 0x0c, 4, "RESERVED" },
+ { 0x10, 4, "PROC_CNT" },
+#if DANGEROUS_REGISTERS
+ /* This register returns 0 on read, but reading it may cause
+ * the system to enter C2 state, which might hang the system.
+ */
+ { 0x14, 1, "LV2" },
+ { 0x15, 1, "RESERVED" },
+ { 0x16, 2, "RESERVED" },
+#endif
+ { 0x18, 4, "RESERVED" },
+ { 0x1c, 4, "RESERVED" },
+ { 0x20, 4, "RESERVED" },
+ { 0x24, 4, "RESERVED" },
+ { 0x28, 4, "GPE0_STS" },
+ { 0x2C, 4, "GPE0_EN" },
+ { 0x30, 4, "SMI_EN" },
+ { 0x34, 4, "SMI_STS" },
+ { 0x38, 2, "ALT_GP_SMI_EN" },
+ { 0x3a, 2, "ALT_GP_SMI_STS" },
+ { 0x3c, 4, "RESERVED" },
+ { 0x40, 4, "RESERVED" },
+ { 0x44, 2, "DEVACT_STS" },
+ { 0x46, 2, "RESERVED" },
+ { 0x48, 4, "RESERVED" },
+ { 0x4c, 4, "RESERVED" },
+ { 0x50, 4, "RESERVED" },
+ { 0x54, 4, "C3_RES" },
+ { 0x58, 4, "RESERVED" },
+ { 0x5c, 4, "RESERVED" },
+ { 0x60, 1, "RESERVED" },
+ { 0x64, 4, "RESERVED" },
+ { 0x68, 4, "RESERVED" },
+ { 0x6c, 4, "RESERVED" },
+ { 0x70, 4, "RESERVED" },
+ { 0x74, 4, "RESERVED" },
+ { 0x78, 4, "RESERVED" },
+ { 0x7c, 4, "RESERVED" },
+};
+
int print_pmbase(struct pci_dev *sb, struct pci_access *pacc)
{
int i, size;
@@ -625,6 +670,13 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc)
pm_registers = i82371xx_pm_registers;
size = ARRAY_SIZE(i82371xx_pm_registers);
break;
+
+ case PCI_DEVICE_ID_INTEL_I63XX:
+ pmbase = pci_read_word(sb, 0x40) & 0xfffc;
+ pm_registers = i63xx_pm_registers;
+ size = ARRAY_SIZE(i63xx_pm_registers);
+ break;
+
case 0x1234: // Dummy for non-existent functionality
printf("This southbridge does not have PMBASE.\n");
return 1;
diff --git a/util/inteltool/rootcmplx.c b/util/inteltool/rootcmplx.c
index a88b608..a478731 100644
--- a/util/inteltool/rootcmplx.c
+++ b/util/inteltool/rootcmplx.c
@@ -46,6 +46,7 @@ int print_rcba(struct pci_dev *sb)
case PCI_DEVICE_ID_INTEL_ICH9ME:
case PCI_DEVICE_ID_INTEL_ICH10R:
case PCI_DEVICE_ID_INTEL_NM10:
+ case PCI_DEVICE_ID_INTEL_I63XX:
rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
break;
case PCI_DEVICE_ID_INTEL_ICH:
More information about the coreboot
mailing list