[coreboot] [RFC] Announcement for Bifferboard port

[Paul Menzel]

Dear coreboot folks,


Rudolf did a great job porting coreboot to the Bifferboard. He wants to
announce it to their list and sent me his draft asking for help
improving the text.

I formatted the text using Markdown [1], so you can also create a HTML
page running *just one* of the following commands.

1. $ markdown bifferboard-announcement.mdwn
2. $ pandoc -o bifferboard-announcement.html bifferboard-announcement.mdwn

Also adding the instructions to the Wiki should be easier now.

In my opinion before posting the announcement a Bifferboard page should
be created in our Wiki though.

Could some of you go over the text and proof read it? Maybe formulate it
the way, people get even more excited or interested? ;-) That would be
awesome.


Thanks,

Paul


[1] https://en.wikipedia.org/wiki/Markdown
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Hi all,


I would like to announce that I ported coreboot to the Bifferboard.

[coreboot](http://coreboot.org) is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

coreboot can carry various payloads, for example [SeaBIOS](http://www.seabios.org/) or even [U-Boot](http://www.denx.de/wiki/U-Boot/) (this is new and not yet tested with the Bifferboard). SeaBIOS provides classic BIOS services, and it is used mainly with [QEMU](http://www.qemu.org), but coreboot uses SeaBIOS with real hardware.

The main advantage in my opinion is to be able to boot from USB natively. With SeaBIOS, the Bifferboard can boot your kernel from an USB medium. There is no need to have the kernel in Bifferboard’s limited flash!

I will have a look how to stick U-Boot to that, so it is more similar to Biffboot. This email is more like an announcement that something like this is possible. Maybe someone interested, could give it a try or even contribute to this.

Please note that I bricked the Bifferboard many times, therefore a serial line interface and JTAG is a must have for the beginning.

I implemented a support to [flashrom](http://flashrom.org), which is a userspace flashing tool.

Also coreboot’s current revision and SeaBIOS (stable) support the Bifferboard.

Instructions for testing
------------------------

### Precautions ###

Make sure you can recover from bricked Bifferboard.

### Get and build coreboot ###

Clone the Git repository:

    git clone http://review.coreboot.org/p/coreboot

Now go to `util/crossgcc` and build a GCC toolchain by running `./buildgcc`. This is needed since typically Ubuntu’s binutils are broken. You can skip this step of course.

Now configure everything with Kconfig.

    make menuconfig

Select *Bifferos/Bifferboad* in the Mainboard menu and in the Payload menu choose *SeaBIOS*.

Please note that you will have to ommit various features to fit everything into 64 KB. But the default ROM chip size is 128 KB which should be enough.

After this step, run `make` to build the image.

`build/coreboot.rom` is a 128 KB file with coreboot and SeaBIOS combined. Please note that you can even add other payloads like kernels if you wish.

### Build Flashrom ###

Now on your Bifferboard, build [Flashrom](http://flashrom.org/Downloads).

    svn co svn://flashrom.org/flashrom/trunk flashrom
    cd flashrom
    make
    sudo make install # You can also run the binary from the build folder.

Current SVN head contains support for the flash chip and the RDC chipset.

### Create and flash the ROM image ###

Now read out the flash:

    flashrom -r backup.rom
    cp backup.rom new.rom

SAVE THIS FILE `backup.rom` TO SECURE PLACE. It contains a backup of your whole flash chip (last 64 KB is Biffboot).

Now you need to combine `coreboot.rom` with `new.rom` by for example using `dd`:

Example for 64 KB 8 MB flash:

    dd if=coreboot.rom of=new.rom bs=1k seek=8128 conv=notrunc

Example for 128 KB 8 MB flash:

    dd if=coreboot.rom of=new.rom bs=1k seek=8064 conv=notrunc

It is time to flash the image to the chip. Please add some swapfile beforehand:

    swapon /swap.swp
    flashrom -w new.rom

You may reboot now. You should see some messages in this moment on serial line. Please note that there is a slight delay in the beginning because ramstage is uncompressing slowly because I did not figure out how to cache certain ROM regions.

Please join the [coreboot mailing list](http://www.coreboot.org/Mailinglist) and the [IRC channel](http://www.coreboot.org/IRC) to discuss this project further.


Thanks,

Rudolf
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