[coreboot] Dual SPI Flash adapter attempt 2.0

[Peter Stuge]

Oliver Schinagl wrote:
> So the big question is; shall I send this to seeed for fabrication
> or does it need some big change?

The RN has slivers of soldermask between pads. Avoid this; it's too
thin to work at all in production and the component size is so small
that you want to avoid any chance of soldermask getting in the way
of soldering. Board production processes are not exact, they are
messy mechanically and chemically, and you should never push your
producer's limits. If their limit is 6 never use less than 8.

The SMD ICs and RN all have the package outline on silk absolutely
tight around the soldermask apertures. Avoid this, again because the
silk is way too close to the pads, and you never want silk anywhere
outside the solder mask.

The U3 "orientation marker" (the arc) is rotated 45 degrees.

The RN outline isn't closed.

Keep in mind that there will be chip mounted on U2 so your JP1 legend
will never be visible. I would center JP1 and put a 1 and a 2 on each
side, and put a 1 and a 2 near the corresponding flash chips.

I don't particularly like that the U1 pins use 2x a 4-pin header
footprint. I would create a copy of the U2 footprint and adapt it to
make room for the SO8 inside of it, to make it completely clear what
goes mounted which way where.

Make sure to check that the sockets and pin headers you will use
actually fit in the holes that are in the footprints. Remember that
the hole in the footprint file is what will get drilled. After
drilling the holes will be plated, so the usable hole diameter is:
$drillsize - 2 * $platingthickness

Drills also never create nominal diameter holes, but always slightly
smaller. It is quite annoying to have boards full of holes that are
too small to fit the part.

The 45 degree PCB corners look fancy but really just add annoying
complexity and problems for the board house. Unneccessary complexity,
strip it off and have simple 90 degree corners.

The v in v0.1 and S in S1 on the bottom of the upper third board from
left is too close to pin U2-5 and pad S1-2 respectively.

The right edge of 'r' in some silk text goes in between pads where I
would make sure to keep clear.

There is way way too much silk for my taste. I don't like silk too
much when space is tight except if something *really* needs to be
explained. "JP1" is useless to all users. The *only* thing that needs
to be explained on the PCBs is what jumper setting activates what
flash chip. Explaining this with this little space is difficult!
Adding the inverter logic gate makes the problem simpler to explain
and means that JP1 has one less pin = more space for text, maybe
"Orig" or such, which would be clear to the user because they put
their original flash chip in the socket.

The silk of RN1 on the back of the third board from the left (as seen
from the front or after pressing Shift-Tab) goes outside the soldermask
aperture onto the keepout between the annular ring and the soldermask.

I would make the SMD pads extend longer "outwards" in order to make
hand soldering easier.

I would completely drop U1 through hole pins and make the PCB
strictly for a surface mounte U1. The board could become smaller
and/or have a little more text explaining the jumper.


All that said I believe you could manufacture this board and that the
PCBs would work. (But they would be a bit tough to populate.)


//Peter